Top Level Module |
top |
Synthesis Process |
Running parser: CPU time = 0h 0m 0.828s, Elapsed time = 0h 0m 0.808s, Peak memory usage = 251.113MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.091s, Peak memory usage = 251.113MB Optimizing Phase 1: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.118s, Peak memory usage = 251.113MB Optimizing Phase 2: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.116s, Peak memory usage = 251.113MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.081s, Peak memory usage = 251.113MB Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 251.113MB Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.024s, Peak memory usage = 251.113MB Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 251.113MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.221s, Peak memory usage = 251.113MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.078s, Peak memory usage = 251.113MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.042s, Peak memory usage = 251.113MB Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 269.199MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.169s, Peak memory usage = 269.199MB Generate output files: CPU time = 0h 0m 0.312s, Elapsed time = 0h 0m 0.371s, Peak memory usage = 273.832MB
|
Total Time and Memory Usage |
CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 273.832MB |
Resource |
Usage |
I/O Port |
53 |
I/O Buf |
50 |
    IBUF |
1 |
    OBUF |
28 |
    TBUF |
2 |
    IOBUF |
16 |
    ELVDS_OBUF |
1 |
    ELVDS_IOBUF |
2 |
Register |
4049 |
    DFF |
229 |
    DFFE |
252 |
    DFFS |
1 |
    DFFR |
1 |
    DFFP |
56 |
    DFFPE |
10 |
    DFFC |
2962 |
    DFFCE |
538 |
LUT |
2485 |
    LUT2 |
551 |
    LUT3 |
899 |
    LUT4 |
1035 |
ALU |
244 |
    ALU |
244 |
SSRAM |
137 |
    RAM16S4 |
44 |
    RAM16SDP4 |
93 |
INV |
27 |
    INV |
27 |
IOLOGIC |
76 |
    IDES8_MEM |
16 |
    OSER8 |
24 |
    OSER8_MEM |
20 |
    IODELAY |
16 |
BSRAM |
4 |
    SDPX9B |
4 |
CLOCK |
5 |
    CLKDIV |
1 |
    DQS |
2 |
    DHCEN |
1 |
    rPLL |
1 |
AT |
DELAY |
TYPE |
RF |
FANOUT |
NODE |
20.000 |
0.000 |
|
|
|
clk |
20.000 |
0.000 |
tCL |
RR |
1 |
clk_ibuf/I |
20.000 |
0.000 |
tINS |
RR |
41 |
clk_ibuf/O |
20.360 |
0.360 |
tNET |
RR |
1 |
u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK |
20.592 |
0.232 |
tC2Q |
RF |
3119 |
u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q |
21.066 |
0.474 |
tNET |
FF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init_s8/I1 |
21.621 |
0.555 |
tINS |
FF |
2 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init_s8/F |
22.095 |
0.474 |
tNET |
FF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init_s9/I2 |
22.548 |
0.453 |
tINS |
FF |
14 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init_s9/F |
23.022 |
0.474 |
tNET |
FF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_s27/I0 |
23.539 |
0.517 |
tINS |
FF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_s27/F |
24.013 |
0.474 |
tNET |
FF |
2 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n463_s0/I1 |
24.583 |
0.570 |
tINS |
FR |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n463_s0/COUT |
24.583 |
0.000 |
tNET |
RR |
2 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n464_s0/CIN |
24.618 |
0.035 |
tINS |
RF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n464_s0/COUT |
24.618 |
0.000 |
tNET |
FF |
2 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n465_s0/CIN |
24.653 |
0.035 |
tINS |
FF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n465_s0/COUT |
24.653 |
0.000 |
tNET |
FF |
2 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n466_s0/CIN |
24.689 |
0.035 |
tINS |
FF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n466_s0/COUT |
24.689 |
0.000 |
tNET |
FF |
2 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n467_s0/CIN |
24.724 |
0.035 |
tINS |
FF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n467_s0/COUT |
24.724 |
0.000 |
tNET |
FF |
2 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n468_s0/CIN |
24.759 |
0.035 |
tINS |
FF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n468_s0/COUT |
24.759 |
0.000 |
tNET |
FF |
2 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n469_s0/CIN |
24.794 |
0.035 |
tINS |
FF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n469_s0/COUT |
24.794 |
0.000 |
tNET |
FF |
2 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n470_s0/CIN |
24.829 |
0.035 |
tINS |
FF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n470_s0/COUT |
24.829 |
0.000 |
tNET |
FF |
2 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n471_s0/CIN |
24.865 |
0.035 |
tINS |
FF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n471_s0/COUT |
24.865 |
0.000 |
tNET |
FF |
2 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n472_s0/CIN |
24.900 |
0.035 |
tINS |
FF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n472_s0/COUT |
24.900 |
0.000 |
tNET |
FF |
2 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n473_s0/CIN |
24.935 |
0.035 |
tINS |
FF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n473_s0/COUT |
24.935 |
0.000 |
tNET |
FF |
2 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n474_s0/CIN |
24.970 |
0.035 |
tINS |
FF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n474_s0/COUT |
24.970 |
0.000 |
tNET |
FF |
2 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n475_s0/CIN |
25.005 |
0.035 |
tINS |
FF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n475_s0/COUT |
25.005 |
0.000 |
tNET |
FF |
2 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n476_s0/CIN |
25.041 |
0.035 |
tINS |
FF |
8 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n476_s0/COUT |
25.515 |
0.474 |
tNET |
FF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_7_G[29]_s0/D |
AT |
DELAY |
TYPE |
RF |
FANOUT |
NODE |
20.000 |
0.000 |
|
|
|
clk |
20.000 |
0.000 |
tCL |
RR |
1 |
clk_ibuf/I |
20.000 |
0.000 |
tINS |
RR |
41 |
clk_ibuf/O |
20.360 |
0.360 |
tNET |
RR |
1 |
u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK |
20.592 |
0.232 |
tC2Q |
RF |
3119 |
u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q |
21.066 |
0.474 |
tNET |
FF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init_s8/I1 |
21.621 |
0.555 |
tINS |
FF |
2 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init_s8/F |
22.095 |
0.474 |
tNET |
FF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init_s9/I2 |
22.548 |
0.453 |
tINS |
FF |
14 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init_s9/F |
23.022 |
0.474 |
tNET |
FF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_s27/I0 |
23.539 |
0.517 |
tINS |
FF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_s27/F |
24.013 |
0.474 |
tNET |
FF |
2 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n463_s0/I1 |
24.583 |
0.570 |
tINS |
FR |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n463_s0/COUT |
24.583 |
0.000 |
tNET |
RR |
2 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n464_s0/CIN |
24.618 |
0.035 |
tINS |
RF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n464_s0/COUT |
24.618 |
0.000 |
tNET |
FF |
2 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n465_s0/CIN |
24.653 |
0.035 |
tINS |
FF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n465_s0/COUT |
24.653 |
0.000 |
tNET |
FF |
2 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n466_s0/CIN |
24.689 |
0.035 |
tINS |
FF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n466_s0/COUT |
24.689 |
0.000 |
tNET |
FF |
2 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n467_s0/CIN |
24.724 |
0.035 |
tINS |
FF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n467_s0/COUT |
24.724 |
0.000 |
tNET |
FF |
2 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n468_s0/CIN |
24.759 |
0.035 |
tINS |
FF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n468_s0/COUT |
24.759 |
0.000 |
tNET |
FF |
2 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n469_s0/CIN |
24.794 |
0.035 |
tINS |
FF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n469_s0/COUT |
24.794 |
0.000 |
tNET |
FF |
2 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n470_s0/CIN |
24.829 |
0.035 |
tINS |
FF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n470_s0/COUT |
24.829 |
0.000 |
tNET |
FF |
2 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n471_s0/CIN |
24.865 |
0.035 |
tINS |
FF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n471_s0/COUT |
24.865 |
0.000 |
tNET |
FF |
2 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n472_s0/CIN |
24.900 |
0.035 |
tINS |
FF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n472_s0/COUT |
24.900 |
0.000 |
tNET |
FF |
2 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n473_s0/CIN |
24.935 |
0.035 |
tINS |
FF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n473_s0/COUT |
24.935 |
0.000 |
tNET |
FF |
2 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n474_s0/CIN |
24.970 |
0.035 |
tINS |
FF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n474_s0/COUT |
24.970 |
0.000 |
tNET |
FF |
2 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n475_s0/CIN |
25.005 |
0.035 |
tINS |
FF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n475_s0/COUT |
25.005 |
0.000 |
tNET |
FF |
2 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n476_s0/CIN |
25.041 |
0.035 |
tINS |
FF |
8 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n476_s0/COUT |
25.515 |
0.474 |
tNET |
FF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_6_G[29]_s0/D |
AT |
DELAY |
TYPE |
RF |
FANOUT |
NODE |
20.000 |
0.000 |
|
|
|
clk |
20.000 |
0.000 |
tCL |
RR |
1 |
clk_ibuf/I |
20.000 |
0.000 |
tINS |
RR |
41 |
clk_ibuf/O |
20.360 |
0.360 |
tNET |
RR |
1 |
u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK |
20.592 |
0.232 |
tC2Q |
RF |
3119 |
u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q |
21.066 |
0.474 |
tNET |
FF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init_s8/I1 |
21.621 |
0.555 |
tINS |
FF |
2 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init_s8/F |
22.095 |
0.474 |
tNET |
FF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init_s9/I2 |
22.548 |
0.453 |
tINS |
FF |
14 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init_s9/F |
23.022 |
0.474 |
tNET |
FF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_s27/I0 |
23.539 |
0.517 |
tINS |
FF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_s27/F |
24.013 |
0.474 |
tNET |
FF |
2 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n463_s0/I1 |
24.583 |
0.570 |
tINS |
FR |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n463_s0/COUT |
24.583 |
0.000 |
tNET |
RR |
2 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n464_s0/CIN |
24.618 |
0.035 |
tINS |
RF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n464_s0/COUT |
24.618 |
0.000 |
tNET |
FF |
2 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n465_s0/CIN |
24.653 |
0.035 |
tINS |
FF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n465_s0/COUT |
24.653 |
0.000 |
tNET |
FF |
2 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n466_s0/CIN |
24.689 |
0.035 |
tINS |
FF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n466_s0/COUT |
24.689 |
0.000 |
tNET |
FF |
2 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n467_s0/CIN |
24.724 |
0.035 |
tINS |
FF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n467_s0/COUT |
24.724 |
0.000 |
tNET |
FF |
2 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n468_s0/CIN |
24.759 |
0.035 |
tINS |
FF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n468_s0/COUT |
24.759 |
0.000 |
tNET |
FF |
2 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n469_s0/CIN |
24.794 |
0.035 |
tINS |
FF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n469_s0/COUT |
24.794 |
0.000 |
tNET |
FF |
2 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n470_s0/CIN |
24.829 |
0.035 |
tINS |
FF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n470_s0/COUT |
24.829 |
0.000 |
tNET |
FF |
2 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n471_s0/CIN |
24.865 |
0.035 |
tINS |
FF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n471_s0/COUT |
24.865 |
0.000 |
tNET |
FF |
2 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n472_s0/CIN |
24.900 |
0.035 |
tINS |
FF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n472_s0/COUT |
24.900 |
0.000 |
tNET |
FF |
2 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n473_s0/CIN |
24.935 |
0.035 |
tINS |
FF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n473_s0/COUT |
24.935 |
0.000 |
tNET |
FF |
2 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n474_s0/CIN |
24.970 |
0.035 |
tINS |
FF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n474_s0/COUT |
24.970 |
0.000 |
tNET |
FF |
2 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n475_s0/CIN |
25.005 |
0.035 |
tINS |
FF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n475_s0/COUT |
25.005 |
0.000 |
tNET |
FF |
2 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n476_s0/CIN |
25.041 |
0.035 |
tINS |
FF |
8 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n476_s0/COUT |
25.515 |
0.474 |
tNET |
FF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_5_G[29]_s0/D |
AT |
DELAY |
TYPE |
RF |
FANOUT |
NODE |
20.000 |
0.000 |
|
|
|
clk |
20.000 |
0.000 |
tCL |
RR |
1 |
clk_ibuf/I |
20.000 |
0.000 |
tINS |
RR |
41 |
clk_ibuf/O |
20.360 |
0.360 |
tNET |
RR |
1 |
u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK |
20.592 |
0.232 |
tC2Q |
RF |
3119 |
u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q |
21.066 |
0.474 |
tNET |
FF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init_s8/I1 |
21.621 |
0.555 |
tINS |
FF |
2 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init_s8/F |
22.095 |
0.474 |
tNET |
FF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init_s9/I2 |
22.548 |
0.453 |
tINS |
FF |
14 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init_s9/F |
23.022 |
0.474 |
tNET |
FF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_s27/I0 |
23.539 |
0.517 |
tINS |
FF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_s27/F |
24.013 |
0.474 |
tNET |
FF |
2 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n463_s0/I1 |
24.583 |
0.570 |
tINS |
FR |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n463_s0/COUT |
24.583 |
0.000 |
tNET |
RR |
2 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n464_s0/CIN |
24.618 |
0.035 |
tINS |
RF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n464_s0/COUT |
24.618 |
0.000 |
tNET |
FF |
2 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n465_s0/CIN |
24.653 |
0.035 |
tINS |
FF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n465_s0/COUT |
24.653 |
0.000 |
tNET |
FF |
2 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n466_s0/CIN |
24.689 |
0.035 |
tINS |
FF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n466_s0/COUT |
24.689 |
0.000 |
tNET |
FF |
2 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n467_s0/CIN |
24.724 |
0.035 |
tINS |
FF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n467_s0/COUT |
24.724 |
0.000 |
tNET |
FF |
2 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n468_s0/CIN |
24.759 |
0.035 |
tINS |
FF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n468_s0/COUT |
24.759 |
0.000 |
tNET |
FF |
2 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n469_s0/CIN |
24.794 |
0.035 |
tINS |
FF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n469_s0/COUT |
24.794 |
0.000 |
tNET |
FF |
2 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n470_s0/CIN |
24.829 |
0.035 |
tINS |
FF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n470_s0/COUT |
24.829 |
0.000 |
tNET |
FF |
2 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n471_s0/CIN |
24.865 |
0.035 |
tINS |
FF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n471_s0/COUT |
24.865 |
0.000 |
tNET |
FF |
2 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n472_s0/CIN |
24.900 |
0.035 |
tINS |
FF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n472_s0/COUT |
24.900 |
0.000 |
tNET |
FF |
2 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n473_s0/CIN |
24.935 |
0.035 |
tINS |
FF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n473_s0/COUT |
24.935 |
0.000 |
tNET |
FF |
2 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n474_s0/CIN |
24.970 |
0.035 |
tINS |
FF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n474_s0/COUT |
24.970 |
0.000 |
tNET |
FF |
2 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n475_s0/CIN |
25.005 |
0.035 |
tINS |
FF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n475_s0/COUT |
25.005 |
0.000 |
tNET |
FF |
2 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n476_s0/CIN |
25.041 |
0.035 |
tINS |
FF |
8 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n476_s0/COUT |
25.515 |
0.474 |
tNET |
FF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_4_G[29]_s0/D |
AT |
DELAY |
TYPE |
RF |
FANOUT |
NODE |
20.000 |
0.000 |
|
|
|
clk |
20.000 |
0.000 |
tCL |
RR |
1 |
clk_ibuf/I |
20.000 |
0.000 |
tINS |
RR |
41 |
clk_ibuf/O |
20.360 |
0.360 |
tNET |
RR |
1 |
u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK |
20.592 |
0.232 |
tC2Q |
RF |
3119 |
u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q |
21.066 |
0.474 |
tNET |
FF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init_s8/I1 |
21.621 |
0.555 |
tINS |
FF |
2 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init_s8/F |
22.095 |
0.474 |
tNET |
FF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init_s9/I2 |
22.548 |
0.453 |
tINS |
FF |
14 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init_s9/F |
23.022 |
0.474 |
tNET |
FF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_s27/I0 |
23.539 |
0.517 |
tINS |
FF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_s27/F |
24.013 |
0.474 |
tNET |
FF |
2 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n463_s0/I1 |
24.583 |
0.570 |
tINS |
FR |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n463_s0/COUT |
24.583 |
0.000 |
tNET |
RR |
2 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n464_s0/CIN |
24.618 |
0.035 |
tINS |
RF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n464_s0/COUT |
24.618 |
0.000 |
tNET |
FF |
2 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n465_s0/CIN |
24.653 |
0.035 |
tINS |
FF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n465_s0/COUT |
24.653 |
0.000 |
tNET |
FF |
2 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n466_s0/CIN |
24.689 |
0.035 |
tINS |
FF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n466_s0/COUT |
24.689 |
0.000 |
tNET |
FF |
2 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n467_s0/CIN |
24.724 |
0.035 |
tINS |
FF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n467_s0/COUT |
24.724 |
0.000 |
tNET |
FF |
2 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n468_s0/CIN |
24.759 |
0.035 |
tINS |
FF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n468_s0/COUT |
24.759 |
0.000 |
tNET |
FF |
2 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n469_s0/CIN |
24.794 |
0.035 |
tINS |
FF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n469_s0/COUT |
24.794 |
0.000 |
tNET |
FF |
2 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n470_s0/CIN |
24.829 |
0.035 |
tINS |
FF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n470_s0/COUT |
24.829 |
0.000 |
tNET |
FF |
2 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n471_s0/CIN |
24.865 |
0.035 |
tINS |
FF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n471_s0/COUT |
24.865 |
0.000 |
tNET |
FF |
2 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n472_s0/CIN |
24.900 |
0.035 |
tINS |
FF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n472_s0/COUT |
24.900 |
0.000 |
tNET |
FF |
2 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n473_s0/CIN |
24.935 |
0.035 |
tINS |
FF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n473_s0/COUT |
24.935 |
0.000 |
tNET |
FF |
2 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n474_s0/CIN |
24.970 |
0.035 |
tINS |
FF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n474_s0/COUT |
24.970 |
0.000 |
tNET |
FF |
2 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n475_s0/CIN |
25.005 |
0.035 |
tINS |
FF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n475_s0/COUT |
25.005 |
0.000 |
tNET |
FF |
2 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n476_s0/CIN |
25.041 |
0.035 |
tINS |
FF |
8 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n476_s0/COUT |
25.515 |
0.474 |
tNET |
FF |
1 |
u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_3_G[29]_s0/D |