Timing Messages

Report Title Timing Analysis Report
Design File E:\myWork\IP\releaseVerify\RefDesign\Memory_Control\DDR3\Gowin_DDR3_Memory_Interface_RefDesign\DDR3_MC_PHY_1vs4\project\impl\gwsynthesis\ddr3_1v4_hs.vg
Physical Constraints File E:\myWork\IP\releaseVerify\RefDesign\Memory_Control\DDR3\Gowin_DDR3_Memory_Interface_RefDesign\DDR3_MC_PHY_1vs4\project\src\ddr3_1v4_hs.cst
Timing Constraint File E:\myWork\IP\releaseVerify\RefDesign\Memory_Control\DDR3\Gowin_DDR3_Memory_Interface_RefDesign\DDR3_MC_PHY_1vs4\project\src\ddr3_1v4_hs.sdc
Tool Version V1.9.9.02
Part Number GW2A-LV18PG256C8/I7
Device GW2A-18
Device Version C
Created Time Wed Mar 27 10:52:15 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model Slow 0.95V 85C C8/I7
Hold Delay Model Fast 1.05V 0C C8/I7
Numbers of Paths Analyzed 10171
Numbers of Endpoints Analyzed 10719
Numbers of Falling Endpoints 2
Numbers of Setup Violated Endpoints 0
Numbers of Hold Violated Endpoints 0

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Objects
clkin Base 20.000 50.000 0.000 10.000 clk
clk_x4 Base 2.500 400.000 0.000 1.250 clk_x4
clkx1 Base 10.000 100.000 0.000 5.000 u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
upll/rpll_inst/CLKOUTP.default_gen_clk Generated 2.857 350.000 0.000 1.429 clk_ibuf/I clkin upll/rpll_inst/CLKOUTP
upll/rpll_inst/CLKOUTD.default_gen_clk Generated 5.714 175.000 0.000 2.857 clk_ibuf/I clkin upll/rpll_inst/CLKOUTD
upll/rpll_inst/CLKOUTD3.default_gen_clk Generated 8.571 116.667 0.000 4.286 clk_ibuf/I clkin upll/rpll_inst/CLKOUTD3

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 clkin 50.000(MHz) 228.987(MHz) 6 TOP
2 clk_x4 400.000(MHz) 2016.129(MHz) 1 TOP
3 clkx1 100.000(MHz) 103.731(MHz) 8 TOP

No timing paths to get frequency of upll/rpll_inst/CLKOUTP.default_gen_clk!

No timing paths to get frequency of upll/rpll_inst/CLKOUTD.default_gen_clk!

No timing paths to get frequency of upll/rpll_inst/CLKOUTD3.default_gen_clk!

Total Negative Slack Summary:

Clock Name Analysis Type Endpoints TNS Number of Endpoints
clkin Setup 0.000 0
clkin Hold 0.000 0
clk_x4 Setup 0.000 0
clk_x4 Hold 0.000 0
clkx1 Setup 0.000 0
clkx1 Hold 0.000 0
upll/rpll_inst/CLKOUTP.default_gen_clk Setup 0.000 0
upll/rpll_inst/CLKOUTP.default_gen_clk Hold 0.000 0
upll/rpll_inst/CLKOUTD.default_gen_clk Setup 0.000 0
upll/rpll_inst/CLKOUTD.default_gen_clk Hold 0.000 0
upll/rpll_inst/CLKOUTD3.default_gen_clk Setup 0.000 0
upll/rpll_inst/CLKOUTD3.default_gen_clk Hold 0.000 0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.360 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/Q u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_WRITE_s4/D clkx1:[R] clkx1:[R] 10.000 0.000 9.605
2 0.360 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/Q u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/idle2_s0/D clkx1:[R] clkx1:[R] 10.000 0.000 9.605
3 1.172 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/Q u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_READ_s6/D clkx1:[R] clkx1:[R] 10.000 0.000 8.793
4 1.172 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/Q u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/idle3_s0/D clkx1:[R] clkx1:[R] 10.000 0.000 8.793
5 1.246 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/Q u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_WP2SRE_s14/D clkx1:[R] clkx1:[R] 10.000 0.000 8.719
6 1.285 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/Q u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_ZQ_s14/D clkx1:[R] clkx1:[R] 10.000 0.000 8.680
7 1.318 u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_3_G[29]_s0/D clkin:[R] clkx1:[R] 10.000 2.088 6.524
8 1.318 u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_2_G[29]_s0/D clkin:[R] clkx1:[R] 10.000 2.088 6.524
9 1.318 u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_0_G[29]_s0/D clkin:[R] clkx1:[R] 10.000 2.088 6.524
10 1.332 u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_4_G[29]_s0/D clkin:[R] clkx1:[R] 10.000 2.088 6.510
11 1.332 u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_1_G[29]_s0/D clkin:[R] clkx1:[R] 10.000 2.088 6.510
12 1.340 u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_5_G[29]_s0/D clkin:[R] clkx1:[R] 10.000 2.088 6.502
13 1.462 u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_7_G[29]_s0/D clkin:[R] clkx1:[R] 10.000 2.088 6.380
14 1.462 u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_6_G[29]_s0/D clkin:[R] clkx1:[R] 10.000 2.088 6.380
15 1.681 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/Q u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_RP2AW_s10/D clkx1:[R] clkx1:[R] 10.000 0.000 8.284
16 1.715 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/Q u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_ACT2RD_s6/D clkx1:[R] clkx1:[R] 10.000 0.000 8.250
17 1.723 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/Q u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_RP2SRE_s14/D clkx1:[R] clkx1:[R] 10.000 0.000 8.242
18 1.755 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/Q u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_RP2REF_s14/D clkx1:[R] clkx1:[R] 10.000 0.000 8.210
19 1.787 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/Q u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_R2W_s6/D clkx1:[R] clkx1:[R] 10.000 0.000 8.178
20 1.787 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/Q u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_W2R_s8/D clkx1:[R] clkx1:[R] 10.000 0.000 8.178
21 1.881 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/Q u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_ACT2WR_s10/D clkx1:[R] clkx1:[R] 10.000 0.000 8.084
22 1.952 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/Q u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_WP2REF_s14/D clkx1:[R] clkx1:[R] 10.000 0.000 8.013
23 1.952 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/Q u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_WP2AR_s8/D clkx1:[R] clkx1:[R] 10.000 0.000 8.013
24 1.952 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/Q u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_WP2AW_s12/D clkx1:[R] clkx1:[R] 10.000 0.000 8.013
25 1.970 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/Q u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/idle1_s0/D clkx1:[R] clkx1:[R] 10.000 0.000 7.995

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.074 u_ddr3/gw3_top/u_ddr_phy_top/mux_wrdata_60_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_2_s/DI[3] clkx1:[R] clkx1:[R] 0.000 0.000 0.323
2 0.076 u_ddr3/gw3_top/u_ddr_phy_top/mux_wrdata_12_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_2_s/DI[0] clkx1:[R] clkx1:[R] 0.000 0.000 0.325
3 0.198 u_ddr3/gw3_top/u_ddr_phy_top/mux_wrdata_29_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_2_s/DI[9] clkx1:[R] clkx1:[R] 0.000 0.000 0.447
4 0.198 u_ddr3/gw3_top/u_ddr_phy_top/mux_wrdata_28_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_2_s/DI[1] clkx1:[R] clkx1:[R] 0.000 0.000 0.447
5 0.213 u_ddr3/gw3_top/u_ddr_phy_top/mux_wrdata_34_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_3_s/DI[22] clkx1:[R] clkx1:[R] 0.000 0.000 0.462
6 0.213 u_ddr3/gw3_top/u_ddr_phy_top/mux_wrdata_1_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_3_s/DI[12] clkx1:[R] clkx1:[R] 0.000 0.000 0.462
7 0.213 u_ddr3/gw3_top/u_ddr_phy_top/mux_wrdata_32_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_3_s/DI[6] clkx1:[R] clkx1:[R] 0.000 0.000 0.462
8 0.213 u_ddr3/gw3_top/u_ddr_phy_top/mux_wrdata_62_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_2_s/DI[19] clkx1:[R] clkx1:[R] 0.000 0.000 0.462
9 0.213 u_ddr3/gw3_top/u_ddr_phy_top/mux_wrdata_14_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_2_s/DI[16] clkx1:[R] clkx1:[R] 0.000 0.000 0.462
10 0.213 u_ddr3/gw3_top/u_ddr_phy_top/mux_wrdata_45_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_2_s/DI[10] clkx1:[R] clkx1:[R] 0.000 0.000 0.462
11 0.225 u_ddr3/gw3_top/u_ddr_phy_top/mux_wrdata_66_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_3_s/DI[24] clkx1:[R] clkx1:[R] 0.000 0.000 0.474
12 0.225 u_ddr3/gw3_top/u_ddr_phy_top/mux_wrdata_65_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_3_s/DI[16] clkx1:[R] clkx1:[R] 0.000 0.000 0.474
13 0.225 u_ddr3/gw3_top/u_ddr_phy_top/mux_wrdata_47_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_2_s/DI[26] clkx1:[R] clkx1:[R] 0.000 0.000 0.474
14 0.311 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_3_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[3] clkx1:[R] clkx1:[R] 0.000 0.000 0.323
15 0.311 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_2_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[2] clkx1:[R] clkx1:[R] 0.000 0.000 0.323
16 0.311 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_1_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[1] clkx1:[R] clkx1:[R] 0.000 0.000 0.323
17 0.311 u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_40_s0/Q u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_10_s/DI[0] clkx1:[R] clkx1:[R] 0.000 0.000 0.323
18 0.313 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_4_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/DI[0] clkx1:[R] clkx1:[R] 0.000 0.000 0.325
19 0.313 u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_127_s0/Q u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_31_s/DI[3] clkx1:[R] clkx1:[R] 0.000 0.000 0.325
20 0.314 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/wstep_reg_13_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/wstep_reg_d_0_s14/DI[1] clkx1:[R] clkx1:[R] 0.000 0.000 0.326
21 0.314 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/wstep_reg_2_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/wstep_reg_d_0_s8/DI[2] clkx1:[R] clkx1:[R] 0.000 0.000 0.326
22 0.317 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_calibration_logic_gen[1].read_adj_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_calibration_logic_gen[1].read_i_3_s0/CE clkx1:[R] clkx1:[R] 0.000 0.000 0.328
23 0.318 u_ddr3/gw3_top/u_ddr_phy_top/u_init_rmove_mod/init_rmove_done_rr_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_init_rmove_mod/rdir_1_s0/CE clkx1:[R] clkx1:[R] 0.000 0.000 0.329
24 0.319 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_cal_state.READ_CAL_DONE_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_cal_complete_s0/CE clkx1:[R] clkx1:[R] 0.000 0.000 0.330
25 0.319 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/wrlvl_state.WRLVL_DONE_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/wrlvl_complete_s0/CE clkx1:[R] clkx1:[R] 0.000 0.000 0.330

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 1.257 u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_calibration_logic_gen[1].rburst_neg_s0/CLEAR clkin:[R] clkx1:[F] 5.000 2.085 1.588
2 1.257 u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_calibration_logic_gen[0].rburst_neg_s0/CLEAR clkin:[R] clkx1:[F] 5.000 2.085 1.588
3 5.002 u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_Empty_reg_s0/PRESET clkin:[R] clkx1:[R] 10.000 2.088 2.840
4 5.002 u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_3_s0/CLEAR clkin:[R] clkx1:[R] 10.000 2.088 2.840
5 5.002 u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_0_s0/CLEAR clkin:[R] clkx1:[R] 10.000 2.088 2.840
6 5.002 u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_1_s0/CLEAR clkin:[R] clkx1:[R] 10.000 2.088 2.840
7 5.002 u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_2_s0/CLEAR clkin:[R] clkx1:[R] 10.000 2.088 2.840
8 5.002 u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_3_s0/CLEAR clkin:[R] clkx1:[R] 10.000 2.088 2.840
9 5.002 u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_0_s0/CLEAR clkin:[R] clkx1:[R] 10.000 2.088 2.840
10 5.002 u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_1_s0/CLEAR clkin:[R] clkx1:[R] 10.000 2.088 2.840
11 5.002 u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_2_s0/CLEAR clkin:[R] clkx1:[R] 10.000 2.088 2.840
12 5.002 u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_0_s0/CLEAR clkin:[R] clkx1:[R] 10.000 2.088 2.840
13 5.002 u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_1_s0/CLEAR clkin:[R] clkx1:[R] 10.000 2.088 2.840
14 5.002 u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_2_s0/CLEAR clkin:[R] clkx1:[R] 10.000 2.088 2.840
15 5.002 u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_3_s0/CLEAR clkin:[R] clkx1:[R] 10.000 2.088 2.840
16 5.002 u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_0_s0/CLEAR clkin:[R] clkx1:[R] 10.000 2.088 2.840
17 5.002 u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_1_s0/CLEAR clkin:[R] clkx1:[R] 10.000 2.088 2.840
18 5.002 u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_2_s0/CLEAR clkin:[R] clkx1:[R] 10.000 2.088 2.840
19 5.002 u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_3_s0/CLEAR clkin:[R] clkx1:[R] 10.000 2.088 2.840
20 5.002 u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_0_s0/CLEAR clkin:[R] clkx1:[R] 10.000 2.088 2.840
21 5.002 u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_1_s0/CLEAR clkin:[R] clkx1:[R] 10.000 2.088 2.840
22 5.002 u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_2_s0/CLEAR clkin:[R] clkx1:[R] 10.000 2.088 2.840
23 5.002 u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_Empty_reg_s0/PRESET clkin:[R] clkx1:[R] 10.000 2.088 2.840
24 5.002 u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_3_s0/CLEAR clkin:[R] clkx1:[R] 10.000 2.088 2.840
25 5.002 u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_0_s0/CLEAR clkin:[R] clkx1:[R] 10.000 2.088 2.840

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 1.294 u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_Empty_reg_s0/PRESET clkx1:[R] clkx1:[R] 0.000 0.000 1.305
2 1.294 u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_3_s0/CLEAR clkx1:[R] clkx1:[R] 0.000 0.000 1.305
3 1.294 u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_0_s0/CLEAR clkx1:[R] clkx1:[R] 0.000 0.000 1.305
4 1.294 u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_1_s0/CLEAR clkx1:[R] clkx1:[R] 0.000 0.000 1.305
5 1.294 u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_2_s0/CLEAR clkx1:[R] clkx1:[R] 0.000 0.000 1.305
6 1.294 u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_3_s0/CLEAR clkx1:[R] clkx1:[R] 0.000 0.000 1.305
7 1.294 u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_0_s0/CLEAR clkx1:[R] clkx1:[R] 0.000 0.000 1.305
8 1.294 u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_1_s0/CLEAR clkx1:[R] clkx1:[R] 0.000 0.000 1.305
9 1.294 u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_2_s0/CLEAR clkx1:[R] clkx1:[R] 0.000 0.000 1.305
10 1.294 u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_0_s0/CLEAR clkx1:[R] clkx1:[R] 0.000 0.000 1.305
11 1.294 u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_1_s0/CLEAR clkx1:[R] clkx1:[R] 0.000 0.000 1.305
12 1.294 u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_2_s0/CLEAR clkx1:[R] clkx1:[R] 0.000 0.000 1.305
13 1.294 u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_3_s0/CLEAR clkx1:[R] clkx1:[R] 0.000 0.000 1.305
14 1.294 u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_0_s0/CLEAR clkx1:[R] clkx1:[R] 0.000 0.000 1.305
15 1.294 u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_1_s0/CLEAR clkx1:[R] clkx1:[R] 0.000 0.000 1.305
16 1.294 u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_2_s0/CLEAR clkx1:[R] clkx1:[R] 0.000 0.000 1.305
17 1.294 u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_3_s0/CLEAR clkx1:[R] clkx1:[R] 0.000 0.000 1.305
18 1.294 u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_0_s0/CLEAR clkx1:[R] clkx1:[R] 0.000 0.000 1.305
19 1.294 u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_1_s0/CLEAR clkx1:[R] clkx1:[R] 0.000 0.000 1.305
20 1.294 u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_2_s0/CLEAR clkx1:[R] clkx1:[R] 0.000 0.000 1.305
21 1.294 u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_Empty_reg_s0/PRESET clkx1:[R] clkx1:[R] 0.000 0.000 1.305
22 1.294 u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_3_s0/CLEAR clkx1:[R] clkx1:[R] 0.000 0.000 1.305
23 1.294 u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_0_s0/CLEAR clkx1:[R] clkx1:[R] 0.000 0.000 1.305
24 1.294 u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_1_s0/CLEAR clkx1:[R] clkx1:[R] 0.000 0.000 1.305
25 1.294 u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_2_s0/CLEAR clkx1:[R] clkx1:[R] 0.000 0.000 1.305

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number Slack Actual Width Required Width Type Clock Objects
1 3.237 4.237 1.000 Low Pulse Width clkx1 led_cnt_31_s0
2 3.237 4.237 1.000 Low Pulse Width clkx1 led_cnt_24_s0
3 3.237 4.237 1.000 Low Pulse Width clkx1 led_cnt_16_s0
4 3.237 4.237 1.000 Low Pulse Width clkx1 led_cnt_12_s0
5 3.237 4.237 1.000 Low Pulse Width clkx1 led_cnt_10_s0
6 3.237 4.237 1.000 Low Pulse Width clkx1 led_cnt_9_s0
7 3.237 4.237 1.000 Low Pulse Width clkx1 u_rd/app_rd_data_r_74_s0
8 3.237 4.237 1.000 Low Pulse Width clkx1 u_rd/app_rd_data_rr_75_s0
9 3.237 4.237 1.000 Low Pulse Width clkx1 u_ddr3/gw3_top/gwmc_app_wdf_wdata_25_s0
10 3.237 4.237 1.000 Low Pulse Width clkx1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_4_G[15]_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 0.360
Data Arrival Time 11.877
Data Required Time 12.236
From u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0
To u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_WRITE_s4
Launch Clk clkx1:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
2.271 2.271 tNET RR 1 R20C17[0][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/CLK
2.503 0.232 tC2Q RF 128 R20C17[0][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/Q
4.891 2.388 tNET FF 1 R13C19[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_168_G[0]_s3/I2
5.408 0.517 tINS FF 1 R13C19[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_168_G[0]_s3/F
5.408 0.000 tNET FF 1 R13C19[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_168_G[0]_s1/I0
5.511 0.103 tINS FF 1 R13C19[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_168_G[0]_s1/O
5.511 0.000 tNET FF 1 R13C19[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_168_G[0]_s0/I0
5.614 0.103 tINS FF 5 R13C19[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_168_G[0]_s0/O
6.763 1.149 tNET FF 1 R22C8[1][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s24/I2
7.134 0.371 tINS FF 1 R22C8[1][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s24/F
7.134 0.000 tNET FF 1 R22C8[1][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s22/I0
7.237 0.103 tINS FF 1 R22C8[1][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s22/O
7.237 0.000 tNET FF 1 R22C8[0][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s21/I0
7.340 0.103 tINS FF 4 R22C8[0][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s21/O
7.779 0.439 tNET FF 1 R21C9[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_W2R_s58/I2
8.150 0.371 tINS FF 2 R21C9[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_W2R_s58/F
8.839 0.688 tNET FF 1 R22C15[0][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s73/I1
9.292 0.453 tINS FF 1 R22C15[0][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s73/F
9.948 0.656 tNET FF 1 R22C16[3][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s70/I0
10.465 0.517 tINS FF 1 R22C16[3][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s70/F
10.878 0.413 tNET FF 1 R22C17[2][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s68/I2
11.331 0.453 tINS FF 2 R22C17[2][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s68/F
11.877 0.546 tNET FF 1 R23C17[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_WRITE_s4/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clkx1
10.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
12.271 2.271 tNET RR 1 R23C17[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_WRITE_s4/CLK
12.236 -0.035 tSu 1 R23C17[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_WRITE_s4

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay cell: 3.094, 32.211%; route: 6.279, 65.373%; tC2Q: 0.232, 2.415%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.271, 100.000%

Path2

Path Summary:

Slack 0.360
Data Arrival Time 11.877
Data Required Time 12.236
From u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0
To u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/idle2_s0
Launch Clk clkx1:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
2.271 2.271 tNET RR 1 R20C17[0][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/CLK
2.503 0.232 tC2Q RF 128 R20C17[0][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/Q
4.891 2.388 tNET FF 1 R13C19[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_168_G[0]_s3/I2
5.408 0.517 tINS FF 1 R13C19[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_168_G[0]_s3/F
5.408 0.000 tNET FF 1 R13C19[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_168_G[0]_s1/I0
5.511 0.103 tINS FF 1 R13C19[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_168_G[0]_s1/O
5.511 0.000 tNET FF 1 R13C19[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_168_G[0]_s0/I0
5.614 0.103 tINS FF 5 R13C19[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_168_G[0]_s0/O
6.763 1.149 tNET FF 1 R22C8[1][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s24/I2
7.134 0.371 tINS FF 1 R22C8[1][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s24/F
7.134 0.000 tNET FF 1 R22C8[1][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s22/I0
7.237 0.103 tINS FF 1 R22C8[1][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s22/O
7.237 0.000 tNET FF 1 R22C8[0][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s21/I0
7.340 0.103 tINS FF 4 R22C8[0][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s21/O
7.779 0.439 tNET FF 1 R21C9[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_W2R_s58/I2
8.150 0.371 tINS FF 2 R21C9[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_W2R_s58/F
8.839 0.688 tNET FF 1 R22C15[0][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s73/I1
9.292 0.453 tINS FF 1 R22C15[0][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s73/F
9.948 0.656 tNET FF 1 R22C16[3][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s70/I0
10.465 0.517 tINS FF 1 R22C16[3][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s70/F
10.878 0.413 tNET FF 1 R22C17[2][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s68/I2
11.331 0.453 tINS FF 2 R22C17[2][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s68/F
11.877 0.546 tNET FF 1 R23C17[2][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/idle2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clkx1
10.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
12.271 2.271 tNET RR 1 R23C17[2][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/idle2_s0/CLK
12.236 -0.035 tSu 1 R23C17[2][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/idle2_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay cell: 3.094, 32.211%; route: 6.279, 65.373%; tC2Q: 0.232, 2.415%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.271, 100.000%

Path3

Path Summary:

Slack 1.172
Data Arrival Time 11.064
Data Required Time 12.236
From u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0
To u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_READ_s6
Launch Clk clkx1:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
2.271 2.271 tNET RR 1 R20C17[0][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/CLK
2.503 0.232 tC2Q RF 128 R20C17[0][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/Q
4.891 2.388 tNET FF 1 R13C19[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_168_G[0]_s3/I2
5.408 0.517 tINS FF 1 R13C19[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_168_G[0]_s3/F
5.408 0.000 tNET FF 1 R13C19[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_168_G[0]_s1/I0
5.511 0.103 tINS FF 1 R13C19[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_168_G[0]_s1/O
5.511 0.000 tNET FF 1 R13C19[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_168_G[0]_s0/I0
5.614 0.103 tINS FF 5 R13C19[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_168_G[0]_s0/O
6.763 1.149 tNET FF 1 R22C8[1][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s24/I2
7.134 0.371 tINS FF 1 R22C8[1][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s24/F
7.134 0.000 tNET FF 1 R22C8[1][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s22/I0
7.237 0.103 tINS FF 1 R22C8[1][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s22/O
7.237 0.000 tNET FF 1 R22C8[0][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s21/I0
7.340 0.103 tINS FF 4 R22C8[0][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s21/O
7.779 0.439 tNET FF 1 R21C9[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_W2R_s58/I2
8.150 0.371 tINS FF 2 R21C9[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_W2R_s58/F
8.915 0.765 tNET FF 1 R22C15[2][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_READ_s72/I1
9.464 0.549 tINS FR 1 R22C15[2][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_READ_s72/F
9.466 0.001 tNET RR 1 R22C15[2][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_READ_s70/I0
9.928 0.462 tINS RR 1 R22C15[2][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_READ_s70/F
9.929 0.001 tNET RR 1 R22C15[3][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_READ_s68/I2
10.446 0.517 tINS RF 2 R22C15[3][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_READ_s68/F
11.064 0.618 tNET FF 1 R23C15[2][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_READ_s6/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clkx1
10.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
12.271 2.271 tNET RR 1 R23C15[2][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_READ_s6/CLK
12.236 -0.035 tSu 1 R23C15[2][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_READ_s6

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay cell: 3.199, 36.382%; route: 5.362, 60.980%; tC2Q: 0.232, 2.638%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.271, 100.000%

Path4

Path Summary:

Slack 1.172
Data Arrival Time 11.064
Data Required Time 12.236
From u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0
To u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/idle3_s0
Launch Clk clkx1:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
2.271 2.271 tNET RR 1 R20C17[0][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/CLK
2.503 0.232 tC2Q RF 128 R20C17[0][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/Q
4.891 2.388 tNET FF 1 R13C19[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_168_G[0]_s3/I2
5.408 0.517 tINS FF 1 R13C19[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_168_G[0]_s3/F
5.408 0.000 tNET FF 1 R13C19[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_168_G[0]_s1/I0
5.511 0.103 tINS FF 1 R13C19[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_168_G[0]_s1/O
5.511 0.000 tNET FF 1 R13C19[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_168_G[0]_s0/I0
5.614 0.103 tINS FF 5 R13C19[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_168_G[0]_s0/O
6.763 1.149 tNET FF 1 R22C8[1][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s24/I2
7.134 0.371 tINS FF 1 R22C8[1][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s24/F
7.134 0.000 tNET FF 1 R22C8[1][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s22/I0
7.237 0.103 tINS FF 1 R22C8[1][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s22/O
7.237 0.000 tNET FF 1 R22C8[0][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s21/I0
7.340 0.103 tINS FF 4 R22C8[0][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s21/O
7.779 0.439 tNET FF 1 R21C9[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_W2R_s58/I2
8.150 0.371 tINS FF 2 R21C9[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_W2R_s58/F
8.915 0.765 tNET FF 1 R22C15[2][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_READ_s72/I1
9.464 0.549 tINS FR 1 R22C15[2][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_READ_s72/F
9.466 0.001 tNET RR 1 R22C15[2][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_READ_s70/I0
9.928 0.462 tINS RR 1 R22C15[2][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_READ_s70/F
9.929 0.001 tNET RR 1 R22C15[3][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_READ_s68/I2
10.446 0.517 tINS RF 2 R22C15[3][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_READ_s68/F
11.064 0.618 tNET FF 1 R24C15[2][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/idle3_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clkx1
10.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
12.271 2.271 tNET RR 1 R24C15[2][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/idle3_s0/CLK
12.236 -0.035 tSu 1 R24C15[2][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/idle3_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay cell: 3.199, 36.382%; route: 5.362, 60.980%; tC2Q: 0.232, 2.638%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.271, 100.000%

Path5

Path Summary:

Slack 1.246
Data Arrival Time 10.990
Data Required Time 12.236
From u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0
To u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_WP2SRE_s14
Launch Clk clkx1:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
2.271 2.271 tNET RR 1 R20C17[0][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/CLK
2.503 0.232 tC2Q RF 128 R20C17[0][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/Q
4.631 2.128 tNET FF 1 R13C18[3][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s4/I2
5.186 0.555 tINS FF 1 R13C18[3][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s4/F
5.186 0.000 tNET FF 1 R13C18[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s1/I1
5.289 0.103 tINS FF 1 R13C18[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s1/O
5.289 0.000 tNET FF 1 R13C18[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s0/I0
5.392 0.103 tINS FF 7 R13C18[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s0/O
6.350 0.958 tNET FF 1 R23C15[1][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_SREI_s58/I0
6.803 0.453 tINS FF 6 R23C15[1][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_SREI_s58/F
7.753 0.949 tNET FF 1 R24C14[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_SREI_s56/I0
8.206 0.453 tINS FF 3 R24C14[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_SREI_s56/F
8.611 0.406 tNET FF 1 R22C14[2][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s74/I2
8.982 0.371 tINS FF 8 R22C14[2][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s74/F
9.004 0.022 tNET FF 1 R22C14[3][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WP2AW_s58/I2
9.521 0.517 tINS FF 4 R22C14[3][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WP2AW_s58/F
10.420 0.899 tNET FF 1 R22C16[2][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WP2SRE_s54/I0
10.990 0.570 tINS FR 1 R22C16[2][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WP2SRE_s54/F
10.990 0.000 tNET RR 1 R22C16[2][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_WP2SRE_s14/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clkx1
10.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
12.271 2.271 tNET RR 1 R22C16[2][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_WP2SRE_s14/CLK
12.236 -0.035 tSu 1 R22C16[2][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_WP2SRE_s14

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay cell: 3.125, 35.843%; route: 5.362, 61.496%; tC2Q: 0.232, 2.661%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.271, 100.000%

Path6

Path Summary:

Slack 1.285
Data Arrival Time 10.951
Data Required Time 12.236
From u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0
To u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_ZQ_s14
Launch Clk clkx1:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
2.271 2.271 tNET RR 1 R20C17[0][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/CLK
2.503 0.232 tC2Q RF 128 R20C17[0][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/Q
4.631 2.128 tNET FF 1 R13C18[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s3/I2
5.186 0.555 tINS FF 1 R13C18[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s3/F
5.186 0.000 tNET FF 1 R13C18[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s1/I0
5.289 0.103 tINS FF 1 R13C18[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s1/O
5.289 0.000 tNET FF 1 R13C18[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s0/I0
5.392 0.103 tINS FF 7 R13C18[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s0/O
6.350 0.958 tNET FF 1 R23C15[1][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_SREI_s58/I0
6.803 0.453 tINS FF 6 R23C15[1][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_SREI_s58/F
7.753 0.949 tNET FF 1 R24C14[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_SREI_s56/I0
8.206 0.453 tINS FF 3 R24C14[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_SREI_s56/F
8.611 0.406 tNET FF 1 R22C14[2][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s74/I2
8.982 0.371 tINS FF 8 R22C14[2][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s74/F
9.179 0.197 tNET FF 1 R22C15[3][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_ZQ_s56/I1
9.550 0.371 tINS FF 5 R22C15[3][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_ZQ_s56/F
10.402 0.852 tNET FF 1 R26C18[0][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_ZQ_s55/I2
10.951 0.549 tINS FR 1 R26C18[0][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_ZQ_s55/F
10.951 0.000 tNET RR 1 R26C18[0][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_ZQ_s14/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clkx1
10.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
12.271 2.271 tNET RR 1 R26C18[0][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_ZQ_s14/CLK
12.236 -0.035 tSu 1 R26C18[0][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_ZQ_s14

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay cell: 2.958, 34.079%; route: 5.490, 63.248%; tC2Q: 0.232, 2.673%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.271, 100.000%

Path7

Path Summary:

Slack 1.318
Data Arrival Time 10.883
Data Required Time 12.201
From u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_3_G[29]_s0
Launch Clk clkin:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
2.088 2.088 tINS RR 41 IOT27[A] clk_ibuf/O
4.359 2.271 tNET RR 1 R27C37[2][B] u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
4.591 0.232 tC2Q RF 3119 R27C37[2][B] u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
6.190 1.598 tNET FF 1 R17C23[0][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init_s8/I1
6.561 0.371 tINS FF 2 R17C23[0][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init_s8/F
7.221 0.660 tNET FF 1 R14C22[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init_s9/I2
7.592 0.371 tINS FF 14 R14C22[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init_s9/F
8.023 0.431 tNET FF 1 R15C23[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_s35/I0
8.578 0.555 tINS FF 1 R15C23[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_s35/F
8.991 0.413 tNET FF 2 R16C22[1][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n471_s0/I1
9.561 0.570 tINS FR 1 R16C22[1][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n471_s0/COUT
9.561 0.000 tNET RR 2 R16C22[2][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n472_s0/CIN
9.596 0.035 tINS RF 1 R16C22[2][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n472_s0/COUT
9.596 0.000 tNET FF 2 R16C22[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n473_s0/CIN
9.631 0.035 tINS FF 1 R16C22[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n473_s0/COUT
9.631 0.000 tNET FF 2 R16C23[0][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n474_s0/CIN
9.666 0.035 tINS FF 1 R16C23[0][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n474_s0/COUT
9.666 0.000 tNET FF 2 R16C23[0][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n475_s0/CIN
9.702 0.035 tINS FF 1 R16C23[0][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n475_s0/COUT
9.702 0.000 tNET FF 2 R16C23[1][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n476_s0/CIN
9.737 0.035 tINS FF 8 R16C23[1][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n476_s0/COUT
10.883 1.146 tNET FF 1 R17C20[0][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_3_G[29]_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clkx1
10.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
12.271 2.271 tNET RR 1 R17C20[0][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_3_G[29]_s0/CLK
12.236 -0.035 tUnc u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_3_G[29]_s0
12.201 -0.035 tSu 1 R17C20[0][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_3_G[29]_s0

Path Statistics:

Clock Skew -2.088
Setup Relationship 10.000
Logic Level 6
Arrival Clock Path Delay cell: 2.088, 47.897%; route: 2.271, 52.103%
Arrival Data Path Delay cell: 2.043, 31.317%; route: 4.249, 65.127%; tC2Q: 0.232, 3.556%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.271, 100.000%

Path8

Path Summary:

Slack 1.318
Data Arrival Time 10.883
Data Required Time 12.201
From u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_2_G[29]_s0
Launch Clk clkin:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
2.088 2.088 tINS RR 41 IOT27[A] clk_ibuf/O
4.359 2.271 tNET RR 1 R27C37[2][B] u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
4.591 0.232 tC2Q RF 3119 R27C37[2][B] u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
6.190 1.598 tNET FF 1 R17C23[0][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init_s8/I1
6.561 0.371 tINS FF 2 R17C23[0][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init_s8/F
7.221 0.660 tNET FF 1 R14C22[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init_s9/I2
7.592 0.371 tINS FF 14 R14C22[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init_s9/F
8.023 0.431 tNET FF 1 R15C23[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_s35/I0
8.578 0.555 tINS FF 1 R15C23[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_s35/F
8.991 0.413 tNET FF 2 R16C22[1][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n471_s0/I1
9.561 0.570 tINS FR 1 R16C22[1][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n471_s0/COUT
9.561 0.000 tNET RR 2 R16C22[2][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n472_s0/CIN
9.596 0.035 tINS RF 1 R16C22[2][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n472_s0/COUT
9.596 0.000 tNET FF 2 R16C22[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n473_s0/CIN
9.631 0.035 tINS FF 1 R16C22[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n473_s0/COUT
9.631 0.000 tNET FF 2 R16C23[0][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n474_s0/CIN
9.666 0.035 tINS FF 1 R16C23[0][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n474_s0/COUT
9.666 0.000 tNET FF 2 R16C23[0][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n475_s0/CIN
9.702 0.035 tINS FF 1 R16C23[0][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n475_s0/COUT
9.702 0.000 tNET FF 2 R16C23[1][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n476_s0/CIN
9.737 0.035 tINS FF 8 R16C23[1][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n476_s0/COUT
10.883 1.146 tNET FF 1 R17C20[2][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_2_G[29]_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clkx1
10.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
12.271 2.271 tNET RR 1 R17C20[2][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_2_G[29]_s0/CLK
12.236 -0.035 tUnc u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_2_G[29]_s0
12.201 -0.035 tSu 1 R17C20[2][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_2_G[29]_s0

Path Statistics:

Clock Skew -2.088
Setup Relationship 10.000
Logic Level 6
Arrival Clock Path Delay cell: 2.088, 47.897%; route: 2.271, 52.103%
Arrival Data Path Delay cell: 2.043, 31.317%; route: 4.249, 65.127%; tC2Q: 0.232, 3.556%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.271, 100.000%

Path9

Path Summary:

Slack 1.318
Data Arrival Time 10.883
Data Required Time 12.201
From u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_0_G[29]_s0
Launch Clk clkin:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
2.088 2.088 tINS RR 41 IOT27[A] clk_ibuf/O
4.359 2.271 tNET RR 1 R27C37[2][B] u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
4.591 0.232 tC2Q RF 3119 R27C37[2][B] u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
6.190 1.598 tNET FF 1 R17C23[0][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init_s8/I1
6.561 0.371 tINS FF 2 R17C23[0][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init_s8/F
7.221 0.660 tNET FF 1 R14C22[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init_s9/I2
7.592 0.371 tINS FF 14 R14C22[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init_s9/F
8.023 0.431 tNET FF 1 R15C23[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_s35/I0
8.578 0.555 tINS FF 1 R15C23[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_s35/F
8.991 0.413 tNET FF 2 R16C22[1][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n471_s0/I1
9.561 0.570 tINS FR 1 R16C22[1][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n471_s0/COUT
9.561 0.000 tNET RR 2 R16C22[2][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n472_s0/CIN
9.596 0.035 tINS RF 1 R16C22[2][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n472_s0/COUT
9.596 0.000 tNET FF 2 R16C22[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n473_s0/CIN
9.631 0.035 tINS FF 1 R16C22[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n473_s0/COUT
9.631 0.000 tNET FF 2 R16C23[0][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n474_s0/CIN
9.666 0.035 tINS FF 1 R16C23[0][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n474_s0/COUT
9.666 0.000 tNET FF 2 R16C23[0][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n475_s0/CIN
9.702 0.035 tINS FF 1 R16C23[0][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n475_s0/COUT
9.702 0.000 tNET FF 2 R16C23[1][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n476_s0/CIN
9.737 0.035 tINS FF 8 R16C23[1][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n476_s0/COUT
10.883 1.146 tNET FF 1 R17C20[1][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_0_G[29]_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clkx1
10.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
12.271 2.271 tNET RR 1 R17C20[1][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_0_G[29]_s0/CLK
12.236 -0.035 tUnc u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_0_G[29]_s0
12.201 -0.035 tSu 1 R17C20[1][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_0_G[29]_s0

Path Statistics:

Clock Skew -2.088
Setup Relationship 10.000
Logic Level 6
Arrival Clock Path Delay cell: 2.088, 47.897%; route: 2.271, 52.103%
Arrival Data Path Delay cell: 2.043, 31.317%; route: 4.249, 65.127%; tC2Q: 0.232, 3.556%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.271, 100.000%

Path10

Path Summary:

Slack 1.332
Data Arrival Time 10.869
Data Required Time 12.201
From u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_4_G[29]_s0
Launch Clk clkin:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
2.088 2.088 tINS RR 41 IOT27[A] clk_ibuf/O
4.359 2.271 tNET RR 1 R27C37[2][B] u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
4.591 0.232 tC2Q RF 3119 R27C37[2][B] u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
6.190 1.598 tNET FF 1 R17C23[0][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init_s8/I1
6.561 0.371 tINS FF 2 R17C23[0][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init_s8/F
7.221 0.660 tNET FF 1 R14C22[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init_s9/I2
7.592 0.371 tINS FF 14 R14C22[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init_s9/F
8.023 0.431 tNET FF 1 R15C23[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_s35/I0
8.578 0.555 tINS FF 1 R15C23[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_s35/F
8.991 0.413 tNET FF 2 R16C22[1][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n471_s0/I1
9.561 0.570 tINS FR 1 R16C22[1][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n471_s0/COUT
9.561 0.000 tNET RR 2 R16C22[2][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n472_s0/CIN
9.596 0.035 tINS RF 1 R16C22[2][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n472_s0/COUT
9.596 0.000 tNET FF 2 R16C22[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n473_s0/CIN
9.631 0.035 tINS FF 1 R16C22[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n473_s0/COUT
9.631 0.000 tNET FF 2 R16C23[0][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n474_s0/CIN
9.666 0.035 tINS FF 1 R16C23[0][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n474_s0/COUT
9.666 0.000 tNET FF 2 R16C23[0][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n475_s0/CIN
9.702 0.035 tINS FF 1 R16C23[0][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n475_s0/COUT
9.702 0.000 tNET FF 2 R16C23[1][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n476_s0/CIN
9.737 0.035 tINS FF 8 R16C23[1][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n476_s0/COUT
10.869 1.132 tNET FF 1 R16C19[1][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_4_G[29]_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clkx1
10.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
12.271 2.271 tNET RR 1 R16C19[1][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_4_G[29]_s0/CLK
12.236 -0.035 tUnc u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_4_G[29]_s0
12.201 -0.035 tSu 1 R16C19[1][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_4_G[29]_s0

Path Statistics:

Clock Skew -2.088
Setup Relationship 10.000
Logic Level 6
Arrival Clock Path Delay cell: 2.088, 47.897%; route: 2.271, 52.103%
Arrival Data Path Delay cell: 2.043, 31.385%; route: 4.235, 65.051%; tC2Q: 0.232, 3.564%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.271, 100.000%

Path11

Path Summary:

Slack 1.332
Data Arrival Time 10.869
Data Required Time 12.201
From u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_1_G[29]_s0
Launch Clk clkin:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
2.088 2.088 tINS RR 41 IOT27[A] clk_ibuf/O
4.359 2.271 tNET RR 1 R27C37[2][B] u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
4.591 0.232 tC2Q RF 3119 R27C37[2][B] u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
6.190 1.598 tNET FF 1 R17C23[0][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init_s8/I1
6.561 0.371 tINS FF 2 R17C23[0][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init_s8/F
7.221 0.660 tNET FF 1 R14C22[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init_s9/I2
7.592 0.371 tINS FF 14 R14C22[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init_s9/F
8.023 0.431 tNET FF 1 R15C23[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_s35/I0
8.578 0.555 tINS FF 1 R15C23[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_s35/F
8.991 0.413 tNET FF 2 R16C22[1][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n471_s0/I1
9.561 0.570 tINS FR 1 R16C22[1][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n471_s0/COUT
9.561 0.000 tNET RR 2 R16C22[2][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n472_s0/CIN
9.596 0.035 tINS RF 1 R16C22[2][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n472_s0/COUT
9.596 0.000 tNET FF 2 R16C22[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n473_s0/CIN
9.631 0.035 tINS FF 1 R16C22[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n473_s0/COUT
9.631 0.000 tNET FF 2 R16C23[0][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n474_s0/CIN
9.666 0.035 tINS FF 1 R16C23[0][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n474_s0/COUT
9.666 0.000 tNET FF 2 R16C23[0][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n475_s0/CIN
9.702 0.035 tINS FF 1 R16C23[0][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n475_s0/COUT
9.702 0.000 tNET FF 2 R16C23[1][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n476_s0/CIN
9.737 0.035 tINS FF 8 R16C23[1][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n476_s0/COUT
10.869 1.132 tNET FF 1 R16C19[0][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_1_G[29]_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clkx1
10.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
12.271 2.271 tNET RR 1 R16C19[0][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_1_G[29]_s0/CLK
12.236 -0.035 tUnc u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_1_G[29]_s0
12.201 -0.035 tSu 1 R16C19[0][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_1_G[29]_s0

Path Statistics:

Clock Skew -2.088
Setup Relationship 10.000
Logic Level 6
Arrival Clock Path Delay cell: 2.088, 47.897%; route: 2.271, 52.103%
Arrival Data Path Delay cell: 2.043, 31.385%; route: 4.235, 65.051%; tC2Q: 0.232, 3.564%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.271, 100.000%

Path12

Path Summary:

Slack 1.340
Data Arrival Time 10.861
Data Required Time 12.201
From u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_5_G[29]_s0
Launch Clk clkin:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
2.088 2.088 tINS RR 41 IOT27[A] clk_ibuf/O
4.359 2.271 tNET RR 1 R27C37[2][B] u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
4.591 0.232 tC2Q RF 3119 R27C37[2][B] u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
6.190 1.598 tNET FF 1 R17C23[0][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init_s8/I1
6.561 0.371 tINS FF 2 R17C23[0][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init_s8/F
7.221 0.660 tNET FF 1 R14C22[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init_s9/I2
7.592 0.371 tINS FF 14 R14C22[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init_s9/F
8.023 0.431 tNET FF 1 R15C23[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_s35/I0
8.578 0.555 tINS FF 1 R15C23[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_s35/F
8.991 0.413 tNET FF 2 R16C22[1][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n471_s0/I1
9.561 0.570 tINS FR 1 R16C22[1][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n471_s0/COUT
9.561 0.000 tNET RR 2 R16C22[2][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n472_s0/CIN
9.596 0.035 tINS RF 1 R16C22[2][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n472_s0/COUT
9.596 0.000 tNET FF 2 R16C22[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n473_s0/CIN
9.631 0.035 tINS FF 1 R16C22[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n473_s0/COUT
9.631 0.000 tNET FF 2 R16C23[0][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n474_s0/CIN
9.666 0.035 tINS FF 1 R16C23[0][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n474_s0/COUT
9.666 0.000 tNET FF 2 R16C23[0][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n475_s0/CIN
9.702 0.035 tINS FF 1 R16C23[0][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n475_s0/COUT
9.702 0.000 tNET FF 2 R16C23[1][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n476_s0/CIN
9.737 0.035 tINS FF 8 R16C23[1][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n476_s0/COUT
10.861 1.124 tNET FF 1 R16C19[2][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_5_G[29]_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clkx1
10.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
12.271 2.271 tNET RR 1 R16C19[2][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_5_G[29]_s0/CLK
12.236 -0.035 tUnc u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_5_G[29]_s0
12.201 -0.035 tSu 1 R16C19[2][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_5_G[29]_s0

Path Statistics:

Clock Skew -2.088
Setup Relationship 10.000
Logic Level 6
Arrival Clock Path Delay cell: 2.088, 47.897%; route: 2.271, 52.103%
Arrival Data Path Delay cell: 2.043, 31.423%; route: 4.227, 65.009%; tC2Q: 0.232, 3.568%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.271, 100.000%

Path13

Path Summary:

Slack 1.462
Data Arrival Time 10.739
Data Required Time 12.201
From u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_7_G[29]_s0
Launch Clk clkin:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
2.088 2.088 tINS RR 41 IOT27[A] clk_ibuf/O
4.359 2.271 tNET RR 1 R27C37[2][B] u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
4.591 0.232 tC2Q RF 3119 R27C37[2][B] u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
6.190 1.598 tNET FF 1 R17C23[0][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init_s8/I1
6.561 0.371 tINS FF 2 R17C23[0][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init_s8/F
7.221 0.660 tNET FF 1 R14C22[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init_s9/I2
7.592 0.371 tINS FF 14 R14C22[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init_s9/F
8.023 0.431 tNET FF 1 R15C23[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_s35/I0
8.578 0.555 tINS FF 1 R15C23[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_s35/F
8.991 0.413 tNET FF 2 R16C22[1][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n471_s0/I1
9.561 0.570 tINS FR 1 R16C22[1][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n471_s0/COUT
9.561 0.000 tNET RR 2 R16C22[2][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n472_s0/CIN
9.596 0.035 tINS RF 1 R16C22[2][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n472_s0/COUT
9.596 0.000 tNET FF 2 R16C22[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n473_s0/CIN
9.631 0.035 tINS FF 1 R16C22[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n473_s0/COUT
9.631 0.000 tNET FF 2 R16C23[0][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n474_s0/CIN
9.666 0.035 tINS FF 1 R16C23[0][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n474_s0/COUT
9.666 0.000 tNET FF 2 R16C23[0][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n475_s0/CIN
9.702 0.035 tINS FF 1 R16C23[0][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n475_s0/COUT
9.702 0.000 tNET FF 2 R16C23[1][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n476_s0/CIN
9.737 0.035 tINS FF 8 R16C23[1][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n476_s0/COUT
10.739 1.003 tNET FF 1 R17C19[0][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_7_G[29]_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clkx1
10.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
12.271 2.271 tNET RR 1 R17C19[0][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_7_G[29]_s0/CLK
12.236 -0.035 tUnc u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_7_G[29]_s0
12.201 -0.035 tSu 1 R17C19[0][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_7_G[29]_s0

Path Statistics:

Clock Skew -2.088
Setup Relationship 10.000
Logic Level 6
Arrival Clock Path Delay cell: 2.088, 47.897%; route: 2.271, 52.103%
Arrival Data Path Delay cell: 2.043, 32.022%; route: 4.105, 64.342%; tC2Q: 0.232, 3.636%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.271, 100.000%

Path14

Path Summary:

Slack 1.462
Data Arrival Time 10.739
Data Required Time 12.201
From u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_6_G[29]_s0
Launch Clk clkin:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
2.088 2.088 tINS RR 41 IOT27[A] clk_ibuf/O
4.359 2.271 tNET RR 1 R27C37[2][B] u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
4.591 0.232 tC2Q RF 3119 R27C37[2][B] u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
6.190 1.598 tNET FF 1 R17C23[0][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init_s8/I1
6.561 0.371 tINS FF 2 R17C23[0][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init_s8/F
7.221 0.660 tNET FF 1 R14C22[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init_s9/I2
7.592 0.371 tINS FF 14 R14C22[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init_s9/F
8.023 0.431 tNET FF 1 R15C23[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_s35/I0
8.578 0.555 tINS FF 1 R15C23[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_s35/F
8.991 0.413 tNET FF 2 R16C22[1][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n471_s0/I1
9.561 0.570 tINS FR 1 R16C22[1][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n471_s0/COUT
9.561 0.000 tNET RR 2 R16C22[2][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n472_s0/CIN
9.596 0.035 tINS RF 1 R16C22[2][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n472_s0/COUT
9.596 0.000 tNET FF 2 R16C22[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n473_s0/CIN
9.631 0.035 tINS FF 1 R16C22[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n473_s0/COUT
9.631 0.000 tNET FF 2 R16C23[0][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n474_s0/CIN
9.666 0.035 tINS FF 1 R16C23[0][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n474_s0/COUT
9.666 0.000 tNET FF 2 R16C23[0][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n475_s0/CIN
9.702 0.035 tINS FF 1 R16C23[0][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n475_s0/COUT
9.702 0.000 tNET FF 2 R16C23[1][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n476_s0/CIN
9.737 0.035 tINS FF 8 R16C23[1][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n476_s0/COUT
10.739 1.003 tNET FF 1 R17C19[1][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_6_G[29]_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clkx1
10.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
12.271 2.271 tNET RR 1 R17C19[1][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_6_G[29]_s0/CLK
12.236 -0.035 tUnc u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_6_G[29]_s0
12.201 -0.035 tSu 1 R17C19[1][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_6_G[29]_s0

Path Statistics:

Clock Skew -2.088
Setup Relationship 10.000
Logic Level 6
Arrival Clock Path Delay cell: 2.088, 47.897%; route: 2.271, 52.103%
Arrival Data Path Delay cell: 2.043, 32.022%; route: 4.105, 64.342%; tC2Q: 0.232, 3.636%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.271, 100.000%

Path15

Path Summary:

Slack 1.681
Data Arrival Time 10.555
Data Required Time 12.236
From u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0
To u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_RP2AW_s10
Launch Clk clkx1:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
2.271 2.271 tNET RR 1 R20C17[0][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/CLK
2.503 0.232 tC2Q RF 128 R20C17[0][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/Q
4.631 2.128 tNET FF 1 R13C18[3][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s4/I2
5.186 0.555 tINS FF 1 R13C18[3][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s4/F
5.186 0.000 tNET FF 1 R13C18[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s1/I1
5.289 0.103 tINS FF 1 R13C18[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s1/O
5.289 0.000 tNET FF 1 R13C18[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s0/I0
5.392 0.103 tINS FF 7 R13C18[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s0/O
6.350 0.958 tNET FF 1 R23C15[1][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_SREI_s58/I0
6.803 0.453 tINS FF 6 R23C15[1][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_SREI_s58/F
7.753 0.949 tNET FF 1 R24C14[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_SREI_s56/I0
8.206 0.453 tINS FF 3 R24C14[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_SREI_s56/F
8.611 0.406 tNET FF 1 R22C14[2][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s74/I2
8.982 0.371 tINS FF 8 R22C14[2][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s74/F
9.004 0.022 tNET FF 1 R22C14[2][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_RP2AW_s59/I3
9.521 0.517 tINS FF 4 R22C14[2][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_RP2AW_s59/F
10.093 0.572 tNET FF 1 R23C15[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_RP2AW_s56/I2
10.555 0.462 tINS FR 1 R23C15[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_RP2AW_s56/F
10.555 0.000 tNET RR 1 R23C15[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_RP2AW_s10/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clkx1
10.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
12.271 2.271 tNET RR 1 R23C15[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_RP2AW_s10/CLK
12.236 -0.035 tSu 1 R23C15[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_RP2AW_s10

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay cell: 3.017, 36.421%; route: 5.035, 60.779%; tC2Q: 0.232, 2.801%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.271, 100.000%

Path16

Path Summary:

Slack 1.715
Data Arrival Time 10.521
Data Required Time 12.236
From u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0
To u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_ACT2RD_s6
Launch Clk clkx1:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
2.271 2.271 tNET RR 1 R20C17[0][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/CLK
2.503 0.232 tC2Q RF 128 R20C17[0][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/Q
4.631 2.128 tNET FF 1 R13C18[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s3/I2
5.186 0.555 tINS FF 1 R13C18[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s3/F
5.186 0.000 tNET FF 1 R13C18[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s1/I0
5.289 0.103 tINS FF 1 R13C18[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s1/O
5.289 0.000 tNET FF 1 R13C18[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s0/I0
5.392 0.103 tINS FF 7 R13C18[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s0/O
6.350 0.958 tNET FF 1 R23C15[1][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_SREI_s58/I0
6.803 0.453 tINS FF 6 R23C15[1][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_SREI_s58/F
7.753 0.949 tNET FF 1 R24C14[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_SREI_s56/I0
8.206 0.453 tINS FF 3 R24C14[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_SREI_s56/F
8.611 0.406 tNET FF 1 R22C14[2][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s74/I2
8.982 0.371 tINS FF 8 R22C14[2][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s74/F
9.179 0.197 tNET FF 1 R22C15[3][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_ZQ_s56/I1
9.550 0.371 tINS FF 5 R22C15[3][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_ZQ_s56/F
9.972 0.422 tNET FF 1 R22C13[2][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_ACT2RD_s55/I0
10.521 0.549 tINS FR 1 R22C13[2][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_ACT2RD_s55/F
10.521 0.000 tNET RR 1 R22C13[2][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_ACT2RD_s6/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clkx1
10.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
12.271 2.271 tNET RR 1 R22C13[2][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_ACT2RD_s6/CLK
12.236 -0.035 tSu 1 R22C13[2][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_ACT2RD_s6

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay cell: 2.958, 35.854%; route: 5.060, 61.333%; tC2Q: 0.232, 2.812%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.271, 100.000%

Path17

Path Summary:

Slack 1.723
Data Arrival Time 10.513
Data Required Time 12.236
From u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0
To u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_RP2SRE_s14
Launch Clk clkx1:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
2.271 2.271 tNET RR 1 R20C17[0][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/CLK
2.503 0.232 tC2Q RF 128 R20C17[0][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/Q
4.631 2.128 tNET FF 1 R13C18[3][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s4/I2
5.186 0.555 tINS FF 1 R13C18[3][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s4/F
5.186 0.000 tNET FF 1 R13C18[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s1/I1
5.289 0.103 tINS FF 1 R13C18[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s1/O
5.289 0.000 tNET FF 1 R13C18[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s0/I0
5.392 0.103 tINS FF 7 R13C18[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s0/O
6.350 0.958 tNET FF 1 R23C15[1][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_SREI_s58/I0
6.803 0.453 tINS FF 6 R23C15[1][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_SREI_s58/F
7.753 0.949 tNET FF 1 R24C14[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_SREI_s56/I0
8.206 0.453 tINS FF 3 R24C14[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_SREI_s56/F
8.611 0.406 tNET FF 1 R22C14[2][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s74/I2
8.982 0.371 tINS FF 8 R22C14[2][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s74/F
9.004 0.022 tNET FF 1 R22C14[2][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_RP2AW_s59/I3
9.521 0.517 tINS FF 4 R22C14[2][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_RP2AW_s59/F
9.943 0.422 tNET FF 1 R22C16[1][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_RP2SRE_s54/I0
10.513 0.570 tINS FR 1 R22C16[1][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_RP2SRE_s54/F
10.513 0.000 tNET RR 1 R22C16[1][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_RP2SRE_s14/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clkx1
10.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
12.271 2.271 tNET RR 1 R22C16[1][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_RP2SRE_s14/CLK
12.236 -0.035 tSu 1 R22C16[1][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_RP2SRE_s14

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay cell: 3.125, 37.916%; route: 4.885, 59.269%; tC2Q: 0.232, 2.815%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.271, 100.000%

Path18

Path Summary:

Slack 1.755
Data Arrival Time 10.482
Data Required Time 12.236
From u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0
To u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_RP2REF_s14
Launch Clk clkx1:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
2.271 2.271 tNET RR 1 R20C17[0][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/CLK
2.503 0.232 tC2Q RF 128 R20C17[0][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/Q
4.631 2.128 tNET FF 1 R13C18[3][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s4/I2
5.186 0.555 tINS FF 1 R13C18[3][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s4/F
5.186 0.000 tNET FF 1 R13C18[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s1/I1
5.289 0.103 tINS FF 1 R13C18[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s1/O
5.289 0.000 tNET FF 1 R13C18[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s0/I0
5.392 0.103 tINS FF 7 R13C18[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s0/O
6.350 0.958 tNET FF 1 R23C15[1][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_SREI_s58/I0
6.803 0.453 tINS FF 6 R23C15[1][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_SREI_s58/F
7.753 0.949 tNET FF 1 R24C14[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_SREI_s56/I0
8.206 0.453 tINS FF 3 R24C14[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_SREI_s56/F
8.611 0.406 tNET FF 1 R22C14[2][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s74/I2
8.982 0.371 tINS FF 8 R22C14[2][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s74/F
9.004 0.022 tNET FF 1 R22C14[2][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_RP2AW_s59/I3
9.521 0.517 tINS FF 4 R22C14[2][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_RP2AW_s59/F
9.933 0.411 tNET FF 1 R22C16[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_RP2REF_s54/I0
10.482 0.549 tINS FR 1 R22C16[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_RP2REF_s54/F
10.482 0.000 tNET RR 1 R22C16[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_RP2REF_s14/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clkx1
10.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
12.271 2.271 tNET RR 1 R22C16[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_RP2REF_s14/CLK
12.236 -0.035 tSu 1 R22C16[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_RP2REF_s14

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay cell: 3.104, 37.805%; route: 4.874, 59.369%; tC2Q: 0.232, 2.826%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.271, 100.000%

Path19

Path Summary:

Slack 1.787
Data Arrival Time 10.449
Data Required Time 12.236
From u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0
To u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_R2W_s6
Launch Clk clkx1:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
2.271 2.271 tNET RR 1 R20C17[0][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/CLK
2.503 0.232 tC2Q RF 128 R20C17[0][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/Q
4.631 2.128 tNET FF 1 R13C18[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s3/I2
5.186 0.555 tINS FF 1 R13C18[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s3/F
5.186 0.000 tNET FF 1 R13C18[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s1/I0
5.289 0.103 tINS FF 1 R13C18[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s1/O
5.289 0.000 tNET FF 1 R13C18[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s0/I0
5.392 0.103 tINS FF 7 R13C18[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s0/O
6.350 0.958 tNET FF 1 R23C15[1][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_SREI_s58/I0
6.803 0.453 tINS FF 6 R23C15[1][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_SREI_s58/F
7.753 0.949 tNET FF 1 R24C14[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_SREI_s56/I0
8.206 0.453 tINS FF 3 R24C14[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_SREI_s56/F
8.611 0.406 tNET FF 1 R22C14[2][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s74/I2
8.982 0.371 tINS FF 8 R22C14[2][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s74/F
9.179 0.197 tNET FF 1 R22C15[3][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_ZQ_s56/I1
9.550 0.371 tINS FF 5 R22C15[3][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_ZQ_s56/F
9.987 0.437 tNET FF 1 R22C18[0][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_R2W_s54/I2
10.449 0.462 tINS FR 1 R22C18[0][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_R2W_s54/F
10.449 0.000 tNET RR 1 R22C18[0][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_R2W_s6/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clkx1
10.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
12.271 2.271 tNET RR 1 R22C18[0][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_R2W_s6/CLK
12.236 -0.035 tSu 1 R22C18[0][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_R2W_s6

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay cell: 2.871, 35.107%; route: 5.075, 62.056%; tC2Q: 0.232, 2.837%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.271, 100.000%

Path20

Path Summary:

Slack 1.787
Data Arrival Time 10.449
Data Required Time 12.236
From u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0
To u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_W2R_s8
Launch Clk clkx1:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
2.271 2.271 tNET RR 1 R20C17[0][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/CLK
2.503 0.232 tC2Q RF 128 R20C17[0][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/Q
4.631 2.128 tNET FF 1 R13C18[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s3/I2
5.186 0.555 tINS FF 1 R13C18[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s3/F
5.186 0.000 tNET FF 1 R13C18[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s1/I0
5.289 0.103 tINS FF 1 R13C18[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s1/O
5.289 0.000 tNET FF 1 R13C18[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s0/I0
5.392 0.103 tINS FF 7 R13C18[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s0/O
6.350 0.958 tNET FF 1 R23C15[1][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_SREI_s58/I0
6.803 0.453 tINS FF 6 R23C15[1][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_SREI_s58/F
7.753 0.949 tNET FF 1 R24C14[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_SREI_s56/I0
8.206 0.453 tINS FF 3 R24C14[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_SREI_s56/F
8.611 0.406 tNET FF 1 R22C14[2][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s74/I2
8.982 0.371 tINS FF 8 R22C14[2][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s74/F
9.179 0.197 tNET FF 1 R22C15[3][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_ZQ_s56/I1
9.550 0.371 tINS FF 5 R22C15[3][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_ZQ_s56/F
9.987 0.437 tNET FF 1 R22C18[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_W2R_s54/I2
10.449 0.462 tINS FR 1 R22C18[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_W2R_s54/F
10.449 0.000 tNET RR 1 R22C18[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_W2R_s8/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clkx1
10.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
12.271 2.271 tNET RR 1 R22C18[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_W2R_s8/CLK
12.236 -0.035 tSu 1 R22C18[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_W2R_s8

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay cell: 2.871, 35.107%; route: 5.075, 62.056%; tC2Q: 0.232, 2.837%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.271, 100.000%

Path21

Path Summary:

Slack 1.881
Data Arrival Time 10.355
Data Required Time 12.236
From u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0
To u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_ACT2WR_s10
Launch Clk clkx1:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
2.271 2.271 tNET RR 1 R20C17[0][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/CLK
2.503 0.232 tC2Q RF 128 R20C17[0][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/Q
4.631 2.128 tNET FF 1 R13C18[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s3/I2
5.186 0.555 tINS FF 1 R13C18[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s3/F
5.186 0.000 tNET FF 1 R13C18[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s1/I0
5.289 0.103 tINS FF 1 R13C18[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s1/O
5.289 0.000 tNET FF 1 R13C18[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s0/I0
5.392 0.103 tINS FF 7 R13C18[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s0/O
6.350 0.958 tNET FF 1 R23C15[1][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_SREI_s58/I0
6.803 0.453 tINS FF 6 R23C15[1][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_SREI_s58/F
7.753 0.949 tNET FF 1 R24C14[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_SREI_s56/I0
8.206 0.453 tINS FF 3 R24C14[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_SREI_s56/F
8.611 0.406 tNET FF 1 R22C14[2][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s74/I2
8.982 0.371 tINS FF 8 R22C14[2][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s74/F
9.179 0.197 tNET FF 1 R22C15[3][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_ZQ_s56/I1
9.550 0.371 tINS FF 5 R22C15[3][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_ZQ_s56/F
9.806 0.256 tNET FF 1 R22C17[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_ACT2WR_s55/I0
10.355 0.549 tINS FR 1 R22C17[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_ACT2WR_s55/F
10.355 0.000 tNET RR 1 R22C17[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_ACT2WR_s10/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clkx1
10.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
12.271 2.271 tNET RR 1 R22C17[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_ACT2WR_s10/CLK
12.236 -0.035 tSu 1 R22C17[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_ACT2WR_s10

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay cell: 2.958, 36.591%; route: 4.894, 60.539%; tC2Q: 0.232, 2.870%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.271, 100.000%

Path22

Path Summary:

Slack 1.952
Data Arrival Time 10.284
Data Required Time 12.236
From u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0
To u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_WP2REF_s14
Launch Clk clkx1:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
2.271 2.271 tNET RR 1 R20C17[0][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/CLK
2.503 0.232 tC2Q RF 128 R20C17[0][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/Q
4.631 2.128 tNET FF 1 R13C18[3][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s4/I2
5.186 0.555 tINS FF 1 R13C18[3][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s4/F
5.186 0.000 tNET FF 1 R13C18[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s1/I1
5.289 0.103 tINS FF 1 R13C18[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s1/O
5.289 0.000 tNET FF 1 R13C18[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s0/I0
5.392 0.103 tINS FF 7 R13C18[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s0/O
6.350 0.958 tNET FF 1 R23C15[1][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_SREI_s58/I0
6.803 0.453 tINS FF 6 R23C15[1][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_SREI_s58/F
7.753 0.949 tNET FF 1 R24C14[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_SREI_s56/I0
8.206 0.453 tINS FF 3 R24C14[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_SREI_s56/F
8.611 0.406 tNET FF 1 R22C14[2][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s74/I2
8.982 0.371 tINS FF 8 R22C14[2][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s74/F
9.004 0.022 tNET FF 1 R22C14[3][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WP2AW_s58/I2
9.553 0.549 tINS FR 4 R22C14[3][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WP2AW_s58/F
9.735 0.182 tNET RR 1 R22C13[0][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WP2REF_s54/I0
10.284 0.549 tINS RR 1 R22C13[0][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WP2REF_s54/F
10.284 0.000 tNET RR 1 R22C13[0][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_WP2REF_s14/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clkx1
10.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
12.271 2.271 tNET RR 1 R22C13[0][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_WP2REF_s14/CLK
12.236 -0.035 tSu 1 R22C13[0][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_WP2REF_s14

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay cell: 3.136, 39.136%; route: 4.645, 57.968%; tC2Q: 0.232, 2.895%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.271, 100.000%

Path23

Path Summary:

Slack 1.952
Data Arrival Time 10.284
Data Required Time 12.236
From u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0
To u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_WP2AR_s8
Launch Clk clkx1:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
2.271 2.271 tNET RR 1 R20C17[0][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/CLK
2.503 0.232 tC2Q RF 128 R20C17[0][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/Q
4.631 2.128 tNET FF 1 R13C18[3][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s4/I2
5.186 0.555 tINS FF 1 R13C18[3][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s4/F
5.186 0.000 tNET FF 1 R13C18[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s1/I1
5.289 0.103 tINS FF 1 R13C18[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s1/O
5.289 0.000 tNET FF 1 R13C18[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s0/I0
5.392 0.103 tINS FF 7 R13C18[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s0/O
6.350 0.958 tNET FF 1 R23C15[1][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_SREI_s58/I0
6.803 0.453 tINS FF 6 R23C15[1][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_SREI_s58/F
7.753 0.949 tNET FF 1 R24C14[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_SREI_s56/I0
8.206 0.453 tINS FF 3 R24C14[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_SREI_s56/F
8.611 0.406 tNET FF 1 R22C14[2][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s74/I2
8.982 0.371 tINS FF 8 R22C14[2][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s74/F
9.004 0.022 tNET FF 1 R22C14[3][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WP2AW_s58/I2
9.553 0.549 tINS FR 4 R22C14[3][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WP2AW_s58/F
9.735 0.182 tNET RR 1 R22C13[1][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WP2AR_s55/I2
10.284 0.549 tINS RR 1 R22C13[1][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WP2AR_s55/F
10.284 0.000 tNET RR 1 R22C13[1][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_WP2AR_s8/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clkx1
10.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
12.271 2.271 tNET RR 1 R22C13[1][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_WP2AR_s8/CLK
12.236 -0.035 tSu 1 R22C13[1][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_WP2AR_s8

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay cell: 3.136, 39.136%; route: 4.645, 57.968%; tC2Q: 0.232, 2.895%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.271, 100.000%

Path24

Path Summary:

Slack 1.952
Data Arrival Time 10.284
Data Required Time 12.236
From u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0
To u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_WP2AW_s12
Launch Clk clkx1:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
2.271 2.271 tNET RR 1 R20C17[0][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/CLK
2.503 0.232 tC2Q RF 128 R20C17[0][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/Q
4.631 2.128 tNET FF 1 R13C18[3][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s4/I2
5.186 0.555 tINS FF 1 R13C18[3][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s4/F
5.186 0.000 tNET FF 1 R13C18[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s1/I1
5.289 0.103 tINS FF 1 R13C18[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s1/O
5.289 0.000 tNET FF 1 R13C18[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s0/I0
5.392 0.103 tINS FF 7 R13C18[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s0/O
6.350 0.958 tNET FF 1 R23C15[1][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_SREI_s58/I0
6.803 0.453 tINS FF 6 R23C15[1][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_SREI_s58/F
7.753 0.949 tNET FF 1 R24C14[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_SREI_s56/I0
8.206 0.453 tINS FF 3 R24C14[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_SREI_s56/F
8.611 0.406 tNET FF 1 R22C14[2][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s74/I2
8.982 0.371 tINS FF 8 R22C14[2][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s74/F
9.004 0.022 tNET FF 1 R22C14[3][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WP2AW_s58/I2
9.553 0.549 tINS FR 4 R22C14[3][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WP2AW_s58/F
9.735 0.182 tNET RR 1 R22C13[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WP2AW_s56/I2
10.284 0.549 tINS RR 1 R22C13[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WP2AW_s56/F
10.284 0.000 tNET RR 1 R22C13[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_WP2AW_s12/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clkx1
10.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
12.271 2.271 tNET RR 1 R22C13[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_WP2AW_s12/CLK
12.236 -0.035 tSu 1 R22C13[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_WP2AW_s12

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay cell: 3.136, 39.136%; route: 4.645, 57.968%; tC2Q: 0.232, 2.895%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.271, 100.000%

Path25

Path Summary:

Slack 1.970
Data Arrival Time 10.267
Data Required Time 12.236
From u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0
To u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/idle1_s0
Launch Clk clkx1:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
2.271 2.271 tNET RR 1 R20C17[0][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/CLK
2.503 0.232 tC2Q RF 128 R20C17[0][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/Q
4.631 2.128 tNET FF 1 R13C18[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s3/I2
5.186 0.555 tINS FF 1 R13C18[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s3/F
5.186 0.000 tNET FF 1 R13C18[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s1/I0
5.289 0.103 tINS FF 1 R13C18[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s1/O
5.289 0.000 tNET FF 1 R13C18[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s0/I0
5.392 0.103 tINS FF 7 R13C18[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s0/O
6.350 0.958 tNET FF 1 R23C15[1][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_SREI_s58/I0
6.803 0.453 tINS FF 6 R23C15[1][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_SREI_s58/F
7.753 0.949 tNET FF 1 R24C14[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_SREI_s56/I0
8.215 0.462 tINS FR 3 R24C14[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_SREI_s56/F
8.390 0.175 tNET RR 1 R23C14[2][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_IDLE_s71/I2
8.960 0.570 tINS RR 1 R23C14[2][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_IDLE_s71/F
8.961 0.001 tNET RR 1 R23C14[3][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_IDLE_s68/I3
9.478 0.517 tINS RF 2 R23C14[3][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_IDLE_s68/F
10.267 0.789 tNET FF 1 R24C15[0][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/idle1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clkx1
10.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
12.271 2.271 tNET RR 1 R24C15[0][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/idle1_s0/CLK
12.236 -0.035 tSu 1 R24C15[0][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/idle1_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay cell: 2.763, 34.558%; route: 5.000, 62.541%; tC2Q: 0.232, 2.902%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.271, 100.000%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 0.074
Data Arrival Time 1.834
Data Required Time 1.760
From u_ddr3/gw3_top/u_ddr_phy_top/mux_wrdata_60_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_2_s
Launch Clk clkx1:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R27C32[0][A] u_ddr3/gw3_top/u_ddr_phy_top/mux_wrdata_60_s0/CLK
1.712 0.201 tC2Q RF 1 R27C32[0][A] u_ddr3/gw3_top/u_ddr_phy_top/mux_wrdata_60_s0/Q
1.834 0.122 tNET FF 1 BSRAM_R28[8] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_2_s/DI[3]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 BSRAM_R28[8] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_2_s/CLKA
1.760 0.249 tHld 1 BSRAM_R28[8] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_2_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.122, 37.751%; tC2Q: 0.201, 62.249%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%

Path2

Path Summary:

Slack 0.076
Data Arrival Time 1.836
Data Required Time 1.760
From u_ddr3/gw3_top/u_ddr_phy_top/mux_wrdata_12_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_2_s
Launch Clk clkx1:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R30C32[1][A] u_ddr3/gw3_top/u_ddr_phy_top/mux_wrdata_12_s0/CLK
1.713 0.202 tC2Q RR 1 R30C32[1][A] u_ddr3/gw3_top/u_ddr_phy_top/mux_wrdata_12_s0/Q
1.836 0.123 tNET RR 1 BSRAM_R28[8] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_2_s/DI[0]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 BSRAM_R28[8] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_2_s/CLKA
1.760 0.249 tHld 1 BSRAM_R28[8] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_2_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.123, 37.889%; tC2Q: 0.202, 62.111%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%

Path3

Path Summary:

Slack 0.198
Data Arrival Time 1.958
Data Required Time 1.760
From u_ddr3/gw3_top/u_ddr_phy_top/mux_wrdata_29_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_2_s
Launch Clk clkx1:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R32C32[2][A] u_ddr3/gw3_top/u_ddr_phy_top/mux_wrdata_29_s0/CLK
1.713 0.202 tC2Q RR 1 R32C32[2][A] u_ddr3/gw3_top/u_ddr_phy_top/mux_wrdata_29_s0/Q
1.958 0.245 tNET RR 1 BSRAM_R28[8] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_2_s/DI[9]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 BSRAM_R28[8] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_2_s/CLKA
1.760 0.249 tHld 1 BSRAM_R28[8] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_2_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.245, 54.832%; tC2Q: 0.202, 45.168%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%

Path4

Path Summary:

Slack 0.198
Data Arrival Time 1.958
Data Required Time 1.760
From u_ddr3/gw3_top/u_ddr_phy_top/mux_wrdata_28_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_2_s
Launch Clk clkx1:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R26C34[0][A] u_ddr3/gw3_top/u_ddr_phy_top/mux_wrdata_28_s0/CLK
1.713 0.202 tC2Q RR 1 R26C34[0][A] u_ddr3/gw3_top/u_ddr_phy_top/mux_wrdata_28_s0/Q
1.958 0.245 tNET RR 1 BSRAM_R28[8] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_2_s/DI[1]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 BSRAM_R28[8] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_2_s/CLKA
1.760 0.249 tHld 1 BSRAM_R28[8] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_2_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.245, 54.832%; tC2Q: 0.202, 45.168%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%

Path5

Path Summary:

Slack 0.213
Data Arrival Time 1.974
Data Required Time 1.760
From u_ddr3/gw3_top/u_ddr_phy_top/mux_wrdata_34_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_3_s
Launch Clk clkx1:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R29C34[1][B] u_ddr3/gw3_top/u_ddr_phy_top/mux_wrdata_34_s0/CLK
1.713 0.202 tC2Q RR 1 R29C34[1][B] u_ddr3/gw3_top/u_ddr_phy_top/mux_wrdata_34_s0/Q
1.974 0.260 tNET RR 1 BSRAM_R28[9] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_3_s/DI[22]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 BSRAM_R28[9] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_3_s/CLKA
1.760 0.249 tHld 1 BSRAM_R28[9] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_3_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%

Path6

Path Summary:

Slack 0.213
Data Arrival Time 1.974
Data Required Time 1.760
From u_ddr3/gw3_top/u_ddr_phy_top/mux_wrdata_1_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_3_s
Launch Clk clkx1:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R26C35[2][B] u_ddr3/gw3_top/u_ddr_phy_top/mux_wrdata_1_s0/CLK
1.713 0.202 tC2Q RR 1 R26C35[2][B] u_ddr3/gw3_top/u_ddr_phy_top/mux_wrdata_1_s0/Q
1.974 0.260 tNET RR 1 BSRAM_R28[9] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_3_s/DI[12]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 BSRAM_R28[9] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_3_s/CLKA
1.760 0.249 tHld 1 BSRAM_R28[9] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_3_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%

Path7

Path Summary:

Slack 0.213
Data Arrival Time 1.974
Data Required Time 1.760
From u_ddr3/gw3_top/u_ddr_phy_top/mux_wrdata_32_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_3_s
Launch Clk clkx1:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R27C34[0][A] u_ddr3/gw3_top/u_ddr_phy_top/mux_wrdata_32_s0/CLK
1.713 0.202 tC2Q RR 1 R27C34[0][A] u_ddr3/gw3_top/u_ddr_phy_top/mux_wrdata_32_s0/Q
1.974 0.260 tNET RR 1 BSRAM_R28[9] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_3_s/DI[6]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 BSRAM_R28[9] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_3_s/CLKA
1.760 0.249 tHld 1 BSRAM_R28[9] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_3_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%

Path8

Path Summary:

Slack 0.213
Data Arrival Time 1.974
Data Required Time 1.760
From u_ddr3/gw3_top/u_ddr_phy_top/mux_wrdata_62_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_2_s
Launch Clk clkx1:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R27C32[0][B] u_ddr3/gw3_top/u_ddr_phy_top/mux_wrdata_62_s0/CLK
1.713 0.202 tC2Q RR 1 R27C32[0][B] u_ddr3/gw3_top/u_ddr_phy_top/mux_wrdata_62_s0/Q
1.974 0.260 tNET RR 1 BSRAM_R28[8] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_2_s/DI[19]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 BSRAM_R28[8] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_2_s/CLKA
1.760 0.249 tHld 1 BSRAM_R28[8] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_2_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%

Path9

Path Summary:

Slack 0.213
Data Arrival Time 1.974
Data Required Time 1.760
From u_ddr3/gw3_top/u_ddr_phy_top/mux_wrdata_14_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_2_s
Launch Clk clkx1:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R30C32[0][B] u_ddr3/gw3_top/u_ddr_phy_top/mux_wrdata_14_s0/CLK
1.713 0.202 tC2Q RR 1 R30C32[0][B] u_ddr3/gw3_top/u_ddr_phy_top/mux_wrdata_14_s0/Q
1.974 0.260 tNET RR 1 BSRAM_R28[8] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_2_s/DI[16]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 BSRAM_R28[8] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_2_s/CLKA
1.760 0.249 tHld 1 BSRAM_R28[8] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_2_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%

Path10

Path Summary:

Slack 0.213
Data Arrival Time 1.974
Data Required Time 1.760
From u_ddr3/gw3_top/u_ddr_phy_top/mux_wrdata_45_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_2_s
Launch Clk clkx1:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R27C34[2][B] u_ddr3/gw3_top/u_ddr_phy_top/mux_wrdata_45_s0/CLK
1.713 0.202 tC2Q RR 1 R27C34[2][B] u_ddr3/gw3_top/u_ddr_phy_top/mux_wrdata_45_s0/Q
1.974 0.260 tNET RR 1 BSRAM_R28[8] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_2_s/DI[10]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 BSRAM_R28[8] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_2_s/CLKA
1.760 0.249 tHld 1 BSRAM_R28[8] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_2_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%

Path11

Path Summary:

Slack 0.225
Data Arrival Time 1.986
Data Required Time 1.760
From u_ddr3/gw3_top/u_ddr_phy_top/mux_wrdata_66_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_3_s
Launch Clk clkx1:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R27C44[2][A] u_ddr3/gw3_top/u_ddr_phy_top/mux_wrdata_66_s0/CLK
1.713 0.202 tC2Q RR 1 R27C44[2][A] u_ddr3/gw3_top/u_ddr_phy_top/mux_wrdata_66_s0/Q
1.986 0.272 tNET RR 1 BSRAM_R28[9] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_3_s/DI[24]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 BSRAM_R28[9] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_3_s/CLKA
1.760 0.249 tHld 1 BSRAM_R28[9] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_3_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.272, 57.427%; tC2Q: 0.202, 42.573%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%

Path12

Path Summary:

Slack 0.225
Data Arrival Time 1.986
Data Required Time 1.760
From u_ddr3/gw3_top/u_ddr_phy_top/mux_wrdata_65_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_3_s
Launch Clk clkx1:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R27C32[1][B] u_ddr3/gw3_top/u_ddr_phy_top/mux_wrdata_65_s0/CLK
1.713 0.202 tC2Q RR 1 R27C32[1][B] u_ddr3/gw3_top/u_ddr_phy_top/mux_wrdata_65_s0/Q
1.986 0.272 tNET RR 1 BSRAM_R28[9] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_3_s/DI[16]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 BSRAM_R28[9] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_3_s/CLKA
1.760 0.249 tHld 1 BSRAM_R28[9] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_3_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.272, 57.427%; tC2Q: 0.202, 42.573%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%

Path13

Path Summary:

Slack 0.225
Data Arrival Time 1.986
Data Required Time 1.760
From u_ddr3/gw3_top/u_ddr_phy_top/mux_wrdata_47_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_2_s
Launch Clk clkx1:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R27C42[0][B] u_ddr3/gw3_top/u_ddr_phy_top/mux_wrdata_47_s0/CLK
1.713 0.202 tC2Q RR 1 R27C42[0][B] u_ddr3/gw3_top/u_ddr_phy_top/mux_wrdata_47_s0/Q
1.986 0.272 tNET RR 1 BSRAM_R28[8] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_2_s/DI[26]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 BSRAM_R28[8] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_2_s/CLKA
1.760 0.249 tHld 1 BSRAM_R28[8] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_2_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.272, 57.427%; tC2Q: 0.202, 42.573%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%

Path14

Path Summary:

Slack 0.311
Data Arrival Time 1.834
Data Required Time 1.523
From u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_3_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s
Launch Clk clkx1:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R34C19[1][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_3_s0/CLK
1.712 0.201 tC2Q RF 1 R34C19[1][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_3_s0/Q
1.834 0.122 tNET FF 1 R33C19 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[3]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R33C19 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLK
1.523 0.012 tHld 1 R33C19 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.122, 37.751%; tC2Q: 0.201, 62.249%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%

Path15

Path Summary:

Slack 0.311
Data Arrival Time 1.834
Data Required Time 1.523
From u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_2_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s
Launch Clk clkx1:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R34C19[2][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_2_s0/CLK
1.712 0.201 tC2Q RF 1 R34C19[2][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_2_s0/Q
1.834 0.122 tNET FF 1 R33C19 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[2]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R33C19 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLK
1.523 0.012 tHld 1 R33C19 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.122, 37.751%; tC2Q: 0.201, 62.249%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%

Path16

Path Summary:

Slack 0.311
Data Arrival Time 1.834
Data Required Time 1.523
From u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_1_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s
Launch Clk clkx1:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R34C19[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_1_s0/CLK
1.712 0.201 tC2Q RF 1 R34C19[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_1_s0/Q
1.834 0.122 tNET FF 1 R33C19 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[1]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R33C19 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLK
1.523 0.012 tHld 1 R33C19 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.122, 37.751%; tC2Q: 0.201, 62.249%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%

Path17

Path Summary:

Slack 0.311
Data Arrival Time 1.834
Data Required Time 1.523
From u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_40_s0
To u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_10_s
Launch Clk clkx1:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R13C31[1][B] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_40_s0/CLK
1.712 0.201 tC2Q RF 1 R13C31[1][B] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_40_s0/Q
1.834 0.122 tNET FF 1 R14C31 u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_10_s/DI[0]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R14C31 u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_10_s/CLK
1.523 0.012 tHld 1 R14C31 u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_10_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.122, 37.751%; tC2Q: 0.201, 62.249%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%

Path18

Path Summary:

Slack 0.313
Data Arrival Time 1.836
Data Required Time 1.523
From u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_4_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s
Launch Clk clkx1:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R34C20[1][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_4_s0/CLK
1.713 0.202 tC2Q RR 1 R34C20[1][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_4_s0/Q
1.836 0.123 tNET RR 1 R32C20 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/DI[0]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R32C20 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/CLK
1.523 0.012 tHld 1 R32C20 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.123, 37.889%; tC2Q: 0.202, 62.111%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%

Path19

Path Summary:

Slack 0.313
Data Arrival Time 1.836
Data Required Time 1.523
From u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_127_s0
To u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_31_s
Launch Clk clkx1:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R14C42[0][A] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_127_s0/CLK
1.713 0.202 tC2Q RR 1 R14C42[0][A] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_127_s0/Q
1.836 0.123 tNET RR 1 R14C40 u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_31_s/DI[3]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R14C40 u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_31_s/CLK
1.523 0.012 tHld 1 R14C40 u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_31_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.123, 37.889%; tC2Q: 0.202, 62.111%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%

Path20

Path Summary:

Slack 0.314
Data Arrival Time 1.838
Data Required Time 1.523
From u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/wstep_reg_13_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/wstep_reg_d_0_s14
Launch Clk clkx1:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R35C44[2][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/wstep_reg_13_s0/CLK
1.713 0.202 tC2Q RR 2 R35C44[2][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/wstep_reg_13_s0/Q
1.838 0.124 tNET RR 1 R33C44 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/wstep_reg_d_0_s14/DI[1]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R33C44 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/wstep_reg_d_0_s14/CLK
1.523 0.012 tHld 1 R33C44 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/wstep_reg_d_0_s14

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.124, 38.121%; tC2Q: 0.202, 61.879%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%

Path21

Path Summary:

Slack 0.314
Data Arrival Time 1.838
Data Required Time 1.523
From u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/wstep_reg_2_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/wstep_reg_d_0_s8
Launch Clk clkx1:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R35C42[1][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/wstep_reg_2_s0/CLK
1.713 0.202 tC2Q RR 2 R35C42[1][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/wstep_reg_2_s0/Q
1.838 0.124 tNET RR 1 R33C42 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/wstep_reg_d_0_s8/DI[2]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R33C42 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/wstep_reg_d_0_s8/CLK
1.523 0.012 tHld 1 R33C42 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/wstep_reg_d_0_s8

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.124, 38.121%; tC2Q: 0.202, 61.879%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%

Path22

Path Summary:

Slack 0.317
Data Arrival Time 1.839
Data Required Time 1.522
From u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_calibration_logic_gen[1].read_adj_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_calibration_logic_gen[1].read_i_3_s0
Launch Clk clkx1:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R33C41[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_calibration_logic_gen[1].read_adj_s0/CLK
1.713 0.202 tC2Q RR 4 R33C41[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_calibration_logic_gen[1].read_adj_s0/Q
1.839 0.126 tNET RR 1 R33C40[2][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_calibration_logic_gen[1].read_i_3_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R33C40[2][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_calibration_logic_gen[1].read_i_3_s0/CLK
1.522 0.011 tHld 1 R33C40[2][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_calibration_logic_gen[1].read_i_3_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.126, 38.352%; tC2Q: 0.202, 61.648%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%

Path23

Path Summary:

Slack 0.318
Data Arrival Time 1.840
Data Required Time 1.522
From u_ddr3/gw3_top/u_ddr_phy_top/u_init_rmove_mod/init_rmove_done_rr_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_init_rmove_mod/rdir_1_s0
Launch Clk clkx1:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R38C45[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_init_rmove_mod/init_rmove_done_rr_s0/CLK
1.713 0.202 tC2Q RR 1 R38C45[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_init_rmove_mod/init_rmove_done_rr_s0/Q
1.840 0.127 tNET RR 1 R38C45[1][A] u_ddr3/gw3_top/u_ddr_phy_top/u_init_rmove_mod/rdir_1_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R38C45[1][A] u_ddr3/gw3_top/u_ddr_phy_top/u_init_rmove_mod/rdir_1_s0/CLK
1.522 0.011 tHld 1 R38C45[1][A] u_ddr3/gw3_top/u_ddr_phy_top/u_init_rmove_mod/rdir_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.127, 38.638%; tC2Q: 0.202, 61.362%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%

Path24

Path Summary:

Slack 0.319
Data Arrival Time 1.842
Data Required Time 1.522
From u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_cal_state.READ_CAL_DONE_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_cal_complete_s0
Launch Clk clkx1:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R29C44[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_cal_state.READ_CAL_DONE_s0/CLK
1.713 0.202 tC2Q RR 2 R29C44[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_cal_state.READ_CAL_DONE_s0/Q
1.842 0.128 tNET RR 1 R29C44[1][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_cal_complete_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R29C44[1][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_cal_complete_s0/CLK
1.522 0.011 tHld 1 R29C44[1][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_cal_complete_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.128, 38.865%; tC2Q: 0.202, 61.135%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%

Path25

Path Summary:

Slack 0.319
Data Arrival Time 1.842
Data Required Time 1.522
From u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/wrlvl_state.WRLVL_DONE_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/wrlvl_complete_s0
Launch Clk clkx1:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R31C45[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/wrlvl_state.WRLVL_DONE_s0/CLK
1.713 0.202 tC2Q RR 2 R31C45[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/wrlvl_state.WRLVL_DONE_s0/Q
1.842 0.128 tNET RR 1 R31C45[2][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/wrlvl_complete_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R31C45[2][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/wrlvl_complete_s0/CLK
1.522 0.011 tHld 1 R31C45[2][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/wrlvl_complete_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.128, 38.865%; tC2Q: 0.202, 61.135%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 1.257
Data Arrival Time 5.947
Data Required Time 7.204
From u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_calibration_logic_gen[1].rburst_neg_s0
Launch Clk clkin:[R]
Latch Clk clkx1:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
2.088 2.088 tINS RR 41 IOT27[A] clk_ibuf/O
4.359 2.271 tNET RR 1 R27C37[2][B] u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
4.591 0.232 tC2Q RF 3119 R27C37[2][B] u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
5.947 1.356 tNET FF 1 R31C40[2][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_calibration_logic_gen[1].rburst_neg_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clkx1
5.000 0.000 tCL FF 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
7.274 2.274 tNET FF 1 R31C40[2][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_calibration_logic_gen[1].rburst_neg_s0/CLK
7.239 -0.035 tUnc u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_calibration_logic_gen[1].rburst_neg_s0
7.204 -0.035 tSu 1 R31C40[2][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_calibration_logic_gen[1].rburst_neg_s0

Path Statistics:

Clock Skew -2.085
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 2.088, 47.897%; route: 2.271, 52.103%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.356, 85.387%; tC2Q: 0.232, 14.613%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.274, 100.000%

Path2

Path Summary:

Slack 1.257
Data Arrival Time 5.947
Data Required Time 7.204
From u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_calibration_logic_gen[0].rburst_neg_s0
Launch Clk clkin:[R]
Latch Clk clkx1:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
2.088 2.088 tINS RR 41 IOT27[A] clk_ibuf/O
4.359 2.271 tNET RR 1 R27C37[2][B] u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
4.591 0.232 tC2Q RF 3119 R27C37[2][B] u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
5.947 1.356 tNET FF 1 R30C37[2][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_calibration_logic_gen[0].rburst_neg_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clkx1
5.000 0.000 tCL FF 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
7.274 2.274 tNET FF 1 R30C37[2][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_calibration_logic_gen[0].rburst_neg_s0/CLK
7.239 -0.035 tUnc u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_calibration_logic_gen[0].rburst_neg_s0
7.204 -0.035 tSu 1 R30C37[2][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_calibration_logic_gen[0].rburst_neg_s0

Path Statistics:

Clock Skew -2.085
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 2.088, 47.897%; route: 2.271, 52.103%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.356, 85.387%; tC2Q: 0.232, 14.613%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.274, 100.000%

Path3

Path Summary:

Slack 5.002
Data Arrival Time 7.199
Data Required Time 12.201
From u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_Empty_reg_s0
Launch Clk clkin:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
2.088 2.088 tINS RR 41 IOT27[A] clk_ibuf/O
4.359 2.271 tNET RR 1 R27C37[2][B] u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
4.591 0.232 tC2Q RF 3119 R27C37[2][B] u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
6.190 1.598 tNET FF 1 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I0
6.561 0.371 tINS FF 40 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
7.199 0.639 tNET FF 1 R45C21[2][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_Empty_reg_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clkx1
10.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
12.271 2.271 tNET RR 1 R45C21[2][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_Empty_reg_s0/CLK
12.236 -0.035 tUnc u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_Empty_reg_s0
12.201 -0.035 tSu 1 R45C21[2][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_Empty_reg_s0

Path Statistics:

Clock Skew -2.088
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 2.088, 47.897%; route: 2.271, 52.103%
Arrival Data Path Delay cell: 0.371, 13.063%; route: 2.237, 78.768%; tC2Q: 0.232, 8.169%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.271, 100.000%

Path4

Path Summary:

Slack 5.002
Data Arrival Time 7.199
Data Required Time 12.201
From u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_3_s0
Launch Clk clkin:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
2.088 2.088 tINS RR 41 IOT27[A] clk_ibuf/O
4.359 2.271 tNET RR 1 R27C37[2][B] u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
4.591 0.232 tC2Q RF 3119 R27C37[2][B] u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
6.190 1.598 tNET FF 1 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I0
6.561 0.371 tINS FF 40 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
7.199 0.639 tNET FF 1 R44C20[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_3_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clkx1
10.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
12.271 2.271 tNET RR 1 R44C20[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_3_s0/CLK
12.236 -0.035 tUnc u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_3_s0
12.201 -0.035 tSu 1 R44C20[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_3_s0

Path Statistics:

Clock Skew -2.088
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 2.088, 47.897%; route: 2.271, 52.103%
Arrival Data Path Delay cell: 0.371, 13.063%; route: 2.237, 78.768%; tC2Q: 0.232, 8.169%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.271, 100.000%

Path5

Path Summary:

Slack 5.002
Data Arrival Time 7.199
Data Required Time 12.201
From u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_0_s0
Launch Clk clkin:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
2.088 2.088 tINS RR 41 IOT27[A] clk_ibuf/O
4.359 2.271 tNET RR 1 R27C37[2][B] u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
4.591 0.232 tC2Q RF 3119 R27C37[2][B] u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
6.190 1.598 tNET FF 1 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I0
6.561 0.371 tINS FF 40 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
7.199 0.639 tNET FF 1 R47C20[2][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clkx1
10.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
12.271 2.271 tNET RR 1 R47C20[2][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_0_s0/CLK
12.236 -0.035 tUnc u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_0_s0
12.201 -0.035 tSu 1 R47C20[2][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_0_s0

Path Statistics:

Clock Skew -2.088
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 2.088, 47.897%; route: 2.271, 52.103%
Arrival Data Path Delay cell: 0.371, 13.063%; route: 2.237, 78.768%; tC2Q: 0.232, 8.169%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.271, 100.000%

Path6

Path Summary:

Slack 5.002
Data Arrival Time 7.199
Data Required Time 12.201
From u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_1_s0
Launch Clk clkin:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
2.088 2.088 tINS RR 41 IOT27[A] clk_ibuf/O
4.359 2.271 tNET RR 1 R27C37[2][B] u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
4.591 0.232 tC2Q RF 3119 R27C37[2][B] u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
6.190 1.598 tNET FF 1 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I0
6.561 0.371 tINS FF 40 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
7.199 0.639 tNET FF 1 R43C20[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clkx1
10.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
12.271 2.271 tNET RR 1 R43C20[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_1_s0/CLK
12.236 -0.035 tUnc u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_1_s0
12.201 -0.035 tSu 1 R43C20[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_1_s0

Path Statistics:

Clock Skew -2.088
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 2.088, 47.897%; route: 2.271, 52.103%
Arrival Data Path Delay cell: 0.371, 13.063%; route: 2.237, 78.768%; tC2Q: 0.232, 8.169%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.271, 100.000%

Path7

Path Summary:

Slack 5.002
Data Arrival Time 7.199
Data Required Time 12.201
From u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_2_s0
Launch Clk clkin:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
2.088 2.088 tINS RR 41 IOT27[A] clk_ibuf/O
4.359 2.271 tNET RR 1 R27C37[2][B] u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
4.591 0.232 tC2Q RF 3119 R27C37[2][B] u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
6.190 1.598 tNET FF 1 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I0
6.561 0.371 tINS FF 40 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
7.199 0.639 tNET FF 1 R44C20[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_2_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clkx1
10.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
12.271 2.271 tNET RR 1 R44C20[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_2_s0/CLK
12.236 -0.035 tUnc u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_2_s0
12.201 -0.035 tSu 1 R44C20[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_2_s0

Path Statistics:

Clock Skew -2.088
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 2.088, 47.897%; route: 2.271, 52.103%
Arrival Data Path Delay cell: 0.371, 13.063%; route: 2.237, 78.768%; tC2Q: 0.232, 8.169%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.271, 100.000%

Path8

Path Summary:

Slack 5.002
Data Arrival Time 7.199
Data Required Time 12.201
From u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_3_s0
Launch Clk clkin:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
2.088 2.088 tINS RR 41 IOT27[A] clk_ibuf/O
4.359 2.271 tNET RR 1 R27C37[2][B] u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
4.591 0.232 tC2Q RF 3119 R27C37[2][B] u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
6.190 1.598 tNET FF 1 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I0
6.561 0.371 tINS FF 40 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
7.199 0.639 tNET FF 1 R45C20[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_3_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clkx1
10.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
12.271 2.271 tNET RR 1 R45C20[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_3_s0/CLK
12.236 -0.035 tUnc u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_3_s0
12.201 -0.035 tSu 1 R45C20[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_3_s0

Path Statistics:

Clock Skew -2.088
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 2.088, 47.897%; route: 2.271, 52.103%
Arrival Data Path Delay cell: 0.371, 13.063%; route: 2.237, 78.768%; tC2Q: 0.232, 8.169%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.271, 100.000%

Path9

Path Summary:

Slack 5.002
Data Arrival Time 7.199
Data Required Time 12.201
From u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_0_s0
Launch Clk clkin:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
2.088 2.088 tINS RR 41 IOT27[A] clk_ibuf/O
4.359 2.271 tNET RR 1 R27C37[2][B] u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
4.591 0.232 tC2Q RF 3119 R27C37[2][B] u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
6.190 1.598 tNET FF 1 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I0
6.561 0.371 tINS FF 40 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
7.199 0.639 tNET FF 1 R44C21[1][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clkx1
10.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
12.271 2.271 tNET RR 1 R44C21[1][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_0_s0/CLK
12.236 -0.035 tUnc u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_0_s0
12.201 -0.035 tSu 1 R44C21[1][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_0_s0

Path Statistics:

Clock Skew -2.088
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 2.088, 47.897%; route: 2.271, 52.103%
Arrival Data Path Delay cell: 0.371, 13.063%; route: 2.237, 78.768%; tC2Q: 0.232, 8.169%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.271, 100.000%

Path10

Path Summary:

Slack 5.002
Data Arrival Time 7.199
Data Required Time 12.201
From u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_1_s0
Launch Clk clkin:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
2.088 2.088 tINS RR 41 IOT27[A] clk_ibuf/O
4.359 2.271 tNET RR 1 R27C37[2][B] u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
4.591 0.232 tC2Q RF 3119 R27C37[2][B] u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
6.190 1.598 tNET FF 1 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I0
6.561 0.371 tINS FF 40 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
7.199 0.639 tNET FF 1 R44C20[1][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clkx1
10.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
12.271 2.271 tNET RR 1 R44C20[1][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_1_s0/CLK
12.236 -0.035 tUnc u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_1_s0
12.201 -0.035 tSu 1 R44C20[1][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_1_s0

Path Statistics:

Clock Skew -2.088
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 2.088, 47.897%; route: 2.271, 52.103%
Arrival Data Path Delay cell: 0.371, 13.063%; route: 2.237, 78.768%; tC2Q: 0.232, 8.169%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.271, 100.000%

Path11

Path Summary:

Slack 5.002
Data Arrival Time 7.199
Data Required Time 12.201
From u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_2_s0
Launch Clk clkin:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
2.088 2.088 tINS RR 41 IOT27[A] clk_ibuf/O
4.359 2.271 tNET RR 1 R27C37[2][B] u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
4.591 0.232 tC2Q RF 3119 R27C37[2][B] u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
6.190 1.598 tNET FF 1 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I0
6.561 0.371 tINS FF 40 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
7.199 0.639 tNET FF 1 R45C20[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_2_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clkx1
10.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
12.271 2.271 tNET RR 1 R45C20[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_2_s0/CLK
12.236 -0.035 tUnc u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_2_s0
12.201 -0.035 tSu 1 R45C20[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_2_s0

Path Statistics:

Clock Skew -2.088
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 2.088, 47.897%; route: 2.271, 52.103%
Arrival Data Path Delay cell: 0.371, 13.063%; route: 2.237, 78.768%; tC2Q: 0.232, 8.169%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.271, 100.000%

Path12

Path Summary:

Slack 5.002
Data Arrival Time 7.199
Data Required Time 12.201
From u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_0_s0
Launch Clk clkin:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
2.088 2.088 tINS RR 41 IOT27[A] clk_ibuf/O
4.359 2.271 tNET RR 1 R27C37[2][B] u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
4.591 0.232 tC2Q RF 3119 R27C37[2][B] u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
6.190 1.598 tNET FF 1 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I0
6.561 0.371 tINS FF 40 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
7.199 0.639 tNET FF 1 R47C20[1][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clkx1
10.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
12.271 2.271 tNET RR 1 R47C20[1][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_0_s0/CLK
12.236 -0.035 tUnc u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_0_s0
12.201 -0.035 tSu 1 R47C20[1][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_0_s0

Path Statistics:

Clock Skew -2.088
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 2.088, 47.897%; route: 2.271, 52.103%
Arrival Data Path Delay cell: 0.371, 13.063%; route: 2.237, 78.768%; tC2Q: 0.232, 8.169%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.271, 100.000%

Path13

Path Summary:

Slack 5.002
Data Arrival Time 7.199
Data Required Time 12.201
From u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_1_s0
Launch Clk clkin:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
2.088 2.088 tINS RR 41 IOT27[A] clk_ibuf/O
4.359 2.271 tNET RR 1 R27C37[2][B] u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
4.591 0.232 tC2Q RF 3119 R27C37[2][B] u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
6.190 1.598 tNET FF 1 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I0
6.561 0.371 tINS FF 40 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
7.199 0.639 tNET FF 1 R45C22[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clkx1
10.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
12.271 2.271 tNET RR 1 R45C22[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_1_s0/CLK
12.236 -0.035 tUnc u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_1_s0
12.201 -0.035 tSu 1 R45C22[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_1_s0

Path Statistics:

Clock Skew -2.088
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 2.088, 47.897%; route: 2.271, 52.103%
Arrival Data Path Delay cell: 0.371, 13.063%; route: 2.237, 78.768%; tC2Q: 0.232, 8.169%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.271, 100.000%

Path14

Path Summary:

Slack 5.002
Data Arrival Time 7.199
Data Required Time 12.201
From u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_2_s0
Launch Clk clkin:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
2.088 2.088 tINS RR 41 IOT27[A] clk_ibuf/O
4.359 2.271 tNET RR 1 R27C37[2][B] u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
4.591 0.232 tC2Q RF 3119 R27C37[2][B] u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
6.190 1.598 tNET FF 1 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I0
6.561 0.371 tINS FF 40 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
7.199 0.639 tNET FF 1 R47C20[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_2_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clkx1
10.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
12.271 2.271 tNET RR 1 R47C20[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_2_s0/CLK
12.236 -0.035 tUnc u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_2_s0
12.201 -0.035 tSu 1 R47C20[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_2_s0

Path Statistics:

Clock Skew -2.088
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 2.088, 47.897%; route: 2.271, 52.103%
Arrival Data Path Delay cell: 0.371, 13.063%; route: 2.237, 78.768%; tC2Q: 0.232, 8.169%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.271, 100.000%

Path15

Path Summary:

Slack 5.002
Data Arrival Time 7.199
Data Required Time 12.201
From u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_3_s0
Launch Clk clkin:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
2.088 2.088 tINS RR 41 IOT27[A] clk_ibuf/O
4.359 2.271 tNET RR 1 R27C37[2][B] u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
4.591 0.232 tC2Q RF 3119 R27C37[2][B] u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
6.190 1.598 tNET FF 1 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I0
6.561 0.371 tINS FF 40 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
7.199 0.639 tNET FF 1 R47C21[2][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_3_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clkx1
10.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
12.271 2.271 tNET RR 1 R47C21[2][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_3_s0/CLK
12.236 -0.035 tUnc u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_3_s0
12.201 -0.035 tSu 1 R47C21[2][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_3_s0

Path Statistics:

Clock Skew -2.088
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 2.088, 47.897%; route: 2.271, 52.103%
Arrival Data Path Delay cell: 0.371, 13.063%; route: 2.237, 78.768%; tC2Q: 0.232, 8.169%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.271, 100.000%

Path16

Path Summary:

Slack 5.002
Data Arrival Time 7.199
Data Required Time 12.201
From u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_0_s0
Launch Clk clkin:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
2.088 2.088 tINS RR 41 IOT27[A] clk_ibuf/O
4.359 2.271 tNET RR 1 R27C37[2][B] u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
4.591 0.232 tC2Q RF 3119 R27C37[2][B] u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
6.190 1.598 tNET FF 1 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I0
6.561 0.371 tINS FF 40 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
7.199 0.639 tNET FF 1 R44C21[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clkx1
10.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
12.271 2.271 tNET RR 1 R44C21[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_0_s0/CLK
12.236 -0.035 tUnc u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_0_s0
12.201 -0.035 tSu 1 R44C21[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_0_s0

Path Statistics:

Clock Skew -2.088
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 2.088, 47.897%; route: 2.271, 52.103%
Arrival Data Path Delay cell: 0.371, 13.063%; route: 2.237, 78.768%; tC2Q: 0.232, 8.169%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.271, 100.000%

Path17

Path Summary:

Slack 5.002
Data Arrival Time 7.199
Data Required Time 12.201
From u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_1_s0
Launch Clk clkin:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
2.088 2.088 tINS RR 41 IOT27[A] clk_ibuf/O
4.359 2.271 tNET RR 1 R27C37[2][B] u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
4.591 0.232 tC2Q RF 3119 R27C37[2][B] u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
6.190 1.598 tNET FF 1 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I0
6.561 0.371 tINS FF 40 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
7.199 0.639 tNET FF 1 R44C20[1][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clkx1
10.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
12.271 2.271 tNET RR 1 R44C20[1][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_1_s0/CLK
12.236 -0.035 tUnc u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_1_s0
12.201 -0.035 tSu 1 R44C20[1][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_1_s0

Path Statistics:

Clock Skew -2.088
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 2.088, 47.897%; route: 2.271, 52.103%
Arrival Data Path Delay cell: 0.371, 13.063%; route: 2.237, 78.768%; tC2Q: 0.232, 8.169%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.271, 100.000%

Path18

Path Summary:

Slack 5.002
Data Arrival Time 7.199
Data Required Time 12.201
From u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_2_s0
Launch Clk clkin:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
2.088 2.088 tINS RR 41 IOT27[A] clk_ibuf/O
4.359 2.271 tNET RR 1 R27C37[2][B] u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
4.591 0.232 tC2Q RF 3119 R27C37[2][B] u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
6.190 1.598 tNET FF 1 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I0
6.561 0.371 tINS FF 40 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
7.199 0.639 tNET FF 1 R45C21[2][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_2_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clkx1
10.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
12.271 2.271 tNET RR 1 R45C21[2][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_2_s0/CLK
12.236 -0.035 tUnc u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_2_s0
12.201 -0.035 tSu 1 R45C21[2][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_2_s0

Path Statistics:

Clock Skew -2.088
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 2.088, 47.897%; route: 2.271, 52.103%
Arrival Data Path Delay cell: 0.371, 13.063%; route: 2.237, 78.768%; tC2Q: 0.232, 8.169%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.271, 100.000%

Path19

Path Summary:

Slack 5.002
Data Arrival Time 7.199
Data Required Time 12.201
From u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_3_s0
Launch Clk clkin:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
2.088 2.088 tINS RR 41 IOT27[A] clk_ibuf/O
4.359 2.271 tNET RR 1 R27C37[2][B] u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
4.591 0.232 tC2Q RF 3119 R27C37[2][B] u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
6.190 1.598 tNET FF 1 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I0
6.561 0.371 tINS FF 40 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
7.199 0.639 tNET FF 1 R44C20[2][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_3_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clkx1
10.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
12.271 2.271 tNET RR 1 R44C20[2][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_3_s0/CLK
12.236 -0.035 tUnc u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_3_s0
12.201 -0.035 tSu 1 R44C20[2][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_3_s0

Path Statistics:

Clock Skew -2.088
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 2.088, 47.897%; route: 2.271, 52.103%
Arrival Data Path Delay cell: 0.371, 13.063%; route: 2.237, 78.768%; tC2Q: 0.232, 8.169%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.271, 100.000%

Path20

Path Summary:

Slack 5.002
Data Arrival Time 7.199
Data Required Time 12.201
From u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_0_s0
Launch Clk clkin:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
2.088 2.088 tINS RR 41 IOT27[A] clk_ibuf/O
4.359 2.271 tNET RR 1 R27C37[2][B] u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
4.591 0.232 tC2Q RF 3119 R27C37[2][B] u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
6.190 1.598 tNET FF 1 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I0
6.561 0.371 tINS FF 40 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
7.199 0.639 tNET FF 1 R44C21[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clkx1
10.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
12.271 2.271 tNET RR 1 R44C21[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_0_s0/CLK
12.236 -0.035 tUnc u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_0_s0
12.201 -0.035 tSu 1 R44C21[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_0_s0

Path Statistics:

Clock Skew -2.088
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 2.088, 47.897%; route: 2.271, 52.103%
Arrival Data Path Delay cell: 0.371, 13.063%; route: 2.237, 78.768%; tC2Q: 0.232, 8.169%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.271, 100.000%

Path21

Path Summary:

Slack 5.002
Data Arrival Time 7.199
Data Required Time 12.201
From u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_1_s0
Launch Clk clkin:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
2.088 2.088 tINS RR 41 IOT27[A] clk_ibuf/O
4.359 2.271 tNET RR 1 R27C37[2][B] u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
4.591 0.232 tC2Q RF 3119 R27C37[2][B] u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
6.190 1.598 tNET FF 1 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I0
6.561 0.371 tINS FF 40 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
7.199 0.639 tNET FF 1 R44C20[2][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clkx1
10.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
12.271 2.271 tNET RR 1 R44C20[2][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_1_s0/CLK
12.236 -0.035 tUnc u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_1_s0
12.201 -0.035 tSu 1 R44C20[2][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_1_s0

Path Statistics:

Clock Skew -2.088
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 2.088, 47.897%; route: 2.271, 52.103%
Arrival Data Path Delay cell: 0.371, 13.063%; route: 2.237, 78.768%; tC2Q: 0.232, 8.169%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.271, 100.000%

Path22

Path Summary:

Slack 5.002
Data Arrival Time 7.199
Data Required Time 12.201
From u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_2_s0
Launch Clk clkin:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
2.088 2.088 tINS RR 41 IOT27[A] clk_ibuf/O
4.359 2.271 tNET RR 1 R27C37[2][B] u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
4.591 0.232 tC2Q RF 3119 R27C37[2][B] u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
6.190 1.598 tNET FF 1 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I0
6.561 0.371 tINS FF 40 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
7.199 0.639 tNET FF 1 R45C22[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_2_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clkx1
10.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
12.271 2.271 tNET RR 1 R45C22[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_2_s0/CLK
12.236 -0.035 tUnc u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_2_s0
12.201 -0.035 tSu 1 R45C22[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_2_s0

Path Statistics:

Clock Skew -2.088
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 2.088, 47.897%; route: 2.271, 52.103%
Arrival Data Path Delay cell: 0.371, 13.063%; route: 2.237, 78.768%; tC2Q: 0.232, 8.169%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.271, 100.000%

Path23

Path Summary:

Slack 5.002
Data Arrival Time 7.199
Data Required Time 12.201
From u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_Empty_reg_s0
Launch Clk clkin:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
2.088 2.088 tINS RR 41 IOT27[A] clk_ibuf/O
4.359 2.271 tNET RR 1 R27C37[2][B] u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
4.591 0.232 tC2Q RF 3119 R27C37[2][B] u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
6.190 1.598 tNET FF 1 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I0
6.561 0.371 tINS FF 40 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
7.199 0.639 tNET FF 1 R40C22[1][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_Empty_reg_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clkx1
10.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
12.271 2.271 tNET RR 1 R40C22[1][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_Empty_reg_s0/CLK
12.236 -0.035 tUnc u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_Empty_reg_s0
12.201 -0.035 tSu 1 R40C22[1][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_Empty_reg_s0

Path Statistics:

Clock Skew -2.088
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 2.088, 47.897%; route: 2.271, 52.103%
Arrival Data Path Delay cell: 0.371, 13.063%; route: 2.237, 78.768%; tC2Q: 0.232, 8.169%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.271, 100.000%

Path24

Path Summary:

Slack 5.002
Data Arrival Time 7.199
Data Required Time 12.201
From u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_3_s0
Launch Clk clkin:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
2.088 2.088 tINS RR 41 IOT27[A] clk_ibuf/O
4.359 2.271 tNET RR 1 R27C37[2][B] u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
4.591 0.232 tC2Q RF 3119 R27C37[2][B] u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
6.190 1.598 tNET FF 1 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I0
6.561 0.371 tINS FF 40 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
7.199 0.639 tNET FF 1 R40C22[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_3_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clkx1
10.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
12.271 2.271 tNET RR 1 R40C22[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_3_s0/CLK
12.236 -0.035 tUnc u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_3_s0
12.201 -0.035 tSu 1 R40C22[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_3_s0

Path Statistics:

Clock Skew -2.088
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 2.088, 47.897%; route: 2.271, 52.103%
Arrival Data Path Delay cell: 0.371, 13.063%; route: 2.237, 78.768%; tC2Q: 0.232, 8.169%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.271, 100.000%

Path25

Path Summary:

Slack 5.002
Data Arrival Time 7.199
Data Required Time 12.201
From u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_0_s0
Launch Clk clkin:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOT27[A] clk_ibuf/I
2.088 2.088 tINS RR 41 IOT27[A] clk_ibuf/O
4.359 2.271 tNET RR 1 R27C37[2][B] u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
4.591 0.232 tC2Q RF 3119 R27C37[2][B] u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
6.190 1.598 tNET FF 1 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I0
6.561 0.371 tINS FF 40 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
7.199 0.639 tNET FF 1 R43C21[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clkx1
10.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
12.271 2.271 tNET RR 1 R43C21[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_0_s0/CLK
12.236 -0.035 tUnc u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_0_s0
12.201 -0.035 tSu 1 R43C21[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_0_s0

Path Statistics:

Clock Skew -2.088
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 2.088, 47.897%; route: 2.271, 52.103%
Arrival Data Path Delay cell: 0.371, 13.063%; route: 2.237, 78.768%; tC2Q: 0.232, 8.169%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.271, 100.000%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 1.294
Data Arrival Time 2.817
Data Required Time 1.522
From u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_Empty_reg_s0
Launch Clk clkx1:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R45C39[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
1.713 0.202 tC2Q RR 1 R45C39[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
2.150 0.437 tNET RR 1 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
2.460 0.310 tINS RR 40 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
2.817 0.357 tNET RR 1 R45C21[2][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_Empty_reg_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R45C21[2][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_Empty_reg_s0/CLK
1.522 0.011 tHld 1 R45C21[2][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_Empty_reg_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay cell: 0.310, 23.747%; route: 0.793, 60.779%; tC2Q: 0.202, 15.474%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%

Path2

Path Summary:

Slack 1.294
Data Arrival Time 2.817
Data Required Time 1.522
From u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_3_s0
Launch Clk clkx1:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R45C39[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
1.713 0.202 tC2Q RR 1 R45C39[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
2.150 0.437 tNET RR 1 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
2.460 0.310 tINS RR 40 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
2.817 0.357 tNET RR 1 R44C20[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_3_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R44C20[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_3_s0/CLK
1.522 0.011 tHld 1 R44C20[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_3_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay cell: 0.310, 23.747%; route: 0.793, 60.779%; tC2Q: 0.202, 15.474%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%

Path3

Path Summary:

Slack 1.294
Data Arrival Time 2.817
Data Required Time 1.522
From u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_0_s0
Launch Clk clkx1:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R45C39[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
1.713 0.202 tC2Q RR 1 R45C39[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
2.150 0.437 tNET RR 1 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
2.460 0.310 tINS RR 40 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
2.817 0.357 tNET RR 1 R47C20[2][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R47C20[2][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_0_s0/CLK
1.522 0.011 tHld 1 R47C20[2][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay cell: 0.310, 23.747%; route: 0.793, 60.779%; tC2Q: 0.202, 15.474%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%

Path4

Path Summary:

Slack 1.294
Data Arrival Time 2.817
Data Required Time 1.522
From u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_1_s0
Launch Clk clkx1:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R45C39[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
1.713 0.202 tC2Q RR 1 R45C39[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
2.150 0.437 tNET RR 1 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
2.460 0.310 tINS RR 40 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
2.817 0.357 tNET RR 1 R43C20[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R43C20[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_1_s0/CLK
1.522 0.011 tHld 1 R43C20[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay cell: 0.310, 23.747%; route: 0.793, 60.779%; tC2Q: 0.202, 15.474%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%

Path5

Path Summary:

Slack 1.294
Data Arrival Time 2.817
Data Required Time 1.522
From u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_2_s0
Launch Clk clkx1:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R45C39[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
1.713 0.202 tC2Q RR 1 R45C39[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
2.150 0.437 tNET RR 1 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
2.460 0.310 tINS RR 40 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
2.817 0.357 tNET RR 1 R44C20[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_2_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R44C20[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_2_s0/CLK
1.522 0.011 tHld 1 R44C20[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_2_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay cell: 0.310, 23.747%; route: 0.793, 60.779%; tC2Q: 0.202, 15.474%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%

Path6

Path Summary:

Slack 1.294
Data Arrival Time 2.817
Data Required Time 1.522
From u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_3_s0
Launch Clk clkx1:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R45C39[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
1.713 0.202 tC2Q RR 1 R45C39[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
2.150 0.437 tNET RR 1 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
2.460 0.310 tINS RR 40 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
2.817 0.357 tNET RR 1 R45C20[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_3_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R45C20[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_3_s0/CLK
1.522 0.011 tHld 1 R45C20[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_3_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay cell: 0.310, 23.747%; route: 0.793, 60.779%; tC2Q: 0.202, 15.474%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%

Path7

Path Summary:

Slack 1.294
Data Arrival Time 2.817
Data Required Time 1.522
From u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_0_s0
Launch Clk clkx1:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R45C39[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
1.713 0.202 tC2Q RR 1 R45C39[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
2.150 0.437 tNET RR 1 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
2.460 0.310 tINS RR 40 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
2.817 0.357 tNET RR 1 R44C21[1][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R44C21[1][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_0_s0/CLK
1.522 0.011 tHld 1 R44C21[1][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay cell: 0.310, 23.747%; route: 0.793, 60.779%; tC2Q: 0.202, 15.474%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%

Path8

Path Summary:

Slack 1.294
Data Arrival Time 2.817
Data Required Time 1.522
From u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_1_s0
Launch Clk clkx1:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R45C39[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
1.713 0.202 tC2Q RR 1 R45C39[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
2.150 0.437 tNET RR 1 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
2.460 0.310 tINS RR 40 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
2.817 0.357 tNET RR 1 R44C20[1][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R44C20[1][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_1_s0/CLK
1.522 0.011 tHld 1 R44C20[1][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay cell: 0.310, 23.747%; route: 0.793, 60.779%; tC2Q: 0.202, 15.474%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%

Path9

Path Summary:

Slack 1.294
Data Arrival Time 2.817
Data Required Time 1.522
From u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_2_s0
Launch Clk clkx1:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R45C39[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
1.713 0.202 tC2Q RR 1 R45C39[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
2.150 0.437 tNET RR 1 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
2.460 0.310 tINS RR 40 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
2.817 0.357 tNET RR 1 R45C20[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_2_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R45C20[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_2_s0/CLK
1.522 0.011 tHld 1 R45C20[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_2_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay cell: 0.310, 23.747%; route: 0.793, 60.779%; tC2Q: 0.202, 15.474%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%

Path10

Path Summary:

Slack 1.294
Data Arrival Time 2.817
Data Required Time 1.522
From u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_0_s0
Launch Clk clkx1:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R45C39[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
1.713 0.202 tC2Q RR 1 R45C39[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
2.150 0.437 tNET RR 1 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
2.460 0.310 tINS RR 40 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
2.817 0.357 tNET RR 1 R47C20[1][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R47C20[1][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_0_s0/CLK
1.522 0.011 tHld 1 R47C20[1][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay cell: 0.310, 23.747%; route: 0.793, 60.779%; tC2Q: 0.202, 15.474%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%

Path11

Path Summary:

Slack 1.294
Data Arrival Time 2.817
Data Required Time 1.522
From u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_1_s0
Launch Clk clkx1:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R45C39[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
1.713 0.202 tC2Q RR 1 R45C39[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
2.150 0.437 tNET RR 1 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
2.460 0.310 tINS RR 40 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
2.817 0.357 tNET RR 1 R45C22[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R45C22[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_1_s0/CLK
1.522 0.011 tHld 1 R45C22[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay cell: 0.310, 23.747%; route: 0.793, 60.779%; tC2Q: 0.202, 15.474%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%

Path12

Path Summary:

Slack 1.294
Data Arrival Time 2.817
Data Required Time 1.522
From u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_2_s0
Launch Clk clkx1:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R45C39[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
1.713 0.202 tC2Q RR 1 R45C39[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
2.150 0.437 tNET RR 1 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
2.460 0.310 tINS RR 40 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
2.817 0.357 tNET RR 1 R47C20[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_2_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R47C20[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_2_s0/CLK
1.522 0.011 tHld 1 R47C20[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_2_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay cell: 0.310, 23.747%; route: 0.793, 60.779%; tC2Q: 0.202, 15.474%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%

Path13

Path Summary:

Slack 1.294
Data Arrival Time 2.817
Data Required Time 1.522
From u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_3_s0
Launch Clk clkx1:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R45C39[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
1.713 0.202 tC2Q RR 1 R45C39[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
2.150 0.437 tNET RR 1 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
2.460 0.310 tINS RR 40 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
2.817 0.357 tNET RR 1 R47C21[2][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_3_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R47C21[2][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_3_s0/CLK
1.522 0.011 tHld 1 R47C21[2][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_3_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay cell: 0.310, 23.747%; route: 0.793, 60.779%; tC2Q: 0.202, 15.474%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%

Path14

Path Summary:

Slack 1.294
Data Arrival Time 2.817
Data Required Time 1.522
From u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_0_s0
Launch Clk clkx1:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R45C39[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
1.713 0.202 tC2Q RR 1 R45C39[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
2.150 0.437 tNET RR 1 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
2.460 0.310 tINS RR 40 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
2.817 0.357 tNET RR 1 R44C21[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R44C21[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_0_s0/CLK
1.522 0.011 tHld 1 R44C21[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay cell: 0.310, 23.747%; route: 0.793, 60.779%; tC2Q: 0.202, 15.474%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%

Path15

Path Summary:

Slack 1.294
Data Arrival Time 2.817
Data Required Time 1.522
From u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_1_s0
Launch Clk clkx1:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R45C39[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
1.713 0.202 tC2Q RR 1 R45C39[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
2.150 0.437 tNET RR 1 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
2.460 0.310 tINS RR 40 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
2.817 0.357 tNET RR 1 R44C20[1][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R44C20[1][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_1_s0/CLK
1.522 0.011 tHld 1 R44C20[1][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay cell: 0.310, 23.747%; route: 0.793, 60.779%; tC2Q: 0.202, 15.474%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%

Path16

Path Summary:

Slack 1.294
Data Arrival Time 2.817
Data Required Time 1.522
From u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_2_s0
Launch Clk clkx1:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R45C39[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
1.713 0.202 tC2Q RR 1 R45C39[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
2.150 0.437 tNET RR 1 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
2.460 0.310 tINS RR 40 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
2.817 0.357 tNET RR 1 R45C21[2][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_2_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R45C21[2][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_2_s0/CLK
1.522 0.011 tHld 1 R45C21[2][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_2_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay cell: 0.310, 23.747%; route: 0.793, 60.779%; tC2Q: 0.202, 15.474%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%

Path17

Path Summary:

Slack 1.294
Data Arrival Time 2.817
Data Required Time 1.522
From u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_3_s0
Launch Clk clkx1:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R45C39[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
1.713 0.202 tC2Q RR 1 R45C39[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
2.150 0.437 tNET RR 1 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
2.460 0.310 tINS RR 40 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
2.817 0.357 tNET RR 1 R44C20[2][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_3_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R44C20[2][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_3_s0/CLK
1.522 0.011 tHld 1 R44C20[2][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_3_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay cell: 0.310, 23.747%; route: 0.793, 60.779%; tC2Q: 0.202, 15.474%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%

Path18

Path Summary:

Slack 1.294
Data Arrival Time 2.817
Data Required Time 1.522
From u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_0_s0
Launch Clk clkx1:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R45C39[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
1.713 0.202 tC2Q RR 1 R45C39[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
2.150 0.437 tNET RR 1 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
2.460 0.310 tINS RR 40 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
2.817 0.357 tNET RR 1 R44C21[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R44C21[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_0_s0/CLK
1.522 0.011 tHld 1 R44C21[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay cell: 0.310, 23.747%; route: 0.793, 60.779%; tC2Q: 0.202, 15.474%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%

Path19

Path Summary:

Slack 1.294
Data Arrival Time 2.817
Data Required Time 1.522
From u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_1_s0
Launch Clk clkx1:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R45C39[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
1.713 0.202 tC2Q RR 1 R45C39[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
2.150 0.437 tNET RR 1 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
2.460 0.310 tINS RR 40 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
2.817 0.357 tNET RR 1 R44C20[2][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R44C20[2][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_1_s0/CLK
1.522 0.011 tHld 1 R44C20[2][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay cell: 0.310, 23.747%; route: 0.793, 60.779%; tC2Q: 0.202, 15.474%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%

Path20

Path Summary:

Slack 1.294
Data Arrival Time 2.817
Data Required Time 1.522
From u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_2_s0
Launch Clk clkx1:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R45C39[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
1.713 0.202 tC2Q RR 1 R45C39[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
2.150 0.437 tNET RR 1 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
2.460 0.310 tINS RR 40 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
2.817 0.357 tNET RR 1 R45C22[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_2_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R45C22[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_2_s0/CLK
1.522 0.011 tHld 1 R45C22[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_2_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay cell: 0.310, 23.747%; route: 0.793, 60.779%; tC2Q: 0.202, 15.474%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%

Path21

Path Summary:

Slack 1.294
Data Arrival Time 2.817
Data Required Time 1.522
From u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_Empty_reg_s0
Launch Clk clkx1:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R45C39[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
1.713 0.202 tC2Q RR 1 R45C39[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
2.150 0.437 tNET RR 1 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
2.460 0.310 tINS RR 40 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
2.817 0.357 tNET RR 1 R40C22[1][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_Empty_reg_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R40C22[1][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_Empty_reg_s0/CLK
1.522 0.011 tHld 1 R40C22[1][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_Empty_reg_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay cell: 0.310, 23.747%; route: 0.793, 60.779%; tC2Q: 0.202, 15.474%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%

Path22

Path Summary:

Slack 1.294
Data Arrival Time 2.817
Data Required Time 1.522
From u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_3_s0
Launch Clk clkx1:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R45C39[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
1.713 0.202 tC2Q RR 1 R45C39[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
2.150 0.437 tNET RR 1 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
2.460 0.310 tINS RR 40 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
2.817 0.357 tNET RR 1 R40C22[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_3_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R40C22[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_3_s0/CLK
1.522 0.011 tHld 1 R40C22[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_3_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay cell: 0.310, 23.747%; route: 0.793, 60.779%; tC2Q: 0.202, 15.474%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%

Path23

Path Summary:

Slack 1.294
Data Arrival Time 2.817
Data Required Time 1.522
From u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_0_s0
Launch Clk clkx1:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R45C39[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
1.713 0.202 tC2Q RR 1 R45C39[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
2.150 0.437 tNET RR 1 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
2.460 0.310 tINS RR 40 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
2.817 0.357 tNET RR 1 R43C21[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R43C21[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_0_s0/CLK
1.522 0.011 tHld 1 R43C21[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay cell: 0.310, 23.747%; route: 0.793, 60.779%; tC2Q: 0.202, 15.474%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%

Path24

Path Summary:

Slack 1.294
Data Arrival Time 2.817
Data Required Time 1.522
From u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_1_s0
Launch Clk clkx1:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R45C39[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
1.713 0.202 tC2Q RR 1 R45C39[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
2.150 0.437 tNET RR 1 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
2.460 0.310 tINS RR 40 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
2.817 0.357 tNET RR 1 R44C21[1][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R44C21[1][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_1_s0/CLK
1.522 0.011 tHld 1 R44C21[1][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay cell: 0.310, 23.747%; route: 0.793, 60.779%; tC2Q: 0.202, 15.474%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%

Path25

Path Summary:

Slack 1.294
Data Arrival Time 2.817
Data Required Time 1.522
From u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_2_s0
Launch Clk clkx1:[R]
Latch Clk clkx1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R45C39[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
1.713 0.202 tC2Q RR 1 R45C39[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
2.150 0.437 tNET RR 1 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
2.460 0.310 tINS RR 40 R45C23[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
2.817 0.357 tNET RR 1 R44C22[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_2_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkx1
0.000 0.000 tCL RR 4216 BOTTOMSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
1.511 1.511 tNET RR 1 R44C22[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_2_s0/CLK
1.522 0.011 tHld 1 R44C22[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_2_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay cell: 0.310, 23.747%; route: 0.793, 60.779%; tC2Q: 0.202, 15.474%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.511, 100.000%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack: 3.237
Actual Width: 4.237
Required Width: 1.000
Type: Low Pulse Width
Clock: clkx1
Objects: led_cnt_31_s0

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clkx1
5.000 0.000 tCL FF u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
7.274 2.274 tNET FF led_cnt_31_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clkx1
10.000 0.000 tCL RR u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
11.511 1.511 tNET RR led_cnt_31_s0/CLK

MPW2

MPW Summary:

Slack: 3.237
Actual Width: 4.237
Required Width: 1.000
Type: Low Pulse Width
Clock: clkx1
Objects: led_cnt_24_s0

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clkx1
5.000 0.000 tCL FF u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
7.274 2.274 tNET FF led_cnt_24_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clkx1
10.000 0.000 tCL RR u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
11.511 1.511 tNET RR led_cnt_24_s0/CLK

MPW3

MPW Summary:

Slack: 3.237
Actual Width: 4.237
Required Width: 1.000
Type: Low Pulse Width
Clock: clkx1
Objects: led_cnt_16_s0

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clkx1
5.000 0.000 tCL FF u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
7.274 2.274 tNET FF led_cnt_16_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clkx1
10.000 0.000 tCL RR u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
11.511 1.511 tNET RR led_cnt_16_s0/CLK

MPW4

MPW Summary:

Slack: 3.237
Actual Width: 4.237
Required Width: 1.000
Type: Low Pulse Width
Clock: clkx1
Objects: led_cnt_12_s0

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clkx1
5.000 0.000 tCL FF u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
7.274 2.274 tNET FF led_cnt_12_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clkx1
10.000 0.000 tCL RR u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
11.511 1.511 tNET RR led_cnt_12_s0/CLK

MPW5

MPW Summary:

Slack: 3.237
Actual Width: 4.237
Required Width: 1.000
Type: Low Pulse Width
Clock: clkx1
Objects: led_cnt_10_s0

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clkx1
5.000 0.000 tCL FF u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
7.274 2.274 tNET FF led_cnt_10_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clkx1
10.000 0.000 tCL RR u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
11.511 1.511 tNET RR led_cnt_10_s0/CLK

MPW6

MPW Summary:

Slack: 3.237
Actual Width: 4.237
Required Width: 1.000
Type: Low Pulse Width
Clock: clkx1
Objects: led_cnt_9_s0

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clkx1
5.000 0.000 tCL FF u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
7.274 2.274 tNET FF led_cnt_9_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clkx1
10.000 0.000 tCL RR u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
11.511 1.511 tNET RR led_cnt_9_s0/CLK

MPW7

MPW Summary:

Slack: 3.237
Actual Width: 4.237
Required Width: 1.000
Type: Low Pulse Width
Clock: clkx1
Objects: u_rd/app_rd_data_r_74_s0

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clkx1
5.000 0.000 tCL FF u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
7.274 2.274 tNET FF u_rd/app_rd_data_r_74_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clkx1
10.000 0.000 tCL RR u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
11.511 1.511 tNET RR u_rd/app_rd_data_r_74_s0/CLK

MPW8

MPW Summary:

Slack: 3.237
Actual Width: 4.237
Required Width: 1.000
Type: Low Pulse Width
Clock: clkx1
Objects: u_rd/app_rd_data_rr_75_s0

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clkx1
5.000 0.000 tCL FF u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
7.274 2.274 tNET FF u_rd/app_rd_data_rr_75_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clkx1
10.000 0.000 tCL RR u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
11.511 1.511 tNET RR u_rd/app_rd_data_rr_75_s0/CLK

MPW9

MPW Summary:

Slack: 3.237
Actual Width: 4.237
Required Width: 1.000
Type: Low Pulse Width
Clock: clkx1
Objects: u_ddr3/gw3_top/gwmc_app_wdf_wdata_25_s0

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clkx1
5.000 0.000 tCL FF u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
7.274 2.274 tNET FF u_ddr3/gw3_top/gwmc_app_wdf_wdata_25_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clkx1
10.000 0.000 tCL RR u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
11.511 1.511 tNET RR u_ddr3/gw3_top/gwmc_app_wdf_wdata_25_s0/CLK

MPW10

MPW Summary:

Slack: 3.237
Actual Width: 4.237
Required Width: 1.000
Type: Low Pulse Width
Clock: clkx1
Objects: u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_4_G[15]_s0

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clkx1
5.000 0.000 tCL FF u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
7.274 2.274 tNET FF u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_4_G[15]_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clkx1
10.000 0.000 tCL RR u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
11.511 1.511 tNET RR u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_4_G[15]_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT NET NAME WORST SLACK MAX DELAY
4216 clk_x1 0.360 2.274
3119 ddr_rst 1.257 1.598
177 eye_calib_start_rr[0] 6.530 2.585
149 dqsts1 7.558 1.626
148 dqs_reg 7.238 2.152
144 n28_3 6.811 1.341
129 phy_rddata_valid_d1 7.739 1.815
128 raddr[2] 0.360 2.630
87 mc_wrdata_dly_0_9 5.475 1.315
87 mc_wrdata_dly_0_10 5.562 1.597

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC ROUTE CONGESTIONS
R22C16 86.11%
R22C33 86.11%
R44C20 84.72%
R39C34 83.33%
R41C34 83.33%
R13C24 83.33%
R36C31 83.33%
R33C35 83.33%
R33C38 83.33%
R33C41 83.33%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type State Detail Command
TC_CLOCK Actived create_clock -name clkin -period 20 -waveform {0 10} [get_ports {clk}]
TC_CLOCK Actived create_clock -name clk_x4 -period 2.5 -waveform {0 1.25} [get_nets {clk_x4}]
TC_CLOCK Actived create_clock -name clkx1 -period 10 -waveform {0 5} [get_pins {u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT}]
TC_FALSE_PATH Actived set_false_path -from [get_clocks {clk_x4}] -to [get_clocks {clkx1}]
TC_FALSE_PATH Actived set_false_path -from [get_clocks {clkx1}] -to [get_clocks {clk_x4}]
TC_FALSE_PATH Actived set_false_path -from [get_clocks {clkx1}] -to [get_clocks {clkin}]
TC_FALSE_PATH Actived set_false_path -from [get_clocks {clkin}] -to [get_clocks {clk_x4}]