Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | E:\myWork\IP\releaseVerify\version\1.9.9.02\DDR3_MC_PHY_1vs4_5a25k\project\src\button.v E:\myWork\IP\releaseVerify\version\1.9.9.02\DDR3_MC_PHY_1vs4_5a25k\project\src\ddr3_memory_interface\ddr3_memory_interface.v E:\myWork\IP\releaseVerify\version\1.9.9.02\DDR3_MC_PHY_1vs4_5a25k\project\src\ddrtest.v E:\myWork\IP\releaseVerify\version\1.9.9.02\DDR3_MC_PHY_1vs4_5a25k\project\src\gowin_pll\gowin_pll.v E:\myWork\IP\releaseVerify\version\1.9.9.02\DDR3_MC_PHY_1vs4_5a25k\project\src\pll_mDRP_intf.v E:\myWork\IP\releaseVerify\version\1.9.9.02\DDR3_MC_PHY_1vs4_5a25k\project\src\top.v |
GowinSynthesis Constraints File | --- |
Tool Version | V1.9.9.02 |
Part Number | GW5A-LV25UG324ES |
Device | GW5A-25 |
Device Version | A |
Created Time | Tue Mar 26 14:27:12 2024 |
Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | top |
Synthesis Process | Running parser: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 660.789MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.187s, Elapsed time = 0h 0m 0.188s, Peak memory usage = 660.789MB Optimizing Phase 1: CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.195s, Peak memory usage = 660.789MB Optimizing Phase 2: CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.208s, Peak memory usage = 660.789MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.149s, Peak memory usage = 660.789MB Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 660.789MB Inferring Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.038s, Peak memory usage = 660.789MB Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 660.789MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.453s, Elapsed time = 0h 0m 0.452s, Peak memory usage = 660.789MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.141s, Peak memory usage = 660.789MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.078s, Peak memory usage = 660.789MB Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 660.789MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.234s, Elapsed time = 0h 0m 0.257s, Peak memory usage = 660.789MB Generate output files: CPU time = 0h 0m 0.562s, Elapsed time = 0h 0m 0.625s, Peak memory usage = 660.789MB |
Total Time and Memory Usage | CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s, Peak memory usage = 660.789MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 76 |
I/O Buf | 71 |
    IBUF | 2 |
    OBUF | 28 |
    TBUF | 4 |
    IOBUF | 32 |
    ELVDS_OBUF | 1 |
    ELVDS_IOBUF | 4 |
Register | 6341 |
    DFFSE | 2 |
    DFFRE | 491 |
    DFFPE | 74 |
    DFFCE | 5774 |
LUT | 3718 |
    LUT2 | 709 |
    LUT3 | 1679 |
    LUT4 | 1330 |
ALU | 447 |
    ALU | 447 |
INV | 33 |
    INV | 33 |
IOLOGIC | 128 |
    IDES8_MEM | 32 |
    OSER8 | 24 |
    OSER8_MEM | 40 |
    IODELAY | 32 |
BSRAM | 24 |
    SDPB | 8 |
    SDPX9B | 16 |
CLOCK | 7 |
    CLKDIV | 1 |
    DQS | 4 |
    DDRDLL | 1 |
    PLLA | 1 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 4198(3751 LUT, 447 ALU) / 23040 | 19% |
Register | 6341 / 23685 | 27% |
  --Register as Latch | 0 / 23685 | 0% |
  --Register as FF | 6341 / 23685 | 27% |
BSRAM | 24 / 56 | 43% |
Timing
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|
clk_g | Base | 20.000 | 50.0 | 0.000 | 10.000 | clk_g_ibuf/I | ||
Gowin_PLL_inst/PLLA_inst/CLKOUT2.default_gen_clk | Generated | 2.500 | 400.0 | 0.000 | 1.250 | clk_g_ibuf/I | clk_g | Gowin_PLL_inst/PLLA_inst/CLKOUT2 |
u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | Generated | 10.000 | 100.0 | 0.000 | 5.000 | Gowin_PLL_inst/PLLA_inst/CLKOUT2 | Gowin_PLL_inst/PLLA_inst/CLKOUT2.default_gen_clk | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
Max Frequency Summary:
No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | clk_g | 50.000(MHz) | 193.143(MHz) | 6 | TOP |
2 | Gowin_PLL_inst/PLLA_inst/CLKOUT2.default_gen_clk | 400.000(MHz) | 1164.144(MHz) | 1 | TOP |
3 | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | 100.000(MHz) | 173.160(MHz) | 3 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | -0.965 |
Data Arrival Time | 2.351 |
Data Required Time | 1.386 |
From | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_3_s0 |
To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
Launch Clk | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[F] |
Latch Clk | Gowin_PLL_inst/PLLA_inst/CLKOUT2.default_gen_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
0.317 | 0.317 | tCL | RR | 6401 | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
0.692 | 0.375 | tNET | RR | 1 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_3_s0/CLK |
1.075 | 0.382 | tC2Q | RR | 9 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_3_s0/Q |
1.450 | 0.375 | tNET | RR | 1 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_3_s/I0 |
1.976 | 0.526 | tINS | RR | 1 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_3_s/F |
2.351 | 0.375 | tNET | RR | 1 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
1.250 | 0.000 | Gowin_PLL_inst/PLLA_inst/CLKOUT2.default_gen_clk | |||
1.555 | 0.305 | tCL | FF | 102 | Gowin_PLL_inst/PLLA_inst/CLKOUT2 |
1.905 | 0.350 | tNET | FF | 1 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
1.870 | -0.035 | tUnc | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs | ||
1.386 | -0.484 | tSu | 1 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
Clock Skew: | -0.038 |
Setup Relationship: | 1.250 |
Logic Level: | 2 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Arrival Data Path Delay: | cell: 0.526, 31.726%; route: 0.750, 45.214%; tC2Q: 0.382, 23.060% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 2
Path Summary:Slack | -0.965 |
Data Arrival Time | 2.351 |
Data Required Time | 1.386 |
From | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_2_s0 |
To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
Launch Clk | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[F] |
Latch Clk | Gowin_PLL_inst/PLLA_inst/CLKOUT2.default_gen_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
0.317 | 0.317 | tCL | RR | 6401 | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
0.692 | 0.375 | tNET | RR | 1 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_2_s0/CLK |
1.075 | 0.382 | tC2Q | RR | 9 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_2_s0/Q |
1.450 | 0.375 | tNET | RR | 1 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_2_s/I0 |
1.976 | 0.526 | tINS | RR | 1 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_2_s/F |
2.351 | 0.375 | tNET | RR | 1 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
1.250 | 0.000 | Gowin_PLL_inst/PLLA_inst/CLKOUT2.default_gen_clk | |||
1.555 | 0.305 | tCL | FF | 102 | Gowin_PLL_inst/PLLA_inst/CLKOUT2 |
1.905 | 0.350 | tNET | FF | 1 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
1.870 | -0.035 | tUnc | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs | ||
1.386 | -0.484 | tSu | 1 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
Clock Skew: | -0.038 |
Setup Relationship: | 1.250 |
Logic Level: | 2 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Arrival Data Path Delay: | cell: 0.526, 31.726%; route: 0.750, 45.214%; tC2Q: 0.382, 23.060% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 3
Path Summary:Slack | -0.965 |
Data Arrival Time | 2.351 |
Data Required Time | 1.386 |
From | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_1_s0 |
To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
Launch Clk | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[F] |
Latch Clk | Gowin_PLL_inst/PLLA_inst/CLKOUT2.default_gen_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
0.317 | 0.317 | tCL | RR | 6401 | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
0.692 | 0.375 | tNET | RR | 1 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_1_s0/CLK |
1.075 | 0.382 | tC2Q | RR | 9 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_1_s0/Q |
1.450 | 0.375 | tNET | RR | 1 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_1_s/I0 |
1.976 | 0.526 | tINS | RR | 1 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_1_s/F |
2.351 | 0.375 | tNET | RR | 1 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
1.250 | 0.000 | Gowin_PLL_inst/PLLA_inst/CLKOUT2.default_gen_clk | |||
1.555 | 0.305 | tCL | FF | 102 | Gowin_PLL_inst/PLLA_inst/CLKOUT2 |
1.905 | 0.350 | tNET | FF | 1 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
1.870 | -0.035 | tUnc | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs | ||
1.386 | -0.484 | tSu | 1 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
Clock Skew: | -0.038 |
Setup Relationship: | 1.250 |
Logic Level: | 2 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Arrival Data Path Delay: | cell: 0.526, 31.726%; route: 0.750, 45.214%; tC2Q: 0.382, 23.060% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 4
Path Summary:Slack | -0.965 |
Data Arrival Time | 2.351 |
Data Required Time | 1.386 |
From | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_0_s0 |
To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
Launch Clk | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[F] |
Latch Clk | Gowin_PLL_inst/PLLA_inst/CLKOUT2.default_gen_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
0.317 | 0.317 | tCL | RR | 6401 | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
0.692 | 0.375 | tNET | RR | 1 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_0_s0/CLK |
1.075 | 0.382 | tC2Q | RR | 9 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_0_s0/Q |
1.450 | 0.375 | tNET | RR | 1 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_0_s/I0 |
1.976 | 0.526 | tINS | RR | 1 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_0_s/F |
2.351 | 0.375 | tNET | RR | 1 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
1.250 | 0.000 | Gowin_PLL_inst/PLLA_inst/CLKOUT2.default_gen_clk | |||
1.555 | 0.305 | tCL | FF | 102 | Gowin_PLL_inst/PLLA_inst/CLKOUT2 |
1.905 | 0.350 | tNET | FF | 1 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
1.870 | -0.035 | tUnc | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs | ||
1.386 | -0.484 | tSu | 1 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
Clock Skew: | -0.038 |
Setup Relationship: | 1.250 |
Logic Level: | 2 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Arrival Data Path Delay: | cell: 0.526, 31.726%; route: 0.750, 45.214%; tC2Q: 0.382, 23.060% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 5
Path Summary:Slack | 1.633 |
Data Arrival Time | 8.961 |
Data Required Time | 10.594 |
From | u_ddr3/gw3_top/u_ddr_phy_top/u_dll |
To | u_ddr3/gw3_top/u_ddr_phy_top/dll_step_base_0_s0 |
Launch Clk | Gowin_PLL_inst/PLLA_inst/CLKOUT2.default_gen_clk[R] |
Latch Clk | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
7.500 | 0.000 | Gowin_PLL_inst/PLLA_inst/CLKOUT2.default_gen_clk | |||
7.805 | 0.305 | tCL | RR | 102 | Gowin_PLL_inst/PLLA_inst/CLKOUT2 |
8.180 | 0.375 | tNET | RR | 8 | u_ddr3/gw3_top/u_ddr_phy_top/u_dll/CLKIN |
8.586 | 0.406 | tINS | RR | 5 | u_ddr3/gw3_top/u_ddr_phy_top/u_dll/STEP[0] |
8.961 | 0.375 | tNET | RR | 1 | u_ddr3/gw3_top/u_ddr_phy_top/dll_step_base_0_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
10.318 | 0.317 | tCL | RR | 6401 | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
10.693 | 0.375 | tNET | RR | 1 | u_ddr3/gw3_top/u_ddr_phy_top/dll_step_base_0_s0/CLK |
10.658 | -0.035 | tUnc | u_ddr3/gw3_top/u_ddr_phy_top/dll_step_base_0_s0 | ||
10.594 | -0.064 | tSu | 1 | u_ddr3/gw3_top/u_ddr_phy_top/dll_step_base_0_s0 |
Clock Skew: | 0.387 |
Setup Relationship: | 2.500 |
Logic Level: | 2 |
Arrival Clock Path Delay: | cell: 0.000, 100.000%; route: 0.000, 0.000% |
Arrival Data Path Delay: | cell: 0.406, 35.122%; route: 0.375, 32.439%; tC2Q: 0.375, 32.439% |
Required Clock Path Delay: | cell: 0.000, 100.000%; route: 0.000, 0.000% |