Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\DDR3\data\ddr3_1_4code_hs\ddr3_1_4code_hs.v C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\DDR3\data\ddr3_1_4code_hs\DDR3_TOP.v |
GowinSynthesis Constraints File | --- |
Tool Version | V1.9.9.02 |
Part Number | GW2A-LV18PG256C8/I7 |
Device | GW2A-18 |
Device Version | C |
Created Time | Wed Mar 27 10:51:53 2024 |
Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | DDR3_Memory_Interface_Top |
Synthesis Process | Running parser: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 147.273MB Running netlist conversion: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.082s, Peak memory usage = 147.273MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.312s, Elapsed time = 0h 0m 0.308s, Peak memory usage = 147.273MB Optimizing Phase 1: CPU time = 0h 0m 0.187s, Elapsed time = 0h 0m 0.189s, Peak memory usage = 147.273MB Optimizing Phase 2: CPU time = 0h 0m 0.718s, Elapsed time = 0h 0m 0.698s, Peak memory usage = 147.273MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.437s, Elapsed time = 0h 0m 0.445s, Peak memory usage = 147.273MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 147.273MB Inferring Phase 2: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.048s, Peak memory usage = 147.273MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.014s, Peak memory usage = 147.273MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.468s, Elapsed time = 0h 0m 0.466s, Peak memory usage = 147.273MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.115s, Peak memory usage = 147.273MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.093s, Peak memory usage = 147.273MB Tech-Mapping Phase 3: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 164.297MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.437s, Elapsed time = 0h 0m 0.446s, Peak memory usage = 164.297MB Generate output files: CPU time = 0h 0m 0.296s, Elapsed time = 0h 0m 0.334s, Peak memory usage = 164.297MB |
Total Time and Memory Usage | CPU time = 0h 0m 7s, Elapsed time = 0h 0m 7s, Peak memory usage = 164.297MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 370 |
I/O Buf | 364 |
    IBUF | 182 |
    OBUF | 161 |
    TBUF | 2 |
    IOBUF | 16 |
    ELVDS_OBUF | 1 |
    ELVDS_IOBUF | 2 |
Register | 3619 |
    DFF | 229 |
    DFFE | 252 |
    DFFS | 1 |
    DFFR | 1 |
    DFFP | 56 |
    DFFPE | 9 |
    DFFC | 2582 |
    DFFCE | 489 |
LUT | 2114 |
    LUT2 | 487 |
    LUT3 | 805 |
    LUT4 | 822 |
ALU | 124 |
    ALU | 124 |
SSRAM | 137 |
    RAM16S4 | 44 |
    RAM16SDP4 | 93 |
INV | 25 |
    INV | 25 |
IOLOGIC | 76 |
    IDES8_MEM | 16 |
    OSER8 | 24 |
    OSER8_MEM | 20 |
    IODELAY | 16 |
BSRAM | 4 |
    SDPX9B | 4 |
CLOCK | 4 |
    CLKDIV | 1 |
    DQS | 2 |
    DHCEN | 1 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 3085(2139 LUT, 124 ALU, 137 RAM16) / 20736 | 15% |
Register | 3619 / 16173 | 23% |
  --Register as Latch | 0 / 16173 | 0% |
  --Register as FF | 3619 / 16173 | 23% |
BSRAM | 4 / 46 | 9% |
Timing
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|
memory_clk | Base | 10.000 | 100.0 | 0.000 | 5.000 | memory_clk_ibuf/I | ||
clk | Base | 10.000 | 100.0 | 0.000 | 5.000 | clk_ibuf/I | ||
gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | Generated | 40.000 | 25.0 | 0.000 | 20.000 | memory_clk_ibuf/I | memory_clk | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
Max Frequency Summary:
No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | memory_clk | 100.000(MHz) | 1030.929(MHz) | 1 | TOP |
2 | clk | 100.000(MHz) | 161.838(MHz) | 7 | TOP |
3 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | 25.000(MHz) | 179.019(MHz) | 3 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | 3.176 |
Data Arrival Time | 2.436 |
Data Required Time | 5.612 |
From | gw3_top/u_ddr_phy_top/u_ddr_init/hold_gen[1].hold_i_s0 |
To | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
Launch Clk | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[F] |
Latch Clk | memory_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
0.341 | 0.341 | tCL | RR | 3787 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
0.701 | 0.360 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/hold_gen[1].hold_i_s0/CLK |
0.933 | 0.232 | tC2Q | RF | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/hold_gen[1].hold_i_s0/Q |
1.407 | 0.474 | tNET | FF | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_1_s/I1 |
1.962 | 0.555 | tINS | FF | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_1_s/F |
2.436 | 0.474 | tNET | FF | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
5.000 | 0.000 | memory_clk | |||
5.000 | 0.000 | tCL | FF | 1 | memory_clk_ibuf/I |
5.000 | 0.000 | tINS | FF | 1 | memory_clk_ibuf/O |
5.474 | 0.474 | tNET | FF | 3 | gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN |
5.660 | 0.186 | tINS | FF | 64 | gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT |
6.134 | 0.474 | tNET | FF | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
6.099 | -0.035 | tUnc | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs | ||
5.612 | -0.487 | tSu | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
Clock Skew: | 0.433 |
Setup Relationship: | 5.000 |
Logic Level: | 2 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Arrival Data Path Delay: | cell: 0.555, 31.988%; route: 0.948, 54.640%; tC2Q: 0.232, 13.372% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Path 2
Path Summary:Slack | 3.176 |
Data Arrival Time | 2.436 |
Data Required Time | 5.612 |
From | gw3_top/u_ddr_phy_top/u_ddr_init/hold_gen[0].hold_i_s0 |
To | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
Launch Clk | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[F] |
Latch Clk | memory_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
0.341 | 0.341 | tCL | RR | 3787 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
0.701 | 0.360 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/hold_gen[0].hold_i_s0/CLK |
0.933 | 0.232 | tC2Q | RF | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/hold_gen[0].hold_i_s0/Q |
1.407 | 0.474 | tNET | FF | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_0_s/I1 |
1.962 | 0.555 | tINS | FF | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_0_s/F |
2.436 | 0.474 | tNET | FF | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
5.000 | 0.000 | memory_clk | |||
5.000 | 0.000 | tCL | FF | 1 | memory_clk_ibuf/I |
5.000 | 0.000 | tINS | FF | 1 | memory_clk_ibuf/O |
5.474 | 0.474 | tNET | FF | 3 | gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN |
5.660 | 0.186 | tINS | FF | 64 | gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT |
6.134 | 0.474 | tNET | FF | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
6.099 | -0.035 | tUnc | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs | ||
5.612 | -0.487 | tSu | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
Clock Skew: | 0.433 |
Setup Relationship: | 5.000 |
Logic Level: | 2 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Arrival Data Path Delay: | cell: 0.555, 31.988%; route: 0.948, 54.640%; tC2Q: 0.232, 13.372% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Path 3
Path Summary:Slack | 3.821 |
Data Arrival Time | 6.504 |
Data Required Time | 10.325 |
From | gw3_top/u_ddr_phy_top/ddr_sync/cs_memsync_4_s0 |
To | gw3_top/u_ddr_phy_top/ddr_sync/cs_memsync_5_s0 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.000 | 0.000 | tINS | RR | 40 | clk_ibuf/O |
0.360 | 0.360 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/cs_memsync_4_s0/CLK |
0.592 | 0.232 | tC2Q | RF | 7 | gw3_top/u_ddr_phy_top/ddr_sync/cs_memsync_4_s0/Q |
1.066 | 0.474 | tNET | FF | 1 | gw3_top/u_ddr_phy_top/ddr_sync/ns_memsync_0_s14/I1 |
1.621 | 0.555 | tINS | FF | 3 | gw3_top/u_ddr_phy_top/ddr_sync/ns_memsync_0_s14/F |
2.095 | 0.474 | tNET | FF | 1 | gw3_top/u_ddr_phy_top/ddr_sync/ns_memsync_2_s13/I3 |
2.466 | 0.371 | tINS | FF | 5 | gw3_top/u_ddr_phy_top/ddr_sync/ns_memsync_2_s13/F |
2.940 | 0.474 | tNET | FF | 1 | gw3_top/u_ddr_phy_top/ddr_sync/ns_memsync_5_s13/I1 |
3.495 | 0.555 | tINS | FF | 2 | gw3_top/u_ddr_phy_top/ddr_sync/ns_memsync_5_s13/F |
3.969 | 0.474 | tNET | FF | 1 | gw3_top/u_ddr_phy_top/ddr_sync/flag_d_1_s14/I3 |
4.340 | 0.371 | tINS | FF | 1 | gw3_top/u_ddr_phy_top/ddr_sync/flag_d_1_s14/F |
4.814 | 0.474 | tNET | FF | 1 | gw3_top/u_ddr_phy_top/ddr_sync/flag_d_1_s11/I3 |
5.185 | 0.371 | tINS | FF | 2 | gw3_top/u_ddr_phy_top/ddr_sync/flag_d_1_s11/F |
5.659 | 0.474 | tNET | FF | 1 | gw3_top/u_ddr_phy_top/ddr_sync/ns_memsync_5_s12/I3 |
6.030 | 0.371 | tINS | FF | 1 | gw3_top/u_ddr_phy_top/ddr_sync/ns_memsync_5_s12/F |
6.504 | 0.474 | tNET | FF | 1 | gw3_top/u_ddr_phy_top/ddr_sync/cs_memsync_5_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk | |||
10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
10.000 | 0.000 | tINS | RR | 40 | clk_ibuf/O |
10.360 | 0.360 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/cs_memsync_5_s0/CLK |
10.325 | -0.035 | tSu | 1 | gw3_top/u_ddr_phy_top/ddr_sync/cs_memsync_5_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 7 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Arrival Data Path Delay: | cell: 2.594, 42.220%; route: 3.318, 54.004%; tC2Q: 0.232, 3.776% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Path 4
Path Summary:Slack | 4.187 |
Data Arrival Time | 1.066 |
Data Required Time | 5.253 |
From | gw3_top/u_ddr_phy_top/stop_reg_2_s0 |
To | gw3_top/u_ddr_phy_top/fclk_dhcen |
Launch Clk | clk[F] |
Latch Clk | memory_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.000 | 0.000 | tINS | RR | 40 | clk_ibuf/O |
0.360 | 0.360 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/stop_reg_2_s0/CLK |
0.592 | 0.232 | tC2Q | RF | 1 | gw3_top/u_ddr_phy_top/stop_reg_2_s0/Q |
1.066 | 0.474 | tNET | FF | 1 | gw3_top/u_ddr_phy_top/fclk_dhcen/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
5.000 | 0.000 | memory_clk | |||
5.000 | 0.000 | tCL | FF | 1 | memory_clk_ibuf/I |
5.000 | 0.000 | tINS | FF | 1 | memory_clk_ibuf/O |
5.474 | 0.474 | tNET | FF | 3 | gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN |
5.439 | -0.035 | tUnc | gw3_top/u_ddr_phy_top/fclk_dhcen | ||
5.253 | -0.186 | tSu | 1 | gw3_top/u_ddr_phy_top/fclk_dhcen |
Clock Skew: | 0.114 |
Setup Relationship: | 5.000 |
Logic Level: | 1 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.474, 67.139%; tC2Q: 0.232, 32.861% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Path 5
Path Summary:Slack | 4.482 |
Data Arrival Time | 5.843 |
Data Required Time | 10.325 |
From | gw3_top/u_ddr_phy_top/ddr_sync/flag_0_s4 |
To | gw3_top/u_ddr_phy_top/ddr_sync/count_0_s0 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.000 | 0.000 | tINS | RR | 40 | clk_ibuf/O |
0.360 | 0.360 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/flag_0_s4/CLK |
0.592 | 0.232 | tC2Q | RF | 10 | gw3_top/u_ddr_phy_top/ddr_sync/flag_0_s4/Q |
1.066 | 0.474 | tNET | FF | 1 | gw3_top/u_ddr_phy_top/ddr_sync/ns_memsync_2_s16/I1 |
1.621 | 0.555 | tINS | FF | 1 | gw3_top/u_ddr_phy_top/ddr_sync/ns_memsync_2_s16/F |
2.095 | 0.474 | tNET | FF | 1 | gw3_top/u_ddr_phy_top/ddr_sync/ns_memsync_2_s14/I1 |
2.650 | 0.555 | tINS | FF | 2 | gw3_top/u_ddr_phy_top/ddr_sync/ns_memsync_2_s14/F |
3.124 | 0.474 | tNET | FF | 1 | gw3_top/u_ddr_phy_top/ddr_sync/n298_s6/I3 |
3.495 | 0.371 | tINS | FF | 1 | gw3_top/u_ddr_phy_top/ddr_sync/n298_s6/F |
3.969 | 0.474 | tNET | FF | 1 | gw3_top/u_ddr_phy_top/ddr_sync/n298_s4/I3 |
4.340 | 0.371 | tINS | FF | 3 | gw3_top/u_ddr_phy_top/ddr_sync/n298_s4/F |
4.814 | 0.474 | tNET | FF | 1 | gw3_top/u_ddr_phy_top/ddr_sync/n298_s3/I1 |
5.369 | 0.555 | tINS | FF | 1 | gw3_top/u_ddr_phy_top/ddr_sync/n298_s3/F |
5.843 | 0.474 | tNET | FF | 1 | gw3_top/u_ddr_phy_top/ddr_sync/count_0_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk | |||
10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
10.000 | 0.000 | tINS | RR | 40 | clk_ibuf/O |
10.360 | 0.360 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/count_0_s0/CLK |
10.325 | -0.035 | tSu | 1 | gw3_top/u_ddr_phy_top/ddr_sync/count_0_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 6 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Arrival Data Path Delay: | cell: 2.407, 43.899%; route: 2.844, 51.870%; tC2Q: 0.232, 4.231% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |