Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | D:\Gowin\Gowin_V1.9.9.02_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v D:\Gowin\Gowin_V1.9.9.02_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v D:\Gowin\Gowin_V1.9.9.02_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v D:\Gowin\Gowin_V1.9.9.02_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v D:\Gowin\Gowin_V1.9.9.02_x64\IDE\data\ipcores\GAO\GW_CON\gw_con_top.v D:\Gowin\Gowin_V1.9.9.02_x64\IDE\data\ipcores\gw_jtag.v E:\memory\DDR3\Gowin_DDR3_Memory_Interface_RefDesign\DDR3_MC_PHY_1vs4\project\impl\gao\gw_gao_top.v |
GowinSynthesis Constraints File | --- |
Tool Version | V1.9.9.02 |
Part Number | GW2A-LV18PG256C8/I7 |
Device | GW2A-18 |
Device Version | C |
Created Time | Thu Mar 14 12:26:19 2024 |
Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | gw_gao |
Synthesis Process | Running parser: CPU time = 0h 0m 0.375s, Elapsed time = 0h 0m 0.492s, Peak memory usage = 78.008MB Running netlist conversion: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 78.008MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.051s, Peak memory usage = 78.008MB Optimizing Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.025s, Peak memory usage = 78.008MB Optimizing Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.058s, Peak memory usage = 78.008MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.014s, Peak memory usage = 78.008MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 78.008MB Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 78.008MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 78.008MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.04s, Peak memory usage = 78.008MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 78.008MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 78.008MB Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 2s, Peak memory usage = 106.062MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.06s, Peak memory usage = 106.062MB Generate output files: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.054s, Peak memory usage = 106.062MB |
Total Time and Memory Usage | CPU time = 0h 0m 1s, Elapsed time = 0h 0m 2s, Peak memory usage = 106.062MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 148 |
I/O Buf | 148 |
    IBUF | 147 |
    OBUF | 1 |
Register | 814 |
    DFF | 293 |
    DFFR | 1 |
    DFFP | 3 |
    DFFPE | 33 |
    DFFC | 27 |
    DFFCE | 457 |
LUT | 546 |
    LUT2 | 62 |
    LUT3 | 122 |
    LUT4 | 362 |
MUX | 1 |
    MUX16 | 1 |
ALU | 13 |
    ALU | 13 |
INV | 4 |
    INV | 4 |
BSRAM | 8 |
    SDPX9B | 8 |
Black Box | 1 |
    GW_JTAG | 1 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 571(558 LUT, 13 ALU) / 20736 | 3% |
Register | 814 / 16173 | 6% |
  --Register as Latch | 0 / 16173 | 0% |
  --Register as FF | 814 / 16173 | 6% |
BSRAM | 8 / 46 | 18% |
Timing
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|
clk_x1 | Base | 10.000 | 100.0 | 0.000 | 5.000 | clk_x1_ibuf/I | ||
u_icon_top/n19_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 | u_icon_top/n19_s2/O | ||
u_la0_top/n15_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 | u_la0_top/n15_s2/O |
Max Frequency Summary:
No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | clk_x1 | 100.000(MHz) | 210.305(MHz) | 5 | TOP |
2 | u_icon_top/n19_6 | 100.000(MHz) | 1349.527(MHz) | 1 | TOP |
3 | u_la0_top/n15_6 | 100.000(MHz) | 1349.527(MHz) | 1 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | 5.245 |
Data Arrival Time | 5.762 |
Data Required Time | 11.007 |
From | u_la0_top/capture_window_sel_0_s3 |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_9_s0 |
Launch Clk | clk_x1[R] |
Latch Clk | clk_x1[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk_x1 | |||
0.000 | 0.000 | tCL | RR | 1 | clk_x1_ibuf/I |
0.683 | 0.683 | tINS | RR | 355 | clk_x1_ibuf/O |
1.043 | 0.360 | tNET | RR | 1 | u_la0_top/capture_window_sel_0_s3/CLK |
1.275 | 0.232 | tC2Q | RF | 14 | u_la0_top/capture_window_sel_0_s3/Q |
1.748 | 0.474 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s17/I1 |
2.303 | 0.555 | tINS | FF | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s17/F |
2.777 | 0.474 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s15/I1 |
3.332 | 0.555 | tINS | FF | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s15/F |
3.806 | 0.474 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s12/I1 |
4.361 | 0.555 | tINS | FF | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s12/F |
4.835 | 0.474 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s10/I2 |
5.288 | 0.453 | tINS | FF | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s10/F |
5.762 | 0.474 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_9_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk_x1 | |||
10.000 | 0.000 | tCL | RR | 1 | clk_x1_ibuf/I |
10.682 | 0.683 | tINS | RR | 355 | clk_x1_ibuf/O |
11.042 | 0.360 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_9_s0/CLK |
11.007 | -0.035 | tSu | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_9_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.683, 65.468%; route: 0.360, 34.532% |
Arrival Data Path Delay: | cell: 2.118, 44.873%; route: 2.370, 50.212%; tC2Q: 0.232, 4.915% |
Required Clock Path Delay: | cell: 0.683, 65.468%; route: 0.360, 34.532% |
Path 2
Path Summary:Slack | 5.283 |
Data Arrival Time | 5.725 |
Data Required Time | 11.007 |
From | u_la0_top/u_ao_mem_ctrl/capture_length_3_s1 |
To | u_la0_top/u_ao_mem_ctrl/capture_length_7_s1 |
Launch Clk | clk_x1[R] |
Latch Clk | clk_x1[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk_x1 | |||
0.000 | 0.000 | tCL | RR | 1 | clk_x1_ibuf/I |
0.683 | 0.683 | tINS | RR | 355 | clk_x1_ibuf/O |
1.043 | 0.360 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/CLK |
1.275 | 0.232 | tC2Q | RF | 3 | u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/Q |
1.748 | 0.474 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/n830_s2/I1 |
2.303 | 0.555 | tINS | FF | 5 | u_la0_top/u_ao_mem_ctrl/n830_s2/F |
2.777 | 0.474 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/n828_s1/I2 |
3.230 | 0.453 | tINS | FF | 2 | u_la0_top/u_ao_mem_ctrl/n828_s1/F |
3.704 | 0.474 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/n827_s1/I1 |
4.260 | 0.555 | tINS | FF | 1 | u_la0_top/u_ao_mem_ctrl/n827_s1/F |
4.734 | 0.474 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/n827_s2/I0 |
5.251 | 0.517 | tINS | FF | 1 | u_la0_top/u_ao_mem_ctrl/n827_s2/F |
5.725 | 0.474 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk_x1 | |||
10.000 | 0.000 | tCL | RR | 1 | clk_x1_ibuf/I |
10.682 | 0.683 | tINS | RR | 355 | clk_x1_ibuf/O |
11.042 | 0.360 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLK |
11.007 | -0.035 | tSu | 1 | u_la0_top/u_ao_mem_ctrl/capture_length_7_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.683, 65.468%; route: 0.360, 34.532% |
Arrival Data Path Delay: | cell: 2.080, 44.425%; route: 2.370, 50.620%; tC2Q: 0.232, 4.955% |
Required Clock Path Delay: | cell: 0.683, 65.468%; route: 0.360, 34.532% |
Path 3
Path Summary:Slack | 5.321 |
Data Arrival Time | 5.687 |
Data Required Time | 11.007 |
From | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1 |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1 |
Launch Clk | clk_x1[R] |
Latch Clk | clk_x1[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk_x1 | |||
0.000 | 0.000 | tCL | RR | 1 | clk_x1_ibuf/I |
0.683 | 0.683 | tINS | RR | 355 | clk_x1_ibuf/O |
1.043 | 0.360 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK |
1.275 | 0.232 | tC2Q | RF | 11 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/Q |
1.748 | 0.474 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/n920_s8/I0 |
2.266 | 0.517 | tINS | FF | 1 | u_la0_top/u_ao_mem_ctrl/n920_s8/F |
2.740 | 0.474 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/n920_s5/I1 |
3.295 | 0.555 | tINS | FF | 2 | u_la0_top/u_ao_mem_ctrl/n920_s5/F |
3.769 | 0.474 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/n920_s4/I0 |
4.286 | 0.517 | tINS | FF | 10 | u_la0_top/u_ao_mem_ctrl/n920_s4/F |
4.760 | 0.474 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/n928_s1/I2 |
5.213 | 0.453 | tINS | FF | 1 | u_la0_top/u_ao_mem_ctrl/n928_s1/F |
5.687 | 0.474 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk_x1 | |||
10.000 | 0.000 | tCL | RR | 1 | clk_x1_ibuf/I |
10.682 | 0.683 | tINS | RR | 355 | clk_x1_ibuf/O |
11.042 | 0.360 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK |
11.007 | -0.035 | tSu | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.683, 65.468%; route: 0.360, 34.532% |
Arrival Data Path Delay: | cell: 2.042, 43.971%; route: 2.370, 51.033%; tC2Q: 0.232, 4.996% |
Required Clock Path Delay: | cell: 0.683, 65.468%; route: 0.360, 34.532% |
Path 4
Path Summary:Slack | 5.321 |
Data Arrival Time | 5.687 |
Data Required Time | 11.007 |
From | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1 |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1 |
Launch Clk | clk_x1[R] |
Latch Clk | clk_x1[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk_x1 | |||
0.000 | 0.000 | tCL | RR | 1 | clk_x1_ibuf/I |
0.683 | 0.683 | tINS | RR | 355 | clk_x1_ibuf/O |
1.043 | 0.360 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK |
1.275 | 0.232 | tC2Q | RF | 11 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/Q |
1.748 | 0.474 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/n920_s8/I0 |
2.266 | 0.517 | tINS | FF | 1 | u_la0_top/u_ao_mem_ctrl/n920_s8/F |
2.740 | 0.474 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/n920_s5/I1 |
3.295 | 0.555 | tINS | FF | 2 | u_la0_top/u_ao_mem_ctrl/n920_s5/F |
3.769 | 0.474 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/n920_s4/I0 |
4.286 | 0.517 | tINS | FF | 10 | u_la0_top/u_ao_mem_ctrl/n920_s4/F |
4.760 | 0.474 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/n926_s1/I2 |
5.213 | 0.453 | tINS | FF | 1 | u_la0_top/u_ao_mem_ctrl/n926_s1/F |
5.687 | 0.474 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk_x1 | |||
10.000 | 0.000 | tCL | RR | 1 | clk_x1_ibuf/I |
10.682 | 0.683 | tINS | RR | 355 | clk_x1_ibuf/O |
11.042 | 0.360 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK |
11.007 | -0.035 | tSu | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.683, 65.468%; route: 0.360, 34.532% |
Arrival Data Path Delay: | cell: 2.042, 43.971%; route: 2.370, 51.033%; tC2Q: 0.232, 4.996% |
Required Clock Path Delay: | cell: 0.683, 65.468%; route: 0.360, 34.532% |
Path 5
Path Summary:Slack | 5.321 |
Data Arrival Time | 5.687 |
Data Required Time | 11.007 |
From | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1 |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1 |
Launch Clk | clk_x1[R] |
Latch Clk | clk_x1[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk_x1 | |||
0.000 | 0.000 | tCL | RR | 1 | clk_x1_ibuf/I |
0.683 | 0.683 | tINS | RR | 355 | clk_x1_ibuf/O |
1.043 | 0.360 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK |
1.275 | 0.232 | tC2Q | RF | 11 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/Q |
1.748 | 0.474 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/n920_s8/I0 |
2.266 | 0.517 | tINS | FF | 1 | u_la0_top/u_ao_mem_ctrl/n920_s8/F |
2.740 | 0.474 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/n920_s5/I1 |
3.295 | 0.555 | tINS | FF | 2 | u_la0_top/u_ao_mem_ctrl/n920_s5/F |
3.769 | 0.474 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/n920_s4/I0 |
4.286 | 0.517 | tINS | FF | 10 | u_la0_top/u_ao_mem_ctrl/n920_s4/F |
4.760 | 0.474 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/n923_s1/I2 |
5.213 | 0.453 | tINS | FF | 1 | u_la0_top/u_ao_mem_ctrl/n923_s1/F |
5.687 | 0.474 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk_x1 | |||
10.000 | 0.000 | tCL | RR | 1 | clk_x1_ibuf/I |
10.682 | 0.683 | tINS | RR | 355 | clk_x1_ibuf/O |
11.042 | 0.360 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK |
11.007 | -0.035 | tSu | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.683, 65.468%; route: 0.360, 34.532% |
Arrival Data Path Delay: | cell: 2.042, 43.971%; route: 2.370, 51.033%; tC2Q: 0.232, 4.996% |
Required Clock Path Delay: | cell: 0.683, 65.468%; route: 0.360, 34.532% |