Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\DDR3\data\ddr3_1_4code_hs\ddr3_1_4code_hs.v C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\DDR3\data\ddr3_1_4code_hs\DDR3_TOP.v |
GowinSynthesis Constraints File | --- |
Tool Version | V1.9.9.02 |
Part Number | GW5AST-LV138FPG676AES |
Device | GW5AST-138 |
Device Version | B |
Created Time | Tue Mar 26 14:38:14 2024 |
Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | DDR3_Memory_Interface_Top |
Synthesis Process | Running parser: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 180.824MB Running netlist conversion: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.148s, Peak memory usage = 180.824MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.515s, Elapsed time = 0h 0m 0.523s, Peak memory usage = 180.824MB Optimizing Phase 1: CPU time = 0h 0m 0.359s, Elapsed time = 0h 0m 0.35s, Peak memory usage = 180.824MB Optimizing Phase 2: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 180.824MB Running inference: Inferring Phase 0: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 180.824MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 180.824MB Inferring Phase 2: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.067s, Peak memory usage = 180.824MB Inferring Phase 3: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.023s, Peak memory usage = 180.824MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.687s, Elapsed time = 0h 0m 0.698s, Peak memory usage = 180.824MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.187s, Elapsed time = 0h 0m 0.181s, Peak memory usage = 180.824MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.162s, Peak memory usage = 180.824MB Tech-Mapping Phase 3: CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s, Peak memory usage = 187.836MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.64s, Elapsed time = 0h 0m 0.676s, Peak memory usage = 187.836MB Generate output files: CPU time = 0h 0m 0.984s, Elapsed time = 0h 0m 0.994s, Peak memory usage = 199.086MB |
Total Time and Memory Usage | CPU time = 0h 0m 10s, Elapsed time = 0h 0m 10s, Peak memory usage = 199.086MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 665 |
I/O Buf | 657 |
    IBUF | 326 |
    OBUF | 290 |
    TBUF | 4 |
    IOBUF | 32 |
    ELVDS_OBUF | 1 |
    ELVDS_IOBUF | 4 |
Register | 5588 |
    DFFSE | 1 |
    DFFRE | 453 |
    DFFPE | 73 |
    DFFCE | 5061 |
LUT | 3321 |
    LUT2 | 635 |
    LUT3 | 1625 |
    LUT4 | 1061 |
ALU | 188 |
    ALU | 188 |
INV | 28 |
    INV | 28 |
IOLOGIC | 128 |
    IDES8_MEM | 32 |
    OSER8 | 24 |
    OSER8_MEM | 40 |
    IODELAY | 32 |
BSRAM | 24 |
    SDPB | 8 |
    SDPX9B | 16 |
CLOCK | 6 |
    CLKDIV | 1 |
    DQS | 4 |
    DDRDLL | 1 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 3537(3349 LUT, 188 ALU) / 138240 | 3% |
Register | 5588 / 139140 | 5% |
  --Register as Latch | 0 / 139140 | 0% |
  --Register as FF | 5588 / 139140 | 5% |
BSRAM | 24 / 340 | 8% |
Timing
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|
memory_clk | Base | 10.000 | 100.0 | 0.000 | 5.000 | memory_clk_ibuf/I | ||
clk | Base | 10.000 | 100.0 | 0.000 | 5.000 | clk_ibuf/I | ||
gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | Generated | 40.000 | 25.0 | 0.000 | 20.000 | memory_clk_ibuf/I | memory_clk | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
Max Frequency Summary:
No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | memory_clk | 100.000(MHz) | 1115.449(MHz) | 1 | TOP |
2 | clk | 100.000(MHz) | 181.365(MHz) | 6 | TOP |
3 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | 25.000(MHz) | 161.225(MHz) | 3 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | 2.332 |
Data Arrival Time | 2.534 |
Data Required Time | 4.866 |
From | gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_3_s0 |
To | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
Launch Clk | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[F] |
Latch Clk | memory_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
0.336 | 0.336 | tCL | RR | 5697 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
0.748 | 0.413 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_3_s0/CLK |
1.131 | 0.382 | tC2Q | RR | 9 | gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_3_s0/Q |
1.543 | 0.413 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_3_s/I0 |
2.122 | 0.579 | tINS | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_3_s/F |
2.534 | 0.413 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
5.000 | 0.000 | memory_clk | |||
5.000 | 0.000 | tCL | FF | 1 | memory_clk_ibuf/I |
5.000 | 0.000 | tINS | FF | 102 | memory_clk_ibuf/O |
5.385 | 0.385 | tNET | FF | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
5.350 | -0.035 | tUnc | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs | ||
4.866 | -0.484 | tSu | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
Clock Skew: | -0.363 |
Setup Relationship: | 5.000 |
Logic Level: | 2 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Arrival Data Path Delay: | cell: 0.579, 32.400%; route: 0.825, 46.186%; tC2Q: 0.382, 21.414% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 2
Path Summary:Slack | 2.332 |
Data Arrival Time | 2.534 |
Data Required Time | 4.866 |
From | gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_2_s0 |
To | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
Launch Clk | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[F] |
Latch Clk | memory_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
0.336 | 0.336 | tCL | RR | 5697 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
0.748 | 0.413 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_2_s0/CLK |
1.131 | 0.382 | tC2Q | RR | 9 | gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_2_s0/Q |
1.543 | 0.413 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_2_s/I0 |
2.122 | 0.579 | tINS | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_2_s/F |
2.534 | 0.413 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
5.000 | 0.000 | memory_clk | |||
5.000 | 0.000 | tCL | FF | 1 | memory_clk_ibuf/I |
5.000 | 0.000 | tINS | FF | 102 | memory_clk_ibuf/O |
5.385 | 0.385 | tNET | FF | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
5.350 | -0.035 | tUnc | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs | ||
4.866 | -0.484 | tSu | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
Clock Skew: | -0.363 |
Setup Relationship: | 5.000 |
Logic Level: | 2 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Arrival Data Path Delay: | cell: 0.579, 32.400%; route: 0.825, 46.186%; tC2Q: 0.382, 21.414% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 3
Path Summary:Slack | 2.332 |
Data Arrival Time | 2.534 |
Data Required Time | 4.866 |
From | gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_1_s0 |
To | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
Launch Clk | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[F] |
Latch Clk | memory_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
0.336 | 0.336 | tCL | RR | 5697 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
0.748 | 0.413 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_1_s0/CLK |
1.131 | 0.382 | tC2Q | RR | 9 | gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_1_s0/Q |
1.543 | 0.413 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_1_s/I0 |
2.122 | 0.579 | tINS | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_1_s/F |
2.534 | 0.413 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
5.000 | 0.000 | memory_clk | |||
5.000 | 0.000 | tCL | FF | 1 | memory_clk_ibuf/I |
5.000 | 0.000 | tINS | FF | 102 | memory_clk_ibuf/O |
5.385 | 0.385 | tNET | FF | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
5.350 | -0.035 | tUnc | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs | ||
4.866 | -0.484 | tSu | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
Clock Skew: | -0.363 |
Setup Relationship: | 5.000 |
Logic Level: | 2 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Arrival Data Path Delay: | cell: 0.579, 32.400%; route: 0.825, 46.186%; tC2Q: 0.382, 21.414% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 4
Path Summary:Slack | 2.332 |
Data Arrival Time | 2.534 |
Data Required Time | 4.866 |
From | gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_0_s0 |
To | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
Launch Clk | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[F] |
Latch Clk | memory_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
0.336 | 0.336 | tCL | RR | 5697 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
0.748 | 0.413 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_0_s0/CLK |
1.131 | 0.382 | tC2Q | RR | 9 | gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_0_s0/Q |
1.543 | 0.413 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_0_s/I0 |
2.122 | 0.579 | tINS | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_0_s/F |
2.534 | 0.413 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
5.000 | 0.000 | memory_clk | |||
5.000 | 0.000 | tCL | FF | 1 | memory_clk_ibuf/I |
5.000 | 0.000 | tINS | FF | 102 | memory_clk_ibuf/O |
5.385 | 0.385 | tNET | FF | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
5.350 | -0.035 | tUnc | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs | ||
4.866 | -0.484 | tSu | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
Clock Skew: | -0.363 |
Setup Relationship: | 5.000 |
Logic Level: | 2 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Arrival Data Path Delay: | cell: 0.579, 32.400%; route: 0.825, 46.186%; tC2Q: 0.382, 21.414% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 5
Path Summary:Slack | 4.486 |
Data Arrival Time | 5.863 |
Data Required Time | 10.349 |
From | gw3_top/u_ddr_phy_top/ddr_sync/cs_memsync_5_s0 |
To | gw3_top/u_ddr_phy_top/ddr_sync/cs_memsync_5_s0 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.000 | 0.000 | tINS | RR | 40 | clk_ibuf/O |
0.413 | 0.413 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/cs_memsync_5_s0/CLK |
0.795 | 0.382 | tC2Q | RR | 4 | gw3_top/u_ddr_phy_top/ddr_sync/cs_memsync_5_s0/Q |
1.207 | 0.413 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/ns_memsync_2_s16/I0 |
1.786 | 0.579 | tINS | RR | 2 | gw3_top/u_ddr_phy_top/ddr_sync/ns_memsync_2_s16/F |
2.199 | 0.413 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/ns_memsync_2_s13/I3 |
2.487 | 0.289 | tINS | RR | 3 | gw3_top/u_ddr_phy_top/ddr_sync/ns_memsync_2_s13/F |
2.900 | 0.413 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/ns_memsync_0_s16/I0 |
3.479 | 0.579 | tINS | RR | 2 | gw3_top/u_ddr_phy_top/ddr_sync/ns_memsync_0_s16/F |
3.891 | 0.413 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/ns_memsync_5_s13/I1 |
4.459 | 0.567 | tINS | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/ns_memsync_5_s13/F |
4.871 | 0.413 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/ns_memsync_5_s12/I0 |
5.450 | 0.579 | tINS | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/ns_memsync_5_s12/F |
5.863 | 0.413 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/cs_memsync_5_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk | |||
10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
10.000 | 0.000 | tINS | RR | 40 | clk_ibuf/O |
10.413 | 0.413 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/cs_memsync_5_s0/CLK |
10.349 | -0.064 | tSu | 1 | gw3_top/u_ddr_phy_top/ddr_sync/cs_memsync_5_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 6 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Arrival Data Path Delay: | cell: 2.593, 47.569%; route: 2.475, 45.413%; tC2Q: 0.382, 7.018% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |