Synthesis Messages

Report Title GowinSynthesis Report
Design File E:\myWork\IP\releaseVerify\RefDesign\Memory_Control\DDR3\Gowin_DDR3_Memory_Interface_RefDesign\DDR3_MC_PHY_1vs4_5a138k\project\src\ddr3_memory_interface\ddr3_memory_interface.v
E:\myWork\IP\releaseVerify\RefDesign\Memory_Control\DDR3\Gowin_DDR3_Memory_Interface_RefDesign\DDR3_MC_PHY_1vs4_5a138k\project\src\ddrtest.v
E:\myWork\IP\releaseVerify\RefDesign\Memory_Control\DDR3\Gowin_DDR3_Memory_Interface_RefDesign\DDR3_MC_PHY_1vs4_5a138k\project\src\gowin_pll\gowin_pll.v
E:\myWork\IP\releaseVerify\RefDesign\Memory_Control\DDR3\Gowin_DDR3_Memory_Interface_RefDesign\DDR3_MC_PHY_1vs4_5a138k\project\src\top.v
GowinSynthesis Constraints File ---
Tool Version V1.9.9.02
Part Number GW5AST-LV138FPG676AES
Device GW5AST-138
Device Version B
Created Time Tue Mar 26 14:38:24 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module top
Synthesis Process Running parser:
    CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 276.723MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.169s, Peak memory usage = 276.723MB
    Optimizing Phase 1: CPU time = 0h 0m 0.187s, Elapsed time = 0h 0m 0.188s, Peak memory usage = 276.723MB
    Optimizing Phase 2: CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.2s, Peak memory usage = 276.723MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.145s, Peak memory usage = 276.723MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 276.723MB
    Inferring Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.038s, Peak memory usage = 276.723MB
    Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 276.723MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.421s, Elapsed time = 0h 0m 0.421s, Peak memory usage = 276.723MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.138s, Peak memory usage = 276.723MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.074s, Peak memory usage = 276.723MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 279.641MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.234s, Elapsed time = 0h 0m 0.244s, Peak memory usage = 279.641MB
Generate output files:
    CPU time = 0h 0m 0.625s, Elapsed time = 0h 0m 0.631s, Peak memory usage = 309.609MB
Total Time and Memory Usage CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s, Peak memory usage = 309.609MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 75
I/O Buf 70
    IBUF 1
    OBUF 28
    TBUF 4
    IOBUF 32
    ELVDS_OBUF 1
    ELVDS_IOBUF 4
Register 6293
    DFFSE 1
    DFFRE 453
    DFFPE 74
    DFFCE 5765
LUT 3704
    LUT2 693
    LUT3 1709
    LUT4 1302
ALU 428
    ALU 428
INV 29
    INV 29
IOLOGIC 128
    IDES8_MEM 32
    OSER8 24
    OSER8_MEM 40
    IODELAY 32
BSRAM 24
    SDPB 8
    SDPX9B 16
CLOCK 7
    PLL 1
    CLKDIV 1
    DQS 4
    DDRDLL 1

Resource Utilization Summary

Resource Usage Utilization
Logic 4161(3733 LUT, 428 ALU) / 138240 4%
Register 6293 / 139140 5%
  --Register as Latch 0 / 139140 0%
  --Register as FF 6293 / 139140 5%
BSRAM 24 / 340 8%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
clk Base 20.000 50.0 0.000 10.000 clk_ibuf/I
Gowin_PLL_inst/PLL_inst/CLKOUT2.default_gen_clk Generated 2.500 400.0 0.000 1.250 clk_ibuf/I clk Gowin_PLL_inst/PLL_inst/CLKOUT2
u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk Generated 10.000 100.0 0.000 5.000 Gowin_PLL_inst/PLL_inst/CLKOUT2 Gowin_PLL_inst/PLL_inst/CLKOUT2.default_gen_clk u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 50.000(MHz) 181.365(MHz) 6 TOP
2 Gowin_PLL_inst/PLL_inst/CLKOUT2.default_gen_clk 400.000(MHz) 1115.449(MHz) 1 TOP
3 u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk 100.000(MHz) 161.225(MHz) 3 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack -1.095
Data Arrival Time 2.534
Data Required Time 1.440
From u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_3_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Launch Clk u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[F]
Latch Clk Gowin_PLL_inst/PLL_inst/CLKOUT2.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.336 0.336 tCL RR 6401 u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.748 0.413 tNET RR 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_3_s0/CLK
1.131 0.382 tC2Q RR 9 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_3_s0/Q
1.543 0.413 tNET RR 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_3_s/I0
2.122 0.579 tINS RR 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_3_s/F
2.534 0.413 tNET RR 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
1.250 0.000 Gowin_PLL_inst/PLL_inst/CLKOUT2.default_gen_clk
1.574 0.324 tCL FF 102 Gowin_PLL_inst/PLL_inst/CLKOUT2
1.959 0.385 tNET FF 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
1.924 -0.035 tUnc u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
1.440 -0.484 tSu 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Path Statistics:
Clock Skew: -0.039
Setup Relationship: 1.250
Logic Level: 2
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 0.579, 32.400%; route: 0.825, 46.186%; tC2Q: 0.382, 21.414%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 2

Path Summary:
Slack -1.095
Data Arrival Time 2.534
Data Required Time 1.440
From u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_2_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Launch Clk u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[F]
Latch Clk Gowin_PLL_inst/PLL_inst/CLKOUT2.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.336 0.336 tCL RR 6401 u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.748 0.413 tNET RR 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_2_s0/CLK
1.131 0.382 tC2Q RR 9 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_2_s0/Q
1.543 0.413 tNET RR 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_2_s/I0
2.122 0.579 tINS RR 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_2_s/F
2.534 0.413 tNET RR 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
1.250 0.000 Gowin_PLL_inst/PLL_inst/CLKOUT2.default_gen_clk
1.574 0.324 tCL FF 102 Gowin_PLL_inst/PLL_inst/CLKOUT2
1.959 0.385 tNET FF 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
1.924 -0.035 tUnc u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
1.440 -0.484 tSu 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Path Statistics:
Clock Skew: -0.039
Setup Relationship: 1.250
Logic Level: 2
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 0.579, 32.400%; route: 0.825, 46.186%; tC2Q: 0.382, 21.414%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 3

Path Summary:
Slack -1.095
Data Arrival Time 2.534
Data Required Time 1.440
From u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_1_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Launch Clk u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[F]
Latch Clk Gowin_PLL_inst/PLL_inst/CLKOUT2.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.336 0.336 tCL RR 6401 u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.748 0.413 tNET RR 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_1_s0/CLK
1.131 0.382 tC2Q RR 9 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_1_s0/Q
1.543 0.413 tNET RR 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_1_s/I0
2.122 0.579 tINS RR 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_1_s/F
2.534 0.413 tNET RR 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
1.250 0.000 Gowin_PLL_inst/PLL_inst/CLKOUT2.default_gen_clk
1.574 0.324 tCL FF 102 Gowin_PLL_inst/PLL_inst/CLKOUT2
1.959 0.385 tNET FF 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
1.924 -0.035 tUnc u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
1.440 -0.484 tSu 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Path Statistics:
Clock Skew: -0.039
Setup Relationship: 1.250
Logic Level: 2
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 0.579, 32.400%; route: 0.825, 46.186%; tC2Q: 0.382, 21.414%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 4

Path Summary:
Slack -1.095
Data Arrival Time 2.534
Data Required Time 1.440
From u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_0_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Launch Clk u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[F]
Latch Clk Gowin_PLL_inst/PLL_inst/CLKOUT2.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.336 0.336 tCL RR 6401 u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.748 0.413 tNET RR 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_0_s0/CLK
1.131 0.382 tC2Q RR 9 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_0_s0/Q
1.543 0.413 tNET RR 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_0_s/I0
2.122 0.579 tINS RR 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_0_s/F
2.534 0.413 tNET RR 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
1.250 0.000 Gowin_PLL_inst/PLL_inst/CLKOUT2.default_gen_clk
1.574 0.324 tCL FF 102 Gowin_PLL_inst/PLL_inst/CLKOUT2
1.959 0.385 tNET FF 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
1.924 -0.035 tUnc u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
1.440 -0.484 tSu 1 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Path Statistics:
Clock Skew: -0.039
Setup Relationship: 1.250
Logic Level: 2
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 0.579, 32.400%; route: 0.825, 46.186%; tC2Q: 0.382, 21.414%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 5

Path Summary:
Slack 1.247
Data Arrival Time 9.437
Data Required Time 10.684
From u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_1_G[24]_s0
To u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_WRITE_s4
Launch Clk u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R]
Latch Clk u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.336 0.336 tCL RR 6401 u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.748 0.413 tNET RR 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_1_G[24]_s0/CLK
1.131 0.382 tC2Q RR 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_1_G[24]_s0/Q
1.543 0.413 tNET RR 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_168_G[0]_s5/I0
2.122 0.579 tINS RR 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_168_G[0]_s5/F
2.534 0.413 tNET RR 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_168_G[0]_s2/I0
2.684 0.150 tINS RR 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_168_G[0]_s2/O
3.097 0.413 tNET RR 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_168_G[0]_s0/I1
3.183 0.086 tINS RR 5 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_168_G[0]_s0/O
3.596 0.413 tNET RR 1 u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s25/I2
4.103 0.507 tINS RR 1 u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s25/F
4.516 0.413 tNET RR 1 u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s22/I1
4.666 0.150 tINS RR 1 u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s22/O
5.078 0.413 tNET RR 1 u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s21/I0
5.164 0.086 tINS RR 4 u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s21/O
5.577 0.413 tNET RR 1 u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_W2R_s59/I2
6.084 0.507 tINS RR 2 u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_W2R_s59/F
6.497 0.413 tNET RR 1 u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s75/I1
7.064 0.567 tINS RR 1 u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s75/F
7.477 0.413 tNET RR 1 u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s70/I1
8.044 0.567 tINS RR 1 u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s70/F
8.457 0.413 tNET RR 1 u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s68/I1
9.024 0.567 tINS RR 2 u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s68/F
9.437 0.413 tNET RR 1 u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_WRITE_s4/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
10.336 0.336 tCL RR 6401 u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.748 0.413 tNET RR 1 u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_WRITE_s4/CLK
10.684 -0.064 tSu 1 u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_WRITE_s4
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 8
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 3.769, 43.375%; route: 4.537, 52.223%; tC2Q: 0.382, 4.402%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%