Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\DDR3\data\ddr3_1_4code_hs\ddr3_1_4code_hs.v C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\DDR3\data\ddr3_1_4code_hs\DDR3_TOP.v |
GowinSynthesis Constraints File | --- |
Tool Version | V1.9.9.02 |
Part Number | GW5A-LV25UG324ES |
Device | GW5A-25 |
Device Version | A |
Created Time | Tue Mar 26 14:26:59 2024 |
Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | DDR3_Memory_Interface_Top |
Synthesis Process | Running parser: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 180.949MB Running netlist conversion: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.148s, Peak memory usage = 180.949MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.531s, Elapsed time = 0h 0m 0.534s, Peak memory usage = 180.949MB Optimizing Phase 1: CPU time = 0h 0m 0.343s, Elapsed time = 0h 0m 0.346s, Peak memory usage = 180.949MB Optimizing Phase 2: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 180.949MB Running inference: Inferring Phase 0: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 180.949MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 180.949MB Inferring Phase 2: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.064s, Peak memory usage = 180.949MB Inferring Phase 3: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.023s, Peak memory usage = 180.949MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.718s, Elapsed time = 0h 0m 0.715s, Peak memory usage = 180.949MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.187s, Elapsed time = 0h 0m 0.187s, Peak memory usage = 180.949MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.165s, Peak memory usage = 180.949MB Tech-Mapping Phase 3: CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s, Peak memory usage = 188.805MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.625s, Elapsed time = 0h 0m 0.643s, Peak memory usage = 188.805MB Generate output files: CPU time = 0h 0m 0.968s, Elapsed time = 0h 0m 0.984s, Peak memory usage = 199.609MB |
Total Time and Memory Usage | CPU time = 0h 0m 10s, Elapsed time = 0h 0m 10s, Peak memory usage = 199.609MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 665 |
I/O Buf | 657 |
    IBUF | 326 |
    OBUF | 290 |
    TBUF | 4 |
    IOBUF | 32 |
    ELVDS_OBUF | 1 |
    ELVDS_IOBUF | 4 |
Register | 5588 |
    DFFSE | 1 |
    DFFRE | 453 |
    DFFPE | 73 |
    DFFCE | 5061 |
LUT | 3328 |
    LUT2 | 651 |
    LUT3 | 1580 |
    LUT4 | 1097 |
ALU | 188 |
    ALU | 188 |
INV | 27 |
    INV | 27 |
IOLOGIC | 128 |
    IDES8_MEM | 32 |
    OSER8 | 24 |
    OSER8_MEM | 40 |
    IODELAY | 32 |
BSRAM | 24 |
    SDPB | 8 |
    SDPX9B | 16 |
CLOCK | 6 |
    CLKDIV | 1 |
    DQS | 4 |
    DDRDLL | 1 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 3543(3355 LUT, 188 ALU) / 23040 | 16% |
Register | 5588 / 23685 | 24% |
  --Register as Latch | 0 / 23685 | 0% |
  --Register as FF | 5588 / 23685 | 24% |
BSRAM | 24 / 56 | 43% |
Timing
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|
memory_clk | Base | 10.000 | 100.0 | 0.000 | 5.000 | memory_clk_ibuf/I | ||
clk | Base | 10.000 | 100.0 | 0.000 | 5.000 | clk_ibuf/I | ||
gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | Generated | 40.000 | 25.0 | 0.000 | 20.000 | memory_clk_ibuf/I | memory_clk | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
Max Frequency Summary:
No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | memory_clk | 100.000(MHz) | 1164.144(MHz) | 1 | TOP |
2 | clk | 100.000(MHz) | 193.143(MHz) | 6 | TOP |
3 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | 25.000(MHz) | 173.160(MHz) | 3 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | 2.480 |
Data Arrival Time | 2.351 |
Data Required Time | 4.831 |
From | gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_3_s0 |
To | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
Launch Clk | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[F] |
Latch Clk | memory_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
0.317 | 0.317 | tCL | RR | 5697 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
0.692 | 0.375 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_3_s0/CLK |
1.075 | 0.382 | tC2Q | RR | 9 | gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_3_s0/Q |
1.450 | 0.375 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_3_s/I0 |
1.976 | 0.526 | tINS | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_3_s/F |
2.351 | 0.375 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
5.000 | 0.000 | memory_clk | |||
5.000 | 0.000 | tCL | FF | 1 | memory_clk_ibuf/I |
5.000 | 0.000 | tINS | FF | 102 | memory_clk_ibuf/O |
5.350 | 0.350 | tNET | FF | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
5.315 | -0.035 | tUnc | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs | ||
4.831 | -0.484 | tSu | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
Clock Skew: | -0.343 |
Setup Relationship: | 5.000 |
Logic Level: | 2 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Arrival Data Path Delay: | cell: 0.526, 31.726%; route: 0.750, 45.214%; tC2Q: 0.382, 23.060% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 2
Path Summary:Slack | 2.480 |
Data Arrival Time | 2.351 |
Data Required Time | 4.831 |
From | gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_2_s0 |
To | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
Launch Clk | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[F] |
Latch Clk | memory_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
0.317 | 0.317 | tCL | RR | 5697 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
0.692 | 0.375 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_2_s0/CLK |
1.075 | 0.382 | tC2Q | RR | 9 | gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_2_s0/Q |
1.450 | 0.375 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_2_s/I0 |
1.976 | 0.526 | tINS | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_2_s/F |
2.351 | 0.375 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
5.000 | 0.000 | memory_clk | |||
5.000 | 0.000 | tCL | FF | 1 | memory_clk_ibuf/I |
5.000 | 0.000 | tINS | FF | 102 | memory_clk_ibuf/O |
5.350 | 0.350 | tNET | FF | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
5.315 | -0.035 | tUnc | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs | ||
4.831 | -0.484 | tSu | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
Clock Skew: | -0.343 |
Setup Relationship: | 5.000 |
Logic Level: | 2 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Arrival Data Path Delay: | cell: 0.526, 31.726%; route: 0.750, 45.214%; tC2Q: 0.382, 23.060% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 3
Path Summary:Slack | 2.480 |
Data Arrival Time | 2.351 |
Data Required Time | 4.831 |
From | gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_1_s0 |
To | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
Launch Clk | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[F] |
Latch Clk | memory_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
0.317 | 0.317 | tCL | RR | 5697 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
0.692 | 0.375 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_1_s0/CLK |
1.075 | 0.382 | tC2Q | RR | 9 | gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_1_s0/Q |
1.450 | 0.375 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_1_s/I0 |
1.976 | 0.526 | tINS | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_1_s/F |
2.351 | 0.375 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
5.000 | 0.000 | memory_clk | |||
5.000 | 0.000 | tCL | FF | 1 | memory_clk_ibuf/I |
5.000 | 0.000 | tINS | FF | 102 | memory_clk_ibuf/O |
5.350 | 0.350 | tNET | FF | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
5.315 | -0.035 | tUnc | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs | ||
4.831 | -0.484 | tSu | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
Clock Skew: | -0.343 |
Setup Relationship: | 5.000 |
Logic Level: | 2 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Arrival Data Path Delay: | cell: 0.526, 31.726%; route: 0.750, 45.214%; tC2Q: 0.382, 23.060% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 4
Path Summary:Slack | 2.480 |
Data Arrival Time | 2.351 |
Data Required Time | 4.831 |
From | gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_0_s0 |
To | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
Launch Clk | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[F] |
Latch Clk | memory_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
0.317 | 0.317 | tCL | RR | 5697 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
0.692 | 0.375 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_0_s0/CLK |
1.075 | 0.382 | tC2Q | RR | 9 | gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_0_s0/Q |
1.450 | 0.375 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_0_s/I0 |
1.976 | 0.526 | tINS | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_0_s/F |
2.351 | 0.375 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
5.000 | 0.000 | memory_clk | |||
5.000 | 0.000 | tCL | FF | 1 | memory_clk_ibuf/I |
5.000 | 0.000 | tINS | FF | 102 | memory_clk_ibuf/O |
5.350 | 0.350 | tNET | FF | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
5.315 | -0.035 | tUnc | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs | ||
4.831 | -0.484 | tSu | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
Clock Skew: | -0.343 |
Setup Relationship: | 5.000 |
Logic Level: | 2 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Arrival Data Path Delay: | cell: 0.526, 31.726%; route: 0.750, 45.214%; tC2Q: 0.382, 23.060% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 5
Path Summary:Slack | 4.822 |
Data Arrival Time | 5.489 |
Data Required Time | 10.311 |
From | gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_0_s3 |
To | gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_13_s1 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.000 | 0.000 | tINS | RR | 40 | clk_ibuf/O |
0.375 | 0.375 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_0_s3/CLK |
0.757 | 0.382 | tC2Q | RR | 6 | gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_0_s3/Q |
1.132 | 0.375 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/n53_s2/I0 |
1.659 | 0.526 | tINS | RR | 4 | gw3_top/u_ddr_phy_top/ddr_sync/n53_s2/F |
2.034 | 0.375 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/n50_s3/I1 |
2.550 | 0.516 | tINS | RR | 5 | gw3_top/u_ddr_phy_top/ddr_sync/n50_s3/F |
2.925 | 0.375 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/n46_s2/I2 |
3.386 | 0.461 | tINS | RR | 3 | gw3_top/u_ddr_phy_top/ddr_sync/n46_s2/F |
3.761 | 0.375 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/n44_s2/I2 |
4.223 | 0.461 | tINS | RR | 2 | gw3_top/u_ddr_phy_top/ddr_sync/n44_s2/F |
4.598 | 0.375 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/n44_s3/I1 |
5.114 | 0.516 | tINS | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/n44_s3/F |
5.489 | 0.375 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_13_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk | |||
10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
10.000 | 0.000 | tINS | RR | 40 | clk_ibuf/O |
10.375 | 0.375 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_13_s1/CLK |
10.311 | -0.064 | tSu | 1 | gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_13_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 6 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Arrival Data Path Delay: | cell: 2.481, 48.521%; route: 2.250, 43.999%; tC2Q: 0.382, 7.480% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |