Timing Messages
Report Title | Timing Analysis Report |
Design File | E:\myWork\IP\releaseVerify\RefDesign\Memory_Control\DDR3\Gowin_DDR3_Memory_Interface_RefDesign\DDR3_MC_PHY_1vs2\project\impl\gwsynthesis\ddr3_ref_design.vg |
Physical Constraints File | E:\myWork\IP\releaseVerify\RefDesign\Memory_Control\DDR3\Gowin_DDR3_Memory_Interface_RefDesign\DDR3_MC_PHY_1vs2\project\src\ddr3.cst |
Timing Constraint File | E:\myWork\IP\releaseVerify\RefDesign\Memory_Control\DDR3\Gowin_DDR3_Memory_Interface_RefDesign\DDR3_MC_PHY_1vs2\project\src\ddr3.sdc |
Tool Version | V1.9.9.02 |
Part Number | GW2A-LV18PG256C8/I7 |
Device | GW2A-18 |
Created Time | Tue Mar 26 15:11:25 2024 |
Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved. |
Timing Summaries
STA Tool Run Summary:
Setup Delay Model | Slow 0.95V 85C C8/I7 |
Hold Delay Model | Fast 1.05V 0C C8/I7 |
Numbers of Paths Analyzed | 6348 |
Numbers of Endpoints Analyzed | 6957 |
Numbers of Falling Endpoints | 3 |
Numbers of Setup Violated Endpoints | 0 |
Numbers of Hold Violated Endpoints | 0 |
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Objects |
---|---|---|---|---|---|---|---|---|
clk | Base | 20.000 | 50.000 | 0.000 | 10.000 | clk | ||
tck_pad_i | Base | 10.000 | 100.000 | 0.000 | 5.000 | tck_pad_i | ||
clk_x1 | Base | 10.000 | 100.000 | 0.000 | 5.000 | clk_x1 | ||
memory_clk | Base | 5.000 | 200.000 | 0.000 | 2.500 | memory_clk | ||
pll/rpll_inst/CLKOUTP.default_gen_clk | Generated | 5.000 | 200.000 | 0.000 | 2.500 | clk_ibuf/I | clk | pll/rpll_inst/CLKOUTP |
pll/rpll_inst/CLKOUTD.default_gen_clk | Generated | 10.000 | 100.000 | 0.000 | 5.000 | clk_ibuf/I | clk | pll/rpll_inst/CLKOUTD |
pll/rpll_inst/CLKOUTD3.default_gen_clk | Generated | 15.000 | 66.667 | 0.000 | 7.500 | clk_ibuf/I | clk | pll/rpll_inst/CLKOUTD3 |
Max Frequency Summary:
NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | clk | 50.000(MHz) | 239.841(MHz) | 6 | TOP |
2 | tck_pad_i | 100.000(MHz) | 112.538(MHz) | 7 | TOP |
3 | clk_x1 | 100.000(MHz) | 111.967(MHz) | 9 | TOP |
4 | memory_clk | 200.000(MHz) | 2016.130(MHz) | 1 | TOP |
No timing paths to get frequency of pll/rpll_inst/CLKOUTP.default_gen_clk!
No timing paths to get frequency of pll/rpll_inst/CLKOUTD.default_gen_clk!
No timing paths to get frequency of pll/rpll_inst/CLKOUTD3.default_gen_clk!
Total Negative Slack Summary:
Clock Name | Analysis Type | Endpoints TNS | Number of Endpoints |
---|---|---|---|
clk | Setup | 0.000 | 0 |
clk | Hold | 0.000 | 0 |
tck_pad_i | Setup | 0.000 | 0 |
tck_pad_i | Hold | 0.000 | 0 |
clk_x1 | Setup | 0.000 | 0 |
clk_x1 | Hold | 0.000 | 0 |
memory_clk | Setup | 0.000 | 0 |
memory_clk | Hold | 0.000 | 0 |
pll/rpll_inst/CLKOUTP.default_gen_clk | Setup | 0.000 | 0 |
pll/rpll_inst/CLKOUTP.default_gen_clk | Hold | 0.000 | 0 |
pll/rpll_inst/CLKOUTD.default_gen_clk | Setup | 0.000 | 0 |
pll/rpll_inst/CLKOUTD.default_gen_clk | Hold | 0.000 | 0 |
pll/rpll_inst/CLKOUTD3.default_gen_clk | Setup | 0.000 | 0 |
pll/rpll_inst/CLKOUTD3.default_gen_clk | Hold | 0.000 | 0 |
Timing Details
Path Slacks Table:
Setup Paths Table
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 1.069 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate_29_s0/Q | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_wr_data0/wr_fifo/Almost_Full_s0/D | clk_x1:[R] | clk_x1:[R] | 10.000 | 0.000 | 8.896 |
2 | 1.114 | gw_gao_inst_0/u_la0_top/word_count_3_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CEB | tck_pad_i:[R] | tck_pad_i:[R] | 10.000 | 0.000 | 8.799 |
3 | 1.280 | gw_gao_inst_0/u_la0_top/word_count_3_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CEB | tck_pad_i:[R] | tck_pad_i:[R] | 10.000 | 0.000 | 8.633 |
4 | 1.309 | gw_gao_inst_0/u_la0_top/word_count_3_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s/CEB | tck_pad_i:[R] | tck_pad_i:[R] | 10.000 | 0.000 | 8.604 |
5 | 1.425 | gw_gao_inst_0/u_la0_top/word_count_3_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_9_s/CEB | tck_pad_i:[R] | tck_pad_i:[R] | 10.000 | 0.000 | 8.488 |
6 | 1.437 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate_29_s0/Q | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_wr_data0/wr_fifo/Empty_s0/D | clk_x1:[R] | clk_x1:[R] | 10.000 | 0.000 | 8.528 |
7 | 1.467 | gw_gao_inst_0/u_la0_top/word_count_3_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CEB | tck_pad_i:[R] | tck_pad_i:[R] | 10.000 | 0.000 | 8.446 |
8 | 1.470 | gw_gao_inst_0/u_la0_top/word_count_3_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_8_s/CEB | tck_pad_i:[R] | tck_pad_i:[R] | 10.000 | 0.000 | 8.443 |
9 | 1.665 | gw_gao_inst_0/u_la0_top/word_count_3_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/CEB | tck_pad_i:[R] | tck_pad_i:[R] | 10.000 | 0.000 | 8.248 |
10 | 1.714 | gw_gao_inst_0/u_la0_top/word_count_3_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CEB | tck_pad_i:[R] | tck_pad_i:[R] | 10.000 | 0.000 | 8.199 |
11 | 1.901 | gw_gao_inst_0/u_la0_top/word_count_3_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CEB | tck_pad_i:[R] | tck_pad_i:[R] | 10.000 | 0.000 | 8.012 |
12 | 1.965 | gw_gao_inst_0/u_la0_top/word_count_3_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/CEB | tck_pad_i:[R] | tck_pad_i:[R] | 10.000 | 0.000 | 7.948 |
13 | 2.050 | gw_gao_inst_0/u_la0_top/word_count_3_s0/Q | gw_gao_inst_0/u_la0_top/word_count_6_s0/CE | tck_pad_i:[R] | tck_pad_i:[R] | 10.000 | 0.000 | 7.915 |
14 | 2.050 | gw_gao_inst_0/u_la0_top/word_count_3_s0/Q | gw_gao_inst_0/u_la0_top/word_count_7_s0/CE | tck_pad_i:[R] | tck_pad_i:[R] | 10.000 | 0.000 | 7.915 |
15 | 2.050 | gw_gao_inst_0/u_la0_top/word_count_3_s0/Q | gw_gao_inst_0/u_la0_top/word_count_13_s0/CE | tck_pad_i:[R] | tck_pad_i:[R] | 10.000 | 0.000 | 7.915 |
16 | 2.050 | gw_gao_inst_0/u_la0_top/word_count_3_s0/Q | gw_gao_inst_0/u_la0_top/word_count_14_s0/CE | tck_pad_i:[R] | tck_pad_i:[R] | 10.000 | 0.000 | 7.915 |
17 | 2.050 | gw_gao_inst_0/u_la0_top/word_count_3_s0/Q | gw_gao_inst_0/u_la0_top/word_count_15_s0/CE | tck_pad_i:[R] | tck_pad_i:[R] | 10.000 | 0.000 | 7.915 |
18 | 2.056 | gw_gao_inst_0/u_la0_top/word_count_3_s0/Q | gw_gao_inst_0/u_la0_top/word_count_8_s0/CE | tck_pad_i:[R] | tck_pad_i:[R] | 10.000 | 0.000 | 7.909 |
19 | 2.056 | gw_gao_inst_0/u_la0_top/word_count_3_s0/Q | gw_gao_inst_0/u_la0_top/word_count_10_s0/CE | tck_pad_i:[R] | tck_pad_i:[R] | 10.000 | 0.000 | 7.909 |
20 | 2.056 | gw_gao_inst_0/u_la0_top/word_count_3_s0/Q | gw_gao_inst_0/u_la0_top/word_count_11_s0/CE | tck_pad_i:[R] | tck_pad_i:[R] | 10.000 | 0.000 | 7.909 |
21 | 2.056 | gw_gao_inst_0/u_la0_top/word_count_3_s0/Q | gw_gao_inst_0/u_la0_top/word_count_12_s0/CE | tck_pad_i:[R] | tck_pad_i:[R] | 10.000 | 0.000 | 7.909 |
22 | 2.062 | gw_gao_inst_0/u_la0_top/word_count_3_s0/Q | gw_gao_inst_0/u_la0_top/word_count_4_s0/CE | tck_pad_i:[R] | tck_pad_i:[R] | 10.000 | 0.000 | 7.903 |
23 | 2.062 | gw_gao_inst_0/u_la0_top/word_count_3_s0/Q | gw_gao_inst_0/u_la0_top/word_count_5_s0/CE | tck_pad_i:[R] | tck_pad_i:[R] | 10.000 | 0.000 | 7.903 |
24 | 2.062 | gw_gao_inst_0/u_la0_top/word_count_3_s0/Q | gw_gao_inst_0/u_la0_top/word_count_9_s0/CE | tck_pad_i:[R] | tck_pad_i:[R] | 10.000 | 0.000 | 7.903 |
25 | 2.172 | gw_gao_inst_0/u_la0_top/word_count_3_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_19_s1/D | tck_pad_i:[R] | tck_pad_i:[R] | 10.000 | 0.000 | 7.793 |
Hold Paths Table
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 0.190 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_9_s/CEA | clk_x1:[R] | clk_x1:[R] | 0.000 | 0.000 | 0.202 |
2 | 0.190 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_8_s/CEA | clk_x1:[R] | clk_x1:[R] | 0.000 | 0.000 | 0.202 |
3 | 0.190 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s/CEA | clk_x1:[R] | clk_x1:[R] | 0.000 | 0.000 | 0.202 |
4 | 0.190 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/CEA | clk_x1:[R] | clk_x1:[R] | 0.000 | 0.000 | 0.202 |
5 | 0.190 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/CEA | clk_x1:[R] | clk_x1:[R] | 0.000 | 0.000 | 0.202 |
6 | 0.190 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CEA | clk_x1:[R] | clk_x1:[R] | 0.000 | 0.000 | 0.202 |
7 | 0.190 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CEA | clk_x1:[R] | clk_x1:[R] | 0.000 | 0.000 | 0.202 |
8 | 0.190 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CEA | clk_x1:[R] | clk_x1:[R] | 0.000 | 0.000 | 0.202 |
9 | 0.190 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CEA | clk_x1:[R] | clk_x1:[R] | 0.000 | 0.000 | 0.202 |
10 | 0.190 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CEA | clk_x1:[R] | clk_x1:[R] | 0.000 | 0.000 | 0.202 |
11 | 0.213 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_53_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[17] | clk_x1:[R] | clk_x1:[R] | 0.000 | 0.000 | 0.462 |
12 | 0.213 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_52_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[16] | clk_x1:[R] | clk_x1:[R] | 0.000 | 0.000 | 0.462 |
13 | 0.234 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/oserdes_d_reg_35_s0/Q | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[17].u_cmd_gen/D2 | clk_x1:[R] | clk_x1:[R] | 0.000 | 0.000 | 0.329 |
14 | 0.246 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/oserdes_d_reg_35_s0/Q | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[17].u_cmd_gen/D3 | clk_x1:[R] | clk_x1:[R] | 0.000 | 0.000 | 0.329 |
15 | 0.307 | gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0/Q | gw_gao_inst_0/u_la0_top/capture_end_tck_1_s0/D | tck_pad_i:[R] | tck_pad_i:[R] | 0.000 | 0.000 | 0.318 |
16 | 0.313 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gwmc_rank_ctrl0/cmd1_3_s0/Q | u_ddr3/u_gw3_phy_mc/u_gwmc_top/mc_address_dly_0_s14/DI[2] | clk_x1:[R] | clk_x1:[R] | 0.000 | 0.000 | 0.325 |
17 | 0.334 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides4/RADDR[2] | memory_clk:[R] | memory_clk:[R] | 0.000 | 0.000 | 0.334 |
18 | 0.334 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[1] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides4/RADDR[1] | memory_clk:[R] | memory_clk:[R] | 0.000 | 0.000 | 0.334 |
19 | 0.334 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides4/RADDR[0] | memory_clk:[R] | memory_clk:[R] | 0.000 | 0.000 | 0.334 |
20 | 0.334 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides4/RADDR[2] | memory_clk:[R] | memory_clk:[R] | 0.000 | 0.000 | 0.334 |
21 | 0.334 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[1] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides4/RADDR[1] | memory_clk:[R] | memory_clk:[R] | 0.000 | 0.000 | 0.334 |
22 | 0.334 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides4/RADDR[0] | memory_clk:[R] | memory_clk:[R] | 0.000 | 0.000 | 0.334 |
23 | 0.334 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides4/RADDR[2] | memory_clk:[R] | memory_clk:[R] | 0.000 | 0.000 | 0.334 |
24 | 0.334 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[1] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides4/RADDR[1] | memory_clk:[R] | memory_clk:[R] | 0.000 | 0.000 | 0.334 |
25 | 0.334 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides4/RADDR[0] | memory_clk:[R] | memory_clk:[R] | 0.000 | 0.000 | 0.334 |
Recovery Paths Table
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 2.644 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR | clk_x1:[F] | clk_x1:[R] | 5.000 | 0.003 | 2.318 |
2 | 2.644 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_2_s0/CLEAR | clk_x1:[F] | clk_x1:[R] | 5.000 | 0.003 | 2.318 |
3 | 2.644 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_0_s0/CLEAR | clk_x1:[F] | clk_x1:[R] | 5.000 | 0.003 | 2.318 |
4 | 2.898 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR | clk_x1:[F] | clk_x1:[R] | 5.000 | 0.003 | 2.064 |
5 | 2.898 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0/CLEAR | clk_x1:[F] | clk_x1:[R] | 5.000 | 0.003 | 2.064 |
6 | 2.904 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_1_s0/CLEAR | clk_x1:[F] | clk_x1:[R] | 5.000 | 0.003 | 2.058 |
7 | 3.147 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_2_s0/CLEAR | clk_x1:[F] | clk_x1:[R] | 5.000 | 0.003 | 1.815 |
8 | 3.152 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR | clk_x1:[F] | clk_x1:[R] | 5.000 | 0.003 | 1.810 |
9 | 3.180 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_1_s0/CLEAR | clk_x1:[F] | clk_x1:[R] | 5.000 | 0.003 | 1.782 |
10 | 3.422 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_2_s0/CLEAR | clk_x1:[F] | clk_x1:[R] | 5.000 | 0.003 | 1.540 |
11 | 3.519 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR | clk_x1:[F] | clk_x1:[R] | 5.000 | 0.003 | 1.443 |
12 | 3.519 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR | clk_x1:[F] | clk_x1:[R] | 5.000 | 0.003 | 1.443 |
13 | 3.519 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR | clk_x1:[F] | clk_x1:[R] | 5.000 | 0.003 | 1.443 |
14 | 3.519 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR | clk_x1:[F] | clk_x1:[R] | 5.000 | 0.003 | 1.443 |
15 | 3.519 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR | clk_x1:[F] | clk_x1:[R] | 5.000 | 0.003 | 1.443 |
16 | 3.519 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR | clk_x1:[F] | clk_x1:[R] | 5.000 | 0.003 | 1.443 |
17 | 3.519 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR | clk_x1:[F] | clk_x1:[R] | 5.000 | 0.003 | 1.443 |
18 | 3.519 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR | clk_x1:[F] | clk_x1:[R] | 5.000 | 0.003 | 1.443 |
19 | 3.519 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR | clk_x1:[F] | clk_x1:[R] | 5.000 | 0.003 | 1.443 |
20 | 3.519 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR | clk_x1:[F] | clk_x1:[R] | 5.000 | 0.003 | 1.443 |
21 | 3.519 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR | clk_x1:[F] | clk_x1:[R] | 5.000 | 0.003 | 1.443 |
22 | 3.519 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR | clk_x1:[F] | clk_x1:[R] | 5.000 | 0.003 | 1.443 |
23 | 3.519 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR | clk_x1:[F] | clk_x1:[R] | 5.000 | 0.003 | 1.443 |
24 | 3.519 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR | clk_x1:[F] | clk_x1:[R] | 5.000 | 0.003 | 1.443 |
25 | 3.519 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR | clk_x1:[F] | clk_x1:[R] | 5.000 | 0.003 | 1.443 |
Removal Paths Table
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 5.448 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLEAR | clk_x1:[F] | clk_x1:[R] | -5.000 | 0.002 | 0.457 |
2 | 5.448 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLEAR | clk_x1:[F] | clk_x1:[R] | -5.000 | 0.002 | 0.457 |
3 | 5.448 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLEAR | clk_x1:[F] | clk_x1:[R] | -5.000 | 0.002 | 0.457 |
4 | 5.448 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/triger_s0/CLEAR | clk_x1:[F] | clk_x1:[R] | -5.000 | 0.002 | 0.457 |
5 | 5.448 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLEAR | clk_x1:[F] | clk_x1:[R] | -5.000 | 0.002 | 0.457 |
6 | 5.573 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR | clk_x1:[F] | clk_x1:[R] | -5.000 | 0.002 | 0.582 |
7 | 5.573 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR | clk_x1:[F] | clk_x1:[R] | -5.000 | 0.002 | 0.582 |
8 | 5.575 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/start_reg_s0/CLEAR | clk_x1:[F] | clk_x1:[R] | -5.000 | 0.002 | 0.584 |
9 | 5.575 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLEAR | clk_x1:[F] | clk_x1:[R] | -5.000 | 0.002 | 0.584 |
10 | 5.575 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLEAR | clk_x1:[F] | clk_x1:[R] | -5.000 | 0.002 | 0.584 |
11 | 5.576 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLEAR | clk_x1:[F] | clk_x1:[R] | -5.000 | 0.002 | 0.585 |
12 | 5.576 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLEAR | clk_x1:[F] | clk_x1:[R] | -5.000 | 0.002 | 0.585 |
13 | 5.695 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLEAR | clk_x1:[F] | clk_x1:[R] | -5.000 | 0.002 | 0.704 |
14 | 5.700 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR | clk_x1:[F] | clk_x1:[R] | -5.000 | 0.002 | 0.709 |
15 | 5.700 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLEAR | clk_x1:[F] | clk_x1:[R] | -5.000 | 0.002 | 0.709 |
16 | 5.701 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR | clk_x1:[F] | clk_x1:[R] | -5.000 | 0.002 | 0.710 |
17 | 5.701 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR | clk_x1:[F] | clk_x1:[R] | -5.000 | 0.002 | 0.710 |
18 | 5.701 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLEAR | clk_x1:[F] | clk_x1:[R] | -5.000 | 0.002 | 0.710 |
19 | 5.703 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR | clk_x1:[F] | clk_x1:[R] | -5.000 | 0.002 | 0.712 |
20 | 5.703 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET | clk_x1:[F] | clk_x1:[R] | -5.000 | 0.002 | 0.712 |
21 | 5.730 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR | clk_x1:[F] | clk_x1:[R] | -5.000 | 0.002 | 0.739 |
22 | 5.730 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR | clk_x1:[F] | clk_x1:[R] | -5.000 | 0.002 | 0.739 |
23 | 5.739 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET | clk_x1:[F] | clk_x1:[R] | -5.000 | 0.002 | 0.748 |
24 | 5.739 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR | clk_x1:[F] | clk_x1:[R] | -5.000 | 0.002 | 0.748 |
25 | 5.823 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLEAR | clk_x1:[F] | clk_x1:[R] | -5.000 | 0.002 | 0.832 |
Minimum Pulse Width Table:
Number | Slack | Actual Width | Required Width | Type | Clock | Objects |
---|---|---|---|---|---|---|
1 | 0.837 | 1.837 | 1.000 | High Pulse Width | clk | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/stop_reg_1_s0 |
2 | 0.837 | 1.837 | 1.000 | High Pulse Width | clk | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/stop_reg_0_s0 |
3 | 0.837 | 1.837 | 1.000 | High Pulse Width | clk | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/ddr_rsti_reg_0_s0 |
4 | 0.837 | 1.837 | 1.000 | High Pulse Width | clk | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/uddcntln_reg_0_s0 |
5 | 0.837 | 1.837 | 1.000 | High Pulse Width | clk | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/cs_memsync_4_s0 |
6 | 0.837 | 1.837 | 1.000 | High Pulse Width | clk | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/lock_cnt_8_s1 |
7 | 0.837 | 1.837 | 1.000 | High Pulse Width | clk | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/lock_cnt_9_s1 |
8 | 0.837 | 1.837 | 1.000 | High Pulse Width | clk | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/cs_memsync_5_s0 |
9 | 0.837 | 1.837 | 1.000 | High Pulse Width | clk | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/lock_cnt_10_s1 |
10 | 0.837 | 1.837 | 1.000 | High Pulse Width | clk | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/lock_cnt_11_s1 |
Timing Report By Analysis Type:
Setup Analysis Report
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 1.069 |
Data Arrival Time | 11.168 |
Data Required Time | 12.236 |
From | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate_29_s0 |
To | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_wr_data0/wr_fifo/Almost_Full_s0 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
2.271 | 2.271 | tNET | RR | 1 | R36C19[1][A] | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate_29_s0/CLK |
2.503 | 0.232 | tC2Q | RF | 10 | R36C19[1][A] | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate_29_s0/Q |
3.471 | 0.968 | tNET | FF | 1 | R40C15[2][B] | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gwmc_bank_ctrl0/n1193_s12/I1 |
4.026 | 0.555 | tINS | FF | 5 | R40C15[2][B] | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gwmc_bank_ctrl0/n1193_s12/F |
4.553 | 0.527 | tNET | FF | 1 | R36C14[3][B] | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gwmc_bank_ctrl0/send_wr_Z_s1/I1 |
5.006 | 0.453 | tINS | FF | 6 | R36C14[3][B] | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gwmc_bank_ctrl0/send_wr_Z_s1/F |
5.825 | 0.819 | tNET | FF | 1 | R34C17[2][A] | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_wr_data0/wr_fifo/n28_s0/I3 |
6.380 | 0.555 | tINS | FF | 81 | R34C17[2][A] | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_wr_data0/wr_fifo/n28_s0/F |
7.314 | 0.934 | tNET | FF | 1 | R30C16[3][B] | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_wr_data0/wr_fifo/n641_s3/I3 |
7.831 | 0.517 | tINS | FF | 4 | R30C16[3][B] | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_wr_data0/wr_fifo/n641_s3/F |
8.084 | 0.253 | tNET | FF | 1 | R31C16[3][A] | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_wr_data0/wr_fifo/rbin_next_3_s3/I1 |
8.639 | 0.555 | tINS | FF | 3 | R31C16[3][A] | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_wr_data0/wr_fifo/rbin_next_3_s3/F |
8.802 | 0.163 | tNET | FF | 2 | R31C16[2][A] | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_wr_data0/wr_fifo/wcnt_sub_3_s/I1 |
9.173 | 0.371 | tINS | FF | 1 | R31C16[2][A] | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_wr_data0/wr_fifo/wcnt_sub_3_s/COUT |
10.056 | 0.883 | tNET | FF | 1 | R32C17[3][A] | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_wr_data0/wr_fifo/awfull_val_s17/I2 |
10.427 | 0.371 | tINS | FF | 1 | R32C17[3][A] | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_wr_data0/wr_fifo/awfull_val_s17/F |
10.598 | 0.170 | tNET | FF | 1 | R31C17[2][A] | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_wr_data0/wr_fifo/awfull_val_s16/I0 |
11.168 | 0.570 | tINS | FR | 1 | R31C17[2][A] | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_wr_data0/wr_fifo/awfull_val_s16/F |
11.168 | 0.000 | tNET | RR | 1 | R31C17[2][A] | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_wr_data0/wr_fifo/Almost_Full_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk_x1 | ||||
10.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
12.271 | 2.271 | tNET | RR | 1 | R31C17[2][A] | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_wr_data0/wr_fifo/Almost_Full_s0/CLK |
12.236 | -0.035 | tSu | 1 | R31C17[2][A] | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_wr_data0/wr_fifo/Almost_Full_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 9 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 3.947, 44.367%; route: 4.717, 53.025%; tC2Q: 0.232, 2.608% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path2
Path Summary:
Slack | 1.114 |
Data Arrival Time | 16.521 |
Data Required Time | 17.635 |
From | gw_gao_inst_0/u_la0_top/word_count_3_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s |
Launch Clk | tck_pad_i:[R] |
Latch Clk | tck_pad_i:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/I |
4.230 | 4.230 | tINS | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/O |
4.230 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
4.912 | 0.683 | tINS | RR | 631 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
7.722 | 2.810 | tNET | RR | 1 | R21C39[1][A] | gw_gao_inst_0/u_la0_top/word_count_3_s0/CLK |
7.954 | 0.232 | tC2Q | RF | 3 | R21C39[1][A] | gw_gao_inst_0/u_la0_top/word_count_3_s0/Q |
8.914 | 0.960 | tNET | FF | 1 | R16C32[3][B] | gw_gao_inst_0/u_la0_top/data_to_word_counter_4_s1/I3 |
9.431 | 0.517 | tINS | FF | 9 | R16C32[3][B] | gw_gao_inst_0/u_la0_top/data_to_word_counter_4_s1/F |
10.376 | 0.945 | tNET | FF | 1 | R14C27[3][A] | gw_gao_inst_0/u_la0_top/data_to_addr_counter_9_s3/I0 |
10.829 | 0.453 | tINS | FF | 8 | R14C27[3][A] | gw_gao_inst_0/u_la0_top/data_to_addr_counter_9_s3/F |
11.817 | 0.987 | tNET | FF | 1 | R20C36[2][A] | gw_gao_inst_0/u_la0_top/jtag_strobe_i_s4/I2 |
12.372 | 0.555 | tINS | FF | 1 | R20C36[2][A] | gw_gao_inst_0/u_la0_top/jtag_strobe_i_s4/F |
13.056 | 0.684 | tNET | FF | 1 | R15C34[3][B] | gw_gao_inst_0/u_la0_top/jtag_strobe_i_s2/I1 |
13.611 | 0.555 | tINS | FF | 1 | R15C34[3][B] | gw_gao_inst_0/u_la0_top/jtag_strobe_i_s2/F |
14.024 | 0.413 | tNET | FF | 1 | R14C33[2][B] | gw_gao_inst_0/u_la0_top/jtag_strobe_i_s1/I1 |
14.594 | 0.570 | tINS | FR | 1 | R14C33[2][B] | gw_gao_inst_0/u_la0_top/jtag_strobe_i_s1/F |
14.595 | 0.001 | tNET | RR | 1 | R14C33[3][A] | gw_gao_inst_0/u_la0_top/jtag_strobe_i_s0/I1 |
15.144 | 0.549 | tINS | RR | 110 | R14C33[3][A] | gw_gao_inst_0/u_la0_top/jtag_strobe_i_s0/F |
16.521 | 1.377 | tNET | RR | 1 | BSRAM_R28[5] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CEB |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | tck_pad_i | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/I |
14.230 | 4.230 | tINS | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/O |
14.230 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
14.912 | 0.683 | tINS | RR | 631 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
17.722 | 2.810 | tNET | RR | 1 | BSRAM_R28[5] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKB |
17.635 | -0.087 | tSu | 1 | BSRAM_R28[5] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 4.912, 63.614%; route: 2.810, 36.386% |
Arrival Data Path Delay | cell: 3.199, 36.357%; route: 5.368, 61.006%; tC2Q: 0.232, 2.637% |
Required Clock Path Delay | cell: 4.912, 63.614%; route: 2.810, 36.386% |
Path3
Path Summary:
Slack | 1.280 |
Data Arrival Time | 16.355 |
Data Required Time | 17.635 |
From | gw_gao_inst_0/u_la0_top/word_count_3_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Launch Clk | tck_pad_i:[R] |
Latch Clk | tck_pad_i:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/I |
4.230 | 4.230 | tINS | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/O |
4.230 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
4.912 | 0.683 | tINS | RR | 631 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
7.722 | 2.810 | tNET | RR | 1 | R21C39[1][A] | gw_gao_inst_0/u_la0_top/word_count_3_s0/CLK |
7.954 | 0.232 | tC2Q | RF | 3 | R21C39[1][A] | gw_gao_inst_0/u_la0_top/word_count_3_s0/Q |
8.914 | 0.960 | tNET | FF | 1 | R16C32[3][B] | gw_gao_inst_0/u_la0_top/data_to_word_counter_4_s1/I3 |
9.431 | 0.517 | tINS | FF | 9 | R16C32[3][B] | gw_gao_inst_0/u_la0_top/data_to_word_counter_4_s1/F |
10.376 | 0.945 | tNET | FF | 1 | R14C27[3][A] | gw_gao_inst_0/u_la0_top/data_to_addr_counter_9_s3/I0 |
10.829 | 0.453 | tINS | FF | 8 | R14C27[3][A] | gw_gao_inst_0/u_la0_top/data_to_addr_counter_9_s3/F |
11.817 | 0.987 | tNET | FF | 1 | R20C36[2][A] | gw_gao_inst_0/u_la0_top/jtag_strobe_i_s4/I2 |
12.372 | 0.555 | tINS | FF | 1 | R20C36[2][A] | gw_gao_inst_0/u_la0_top/jtag_strobe_i_s4/F |
13.056 | 0.684 | tNET | FF | 1 | R15C34[3][B] | gw_gao_inst_0/u_la0_top/jtag_strobe_i_s2/I1 |
13.611 | 0.555 | tINS | FF | 1 | R15C34[3][B] | gw_gao_inst_0/u_la0_top/jtag_strobe_i_s2/F |
14.024 | 0.413 | tNET | FF | 1 | R14C33[2][B] | gw_gao_inst_0/u_la0_top/jtag_strobe_i_s1/I1 |
14.594 | 0.570 | tINS | FR | 1 | R14C33[2][B] | gw_gao_inst_0/u_la0_top/jtag_strobe_i_s1/F |
14.595 | 0.001 | tNET | RR | 1 | R14C33[3][A] | gw_gao_inst_0/u_la0_top/jtag_strobe_i_s0/I1 |
15.144 | 0.549 | tINS | RR | 110 | R14C33[3][A] | gw_gao_inst_0/u_la0_top/jtag_strobe_i_s0/F |
16.355 | 1.211 | tNET | RR | 1 | BSRAM_R28[6] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CEB |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | tck_pad_i | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/I |
14.230 | 4.230 | tINS | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/O |
14.230 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
14.912 | 0.683 | tINS | RR | 631 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
17.722 | 2.810 | tNET | RR | 1 | BSRAM_R28[6] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKB |
17.635 | -0.087 | tSu | 1 | BSRAM_R28[6] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 4.912, 63.614%; route: 2.810, 36.386% |
Arrival Data Path Delay | cell: 3.199, 37.055%; route: 5.202, 60.258%; tC2Q: 0.232, 2.687% |
Required Clock Path Delay | cell: 4.912, 63.614%; route: 2.810, 36.386% |
Path4
Path Summary:
Slack | 1.309 |
Data Arrival Time | 16.326 |
Data Required Time | 17.635 |
From | gw_gao_inst_0/u_la0_top/word_count_3_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s |
Launch Clk | tck_pad_i:[R] |
Latch Clk | tck_pad_i:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/I |
4.230 | 4.230 | tINS | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/O |
4.230 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
4.912 | 0.683 | tINS | RR | 631 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
7.722 | 2.810 | tNET | RR | 1 | R21C39[1][A] | gw_gao_inst_0/u_la0_top/word_count_3_s0/CLK |
7.954 | 0.232 | tC2Q | RF | 3 | R21C39[1][A] | gw_gao_inst_0/u_la0_top/word_count_3_s0/Q |
8.914 | 0.960 | tNET | FF | 1 | R16C32[3][B] | gw_gao_inst_0/u_la0_top/data_to_word_counter_4_s1/I3 |
9.431 | 0.517 | tINS | FF | 9 | R16C32[3][B] | gw_gao_inst_0/u_la0_top/data_to_word_counter_4_s1/F |
10.376 | 0.945 | tNET | FF | 1 | R14C27[3][A] | gw_gao_inst_0/u_la0_top/data_to_addr_counter_9_s3/I0 |
10.829 | 0.453 | tINS | FF | 8 | R14C27[3][A] | gw_gao_inst_0/u_la0_top/data_to_addr_counter_9_s3/F |
11.817 | 0.987 | tNET | FF | 1 | R20C36[2][A] | gw_gao_inst_0/u_la0_top/jtag_strobe_i_s4/I2 |
12.372 | 0.555 | tINS | FF | 1 | R20C36[2][A] | gw_gao_inst_0/u_la0_top/jtag_strobe_i_s4/F |
13.056 | 0.684 | tNET | FF | 1 | R15C34[3][B] | gw_gao_inst_0/u_la0_top/jtag_strobe_i_s2/I1 |
13.611 | 0.555 | tINS | FF | 1 | R15C34[3][B] | gw_gao_inst_0/u_la0_top/jtag_strobe_i_s2/F |
14.024 | 0.413 | tNET | FF | 1 | R14C33[2][B] | gw_gao_inst_0/u_la0_top/jtag_strobe_i_s1/I1 |
14.594 | 0.570 | tINS | FR | 1 | R14C33[2][B] | gw_gao_inst_0/u_la0_top/jtag_strobe_i_s1/F |
14.595 | 0.001 | tNET | RR | 1 | R14C33[3][A] | gw_gao_inst_0/u_la0_top/jtag_strobe_i_s0/I1 |
15.144 | 0.549 | tINS | RR | 110 | R14C33[3][A] | gw_gao_inst_0/u_la0_top/jtag_strobe_i_s0/F |
16.326 | 1.182 | tNET | RR | 1 | BSRAM_R28[10] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s/CEB |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | tck_pad_i | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/I |
14.230 | 4.230 | tINS | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/O |
14.230 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
14.912 | 0.683 | tINS | RR | 631 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
17.722 | 2.810 | tNET | RR | 1 | BSRAM_R28[10] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s/CLKB |
17.635 | -0.087 | tSu | 1 | BSRAM_R28[10] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 4.912, 63.614%; route: 2.810, 36.386% |
Arrival Data Path Delay | cell: 3.199, 37.181%; route: 5.173, 60.122%; tC2Q: 0.232, 2.696% |
Required Clock Path Delay | cell: 4.912, 63.614%; route: 2.810, 36.386% |
Path5
Path Summary:
Slack | 1.425 |
Data Arrival Time | 16.210 |
Data Required Time | 17.635 |
From | gw_gao_inst_0/u_la0_top/word_count_3_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_9_s |
Launch Clk | tck_pad_i:[R] |
Latch Clk | tck_pad_i:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/I |
4.230 | 4.230 | tINS | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/O |
4.230 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
4.912 | 0.683 | tINS | RR | 631 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
7.722 | 2.810 | tNET | RR | 1 | R21C39[1][A] | gw_gao_inst_0/u_la0_top/word_count_3_s0/CLK |
7.954 | 0.232 | tC2Q | RF | 3 | R21C39[1][A] | gw_gao_inst_0/u_la0_top/word_count_3_s0/Q |
8.914 | 0.960 | tNET | FF | 1 | R16C32[3][B] | gw_gao_inst_0/u_la0_top/data_to_word_counter_4_s1/I3 |
9.431 | 0.517 | tINS | FF | 9 | R16C32[3][B] | gw_gao_inst_0/u_la0_top/data_to_word_counter_4_s1/F |
10.376 | 0.945 | tNET | FF | 1 | R14C27[3][A] | gw_gao_inst_0/u_la0_top/data_to_addr_counter_9_s3/I0 |
10.829 | 0.453 | tINS | FF | 8 | R14C27[3][A] | gw_gao_inst_0/u_la0_top/data_to_addr_counter_9_s3/F |
11.817 | 0.987 | tNET | FF | 1 | R20C36[2][A] | gw_gao_inst_0/u_la0_top/jtag_strobe_i_s4/I2 |
12.372 | 0.555 | tINS | FF | 1 | R20C36[2][A] | gw_gao_inst_0/u_la0_top/jtag_strobe_i_s4/F |
13.056 | 0.684 | tNET | FF | 1 | R15C34[3][B] | gw_gao_inst_0/u_la0_top/jtag_strobe_i_s2/I1 |
13.611 | 0.555 | tINS | FF | 1 | R15C34[3][B] | gw_gao_inst_0/u_la0_top/jtag_strobe_i_s2/F |
14.024 | 0.413 | tNET | FF | 1 | R14C33[2][B] | gw_gao_inst_0/u_la0_top/jtag_strobe_i_s1/I1 |
14.594 | 0.570 | tINS | FR | 1 | R14C33[2][B] | gw_gao_inst_0/u_la0_top/jtag_strobe_i_s1/F |
14.595 | 0.001 | tNET | RR | 1 | R14C33[3][A] | gw_gao_inst_0/u_la0_top/jtag_strobe_i_s0/I1 |
15.144 | 0.549 | tINS | RR | 110 | R14C33[3][A] | gw_gao_inst_0/u_la0_top/jtag_strobe_i_s0/F |
16.210 | 1.065 | tNET | RR | 1 | BSRAM_R28[12] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_9_s/CEB |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | tck_pad_i | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/I |
14.230 | 4.230 | tINS | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/O |
14.230 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
14.912 | 0.683 | tINS | RR | 631 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
17.722 | 2.810 | tNET | RR | 1 | BSRAM_R28[12] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_9_s/CLKB |
17.635 | -0.087 | tSu | 1 | BSRAM_R28[12] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_9_s |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 4.912, 63.614%; route: 2.810, 36.386% |
Arrival Data Path Delay | cell: 3.199, 37.690%; route: 5.057, 59.576%; tC2Q: 0.232, 2.733% |
Required Clock Path Delay | cell: 4.912, 63.614%; route: 2.810, 36.386% |
Path6
Path Summary:
Slack | 1.437 |
Data Arrival Time | 10.799 |
Data Required Time | 12.236 |
From | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate_29_s0 |
To | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_wr_data0/wr_fifo/Empty_s0 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
2.271 | 2.271 | tNET | RR | 1 | R36C19[1][A] | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate_29_s0/CLK |
2.503 | 0.232 | tC2Q | RF | 10 | R36C19[1][A] | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate_29_s0/Q |
3.471 | 0.968 | tNET | FF | 1 | R40C15[2][B] | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gwmc_bank_ctrl0/n1193_s12/I1 |
4.026 | 0.555 | tINS | FF | 5 | R40C15[2][B] | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gwmc_bank_ctrl0/n1193_s12/F |
4.553 | 0.527 | tNET | FF | 1 | R36C14[3][B] | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gwmc_bank_ctrl0/send_wr_Z_s1/I1 |
5.006 | 0.453 | tINS | FF | 6 | R36C14[3][B] | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gwmc_bank_ctrl0/send_wr_Z_s1/F |
5.825 | 0.819 | tNET | FF | 1 | R34C17[2][A] | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_wr_data0/wr_fifo/n28_s0/I3 |
6.380 | 0.555 | tINS | FF | 81 | R34C17[2][A] | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_wr_data0/wr_fifo/n28_s0/F |
7.314 | 0.934 | tNET | FF | 1 | R30C16[3][B] | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_wr_data0/wr_fifo/n641_s3/I3 |
7.831 | 0.517 | tINS | FF | 4 | R30C16[3][B] | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_wr_data0/wr_fifo/n641_s3/F |
8.084 | 0.253 | tNET | FF | 1 | R31C16[3][A] | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_wr_data0/wr_fifo/rbin_next_3_s3/I1 |
8.654 | 0.570 | tINS | FR | 3 | R31C16[3][A] | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_wr_data0/wr_fifo/rbin_next_3_s3/F |
8.829 | 0.175 | tNET | RR | 2 | R31C15[2][A] | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_wr_data0/wr_fifo/n655_s0/I0 |
9.346 | 0.517 | tINS | RF | 1 | R31C15[2][A] | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_wr_data0/wr_fifo/n655_s0/COUT |
10.229 | 0.883 | tNET | FF | 1 | R31C17[2][B] | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_wr_data0/wr_fifo/rempty_val_s2/I3 |
10.799 | 0.570 | tINS | FR | 1 | R31C17[2][B] | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_wr_data0/wr_fifo/rempty_val_s2/F |
10.799 | 0.000 | tNET | RR | 1 | R31C17[2][B] | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_wr_data0/wr_fifo/Empty_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk_x1 | ||||
10.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
12.271 | 2.271 | tNET | RR | 1 | R31C17[2][B] | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_wr_data0/wr_fifo/Empty_s0/CLK |
12.236 | -0.035 | tSu | 1 | R31C17[2][B] | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_wr_data0/wr_fifo/Empty_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 8 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 3.737, 43.821%; route: 4.559, 53.459%; tC2Q: 0.232, 2.720% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path7
Path Summary:
Slack | 1.467 |
Data Arrival Time | 16.168 |
Data Required Time | 17.635 |
From | gw_gao_inst_0/u_la0_top/word_count_3_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s |
Launch Clk | tck_pad_i:[R] |
Latch Clk | tck_pad_i:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/I |
4.230 | 4.230 | tINS | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/O |
4.230 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
4.912 | 0.683 | tINS | RR | 631 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
7.722 | 2.810 | tNET | RR | 1 | R21C39[1][A] | gw_gao_inst_0/u_la0_top/word_count_3_s0/CLK |
7.954 | 0.232 | tC2Q | RF | 3 | R21C39[1][A] | gw_gao_inst_0/u_la0_top/word_count_3_s0/Q |
8.914 | 0.960 | tNET | FF | 1 | R16C32[3][B] | gw_gao_inst_0/u_la0_top/data_to_word_counter_4_s1/I3 |
9.431 | 0.517 | tINS | FF | 9 | R16C32[3][B] | gw_gao_inst_0/u_la0_top/data_to_word_counter_4_s1/F |
10.376 | 0.945 | tNET | FF | 1 | R14C27[3][A] | gw_gao_inst_0/u_la0_top/data_to_addr_counter_9_s3/I0 |
10.829 | 0.453 | tINS | FF | 8 | R14C27[3][A] | gw_gao_inst_0/u_la0_top/data_to_addr_counter_9_s3/F |
11.817 | 0.987 | tNET | FF | 1 | R20C36[2][A] | gw_gao_inst_0/u_la0_top/jtag_strobe_i_s4/I2 |
12.372 | 0.555 | tINS | FF | 1 | R20C36[2][A] | gw_gao_inst_0/u_la0_top/jtag_strobe_i_s4/F |
13.056 | 0.684 | tNET | FF | 1 | R15C34[3][B] | gw_gao_inst_0/u_la0_top/jtag_strobe_i_s2/I1 |
13.611 | 0.555 | tINS | FF | 1 | R15C34[3][B] | gw_gao_inst_0/u_la0_top/jtag_strobe_i_s2/F |
14.024 | 0.413 | tNET | FF | 1 | R14C33[2][B] | gw_gao_inst_0/u_la0_top/jtag_strobe_i_s1/I1 |
14.594 | 0.570 | tINS | FR | 1 | R14C33[2][B] | gw_gao_inst_0/u_la0_top/jtag_strobe_i_s1/F |
14.595 | 0.001 | tNET | RR | 1 | R14C33[3][A] | gw_gao_inst_0/u_la0_top/jtag_strobe_i_s0/I1 |
15.144 | 0.549 | tINS | RR | 110 | R14C33[3][A] | gw_gao_inst_0/u_la0_top/jtag_strobe_i_s0/F |
16.168 | 1.024 | tNET | RR | 1 | BSRAM_R28[7] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CEB |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | tck_pad_i | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/I |
14.230 | 4.230 | tINS | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/O |
14.230 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
14.912 | 0.683 | tINS | RR | 631 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
17.722 | 2.810 | tNET | RR | 1 | BSRAM_R28[7] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKB |
17.635 | -0.087 | tSu | 1 | BSRAM_R28[7] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 4.912, 63.614%; route: 2.810, 36.386% |
Arrival Data Path Delay | cell: 3.199, 37.875%; route: 5.015, 59.378%; tC2Q: 0.232, 2.747% |
Required Clock Path Delay | cell: 4.912, 63.614%; route: 2.810, 36.386% |
Path8
Path Summary:
Slack | 1.470 |
Data Arrival Time | 16.165 |
Data Required Time | 17.635 |
From | gw_gao_inst_0/u_la0_top/word_count_3_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_8_s |
Launch Clk | tck_pad_i:[R] |
Latch Clk | tck_pad_i:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/I |
4.230 | 4.230 | tINS | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/O |
4.230 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
4.912 | 0.683 | tINS | RR | 631 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
7.722 | 2.810 | tNET | RR | 1 | R21C39[1][A] | gw_gao_inst_0/u_la0_top/word_count_3_s0/CLK |
7.954 | 0.232 | tC2Q | RF | 3 | R21C39[1][A] | gw_gao_inst_0/u_la0_top/word_count_3_s0/Q |
8.914 | 0.960 | tNET | FF | 1 | R16C32[3][B] | gw_gao_inst_0/u_la0_top/data_to_word_counter_4_s1/I3 |
9.431 | 0.517 | tINS | FF | 9 | R16C32[3][B] | gw_gao_inst_0/u_la0_top/data_to_word_counter_4_s1/F |
10.376 | 0.945 | tNET | FF | 1 | R14C27[3][A] | gw_gao_inst_0/u_la0_top/data_to_addr_counter_9_s3/I0 |
10.829 | 0.453 | tINS | FF | 8 | R14C27[3][A] | gw_gao_inst_0/u_la0_top/data_to_addr_counter_9_s3/F |
11.817 | 0.987 | tNET | FF | 1 | R20C36[2][A] | gw_gao_inst_0/u_la0_top/jtag_strobe_i_s4/I2 |
12.372 | 0.555 | tINS | FF | 1 | R20C36[2][A] | gw_gao_inst_0/u_la0_top/jtag_strobe_i_s4/F |
13.056 | 0.684 | tNET | FF | 1 | R15C34[3][B] | gw_gao_inst_0/u_la0_top/jtag_strobe_i_s2/I1 |
13.611 | 0.555 | tINS | FF | 1 | R15C34[3][B] | gw_gao_inst_0/u_la0_top/jtag_strobe_i_s2/F |
14.024 | 0.413 | tNET | FF | 1 | R14C33[2][B] | gw_gao_inst_0/u_la0_top/jtag_strobe_i_s1/I1 |
14.594 | 0.570 | tINS | FR | 1 | R14C33[2][B] | gw_gao_inst_0/u_la0_top/jtag_strobe_i_s1/F |
14.595 | 0.001 | tNET | RR | 1 | R14C33[3][A] | gw_gao_inst_0/u_la0_top/jtag_strobe_i_s0/I1 |
15.144 | 0.549 | tINS | RR | 110 | R14C33[3][A] | gw_gao_inst_0/u_la0_top/jtag_strobe_i_s0/F |
16.165 | 1.021 | tNET | RR | 1 | BSRAM_R28[11] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_8_s/CEB |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | tck_pad_i | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/I |
14.230 | 4.230 | tINS | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/O |
14.230 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
14.912 | 0.683 | tINS | RR | 631 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
17.722 | 2.810 | tNET | RR | 1 | BSRAM_R28[11] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_8_s/CLKB |
17.635 | -0.087 | tSu | 1 | BSRAM_R28[11] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_8_s |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 4.912, 63.614%; route: 2.810, 36.386% |
Arrival Data Path Delay | cell: 3.199, 37.889%; route: 5.012, 59.363%; tC2Q: 0.232, 2.748% |
Required Clock Path Delay | cell: 4.912, 63.614%; route: 2.810, 36.386% |
Path9
Path Summary:
Slack | 1.665 |
Data Arrival Time | 15.970 |
Data Required Time | 17.635 |
From | gw_gao_inst_0/u_la0_top/word_count_3_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s |
Launch Clk | tck_pad_i:[R] |
Latch Clk | tck_pad_i:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/I |
4.230 | 4.230 | tINS | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/O |
4.230 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
4.912 | 0.683 | tINS | RR | 631 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
7.722 | 2.810 | tNET | RR | 1 | R21C39[1][A] | gw_gao_inst_0/u_la0_top/word_count_3_s0/CLK |
7.954 | 0.232 | tC2Q | RF | 3 | R21C39[1][A] | gw_gao_inst_0/u_la0_top/word_count_3_s0/Q |
8.914 | 0.960 | tNET | FF | 1 | R16C32[3][B] | gw_gao_inst_0/u_la0_top/data_to_word_counter_4_s1/I3 |
9.431 | 0.517 | tINS | FF | 9 | R16C32[3][B] | gw_gao_inst_0/u_la0_top/data_to_word_counter_4_s1/F |
10.376 | 0.945 | tNET | FF | 1 | R14C27[3][A] | gw_gao_inst_0/u_la0_top/data_to_addr_counter_9_s3/I0 |
10.829 | 0.453 | tINS | FF | 8 | R14C27[3][A] | gw_gao_inst_0/u_la0_top/data_to_addr_counter_9_s3/F |
11.817 | 0.987 | tNET | FF | 1 | R20C36[2][A] | gw_gao_inst_0/u_la0_top/jtag_strobe_i_s4/I2 |
12.372 | 0.555 | tINS | FF | 1 | R20C36[2][A] | gw_gao_inst_0/u_la0_top/jtag_strobe_i_s4/F |
13.056 | 0.684 | tNET | FF | 1 | R15C34[3][B] | gw_gao_inst_0/u_la0_top/jtag_strobe_i_s2/I1 |
13.611 | 0.555 | tINS | FF | 1 | R15C34[3][B] | gw_gao_inst_0/u_la0_top/jtag_strobe_i_s2/F |
14.024 | 0.413 | tNET | FF | 1 | R14C33[2][B] | gw_gao_inst_0/u_la0_top/jtag_strobe_i_s1/I1 |
14.594 | 0.570 | tINS | FR | 1 | R14C33[2][B] | gw_gao_inst_0/u_la0_top/jtag_strobe_i_s1/F |
14.595 | 0.001 | tNET | RR | 1 | R14C33[3][A] | gw_gao_inst_0/u_la0_top/jtag_strobe_i_s0/I1 |
15.144 | 0.549 | tINS | RR | 110 | R14C33[3][A] | gw_gao_inst_0/u_la0_top/jtag_strobe_i_s0/F |
15.970 | 0.826 | tNET | RR | 1 | BSRAM_R28[8] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/CEB |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | tck_pad_i | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/I |
14.230 | 4.230 | tINS | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/O |
14.230 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
14.912 | 0.683 | tINS | RR | 631 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
17.722 | 2.810 | tNET | RR | 1 | BSRAM_R28[8] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/CLKB |
17.635 | -0.087 | tSu | 1 | BSRAM_R28[8] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 4.912, 63.614%; route: 2.810, 36.386% |
Arrival Data Path Delay | cell: 3.199, 38.785%; route: 4.817, 58.403%; tC2Q: 0.232, 2.813% |
Required Clock Path Delay | cell: 4.912, 63.614%; route: 2.810, 36.386% |
Path10
Path Summary:
Slack | 1.714 |
Data Arrival Time | 15.921 |
Data Required Time | 17.635 |
From | gw_gao_inst_0/u_la0_top/word_count_3_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s |
Launch Clk | tck_pad_i:[R] |
Latch Clk | tck_pad_i:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/I |
4.230 | 4.230 | tINS | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/O |
4.230 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
4.912 | 0.683 | tINS | RR | 631 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
7.722 | 2.810 | tNET | RR | 1 | R21C39[1][A] | gw_gao_inst_0/u_la0_top/word_count_3_s0/CLK |
7.954 | 0.232 | tC2Q | RF | 3 | R21C39[1][A] | gw_gao_inst_0/u_la0_top/word_count_3_s0/Q |
8.914 | 0.960 | tNET | FF | 1 | R16C32[3][B] | gw_gao_inst_0/u_la0_top/data_to_word_counter_4_s1/I3 |
9.431 | 0.517 | tINS | FF | 9 | R16C32[3][B] | gw_gao_inst_0/u_la0_top/data_to_word_counter_4_s1/F |
10.376 | 0.945 | tNET | FF | 1 | R14C27[3][A] | gw_gao_inst_0/u_la0_top/data_to_addr_counter_9_s3/I0 |
10.829 | 0.453 | tINS | FF | 8 | R14C27[3][A] | gw_gao_inst_0/u_la0_top/data_to_addr_counter_9_s3/F |
11.817 | 0.987 | tNET | FF | 1 | R20C36[2][A] | gw_gao_inst_0/u_la0_top/jtag_strobe_i_s4/I2 |
12.372 | 0.555 | tINS | FF | 1 | R20C36[2][A] | gw_gao_inst_0/u_la0_top/jtag_strobe_i_s4/F |
13.056 | 0.684 | tNET | FF | 1 | R15C34[3][B] | gw_gao_inst_0/u_la0_top/jtag_strobe_i_s2/I1 |
13.611 | 0.555 | tINS | FF | 1 | R15C34[3][B] | gw_gao_inst_0/u_la0_top/jtag_strobe_i_s2/F |
14.024 | 0.413 | tNET | FF | 1 | R14C33[2][B] | gw_gao_inst_0/u_la0_top/jtag_strobe_i_s1/I1 |
14.594 | 0.570 | tINS | FR | 1 | R14C33[2][B] | gw_gao_inst_0/u_la0_top/jtag_strobe_i_s1/F |
14.595 | 0.001 | tNET | RR | 1 | R14C33[3][A] | gw_gao_inst_0/u_la0_top/jtag_strobe_i_s0/I1 |
15.144 | 0.549 | tINS | RR | 110 | R14C33[3][A] | gw_gao_inst_0/u_la0_top/jtag_strobe_i_s0/F |
15.921 | 0.777 | tNET | RR | 1 | BSRAM_R10[7] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CEB |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | tck_pad_i | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/I |
14.230 | 4.230 | tINS | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/O |
14.230 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
14.912 | 0.683 | tINS | RR | 631 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
17.722 | 2.810 | tNET | RR | 1 | BSRAM_R10[7] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKB |
17.635 | -0.087 | tSu | 1 | BSRAM_R10[7] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 4.912, 63.614%; route: 2.810, 36.386% |
Arrival Data Path Delay | cell: 3.199, 39.017%; route: 4.768, 58.153%; tC2Q: 0.232, 2.830% |
Required Clock Path Delay | cell: 4.912, 63.614%; route: 2.810, 36.386% |
Path11
Path Summary:
Slack | 1.901 |
Data Arrival Time | 15.734 |
Data Required Time | 17.635 |
From | gw_gao_inst_0/u_la0_top/word_count_3_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s |
Launch Clk | tck_pad_i:[R] |
Latch Clk | tck_pad_i:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/I |
4.230 | 4.230 | tINS | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/O |
4.230 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
4.912 | 0.683 | tINS | RR | 631 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
7.722 | 2.810 | tNET | RR | 1 | R21C39[1][A] | gw_gao_inst_0/u_la0_top/word_count_3_s0/CLK |
7.954 | 0.232 | tC2Q | RF | 3 | R21C39[1][A] | gw_gao_inst_0/u_la0_top/word_count_3_s0/Q |
8.914 | 0.960 | tNET | FF | 1 | R16C32[3][B] | gw_gao_inst_0/u_la0_top/data_to_word_counter_4_s1/I3 |
9.431 | 0.517 | tINS | FF | 9 | R16C32[3][B] | gw_gao_inst_0/u_la0_top/data_to_word_counter_4_s1/F |
10.376 | 0.945 | tNET | FF | 1 | R14C27[3][A] | gw_gao_inst_0/u_la0_top/data_to_addr_counter_9_s3/I0 |
10.829 | 0.453 | tINS | FF | 8 | R14C27[3][A] | gw_gao_inst_0/u_la0_top/data_to_addr_counter_9_s3/F |
11.817 | 0.987 | tNET | FF | 1 | R20C36[2][A] | gw_gao_inst_0/u_la0_top/jtag_strobe_i_s4/I2 |
12.372 | 0.555 | tINS | FF | 1 | R20C36[2][A] | gw_gao_inst_0/u_la0_top/jtag_strobe_i_s4/F |
13.056 | 0.684 | tNET | FF | 1 | R15C34[3][B] | gw_gao_inst_0/u_la0_top/jtag_strobe_i_s2/I1 |
13.611 | 0.555 | tINS | FF | 1 | R15C34[3][B] | gw_gao_inst_0/u_la0_top/jtag_strobe_i_s2/F |
14.024 | 0.413 | tNET | FF | 1 | R14C33[2][B] | gw_gao_inst_0/u_la0_top/jtag_strobe_i_s1/I1 |
14.594 | 0.570 | tINS | FR | 1 | R14C33[2][B] | gw_gao_inst_0/u_la0_top/jtag_strobe_i_s1/F |
14.595 | 0.001 | tNET | RR | 1 | R14C33[3][A] | gw_gao_inst_0/u_la0_top/jtag_strobe_i_s0/I1 |
15.144 | 0.549 | tINS | RR | 110 | R14C33[3][A] | gw_gao_inst_0/u_la0_top/jtag_strobe_i_s0/F |
15.734 | 0.590 | tNET | RR | 1 | BSRAM_R10[8] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CEB |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | tck_pad_i | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/I |
14.230 | 4.230 | tINS | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/O |
14.230 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
14.912 | 0.683 | tINS | RR | 631 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
17.722 | 2.810 | tNET | RR | 1 | BSRAM_R10[8] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CLKB |
17.635 | -0.087 | tSu | 1 | BSRAM_R10[8] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 4.912, 63.614%; route: 2.810, 36.386% |
Arrival Data Path Delay | cell: 3.199, 39.928%; route: 4.581, 57.177%; tC2Q: 0.232, 2.896% |
Required Clock Path Delay | cell: 4.912, 63.614%; route: 2.810, 36.386% |
Path12
Path Summary:
Slack | 1.965 |
Data Arrival Time | 15.671 |
Data Required Time | 17.635 |
From | gw_gao_inst_0/u_la0_top/word_count_3_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s |
Launch Clk | tck_pad_i:[R] |
Latch Clk | tck_pad_i:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/I |
4.230 | 4.230 | tINS | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/O |
4.230 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
4.912 | 0.683 | tINS | RR | 631 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
7.722 | 2.810 | tNET | RR | 1 | R21C39[1][A] | gw_gao_inst_0/u_la0_top/word_count_3_s0/CLK |
7.954 | 0.232 | tC2Q | RF | 3 | R21C39[1][A] | gw_gao_inst_0/u_la0_top/word_count_3_s0/Q |
8.914 | 0.960 | tNET | FF | 1 | R16C32[3][B] | gw_gao_inst_0/u_la0_top/data_to_word_counter_4_s1/I3 |
9.431 | 0.517 | tINS | FF | 9 | R16C32[3][B] | gw_gao_inst_0/u_la0_top/data_to_word_counter_4_s1/F |
10.376 | 0.945 | tNET | FF | 1 | R14C27[3][A] | gw_gao_inst_0/u_la0_top/data_to_addr_counter_9_s3/I0 |
10.829 | 0.453 | tINS | FF | 8 | R14C27[3][A] | gw_gao_inst_0/u_la0_top/data_to_addr_counter_9_s3/F |
11.817 | 0.987 | tNET | FF | 1 | R20C36[2][A] | gw_gao_inst_0/u_la0_top/jtag_strobe_i_s4/I2 |
12.372 | 0.555 | tINS | FF | 1 | R20C36[2][A] | gw_gao_inst_0/u_la0_top/jtag_strobe_i_s4/F |
13.056 | 0.684 | tNET | FF | 1 | R15C34[3][B] | gw_gao_inst_0/u_la0_top/jtag_strobe_i_s2/I1 |
13.611 | 0.555 | tINS | FF | 1 | R15C34[3][B] | gw_gao_inst_0/u_la0_top/jtag_strobe_i_s2/F |
14.024 | 0.413 | tNET | FF | 1 | R14C33[2][B] | gw_gao_inst_0/u_la0_top/jtag_strobe_i_s1/I1 |
14.594 | 0.570 | tINS | FR | 1 | R14C33[2][B] | gw_gao_inst_0/u_la0_top/jtag_strobe_i_s1/F |
14.595 | 0.001 | tNET | RR | 1 | R14C33[3][A] | gw_gao_inst_0/u_la0_top/jtag_strobe_i_s0/I1 |
15.144 | 0.549 | tINS | RR | 110 | R14C33[3][A] | gw_gao_inst_0/u_la0_top/jtag_strobe_i_s0/F |
15.671 | 0.526 | tNET | RR | 1 | BSRAM_R10[9] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/CEB |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | tck_pad_i | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/I |
14.230 | 4.230 | tINS | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/O |
14.230 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
14.912 | 0.683 | tINS | RR | 631 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
17.722 | 2.810 | tNET | RR | 1 | BSRAM_R10[9] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/CLKB |
17.635 | -0.087 | tSu | 1 | BSRAM_R10[9] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 4.912, 63.614%; route: 2.810, 36.386% |
Arrival Data Path Delay | cell: 3.199, 40.247%; route: 4.517, 56.834%; tC2Q: 0.232, 2.919% |
Required Clock Path Delay | cell: 4.912, 63.614%; route: 2.810, 36.386% |
Path13
Path Summary:
Slack | 2.050 |
Data Arrival Time | 15.637 |
Data Required Time | 17.687 |
From | gw_gao_inst_0/u_la0_top/word_count_3_s0 |
To | gw_gao_inst_0/u_la0_top/word_count_6_s0 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | tck_pad_i:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/I |
4.230 | 4.230 | tINS | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/O |
4.230 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
4.912 | 0.683 | tINS | RR | 631 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
7.722 | 2.810 | tNET | RR | 1 | R21C39[1][A] | gw_gao_inst_0/u_la0_top/word_count_3_s0/CLK |
7.954 | 0.232 | tC2Q | RF | 3 | R21C39[1][A] | gw_gao_inst_0/u_la0_top/word_count_3_s0/Q |
8.914 | 0.960 | tNET | FF | 1 | R16C32[3][B] | gw_gao_inst_0/u_la0_top/data_to_word_counter_4_s1/I3 |
9.431 | 0.517 | tINS | FF | 9 | R16C32[3][B] | gw_gao_inst_0/u_la0_top/data_to_word_counter_4_s1/F |
10.376 | 0.945 | tNET | FF | 1 | R14C27[3][A] | gw_gao_inst_0/u_la0_top/data_to_addr_counter_9_s3/I0 |
10.829 | 0.453 | tINS | FF | 8 | R14C27[3][A] | gw_gao_inst_0/u_la0_top/data_to_addr_counter_9_s3/F |
11.303 | 0.474 | tNET | FF | 1 | R14C36[3][B] | gw_gao_inst_0/u_la0_top/module_next_state_2_s28/I1 |
11.858 | 0.555 | tINS | FF | 2 | R14C36[3][B] | gw_gao_inst_0/u_la0_top/module_next_state_2_s28/F |
12.260 | 0.401 | tNET | FF | 1 | R14C34[3][A] | gw_gao_inst_0/u_la0_top/module_next_state_2_s25/I2 |
12.830 | 0.570 | tINS | FR | 2 | R14C34[3][A] | gw_gao_inst_0/u_la0_top/module_next_state_2_s25/F |
13.003 | 0.174 | tNET | RR | 1 | R14C34[3][B] | gw_gao_inst_0/u_la0_top/word_ct_en_s26/I0 |
13.558 | 0.555 | tINS | RF | 3 | R14C34[3][B] | gw_gao_inst_0/u_la0_top/word_ct_en_s26/F |
14.058 | 0.500 | tNET | FF | 1 | R16C36[3][B] | gw_gao_inst_0/u_la0_top/word_ct_en_s23/I2 |
14.607 | 0.549 | tINS | FR | 16 | R16C36[3][B] | gw_gao_inst_0/u_la0_top/word_ct_en_s23/F |
15.637 | 1.029 | tNET | RR | 1 | R16C26[1][A] | gw_gao_inst_0/u_la0_top/word_count_6_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | tck_pad_i | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/I |
14.230 | 4.230 | tINS | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/O |
14.230 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
14.912 | 0.683 | tINS | RR | 631 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
17.722 | 2.810 | tNET | RR | 1 | R16C26[1][A] | gw_gao_inst_0/u_la0_top/word_count_6_s0/CLK |
17.687 | -0.035 | tSu | 1 | R16C26[1][A] | gw_gao_inst_0/u_la0_top/word_count_6_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 4.912, 63.614%; route: 2.810, 36.386% |
Arrival Data Path Delay | cell: 3.199, 40.419%; route: 4.484, 56.650%; tC2Q: 0.232, 2.931% |
Required Clock Path Delay | cell: 4.912, 63.614%; route: 2.810, 36.386% |
Path14
Path Summary:
Slack | 2.050 |
Data Arrival Time | 15.637 |
Data Required Time | 17.687 |
From | gw_gao_inst_0/u_la0_top/word_count_3_s0 |
To | gw_gao_inst_0/u_la0_top/word_count_7_s0 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | tck_pad_i:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/I |
4.230 | 4.230 | tINS | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/O |
4.230 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
4.912 | 0.683 | tINS | RR | 631 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
7.722 | 2.810 | tNET | RR | 1 | R21C39[1][A] | gw_gao_inst_0/u_la0_top/word_count_3_s0/CLK |
7.954 | 0.232 | tC2Q | RF | 3 | R21C39[1][A] | gw_gao_inst_0/u_la0_top/word_count_3_s0/Q |
8.914 | 0.960 | tNET | FF | 1 | R16C32[3][B] | gw_gao_inst_0/u_la0_top/data_to_word_counter_4_s1/I3 |
9.431 | 0.517 | tINS | FF | 9 | R16C32[3][B] | gw_gao_inst_0/u_la0_top/data_to_word_counter_4_s1/F |
10.376 | 0.945 | tNET | FF | 1 | R14C27[3][A] | gw_gao_inst_0/u_la0_top/data_to_addr_counter_9_s3/I0 |
10.829 | 0.453 | tINS | FF | 8 | R14C27[3][A] | gw_gao_inst_0/u_la0_top/data_to_addr_counter_9_s3/F |
11.303 | 0.474 | tNET | FF | 1 | R14C36[3][B] | gw_gao_inst_0/u_la0_top/module_next_state_2_s28/I1 |
11.858 | 0.555 | tINS | FF | 2 | R14C36[3][B] | gw_gao_inst_0/u_la0_top/module_next_state_2_s28/F |
12.260 | 0.401 | tNET | FF | 1 | R14C34[3][A] | gw_gao_inst_0/u_la0_top/module_next_state_2_s25/I2 |
12.830 | 0.570 | tINS | FR | 2 | R14C34[3][A] | gw_gao_inst_0/u_la0_top/module_next_state_2_s25/F |
13.003 | 0.174 | tNET | RR | 1 | R14C34[3][B] | gw_gao_inst_0/u_la0_top/word_ct_en_s26/I0 |
13.558 | 0.555 | tINS | RF | 3 | R14C34[3][B] | gw_gao_inst_0/u_la0_top/word_ct_en_s26/F |
14.058 | 0.500 | tNET | FF | 1 | R16C36[3][B] | gw_gao_inst_0/u_la0_top/word_ct_en_s23/I2 |
14.607 | 0.549 | tINS | FR | 16 | R16C36[3][B] | gw_gao_inst_0/u_la0_top/word_ct_en_s23/F |
15.637 | 1.029 | tNET | RR | 1 | R16C26[0][B] | gw_gao_inst_0/u_la0_top/word_count_7_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | tck_pad_i | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/I |
14.230 | 4.230 | tINS | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/O |
14.230 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
14.912 | 0.683 | tINS | RR | 631 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
17.722 | 2.810 | tNET | RR | 1 | R16C26[0][B] | gw_gao_inst_0/u_la0_top/word_count_7_s0/CLK |
17.687 | -0.035 | tSu | 1 | R16C26[0][B] | gw_gao_inst_0/u_la0_top/word_count_7_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 4.912, 63.614%; route: 2.810, 36.386% |
Arrival Data Path Delay | cell: 3.199, 40.419%; route: 4.484, 56.650%; tC2Q: 0.232, 2.931% |
Required Clock Path Delay | cell: 4.912, 63.614%; route: 2.810, 36.386% |
Path15
Path Summary:
Slack | 2.050 |
Data Arrival Time | 15.637 |
Data Required Time | 17.687 |
From | gw_gao_inst_0/u_la0_top/word_count_3_s0 |
To | gw_gao_inst_0/u_la0_top/word_count_13_s0 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | tck_pad_i:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/I |
4.230 | 4.230 | tINS | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/O |
4.230 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
4.912 | 0.683 | tINS | RR | 631 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
7.722 | 2.810 | tNET | RR | 1 | R21C39[1][A] | gw_gao_inst_0/u_la0_top/word_count_3_s0/CLK |
7.954 | 0.232 | tC2Q | RF | 3 | R21C39[1][A] | gw_gao_inst_0/u_la0_top/word_count_3_s0/Q |
8.914 | 0.960 | tNET | FF | 1 | R16C32[3][B] | gw_gao_inst_0/u_la0_top/data_to_word_counter_4_s1/I3 |
9.431 | 0.517 | tINS | FF | 9 | R16C32[3][B] | gw_gao_inst_0/u_la0_top/data_to_word_counter_4_s1/F |
10.376 | 0.945 | tNET | FF | 1 | R14C27[3][A] | gw_gao_inst_0/u_la0_top/data_to_addr_counter_9_s3/I0 |
10.829 | 0.453 | tINS | FF | 8 | R14C27[3][A] | gw_gao_inst_0/u_la0_top/data_to_addr_counter_9_s3/F |
11.303 | 0.474 | tNET | FF | 1 | R14C36[3][B] | gw_gao_inst_0/u_la0_top/module_next_state_2_s28/I1 |
11.858 | 0.555 | tINS | FF | 2 | R14C36[3][B] | gw_gao_inst_0/u_la0_top/module_next_state_2_s28/F |
12.260 | 0.401 | tNET | FF | 1 | R14C34[3][A] | gw_gao_inst_0/u_la0_top/module_next_state_2_s25/I2 |
12.830 | 0.570 | tINS | FR | 2 | R14C34[3][A] | gw_gao_inst_0/u_la0_top/module_next_state_2_s25/F |
13.003 | 0.174 | tNET | RR | 1 | R14C34[3][B] | gw_gao_inst_0/u_la0_top/word_ct_en_s26/I0 |
13.558 | 0.555 | tINS | RF | 3 | R14C34[3][B] | gw_gao_inst_0/u_la0_top/word_ct_en_s26/F |
14.058 | 0.500 | tNET | FF | 1 | R16C36[3][B] | gw_gao_inst_0/u_la0_top/word_ct_en_s23/I2 |
14.607 | 0.549 | tINS | FR | 16 | R16C36[3][B] | gw_gao_inst_0/u_la0_top/word_ct_en_s23/F |
15.637 | 1.029 | tNET | RR | 1 | R16C26[1][B] | gw_gao_inst_0/u_la0_top/word_count_13_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | tck_pad_i | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/I |
14.230 | 4.230 | tINS | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/O |
14.230 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
14.912 | 0.683 | tINS | RR | 631 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
17.722 | 2.810 | tNET | RR | 1 | R16C26[1][B] | gw_gao_inst_0/u_la0_top/word_count_13_s0/CLK |
17.687 | -0.035 | tSu | 1 | R16C26[1][B] | gw_gao_inst_0/u_la0_top/word_count_13_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 4.912, 63.614%; route: 2.810, 36.386% |
Arrival Data Path Delay | cell: 3.199, 40.419%; route: 4.484, 56.650%; tC2Q: 0.232, 2.931% |
Required Clock Path Delay | cell: 4.912, 63.614%; route: 2.810, 36.386% |
Path16
Path Summary:
Slack | 2.050 |
Data Arrival Time | 15.637 |
Data Required Time | 17.687 |
From | gw_gao_inst_0/u_la0_top/word_count_3_s0 |
To | gw_gao_inst_0/u_la0_top/word_count_14_s0 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | tck_pad_i:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/I |
4.230 | 4.230 | tINS | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/O |
4.230 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
4.912 | 0.683 | tINS | RR | 631 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
7.722 | 2.810 | tNET | RR | 1 | R21C39[1][A] | gw_gao_inst_0/u_la0_top/word_count_3_s0/CLK |
7.954 | 0.232 | tC2Q | RF | 3 | R21C39[1][A] | gw_gao_inst_0/u_la0_top/word_count_3_s0/Q |
8.914 | 0.960 | tNET | FF | 1 | R16C32[3][B] | gw_gao_inst_0/u_la0_top/data_to_word_counter_4_s1/I3 |
9.431 | 0.517 | tINS | FF | 9 | R16C32[3][B] | gw_gao_inst_0/u_la0_top/data_to_word_counter_4_s1/F |
10.376 | 0.945 | tNET | FF | 1 | R14C27[3][A] | gw_gao_inst_0/u_la0_top/data_to_addr_counter_9_s3/I0 |
10.829 | 0.453 | tINS | FF | 8 | R14C27[3][A] | gw_gao_inst_0/u_la0_top/data_to_addr_counter_9_s3/F |
11.303 | 0.474 | tNET | FF | 1 | R14C36[3][B] | gw_gao_inst_0/u_la0_top/module_next_state_2_s28/I1 |
11.858 | 0.555 | tINS | FF | 2 | R14C36[3][B] | gw_gao_inst_0/u_la0_top/module_next_state_2_s28/F |
12.260 | 0.401 | tNET | FF | 1 | R14C34[3][A] | gw_gao_inst_0/u_la0_top/module_next_state_2_s25/I2 |
12.830 | 0.570 | tINS | FR | 2 | R14C34[3][A] | gw_gao_inst_0/u_la0_top/module_next_state_2_s25/F |
13.003 | 0.174 | tNET | RR | 1 | R14C34[3][B] | gw_gao_inst_0/u_la0_top/word_ct_en_s26/I0 |
13.558 | 0.555 | tINS | RF | 3 | R14C34[3][B] | gw_gao_inst_0/u_la0_top/word_ct_en_s26/F |
14.058 | 0.500 | tNET | FF | 1 | R16C36[3][B] | gw_gao_inst_0/u_la0_top/word_ct_en_s23/I2 |
14.607 | 0.549 | tINS | FR | 16 | R16C36[3][B] | gw_gao_inst_0/u_la0_top/word_ct_en_s23/F |
15.637 | 1.029 | tNET | RR | 1 | R16C26[2][B] | gw_gao_inst_0/u_la0_top/word_count_14_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | tck_pad_i | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/I |
14.230 | 4.230 | tINS | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/O |
14.230 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
14.912 | 0.683 | tINS | RR | 631 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
17.722 | 2.810 | tNET | RR | 1 | R16C26[2][B] | gw_gao_inst_0/u_la0_top/word_count_14_s0/CLK |
17.687 | -0.035 | tSu | 1 | R16C26[2][B] | gw_gao_inst_0/u_la0_top/word_count_14_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 4.912, 63.614%; route: 2.810, 36.386% |
Arrival Data Path Delay | cell: 3.199, 40.419%; route: 4.484, 56.650%; tC2Q: 0.232, 2.931% |
Required Clock Path Delay | cell: 4.912, 63.614%; route: 2.810, 36.386% |
Path17
Path Summary:
Slack | 2.050 |
Data Arrival Time | 15.637 |
Data Required Time | 17.687 |
From | gw_gao_inst_0/u_la0_top/word_count_3_s0 |
To | gw_gao_inst_0/u_la0_top/word_count_15_s0 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | tck_pad_i:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/I |
4.230 | 4.230 | tINS | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/O |
4.230 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
4.912 | 0.683 | tINS | RR | 631 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
7.722 | 2.810 | tNET | RR | 1 | R21C39[1][A] | gw_gao_inst_0/u_la0_top/word_count_3_s0/CLK |
7.954 | 0.232 | tC2Q | RF | 3 | R21C39[1][A] | gw_gao_inst_0/u_la0_top/word_count_3_s0/Q |
8.914 | 0.960 | tNET | FF | 1 | R16C32[3][B] | gw_gao_inst_0/u_la0_top/data_to_word_counter_4_s1/I3 |
9.431 | 0.517 | tINS | FF | 9 | R16C32[3][B] | gw_gao_inst_0/u_la0_top/data_to_word_counter_4_s1/F |
10.376 | 0.945 | tNET | FF | 1 | R14C27[3][A] | gw_gao_inst_0/u_la0_top/data_to_addr_counter_9_s3/I0 |
10.829 | 0.453 | tINS | FF | 8 | R14C27[3][A] | gw_gao_inst_0/u_la0_top/data_to_addr_counter_9_s3/F |
11.303 | 0.474 | tNET | FF | 1 | R14C36[3][B] | gw_gao_inst_0/u_la0_top/module_next_state_2_s28/I1 |
11.858 | 0.555 | tINS | FF | 2 | R14C36[3][B] | gw_gao_inst_0/u_la0_top/module_next_state_2_s28/F |
12.260 | 0.401 | tNET | FF | 1 | R14C34[3][A] | gw_gao_inst_0/u_la0_top/module_next_state_2_s25/I2 |
12.830 | 0.570 | tINS | FR | 2 | R14C34[3][A] | gw_gao_inst_0/u_la0_top/module_next_state_2_s25/F |
13.003 | 0.174 | tNET | RR | 1 | R14C34[3][B] | gw_gao_inst_0/u_la0_top/word_ct_en_s26/I0 |
13.558 | 0.555 | tINS | RF | 3 | R14C34[3][B] | gw_gao_inst_0/u_la0_top/word_ct_en_s26/F |
14.058 | 0.500 | tNET | FF | 1 | R16C36[3][B] | gw_gao_inst_0/u_la0_top/word_ct_en_s23/I2 |
14.607 | 0.549 | tINS | FR | 16 | R16C36[3][B] | gw_gao_inst_0/u_la0_top/word_ct_en_s23/F |
15.637 | 1.029 | tNET | RR | 1 | R16C26[2][A] | gw_gao_inst_0/u_la0_top/word_count_15_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | tck_pad_i | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/I |
14.230 | 4.230 | tINS | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/O |
14.230 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
14.912 | 0.683 | tINS | RR | 631 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
17.722 | 2.810 | tNET | RR | 1 | R16C26[2][A] | gw_gao_inst_0/u_la0_top/word_count_15_s0/CLK |
17.687 | -0.035 | tSu | 1 | R16C26[2][A] | gw_gao_inst_0/u_la0_top/word_count_15_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 4.912, 63.614%; route: 2.810, 36.386% |
Arrival Data Path Delay | cell: 3.199, 40.419%; route: 4.484, 56.650%; tC2Q: 0.232, 2.931% |
Required Clock Path Delay | cell: 4.912, 63.614%; route: 2.810, 36.386% |
Path18
Path Summary:
Slack | 2.056 |
Data Arrival Time | 15.631 |
Data Required Time | 17.687 |
From | gw_gao_inst_0/u_la0_top/word_count_3_s0 |
To | gw_gao_inst_0/u_la0_top/word_count_8_s0 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | tck_pad_i:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/I |
4.230 | 4.230 | tINS | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/O |
4.230 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
4.912 | 0.683 | tINS | RR | 631 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
7.722 | 2.810 | tNET | RR | 1 | R21C39[1][A] | gw_gao_inst_0/u_la0_top/word_count_3_s0/CLK |
7.954 | 0.232 | tC2Q | RF | 3 | R21C39[1][A] | gw_gao_inst_0/u_la0_top/word_count_3_s0/Q |
8.914 | 0.960 | tNET | FF | 1 | R16C32[3][B] | gw_gao_inst_0/u_la0_top/data_to_word_counter_4_s1/I3 |
9.431 | 0.517 | tINS | FF | 9 | R16C32[3][B] | gw_gao_inst_0/u_la0_top/data_to_word_counter_4_s1/F |
10.376 | 0.945 | tNET | FF | 1 | R14C27[3][A] | gw_gao_inst_0/u_la0_top/data_to_addr_counter_9_s3/I0 |
10.829 | 0.453 | tINS | FF | 8 | R14C27[3][A] | gw_gao_inst_0/u_la0_top/data_to_addr_counter_9_s3/F |
11.303 | 0.474 | tNET | FF | 1 | R14C36[3][B] | gw_gao_inst_0/u_la0_top/module_next_state_2_s28/I1 |
11.858 | 0.555 | tINS | FF | 2 | R14C36[3][B] | gw_gao_inst_0/u_la0_top/module_next_state_2_s28/F |
12.260 | 0.401 | tNET | FF | 1 | R14C34[3][A] | gw_gao_inst_0/u_la0_top/module_next_state_2_s25/I2 |
12.830 | 0.570 | tINS | FR | 2 | R14C34[3][A] | gw_gao_inst_0/u_la0_top/module_next_state_2_s25/F |
13.003 | 0.174 | tNET | RR | 1 | R14C34[3][B] | gw_gao_inst_0/u_la0_top/word_ct_en_s26/I0 |
13.558 | 0.555 | tINS | RF | 3 | R14C34[3][B] | gw_gao_inst_0/u_la0_top/word_ct_en_s26/F |
14.058 | 0.500 | tNET | FF | 1 | R16C36[3][B] | gw_gao_inst_0/u_la0_top/word_ct_en_s23/I2 |
14.607 | 0.549 | tINS | FR | 16 | R16C36[3][B] | gw_gao_inst_0/u_la0_top/word_ct_en_s23/F |
15.631 | 1.023 | tNET | RR | 1 | R16C25[2][A] | gw_gao_inst_0/u_la0_top/word_count_8_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | tck_pad_i | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/I |
14.230 | 4.230 | tINS | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/O |
14.230 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
14.912 | 0.683 | tINS | RR | 631 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
17.722 | 2.810 | tNET | RR | 1 | R16C25[2][A] | gw_gao_inst_0/u_la0_top/word_count_8_s0/CLK |
17.687 | -0.035 | tSu | 1 | R16C25[2][A] | gw_gao_inst_0/u_la0_top/word_count_8_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 4.912, 63.614%; route: 2.810, 36.386% |
Arrival Data Path Delay | cell: 3.199, 40.449%; route: 4.478, 56.617%; tC2Q: 0.232, 2.933% |
Required Clock Path Delay | cell: 4.912, 63.614%; route: 2.810, 36.386% |
Path19
Path Summary:
Slack | 2.056 |
Data Arrival Time | 15.631 |
Data Required Time | 17.687 |
From | gw_gao_inst_0/u_la0_top/word_count_3_s0 |
To | gw_gao_inst_0/u_la0_top/word_count_10_s0 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | tck_pad_i:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/I |
4.230 | 4.230 | tINS | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/O |
4.230 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
4.912 | 0.683 | tINS | RR | 631 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
7.722 | 2.810 | tNET | RR | 1 | R21C39[1][A] | gw_gao_inst_0/u_la0_top/word_count_3_s0/CLK |
7.954 | 0.232 | tC2Q | RF | 3 | R21C39[1][A] | gw_gao_inst_0/u_la0_top/word_count_3_s0/Q |
8.914 | 0.960 | tNET | FF | 1 | R16C32[3][B] | gw_gao_inst_0/u_la0_top/data_to_word_counter_4_s1/I3 |
9.431 | 0.517 | tINS | FF | 9 | R16C32[3][B] | gw_gao_inst_0/u_la0_top/data_to_word_counter_4_s1/F |
10.376 | 0.945 | tNET | FF | 1 | R14C27[3][A] | gw_gao_inst_0/u_la0_top/data_to_addr_counter_9_s3/I0 |
10.829 | 0.453 | tINS | FF | 8 | R14C27[3][A] | gw_gao_inst_0/u_la0_top/data_to_addr_counter_9_s3/F |
11.303 | 0.474 | tNET | FF | 1 | R14C36[3][B] | gw_gao_inst_0/u_la0_top/module_next_state_2_s28/I1 |
11.858 | 0.555 | tINS | FF | 2 | R14C36[3][B] | gw_gao_inst_0/u_la0_top/module_next_state_2_s28/F |
12.260 | 0.401 | tNET | FF | 1 | R14C34[3][A] | gw_gao_inst_0/u_la0_top/module_next_state_2_s25/I2 |
12.830 | 0.570 | tINS | FR | 2 | R14C34[3][A] | gw_gao_inst_0/u_la0_top/module_next_state_2_s25/F |
13.003 | 0.174 | tNET | RR | 1 | R14C34[3][B] | gw_gao_inst_0/u_la0_top/word_ct_en_s26/I0 |
13.558 | 0.555 | tINS | RF | 3 | R14C34[3][B] | gw_gao_inst_0/u_la0_top/word_ct_en_s26/F |
14.058 | 0.500 | tNET | FF | 1 | R16C36[3][B] | gw_gao_inst_0/u_la0_top/word_ct_en_s23/I2 |
14.607 | 0.549 | tINS | FR | 16 | R16C36[3][B] | gw_gao_inst_0/u_la0_top/word_ct_en_s23/F |
15.631 | 1.023 | tNET | RR | 1 | R16C25[2][B] | gw_gao_inst_0/u_la0_top/word_count_10_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | tck_pad_i | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/I |
14.230 | 4.230 | tINS | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/O |
14.230 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
14.912 | 0.683 | tINS | RR | 631 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
17.722 | 2.810 | tNET | RR | 1 | R16C25[2][B] | gw_gao_inst_0/u_la0_top/word_count_10_s0/CLK |
17.687 | -0.035 | tSu | 1 | R16C25[2][B] | gw_gao_inst_0/u_la0_top/word_count_10_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 4.912, 63.614%; route: 2.810, 36.386% |
Arrival Data Path Delay | cell: 3.199, 40.449%; route: 4.478, 56.617%; tC2Q: 0.232, 2.933% |
Required Clock Path Delay | cell: 4.912, 63.614%; route: 2.810, 36.386% |
Path20
Path Summary:
Slack | 2.056 |
Data Arrival Time | 15.631 |
Data Required Time | 17.687 |
From | gw_gao_inst_0/u_la0_top/word_count_3_s0 |
To | gw_gao_inst_0/u_la0_top/word_count_11_s0 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | tck_pad_i:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/I |
4.230 | 4.230 | tINS | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/O |
4.230 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
4.912 | 0.683 | tINS | RR | 631 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
7.722 | 2.810 | tNET | RR | 1 | R21C39[1][A] | gw_gao_inst_0/u_la0_top/word_count_3_s0/CLK |
7.954 | 0.232 | tC2Q | RF | 3 | R21C39[1][A] | gw_gao_inst_0/u_la0_top/word_count_3_s0/Q |
8.914 | 0.960 | tNET | FF | 1 | R16C32[3][B] | gw_gao_inst_0/u_la0_top/data_to_word_counter_4_s1/I3 |
9.431 | 0.517 | tINS | FF | 9 | R16C32[3][B] | gw_gao_inst_0/u_la0_top/data_to_word_counter_4_s1/F |
10.376 | 0.945 | tNET | FF | 1 | R14C27[3][A] | gw_gao_inst_0/u_la0_top/data_to_addr_counter_9_s3/I0 |
10.829 | 0.453 | tINS | FF | 8 | R14C27[3][A] | gw_gao_inst_0/u_la0_top/data_to_addr_counter_9_s3/F |
11.303 | 0.474 | tNET | FF | 1 | R14C36[3][B] | gw_gao_inst_0/u_la0_top/module_next_state_2_s28/I1 |
11.858 | 0.555 | tINS | FF | 2 | R14C36[3][B] | gw_gao_inst_0/u_la0_top/module_next_state_2_s28/F |
12.260 | 0.401 | tNET | FF | 1 | R14C34[3][A] | gw_gao_inst_0/u_la0_top/module_next_state_2_s25/I2 |
12.830 | 0.570 | tINS | FR | 2 | R14C34[3][A] | gw_gao_inst_0/u_la0_top/module_next_state_2_s25/F |
13.003 | 0.174 | tNET | RR | 1 | R14C34[3][B] | gw_gao_inst_0/u_la0_top/word_ct_en_s26/I0 |
13.558 | 0.555 | tINS | RF | 3 | R14C34[3][B] | gw_gao_inst_0/u_la0_top/word_ct_en_s26/F |
14.058 | 0.500 | tNET | FF | 1 | R16C36[3][B] | gw_gao_inst_0/u_la0_top/word_ct_en_s23/I2 |
14.607 | 0.549 | tINS | FR | 16 | R16C36[3][B] | gw_gao_inst_0/u_la0_top/word_ct_en_s23/F |
15.631 | 1.023 | tNET | RR | 1 | R16C25[1][B] | gw_gao_inst_0/u_la0_top/word_count_11_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | tck_pad_i | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/I |
14.230 | 4.230 | tINS | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/O |
14.230 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
14.912 | 0.683 | tINS | RR | 631 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
17.722 | 2.810 | tNET | RR | 1 | R16C25[1][B] | gw_gao_inst_0/u_la0_top/word_count_11_s0/CLK |
17.687 | -0.035 | tSu | 1 | R16C25[1][B] | gw_gao_inst_0/u_la0_top/word_count_11_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 4.912, 63.614%; route: 2.810, 36.386% |
Arrival Data Path Delay | cell: 3.199, 40.449%; route: 4.478, 56.617%; tC2Q: 0.232, 2.933% |
Required Clock Path Delay | cell: 4.912, 63.614%; route: 2.810, 36.386% |
Path21
Path Summary:
Slack | 2.056 |
Data Arrival Time | 15.631 |
Data Required Time | 17.687 |
From | gw_gao_inst_0/u_la0_top/word_count_3_s0 |
To | gw_gao_inst_0/u_la0_top/word_count_12_s0 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | tck_pad_i:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/I |
4.230 | 4.230 | tINS | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/O |
4.230 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
4.912 | 0.683 | tINS | RR | 631 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
7.722 | 2.810 | tNET | RR | 1 | R21C39[1][A] | gw_gao_inst_0/u_la0_top/word_count_3_s0/CLK |
7.954 | 0.232 | tC2Q | RF | 3 | R21C39[1][A] | gw_gao_inst_0/u_la0_top/word_count_3_s0/Q |
8.914 | 0.960 | tNET | FF | 1 | R16C32[3][B] | gw_gao_inst_0/u_la0_top/data_to_word_counter_4_s1/I3 |
9.431 | 0.517 | tINS | FF | 9 | R16C32[3][B] | gw_gao_inst_0/u_la0_top/data_to_word_counter_4_s1/F |
10.376 | 0.945 | tNET | FF | 1 | R14C27[3][A] | gw_gao_inst_0/u_la0_top/data_to_addr_counter_9_s3/I0 |
10.829 | 0.453 | tINS | FF | 8 | R14C27[3][A] | gw_gao_inst_0/u_la0_top/data_to_addr_counter_9_s3/F |
11.303 | 0.474 | tNET | FF | 1 | R14C36[3][B] | gw_gao_inst_0/u_la0_top/module_next_state_2_s28/I1 |
11.858 | 0.555 | tINS | FF | 2 | R14C36[3][B] | gw_gao_inst_0/u_la0_top/module_next_state_2_s28/F |
12.260 | 0.401 | tNET | FF | 1 | R14C34[3][A] | gw_gao_inst_0/u_la0_top/module_next_state_2_s25/I2 |
12.830 | 0.570 | tINS | FR | 2 | R14C34[3][A] | gw_gao_inst_0/u_la0_top/module_next_state_2_s25/F |
13.003 | 0.174 | tNET | RR | 1 | R14C34[3][B] | gw_gao_inst_0/u_la0_top/word_ct_en_s26/I0 |
13.558 | 0.555 | tINS | RF | 3 | R14C34[3][B] | gw_gao_inst_0/u_la0_top/word_ct_en_s26/F |
14.058 | 0.500 | tNET | FF | 1 | R16C36[3][B] | gw_gao_inst_0/u_la0_top/word_ct_en_s23/I2 |
14.607 | 0.549 | tINS | FR | 16 | R16C36[3][B] | gw_gao_inst_0/u_la0_top/word_ct_en_s23/F |
15.631 | 1.023 | tNET | RR | 1 | R16C25[1][A] | gw_gao_inst_0/u_la0_top/word_count_12_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | tck_pad_i | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/I |
14.230 | 4.230 | tINS | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/O |
14.230 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
14.912 | 0.683 | tINS | RR | 631 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
17.722 | 2.810 | tNET | RR | 1 | R16C25[1][A] | gw_gao_inst_0/u_la0_top/word_count_12_s0/CLK |
17.687 | -0.035 | tSu | 1 | R16C25[1][A] | gw_gao_inst_0/u_la0_top/word_count_12_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 4.912, 63.614%; route: 2.810, 36.386% |
Arrival Data Path Delay | cell: 3.199, 40.449%; route: 4.478, 56.617%; tC2Q: 0.232, 2.933% |
Required Clock Path Delay | cell: 4.912, 63.614%; route: 2.810, 36.386% |
Path22
Path Summary:
Slack | 2.062 |
Data Arrival Time | 15.625 |
Data Required Time | 17.687 |
From | gw_gao_inst_0/u_la0_top/word_count_3_s0 |
To | gw_gao_inst_0/u_la0_top/word_count_4_s0 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | tck_pad_i:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/I |
4.230 | 4.230 | tINS | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/O |
4.230 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
4.912 | 0.683 | tINS | RR | 631 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
7.722 | 2.810 | tNET | RR | 1 | R21C39[1][A] | gw_gao_inst_0/u_la0_top/word_count_3_s0/CLK |
7.954 | 0.232 | tC2Q | RF | 3 | R21C39[1][A] | gw_gao_inst_0/u_la0_top/word_count_3_s0/Q |
8.914 | 0.960 | tNET | FF | 1 | R16C32[3][B] | gw_gao_inst_0/u_la0_top/data_to_word_counter_4_s1/I3 |
9.431 | 0.517 | tINS | FF | 9 | R16C32[3][B] | gw_gao_inst_0/u_la0_top/data_to_word_counter_4_s1/F |
10.376 | 0.945 | tNET | FF | 1 | R14C27[3][A] | gw_gao_inst_0/u_la0_top/data_to_addr_counter_9_s3/I0 |
10.829 | 0.453 | tINS | FF | 8 | R14C27[3][A] | gw_gao_inst_0/u_la0_top/data_to_addr_counter_9_s3/F |
11.303 | 0.474 | tNET | FF | 1 | R14C36[3][B] | gw_gao_inst_0/u_la0_top/module_next_state_2_s28/I1 |
11.858 | 0.555 | tINS | FF | 2 | R14C36[3][B] | gw_gao_inst_0/u_la0_top/module_next_state_2_s28/F |
12.260 | 0.401 | tNET | FF | 1 | R14C34[3][A] | gw_gao_inst_0/u_la0_top/module_next_state_2_s25/I2 |
12.830 | 0.570 | tINS | FR | 2 | R14C34[3][A] | gw_gao_inst_0/u_la0_top/module_next_state_2_s25/F |
13.003 | 0.174 | tNET | RR | 1 | R14C34[3][B] | gw_gao_inst_0/u_la0_top/word_ct_en_s26/I0 |
13.558 | 0.555 | tINS | RF | 3 | R14C34[3][B] | gw_gao_inst_0/u_la0_top/word_ct_en_s26/F |
14.058 | 0.500 | tNET | FF | 1 | R16C36[3][B] | gw_gao_inst_0/u_la0_top/word_ct_en_s23/I2 |
14.607 | 0.549 | tINS | FR | 16 | R16C36[3][B] | gw_gao_inst_0/u_la0_top/word_ct_en_s23/F |
15.625 | 1.018 | tNET | RR | 1 | R15C26[2][B] | gw_gao_inst_0/u_la0_top/word_count_4_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | tck_pad_i | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/I |
14.230 | 4.230 | tINS | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/O |
14.230 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
14.912 | 0.683 | tINS | RR | 631 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
17.722 | 2.810 | tNET | RR | 1 | R15C26[2][B] | gw_gao_inst_0/u_la0_top/word_count_4_s0/CLK |
17.687 | -0.035 | tSu | 1 | R15C26[2][B] | gw_gao_inst_0/u_la0_top/word_count_4_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 4.912, 63.614%; route: 2.810, 36.386% |
Arrival Data Path Delay | cell: 3.199, 40.479%; route: 4.472, 56.585%; tC2Q: 0.232, 2.936% |
Required Clock Path Delay | cell: 4.912, 63.614%; route: 2.810, 36.386% |
Path23
Path Summary:
Slack | 2.062 |
Data Arrival Time | 15.625 |
Data Required Time | 17.687 |
From | gw_gao_inst_0/u_la0_top/word_count_3_s0 |
To | gw_gao_inst_0/u_la0_top/word_count_5_s0 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | tck_pad_i:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/I |
4.230 | 4.230 | tINS | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/O |
4.230 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
4.912 | 0.683 | tINS | RR | 631 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
7.722 | 2.810 | tNET | RR | 1 | R21C39[1][A] | gw_gao_inst_0/u_la0_top/word_count_3_s0/CLK |
7.954 | 0.232 | tC2Q | RF | 3 | R21C39[1][A] | gw_gao_inst_0/u_la0_top/word_count_3_s0/Q |
8.914 | 0.960 | tNET | FF | 1 | R16C32[3][B] | gw_gao_inst_0/u_la0_top/data_to_word_counter_4_s1/I3 |
9.431 | 0.517 | tINS | FF | 9 | R16C32[3][B] | gw_gao_inst_0/u_la0_top/data_to_word_counter_4_s1/F |
10.376 | 0.945 | tNET | FF | 1 | R14C27[3][A] | gw_gao_inst_0/u_la0_top/data_to_addr_counter_9_s3/I0 |
10.829 | 0.453 | tINS | FF | 8 | R14C27[3][A] | gw_gao_inst_0/u_la0_top/data_to_addr_counter_9_s3/F |
11.303 | 0.474 | tNET | FF | 1 | R14C36[3][B] | gw_gao_inst_0/u_la0_top/module_next_state_2_s28/I1 |
11.858 | 0.555 | tINS | FF | 2 | R14C36[3][B] | gw_gao_inst_0/u_la0_top/module_next_state_2_s28/F |
12.260 | 0.401 | tNET | FF | 1 | R14C34[3][A] | gw_gao_inst_0/u_la0_top/module_next_state_2_s25/I2 |
12.830 | 0.570 | tINS | FR | 2 | R14C34[3][A] | gw_gao_inst_0/u_la0_top/module_next_state_2_s25/F |
13.003 | 0.174 | tNET | RR | 1 | R14C34[3][B] | gw_gao_inst_0/u_la0_top/word_ct_en_s26/I0 |
13.558 | 0.555 | tINS | RF | 3 | R14C34[3][B] | gw_gao_inst_0/u_la0_top/word_ct_en_s26/F |
14.058 | 0.500 | tNET | FF | 1 | R16C36[3][B] | gw_gao_inst_0/u_la0_top/word_ct_en_s23/I2 |
14.607 | 0.549 | tINS | FR | 16 | R16C36[3][B] | gw_gao_inst_0/u_la0_top/word_ct_en_s23/F |
15.625 | 1.018 | tNET | RR | 1 | R14C26[2][A] | gw_gao_inst_0/u_la0_top/word_count_5_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | tck_pad_i | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/I |
14.230 | 4.230 | tINS | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/O |
14.230 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
14.912 | 0.683 | tINS | RR | 631 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
17.722 | 2.810 | tNET | RR | 1 | R14C26[2][A] | gw_gao_inst_0/u_la0_top/word_count_5_s0/CLK |
17.687 | -0.035 | tSu | 1 | R14C26[2][A] | gw_gao_inst_0/u_la0_top/word_count_5_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 4.912, 63.614%; route: 2.810, 36.386% |
Arrival Data Path Delay | cell: 3.199, 40.479%; route: 4.472, 56.585%; tC2Q: 0.232, 2.936% |
Required Clock Path Delay | cell: 4.912, 63.614%; route: 2.810, 36.386% |
Path24
Path Summary:
Slack | 2.062 |
Data Arrival Time | 15.625 |
Data Required Time | 17.687 |
From | gw_gao_inst_0/u_la0_top/word_count_3_s0 |
To | gw_gao_inst_0/u_la0_top/word_count_9_s0 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | tck_pad_i:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/I |
4.230 | 4.230 | tINS | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/O |
4.230 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
4.912 | 0.683 | tINS | RR | 631 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
7.722 | 2.810 | tNET | RR | 1 | R21C39[1][A] | gw_gao_inst_0/u_la0_top/word_count_3_s0/CLK |
7.954 | 0.232 | tC2Q | RF | 3 | R21C39[1][A] | gw_gao_inst_0/u_la0_top/word_count_3_s0/Q |
8.914 | 0.960 | tNET | FF | 1 | R16C32[3][B] | gw_gao_inst_0/u_la0_top/data_to_word_counter_4_s1/I3 |
9.431 | 0.517 | tINS | FF | 9 | R16C32[3][B] | gw_gao_inst_0/u_la0_top/data_to_word_counter_4_s1/F |
10.376 | 0.945 | tNET | FF | 1 | R14C27[3][A] | gw_gao_inst_0/u_la0_top/data_to_addr_counter_9_s3/I0 |
10.829 | 0.453 | tINS | FF | 8 | R14C27[3][A] | gw_gao_inst_0/u_la0_top/data_to_addr_counter_9_s3/F |
11.303 | 0.474 | tNET | FF | 1 | R14C36[3][B] | gw_gao_inst_0/u_la0_top/module_next_state_2_s28/I1 |
11.858 | 0.555 | tINS | FF | 2 | R14C36[3][B] | gw_gao_inst_0/u_la0_top/module_next_state_2_s28/F |
12.260 | 0.401 | tNET | FF | 1 | R14C34[3][A] | gw_gao_inst_0/u_la0_top/module_next_state_2_s25/I2 |
12.830 | 0.570 | tINS | FR | 2 | R14C34[3][A] | gw_gao_inst_0/u_la0_top/module_next_state_2_s25/F |
13.003 | 0.174 | tNET | RR | 1 | R14C34[3][B] | gw_gao_inst_0/u_la0_top/word_ct_en_s26/I0 |
13.558 | 0.555 | tINS | RF | 3 | R14C34[3][B] | gw_gao_inst_0/u_la0_top/word_ct_en_s26/F |
14.058 | 0.500 | tNET | FF | 1 | R16C36[3][B] | gw_gao_inst_0/u_la0_top/word_ct_en_s23/I2 |
14.607 | 0.549 | tINS | FR | 16 | R16C36[3][B] | gw_gao_inst_0/u_la0_top/word_ct_en_s23/F |
15.625 | 1.018 | tNET | RR | 1 | R15C26[2][A] | gw_gao_inst_0/u_la0_top/word_count_9_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | tck_pad_i | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/I |
14.230 | 4.230 | tINS | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/O |
14.230 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
14.912 | 0.683 | tINS | RR | 631 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
17.722 | 2.810 | tNET | RR | 1 | R15C26[2][A] | gw_gao_inst_0/u_la0_top/word_count_9_s0/CLK |
17.687 | -0.035 | tSu | 1 | R15C26[2][A] | gw_gao_inst_0/u_la0_top/word_count_9_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 4.912, 63.614%; route: 2.810, 36.386% |
Arrival Data Path Delay | cell: 3.199, 40.479%; route: 4.472, 56.585%; tC2Q: 0.232, 2.936% |
Required Clock Path Delay | cell: 4.912, 63.614%; route: 2.810, 36.386% |
Path25
Path Summary:
Slack | 2.172 |
Data Arrival Time | 15.515 |
Data Required Time | 17.687 |
From | gw_gao_inst_0/u_la0_top/word_count_3_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_19_s1 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | tck_pad_i:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/I |
4.230 | 4.230 | tINS | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/O |
4.230 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
4.912 | 0.683 | tINS | RR | 631 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
7.722 | 2.810 | tNET | RR | 1 | R21C39[1][A] | gw_gao_inst_0/u_la0_top/word_count_3_s0/CLK |
7.954 | 0.232 | tC2Q | RF | 3 | R21C39[1][A] | gw_gao_inst_0/u_la0_top/word_count_3_s0/Q |
8.914 | 0.960 | tNET | FF | 1 | R16C32[3][B] | gw_gao_inst_0/u_la0_top/data_to_word_counter_4_s1/I3 |
9.431 | 0.517 | tINS | FF | 9 | R16C32[3][B] | gw_gao_inst_0/u_la0_top/data_to_word_counter_4_s1/F |
10.376 | 0.945 | tNET | FF | 1 | R14C27[3][A] | gw_gao_inst_0/u_la0_top/data_to_addr_counter_9_s3/I0 |
10.829 | 0.453 | tINS | FF | 8 | R14C27[3][A] | gw_gao_inst_0/u_la0_top/data_to_addr_counter_9_s3/F |
11.527 | 0.698 | tNET | FF | 1 | R15C34[3][A] | gw_gao_inst_0/u_la0_top/module_next_state_0_s24/I0 |
12.044 | 0.517 | tINS | FF | 1 | R15C34[3][A] | gw_gao_inst_0/u_la0_top/module_next_state_0_s24/F |
12.457 | 0.413 | tNET | FF | 1 | R14C35[2][B] | gw_gao_inst_0/u_la0_top/module_next_state_0_s22/I1 |
13.012 | 0.555 | tINS | FF | 7 | R14C35[2][B] | gw_gao_inst_0/u_la0_top/module_next_state_0_s22/F |
13.549 | 0.537 | tNET | FF | 1 | R15C39[2][B] | gw_gao_inst_0/u_la0_top/u_ao_crc32/n82_s3/I0 |
14.104 | 0.555 | tINS | FF | 14 | R15C39[2][B] | gw_gao_inst_0/u_la0_top/u_ao_crc32/n82_s3/F |
15.053 | 0.949 | tNET | FF | 1 | R21C36[0][A] | gw_gao_inst_0/u_la0_top/u_ao_crc32/n94_s2/I2 |
15.515 | 0.462 | tINS | FR | 1 | R21C36[0][A] | gw_gao_inst_0/u_la0_top/u_ao_crc32/n94_s2/F |
15.515 | 0.000 | tNET | RR | 1 | R21C36[0][A] | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_19_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | tck_pad_i | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/I |
14.230 | 4.230 | tINS | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/O |
14.230 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
14.912 | 0.683 | tINS | RR | 631 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
17.722 | 2.810 | tNET | RR | 1 | R21C36[0][A] | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_19_s1/CLK |
17.687 | -0.035 | tSu | 1 | R21C36[0][A] | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_19_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 4.912, 63.614%; route: 2.810, 36.386% |
Arrival Data Path Delay | cell: 3.059, 39.254%; route: 4.502, 57.768%; tC2Q: 0.232, 2.977% |
Required Clock Path Delay | cell: 4.912, 63.614%; route: 2.810, 36.386% |
Hold Analysis Report
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 0.190 |
Data Arrival Time | 1.713 |
Data Required Time | 1.523 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_9_s |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R18C19[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK |
1.713 | 0.202 | tC2Q | RR | 18 | R18C19[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q |
1.713 | 0.000 | tNET | RR | 1 | BSRAM_R28[12] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_9_s/CEA |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | BSRAM_R28[12] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_9_s/CLKA |
1.523 | 0.012 | tHld | 1 | BSRAM_R28[12] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_9_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.202, 100.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path2
Path Summary:
Slack | 0.190 |
Data Arrival Time | 1.713 |
Data Required Time | 1.523 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_8_s |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R18C19[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK |
1.713 | 0.202 | tC2Q | RR | 18 | R18C19[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q |
1.713 | 0.000 | tNET | RR | 1 | BSRAM_R28[11] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_8_s/CEA |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | BSRAM_R28[11] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_8_s/CLKA |
1.523 | 0.012 | tHld | 1 | BSRAM_R28[11] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_8_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.202, 100.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path3
Path Summary:
Slack | 0.190 |
Data Arrival Time | 1.713 |
Data Required Time | 1.523 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R18C19[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK |
1.713 | 0.202 | tC2Q | RR | 18 | R18C19[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q |
1.713 | 0.000 | tNET | RR | 1 | BSRAM_R28[10] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s/CEA |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | BSRAM_R28[10] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s/CLKA |
1.523 | 0.012 | tHld | 1 | BSRAM_R28[10] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.202, 100.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path4
Path Summary:
Slack | 0.190 |
Data Arrival Time | 1.713 |
Data Required Time | 1.523 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R18C19[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK |
1.713 | 0.202 | tC2Q | RR | 18 | R18C19[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q |
1.713 | 0.000 | tNET | RR | 1 | BSRAM_R28[8] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/CEA |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | BSRAM_R28[8] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/CLKA |
1.523 | 0.012 | tHld | 1 | BSRAM_R28[8] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.202, 100.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path5
Path Summary:
Slack | 0.190 |
Data Arrival Time | 1.713 |
Data Required Time | 1.523 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R18C19[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK |
1.713 | 0.202 | tC2Q | RR | 18 | R18C19[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q |
1.713 | 0.000 | tNET | RR | 1 | BSRAM_R10[9] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/CEA |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | BSRAM_R10[9] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/CLKA |
1.523 | 0.012 | tHld | 1 | BSRAM_R10[9] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.202, 100.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path6
Path Summary:
Slack | 0.190 |
Data Arrival Time | 1.713 |
Data Required Time | 1.523 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R18C19[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK |
1.713 | 0.202 | tC2Q | RR | 18 | R18C19[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q |
1.713 | 0.000 | tNET | RR | 1 | BSRAM_R10[8] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CEA |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | BSRAM_R10[8] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CLKA |
1.523 | 0.012 | tHld | 1 | BSRAM_R10[8] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.202, 100.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path7
Path Summary:
Slack | 0.190 |
Data Arrival Time | 1.713 |
Data Required Time | 1.523 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R18C19[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK |
1.713 | 0.202 | tC2Q | RR | 18 | R18C19[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q |
1.713 | 0.000 | tNET | RR | 1 | BSRAM_R10[7] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CEA |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | BSRAM_R10[7] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA |
1.523 | 0.012 | tHld | 1 | BSRAM_R10[7] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.202, 100.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path8
Path Summary:
Slack | 0.190 |
Data Arrival Time | 1.713 |
Data Required Time | 1.523 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R18C19[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK |
1.713 | 0.202 | tC2Q | RR | 18 | R18C19[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q |
1.713 | 0.000 | tNET | RR | 1 | BSRAM_R28[7] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CEA |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | BSRAM_R28[7] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA |
1.523 | 0.012 | tHld | 1 | BSRAM_R28[7] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.202, 100.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path9
Path Summary:
Slack | 0.190 |
Data Arrival Time | 1.713 |
Data Required Time | 1.523 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R18C19[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK |
1.713 | 0.202 | tC2Q | RR | 18 | R18C19[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q |
1.713 | 0.000 | tNET | RR | 1 | BSRAM_R28[6] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CEA |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | BSRAM_R28[6] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA |
1.523 | 0.012 | tHld | 1 | BSRAM_R28[6] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.202, 100.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path10
Path Summary:
Slack | 0.190 |
Data Arrival Time | 1.713 |
Data Required Time | 1.523 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R18C19[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK |
1.713 | 0.202 | tC2Q | RR | 18 | R18C19[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q |
1.713 | 0.000 | tNET | RR | 1 | BSRAM_R28[5] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CEA |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | BSRAM_R28[5] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA |
1.523 | 0.012 | tHld | 1 | BSRAM_R28[5] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.202, 100.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path11
Path Summary:
Slack | 0.213 |
Data Arrival Time | 1.974 |
Data Required Time | 1.760 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_53_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R25C24[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_53_s0/CLK |
1.713 | 0.202 | tC2Q | RR | 1 | R25C24[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_53_s0/Q |
1.974 | 0.260 | tNET | RR | 1 | BSRAM_R28[7] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[17] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | BSRAM_R28[7] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA |
1.760 | 0.249 | tHld | 1 | BSRAM_R28[7] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path12
Path Summary:
Slack | 0.213 |
Data Arrival Time | 1.974 |
Data Required Time | 1.760 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_52_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R25C24[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_52_s0/CLK |
1.713 | 0.202 | tC2Q | RR | 1 | R25C24[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_52_s0/Q |
1.974 | 0.260 | tNET | RR | 1 | BSRAM_R28[7] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[16] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | BSRAM_R28[7] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA |
1.760 | 0.249 | tHld | 1 | BSRAM_R28[7] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path13
Path Summary:
Slack | 0.234 |
Data Arrival Time | 1.840 |
Data Required Time | 1.606 |
From | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/oserdes_d_reg_35_s0 |
To | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[17].u_cmd_gen |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R40C2[0][A] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/oserdes_d_reg_35_s0/CLK |
1.712 | 0.201 | tC2Q | RF | 2 | R40C2[0][A] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/oserdes_d_reg_35_s0/Q |
1.840 | 0.128 | tNET | FF | 1 | IOL40[A] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[17].u_cmd_gen/D2 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | IOL40[A] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[17].u_cmd_gen/PCLK |
1.606 | 0.095 | tHld | 1 | IOL40[A] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[17].u_cmd_gen |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.128, 38.816%; tC2Q: 0.201, 61.184% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path14
Path Summary:
Slack | 0.246 |
Data Arrival Time | 1.840 |
Data Required Time | 1.594 |
From | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/oserdes_d_reg_35_s0 |
To | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[17].u_cmd_gen |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R40C2[0][A] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/oserdes_d_reg_35_s0/CLK |
1.712 | 0.201 | tC2Q | RF | 2 | R40C2[0][A] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/oserdes_d_reg_35_s0/Q |
1.840 | 0.128 | tNET | FF | 1 | IOL40[A] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[17].u_cmd_gen/D3 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | IOL40[A] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[17].u_cmd_gen/PCLK |
1.594 | 0.083 | tHld | 1 | IOL40[A] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[17].u_cmd_gen |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.128, 38.816%; tC2Q: 0.201, 61.184% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path15
Path Summary:
Slack | 0.307 |
Data Arrival Time | 6.012 |
Data Required Time | 5.705 |
From | gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0 |
To | gw_gao_inst_0/u_la0_top/capture_end_tck_1_s0 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | tck_pad_i:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/I |
3.126 | 3.126 | tINS | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/O |
3.126 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
3.802 | 0.675 | tINS | RR | 631 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
5.694 | 1.892 | tNET | RR | 1 | R15C20[0][B] | gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0/CLK |
5.895 | 0.201 | tC2Q | RF | 1 | R15C20[0][B] | gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0/Q |
6.012 | 0.117 | tNET | FF | 1 | R15C20[0][A] | gw_gao_inst_0/u_la0_top/capture_end_tck_1_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/I |
3.126 | 3.126 | tINS | RR | 1 | IOR26[A] | gw_gao_inst_0/tck_ibuf/O |
3.126 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
3.802 | 0.675 | tINS | RR | 631 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
5.694 | 1.892 | tNET | RR | 1 | R15C20[0][A] | gw_gao_inst_0/u_la0_top/capture_end_tck_1_s0/CLK |
5.705 | 0.011 | tHld | 1 | R15C20[0][A] | gw_gao_inst_0/u_la0_top/capture_end_tck_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 3.802, 66.767%; route: 1.892, 33.233% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.117, 36.787%; tC2Q: 0.201, 63.213% |
Required Clock Path Delay | cell: 3.802, 66.767%; route: 1.892, 33.233% |
Path16
Path Summary:
Slack | 0.313 |
Data Arrival Time | 1.836 |
Data Required Time | 1.523 |
From | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gwmc_rank_ctrl0/cmd1_3_s0 |
To | u_ddr3/u_gw3_phy_mc/u_gwmc_top/mc_address_dly_0_s14 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R42C21[2][A] | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gwmc_rank_ctrl0/cmd1_3_s0/CLK |
1.713 | 0.202 | tC2Q | RR | 1 | R42C21[2][A] | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gwmc_rank_ctrl0/cmd1_3_s0/Q |
1.836 | 0.123 | tNET | RR | 1 | R42C23 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/mc_address_dly_0_s14/DI[2] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R42C23 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/mc_address_dly_0_s14/CLK |
1.523 | 0.012 | tHld | 1 | R42C23 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/mc_address_dly_0_s14 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.123, 37.889%; tC2Q: 0.202, 62.111% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path17
Path Summary:
Slack | 0.334 |
Data Arrival Time | 0.583 |
Data Required Time | 0.249 |
From | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
To | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides4 |
Launch Clk | memory_clk:[R] |
Latch Clk | memory_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | memory_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | PLL_L[0] | pll/rpll_inst/CLKOUT |
0.000 | 0.000 | tNET | RR | 3 | - | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclk_dhcen/CLKIN |
0.156 | 0.156 | tINS | RR | 64 | - | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclk_dhcen/CLKOUT |
0.249 | 0.093 | tNET | RR | 5 | R56C45 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
0.583 | 0.334 | tC2Q | RR | 8 | R56C45 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2] |
0.583 | 0.000 | tNET | RR | 1 | IOB43[A] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides4/RADDR[2] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | memory_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | PLL_L[0] | pll/rpll_inst/CLKOUT |
0.000 | 0.000 | tNET | RR | 3 | - | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclk_dhcen/CLKIN |
0.156 | 0.156 | tINS | RR | 64 | - | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclk_dhcen/CLKOUT |
0.249 | 0.093 | tNET | RR | 1 | IOB43[A] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides4/FCLK |
0.249 | 0.000 | tHld | 1 | IOB43[A] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides4 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.156, 62.583%; route: 0.093, 37.417% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.334, 100.000% |
Required Clock Path Delay | cell: 0.156, 62.583%; route: 0.093, 37.417% |
Path18
Path Summary:
Slack | 0.334 |
Data Arrival Time | 0.583 |
Data Required Time | 0.249 |
From | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
To | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides4 |
Launch Clk | memory_clk:[R] |
Latch Clk | memory_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | memory_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | PLL_L[0] | pll/rpll_inst/CLKOUT |
0.000 | 0.000 | tNET | RR | 3 | - | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclk_dhcen/CLKIN |
0.156 | 0.156 | tINS | RR | 64 | - | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclk_dhcen/CLKOUT |
0.249 | 0.093 | tNET | RR | 5 | R56C45 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
0.583 | 0.334 | tC2Q | RR | 8 | R56C45 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[1] |
0.583 | 0.000 | tNET | RR | 1 | IOB43[A] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides4/RADDR[1] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | memory_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | PLL_L[0] | pll/rpll_inst/CLKOUT |
0.000 | 0.000 | tNET | RR | 3 | - | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclk_dhcen/CLKIN |
0.156 | 0.156 | tINS | RR | 64 | - | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclk_dhcen/CLKOUT |
0.249 | 0.093 | tNET | RR | 1 | IOB43[A] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides4/FCLK |
0.249 | 0.000 | tHld | 1 | IOB43[A] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides4 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.156, 62.583%; route: 0.093, 37.417% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.334, 100.000% |
Required Clock Path Delay | cell: 0.156, 62.583%; route: 0.093, 37.417% |
Path19
Path Summary:
Slack | 0.334 |
Data Arrival Time | 0.583 |
Data Required Time | 0.249 |
From | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
To | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides4 |
Launch Clk | memory_clk:[R] |
Latch Clk | memory_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | memory_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | PLL_L[0] | pll/rpll_inst/CLKOUT |
0.000 | 0.000 | tNET | RR | 3 | - | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclk_dhcen/CLKIN |
0.156 | 0.156 | tINS | RR | 64 | - | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclk_dhcen/CLKOUT |
0.249 | 0.093 | tNET | RR | 5 | R56C45 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
0.583 | 0.334 | tC2Q | RR | 8 | R56C45 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[0] |
0.583 | 0.000 | tNET | RR | 1 | IOB43[A] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides4/RADDR[0] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | memory_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | PLL_L[0] | pll/rpll_inst/CLKOUT |
0.000 | 0.000 | tNET | RR | 3 | - | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclk_dhcen/CLKIN |
0.156 | 0.156 | tINS | RR | 64 | - | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclk_dhcen/CLKOUT |
0.249 | 0.093 | tNET | RR | 1 | IOB43[A] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides4/FCLK |
0.249 | 0.000 | tHld | 1 | IOB43[A] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides4 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.156, 62.583%; route: 0.093, 37.417% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.334, 100.000% |
Required Clock Path Delay | cell: 0.156, 62.583%; route: 0.093, 37.417% |
Path20
Path Summary:
Slack | 0.334 |
Data Arrival Time | 0.583 |
Data Required Time | 0.249 |
From | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
To | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides4 |
Launch Clk | memory_clk:[R] |
Latch Clk | memory_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | memory_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | PLL_L[0] | pll/rpll_inst/CLKOUT |
0.000 | 0.000 | tNET | RR | 3 | - | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclk_dhcen/CLKIN |
0.156 | 0.156 | tINS | RR | 64 | - | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclk_dhcen/CLKOUT |
0.249 | 0.093 | tNET | RR | 5 | R56C45 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
0.583 | 0.334 | tC2Q | RR | 8 | R56C45 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2] |
0.583 | 0.000 | tNET | RR | 1 | IOB44[A] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides4/RADDR[2] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | memory_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | PLL_L[0] | pll/rpll_inst/CLKOUT |
0.000 | 0.000 | tNET | RR | 3 | - | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclk_dhcen/CLKIN |
0.156 | 0.156 | tINS | RR | 64 | - | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclk_dhcen/CLKOUT |
0.249 | 0.093 | tNET | RR | 1 | IOB44[A] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides4/FCLK |
0.249 | 0.000 | tHld | 1 | IOB44[A] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides4 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.156, 62.583%; route: 0.093, 37.417% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.334, 100.000% |
Required Clock Path Delay | cell: 0.156, 62.583%; route: 0.093, 37.417% |
Path21
Path Summary:
Slack | 0.334 |
Data Arrival Time | 0.583 |
Data Required Time | 0.249 |
From | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
To | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides4 |
Launch Clk | memory_clk:[R] |
Latch Clk | memory_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | memory_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | PLL_L[0] | pll/rpll_inst/CLKOUT |
0.000 | 0.000 | tNET | RR | 3 | - | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclk_dhcen/CLKIN |
0.156 | 0.156 | tINS | RR | 64 | - | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclk_dhcen/CLKOUT |
0.249 | 0.093 | tNET | RR | 5 | R56C45 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
0.583 | 0.334 | tC2Q | RR | 8 | R56C45 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[1] |
0.583 | 0.000 | tNET | RR | 1 | IOB44[A] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides4/RADDR[1] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | memory_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | PLL_L[0] | pll/rpll_inst/CLKOUT |
0.000 | 0.000 | tNET | RR | 3 | - | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclk_dhcen/CLKIN |
0.156 | 0.156 | tINS | RR | 64 | - | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclk_dhcen/CLKOUT |
0.249 | 0.093 | tNET | RR | 1 | IOB44[A] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides4/FCLK |
0.249 | 0.000 | tHld | 1 | IOB44[A] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides4 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.156, 62.583%; route: 0.093, 37.417% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.334, 100.000% |
Required Clock Path Delay | cell: 0.156, 62.583%; route: 0.093, 37.417% |
Path22
Path Summary:
Slack | 0.334 |
Data Arrival Time | 0.583 |
Data Required Time | 0.249 |
From | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
To | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides4 |
Launch Clk | memory_clk:[R] |
Latch Clk | memory_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | memory_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | PLL_L[0] | pll/rpll_inst/CLKOUT |
0.000 | 0.000 | tNET | RR | 3 | - | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclk_dhcen/CLKIN |
0.156 | 0.156 | tINS | RR | 64 | - | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclk_dhcen/CLKOUT |
0.249 | 0.093 | tNET | RR | 5 | R56C45 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
0.583 | 0.334 | tC2Q | RR | 8 | R56C45 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[0] |
0.583 | 0.000 | tNET | RR | 1 | IOB44[A] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides4/RADDR[0] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | memory_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | PLL_L[0] | pll/rpll_inst/CLKOUT |
0.000 | 0.000 | tNET | RR | 3 | - | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclk_dhcen/CLKIN |
0.156 | 0.156 | tINS | RR | 64 | - | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclk_dhcen/CLKOUT |
0.249 | 0.093 | tNET | RR | 1 | IOB44[A] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides4/FCLK |
0.249 | 0.000 | tHld | 1 | IOB44[A] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides4 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.156, 62.583%; route: 0.093, 37.417% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.334, 100.000% |
Required Clock Path Delay | cell: 0.156, 62.583%; route: 0.093, 37.417% |
Path23
Path Summary:
Slack | 0.334 |
Data Arrival Time | 0.583 |
Data Required Time | 0.249 |
From | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
To | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides4 |
Launch Clk | memory_clk:[R] |
Latch Clk | memory_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | memory_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | PLL_L[0] | pll/rpll_inst/CLKOUT |
0.000 | 0.000 | tNET | RR | 3 | - | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclk_dhcen/CLKIN |
0.156 | 0.156 | tINS | RR | 64 | - | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclk_dhcen/CLKOUT |
0.249 | 0.093 | tNET | RR | 5 | R56C45 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
0.583 | 0.334 | tC2Q | RR | 8 | R56C45 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2] |
0.583 | 0.000 | tNET | RR | 1 | IOB32[A] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides4/RADDR[2] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | memory_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | PLL_L[0] | pll/rpll_inst/CLKOUT |
0.000 | 0.000 | tNET | RR | 3 | - | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclk_dhcen/CLKIN |
0.156 | 0.156 | tINS | RR | 64 | - | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclk_dhcen/CLKOUT |
0.249 | 0.093 | tNET | RR | 1 | IOB32[A] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides4/FCLK |
0.249 | 0.000 | tHld | 1 | IOB32[A] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides4 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.156, 62.583%; route: 0.093, 37.417% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.334, 100.000% |
Required Clock Path Delay | cell: 0.156, 62.583%; route: 0.093, 37.417% |
Path24
Path Summary:
Slack | 0.334 |
Data Arrival Time | 0.583 |
Data Required Time | 0.249 |
From | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
To | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides4 |
Launch Clk | memory_clk:[R] |
Latch Clk | memory_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | memory_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | PLL_L[0] | pll/rpll_inst/CLKOUT |
0.000 | 0.000 | tNET | RR | 3 | - | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclk_dhcen/CLKIN |
0.156 | 0.156 | tINS | RR | 64 | - | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclk_dhcen/CLKOUT |
0.249 | 0.093 | tNET | RR | 5 | R56C45 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
0.583 | 0.334 | tC2Q | RR | 8 | R56C45 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[1] |
0.583 | 0.000 | tNET | RR | 1 | IOB32[A] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides4/RADDR[1] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | memory_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | PLL_L[0] | pll/rpll_inst/CLKOUT |
0.000 | 0.000 | tNET | RR | 3 | - | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclk_dhcen/CLKIN |
0.156 | 0.156 | tINS | RR | 64 | - | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclk_dhcen/CLKOUT |
0.249 | 0.093 | tNET | RR | 1 | IOB32[A] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides4/FCLK |
0.249 | 0.000 | tHld | 1 | IOB32[A] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides4 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.156, 62.583%; route: 0.093, 37.417% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.334, 100.000% |
Required Clock Path Delay | cell: 0.156, 62.583%; route: 0.093, 37.417% |
Path25
Path Summary:
Slack | 0.334 |
Data Arrival Time | 0.583 |
Data Required Time | 0.249 |
From | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
To | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides4 |
Launch Clk | memory_clk:[R] |
Latch Clk | memory_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | memory_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | PLL_L[0] | pll/rpll_inst/CLKOUT |
0.000 | 0.000 | tNET | RR | 3 | - | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclk_dhcen/CLKIN |
0.156 | 0.156 | tINS | RR | 64 | - | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclk_dhcen/CLKOUT |
0.249 | 0.093 | tNET | RR | 5 | R56C45 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
0.583 | 0.334 | tC2Q | RR | 8 | R56C45 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[0] |
0.583 | 0.000 | tNET | RR | 1 | IOB32[A] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides4/RADDR[0] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | memory_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | PLL_L[0] | pll/rpll_inst/CLKOUT |
0.000 | 0.000 | tNET | RR | 3 | - | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclk_dhcen/CLKIN |
0.156 | 0.156 | tINS | RR | 64 | - | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclk_dhcen/CLKOUT |
0.249 | 0.093 | tNET | RR | 1 | IOB32[A] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides4/FCLK |
0.249 | 0.000 | tHld | 1 | IOB32[A] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides4 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.156, 62.583%; route: 0.093, 37.417% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.334, 100.000% |
Required Clock Path Delay | cell: 0.156, 62.583%; route: 0.093, 37.417% |
Recovery Analysis Report
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 2.644 |
Data Arrival Time | 9.592 |
Data Required Time | 12.236 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0 |
Launch Clk | clk_x1:[F] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk_x1 | ||||
5.000 | 0.000 | tCL | FF | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
7.274 | 2.274 | tNET | FF | 1 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
7.506 | 0.232 | tC2Q | FF | 60 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
9.592 | 2.086 | tNET | FF | 1 | R25C38[0][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk_x1 | ||||
10.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
12.271 | 2.271 | tNET | RR | 1 | R25C38[0][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLK |
12.236 | -0.035 | tSu | 1 | R25C38[0][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0 |
Path Statistics:
Clock Skew | -0.003 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.274, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.086, 89.991%; tC2Q: 0.232, 10.009% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path2
Path Summary:
Slack | 2.644 |
Data Arrival Time | 9.592 |
Data Required Time | 12.236 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_2_s0 |
Launch Clk | clk_x1:[F] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk_x1 | ||||
5.000 | 0.000 | tCL | FF | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
7.274 | 2.274 | tNET | FF | 1 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
7.506 | 0.232 | tC2Q | FF | 60 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
9.592 | 2.086 | tNET | FF | 1 | R25C38[1][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_2_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk_x1 | ||||
10.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
12.271 | 2.271 | tNET | RR | 1 | R25C38[1][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_2_s0/CLK |
12.236 | -0.035 | tSu | 1 | R25C38[1][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_2_s0 |
Path Statistics:
Clock Skew | -0.003 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.274, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.086, 89.991%; tC2Q: 0.232, 10.009% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path3
Path Summary:
Slack | 2.644 |
Data Arrival Time | 9.592 |
Data Required Time | 12.236 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_0_s0 |
Launch Clk | clk_x1:[F] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk_x1 | ||||
5.000 | 0.000 | tCL | FF | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
7.274 | 2.274 | tNET | FF | 1 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
7.506 | 0.232 | tC2Q | FF | 60 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
9.592 | 2.086 | tNET | FF | 1 | R25C38[2][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk_x1 | ||||
10.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
12.271 | 2.271 | tNET | RR | 1 | R25C38[2][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_0_s0/CLK |
12.236 | -0.035 | tSu | 1 | R25C38[2][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_0_s0 |
Path Statistics:
Clock Skew | -0.003 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.274, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.086, 89.991%; tC2Q: 0.232, 10.009% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path4
Path Summary:
Slack | 2.898 |
Data Arrival Time | 9.338 |
Data Required Time | 12.236 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0 |
Launch Clk | clk_x1:[F] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk_x1 | ||||
5.000 | 0.000 | tCL | FF | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
7.274 | 2.274 | tNET | FF | 1 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
7.506 | 0.232 | tC2Q | FF | 60 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
9.338 | 1.832 | tNET | FF | 1 | R24C38[2][B] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk_x1 | ||||
10.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
12.271 | 2.271 | tNET | RR | 1 | R24C38[2][B] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLK |
12.236 | -0.035 | tSu | 1 | R24C38[2][B] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0 |
Path Statistics:
Clock Skew | -0.003 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.274, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.832, 88.759%; tC2Q: 0.232, 11.241% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path5
Path Summary:
Slack | 2.898 |
Data Arrival Time | 9.338 |
Data Required Time | 12.236 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0 |
Launch Clk | clk_x1:[F] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk_x1 | ||||
5.000 | 0.000 | tCL | FF | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
7.274 | 2.274 | tNET | FF | 1 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
7.506 | 0.232 | tC2Q | FF | 60 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
9.338 | 1.832 | tNET | FF | 1 | R24C38[2][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk_x1 | ||||
10.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
12.271 | 2.271 | tNET | RR | 1 | R24C38[2][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0/CLK |
12.236 | -0.035 | tSu | 1 | R24C38[2][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0 |
Path Statistics:
Clock Skew | -0.003 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.274, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.832, 88.759%; tC2Q: 0.232, 11.241% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path6
Path Summary:
Slack | 2.904 |
Data Arrival Time | 9.332 |
Data Required Time | 12.236 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_1_s0 |
Launch Clk | clk_x1:[F] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk_x1 | ||||
5.000 | 0.000 | tCL | FF | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
7.274 | 2.274 | tNET | FF | 1 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
7.506 | 0.232 | tC2Q | FF | 60 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
9.332 | 1.826 | tNET | FF | 1 | R23C38[2][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk_x1 | ||||
10.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
12.271 | 2.271 | tNET | RR | 1 | R23C38[2][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_1_s0/CLK |
12.236 | -0.035 | tSu | 1 | R23C38[2][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_1_s0 |
Path Statistics:
Clock Skew | -0.003 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.274, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.826, 88.728%; tC2Q: 0.232, 11.272% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path7
Path Summary:
Slack | 3.147 |
Data Arrival Time | 9.090 |
Data Required Time | 12.236 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_2_s0 |
Launch Clk | clk_x1:[F] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk_x1 | ||||
5.000 | 0.000 | tCL | FF | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
7.274 | 2.274 | tNET | FF | 1 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
7.506 | 0.232 | tC2Q | FF | 60 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
9.090 | 1.583 | tNET | FF | 1 | R22C38[0][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_2_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk_x1 | ||||
10.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
12.271 | 2.271 | tNET | RR | 1 | R22C38[0][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_2_s0/CLK |
12.236 | -0.035 | tSu | 1 | R22C38[0][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_2_s0 |
Path Statistics:
Clock Skew | -0.003 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.274, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.583, 87.220%; tC2Q: 0.232, 12.780% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path8
Path Summary:
Slack | 3.152 |
Data Arrival Time | 9.084 |
Data Required Time | 12.236 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0 |
Launch Clk | clk_x1:[F] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk_x1 | ||||
5.000 | 0.000 | tCL | FF | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
7.274 | 2.274 | tNET | FF | 1 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
7.506 | 0.232 | tC2Q | FF | 60 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
9.084 | 1.578 | tNET | FF | 1 | R24C37[2][B] | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk_x1 | ||||
10.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
12.271 | 2.271 | tNET | RR | 1 | R24C37[2][B] | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLK |
12.236 | -0.035 | tSu | 1 | R24C37[2][B] | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0 |
Path Statistics:
Clock Skew | -0.003 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.274, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.578, 87.180%; tC2Q: 0.232, 12.820% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path9
Path Summary:
Slack | 3.180 |
Data Arrival Time | 9.057 |
Data Required Time | 12.236 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_1_s0 |
Launch Clk | clk_x1:[F] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk_x1 | ||||
5.000 | 0.000 | tCL | FF | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
7.274 | 2.274 | tNET | FF | 1 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
7.506 | 0.232 | tC2Q | FF | 60 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
9.057 | 1.550 | tNET | FF | 1 | R23C30[2][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk_x1 | ||||
10.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
12.271 | 2.271 | tNET | RR | 1 | R23C30[2][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_1_s0/CLK |
12.236 | -0.035 | tSu | 1 | R23C30[2][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_1_s0 |
Path Statistics:
Clock Skew | -0.003 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.274, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.550, 86.983%; tC2Q: 0.232, 13.017% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path10
Path Summary:
Slack | 3.422 |
Data Arrival Time | 8.814 |
Data Required Time | 12.236 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_2_s0 |
Launch Clk | clk_x1:[F] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk_x1 | ||||
5.000 | 0.000 | tCL | FF | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
7.274 | 2.274 | tNET | FF | 1 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
7.506 | 0.232 | tC2Q | FF | 60 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
8.814 | 1.308 | tNET | FF | 1 | R22C30[0][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_2_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk_x1 | ||||
10.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
12.271 | 2.271 | tNET | RR | 1 | R22C30[0][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_2_s0/CLK |
12.236 | -0.035 | tSu | 1 | R22C30[0][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_2_s0 |
Path Statistics:
Clock Skew | -0.003 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.274, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.308, 84.931%; tC2Q: 0.232, 15.069% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path11
Path Summary:
Slack | 3.519 |
Data Arrival Time | 8.717 |
Data Required Time | 12.236 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1 |
Launch Clk | clk_x1:[F] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk_x1 | ||||
5.000 | 0.000 | tCL | FF | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
7.274 | 2.274 | tNET | FF | 1 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
7.506 | 0.232 | tC2Q | FF | 60 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
8.717 | 1.211 | tNET | FF | 1 | R25C18[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk_x1 | ||||
10.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
12.271 | 2.271 | tNET | RR | 1 | R25C18[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK |
12.236 | -0.035 | tSu | 1 | R25C18[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1 |
Path Statistics:
Clock Skew | -0.003 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.274, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.211, 83.918%; tC2Q: 0.232, 16.082% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path12
Path Summary:
Slack | 3.519 |
Data Arrival Time | 8.717 |
Data Required Time | 12.236 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1 |
Launch Clk | clk_x1:[F] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk_x1 | ||||
5.000 | 0.000 | tCL | FF | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
7.274 | 2.274 | tNET | FF | 1 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
7.506 | 0.232 | tC2Q | FF | 60 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
8.717 | 1.211 | tNET | FF | 1 | R25C18[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk_x1 | ||||
10.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
12.271 | 2.271 | tNET | RR | 1 | R25C18[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK |
12.236 | -0.035 | tSu | 1 | R25C18[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1 |
Path Statistics:
Clock Skew | -0.003 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.274, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.211, 83.918%; tC2Q: 0.232, 16.082% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path13
Path Summary:
Slack | 3.519 |
Data Arrival Time | 8.717 |
Data Required Time | 12.236 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1 |
Launch Clk | clk_x1:[F] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk_x1 | ||||
5.000 | 0.000 | tCL | FF | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
7.274 | 2.274 | tNET | FF | 1 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
7.506 | 0.232 | tC2Q | FF | 60 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
8.717 | 1.211 | tNET | FF | 1 | R25C18[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk_x1 | ||||
10.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
12.271 | 2.271 | tNET | RR | 1 | R25C18[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK |
12.236 | -0.035 | tSu | 1 | R25C18[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1 |
Path Statistics:
Clock Skew | -0.003 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.274, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.211, 83.918%; tC2Q: 0.232, 16.082% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path14
Path Summary:
Slack | 3.519 |
Data Arrival Time | 8.717 |
Data Required Time | 12.236 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1 |
Launch Clk | clk_x1:[F] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk_x1 | ||||
5.000 | 0.000 | tCL | FF | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
7.274 | 2.274 | tNET | FF | 1 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
7.506 | 0.232 | tC2Q | FF | 60 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
8.717 | 1.211 | tNET | FF | 1 | R22C19[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk_x1 | ||||
10.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
12.271 | 2.271 | tNET | RR | 1 | R22C19[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK |
12.236 | -0.035 | tSu | 1 | R22C19[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1 |
Path Statistics:
Clock Skew | -0.003 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.274, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.211, 83.918%; tC2Q: 0.232, 16.082% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path15
Path Summary:
Slack | 3.519 |
Data Arrival Time | 8.717 |
Data Required Time | 12.236 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1 |
Launch Clk | clk_x1:[F] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk_x1 | ||||
5.000 | 0.000 | tCL | FF | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
7.274 | 2.274 | tNET | FF | 1 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
7.506 | 0.232 | tC2Q | FF | 60 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
8.717 | 1.211 | tNET | FF | 1 | R22C19[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk_x1 | ||||
10.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
12.271 | 2.271 | tNET | RR | 1 | R22C19[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK |
12.236 | -0.035 | tSu | 1 | R22C19[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1 |
Path Statistics:
Clock Skew | -0.003 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.274, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.211, 83.918%; tC2Q: 0.232, 16.082% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path16
Path Summary:
Slack | 3.519 |
Data Arrival Time | 8.717 |
Data Required Time | 12.236 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1 |
Launch Clk | clk_x1:[F] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk_x1 | ||||
5.000 | 0.000 | tCL | FF | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
7.274 | 2.274 | tNET | FF | 1 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
7.506 | 0.232 | tC2Q | FF | 60 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
8.717 | 1.211 | tNET | FF | 1 | R22C18[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk_x1 | ||||
10.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
12.271 | 2.271 | tNET | RR | 1 | R22C18[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK |
12.236 | -0.035 | tSu | 1 | R22C18[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1 |
Path Statistics:
Clock Skew | -0.003 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.274, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.211, 83.918%; tC2Q: 0.232, 16.082% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path17
Path Summary:
Slack | 3.519 |
Data Arrival Time | 8.717 |
Data Required Time | 12.236 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1 |
Launch Clk | clk_x1:[F] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk_x1 | ||||
5.000 | 0.000 | tCL | FF | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
7.274 | 2.274 | tNET | FF | 1 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
7.506 | 0.232 | tC2Q | FF | 60 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
8.717 | 1.211 | tNET | FF | 1 | R22C18[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk_x1 | ||||
10.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
12.271 | 2.271 | tNET | RR | 1 | R22C18[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK |
12.236 | -0.035 | tSu | 1 | R22C18[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1 |
Path Statistics:
Clock Skew | -0.003 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.274, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.211, 83.918%; tC2Q: 0.232, 16.082% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path18
Path Summary:
Slack | 3.519 |
Data Arrival Time | 8.717 |
Data Required Time | 12.236 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1 |
Launch Clk | clk_x1:[F] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk_x1 | ||||
5.000 | 0.000 | tCL | FF | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
7.274 | 2.274 | tNET | FF | 1 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
7.506 | 0.232 | tC2Q | FF | 60 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
8.717 | 1.211 | tNET | FF | 1 | R22C18[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk_x1 | ||||
10.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
12.271 | 2.271 | tNET | RR | 1 | R22C18[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK |
12.236 | -0.035 | tSu | 1 | R22C18[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1 |
Path Statistics:
Clock Skew | -0.003 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.274, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.211, 83.918%; tC2Q: 0.232, 16.082% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path19
Path Summary:
Slack | 3.519 |
Data Arrival Time | 8.717 |
Data Required Time | 12.236 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1 |
Launch Clk | clk_x1:[F] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk_x1 | ||||
5.000 | 0.000 | tCL | FF | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
7.274 | 2.274 | tNET | FF | 1 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
7.506 | 0.232 | tC2Q | FF | 60 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
8.717 | 1.211 | tNET | FF | 1 | R20C19[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk_x1 | ||||
10.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
12.271 | 2.271 | tNET | RR | 1 | R20C19[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLK |
12.236 | -0.035 | tSu | 1 | R20C19[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1 |
Path Statistics:
Clock Skew | -0.003 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.274, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.211, 83.918%; tC2Q: 0.232, 16.082% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path20
Path Summary:
Slack | 3.519 |
Data Arrival Time | 8.717 |
Data Required Time | 12.236 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1 |
Launch Clk | clk_x1:[F] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk_x1 | ||||
5.000 | 0.000 | tCL | FF | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
7.274 | 2.274 | tNET | FF | 1 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
7.506 | 0.232 | tC2Q | FF | 60 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
8.717 | 1.211 | tNET | FF | 1 | R20C19[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk_x1 | ||||
10.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
12.271 | 2.271 | tNET | RR | 1 | R20C19[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLK |
12.236 | -0.035 | tSu | 1 | R20C19[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1 |
Path Statistics:
Clock Skew | -0.003 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.274, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.211, 83.918%; tC2Q: 0.232, 16.082% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path21
Path Summary:
Slack | 3.519 |
Data Arrival Time | 8.717 |
Data Required Time | 12.236 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1 |
Launch Clk | clk_x1:[F] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk_x1 | ||||
5.000 | 0.000 | tCL | FF | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
7.274 | 2.274 | tNET | FF | 1 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
7.506 | 0.232 | tC2Q | FF | 60 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
8.717 | 1.211 | tNET | FF | 1 | R20C19[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk_x1 | ||||
10.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
12.271 | 2.271 | tNET | RR | 1 | R20C19[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLK |
12.236 | -0.035 | tSu | 1 | R20C19[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1 |
Path Statistics:
Clock Skew | -0.003 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.274, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.211, 83.918%; tC2Q: 0.232, 16.082% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path22
Path Summary:
Slack | 3.519 |
Data Arrival Time | 8.717 |
Data Required Time | 12.236 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1 |
Launch Clk | clk_x1:[F] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk_x1 | ||||
5.000 | 0.000 | tCL | FF | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
7.274 | 2.274 | tNET | FF | 1 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
7.506 | 0.232 | tC2Q | FF | 60 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
8.717 | 1.211 | tNET | FF | 1 | R20C18[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk_x1 | ||||
10.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
12.271 | 2.271 | tNET | RR | 1 | R20C18[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLK |
12.236 | -0.035 | tSu | 1 | R20C18[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1 |
Path Statistics:
Clock Skew | -0.003 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.274, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.211, 83.918%; tC2Q: 0.232, 16.082% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path23
Path Summary:
Slack | 3.519 |
Data Arrival Time | 8.717 |
Data Required Time | 12.236 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1 |
Launch Clk | clk_x1:[F] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk_x1 | ||||
5.000 | 0.000 | tCL | FF | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
7.274 | 2.274 | tNET | FF | 1 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
7.506 | 0.232 | tC2Q | FF | 60 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
8.717 | 1.211 | tNET | FF | 1 | R20C18[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk_x1 | ||||
10.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
12.271 | 2.271 | tNET | RR | 1 | R20C18[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLK |
12.236 | -0.035 | tSu | 1 | R20C18[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1 |
Path Statistics:
Clock Skew | -0.003 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.274, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.211, 83.918%; tC2Q: 0.232, 16.082% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path24
Path Summary:
Slack | 3.519 |
Data Arrival Time | 8.717 |
Data Required Time | 12.236 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1 |
Launch Clk | clk_x1:[F] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk_x1 | ||||
5.000 | 0.000 | tCL | FF | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
7.274 | 2.274 | tNET | FF | 1 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
7.506 | 0.232 | tC2Q | FF | 60 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
8.717 | 1.211 | tNET | FF | 1 | R20C18[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk_x1 | ||||
10.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
12.271 | 2.271 | tNET | RR | 1 | R20C18[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLK |
12.236 | -0.035 | tSu | 1 | R20C18[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1 |
Path Statistics:
Clock Skew | -0.003 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.274, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.211, 83.918%; tC2Q: 0.232, 16.082% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path25
Path Summary:
Slack | 3.519 |
Data Arrival Time | 8.717 |
Data Required Time | 12.236 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1 |
Launch Clk | clk_x1:[F] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk_x1 | ||||
5.000 | 0.000 | tCL | FF | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
7.274 | 2.274 | tNET | FF | 1 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
7.506 | 0.232 | tC2Q | FF | 60 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
8.717 | 1.211 | tNET | FF | 1 | R20C18[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk_x1 | ||||
10.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
12.271 | 2.271 | tNET | RR | 1 | R20C18[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLK |
12.236 | -0.035 | tSu | 1 | R20C18[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1 |
Path Statistics:
Clock Skew | -0.003 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.274, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.211, 83.918%; tC2Q: 0.232, 16.082% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Removal Analysis Report
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 5.448 |
Data Arrival Time | 6.970 |
Data Required Time | 1.522 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3 |
Launch Clk | clk_x1:[F] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk_x1 | ||||
5.000 | 0.000 | tCL | FF | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
6.514 | 1.514 | tNET | FF | 1 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.716 | 0.202 | tC2Q | FR | 60 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.970 | 0.255 | tNET | RR | 1 | R14C23[2][B] | gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R14C23[2][B] | gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLK |
1.522 | 0.011 | tHld | 1 | R14C23[2][B] | gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3 |
Path Statistics:
Clock Skew | -0.002 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.514, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.255, 55.763%; tC2Q: 0.202, 44.237% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path2
Path Summary:
Slack | 5.448 |
Data Arrival Time | 6.970 |
Data Required Time | 1.522 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1 |
Launch Clk | clk_x1:[F] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk_x1 | ||||
5.000 | 0.000 | tCL | FF | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
6.514 | 1.514 | tNET | FF | 1 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.716 | 0.202 | tC2Q | FR | 60 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.970 | 0.255 | tNET | RR | 1 | R16C21[0][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R16C21[0][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLK |
1.522 | 0.011 | tHld | 1 | R16C21[0][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1 |
Path Statistics:
Clock Skew | -0.002 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.514, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.255, 55.763%; tC2Q: 0.202, 44.237% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path3
Path Summary:
Slack | 5.448 |
Data Arrival Time | 6.970 |
Data Required Time | 1.522 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1 |
Launch Clk | clk_x1:[F] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk_x1 | ||||
5.000 | 0.000 | tCL | FF | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
6.514 | 1.514 | tNET | FF | 1 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.716 | 0.202 | tC2Q | FR | 60 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.970 | 0.255 | tNET | RR | 1 | R16C21[0][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R16C21[0][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLK |
1.522 | 0.011 | tHld | 1 | R16C21[0][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1 |
Path Statistics:
Clock Skew | -0.002 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.514, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.255, 55.763%; tC2Q: 0.202, 44.237% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path4
Path Summary:
Slack | 5.448 |
Data Arrival Time | 6.970 |
Data Required Time | 1.522 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/triger_s0 |
Launch Clk | clk_x1:[F] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk_x1 | ||||
5.000 | 0.000 | tCL | FF | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
6.514 | 1.514 | tNET | FF | 1 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.716 | 0.202 | tC2Q | FR | 60 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.970 | 0.255 | tNET | RR | 1 | R15C23[2][A] | gw_gao_inst_0/u_la0_top/triger_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R15C23[2][A] | gw_gao_inst_0/u_la0_top/triger_s0/CLK |
1.522 | 0.011 | tHld | 1 | R15C23[2][A] | gw_gao_inst_0/u_la0_top/triger_s0 |
Path Statistics:
Clock Skew | -0.002 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.514, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.255, 55.763%; tC2Q: 0.202, 44.237% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path5
Path Summary:
Slack | 5.448 |
Data Arrival Time | 6.970 |
Data Required Time | 1.522 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0 |
Launch Clk | clk_x1:[F] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk_x1 | ||||
5.000 | 0.000 | tCL | FF | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
6.514 | 1.514 | tNET | FF | 1 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.716 | 0.202 | tC2Q | FR | 60 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.970 | 0.255 | tNET | RR | 1 | R14C23[2][A] | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R14C23[2][A] | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLK |
1.522 | 0.011 | tHld | 1 | R14C23[2][A] | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0 |
Path Statistics:
Clock Skew | -0.002 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.514, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.255, 55.763%; tC2Q: 0.202, 44.237% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path6
Path Summary:
Slack | 5.573 |
Data Arrival Time | 7.095 |
Data Required Time | 1.522 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1 |
Launch Clk | clk_x1:[F] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk_x1 | ||||
5.000 | 0.000 | tCL | FF | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
6.514 | 1.514 | tNET | FF | 1 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.716 | 0.202 | tC2Q | FR | 60 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
7.095 | 0.380 | tNET | RR | 1 | R15C21[2][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R15C21[2][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLK |
1.522 | 0.011 | tHld | 1 | R15C21[2][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1 |
Path Statistics:
Clock Skew | -0.002 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.514, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.380, 65.270%; tC2Q: 0.202, 34.730% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path7
Path Summary:
Slack | 5.573 |
Data Arrival Time | 7.095 |
Data Required Time | 1.522 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1 |
Launch Clk | clk_x1:[F] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk_x1 | ||||
5.000 | 0.000 | tCL | FF | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
6.514 | 1.514 | tNET | FF | 1 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.716 | 0.202 | tC2Q | FR | 60 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
7.095 | 0.380 | tNET | RR | 1 | R16C19[2][B] | gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R16C19[2][B] | gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLK |
1.522 | 0.011 | tHld | 1 | R16C19[2][B] | gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1 |
Path Statistics:
Clock Skew | -0.002 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.514, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.380, 65.270%; tC2Q: 0.202, 34.730% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path8
Path Summary:
Slack | 5.575 |
Data Arrival Time | 7.097 |
Data Required Time | 1.522 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/start_reg_s0 |
Launch Clk | clk_x1:[F] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk_x1 | ||||
5.000 | 0.000 | tCL | FF | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
6.514 | 1.514 | tNET | FF | 1 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.716 | 0.202 | tC2Q | FR | 60 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
7.097 | 0.382 | tNET | RR | 1 | R16C20[0][A] | gw_gao_inst_0/u_la0_top/start_reg_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R16C20[0][A] | gw_gao_inst_0/u_la0_top/start_reg_s0/CLK |
1.522 | 0.011 | tHld | 1 | R16C20[0][A] | gw_gao_inst_0/u_la0_top/start_reg_s0 |
Path Statistics:
Clock Skew | -0.002 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.514, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.382, 65.388%; tC2Q: 0.202, 34.612% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path9
Path Summary:
Slack | 5.575 |
Data Arrival Time | 7.097 |
Data Required Time | 1.522 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0 |
Launch Clk | clk_x1:[F] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk_x1 | ||||
5.000 | 0.000 | tCL | FF | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
6.514 | 1.514 | tNET | FF | 1 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.716 | 0.202 | tC2Q | FR | 60 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
7.097 | 0.382 | tNET | RR | 1 | R16C20[1][A] | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R16C20[1][A] | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLK |
1.522 | 0.011 | tHld | 1 | R16C20[1][A] | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0 |
Path Statistics:
Clock Skew | -0.002 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.514, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.382, 65.388%; tC2Q: 0.202, 34.612% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path10
Path Summary:
Slack | 5.575 |
Data Arrival Time | 7.097 |
Data Required Time | 1.522 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0 |
Launch Clk | clk_x1:[F] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk_x1 | ||||
5.000 | 0.000 | tCL | FF | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
6.514 | 1.514 | tNET | FF | 1 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.716 | 0.202 | tC2Q | FR | 60 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
7.097 | 0.382 | tNET | RR | 1 | R16C20[1][B] | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R16C20[1][B] | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLK |
1.522 | 0.011 | tHld | 1 | R16C20[1][B] | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0 |
Path Statistics:
Clock Skew | -0.002 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.514, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.382, 65.388%; tC2Q: 0.202, 34.612% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path11
Path Summary:
Slack | 5.576 |
Data Arrival Time | 7.098 |
Data Required Time | 1.522 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3 |
Launch Clk | clk_x1:[F] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk_x1 | ||||
5.000 | 0.000 | tCL | FF | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
6.514 | 1.514 | tNET | FF | 1 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.716 | 0.202 | tC2Q | FR | 60 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
7.098 | 0.383 | tNET | RR | 1 | R14C21[2][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R14C21[2][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLK |
1.522 | 0.011 | tHld | 1 | R14C21[2][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3 |
Path Statistics:
Clock Skew | -0.002 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.514, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.383, 65.449%; tC2Q: 0.202, 34.551% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path12
Path Summary:
Slack | 5.576 |
Data Arrival Time | 7.098 |
Data Required Time | 1.522 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0 |
Launch Clk | clk_x1:[F] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk_x1 | ||||
5.000 | 0.000 | tCL | FF | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
6.514 | 1.514 | tNET | FF | 1 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.716 | 0.202 | tC2Q | FR | 60 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
7.098 | 0.383 | tNET | RR | 1 | R14C21[2][B] | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R14C21[2][B] | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLK |
1.522 | 0.011 | tHld | 1 | R14C21[2][B] | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0 |
Path Statistics:
Clock Skew | -0.002 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.514, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.383, 65.449%; tC2Q: 0.202, 34.551% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path13
Path Summary:
Slack | 5.695 |
Data Arrival Time | 7.217 |
Data Required Time | 1.522 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1 |
Launch Clk | clk_x1:[F] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk_x1 | ||||
5.000 | 0.000 | tCL | FF | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
6.514 | 1.514 | tNET | FF | 1 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.716 | 0.202 | tC2Q | FR | 60 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
7.217 | 0.502 | tNET | RR | 1 | R15C19[2][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R15C19[2][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLK |
1.522 | 0.011 | tHld | 1 | R15C19[2][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1 |
Path Statistics:
Clock Skew | -0.002 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.514, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.502, 71.292%; tC2Q: 0.202, 28.708% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path14
Path Summary:
Slack | 5.700 |
Data Arrival Time | 7.222 |
Data Required Time | 1.522 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1 |
Launch Clk | clk_x1:[F] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk_x1 | ||||
5.000 | 0.000 | tCL | FF | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
6.514 | 1.514 | tNET | FF | 1 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.716 | 0.202 | tC2Q | FR | 60 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
7.222 | 0.507 | tNET | RR | 1 | R15C20[2][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R15C20[2][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLK |
1.522 | 0.011 | tHld | 1 | R15C20[2][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1 |
Path Statistics:
Clock Skew | -0.002 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.514, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.507, 71.493%; tC2Q: 0.202, 28.507% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path15
Path Summary:
Slack | 5.700 |
Data Arrival Time | 7.222 |
Data Required Time | 1.522 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1 |
Launch Clk | clk_x1:[F] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk_x1 | ||||
5.000 | 0.000 | tCL | FF | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
6.514 | 1.514 | tNET | FF | 1 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.716 | 0.202 | tC2Q | FR | 60 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
7.222 | 0.507 | tNET | RR | 1 | R15C20[2][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R15C20[2][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLK |
1.522 | 0.011 | tHld | 1 | R15C20[2][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1 |
Path Statistics:
Clock Skew | -0.002 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.514, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.507, 71.493%; tC2Q: 0.202, 28.507% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path16
Path Summary:
Slack | 5.701 |
Data Arrival Time | 7.223 |
Data Required Time | 1.522 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1 |
Launch Clk | clk_x1:[F] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk_x1 | ||||
5.000 | 0.000 | tCL | FF | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
6.514 | 1.514 | tNET | FF | 1 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.716 | 0.202 | tC2Q | FR | 60 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
7.223 | 0.508 | tNET | RR | 1 | R14C22[2][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R14C22[2][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLK |
1.522 | 0.011 | tHld | 1 | R14C22[2][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1 |
Path Statistics:
Clock Skew | -0.002 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.514, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.508, 71.535%; tC2Q: 0.202, 28.465% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path17
Path Summary:
Slack | 5.701 |
Data Arrival Time | 7.223 |
Data Required Time | 1.522 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1 |
Launch Clk | clk_x1:[F] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk_x1 | ||||
5.000 | 0.000 | tCL | FF | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
6.514 | 1.514 | tNET | FF | 1 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.716 | 0.202 | tC2Q | FR | 60 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
7.223 | 0.508 | tNET | RR | 1 | R14C19[2][B] | gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R14C19[2][B] | gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLK |
1.522 | 0.011 | tHld | 1 | R14C19[2][B] | gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1 |
Path Statistics:
Clock Skew | -0.002 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.514, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.508, 71.535%; tC2Q: 0.202, 28.465% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path18
Path Summary:
Slack | 5.701 |
Data Arrival Time | 7.223 |
Data Required Time | 1.522 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1 |
Launch Clk | clk_x1:[F] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk_x1 | ||||
5.000 | 0.000 | tCL | FF | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
6.514 | 1.514 | tNET | FF | 1 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.716 | 0.202 | tC2Q | FR | 60 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
7.223 | 0.508 | tNET | RR | 1 | R14C19[2][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R14C19[2][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLK |
1.522 | 0.011 | tHld | 1 | R14C19[2][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1 |
Path Statistics:
Clock Skew | -0.002 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.514, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.508, 71.535%; tC2Q: 0.202, 28.465% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path19
Path Summary:
Slack | 5.703 |
Data Arrival Time | 7.225 |
Data Required Time | 1.522 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1 |
Launch Clk | clk_x1:[F] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk_x1 | ||||
5.000 | 0.000 | tCL | FF | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
6.514 | 1.514 | tNET | FF | 1 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.716 | 0.202 | tC2Q | FR | 60 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
7.225 | 0.510 | tNET | RR | 1 | R17C19[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R17C19[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK |
1.522 | 0.011 | tHld | 1 | R17C19[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1 |
Path Statistics:
Clock Skew | -0.002 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.514, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.510, 71.614%; tC2Q: 0.202, 28.386% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path20
Path Summary:
Slack | 5.703 |
Data Arrival Time | 7.225 |
Data Required Time | 1.522 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_end_dly_s0 |
Launch Clk | clk_x1:[F] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk_x1 | ||||
5.000 | 0.000 | tCL | FF | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
6.514 | 1.514 | tNET | FF | 1 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.716 | 0.202 | tC2Q | FR | 60 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
7.225 | 0.510 | tNET | RR | 1 | R17C19[1][A] | gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R17C19[1][A] | gw_gao_inst_0/u_la0_top/capture_end_dly_s0/CLK |
1.522 | 0.011 | tHld | 1 | R17C19[1][A] | gw_gao_inst_0/u_la0_top/capture_end_dly_s0 |
Path Statistics:
Clock Skew | -0.002 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.514, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.510, 71.614%; tC2Q: 0.202, 28.386% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path21
Path Summary:
Slack | 5.730 |
Data Arrival Time | 7.253 |
Data Required Time | 1.522 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1 |
Launch Clk | clk_x1:[F] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk_x1 | ||||
5.000 | 0.000 | tCL | FF | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
6.514 | 1.514 | tNET | FF | 1 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.716 | 0.202 | tC2Q | FR | 60 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
7.253 | 0.537 | tNET | RR | 1 | R18C18[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R18C18[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLK |
1.522 | 0.011 | tHld | 1 | R18C18[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1 |
Path Statistics:
Clock Skew | -0.002 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.514, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.537, 72.669%; tC2Q: 0.202, 27.331% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path22
Path Summary:
Slack | 5.730 |
Data Arrival Time | 7.253 |
Data Required Time | 1.522 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1 |
Launch Clk | clk_x1:[F] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk_x1 | ||||
5.000 | 0.000 | tCL | FF | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
6.514 | 1.514 | tNET | FF | 1 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.716 | 0.202 | tC2Q | FR | 60 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
7.253 | 0.537 | tNET | RR | 1 | R18C18[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R18C18[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLK |
1.522 | 0.011 | tHld | 1 | R18C18[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1 |
Path Statistics:
Clock Skew | -0.002 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.514, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.537, 72.669%; tC2Q: 0.202, 27.331% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path23
Path Summary:
Slack | 5.739 |
Data Arrival Time | 7.262 |
Data Required Time | 1.522 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1 |
Launch Clk | clk_x1:[F] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk_x1 | ||||
5.000 | 0.000 | tCL | FF | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
6.514 | 1.514 | tNET | FF | 1 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.716 | 0.202 | tC2Q | FR | 60 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
7.262 | 0.546 | tNET | RR | 1 | R18C19[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R18C19[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/CLK |
1.522 | 0.011 | tHld | 1 | R18C19[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1 |
Path Statistics:
Clock Skew | -0.002 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.514, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.546, 72.996%; tC2Q: 0.202, 27.004% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path24
Path Summary:
Slack | 5.739 |
Data Arrival Time | 7.262 |
Data Required Time | 1.522 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1 |
Launch Clk | clk_x1:[F] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk_x1 | ||||
5.000 | 0.000 | tCL | FF | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
6.514 | 1.514 | tNET | FF | 1 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.716 | 0.202 | tC2Q | FR | 60 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
7.262 | 0.546 | tNET | RR | 1 | R18C19[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R18C19[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK |
1.522 | 0.011 | tHld | 1 | R18C19[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1 |
Path Statistics:
Clock Skew | -0.002 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.514, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.546, 72.996%; tC2Q: 0.202, 27.004% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path25
Path Summary:
Slack | 5.823 |
Data Arrival Time | 7.345 |
Data Required Time | 1.522 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1 |
Launch Clk | clk_x1:[F] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk_x1 | ||||
5.000 | 0.000 | tCL | FF | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
6.514 | 1.514 | tNET | FF | 1 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.716 | 0.202 | tC2Q | FR | 60 | R16C23[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
7.345 | 0.630 | tNET | RR | 1 | R14C20[2][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1848 | BOTTOMSIDE[0] | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R14C20[2][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLK |
1.522 | 0.011 | tHld | 1 | R14C20[2][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1 |
Path Statistics:
Clock Skew | -0.002 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.514, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.630, 75.711%; tC2Q: 0.202, 24.289% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Minimum Pulse Width Report:
Report Command:report_min_pulse_width -nworst 10 -detail
MPW1
MPW Summary:
Slack: | 0.837 |
Actual Width: | 1.837 |
Required Width: | 1.000 |
Type: | High Pulse Width |
Clock: | clk |
Objects: | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/stop_reg_1_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||
0.000 | 0.000 | clk | ||
0.000 | 0.000 | tCL | RR | clk_ibuf/I |
9.781 | 9.781 | tINS | RR | clk_ibuf/O |
12.052 | 2.271 | tNET | RR | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/stop_reg_1_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk | ||
10.000 | 0.000 | tCL | FF | clk_ibuf/I |
12.376 | 2.376 | tINS | FF | clk_ibuf/O |
13.889 | 1.514 | tNET | FF | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/stop_reg_1_s0/CLK |
MPW2
MPW Summary:
Slack: | 0.837 |
Actual Width: | 1.837 |
Required Width: | 1.000 |
Type: | High Pulse Width |
Clock: | clk |
Objects: | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/stop_reg_0_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||
0.000 | 0.000 | clk | ||
0.000 | 0.000 | tCL | RR | clk_ibuf/I |
9.781 | 9.781 | tINS | RR | clk_ibuf/O |
12.052 | 2.271 | tNET | RR | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/stop_reg_0_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk | ||
10.000 | 0.000 | tCL | FF | clk_ibuf/I |
12.376 | 2.376 | tINS | FF | clk_ibuf/O |
13.889 | 1.514 | tNET | FF | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/stop_reg_0_s0/CLK |
MPW3
MPW Summary:
Slack: | 0.837 |
Actual Width: | 1.837 |
Required Width: | 1.000 |
Type: | High Pulse Width |
Clock: | clk |
Objects: | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/ddr_rsti_reg_0_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||
0.000 | 0.000 | clk | ||
0.000 | 0.000 | tCL | RR | clk_ibuf/I |
9.781 | 9.781 | tINS | RR | clk_ibuf/O |
12.052 | 2.271 | tNET | RR | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/ddr_rsti_reg_0_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk | ||
10.000 | 0.000 | tCL | FF | clk_ibuf/I |
12.376 | 2.376 | tINS | FF | clk_ibuf/O |
13.889 | 1.514 | tNET | FF | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/ddr_rsti_reg_0_s0/CLK |
MPW4
MPW Summary:
Slack: | 0.837 |
Actual Width: | 1.837 |
Required Width: | 1.000 |
Type: | High Pulse Width |
Clock: | clk |
Objects: | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/uddcntln_reg_0_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||
0.000 | 0.000 | clk | ||
0.000 | 0.000 | tCL | RR | clk_ibuf/I |
9.781 | 9.781 | tINS | RR | clk_ibuf/O |
12.052 | 2.271 | tNET | RR | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/uddcntln_reg_0_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk | ||
10.000 | 0.000 | tCL | FF | clk_ibuf/I |
12.376 | 2.376 | tINS | FF | clk_ibuf/O |
13.889 | 1.514 | tNET | FF | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/uddcntln_reg_0_s0/CLK |
MPW5
MPW Summary:
Slack: | 0.837 |
Actual Width: | 1.837 |
Required Width: | 1.000 |
Type: | High Pulse Width |
Clock: | clk |
Objects: | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/cs_memsync_4_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||
0.000 | 0.000 | clk | ||
0.000 | 0.000 | tCL | RR | clk_ibuf/I |
9.781 | 9.781 | tINS | RR | clk_ibuf/O |
12.052 | 2.271 | tNET | RR | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/cs_memsync_4_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk | ||
10.000 | 0.000 | tCL | FF | clk_ibuf/I |
12.376 | 2.376 | tINS | FF | clk_ibuf/O |
13.889 | 1.514 | tNET | FF | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/cs_memsync_4_s0/CLK |
MPW6
MPW Summary:
Slack: | 0.837 |
Actual Width: | 1.837 |
Required Width: | 1.000 |
Type: | High Pulse Width |
Clock: | clk |
Objects: | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/lock_cnt_8_s1 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||
0.000 | 0.000 | clk | ||
0.000 | 0.000 | tCL | RR | clk_ibuf/I |
9.781 | 9.781 | tINS | RR | clk_ibuf/O |
12.052 | 2.271 | tNET | RR | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/lock_cnt_8_s1/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk | ||
10.000 | 0.000 | tCL | FF | clk_ibuf/I |
12.376 | 2.376 | tINS | FF | clk_ibuf/O |
13.889 | 1.514 | tNET | FF | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/lock_cnt_8_s1/CLK |
MPW7
MPW Summary:
Slack: | 0.837 |
Actual Width: | 1.837 |
Required Width: | 1.000 |
Type: | High Pulse Width |
Clock: | clk |
Objects: | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/lock_cnt_9_s1 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||
0.000 | 0.000 | clk | ||
0.000 | 0.000 | tCL | RR | clk_ibuf/I |
9.781 | 9.781 | tINS | RR | clk_ibuf/O |
12.052 | 2.271 | tNET | RR | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/lock_cnt_9_s1/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk | ||
10.000 | 0.000 | tCL | FF | clk_ibuf/I |
12.376 | 2.376 | tINS | FF | clk_ibuf/O |
13.889 | 1.514 | tNET | FF | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/lock_cnt_9_s1/CLK |
MPW8
MPW Summary:
Slack: | 0.837 |
Actual Width: | 1.837 |
Required Width: | 1.000 |
Type: | High Pulse Width |
Clock: | clk |
Objects: | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/cs_memsync_5_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||
0.000 | 0.000 | clk | ||
0.000 | 0.000 | tCL | RR | clk_ibuf/I |
9.781 | 9.781 | tINS | RR | clk_ibuf/O |
12.052 | 2.271 | tNET | RR | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/cs_memsync_5_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk | ||
10.000 | 0.000 | tCL | FF | clk_ibuf/I |
12.376 | 2.376 | tINS | FF | clk_ibuf/O |
13.889 | 1.514 | tNET | FF | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/cs_memsync_5_s0/CLK |
MPW9
MPW Summary:
Slack: | 0.837 |
Actual Width: | 1.837 |
Required Width: | 1.000 |
Type: | High Pulse Width |
Clock: | clk |
Objects: | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/lock_cnt_10_s1 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||
0.000 | 0.000 | clk | ||
0.000 | 0.000 | tCL | RR | clk_ibuf/I |
9.781 | 9.781 | tINS | RR | clk_ibuf/O |
12.052 | 2.271 | tNET | RR | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/lock_cnt_10_s1/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk | ||
10.000 | 0.000 | tCL | FF | clk_ibuf/I |
12.376 | 2.376 | tINS | FF | clk_ibuf/O |
13.889 | 1.514 | tNET | FF | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/lock_cnt_10_s1/CLK |
MPW10
MPW Summary:
Slack: | 0.837 |
Actual Width: | 1.837 |
Required Width: | 1.000 |
Type: | High Pulse Width |
Clock: | clk |
Objects: | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/lock_cnt_11_s1 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||
0.000 | 0.000 | clk | ||
0.000 | 0.000 | tCL | RR | clk_ibuf/I |
9.781 | 9.781 | tINS | RR | clk_ibuf/O |
12.052 | 2.271 | tNET | RR | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/lock_cnt_11_s1/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk | ||
10.000 | 0.000 | tCL | FF | clk_ibuf/I |
12.376 | 2.376 | tINS | FF | clk_ibuf/O |
13.889 | 1.514 | tNET | FF | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/lock_cnt_11_s1/CLK |
High Fanout Nets Report:
Report Command:report_high_fanout_nets -max_nets 10
FANOUT | NET NAME | WORST SLACK | MAX DELAY |
---|---|---|---|
1848 | clk_x1 | 1.069 | 2.274 |
631 | control0[0] | 1.114 | 2.925 |
190 | n20_3 | 6.705 | 1.357 |
169 | data_out_shift_reg_167_7 | 2.717 | 1.628 |
169 | n1371_5 | 2.717 | 1.262 |
153 | n1371_4 | 2.717 | 1.550 |
136 | init_calib_complete | 3.340 | 2.091 |
110 | jtag_strobe_i | 1.114 | 1.695 |
91 | rvalid[0] | 5.054 | 2.347 |
90 | n151_4 | 3.340 | 1.256 |
Route Congestions Report:
Report Command:report_route_congestion -max_grids 10
GRID LOC | ROUTE CONGESTIONS |
---|---|
R34C15 | 88.89% |
R16C32 | 87.50% |
R16C38 | 87.50% |
R18C36 | 87.50% |
R29C36 | 87.50% |
R31C36 | 87.50% |
R47C27 | 87.50% |
R27C35 | 87.50% |
R45C27 | 87.50% |
R17C35 | 86.11% |
Timing Exceptions Report:
Setup Analysis Report
Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Hold Analysis Report
Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Recovery Analysis Report
Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Removal Analysis Report
Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Timing Constraints Report:
SDC Command Type | State | Detail Command |
---|---|---|
TC_CLOCK | Actived | create_clock -name clk -period 20 -waveform {0 10} [get_ports {clk}] |
TC_CLOCK | Actived | create_clock -name tck_pad_i -period 10 -waveform {0 5} [get_ports {tck_pad_i}] -add |
TC_CLOCK | Actived | create_clock -name clk_x1 -period 10 -waveform {0 5} [get_nets {clk_x1}] -add |
TC_CLOCK | Actived | create_clock -name memory_clk -period 5 -waveform {0 2.5} [get_nets {memory_clk}] -add |
TC_CLOCK_GROUP | Actived | set_clock_groups -exclusive -group [get_clocks {clk}] -group [get_clocks {memory_clk}] -group [get_clocks {clk_x1}] -group [get_clocks {tck_pad_i}] |