Synthesis Messages

Report Title GowinSynthesis Report
Design File E:\myWork\IP\releaseVerify\RefDesign\Memory_Control\DDR3\Gowin_DDR3_Memory_Interface_RefDesign\DDR3_MC_PHY_1vs4\project\src\button.v
E:\myWork\IP\releaseVerify\RefDesign\Memory_Control\DDR3\Gowin_DDR3_Memory_Interface_RefDesign\DDR3_MC_PHY_1vs4\project\src\ddr3_memory_interface\ddr3_memory_interface.v
E:\myWork\IP\releaseVerify\RefDesign\Memory_Control\DDR3\Gowin_DDR3_Memory_Interface_RefDesign\DDR3_MC_PHY_1vs4\project\src\ddrtest.v
E:\myWork\IP\releaseVerify\RefDesign\Memory_Control\DDR3\Gowin_DDR3_Memory_Interface_RefDesign\DDR3_MC_PHY_1vs4\project\src\gowin_rpll\gowin_rpll.v
E:\myWork\IP\releaseVerify\RefDesign\Memory_Control\DDR3\Gowin_DDR3_Memory_Interface_RefDesign\DDR3_MC_PHY_1vs4\project\src\top.v
GowinSynthesis Constraints File ---
Tool Version V1.9.9.02
Part Number GW2A-LV18PG256C8/I7
Device GW2A-18
Device Version C
Created Time Wed Mar 27 10:51:59 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.828s, Elapsed time = 0h 0m 0.808s, Peak memory usage = 251.113MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.091s, Peak memory usage = 251.113MB
    Optimizing Phase 1: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.118s, Peak memory usage = 251.113MB
    Optimizing Phase 2: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.116s, Peak memory usage = 251.113MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.081s, Peak memory usage = 251.113MB
    Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 251.113MB
    Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.024s, Peak memory usage = 251.113MB
    Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 251.113MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.221s, Peak memory usage = 251.113MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.078s, Peak memory usage = 251.113MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.042s, Peak memory usage = 251.113MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 269.199MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.169s, Peak memory usage = 269.199MB
Generate output files:
    CPU time = 0h 0m 0.312s, Elapsed time = 0h 0m 0.371s, Peak memory usage = 273.832MB
Total Time and Memory Usage CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 273.832MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 53
I/O Buf 50
    IBUF 1
    OBUF 28
    TBUF 2
    IOBUF 16
    ELVDS_OBUF 1
    ELVDS_IOBUF 2
Register 4049
    DFF 229
    DFFE 252
    DFFS 1
    DFFR 1
    DFFP 56
    DFFPE 10
    DFFC 2962
    DFFCE 538
LUT 2485
    LUT2 551
    LUT3 899
    LUT4 1035
ALU 244
    ALU 244
SSRAM 137
    RAM16S4 44
    RAM16SDP4 93
INV 27
    INV 27
IOLOGIC 76
    IDES8_MEM 16
    OSER8 24
    OSER8_MEM 20
    IODELAY 16
BSRAM 4
    SDPX9B 4
CLOCK 5
    CLKDIV 1
    DQS 2
    DHCEN 1
    rPLL 1

Resource Utilization Summary

Resource Usage Utilization
Logic 3578(2512 LUT, 244 ALU, 137 RAM16) / 20736 18%
Register 4049 / 16173 26%
  --Register as Latch 0 / 16173 0%
  --Register as FF 4049 / 16173 26%
BSRAM 4 / 46 9%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
clk Base 20.000 50.0 0.000 10.000 clk_ibuf/I
upll/rpll_inst/CLKOUT.default_gen_clk Generated 2.857 350.0 0.000 1.429 clk_ibuf/I clk upll/rpll_inst/CLKOUT
upll/rpll_inst/CLKOUTP.default_gen_clk Generated 2.857 350.0 0.000 1.429 clk_ibuf/I clk upll/rpll_inst/CLKOUTP
upll/rpll_inst/CLKOUTD.default_gen_clk Generated 5.714 175.0 0.000 2.857 clk_ibuf/I clk upll/rpll_inst/CLKOUTD
upll/rpll_inst/CLKOUTD3.default_gen_clk Generated 8.571 116.7 0.000 4.286 clk_ibuf/I clk upll/rpll_inst/CLKOUTD3
u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk Generated 11.429 87.5 0.000 5.714 upll/rpll_inst/CLKOUT upll/rpll_inst/CLKOUT.default_gen_clk u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 50.000(MHz) 161.839(MHz) 7 TOP
2 upll/rpll_inst/CLKOUT.default_gen_clk 350.000(MHz) 1030.928(MHz) 1 TOP
3 u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk 87.500(MHz) 179.019(MHz) 3 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack -2.026
Data Arrival Time 25.515
Data Required Time 23.488
From u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_7_G[29]_s0
Launch Clk clk[R]
Latch Clk u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 41 clk_ibuf/O
20.360 0.360 tNET RR 1 u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
20.592 0.232 tC2Q RF 3119 u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
21.066 0.474 tNET FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init_s8/I1
21.621 0.555 tINS FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init_s8/F
22.095 0.474 tNET FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init_s9/I2
22.548 0.453 tINS FF 14 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init_s9/F
23.022 0.474 tNET FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_s27/I0
23.539 0.517 tINS FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_s27/F
24.013 0.474 tNET FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n463_s0/I1
24.583 0.570 tINS FR 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n463_s0/COUT
24.583 0.000 tNET RR 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n464_s0/CIN
24.618 0.035 tINS RF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n464_s0/COUT
24.618 0.000 tNET FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n465_s0/CIN
24.653 0.035 tINS FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n465_s0/COUT
24.653 0.000 tNET FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n466_s0/CIN
24.689 0.035 tINS FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n466_s0/COUT
24.689 0.000 tNET FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n467_s0/CIN
24.724 0.035 tINS FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n467_s0/COUT
24.724 0.000 tNET FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n468_s0/CIN
24.759 0.035 tINS FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n468_s0/COUT
24.759 0.000 tNET FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n469_s0/CIN
24.794 0.035 tINS FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n469_s0/COUT
24.794 0.000 tNET FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n470_s0/CIN
24.829 0.035 tINS FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n470_s0/COUT
24.829 0.000 tNET FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n471_s0/CIN
24.865 0.035 tINS FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n471_s0/COUT
24.865 0.000 tNET FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n472_s0/CIN
24.900 0.035 tINS FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n472_s0/COUT
24.900 0.000 tNET FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n473_s0/CIN
24.935 0.035 tINS FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n473_s0/COUT
24.935 0.000 tNET FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n474_s0/CIN
24.970 0.035 tINS FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n474_s0/COUT
24.970 0.000 tNET FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n475_s0/CIN
25.005 0.035 tINS FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n475_s0/COUT
25.005 0.000 tNET FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n476_s0/CIN
25.041 0.035 tINS FF 8 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n476_s0/COUT
25.515 0.474 tNET FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_7_G[29]_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
22.857 0.000 u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
23.198 0.341 tCL RR 4216 u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
23.558 0.360 tNET RR 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_7_G[29]_s0/CLK
23.523 -0.035 tUnc u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_7_G[29]_s0
23.488 -0.035 tSu 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_7_G[29]_s0
Path Statistics:
Clock Skew: 0.341
Setup Relationship: 2.857
Logic Level: 7
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%
Arrival Data Path Delay: cell: 2.553, 49.521%; route: 2.370, 45.978%; tC2Q: 0.232, 4.501%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%

Path 2

Path Summary:
Slack -2.026
Data Arrival Time 25.515
Data Required Time 23.488
From u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_6_G[29]_s0
Launch Clk clk[R]
Latch Clk u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 41 clk_ibuf/O
20.360 0.360 tNET RR 1 u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
20.592 0.232 tC2Q RF 3119 u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
21.066 0.474 tNET FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init_s8/I1
21.621 0.555 tINS FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init_s8/F
22.095 0.474 tNET FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init_s9/I2
22.548 0.453 tINS FF 14 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init_s9/F
23.022 0.474 tNET FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_s27/I0
23.539 0.517 tINS FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_s27/F
24.013 0.474 tNET FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n463_s0/I1
24.583 0.570 tINS FR 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n463_s0/COUT
24.583 0.000 tNET RR 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n464_s0/CIN
24.618 0.035 tINS RF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n464_s0/COUT
24.618 0.000 tNET FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n465_s0/CIN
24.653 0.035 tINS FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n465_s0/COUT
24.653 0.000 tNET FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n466_s0/CIN
24.689 0.035 tINS FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n466_s0/COUT
24.689 0.000 tNET FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n467_s0/CIN
24.724 0.035 tINS FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n467_s0/COUT
24.724 0.000 tNET FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n468_s0/CIN
24.759 0.035 tINS FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n468_s0/COUT
24.759 0.000 tNET FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n469_s0/CIN
24.794 0.035 tINS FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n469_s0/COUT
24.794 0.000 tNET FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n470_s0/CIN
24.829 0.035 tINS FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n470_s0/COUT
24.829 0.000 tNET FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n471_s0/CIN
24.865 0.035 tINS FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n471_s0/COUT
24.865 0.000 tNET FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n472_s0/CIN
24.900 0.035 tINS FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n472_s0/COUT
24.900 0.000 tNET FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n473_s0/CIN
24.935 0.035 tINS FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n473_s0/COUT
24.935 0.000 tNET FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n474_s0/CIN
24.970 0.035 tINS FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n474_s0/COUT
24.970 0.000 tNET FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n475_s0/CIN
25.005 0.035 tINS FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n475_s0/COUT
25.005 0.000 tNET FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n476_s0/CIN
25.041 0.035 tINS FF 8 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n476_s0/COUT
25.515 0.474 tNET FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_6_G[29]_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
22.857 0.000 u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
23.198 0.341 tCL RR 4216 u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
23.558 0.360 tNET RR 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_6_G[29]_s0/CLK
23.523 -0.035 tUnc u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_6_G[29]_s0
23.488 -0.035 tSu 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_6_G[29]_s0
Path Statistics:
Clock Skew: 0.341
Setup Relationship: 2.857
Logic Level: 7
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%
Arrival Data Path Delay: cell: 2.553, 49.521%; route: 2.370, 45.978%; tC2Q: 0.232, 4.501%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%

Path 3

Path Summary:
Slack -2.026
Data Arrival Time 25.515
Data Required Time 23.488
From u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_5_G[29]_s0
Launch Clk clk[R]
Latch Clk u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 41 clk_ibuf/O
20.360 0.360 tNET RR 1 u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
20.592 0.232 tC2Q RF 3119 u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
21.066 0.474 tNET FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init_s8/I1
21.621 0.555 tINS FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init_s8/F
22.095 0.474 tNET FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init_s9/I2
22.548 0.453 tINS FF 14 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init_s9/F
23.022 0.474 tNET FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_s27/I0
23.539 0.517 tINS FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_s27/F
24.013 0.474 tNET FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n463_s0/I1
24.583 0.570 tINS FR 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n463_s0/COUT
24.583 0.000 tNET RR 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n464_s0/CIN
24.618 0.035 tINS RF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n464_s0/COUT
24.618 0.000 tNET FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n465_s0/CIN
24.653 0.035 tINS FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n465_s0/COUT
24.653 0.000 tNET FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n466_s0/CIN
24.689 0.035 tINS FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n466_s0/COUT
24.689 0.000 tNET FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n467_s0/CIN
24.724 0.035 tINS FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n467_s0/COUT
24.724 0.000 tNET FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n468_s0/CIN
24.759 0.035 tINS FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n468_s0/COUT
24.759 0.000 tNET FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n469_s0/CIN
24.794 0.035 tINS FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n469_s0/COUT
24.794 0.000 tNET FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n470_s0/CIN
24.829 0.035 tINS FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n470_s0/COUT
24.829 0.000 tNET FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n471_s0/CIN
24.865 0.035 tINS FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n471_s0/COUT
24.865 0.000 tNET FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n472_s0/CIN
24.900 0.035 tINS FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n472_s0/COUT
24.900 0.000 tNET FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n473_s0/CIN
24.935 0.035 tINS FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n473_s0/COUT
24.935 0.000 tNET FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n474_s0/CIN
24.970 0.035 tINS FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n474_s0/COUT
24.970 0.000 tNET FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n475_s0/CIN
25.005 0.035 tINS FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n475_s0/COUT
25.005 0.000 tNET FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n476_s0/CIN
25.041 0.035 tINS FF 8 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n476_s0/COUT
25.515 0.474 tNET FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_5_G[29]_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
22.857 0.000 u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
23.198 0.341 tCL RR 4216 u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
23.558 0.360 tNET RR 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_5_G[29]_s0/CLK
23.523 -0.035 tUnc u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_5_G[29]_s0
23.488 -0.035 tSu 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_5_G[29]_s0
Path Statistics:
Clock Skew: 0.341
Setup Relationship: 2.857
Logic Level: 7
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%
Arrival Data Path Delay: cell: 2.553, 49.521%; route: 2.370, 45.978%; tC2Q: 0.232, 4.501%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%

Path 4

Path Summary:
Slack -2.026
Data Arrival Time 25.515
Data Required Time 23.488
From u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_4_G[29]_s0
Launch Clk clk[R]
Latch Clk u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 41 clk_ibuf/O
20.360 0.360 tNET RR 1 u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
20.592 0.232 tC2Q RF 3119 u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
21.066 0.474 tNET FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init_s8/I1
21.621 0.555 tINS FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init_s8/F
22.095 0.474 tNET FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init_s9/I2
22.548 0.453 tINS FF 14 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init_s9/F
23.022 0.474 tNET FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_s27/I0
23.539 0.517 tINS FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_s27/F
24.013 0.474 tNET FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n463_s0/I1
24.583 0.570 tINS FR 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n463_s0/COUT
24.583 0.000 tNET RR 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n464_s0/CIN
24.618 0.035 tINS RF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n464_s0/COUT
24.618 0.000 tNET FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n465_s0/CIN
24.653 0.035 tINS FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n465_s0/COUT
24.653 0.000 tNET FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n466_s0/CIN
24.689 0.035 tINS FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n466_s0/COUT
24.689 0.000 tNET FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n467_s0/CIN
24.724 0.035 tINS FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n467_s0/COUT
24.724 0.000 tNET FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n468_s0/CIN
24.759 0.035 tINS FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n468_s0/COUT
24.759 0.000 tNET FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n469_s0/CIN
24.794 0.035 tINS FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n469_s0/COUT
24.794 0.000 tNET FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n470_s0/CIN
24.829 0.035 tINS FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n470_s0/COUT
24.829 0.000 tNET FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n471_s0/CIN
24.865 0.035 tINS FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n471_s0/COUT
24.865 0.000 tNET FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n472_s0/CIN
24.900 0.035 tINS FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n472_s0/COUT
24.900 0.000 tNET FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n473_s0/CIN
24.935 0.035 tINS FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n473_s0/COUT
24.935 0.000 tNET FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n474_s0/CIN
24.970 0.035 tINS FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n474_s0/COUT
24.970 0.000 tNET FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n475_s0/CIN
25.005 0.035 tINS FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n475_s0/COUT
25.005 0.000 tNET FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n476_s0/CIN
25.041 0.035 tINS FF 8 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n476_s0/COUT
25.515 0.474 tNET FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_4_G[29]_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
22.857 0.000 u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
23.198 0.341 tCL RR 4216 u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
23.558 0.360 tNET RR 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_4_G[29]_s0/CLK
23.523 -0.035 tUnc u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_4_G[29]_s0
23.488 -0.035 tSu 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_4_G[29]_s0
Path Statistics:
Clock Skew: 0.341
Setup Relationship: 2.857
Logic Level: 7
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%
Arrival Data Path Delay: cell: 2.553, 49.521%; route: 2.370, 45.978%; tC2Q: 0.232, 4.501%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%

Path 5

Path Summary:
Slack -2.026
Data Arrival Time 25.515
Data Required Time 23.488
From u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_3_G[29]_s0
Launch Clk clk[R]
Latch Clk u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 41 clk_ibuf/O
20.360 0.360 tNET RR 1 u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
20.592 0.232 tC2Q RF 3119 u_ddr3/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
21.066 0.474 tNET FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init_s8/I1
21.621 0.555 tINS FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init_s8/F
22.095 0.474 tNET FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init_s9/I2
22.548 0.453 tINS FF 14 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init_s9/F
23.022 0.474 tNET FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_s27/I0
23.539 0.517 tINS FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_s27/F
24.013 0.474 tNET FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n463_s0/I1
24.583 0.570 tINS FR 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n463_s0/COUT
24.583 0.000 tNET RR 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n464_s0/CIN
24.618 0.035 tINS RF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n464_s0/COUT
24.618 0.000 tNET FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n465_s0/CIN
24.653 0.035 tINS FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n465_s0/COUT
24.653 0.000 tNET FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n466_s0/CIN
24.689 0.035 tINS FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n466_s0/COUT
24.689 0.000 tNET FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n467_s0/CIN
24.724 0.035 tINS FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n467_s0/COUT
24.724 0.000 tNET FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n468_s0/CIN
24.759 0.035 tINS FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n468_s0/COUT
24.759 0.000 tNET FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n469_s0/CIN
24.794 0.035 tINS FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n469_s0/COUT
24.794 0.000 tNET FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n470_s0/CIN
24.829 0.035 tINS FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n470_s0/COUT
24.829 0.000 tNET FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n471_s0/CIN
24.865 0.035 tINS FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n471_s0/COUT
24.865 0.000 tNET FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n472_s0/CIN
24.900 0.035 tINS FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n472_s0/COUT
24.900 0.000 tNET FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n473_s0/CIN
24.935 0.035 tINS FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n473_s0/COUT
24.935 0.000 tNET FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n474_s0/CIN
24.970 0.035 tINS FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n474_s0/COUT
24.970 0.000 tNET FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n475_s0/CIN
25.005 0.035 tINS FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n475_s0/COUT
25.005 0.000 tNET FF 2 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n476_s0/CIN
25.041 0.035 tINS FF 8 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/n476_s0/COUT
25.515 0.474 tNET FF 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_3_G[29]_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
22.857 0.000 u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
23.198 0.341 tCL RR 4216 u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
23.558 0.360 tNET RR 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_3_G[29]_s0/CLK
23.523 -0.035 tUnc u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_3_G[29]_s0
23.488 -0.035 tSu 1 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_mem_RAMREG_3_G[29]_s0
Path Statistics:
Clock Skew: 0.341
Setup Relationship: 2.857
Logic Level: 7
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%
Arrival Data Path Delay: cell: 2.553, 49.521%; route: 2.370, 45.978%; tC2Q: 0.232, 4.501%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%