Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\DDR3\data\ddr3_1_2\ddr3_1_2code.v C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\DDR3\data\ddr3_1_2\DDR3_TOP.v |
GowinSynthesis Constraints File | --- |
Tool Version | V1.9.9.02 |
Part Number | GW2A-LV18PG256C8/I7 |
Device | GW2A-1 |
Device Version | 8 |
Created Time | Tue Mar 26 15:09:22 2024 |
Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | DDR3_Memory_Interface_Top |
Synthesis Process | Running parser: CPU time = 0h 0m 0.64s, Elapsed time = 0h 0m 0.677s, Peak memory usage = 119.742MB Running netlist conversion: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.036s, Peak memory usage = 119.742MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.108s, Peak memory usage = 119.742MB Optimizing Phase 1: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.081s, Peak memory usage = 119.742MB Optimizing Phase 2: CPU time = 0h 0m 0.281s, Elapsed time = 0h 0m 0.276s, Peak memory usage = 119.742MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.14s, Peak memory usage = 119.742MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 119.742MB Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 119.742MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 119.742MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.154s, Peak memory usage = 119.742MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.06s, Peak memory usage = 119.742MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.018s, Peak memory usage = 119.742MB Tech-Mapping Phase 3: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 144.914MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.187s, Elapsed time = 0h 0m 0.195s, Peak memory usage = 144.914MB Generate output files: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.132s, Peak memory usage = 144.914MB |
Total Time and Memory Usage | CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s, Peak memory usage = 144.914MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 234 |
I/O Buf | 229 |
    IBUF | 111 |
    OBUF | 99 |
    IOBUF | 16 |
    ELVDS_OBUF | 1 |
    ELVDS_IOBUF | 2 |
Register | 1050 |
    DFF | 53 |
    DFFE | 4 |
    DFFR | 1 |
    DFFP | 58 |
    DFFPE | 2 |
    DFFC | 648 |
    DFFCE | 284 |
LUT | 1171 |
    LUT2 | 345 |
    LUT3 | 269 |
    LUT4 | 557 |
ALU | 90 |
    ALU | 90 |
SSRAM | 46 |
    RAM16S4 | 7 |
    RAM16SDP4 | 39 |
INV | 20 |
    INV | 20 |
IOLOGIC | 100 |
    IDES4_MEM | 16 |
    OSER4 | 24 |
    OSER4_MEM | 20 |
    IODELAY | 40 |
BSRAM | 4 |
    SDPB | 2 |
    SDPX9B | 2 |
CLOCK | 4 |
    CLKDIV | 1 |
    DQS | 2 |
    DHCEN | 1 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 1557(1191 LUT, 90 ALU, 46 RAM16) / 20736 | 8% |
Register | 1050 / 16173 | 7% |
  --Register as Latch | 0 / 16173 | 0% |
  --Register as FF | 1050 / 16173 | 7% |
BSRAM | 4 / 46 | 9% |
Timing
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|
memory_clk | Base | 10.000 | 100.0 | 0.000 | 5.000 | memory_clk_ibuf/I | ||
clk | Base | 10.000 | 100.0 | 0.000 | 5.000 | clk_ibuf/I | ||
u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | Generated | 20.000 | 50.0 | 0.000 | 10.000 | memory_clk_ibuf/I | memory_clk | u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
Max Frequency Summary:
No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | memory_clk | 100.000(MHz) | 1030.929(MHz) | 1 | TOP |
2 | clk | 100.000(MHz) | 181.884(MHz) | 6 | TOP |
3 | u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | 50.000(MHz) | 156.568(MHz) | 7 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | -1.441 |
Data Arrival Time | 7.053 |
Data Required Time | 5.612 |
From | u_gw3_phy_mc/u_ddr_phy_top/u_ddr_init/timer_cnt_7_s0 |
To | u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
Launch Clk | u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[F] |
Latch Clk | memory_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
0.341 | 0.341 | tCL | RR | 1125 | u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
0.701 | 0.360 | tNET | RR | 1 | u_gw3_phy_mc/u_ddr_phy_top/u_ddr_init/timer_cnt_7_s0/CLK |
0.933 | 0.232 | tC2Q | RF | 7 | u_gw3_phy_mc/u_ddr_phy_top/u_ddr_init/timer_cnt_7_s0/Q |
1.407 | 0.474 | tNET | FF | 1 | u_gw3_phy_mc/u_ddr_phy_top/u_ddr_init/init_next_state.WRITE_LEVELING_s21/I1 |
1.962 | 0.555 | tINS | FF | 1 | u_gw3_phy_mc/u_ddr_phy_top/u_ddr_init/init_next_state.WRITE_LEVELING_s21/F |
2.436 | 0.474 | tNET | FF | 1 | u_gw3_phy_mc/u_ddr_phy_top/u_ddr_init/init_next_state.WRITE_LEVELING_s20/I2 |
2.889 | 0.453 | tINS | FF | 2 | u_gw3_phy_mc/u_ddr_phy_top/u_ddr_init/init_next_state.WRITE_LEVELING_s20/F |
3.363 | 0.474 | tNET | FF | 1 | u_gw3_phy_mc/u_ddr_phy_top/u_ddr_init/read_cal_next_state.READ_CAL_DONE_s18/I2 |
3.816 | 0.453 | tINS | FF | 4 | u_gw3_phy_mc/u_ddr_phy_top/u_ddr_init/read_cal_next_state.READ_CAL_DONE_s18/F |
4.290 | 0.474 | tNET | FF | 1 | u_gw3_phy_mc/u_ddr_phy_top/u_ddr_init/n1446_s4/I2 |
4.743 | 0.453 | tINS | FF | 2 | u_gw3_phy_mc/u_ddr_phy_top/u_ddr_init/n1446_s4/F |
5.217 | 0.474 | tNET | FF | 1 | u_gw3_phy_mc/u_ddr_phy_top/u_ddr_init/n1446_s1/I3 |
5.588 | 0.371 | tINS | FF | 11 | u_gw3_phy_mc/u_ddr_phy_top/u_ddr_init/n1446_s1/F |
6.062 | 0.474 | tNET | FF | 1 | u_gw3_phy_mc/u_ddr_phy_top/u_ddr_init/hold_Z_s/I0 |
6.579 | 0.517 | tINS | FF | 2 | u_gw3_phy_mc/u_ddr_phy_top/u_ddr_init/hold_Z_s/F |
7.053 | 0.474 | tNET | FF | 1 | u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
5.000 | 0.000 | memory_clk | |||
5.000 | 0.000 | tCL | FF | 1 | memory_clk_ibuf/I |
5.000 | 0.000 | tINS | FF | 1 | memory_clk_ibuf/O |
5.474 | 0.474 | tNET | FF | 3 | u_gw3_phy_mc/u_ddr_phy_top/fclk_dhcen/CLKIN |
5.660 | 0.186 | tINS | FF | 64 | u_gw3_phy_mc/u_ddr_phy_top/fclk_dhcen/CLKOUT |
6.134 | 0.474 | tNET | FF | 1 | u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
6.099 | -0.035 | tUnc | u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs | ||
5.612 | -0.487 | tSu | 1 | u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
Clock Skew: | 0.433 |
Setup Relationship: | 5.000 |
Logic Level: | 7 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Arrival Data Path Delay: | cell: 2.802, 44.112%; route: 3.318, 52.236%; tC2Q: 0.232, 3.652% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Path 2
Path Summary:Slack | -1.441 |
Data Arrival Time | 7.053 |
Data Required Time | 5.612 |
From | u_gw3_phy_mc/u_ddr_phy_top/u_ddr_init/timer_cnt_7_s0 |
To | u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
Launch Clk | u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[F] |
Latch Clk | memory_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
0.341 | 0.341 | tCL | RR | 1125 | u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
0.701 | 0.360 | tNET | RR | 1 | u_gw3_phy_mc/u_ddr_phy_top/u_ddr_init/timer_cnt_7_s0/CLK |
0.933 | 0.232 | tC2Q | RF | 7 | u_gw3_phy_mc/u_ddr_phy_top/u_ddr_init/timer_cnt_7_s0/Q |
1.407 | 0.474 | tNET | FF | 1 | u_gw3_phy_mc/u_ddr_phy_top/u_ddr_init/init_next_state.WRITE_LEVELING_s21/I1 |
1.962 | 0.555 | tINS | FF | 1 | u_gw3_phy_mc/u_ddr_phy_top/u_ddr_init/init_next_state.WRITE_LEVELING_s21/F |
2.436 | 0.474 | tNET | FF | 1 | u_gw3_phy_mc/u_ddr_phy_top/u_ddr_init/init_next_state.WRITE_LEVELING_s20/I2 |
2.889 | 0.453 | tINS | FF | 2 | u_gw3_phy_mc/u_ddr_phy_top/u_ddr_init/init_next_state.WRITE_LEVELING_s20/F |
3.363 | 0.474 | tNET | FF | 1 | u_gw3_phy_mc/u_ddr_phy_top/u_ddr_init/read_cal_next_state.READ_CAL_DONE_s18/I2 |
3.816 | 0.453 | tINS | FF | 4 | u_gw3_phy_mc/u_ddr_phy_top/u_ddr_init/read_cal_next_state.READ_CAL_DONE_s18/F |
4.290 | 0.474 | tNET | FF | 1 | u_gw3_phy_mc/u_ddr_phy_top/u_ddr_init/n1446_s4/I2 |
4.743 | 0.453 | tINS | FF | 2 | u_gw3_phy_mc/u_ddr_phy_top/u_ddr_init/n1446_s4/F |
5.217 | 0.474 | tNET | FF | 1 | u_gw3_phy_mc/u_ddr_phy_top/u_ddr_init/n1446_s1/I3 |
5.588 | 0.371 | tINS | FF | 11 | u_gw3_phy_mc/u_ddr_phy_top/u_ddr_init/n1446_s1/F |
6.062 | 0.474 | tNET | FF | 1 | u_gw3_phy_mc/u_ddr_phy_top/u_ddr_init/hold_Z_s/I0 |
6.579 | 0.517 | tINS | FF | 2 | u_gw3_phy_mc/u_ddr_phy_top/u_ddr_init/hold_Z_s/F |
7.053 | 0.474 | tNET | FF | 1 | u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
5.000 | 0.000 | memory_clk | |||
5.000 | 0.000 | tCL | FF | 1 | memory_clk_ibuf/I |
5.000 | 0.000 | tINS | FF | 1 | memory_clk_ibuf/O |
5.474 | 0.474 | tNET | FF | 3 | u_gw3_phy_mc/u_ddr_phy_top/fclk_dhcen/CLKIN |
5.660 | 0.186 | tINS | FF | 64 | u_gw3_phy_mc/u_ddr_phy_top/fclk_dhcen/CLKOUT |
6.134 | 0.474 | tNET | FF | 1 | u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
6.099 | -0.035 | tUnc | u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs | ||
5.612 | -0.487 | tSu | 1 | u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
Clock Skew: | 0.433 |
Setup Relationship: | 5.000 |
Logic Level: | 7 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Arrival Data Path Delay: | cell: 2.802, 44.112%; route: 3.318, 52.236%; tC2Q: 0.232, 3.652% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Path 3
Path Summary:Slack | 4.187 |
Data Arrival Time | 1.066 |
Data Required Time | 5.253 |
From | u_gw3_phy_mc/u_ddr_phy_top/stop_reg_2_s0 |
To | u_gw3_phy_mc/u_ddr_phy_top/fclk_dhcen |
Launch Clk | clk[F] |
Latch Clk | memory_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.000 | 0.000 | tINS | RR | 42 | clk_ibuf/O |
0.360 | 0.360 | tNET | RR | 1 | u_gw3_phy_mc/u_ddr_phy_top/stop_reg_2_s0/CLK |
0.592 | 0.232 | tC2Q | RF | 1 | u_gw3_phy_mc/u_ddr_phy_top/stop_reg_2_s0/Q |
1.066 | 0.474 | tNET | FF | 1 | u_gw3_phy_mc/u_ddr_phy_top/fclk_dhcen/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
5.000 | 0.000 | memory_clk | |||
5.000 | 0.000 | tCL | FF | 1 | memory_clk_ibuf/I |
5.000 | 0.000 | tINS | FF | 1 | memory_clk_ibuf/O |
5.474 | 0.474 | tNET | FF | 3 | u_gw3_phy_mc/u_ddr_phy_top/fclk_dhcen/CLKIN |
5.439 | -0.035 | tUnc | u_gw3_phy_mc/u_ddr_phy_top/fclk_dhcen | ||
5.253 | -0.186 | tSu | 1 | u_gw3_phy_mc/u_ddr_phy_top/fclk_dhcen |
Clock Skew: | 0.114 |
Setup Relationship: | 5.000 |
Logic Level: | 1 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.474, 67.139%; tC2Q: 0.232, 32.861% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Path 4
Path Summary:Slack | 4.502 |
Data Arrival Time | 5.823 |
Data Required Time | 10.325 |
From | u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/cs_memsync_4_s0 |
To | u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/count_0_s0 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.000 | 0.000 | tINS | RR | 42 | clk_ibuf/O |
0.360 | 0.360 | tNET | RR | 1 | u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/cs_memsync_4_s0/CLK |
0.592 | 0.232 | tC2Q | RF | 8 | u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/cs_memsync_4_s0/Q |
1.066 | 0.474 | tNET | FF | 1 | u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/ns_memsync_2_s17/I1 |
1.621 | 0.555 | tINS | FF | 1 | u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/ns_memsync_2_s17/F |
2.095 | 0.474 | tNET | FF | 1 | u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/ns_memsync_2_s14/I2 |
2.548 | 0.453 | tINS | FF | 4 | u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/ns_memsync_2_s14/F |
3.022 | 0.474 | tNET | FF | 1 | u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/n295_s5/I2 |
3.475 | 0.453 | tINS | FF | 1 | u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/n295_s5/F |
3.949 | 0.474 | tNET | FF | 1 | u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/n295_s4/I3 |
4.320 | 0.371 | tINS | FF | 3 | u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/n295_s4/F |
4.794 | 0.474 | tNET | FF | 1 | u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/n295_s3/I1 |
5.349 | 0.555 | tINS | FF | 1 | u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/n295_s3/F |
5.823 | 0.474 | tNET | FF | 1 | u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/count_0_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk | |||
10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
10.000 | 0.000 | tINS | RR | 42 | clk_ibuf/O |
10.360 | 0.360 | tNET | RR | 1 | u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/count_0_s0/CLK |
10.325 | -0.035 | tSu | 1 | u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/count_0_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 6 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Arrival Data Path Delay: | cell: 2.387, 43.694%; route: 2.844, 52.059%; tC2Q: 0.232, 4.247% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Path 5
Path Summary:Slack | 4.502 |
Data Arrival Time | 5.823 |
Data Required Time | 10.325 |
From | u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/cs_memsync_4_s0 |
To | u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/flag_0_s4 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.000 | 0.000 | tINS | RR | 42 | clk_ibuf/O |
0.360 | 0.360 | tNET | RR | 1 | u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/cs_memsync_4_s0/CLK |
0.592 | 0.232 | tC2Q | RF | 8 | u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/cs_memsync_4_s0/Q |
1.066 | 0.474 | tNET | FF | 1 | u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/ns_memsync_2_s17/I1 |
1.621 | 0.555 | tINS | FF | 1 | u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/ns_memsync_2_s17/F |
2.095 | 0.474 | tNET | FF | 1 | u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/ns_memsync_2_s14/I2 |
2.548 | 0.453 | tINS | FF | 4 | u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/ns_memsync_2_s14/F |
3.022 | 0.474 | tNET | FF | 1 | u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/ns_memsync_5_s13/I1 |
3.577 | 0.555 | tINS | FF | 3 | u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/ns_memsync_5_s13/F |
4.051 | 0.474 | tNET | FF | 1 | u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/flag_d_0_s14/I2 |
4.504 | 0.453 | tINS | FF | 1 | u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/flag_d_0_s14/F |
4.978 | 0.474 | tNET | FF | 1 | u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/flag_d_0_s11/I3 |
5.349 | 0.371 | tINS | FF | 1 | u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/flag_d_0_s11/F |
5.823 | 0.474 | tNET | FF | 1 | u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/flag_0_s4/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk | |||
10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
10.000 | 0.000 | tINS | RR | 42 | clk_ibuf/O |
10.360 | 0.360 | tNET | RR | 1 | u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/flag_0_s4/CLK |
10.325 | -0.035 | tSu | 1 | u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/flag_0_s4 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 6 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Arrival Data Path Delay: | cell: 2.387, 43.694%; route: 2.844, 52.059%; tC2Q: 0.232, 4.247% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |