Power Messages

Report Title Power Analysis Report
Design File E:\myWork\IP\releaseVerify\RefDesign\Memory_Control\DDR3\Gowin_DDR3_Memory_Interface_RefDesign\DDR3_MC_PHY_1vs2\project\impl\gwsynthesis\ddr3_ref_design.vg
Physical Constraints File E:\myWork\IP\releaseVerify\RefDesign\Memory_Control\DDR3\Gowin_DDR3_Memory_Interface_RefDesign\DDR3_MC_PHY_1vs2\project\src\ddr3.cst
Timing Constraints File E:\myWork\IP\releaseVerify\RefDesign\Memory_Control\DDR3\Gowin_DDR3_Memory_Interface_RefDesign\DDR3_MC_PHY_1vs2\project\src\ddr3.sdc
Tool Version V1.9.9.02
Part Number GW2A-LV18PG256C8/I7
Device GW2A-18
Created Time Tue Mar 26 15:11:24 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

Power Summary

Power Information:

Total Power (mW) 411.352
Quiescent Power (mW) 91.297
Dynamic Power (mW) 320.055

Thermal Information:

Junction Temperature 38.172
Theta JA 32.020
Max Allowed Ambient Temperature 71.828

Configure Information:

Default IO Toggle Rate 0.125
Default Remain Toggle Rate 0.125
Use Vectorless Estimation false
Filter Glitches false
Related Vcd File
Related Saif File
Use Custom Theta JA false
Air Flow LFM_0
Heat Sink None
Use Custom Theta SA false
Board Thermal Model None
Use Custom Theta JB false
Ambient Temperature 25.000

Supply Information:

Voltage Source Voltage Dynamic Current(mA) Quiescent Current(mA) Power(mW)
VCC 1.000 294.460 61.452 355.912
VCCX 2.500 6.378 11.364 44.354
VCCIO15 1.500 5.967 0.876 10.265
VCCIO18 1.800 0.389 0.068 0.821

Power Details

Power By Block Type:

Block Type Total Power(mW) Static Power(mW) Average Toggle Rate(millions of transitions/sec)
Logic 4.031 NA 12.292
IO 41.139 8.911 29.452
BSRAM 216.720 NA NA
PLL 20.920 NA NA
DLL 46.080 NA NA
DQS 135.900 NA NA

Power By Hierarchy:

Hierarchy Entity Total Power(mW) Block Dynamic Power(mW)
ddr3_syn_top 423.652 423.652(423.582)
ddr3_syn_top/gw_gao_inst_0/ 153.202 153.202(153.202)
ddr3_syn_top/gw_gao_inst_0/u_icon_top/ 0.026 0.026(0.000)
ddr3_syn_top/gw_gao_inst_0/u_la0_top/ 153.176 153.176(152.463)
ddr3_syn_top/gw_gao_inst_0/u_la0_top/u_ao_crc32/ 0.054 0.054(0.000)
ddr3_syn_top/gw_gao_inst_0/u_la0_top/u_ao_match_0/ 0.026 0.026(0.000)
ddr3_syn_top/gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/ 152.383 152.383(0.000)
ddr3_syn_top/pll/ 20.920 20.920(0.000)
ddr3_syn_top/u_ddr3/ 248.924 248.924(248.924)
ddr3_syn_top/u_ddr3/u_gw3_phy_mc/ 248.924 248.924(248.924)
ddr3_syn_top/u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/ 247.701 247.701(201.369)
ddr3_syn_top/u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/ddr_sync/ 0.041 0.041(0.000)
ddr3_syn_top/u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_init/ 0.481 0.481(0.000)
ddr3_syn_top/u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/ 200.847 200.847(200.774)
ddr3_syn_top/u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/ 132.583 132.583(132.574)
ddr3_syn_top/u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/ 67.953 67.953(0.000)
ddr3_syn_top/u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/ 31.860 31.860(0.000)
ddr3_syn_top/u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/ 32.761 32.761(0.000)
ddr3_syn_top/u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/ 67.959 67.959(67.950)
ddr3_syn_top/u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/ 67.950 67.950(0.000)
ddr3_syn_top/u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/ 0.123 0.123(0.083)
ddr3_syn_top/u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_cmd_fifo/ 0.083 0.083(0.000)
ddr3_syn_top/u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/u_fifo_ctrl/ 0.110 0.110(0.000)
ddr3_syn_top/u_ddr3/u_gw3_phy_mc/u_gwmc_top/ 1.223 1.223(1.065)
ddr3_syn_top/u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_cmd0/ 0.259 0.259(0.000)
ddr3_syn_top/u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_rd_data0/ 0.101 0.101(0.000)
ddr3_syn_top/u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_wr_data0/ 0.260 0.260(0.187)
ddr3_syn_top/u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_wr_data0/wr_fifo/ 0.187 0.187(0.000)
ddr3_syn_top/u_ddr3/u_gw3_phy_mc/u_gwmc_top/gwmc_bank_ctrl0/ 0.327 0.327(0.000)
ddr3_syn_top/u_ddr3/u_gw3_phy_mc/u_gwmc_top/gwmc_rank_ctrl0/ 0.084 0.084(0.000)
ddr3_syn_top/u_ddr3/u_gw3_phy_mc/u_gwmc_top/gwmc_timing_ctrl0/ 0.034 0.034(0.000)
ddr3_syn_top/u_rd/ 0.536 0.536(0.000)

Power By Clock Domain:

Clock Domain Clock Frequency(Mhz) Total Dynamic Power(mW)
tck_pad_i 100.000 76.842
clk_x1 100.000 143.905
NO CLOCK DOMAIN 0.000 0.000
clk 50.000 20.972
memory_clk 200.000 182.007