Timing Messages

Report Title Timing Analysis Report
Design File E:\myWork\IP\releaseVerify\version\1.9.9.02\DDR3_MC_PHY_1vs4_5a25k\project\impl\gwsynthesis\ddr3_1v4_hs.vg
Physical Constraints File E:\myWork\IP\releaseVerify\version\1.9.9.02\DDR3_MC_PHY_1vs4_5a25k\project\src\ddr3_1v4_hs.cst
Timing Constraint File E:\myWork\IP\releaseVerify\version\1.9.9.02\DDR3_MC_PHY_1vs4_5a25k\project\src\ddr3_1v4_hs.sdc
Tool Version V1.9.9.02
Part Number GW5A-LV25UG324ES
Device GW5A-25
Device Version A
Created Time Tue Mar 26 14:27:48 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model Slow 0.855V 0C ES
Hold Delay Model Fast 0.945V 85C ES
Numbers of Paths Analyzed 15406
Numbers of Endpoints Analyzed 21871
Numbers of Falling Endpoints 0
Numbers of Setup Violated Endpoints 0
Numbers of Hold Violated Endpoints 0

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Objects
clk4x Base 2.500 400.000 0.000 1.250 Gowin_PLL_inst/PLLA_inst/CLKOUT2
clk1x Base 10.000 100.000 0.000 5.000 u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
clkin Base 20.000 50.000 0.000 10.000 clk_g

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk4x 400.000(MHz) 2016.129(MHz) 1 TOP
2 clk1x 100.000(MHz) 100.357(MHz) 7 TOP
3 clkin 50.000(MHz) 238.521(MHz) 6 TOP

Total Negative Slack Summary:

Clock Name Analysis Type Endpoints TNS Number of Endpoints
clk4x Setup 0.000 0
clk4x Hold 0.000 0
clk1x Setup 0.000 0
clk1x Hold 0.000 0
clkin Setup 0.000 0
clkin Hold 0.000 0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.036 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/Q u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_IDLE_s2/D clk1x:[R] clk1x:[R] 10.000 -0.024 9.925
2 0.036 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/Q u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/idle1_s0/D clk1x:[R] clk1x:[R] 10.000 -0.024 9.925
3 0.114 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/Q u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_SREE_s2/D clk1x:[R] clk1x:[R] 10.000 -0.031 9.854
4 0.194 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/Q u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_SRE_s4/D clk1x:[R] clk1x:[R] 10.000 -0.031 9.774
5 0.633 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/Q u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_POWERON_s14/D clk1x:[R] clk1x:[R] 10.000 -0.024 9.327
6 0.644 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/Q u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/idle2_s0/D clk1x:[R] clk1x:[R] 10.000 -0.024 9.316
7 0.779 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_Empty_reg_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_Empty_reg_s0/D clk1x:[R] clk1x:[R] 10.000 0.000 9.157
8 0.819 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/Q u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_R2W_s6/D clk1x:[R] clk1x:[R] 10.000 -0.039 9.162
9 0.971 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/Q u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_ACT2RD_s6/D clk1x:[R] clk1x:[R] 10.000 -0.051 9.016
10 0.994 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/Q u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_RP2AW_s10/D clk1x:[R] clk1x:[R] 10.000 -0.005 8.947
11 1.008 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_1_s0/Q u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/idle3_s0/D clk1x:[R] clk1x:[R] 10.000 -0.044 8.972
12 1.056 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/Q u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_WRITE_s4/D clk1x:[R] clk1x:[R] 10.000 -0.036 8.916
13 1.174 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/Q u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_ACT2WR_s10/D clk1x:[R] clk1x:[R] 10.000 0.004 8.757
14 1.174 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/Q u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_W2R_s8/D clk1x:[R] clk1x:[R] 10.000 0.004 8.757
15 1.386 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/Q u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_RP2SRE_s14/D clk1x:[R] clk1x:[R] 10.000 -0.007 8.557
16 1.425 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_1_s0/Q u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_READ_s6/D clk1x:[R] clk1x:[R] 10.000 -0.061 8.572
17 1.569 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/Q u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_RP2REF_s14/D clk1x:[R] clk1x:[R] 10.000 0.002 8.365
18 1.735 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_1_s0/Q u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_ACT_WR_s4/D clk1x:[R] clk1x:[R] 10.000 -0.025 8.226
19 1.736 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/Q u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_RP2AR_s6/D clk1x:[R] clk1x:[R] 10.000 -0.007 8.207
20 1.791 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_1_s0/Q u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_ACT_RD_s4/D clk1x:[R] clk1x:[R] 10.000 -0.071 8.216
21 1.918 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_Empty_reg_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rbin_3_s0/D clk1x:[R] clk1x:[R] 10.000 -0.009 8.028
22 1.945 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_1_s0/Q u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_WP2AW_s12/D clk1x:[R] clk1x:[R] 10.000 -0.056 8.047
23 1.970 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/Q u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_ZQ_s14/D clk1x:[R] clk1x:[R] 10.000 -0.034 8.000
24 1.989 u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/Q u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_REF_s4/D clk1x:[R] clk1x:[R] 10.000 -0.034 7.981
25 2.004 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem/RADDR[2] clk4x:[R] clk4x:[R] 2.500 0.000 0.496

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.048 u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_mask_r_11_s0/Q u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_7_s/DI[15] clk1x:[R] clk1x:[R] 0.000 0.001 0.296
2 0.067 u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_150_s0/Q u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_4_s/DI[6] clk1x:[R] clk1x:[R] 0.000 0.012 0.304
3 0.077 u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_214_s0/Q u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_5_s/DI[34] clk1x:[R] clk1x:[R] 0.000 0.023 0.304
4 0.077 u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_210_s0/Q u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_5_s/DI[30] clk1x:[R] clk1x:[R] 0.000 0.023 0.304
5 0.078 u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_229_s0/Q u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_6_s/DI[13] clk1x:[R] clk1x:[R] 0.000 0.021 0.306
6 0.086 u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_mask_r_4_s0/Q u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_7_s/DI[8] clk1x:[R] clk1x:[R] 0.000 0.016 0.319
7 0.154 u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_146_s0/Q u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_4_s/DI[2] clk1x:[R] clk1x:[R] 0.000 0.003 0.400
8 0.161 u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_152_s0/Q u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_4_s/DI[8] clk1x:[R] clk1x:[R] 0.000 0.012 0.397
9 0.161 u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_218_s0/Q u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_6_s/DI[2] clk1x:[R] clk1x:[R] 0.000 0.013 0.397
10 0.161 u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_216_s0/Q u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_6_s/DI[0] clk1x:[R] clk1x:[R] 0.000 0.013 0.397
11 0.174 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_63_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/DI[31] clk1x:[R] clk1x:[R] 0.000 0.006 0.416
12 0.174 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_62_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/DI[30] clk1x:[R] clk1x:[R] 0.000 0.006 0.416
13 0.174 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_60_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/DI[28] clk1x:[R] clk1x:[R] 0.000 0.006 0.416
14 0.174 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_56_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/DI[24] clk1x:[R] clk1x:[R] 0.000 0.006 0.416
15 0.174 u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_mask_r_1_s0/Q u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_7_s/DI[5] clk1x:[R] clk1x:[R] 0.000 0.011 0.412
16 0.178 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_61_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/DI[29] clk1x:[R] clk1x:[R] 0.000 0.011 0.416
17 0.178 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_59_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/DI[27] clk1x:[R] clk1x:[R] 0.000 0.011 0.416
18 0.178 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_57_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/DI[25] clk1x:[R] clk1x:[R] 0.000 0.011 0.416
19 0.178 u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_87_s0/Q u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_2_s/DI[15] clk1x:[R] clk1x:[R] 0.000 0.011 0.416
20 0.178 u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_86_s0/Q u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_2_s/DI[14] clk1x:[R] clk1x:[R] 0.000 0.011 0.416
21 0.179 u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_151_s0/Q u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_4_s/DI[7] clk1x:[R] clk1x:[R] 0.000 0.009 0.419
22 0.180 u_ddr3/gw3_top/u_ddr_phy_top/mux_wrdata_248_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem8_mem8_0_4_s/DI[15] clk1x:[R] clk1x:[R] 0.000 0.013 0.416
23 0.180 u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_230_s0/Q u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_6_s/DI[14] clk1x:[R] clk1x:[R] 0.000 0.013 0.416
24 0.186 u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_136_s0/Q u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_3_s/DI[28] clk1x:[R] clk1x:[R] 0.000 0.016 0.419
25 0.186 u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_170_s0/Q u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_4_s/DI[26] clk1x:[R] clk1x:[R] 0.000 0.012 0.424

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 4.662 u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rbin_1_s0/CLEAR clk1x:[R] clk1x:[R] 10.000 -0.030 5.021
2 4.662 u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rbin_2_s0/CLEAR clk1x:[R] clk1x:[R] 10.000 -0.030 5.021
3 4.662 u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rbin_3_s0/CLEAR clk1x:[R] clk1x:[R] 10.000 -0.030 5.021
4 4.852 u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_wbin_1_s0/CLEAR clk1x:[R] clk1x:[R] 10.000 -0.028 4.829
5 4.852 u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_wptr_0_s0/CLEAR clk1x:[R] clk1x:[R] 10.000 -0.028 4.829
6 4.852 u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_wptr_2_s0/CLEAR clk1x:[R] clk1x:[R] 10.000 -0.028 4.829
7 4.852 u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq2_wptr_0_s0/CLEAR clk1x:[R] clk1x:[R] 10.000 -0.028 4.829
8 4.852 u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq2_wptr_2_s0/CLEAR clk1x:[R] clk1x:[R] 10.000 -0.028 4.829
9 4.852 u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq1_wptr_0_s0/CLEAR clk1x:[R] clk1x:[R] 10.000 -0.028 4.829
10 4.852 u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq1_wptr_2_s0/CLEAR clk1x:[R] clk1x:[R] 10.000 -0.028 4.829
11 4.862 u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_wbin_0_s0/CLEAR clk1x:[R] clk1x:[R] 10.000 -0.012 4.803
12 4.871 u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_Empty_reg_s0/PRESET clk1x:[R] clk1x:[R] 10.000 -0.021 4.803
13 5.024 u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_Empty_reg_s0/PRESET clk1x:[R] clk1x:[R] 10.000 -0.055 4.684
14 5.024 u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rbin_1_s0/CLEAR clk1x:[R] clk1x:[R] 10.000 -0.055 4.684
15 5.024 u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rbin_2_s0/CLEAR clk1x:[R] clk1x:[R] 10.000 -0.055 4.684
16 5.024 u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rbin_3_s0/CLEAR clk1x:[R] clk1x:[R] 10.000 -0.055 4.684
17 5.043 u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq1_wptr_3_s0/CLEAR clk1x:[R] clk1x:[R] 10.000 -0.010 4.619
18 5.043 u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_wbin_2_s0/CLEAR clk1x:[R] clk1x:[R] 10.000 -0.010 4.619
19 5.043 u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_wbin_3_s0/CLEAR clk1x:[R] clk1x:[R] 10.000 -0.010 4.619
20 5.043 u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq2_wptr_3_s0/CLEAR clk1x:[R] clk1x:[R] 10.000 -0.010 4.619
21 5.053 u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_wptr_1_s0/CLEAR clk1x:[R] clk1x:[R] 10.000 -0.019 4.619
22 5.053 u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rbin_0_s0/CLEAR clk1x:[R] clk1x:[R] 10.000 -0.019 4.619
23 5.053 u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq2_wptr_1_s0/CLEAR clk1x:[R] clk1x:[R] 10.000 -0.019 4.619
24 5.053 u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq1_wptr_1_s0/CLEAR clk1x:[R] clk1x:[R] 10.000 -0.019 4.619
25 5.218 u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rq1_wptr_3_s0/CLEAR clk1x:[R] clk1x:[R] 10.000 -0.048 4.483

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 1.674 btn/out_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/wloadn_3_s0/CLEAR clkin:[R] clkin:[R] 0.000 0.028 1.457
2 1.694 u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_0_s0/CLEAR clk1x:[R] clk1x:[R] 0.000 -0.040 1.545
3 1.752 btn/out_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0/CLEAR clkin:[R] clkin:[R] 0.000 0.016 1.547
4 1.752 btn/out_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_syn_0_s0/CLEAR clkin:[R] clkin:[R] 0.000 0.016 1.547
5 1.752 btn/out_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_syn_1_s0/CLEAR clkin:[R] clkin:[R] 0.000 0.016 1.547
6 1.752 btn/out_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/stop_reg_0_s0/CLEAR clkin:[R] clkin:[R] 0.000 0.016 1.547
7 1.752 btn/out_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/stop_reg_1_s0/CLEAR clkin:[R] clkin:[R] 0.000 0.016 1.547
8 1.752 btn/out_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/stop_reg_2_s0/CLEAR clkin:[R] clkin:[R] 0.000 0.016 1.547
9 1.821 u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_Empty_reg_s0/PRESET clk1x:[R] clk1x:[R] 0.000 -0.040 1.672
10 1.826 u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_3_s0/CLEAR clk1x:[R] clk1x:[R] 0.000 -0.035 1.672
11 1.826 u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_1_s0/CLEAR clk1x:[R] clk1x:[R] 0.000 -0.035 1.672
12 1.826 u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_3_s0/CLEAR clk1x:[R] clk1x:[R] 0.000 -0.035 1.672
13 1.826 u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_3_s0/CLEAR clk1x:[R] clk1x:[R] 0.000 -0.035 1.672
14 1.868 u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_2_s0/CLEAR clk1x:[R] clk1x:[R] 0.000 -0.042 1.721
15 1.868 u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wptr_1_s0/CLEAR clk1x:[R] clk1x:[R] 0.000 -0.042 1.721
16 1.868 u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wptr_2_s0/CLEAR clk1x:[R] clk1x:[R] 0.000 -0.042 1.721
17 1.868 u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_1_s0/CLEAR clk1x:[R] clk1x:[R] 0.000 -0.042 1.721
18 1.868 u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_1_s0/CLEAR clk1x:[R] clk1x:[R] 0.000 -0.042 1.721
19 1.963 btn/out_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_d2_s0/CLEAR clkin:[R] clkin:[R] 0.000 0.004 1.770
20 1.965 btn/out_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_8_s1/CLEAR clkin:[R] clkin:[R] 0.000 0.007 1.770
21 1.965 btn/out_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_9_s1/CLEAR clkin:[R] clkin:[R] 0.000 0.007 1.770
22 1.965 btn/out_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_10_s1/CLEAR clkin:[R] clkin:[R] 0.000 0.007 1.770
23 1.965 btn/out_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/count_1_s0/CLEAR clkin:[R] clkin:[R] 0.000 0.007 1.770
24 1.990 u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_1_s0/CLEAR clk1x:[R] clk1x:[R] 0.000 -0.042 1.844
25 1.990 u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_2_s0/CLEAR clk1x:[R] clk1x:[R] 0.000 -0.042 1.844

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number Slack Actual Width Required Width Type Clock Objects
1 3.494 4.494 1.000 Low Pulse Width clk1x u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_3_s
2 3.494 4.494 1.000 Low Pulse Width clk1x u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_4_s
3 3.496 4.496 1.000 High Pulse Width clk1x u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_3_s
4 3.496 4.496 1.000 High Pulse Width clk1x u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_4_s
5 3.499 4.499 1.000 Low Pulse Width clk1x u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem8_mem8_0_2_s
6 3.499 4.499 1.000 Low Pulse Width clk1x u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s
7 3.499 4.499 1.000 Low Pulse Width clk1x u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s
8 3.499 4.499 1.000 Low Pulse Width clk1x u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s
9 3.499 4.499 1.000 Low Pulse Width clk1x u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem8_mem8_0_3_s
10 3.499 4.499 1.000 Low Pulse Width clk1x u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem8_mem8_0_5_s

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 0.036
Data Arrival Time 10.787
Data Required Time 10.822
From u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0
To u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_IDLE_s2
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.862 0.862 tNET RR 1 R29C39[1][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/CLK
1.244 0.382 tC2Q RR 128 R29C39[1][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/Q
3.198 1.954 tNET RR 1 R26C46[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s3/I2
3.488 0.290 tINS RF 1 R26C46[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s3/F
3.488 0.000 tNET FF 1 R26C46[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s1/I0
3.684 0.196 tINS FF 1 R26C46[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s1/O
3.684 0.000 tNET FF 1 R26C46[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s0/I0
3.786 0.101 tINS FF 7 R26C46[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s0/O
4.748 0.963 tNET FF 1 R18C43[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s82/I1
5.274 0.526 tINS FR 5 R18C43[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s82/F
6.168 0.894 tNET RR 1 R21C41[0][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_READ_s71/I0
6.694 0.526 tINS RR 2 R21C41[0][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_READ_s71/F
6.889 0.195 tNET RR 1 R21C39[3][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_IDLE_s71/I3
7.411 0.521 tINS RR 4 R21C39[3][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_IDLE_s71/F
8.306 0.895 tNET RR 1 R18C40[3][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_IDLE_s75/I0
8.803 0.498 tINS RR 8 R18C40[3][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_IDLE_s75/F
9.697 0.894 tNET RR 1 R21C42[3][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_IDLE_s68/I0
10.194 0.498 tINS RR 2 R21C42[3][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_IDLE_s68/F
10.787 0.592 tNET RR 1 R23C42[2][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_IDLE_s2/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk1x
10.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.886 0.886 tNET RR 1 R23C42[2][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_IDLE_s2/CLK
10.822 -0.064 tSu 1 R23C42[2][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_IDLE_s2

Path Statistics:

Clock Skew 0.024
Setup Relationship 10.000
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.862, 100.000%
Arrival Data Path Delay cell: 3.156, 31.801%; route: 6.386, 64.345%; tC2Q: 0.382, 3.854%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.886, 100.000%

Path2

Path Summary:

Slack 0.036
Data Arrival Time 10.787
Data Required Time 10.822
From u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0
To u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/idle1_s0
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.862 0.862 tNET RR 1 R29C39[1][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/CLK
1.244 0.382 tC2Q RR 128 R29C39[1][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/Q
3.198 1.954 tNET RR 1 R26C46[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s3/I2
3.488 0.290 tINS RF 1 R26C46[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s3/F
3.488 0.000 tNET FF 1 R26C46[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s1/I0
3.684 0.196 tINS FF 1 R26C46[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s1/O
3.684 0.000 tNET FF 1 R26C46[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s0/I0
3.786 0.101 tINS FF 7 R26C46[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s0/O
4.748 0.963 tNET FF 1 R18C43[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s82/I1
5.274 0.526 tINS FR 5 R18C43[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s82/F
6.168 0.894 tNET RR 1 R21C41[0][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_READ_s71/I0
6.694 0.526 tINS RR 2 R21C41[0][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_READ_s71/F
6.889 0.195 tNET RR 1 R21C39[3][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_IDLE_s71/I3
7.411 0.521 tINS RR 4 R21C39[3][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_IDLE_s71/F
8.306 0.895 tNET RR 1 R18C40[3][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_IDLE_s75/I0
8.803 0.498 tINS RR 8 R18C40[3][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_IDLE_s75/F
9.697 0.894 tNET RR 1 R21C42[3][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_IDLE_s68/I0
10.194 0.498 tINS RR 2 R21C42[3][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_IDLE_s68/F
10.787 0.592 tNET RR 1 R23C42[0][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/idle1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk1x
10.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.886 0.886 tNET RR 1 R23C42[0][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/idle1_s0/CLK
10.822 -0.064 tSu 1 R23C42[0][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/idle1_s0

Path Statistics:

Clock Skew 0.024
Setup Relationship 10.000
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.862, 100.000%
Arrival Data Path Delay cell: 3.156, 31.801%; route: 6.386, 64.345%; tC2Q: 0.382, 3.854%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.886, 100.000%

Path3

Path Summary:

Slack 0.114
Data Arrival Time 10.716
Data Required Time 10.829
From u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0
To u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_SREE_s2
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.862 0.862 tNET RR 1 R29C39[1][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/CLK
1.244 0.382 tC2Q RR 128 R29C39[1][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/Q
3.198 1.954 tNET RR 1 R26C46[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s3/I2
3.488 0.290 tINS RF 1 R26C46[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s3/F
3.488 0.000 tNET FF 1 R26C46[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s1/I0
3.684 0.196 tINS FF 1 R26C46[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s1/O
3.684 0.000 tNET FF 1 R26C46[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s0/I0
3.786 0.101 tINS FF 7 R26C46[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s0/O
4.748 0.963 tNET FF 1 R18C43[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s82/I1
5.274 0.526 tINS FR 5 R18C43[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s82/F
6.168 0.894 tNET RR 1 R21C41[0][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_READ_s71/I0
6.694 0.526 tINS RR 2 R21C41[0][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_READ_s71/F
6.889 0.195 tNET RR 1 R21C39[3][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_IDLE_s71/I3
7.411 0.521 tINS RR 4 R21C39[3][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_IDLE_s71/F
8.306 0.895 tNET RR 1 R18C40[3][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_IDLE_s75/I0
8.803 0.498 tINS RR 8 R18C40[3][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_IDLE_s75/F
10.254 1.451 tNET RR 1 R24C43[2][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_SREE_s53/I0
10.716 0.461 tINS RR 1 R24C43[2][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_SREE_s53/F
10.716 0.000 tNET RR 1 R24C43[2][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_SREE_s2/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk1x
10.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.893 0.893 tNET RR 1 R24C43[2][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_SREE_s2/CLK
10.829 -0.064 tSu 1 R24C43[2][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_SREE_s2

Path Statistics:

Clock Skew 0.031
Setup Relationship 10.000
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.862, 100.000%
Arrival Data Path Delay cell: 3.120, 31.663%; route: 6.351, 64.455%; tC2Q: 0.382, 3.882%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.893, 100.000%

Path4

Path Summary:

Slack 0.194
Data Arrival Time 10.636
Data Required Time 10.829
From u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0
To u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_SRE_s4
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.862 0.862 tNET RR 1 R29C39[1][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/CLK
1.244 0.382 tC2Q RR 128 R29C39[1][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/Q
3.198 1.954 tNET RR 1 R26C46[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s3/I2
3.488 0.290 tINS RF 1 R26C46[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s3/F
3.488 0.000 tNET FF 1 R26C46[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s1/I0
3.684 0.196 tINS FF 1 R26C46[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s1/O
3.684 0.000 tNET FF 1 R26C46[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s0/I0
3.786 0.101 tINS FF 7 R26C46[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s0/O
4.748 0.963 tNET FF 1 R18C43[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s82/I1
5.274 0.526 tINS FR 5 R18C43[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s82/F
6.168 0.894 tNET RR 1 R21C41[0][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_READ_s71/I0
6.694 0.526 tINS RR 2 R21C41[0][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_READ_s71/F
6.889 0.195 tNET RR 1 R21C39[3][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_IDLE_s71/I3
7.411 0.521 tINS RR 4 R21C39[3][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_IDLE_s71/F
8.306 0.895 tNET RR 1 R18C40[3][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_IDLE_s75/I0
8.803 0.498 tINS RR 8 R18C40[3][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_IDLE_s75/F
10.119 1.316 tNET RR 1 R24C43[2][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_SRE_s55/I0
10.636 0.516 tINS RR 1 R24C43[2][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_SRE_s55/F
10.636 0.000 tNET RR 1 R24C43[2][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_SRE_s4/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk1x
10.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.893 0.893 tNET RR 1 R24C43[2][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_SRE_s4/CLK
10.829 -0.064 tSu 1 R24C43[2][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_SRE_s4

Path Statistics:

Clock Skew 0.031
Setup Relationship 10.000
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.862, 100.000%
Arrival Data Path Delay cell: 3.175, 32.485%; route: 6.216, 63.601%; tC2Q: 0.382, 3.914%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.893, 100.000%

Path5

Path Summary:

Slack 0.633
Data Arrival Time 10.189
Data Required Time 10.822
From u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0
To u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_POWERON_s14
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.862 0.862 tNET RR 1 R29C39[1][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/CLK
1.244 0.382 tC2Q RR 128 R29C39[1][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/Q
3.198 1.954 tNET RR 1 R26C46[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s3/I2
3.488 0.290 tINS RF 1 R26C46[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s3/F
3.488 0.000 tNET FF 1 R26C46[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s1/I0
3.684 0.196 tINS FF 1 R26C46[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s1/O
3.684 0.000 tNET FF 1 R26C46[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s0/I0
3.786 0.101 tINS FF 7 R26C46[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s0/O
4.748 0.963 tNET FF 1 R18C43[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s82/I1
5.274 0.526 tINS FR 5 R18C43[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s82/F
6.168 0.894 tNET RR 1 R21C41[0][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_READ_s71/I0
6.694 0.526 tINS RR 2 R21C41[0][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_READ_s71/F
6.889 0.195 tNET RR 1 R21C39[3][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_IDLE_s71/I3
7.411 0.521 tINS RR 4 R21C39[3][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_IDLE_s71/F
8.306 0.895 tNET RR 1 R18C40[3][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_IDLE_s75/I0
8.803 0.498 tINS RR 8 R18C40[3][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_IDLE_s75/F
9.927 1.124 tNET RR 1 R23C38[0][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_POWERON_s52/I0
10.189 0.262 tINS RR 1 R23C38[0][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_POWERON_s52/F
10.189 0.000 tNET RR 1 R23C38[0][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_POWERON_s14/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk1x
10.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.886 0.886 tNET RR 1 R23C38[0][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_POWERON_s14/CLK
10.822 -0.064 tSu 1 R23C38[0][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_POWERON_s14

Path Statistics:

Clock Skew 0.024
Setup Relationship 10.000
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.862, 100.000%
Arrival Data Path Delay cell: 2.921, 31.319%; route: 6.024, 64.581%; tC2Q: 0.382, 4.101%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.886, 100.000%

Path6

Path Summary:

Slack 0.644
Data Arrival Time 10.178
Data Required Time 10.822
From u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0
To u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/idle2_s0
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.862 0.862 tNET RR 1 R29C39[1][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/CLK
1.244 0.382 tC2Q RR 128 R29C39[1][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/Q
3.198 1.954 tNET RR 1 R26C46[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s3/I2
3.488 0.290 tINS RF 1 R26C46[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s3/F
3.488 0.000 tNET FF 1 R26C46[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s1/I0
3.684 0.196 tINS FF 1 R26C46[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s1/O
3.684 0.000 tNET FF 1 R26C46[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s0/I0
3.786 0.101 tINS FF 7 R26C46[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s0/O
5.709 1.924 tNET FF 1 R18C43[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/cmd_write_Z_s/I1
6.231 0.521 tINS FR 5 R18C43[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/cmd_write_Z_s/F
7.297 1.066 tNET RR 1 R21C41[2][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s77/I2
7.823 0.526 tINS RR 1 R21C41[2][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s77/F
8.171 0.347 tNET RR 1 R22C40[0][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s71/I0
8.697 0.526 tINS RR 1 R22C40[0][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s71/F
8.854 0.157 tNET RR 1 R22C39[3][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s68/I3
9.376 0.521 tINS RR 2 R22C39[3][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s68/F
10.178 0.802 tNET RR 1 R23C42[1][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/idle2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk1x
10.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.886 0.886 tNET RR 1 R23C42[1][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/idle2_s0/CLK
10.822 -0.064 tSu 1 R23C42[1][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/idle2_s0

Path Statistics:

Clock Skew 0.024
Setup Relationship 10.000
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.862, 100.000%
Arrival Data Path Delay cell: 2.683, 28.794%; route: 6.251, 67.100%; tC2Q: 0.382, 4.106%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.886, 100.000%

Path7

Path Summary:

Slack 0.779
Data Arrival Time 10.026
Data Required Time 10.805
From u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_Empty_reg_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_Empty_reg_s0
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.869 0.869 tNET RR 1 R36C87[2][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_Empty_reg_s0/CLK
1.251 0.382 tC2Q RR 4 R36C87[2][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_Empty_reg_s0/Q
4.166 2.915 tNET RR 1 R9C77[3][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/n67_s2/I2
4.581 0.415 tINS RR 10 R9C77[3][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/n67_s2/F
7.217 2.636 tNET RR 1 R35C87[3][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rgraynext_1_s2/I2
7.482 0.265 tINS RR 6 R35C87[3][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rgraynext_1_s2/F
7.970 0.487 tNET RR 1 R36C87[3][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rgraynext_0_s1/I2
8.467 0.498 tINS RR 1 R36C87[3][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rgraynext_0_s1/F
8.605 0.137 tNET RR 2 R36C87[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/n31_s0/I0
9.161 0.556 tINS RF 1 R36C87[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/n31_s0/COUT
9.161 0.000 tNET FF 2 R36C87[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/n32_s0/CIN
9.211 0.050 tINS FR 1 R36C87[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/n32_s0/COUT
9.211 0.000 tNET RR 2 R36C87[1][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/n33_s0/CIN
9.261 0.050 tINS RF 1 R36C87[1][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/n33_s0/COUT
9.510 0.249 tNET FF 1 R36C87[2][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rempty_val_s1/I2
10.026 0.516 tINS FR 1 R36C87[2][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rempty_val_s1/F
10.026 0.000 tNET RR 1 R36C87[2][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_Empty_reg_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk1x
10.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.869 0.869 tNET RR 1 R36C87[2][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_Empty_reg_s0/CLK
10.805 -0.064 tSu 1 R36C87[2][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_Empty_reg_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.869, 100.000%
Arrival Data Path Delay cell: 2.350, 25.662%; route: 6.425, 70.161%; tC2Q: 0.382, 4.177%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.869, 100.000%

Path8

Path Summary:

Slack 0.819
Data Arrival Time 10.024
Data Required Time 10.843
From u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0
To u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_R2W_s6
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.862 0.862 tNET RR 1 R29C39[1][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/CLK
1.244 0.382 tC2Q RR 128 R29C39[1][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/Q
3.198 1.954 tNET RR 1 R26C46[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s3/I2
3.488 0.290 tINS RF 1 R26C46[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s3/F
3.488 0.000 tNET FF 1 R26C46[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s1/I0
3.684 0.196 tINS FF 1 R26C46[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s1/O
3.684 0.000 tNET FF 1 R26C46[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s0/I0
3.786 0.101 tINS FF 7 R26C46[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s0/O
4.748 0.963 tNET FF 1 R18C43[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s82/I1
5.274 0.526 tINS FR 5 R18C43[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s82/F
6.168 0.894 tNET RR 1 R21C41[0][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_READ_s71/I0
6.694 0.526 tINS RR 2 R21C41[0][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_READ_s71/F
6.889 0.195 tNET RR 1 R21C39[3][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_IDLE_s71/I3
7.411 0.521 tINS RR 4 R21C39[3][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_IDLE_s71/F
8.306 0.895 tNET RR 1 R18C40[3][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_IDLE_s75/I0
8.803 0.498 tINS RR 8 R18C40[3][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_IDLE_s75/F
9.734 0.931 tNET RR 1 R21C41[3][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_R2W_s54/I0
10.024 0.290 tINS RF 1 R21C41[3][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_R2W_s54/F
10.024 0.000 tNET FF 1 R21C41[3][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_R2W_s6/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk1x
10.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.901 0.901 tNET RR 1 R21C41[3][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_R2W_s6/CLK
10.843 -0.058 tSu 1 R21C41[3][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_R2W_s6

Path Statistics:

Clock Skew 0.039
Setup Relationship 10.000
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.862, 100.000%
Arrival Data Path Delay cell: 2.949, 32.183%; route: 5.831, 63.643%; tC2Q: 0.382, 4.175%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.901, 100.000%

Path9

Path Summary:

Slack 0.971
Data Arrival Time 9.878
Data Required Time 10.849
From u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0
To u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_ACT2RD_s6
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.862 0.862 tNET RR 1 R29C39[1][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/CLK
1.244 0.382 tC2Q RR 128 R29C39[1][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/Q
3.198 1.954 tNET RR 1 R26C46[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s3/I2
3.488 0.290 tINS RF 1 R26C46[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s3/F
3.488 0.000 tNET FF 1 R26C46[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s1/I0
3.684 0.196 tINS FF 1 R26C46[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s1/O
3.684 0.000 tNET FF 1 R26C46[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s0/I0
3.786 0.101 tINS FF 7 R26C46[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s0/O
4.748 0.963 tNET FF 1 R18C43[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s82/I1
5.274 0.526 tINS FR 5 R18C43[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s82/F
6.168 0.894 tNET RR 1 R21C41[0][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_READ_s71/I0
6.694 0.526 tINS RR 2 R21C41[0][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_READ_s71/F
6.889 0.195 tNET RR 1 R21C39[3][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_IDLE_s71/I3
7.411 0.521 tINS RR 4 R21C39[3][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_IDLE_s71/F
8.306 0.895 tNET RR 1 R18C40[3][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_IDLE_s75/I0
8.803 0.498 tINS RR 8 R18C40[3][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_IDLE_s75/F
9.352 0.549 tNET RR 1 R20C40[0][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_ACT2RD_s55/I0
9.878 0.526 tINS RR 1 R20C40[0][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_ACT2RD_s55/F
9.878 0.000 tNET RR 1 R20C40[0][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_ACT2RD_s6/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk1x
10.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.913 0.913 tNET RR 1 R20C40[0][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_ACT2RD_s6/CLK
10.849 -0.064 tSu 1 R20C40[0][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_ACT2RD_s6

Path Statistics:

Clock Skew 0.051
Setup Relationship 10.000
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.862, 100.000%
Arrival Data Path Delay cell: 3.185, 35.325%; route: 5.449, 60.433%; tC2Q: 0.382, 4.242%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.913, 100.000%

Path10

Path Summary:

Slack 0.994
Data Arrival Time 9.809
Data Required Time 10.803
From u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0
To u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_RP2AW_s10
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.862 0.862 tNET RR 1 R29C39[1][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/CLK
1.244 0.382 tC2Q RR 128 R29C39[1][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/Q
3.198 1.954 tNET RR 1 R26C46[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s3/I2
3.488 0.290 tINS RF 1 R26C46[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s3/F
3.488 0.000 tNET FF 1 R26C46[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s1/I0
3.684 0.196 tINS FF 1 R26C46[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s1/O
3.684 0.000 tNET FF 1 R26C46[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s0/I0
3.786 0.101 tINS FF 7 R26C46[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s0/O
4.748 0.963 tNET FF 1 R18C43[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s82/I1
5.274 0.526 tINS FR 5 R18C43[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s82/F
6.168 0.894 tNET RR 1 R21C41[0][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_READ_s71/I0
6.694 0.526 tINS RR 2 R21C41[0][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_READ_s71/F
6.889 0.195 tNET RR 1 R21C39[3][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_IDLE_s71/I3
7.411 0.521 tINS RR 4 R21C39[3][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_IDLE_s71/F
8.341 0.930 tNET RR 1 R18C41[2][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_RP2AW_s57/I3
8.603 0.262 tINS RR 4 R18C41[2][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_RP2AW_s57/F
9.283 0.680 tNET RR 1 R17C43[0][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_RP2AW_s56/I0
9.809 0.526 tINS RR 1 R17C43[0][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_RP2AW_s56/F
9.809 0.000 tNET RR 1 R17C43[0][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_RP2AW_s10/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk1x
10.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.867 0.867 tNET RR 1 R17C43[0][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_RP2AW_s10/CLK
10.803 -0.064 tSu 1 R17C43[0][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_RP2AW_s10

Path Statistics:

Clock Skew 0.005
Setup Relationship 10.000
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.862, 100.000%
Arrival Data Path Delay cell: 2.950, 32.970%; route: 5.615, 62.755%; tC2Q: 0.382, 4.275%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.867, 100.000%

Path11

Path Summary:

Slack 1.008
Data Arrival Time 9.814
Data Required Time 10.822
From u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_1_s0
To u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/idle3_s0
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.842 0.842 tNET RR 1 R31C38[2][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_1_s0/CLK
1.209 0.368 tC2Q RF 68 R31C38[2][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_1_s0/Q
2.791 1.581 tNET FF 1 R36C42[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_168_G[0]_s1/S0
3.043 0.252 tINS FR 1 R36C42[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_168_G[0]_s1/O
3.043 0.000 tNET RR 1 R36C42[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_168_G[0]_s0/I0
3.129 0.086 tINS RR 5 R36C42[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_168_G[0]_s0/O
5.106 1.976 tNET RR 1 R17C44[2][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s26/I2
5.567 0.461 tINS RR 1 R17C44[2][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s26/F
5.567 0.000 tNET RR 1 R17C44[2][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s23/I0
5.703 0.136 tINS RR 1 R17C44[2][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s23/O
5.703 0.000 tNET RR 1 R17C44[2][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s21/I1
5.789 0.086 tINS RR 3 R17C44[2][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s21/O
5.952 0.162 tNET RR 1 R17C44[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_W2R_s55/I2
6.468 0.516 tINS RR 4 R17C44[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_W2R_s55/F
7.587 1.119 tNET RR 1 R20C41[2][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_READ_s73/I2
8.048 0.461 tINS RR 1 R20C41[2][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_READ_s73/F
8.051 0.003 tNET RR 1 R20C41[3][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_READ_s69/I2
8.548 0.498 tINS RR 1 R20C41[3][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_READ_s69/F
8.551 0.003 tNET RR 1 R20C41[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_READ_s68/I1
9.012 0.461 tINS RR 2 R20C41[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_READ_s68/F
9.814 0.802 tNET RR 1 R23C42[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/idle3_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk1x
10.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.886 0.886 tNET RR 1 R23C42[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/idle3_s0/CLK
10.822 -0.064 tSu 1 R23C42[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/idle3_s0

Path Statistics:

Clock Skew 0.044
Setup Relationship 10.000
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.842, 100.000%
Arrival Data Path Delay cell: 2.959, 32.976%; route: 5.646, 62.928%; tC2Q: 0.368, 4.096%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.886, 100.000%

Path12

Path Summary:

Slack 1.056
Data Arrival Time 9.778
Data Required Time 10.834
From u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0
To u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_WRITE_s4
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.862 0.862 tNET RR 1 R29C39[1][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/CLK
1.244 0.382 tC2Q RR 128 R29C39[1][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/Q
3.198 1.954 tNET RR 1 R26C46[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s3/I2
3.488 0.290 tINS RF 1 R26C46[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s3/F
3.488 0.000 tNET FF 1 R26C46[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s1/I0
3.684 0.196 tINS FF 1 R26C46[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s1/O
3.684 0.000 tNET FF 1 R26C46[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s0/I0
3.786 0.101 tINS FF 7 R26C46[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s0/O
5.709 1.924 tNET FF 1 R18C43[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/cmd_write_Z_s/I1
6.231 0.521 tINS FR 5 R18C43[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/cmd_write_Z_s/F
7.297 1.066 tNET RR 1 R21C41[2][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s77/I2
7.823 0.526 tINS RR 1 R21C41[2][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s77/F
8.171 0.347 tNET RR 1 R22C40[0][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s71/I0
8.697 0.526 tINS RR 1 R22C40[0][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s71/F
8.854 0.157 tNET RR 1 R22C39[3][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s68/I3
9.376 0.521 tINS RR 2 R22C39[3][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s68/F
9.778 0.402 tNET RR 1 R22C39[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_WRITE_s4/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk1x
10.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.898 0.898 tNET RR 1 R22C39[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_WRITE_s4/CLK
10.834 -0.064 tSu 1 R22C39[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_WRITE_s4

Path Statistics:

Clock Skew 0.036
Setup Relationship 10.000
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.862, 100.000%
Arrival Data Path Delay cell: 2.683, 30.086%; route: 5.851, 65.625%; tC2Q: 0.382, 4.290%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.898, 100.000%

Path13

Path Summary:

Slack 1.174
Data Arrival Time 9.619
Data Required Time 10.794
From u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0
To u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_ACT2WR_s10
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.862 0.862 tNET RR 1 R29C39[1][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/CLK
1.244 0.382 tC2Q RR 128 R29C39[1][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/Q
3.198 1.954 tNET RR 1 R26C46[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s3/I2
3.488 0.290 tINS RF 1 R26C46[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s3/F
3.488 0.000 tNET FF 1 R26C46[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s1/I0
3.684 0.196 tINS FF 1 R26C46[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s1/O
3.684 0.000 tNET FF 1 R26C46[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s0/I0
3.786 0.101 tINS FF 7 R26C46[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s0/O
4.748 0.963 tNET FF 1 R18C43[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s82/I1
5.274 0.526 tINS FR 5 R18C43[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s82/F
6.168 0.894 tNET RR 1 R21C41[0][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_READ_s71/I0
6.694 0.526 tINS RR 2 R21C41[0][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_READ_s71/F
6.889 0.195 tNET RR 1 R21C39[3][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_IDLE_s71/I3
7.411 0.521 tINS RR 4 R21C39[3][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_IDLE_s71/F
8.306 0.895 tNET RR 1 R18C40[3][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_IDLE_s75/I0
8.803 0.498 tINS RR 8 R18C40[3][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_IDLE_s75/F
9.158 0.355 tNET RR 1 R17C42[1][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_ACT2WR_s55/I0
9.619 0.461 tINS RR 1 R17C42[1][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_ACT2WR_s55/F
9.619 0.000 tNET RR 1 R17C42[1][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_ACT2WR_s10/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk1x
10.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.858 0.857 tNET RR 1 R17C42[1][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_ACT2WR_s10/CLK
10.794 -0.064 tSu 1 R17C42[1][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_ACT2WR_s10

Path Statistics:

Clock Skew -0.004
Setup Relationship 10.000
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.862, 100.000%
Arrival Data Path Delay cell: 3.120, 35.627%; route: 5.255, 60.006%; tC2Q: 0.382, 4.368%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.857, 100.000%

Path14

Path Summary:

Slack 1.174
Data Arrival Time 9.619
Data Required Time 10.794
From u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0
To u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_W2R_s8
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.862 0.862 tNET RR 1 R29C39[1][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/CLK
1.244 0.382 tC2Q RR 128 R29C39[1][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/Q
3.198 1.954 tNET RR 1 R26C46[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s3/I2
3.488 0.290 tINS RF 1 R26C46[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s3/F
3.488 0.000 tNET FF 1 R26C46[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s1/I0
3.684 0.196 tINS FF 1 R26C46[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s1/O
3.684 0.000 tNET FF 1 R26C46[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s0/I0
3.786 0.101 tINS FF 7 R26C46[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s0/O
4.748 0.963 tNET FF 1 R18C43[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s82/I1
5.274 0.526 tINS FR 5 R18C43[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s82/F
6.168 0.894 tNET RR 1 R21C41[0][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_READ_s71/I0
6.694 0.526 tINS RR 2 R21C41[0][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_READ_s71/F
6.889 0.195 tNET RR 1 R21C39[3][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_IDLE_s71/I3
7.411 0.521 tINS RR 4 R21C39[3][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_IDLE_s71/F
8.306 0.895 tNET RR 1 R18C40[3][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_IDLE_s75/I0
8.803 0.498 tINS RR 8 R18C40[3][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_IDLE_s75/F
9.158 0.355 tNET RR 1 R17C42[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_W2R_s54/I2
9.619 0.461 tINS RR 1 R17C42[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_W2R_s54/F
9.619 0.000 tNET RR 1 R17C42[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_W2R_s8/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk1x
10.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.858 0.857 tNET RR 1 R17C42[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_W2R_s8/CLK
10.794 -0.064 tSu 1 R17C42[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_W2R_s8

Path Statistics:

Clock Skew -0.004
Setup Relationship 10.000
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.862, 100.000%
Arrival Data Path Delay cell: 3.120, 35.627%; route: 5.255, 60.006%; tC2Q: 0.382, 4.368%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.857, 100.000%

Path15

Path Summary:

Slack 1.386
Data Arrival Time 9.419
Data Required Time 10.805
From u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0
To u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_RP2SRE_s14
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.862 0.862 tNET RR 1 R29C39[1][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/CLK
1.244 0.382 tC2Q RR 128 R29C39[1][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/Q
3.198 1.954 tNET RR 1 R26C46[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s3/I2
3.488 0.290 tINS RF 1 R26C46[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s3/F
3.488 0.000 tNET FF 1 R26C46[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s1/I0
3.684 0.196 tINS FF 1 R26C46[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s1/O
3.684 0.000 tNET FF 1 R26C46[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s0/I0
3.786 0.101 tINS FF 7 R26C46[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s0/O
4.748 0.963 tNET FF 1 R18C43[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s82/I1
5.274 0.526 tINS FR 5 R18C43[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s82/F
6.168 0.894 tNET RR 1 R21C41[0][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_READ_s71/I0
6.694 0.526 tINS RR 2 R21C41[0][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_READ_s71/F
6.889 0.195 tNET RR 1 R21C39[3][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_IDLE_s71/I3
7.411 0.521 tINS RR 4 R21C39[3][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_IDLE_s71/F
8.341 0.930 tNET RR 1 R18C41[2][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_RP2AW_s57/I3
8.603 0.262 tINS RR 4 R18C41[2][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_RP2AW_s57/F
8.958 0.355 tNET RR 1 R18C43[0][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_RP2SRE_s54/I0
9.419 0.461 tINS RR 1 R18C43[0][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_RP2SRE_s54/F
9.419 0.000 tNET RR 1 R18C43[0][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_RP2SRE_s14/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk1x
10.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.869 0.869 tNET RR 1 R18C43[0][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_RP2SRE_s14/CLK
10.805 -0.064 tSu 1 R18C43[0][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_RP2SRE_s14

Path Statistics:

Clock Skew 0.007
Setup Relationship 10.000
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.862, 100.000%
Arrival Data Path Delay cell: 2.885, 33.713%; route: 5.290, 61.817%; tC2Q: 0.382, 4.470%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.869, 100.000%

Path16

Path Summary:

Slack 1.425
Data Arrival Time 9.414
Data Required Time 10.839
From u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_1_s0
To u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_READ_s6
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.842 0.842 tNET RR 1 R31C38[2][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_1_s0/CLK
1.209 0.368 tC2Q RF 68 R31C38[2][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_1_s0/Q
2.791 1.581 tNET FF 1 R36C42[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_168_G[0]_s1/S0
3.043 0.252 tINS FR 1 R36C42[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_168_G[0]_s1/O
3.043 0.000 tNET RR 1 R36C42[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_168_G[0]_s0/I0
3.129 0.086 tINS RR 5 R36C42[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_168_G[0]_s0/O
5.106 1.976 tNET RR 1 R17C44[2][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s26/I2
5.567 0.461 tINS RR 1 R17C44[2][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s26/F
5.567 0.000 tNET RR 1 R17C44[2][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s23/I0
5.703 0.136 tINS RR 1 R17C44[2][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s23/O
5.703 0.000 tNET RR 1 R17C44[2][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s21/I1
5.789 0.086 tINS RR 3 R17C44[2][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s21/O
5.952 0.162 tNET RR 1 R17C44[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_W2R_s55/I2
6.468 0.516 tINS RR 4 R17C44[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_W2R_s55/F
7.587 1.119 tNET RR 1 R20C41[2][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_READ_s73/I2
8.048 0.461 tINS RR 1 R20C41[2][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_READ_s73/F
8.051 0.003 tNET RR 1 R20C41[3][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_READ_s69/I2
8.548 0.498 tINS RR 1 R20C41[3][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_READ_s69/F
8.551 0.003 tNET RR 1 R20C41[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_READ_s68/I1
9.012 0.461 tINS RR 2 R20C41[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_READ_s68/F
9.414 0.402 tNET RR 1 R20C41[0][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_READ_s6/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk1x
10.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.903 0.903 tNET RR 1 R20C41[0][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_READ_s6/CLK
10.839 -0.064 tSu 1 R20C41[0][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_READ_s6

Path Statistics:

Clock Skew 0.061
Setup Relationship 10.000
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.842, 100.000%
Arrival Data Path Delay cell: 2.959, 34.514%; route: 5.246, 61.199%; tC2Q: 0.368, 4.287%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.903, 100.000%

Path17

Path Summary:

Slack 1.569
Data Arrival Time 9.227
Data Required Time 10.796
From u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0
To u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_RP2REF_s14
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.862 0.862 tNET RR 1 R29C39[1][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/CLK
1.244 0.382 tC2Q RR 128 R29C39[1][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/Q
3.198 1.954 tNET RR 1 R26C46[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s3/I2
3.488 0.290 tINS RF 1 R26C46[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s3/F
3.488 0.000 tNET FF 1 R26C46[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s1/I0
3.684 0.196 tINS FF 1 R26C46[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s1/O
3.684 0.000 tNET FF 1 R26C46[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s0/I0
3.786 0.101 tINS FF 7 R26C46[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s0/O
4.748 0.963 tNET FF 1 R18C43[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s82/I1
5.274 0.526 tINS FR 5 R18C43[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s82/F
6.168 0.894 tNET RR 1 R21C41[0][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_READ_s71/I0
6.694 0.526 tINS RR 2 R21C41[0][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_READ_s71/F
6.889 0.195 tNET RR 1 R21C39[3][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_IDLE_s71/I3
7.411 0.521 tINS RR 4 R21C39[3][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_IDLE_s71/F
8.341 0.930 tNET RR 1 R18C41[2][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_RP2AW_s57/I3
8.603 0.262 tINS RR 4 R18C41[2][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_RP2AW_s57/F
8.766 0.162 tNET RR 1 R18C42[1][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_RP2REF_s54/I0
9.227 0.461 tINS RR 1 R18C42[1][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_RP2REF_s54/F
9.227 0.000 tNET RR 1 R18C42[1][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_RP2REF_s14/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk1x
10.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.859 0.859 tNET RR 1 R18C42[1][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_RP2REF_s14/CLK
10.796 -0.064 tSu 1 R18C42[1][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_RP2REF_s14

Path Statistics:

Clock Skew -0.002
Setup Relationship 10.000
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.862, 100.000%
Arrival Data Path Delay cell: 2.885, 34.489%; route: 5.098, 60.938%; tC2Q: 0.382, 4.573%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.859, 100.000%

Path18

Path Summary:

Slack 1.735
Data Arrival Time 9.068
Data Required Time 10.803
From u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_1_s0
To u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_ACT_WR_s4
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.842 0.842 tNET RR 1 R31C38[2][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_1_s0/CLK
1.209 0.368 tC2Q RF 68 R31C38[2][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_1_s0/Q
2.791 1.581 tNET FF 1 R36C42[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_168_G[0]_s1/S0
3.043 0.252 tINS FR 1 R36C42[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_168_G[0]_s1/O
3.043 0.000 tNET RR 1 R36C42[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_168_G[0]_s0/I0
3.129 0.086 tINS RR 5 R36C42[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_168_G[0]_s0/O
5.106 1.976 tNET RR 1 R17C44[2][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s26/I2
5.567 0.461 tINS RR 1 R17C44[2][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s26/F
5.567 0.000 tNET RR 1 R17C44[2][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s23/I0
5.703 0.136 tINS RR 1 R17C44[2][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s23/O
5.703 0.000 tNET RR 1 R17C44[2][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s21/I1
5.789 0.086 tINS RR 3 R17C44[2][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s21/O
5.952 0.162 tNET RR 1 R17C44[1][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_ACT_WR_s71/I1
6.468 0.516 tINS RR 2 R17C44[1][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_ACT_WR_s71/F
7.143 0.675 tNET RR 1 R18C41[3][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_ACT_WR_s69/I1
7.641 0.498 tINS RR 1 R18C41[3][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_ACT_WR_s69/F
7.988 0.347 tNET RR 1 R17C42[2][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_ACT_WR_s66/I3
8.449 0.461 tINS RR 1 R17C42[2][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_ACT_WR_s66/F
8.607 0.157 tNET RR 1 R17C43[0][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_ACT_WR_s65/I2
9.068 0.461 tINS RR 1 R17C43[0][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_ACT_WR_s65/F
9.068 0.000 tNET RR 1 R17C43[0][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_ACT_WR_s4/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk1x
10.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.867 0.867 tNET RR 1 R17C43[0][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_ACT_WR_s4/CLK
10.803 -0.064 tSu 1 R17C43[0][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_ACT_WR_s4

Path Statistics:

Clock Skew 0.025
Setup Relationship 10.000
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.842, 100.000%
Arrival Data Path Delay cell: 2.959, 35.967%; route: 4.900, 59.565%; tC2Q: 0.368, 4.467%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.867, 100.000%

Path19

Path Summary:

Slack 1.736
Data Arrival Time 9.069
Data Required Time 10.805
From u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0
To u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_RP2AR_s6
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.862 0.862 tNET RR 1 R29C39[1][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/CLK
1.244 0.382 tC2Q RR 128 R29C39[1][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/Q
3.198 1.954 tNET RR 1 R26C46[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s3/I2
3.488 0.290 tINS RF 1 R26C46[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s3/F
3.488 0.000 tNET FF 1 R26C46[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s1/I0
3.684 0.196 tINS FF 1 R26C46[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s1/O
3.684 0.000 tNET FF 1 R26C46[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s0/I0
3.786 0.101 tINS FF 7 R26C46[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s0/O
4.748 0.963 tNET FF 1 R18C43[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s82/I1
5.274 0.526 tINS FR 5 R18C43[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s82/F
6.168 0.894 tNET RR 1 R21C41[0][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_READ_s71/I0
6.694 0.526 tINS RR 2 R21C41[0][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_READ_s71/F
6.889 0.195 tNET RR 1 R21C39[3][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_IDLE_s71/I3
7.411 0.521 tINS RR 4 R21C39[3][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_IDLE_s71/F
8.341 0.930 tNET RR 1 R18C41[2][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_RP2AW_s57/I3
8.603 0.262 tINS RR 4 R18C41[2][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_RP2AW_s57/F
8.608 0.005 tNET RR 1 R18C41[0][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_RP2AR_s55/I0
9.069 0.461 tINS RR 1 R18C41[0][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_RP2AR_s55/F
9.069 0.000 tNET RR 1 R18C41[0][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_RP2AR_s6/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk1x
10.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.869 0.869 tNET RR 1 R18C41[0][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_RP2AR_s6/CLK
10.805 -0.064 tSu 1 R18C41[0][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_RP2AR_s6

Path Statistics:

Clock Skew 0.007
Setup Relationship 10.000
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.862, 100.000%
Arrival Data Path Delay cell: 2.885, 35.151%; route: 4.940, 60.189%; tC2Q: 0.382, 4.660%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.869, 100.000%

Path20

Path Summary:

Slack 1.791
Data Arrival Time 9.058
Data Required Time 10.849
From u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_1_s0
To u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_ACT_RD_s4
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.842 0.842 tNET RR 1 R31C38[2][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_1_s0/CLK
1.209 0.368 tC2Q RF 68 R31C38[2][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_1_s0/Q
2.791 1.581 tNET FF 1 R36C42[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_168_G[0]_s1/S0
3.043 0.252 tINS FR 1 R36C42[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_168_G[0]_s1/O
3.043 0.000 tNET RR 1 R36C42[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_168_G[0]_s0/I0
3.129 0.086 tINS RR 5 R36C42[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_168_G[0]_s0/O
5.106 1.976 tNET RR 1 R17C44[2][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s26/I2
5.567 0.461 tINS RR 1 R17C44[2][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s26/F
5.567 0.000 tNET RR 1 R17C44[2][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s23/I0
5.703 0.136 tINS RR 1 R17C44[2][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s23/O
5.703 0.000 tNET RR 1 R17C44[2][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s21/I1
5.789 0.086 tINS RR 3 R17C44[2][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s21/O
5.952 0.162 tNET RR 1 R17C44[1][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_ACT_WR_s71/I1
6.468 0.516 tINS RR 2 R17C44[1][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_ACT_WR_s71/F
7.008 0.540 tNET RR 1 R18C41[2][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_ACT_RD_s70/I1
7.469 0.461 tINS RR 1 R18C41[2][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_ACT_RD_s70/F
8.302 0.833 tNET RR 1 R20C40[3][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_ACT_RD_s68/I3
8.592 0.290 tINS RF 1 R20C40[3][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_ACT_RD_s68/F
8.597 0.005 tNET FF 1 R20C40[1][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_ACT_RD_s67/I2
9.058 0.461 tINS FR 1 R20C40[1][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_ACT_RD_s67/F
9.058 0.000 tNET RR 1 R20C40[1][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_ACT_RD_s4/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk1x
10.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.913 0.913 tNET RR 1 R20C40[1][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_ACT_RD_s4/CLK
10.849 -0.064 tSu 1 R20C40[1][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_ACT_RD_s4

Path Statistics:

Clock Skew 0.071
Setup Relationship 10.000
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.842, 100.000%
Arrival Data Path Delay cell: 2.751, 33.485%; route: 5.097, 62.042%; tC2Q: 0.368, 4.473%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.913, 100.000%

Path21

Path Summary:

Slack 1.918
Data Arrival Time 8.896
Data Required Time 10.814
From u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_Empty_reg_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rbin_3_s0
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.869 0.869 tNET RR 1 R36C87[2][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_Empty_reg_s0/CLK
1.251 0.382 tC2Q RR 4 R36C87[2][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_Empty_reg_s0/Q
4.166 2.915 tNET RR 1 R9C77[3][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/n67_s2/I2
4.581 0.415 tINS RR 10 R9C77[3][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/n67_s2/F
7.217 2.636 tNET RR 1 R35C87[3][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rgraynext_1_s2/I2
7.482 0.265 tINS RR 6 R35C87[3][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rgraynext_1_s2/F
7.977 0.495 tNET RR 1 R36C88[2][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rbinnext_3_s2/I2
8.494 0.516 tINS RR 2 R36C88[2][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rbinnext_3_s2/F
8.896 0.402 tNET RR 1 R36C88[1][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rbin_3_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk1x
10.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.878 0.878 tNET RR 1 R36C88[1][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rbin_3_s0/CLK
10.814 -0.064 tSu 1 R36C88[1][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rbin_3_s0

Path Statistics:

Clock Skew 0.009
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.869, 100.000%
Arrival Data Path Delay cell: 1.196, 14.902%; route: 6.449, 80.333%; tC2Q: 0.382, 4.765%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.878, 100.000%

Path22

Path Summary:

Slack 1.945
Data Arrival Time 8.889
Data Required Time 10.834
From u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_1_s0
To u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_WP2AW_s12
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.842 0.842 tNET RR 1 R31C38[2][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_1_s0/CLK
1.209 0.368 tC2Q RF 68 R31C38[2][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_1_s0/Q
2.791 1.581 tNET FF 1 R36C42[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_168_G[0]_s1/S0
3.043 0.252 tINS FR 1 R36C42[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_168_G[0]_s1/O
3.043 0.000 tNET RR 1 R36C42[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_168_G[0]_s0/I0
3.129 0.086 tINS RR 5 R36C42[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_168_G[0]_s0/O
5.106 1.976 tNET RR 1 R17C44[2][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s26/I2
5.567 0.461 tINS RR 1 R17C44[2][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s26/F
5.567 0.000 tNET RR 1 R17C44[2][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s23/I0
5.703 0.136 tINS RR 1 R17C44[2][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s23/O
5.703 0.000 tNET RR 1 R17C44[2][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s21/I1
5.789 0.086 tINS RR 3 R17C44[2][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s21/O
5.984 0.195 tNET RR 1 R17C44[0][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WP2AR_s56/I0
6.501 0.516 tINS RR 4 R17C44[0][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WP2AR_s56/F
7.964 1.464 tNET RR 1 R22C39[2][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WP2AW_s61/I3
8.426 0.461 tINS RR 1 R22C39[2][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WP2AW_s61/F
8.428 0.003 tNET RR 1 R22C39[1][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WP2AW_s60/I3
8.889 0.461 tINS RR 1 R22C39[1][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WP2AW_s60/F
8.889 0.000 tNET RR 1 R22C39[1][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_WP2AW_s12/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk1x
10.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.898 0.898 tNET RR 1 R22C39[1][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_WP2AW_s12/CLK
10.834 -0.064 tSu 1 R22C39[1][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_WP2AW_s12

Path Statistics:

Clock Skew 0.056
Setup Relationship 10.000
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.842, 100.000%
Arrival Data Path Delay cell: 2.461, 30.584%; route: 5.219, 64.849%; tC2Q: 0.368, 4.567%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.898, 100.000%

Path23

Path Summary:

Slack 1.970
Data Arrival Time 8.862
Data Required Time 10.832
From u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0
To u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_ZQ_s14
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.862 0.862 tNET RR 1 R29C39[1][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/CLK
1.244 0.382 tC2Q RR 128 R29C39[1][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/Q
3.198 1.954 tNET RR 1 R26C46[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s3/I2
3.488 0.290 tINS RF 1 R26C46[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s3/F
3.488 0.000 tNET FF 1 R26C46[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s1/I0
3.684 0.196 tINS FF 1 R26C46[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s1/O
3.684 0.000 tNET FF 1 R26C46[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s0/I0
3.786 0.101 tINS FF 7 R26C46[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s0/O
4.748 0.963 tNET FF 1 R18C43[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s82/I1
5.274 0.526 tINS FR 5 R18C43[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s82/F
6.169 0.895 tNET RR 1 R21C42[0][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_SREI_s59/I0
6.686 0.516 tINS RR 3 R21C42[0][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_SREI_s59/F
7.363 0.677 tNET RR 1 R23C39[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_ZQ_s58/I0
7.879 0.516 tINS RR 1 R23C39[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_ZQ_s58/F
7.882 0.003 tNET RR 1 R23C39[2][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_ZQ_s57/I2
8.398 0.516 tINS RR 1 R23C39[2][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_ZQ_s57/F
8.401 0.003 tNET RR 1 R23C39[0][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_ZQ_s55/I2
8.862 0.461 tINS RR 1 R23C39[0][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_ZQ_s55/F
8.862 0.000 tNET RR 1 R23C39[0][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_ZQ_s14/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk1x
10.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.896 0.896 tNET RR 1 R23C39[0][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_ZQ_s14/CLK
10.832 -0.064 tSu 1 R23C39[0][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_ZQ_s14

Path Statistics:

Clock Skew 0.034
Setup Relationship 10.000
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.862, 100.000%
Arrival Data Path Delay cell: 3.124, 39.047%; route: 4.494, 56.172%; tC2Q: 0.382, 4.781%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.896, 100.000%

Path24

Path Summary:

Slack 1.989
Data Arrival Time 8.843
Data Required Time 10.832
From u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0
To u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_REF_s4
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.862 0.862 tNET RR 1 R29C39[1][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/CLK
1.244 0.382 tC2Q RR 128 R29C39[1][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_2_s0/Q
3.198 1.954 tNET RR 1 R26C46[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s3/I2
3.488 0.290 tINS RF 1 R26C46[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s3/F
3.488 0.000 tNET FF 1 R26C46[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s1/I0
3.684 0.196 tINS FF 1 R26C46[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s1/O
3.684 0.000 tNET FF 1 R26C46[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s0/I0
3.786 0.101 tINS FF 7 R26C46[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_189_G[0]_s0/O
4.748 0.963 tNET FF 1 R18C43[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s82/I1
5.274 0.526 tINS FR 5 R18C43[1][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s82/F
6.169 0.895 tNET RR 1 R21C42[0][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_SREI_s59/I0
6.686 0.516 tINS RR 3 R21C42[0][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_SREI_s59/F
7.363 0.677 tNET RR 1 R23C39[2][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_REF_s65/I1
7.879 0.516 tINS RR 1 R23C39[2][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_REF_s65/F
7.882 0.003 tNET RR 1 R23C39[3][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_REF_s62/I1
8.379 0.498 tINS RR 1 R23C39[3][A] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_REF_s62/F
8.382 0.003 tNET RR 1 R23C39[0][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_REF_s57/I2
8.843 0.461 tINS RR 1 R23C39[0][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_REF_s57/F
8.843 0.000 tNET RR 1 R23C39[0][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_REF_s4/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk1x
10.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.896 0.896 tNET RR 1 R23C39[0][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_REF_s4/CLK
10.832 -0.064 tSu 1 R23C39[0][B] u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_REF_s4

Path Statistics:

Clock Skew 0.034
Setup Relationship 10.000
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.862, 100.000%
Arrival Data Path Delay cell: 3.105, 38.904%; route: 4.494, 56.304%; tC2Q: 0.382, 4.792%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.896, 100.000%

Path25

Path Summary:

Slack 2.004
Data Arrival Time 0.496
Data Required Time 2.500
From u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem
Launch Clk clk4x:[R]
Latch Clk clk4x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk4x
0.000 0.000 tCL RR 102 PLL_T Gowin_PLL_inst/PLLA_inst/CLKOUT2
0.000 0.000 tNET RR 5 R38C64 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.496 0.496 tC2Q RF 8 R38C64 u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2]
0.496 0.000 tNET FF 1 IOB71[B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem/RADDR[2]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
2.500 2.500 active clock edge time
2.500 0.000 clk4x
2.500 0.000 tCL RR 102 PLL_T Gowin_PLL_inst/PLLA_inst/CLKOUT2
2.500 0.000 tNET RR 1 IOB71[B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem/FCLK
2.500 0.000 tSu 1 IOB71[B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem

Path Statistics:

Clock Skew 0.000
Setup Relationship 2.500
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 0.048
Data Arrival Time 0.671
Data Required Time 0.623
From u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_mask_r_11_s0
To u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_7_s
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.375 0.375 tNET RR 1 R9C57[0][B] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_mask_r_11_s0/CLK
0.555 0.180 tC2Q RR 1 R9C57[0][B] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_mask_r_11_s0/Q
0.671 0.116 tNET RR 1 BSRAM_R10[17] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_7_s/DI[15]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.374 0.374 tNET RR 1 BSRAM_R10[17] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_7_s/CLKA
0.623 0.249 tHld 1 BSRAM_R10[17] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_7_s

Path Statistics:

Clock Skew -0.001
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.116, 39.241%; tC2Q: 0.180, 60.759%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.374, 100.000%

Path2

Path Summary:

Slack 0.067
Data Arrival Time 0.694
Data Required Time 0.627
From u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_150_s0
To u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_4_s
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.391 0.391 tNET RR 1 R8C47[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_150_s0/CLK
0.571 0.180 tC2Q RR 1 R8C47[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_150_s0/Q
0.694 0.124 tNET RR 1 BSRAM_R10[14] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_4_s/DI[6]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.378 0.378 tNET RR 1 BSRAM_R10[14] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_4_s/CLKA
0.627 0.249 tHld 1 BSRAM_R10[14] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_4_s

Path Statistics:

Clock Skew -0.012
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.391, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.124, 40.741%; tC2Q: 0.180, 59.259%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.378, 100.000%

Path3

Path Summary:

Slack 0.077
Data Arrival Time 0.690
Data Required Time 0.613
From u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_214_s0
To u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_5_s
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.386 0.386 tNET RR 1 R8C52[2][A] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_214_s0/CLK
0.566 0.180 tC2Q RR 1 R8C52[2][A] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_214_s0/Q
0.690 0.124 tNET RR 1 BSRAM_R10[15] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_5_s/DI[34]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.364 0.364 tNET RR 1 BSRAM_R10[15] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_5_s/CLKA
0.613 0.249 tHld 1 BSRAM_R10[15] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_5_s

Path Statistics:

Clock Skew -0.023
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.386, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.124, 40.741%; tC2Q: 0.180, 59.259%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.364, 100.000%

Path4

Path Summary:

Slack 0.077
Data Arrival Time 0.690
Data Required Time 0.613
From u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_210_s0
To u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_5_s
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.386 0.386 tNET RR 1 R8C52[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_210_s0/CLK
0.566 0.180 tC2Q RR 1 R8C52[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_210_s0/Q
0.690 0.124 tNET RR 1 BSRAM_R10[15] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_5_s/DI[30]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.364 0.364 tNET RR 1 BSRAM_R10[15] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_5_s/CLKA
0.613 0.249 tHld 1 BSRAM_R10[15] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_5_s

Path Statistics:

Clock Skew -0.023
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.386, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.124, 40.741%; tC2Q: 0.180, 59.259%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.364, 100.000%

Path5

Path Summary:

Slack 0.078
Data Arrival Time 0.696
Data Required Time 0.618
From u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_229_s0
To u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_6_s
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.390 0.390 tNET RR 1 R6C53[1][B] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_229_s0/CLK
0.570 0.180 tC2Q RR 1 R6C53[1][B] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_229_s0/Q
0.696 0.126 tNET RR 1 BSRAM_R10[16] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_6_s/DI[13]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.369 0.369 tNET RR 1 BSRAM_R10[16] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_6_s/CLKA
0.618 0.249 tHld 1 BSRAM_R10[16] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_6_s

Path Statistics:

Clock Skew -0.021
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.390, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.126, 41.224%; tC2Q: 0.180, 58.776%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.369, 100.000%

Path6

Path Summary:

Slack 0.086
Data Arrival Time 0.708
Data Required Time 0.623
From u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_mask_r_4_s0
To u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_7_s
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.390 0.390 tNET RR 1 R6C55[1][B] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_mask_r_4_s0/CLK
0.570 0.180 tC2Q RR 1 R6C55[1][B] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_mask_r_4_s0/Q
0.708 0.139 tNET RR 1 BSRAM_R10[17] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_7_s/DI[8]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.374 0.374 tNET RR 1 BSRAM_R10[17] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_7_s/CLKA
0.623 0.249 tHld 1 BSRAM_R10[17] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_7_s

Path Statistics:

Clock Skew -0.016
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.390, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.139, 43.529%; tC2Q: 0.180, 56.471%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.374, 100.000%

Path7

Path Summary:

Slack 0.154
Data Arrival Time 0.781
Data Required Time 0.627
From u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_146_s0
To u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_4_s
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.381 0.381 tNET RR 1 R8C51[0][B] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_146_s0/CLK
0.561 0.180 tC2Q RR 1 R8C51[0][B] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_146_s0/Q
0.781 0.220 tNET RR 1 BSRAM_R10[14] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_4_s/DI[2]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.378 0.378 tNET RR 1 BSRAM_R10[14] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_4_s/CLKA
0.627 0.249 tHld 1 BSRAM_R10[14] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_4_s

Path Statistics:

Clock Skew -0.003
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.381, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.220, 55.000%; tC2Q: 0.180, 45.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.378, 100.000%

Path8

Path Summary:

Slack 0.161
Data Arrival Time 0.788
Data Required Time 0.627
From u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_152_s0
To u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_4_s
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.391 0.391 tNET RR 1 R8C47[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_152_s0/CLK
0.571 0.180 tC2Q RR 1 R8C47[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_152_s0/Q
0.788 0.217 tNET RR 1 BSRAM_R10[14] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_4_s/DI[8]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.378 0.378 tNET RR 1 BSRAM_R10[14] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_4_s/CLKA
0.627 0.249 tHld 1 BSRAM_R10[14] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_4_s

Path Statistics:

Clock Skew -0.012
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.391, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.217, 54.717%; tC2Q: 0.180, 45.283%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.378, 100.000%

Path9

Path Summary:

Slack 0.161
Data Arrival Time 0.779
Data Required Time 0.618
From u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_218_s0
To u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_6_s
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.381 0.381 tNET RR 1 R8C53[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_218_s0/CLK
0.561 0.180 tC2Q RR 1 R8C53[2][B] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_218_s0/Q
0.779 0.217 tNET RR 1 BSRAM_R10[16] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_6_s/DI[2]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.369 0.369 tNET RR 1 BSRAM_R10[16] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_6_s/CLKA
0.618 0.249 tHld 1 BSRAM_R10[16] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_6_s

Path Statistics:

Clock Skew -0.013
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.381, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.217, 54.717%; tC2Q: 0.180, 45.283%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.369, 100.000%

Path10

Path Summary:

Slack 0.161
Data Arrival Time 0.779
Data Required Time 0.618
From u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_216_s0
To u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_6_s
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.381 0.381 tNET RR 1 R8C53[2][A] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_216_s0/CLK
0.561 0.180 tC2Q RR 1 R8C53[2][A] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_216_s0/Q
0.779 0.217 tNET RR 1 BSRAM_R10[16] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_6_s/DI[0]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.369 0.369 tNET RR 1 BSRAM_R10[16] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_6_s/CLKA
0.618 0.249 tHld 1 BSRAM_R10[16] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_6_s

Path Statistics:

Clock Skew -0.013
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.381, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.217, 54.717%; tC2Q: 0.180, 45.283%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.369, 100.000%

Path11

Path Summary:

Slack 0.174
Data Arrival Time 0.786
Data Required Time 0.613
From u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_63_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.370 0.370 tNET RR 1 R9C90[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_63_s0/CLK
0.550 0.180 tC2Q RR 1 R9C90[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_63_s0/Q
0.786 0.236 tNET RR 1 BSRAM_R10[27] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/DI[31]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.364 0.364 tNET RR 1 BSRAM_R10[27] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/CLKA
0.613 0.249 tHld 1 BSRAM_R10[27] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s

Path Statistics:

Clock Skew -0.006
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.370, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.236, 56.757%; tC2Q: 0.180, 43.243%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.364, 100.000%

Path12

Path Summary:

Slack 0.174
Data Arrival Time 0.786
Data Required Time 0.613
From u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_62_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.370 0.370 tNET RR 1 R9C90[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_62_s0/CLK
0.550 0.180 tC2Q RR 1 R9C90[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_62_s0/Q
0.786 0.236 tNET RR 1 BSRAM_R10[27] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/DI[30]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.364 0.364 tNET RR 1 BSRAM_R10[27] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/CLKA
0.613 0.249 tHld 1 BSRAM_R10[27] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s

Path Statistics:

Clock Skew -0.006
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.370, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.236, 56.757%; tC2Q: 0.180, 43.243%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.364, 100.000%

Path13

Path Summary:

Slack 0.174
Data Arrival Time 0.786
Data Required Time 0.613
From u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_60_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.370 0.370 tNET RR 1 R9C90[1][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_60_s0/CLK
0.550 0.180 tC2Q RR 1 R9C90[1][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_60_s0/Q
0.786 0.236 tNET RR 1 BSRAM_R10[27] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/DI[28]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.364 0.364 tNET RR 1 BSRAM_R10[27] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/CLKA
0.613 0.249 tHld 1 BSRAM_R10[27] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s

Path Statistics:

Clock Skew -0.006
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.370, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.236, 56.757%; tC2Q: 0.180, 43.243%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.364, 100.000%

Path14

Path Summary:

Slack 0.174
Data Arrival Time 0.786
Data Required Time 0.613
From u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_56_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.370 0.370 tNET RR 1 R9C90[2][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_56_s0/CLK
0.550 0.180 tC2Q RR 1 R9C90[2][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_56_s0/Q
0.786 0.236 tNET RR 1 BSRAM_R10[27] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/DI[24]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.364 0.364 tNET RR 1 BSRAM_R10[27] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/CLKA
0.613 0.249 tHld 1 BSRAM_R10[27] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s

Path Statistics:

Clock Skew -0.006
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.370, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.236, 56.757%; tC2Q: 0.180, 43.243%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.364, 100.000%

Path15

Path Summary:

Slack 0.174
Data Arrival Time 0.797
Data Required Time 0.623
From u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_mask_r_1_s0
To u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_7_s
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.385 0.385 tNET RR 1 R6C54[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_mask_r_1_s0/CLK
0.565 0.180 tC2Q RR 1 R6C54[3][A] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_mask_r_1_s0/Q
0.797 0.232 tNET RR 1 BSRAM_R10[17] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_7_s/DI[5]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.374 0.374 tNET RR 1 BSRAM_R10[17] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_7_s/CLKA
0.623 0.249 tHld 1 BSRAM_R10[17] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_7_s

Path Statistics:

Clock Skew -0.011
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.385, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.232, 56.364%; tC2Q: 0.180, 43.636%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.374, 100.000%

Path16

Path Summary:

Slack 0.178
Data Arrival Time 0.791
Data Required Time 0.613
From u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_61_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.375 0.375 tNET RR 1 R9C89[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_61_s0/CLK
0.555 0.180 tC2Q RR 1 R9C89[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_61_s0/Q
0.791 0.236 tNET RR 1 BSRAM_R10[27] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/DI[29]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.364 0.364 tNET RR 1 BSRAM_R10[27] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/CLKA
0.613 0.249 tHld 1 BSRAM_R10[27] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s

Path Statistics:

Clock Skew -0.011
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.236, 56.757%; tC2Q: 0.180, 43.243%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.364, 100.000%

Path17

Path Summary:

Slack 0.178
Data Arrival Time 0.791
Data Required Time 0.613
From u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_59_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.375 0.375 tNET RR 1 R9C89[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_59_s0/CLK
0.555 0.180 tC2Q RR 1 R9C89[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_59_s0/Q
0.791 0.236 tNET RR 1 BSRAM_R10[27] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/DI[27]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.364 0.364 tNET RR 1 BSRAM_R10[27] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/CLKA
0.613 0.249 tHld 1 BSRAM_R10[27] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s

Path Statistics:

Clock Skew -0.011
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.236, 56.757%; tC2Q: 0.180, 43.243%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.364, 100.000%

Path18

Path Summary:

Slack 0.178
Data Arrival Time 0.791
Data Required Time 0.613
From u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_57_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.375 0.375 tNET RR 1 R9C89[1][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_57_s0/CLK
0.555 0.180 tC2Q RR 1 R9C89[1][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_57_s0/Q
0.791 0.236 tNET RR 1 BSRAM_R10[27] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/DI[25]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.364 0.364 tNET RR 1 BSRAM_R10[27] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/CLKA
0.613 0.249 tHld 1 BSRAM_R10[27] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s

Path Statistics:

Clock Skew -0.011
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.236, 56.757%; tC2Q: 0.180, 43.243%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.364, 100.000%

Path19

Path Summary:

Slack 0.178
Data Arrival Time 0.796
Data Required Time 0.618
From u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_87_s0
To u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_2_s
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.380 0.380 tNET RR 1 R9C40[0][B] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_87_s0/CLK
0.560 0.180 tC2Q RR 1 R9C40[0][B] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_87_s0/Q
0.796 0.236 tNET RR 1 BSRAM_R10[12] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_2_s/DI[15]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.369 0.369 tNET RR 1 BSRAM_R10[12] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_2_s/CLKA
0.618 0.249 tHld 1 BSRAM_R10[12] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_2_s

Path Statistics:

Clock Skew -0.011
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.380, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.236, 56.757%; tC2Q: 0.180, 43.243%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.369, 100.000%

Path20

Path Summary:

Slack 0.178
Data Arrival Time 0.796
Data Required Time 0.618
From u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_86_s0
To u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_2_s
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.380 0.380 tNET RR 1 R9C40[0][A] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_86_s0/CLK
0.560 0.180 tC2Q RR 1 R9C40[0][A] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_86_s0/Q
0.796 0.236 tNET RR 1 BSRAM_R10[12] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_2_s/DI[14]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.369 0.369 tNET RR 1 BSRAM_R10[12] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_2_s/CLKA
0.618 0.249 tHld 1 BSRAM_R10[12] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_2_s

Path Statistics:

Clock Skew -0.011
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.380, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.236, 56.757%; tC2Q: 0.180, 43.243%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.369, 100.000%

Path21

Path Summary:

Slack 0.179
Data Arrival Time 0.806
Data Required Time 0.627
From u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_151_s0
To u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_4_s
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.387 0.387 tNET RR 1 R7C49[1][A] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_151_s0/CLK
0.567 0.180 tC2Q RR 1 R7C49[1][A] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_151_s0/Q
0.806 0.239 tNET RR 1 BSRAM_R10[14] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_4_s/DI[7]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.378 0.378 tNET RR 1 BSRAM_R10[14] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_4_s/CLKA
0.627 0.249 tHld 1 BSRAM_R10[14] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_4_s

Path Statistics:

Clock Skew -0.009
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.387, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.239, 57.015%; tC2Q: 0.180, 42.985%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.378, 100.000%

Path22

Path Summary:

Slack 0.180
Data Arrival Time 0.793
Data Required Time 0.613
From u_ddr3/gw3_top/u_ddr_phy_top/mux_wrdata_248_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem8_mem8_0_4_s
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.376 0.376 tNET RR 1 R26C74[1][B] u_ddr3/gw3_top/u_ddr_phy_top/mux_wrdata_248_s0/CLK
0.556 0.180 tC2Q RR 1 R26C74[1][B] u_ddr3/gw3_top/u_ddr_phy_top/mux_wrdata_248_s0/Q
0.793 0.236 tNET RR 1 BSRAM_R28[23] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem8_mem8_0_4_s/DI[15]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.364 0.364 tNET RR 1 BSRAM_R28[23] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem8_mem8_0_4_s/CLKA
0.613 0.249 tHld 1 BSRAM_R28[23] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem8_mem8_0_4_s

Path Statistics:

Clock Skew -0.013
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.376, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.236, 56.757%; tC2Q: 0.180, 43.243%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.364, 100.000%

Path23

Path Summary:

Slack 0.180
Data Arrival Time 0.798
Data Required Time 0.618
From u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_230_s0
To u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_6_s
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.381 0.381 tNET RR 1 R8C53[0][A] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_230_s0/CLK
0.561 0.180 tC2Q RR 1 R8C53[0][A] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_230_s0/Q
0.798 0.236 tNET RR 1 BSRAM_R10[16] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_6_s/DI[14]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.369 0.369 tNET RR 1 BSRAM_R10[16] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_6_s/CLKA
0.618 0.249 tHld 1 BSRAM_R10[16] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_6_s

Path Statistics:

Clock Skew -0.013
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.381, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.236, 56.757%; tC2Q: 0.180, 43.243%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.369, 100.000%

Path24

Path Summary:

Slack 0.186
Data Arrival Time 0.808
Data Required Time 0.623
From u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_136_s0
To u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_3_s
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.390 0.390 tNET RR 1 R6C43[0][A] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_136_s0/CLK
0.570 0.180 tC2Q RR 1 R6C43[0][A] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_136_s0/Q
0.808 0.239 tNET RR 1 BSRAM_R10[13] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_3_s/DI[28]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.374 0.374 tNET RR 1 BSRAM_R10[13] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_3_s/CLKA
0.623 0.249 tHld 1 BSRAM_R10[13] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_3_s

Path Statistics:

Clock Skew -0.016
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.390, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.239, 57.015%; tC2Q: 0.180, 42.985%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.374, 100.000%

Path25

Path Summary:

Slack 0.186
Data Arrival Time 0.813
Data Required Time 0.627
From u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_170_s0
To u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_4_s
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.390 0.390 tNET RR 1 R6C49[0][B] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_170_s0/CLK
0.570 0.180 tC2Q RR 1 R6C49[0][B] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_170_s0/Q
0.813 0.244 tNET RR 1 BSRAM_R10[14] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_4_s/DI[26]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.378 0.378 tNET RR 1 BSRAM_R10[14] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_4_s/CLKA
0.627 0.249 tHld 1 BSRAM_R10[14] u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_4_s

Path Statistics:

Clock Skew -0.012
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.390, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.244, 57.522%; tC2Q: 0.180, 42.478%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.378, 100.000%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 4.662
Data Arrival Time 5.869
Data Required Time 10.531
From u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rbin_1_s0
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.848 0.848 tNET RR 1 R32C66[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
1.230 0.382 tC2Q RR 1 R32C66[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
1.368 0.137 tNET RR 1 R32C66[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
1.758 0.390 tINS RF 80 R32C66[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
5.869 4.111 tNET FF 1 R36C88[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rbin_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk1x
10.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.878 0.878 tNET RR 1 R36C88[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rbin_1_s0/CLK
10.531 -0.347 tSu 1 R36C88[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rbin_1_s0

Path Statistics:

Clock Skew 0.030
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.848, 100.000%
Arrival Data Path Delay cell: 0.390, 7.767%; route: 4.249, 84.615%; tC2Q: 0.382, 7.618%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.878, 100.000%

Path2

Path Summary:

Slack 4.662
Data Arrival Time 5.869
Data Required Time 10.531
From u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rbin_2_s0
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.848 0.848 tNET RR 1 R32C66[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
1.230 0.382 tC2Q RR 1 R32C66[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
1.368 0.137 tNET RR 1 R32C66[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
1.758 0.390 tINS RF 80 R32C66[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
5.869 4.111 tNET FF 1 R36C88[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rbin_2_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk1x
10.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.878 0.878 tNET RR 1 R36C88[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rbin_2_s0/CLK
10.531 -0.347 tSu 1 R36C88[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rbin_2_s0

Path Statistics:

Clock Skew 0.030
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.848, 100.000%
Arrival Data Path Delay cell: 0.390, 7.767%; route: 4.249, 84.615%; tC2Q: 0.382, 7.618%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.878, 100.000%

Path3

Path Summary:

Slack 4.662
Data Arrival Time 5.869
Data Required Time 10.531
From u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rbin_3_s0
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.848 0.848 tNET RR 1 R32C66[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
1.230 0.382 tC2Q RR 1 R32C66[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
1.368 0.137 tNET RR 1 R32C66[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
1.758 0.390 tINS RF 80 R32C66[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
5.869 4.111 tNET FF 1 R36C88[1][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rbin_3_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk1x
10.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.878 0.878 tNET RR 1 R36C88[1][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rbin_3_s0/CLK
10.531 -0.347 tSu 1 R36C88[1][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rbin_3_s0

Path Statistics:

Clock Skew 0.030
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.848, 100.000%
Arrival Data Path Delay cell: 0.390, 7.767%; route: 4.249, 84.615%; tC2Q: 0.382, 7.618%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.878, 100.000%

Path4

Path Summary:

Slack 4.852
Data Arrival Time 5.677
Data Required Time 10.529
From u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_wbin_1_s0
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.848 0.848 tNET RR 1 R32C66[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
1.230 0.382 tC2Q RR 1 R32C66[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
1.368 0.137 tNET RR 1 R32C66[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
1.758 0.390 tINS RF 80 R32C66[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
5.677 3.919 tNET FF 1 R35C88[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_wbin_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk1x
10.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.876 0.876 tNET RR 1 R35C88[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_wbin_1_s0/CLK
10.529 -0.347 tSu 1 R35C88[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_wbin_1_s0

Path Statistics:

Clock Skew 0.028
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.848, 100.000%
Arrival Data Path Delay cell: 0.390, 8.077%; route: 4.056, 84.002%; tC2Q: 0.382, 7.921%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.876, 100.000%

Path5

Path Summary:

Slack 4.852
Data Arrival Time 5.677
Data Required Time 10.529
From u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_wptr_0_s0
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.848 0.848 tNET RR 1 R32C66[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
1.230 0.382 tC2Q RR 1 R32C66[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
1.368 0.137 tNET RR 1 R32C66[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
1.758 0.390 tINS RF 80 R32C66[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
5.677 3.919 tNET FF 1 R35C88[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_wptr_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk1x
10.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.876 0.876 tNET RR 1 R35C88[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_wptr_0_s0/CLK
10.529 -0.347 tSu 1 R35C88[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_wptr_0_s0

Path Statistics:

Clock Skew 0.028
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.848, 100.000%
Arrival Data Path Delay cell: 0.390, 8.077%; route: 4.056, 84.002%; tC2Q: 0.382, 7.921%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.876, 100.000%

Path6

Path Summary:

Slack 4.852
Data Arrival Time 5.677
Data Required Time 10.529
From u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_wptr_2_s0
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.848 0.848 tNET RR 1 R32C66[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
1.230 0.382 tC2Q RR 1 R32C66[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
1.368 0.137 tNET RR 1 R32C66[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
1.758 0.390 tINS RF 80 R32C66[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
5.677 3.919 tNET FF 1 R35C88[1][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_wptr_2_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk1x
10.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.876 0.876 tNET RR 1 R35C88[1][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_wptr_2_s0/CLK
10.529 -0.347 tSu 1 R35C88[1][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_wptr_2_s0

Path Statistics:

Clock Skew 0.028
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.848, 100.000%
Arrival Data Path Delay cell: 0.390, 8.077%; route: 4.056, 84.002%; tC2Q: 0.382, 7.921%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.876, 100.000%

Path7

Path Summary:

Slack 4.852
Data Arrival Time 5.677
Data Required Time 10.529
From u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq2_wptr_0_s0
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.848 0.848 tNET RR 1 R32C66[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
1.230 0.382 tC2Q RR 1 R32C66[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
1.368 0.137 tNET RR 1 R32C66[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
1.758 0.390 tINS RF 80 R32C66[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
5.677 3.919 tNET FF 1 R35C88[1][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq2_wptr_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk1x
10.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.876 0.876 tNET RR 1 R35C88[1][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq2_wptr_0_s0/CLK
10.529 -0.347 tSu 1 R35C88[1][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq2_wptr_0_s0

Path Statistics:

Clock Skew 0.028
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.848, 100.000%
Arrival Data Path Delay cell: 0.390, 8.077%; route: 4.056, 84.002%; tC2Q: 0.382, 7.921%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.876, 100.000%

Path8

Path Summary:

Slack 4.852
Data Arrival Time 5.677
Data Required Time 10.529
From u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq2_wptr_2_s0
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.848 0.848 tNET RR 1 R32C66[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
1.230 0.382 tC2Q RR 1 R32C66[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
1.368 0.137 tNET RR 1 R32C66[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
1.758 0.390 tINS RF 80 R32C66[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
5.677 3.919 tNET FF 1 R35C88[2][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq2_wptr_2_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk1x
10.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.876 0.876 tNET RR 1 R35C88[2][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq2_wptr_2_s0/CLK
10.529 -0.347 tSu 1 R35C88[2][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq2_wptr_2_s0

Path Statistics:

Clock Skew 0.028
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.848, 100.000%
Arrival Data Path Delay cell: 0.390, 8.077%; route: 4.056, 84.002%; tC2Q: 0.382, 7.921%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.876, 100.000%

Path9

Path Summary:

Slack 4.852
Data Arrival Time 5.677
Data Required Time 10.529
From u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq1_wptr_0_s0
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.848 0.848 tNET RR 1 R32C66[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
1.230 0.382 tC2Q RR 1 R32C66[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
1.368 0.137 tNET RR 1 R32C66[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
1.758 0.390 tINS RF 80 R32C66[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
5.677 3.919 tNET FF 1 R35C88[2][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq1_wptr_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk1x
10.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.876 0.876 tNET RR 1 R35C88[2][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq1_wptr_0_s0/CLK
10.529 -0.347 tSu 1 R35C88[2][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq1_wptr_0_s0

Path Statistics:

Clock Skew 0.028
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.848, 100.000%
Arrival Data Path Delay cell: 0.390, 8.077%; route: 4.056, 84.002%; tC2Q: 0.382, 7.921%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.876, 100.000%

Path10

Path Summary:

Slack 4.852
Data Arrival Time 5.677
Data Required Time 10.529
From u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq1_wptr_2_s0
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.848 0.848 tNET RR 1 R32C66[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
1.230 0.382 tC2Q RR 1 R32C66[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
1.368 0.137 tNET RR 1 R32C66[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
1.758 0.390 tINS RF 80 R32C66[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
5.677 3.919 tNET FF 1 R35C88[3][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq1_wptr_2_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk1x
10.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.876 0.876 tNET RR 1 R35C88[3][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq1_wptr_2_s0/CLK
10.529 -0.347 tSu 1 R35C88[3][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq1_wptr_2_s0

Path Statistics:

Clock Skew 0.028
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.848, 100.000%
Arrival Data Path Delay cell: 0.390, 8.077%; route: 4.056, 84.002%; tC2Q: 0.382, 7.921%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.876, 100.000%

Path11

Path Summary:

Slack 4.862
Data Arrival Time 5.650
Data Required Time 10.512
From u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_wbin_0_s0
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.848 0.848 tNET RR 1 R32C66[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
1.230 0.382 tC2Q RR 1 R32C66[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
1.368 0.137 tNET RR 1 R32C66[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
1.758 0.390 tINS RF 80 R32C66[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
5.650 3.893 tNET FF 1 R36C86[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_wbin_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk1x
10.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.859 0.859 tNET RR 1 R36C86[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_wbin_0_s0/CLK
10.512 -0.347 tSu 1 R36C86[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_wbin_0_s0

Path Statistics:

Clock Skew 0.012
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.848, 100.000%
Arrival Data Path Delay cell: 0.390, 8.121%; route: 4.030, 83.915%; tC2Q: 0.382, 7.965%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.859, 100.000%

Path12

Path Summary:

Slack 4.871
Data Arrival Time 5.650
Data Required Time 10.521
From u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_Empty_reg_s0
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.848 0.848 tNET RR 1 R32C66[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
1.230 0.382 tC2Q RR 1 R32C66[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
1.368 0.137 tNET RR 1 R32C66[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
1.758 0.390 tINS RF 80 R32C66[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
5.650 3.893 tNET FF 1 R36C87[2][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_Empty_reg_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk1x
10.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.869 0.869 tNET RR 1 R36C87[2][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_Empty_reg_s0/CLK
10.521 -0.347 tSu 1 R36C87[2][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_Empty_reg_s0

Path Statistics:

Clock Skew 0.021
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.848, 100.000%
Arrival Data Path Delay cell: 0.390, 8.121%; route: 4.030, 83.915%; tC2Q: 0.382, 7.965%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.869, 100.000%

Path13

Path Summary:

Slack 5.024
Data Arrival Time 5.532
Data Required Time 10.556
From u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_Empty_reg_s0
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.848 0.848 tNET RR 1 R32C66[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
1.230 0.382 tC2Q RR 1 R32C66[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
1.368 0.137 tNET RR 1 R32C66[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
1.758 0.390 tINS RF 80 R32C66[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
5.532 3.774 tNET FF 1 R2C75[2][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_Empty_reg_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk1x
10.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.903 0.903 tNET RR 1 R2C75[2][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_Empty_reg_s0/CLK
10.556 -0.347 tSu 1 R2C75[2][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_Empty_reg_s0

Path Statistics:

Clock Skew 0.055
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.848, 100.000%
Arrival Data Path Delay cell: 0.390, 8.327%; route: 3.911, 83.507%; tC2Q: 0.382, 8.167%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.903, 100.000%

Path14

Path Summary:

Slack 5.024
Data Arrival Time 5.532
Data Required Time 10.556
From u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rbin_1_s0
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.848 0.848 tNET RR 1 R32C66[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
1.230 0.382 tC2Q RR 1 R32C66[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
1.368 0.137 tNET RR 1 R32C66[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
1.758 0.390 tINS RF 80 R32C66[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
5.532 3.774 tNET FF 1 R2C75[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rbin_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk1x
10.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.903 0.903 tNET RR 1 R2C75[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rbin_1_s0/CLK
10.556 -0.347 tSu 1 R2C75[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rbin_1_s0

Path Statistics:

Clock Skew 0.055
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.848, 100.000%
Arrival Data Path Delay cell: 0.390, 8.327%; route: 3.911, 83.507%; tC2Q: 0.382, 8.167%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.903, 100.000%

Path15

Path Summary:

Slack 5.024
Data Arrival Time 5.532
Data Required Time 10.556
From u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rbin_2_s0
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.848 0.848 tNET RR 1 R32C66[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
1.230 0.382 tC2Q RR 1 R32C66[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
1.368 0.137 tNET RR 1 R32C66[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
1.758 0.390 tINS RF 80 R32C66[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
5.532 3.774 tNET FF 1 R2C75[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rbin_2_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk1x
10.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.903 0.903 tNET RR 1 R2C75[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rbin_2_s0/CLK
10.556 -0.347 tSu 1 R2C75[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rbin_2_s0

Path Statistics:

Clock Skew 0.055
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.848, 100.000%
Arrival Data Path Delay cell: 0.390, 8.327%; route: 3.911, 83.507%; tC2Q: 0.382, 8.167%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.903, 100.000%

Path16

Path Summary:

Slack 5.024
Data Arrival Time 5.532
Data Required Time 10.556
From u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rbin_3_s0
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.848 0.848 tNET RR 1 R32C66[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
1.230 0.382 tC2Q RR 1 R32C66[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
1.368 0.137 tNET RR 1 R32C66[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
1.758 0.390 tINS RF 80 R32C66[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
5.532 3.774 tNET FF 1 R2C75[1][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rbin_3_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk1x
10.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.903 0.903 tNET RR 1 R2C75[1][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rbin_3_s0/CLK
10.556 -0.347 tSu 1 R2C75[1][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rbin_3_s0

Path Statistics:

Clock Skew 0.055
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.848, 100.000%
Arrival Data Path Delay cell: 0.390, 8.327%; route: 3.911, 83.507%; tC2Q: 0.382, 8.167%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.903, 100.000%

Path17

Path Summary:

Slack 5.043
Data Arrival Time 5.467
Data Required Time 10.510
From u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq1_wptr_3_s0
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.848 0.848 tNET RR 1 R32C66[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
1.230 0.382 tC2Q RR 1 R32C66[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
1.368 0.137 tNET RR 1 R32C66[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
1.758 0.390 tINS RF 80 R32C66[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
5.467 3.709 tNET FF 1 R35C86[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq1_wptr_3_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk1x
10.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.858 0.857 tNET RR 1 R35C86[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq1_wptr_3_s0/CLK
10.510 -0.347 tSu 1 R35C86[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq1_wptr_3_s0

Path Statistics:

Clock Skew 0.010
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.848, 100.000%
Arrival Data Path Delay cell: 0.390, 8.444%; route: 3.846, 83.275%; tC2Q: 0.382, 8.281%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.857, 100.000%

Path18

Path Summary:

Slack 5.043
Data Arrival Time 5.467
Data Required Time 10.510
From u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_wbin_2_s0
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.848 0.848 tNET RR 1 R32C66[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
1.230 0.382 tC2Q RR 1 R32C66[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
1.368 0.137 tNET RR 1 R32C66[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
1.758 0.390 tINS RF 80 R32C66[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
5.467 3.709 tNET FF 1 R35C86[1][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_wbin_2_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk1x
10.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.858 0.857 tNET RR 1 R35C86[1][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_wbin_2_s0/CLK
10.510 -0.347 tSu 1 R35C86[1][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_wbin_2_s0

Path Statistics:

Clock Skew 0.010
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.848, 100.000%
Arrival Data Path Delay cell: 0.390, 8.444%; route: 3.846, 83.275%; tC2Q: 0.382, 8.281%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.857, 100.000%

Path19

Path Summary:

Slack 5.043
Data Arrival Time 5.467
Data Required Time 10.510
From u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_wbin_3_s0
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.848 0.848 tNET RR 1 R32C66[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
1.230 0.382 tC2Q RR 1 R32C66[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
1.368 0.137 tNET RR 1 R32C66[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
1.758 0.390 tINS RF 80 R32C66[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
5.467 3.709 tNET FF 1 R35C86[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_wbin_3_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk1x
10.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.858 0.857 tNET RR 1 R35C86[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_wbin_3_s0/CLK
10.510 -0.347 tSu 1 R35C86[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_wbin_3_s0

Path Statistics:

Clock Skew 0.010
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.848, 100.000%
Arrival Data Path Delay cell: 0.390, 8.444%; route: 3.846, 83.275%; tC2Q: 0.382, 8.281%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.857, 100.000%

Path20

Path Summary:

Slack 5.043
Data Arrival Time 5.467
Data Required Time 10.510
From u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq2_wptr_3_s0
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.848 0.848 tNET RR 1 R32C66[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
1.230 0.382 tC2Q RR 1 R32C66[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
1.368 0.137 tNET RR 1 R32C66[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
1.758 0.390 tINS RF 80 R32C66[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
5.467 3.709 tNET FF 1 R35C86[1][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq2_wptr_3_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk1x
10.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.858 0.857 tNET RR 1 R35C86[1][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq2_wptr_3_s0/CLK
10.510 -0.347 tSu 1 R35C86[1][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq2_wptr_3_s0

Path Statistics:

Clock Skew 0.010
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.848, 100.000%
Arrival Data Path Delay cell: 0.390, 8.444%; route: 3.846, 83.275%; tC2Q: 0.382, 8.281%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.857, 100.000%

Path21

Path Summary:

Slack 5.053
Data Arrival Time 5.467
Data Required Time 10.519
From u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_wptr_1_s0
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.848 0.848 tNET RR 1 R32C66[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
1.230 0.382 tC2Q RR 1 R32C66[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
1.368 0.137 tNET RR 1 R32C66[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
1.758 0.390 tINS RF 80 R32C66[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
5.467 3.709 tNET FF 1 R35C87[1][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_wptr_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk1x
10.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.867 0.867 tNET RR 1 R35C87[1][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_wptr_1_s0/CLK
10.519 -0.347 tSu 1 R35C87[1][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_wptr_1_s0

Path Statistics:

Clock Skew 0.019
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.848, 100.000%
Arrival Data Path Delay cell: 0.390, 8.444%; route: 3.846, 83.275%; tC2Q: 0.382, 8.281%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.867, 100.000%

Path22

Path Summary:

Slack 5.053
Data Arrival Time 5.467
Data Required Time 10.519
From u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rbin_0_s0
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.848 0.848 tNET RR 1 R32C66[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
1.230 0.382 tC2Q RR 1 R32C66[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
1.368 0.137 tNET RR 1 R32C66[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
1.758 0.390 tINS RF 80 R32C66[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
5.467 3.709 tNET FF 1 R35C87[2][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rbin_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk1x
10.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.867 0.867 tNET RR 1 R35C87[2][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rbin_0_s0/CLK
10.519 -0.347 tSu 1 R35C87[2][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rbin_0_s0

Path Statistics:

Clock Skew 0.019
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.848, 100.000%
Arrival Data Path Delay cell: 0.390, 8.444%; route: 3.846, 83.275%; tC2Q: 0.382, 8.281%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.867, 100.000%

Path23

Path Summary:

Slack 5.053
Data Arrival Time 5.467
Data Required Time 10.519
From u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq2_wptr_1_s0
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.848 0.848 tNET RR 1 R32C66[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
1.230 0.382 tC2Q RR 1 R32C66[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
1.368 0.137 tNET RR 1 R32C66[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
1.758 0.390 tINS RF 80 R32C66[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
5.467 3.709 tNET FF 1 R35C87[1][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq2_wptr_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk1x
10.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.867 0.867 tNET RR 1 R35C87[1][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq2_wptr_1_s0/CLK
10.519 -0.347 tSu 1 R35C87[1][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq2_wptr_1_s0

Path Statistics:

Clock Skew 0.019
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.848, 100.000%
Arrival Data Path Delay cell: 0.390, 8.444%; route: 3.846, 83.275%; tC2Q: 0.382, 8.281%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.867, 100.000%

Path24

Path Summary:

Slack 5.053
Data Arrival Time 5.467
Data Required Time 10.519
From u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq1_wptr_1_s0
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.848 0.848 tNET RR 1 R32C66[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
1.230 0.382 tC2Q RR 1 R32C66[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
1.368 0.137 tNET RR 1 R32C66[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
1.758 0.390 tINS RF 80 R32C66[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
5.467 3.709 tNET FF 1 R35C87[2][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq1_wptr_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk1x
10.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.867 0.867 tNET RR 1 R35C87[2][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq1_wptr_1_s0/CLK
10.519 -0.347 tSu 1 R35C87[2][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq1_wptr_1_s0

Path Statistics:

Clock Skew 0.019
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.848, 100.000%
Arrival Data Path Delay cell: 0.390, 8.444%; route: 3.846, 83.275%; tC2Q: 0.382, 8.281%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.867, 100.000%

Path25

Path Summary:

Slack 5.218
Data Arrival Time 5.330
Data Required Time 10.548
From u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rq1_wptr_3_s0
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.848 0.848 tNET RR 1 R32C66[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
1.230 0.382 tC2Q RR 1 R32C66[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
1.368 0.137 tNET RR 1 R32C66[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
1.758 0.390 tINS RF 80 R32C66[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
5.330 3.573 tNET FF 1 R5C75[1][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rq1_wptr_3_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk1x
10.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.896 0.896 tNET RR 1 R5C75[1][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rq1_wptr_3_s0/CLK
10.548 -0.347 tSu 1 R5C75[1][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rq1_wptr_3_s0

Path Statistics:

Clock Skew 0.048
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.848, 100.000%
Arrival Data Path Delay cell: 0.390, 8.701%; route: 3.710, 82.766%; tC2Q: 0.382, 8.533%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.896, 100.000%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 1.674
Data Arrival Time 2.535
Data Required Time 0.861
From btn/out_s0
To u_ddr3/gw3_top/u_ddr_phy_top/wloadn_3_s0
Launch Clk clkin:[R]
Latch Clk clkin:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOB29[A] clk_g_ibuf/I
0.675 0.675 tINS RR 90 IOB29[A] clk_g_ibuf/O
1.078 0.402 tNET RR 1 R2C64[1][A] btn/out_s0/CLK
1.258 0.180 tC2Q RR 42 R2C64[1][A] btn/out_s0/Q
2.535 1.278 tNET RR 1 R18C76[0][A] u_ddr3/gw3_top/u_ddr_phy_top/wloadn_3_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOB29[A] clk_g_ibuf/I
0.675 0.675 tINS RR 90 IOB29[A] clk_g_ibuf/O
1.050 0.375 tNET RR 1 R18C76[0][A] u_ddr3/gw3_top/u_ddr_phy_top/wloadn_3_s0/CLK
0.861 -0.189 tHld 1 R18C76[0][A] u_ddr3/gw3_top/u_ddr_phy_top/wloadn_3_s0

Path Statistics:

Clock Skew -0.028
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 62.681%; route: 0.402, 37.319%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.278, 87.650%; tC2Q: 0.180, 12.350%
Required Clock Path Delay cell: 0.675, 64.322%; route: 0.375, 35.678%

Path2

Path Summary:

Slack 1.694
Data Arrival Time 1.901
Data Required Time 0.208
From u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_0_s0
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.356 0.356 tNET RR 1 R32C66[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
0.533 0.176 tC2Q RF 1 R32C66[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
0.615 0.082 tNET FF 1 R32C66[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
0.940 0.325 tINS FR 80 R32C66[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
1.901 0.961 tNET RR 1 R21C77[2][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.396 0.396 tNET RR 1 R21C77[2][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_0_s0/CLK
0.208 -0.189 tHld 1 R21C77[2][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_0_s0

Path Statistics:

Clock Skew 0.040
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.356, 100.000%
Arrival Data Path Delay cell: 0.325, 21.036%; route: 1.044, 67.557%; tC2Q: 0.176, 11.408%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.396, 100.000%

Path3

Path Summary:

Slack 1.752
Data Arrival Time 2.625
Data Required Time 0.873
From btn/out_s0
To u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0
Launch Clk clkin:[R]
Latch Clk clkin:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOB29[A] clk_g_ibuf/I
0.675 0.675 tINS RR 90 IOB29[A] clk_g_ibuf/O
1.078 0.402 tNET RR 1 R2C64[1][A] btn/out_s0/CLK
1.258 0.180 tC2Q RR 42 R2C64[1][A] btn/out_s0/Q
2.625 1.367 tNET RR 1 R25C59[1][A] u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOB29[A] clk_g_ibuf/I
0.675 0.675 tINS RR 90 IOB29[A] clk_g_ibuf/O
1.062 0.386 tNET RR 1 R25C59[1][A] u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0/CLK
0.873 -0.189 tHld 1 R25C59[1][A] u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0

Path Statistics:

Clock Skew -0.016
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 62.681%; route: 0.402, 37.319%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.367, 88.364%; tC2Q: 0.180, 11.636%
Required Clock Path Delay cell: 0.675, 63.621%; route: 0.386, 36.379%

Path4

Path Summary:

Slack 1.752
Data Arrival Time 2.625
Data Required Time 0.873
From btn/out_s0
To u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_syn_0_s0
Launch Clk clkin:[R]
Latch Clk clkin:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOB29[A] clk_g_ibuf/I
0.675 0.675 tINS RR 90 IOB29[A] clk_g_ibuf/O
1.078 0.402 tNET RR 1 R2C64[1][A] btn/out_s0/CLK
1.258 0.180 tC2Q RR 42 R2C64[1][A] btn/out_s0/Q
2.625 1.367 tNET RR 1 R25C59[0][A] u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_syn_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOB29[A] clk_g_ibuf/I
0.675 0.675 tINS RR 90 IOB29[A] clk_g_ibuf/O
1.062 0.386 tNET RR 1 R25C59[0][A] u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_syn_0_s0/CLK
0.873 -0.189 tHld 1 R25C59[0][A] u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_syn_0_s0

Path Statistics:

Clock Skew -0.016
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 62.681%; route: 0.402, 37.319%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.367, 88.364%; tC2Q: 0.180, 11.636%
Required Clock Path Delay cell: 0.675, 63.621%; route: 0.386, 36.379%

Path5

Path Summary:

Slack 1.752
Data Arrival Time 2.625
Data Required Time 0.873
From btn/out_s0
To u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_syn_1_s0
Launch Clk clkin:[R]
Latch Clk clkin:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOB29[A] clk_g_ibuf/I
0.675 0.675 tINS RR 90 IOB29[A] clk_g_ibuf/O
1.078 0.402 tNET RR 1 R2C64[1][A] btn/out_s0/CLK
1.258 0.180 tC2Q RR 42 R2C64[1][A] btn/out_s0/Q
2.625 1.367 tNET RR 1 R25C59[3][A] u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_syn_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOB29[A] clk_g_ibuf/I
0.675 0.675 tINS RR 90 IOB29[A] clk_g_ibuf/O
1.062 0.386 tNET RR 1 R25C59[3][A] u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_syn_1_s0/CLK
0.873 -0.189 tHld 1 R25C59[3][A] u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_syn_1_s0

Path Statistics:

Clock Skew -0.016
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 62.681%; route: 0.402, 37.319%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.367, 88.364%; tC2Q: 0.180, 11.636%
Required Clock Path Delay cell: 0.675, 63.621%; route: 0.386, 36.379%

Path6

Path Summary:

Slack 1.752
Data Arrival Time 2.625
Data Required Time 0.873
From btn/out_s0
To u_ddr3/gw3_top/u_ddr_phy_top/stop_reg_0_s0
Launch Clk clkin:[R]
Latch Clk clkin:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOB29[A] clk_g_ibuf/I
0.675 0.675 tINS RR 90 IOB29[A] clk_g_ibuf/O
1.078 0.402 tNET RR 1 R2C64[1][A] btn/out_s0/CLK
1.258 0.180 tC2Q RR 42 R2C64[1][A] btn/out_s0/Q
2.625 1.367 tNET RR 1 R25C59[2][B] u_ddr3/gw3_top/u_ddr_phy_top/stop_reg_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOB29[A] clk_g_ibuf/I
0.675 0.675 tINS RR 90 IOB29[A] clk_g_ibuf/O
1.062 0.386 tNET RR 1 R25C59[2][B] u_ddr3/gw3_top/u_ddr_phy_top/stop_reg_0_s0/CLK
0.873 -0.189 tHld 1 R25C59[2][B] u_ddr3/gw3_top/u_ddr_phy_top/stop_reg_0_s0

Path Statistics:

Clock Skew -0.016
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 62.681%; route: 0.402, 37.319%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.367, 88.364%; tC2Q: 0.180, 11.636%
Required Clock Path Delay cell: 0.675, 63.621%; route: 0.386, 36.379%

Path7

Path Summary:

Slack 1.752
Data Arrival Time 2.625
Data Required Time 0.873
From btn/out_s0
To u_ddr3/gw3_top/u_ddr_phy_top/stop_reg_1_s0
Launch Clk clkin:[R]
Latch Clk clkin:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOB29[A] clk_g_ibuf/I
0.675 0.675 tINS RR 90 IOB29[A] clk_g_ibuf/O
1.078 0.402 tNET RR 1 R2C64[1][A] btn/out_s0/CLK
1.258 0.180 tC2Q RR 42 R2C64[1][A] btn/out_s0/Q
2.625 1.367 tNET RR 1 R25C59[2][A] u_ddr3/gw3_top/u_ddr_phy_top/stop_reg_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOB29[A] clk_g_ibuf/I
0.675 0.675 tINS RR 90 IOB29[A] clk_g_ibuf/O
1.062 0.386 tNET RR 1 R25C59[2][A] u_ddr3/gw3_top/u_ddr_phy_top/stop_reg_1_s0/CLK
0.873 -0.189 tHld 1 R25C59[2][A] u_ddr3/gw3_top/u_ddr_phy_top/stop_reg_1_s0

Path Statistics:

Clock Skew -0.016
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 62.681%; route: 0.402, 37.319%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.367, 88.364%; tC2Q: 0.180, 11.636%
Required Clock Path Delay cell: 0.675, 63.621%; route: 0.386, 36.379%

Path8

Path Summary:

Slack 1.752
Data Arrival Time 2.625
Data Required Time 0.873
From btn/out_s0
To u_ddr3/gw3_top/u_ddr_phy_top/stop_reg_2_s0
Launch Clk clkin:[R]
Latch Clk clkin:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOB29[A] clk_g_ibuf/I
0.675 0.675 tINS RR 90 IOB29[A] clk_g_ibuf/O
1.078 0.402 tNET RR 1 R2C64[1][A] btn/out_s0/CLK
1.258 0.180 tC2Q RR 42 R2C64[1][A] btn/out_s0/Q
2.625 1.367 tNET RR 1 R25C59[0][B] u_ddr3/gw3_top/u_ddr_phy_top/stop_reg_2_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOB29[A] clk_g_ibuf/I
0.675 0.675 tINS RR 90 IOB29[A] clk_g_ibuf/O
1.062 0.386 tNET RR 1 R25C59[0][B] u_ddr3/gw3_top/u_ddr_phy_top/stop_reg_2_s0/CLK
0.873 -0.189 tHld 1 R25C59[0][B] u_ddr3/gw3_top/u_ddr_phy_top/stop_reg_2_s0

Path Statistics:

Clock Skew -0.016
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 62.681%; route: 0.402, 37.319%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.367, 88.364%; tC2Q: 0.180, 11.636%
Required Clock Path Delay cell: 0.675, 63.621%; route: 0.386, 36.379%

Path9

Path Summary:

Slack 1.821
Data Arrival Time 2.029
Data Required Time 0.208
From u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_Empty_reg_s0
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.356 0.356 tNET RR 1 R32C66[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
0.533 0.176 tC2Q RF 1 R32C66[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
0.615 0.082 tNET FF 1 R32C66[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
0.940 0.325 tINS FR 80 R32C66[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
2.029 1.089 tNET RR 1 R21C79[2][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_Empty_reg_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.396 0.396 tNET RR 1 R21C79[2][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_Empty_reg_s0/CLK
0.208 -0.189 tHld 1 R21C79[2][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_Empty_reg_s0

Path Statistics:

Clock Skew 0.040
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.356, 100.000%
Arrival Data Path Delay cell: 0.325, 19.432%; route: 1.171, 70.030%; tC2Q: 0.176, 10.538%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.396, 100.000%

Path10

Path Summary:

Slack 1.826
Data Arrival Time 2.029
Data Required Time 0.203
From u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_3_s0
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.356 0.356 tNET RR 1 R32C66[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
0.533 0.176 tC2Q RF 1 R32C66[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
0.615 0.082 tNET FF 1 R32C66[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
0.940 0.325 tINS FR 80 R32C66[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
2.029 1.089 tNET RR 1 R21C78[1][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_3_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.391 0.391 tNET RR 1 R21C78[1][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_3_s0/CLK
0.203 -0.189 tHld 1 R21C78[1][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_3_s0

Path Statistics:

Clock Skew 0.035
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.356, 100.000%
Arrival Data Path Delay cell: 0.325, 19.432%; route: 1.171, 70.030%; tC2Q: 0.176, 10.538%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.391, 100.000%

Path11

Path Summary:

Slack 1.826
Data Arrival Time 2.029
Data Required Time 0.203
From u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_1_s0
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.356 0.356 tNET RR 1 R32C66[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
0.533 0.176 tC2Q RF 1 R32C66[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
0.615 0.082 tNET FF 1 R32C66[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
0.940 0.325 tINS FR 80 R32C66[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
2.029 1.089 tNET RR 1 R21C78[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.391 0.391 tNET RR 1 R21C78[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_1_s0/CLK
0.203 -0.189 tHld 1 R21C78[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_1_s0

Path Statistics:

Clock Skew 0.035
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.356, 100.000%
Arrival Data Path Delay cell: 0.325, 19.432%; route: 1.171, 70.030%; tC2Q: 0.176, 10.538%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.391, 100.000%

Path12

Path Summary:

Slack 1.826
Data Arrival Time 2.029
Data Required Time 0.203
From u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_3_s0
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.356 0.356 tNET RR 1 R32C66[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
0.533 0.176 tC2Q RF 1 R32C66[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
0.615 0.082 tNET FF 1 R32C66[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
0.940 0.325 tINS FR 80 R32C66[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
2.029 1.089 tNET RR 1 R21C78[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_3_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.391 0.391 tNET RR 1 R21C78[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_3_s0/CLK
0.203 -0.189 tHld 1 R21C78[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_3_s0

Path Statistics:

Clock Skew 0.035
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.356, 100.000%
Arrival Data Path Delay cell: 0.325, 19.432%; route: 1.171, 70.030%; tC2Q: 0.176, 10.538%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.391, 100.000%

Path13

Path Summary:

Slack 1.826
Data Arrival Time 2.029
Data Required Time 0.203
From u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_3_s0
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.356 0.356 tNET RR 1 R32C66[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
0.533 0.176 tC2Q RF 1 R32C66[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
0.615 0.082 tNET FF 1 R32C66[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
0.940 0.325 tINS FR 80 R32C66[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
2.029 1.089 tNET RR 1 R21C78[1][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_3_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.391 0.391 tNET RR 1 R21C78[1][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_3_s0/CLK
0.203 -0.189 tHld 1 R21C78[1][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_3_s0

Path Statistics:

Clock Skew 0.035
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.356, 100.000%
Arrival Data Path Delay cell: 0.325, 19.432%; route: 1.171, 70.030%; tC2Q: 0.176, 10.538%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.391, 100.000%

Path14

Path Summary:

Slack 1.868
Data Arrival Time 2.077
Data Required Time 0.210
From u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_2_s0
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.356 0.356 tNET RR 1 R32C66[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
0.533 0.176 tC2Q RF 1 R32C66[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
0.615 0.082 tNET FF 1 R32C66[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
0.940 0.325 tINS FR 80 R32C66[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
2.077 1.137 tNET RR 1 R20C77[1][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_2_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.398 0.398 tNET RR 1 R20C77[1][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_2_s0/CLK
0.210 -0.189 tHld 1 R20C77[1][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_2_s0

Path Statistics:

Clock Skew 0.042
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.356, 100.000%
Arrival Data Path Delay cell: 0.325, 18.882%; route: 1.220, 70.879%; tC2Q: 0.176, 10.240%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.398, 100.000%

Path15

Path Summary:

Slack 1.868
Data Arrival Time 2.077
Data Required Time 0.210
From u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wptr_1_s0
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.356 0.356 tNET RR 1 R32C66[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
0.533 0.176 tC2Q RF 1 R32C66[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
0.615 0.082 tNET FF 1 R32C66[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
0.940 0.325 tINS FR 80 R32C66[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
2.077 1.137 tNET RR 1 R20C77[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wptr_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.398 0.398 tNET RR 1 R20C77[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wptr_1_s0/CLK
0.210 -0.189 tHld 1 R20C77[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wptr_1_s0

Path Statistics:

Clock Skew 0.042
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.356, 100.000%
Arrival Data Path Delay cell: 0.325, 18.882%; route: 1.220, 70.879%; tC2Q: 0.176, 10.240%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.398, 100.000%

Path16

Path Summary:

Slack 1.868
Data Arrival Time 2.077
Data Required Time 0.210
From u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wptr_2_s0
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.356 0.356 tNET RR 1 R32C66[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
0.533 0.176 tC2Q RF 1 R32C66[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
0.615 0.082 tNET FF 1 R32C66[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
0.940 0.325 tINS FR 80 R32C66[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
2.077 1.137 tNET RR 1 R20C77[2][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wptr_2_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.398 0.398 tNET RR 1 R20C77[2][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wptr_2_s0/CLK
0.210 -0.189 tHld 1 R20C77[2][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wptr_2_s0

Path Statistics:

Clock Skew 0.042
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.356, 100.000%
Arrival Data Path Delay cell: 0.325, 18.882%; route: 1.220, 70.879%; tC2Q: 0.176, 10.240%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.398, 100.000%

Path17

Path Summary:

Slack 1.868
Data Arrival Time 2.077
Data Required Time 0.210
From u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_1_s0
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.356 0.356 tNET RR 1 R32C66[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
0.533 0.176 tC2Q RF 1 R32C66[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
0.615 0.082 tNET FF 1 R32C66[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
0.940 0.325 tINS FR 80 R32C66[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
2.077 1.137 tNET RR 1 R20C77[1][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.398 0.398 tNET RR 1 R20C77[1][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_1_s0/CLK
0.210 -0.189 tHld 1 R20C77[1][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_1_s0

Path Statistics:

Clock Skew 0.042
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.356, 100.000%
Arrival Data Path Delay cell: 0.325, 18.882%; route: 1.220, 70.879%; tC2Q: 0.176, 10.240%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.398, 100.000%

Path18

Path Summary:

Slack 1.868
Data Arrival Time 2.077
Data Required Time 0.210
From u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_1_s0
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.356 0.356 tNET RR 1 R32C66[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
0.533 0.176 tC2Q RF 1 R32C66[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
0.615 0.082 tNET FF 1 R32C66[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
0.940 0.325 tINS FR 80 R32C66[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
2.077 1.137 tNET RR 1 R20C77[2][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.398 0.398 tNET RR 1 R20C77[2][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_1_s0/CLK
0.210 -0.189 tHld 1 R20C77[2][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_1_s0

Path Statistics:

Clock Skew 0.042
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.356, 100.000%
Arrival Data Path Delay cell: 0.325, 18.882%; route: 1.220, 70.879%; tC2Q: 0.176, 10.240%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.398, 100.000%

Path19

Path Summary:

Slack 1.963
Data Arrival Time 2.848
Data Required Time 0.885
From btn/out_s0
To u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_d2_s0
Launch Clk clkin:[R]
Latch Clk clkin:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOB29[A] clk_g_ibuf/I
0.675 0.675 tINS RR 90 IOB29[A] clk_g_ibuf/O
1.078 0.402 tNET RR 1 R2C64[1][A] btn/out_s0/CLK
1.258 0.180 tC2Q RR 42 R2C64[1][A] btn/out_s0/Q
2.848 1.590 tNET RR 1 R22C58[0][A] u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_d2_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOB29[A] clk_g_ibuf/I
0.675 0.675 tINS RR 90 IOB29[A] clk_g_ibuf/O
1.073 0.398 tNET RR 1 R22C58[0][A] u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_d2_s0/CLK
0.885 -0.189 tHld 1 R22C58[0][A] u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_d2_s0

Path Statistics:

Clock Skew -0.004
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 62.681%; route: 0.402, 37.319%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.590, 89.831%; tC2Q: 0.180, 10.169%
Required Clock Path Delay cell: 0.675, 62.936%; route: 0.398, 37.064%

Path20

Path Summary:

Slack 1.965
Data Arrival Time 2.848
Data Required Time 0.882
From btn/out_s0
To u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_8_s1
Launch Clk clkin:[R]
Latch Clk clkin:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOB29[A] clk_g_ibuf/I
0.675 0.675 tINS RR 90 IOB29[A] clk_g_ibuf/O
1.078 0.402 tNET RR 1 R2C64[1][A] btn/out_s0/CLK
1.258 0.180 tC2Q RR 42 R2C64[1][A] btn/out_s0/Q
2.848 1.590 tNET RR 1 R23C58[3][A] u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_8_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOB29[A] clk_g_ibuf/I
0.675 0.675 tINS RR 90 IOB29[A] clk_g_ibuf/O
1.071 0.396 tNET RR 1 R23C58[3][A] u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_8_s1/CLK
0.882 -0.189 tHld 1 R23C58[3][A] u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_8_s1

Path Statistics:

Clock Skew -0.007
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 62.681%; route: 0.402, 37.319%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.590, 89.831%; tC2Q: 0.180, 10.169%
Required Clock Path Delay cell: 0.675, 63.065%; route: 0.396, 36.935%

Path21

Path Summary:

Slack 1.965
Data Arrival Time 2.848
Data Required Time 0.882
From btn/out_s0
To u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_9_s1
Launch Clk clkin:[R]
Latch Clk clkin:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOB29[A] clk_g_ibuf/I
0.675 0.675 tINS RR 90 IOB29[A] clk_g_ibuf/O
1.078 0.402 tNET RR 1 R2C64[1][A] btn/out_s0/CLK
1.258 0.180 tC2Q RR 42 R2C64[1][A] btn/out_s0/Q
2.848 1.590 tNET RR 1 R23C58[0][B] u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_9_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOB29[A] clk_g_ibuf/I
0.675 0.675 tINS RR 90 IOB29[A] clk_g_ibuf/O
1.071 0.396 tNET RR 1 R23C58[0][B] u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_9_s1/CLK
0.882 -0.189 tHld 1 R23C58[0][B] u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_9_s1

Path Statistics:

Clock Skew -0.007
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 62.681%; route: 0.402, 37.319%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.590, 89.831%; tC2Q: 0.180, 10.169%
Required Clock Path Delay cell: 0.675, 63.065%; route: 0.396, 36.935%

Path22

Path Summary:

Slack 1.965
Data Arrival Time 2.848
Data Required Time 0.882
From btn/out_s0
To u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_10_s1
Launch Clk clkin:[R]
Latch Clk clkin:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOB29[A] clk_g_ibuf/I
0.675 0.675 tINS RR 90 IOB29[A] clk_g_ibuf/O
1.078 0.402 tNET RR 1 R2C64[1][A] btn/out_s0/CLK
1.258 0.180 tC2Q RR 42 R2C64[1][A] btn/out_s0/Q
2.848 1.590 tNET RR 1 R23C58[0][A] u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_10_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOB29[A] clk_g_ibuf/I
0.675 0.675 tINS RR 90 IOB29[A] clk_g_ibuf/O
1.071 0.396 tNET RR 1 R23C58[0][A] u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_10_s1/CLK
0.882 -0.189 tHld 1 R23C58[0][A] u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_10_s1

Path Statistics:

Clock Skew -0.007
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 62.681%; route: 0.402, 37.319%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.590, 89.831%; tC2Q: 0.180, 10.169%
Required Clock Path Delay cell: 0.675, 63.065%; route: 0.396, 36.935%

Path23

Path Summary:

Slack 1.965
Data Arrival Time 2.848
Data Required Time 0.882
From btn/out_s0
To u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/count_1_s0
Launch Clk clkin:[R]
Latch Clk clkin:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOB29[A] clk_g_ibuf/I
0.675 0.675 tINS RR 90 IOB29[A] clk_g_ibuf/O
1.078 0.402 tNET RR 1 R2C64[1][A] btn/out_s0/CLK
1.258 0.180 tC2Q RR 42 R2C64[1][A] btn/out_s0/Q
2.848 1.590 tNET RR 1 R23C58[1][B] u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/count_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOB29[A] clk_g_ibuf/I
0.675 0.675 tINS RR 90 IOB29[A] clk_g_ibuf/O
1.071 0.396 tNET RR 1 R23C58[1][B] u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/count_1_s0/CLK
0.882 -0.189 tHld 1 R23C58[1][B] u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/count_1_s0

Path Statistics:

Clock Skew -0.007
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 62.681%; route: 0.402, 37.319%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.590, 89.831%; tC2Q: 0.180, 10.169%
Required Clock Path Delay cell: 0.675, 63.065%; route: 0.396, 36.935%

Path24

Path Summary:

Slack 1.990
Data Arrival Time 2.200
Data Required Time 0.210
From u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_1_s0
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.356 0.356 tNET RR 1 R32C66[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
0.533 0.176 tC2Q RF 1 R32C66[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
0.615 0.082 tNET FF 1 R32C66[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
0.940 0.325 tINS FR 80 R32C66[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
2.200 1.260 tNET RR 1 R20C79[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.398 0.398 tNET RR 1 R20C79[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_1_s0/CLK
0.210 -0.189 tHld 1 R20C79[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_1_s0

Path Statistics:

Clock Skew 0.042
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.356, 100.000%
Arrival Data Path Delay cell: 0.325, 17.627%; route: 1.342, 72.814%; tC2Q: 0.176, 9.559%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.398, 100.000%

Path25

Path Summary:

Slack 1.990
Data Arrival Time 2.200
Data Required Time 0.210
From u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_2_s0
Launch Clk clk1x:[R]
Latch Clk clk1x:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.356 0.356 tNET RR 1 R32C66[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
0.533 0.176 tC2Q RF 1 R32C66[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
0.615 0.082 tNET FF 1 R32C66[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
0.940 0.325 tINS FR 80 R32C66[0][B] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
2.200 1.260 tNET RR 1 R20C79[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_2_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR 6401 RIGHTSIDE[0] u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.398 0.398 tNET RR 1 R20C79[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_2_s0/CLK
0.210 -0.189 tHld 1 R20C79[0][A] u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_2_s0

Path Statistics:

Clock Skew 0.042
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.356, 100.000%
Arrival Data Path Delay cell: 0.325, 17.627%; route: 1.342, 72.814%; tC2Q: 0.176, 9.559%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.398, 100.000%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack: 3.494
Actual Width: 4.494
Required Width: 1.000
Type: Low Pulse Width
Clock: clk1x
Objects: u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_3_s

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk1x
5.000 0.000 tCL FF u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
5.884 0.884 tNET FF u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_3_s/CLKB

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk1x
10.000 0.000 tCL RR u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.378 0.378 tNET RR u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_3_s/CLKB

MPW2

MPW Summary:

Slack: 3.494
Actual Width: 4.494
Required Width: 1.000
Type: Low Pulse Width
Clock: clk1x
Objects: u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_4_s

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk1x
5.000 0.000 tCL FF u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
5.884 0.884 tNET FF u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_4_s/CLKA

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk1x
10.000 0.000 tCL RR u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.378 0.378 tNET RR u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_4_s/CLKA

MPW3

MPW Summary:

Slack: 3.496
Actual Width: 4.496
Required Width: 1.000
Type: High Pulse Width
Clock: clk1x
Objects: u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_3_s

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.888 0.888 tNET RR u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_3_s/CLKB

Early clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk1x
5.000 0.000 tCL FF u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
5.384 0.384 tNET FF u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_3_s/CLKB

MPW4

MPW Summary:

Slack: 3.496
Actual Width: 4.496
Required Width: 1.000
Type: High Pulse Width
Clock: clk1x
Objects: u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_4_s

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 clk1x
0.000 0.000 tCL RR u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.888 0.888 tNET RR u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_4_s/CLKA

Early clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk1x
5.000 0.000 tCL FF u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
5.384 0.384 tNET FF u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_4_s/CLKA

MPW5

MPW Summary:

Slack: 3.499
Actual Width: 4.499
Required Width: 1.000
Type: Low Pulse Width
Clock: clk1x
Objects: u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem8_mem8_0_2_s

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk1x
5.000 0.000 tCL FF u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
5.875 0.875 tNET FF u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem8_mem8_0_2_s/CLKA

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk1x
10.000 0.000 tCL RR u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.374 0.374 tNET RR u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem8_mem8_0_2_s/CLKA

MPW6

MPW Summary:

Slack: 3.499
Actual Width: 4.499
Required Width: 1.000
Type: Low Pulse Width
Clock: clk1x
Objects: u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk1x
5.000 0.000 tCL FF u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
5.875 0.875 tNET FF u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLKB

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk1x
10.000 0.000 tCL RR u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.374 0.374 tNET RR u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLKB

MPW7

MPW Summary:

Slack: 3.499
Actual Width: 4.499
Required Width: 1.000
Type: Low Pulse Width
Clock: clk1x
Objects: u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk1x
5.000 0.000 tCL FF u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
5.875 0.875 tNET FF u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/CLKA

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk1x
10.000 0.000 tCL RR u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.374 0.374 tNET RR u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/CLKA

MPW8

MPW Summary:

Slack: 3.499
Actual Width: 4.499
Required Width: 1.000
Type: Low Pulse Width
Clock: clk1x
Objects: u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk1x
5.000 0.000 tCL FF u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
5.875 0.875 tNET FF u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/CLKA

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk1x
10.000 0.000 tCL RR u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.374 0.374 tNET RR u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/CLKA

MPW9

MPW Summary:

Slack: 3.499
Actual Width: 4.499
Required Width: 1.000
Type: Low Pulse Width
Clock: clk1x
Objects: u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem8_mem8_0_3_s

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk1x
5.000 0.000 tCL FF u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
5.875 0.875 tNET FF u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem8_mem8_0_3_s/CLKB

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk1x
10.000 0.000 tCL RR u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.374 0.374 tNET RR u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem8_mem8_0_3_s/CLKB

MPW10

MPW Summary:

Slack: 3.499
Actual Width: 4.499
Required Width: 1.000
Type: Low Pulse Width
Clock: clk1x
Objects: u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem8_mem8_0_5_s

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk1x
5.000 0.000 tCL FF u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
5.875 0.875 tNET FF u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem8_mem8_0_5_s/CLKB

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk1x
10.000 0.000 tCL RR u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.374 0.374 tNET RR u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem8_mem8_0_5_s/CLKB

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT NET NAME WORST SLACK MAX DELAY
6401 clk_x1 0.036 0.931
344 eye_calib_start_rr 3.699 4.603
336 ddr_init_internal_rr 5.582 3.003
321 eye_calib_start_rr[0] 5.319 3.709
292 dqsts1 6.357 2.757
291 dqs_reg 5.497 3.551
257 phy_rddata_valid_d1 5.871 3.243
128 raddr[2] 0.036 3.125
108 n258_6 5.346 3.369
102 memory_clk 2.004 0.000

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC ROUTE CONGESTIONS
R28C74 68.06%
R11C72 62.50%
R28C71 62.50%
R28C84 61.11%
R28C68 59.72%
R28C77 59.72%
R28C83 56.94%
R28C70 56.94%
R28C72 56.94%
R22C59 56.94%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type State Detail Command
TC_CLOCK Actived create_clock -name clk4x -period 2.5 -waveform {0 1.25} [get_pins {Gowin_PLL_inst/PLLA_inst/CLKOUT2}]
TC_CLOCK Actived create_clock -name clk1x -period 10 -waveform {0 5} [get_pins {u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT}]
TC_CLOCK Actived create_clock -name clkin -period 20 -waveform {0 10} [get_ports {clk_g}]
TC_CLOCK_GROUP Actived set_clock_groups -asynchronous -group [get_clocks {clkin}] -group [get_clocks {clk4x}]
TC_CLOCK_GROUP Actived set_clock_groups -asynchronous -group [get_clocks {clk4x}] -group [get_clocks {clk1x}]
TC_CLOCK_GROUP Actived set_clock_groups -asynchronous -group [get_clocks {clkin}] -group [get_clocks {clk1x}]