Power Messages

Report Title Power Analysis Report
Design File E:\myWork\IP\releaseVerify\RefDesign\Memory_Control\DDR3\Gowin_DDR3_Memory_Interface_RefDesign\DDR3_MC_PHY_1vs4\project\impl\gwsynthesis\ddr3_1v4_hs.vg
Physical Constraints File E:\myWork\IP\releaseVerify\RefDesign\Memory_Control\DDR3\Gowin_DDR3_Memory_Interface_RefDesign\DDR3_MC_PHY_1vs4\project\src\ddr3_1v4_hs.cst
Timing Constraints File E:\myWork\IP\releaseVerify\RefDesign\Memory_Control\DDR3\Gowin_DDR3_Memory_Interface_RefDesign\DDR3_MC_PHY_1vs4\project\src\ddr3_1v4_hs.sdc
Tool Version V1.9.9.02
Part Number GW2A-LV18PG256C8/I7
Device GW2A-18
Device Version C
Created Time Wed Mar 27 10:52:15 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

Power Summary

Power Information:

Total Power (mW) 353.030
Quiescent Power (mW) 91.476
Dynamic Power (mW) 261.554

Thermal Information:

Junction Temperature 36.304
Theta JA 32.020
Max Allowed Ambient Temperature 73.696

Configure Information:

Default IO Toggle Rate 0.125
Default Remain Toggle Rate 0.125
Use Vectorless Estimation false
Filter Glitches false
Related Vcd File
Related Saif File
Use Custom Theta JA false
Air Flow LFM_0
Heat Sink None
Use Custom Theta SA false
Board Thermal Model None
Use Custom Theta JB false
Ambient Temperature 25.000

Supply Information:

Voltage Source Voltage Dynamic Current(mA) Quiescent Current(mA) Power(mW)
VCC 1.000 214.005 61.459 275.464
VCCX 2.500 11.638 11.364 57.504
VCCIO15 1.500 11.024 0.852 17.813
VCCIO33 3.300 0.582 0.100 2.249

Power Details

Power By Block Type:

Block Type Total Power(mW) Static Power(mW) Average Toggle Rate(millions of transitions/sec)
Logic 6.273 NA 12.393
IO 69.694 8.795 57.537
BSRAM 65.520 NA NA
PLL 36.611 NA NA
DLL 92.160 NA NA
DQS 231.300 NA NA

Power By Hierarchy:

Hierarchy Entity Total Power(mW) Block Dynamic Power(mW)
top 431.864 431.864(431.764)
top/u_ddr3/ 394.183 394.183(394.183)
top/u_ddr3/gw3_top/ 394.183 394.183(393.914)
top/u_ddr3/gw3_top/u_ddr_phy_top/ 392.210 392.210(299.739)
top/u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/ 0.042 0.042(0.000)
top/u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/ 0.789 0.789(0.000)
top/u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/ 297.967 297.967(297.949)
top/u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/ 181.498 181.498(181.389)
top/u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/ 115.769 115.769(0.000)
top/u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/ 0.099 0.099(0.000)
top/u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/ 65.521 65.521(0.000)
top/u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/ 115.972 115.972(115.863)
top/u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/ 115.765 115.765(0.000)
top/u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/ 0.099 0.099(0.000)
top/u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/ 0.039 0.039(0.000)
top/u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/ 0.039 0.039(0.000)
top/u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/of_fifo_ctrl_inst/ 0.036 0.036(0.000)
top/u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/ 0.363 0.363(0.251)
top/u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_cmd_fifo/ 0.154 0.154(0.000)
top/u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/ 0.097 0.097(0.000)
top/u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/ 0.000 0.000(0.000)
top/u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib/ 0.308 0.308(0.000)
top/u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/ 0.127 0.127(0.000)
top/u_ddr3/gw3_top/u_ddr_phy_top/u_init_rmove_mod/ 0.507 0.507(0.000)
top/u_ddr3/gw3_top/u_gwmc_top/ 1.704 1.704(1.444)
top/u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/ 0.431 0.431(0.000)
top/u_ddr3/gw3_top/u_gwmc_top/gw_rd_data0/ 0.195 0.195(0.000)
top/u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/ 0.385 0.385(0.305)
top/u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/ 0.305 0.305(0.000)
top/u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/ 0.335 0.335(0.000)
top/u_ddr3/gw3_top/u_gwmc_top/gwmc_rank_ctrl/ 0.066 0.066(0.000)
top/u_ddr3/gw3_top/u_gwmc_top/gwmc_timing_ctrl/ 0.033 0.033(0.000)
top/u_rd/ 0.970 0.970(0.000)
top/upll/ 36.611 36.611(0.000)

Power By Clock Domain:

Clock Domain Clock Frequency(Mhz) Total Dynamic Power(mW)
clkx1 100.000 71.774
NO CLOCK DOMAIN 0.000 0.000
clkin 50.000 36.667
clk_x4 400.000 323.514