Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | E:\myWork\IP\releaseVerify\RefDesign\Memory_Control\DDR3\Gowin_DDR3_Memory_Interface_RefDesign\DDR3_MC_PHY_1vs2\project\src\ddr3_memory_interface\ddr3_memory_interface.v E:\myWork\IP\releaseVerify\RefDesign\Memory_Control\DDR3\Gowin_DDR3_Memory_Interface_RefDesign\DDR3_MC_PHY_1vs2\project\src\ddr3_syn_top.v E:\myWork\IP\releaseVerify\RefDesign\Memory_Control\DDR3\Gowin_DDR3_Memory_Interface_RefDesign\DDR3_MC_PHY_1vs2\project\src\DDR3_test.v E:\myWork\IP\releaseVerify\RefDesign\Memory_Control\DDR3\Gowin_DDR3_Memory_Interface_RefDesign\DDR3_MC_PHY_1vs2\project\src\gowin_rpll\gowin_rpll.v C:\Gowin\Gowin_V1.9.9.02_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v C:\Gowin\Gowin_V1.9.9.02_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v C:\Gowin\Gowin_V1.9.9.02_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v C:\Gowin\Gowin_V1.9.9.02_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v C:\Gowin\Gowin_V1.9.9.02_x64\IDE\data\ipcores\GAO\GW_CON\gw_con_top.v C:\Gowin\Gowin_V1.9.9.02_x64\IDE\data\ipcores\gw_jtag.v E:\myWork\IP\releaseVerify\RefDesign\Memory_Control\DDR3\Gowin_DDR3_Memory_Interface_RefDesign\DDR3_MC_PHY_1vs2\project\impl\gwsynthesis\RTL_GAO\gw_gao_top.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.9.02 |
| Part Number | GW2A-LV18PG256C8/I7 |
| Device | GW2A-1 |
| Device Version | 8 |
| Created Time | Tue Mar 26 15:11:13 2024 |
| Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | ddr3_syn_top |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.796s, Elapsed time = 0h 0m 0.833s, Peak memory usage = 526.816MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.13s, Peak memory usage = 526.816MB Optimizing Phase 1: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.078s, Peak memory usage = 526.816MB Optimizing Phase 2: CPU time = 0h 0m 0.187s, Elapsed time = 0h 0m 0.174s, Peak memory usage = 526.816MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.057s, Peak memory usage = 526.816MB Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 526.816MB Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 526.816MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 526.816MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.265s, Elapsed time = 0h 0m 0.242s, Peak memory usage = 526.816MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.053s, Peak memory usage = 526.816MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.036s, Peak memory usage = 526.816MB Tech-Mapping Phase 3: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 526.816MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.148s, Peak memory usage = 526.816MB Generate output files: CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.212s, Peak memory usage = 526.816MB |
| Total Time and Memory Usage | CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s, Peak memory usage = 526.816MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 58 |
| I/O Buf | 55 |
| IBUF | 5 |
| OBUF | 31 |
| IOBUF | 16 |
| ELVDS_OBUF | 1 |
| ELVDS_IOBUF | 2 |
| Register | 2119 |
| DFF | 392 |
| DFFE | 4 |
| DFFR | 2 |
| DFFP | 61 |
| DFFPE | 35 |
| DFFC | 796 |
| DFFCE | 829 |
| LUT | 2011 |
| LUT2 | 449 |
| LUT3 | 453 |
| LUT4 | 1109 |
| MUX | 1 |
| MUX16 | 1 |
| ALU | 135 |
| ALU | 135 |
| SSRAM | 46 |
| RAM16S4 | 7 |
| RAM16SDP4 | 39 |
| INV | 28 |
| INV | 28 |
| IOLOGIC | 100 |
| IDES4_MEM | 16 |
| OSER4 | 24 |
| OSER4_MEM | 20 |
| IODELAY | 40 |
| BSRAM | 14 |
| SDPB | 2 |
| SDPX9B | 12 |
| CLOCK | 5 |
| CLKDIV | 1 |
| DQS | 2 |
| DHCEN | 1 |
| rPLL | 1 |
| Black Box | 1 |
| GW_JTAG | 1 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 2458(2047 LUT, 135 ALU, 46 RAM16) / 20736 | 12% |
| Register | 2119 / 16173 | 14% |
| --Register as Latch | 0 / 16173 | 0% |
| --Register as FF | 2119 / 16173 | 14% |
| BSRAM | 14 / 46 | 31% |
Timing
Clock Summary:
| Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|
| clk | Base | 20.000 | 50.0 | 0.000 | 10.000 | clk_ibuf/I | ||
| pll/rpll_inst/CLKOUT.default_gen_clk | Generated | 5.000 | 200.0 | 0.000 | 2.500 | clk_ibuf/I | clk | pll/rpll_inst/CLKOUT |
| pll/rpll_inst/CLKOUTP.default_gen_clk | Generated | 5.000 | 200.0 | 0.000 | 2.500 | clk_ibuf/I | clk | pll/rpll_inst/CLKOUTP |
| pll/rpll_inst/CLKOUTD.default_gen_clk | Generated | 10.000 | 100.0 | 0.000 | 5.000 | clk_ibuf/I | clk | pll/rpll_inst/CLKOUTD |
| pll/rpll_inst/CLKOUTD3.default_gen_clk | Generated | 15.000 | 66.7 | 0.000 | 7.500 | clk_ibuf/I | clk | pll/rpll_inst/CLKOUTD3 |
| u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | Generated | 10.000 | 100.0 | 0.000 | 5.000 | pll/rpll_inst/CLKOUT | pll/rpll_inst/CLKOUT.default_gen_clk | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
Max Frequency Summary:
| No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | clk | 50.000(MHz) | 181.884(MHz) | 6 | TOP |
| 2 | pll/rpll_inst/CLKOUT.default_gen_clk | 200.000(MHz) | 1030.927(MHz) | 1 | TOP |
| 3 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | 100.000(MHz) | 156.568(MHz) | 7 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | -3.441 |
| Data Arrival Time | 7.053 |
| Data Required Time | 3.612 |
| From | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_init/timer_cnt_7_s0 |
| To | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| Launch Clk | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[F] |
| Latch Clk | pll/rpll_inst/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
| 0.341 | 0.341 | tCL | RR | 1682 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
| 0.701 | 0.360 | tNET | RR | 1 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_init/timer_cnt_7_s0/CLK |
| 0.933 | 0.232 | tC2Q | RF | 7 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_init/timer_cnt_7_s0/Q |
| 1.407 | 0.474 | tNET | FF | 1 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_init/init_next_state.WRITE_LEVELING_s21/I1 |
| 1.962 | 0.555 | tINS | FF | 1 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_init/init_next_state.WRITE_LEVELING_s21/F |
| 2.436 | 0.474 | tNET | FF | 1 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_init/init_next_state.WRITE_LEVELING_s20/I2 |
| 2.889 | 0.453 | tINS | FF | 2 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_init/init_next_state.WRITE_LEVELING_s20/F |
| 3.363 | 0.474 | tNET | FF | 1 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_init/read_cal_next_state.READ_CAL_DONE_s18/I2 |
| 3.816 | 0.453 | tINS | FF | 4 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_init/read_cal_next_state.READ_CAL_DONE_s18/F |
| 4.290 | 0.474 | tNET | FF | 1 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_init/n1446_s4/I2 |
| 4.743 | 0.453 | tINS | FF | 2 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_init/n1446_s4/F |
| 5.217 | 0.474 | tNET | FF | 1 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_init/n1446_s1/I3 |
| 5.588 | 0.371 | tINS | FF | 11 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_init/n1446_s1/F |
| 6.062 | 0.474 | tNET | FF | 1 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_init/hold_Z_s/I0 |
| 6.579 | 0.517 | tINS | FF | 2 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_init/hold_Z_s/F |
| 7.053 | 0.474 | tNET | FF | 1 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 2.500 | 0.000 | pll/rpll_inst/CLKOUT.default_gen_clk | |||
| 3.000 | 0.500 | tCL | FF | 1 | pll/rpll_inst/CLKOUT |
| 3.474 | 0.474 | tNET | FF | 3 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclk_dhcen/CLKIN |
| 3.660 | 0.186 | tINS | FF | 64 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclk_dhcen/CLKOUT |
| 4.134 | 0.474 | tNET | FF | 1 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
| 4.099 | -0.035 | tUnc | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs | ||
| 3.612 | -0.487 | tSu | 1 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| Clock Skew: | 0.933 |
| Setup Relationship: | 2.500 |
| Logic Level: | 7 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
| Arrival Data Path Delay: | cell: 2.802, 44.112%; route: 3.318, 52.236%; tC2Q: 0.232, 3.652% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Path 2
Path Summary:| Slack | -3.441 |
| Data Arrival Time | 7.053 |
| Data Required Time | 3.612 |
| From | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_init/timer_cnt_7_s0 |
| To | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| Launch Clk | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[F] |
| Latch Clk | pll/rpll_inst/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
| 0.341 | 0.341 | tCL | RR | 1682 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
| 0.701 | 0.360 | tNET | RR | 1 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_init/timer_cnt_7_s0/CLK |
| 0.933 | 0.232 | tC2Q | RF | 7 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_init/timer_cnt_7_s0/Q |
| 1.407 | 0.474 | tNET | FF | 1 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_init/init_next_state.WRITE_LEVELING_s21/I1 |
| 1.962 | 0.555 | tINS | FF | 1 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_init/init_next_state.WRITE_LEVELING_s21/F |
| 2.436 | 0.474 | tNET | FF | 1 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_init/init_next_state.WRITE_LEVELING_s20/I2 |
| 2.889 | 0.453 | tINS | FF | 2 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_init/init_next_state.WRITE_LEVELING_s20/F |
| 3.363 | 0.474 | tNET | FF | 1 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_init/read_cal_next_state.READ_CAL_DONE_s18/I2 |
| 3.816 | 0.453 | tINS | FF | 4 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_init/read_cal_next_state.READ_CAL_DONE_s18/F |
| 4.290 | 0.474 | tNET | FF | 1 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_init/n1446_s4/I2 |
| 4.743 | 0.453 | tINS | FF | 2 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_init/n1446_s4/F |
| 5.217 | 0.474 | tNET | FF | 1 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_init/n1446_s1/I3 |
| 5.588 | 0.371 | tINS | FF | 11 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_init/n1446_s1/F |
| 6.062 | 0.474 | tNET | FF | 1 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_init/hold_Z_s/I0 |
| 6.579 | 0.517 | tINS | FF | 2 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_init/hold_Z_s/F |
| 7.053 | 0.474 | tNET | FF | 1 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 2.500 | 0.000 | pll/rpll_inst/CLKOUT.default_gen_clk | |||
| 3.000 | 0.500 | tCL | FF | 1 | pll/rpll_inst/CLKOUT |
| 3.474 | 0.474 | tNET | FF | 3 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclk_dhcen/CLKIN |
| 3.660 | 0.186 | tINS | FF | 64 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclk_dhcen/CLKOUT |
| 4.134 | 0.474 | tNET | FF | 1 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
| 4.099 | -0.035 | tUnc | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs | ||
| 3.612 | -0.487 | tSu | 1 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| Clock Skew: | 0.933 |
| Setup Relationship: | 2.500 |
| Logic Level: | 7 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
| Arrival Data Path Delay: | cell: 2.802, 44.112%; route: 3.318, 52.236%; tC2Q: 0.232, 3.652% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Path 3
Path Summary:| Slack | 1.351 |
| Data Arrival Time | 9.315 |
| Data Required Time | 10.666 |
| From | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate_12_s0 |
| To | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_wr_data0/wr_fifo/Almost_Full_s0 |
| Launch Clk | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R] |
| Latch Clk | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
| 0.341 | 0.341 | tCL | RR | 1682 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
| 0.701 | 0.360 | tNET | RR | 1 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate_12_s0/CLK |
| 0.933 | 0.232 | tC2Q | RF | 4 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate_12_s0/Q |
| 1.407 | 0.474 | tNET | FF | 1 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gwmc_bank_ctrl0/n1193_s5/I1 |
| 1.962 | 0.555 | tINS | FF | 5 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gwmc_bank_ctrl0/n1193_s5/F |
| 2.436 | 0.474 | tNET | FF | 1 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gwmc_bank_ctrl0/n1193_s1/I1 |
| 2.991 | 0.555 | tINS | FF | 21 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gwmc_bank_ctrl0/n1193_s1/F |
| 3.465 | 0.474 | tNET | FF | 1 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_wr_data0/wr_fifo/n28_s0/I1 |
| 4.020 | 0.555 | tINS | FF | 81 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_wr_data0/wr_fifo/n28_s0/F |
| 4.494 | 0.474 | tNET | FF | 1 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_wr_data0/wr_fifo/n641_s3/I3 |
| 4.865 | 0.371 | tINS | FF | 4 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_wr_data0/wr_fifo/n641_s3/F |
| 5.339 | 0.474 | tNET | FF | 1 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_wr_data0/wr_fifo/rbin_next_3_s3/I1 |
| 5.894 | 0.555 | tINS | FF | 3 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_wr_data0/wr_fifo/rbin_next_3_s3/F |
| 6.368 | 0.474 | tNET | FF | 2 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_wr_data0/wr_fifo/wcnt_sub_3_s/I1 |
| 6.923 | 0.555 | tINS | FF | 1 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_wr_data0/wr_fifo/wcnt_sub_3_s/COUT |
| 7.397 | 0.474 | tNET | FF | 1 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_wr_data0/wr_fifo/awfull_val_s17/I2 |
| 7.850 | 0.453 | tINS | FF | 1 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_wr_data0/wr_fifo/awfull_val_s17/F |
| 8.324 | 0.474 | tNET | FF | 1 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_wr_data0/wr_fifo/awfull_val_s16/I0 |
| 8.841 | 0.517 | tINS | FF | 1 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_wr_data0/wr_fifo/awfull_val_s16/F |
| 9.315 | 0.474 | tNET | FF | 1 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_wr_data0/wr_fifo/Almost_Full_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
| 10.341 | 0.341 | tCL | RR | 1682 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
| 10.701 | 0.360 | tNET | RR | 1 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_wr_data0/wr_fifo/Almost_Full_s0/CLK |
| 10.666 | -0.035 | tSu | 1 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gw_wr_data0/wr_fifo/Almost_Full_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 9 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
| Arrival Data Path Delay: | cell: 4.116, 47.783%; route: 4.266, 49.524%; tC2Q: 0.232, 2.693% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Path 4
Path Summary:| Slack | 2.187 |
| Data Arrival Time | 1.066 |
| Data Required Time | 3.253 |
| From | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/stop_reg_2_s0 |
| To | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclk_dhcen |
| Launch Clk | clk[F] |
| Latch Clk | pll/rpll_inst/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 43 | clk_ibuf/O |
| 0.360 | 0.360 | tNET | RR | 1 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/stop_reg_2_s0/CLK |
| 0.592 | 0.232 | tC2Q | RF | 1 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/stop_reg_2_s0/Q |
| 1.066 | 0.474 | tNET | FF | 1 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclk_dhcen/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 2.500 | 0.000 | pll/rpll_inst/CLKOUT.default_gen_clk | |||
| 3.000 | 0.500 | tCL | FF | 1 | pll/rpll_inst/CLKOUT |
| 3.474 | 0.474 | tNET | FF | 3 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclk_dhcen/CLKIN |
| 3.439 | -0.035 | tUnc | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclk_dhcen | ||
| 3.253 | -0.186 | tSu | 1 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclk_dhcen |
| Clock Skew: | 0.614 |
| Setup Relationship: | 2.500 |
| Logic Level: | 1 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
| Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.474, 67.139%; tC2Q: 0.232, 32.861% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Path 5
Path Summary:| Slack | 2.380 |
| Data Arrival Time | 8.286 |
| Data Required Time | 10.666 |
| From | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate_23_s0 |
| To | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gwmc_rank_ctrl0/cmd1_17_s0 |
| Launch Clk | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R] |
| Latch Clk | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
| 0.341 | 0.341 | tCL | RR | 1682 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
| 0.701 | 0.360 | tNET | RR | 1 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate_23_s0/CLK |
| 0.933 | 0.232 | tC2Q | RF | 8 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gwmc_bank_ctrl0/gwmc_pstate_23_s0/Q |
| 1.407 | 0.474 | tNET | FF | 1 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gwmc_bank_ctrl0/DQS_WAITE_CNT_3_s10/I1 |
| 1.962 | 0.555 | tINS | FF | 1 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gwmc_bank_ctrl0/DQS_WAITE_CNT_3_s10/F |
| 2.436 | 0.474 | tNET | FF | 1 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gwmc_bank_ctrl0/DQS_WAITE_CNT_3_s7/I1 |
| 2.991 | 0.555 | tINS | FF | 6 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gwmc_bank_ctrl0/DQS_WAITE_CNT_3_s7/F |
| 3.465 | 0.474 | tNET | FF | 1 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gwmc_rank_ctrl0/n235_s10/I2 |
| 3.918 | 0.453 | tINS | FF | 1 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gwmc_rank_ctrl0/n235_s10/F |
| 4.392 | 0.474 | tNET | FF | 1 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gwmc_rank_ctrl0/n235_s6/I3 |
| 4.763 | 0.371 | tINS | FF | 4 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gwmc_rank_ctrl0/n235_s6/F |
| 5.237 | 0.474 | tNET | FF | 1 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gwmc_rank_ctrl0/n255_s4/I1 |
| 5.792 | 0.555 | tINS | FF | 2 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gwmc_rank_ctrl0/n255_s4/F |
| 6.266 | 0.474 | tNET | FF | 1 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gwmc_rank_ctrl0/n255_s2/I1 |
| 6.821 | 0.555 | tINS | FF | 4 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gwmc_rank_ctrl0/n255_s2/F |
| 7.295 | 0.474 | tNET | FF | 1 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gwmc_rank_ctrl0/n238_s2/I0 |
| 7.812 | 0.517 | tINS | FF | 1 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gwmc_rank_ctrl0/n238_s2/F |
| 8.286 | 0.474 | tNET | FF | 1 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gwmc_rank_ctrl0/cmd1_17_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
| 10.341 | 0.341 | tCL | RR | 1682 | u_ddr3/u_gw3_phy_mc/u_ddr_phy_top/fclkdiv/CLKOUT |
| 10.701 | 0.360 | tNET | RR | 1 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gwmc_rank_ctrl0/cmd1_17_s0/CLK |
| 10.666 | -0.035 | tSu | 1 | u_ddr3/u_gw3_phy_mc/u_gwmc_top/gwmc_rank_ctrl0/cmd1_17_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 8 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
| Arrival Data Path Delay: | cell: 3.561, 46.948%; route: 3.792, 49.993%; tC2Q: 0.232, 3.059% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |