PnR Messages

Report Title PnR Report
Design File E:\myWork\IP\releaseVerify\version\1.9.9.02\DDR3_MC_PHY_1vs4_5a25k\project\impl\gwsynthesis\ddr3_1v4_hs.vg
Physical Constraints File E:\myWork\IP\releaseVerify\version\1.9.9.02\DDR3_MC_PHY_1vs4_5a25k\project\src\ddr3_1v4_hs.cst
Timing Constraints File E:\myWork\IP\releaseVerify\version\1.9.9.02\DDR3_MC_PHY_1vs4_5a25k\project\src\ddr3_1v4_hs.sdc
Tool Version V1.9.9.02
Part Number GW5A-LV25UG324ES
Device GW5A-25
Device Version A
Created Time Tue Mar 26 14:27:47 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

PnR Details

Place & Route Process Running placement: Placement Phase 0: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s Placement Phase 1: CPU time = 0h 0m 0.492s, Elapsed time = 0h 0m 0.492s Placement Phase 2: CPU time = 0h 0m 10s, Elapsed time = 0h 0m 10s Placement Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s Total Placement: CPU time = 0h 0m 15s, Elapsed time = 0h 0m 15s Running routing: Routing Phase 0: CPU time = 0h 0m 0.003s, Elapsed time = 0h 0m 0.003s Routing Phase 1: CPU time = 0h 0m 16s, Elapsed time = 0h 0m 16s Routing Phase 2: CPU time = 0h 0m 0.132s, Elapsed time = 0h 0m 0.132s Routing Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s Total Routing: CPU time = 0h 0m 17s, Elapsed time = 0h 0m 17s Generate output files: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s
Total Time and Memory Usage CPU time = 0h 0m 34s, Elapsed time = 0h 0m 34s, Peak memory usage = 663MB

Resource

Resource Usage Summary:

Resource Usage Utilization
Logic 4228/23040 19%
    --LUT,ALU,ROM16 4228(3747 LUT, 481 ALU, 0 ROM16) -
    --SSRAM(RAM16) 0 -
Register 6341/23685 27%
    --Logic Register as Latch 0/23040 0%
    --Logic Register as FF 6339/23040 28%
    --I/O Register as Latch 0/645 0%
    --I/O Register as FF 2/645 <1%
CLS 4818/11520 42%
I/O Port 76 -
I/O Buf 71 -
    --Input Buf 2 -
    --Output Buf 33 -
    --Inout Buf 36 -
IOLOGIC 32 IDES8_MEM
24 OSER8
40 OSER8_MEM
32 IODELAY
45%
BSRAM 8 SDPB
16 SDPX9B
43%
DSP 00%
PLL 1/6 17%
DDRDLL 1/4 25%
DCS 0/8 0%
DQCE 0/40 0%
OSC 0/1 0%
CLKDIV 1/16 7%
DLLDLY 0/8 0%
DQS 4/8 50%
DHCEN 0/16 0%

I/O Bank Usage Summary:

I/O Bank Usage
bank 0 5/30(16%)
bank 1 26/29(89%)
bank 2 22/27(81%)
bank 3 22/27(81%)
bank 4 1/35(2%)
bank 5 0/25(0%)
bank 6 0/17(0%)
bank 7 0/27(0%)
bank 10 0/4(0%)
bank 11 0/1(0%)

Global Clock Usage Summary:

Global Clock Usage
PRIMARY 2/8(25%)
LW 2/8(25%)
GCLK_PIN 13/40(33%)
PLL 1/6(17%)
DDRDLL 1/4(25%)
CLKDIV 1/16(7%)
DLLDLY 0/8(0%)

Global Clock Signals:

Signal Global Clock Location
clk_g_d PRIMARY TR TL BR
clk_x1 PRIMARY TR TL BR BL
pll_lock LW -
u_ddr3/gw3_top/ddr_rst LW -
memory_clk HCLK -

Pinout by Port Name:

Port Name Diff Pair Loc./Bank Constraint Dir. Site IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Vref Single Resistor Diff Resistor BankVccio Pull Strength
clk_g T9/4 Y in IOB29[A] LVCMOS33 OFF NONE OFF ON OFF OFF OFF OFF 3.3 MEDIUM
key D9/0 Y in IOT56[A] LVCMOS15 OFF NONE OFF ON OFF OFF OFF OFF 1.5 MEDIUM
error A8/0 Y out IOT54[B] LVCMOS15 8 NONE OFF OFF OFF OFF OFF OFF 1.5 MEDIUM
error1 B8/0 Y out IOT54[A] LVCMOS15 8 NONE OFF OFF OFF OFF OFF OFF 1.5 MEDIUM
led C8/0 Y out IOT50[B] LVCMOS15 8 NONE OFF OFF OFF OFF OFF OFF 1.5 MEDIUM
init_calib_complete A7/0 Y out IOT48[B] LVCMOS15 8 NONE OFF OFF OFF OFF OFF OFF 1.5 MEDIUM
ddr_addr[0] B11/1 Y out IOT68[A] SSTL15_I 8 NONE OFF OFF OFF OFF OFF OFF 1.5 MEDIUM
ddr_addr[1] A10/1 Y out IOT63[B] SSTL15_I 8 NONE OFF OFF OFF OFF OFF OFF 1.5 MEDIUM
ddr_addr[2] C11/1 Y out IOT61[B] SSTL15_I 8 NONE OFF OFF OFF OFF OFF OFF 1.5 MEDIUM
ddr_addr[3] F11/1 Y out IOT74[A] SSTL15_I 8 NONE OFF OFF OFF OFF OFF OFF 1.5 MEDIUM
ddr_addr[4] A14/1 Y out IOT83[B] SSTL15_I 8 NONE OFF OFF OFF OFF OFF OFF 1.5 MEDIUM
ddr_addr[5] G11/1 Y out IOT70[A] SSTL15_I 8 NONE OFF OFF OFF OFF OFF OFF 1.5 MEDIUM
ddr_addr[6] C12/1 Y out IOT76[B] SSTL15_I 8 NONE OFF OFF OFF OFF OFF OFF 1.5 MEDIUM
ddr_addr[7] F10/1 Y out IOT70[B] SSTL15_I 8 NONE OFF OFF OFF OFF OFF OFF 1.5 MEDIUM
ddr_addr[8] A12/1 Y out IOT72[B] SSTL15_I 8 NONE OFF OFF OFF OFF OFF OFF 1.5 MEDIUM
ddr_addr[9] C10/1 Y out IOT63[A] SSTL15_I 8 NONE OFF OFF OFF OFF OFF OFF 1.5 MEDIUM
ddr_addr[10] F12/1 Y out IOT80[A] SSTL15_I 8 NONE OFF OFF OFF OFF OFF OFF 1.5 MEDIUM
ddr_addr[11] A11/1 Y out IOT68[B] SSTL15_I 8 NONE OFF OFF OFF OFF OFF OFF 1.5 MEDIUM
ddr_addr[12] D12/1 Y out IOT76[A] SSTL15_I 8 NONE OFF OFF OFF OFF OFF OFF 1.5 MEDIUM
ddr_addr[13] G9/1 Y out IOT66[A] SSTL15_I 8 NONE OFF OFF OFF OFF OFF OFF 1.5 MEDIUM
ddr_bank[0] B14/1 Y out IOT83[A] SSTL15_I 8 NONE OFF OFF OFF OFF OFF OFF 1.5 MEDIUM
ddr_bank[1] E12/1 Y out IOT80[B] SSTL15_I 8 NONE OFF OFF OFF OFF OFF OFF 1.5 MEDIUM
ddr_bank[2] D11/1 Y out IOT61[A] SSTL15_I 8 NONE OFF OFF OFF OFF OFF OFF 1.5 MEDIUM
ddr_cs E13/1 Y out IOT85[B] SSTL15_I 8 NONE OFF OFF OFF OFF OFF OFF 1.5 MEDIUM
ddr_ras C15/1 Y out IOT87[A] SSTL15_I 8 NONE OFF OFF OFF OFF OFF OFF 1.5 MEDIUM
ddr_cas F13/1 Y out IOT85[A] SSTL15_I 8 NONE OFF OFF OFF OFF OFF OFF 1.5 MEDIUM
ddr_we C13/1 Y out IOT78[A] SSTL15_I 8 NONE OFF OFF OFF OFF OFF OFF 1.5 MEDIUM
ddr_ck ddr_ck_n D14,C14/1 Y out IOT89 SSTL15D_I 8 NONE OFF OFF OFF OFF OFF OFF 1.5 MEDIUM
ddr_cke A13/1 Y out IOT78[B] SSTL15_I 8 NONE OFF OFF OFF OFF OFF OFF 1.5 MEDIUM
ddr_odt E11/1 Y out IOT74[B] SSTL15_I 8 NONE OFF OFF OFF OFF OFF OFF 1.5 MEDIUM
ddr_reset_n F9/1 Y out IOT66[B] SSTL15_I 8 NONE OFF OFF OFF OFF OFF OFF 1.5 MEDIUM
ddr_dm[0] G14/2 Y out IOR7[B] SSTL15_I 8 NONE OFF OFF OFF OFF OFF OFF 1.5 MEDIUM
ddr_dm[1] H15/2 Y out IOR24[A] SSTL15_I 8 NONE OFF OFF OFF OFF OFF OFF 1.5 MEDIUM
ddr_dm[2] L16/3 Y out IOB91[B] SSTL15_I 8 NONE OFF OFF OFF OFF OFF OFF 1.5 MEDIUM
ddr_dm[3] T18/3 Y out IOB73[B] SSTL15_I 8 NONE OFF OFF OFF OFF OFF OFF 1.5 MEDIUM
ddr_dq[0] E18/2 Y io IOR16[B] SSTL15_I 8 NONE OFF NONE OFF INTERNAL OFF OFF 1.5 MEDIUM
ddr_dq[1] F15/2 Y io IOR14[A] SSTL15_I 8 NONE OFF NONE OFF INTERNAL OFF OFF 1.5 MEDIUM
ddr_dq[2] E16/2 Y io IOR16[A] SSTL15_I 8 NONE OFF NONE OFF INTERNAL OFF OFF 1.5 MEDIUM
ddr_dq[3] F14/2 Y io IOR7[A] SSTL15_I 8 NONE OFF NONE OFF INTERNAL OFF OFF 1.5 MEDIUM
ddr_dq[4] H13/2 Y io IOR18[A] SSTL15_I 8 NONE OFF NONE OFF INTERNAL OFF OFF 1.5 MEDIUM
ddr_dq[5] C17/2 Y io IOR9[A] SSTL15_I 8 NONE OFF NONE OFF INTERNAL OFF OFF 1.5 MEDIUM
ddr_dq[6] F16/2 Y io IOR14[B] SSTL15_I 8 NONE OFF NONE OFF INTERNAL OFF OFF 1.5 MEDIUM
ddr_dq[7] C18/2 Y io IOR9[B] SSTL15_I 8 NONE OFF NONE OFF INTERNAL OFF OFF 1.5 MEDIUM
ddr_dq[8] G16/2 Y io IOR22[A] SSTL15_I 8 NONE OFF NONE OFF INTERNAL OFF OFF 1.5 MEDIUM
ddr_dq[9] K12/2 Y io IOR29[A] SSTL15_I 8 NONE OFF NONE OFF INTERNAL OFF OFF 1.5 MEDIUM
ddr_dq[10] F17/2 Y io IOR20[A] SSTL15_I 8 NONE OFF NONE OFF INTERNAL OFF OFF 1.5 MEDIUM
ddr_dq[11] L12/2 Y io IOR31[A] SSTL15_I 8 NONE OFF NONE OFF INTERNAL OFF OFF 1.5 MEDIUM
ddr_dq[12] G18/2 Y io IOR22[B] SSTL15_I 8 NONE OFF NONE OFF INTERNAL OFF OFF 1.5 MEDIUM
ddr_dq[13] L13/2 Y io IOR31[B] SSTL15_I 8 NONE OFF NONE OFF INTERNAL OFF OFF 1.5 MEDIUM
ddr_dq[14] F18/2 Y io IOR20[B] SSTL15_I 8 NONE OFF NONE OFF INTERNAL OFF OFF 1.5 MEDIUM
ddr_dq[15] K13/2 Y io IOR29[B] SSTL15_I 8 NONE OFF NONE OFF INTERNAL OFF OFF 1.5 MEDIUM
ddr_dq[16] L18/3 Y io IOB83[B] SSTL15_I 8 NONE OFF NONE OFF INTERNAL OFF OFF 1.5 MEDIUM
ddr_dq[17] L15/3 Y io IOB91[A] SSTL15_I 8 NONE OFF NONE OFF INTERNAL OFF OFF 1.5 MEDIUM
ddr_dq[18] M18/3 Y io IOB81[B] SSTL15_I 8 NONE OFF NONE OFF INTERNAL OFF OFF 1.5 MEDIUM
ddr_dq[19] J16/3 Y io IOB87[A] SSTL15_I 8 NONE OFF NONE OFF INTERNAL OFF OFF 1.5 MEDIUM
ddr_dq[20] L17/3 Y io IOB83[A] SSTL15_I 8 NONE OFF NONE OFF INTERNAL OFF OFF 1.5 MEDIUM
ddr_dq[21] H18/3 Y io IOB89[B] SSTL15_I 8 NONE OFF NONE OFF INTERNAL OFF OFF 1.5 MEDIUM
ddr_dq[22] M16/3 Y io IOB81[A] SSTL15_I 8 NONE OFF NONE OFF INTERNAL OFF OFF 1.5 MEDIUM
ddr_dq[23] H17/3 Y io IOB89[A] SSTL15_I 8 NONE OFF NONE OFF INTERNAL OFF OFF 1.5 MEDIUM
ddr_dq[24] P17/3 Y io IOB77[A] SSTL15_I 8 NONE OFF NONE OFF INTERNAL OFF OFF 1.5 MEDIUM
ddr_dq[25] T17/3 Y io IOB73[A] SSTL15_I 8 NONE OFF NONE OFF INTERNAL OFF OFF 1.5 MEDIUM
ddr_dq[26] N17/3 Y io IOB79[A] SSTL15_I 8 NONE OFF NONE OFF INTERNAL OFF OFF 1.5 MEDIUM
ddr_dq[27] N14/3 Y io IOB69[B] SSTL15_I 8 NONE OFF NONE OFF INTERNAL OFF OFF 1.5 MEDIUM
ddr_dq[28] P18/3 Y io IOB77[B] SSTL15_I 8 NONE OFF NONE OFF INTERNAL OFF OFF 1.5 MEDIUM
ddr_dq[29] U17/3 Y io IOB71[A] SSTL15_I 8 NONE OFF NONE OFF INTERNAL OFF OFF 1.5 MEDIUM
ddr_dq[30] N18/3 Y io IOB79[B] SSTL15_I 8 NONE OFF NONE OFF INTERNAL OFF OFF 1.5 MEDIUM
ddr_dq[31] U18/3 Y io IOB71[B] SSTL15_I 8 NONE OFF NONE OFF INTERNAL OFF OFF 1.5 MEDIUM
ddr_dqs[0] ddr_dqs_n[0] D17,D18/2 Y io IOR12 SSTL15D_I 8 NONE OFF NONE OFF OFF OFF OFF 1.5 MEDIUM
ddr_dqs[1] ddr_dqs_n[1] J13,K14/2 Y io IOR26 SSTL15D_I 8 NONE OFF NONE OFF OFF OFF OFF 1.5 MEDIUM
ddr_dqs[2] ddr_dqs_n[2] K17,K18/3 Y io IOB85 SSTL15D_I 8 NONE OFF NONE OFF OFF OFF OFF 1.5 MEDIUM
ddr_dqs[3] ddr_dqs_n[3] N15,N16/3 Y io IOB75 SSTL15D_I 8 NONE OFF NONE OFF OFF OFF OFF 1.5 MEDIUM

All Package Pins:

Loc./Bank Signal Dir. Site IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Vref Single Resistor Diff Resistor Bank Vccio Pull Strength
H4/7 - in IOT1[A] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
H3/7 - in IOT1[B] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
L5/7 - in IOT3[A] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
K5/7 - in IOT3[B] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
H5/7 - in IOT5[B] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
G3/7 - in IOT7[A] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
G1/7 - in IOT7[B] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
H7/7 - in IOT9[A] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
G6/7 - in IOT9[B] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
F2/7 - in IOT11[A] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
F1/7 - in IOT11[B] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
J7/7 - in IOT13[A] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
J6/7 - in IOT13[B] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
E3/7 - in IOT15[A] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
E1/7 - in IOT15[B] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
F4/7 - in IOT17[A] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
F3/7 - in IOT17[B] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
D2/7 - in IOT19[A] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
D1/7 - in IOT19[B] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
L7/7 - in IOT21[A] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
K6/7 - in IOT21[B] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
E4/7 - in IOT23[A] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
D3/7 - in IOT23[B] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
F6/7 - in IOT25[A] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
F5/7 - in IOT25[B] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
C2/7 - in IOT27[A] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
C1/7 - in IOT27[B] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
D4/0 - in IOT29[A] LVCMOS15 8 DOWN OFF ON OFF OFF OFF OFF 1.5 MEDIUM
C4/0 - in IOT29[B] LVCMOS15 8 UP OFF ON OFF OFF OFF OFF 1.5 MEDIUM
B2/0 - in IOT31[A] LVCMOS15 8 UP OFF ON OFF OFF OFF OFF 1.5 MEDIUM
A2/0 - in IOT31[B] LVCMOS15 8 UP OFF ON OFF OFF OFF OFF 1.5 MEDIUM
D6/0 - in IOT33[A] LVCMOS15 8 UP OFF ON OFF OFF OFF OFF 1.5 MEDIUM
C6/0 - in IOT33[B] LVCMOS15 8 UP OFF ON OFF OFF OFF OFF 1.5 MEDIUM
B3/0 - in IOT35[A] LVCMOS15 8 UP OFF ON OFF OFF OFF OFF 1.5 MEDIUM
A3/0 - in IOT35[B] LVCMOS15 8 UP OFF ON OFF OFF OFF OFF 1.5 MEDIUM
B4/0 - in IOT37[A] LVCMOS15 8 UP OFF ON OFF OFF OFF OFF 1.5 MEDIUM
A4/0 - in IOT37[B] LVCMOS15 8 UP OFF ON OFF OFF OFF OFF 1.5 MEDIUM
C5/0 - in IOT39[A] LVCMOS15 8 UP OFF ON OFF OFF OFF OFF 1.5 MEDIUM
A5/0 - in IOT39[B] LVCMOS15 8 UP OFF ON OFF OFF OFF OFF 1.5 MEDIUM
F7/0 - in IOT41[A] LVCMOS15 8 UP OFF ON OFF OFF OFF OFF 1.5 MEDIUM
E6/0 - in IOT41[B] LVCMOS15 8 UP OFF ON OFF OFF OFF OFF 1.5 MEDIUM
B6/0 - in IOT43[A] LVCMOS15 8 UP OFF ON OFF OFF OFF OFF 1.5 MEDIUM
A6/0 - in IOT43[B] LVCMOS15 8 UP OFF ON OFF OFF OFF OFF 1.5 MEDIUM
E7/0 - in IOT45[A] LVCMOS15 8 UP OFF ON OFF OFF OFF OFF 1.5 MEDIUM
E8/0 - in IOT45[B] LVCMOS15 8 UP OFF ON OFF OFF OFF OFF 1.5 MEDIUM
C7/0 - in IOT48[A] LVCMOS15 8 UP OFF ON OFF OFF OFF OFF 1.5 MEDIUM
A7/0 init_calib_complete out IOT48[B] LVCMOS15 8 NONE OFF OFF OFF OFF OFF OFF 1.5 MEDIUM
D8/0 - in IOT50[A] LVCMOS15 8 UP OFF ON OFF OFF OFF OFF 1.5 MEDIUM
C8/0 led out IOT50[B] LVCMOS15 8 NONE OFF OFF OFF OFF OFF OFF 1.5 MEDIUM
G8/0 - in IOT52[A] LVCMOS15 8 UP OFF ON OFF OFF OFF OFF 1.5 MEDIUM
F8/0 - in IOT52[B] LVCMOS15 8 UP OFF ON OFF OFF OFF OFF 1.5 MEDIUM
B8/0 error1 out IOT54[A] LVCMOS15 8 NONE OFF OFF OFF OFF OFF OFF 1.5 MEDIUM
A8/0 error out IOT54[B] LVCMOS15 8 NONE OFF OFF OFF OFF OFF OFF 1.5 MEDIUM
D9/0 key in IOT56[A] LVCMOS15 OFF NONE OFF ON OFF OFF OFF OFF 1.5 MEDIUM
C9/0 - in IOT56[B] LVCMOS15 8 UP OFF ON OFF OFF OFF OFF 1.5 MEDIUM
B9/0 - in IOT58[A] LVCMOS15 8 UP OFF ON OFF OFF OFF OFF 1.5 MEDIUM
A9/0 - in IOT58[B] LVCMOS15 8 UP OFF ON OFF OFF OFF OFF 1.5 MEDIUM
D11/1 ddr_bank[2] out IOT61[A] SSTL15_I 8 NONE OFF OFF OFF OFF OFF OFF 1.5 MEDIUM
C11/1 ddr_addr[2] out IOT61[B] SSTL15_I 8 NONE OFF OFF OFF OFF OFF OFF 1.5 MEDIUM
C10/1 ddr_addr[9] out IOT63[A] SSTL15_I 8 NONE OFF OFF OFF OFF OFF OFF 1.5 MEDIUM
A10/1 ddr_addr[1] out IOT63[B] SSTL15_I 8 NONE OFF OFF OFF OFF OFF OFF 1.5 MEDIUM
G9/1 ddr_addr[13] out IOT66[A] SSTL15_I 8 NONE OFF OFF OFF OFF OFF OFF 1.5 MEDIUM
F9/1 ddr_reset_n out IOT66[B] SSTL15_I 8 NONE OFF OFF OFF OFF OFF OFF 1.5 MEDIUM
B11/1 ddr_addr[0] out IOT68[A] SSTL15_I 8 NONE OFF OFF OFF OFF OFF OFF 1.5 MEDIUM
A11/1 ddr_addr[11] out IOT68[B] SSTL15_I 8 NONE OFF OFF OFF OFF OFF OFF 1.5 MEDIUM
G11/1 ddr_addr[5] out IOT70[A] SSTL15_I 8 NONE OFF OFF OFF OFF OFF OFF 1.5 MEDIUM
F10/1 ddr_addr[7] out IOT70[B] SSTL15_I 8 NONE OFF OFF OFF OFF OFF OFF 1.5 MEDIUM
A12/1 ddr_addr[8] out IOT72[B] SSTL15_I 8 NONE OFF OFF OFF OFF OFF OFF 1.5 MEDIUM
F11/1 ddr_addr[3] out IOT74[A] SSTL15_I 8 NONE OFF OFF OFF OFF OFF OFF 1.5 MEDIUM
E11/1 ddr_odt out IOT74[B] SSTL15_I 8 NONE OFF OFF OFF OFF OFF OFF 1.5 MEDIUM
D12/1 ddr_addr[12] out IOT76[A] SSTL15_I 8 NONE OFF OFF OFF OFF OFF OFF 1.5 MEDIUM
C12/1 ddr_addr[6] out IOT76[B] SSTL15_I 8 NONE OFF OFF OFF OFF OFF OFF 1.5 MEDIUM
C13/1 ddr_we out IOT78[A] SSTL15_I 8 NONE OFF OFF OFF OFF OFF OFF 1.5 MEDIUM
A13/1 ddr_cke out IOT78[B] SSTL15_I 8 NONE OFF OFF OFF OFF OFF OFF 1.5 MEDIUM
F12/1 ddr_addr[10] out IOT80[A] SSTL15_I 8 NONE OFF OFF OFF OFF OFF OFF 1.5 MEDIUM
E12/1 ddr_bank[1] out IOT80[B] SSTL15_I 8 NONE OFF OFF OFF OFF OFF OFF 1.5 MEDIUM
B14/1 ddr_bank[0] out IOT83[A] SSTL15_I 8 NONE OFF OFF OFF OFF OFF OFF 1.5 MEDIUM
A14/1 ddr_addr[4] out IOT83[B] SSTL15_I 8 NONE OFF OFF OFF OFF OFF OFF 1.5 MEDIUM
F13/1 ddr_cas out IOT85[A] SSTL15_I 8 NONE OFF OFF OFF OFF OFF OFF 1.5 MEDIUM
E13/1 ddr_cs out IOT85[B] SSTL15_I 8 NONE OFF OFF OFF OFF OFF OFF 1.5 MEDIUM
C15/1 ddr_ras out IOT87[A] SSTL15_I 8 NONE OFF OFF OFF OFF OFF OFF 1.5 MEDIUM
A15/1 - in IOT87[B] LVCMOS15 8 UP OFF ON OFF OFF OFF OFF 1.5 MEDIUM
D14/1 ddr_ck out IOT89[A] SSTL15D_I 8 NONE OFF OFF OFF OFF OFF OFF 1.5 MEDIUM
C14/1 ddr_ck_n out IOT89[B] SSTL15D_I 8 NONE OFF OFF OFF OFF OFF OFF 1.5 MEDIUM
B16/1 - in IOT91[A] LVCMOS15 8 UP OFF ON OFF OFF OFF OFF 1.5 MEDIUM
A16/1 - in IOT91[B] LVCMOS15 8 UP OFF ON OFF OFF OFF OFF 1.5 MEDIUM
V2/5 - in IOB1[A] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
T4/5 - in IOB2[A] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
N5/5 - in IOB4[A] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
P6/5 - in IOB4[B] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
R7/5 - in IOB6[A] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
T7/5 - in IOB6[B] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
R3/5 - in IOB8[A] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
T3/5 - in IOB8[B] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
U5/5 - in IOB10[A] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
V5/5 - in IOB10[B] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
R5/5 - in IOB12[A] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
T5/5 - in IOB12[B] LVCMOS33 8 DOWN OFF ON OFF OFF OFF OFF 3.3 MEDIUM
N6/5 - in IOB14[A] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
P7/5 - in IOB14[B] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
T6/5 - in IOB16[A] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
V6/5 - in IOB16[B] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
P8/5 - in IOB18[B] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
U7/5 - in IOB20[A] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
V7/5 - in IOB20[B] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
U8/5 - in IOB22[A] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
V8/5 - in IOB22[B] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
M8/5 - in IOB24[A] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
N8/5 - in IOB24[B] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
M10/5 - in IOB26[A] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
N9/5 - in IOB26[B] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
T9/4 clk_g in IOB29[A] LVCMOS33 OFF NONE OFF ON OFF OFF OFF OFF 3.3 MEDIUM
V9/4 - in IOB29[B] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
R8/4 - in IOB31[A] LVCMOS33 8 NONE OFF ON OFF OFF OFF OFF 3.3 MEDIUM
T8/4 - in IOB31[B] LVCMOS33 8 NONE OFF ON OFF OFF OFF OFF 3.3 MEDIUM
U10/4 - in IOB33[A] LVCMOS33 8 NONE OFF ON OFF OFF OFF OFF 3.3 MEDIUM
V10/4 - in IOB33[B] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
R10/4 - in IOB35[A] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
T10/4 - in IOB35[B] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
U3/4 - in IOB37[A] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
V3/4 - in IOB37[B] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
U11/4 - in IOB39[A] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
V11/4 - in IOB39[B] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
N10/4 - in IOB41[A] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
P11/4 - in IOB41[B] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
T12/4 - in IOB43[A] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
V12/4 - in IOB43[B] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
R11/4 - in IOB45[A] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
T11/4 - in IOB45[B] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
M11/4 - in IOB48[A] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
N11/4 - in IOB48[B] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
U13/4 - in IOB50[A] LVCMOS33 8 NONE OFF ON OFF OFF OFF OFF 3.3 MEDIUM
V13/4 - in IOB50[B] LVCMOS33 8 NONE OFF ON OFF OFF OFF OFF 3.3 MEDIUM
N12/4 - in IOB52[A] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
P12/4 - in IOB52[B] LVCMOS33 8 NONE OFF ON OFF OFF OFF OFF 3.3 MEDIUM
T14/4 - in IOB54[A] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
V14/4 - in IOB54[B] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
U15/4 - in IOB56[A] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
V15/4 - in IOB56[B] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
R13/4 - in IOB58[A] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
T13/4 - in IOB58[B] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
U16/4 - in IOB60[A] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
V16/4 - in IOB60[B] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
R15/4 - in IOB62[A] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
T15/4 - in IOB62[B] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
V17/4 - in IOB64[A] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
P15/3 - in IOB65[A] LVCMOS15 8 UP OFF ON OFF OFF OFF OFF 1.5 MEDIUM
P16/3 - out IOB65[B] LVCMOS15 8 UP OFF OFF OFF OFF OFF OFF 1.5 MEDIUM
L14/3 - in IOB67[A] LVCMOS15 8 UP OFF ON OFF OFF OFF OFF 1.5 MEDIUM
M13/3 - in IOB67[B] LVCMOS15 8 UP OFF ON OFF OFF OFF OFF 1.5 MEDIUM
M14/3 - in IOB69[A] LVCMOS15 8 UP OFF ON OFF OFF OFF OFF 1.5 MEDIUM
N14/3 ddr_dq[27] io IOB69[B] SSTL15_I 8 NONE OFF NONE OFF INTERNAL OFF OFF 1.5 MEDIUM
U17/3 ddr_dq[29] io IOB71[A] SSTL15_I 8 NONE OFF NONE OFF INTERNAL OFF OFF 1.5 MEDIUM
U18/3 ddr_dq[31] io IOB71[B] SSTL15_I 8 NONE OFF NONE OFF INTERNAL OFF OFF 1.5 MEDIUM
T17/3 ddr_dq[25] io IOB73[A] SSTL15_I 8 NONE OFF NONE OFF INTERNAL OFF OFF 1.5 MEDIUM
T18/3 ddr_dm[3] out IOB73[B] SSTL15_I 8 NONE OFF OFF OFF OFF OFF OFF 1.5 MEDIUM
N15/3 ddr_dqs[3] io IOB75[A] SSTL15D_I 8 NONE OFF NONE OFF OFF OFF OFF 1.5 MEDIUM
N16/3 ddr_dqs_n[3] io IOB75[B] SSTL15D_I 8 NONE OFF NONE OFF OFF OFF OFF 1.5 MEDIUM
P17/3 ddr_dq[24] io IOB77[A] SSTL15_I 8 NONE OFF NONE OFF INTERNAL OFF OFF 1.5 MEDIUM
P18/3 ddr_dq[28] io IOB77[B] SSTL15_I 8 NONE OFF NONE OFF INTERNAL OFF OFF 1.5 MEDIUM
N17/3 ddr_dq[26] io IOB79[A] SSTL15_I 8 NONE OFF NONE OFF INTERNAL OFF OFF 1.5 MEDIUM
N18/3 ddr_dq[30] io IOB79[B] SSTL15_I 8 NONE OFF NONE OFF INTERNAL OFF OFF 1.5 MEDIUM
M16/3 ddr_dq[22] io IOB81[A] SSTL15_I 8 NONE OFF NONE OFF INTERNAL OFF OFF 1.5 MEDIUM
M18/3 ddr_dq[18] io IOB81[B] SSTL15_I 8 NONE OFF NONE OFF INTERNAL OFF OFF 1.5 MEDIUM
L17/3 ddr_dq[20] io IOB83[A] SSTL15_I 8 NONE OFF NONE OFF INTERNAL OFF OFF 1.5 MEDIUM
L18/3 ddr_dq[16] io IOB83[B] SSTL15_I 8 NONE OFF NONE OFF INTERNAL OFF OFF 1.5 MEDIUM
K17/3 ddr_dqs[2] io IOB85[A] SSTL15D_I 8 NONE OFF NONE OFF OFF OFF OFF 1.5 MEDIUM
K18/3 ddr_dqs_n[2] io IOB85[B] SSTL15D_I 8 NONE OFF NONE OFF OFF OFF OFF 1.5 MEDIUM
J16/3 ddr_dq[19] io IOB87[A] SSTL15_I 8 NONE OFF NONE OFF INTERNAL OFF OFF 1.5 MEDIUM
H17/3 ddr_dq[23] io IOB89[A] SSTL15_I 8 NONE OFF NONE OFF INTERNAL OFF OFF 1.5 MEDIUM
H18/3 ddr_dq[21] io IOB89[B] SSTL15_I 8 NONE OFF NONE OFF INTERNAL OFF OFF 1.5 MEDIUM
L15/3 ddr_dq[17] io IOB91[A] SSTL15_I 8 NONE OFF NONE OFF INTERNAL OFF OFF 1.5 MEDIUM
L16/3 ddr_dm[2] out IOB91[B] SSTL15_I 8 NONE OFF OFF OFF OFF OFF OFF 1.5 MEDIUM
H2/6 - in IOL3[A] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
H1/6 - in IOL3[B] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
K4/6 - in IOL5[A] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
K3/6 - in IOL5[B] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
J1/6 - in IOL7[B] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
L4/6 - in IOL9[A] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
L3/6 - in IOL9[B] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
K2/6 - in IOL12[A] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
K1/6 - in IOL12[B] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
L2/6 - in IOL14[A] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
L1/6 - in IOL14[B] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
M3/6 - in IOL16[A] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
M1/6 - in IOL16[B] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
N2/6 - in IOL18[A] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
N1/6 - in IOL18[B] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
P2/6 - in IOL21[A] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
P1/6 - in IOL21[B] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
A17/10 - in IOR1[A] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
D15/10 - in IOR1[B] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
B18/10 - in IOR3[A] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM
D16/10 - out IOR3[B] LVCMOS33 8 UP OFF OFF OFF OFF OFF OFF 3.3 MEDIUM
H12/2 - in IOR5[A] LVCMOS15 8 UP OFF ON OFF OFF OFF OFF 1.5 MEDIUM
G13/2 - in IOR5[B] LVCMOS15 8 UP OFF ON OFF OFF OFF OFF 1.5 MEDIUM
F14/2 ddr_dq[3] io IOR7[A] SSTL15_I 8 NONE OFF NONE OFF INTERNAL OFF OFF 1.5 MEDIUM
G14/2 ddr_dm[0] out IOR7[B] SSTL15_I 8 NONE OFF OFF OFF OFF OFF OFF 1.5 MEDIUM
C17/2 ddr_dq[5] io IOR9[A] SSTL15_I 8 NONE OFF NONE OFF INTERNAL OFF OFF 1.5 MEDIUM
C18/2 ddr_dq[7] io IOR9[B] SSTL15_I 8 NONE OFF NONE OFF INTERNAL OFF OFF 1.5 MEDIUM
D17/2 ddr_dqs[0] io IOR12[A] SSTL15D_I 8 NONE OFF NONE OFF OFF OFF OFF 1.5 MEDIUM
D18/2 ddr_dqs_n[0] io IOR12[B] SSTL15D_I 8 NONE OFF NONE OFF OFF OFF OFF 1.5 MEDIUM
F15/2 ddr_dq[1] io IOR14[A] SSTL15_I 8 NONE OFF NONE OFF INTERNAL OFF OFF 1.5 MEDIUM
F16/2 ddr_dq[6] io IOR14[B] SSTL15_I 8 NONE OFF NONE OFF INTERNAL OFF OFF 1.5 MEDIUM
E16/2 ddr_dq[2] io IOR16[A] SSTL15_I 8 NONE OFF NONE OFF INTERNAL OFF OFF 1.5 MEDIUM
E18/2 ddr_dq[0] io IOR16[B] SSTL15_I 8 NONE OFF NONE OFF INTERNAL OFF OFF 1.5 MEDIUM
H13/2 ddr_dq[4] io IOR18[A] SSTL15_I 8 NONE OFF NONE OFF INTERNAL OFF OFF 1.5 MEDIUM
H14/2 - in IOR18[B] LVCMOS15 8 UP OFF ON OFF OFF OFF OFF 1.5 MEDIUM
F17/2 ddr_dq[10] io IOR20[A] SSTL15_I 8 NONE OFF NONE OFF INTERNAL OFF OFF 1.5 MEDIUM
F18/2 ddr_dq[14] io IOR20[B] SSTL15_I 8 NONE OFF NONE OFF INTERNAL OFF OFF 1.5 MEDIUM
G16/2 ddr_dq[8] io IOR22[A] SSTL15_I 8 NONE OFF NONE OFF INTERNAL OFF OFF 1.5 MEDIUM
G18/2 ddr_dq[12] io IOR22[B] SSTL15_I 8 NONE OFF NONE OFF INTERNAL OFF OFF 1.5 MEDIUM
H15/2 ddr_dm[1] out IOR24[A] SSTL15_I 8 NONE OFF OFF OFF OFF OFF OFF 1.5 MEDIUM
J13/2 ddr_dqs[1] io IOR26[A] SSTL15D_I 8 NONE OFF NONE OFF OFF OFF OFF 1.5 MEDIUM
K14/2 ddr_dqs_n[1] io IOR26[B] SSTL15D_I 8 NONE OFF NONE OFF OFF OFF OFF 1.5 MEDIUM
K12/2 ddr_dq[9] io IOR29[A] SSTL15_I 8 NONE OFF NONE OFF INTERNAL OFF OFF 1.5 MEDIUM
K13/2 ddr_dq[15] io IOR29[B] SSTL15_I 8 NONE OFF NONE OFF INTERNAL OFF OFF 1.5 MEDIUM
L12/2 ddr_dq[11] io IOR31[A] SSTL15_I 8 NONE OFF NONE OFF INTERNAL OFF OFF 1.5 MEDIUM
L13/2 ddr_dq[13] io IOR31[B] SSTL15_I 8 NONE OFF NONE OFF INTERNAL OFF OFF 1.5 MEDIUM
K15/2 - in IOR33[A] LVCMOS15 8 UP OFF ON OFF OFF OFF OFF 1.5 MEDIUM
K16/2 - in IOR33[B] LVCMOS15 8 UP OFF ON OFF OFF OFF OFF 1.5 MEDIUM
R16/11 - in IOR35[A] LVCMOS33 8 UP OFF ON OFF OFF OFF OFF 3.3 MEDIUM