Timing Messages
Report Title | Timing Analysis Report |
Design File | E:\myWork\IP\releaseVerify\RefDesign\Memory_Control\DDR3\Gowin_DDR3_Memory_Interface_RefDesign\DDR3_MC_PHY_1vs4_5a138k\project\impl\gwsynthesis\ddr3_1v4_hs.vg |
Physical Constraints File | E:\myWork\IP\releaseVerify\RefDesign\Memory_Control\DDR3\Gowin_DDR3_Memory_Interface_RefDesign\DDR3_MC_PHY_1vs4_5a138k\project\src\ddr3_1v4_hs.cst |
Timing Constraint File | E:\myWork\IP\releaseVerify\RefDesign\Memory_Control\DDR3\Gowin_DDR3_Memory_Interface_RefDesign\DDR3_MC_PHY_1vs4_5a138k\project\src\ddr3_1v4_hs.sdc |
Tool Version | V1.9.9.02 |
Part Number | GW5AST-LV138FPG676AES |
Device | GW5AST-138 |
Device Version | B |
Created Time | Tue Mar 26 14:39:28 2024 |
Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved. |
Timing Summaries
STA Tool Run Summary:
Setup Delay Model | Slow 0.855V 0C ES |
Hold Delay Model | Fast 0.945V 85C ES |
Numbers of Paths Analyzed | 15252 |
Numbers of Endpoints Analyzed | 21727 |
Numbers of Falling Endpoints | 0 |
Numbers of Setup Violated Endpoints | 0 |
Numbers of Hold Violated Endpoints | 0 |
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Objects |
---|---|---|---|---|---|---|---|---|
clk400 | Base | 2.500 | 400.000 | 0.000 | 1.250 | memory_clk | ||
clk100 | Base | 10.000 | 100.000 | 0.000 | 5.000 | clk | ||
sysclk | Base | 10.000 | 100.000 | 0.000 | 5.000 | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
Max Frequency Summary:
NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | clk400 | 400.000(MHz) | 2016.130(MHz) | 1 | TOP |
2 | clk100 | 100.000(MHz) | 196.512(MHz) | 6 | TOP |
3 | sysclk | 100.000(MHz) | 100.125(MHz) | 8 | TOP |
Total Negative Slack Summary:
Clock Name | Analysis Type | Endpoints TNS | Number of Endpoints |
---|---|---|---|
clk400 | Setup | 0.000 | 0 |
clk400 | Hold | 0.000 | 0 |
clk100 | Setup | 0.000 | 0 |
clk100 | Hold | 0.000 | 0 |
sysclk | Setup | 0.000 | 0 |
sysclk | Hold | 0.000 | 0 |
Timing Details
Path Slacks Table:
Setup Paths Table
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 0.013 | u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_1_s0/Q | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/idle3_s0/D | sysclk:[R] | sysclk:[R] | 10.000 | -0.007 | 9.931 |
2 | 0.022 | u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_1_s0/Q | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_READ_s6/D | sysclk:[R] | sysclk:[R] | 10.000 | -0.017 | 9.931 |
3 | 0.068 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts_rr_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[2].u_oser8_mem/TX0 | sysclk:[R] | sysclk:[R] | 10.000 | 0.057 | 9.612 |
4 | 0.091 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts0_rr_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/TX3 | sysclk:[R] | sysclk:[R] | 10.000 | 0.064 | 9.582 |
5 | 0.091 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts0_rr_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/TX2 | sysclk:[R] | sysclk:[R] | 10.000 | 0.064 | 9.582 |
6 | 0.113 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts0_rr_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[4].u_oser8_mem/TX3 | sysclk:[R] | sysclk:[R] | 10.000 | 0.037 | 9.587 |
7 | 0.113 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts0_rr_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[4].u_oser8_mem/TX2 | sysclk:[R] | sysclk:[R] | 10.000 | 0.037 | 9.587 |
8 | 0.123 | u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_1_s0/Q | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/idle2_s0/D | sysclk:[R] | sysclk:[R] | 10.000 | -0.007 | 9.821 |
9 | 0.242 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts0_rr_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/TX1 | sysclk:[R] | sysclk:[R] | 10.000 | 0.064 | 9.431 |
10 | 0.249 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts0_rr_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[2].u_oser8_mem/TX1 | sysclk:[R] | sysclk:[R] | 10.000 | 0.057 | 9.431 |
11 | 0.264 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts0_rr_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[4].u_oser8_mem/TX1 | sysclk:[R] | sysclk:[R] | 10.000 | 0.037 | 9.436 |
12 | 0.273 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts_rr_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[4].u_oser8_mem/TX0 | sysclk:[R] | sysclk:[R] | 10.000 | 0.037 | 9.427 |
13 | 0.290 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts0_rr_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[2].u_oser8_mem/TX3 | sysclk:[R] | sysclk:[R] | 10.000 | 0.057 | 9.390 |
14 | 0.290 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts0_rr_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[2].u_oser8_mem/TX2 | sysclk:[R] | sysclk:[R] | 10.000 | 0.057 | 9.390 |
15 | 0.478 | u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_0_s1/Q | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_ACT2WR_s10/D | sysclk:[R] | sysclk:[R] | 10.000 | -0.006 | 9.465 |
16 | 0.621 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts0_rr_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/TX3 | sysclk:[R] | sysclk:[R] | 10.000 | 0.071 | 9.045 |
17 | 0.621 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts0_rr_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/TX2 | sysclk:[R] | sysclk:[R] | 10.000 | 0.071 | 9.045 |
18 | 0.629 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts_rr_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/TX0 | sysclk:[R] | sysclk:[R] | 10.000 | 0.071 | 9.036 |
19 | 0.670 | u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_1_s0/Q | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_WRITE_s4/D | sysclk:[R] | sysclk:[R] | 10.000 | 0.000 | 9.266 |
20 | 0.772 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts0_rr_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/TX1 | sysclk:[R] | sysclk:[R] | 10.000 | 0.071 | 8.894 |
21 | 0.820 | u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_0_s1/Q | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_IDLE_s2/D | sysclk:[R] | sysclk:[R] | 10.000 | -0.035 | 9.151 |
22 | 0.834 | u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_0_s1/Q | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/idle1_s0/D | sysclk:[R] | sysclk:[R] | 10.000 | -0.028 | 9.130 |
23 | 0.839 | u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_0_s1/Q | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_W2R_s8/D | sysclk:[R] | sysclk:[R] | 10.000 | -0.035 | 9.133 |
24 | 0.883 | u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_1_s0/Q | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_ACT_WR_s4/D | sysclk:[R] | sysclk:[R] | 10.000 | 0.014 | 9.038 |
25 | 0.977 | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts0_rr_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/TX3 | sysclk:[R] | sysclk:[R] | 10.000 | 0.075 | 8.685 |
Hold Paths Table
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 0.048 | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_126_s0/Q | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_3_s/DI[18] | sysclk:[R] | sysclk:[R] | 0.000 | 0.001 | 0.296 |
2 | 0.053 | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_172_s0/Q | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_4_s/DI[28] | sysclk:[R] | sysclk:[R] | 0.000 | 0.006 | 0.296 |
3 | 0.054 | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_188_s0/Q | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_5_s/DI[8] | sysclk:[R] | sysclk:[R] | 0.000 | 0.006 | 0.296 |
4 | 0.054 | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_117_s0/Q | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_3_s/DI[9] | sysclk:[R] | sysclk:[R] | 0.000 | 0.006 | 0.296 |
5 | 0.054 | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_113_s0/Q | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_3_s/DI[5] | sysclk:[R] | sysclk:[R] | 0.000 | 0.006 | 0.296 |
6 | 0.067 | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_36_s0/Q | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s/DI[0] | sysclk:[R] | sysclk:[R] | 0.000 | 0.012 | 0.304 |
7 | 0.067 | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_28_s0/Q | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s/DI[28] | sysclk:[R] | sysclk:[R] | 0.000 | 0.013 | 0.304 |
8 | 0.077 | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_62_s0/Q | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s/DI[26] | sysclk:[R] | sysclk:[R] | 0.000 | 0.022 | 0.304 |
9 | 0.161 | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_37_s0/Q | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s/DI[1] | sysclk:[R] | sysclk:[R] | 0.000 | 0.012 | 0.397 |
10 | 0.161 | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_33_s0/Q | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s/DI[33] | sysclk:[R] | sysclk:[R] | 0.000 | 0.013 | 0.397 |
11 | 0.161 | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_32_s0/Q | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s/DI[32] | sysclk:[R] | sysclk:[R] | 0.000 | 0.013 | 0.397 |
12 | 0.161 | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_26_s0/Q | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s/DI[26] | sysclk:[R] | sysclk:[R] | 0.000 | 0.013 | 0.397 |
13 | 0.164 | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_119_s0/Q | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_3_s/DI[11] | sysclk:[R] | sysclk:[R] | 0.000 | -0.004 | 0.416 |
14 | 0.164 | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_112_s0/Q | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_3_s/DI[4] | sysclk:[R] | sysclk:[R] | 0.000 | -0.004 | 0.416 |
15 | 0.166 | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_59_s0/Q | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s/DI[23] | sysclk:[R] | sysclk:[R] | 0.000 | 0.018 | 0.397 |
16 | 0.166 | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_55_s0/Q | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s/DI[19] | sysclk:[R] | sysclk:[R] | 0.000 | 0.018 | 0.397 |
17 | 0.166 | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_49_s0/Q | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s/DI[13] | sysclk:[R] | sysclk:[R] | 0.000 | 0.018 | 0.397 |
18 | 0.169 | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_154_s0/Q | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_4_s/DI[10] | sysclk:[R] | sysclk:[R] | 0.000 | 0.001 | 0.416 |
19 | 0.169 | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_22_s0/Q | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s/DI[22] | sysclk:[R] | sysclk:[R] | 0.000 | 0.001 | 0.416 |
20 | 0.171 | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_67_s0/Q | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s/DI[31] | sysclk:[R] | sysclk:[R] | 0.000 | 0.022 | 0.397 |
21 | 0.173 | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_152_s0/Q | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_4_s/DI[8] | sysclk:[R] | sysclk:[R] | 0.000 | 0.006 | 0.416 |
22 | 0.173 | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_150_s0/Q | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_4_s/DI[6] | sysclk:[R] | sysclk:[R] | 0.000 | 0.006 | 0.416 |
23 | 0.173 | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_149_s0/Q | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_4_s/DI[5] | sysclk:[R] | sysclk:[R] | 0.000 | 0.006 | 0.416 |
24 | 0.173 | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_92_s0/Q | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_2_s/DI[20] | sysclk:[R] | sysclk:[R] | 0.000 | 0.006 | 0.416 |
25 | 0.175 | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_75_s0/Q | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_2_s/DI[3] | sysclk:[R] | sysclk:[R] | 0.000 | 0.007 | 0.416 |
Recovery Paths Table
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 5.589 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rbin_0_s0/CLEAR | sysclk:[R] | sysclk:[R] | 10.000 | -0.020 | 4.083 |
2 | 5.589 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rbin_1_s0/CLEAR | sysclk:[R] | sysclk:[R] | 10.000 | -0.020 | 4.083 |
3 | 5.589 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rbin_2_s0/CLEAR | sysclk:[R] | sysclk:[R] | 10.000 | -0.020 | 4.083 |
4 | 5.589 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rbin_3_s0/CLEAR | sysclk:[R] | sysclk:[R] | 10.000 | -0.020 | 4.083 |
5 | 5.590 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_1_s0/CLEAR | sysclk:[R] | sysclk:[R] | 10.000 | -0.029 | 4.092 |
6 | 5.590 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_2_s0/CLEAR | sysclk:[R] | sysclk:[R] | 10.000 | -0.029 | 4.092 |
7 | 5.590 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wptr_0_s0/CLEAR | sysclk:[R] | sysclk:[R] | 10.000 | -0.029 | 4.092 |
8 | 5.590 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wptr_1_s0/CLEAR | sysclk:[R] | sysclk:[R] | 10.000 | -0.029 | 4.092 |
9 | 5.590 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_1_s0/CLEAR | sysclk:[R] | sysclk:[R] | 10.000 | -0.029 | 4.092 |
10 | 5.639 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_Empty_reg_s0/PRESET | sysclk:[R] | sysclk:[R] | 10.000 | -0.034 | 4.047 |
11 | 5.648 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq1_wptr_3_s0/CLEAR | sysclk:[R] | sysclk:[R] | 10.000 | -0.034 | 4.039 |
12 | 5.648 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rbin_2_s0/CLEAR | sysclk:[R] | sysclk:[R] | 10.000 | -0.034 | 4.039 |
13 | 5.648 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq2_wptr_3_s0/CLEAR | sysclk:[R] | sysclk:[R] | 10.000 | -0.034 | 4.039 |
14 | 5.648 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_3_s0/CLEAR | sysclk:[R] | sysclk:[R] | 10.000 | -0.034 | 4.039 |
15 | 5.648 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_3_s0/CLEAR | sysclk:[R] | sysclk:[R] | 10.000 | -0.034 | 4.039 |
16 | 5.653 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rbin_0_s0/CLEAR | sysclk:[R] | sysclk:[R] | 10.000 | -0.044 | 4.043 |
17 | 5.653 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rbin_1_s0/CLEAR | sysclk:[R] | sysclk:[R] | 10.000 | -0.044 | 4.043 |
18 | 5.653 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rbin_3_s0/CLEAR | sysclk:[R] | sysclk:[R] | 10.000 | -0.044 | 4.043 |
19 | 5.802 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_Empty_reg_s0/PRESET | sysclk:[R] | sysclk:[R] | 10.000 | -0.023 | 3.873 |
20 | 5.811 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_0_s0/CLEAR | sysclk:[R] | sysclk:[R] | 10.000 | -0.032 | 3.873 |
21 | 5.811 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_1_s0/CLEAR | sysclk:[R] | sysclk:[R] | 10.000 | -0.032 | 3.873 |
22 | 5.811 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_0_s0/CLEAR | sysclk:[R] | sysclk:[R] | 10.000 | -0.032 | 3.873 |
23 | 5.833 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_Empty_reg_s0/PRESET | sysclk:[R] | sysclk:[R] | 10.000 | 0.009 | 3.811 |
24 | 5.833 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rq2_wptr_0_s0/CLEAR | sysclk:[R] | sysclk:[R] | 10.000 | 0.009 | 3.811 |
25 | 5.833 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rq1_wptr_0_s0/CLEAR | sysclk:[R] | sysclk:[R] | 10.000 | 0.009 | 3.811 |
Removal Paths Table
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 1.499 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_0_s0/CLEAR | sysclk:[R] | sysclk:[R] | 0.000 | -0.027 | 1.337 |
2 | 1.499 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_0_s0/CLEAR | sysclk:[R] | sysclk:[R] | 0.000 | -0.027 | 1.337 |
3 | 1.499 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_1_s0/CLEAR | sysclk:[R] | sysclk:[R] | 0.000 | -0.027 | 1.337 |
4 | 1.499 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_2_s0/CLEAR | sysclk:[R] | sysclk:[R] | 0.000 | -0.027 | 1.337 |
5 | 1.499 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_3_s0/CLEAR | sysclk:[R] | sysclk:[R] | 0.000 | -0.027 | 1.337 |
6 | 2.226 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rq2_wptr_2_s0/CLEAR | sysclk:[R] | sysclk:[R] | 0.000 | -0.025 | 2.063 |
7 | 2.226 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rq1_wptr_2_s0/CLEAR | sysclk:[R] | sysclk:[R] | 0.000 | -0.025 | 2.063 |
8 | 2.226 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_wbin_2_s0/CLEAR | sysclk:[R] | sysclk:[R] | 0.000 | -0.025 | 2.063 |
9 | 2.226 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq2_wptr_2_s0/CLEAR | sysclk:[R] | sysclk:[R] | 0.000 | -0.025 | 2.063 |
10 | 2.226 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq1_wptr_2_s0/CLEAR | sysclk:[R] | sysclk:[R] | 0.000 | -0.025 | 2.063 |
11 | 2.226 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_0_s0/CLEAR | sysclk:[R] | sysclk:[R] | 0.000 | -0.030 | 2.068 |
12 | 2.226 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_1_s0/CLEAR | sysclk:[R] | sysclk:[R] | 0.000 | -0.030 | 2.068 |
13 | 2.226 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_2_s0/CLEAR | sysclk:[R] | sysclk:[R] | 0.000 | -0.030 | 2.068 |
14 | 2.226 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_3_s0/CLEAR | sysclk:[R] | sysclk:[R] | 0.000 | -0.030 | 2.068 |
15 | 2.226 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_2_s0/CLEAR | sysclk:[R] | sysclk:[R] | 0.000 | -0.025 | 2.063 |
16 | 2.226 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_2_s0/CLEAR | sysclk:[R] | sysclk:[R] | 0.000 | -0.025 | 2.063 |
17 | 2.230 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rq1_wptr_3_s0/CLEAR | sysclk:[R] | sysclk:[R] | 0.000 | 0.000 | 2.041 |
18 | 2.230 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_wptr_1_s0/CLEAR | sysclk:[R] | sysclk:[R] | 0.000 | 0.000 | 2.041 |
19 | 2.230 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_wptr_1_s0/CLEAR | sysclk:[R] | sysclk:[R] | 0.000 | 0.000 | 2.041 |
20 | 2.230 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_1_s0/CLEAR | sysclk:[R] | sysclk:[R] | 0.000 | 0.000 | 2.041 |
21 | 2.230 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_wbin_0_s0/CLEAR | sysclk:[R] | sysclk:[R] | 0.000 | -0.005 | 2.046 |
22 | 2.230 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq2_wptr_1_s0/CLEAR | sysclk:[R] | sysclk:[R] | 0.000 | -0.005 | 2.046 |
23 | 2.230 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq1_wptr_1_s0/CLEAR | sysclk:[R] | sysclk:[R] | 0.000 | -0.005 | 2.046 |
24 | 2.230 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_0_s0/CLEAR | sysclk:[R] | sysclk:[R] | 0.000 | -0.005 | 2.046 |
25 | 2.230 | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_0_s0/CLEAR | sysclk:[R] | sysclk:[R] | 0.000 | -0.005 | 2.046 |
Minimum Pulse Width Table:
Number | Slack | Actual Width | Required Width | Type | Clock | Objects |
---|---|---|---|---|---|---|
1 | 2.565 | 2.815 | 0.250 | Low Pulse Width | clk100 | u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/recalib_s_0_s0 |
2 | 2.565 | 2.815 | 0.250 | Low Pulse Width | clk100 | u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/cs_memsync_4_s0 |
3 | 2.565 | 2.815 | 0.250 | Low Pulse Width | clk100 | u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/cs_memsync_3_s0 |
4 | 2.565 | 2.815 | 0.250 | Low Pulse Width | clk100 | u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/flag_0_s4 |
5 | 2.566 | 2.816 | 0.250 | Low Pulse Width | clk100 | u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_11_s1 |
6 | 2.566 | 2.816 | 0.250 | Low Pulse Width | clk100 | u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_2_s1 |
7 | 2.566 | 2.816 | 0.250 | Low Pulse Width | clk100 | u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/flag_1_s2 |
8 | 2.567 | 2.817 | 0.250 | Low Pulse Width | clk100 | u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_syn_1_s0 |
9 | 2.567 | 2.817 | 0.250 | Low Pulse Width | clk100 | u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_3_s1 |
10 | 2.567 | 2.817 | 0.250 | High Pulse Width | clk100 | u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/cs_memsync_4_s0 |
Timing Report By Analysis Type:
Setup Analysis Report
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 0.013 |
Data Arrival Time | 12.825 |
Data Required Time | 12.837 |
From | u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_1_s0 |
To | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/idle3_s0 |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
2.894 | 2.894 | tNET | RR | 1 | R53C125[0][A] | u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_1_s0/CLK |
3.276 | 0.382 | tC2Q | RR | 68 | R53C125[0][A] | u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_1_s0/Q |
5.527 | 2.251 | tNET | RR | 1 | R49C118[2][A] | u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_168_G[0]_s2/S0 |
5.780 | 0.252 | tINS | RF | 1 | R49C118[2][A] | u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_168_G[0]_s2/O |
5.780 | 0.000 | tNET | FF | 1 | R49C118[2][B] | u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_168_G[0]_s0/I1 |
5.881 | 0.101 | tINS | FF | 5 | R49C118[2][B] | u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_168_G[0]_s0/O |
7.755 | 1.874 | tNET | FF | 1 | R58C103[2][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s27/I2 |
8.333 | 0.579 | tINS | FR | 1 | R58C103[2][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s27/F |
8.333 | 0.000 | tNET | RR | 1 | R58C103[2][A] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s23/I1 |
8.483 | 0.150 | tINS | RR | 1 | R58C103[2][A] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s23/O |
8.483 | 0.000 | tNET | RR | 1 | R58C103[2][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s21/I1 |
8.570 | 0.086 | tINS | RR | 4 | R58C103[2][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s21/O |
8.997 | 0.428 | tNET | RR | 1 | R58C106[0][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_W2R_s59/I2 |
9.576 | 0.579 | tINS | RR | 2 | R58C106[0][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_W2R_s59/F |
10.168 | 0.593 | tNET | RR | 1 | R63C106[1][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_READ_s74/I0 |
10.747 | 0.579 | tINS | RR | 1 | R63C106[1][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_READ_s74/F |
10.750 | 0.003 | tNET | RR | 1 | R63C106[2][A] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_READ_s70/I2 |
11.317 | 0.567 | tINS | RR | 1 | R63C106[2][A] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_READ_s70/F |
11.320 | 0.003 | tNET | RR | 1 | R63C106[1][A] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_READ_s68/I1 |
11.827 | 0.507 | tINS | RR | 2 | R63C106[1][A] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_READ_s68/F |
12.825 | 0.998 | tNET | RR | 1 | R62C100[0][A] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/idle3_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | sysclk | ||||
10.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
12.901 | 2.901 | tNET | RR | 1 | R62C100[0][A] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/idle3_s0/CLK |
12.837 | -0.064 | tSu | 1 | R62C100[0][A] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/idle3_s0 |
Path Statistics:
Clock Skew | 0.007 |
Setup Relationship | 10.000 |
Logic Level | 8 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.894, 100.000% |
Arrival Data Path Delay | cell: 3.401, 34.249%; route: 6.147, 61.899%; tC2Q: 0.382, 3.852% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.901, 100.000% |
Path2
Path Summary:
Slack | 0.022 |
Data Arrival Time | 12.825 |
Data Required Time | 12.847 |
From | u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_1_s0 |
To | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_READ_s6 |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
2.894 | 2.894 | tNET | RR | 1 | R53C125[0][A] | u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_1_s0/CLK |
3.276 | 0.382 | tC2Q | RR | 68 | R53C125[0][A] | u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_1_s0/Q |
5.527 | 2.251 | tNET | RR | 1 | R49C118[2][A] | u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_168_G[0]_s2/S0 |
5.780 | 0.252 | tINS | RF | 1 | R49C118[2][A] | u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_168_G[0]_s2/O |
5.780 | 0.000 | tNET | FF | 1 | R49C118[2][B] | u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_168_G[0]_s0/I1 |
5.881 | 0.101 | tINS | FF | 5 | R49C118[2][B] | u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_168_G[0]_s0/O |
7.755 | 1.874 | tNET | FF | 1 | R58C103[2][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s27/I2 |
8.333 | 0.579 | tINS | FR | 1 | R58C103[2][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s27/F |
8.333 | 0.000 | tNET | RR | 1 | R58C103[2][A] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s23/I1 |
8.483 | 0.150 | tINS | RR | 1 | R58C103[2][A] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s23/O |
8.483 | 0.000 | tNET | RR | 1 | R58C103[2][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s21/I1 |
8.570 | 0.086 | tINS | RR | 4 | R58C103[2][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s21/O |
8.997 | 0.428 | tNET | RR | 1 | R58C106[0][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_W2R_s59/I2 |
9.576 | 0.579 | tINS | RR | 2 | R58C106[0][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_W2R_s59/F |
10.168 | 0.593 | tNET | RR | 1 | R63C106[1][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_READ_s74/I0 |
10.747 | 0.579 | tINS | RR | 1 | R63C106[1][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_READ_s74/F |
10.750 | 0.003 | tNET | RR | 1 | R63C106[2][A] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_READ_s70/I2 |
11.317 | 0.567 | tINS | RR | 1 | R63C106[2][A] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_READ_s70/F |
11.320 | 0.003 | tNET | RR | 1 | R63C106[1][A] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_READ_s68/I1 |
11.827 | 0.507 | tINS | RR | 2 | R63C106[1][A] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_READ_s68/F |
12.825 | 0.998 | tNET | RR | 1 | R62C101[1][A] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_READ_s6/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | sysclk | ||||
10.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
12.910 | 2.910 | tNET | RR | 1 | R62C101[1][A] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_READ_s6/CLK |
12.847 | -0.064 | tSu | 1 | R62C101[1][A] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_READ_s6 |
Path Statistics:
Clock Skew | 0.017 |
Setup Relationship | 10.000 |
Logic Level | 8 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.894, 100.000% |
Arrival Data Path Delay | cell: 3.401, 34.249%; route: 6.147, 61.899%; tC2Q: 0.382, 3.852% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.910, 100.000% |
Path3
Path Summary:
Slack | 0.068 |
Data Arrival Time | 12.521 |
Data Required Time | 12.589 |
From | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts_rr_s0 |
To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[2].u_oser8_mem |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
2.908 | 2.908 | tNET | RR | 1 | R49C51[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts_rr_s0/CLK |
3.291 | 0.382 | tC2Q | RR | 1 | R49C51[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts_rr_s0/Q |
4.698 | 1.408 | tNET | RR | 1 | R49C23[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/n257_s2/I0 |
4.987 | 0.289 | tINS | RR | 36 | R49C23[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/n257_s2/F |
12.521 | 7.534 | tNET | RR | 1 | IOL98[A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[2].u_oser8_mem/TX0 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | sysclk | ||||
10.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
12.852 | 2.852 | tNET | RR | 1 | IOL98[A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[2].u_oser8_mem/PCLK |
12.589 | -0.263 | tSu | 1 | IOL98[A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[2].u_oser8_mem |
Path Statistics:
Clock Skew | -0.057 |
Setup Relationship | 10.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.908, 100.000% |
Arrival Data Path Delay | cell: 0.289, 3.004%; route: 8.941, 93.017%; tC2Q: 0.382, 3.979% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.852, 100.000% |
Path4
Path Summary:
Slack | 0.091 |
Data Arrival Time | 12.491 |
Data Required Time | 12.581 |
From | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts0_rr_s0 |
To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
2.908 | 2.908 | tNET | RR | 1 | R49C51[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts0_rr_s0/CLK |
3.291 | 0.382 | tC2Q | RR | 1 | R49C51[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts0_rr_s0/Q |
4.698 | 1.408 | tNET | RR | 1 | R49C23[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/n258_s2/I0 |
5.277 | 0.579 | tINS | RR | 108 | R49C23[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/n258_s2/F |
12.491 | 7.214 | tNET | RR | 1 | IOL98[B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/TX3 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | sysclk | ||||
10.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
12.844 | 2.844 | tNET | RR | 1 | IOL98[B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/PCLK |
12.581 | -0.263 | tSu | 1 | IOL98[B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem |
Path Statistics:
Clock Skew | -0.064 |
Setup Relationship | 10.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.908, 100.000% |
Arrival Data Path Delay | cell: 0.579, 6.040%; route: 8.621, 89.969%; tC2Q: 0.382, 3.992% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.844, 100.000% |
Path5
Path Summary:
Slack | 0.091 |
Data Arrival Time | 12.491 |
Data Required Time | 12.581 |
From | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts0_rr_s0 |
To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
2.908 | 2.908 | tNET | RR | 1 | R49C51[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts0_rr_s0/CLK |
3.291 | 0.382 | tC2Q | RR | 1 | R49C51[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts0_rr_s0/Q |
4.698 | 1.408 | tNET | RR | 1 | R49C23[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/n258_s2/I0 |
5.277 | 0.579 | tINS | RR | 108 | R49C23[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/n258_s2/F |
12.491 | 7.214 | tNET | RR | 1 | IOL98[B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/TX2 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | sysclk | ||||
10.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
12.844 | 2.844 | tNET | RR | 1 | IOL98[B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/PCLK |
12.581 | -0.263 | tSu | 1 | IOL98[B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem |
Path Statistics:
Clock Skew | -0.064 |
Setup Relationship | 10.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.908, 100.000% |
Arrival Data Path Delay | cell: 0.579, 6.040%; route: 8.621, 89.969%; tC2Q: 0.382, 3.992% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.844, 100.000% |
Path6
Path Summary:
Slack | 0.113 |
Data Arrival Time | 12.496 |
Data Required Time | 12.608 |
From | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts0_rr_s0 |
To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[4].u_oser8_mem |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
2.908 | 2.908 | tNET | RR | 1 | R49C51[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts0_rr_s0/CLK |
3.291 | 0.382 | tC2Q | RR | 1 | R49C51[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts0_rr_s0/Q |
4.698 | 1.408 | tNET | RR | 1 | R49C23[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/n258_s2/I0 |
5.277 | 0.579 | tINS | RR | 108 | R49C23[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/n258_s2/F |
12.496 | 7.219 | tNET | RR | 1 | IOL92[A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[4].u_oser8_mem/TX3 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | sysclk | ||||
10.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
12.871 | 2.871 | tNET | RR | 1 | IOL92[A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[4].u_oser8_mem/PCLK |
12.608 | -0.263 | tSu | 1 | IOL92[A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[4].u_oser8_mem |
Path Statistics:
Clock Skew | -0.037 |
Setup Relationship | 10.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.908, 100.000% |
Arrival Data Path Delay | cell: 0.579, 6.037%; route: 8.626, 89.974%; tC2Q: 0.382, 3.990% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.871, 100.000% |
Path7
Path Summary:
Slack | 0.113 |
Data Arrival Time | 12.496 |
Data Required Time | 12.608 |
From | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts0_rr_s0 |
To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[4].u_oser8_mem |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
2.908 | 2.908 | tNET | RR | 1 | R49C51[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts0_rr_s0/CLK |
3.291 | 0.382 | tC2Q | RR | 1 | R49C51[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts0_rr_s0/Q |
4.698 | 1.408 | tNET | RR | 1 | R49C23[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/n258_s2/I0 |
5.277 | 0.579 | tINS | RR | 108 | R49C23[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/n258_s2/F |
12.496 | 7.219 | tNET | RR | 1 | IOL92[A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[4].u_oser8_mem/TX2 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | sysclk | ||||
10.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
12.871 | 2.871 | tNET | RR | 1 | IOL92[A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[4].u_oser8_mem/PCLK |
12.608 | -0.263 | tSu | 1 | IOL92[A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[4].u_oser8_mem |
Path Statistics:
Clock Skew | -0.037 |
Setup Relationship | 10.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.908, 100.000% |
Arrival Data Path Delay | cell: 0.579, 6.037%; route: 8.626, 89.974%; tC2Q: 0.382, 3.990% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.871, 100.000% |
Path8
Path Summary:
Slack | 0.123 |
Data Arrival Time | 12.715 |
Data Required Time | 12.837 |
From | u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_1_s0 |
To | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/idle2_s0 |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
2.894 | 2.894 | tNET | RR | 1 | R53C125[0][A] | u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_1_s0/CLK |
3.276 | 0.382 | tC2Q | RR | 68 | R53C125[0][A] | u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_1_s0/Q |
5.527 | 2.251 | tNET | RR | 1 | R49C118[2][A] | u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_168_G[0]_s2/S0 |
5.780 | 0.252 | tINS | RF | 1 | R49C118[2][A] | u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_168_G[0]_s2/O |
5.780 | 0.000 | tNET | FF | 1 | R49C118[2][B] | u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_168_G[0]_s0/I1 |
5.881 | 0.101 | tINS | FF | 5 | R49C118[2][B] | u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_168_G[0]_s0/O |
7.755 | 1.874 | tNET | FF | 1 | R58C103[2][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s27/I2 |
8.333 | 0.579 | tINS | FR | 1 | R58C103[2][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s27/F |
8.333 | 0.000 | tNET | RR | 1 | R58C103[2][A] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s23/I1 |
8.483 | 0.150 | tINS | RR | 1 | R58C103[2][A] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s23/O |
8.483 | 0.000 | tNET | RR | 1 | R58C103[2][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s21/I1 |
8.570 | 0.086 | tINS | RR | 4 | R58C103[2][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s21/O |
8.997 | 0.428 | tNET | RR | 1 | R58C106[0][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_W2R_s59/I2 |
9.576 | 0.579 | tINS | RR | 2 | R58C106[0][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_W2R_s59/F |
10.356 | 0.780 | tNET | RR | 1 | R63C106[3][A] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s75/I1 |
10.675 | 0.319 | tINS | RF | 1 | R63C106[3][A] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s75/F |
10.680 | 0.005 | tNET | FF | 1 | R63C106[3][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s70/I1 |
11.136 | 0.456 | tINS | FR | 1 | R63C106[3][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s70/F |
11.138 | 0.003 | tNET | RR | 1 | R63C106[2][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s68/I1 |
11.717 | 0.579 | tINS | RR | 2 | R63C106[2][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s68/F |
12.715 | 0.998 | tNET | RR | 1 | R62C100[1][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/idle2_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | sysclk | ||||
10.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
12.901 | 2.901 | tNET | RR | 1 | R62C100[1][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/idle2_s0/CLK |
12.837 | -0.064 | tSu | 1 | R62C100[1][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/idle2_s0 |
Path Statistics:
Clock Skew | 0.007 |
Setup Relationship | 10.000 |
Logic Level | 8 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.894, 100.000% |
Arrival Data Path Delay | cell: 3.101, 31.578%; route: 6.337, 64.527%; tC2Q: 0.382, 3.895% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.901, 100.000% |
Path9
Path Summary:
Slack | 0.242 |
Data Arrival Time | 12.339 |
Data Required Time | 12.581 |
From | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts0_rr_s0 |
To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
2.908 | 2.908 | tNET | RR | 1 | R49C51[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts0_rr_s0/CLK |
3.291 | 0.382 | tC2Q | RR | 1 | R49C51[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts0_rr_s0/Q |
4.698 | 1.408 | tNET | RR | 1 | R49C23[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/n258_s2/I0 |
5.277 | 0.579 | tINS | RR | 108 | R49C23[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/n258_s2/F |
12.339 | 7.063 | tNET | RR | 1 | IOL98[B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/TX1 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | sysclk | ||||
10.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
12.844 | 2.844 | tNET | RR | 1 | IOL98[B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/PCLK |
12.581 | -0.263 | tSu | 1 | IOL98[B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem |
Path Statistics:
Clock Skew | -0.064 |
Setup Relationship | 10.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.908, 100.000% |
Arrival Data Path Delay | cell: 0.579, 6.137%; route: 8.470, 89.808%; tC2Q: 0.382, 4.056% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.844, 100.000% |
Path10
Path Summary:
Slack | 0.249 |
Data Arrival Time | 12.339 |
Data Required Time | 12.589 |
From | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts0_rr_s0 |
To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[2].u_oser8_mem |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
2.908 | 2.908 | tNET | RR | 1 | R49C51[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts0_rr_s0/CLK |
3.291 | 0.382 | tC2Q | RR | 1 | R49C51[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts0_rr_s0/Q |
4.698 | 1.408 | tNET | RR | 1 | R49C23[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/n258_s2/I0 |
5.277 | 0.579 | tINS | RR | 108 | R49C23[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/n258_s2/F |
12.339 | 7.063 | tNET | RR | 1 | IOL98[A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[2].u_oser8_mem/TX1 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | sysclk | ||||
10.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
12.852 | 2.852 | tNET | RR | 1 | IOL98[A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[2].u_oser8_mem/PCLK |
12.589 | -0.263 | tSu | 1 | IOL98[A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[2].u_oser8_mem |
Path Statistics:
Clock Skew | -0.057 |
Setup Relationship | 10.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.908, 100.000% |
Arrival Data Path Delay | cell: 0.579, 6.137%; route: 8.470, 89.808%; tC2Q: 0.382, 4.056% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.852, 100.000% |
Path11
Path Summary:
Slack | 0.264 |
Data Arrival Time | 12.344 |
Data Required Time | 12.608 |
From | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts0_rr_s0 |
To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[4].u_oser8_mem |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
2.908 | 2.908 | tNET | RR | 1 | R49C51[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts0_rr_s0/CLK |
3.291 | 0.382 | tC2Q | RR | 1 | R49C51[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts0_rr_s0/Q |
4.698 | 1.408 | tNET | RR | 1 | R49C23[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/n258_s2/I0 |
5.277 | 0.579 | tINS | RR | 108 | R49C23[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/n258_s2/F |
12.344 | 7.068 | tNET | RR | 1 | IOL92[A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[4].u_oser8_mem/TX1 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | sysclk | ||||
10.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
12.871 | 2.871 | tNET | RR | 1 | IOL92[A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[4].u_oser8_mem/PCLK |
12.608 | -0.263 | tSu | 1 | IOL92[A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[4].u_oser8_mem |
Path Statistics:
Clock Skew | -0.037 |
Setup Relationship | 10.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.908, 100.000% |
Arrival Data Path Delay | cell: 0.579, 6.133%; route: 8.475, 89.813%; tC2Q: 0.382, 4.054% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.871, 100.000% |
Path12
Path Summary:
Slack | 0.273 |
Data Arrival Time | 12.336 |
Data Required Time | 12.608 |
From | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts_rr_s0 |
To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[4].u_oser8_mem |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
2.908 | 2.908 | tNET | RR | 1 | R49C51[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts_rr_s0/CLK |
3.291 | 0.382 | tC2Q | RR | 1 | R49C51[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts_rr_s0/Q |
4.698 | 1.408 | tNET | RR | 1 | R49C23[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/n257_s2/I0 |
4.987 | 0.289 | tINS | RR | 36 | R49C23[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/n257_s2/F |
12.336 | 7.349 | tNET | RR | 1 | IOL92[A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[4].u_oser8_mem/TX0 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | sysclk | ||||
10.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
12.871 | 2.871 | tNET | RR | 1 | IOL92[A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[4].u_oser8_mem/PCLK |
12.608 | -0.263 | tSu | 1 | IOL92[A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[4].u_oser8_mem |
Path Statistics:
Clock Skew | -0.037 |
Setup Relationship | 10.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.908, 100.000% |
Arrival Data Path Delay | cell: 0.289, 3.063%; route: 8.756, 92.880%; tC2Q: 0.382, 4.057% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.871, 100.000% |
Path13
Path Summary:
Slack | 0.290 |
Data Arrival Time | 12.298 |
Data Required Time | 12.589 |
From | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts0_rr_s0 |
To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[2].u_oser8_mem |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
2.908 | 2.908 | tNET | RR | 1 | R49C51[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts0_rr_s0/CLK |
3.291 | 0.382 | tC2Q | RR | 1 | R49C51[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts0_rr_s0/Q |
4.698 | 1.408 | tNET | RR | 1 | R49C23[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/n258_s2/I0 |
5.277 | 0.579 | tINS | RR | 108 | R49C23[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/n258_s2/F |
12.298 | 7.021 | tNET | RR | 1 | IOL98[A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[2].u_oser8_mem/TX3 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | sysclk | ||||
10.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
12.852 | 2.852 | tNET | RR | 1 | IOL98[A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[2].u_oser8_mem/PCLK |
12.589 | -0.263 | tSu | 1 | IOL98[A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[2].u_oser8_mem |
Path Statistics:
Clock Skew | -0.057 |
Setup Relationship | 10.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.908, 100.000% |
Arrival Data Path Delay | cell: 0.579, 6.163%; route: 8.429, 89.763%; tC2Q: 0.382, 4.073% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.852, 100.000% |
Path14
Path Summary:
Slack | 0.290 |
Data Arrival Time | 12.298 |
Data Required Time | 12.589 |
From | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts0_rr_s0 |
To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[2].u_oser8_mem |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
2.908 | 2.908 | tNET | RR | 1 | R49C51[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts0_rr_s0/CLK |
3.291 | 0.382 | tC2Q | RR | 1 | R49C51[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts0_rr_s0/Q |
4.698 | 1.408 | tNET | RR | 1 | R49C23[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/n258_s2/I0 |
5.277 | 0.579 | tINS | RR | 108 | R49C23[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/n258_s2/F |
12.298 | 7.021 | tNET | RR | 1 | IOL98[A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[2].u_oser8_mem/TX2 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | sysclk | ||||
10.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
12.852 | 2.852 | tNET | RR | 1 | IOL98[A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[2].u_oser8_mem/PCLK |
12.589 | -0.263 | tSu | 1 | IOL98[A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[2].u_oser8_mem |
Path Statistics:
Clock Skew | -0.057 |
Setup Relationship | 10.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.908, 100.000% |
Arrival Data Path Delay | cell: 0.579, 6.163%; route: 8.429, 89.763%; tC2Q: 0.382, 4.073% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.852, 100.000% |
Path15
Path Summary:
Slack | 0.478 |
Data Arrival Time | 12.338 |
Data Required Time | 12.816 |
From | u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_0_s1 |
To | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_ACT2WR_s10 |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
2.873 | 2.873 | tNET | RR | 1 | R52C119[0][A] | u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_0_s1/CLK |
3.241 | 0.368 | tC2Q | RF | 38 | R52C119[0][A] | u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_0_s1/Q |
4.921 | 1.680 | tNET | FF | 1 | R48C123[2][B] | u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s0/S0 |
5.173 | 0.252 | tINS | FR | 5 | R48C123[2][B] | u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s0/O |
7.407 | 2.234 | tNET | RR | 1 | R62C106[3][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_REF_s66/I0 |
7.954 | 0.548 | tINS | RR | 3 | R62C106[3][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_REF_s66/F |
8.588 | 0.634 | tNET | RR | 1 | R63C103[2][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_REF_s64/I1 |
9.096 | 0.507 | tINS | RR | 2 | R63C103[2][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_REF_s64/F |
9.101 | 0.005 | tNET | RR | 1 | R63C103[0][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_IDLE_s71/I3 |
9.679 | 0.579 | tINS | RR | 7 | R63C103[0][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_IDLE_s71/F |
10.093 | 0.414 | tNET | RR | 1 | R63C100[3][A] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_W2R_s57/I1 |
10.667 | 0.574 | tINS | RR | 4 | R63C100[3][A] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_W2R_s57/F |
11.831 | 1.164 | tNET | RR | 1 | R65C102[2][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_ACT2WR_s55/I0 |
12.338 | 0.507 | tINS | RR | 1 | R65C102[2][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_ACT2WR_s55/F |
12.338 | 0.000 | tNET | RR | 1 | R65C102[2][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_ACT2WR_s10/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | sysclk | ||||
10.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
12.879 | 2.879 | tNET | RR | 1 | R65C102[2][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_ACT2WR_s10/CLK |
12.816 | -0.064 | tSu | 1 | R65C102[2][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_ACT2WR_s10 |
Path Statistics:
Clock Skew | 0.006 |
Setup Relationship | 10.000 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.873, 100.000% |
Arrival Data Path Delay | cell: 2.967, 31.352%; route: 6.130, 64.765%; tC2Q: 0.368, 3.883% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.879, 100.000% |
Path16
Path Summary:
Slack | 0.621 |
Data Arrival Time | 11.953 |
Data Required Time | 12.574 |
From | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts0_rr_s0 |
To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
2.908 | 2.908 | tNET | RR | 1 | R49C51[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts0_rr_s0/CLK |
3.291 | 0.382 | tC2Q | RR | 1 | R49C51[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts0_rr_s0/Q |
4.698 | 1.408 | tNET | RR | 1 | R49C23[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/n258_s2/I0 |
5.277 | 0.579 | tINS | RR | 108 | R49C23[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/n258_s2/F |
11.953 | 6.676 | tNET | RR | 1 | IOL89[B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/TX3 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | sysclk | ||||
10.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
12.837 | 2.837 | tNET | RR | 1 | IOL89[B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/PCLK |
12.574 | -0.263 | tSu | 1 | IOL89[B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem |
Path Statistics:
Clock Skew | -0.071 |
Setup Relationship | 10.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.908, 100.000% |
Arrival Data Path Delay | cell: 0.579, 6.399%; route: 8.084, 89.373%; tC2Q: 0.382, 4.229% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.837, 100.000% |
Path17
Path Summary:
Slack | 0.621 |
Data Arrival Time | 11.953 |
Data Required Time | 12.574 |
From | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts0_rr_s0 |
To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
2.908 | 2.908 | tNET | RR | 1 | R49C51[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts0_rr_s0/CLK |
3.291 | 0.382 | tC2Q | RR | 1 | R49C51[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts0_rr_s0/Q |
4.698 | 1.408 | tNET | RR | 1 | R49C23[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/n258_s2/I0 |
5.277 | 0.579 | tINS | RR | 108 | R49C23[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/n258_s2/F |
11.953 | 6.676 | tNET | RR | 1 | IOL89[B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/TX2 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | sysclk | ||||
10.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
12.837 | 2.837 | tNET | RR | 1 | IOL89[B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/PCLK |
12.574 | -0.263 | tSu | 1 | IOL89[B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem |
Path Statistics:
Clock Skew | -0.071 |
Setup Relationship | 10.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.908, 100.000% |
Arrival Data Path Delay | cell: 0.579, 6.399%; route: 8.084, 89.373%; tC2Q: 0.382, 4.229% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.837, 100.000% |
Path18
Path Summary:
Slack | 0.629 |
Data Arrival Time | 11.944 |
Data Required Time | 12.574 |
From | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts_rr_s0 |
To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
2.908 | 2.908 | tNET | RR | 1 | R49C51[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts_rr_s0/CLK |
3.291 | 0.382 | tC2Q | RR | 1 | R49C51[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts_rr_s0/Q |
4.698 | 1.408 | tNET | RR | 1 | R49C23[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/n257_s2/I0 |
4.987 | 0.289 | tINS | RR | 36 | R49C23[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/n257_s2/F |
11.944 | 6.958 | tNET | RR | 1 | IOL89[B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/TX0 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | sysclk | ||||
10.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
12.837 | 2.837 | tNET | RR | 1 | IOL89[B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/PCLK |
12.574 | -0.263 | tSu | 1 | IOL89[B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem |
Path Statistics:
Clock Skew | -0.071 |
Setup Relationship | 10.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.908, 100.000% |
Arrival Data Path Delay | cell: 0.289, 3.195%; route: 8.365, 92.572%; tC2Q: 0.382, 4.233% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.837, 100.000% |
Path19
Path Summary:
Slack | 0.670 |
Data Arrival Time | 12.160 |
Data Required Time | 12.830 |
From | u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_1_s0 |
To | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_WRITE_s4 |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
2.894 | 2.894 | tNET | RR | 1 | R53C125[0][A] | u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_1_s0/CLK |
3.276 | 0.382 | tC2Q | RR | 68 | R53C125[0][A] | u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_1_s0/Q |
5.527 | 2.251 | tNET | RR | 1 | R49C118[2][A] | u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_168_G[0]_s2/S0 |
5.780 | 0.252 | tINS | RF | 1 | R49C118[2][A] | u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_168_G[0]_s2/O |
5.780 | 0.000 | tNET | FF | 1 | R49C118[2][B] | u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_168_G[0]_s0/I1 |
5.881 | 0.101 | tINS | FF | 5 | R49C118[2][B] | u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_168_G[0]_s0/O |
7.755 | 1.874 | tNET | FF | 1 | R58C103[2][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s27/I2 |
8.333 | 0.579 | tINS | FR | 1 | R58C103[2][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s27/F |
8.333 | 0.000 | tNET | RR | 1 | R58C103[2][A] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s23/I1 |
8.483 | 0.150 | tINS | RR | 1 | R58C103[2][A] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s23/O |
8.483 | 0.000 | tNET | RR | 1 | R58C103[2][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s21/I1 |
8.570 | 0.086 | tINS | RR | 4 | R58C103[2][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s21/O |
8.997 | 0.428 | tNET | RR | 1 | R58C106[0][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_W2R_s59/I2 |
9.576 | 0.579 | tINS | RR | 2 | R58C106[0][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_W2R_s59/F |
10.356 | 0.780 | tNET | RR | 1 | R63C106[3][A] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s75/I1 |
10.675 | 0.319 | tINS | RF | 1 | R63C106[3][A] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s75/F |
10.680 | 0.005 | tNET | FF | 1 | R63C106[3][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s70/I1 |
11.136 | 0.456 | tINS | FR | 1 | R63C106[3][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s70/F |
11.138 | 0.003 | tNET | RR | 1 | R63C106[2][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s68/I1 |
11.717 | 0.579 | tINS | RR | 2 | R63C106[2][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_WRITE_s68/F |
12.160 | 0.442 | tNET | RR | 1 | R63C106[0][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_WRITE_s4/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | sysclk | ||||
10.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
12.894 | 2.894 | tNET | RR | 1 | R63C106[0][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_WRITE_s4/CLK |
12.830 | -0.064 | tSu | 1 | R63C106[0][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_WRITE_s4 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 8 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.894, 100.000% |
Arrival Data Path Delay | cell: 3.101, 33.469%; route: 5.782, 62.403%; tC2Q: 0.382, 4.128% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.894, 100.000% |
Path20
Path Summary:
Slack | 0.772 |
Data Arrival Time | 11.802 |
Data Required Time | 12.574 |
From | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts0_rr_s0 |
To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
2.908 | 2.908 | tNET | RR | 1 | R49C51[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts0_rr_s0/CLK |
3.291 | 0.382 | tC2Q | RR | 1 | R49C51[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts0_rr_s0/Q |
4.698 | 1.408 | tNET | RR | 1 | R49C23[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/n258_s2/I0 |
5.277 | 0.579 | tINS | RR | 108 | R49C23[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/n258_s2/F |
11.802 | 6.525 | tNET | RR | 1 | IOL89[B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/TX1 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | sysclk | ||||
10.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
12.837 | 2.837 | tNET | RR | 1 | IOL89[B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/PCLK |
12.574 | -0.263 | tSu | 1 | IOL89[B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem |
Path Statistics:
Clock Skew | -0.071 |
Setup Relationship | 10.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.908, 100.000% |
Arrival Data Path Delay | cell: 0.579, 6.507%; route: 7.933, 89.192%; tC2Q: 0.382, 4.301% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.837, 100.000% |
Path21
Path Summary:
Slack | 0.820 |
Data Arrival Time | 12.024 |
Data Required Time | 12.844 |
From | u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_0_s1 |
To | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_IDLE_s2 |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
2.873 | 2.873 | tNET | RR | 1 | R52C119[0][A] | u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_0_s1/CLK |
3.241 | 0.368 | tC2Q | RF | 38 | R52C119[0][A] | u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_0_s1/Q |
4.921 | 1.680 | tNET | FF | 1 | R48C123[2][B] | u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s0/S0 |
5.173 | 0.252 | tINS | FR | 5 | R48C123[2][B] | u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s0/O |
7.407 | 2.234 | tNET | RR | 1 | R62C106[3][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_REF_s66/I0 |
7.954 | 0.548 | tINS | RR | 3 | R62C106[3][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_REF_s66/F |
8.588 | 0.634 | tNET | RR | 1 | R63C103[2][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_REF_s64/I1 |
9.096 | 0.507 | tINS | RR | 2 | R63C103[2][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_REF_s64/F |
9.101 | 0.005 | tNET | RR | 1 | R63C103[0][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_IDLE_s71/I3 |
9.679 | 0.579 | tINS | RR | 7 | R63C103[0][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_IDLE_s71/F |
10.302 | 0.623 | tNET | RR | 1 | R63C98[2][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_IDLE_s69/I1 |
10.809 | 0.507 | tINS | RR | 1 | R63C98[2][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_IDLE_s69/F |
10.982 | 0.172 | tNET | RR | 1 | R62C98[2][A] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_IDLE_s68/I1 |
11.561 | 0.579 | tINS | RR | 2 | R62C98[2][A] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_IDLE_s68/F |
12.024 | 0.464 | tNET | RR | 1 | R61C98[2][A] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_IDLE_s2/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | sysclk | ||||
10.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
12.908 | 2.908 | tNET | RR | 1 | R61C98[2][A] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_IDLE_s2/CLK |
12.844 | -0.064 | tSu | 1 | R61C98[2][A] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_IDLE_s2 |
Path Statistics:
Clock Skew | 0.035 |
Setup Relationship | 10.000 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.873, 100.000% |
Arrival Data Path Delay | cell: 2.972, 32.482%; route: 5.811, 63.502%; tC2Q: 0.368, 4.016% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.908, 100.000% |
Path22
Path Summary:
Slack | 0.834 |
Data Arrival Time | 12.003 |
Data Required Time | 12.837 |
From | u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_0_s1 |
To | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/idle1_s0 |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
2.873 | 2.873 | tNET | RR | 1 | R52C119[0][A] | u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_0_s1/CLK |
3.241 | 0.368 | tC2Q | RF | 38 | R52C119[0][A] | u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_0_s1/Q |
4.921 | 1.680 | tNET | FF | 1 | R48C123[2][B] | u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s0/S0 |
5.173 | 0.252 | tINS | FR | 5 | R48C123[2][B] | u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s0/O |
7.407 | 2.234 | tNET | RR | 1 | R62C106[3][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_REF_s66/I0 |
7.954 | 0.548 | tINS | RR | 3 | R62C106[3][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_REF_s66/F |
8.588 | 0.634 | tNET | RR | 1 | R63C103[2][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_REF_s64/I1 |
9.096 | 0.507 | tINS | RR | 2 | R63C103[2][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_REF_s64/F |
9.101 | 0.005 | tNET | RR | 1 | R63C103[0][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_IDLE_s71/I3 |
9.679 | 0.579 | tINS | RR | 7 | R63C103[0][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_IDLE_s71/F |
10.302 | 0.623 | tNET | RR | 1 | R63C98[2][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_IDLE_s69/I1 |
10.809 | 0.507 | tINS | RR | 1 | R63C98[2][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_IDLE_s69/F |
10.982 | 0.172 | tNET | RR | 1 | R62C98[2][A] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_IDLE_s68/I1 |
11.561 | 0.579 | tINS | RR | 2 | R62C98[2][A] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_IDLE_s68/F |
12.003 | 0.442 | tNET | RR | 1 | R62C98[1][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/idle1_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | sysclk | ||||
10.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
12.901 | 2.901 | tNET | RR | 1 | R62C98[1][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/idle1_s0/CLK |
12.837 | -0.064 | tSu | 1 | R62C98[1][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/idle1_s0 |
Path Statistics:
Clock Skew | 0.028 |
Setup Relationship | 10.000 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.873, 100.000% |
Arrival Data Path Delay | cell: 2.972, 32.557%; route: 5.790, 63.417%; tC2Q: 0.368, 4.025% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.901, 100.000% |
Path23
Path Summary:
Slack | 0.839 |
Data Arrival Time | 12.006 |
Data Required Time | 12.844 |
From | u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_0_s1 |
To | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_W2R_s8 |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
2.873 | 2.873 | tNET | RR | 1 | R52C119[0][A] | u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_0_s1/CLK |
3.241 | 0.368 | tC2Q | RF | 38 | R52C119[0][A] | u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_0_s1/Q |
4.921 | 1.680 | tNET | FF | 1 | R48C123[2][B] | u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s0/S0 |
5.173 | 0.252 | tINS | FR | 5 | R48C123[2][B] | u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_196_G[0]_s0/O |
7.407 | 2.234 | tNET | RR | 1 | R62C106[3][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_REF_s66/I0 |
7.954 | 0.548 | tINS | RR | 3 | R62C106[3][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_REF_s66/F |
8.588 | 0.634 | tNET | RR | 1 | R63C103[2][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_REF_s64/I1 |
9.096 | 0.507 | tINS | RR | 2 | R63C103[2][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_REF_s64/F |
9.101 | 0.005 | tNET | RR | 1 | R63C103[0][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_IDLE_s71/I3 |
9.679 | 0.579 | tINS | RR | 7 | R63C103[0][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_IDLE_s71/F |
10.093 | 0.414 | tNET | RR | 1 | R63C100[3][A] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_W2R_s57/I1 |
10.667 | 0.574 | tINS | RR | 4 | R63C100[3][A] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_W2R_s57/F |
11.438 | 0.771 | tNET | RR | 1 | R61C102[1][A] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_W2R_s54/I2 |
12.006 | 0.567 | tINS | RR | 1 | R61C102[1][A] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_W2R_s54/F |
12.006 | 0.000 | tNET | RR | 1 | R61C102[1][A] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_W2R_s8/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | sysclk | ||||
10.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
12.908 | 2.908 | tNET | RR | 1 | R61C102[1][A] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_W2R_s8/CLK |
12.844 | -0.064 | tSu | 1 | R61C102[1][A] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_W2R_s8 |
Path Statistics:
Clock Skew | 0.035 |
Setup Relationship | 10.000 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.873, 100.000% |
Arrival Data Path Delay | cell: 3.028, 33.151%; route: 5.738, 62.825%; tC2Q: 0.368, 4.024% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.908, 100.000% |
Path24
Path Summary:
Slack | 0.883 |
Data Arrival Time | 11.932 |
Data Required Time | 12.816 |
From | u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_1_s0 |
To | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_ACT_WR_s4 |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
2.894 | 2.894 | tNET | RR | 1 | R53C125[0][A] | u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_1_s0/CLK |
3.276 | 0.382 | tC2Q | RR | 68 | R53C125[0][A] | u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/raddr_1_s0/Q |
5.527 | 2.251 | tNET | RR | 1 | R49C118[2][A] | u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_168_G[0]_s2/S0 |
5.780 | 0.252 | tINS | RF | 1 | R49C118[2][A] | u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_168_G[0]_s2/O |
5.780 | 0.000 | tNET | FF | 1 | R49C118[2][B] | u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_168_G[0]_s0/I1 |
5.881 | 0.101 | tINS | FF | 5 | R49C118[2][B] | u_ddr3/gw3_top/u_gwmc_top/gw_cmd0/mem_RAMOUT_168_G[0]_s0/O |
7.755 | 1.874 | tNET | FF | 1 | R58C103[2][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s27/I2 |
8.333 | 0.579 | tINS | FR | 1 | R58C103[2][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s27/F |
8.333 | 0.000 | tNET | RR | 1 | R58C103[2][A] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s23/I1 |
8.483 | 0.150 | tINS | RR | 1 | R58C103[2][A] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s23/O |
8.483 | 0.000 | tNET | RR | 1 | R58C103[2][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s21/I1 |
8.570 | 0.086 | tINS | RR | 4 | R58C103[2][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/n949_s21/O |
8.997 | 0.428 | tNET | RR | 1 | R58C106[1][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_ACT_WR_s67/I1 |
9.576 | 0.579 | tINS | RR | 2 | R58C106[1][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_ACT_WR_s67/F |
10.532 | 0.956 | tNET | RR | 1 | R63C102[1][A] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_ACT_WR_s66/I0 |
11.100 | 0.567 | tINS | RR | 1 | R63C102[1][A] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_ACT_WR_s66/F |
11.643 | 0.544 | tNET | RR | 1 | R65C102[1][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_ACT_WR_s65/I2 |
11.932 | 0.289 | tINS | RR | 1 | R65C102[1][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate.GWMCST_ACT_WR_s65/F |
11.932 | 0.000 | tNET | RR | 1 | R65C102[1][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_ACT_WR_s4/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | sysclk | ||||
10.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
12.879 | 2.879 | tNET | RR | 1 | R65C102[1][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_ACT_WR_s4/CLK |
12.816 | -0.064 | tSu | 1 | R65C102[1][B] | u_ddr3/gw3_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_pstate.GWMCST_ACT_WR_s4 |
Path Statistics:
Clock Skew | -0.014 |
Setup Relationship | 10.000 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.894, 100.000% |
Arrival Data Path Delay | cell: 2.604, 28.808%; route: 6.052, 66.961%; tC2Q: 0.382, 4.232% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.879, 100.000% |
Path25
Path Summary:
Slack | 0.977 |
Data Arrival Time | 11.593 |
Data Required Time | 12.570 |
From | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts0_rr_s0 |
To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
2.908 | 2.908 | tNET | RR | 1 | R49C51[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts0_rr_s0/CLK |
3.291 | 0.382 | tC2Q | RR | 1 | R49C51[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/dqts0_rr_s0/Q |
4.698 | 1.408 | tNET | RR | 1 | R49C23[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/n258_s2/I0 |
5.277 | 0.579 | tINS | RR | 108 | R49C23[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/n258_s2/F |
11.593 | 6.316 | tNET | RR | 1 | IOL87[B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/TX3 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | sysclk | ||||
10.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
12.833 | 2.833 | tNET | RR | 1 | IOL87[B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/PCLK |
12.570 | -0.263 | tSu | 1 | IOL87[B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem |
Path Statistics:
Clock Skew | -0.075 |
Setup Relationship | 10.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.908, 100.000% |
Arrival Data Path Delay | cell: 0.579, 6.664%; route: 7.724, 88.932%; tC2Q: 0.382, 4.404% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.833, 100.000% |
Hold Analysis Report
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 0.048 |
Data Arrival Time | 1.581 |
Data Required Time | 1.533 |
From | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_126_s0 |
To | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_3_s |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.285 | 1.285 | tNET | RR | 1 | R63C114[2][B] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_126_s0/CLK |
1.465 | 0.180 | tC2Q | RR | 1 | R63C114[2][B] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_126_s0/Q |
1.581 | 0.116 | tNET | RR | 1 | BSRAM_R64[23][B] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_3_s/DI[18] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.284 | 1.284 | tNET | RR | 1 | BSRAM_R64[23][B] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_3_s/CLKA |
1.533 | 0.249 | tHld | 1 | BSRAM_R64[23][B] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_3_s |
Path Statistics:
Clock Skew | -0.001 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.285, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.116, 39.241%; tC2Q: 0.180, 60.759% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.284, 100.000% |
Path2
Path Summary:
Slack | 0.053 |
Data Arrival Time | 1.581 |
Data Required Time | 1.528 |
From | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_172_s0 |
To | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_4_s |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.285 | 1.285 | tNET | RR | 1 | R63C118[2][B] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_172_s0/CLK |
1.465 | 0.180 | tC2Q | RR | 1 | R63C118[2][B] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_172_s0/Q |
1.581 | 0.116 | tNET | RR | 1 | BSRAM_R64[24] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_4_s/DI[28] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.279 | 1.279 | tNET | RR | 1 | BSRAM_R64[24] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_4_s/CLKA |
1.528 | 0.249 | tHld | 1 | BSRAM_R64[24] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_4_s |
Path Statistics:
Clock Skew | -0.006 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.285, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.116, 39.241%; tC2Q: 0.180, 60.759% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.279, 100.000% |
Path3
Path Summary:
Slack | 0.054 |
Data Arrival Time | 1.576 |
Data Required Time | 1.523 |
From | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_188_s0 |
To | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_5_s |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.280 | 1.280 | tNET | RR | 1 | R63C119[1][A] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_188_s0/CLK |
1.460 | 0.180 | tC2Q | RR | 1 | R63C119[1][A] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_188_s0/Q |
1.576 | 0.116 | tNET | RR | 1 | BSRAM_R64[25][A] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_5_s/DI[8] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.274 | 1.274 | tNET | RR | 1 | BSRAM_R64[25][A] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_5_s/CLKA |
1.523 | 0.249 | tHld | 1 | BSRAM_R64[25][A] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_5_s |
Path Statistics:
Clock Skew | -0.006 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.280, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.116, 39.241%; tC2Q: 0.180, 60.759% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.274, 100.000% |
Path4
Path Summary:
Slack | 0.054 |
Data Arrival Time | 1.586 |
Data Required Time | 1.533 |
From | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_117_s0 |
To | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_3_s |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.290 | 1.290 | tNET | RR | 1 | R63C113[0][A] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_117_s0/CLK |
1.470 | 0.180 | tC2Q | RR | 1 | R63C113[0][A] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_117_s0/Q |
1.586 | 0.116 | tNET | RR | 1 | BSRAM_R64[23][B] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_3_s/DI[9] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.284 | 1.284 | tNET | RR | 1 | BSRAM_R64[23][B] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_3_s/CLKA |
1.533 | 0.249 | tHld | 1 | BSRAM_R64[23][B] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_3_s |
Path Statistics:
Clock Skew | -0.006 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.290, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.116, 39.241%; tC2Q: 0.180, 60.759% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.284, 100.000% |
Path5
Path Summary:
Slack | 0.054 |
Data Arrival Time | 1.586 |
Data Required Time | 1.533 |
From | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_113_s0 |
To | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_3_s |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.290 | 1.290 | tNET | RR | 1 | R63C113[0][B] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_113_s0/CLK |
1.470 | 0.180 | tC2Q | RR | 1 | R63C113[0][B] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_113_s0/Q |
1.586 | 0.116 | tNET | RR | 1 | BSRAM_R64[23][B] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_3_s/DI[5] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.284 | 1.284 | tNET | RR | 1 | BSRAM_R64[23][B] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_3_s/CLKA |
1.533 | 0.249 | tHld | 1 | BSRAM_R64[23][B] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_3_s |
Path Statistics:
Clock Skew | -0.006 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.290, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.116, 39.241%; tC2Q: 0.180, 60.759% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.284, 100.000% |
Path6
Path Summary:
Slack | 0.067 |
Data Arrival Time | 1.590 |
Data Required Time | 1.523 |
From | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_36_s0 |
To | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.286 | 1.286 | tNET | RR | 1 | R62C107[1][A] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_36_s0/CLK |
1.466 | 0.180 | tC2Q | RR | 1 | R62C107[1][A] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_36_s0/Q |
1.590 | 0.124 | tNET | RR | 1 | BSRAM_R64[22] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s/DI[0] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.274 | 1.274 | tNET | RR | 1 | BSRAM_R64[22] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s/CLKA |
1.523 | 0.249 | tHld | 1 | BSRAM_R64[22] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s |
Path Statistics:
Clock Skew | -0.012 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.286, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.124, 40.741%; tC2Q: 0.180, 59.259% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.274, 100.000% |
Path7
Path Summary:
Slack | 0.067 |
Data Arrival Time | 1.595 |
Data Required Time | 1.528 |
From | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_28_s0 |
To | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.291 | 1.291 | tNET | RR | 1 | R62C106[1][B] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_28_s0/CLK |
1.471 | 0.180 | tC2Q | RR | 1 | R62C106[1][B] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_28_s0/Q |
1.595 | 0.124 | tNET | RR | 1 | BSRAM_R64[21][B] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s/DI[28] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.279 | 1.279 | tNET | RR | 1 | BSRAM_R64[21][B] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s/CLKA |
1.528 | 0.249 | tHld | 1 | BSRAM_R64[21][B] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s |
Path Statistics:
Clock Skew | -0.013 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.291, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.124, 40.741%; tC2Q: 0.180, 59.259% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.279, 100.000% |
Path8
Path Summary:
Slack | 0.077 |
Data Arrival Time | 1.600 |
Data Required Time | 1.523 |
From | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_62_s0 |
To | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.296 | 1.296 | tNET | RR | 1 | R62C109[0][B] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_62_s0/CLK |
1.476 | 0.180 | tC2Q | RR | 1 | R62C109[0][B] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_62_s0/Q |
1.600 | 0.124 | tNET | RR | 1 | BSRAM_R64[22] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s/DI[26] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.274 | 1.274 | tNET | RR | 1 | BSRAM_R64[22] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s/CLKA |
1.523 | 0.249 | tHld | 1 | BSRAM_R64[22] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s |
Path Statistics:
Clock Skew | -0.022 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.296, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.124, 40.741%; tC2Q: 0.180, 59.259% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.274, 100.000% |
Path9
Path Summary:
Slack | 0.161 |
Data Arrival Time | 1.684 |
Data Required Time | 1.523 |
From | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_37_s0 |
To | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.286 | 1.286 | tNET | RR | 1 | R62C107[0][B] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_37_s0/CLK |
1.466 | 0.180 | tC2Q | RR | 1 | R62C107[0][B] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_37_s0/Q |
1.684 | 0.217 | tNET | RR | 1 | BSRAM_R64[22] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s/DI[1] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.274 | 1.274 | tNET | RR | 1 | BSRAM_R64[22] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s/CLKA |
1.523 | 0.249 | tHld | 1 | BSRAM_R64[22] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s |
Path Statistics:
Clock Skew | -0.012 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.286, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.217, 54.717%; tC2Q: 0.180, 45.283% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.274, 100.000% |
Path10
Path Summary:
Slack | 0.161 |
Data Arrival Time | 1.689 |
Data Required Time | 1.528 |
From | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_33_s0 |
To | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.291 | 1.291 | tNET | RR | 1 | R62C106[0][B] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_33_s0/CLK |
1.471 | 0.180 | tC2Q | RR | 1 | R62C106[0][B] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_33_s0/Q |
1.689 | 0.217 | tNET | RR | 1 | BSRAM_R64[21][B] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s/DI[33] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.279 | 1.279 | tNET | RR | 1 | BSRAM_R64[21][B] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s/CLKA |
1.528 | 0.249 | tHld | 1 | BSRAM_R64[21][B] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s |
Path Statistics:
Clock Skew | -0.013 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.291, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.217, 54.717%; tC2Q: 0.180, 45.283% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.279, 100.000% |
Path11
Path Summary:
Slack | 0.161 |
Data Arrival Time | 1.689 |
Data Required Time | 1.528 |
From | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_32_s0 |
To | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.291 | 1.291 | tNET | RR | 1 | R62C106[1][A] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_32_s0/CLK |
1.471 | 0.180 | tC2Q | RR | 1 | R62C106[1][A] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_32_s0/Q |
1.689 | 0.217 | tNET | RR | 1 | BSRAM_R64[21][B] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s/DI[32] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.279 | 1.279 | tNET | RR | 1 | BSRAM_R64[21][B] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s/CLKA |
1.528 | 0.249 | tHld | 1 | BSRAM_R64[21][B] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s |
Path Statistics:
Clock Skew | -0.013 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.291, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.217, 54.717%; tC2Q: 0.180, 45.283% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.279, 100.000% |
Path12
Path Summary:
Slack | 0.161 |
Data Arrival Time | 1.689 |
Data Required Time | 1.528 |
From | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_26_s0 |
To | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.291 | 1.291 | tNET | RR | 1 | R62C106[2][A] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_26_s0/CLK |
1.471 | 0.180 | tC2Q | RR | 1 | R62C106[2][A] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_26_s0/Q |
1.689 | 0.217 | tNET | RR | 1 | BSRAM_R64[21][B] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s/DI[26] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.279 | 1.279 | tNET | RR | 1 | BSRAM_R64[21][B] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s/CLKA |
1.528 | 0.249 | tHld | 1 | BSRAM_R64[21][B] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s |
Path Statistics:
Clock Skew | -0.013 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.291, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.217, 54.717%; tC2Q: 0.180, 45.283% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.279, 100.000% |
Path13
Path Summary:
Slack | 0.164 |
Data Arrival Time | 1.696 |
Data Required Time | 1.533 |
From | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_119_s0 |
To | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_3_s |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.280 | 1.280 | tNET | RR | 1 | R63C115[2][A] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_119_s0/CLK |
1.460 | 0.180 | tC2Q | RR | 1 | R63C115[2][A] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_119_s0/Q |
1.696 | 0.236 | tNET | RR | 1 | BSRAM_R64[23][B] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_3_s/DI[11] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.284 | 1.284 | tNET | RR | 1 | BSRAM_R64[23][B] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_3_s/CLKA |
1.533 | 0.249 | tHld | 1 | BSRAM_R64[23][B] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_3_s |
Path Statistics:
Clock Skew | 0.004 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.280, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.236, 56.757%; tC2Q: 0.180, 43.243% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.284, 100.000% |
Path14
Path Summary:
Slack | 0.164 |
Data Arrival Time | 1.696 |
Data Required Time | 1.533 |
From | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_112_s0 |
To | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_3_s |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.280 | 1.280 | tNET | RR | 1 | R63C111[0][B] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_112_s0/CLK |
1.460 | 0.180 | tC2Q | RR | 1 | R63C111[0][B] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_112_s0/Q |
1.696 | 0.236 | tNET | RR | 1 | BSRAM_R64[23][B] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_3_s/DI[4] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.284 | 1.284 | tNET | RR | 1 | BSRAM_R64[23][B] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_3_s/CLKA |
1.533 | 0.249 | tHld | 1 | BSRAM_R64[23][B] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_3_s |
Path Statistics:
Clock Skew | 0.004 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.280, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.236, 56.757%; tC2Q: 0.180, 43.243% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.284, 100.000% |
Path15
Path Summary:
Slack | 0.166 |
Data Arrival Time | 1.689 |
Data Required Time | 1.523 |
From | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_59_s0 |
To | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.291 | 1.291 | tNET | RR | 1 | R62C108[1][B] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_59_s0/CLK |
1.471 | 0.180 | tC2Q | RR | 1 | R62C108[1][B] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_59_s0/Q |
1.689 | 0.217 | tNET | RR | 1 | BSRAM_R64[22] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s/DI[23] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.274 | 1.274 | tNET | RR | 1 | BSRAM_R64[22] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s/CLKA |
1.523 | 0.249 | tHld | 1 | BSRAM_R64[22] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s |
Path Statistics:
Clock Skew | -0.018 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.291, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.217, 54.717%; tC2Q: 0.180, 45.283% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.274, 100.000% |
Path16
Path Summary:
Slack | 0.166 |
Data Arrival Time | 1.689 |
Data Required Time | 1.523 |
From | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_55_s0 |
To | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.291 | 1.291 | tNET | RR | 1 | R62C108[2][B] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_55_s0/CLK |
1.471 | 0.180 | tC2Q | RR | 1 | R62C108[2][B] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_55_s0/Q |
1.689 | 0.217 | tNET | RR | 1 | BSRAM_R64[22] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s/DI[19] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.274 | 1.274 | tNET | RR | 1 | BSRAM_R64[22] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s/CLKA |
1.523 | 0.249 | tHld | 1 | BSRAM_R64[22] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s |
Path Statistics:
Clock Skew | -0.018 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.291, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.217, 54.717%; tC2Q: 0.180, 45.283% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.274, 100.000% |
Path17
Path Summary:
Slack | 0.166 |
Data Arrival Time | 1.689 |
Data Required Time | 1.523 |
From | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_49_s0 |
To | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.291 | 1.291 | tNET | RR | 1 | R62C108[3][A] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_49_s0/CLK |
1.471 | 0.180 | tC2Q | RR | 1 | R62C108[3][A] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_49_s0/Q |
1.689 | 0.217 | tNET | RR | 1 | BSRAM_R64[22] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s/DI[13] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.274 | 1.274 | tNET | RR | 1 | BSRAM_R64[22] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s/CLKA |
1.523 | 0.249 | tHld | 1 | BSRAM_R64[22] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s |
Path Statistics:
Clock Skew | -0.018 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.291, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.217, 54.717%; tC2Q: 0.180, 45.283% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.274, 100.000% |
Path18
Path Summary:
Slack | 0.169 |
Data Arrival Time | 1.696 |
Data Required Time | 1.528 |
From | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_154_s0 |
To | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_4_s |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.280 | 1.280 | tNET | RR | 1 | R63C115[1][A] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_154_s0/CLK |
1.460 | 0.180 | tC2Q | RR | 1 | R63C115[1][A] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_154_s0/Q |
1.696 | 0.236 | tNET | RR | 1 | BSRAM_R64[24] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_4_s/DI[10] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.279 | 1.279 | tNET | RR | 1 | BSRAM_R64[24] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_4_s/CLKA |
1.528 | 0.249 | tHld | 1 | BSRAM_R64[24] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_4_s |
Path Statistics:
Clock Skew | -0.001 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.280, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.236, 56.757%; tC2Q: 0.180, 43.243% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.279, 100.000% |
Path19
Path Summary:
Slack | 0.169 |
Data Arrival Time | 1.696 |
Data Required Time | 1.528 |
From | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_22_s0 |
To | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.280 | 1.280 | tNET | RR | 1 | R63C107[1][B] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_22_s0/CLK |
1.460 | 0.180 | tC2Q | RR | 1 | R63C107[1][B] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_22_s0/Q |
1.696 | 0.236 | tNET | RR | 1 | BSRAM_R64[21][B] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s/DI[22] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.279 | 1.279 | tNET | RR | 1 | BSRAM_R64[21][B] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s/CLKA |
1.528 | 0.249 | tHld | 1 | BSRAM_R64[21][B] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_0_s |
Path Statistics:
Clock Skew | -0.001 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.280, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.236, 56.757%; tC2Q: 0.180, 43.243% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.279, 100.000% |
Path20
Path Summary:
Slack | 0.171 |
Data Arrival Time | 1.694 |
Data Required Time | 1.523 |
From | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_67_s0 |
To | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.296 | 1.296 | tNET | RR | 1 | R62C109[0][A] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_67_s0/CLK |
1.476 | 0.180 | tC2Q | RR | 1 | R62C109[0][A] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_67_s0/Q |
1.694 | 0.217 | tNET | RR | 1 | BSRAM_R64[22] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s/DI[31] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.274 | 1.274 | tNET | RR | 1 | BSRAM_R64[22] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s/CLKA |
1.523 | 0.249 | tHld | 1 | BSRAM_R64[22] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_1_s |
Path Statistics:
Clock Skew | -0.022 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.296, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.217, 54.717%; tC2Q: 0.180, 45.283% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.274, 100.000% |
Path21
Path Summary:
Slack | 0.173 |
Data Arrival Time | 1.701 |
Data Required Time | 1.528 |
From | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_152_s0 |
To | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_4_s |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.285 | 1.285 | tNET | RR | 1 | R63C114[1][A] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_152_s0/CLK |
1.465 | 0.180 | tC2Q | RR | 1 | R63C114[1][A] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_152_s0/Q |
1.701 | 0.236 | tNET | RR | 1 | BSRAM_R64[24] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_4_s/DI[8] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.279 | 1.279 | tNET | RR | 1 | BSRAM_R64[24] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_4_s/CLKA |
1.528 | 0.249 | tHld | 1 | BSRAM_R64[24] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_4_s |
Path Statistics:
Clock Skew | -0.006 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.285, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.236, 56.757%; tC2Q: 0.180, 43.243% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.279, 100.000% |
Path22
Path Summary:
Slack | 0.173 |
Data Arrival Time | 1.701 |
Data Required Time | 1.528 |
From | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_150_s0 |
To | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_4_s |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.285 | 1.285 | tNET | RR | 1 | R63C114[0][B] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_150_s0/CLK |
1.465 | 0.180 | tC2Q | RR | 1 | R63C114[0][B] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_150_s0/Q |
1.701 | 0.236 | tNET | RR | 1 | BSRAM_R64[24] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_4_s/DI[6] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.279 | 1.279 | tNET | RR | 1 | BSRAM_R64[24] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_4_s/CLKA |
1.528 | 0.249 | tHld | 1 | BSRAM_R64[24] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_4_s |
Path Statistics:
Clock Skew | -0.006 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.285, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.236, 56.757%; tC2Q: 0.180, 43.243% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.279, 100.000% |
Path23
Path Summary:
Slack | 0.173 |
Data Arrival Time | 1.701 |
Data Required Time | 1.528 |
From | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_149_s0 |
To | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_4_s |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.285 | 1.285 | tNET | RR | 1 | R63C118[0][B] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_149_s0/CLK |
1.465 | 0.180 | tC2Q | RR | 1 | R63C118[0][B] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_149_s0/Q |
1.701 | 0.236 | tNET | RR | 1 | BSRAM_R64[24] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_4_s/DI[5] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.279 | 1.279 | tNET | RR | 1 | BSRAM_R64[24] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_4_s/CLKA |
1.528 | 0.249 | tHld | 1 | BSRAM_R64[24] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_4_s |
Path Statistics:
Clock Skew | -0.006 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.285, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.236, 56.757%; tC2Q: 0.180, 43.243% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.279, 100.000% |
Path24
Path Summary:
Slack | 0.173 |
Data Arrival Time | 1.701 |
Data Required Time | 1.528 |
From | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_92_s0 |
To | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_2_s |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.285 | 1.285 | tNET | RR | 1 | R63C112[2][B] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_92_s0/CLK |
1.465 | 0.180 | tC2Q | RR | 1 | R63C112[2][B] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_92_s0/Q |
1.701 | 0.236 | tNET | RR | 1 | BSRAM_R64[23][A] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_2_s/DI[20] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.279 | 1.279 | tNET | RR | 1 | BSRAM_R64[23][A] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_2_s/CLKA |
1.528 | 0.249 | tHld | 1 | BSRAM_R64[23][A] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_2_s |
Path Statistics:
Clock Skew | -0.006 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.285, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.236, 56.757%; tC2Q: 0.180, 43.243% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.279, 100.000% |
Path25
Path Summary:
Slack | 0.175 |
Data Arrival Time | 1.702 |
Data Required Time | 1.528 |
From | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_75_s0 |
To | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_2_s |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.286 | 1.286 | tNET | RR | 1 | R62C111[0][B] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_75_s0/CLK |
1.466 | 0.180 | tC2Q | RR | 1 | R62C111[0][B] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/app_wdf_data_r_75_s0/Q |
1.702 | 0.236 | tNET | RR | 1 | BSRAM_R64[23][A] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_2_s/DI[3] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.279 | 1.279 | tNET | RR | 1 | BSRAM_R64[23][A] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_2_s/CLKA |
1.528 | 0.249 | tHld | 1 | BSRAM_R64[23][A] | u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_2_s |
Path Statistics:
Clock Skew | -0.007 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.286, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.236, 56.757%; tC2Q: 0.180, 43.243% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.279, 100.000% |
Recovery Analysis Report
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 5.589 |
Data Arrival Time | 7.018 |
Data Required Time | 12.608 |
From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rbin_0_s0 |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
2.935 | 2.935 | tNET | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
3.318 | 0.382 | tC2Q | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
4.075 | 0.757 | tNET | RR | 1 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
4.435 | 0.360 | tINS | RF | 80 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
7.018 | 2.583 | tNET | FF | 1 | R58C63[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rbin_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | sysclk | ||||
10.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
12.955 | 2.955 | tNET | RR | 1 | R58C63[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rbin_0_s0/CLK |
12.608 | -0.347 | tSu | 1 | R58C63[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rbin_0_s0 |
Path Statistics:
Clock Skew | 0.020 |
Setup Relationship | 10.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.935, 100.000% |
Arrival Data Path Delay | cell: 0.360, 8.816%; route: 3.341, 81.817%; tC2Q: 0.382, 9.367% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.955, 100.000% |
Path2
Path Summary:
Slack | 5.589 |
Data Arrival Time | 7.018 |
Data Required Time | 12.608 |
From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rbin_1_s0 |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
2.935 | 2.935 | tNET | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
3.318 | 0.382 | tC2Q | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
4.075 | 0.757 | tNET | RR | 1 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
4.435 | 0.360 | tINS | RF | 80 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
7.018 | 2.583 | tNET | FF | 1 | R58C63[0][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rbin_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | sysclk | ||||
10.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
12.955 | 2.955 | tNET | RR | 1 | R58C63[0][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rbin_1_s0/CLK |
12.608 | -0.347 | tSu | 1 | R58C63[0][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rbin_1_s0 |
Path Statistics:
Clock Skew | 0.020 |
Setup Relationship | 10.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.935, 100.000% |
Arrival Data Path Delay | cell: 0.360, 8.816%; route: 3.341, 81.817%; tC2Q: 0.382, 9.367% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.955, 100.000% |
Path3
Path Summary:
Slack | 5.589 |
Data Arrival Time | 7.018 |
Data Required Time | 12.608 |
From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rbin_2_s0 |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
2.935 | 2.935 | tNET | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
3.318 | 0.382 | tC2Q | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
4.075 | 0.757 | tNET | RR | 1 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
4.435 | 0.360 | tINS | RF | 80 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
7.018 | 2.583 | tNET | FF | 1 | R58C63[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rbin_2_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | sysclk | ||||
10.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
12.955 | 2.955 | tNET | RR | 1 | R58C63[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rbin_2_s0/CLK |
12.608 | -0.347 | tSu | 1 | R58C63[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rbin_2_s0 |
Path Statistics:
Clock Skew | 0.020 |
Setup Relationship | 10.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.935, 100.000% |
Arrival Data Path Delay | cell: 0.360, 8.816%; route: 3.341, 81.817%; tC2Q: 0.382, 9.367% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.955, 100.000% |
Path4
Path Summary:
Slack | 5.589 |
Data Arrival Time | 7.018 |
Data Required Time | 12.608 |
From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rbin_3_s0 |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
2.935 | 2.935 | tNET | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
3.318 | 0.382 | tC2Q | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
4.075 | 0.757 | tNET | RR | 1 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
4.435 | 0.360 | tINS | RF | 80 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
7.018 | 2.583 | tNET | FF | 1 | R58C63[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rbin_3_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | sysclk | ||||
10.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
12.955 | 2.955 | tNET | RR | 1 | R58C63[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rbin_3_s0/CLK |
12.608 | -0.347 | tSu | 1 | R58C63[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rbin_3_s0 |
Path Statistics:
Clock Skew | 0.020 |
Setup Relationship | 10.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.935, 100.000% |
Arrival Data Path Delay | cell: 0.360, 8.816%; route: 3.341, 81.817%; tC2Q: 0.382, 9.367% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.955, 100.000% |
Path5
Path Summary:
Slack | 5.590 |
Data Arrival Time | 7.027 |
Data Required Time | 12.617 |
From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_1_s0 |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
2.935 | 2.935 | tNET | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
3.318 | 0.382 | tC2Q | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
4.075 | 0.757 | tNET | RR | 1 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
4.435 | 0.360 | tINS | RF | 80 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
7.027 | 2.592 | tNET | FF | 1 | R58C64[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | sysclk | ||||
10.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
12.964 | 2.964 | tNET | RR | 1 | R58C64[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_1_s0/CLK |
12.617 | -0.347 | tSu | 1 | R58C64[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_1_s0 |
Path Statistics:
Clock Skew | 0.029 |
Setup Relationship | 10.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.935, 100.000% |
Arrival Data Path Delay | cell: 0.360, 8.797%; route: 3.350, 81.856%; tC2Q: 0.382, 9.347% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.964, 100.000% |
Path6
Path Summary:
Slack | 5.590 |
Data Arrival Time | 7.027 |
Data Required Time | 12.617 |
From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_2_s0 |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
2.935 | 2.935 | tNET | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
3.318 | 0.382 | tC2Q | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
4.075 | 0.757 | tNET | RR | 1 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
4.435 | 0.360 | tINS | RF | 80 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
7.027 | 2.592 | tNET | FF | 1 | R58C64[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_2_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | sysclk | ||||
10.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
12.964 | 2.964 | tNET | RR | 1 | R58C64[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_2_s0/CLK |
12.617 | -0.347 | tSu | 1 | R58C64[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_2_s0 |
Path Statistics:
Clock Skew | 0.029 |
Setup Relationship | 10.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.935, 100.000% |
Arrival Data Path Delay | cell: 0.360, 8.797%; route: 3.350, 81.856%; tC2Q: 0.382, 9.347% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.964, 100.000% |
Path7
Path Summary:
Slack | 5.590 |
Data Arrival Time | 7.027 |
Data Required Time | 12.617 |
From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wptr_0_s0 |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
2.935 | 2.935 | tNET | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
3.318 | 0.382 | tC2Q | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
4.075 | 0.757 | tNET | RR | 1 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
4.435 | 0.360 | tINS | RF | 80 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
7.027 | 2.592 | tNET | FF | 1 | R58C64[0][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wptr_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | sysclk | ||||
10.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
12.964 | 2.964 | tNET | RR | 1 | R58C64[0][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wptr_0_s0/CLK |
12.617 | -0.347 | tSu | 1 | R58C64[0][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wptr_0_s0 |
Path Statistics:
Clock Skew | 0.029 |
Setup Relationship | 10.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.935, 100.000% |
Arrival Data Path Delay | cell: 0.360, 8.797%; route: 3.350, 81.856%; tC2Q: 0.382, 9.347% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.964, 100.000% |
Path8
Path Summary:
Slack | 5.590 |
Data Arrival Time | 7.027 |
Data Required Time | 12.617 |
From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wptr_1_s0 |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
2.935 | 2.935 | tNET | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
3.318 | 0.382 | tC2Q | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
4.075 | 0.757 | tNET | RR | 1 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
4.435 | 0.360 | tINS | RF | 80 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
7.027 | 2.592 | tNET | FF | 1 | R58C64[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wptr_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | sysclk | ||||
10.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
12.964 | 2.964 | tNET | RR | 1 | R58C64[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wptr_1_s0/CLK |
12.617 | -0.347 | tSu | 1 | R58C64[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wptr_1_s0 |
Path Statistics:
Clock Skew | 0.029 |
Setup Relationship | 10.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.935, 100.000% |
Arrival Data Path Delay | cell: 0.360, 8.797%; route: 3.350, 81.856%; tC2Q: 0.382, 9.347% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.964, 100.000% |
Path9
Path Summary:
Slack | 5.590 |
Data Arrival Time | 7.027 |
Data Required Time | 12.617 |
From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_1_s0 |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
2.935 | 2.935 | tNET | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
3.318 | 0.382 | tC2Q | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
4.075 | 0.757 | tNET | RR | 1 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
4.435 | 0.360 | tINS | RF | 80 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
7.027 | 2.592 | tNET | FF | 1 | R58C64[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | sysclk | ||||
10.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
12.964 | 2.964 | tNET | RR | 1 | R58C64[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_1_s0/CLK |
12.617 | -0.347 | tSu | 1 | R58C64[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_1_s0 |
Path Statistics:
Clock Skew | 0.029 |
Setup Relationship | 10.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.935, 100.000% |
Arrival Data Path Delay | cell: 0.360, 8.797%; route: 3.350, 81.856%; tC2Q: 0.382, 9.347% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.964, 100.000% |
Path10
Path Summary:
Slack | 5.639 |
Data Arrival Time | 6.982 |
Data Required Time | 12.622 |
From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_Empty_reg_s0 |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
2.935 | 2.935 | tNET | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
3.318 | 0.382 | tC2Q | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
4.075 | 0.757 | tNET | RR | 1 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
4.435 | 0.360 | tINS | RF | 80 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
6.983 | 2.547 | tNET | FF | 1 | R56C62[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_Empty_reg_s0/PRESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | sysclk | ||||
10.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
12.969 | 2.969 | tNET | RR | 1 | R56C62[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_Empty_reg_s0/CLK |
12.622 | -0.347 | tSu | 1 | R56C62[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_Empty_reg_s0 |
Path Statistics:
Clock Skew | 0.034 |
Setup Relationship | 10.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.935, 100.000% |
Arrival Data Path Delay | cell: 0.360, 8.894%; route: 3.305, 81.655%; tC2Q: 0.382, 9.450% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.969, 100.000% |
Path11
Path Summary:
Slack | 5.648 |
Data Arrival Time | 6.974 |
Data Required Time | 12.622 |
From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq1_wptr_3_s0 |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
2.935 | 2.935 | tNET | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
3.318 | 0.382 | tC2Q | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
4.075 | 0.757 | tNET | RR | 1 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
4.435 | 0.360 | tINS | RF | 80 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
6.974 | 2.539 | tNET | FF | 1 | R56C60[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq1_wptr_3_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | sysclk | ||||
10.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
12.969 | 2.969 | tNET | RR | 1 | R56C60[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq1_wptr_3_s0/CLK |
12.622 | -0.347 | tSu | 1 | R56C60[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq1_wptr_3_s0 |
Path Statistics:
Clock Skew | 0.034 |
Setup Relationship | 10.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.935, 100.000% |
Arrival Data Path Delay | cell: 0.360, 8.914%; route: 3.296, 81.616%; tC2Q: 0.382, 9.471% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.969, 100.000% |
Path12
Path Summary:
Slack | 5.648 |
Data Arrival Time | 6.974 |
Data Required Time | 12.622 |
From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rbin_2_s0 |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
2.935 | 2.935 | tNET | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
3.318 | 0.382 | tC2Q | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
4.075 | 0.757 | tNET | RR | 1 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
4.435 | 0.360 | tINS | RF | 80 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
6.974 | 2.539 | tNET | FF | 1 | R56C60[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rbin_2_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | sysclk | ||||
10.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
12.969 | 2.969 | tNET | RR | 1 | R56C60[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rbin_2_s0/CLK |
12.622 | -0.347 | tSu | 1 | R56C60[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rbin_2_s0 |
Path Statistics:
Clock Skew | 0.034 |
Setup Relationship | 10.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.935, 100.000% |
Arrival Data Path Delay | cell: 0.360, 8.914%; route: 3.296, 81.616%; tC2Q: 0.382, 9.471% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.969, 100.000% |
Path13
Path Summary:
Slack | 5.648 |
Data Arrival Time | 6.974 |
Data Required Time | 12.622 |
From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq2_wptr_3_s0 |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
2.935 | 2.935 | tNET | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
3.318 | 0.382 | tC2Q | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
4.075 | 0.757 | tNET | RR | 1 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
4.435 | 0.360 | tINS | RF | 80 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
6.974 | 2.539 | tNET | FF | 1 | R56C60[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq2_wptr_3_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | sysclk | ||||
10.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
12.969 | 2.969 | tNET | RR | 1 | R56C60[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq2_wptr_3_s0/CLK |
12.622 | -0.347 | tSu | 1 | R56C60[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq2_wptr_3_s0 |
Path Statistics:
Clock Skew | 0.034 |
Setup Relationship | 10.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.935, 100.000% |
Arrival Data Path Delay | cell: 0.360, 8.914%; route: 3.296, 81.616%; tC2Q: 0.382, 9.471% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.969, 100.000% |
Path14
Path Summary:
Slack | 5.648 |
Data Arrival Time | 6.974 |
Data Required Time | 12.622 |
From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_3_s0 |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
2.935 | 2.935 | tNET | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
3.318 | 0.382 | tC2Q | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
4.075 | 0.757 | tNET | RR | 1 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
4.435 | 0.360 | tINS | RF | 80 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
6.974 | 2.539 | tNET | FF | 1 | R56C60[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_3_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | sysclk | ||||
10.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
12.969 | 2.969 | tNET | RR | 1 | R56C60[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_3_s0/CLK |
12.622 | -0.347 | tSu | 1 | R56C60[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_3_s0 |
Path Statistics:
Clock Skew | 0.034 |
Setup Relationship | 10.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.935, 100.000% |
Arrival Data Path Delay | cell: 0.360, 8.914%; route: 3.296, 81.616%; tC2Q: 0.382, 9.471% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.969, 100.000% |
Path15
Path Summary:
Slack | 5.648 |
Data Arrival Time | 6.974 |
Data Required Time | 12.622 |
From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_3_s0 |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
2.935 | 2.935 | tNET | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
3.318 | 0.382 | tC2Q | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
4.075 | 0.757 | tNET | RR | 1 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
4.435 | 0.360 | tINS | RF | 80 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
6.974 | 2.539 | tNET | FF | 1 | R56C60[0][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_3_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | sysclk | ||||
10.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
12.969 | 2.969 | tNET | RR | 1 | R56C60[0][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_3_s0/CLK |
12.622 | -0.347 | tSu | 1 | R56C60[0][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_3_s0 |
Path Statistics:
Clock Skew | 0.034 |
Setup Relationship | 10.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.935, 100.000% |
Arrival Data Path Delay | cell: 0.360, 8.914%; route: 3.296, 81.616%; tC2Q: 0.382, 9.471% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.969, 100.000% |
Path16
Path Summary:
Slack | 5.653 |
Data Arrival Time | 6.978 |
Data Required Time | 12.631 |
From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rbin_0_s0 |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
2.935 | 2.935 | tNET | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
3.318 | 0.382 | tC2Q | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
4.075 | 0.757 | tNET | RR | 1 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
4.435 | 0.360 | tINS | RF | 80 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
6.978 | 2.543 | tNET | FF | 1 | R56C61[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rbin_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | sysclk | ||||
10.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
12.979 | 2.979 | tNET | RR | 1 | R56C61[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rbin_0_s0/CLK |
12.631 | -0.347 | tSu | 1 | R56C61[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rbin_0_s0 |
Path Statistics:
Clock Skew | 0.044 |
Setup Relationship | 10.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.935, 100.000% |
Arrival Data Path Delay | cell: 0.360, 8.904%; route: 3.301, 81.635%; tC2Q: 0.382, 9.461% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.979, 100.000% |
Path17
Path Summary:
Slack | 5.653 |
Data Arrival Time | 6.978 |
Data Required Time | 12.631 |
From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rbin_1_s0 |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
2.935 | 2.935 | tNET | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
3.318 | 0.382 | tC2Q | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
4.075 | 0.757 | tNET | RR | 1 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
4.435 | 0.360 | tINS | RF | 80 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
6.978 | 2.543 | tNET | FF | 1 | R56C61[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rbin_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | sysclk | ||||
10.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
12.979 | 2.979 | tNET | RR | 1 | R56C61[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rbin_1_s0/CLK |
12.631 | -0.347 | tSu | 1 | R56C61[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rbin_1_s0 |
Path Statistics:
Clock Skew | 0.044 |
Setup Relationship | 10.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.935, 100.000% |
Arrival Data Path Delay | cell: 0.360, 8.904%; route: 3.301, 81.635%; tC2Q: 0.382, 9.461% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.979, 100.000% |
Path18
Path Summary:
Slack | 5.653 |
Data Arrival Time | 6.978 |
Data Required Time | 12.631 |
From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rbin_3_s0 |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
2.935 | 2.935 | tNET | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
3.318 | 0.382 | tC2Q | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
4.075 | 0.757 | tNET | RR | 1 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
4.435 | 0.360 | tINS | RF | 80 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
6.978 | 2.543 | tNET | FF | 1 | R56C61[0][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rbin_3_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | sysclk | ||||
10.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
12.979 | 2.979 | tNET | RR | 1 | R56C61[0][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rbin_3_s0/CLK |
12.631 | -0.347 | tSu | 1 | R56C61[0][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rbin_3_s0 |
Path Statistics:
Clock Skew | 0.044 |
Setup Relationship | 10.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.935, 100.000% |
Arrival Data Path Delay | cell: 0.360, 8.904%; route: 3.301, 81.635%; tC2Q: 0.382, 9.461% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.979, 100.000% |
Path19
Path Summary:
Slack | 5.802 |
Data Arrival Time | 6.808 |
Data Required Time | 12.610 |
From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_Empty_reg_s0 |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
2.935 | 2.935 | tNET | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
3.318 | 0.382 | tC2Q | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
4.075 | 0.757 | tNET | RR | 1 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
4.435 | 0.360 | tINS | RF | 80 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
6.808 | 2.373 | tNET | FF | 1 | R57C63[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_Empty_reg_s0/PRESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | sysclk | ||||
10.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
12.958 | 2.958 | tNET | RR | 1 | R57C63[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_Empty_reg_s0/CLK |
12.610 | -0.347 | tSu | 1 | R57C63[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_Empty_reg_s0 |
Path Statistics:
Clock Skew | 0.023 |
Setup Relationship | 10.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.935, 100.000% |
Arrival Data Path Delay | cell: 0.360, 9.294%; route: 3.131, 80.831%; tC2Q: 0.382, 9.875% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.958, 100.000% |
Path20
Path Summary:
Slack | 5.811 |
Data Arrival Time | 6.808 |
Data Required Time | 12.619 |
From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_0_s0 |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
2.935 | 2.935 | tNET | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
3.318 | 0.382 | tC2Q | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
4.075 | 0.757 | tNET | RR | 1 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
4.435 | 0.360 | tINS | RF | 80 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
6.808 | 2.373 | tNET | FF | 1 | R57C64[0][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | sysclk | ||||
10.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
12.967 | 2.967 | tNET | RR | 1 | R57C64[0][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_0_s0/CLK |
12.619 | -0.347 | tSu | 1 | R57C64[0][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_0_s0 |
Path Statistics:
Clock Skew | 0.032 |
Setup Relationship | 10.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.935, 100.000% |
Arrival Data Path Delay | cell: 0.360, 9.294%; route: 3.131, 80.831%; tC2Q: 0.382, 9.875% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.967, 100.000% |
Path21
Path Summary:
Slack | 5.811 |
Data Arrival Time | 6.808 |
Data Required Time | 12.619 |
From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_1_s0 |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
2.935 | 2.935 | tNET | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
3.318 | 0.382 | tC2Q | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
4.075 | 0.757 | tNET | RR | 1 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
4.435 | 0.360 | tINS | RF | 80 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
6.808 | 2.373 | tNET | FF | 1 | R57C64[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | sysclk | ||||
10.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
12.967 | 2.967 | tNET | RR | 1 | R57C64[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_1_s0/CLK |
12.619 | -0.347 | tSu | 1 | R57C64[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_1_s0 |
Path Statistics:
Clock Skew | 0.032 |
Setup Relationship | 10.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.935, 100.000% |
Arrival Data Path Delay | cell: 0.360, 9.294%; route: 3.131, 80.831%; tC2Q: 0.382, 9.875% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.967, 100.000% |
Path22
Path Summary:
Slack | 5.811 |
Data Arrival Time | 6.808 |
Data Required Time | 12.619 |
From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_0_s0 |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
2.935 | 2.935 | tNET | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
3.318 | 0.382 | tC2Q | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
4.075 | 0.757 | tNET | RR | 1 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
4.435 | 0.360 | tINS | RF | 80 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
6.808 | 2.373 | tNET | FF | 1 | R57C64[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | sysclk | ||||
10.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
12.967 | 2.967 | tNET | RR | 1 | R57C64[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_0_s0/CLK |
12.619 | -0.347 | tSu | 1 | R57C64[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_0_s0 |
Path Statistics:
Clock Skew | 0.032 |
Setup Relationship | 10.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.935, 100.000% |
Arrival Data Path Delay | cell: 0.360, 9.294%; route: 3.131, 80.831%; tC2Q: 0.382, 9.875% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.967, 100.000% |
Path23
Path Summary:
Slack | 5.833 |
Data Arrival Time | 6.746 |
Data Required Time | 12.578 |
From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_Empty_reg_s0 |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
2.935 | 2.935 | tNET | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
3.318 | 0.382 | tC2Q | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
4.075 | 0.757 | tNET | RR | 1 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
4.435 | 0.360 | tINS | RF | 80 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
6.746 | 2.311 | tNET | FF | 1 | R54C63[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_Empty_reg_s0/PRESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | sysclk | ||||
10.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
12.926 | 2.926 | tNET | RR | 1 | R54C63[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_Empty_reg_s0/CLK |
12.578 | -0.347 | tSu | 1 | R54C63[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_Empty_reg_s0 |
Path Statistics:
Clock Skew | -0.009 |
Setup Relationship | 10.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.935, 100.000% |
Arrival Data Path Delay | cell: 0.360, 9.447%; route: 3.068, 80.515%; tC2Q: 0.382, 10.038% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.926, 100.000% |
Path24
Path Summary:
Slack | 5.833 |
Data Arrival Time | 6.746 |
Data Required Time | 12.578 |
From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rq2_wptr_0_s0 |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
2.935 | 2.935 | tNET | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
3.318 | 0.382 | tC2Q | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
4.075 | 0.757 | tNET | RR | 1 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
4.435 | 0.360 | tINS | RF | 80 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
6.746 | 2.311 | tNET | FF | 1 | R54C63[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rq2_wptr_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | sysclk | ||||
10.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
12.926 | 2.926 | tNET | RR | 1 | R54C63[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rq2_wptr_0_s0/CLK |
12.578 | -0.347 | tSu | 1 | R54C63[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rq2_wptr_0_s0 |
Path Statistics:
Clock Skew | -0.009 |
Setup Relationship | 10.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.935, 100.000% |
Arrival Data Path Delay | cell: 0.360, 9.447%; route: 3.068, 80.515%; tC2Q: 0.382, 10.038% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.926, 100.000% |
Path25
Path Summary:
Slack | 5.833 |
Data Arrival Time | 6.746 |
Data Required Time | 12.578 |
From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rq1_wptr_0_s0 |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
2.935 | 2.935 | tNET | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
3.318 | 0.382 | tC2Q | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
4.075 | 0.757 | tNET | RR | 1 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
4.435 | 0.360 | tINS | RF | 80 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
6.746 | 2.311 | tNET | FF | 1 | R54C63[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rq1_wptr_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | sysclk | ||||
10.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
12.926 | 2.926 | tNET | RR | 1 | R54C63[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rq1_wptr_0_s0/CLK |
12.578 | -0.347 | tSu | 1 | R54C63[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rq1_wptr_0_s0 |
Path Statistics:
Clock Skew | -0.009 |
Setup Relationship | 10.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.935, 100.000% |
Arrival Data Path Delay | cell: 0.360, 9.447%; route: 3.068, 80.515%; tC2Q: 0.382, 10.038% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.926, 100.000% |
Removal Analysis Report
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 1.499 |
Data Arrival Time | 2.620 |
Data Required Time | 1.121 |
From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_0_s0 |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.282 | 1.282 | tNET | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
1.462 | 0.180 | tC2Q | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
1.906 | 0.444 | tNET | RR | 1 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
2.161 | 0.255 | tINS | RR | 80 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
2.620 | 0.459 | tNET | RR | 1 | R56C66[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.310 | 1.310 | tNET | RR | 1 | R56C66[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_0_s0/CLK |
1.121 | -0.189 | tHld | 1 | R56C66[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_0_s0 |
Path Statistics:
Clock Skew | 0.027 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.282, 100.000% |
Arrival Data Path Delay | cell: 0.255, 19.065%; route: 0.903, 67.477%; tC2Q: 0.180, 13.458% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.310, 100.000% |
Path2
Path Summary:
Slack | 1.499 |
Data Arrival Time | 2.620 |
Data Required Time | 1.121 |
From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_0_s0 |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.282 | 1.282 | tNET | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
1.462 | 0.180 | tC2Q | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
1.906 | 0.444 | tNET | RR | 1 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
2.161 | 0.255 | tINS | RR | 80 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
2.620 | 0.459 | tNET | RR | 1 | R56C66[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.310 | 1.310 | tNET | RR | 1 | R56C66[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_0_s0/CLK |
1.121 | -0.189 | tHld | 1 | R56C66[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_0_s0 |
Path Statistics:
Clock Skew | 0.027 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.282, 100.000% |
Arrival Data Path Delay | cell: 0.255, 19.065%; route: 0.903, 67.477%; tC2Q: 0.180, 13.458% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.310, 100.000% |
Path3
Path Summary:
Slack | 1.499 |
Data Arrival Time | 2.620 |
Data Required Time | 1.121 |
From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_1_s0 |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.282 | 1.282 | tNET | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
1.462 | 0.180 | tC2Q | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
1.906 | 0.444 | tNET | RR | 1 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
2.161 | 0.255 | tINS | RR | 80 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
2.620 | 0.459 | tNET | RR | 1 | R56C66[0][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.310 | 1.310 | tNET | RR | 1 | R56C66[0][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_1_s0/CLK |
1.121 | -0.189 | tHld | 1 | R56C66[0][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_1_s0 |
Path Statistics:
Clock Skew | 0.027 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.282, 100.000% |
Arrival Data Path Delay | cell: 0.255, 19.065%; route: 0.903, 67.477%; tC2Q: 0.180, 13.458% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.310, 100.000% |
Path4
Path Summary:
Slack | 1.499 |
Data Arrival Time | 2.620 |
Data Required Time | 1.121 |
From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_2_s0 |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.282 | 1.282 | tNET | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
1.462 | 0.180 | tC2Q | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
1.906 | 0.444 | tNET | RR | 1 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
2.161 | 0.255 | tINS | RR | 80 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
2.620 | 0.459 | tNET | RR | 1 | R56C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_2_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.310 | 1.310 | tNET | RR | 1 | R56C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_2_s0/CLK |
1.121 | -0.189 | tHld | 1 | R56C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_2_s0 |
Path Statistics:
Clock Skew | 0.027 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.282, 100.000% |
Arrival Data Path Delay | cell: 0.255, 19.065%; route: 0.903, 67.477%; tC2Q: 0.180, 13.458% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.310, 100.000% |
Path5
Path Summary:
Slack | 1.499 |
Data Arrival Time | 2.620 |
Data Required Time | 1.121 |
From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_3_s0 |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.282 | 1.282 | tNET | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
1.462 | 0.180 | tC2Q | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
1.906 | 0.444 | tNET | RR | 1 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
2.161 | 0.255 | tINS | RR | 80 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
2.620 | 0.459 | tNET | RR | 1 | R56C66[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_3_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.310 | 1.310 | tNET | RR | 1 | R56C66[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_3_s0/CLK |
1.121 | -0.189 | tHld | 1 | R56C66[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_3_s0 |
Path Statistics:
Clock Skew | 0.027 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.282, 100.000% |
Arrival Data Path Delay | cell: 0.255, 19.065%; route: 0.903, 67.477%; tC2Q: 0.180, 13.458% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.310, 100.000% |
Path6
Path Summary:
Slack | 2.226 |
Data Arrival Time | 3.345 |
Data Required Time | 1.119 |
From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rq2_wptr_2_s0 |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.282 | 1.282 | tNET | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
1.462 | 0.180 | tC2Q | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
1.906 | 0.444 | tNET | RR | 1 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
2.161 | 0.255 | tINS | RR | 80 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
3.345 | 1.184 | tNET | RR | 1 | R57C60[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rq2_wptr_2_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.307 | 1.307 | tNET | RR | 1 | R57C60[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rq2_wptr_2_s0/CLK |
1.119 | -0.189 | tHld | 1 | R57C60[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rq2_wptr_2_s0 |
Path Statistics:
Clock Skew | 0.025 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.282, 100.000% |
Arrival Data Path Delay | cell: 0.255, 12.362%; route: 1.628, 78.912%; tC2Q: 0.180, 8.726% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.307, 100.000% |
Path7
Path Summary:
Slack | 2.226 |
Data Arrival Time | 3.345 |
Data Required Time | 1.119 |
From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rq1_wptr_2_s0 |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.282 | 1.282 | tNET | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
1.462 | 0.180 | tC2Q | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
1.906 | 0.444 | tNET | RR | 1 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
2.161 | 0.255 | tINS | RR | 80 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
3.345 | 1.184 | tNET | RR | 1 | R57C60[2][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rq1_wptr_2_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.307 | 1.307 | tNET | RR | 1 | R57C60[2][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rq1_wptr_2_s0/CLK |
1.119 | -0.189 | tHld | 1 | R57C60[2][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rq1_wptr_2_s0 |
Path Statistics:
Clock Skew | 0.025 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.282, 100.000% |
Arrival Data Path Delay | cell: 0.255, 12.362%; route: 1.628, 78.912%; tC2Q: 0.180, 8.726% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.307, 100.000% |
Path8
Path Summary:
Slack | 2.226 |
Data Arrival Time | 3.345 |
Data Required Time | 1.119 |
From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_wbin_2_s0 |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.282 | 1.282 | tNET | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
1.462 | 0.180 | tC2Q | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
1.906 | 0.444 | tNET | RR | 1 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
2.161 | 0.255 | tINS | RR | 80 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
3.345 | 1.184 | tNET | RR | 1 | R57C60[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_wbin_2_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.307 | 1.307 | tNET | RR | 1 | R57C60[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_wbin_2_s0/CLK |
1.119 | -0.189 | tHld | 1 | R57C60[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_wbin_2_s0 |
Path Statistics:
Clock Skew | 0.025 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.282, 100.000% |
Arrival Data Path Delay | cell: 0.255, 12.362%; route: 1.628, 78.912%; tC2Q: 0.180, 8.726% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.307, 100.000% |
Path9
Path Summary:
Slack | 2.226 |
Data Arrival Time | 3.345 |
Data Required Time | 1.119 |
From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq2_wptr_2_s0 |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.282 | 1.282 | tNET | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
1.462 | 0.180 | tC2Q | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
1.906 | 0.444 | tNET | RR | 1 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
2.161 | 0.255 | tINS | RR | 80 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
3.345 | 1.184 | tNET | RR | 1 | R57C60[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq2_wptr_2_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.307 | 1.307 | tNET | RR | 1 | R57C60[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq2_wptr_2_s0/CLK |
1.119 | -0.189 | tHld | 1 | R57C60[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq2_wptr_2_s0 |
Path Statistics:
Clock Skew | 0.025 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.282, 100.000% |
Arrival Data Path Delay | cell: 0.255, 12.362%; route: 1.628, 78.912%; tC2Q: 0.180, 8.726% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.307, 100.000% |
Path10
Path Summary:
Slack | 2.226 |
Data Arrival Time | 3.345 |
Data Required Time | 1.119 |
From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq1_wptr_2_s0 |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.282 | 1.282 | tNET | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
1.462 | 0.180 | tC2Q | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
1.906 | 0.444 | tNET | RR | 1 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
2.161 | 0.255 | tINS | RR | 80 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
3.345 | 1.184 | tNET | RR | 1 | R57C60[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq1_wptr_2_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.307 | 1.307 | tNET | RR | 1 | R57C60[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq1_wptr_2_s0/CLK |
1.119 | -0.189 | tHld | 1 | R57C60[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq1_wptr_2_s0 |
Path Statistics:
Clock Skew | 0.025 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.282, 100.000% |
Arrival Data Path Delay | cell: 0.255, 12.362%; route: 1.628, 78.912%; tC2Q: 0.180, 8.726% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.307, 100.000% |
Path11
Path Summary:
Slack | 2.226 |
Data Arrival Time | 3.350 |
Data Required Time | 1.124 |
From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_0_s0 |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.282 | 1.282 | tNET | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
1.462 | 0.180 | tC2Q | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
1.906 | 0.444 | tNET | RR | 1 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
2.161 | 0.255 | tINS | RR | 80 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
3.350 | 1.189 | tNET | RR | 1 | R57C61[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.313 | 1.313 | tNET | RR | 1 | R57C61[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_0_s0/CLK |
1.124 | -0.189 | tHld | 1 | R57C61[1][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_0_s0 |
Path Statistics:
Clock Skew | 0.030 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.282, 100.000% |
Arrival Data Path Delay | cell: 0.255, 12.332%; route: 1.633, 78.963%; tC2Q: 0.180, 8.705% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.313, 100.000% |
Path12
Path Summary:
Slack | 2.226 |
Data Arrival Time | 3.350 |
Data Required Time | 1.124 |
From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_1_s0 |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.282 | 1.282 | tNET | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
1.462 | 0.180 | tC2Q | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
1.906 | 0.444 | tNET | RR | 1 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
2.161 | 0.255 | tINS | RR | 80 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
3.350 | 1.189 | tNET | RR | 1 | R57C61[0][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.313 | 1.313 | tNET | RR | 1 | R57C61[0][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_1_s0/CLK |
1.124 | -0.189 | tHld | 1 | R57C61[0][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_1_s0 |
Path Statistics:
Clock Skew | 0.030 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.282, 100.000% |
Arrival Data Path Delay | cell: 0.255, 12.332%; route: 1.633, 78.963%; tC2Q: 0.180, 8.705% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.313, 100.000% |
Path13
Path Summary:
Slack | 2.226 |
Data Arrival Time | 3.350 |
Data Required Time | 1.124 |
From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_2_s0 |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.282 | 1.282 | tNET | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
1.462 | 0.180 | tC2Q | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
1.906 | 0.444 | tNET | RR | 1 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
2.161 | 0.255 | tINS | RR | 80 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
3.350 | 1.189 | tNET | RR | 1 | R57C61[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_2_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.313 | 1.313 | tNET | RR | 1 | R57C61[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_2_s0/CLK |
1.124 | -0.189 | tHld | 1 | R57C61[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_2_s0 |
Path Statistics:
Clock Skew | 0.030 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.282, 100.000% |
Arrival Data Path Delay | cell: 0.255, 12.332%; route: 1.633, 78.963%; tC2Q: 0.180, 8.705% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.313, 100.000% |
Path14
Path Summary:
Slack | 2.226 |
Data Arrival Time | 3.350 |
Data Required Time | 1.124 |
From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_3_s0 |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.282 | 1.282 | tNET | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
1.462 | 0.180 | tC2Q | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
1.906 | 0.444 | tNET | RR | 1 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
2.161 | 0.255 | tINS | RR | 80 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
3.350 | 1.189 | tNET | RR | 1 | R57C61[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_3_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.313 | 1.313 | tNET | RR | 1 | R57C61[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_3_s0/CLK |
1.124 | -0.189 | tHld | 1 | R57C61[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_3_s0 |
Path Statistics:
Clock Skew | 0.030 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.282, 100.000% |
Arrival Data Path Delay | cell: 0.255, 12.332%; route: 1.633, 78.963%; tC2Q: 0.180, 8.705% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.313, 100.000% |
Path15
Path Summary:
Slack | 2.226 |
Data Arrival Time | 3.345 |
Data Required Time | 1.119 |
From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_2_s0 |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.282 | 1.282 | tNET | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
1.462 | 0.180 | tC2Q | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
1.906 | 0.444 | tNET | RR | 1 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
2.161 | 0.255 | tINS | RR | 80 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
3.345 | 1.184 | tNET | RR | 1 | R57C60[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_2_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.307 | 1.307 | tNET | RR | 1 | R57C60[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_2_s0/CLK |
1.119 | -0.189 | tHld | 1 | R57C60[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_2_s0 |
Path Statistics:
Clock Skew | 0.025 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.282, 100.000% |
Arrival Data Path Delay | cell: 0.255, 12.362%; route: 1.628, 78.912%; tC2Q: 0.180, 8.726% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.307, 100.000% |
Path16
Path Summary:
Slack | 2.226 |
Data Arrival Time | 3.345 |
Data Required Time | 1.119 |
From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_2_s0 |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.282 | 1.282 | tNET | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
1.462 | 0.180 | tC2Q | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
1.906 | 0.444 | tNET | RR | 1 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
2.161 | 0.255 | tINS | RR | 80 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
3.345 | 1.184 | tNET | RR | 1 | R57C60[0][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_2_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.307 | 1.307 | tNET | RR | 1 | R57C60[0][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_2_s0/CLK |
1.119 | -0.189 | tHld | 1 | R57C60[0][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_2_s0 |
Path Statistics:
Clock Skew | 0.025 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.282, 100.000% |
Arrival Data Path Delay | cell: 0.255, 12.362%; route: 1.628, 78.912%; tC2Q: 0.180, 8.726% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.307, 100.000% |
Path17
Path Summary:
Slack | 2.230 |
Data Arrival Time | 3.323 |
Data Required Time | 1.093 |
From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rq1_wptr_3_s0 |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.282 | 1.282 | tNET | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
1.462 | 0.180 | tC2Q | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
1.906 | 0.444 | tNET | RR | 1 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
2.161 | 0.255 | tINS | RR | 80 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
3.323 | 1.163 | tNET | RR | 1 | R54C60[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rq1_wptr_3_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.282 | 1.282 | tNET | RR | 1 | R54C60[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rq1_wptr_3_s0/CLK |
1.093 | -0.189 | tHld | 1 | R54C60[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_rq1_wptr_3_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.282, 100.000% |
Arrival Data Path Delay | cell: 0.255, 12.492%; route: 1.606, 78.690%; tC2Q: 0.180, 8.818% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.282, 100.000% |
Path18
Path Summary:
Slack | 2.230 |
Data Arrival Time | 3.323 |
Data Required Time | 1.093 |
From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_wptr_1_s0 |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.282 | 1.282 | tNET | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
1.462 | 0.180 | tC2Q | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
1.906 | 0.444 | tNET | RR | 1 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
2.161 | 0.255 | tINS | RR | 80 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
3.323 | 1.163 | tNET | RR | 1 | R54C60[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_wptr_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.282 | 1.282 | tNET | RR | 1 | R54C60[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_wptr_1_s0/CLK |
1.093 | -0.189 | tHld | 1 | R54C60[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_wptr_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.282, 100.000% |
Arrival Data Path Delay | cell: 0.255, 12.492%; route: 1.606, 78.690%; tC2Q: 0.180, 8.818% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.282, 100.000% |
Path19
Path Summary:
Slack | 2.230 |
Data Arrival Time | 3.323 |
Data Required Time | 1.093 |
From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_wptr_1_s0 |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.282 | 1.282 | tNET | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
1.462 | 0.180 | tC2Q | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
1.906 | 0.444 | tNET | RR | 1 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
2.161 | 0.255 | tINS | RR | 80 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
3.323 | 1.163 | tNET | RR | 1 | R54C60[0][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_wptr_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.282 | 1.282 | tNET | RR | 1 | R54C60[0][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_wptr_1_s0/CLK |
1.093 | -0.189 | tHld | 1 | R54C60[0][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_wptr_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.282, 100.000% |
Arrival Data Path Delay | cell: 0.255, 12.492%; route: 1.606, 78.690%; tC2Q: 0.180, 8.818% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.282, 100.000% |
Path20
Path Summary:
Slack | 2.230 |
Data Arrival Time | 3.323 |
Data Required Time | 1.093 |
From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_1_s0 |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.282 | 1.282 | tNET | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
1.462 | 0.180 | tC2Q | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
1.906 | 0.444 | tNET | RR | 1 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
2.161 | 0.255 | tINS | RR | 80 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
3.323 | 1.163 | tNET | RR | 1 | R54C60[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.282 | 1.282 | tNET | RR | 1 | R54C60[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_1_s0/CLK |
1.093 | -0.189 | tHld | 1 | R54C60[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.282, 100.000% |
Arrival Data Path Delay | cell: 0.255, 12.492%; route: 1.606, 78.690%; tC2Q: 0.180, 8.818% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.282, 100.000% |
Path21
Path Summary:
Slack | 2.230 |
Data Arrival Time | 3.328 |
Data Required Time | 1.098 |
From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_wbin_0_s0 |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.282 | 1.282 | tNET | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
1.462 | 0.180 | tC2Q | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
1.906 | 0.444 | tNET | RR | 1 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
2.161 | 0.255 | tINS | RR | 80 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
3.328 | 1.168 | tNET | RR | 1 | R54C61[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_wbin_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.287 | 1.287 | tNET | RR | 1 | R54C61[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_wbin_0_s0/CLK |
1.098 | -0.189 | tHld | 1 | R54C61[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[3].fifo_ctrl/if_wbin_0_s0 |
Path Statistics:
Clock Skew | 0.005 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.282, 100.000% |
Arrival Data Path Delay | cell: 0.255, 12.462%; route: 1.611, 78.742%; tC2Q: 0.180, 8.797% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.287, 100.000% |
Path22
Path Summary:
Slack | 2.230 |
Data Arrival Time | 3.328 |
Data Required Time | 1.098 |
From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq2_wptr_1_s0 |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.282 | 1.282 | tNET | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
1.462 | 0.180 | tC2Q | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
1.906 | 0.444 | tNET | RR | 1 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
2.161 | 0.255 | tINS | RR | 80 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
3.328 | 1.168 | tNET | RR | 1 | R54C61[2][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq2_wptr_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.287 | 1.287 | tNET | RR | 1 | R54C61[2][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq2_wptr_1_s0/CLK |
1.098 | -0.189 | tHld | 1 | R54C61[2][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq2_wptr_1_s0 |
Path Statistics:
Clock Skew | 0.005 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.282, 100.000% |
Arrival Data Path Delay | cell: 0.255, 12.462%; route: 1.611, 78.742%; tC2Q: 0.180, 8.797% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.287, 100.000% |
Path23
Path Summary:
Slack | 2.230 |
Data Arrival Time | 3.328 |
Data Required Time | 1.098 |
From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq1_wptr_1_s0 |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.282 | 1.282 | tNET | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
1.462 | 0.180 | tC2Q | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
1.906 | 0.444 | tNET | RR | 1 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
2.161 | 0.255 | tINS | RR | 80 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
3.328 | 1.168 | tNET | RR | 1 | R54C61[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq1_wptr_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.287 | 1.287 | tNET | RR | 1 | R54C61[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq1_wptr_1_s0/CLK |
1.098 | -0.189 | tHld | 1 | R54C61[3][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[2].fifo_ctrl/if_rq1_wptr_1_s0 |
Path Statistics:
Clock Skew | 0.005 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.282, 100.000% |
Arrival Data Path Delay | cell: 0.255, 12.462%; route: 1.611, 78.742%; tC2Q: 0.180, 8.797% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.287, 100.000% |
Path24
Path Summary:
Slack | 2.230 |
Data Arrival Time | 3.328 |
Data Required Time | 1.098 |
From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_0_s0 |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.282 | 1.282 | tNET | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
1.462 | 0.180 | tC2Q | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
1.906 | 0.444 | tNET | RR | 1 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
2.161 | 0.255 | tINS | RR | 80 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
3.328 | 1.168 | tNET | RR | 1 | R54C61[0][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.287 | 1.287 | tNET | RR | 1 | R54C61[0][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_0_s0/CLK |
1.098 | -0.189 | tHld | 1 | R54C61[0][B] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_0_s0 |
Path Statistics:
Clock Skew | 0.005 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.282, 100.000% |
Arrival Data Path Delay | cell: 0.255, 12.462%; route: 1.611, 78.742%; tC2Q: 0.180, 8.797% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.287, 100.000% |
Path25
Path Summary:
Slack | 2.230 |
Data Arrival Time | 3.328 |
Data Required Time | 1.098 |
From | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0 |
To | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_0_s0 |
Launch Clk | sysclk:[R] |
Latch Clk | sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.282 | 1.282 | tNET | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK |
1.462 | 0.180 | tC2Q | RR | 1 | R54C78[2][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q |
1.906 | 0.444 | tNET | RR | 1 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1 |
2.161 | 0.255 | tINS | RR | 80 | R54C66[0][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F |
3.328 | 1.168 | tNET | RR | 1 | R54C61[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sysclk | ||||
0.000 | 0.000 | tCL | RR | 6401 | LEFTSIDE[4] | u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
1.287 | 1.287 | tNET | RR | 1 | R54C61[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_0_s0/CLK |
1.098 | -0.189 | tHld | 1 | R54C61[1][A] | u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_0_s0 |
Path Statistics:
Clock Skew | 0.005 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.282, 100.000% |
Arrival Data Path Delay | cell: 0.255, 12.462%; route: 1.611, 78.742%; tC2Q: 0.180, 8.797% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.287, 100.000% |
Minimum Pulse Width Report:
Report Command:report_min_pulse_width -nworst 10 -detail
MPW1
MPW Summary:
Slack: | 2.565 |
Actual Width: | 2.815 |
Required Width: | 0.250 |
Type: | Low Pulse Width |
Clock: | clk100 |
Objects: | u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/recalib_s_0_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | clk100 | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | clk_ibuf/O |
10.459 | 4.772 | tNET | FF | u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/recalib_s_0_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk100 | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.675 | 0.675 | tINS | RR | clk_ibuf/O |
13.274 | 2.599 | tNET | RR | u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/recalib_s_0_s0/CLK |
MPW2
MPW Summary:
Slack: | 2.565 |
Actual Width: | 2.815 |
Required Width: | 0.250 |
Type: | Low Pulse Width |
Clock: | clk100 |
Objects: | u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/cs_memsync_4_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | clk100 | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | clk_ibuf/O |
10.459 | 4.772 | tNET | FF | u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/cs_memsync_4_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk100 | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.675 | 0.675 | tINS | RR | clk_ibuf/O |
13.274 | 2.599 | tNET | RR | u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/cs_memsync_4_s0/CLK |
MPW3
MPW Summary:
Slack: | 2.565 |
Actual Width: | 2.815 |
Required Width: | 0.250 |
Type: | Low Pulse Width |
Clock: | clk100 |
Objects: | u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/cs_memsync_3_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | clk100 | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | clk_ibuf/O |
10.459 | 4.772 | tNET | FF | u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/cs_memsync_3_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk100 | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.675 | 0.675 | tINS | RR | clk_ibuf/O |
13.274 | 2.599 | tNET | RR | u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/cs_memsync_3_s0/CLK |
MPW4
MPW Summary:
Slack: | 2.565 |
Actual Width: | 2.815 |
Required Width: | 0.250 |
Type: | Low Pulse Width |
Clock: | clk100 |
Objects: | u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/flag_0_s4 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | clk100 | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | clk_ibuf/O |
10.459 | 4.772 | tNET | FF | u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/flag_0_s4/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk100 | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.675 | 0.675 | tINS | RR | clk_ibuf/O |
13.274 | 2.599 | tNET | RR | u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/flag_0_s4/CLK |
MPW5
MPW Summary:
Slack: | 2.566 |
Actual Width: | 2.816 |
Required Width: | 0.250 |
Type: | Low Pulse Width |
Clock: | clk100 |
Objects: | u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_11_s1 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | clk100 | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | clk_ibuf/O |
10.453 | 4.766 | tNET | FF | u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_11_s1/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk100 | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.675 | 0.675 | tINS | RR | clk_ibuf/O |
13.269 | 2.594 | tNET | RR | u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_11_s1/CLK |
MPW6
MPW Summary:
Slack: | 2.566 |
Actual Width: | 2.816 |
Required Width: | 0.250 |
Type: | Low Pulse Width |
Clock: | clk100 |
Objects: | u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_2_s1 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | clk100 | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | clk_ibuf/O |
10.453 | 4.766 | tNET | FF | u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_2_s1/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk100 | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.675 | 0.675 | tINS | RR | clk_ibuf/O |
13.269 | 2.594 | tNET | RR | u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_2_s1/CLK |
MPW7
MPW Summary:
Slack: | 2.566 |
Actual Width: | 2.816 |
Required Width: | 0.250 |
Type: | Low Pulse Width |
Clock: | clk100 |
Objects: | u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/flag_1_s2 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | clk100 | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | clk_ibuf/O |
10.453 | 4.766 | tNET | FF | u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/flag_1_s2/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk100 | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.675 | 0.675 | tINS | RR | clk_ibuf/O |
13.269 | 2.594 | tNET | RR | u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/flag_1_s2/CLK |
MPW8
MPW Summary:
Slack: | 2.567 |
Actual Width: | 2.817 |
Required Width: | 0.250 |
Type: | Low Pulse Width |
Clock: | clk100 |
Objects: | u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_syn_1_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | clk100 | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | clk_ibuf/O |
10.447 | 4.760 | tNET | FF | u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_syn_1_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk100 | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.675 | 0.675 | tINS | RR | clk_ibuf/O |
13.264 | 2.589 | tNET | RR | u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_syn_1_s0/CLK |
MPW9
MPW Summary:
Slack: | 2.567 |
Actual Width: | 2.817 |
Required Width: | 0.250 |
Type: | Low Pulse Width |
Clock: | clk100 |
Objects: | u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_3_s1 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | clk100 | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | clk_ibuf/O |
10.447 | 4.760 | tNET | FF | u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_3_s1/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk100 | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.675 | 0.675 | tINS | RR | clk_ibuf/O |
13.264 | 2.589 | tNET | RR | u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_3_s1/CLK |
MPW10
MPW Summary:
Slack: | 2.567 |
Actual Width: | 2.817 |
Required Width: | 0.250 |
Type: | High Pulse Width |
Clock: | clk100 |
Objects: | u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/cs_memsync_4_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||
0.000 | 0.000 | clk100 | ||
0.000 | 0.000 | tCL | RR | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | clk_ibuf/O |
5.978 | 5.295 | tNET | RR | u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/cs_memsync_4_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | clk100 | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | clk_ibuf/O |
8.795 | 3.117 | tNET | FF | u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/cs_memsync_4_s0/CLK |
High Fanout Nets Report:
Report Command:report_high_fanout_nets -max_nets 10
FANOUT | NET NAME | WORST SLACK | MAX DELAY |
---|---|---|---|
6401 | clk_x1 | 0.013 | 2.998 |
344 | eye_calib_start_rr | 2.255 | 4.075 |
336 | ddr_init_internal_rr | 3.802 | 4.940 |
321 | eye_calib_start_rr[0] | 4.633 | 4.301 |
293 | dqsts1 | 3.954 | 5.129 |
292 | dqs_reg | 3.870 | 5.206 |
257 | phy_rddata_valid_d1 | 5.847 | 3.529 |
128 | raddr[2] | 0.813 | 2.531 |
108 | n258_6 | 0.091 | 7.229 |
102 | memory_clk | 2.004 | 0.005 |
Route Congestions Report:
Report Command:report_route_congestion -max_grids 10
GRID LOC | ROUTE CONGESTIONS |
---|---|
R47C82 | 70.83% |
R63C102 | 70.83% |
R62C67 | 68.06% |
R47C83 | 66.67% |
R62C50 | 66.67% |
R62C110 | 66.67% |
R48C128 | 65.28% |
R63C48 | 65.28% |
R59C85 | 65.28% |
R48C79 | 63.89% |
Timing Exceptions Report:
Setup Analysis Report
Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Hold Analysis Report
Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Recovery Analysis Report
Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Removal Analysis Report
Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Timing Constraints Report:
SDC Command Type | State | Detail Command |
---|---|---|
TC_CLOCK | Actived | create_clock -name clk400 -period 2.5 -waveform {0 1.25} [get_nets {memory_clk}] |
TC_CLOCK | Actived | create_clock -name clk100 -period 10 -waveform {0 5} [get_ports {clk}] |
TC_CLOCK | Actived | create_clock -name sysclk -period 10 -waveform {0 5} [get_pins {u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT}] |
TC_CLOCK_GROUP | Actived | set_clock_groups -asynchronous -group [get_clocks {clk100}] -group [get_clocks {sysclk}] |
TC_CLOCK_GROUP | Actived | set_clock_groups -asynchronous -group [get_clocks {sysclk}] -group [get_clocks {clk400}] |
TC_CLOCK_GROUP | Actived | set_clock_groups -asynchronous -group [get_clocks {clk100}] -group [get_clocks {clk400}] |