Synthesis Messages

Report Title GowinSynthesis Report
Design File E:\myWork\IP\releaseVerify\new\RefDesign\Memory_Control\DDR3\Gowin_DDR3_Memory_Interface_refDesign\DDR3_MC_PHY_1vs4_2A18K\project\src\DDR3_test_rst.v
E:\myWork\IP\releaseVerify\new\RefDesign\Memory_Control\DDR3\Gowin_DDR3_Memory_Interface_refDesign\DDR3_MC_PHY_1vs4_2A18K\project\src\ddr3_memory_interface\ddr3_memory_interface.v
E:\myWork\IP\releaseVerify\new\RefDesign\Memory_Control\DDR3\Gowin_DDR3_Memory_Interface_refDesign\DDR3_MC_PHY_1vs4_2A18K\project\src\ddr3_syn_top.v
E:\myWork\IP\releaseVerify\new\RefDesign\Memory_Control\DDR3\Gowin_DDR3_Memory_Interface_refDesign\DDR3_MC_PHY_1vs4_2A18K\project\src\gowin_rpll\gowin_rpll.v
E:\myWork\IP\releaseVerify\new\RefDesign\Memory_Control\DDR3\Gowin_DDR3_Memory_Interface_refDesign\DDR3_MC_PHY_1vs4_2A18K\project\src\key_debounce.v
GowinSynthesis Constraints File ---
GowinSynthesis Version GowinSynthesis V1.9.8
Part Number GW2A-LV18PG256C8/I7
Device GW2A-18
Created Time Mon Aug 30 14:23:45 2021
Legal Announcement Copyright (C)2014-2021 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module ddr3_syn_top
Synthesis Process Running parser:
    CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 166.801MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.359s, Elapsed time = 0h 0m 0.356s, Peak memory usage = 166.801MB
    Optimizing Phase 1: CPU time = 0h 0m 0.25s, Elapsed time = 0h 0m 0.247s, Peak memory usage = 166.801MB
    Optimizing Phase 2: CPU time = 0h 0m 0.562s, Elapsed time = 0h 0m 0.565s, Peak memory usage = 166.801MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.085s, Peak memory usage = 166.801MB
    Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 166.801MB
    Inferring Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.03s, Peak memory usage = 166.801MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 166.801MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.193s, Peak memory usage = 166.801MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.031s, Peak memory usage = 166.801MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.021s, Peak memory usage = 166.801MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 175.688MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.123s, Peak memory usage = 175.688MB
Generate output files:
    CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.198s, Peak memory usage = 175.688MB
Total Time and Memory Usage CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s, Peak memory usage = 175.688MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 56
I/O Buf 51
    IBUF 2
    OBUF 28
    TBUF 2
    IOBUF 16
    ELVDS_OBUF 1
    ELVDS_IOBUF 2
Register 1427
    DFF 98
    DFFE 5
    DFFS 1
    DFFR 21
    DFFP 58
    DFFPE 3
    DFFC 804
    DFFCE 436
    DLCE 1
LUT 1616
    LUT2 353
    LUT3 345
    LUT4 918
ALU 153
    ALU 153
SSRAM 110
    RAM16S4 40
    RAM16SDP4 70
INV 21
    INV 21
IOLOGIC 98
    IDES8_MEM 16
    OSER8 23
    OSER8_MEM 20
    IODELAY 39
BSRAM 12
    SDPX9B 8
    pROMX9 4
CLOCK 6
    DLL 1
    CLKDIV 1
    DQS 2
    DHCEN 1
    rPLL 1

Resource Utilization Summary

Resource Usage Utilization
Logic 2450(1637 LUTs, 153 ALUs, 110 SSRAMs) / 20736 12%
Register 1427 / 16173 9%
  --Register as Latch 1 / 16173 1%
  --Register as FF 1426 / 16173 9%
BSRAM 12 / 46 26%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
clk Base 20.000 50.0 0.000 10.000 clk_ibuf/I
ddr_rst Base 10.000 100.0 0.000 5.000 u_ddr3/gw3_top/i4/ddr_rsti_reg_2_s0/Q
pll/rpll_inst/CLKOUT.default_gen_clk Generated 2.500 400.0 0.000 1.250 clk_ibuf/I clk pll/rpll_inst/CLKOUT
pll/rpll_inst/CLKOUTP.default_gen_clk Generated 2.500 400.0 0.000 1.250 clk_ibuf/I clk pll/rpll_inst/CLKOUTP
pll/rpll_inst/CLKOUTD.default_gen_clk Generated 5.000 200.0 0.000 2.500 clk_ibuf/I clk pll/rpll_inst/CLKOUTD
pll/rpll_inst/CLKOUTD3.default_gen_clk Generated 7.500 133.3 0.000 3.750 clk_ibuf/I clk pll/rpll_inst/CLKOUTD3
u_ddr3/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk Generated 10.000 100.0 0.000 5.000 pll/rpll_inst/CLKOUT pll/rpll_inst/CLKOUT.default_gen_clk u_ddr3/gw3_top/i4/fclkdiv/CLKOUT

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 50.0(MHz) 241.5(MHz) 6 TOP
2 ddr_rst 100.0(MHz) 683.1(MHz) 2 TOP
3 pll/rpll_inst/CLKOUT.default_gen_clk 400.0(MHz) 1364.3(MHz) 1 TOP
4 u_ddr3/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk 100.0(MHz) 173.6(MHz) 8 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 0.579
Data Arrival Time 9.701
Data Required Time 10.281
From u_ddr3/gw3_top/i4/ddr3_dll
To u_ddr3/gw3_top/i4/dll_step_base_0_s0
Launch Clk pll/rpll_inst/CLKOUT.default_gen_clk[R]
Latch Clk u_ddr3/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
7.500 0.000 pll/rpll_inst/CLKOUT.default_gen_clk
8.529 1.029 tCL RR 1 pll/rpll_inst/CLKOUT
8.709 0.180 tNET RR 3 u_ddr3/gw3_top/i4/fclk_dhcen/CLKIN
8.891 0.182 tINS RR 63 u_ddr3/gw3_top/i4/fclk_dhcen/CLKOUT
9.071 0.180 tNET RR 8 u_ddr3/gw3_top/i4/ddr3_dll/CLKIN
9.464 0.393 tINS RF 4 u_ddr3/gw3_top/i4/ddr3_dll/STEP[0]
9.701 0.237 tNET FF 1 u_ddr3/gw3_top/i4/dll_step_base_0_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 u_ddr3/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk
10.170 0.170 tCL RR 1551 u_ddr3/gw3_top/i4/fclkdiv/CLKOUT
10.351 0.180 tNET RR 1 u_ddr3/gw3_top/i4/dll_step_base_0_s0/CLK
10.316 -0.035 tUnc u_ddr3/gw3_top/i4/dll_step_base_0_s0
10.281 -0.035 tSu 1 u_ddr3/gw3_top/i4/dll_step_base_0_s0
Path Statistics:
Clock Skew: -1.041
Setup Relationship: 2.500
Logic Level: 2
Arrival Clock Path Delay: cell: 0.182, 50.276%; route: 0.180, 49.724%
Arrival Data Path Delay: cell: 0.393, 48.519%; route: 0.237, 29.259%; tC2Q: 0.180, 22.222%
Required Clock Path Delay: cell: 0.182, 50.276%; route: 0.180, 49.724%

Path 2

Path Summary:
Slack 0.579
Data Arrival Time 9.701
Data Required Time 10.281
From u_ddr3/gw3_top/i4/ddr3_dll
To u_ddr3/gw3_top/i4/dll_step_base_1_s0
Launch Clk pll/rpll_inst/CLKOUT.default_gen_clk[R]
Latch Clk u_ddr3/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
7.500 0.000 pll/rpll_inst/CLKOUT.default_gen_clk
8.529 1.029 tCL RR 1 pll/rpll_inst/CLKOUT
8.709 0.180 tNET RR 3 u_ddr3/gw3_top/i4/fclk_dhcen/CLKIN
8.891 0.182 tINS RR 63 u_ddr3/gw3_top/i4/fclk_dhcen/CLKOUT
9.071 0.180 tNET RR 8 u_ddr3/gw3_top/i4/ddr3_dll/CLKIN
9.464 0.393 tINS RF 4 u_ddr3/gw3_top/i4/ddr3_dll/STEP[1]
9.701 0.237 tNET FF 1 u_ddr3/gw3_top/i4/dll_step_base_1_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 u_ddr3/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk
10.170 0.170 tCL RR 1551 u_ddr3/gw3_top/i4/fclkdiv/CLKOUT
10.351 0.180 tNET RR 1 u_ddr3/gw3_top/i4/dll_step_base_1_s0/CLK
10.316 -0.035 tUnc u_ddr3/gw3_top/i4/dll_step_base_1_s0
10.281 -0.035 tSu 1 u_ddr3/gw3_top/i4/dll_step_base_1_s0
Path Statistics:
Clock Skew: -1.041
Setup Relationship: 2.500
Logic Level: 2
Arrival Clock Path Delay: cell: 0.182, 50.276%; route: 0.180, 49.724%
Arrival Data Path Delay: cell: 0.393, 48.519%; route: 0.237, 29.259%; tC2Q: 0.180, 22.222%
Required Clock Path Delay: cell: 0.182, 50.276%; route: 0.180, 49.724%

Path 3

Path Summary:
Slack 0.579
Data Arrival Time 9.701
Data Required Time 10.281
From u_ddr3/gw3_top/i4/ddr3_dll
To u_ddr3/gw3_top/i4/dll_step_base_2_s0
Launch Clk pll/rpll_inst/CLKOUT.default_gen_clk[R]
Latch Clk u_ddr3/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
7.500 0.000 pll/rpll_inst/CLKOUT.default_gen_clk
8.529 1.029 tCL RR 1 pll/rpll_inst/CLKOUT
8.709 0.180 tNET RR 3 u_ddr3/gw3_top/i4/fclk_dhcen/CLKIN
8.891 0.182 tINS RR 63 u_ddr3/gw3_top/i4/fclk_dhcen/CLKOUT
9.071 0.180 tNET RR 8 u_ddr3/gw3_top/i4/ddr3_dll/CLKIN
9.464 0.393 tINS RF 4 u_ddr3/gw3_top/i4/ddr3_dll/STEP[2]
9.701 0.237 tNET FF 1 u_ddr3/gw3_top/i4/dll_step_base_2_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 u_ddr3/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk
10.170 0.170 tCL RR 1551 u_ddr3/gw3_top/i4/fclkdiv/CLKOUT
10.351 0.180 tNET RR 1 u_ddr3/gw3_top/i4/dll_step_base_2_s0/CLK
10.316 -0.035 tUnc u_ddr3/gw3_top/i4/dll_step_base_2_s0
10.281 -0.035 tSu 1 u_ddr3/gw3_top/i4/dll_step_base_2_s0
Path Statistics:
Clock Skew: -1.041
Setup Relationship: 2.500
Logic Level: 2
Arrival Clock Path Delay: cell: 0.182, 50.276%; route: 0.180, 49.724%
Arrival Data Path Delay: cell: 0.393, 48.519%; route: 0.237, 29.259%; tC2Q: 0.180, 22.222%
Required Clock Path Delay: cell: 0.182, 50.276%; route: 0.180, 49.724%

Path 4

Path Summary:
Slack 0.579
Data Arrival Time 9.701
Data Required Time 10.281
From u_ddr3/gw3_top/i4/ddr3_dll
To u_ddr3/gw3_top/i4/dll_step_base_3_s0
Launch Clk pll/rpll_inst/CLKOUT.default_gen_clk[R]
Latch Clk u_ddr3/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
7.500 0.000 pll/rpll_inst/CLKOUT.default_gen_clk
8.529 1.029 tCL RR 1 pll/rpll_inst/CLKOUT
8.709 0.180 tNET RR 3 u_ddr3/gw3_top/i4/fclk_dhcen/CLKIN
8.891 0.182 tINS RR 63 u_ddr3/gw3_top/i4/fclk_dhcen/CLKOUT
9.071 0.180 tNET RR 8 u_ddr3/gw3_top/i4/ddr3_dll/CLKIN
9.464 0.393 tINS RF 4 u_ddr3/gw3_top/i4/ddr3_dll/STEP[3]
9.701 0.237 tNET FF 1 u_ddr3/gw3_top/i4/dll_step_base_3_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 u_ddr3/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk
10.170 0.170 tCL RR 1551 u_ddr3/gw3_top/i4/fclkdiv/CLKOUT
10.351 0.180 tNET RR 1 u_ddr3/gw3_top/i4/dll_step_base_3_s0/CLK
10.316 -0.035 tUnc u_ddr3/gw3_top/i4/dll_step_base_3_s0
10.281 -0.035 tSu 1 u_ddr3/gw3_top/i4/dll_step_base_3_s0
Path Statistics:
Clock Skew: -1.041
Setup Relationship: 2.500
Logic Level: 2
Arrival Clock Path Delay: cell: 0.182, 50.276%; route: 0.180, 49.724%
Arrival Data Path Delay: cell: 0.393, 48.519%; route: 0.237, 29.259%; tC2Q: 0.180, 22.222%
Required Clock Path Delay: cell: 0.182, 50.276%; route: 0.180, 49.724%

Path 5

Path Summary:
Slack 0.579
Data Arrival Time 9.701
Data Required Time 10.281
From u_ddr3/gw3_top/i4/ddr3_dll
To u_ddr3/gw3_top/i4/dll_step_base_4_s0
Launch Clk pll/rpll_inst/CLKOUT.default_gen_clk[R]
Latch Clk u_ddr3/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
7.500 0.000 pll/rpll_inst/CLKOUT.default_gen_clk
8.529 1.029 tCL RR 1 pll/rpll_inst/CLKOUT
8.709 0.180 tNET RR 3 u_ddr3/gw3_top/i4/fclk_dhcen/CLKIN
8.891 0.182 tINS RR 63 u_ddr3/gw3_top/i4/fclk_dhcen/CLKOUT
9.071 0.180 tNET RR 8 u_ddr3/gw3_top/i4/ddr3_dll/CLKIN
9.464 0.393 tINS RF 4 u_ddr3/gw3_top/i4/ddr3_dll/STEP[4]
9.701 0.237 tNET FF 1 u_ddr3/gw3_top/i4/dll_step_base_4_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 u_ddr3/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk
10.170 0.170 tCL RR 1551 u_ddr3/gw3_top/i4/fclkdiv/CLKOUT
10.351 0.180 tNET RR 1 u_ddr3/gw3_top/i4/dll_step_base_4_s0/CLK
10.316 -0.035 tUnc u_ddr3/gw3_top/i4/dll_step_base_4_s0
10.281 -0.035 tSu 1 u_ddr3/gw3_top/i4/dll_step_base_4_s0
Path Statistics:
Clock Skew: -1.041
Setup Relationship: 2.500
Logic Level: 2
Arrival Clock Path Delay: cell: 0.182, 50.276%; route: 0.180, 49.724%
Arrival Data Path Delay: cell: 0.393, 48.519%; route: 0.237, 29.259%; tC2Q: 0.180, 22.222%
Required Clock Path Delay: cell: 0.182, 50.276%; route: 0.180, 49.724%