Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | C:\Gowin\Gowin_V1.9.8\IDE\ipcore\DDR3\data\ddr3_1_4\ddr3_1_4code.v C:\Gowin\Gowin_V1.9.8\IDE\ipcore\DDR3\data\ddr3_1_4\DDR3_TOP.v |
GowinSynthesis Constraints File | --- |
GowinSynthesis Version | GowinSynthesis V1.9.8 |
Part Number | GW2A-LV18PG256C8/I7 |
Device | GW2A-18 |
Created Time | Mon Aug 30 10:54:58 2021 |
Legal Announcement | Copyright (C)2014-2021 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | DDR3_Memory_Interface_Top |
Synthesis Process | Running parser: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 59.184MB Running netlist conversion: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.067s, Peak memory usage = 59.184MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.187s, Elapsed time = 0h 0m 0.192s, Peak memory usage = 59.184MB Optimizing Phase 1: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.134s, Peak memory usage = 59.184MB Optimizing Phase 2: CPU time = 0h 0m 0.359s, Elapsed time = 0h 0m 0.369s, Peak memory usage = 59.184MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.208s, Peak memory usage = 59.184MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 59.184MB Inferring Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.031s, Peak memory usage = 59.184MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 59.184MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.25s, Elapsed time = 0h 0m 0.243s, Peak memory usage = 59.184MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.082s, Peak memory usage = 59.184MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.039s, Peak memory usage = 59.184MB Tech-Mapping Phase 3: CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s, Peak memory usage = 70.746MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.343s, Elapsed time = 0h 0m 0.359s, Peak memory usage = 70.746MB Generate output files: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.186s, Peak memory usage = 70.746MB |
Total Time and Memory Usage | CPU time = 0h 0m 6s, Elapsed time = 0h 0m 6s, Peak memory usage = 70.746MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 376 |
I/O Buf | 370 |
    IBUF | 189 |
    OBUF | 160 |
    TBUF | 2 |
    IOBUF | 16 |
    ELVDS_OBUF | 1 |
    ELVDS_IOBUF | 2 |
Register | 1305 |
    DFF | 100 |
    DFFE | 4 |
    DFFS | 1 |
    DFFR | 1 |
    DFFP | 58 |
    DFFPE | 3 |
    DFFC | 773 |
    DFFCE | 364 |
    DLCE | 1 |
LUT | 1342 |
    LUT2 | 340 |
    LUT3 | 261 |
    LUT4 | 741 |
ALU | 112 |
    ALU | 112 |
SSRAM | 111 |
    RAM16S4 | 40 |
    RAM16SDP4 | 71 |
INV | 19 |
    INV | 19 |
IOLOGIC | 100 |
    IDES8_MEM | 16 |
    OSER8 | 24 |
    OSER8_MEM | 20 |
    IODELAY | 40 |
BSRAM | 8 |
    SDPX9B | 8 |
CLOCK | 5 |
    DLL | 1 |
    CLKDIV | 1 |
    DQS | 2 |
    DHCEN | 1 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 2139(1361 LUTs, 112 ALUs, 111 SSRAMs) / 20736 | 10% |
Register | 1305 / 16173 | 8% |
  --Register as Latch | 1 / 16173 | 1% |
  --Register as FF | 1304 / 16173 | 8% |
BSRAM | 8 / 46 | 17% |
Timing
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|
memory_clk | Base | 10.000 | 100.0 | 0.000 | 5.000 | memory_clk_ibuf/I | ||
clk | Base | 10.000 | 100.0 | 0.000 | 5.000 | clk_ibuf/I | ||
ddr_rst_d | Base | 10.000 | 100.0 | 0.000 | 5.000 | gw3_top/i4/ddr_rsti_reg_2_s0/Q | ||
gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk | Generated | 40.000 | 25.0 | 0.000 | 20.000 | memory_clk_ibuf/I | memory_clk | gw3_top/i4/fclkdiv/CLKOUT |
Max Frequency Summary:
No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | memory_clk | 100.0(MHz) | 1364.3(MHz) | 1 | TOP |
2 | clk | 100.0(MHz) | 241.5(MHz) | 6 | TOP |
3 | ddr_rst_d | 100.0(MHz) | 683.1(MHz) | 2 | TOP |
4 | gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk | 25.0(MHz) | 173.6(MHz) | 8 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | 3.421 |
Data Arrival Time | 36.396 |
Data Required Time | 39.817 |
From | gw3_top/i4/u_ddr_phy_init/read_reg_3_s4 |
To | gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs |
Launch Clk | ddr_rst_d[R] |
Latch Clk | gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk[F] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
35.000 | 0.000 | ddr_rst_d | |||
35.000 | 0.000 | tCL | FF | 1185 | gw3_top/i4/ddr_rsti_reg_2_s0/Q |
35.237 | 0.237 | tNET | FF | 1 | gw3_top/i4/u_ddr_phy_init/read_reg_3_s4/G |
35.469 | 0.232 | tC2Q | FF | 8 | gw3_top/i4/u_ddr_phy_init/read_reg_3_s4/Q |
35.706 | 0.237 | tNET | FF | 1 | gw3_top/i4/u_ddr_phy_init/read_7_s0/I2 |
36.159 | 0.453 | tINS | FF | 1 | gw3_top/i4/u_ddr_phy_init/read_7_s0/F |
36.396 | 0.237 | tNET | FF | 1 | gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/READ[3] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
40.000 | 0.000 | gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk | |||
40.171 | 0.170 | tCL | RR | 1451 | gw3_top/i4/fclkdiv/CLKOUT |
40.350 | 0.180 | tNET | RR | 1 | gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/PCLK |
40.315 | -0.035 | tUnc | gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs | ||
39.816 | -0.499 | tSu | 1 | gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs |
Clock Skew: | 0.113 |
Setup Relationship: | 5.000 |
Logic Level: | 2 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.237, 100.000% |
Arrival Data Path Delay: | cell: 0.453, 39.085%; route: 0.474, 40.898%; tC2Q: 0.232, 20.017% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.237, 100.000% |
Path 2
Path Summary:Slack | 3.421 |
Data Arrival Time | 36.396 |
Data Required Time | 39.817 |
From | gw3_top/i4/u_ddr_phy_init/read_reg_3_s4 |
To | gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs |
Launch Clk | ddr_rst_d[R] |
Latch Clk | gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk[F] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
35.000 | 0.000 | ddr_rst_d | |||
35.000 | 0.000 | tCL | FF | 1185 | gw3_top/i4/ddr_rsti_reg_2_s0/Q |
35.237 | 0.237 | tNET | FF | 1 | gw3_top/i4/u_ddr_phy_init/read_reg_3_s4/G |
35.469 | 0.232 | tC2Q | FF | 8 | gw3_top/i4/u_ddr_phy_init/read_reg_3_s4/Q |
35.706 | 0.237 | tNET | FF | 1 | gw3_top/i4/u_ddr_phy_init/read_6_s0/I2 |
36.159 | 0.453 | tINS | FF | 1 | gw3_top/i4/u_ddr_phy_init/read_6_s0/F |
36.396 | 0.237 | tNET | FF | 1 | gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/READ[2] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
40.000 | 0.000 | gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk | |||
40.171 | 0.170 | tCL | RR | 1451 | gw3_top/i4/fclkdiv/CLKOUT |
40.350 | 0.180 | tNET | RR | 1 | gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/PCLK |
40.315 | -0.035 | tUnc | gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs | ||
39.816 | -0.499 | tSu | 1 | gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs |
Clock Skew: | 0.113 |
Setup Relationship: | 5.000 |
Logic Level: | 2 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.237, 100.000% |
Arrival Data Path Delay: | cell: 0.453, 39.085%; route: 0.474, 40.898%; tC2Q: 0.232, 20.017% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.237, 100.000% |
Path 3
Path Summary:Slack | 3.421 |
Data Arrival Time | 36.396 |
Data Required Time | 39.817 |
From | gw3_top/i4/u_ddr_phy_init/read_reg_3_s4 |
To | gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs |
Launch Clk | ddr_rst_d[R] |
Latch Clk | gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk[F] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
35.000 | 0.000 | ddr_rst_d | |||
35.000 | 0.000 | tCL | FF | 1185 | gw3_top/i4/ddr_rsti_reg_2_s0/Q |
35.237 | 0.237 | tNET | FF | 1 | gw3_top/i4/u_ddr_phy_init/read_reg_3_s4/G |
35.469 | 0.232 | tC2Q | FF | 8 | gw3_top/i4/u_ddr_phy_init/read_reg_3_s4/Q |
35.706 | 0.237 | tNET | FF | 1 | gw3_top/i4/u_ddr_phy_init/read_5_s0/I2 |
36.159 | 0.453 | tINS | FF | 1 | gw3_top/i4/u_ddr_phy_init/read_5_s0/F |
36.396 | 0.237 | tNET | FF | 1 | gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/READ[1] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
40.000 | 0.000 | gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk | |||
40.171 | 0.170 | tCL | RR | 1451 | gw3_top/i4/fclkdiv/CLKOUT |
40.350 | 0.180 | tNET | RR | 1 | gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/PCLK |
40.315 | -0.035 | tUnc | gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs | ||
39.816 | -0.499 | tSu | 1 | gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs |
Clock Skew: | 0.113 |
Setup Relationship: | 5.000 |
Logic Level: | 2 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.237, 100.000% |
Arrival Data Path Delay: | cell: 0.453, 39.085%; route: 0.474, 40.898%; tC2Q: 0.232, 20.017% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.237, 100.000% |
Path 4
Path Summary:Slack | 3.421 |
Data Arrival Time | 36.396 |
Data Required Time | 39.817 |
From | gw3_top/i4/u_ddr_phy_init/read_reg_3_s4 |
To | gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs |
Launch Clk | ddr_rst_d[R] |
Latch Clk | gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk[F] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
35.000 | 0.000 | ddr_rst_d | |||
35.000 | 0.000 | tCL | FF | 1185 | gw3_top/i4/ddr_rsti_reg_2_s0/Q |
35.237 | 0.237 | tNET | FF | 1 | gw3_top/i4/u_ddr_phy_init/read_reg_3_s4/G |
35.469 | 0.232 | tC2Q | FF | 8 | gw3_top/i4/u_ddr_phy_init/read_reg_3_s4/Q |
35.706 | 0.237 | tNET | FF | 1 | gw3_top/i4/u_ddr_phy_init/read_4_s0/I2 |
36.159 | 0.453 | tINS | FF | 1 | gw3_top/i4/u_ddr_phy_init/read_4_s0/F |
36.396 | 0.237 | tNET | FF | 1 | gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/READ[0] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
40.000 | 0.000 | gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk | |||
40.171 | 0.170 | tCL | RR | 1451 | gw3_top/i4/fclkdiv/CLKOUT |
40.350 | 0.180 | tNET | RR | 1 | gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/PCLK |
40.315 | -0.035 | tUnc | gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs | ||
39.816 | -0.499 | tSu | 1 | gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs |
Clock Skew: | 0.113 |
Setup Relationship: | 5.000 |
Logic Level: | 2 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.237, 100.000% |
Arrival Data Path Delay: | cell: 0.453, 39.085%; route: 0.474, 40.898%; tC2Q: 0.232, 20.017% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.237, 100.000% |
Path 5
Path Summary:Slack | 3.421 |
Data Arrival Time | 36.396 |
Data Required Time | 39.817 |
From | gw3_top/i4/u_ddr_phy_init/read_reg_3_s4 |
To | gw3_top/i4/u_ddr_phy_wd/data_lane_gen[0].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs |
Launch Clk | ddr_rst_d[R] |
Latch Clk | gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk[F] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
35.000 | 0.000 | ddr_rst_d | |||
35.000 | 0.000 | tCL | FF | 1185 | gw3_top/i4/ddr_rsti_reg_2_s0/Q |
35.237 | 0.237 | tNET | FF | 1 | gw3_top/i4/u_ddr_phy_init/read_reg_3_s4/G |
35.469 | 0.232 | tC2Q | FF | 8 | gw3_top/i4/u_ddr_phy_init/read_reg_3_s4/Q |
35.706 | 0.237 | tNET | FF | 1 | gw3_top/i4/u_ddr_phy_init/read_3_s0/I2 |
36.159 | 0.453 | tINS | FF | 1 | gw3_top/i4/u_ddr_phy_init/read_3_s0/F |
36.396 | 0.237 | tNET | FF | 1 | gw3_top/i4/u_ddr_phy_wd/data_lane_gen[0].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/READ[3] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
40.000 | 0.000 | gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk | |||
40.171 | 0.170 | tCL | RR | 1451 | gw3_top/i4/fclkdiv/CLKOUT |
40.350 | 0.180 | tNET | RR | 1 | gw3_top/i4/u_ddr_phy_wd/data_lane_gen[0].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/PCLK |
40.315 | -0.035 | tUnc | gw3_top/i4/u_ddr_phy_wd/data_lane_gen[0].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs | ||
39.816 | -0.499 | tSu | 1 | gw3_top/i4/u_ddr_phy_wd/data_lane_gen[0].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs |
Clock Skew: | 0.113 |
Setup Relationship: | 5.000 |
Logic Level: | 2 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.237, 100.000% |
Arrival Data Path Delay: | cell: 0.453, 39.085%; route: 0.474, 40.898%; tC2Q: 0.232, 20.017% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.237, 100.000% |