Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Program Files\Gowin\Gowin_V1.9.8\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v
D:\Program Files\Gowin\Gowin_V1.9.8\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v
D:\Program Files\Gowin\Gowin_V1.9.8\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v
D:\Program Files\Gowin\Gowin_V1.9.8\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v
D:\Program Files\Gowin\Gowin_V1.9.8\IDE\data\ipcores\GAO\GW_CON\gw_con_top.v
D:\Program Files\Gowin\Gowin_V1.9.8\IDE\data\ipcores\gw_jtag.v
C:\Users\boxian\Desktop\ref_design\Gowin_DDR3_Memory_Interface_refDesign (1)\Gowin_DDR3_Memory_Interface_refDesign\DDR3_MC_PHY_1vs2_2A55K\project\impl\gao\gw_gao_top.v
GowinSynthesis Constraints File ---
GowinSynthesis Version GowinSynthesis V1.9.8
Part Number GW2A-LV55PG484C8/I7
Device GW2A-55
Created Time Fri Aug 27 09:21:11 2021
Legal Announcement Copyright (C)2014-2021 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module gw_gao
Synthesis Process Running parser:
    CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 37.605MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 37.605MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.05s, Peak memory usage = 37.605MB
    Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.023s, Peak memory usage = 37.605MB
    Optimizing Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.051s, Peak memory usage = 37.605MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 37.605MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 37.605MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 37.605MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 37.605MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.029s, Peak memory usage = 37.605MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 37.605MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 37.605MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 52.391MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.059s, Peak memory usage = 52.391MB
Generate output files:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.037s, Peak memory usage = 52.391MB
Total Time and Memory Usage CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 52.391MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 70
I/O Buf 70
    IBUF 69
    OBUF 1
Register 480
    DFF 130
    DFFP 1
    DFFPE 33
    DFFC 24
    DFFCE 286
    DFFNP 2
    DFFNC 4
LUT 385
    LUT2 25
    LUT3 79
    LUT4 281
MUX 1
    MUX16 1
ALU 10
    ALU 10
INV 2
    INV 2
BSRAM 4
    SDPX9B 4
Black Box 1
    GW_JTAG 1

Resource Utilization Summary

Resource Usage Utilization
Logic 405(395 LUTs, 10 ALUs) / 54720 1%
Register 480 / 41997 1%
  --Register as Latch 0 / 41997 0%
  --Register as FF 480 / 41997 1%
BSRAM 4 / 140 3%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
clk_x1 Base 10.000 100.0 0.000 5.000 clk_x1_ibuf/I

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk_x1 100.0(MHz) 286.1(MHz) 5 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 6.505
Data Arrival Time 4.322
Data Required Time 10.828
From u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
To u_la0_top/u_ao_mem_ctrl/capture_loop_s1
Launch Clk clk_x1[R]
Latch Clk clk_x1[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1 clk_x1_ibuf/I
0.683 0.683 tINS RR 183 clk_x1_ibuf/O
0.863 0.180 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK
1.095 0.232 tC2Q RF 7 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/Q
1.332 0.237 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n469_s8/I0
1.849 0.517 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n469_s8/F
2.086 0.237 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n469_s6/I0
2.602 0.517 tINS FF 2 u_la0_top/u_ao_mem_ctrl/n469_s6/F
2.839 0.237 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n469_s4/I0
3.356 0.517 tINS FF 10 u_la0_top/u_ao_mem_ctrl/n469_s4/F
3.593 0.237 tNET FF 1 u_la0_top/u_ao_mem_ctrl/capture_loop_s4/I0
4.142 0.549 tINS FR 1 u_la0_top/u_ao_mem_ctrl/capture_loop_s4/F
4.322 0.180 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_x1
10.000 0.000 tCL RR 1 clk_x1_ibuf/I
10.682 0.683 tINS RR 183 clk_x1_ibuf/O
10.863 0.180 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK
10.828 -0.035 tSu 1 u_la0_top/u_ao_mem_ctrl/capture_loop_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 2.100, 60.694%; route: 1.128, 32.601%; tC2Q: 0.232, 6.705%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 2

Path Summary:
Slack 6.512
Data Arrival Time 4.316
Data Required Time 10.828
From u_la0_top/u_ao_mem_ctrl/capture_length_1_s1
To u_la0_top/u_ao_mem_ctrl/capture_length_8_s1
Launch Clk clk_x1[R]
Latch Clk clk_x1[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1 clk_x1_ibuf/I
0.683 0.683 tINS RR 183 clk_x1_ibuf/O
0.863 0.180 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLK
1.095 0.232 tC2Q RF 5 u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/Q
1.332 0.237 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n390_s1/I1
1.887 0.555 tINS FF 4 u_la0_top/u_ao_mem_ctrl/n390_s1/F
2.124 0.237 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n387_s1/I3
2.495 0.371 tINS FF 3 u_la0_top/u_ao_mem_ctrl/n387_s1/F
2.732 0.237 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n386_s1/I1
3.287 0.555 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n386_s1/F
3.524 0.237 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n386_s0/I1
4.079 0.555 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n386_s0/F
4.316 0.237 tNET FF 1 u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_x1
10.000 0.000 tCL RR 1 clk_x1_ibuf/I
10.682 0.683 tINS RR 183 clk_x1_ibuf/O
10.863 0.180 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLK
10.828 -0.035 tSu 1 u_la0_top/u_ao_mem_ctrl/capture_length_8_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 2.036, 58.963%; route: 1.185, 34.318%; tC2Q: 0.232, 6.719%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 3

Path Summary:
Slack 6.532
Data Arrival Time 4.296
Data Required Time 10.828
From u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
Launch Clk clk_x1[R]
Latch Clk clk_x1[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1 clk_x1_ibuf/I
0.683 0.683 tINS RR 183 clk_x1_ibuf/O
0.863 0.180 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
1.095 0.232 tC2Q RF 9 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/Q
1.332 0.237 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n474_s2/I1
1.887 0.555 tINS FF 3 u_la0_top/u_ao_mem_ctrl/n474_s2/F
2.124 0.237 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n472_s2/I2
2.577 0.453 tINS FF 4 u_la0_top/u_ao_mem_ctrl/n472_s2/F
2.814 0.237 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n471_s2/I1
3.369 0.555 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n471_s2/F
3.606 0.237 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n471_s1/I2
4.059 0.453 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n471_s1/F
4.296 0.237 tNET FF 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_x1
10.000 0.000 tCL RR 1 clk_x1_ibuf/I
10.682 0.683 tINS RR 183 clk_x1_ibuf/O
10.863 0.180 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK
10.828 -0.035 tSu 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 2.016, 58.724%; route: 1.185, 34.518%; tC2Q: 0.232, 6.758%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 4

Path Summary:
Slack 6.532
Data Arrival Time 4.296
Data Required Time 10.828
From u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
Launch Clk clk_x1[R]
Latch Clk clk_x1[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1 clk_x1_ibuf/I
0.683 0.683 tINS RR 183 clk_x1_ibuf/O
0.863 0.180 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
1.095 0.232 tC2Q RF 9 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/Q
1.332 0.237 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n474_s2/I1
1.887 0.555 tINS FF 3 u_la0_top/u_ao_mem_ctrl/n474_s2/F
2.124 0.237 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n472_s2/I2
2.577 0.453 tINS FF 4 u_la0_top/u_ao_mem_ctrl/n472_s2/F
2.814 0.237 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n470_s3/I2
3.267 0.453 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n470_s3/F
3.504 0.237 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n470_s1/I1
4.059 0.555 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n470_s1/F
4.296 0.237 tNET FF 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_x1
10.000 0.000 tCL RR 1 clk_x1_ibuf/I
10.682 0.683 tINS RR 183 clk_x1_ibuf/O
10.863 0.180 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK
10.828 -0.035 tSu 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 2.016, 58.724%; route: 1.185, 34.518%; tC2Q: 0.232, 6.758%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 5

Path Summary:
Slack 6.544
Data Arrival Time 4.283
Data Required Time 10.828
From u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Launch Clk clk_x1[R]
Latch Clk clk_x1[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1 clk_x1_ibuf/I
0.683 0.683 tINS RR 183 clk_x1_ibuf/O
0.863 0.180 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK
1.095 0.232 tC2Q RF 7 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/Q
1.332 0.237 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n469_s8/I0
1.849 0.517 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n469_s8/F
2.086 0.237 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n469_s6/I0
2.602 0.517 tINS FF 2 u_la0_top/u_ao_mem_ctrl/n469_s6/F
2.839 0.237 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n469_s4/I0
3.356 0.517 tINS FF 10 u_la0_top/u_ao_mem_ctrl/n469_s4/F
3.593 0.237 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n477_s1/I2
4.046 0.453 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n477_s1/F
4.283 0.237 tNET FF 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_x1
10.000 0.000 tCL RR 1 clk_x1_ibuf/I
10.682 0.683 tINS RR 183 clk_x1_ibuf/O
10.863 0.180 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
10.828 -0.035 tSu 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 2.004, 58.579%; route: 1.185, 34.639%; tC2Q: 0.232, 6.782%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%