Hierarchy Module Resource

MODULE NAME REG NUMBER ALU NUMBER LUT NUMBER DSP NUMBER BSRAM NUMBER SSRAM NUMBER
ddr3_syn_top (E:/myWork/IP/releaseVerify/new/RefDesign/Memory_Control/DDR3/Gowin_DDR3_Memory_Interface_refDesign/DDR3_MC_PHY_1vs4_2A18K/project/src/ddr3_syn_top.v) 26 - 54 - - -
    |--u5 (E:/myWork/IP/releaseVerify/new/RefDesign/Memory_Control/DDR3/Gowin_DDR3_Memory_Interface_refDesign/DDR3_MC_PHY_1vs4_2A18K/project/src/ddr3_syn_top.v) 23 19 9 - - -
    |--pll (E:/myWork/IP/releaseVerify/new/RefDesign/Memory_Control/DDR3/Gowin_DDR3_Memory_Interface_refDesign/DDR3_MC_PHY_1vs4_2A18K/project/src/ddr3_syn_top.v) - - - - - -
    |--u_rd (E:/myWork/IP/releaseVerify/new/RefDesign/Memory_Control/DDR3/Gowin_DDR3_Memory_Interface_refDesign/DDR3_MC_PHY_1vs4_2A18K/project/src/ddr3_syn_top.v) 81 22 214 - 4 -
    |--u_ddr3 (E:/myWork/IP/releaseVerify/new/RefDesign/Memory_Control/DDR3/Gowin_DDR3_Memory_Interface_refDesign/DDR3_MC_PHY_1vs4_2A18K/project/src/ddr3_syn_top.v) 1297 112 1360 - 8 110