Hierarchy Module Resource
MODULE NAME |
REG NUMBER |
ALU NUMBER |
LUT NUMBER |
DSP NUMBER |
BSRAM NUMBER |
SSRAM NUMBER |
ddr3_syn_top (E:/myWork/IP/releaseVerify/new/RefDesign/Memory_Control/DDR3/Gowin_DDR3_Memory_Interface_refDesign/DDR3_MC_PHY_1vs2_2A55K/project/src/ddr3_syn_top.v) |
- |
- |
2 |
- |
- |
- |
    |--u2
(E:/myWork/IP/releaseVerify/new/RefDesign/Memory_Control/DDR3/Gowin_DDR3_Memory_Interface_refDesign/DDR3_MC_PHY_1vs2_2A55K/project/src/ddr3_syn_top.v) |
23 |
- |
39 |
- |
- |
- |
    |--u3
(E:/myWork/IP/releaseVerify/new/RefDesign/Memory_Control/DDR3/Gowin_DDR3_Memory_Interface_refDesign/DDR3_MC_PHY_1vs2_2A55K/project/src/ddr3_syn_top.v) |
23 |
- |
36 |
- |
- |
- |
    |--u4
(E:/myWork/IP/releaseVerify/new/RefDesign/Memory_Control/DDR3/Gowin_DDR3_Memory_Interface_refDesign/DDR3_MC_PHY_1vs2_2A55K/project/src/ddr3_syn_top.v) |
23 |
- |
38 |
- |
- |
- |
    |--u5
(E:/myWork/IP/releaseVerify/new/RefDesign/Memory_Control/DDR3/Gowin_DDR3_Memory_Interface_refDesign/DDR3_MC_PHY_1vs2_2A55K/project/src/ddr3_syn_top.v) |
23 |
19 |
9 |
- |
- |
- |
    |--u_rd
(E:/myWork/IP/releaseVerify/new/RefDesign/Memory_Control/DDR3/Gowin_DDR3_Memory_Interface_refDesign/DDR3_MC_PHY_1vs2_2A55K/project/src/ddr3_syn_top.v) |
161 |
9 |
266 |
- |
2 |
- |
    |--u_ddr3
(E:/myWork/IP/releaseVerify/new/RefDesign/Memory_Control/DDR3/Gowin_DDR3_Memory_Interface_refDesign/DDR3_MC_PHY_1vs2_2A55K/project/src/ddr3_syn_top.v) |
1137 |
85 |
1177 |
- |
4 |
48 |