Synthesis Messages

Report Title GowinSynthesis Report
Design File E:\myWork\IP\releaseVerify\new\RefDesign\Memory_Control\DDR3\Gowin_DDR3_Memory_Interface_refDesign\DDR3_MC_PHY_1vs2_2A55K\project\src\DDR3_test_rst.v
E:\myWork\IP\releaseVerify\new\RefDesign\Memory_Control\DDR3\Gowin_DDR3_Memory_Interface_refDesign\DDR3_MC_PHY_1vs2_2A55K\project\src\ddr3_syn_top.v
E:\myWork\IP\releaseVerify\new\RefDesign\Memory_Control\DDR3\Gowin_DDR3_Memory_Interface_refDesign\DDR3_MC_PHY_1vs2_2A55K\project\src\key_debounce.v
E:\myWork\IP\releaseVerify\new\RefDesign\Memory_Control\DDR3\Gowin_DDR3_Memory_Interface_refDesign\DDR3_MC_PHY_1vs2_2A55K\project\src\ddr3_memory_interface\ddr3_memory_interface.v
GowinSynthesis Constraints File ---
GowinSynthesis Version GowinSynthesis V1.9.8
Part Number GW2A-LV55PG484C8/I7
Device GW2A-55
Created Time Mon Aug 30 10:01:08 2021
Legal Announcement Copyright (C)2014-2021 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module ddr3_syn_top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.796s, Elapsed time = 0h 0m 0.916s, Peak memory usage = 385.313MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.087s, Peak memory usage = 385.313MB
    Optimizing Phase 1: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.081s, Peak memory usage = 385.313MB
    Optimizing Phase 2: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.112s, Peak memory usage = 385.313MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.044s, Peak memory usage = 385.313MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 385.313MB
    Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 385.313MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 385.313MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.132s, Peak memory usage = 385.313MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.033s, Peak memory usage = 385.313MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.022s, Peak memory usage = 385.313MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 385.313MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.102s, Peak memory usage = 385.313MB
Generate output files:
    CPU time = 0h 0m 0.187s, Elapsed time = 0h 0m 0.177s, Peak memory usage = 385.313MB
Total Time and Memory Usage CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 385.313MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 63
I/O Buf 60
    IBUF 5
    OBUF 34
    TBUF 2
    IOBUF 16
    ELVDS_OBUF 1
    ELVDS_IOBUF 2
Register 1390
    DFF 123
    DFFE 79
    DFFS 5
    DFFSE 26
    DFFR 46
    DFFRE 46
    DFFP 56
    DFFPE 10
    DFFC 733
    DFFCE 266
LUT 1538
    LUT2 369
    LUT3 309
    LUT4 860
ALU 113
    ALU 113
SSRAM 48
    RAM16S4 8
    RAM16SDP4 40
INV 29
    INV 29
IOLOGIC 76
    IDES4_MEM 16
    OSER4 24
    OSER4_MEM 20
    IODELAY 16
BSRAM 6
    SDPX9B 6
CLOCK 6
    PLL 1
    DLL 1
    CLKDIV 1
    DQS 2
    DHCEN 1

Resource Utilization Summary

Resource Usage Utilization
Logic 1968(1567 LUTs, 113 ALUs, 48 SSRAMs) / 54720 4%
Register 1390 / 41997 3%
  --Register as Latch 0 / 41997 0%
  --Register as FF 1390 / 41997 3%
BSRAM 6 / 140 4%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
clk Base 20.000 50.0 0.000 10.000 clk_ibuf/I
u_ddr3/gw3mc_top/u_ddr_phy_top/u_PLL/CLKOUT.default_gen_clk Generated 5.000 200.0 0.000 2.500 clk_ibuf/I clk u_ddr3/gw3mc_top/u_ddr_phy_top/u_PLL/CLKOUT
u_ddr3/gw3mc_top/u_ddr_phy_top/u_PLL/CLKOUTP.default_gen_clk Generated 5.000 200.0 2.500 0.000 clk_ibuf/I clk u_ddr3/gw3mc_top/u_ddr_phy_top/u_PLL/CLKOUTP
u_ddr3/gw3mc_top/u_ddr_phy_top/u_PLL/CLKOUTD.default_gen_clk Generated 10.000 100.0 0.000 5.000 clk_ibuf/I clk u_ddr3/gw3mc_top/u_ddr_phy_top/u_PLL/CLKOUTD
u_ddr3/gw3mc_top/u_ddr_phy_top/u_PLL/CLKOUTD3.default_gen_clk Generated 15.000 66.7 0.000 7.500 clk_ibuf/I clk u_ddr3/gw3mc_top/u_ddr_phy_top/u_PLL/CLKOUTD3
u_ddr3/gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT.default_gen_clk Generated 10.000 100.0 0.000 5.000 u_ddr3/gw3mc_top/u_ddr_phy_top/u_PLL/CLKOUT u_ddr3/gw3mc_top/u_ddr_phy_top/u_PLL/CLKOUT.default_gen_clk u_ddr3/gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 50.0(MHz) 213.5(MHz) 7 TOP
2 u_ddr3/gw3mc_top/u_ddr_phy_top/u_PLL/CLKOUT.default_gen_clk 200.0(MHz) 1364.3(MHz) 1 TOP
3 u_ddr3/gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT.default_gen_clk 100.0(MHz) 165.7(MHz) 8 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack -1.806
Data Arrival Time 5.474
Data Required Time 3.667
From u_ddr3/gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_mem_sync/dll_rst_s0
To u_ddr3/gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Launch Clk clk[F]
Latch Clk u_ddr3/gw3mc_top/u_ddr_phy_top/u_PLL/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.683 0.683 tINS RR 126 clk_ibuf/O
0.863 0.180 tNET RR 1 u_ddr3/gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_mem_sync/dll_rst_s0/CLK
1.095 0.232 tC2Q RF 4 u_ddr3/gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_mem_sync/dll_rst_s0/Q
1.332 0.237 tNET FF 1 u_ddr3/gw3mc_top/u_ddr_phy_top/n303_s1/I1
1.887 0.555 tINS FF 5 u_ddr3/gw3mc_top/u_ddr_phy_top/n303_s1/F
2.124 0.237 tNET FF 1 u_ddr3/gw3mc_top/u_ddr_phy_top/u_ddr_init/n1813_s4/I2
2.577 0.453 tINS FF 3 u_ddr3/gw3mc_top/u_ddr_phy_top/u_ddr_init/n1813_s4/F
2.814 0.237 tNET FF 1 u_ddr3/gw3mc_top/u_ddr_phy_top/u_ddr_init/n1813_s1/I2
3.267 0.453 tINS FF 1 u_ddr3/gw3mc_top/u_ddr_phy_top/u_ddr_init/n1813_s1/F
3.504 0.237 tNET FF 1 u_ddr3/gw3mc_top/u_ddr_phy_top/u_ddr_init/read_cal_next_state.READ_CAL_PRECHARGE_s17/I3
3.875 0.371 tINS FF 2 u_ddr3/gw3mc_top/u_ddr_phy_top/u_ddr_init/read_cal_next_state.READ_CAL_PRECHARGE_s17/F
4.112 0.237 tNET FF 1 u_ddr3/gw3mc_top/u_ddr_phy_top/u_ddr_init/read_cal_next_state.READ_CAL_RSEL_ADJ_s15/I0
4.629 0.517 tINS FF 3 u_ddr3/gw3mc_top/u_ddr_phy_top/u_ddr_init/read_cal_next_state.READ_CAL_RSEL_ADJ_s15/F
4.866 0.237 tNET FF 1 u_ddr3/gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/pause_en_s0/I3
5.237 0.371 tINS FF 2 u_ddr3/gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/pause_en_s0/F
5.474 0.237 tNET FF 1 u_ddr3/gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
2.500 0.000 u_ddr3/gw3mc_top/u_ddr_phy_top/u_PLL/CLKOUT.default_gen_clk
3.529 1.029 tCL FF 1 u_ddr3/gw3mc_top/u_ddr_phy_top/u_PLL/CLKOUT
3.766 0.237 tNET FF 3 u_ddr3/gw3mc_top/u_ddr_phy_top/u_dhcen/CLKIN
3.952 0.186 tINS FF 64 u_ddr3/gw3mc_top/u_ddr_phy_top/u_dhcen/CLKOUT
4.189 0.237 tNET FF 1 u_ddr3/gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
4.154 -0.035 tUnc u_ddr3/gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
3.667 -0.487 tSu 1 u_ddr3/gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Path Statistics:
Clock Skew: 0.827
Setup Relationship: 2.500
Logic Level: 7
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 2.720, 58.990%; route: 1.659, 35.979%; tC2Q: 0.232, 5.031%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 2

Path Summary:
Slack -1.806
Data Arrival Time 5.474
Data Required Time 3.667
From u_ddr3/gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_mem_sync/dll_rst_s0
To u_ddr3/gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Launch Clk clk[F]
Latch Clk u_ddr3/gw3mc_top/u_ddr_phy_top/u_PLL/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.683 0.683 tINS RR 126 clk_ibuf/O
0.863 0.180 tNET RR 1 u_ddr3/gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_mem_sync/dll_rst_s0/CLK
1.095 0.232 tC2Q RF 4 u_ddr3/gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_mem_sync/dll_rst_s0/Q
1.332 0.237 tNET FF 1 u_ddr3/gw3mc_top/u_ddr_phy_top/n303_s1/I1
1.887 0.555 tINS FF 5 u_ddr3/gw3mc_top/u_ddr_phy_top/n303_s1/F
2.124 0.237 tNET FF 1 u_ddr3/gw3mc_top/u_ddr_phy_top/u_ddr_init/n1813_s4/I2
2.577 0.453 tINS FF 3 u_ddr3/gw3mc_top/u_ddr_phy_top/u_ddr_init/n1813_s4/F
2.814 0.237 tNET FF 1 u_ddr3/gw3mc_top/u_ddr_phy_top/u_ddr_init/n1813_s1/I2
3.267 0.453 tINS FF 1 u_ddr3/gw3mc_top/u_ddr_phy_top/u_ddr_init/n1813_s1/F
3.504 0.237 tNET FF 1 u_ddr3/gw3mc_top/u_ddr_phy_top/u_ddr_init/read_cal_next_state.READ_CAL_PRECHARGE_s17/I3
3.875 0.371 tINS FF 2 u_ddr3/gw3mc_top/u_ddr_phy_top/u_ddr_init/read_cal_next_state.READ_CAL_PRECHARGE_s17/F
4.112 0.237 tNET FF 1 u_ddr3/gw3mc_top/u_ddr_phy_top/u_ddr_init/read_cal_next_state.READ_CAL_RSEL_ADJ_s15/I0
4.629 0.517 tINS FF 3 u_ddr3/gw3mc_top/u_ddr_phy_top/u_ddr_init/read_cal_next_state.READ_CAL_RSEL_ADJ_s15/F
4.866 0.237 tNET FF 1 u_ddr3/gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/pause_en_s0/I3
5.237 0.371 tINS FF 2 u_ddr3/gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/pause_en_s0/F
5.474 0.237 tNET FF 1 u_ddr3/gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
2.500 0.000 u_ddr3/gw3mc_top/u_ddr_phy_top/u_PLL/CLKOUT.default_gen_clk
3.529 1.029 tCL FF 1 u_ddr3/gw3mc_top/u_ddr_phy_top/u_PLL/CLKOUT
3.766 0.237 tNET FF 3 u_ddr3/gw3mc_top/u_ddr_phy_top/u_dhcen/CLKIN
3.952 0.186 tINS FF 64 u_ddr3/gw3mc_top/u_ddr_phy_top/u_dhcen/CLKOUT
4.189 0.237 tNET FF 1 u_ddr3/gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
4.154 -0.035 tUnc u_ddr3/gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
3.667 -0.487 tSu 1 u_ddr3/gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Path Statistics:
Clock Skew: 0.827
Setup Relationship: 2.500
Logic Level: 7
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 2.720, 58.990%; route: 1.659, 35.979%; tC2Q: 0.232, 5.031%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 3

Path Summary:
Slack 2.214
Data Arrival Time 1.331
Data Required Time 3.545
From u_ddr3/gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_mem_sync/cs_memsync_4_s0
To u_ddr3/gw3mc_top/u_ddr_phy_top/u_dhcen
Launch Clk clk[F]
Latch Clk u_ddr3/gw3mc_top/u_ddr_phy_top/u_PLL/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.683 0.683 tINS RR 126 clk_ibuf/O
0.863 0.180 tNET RR 1 u_ddr3/gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_mem_sync/cs_memsync_4_s0/CLK
1.095 0.232 tC2Q RF 7 u_ddr3/gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_mem_sync/cs_memsync_4_s0/Q
1.332 0.237 tNET FF 1 u_ddr3/gw3mc_top/u_ddr_phy_top/u_dhcen/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
2.500 0.000 u_ddr3/gw3mc_top/u_ddr_phy_top/u_PLL/CLKOUT.default_gen_clk
3.529 1.029 tCL FF 1 u_ddr3/gw3mc_top/u_ddr_phy_top/u_PLL/CLKOUT
3.766 0.237 tNET FF 3 u_ddr3/gw3mc_top/u_ddr_phy_top/u_dhcen/CLKIN
3.731 -0.035 tUnc u_ddr3/gw3mc_top/u_ddr_phy_top/u_dhcen
3.545 -0.186 tSu 1 u_ddr3/gw3mc_top/u_ddr_phy_top/u_dhcen
Path Statistics:
Clock Skew: 0.404
Setup Relationship: 2.500
Logic Level: 1
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 0.000, 0.000%; route: 0.237, 50.533%; tC2Q: 0.232, 49.467%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 4

Path Summary:
Slack 3.964
Data Arrival Time 6.352
Data Required Time 10.316
From u_ddr3/gw3mc_top/u_gwmc_top/gwmc_bank_ctrl/bank_acted_3_s1
To u_ddr3/gw3mc_top/u_gwmc_top/gwmc_bank_ctrl/idle_s0
Launch Clk u_ddr3/gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT.default_gen_clk[R]
Latch Clk u_ddr3/gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 u_ddr3/gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT.default_gen_clk
0.170 0.170 tCL RR 1387 u_ddr3/gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.350 0.180 tNET RR 1 u_ddr3/gw3mc_top/u_gwmc_top/gwmc_bank_ctrl/bank_acted_3_s1/CLK
0.582 0.232 tC2Q RF 1 u_ddr3/gw3mc_top/u_gwmc_top/gwmc_bank_ctrl/bank_acted_3_s1/Q
0.819 0.237 tNET FF 1 u_ddr3/gw3mc_top/u_gwmc_top/gwmc_bank_ctrl/n245_s25/I1
1.375 0.555 tINS FF 1 u_ddr3/gw3mc_top/u_gwmc_top/gwmc_bank_ctrl/n245_s25/F
1.612 0.237 tNET FF 1 u_ddr3/gw3mc_top/u_gwmc_top/gwmc_bank_ctrl/n245_s22/I1
1.714 0.103 tINS FF 1 u_ddr3/gw3mc_top/u_gwmc_top/gwmc_bank_ctrl/n245_s22/O
1.951 0.237 tNET FF 1 u_ddr3/gw3mc_top/u_gwmc_top/gwmc_bank_ctrl/n245_s21/I0
2.054 0.103 tINS FF 2 u_ddr3/gw3mc_top/u_gwmc_top/gwmc_bank_ctrl/n245_s21/O
2.291 0.237 tNET FF 1 u_ddr3/gw3mc_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate_16_s33/I1
2.846 0.555 tINS FF 2 u_ddr3/gw3mc_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate_16_s33/F
3.083 0.237 tNET FF 1 u_ddr3/gw3mc_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate_16_s31/I3
3.454 0.371 tINS FF 2 u_ddr3/gw3mc_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate_16_s31/F
3.691 0.237 tNET FF 1 u_ddr3/gw3mc_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate_4_s33/I3
4.063 0.371 tINS FF 1 u_ddr3/gw3mc_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate_4_s33/F
4.299 0.237 tNET FF 1 u_ddr3/gw3mc_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate_4_s31/I3
4.670 0.371 tINS FF 2 u_ddr3/gw3mc_top/u_gwmc_top/gwmc_bank_ctrl/gwmc_nstate_4_s31/F
4.907 0.237 tNET FF 1 u_ddr3/gw3mc_top/u_gwmc_top/gwmc_bank_ctrl/n1155_s3/I0
5.424 0.517 tINS FF 1 u_ddr3/gw3mc_top/u_gwmc_top/gwmc_bank_ctrl/n1155_s3/F
5.661 0.237 tNET FF 1 u_ddr3/gw3mc_top/u_gwmc_top/gwmc_bank_ctrl/n1155_s0/I2
6.115 0.453 tINS FF 1 u_ddr3/gw3mc_top/u_gwmc_top/gwmc_bank_ctrl/n1155_s0/F
6.352 0.237 tNET FF 1 u_ddr3/gw3mc_top/u_gwmc_top/gwmc_bank_ctrl/idle_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 u_ddr3/gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT.default_gen_clk
10.170 0.170 tCL RR 1387 u_ddr3/gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
10.351 0.180 tNET RR 1 u_ddr3/gw3mc_top/u_gwmc_top/gwmc_bank_ctrl/idle_s0/CLK
10.316 -0.035 tSu 1 u_ddr3/gw3mc_top/u_gwmc_top/gwmc_bank_ctrl/idle_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 8
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay: cell: 3.399, 56.641%; route: 2.370, 39.493%; tC2Q: 0.232, 3.866%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.180, 100.000%

Path 5

Path Summary:
Slack 4.267
Data Arrival Time 2.304
Data Required Time 6.571
From u_ddr3/gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To u_ddr3/gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides4
Launch Clk u_ddr3/gw3mc_top/u_ddr_phy_top/u_PLL/CLKOUT.default_gen_clk[R]
Latch Clk u_ddr3/gw3mc_top/u_ddr_phy_top/u_PLL/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 u_ddr3/gw3mc_top/u_ddr_phy_top/u_PLL/CLKOUT.default_gen_clk
1.029 1.029 tCL RR 1 u_ddr3/gw3mc_top/u_ddr_phy_top/u_PLL/CLKOUT
1.209 0.180 tNET RR 3 u_ddr3/gw3mc_top/u_ddr_phy_top/u_dhcen/CLKIN
1.391 0.182 tINS RR 64 u_ddr3/gw3mc_top/u_ddr_phy_top/u_dhcen/CLKOUT
1.571 0.180 tNET RR 5 u_ddr3/gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
2.067 0.496 tC2Q RF 8 u_ddr3/gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2]
2.304 0.237 tNET FF 1 u_ddr3/gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides4/RADDR[2]
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
5.000 0.000 u_ddr3/gw3mc_top/u_ddr_phy_top/u_PLL/CLKOUT.default_gen_clk
6.029 1.029 tCL RR 1 u_ddr3/gw3mc_top/u_ddr_phy_top/u_PLL/CLKOUT
6.209 0.180 tNET RR 3 u_ddr3/gw3mc_top/u_ddr_phy_top/u_dhcen/CLKIN
6.391 0.182 tINS RR 64 u_ddr3/gw3mc_top/u_ddr_phy_top/u_dhcen/CLKOUT
6.571 0.180 tNET RR 1 u_ddr3/gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides4/FCLK
6.571 0.000 tSu 1 u_ddr3/gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides4
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 5.000
Logic Level: 1
Arrival Clock Path Delay: cell: 0.182, 33.579%; route: 0.360, 66.421%
Arrival Data Path Delay: cell: 0.000, 0.000%; route: 0.237, 32.333%; tC2Q: 0.496, 67.667%
Required Clock Path Delay: cell: 0.182, 33.579%; route: 0.360, 66.421%