Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\DDS_II\data\dds_ii_top.v
C:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\DDS_II\data\dds_ii_core_encryption.v
GowinSynthesis Constraints File ---
Version V1.9.9 Beta-3
Part Number GW5AST-LV138FPG676AES
Device GW5AST-138
Device Version B
Created Time Fri Aug 11 08:37:41 2023
Legal Announcement Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module DDS_II_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.328s, Elapsed time = 0h 0m 0.34s, Peak memory usage = 43.742MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 43.742MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.015s, Peak memory usage = 43.742MB
    Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 43.742MB
    Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 43.742MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 43.742MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 43.742MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 43.742MB
    Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 43.742MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.033s, Peak memory usage = 43.742MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 43.742MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 43.742MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.875s, Elapsed time = 0h 0m 0.885s, Peak memory usage = 55.441MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.019s, Peak memory usage = 55.441MB
Generate output files:
    CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.042s, Peak memory usage = 55.441MB
Total Time and Memory Usage CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 55.441MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 62
I/O Buf 62
    IBUF 29
    OBUF 33
Register 421
    DFFRE 421
LUT 298
    LUT2 34
    LUT3 64
    LUT4 200
ALU 84
    ALU 84
INV 3
    INV 3
DSP
    MULTALU27X18 3
BSRAM 1
    pROM 1

Resource Utilization Summary

Resource Usage Utilization
Logic 385(301 LUT, 84 ALU) / 138240 <1%
Register 421 / 139140 <1%
  --Register as Latch 0 / 139140 0%
  --Register as FF 421 / 139140 <1%
BSRAM 1 / 340 <1%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
clk_i Base 10.000 100.0 0.000 5.000 clk_i_ibuf/I

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk_i 100.0(MHz) 218.3(MHz) 1 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 5.419
Data Arrival Time 5.188
Data Required Time 10.607
From u_dds_compiler_core/u_dds_taylor_corr/dds10_multi/multalu27x18_inst
To u_dds_compiler_core/u_dds_taylor_corr/dds2_multi/multalu27x18_inst
Launch Clk clk_i[R]
Latch Clk clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_i
0.000 0.000 tCL RR 1 clk_i_ibuf/I
0.683 0.683 tINS RR 425 clk_i_ibuf/O
0.863 0.180 tNET RR 26 u_dds_compiler_core/u_dds_taylor_corr/dds10_multi/multalu27x18_inst/CLK[0]
4.951 4.089 tC2Q RF 2 u_dds_compiler_core/u_dds_taylor_corr/dds10_multi/multalu27x18_inst/DOUT[25]
5.188 0.237 tNET FF 1 u_dds_compiler_core/u_dds_taylor_corr/dds2_multi/multalu27x18_inst/A[25]
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_i
10.000 0.000 tCL RR 1 clk_i_ibuf/I
10.682 0.683 tINS RR 425 clk_i_ibuf/O
10.863 0.180 tNET RR 1 u_dds_compiler_core/u_dds_taylor_corr/dds2_multi/multalu27x18_inst/CLK[0]
10.607 -0.255 tSu 1 u_dds_compiler_core/u_dds_taylor_corr/dds2_multi/multalu27x18_inst
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 1
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 0.000, 0.000%; route: 0.237, 5.479%; tC2Q: 4.089, 94.521%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 2

Path Summary:
Slack 5.419
Data Arrival Time 5.188
Data Required Time 10.607
From u_dds_compiler_core/u_dds_taylor_corr/dds10_multi/multalu27x18_inst
To u_dds_compiler_core/u_dds_taylor_corr/dds2_multi/multalu27x18_inst
Launch Clk clk_i[R]
Latch Clk clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_i
0.000 0.000 tCL RR 1 clk_i_ibuf/I
0.683 0.683 tINS RR 425 clk_i_ibuf/O
0.863 0.180 tNET RR 26 u_dds_compiler_core/u_dds_taylor_corr/dds10_multi/multalu27x18_inst/CLK[0]
4.951 4.089 tC2Q RF 2 u_dds_compiler_core/u_dds_taylor_corr/dds10_multi/multalu27x18_inst/DOUT[24]
5.188 0.237 tNET FF 1 u_dds_compiler_core/u_dds_taylor_corr/dds2_multi/multalu27x18_inst/A[24]
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_i
10.000 0.000 tCL RR 1 clk_i_ibuf/I
10.682 0.683 tINS RR 425 clk_i_ibuf/O
10.863 0.180 tNET RR 1 u_dds_compiler_core/u_dds_taylor_corr/dds2_multi/multalu27x18_inst/CLK[0]
10.607 -0.255 tSu 1 u_dds_compiler_core/u_dds_taylor_corr/dds2_multi/multalu27x18_inst
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 1
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 0.000, 0.000%; route: 0.237, 5.479%; tC2Q: 4.089, 94.521%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 3

Path Summary:
Slack 5.419
Data Arrival Time 5.188
Data Required Time 10.607
From u_dds_compiler_core/u_dds_taylor_corr/dds10_multi/multalu27x18_inst
To u_dds_compiler_core/u_dds_taylor_corr/dds2_multi/multalu27x18_inst
Launch Clk clk_i[R]
Latch Clk clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_i
0.000 0.000 tCL RR 1 clk_i_ibuf/I
0.683 0.683 tINS RR 425 clk_i_ibuf/O
0.863 0.180 tNET RR 26 u_dds_compiler_core/u_dds_taylor_corr/dds10_multi/multalu27x18_inst/CLK[0]
4.951 4.089 tC2Q RF 2 u_dds_compiler_core/u_dds_taylor_corr/dds10_multi/multalu27x18_inst/DOUT[23]
5.188 0.237 tNET FF 1 u_dds_compiler_core/u_dds_taylor_corr/dds2_multi/multalu27x18_inst/A[23]
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_i
10.000 0.000 tCL RR 1 clk_i_ibuf/I
10.682 0.683 tINS RR 425 clk_i_ibuf/O
10.863 0.180 tNET RR 1 u_dds_compiler_core/u_dds_taylor_corr/dds2_multi/multalu27x18_inst/CLK[0]
10.607 -0.255 tSu 1 u_dds_compiler_core/u_dds_taylor_corr/dds2_multi/multalu27x18_inst
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 1
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 0.000, 0.000%; route: 0.237, 5.479%; tC2Q: 4.089, 94.521%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 4

Path Summary:
Slack 5.419
Data Arrival Time 5.188
Data Required Time 10.607
From u_dds_compiler_core/u_dds_taylor_corr/dds10_multi/multalu27x18_inst
To u_dds_compiler_core/u_dds_taylor_corr/dds2_multi/multalu27x18_inst
Launch Clk clk_i[R]
Latch Clk clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_i
0.000 0.000 tCL RR 1 clk_i_ibuf/I
0.683 0.683 tINS RR 425 clk_i_ibuf/O
0.863 0.180 tNET RR 26 u_dds_compiler_core/u_dds_taylor_corr/dds10_multi/multalu27x18_inst/CLK[0]
4.951 4.089 tC2Q RF 2 u_dds_compiler_core/u_dds_taylor_corr/dds10_multi/multalu27x18_inst/DOUT[22]
5.188 0.237 tNET FF 1 u_dds_compiler_core/u_dds_taylor_corr/dds2_multi/multalu27x18_inst/A[22]
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_i
10.000 0.000 tCL RR 1 clk_i_ibuf/I
10.682 0.683 tINS RR 425 clk_i_ibuf/O
10.863 0.180 tNET RR 1 u_dds_compiler_core/u_dds_taylor_corr/dds2_multi/multalu27x18_inst/CLK[0]
10.607 -0.255 tSu 1 u_dds_compiler_core/u_dds_taylor_corr/dds2_multi/multalu27x18_inst
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 1
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 0.000, 0.000%; route: 0.237, 5.479%; tC2Q: 4.089, 94.521%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 5

Path Summary:
Slack 5.419
Data Arrival Time 5.188
Data Required Time 10.607
From u_dds_compiler_core/u_dds_taylor_corr/dds10_multi/multalu27x18_inst
To u_dds_compiler_core/u_dds_taylor_corr/dds2_multi/multalu27x18_inst
Launch Clk clk_i[R]
Latch Clk clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_i
0.000 0.000 tCL RR 1 clk_i_ibuf/I
0.683 0.683 tINS RR 425 clk_i_ibuf/O
0.863 0.180 tNET RR 26 u_dds_compiler_core/u_dds_taylor_corr/dds10_multi/multalu27x18_inst/CLK[0]
4.951 4.089 tC2Q RF 2 u_dds_compiler_core/u_dds_taylor_corr/dds10_multi/multalu27x18_inst/DOUT[21]
5.188 0.237 tNET FF 1 u_dds_compiler_core/u_dds_taylor_corr/dds2_multi/multalu27x18_inst/A[21]
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_i
10.000 0.000 tCL RR 1 clk_i_ibuf/I
10.682 0.683 tINS RR 425 clk_i_ibuf/O
10.863 0.180 tNET RR 1 u_dds_compiler_core/u_dds_taylor_corr/dds2_multi/multalu27x18_inst/CLK[0]
10.607 -0.255 tSu 1 u_dds_compiler_core/u_dds_taylor_corr/dds2_multi/multalu27x18_inst
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 1
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 0.000, 0.000%; route: 0.237, 5.479%; tC2Q: 4.089, 94.521%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%