Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\MIPI_BYTE_TO_PIXEL\data\byte_to_pixel.v C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\MIPI_BYTE_TO_PIXEL\data\byte_to_pixel_wrap.v |
GowinSynthesis Constraints File | --- |
Tool Version | V1.9.9.02 |
Part Number | GW5A-LV25UG324ES |
Device | GW5A-25 |
Device Version | A |
Created Time | Tue Mar 19 16:47:42 2024 |
Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | Byte_to_Pixel_Top |
Synthesis Process | Running parser: CPU time = 0h 0m 0.328s, Elapsed time = 0h 0m 0.318s, Peak memory usage = 111.918MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 111.918MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 111.918MB Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 111.918MB Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 111.918MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 111.918MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 111.918MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 111.918MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 111.918MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 111.918MB Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 111.918MB Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 111.918MB Tech-Mapping Phase 3: CPU time = 0h 0m 0.484s, Elapsed time = 0h 0m 0.532s, Peak memory usage = 135.609MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.052s, Peak memory usage = 135.609MB Generate output files: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.019s, Peak memory usage = 135.609MB |
Total Time and Memory Usage | CPU time = 0h 0m 0.918s, Elapsed time = 0h 0m 0.972s, Peak memory usage = 135.609MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 55 |
I/O Buf | 55 |
    IBUF | 45 |
    OBUF | 10 |
Register | 207 |
    DFFSE | 2 |
    DFFRE | 52 |
    DFFPE | 7 |
    DFFCE | 146 |
LUT | 137 |
    LUT2 | 23 |
    LUT3 | 37 |
    LUT4 | 77 |
ALU | 20 |
    ALU | 20 |
INV | 6 |
    INV | 6 |
BSRAM | 1 |
    SDPB | 1 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 163(143 LUT, 20 ALU) / 23040 | <1% |
Register | 207 / 23685 | <1% |
  --Register as Latch | 0 / 23685 | 0% |
  --Register as FF | 207 / 23685 | <1% |
BSRAM | 1 / 56 | 2% |
Timing
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|
I_BYTE_CLK | Base | 10.000 | 100.0 | 0.000 | 5.000 | I_BYTE_CLK_ibuf/I | ||
I_PIXEL_CLK | Base | 10.000 | 100.0 | 0.000 | 5.000 | I_PIXEL_CLK_ibuf/I |
Max Frequency Summary:
No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | I_BYTE_CLK | 100.000(MHz) | 183.866(MHz) | 7 | TOP |
2 | I_PIXEL_CLK | 100.000(MHz) | 226.950(MHz) | 5 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | 4.561 |
Data Arrival Time | 6.433 |
Data Required Time | 10.994 |
From | u_b2p_inst/u_mid_fifo/rRPtrWsync_3_s0 |
To | u_b2p_inst/u_mid_fifo/rFull_s0 |
Launch Clk | I_BYTE_CLK[R] |
Latch Clk | I_BYTE_CLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | I_BYTE_CLK | |||
0.000 | 0.000 | tCL | RR | 1 | I_BYTE_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 162 | I_BYTE_CLK_ibuf/O |
1.058 | 0.375 | tNET | RR | 1 | u_b2p_inst/u_mid_fifo/rRPtrWsync_3_s0/CLK |
1.440 | 0.382 | tC2Q | RR | 2 | u_b2p_inst/u_mid_fifo/rRPtrWsync_3_s0/Q |
1.815 | 0.375 | tNET | RR | 1 | u_b2p_inst/u_mid_fifo/wRPtrBinX_3_s0/I0 |
2.341 | 0.526 | tINS | RR | 5 | u_b2p_inst/u_mid_fifo/wRPtrBinX_3_s0/F |
2.716 | 0.375 | tNET | RR | 1 | u_b2p_inst/u_mid_fifo/wRPtrBinX_2_s0/I1 |
3.233 | 0.516 | tINS | RR | 1 | u_b2p_inst/u_mid_fifo/wRPtrBinX_2_s0/F |
3.608 | 0.375 | tNET | RR | 2 | u_b2p_inst/u_mid_fifo/n401_s0/I1 |
4.170 | 0.563 | tINS | RF | 1 | u_b2p_inst/u_mid_fifo/n401_s0/COUT |
4.170 | 0.000 | tNET | FF | 2 | u_b2p_inst/u_mid_fifo/n402_s0/CIN |
4.220 | 0.050 | tINS | FR | 1 | u_b2p_inst/u_mid_fifo/n402_s0/COUT |
4.220 | 0.000 | tNET | RR | 2 | u_b2p_inst/u_mid_fifo/n403_s0/CIN |
4.270 | 0.050 | tINS | RR | 1 | u_b2p_inst/u_mid_fifo/n403_s0/COUT |
4.270 | 0.000 | tNET | RR | 2 | u_b2p_inst/u_mid_fifo/n404_s0/CIN |
4.320 | 0.050 | tINS | RR | 1 | u_b2p_inst/u_mid_fifo/n404_s0/COUT |
4.695 | 0.375 | tNET | RR | 1 | u_b2p_inst/u_mid_fifo/n418_s3/I0 |
5.221 | 0.526 | tINS | RR | 1 | u_b2p_inst/u_mid_fifo/n418_s3/F |
5.596 | 0.375 | tNET | RR | 1 | u_b2p_inst/u_mid_fifo/n418_s0/I2 |
6.058 | 0.461 | tINS | RR | 1 | u_b2p_inst/u_mid_fifo/n418_s0/F |
6.433 | 0.375 | tNET | RR | 1 | u_b2p_inst/u_mid_fifo/rFull_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | I_BYTE_CLK | |||
10.000 | 0.000 | tCL | RR | 1 | I_BYTE_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 162 | I_BYTE_CLK_ibuf/O |
11.057 | 0.375 | tNET | RR | 1 | u_b2p_inst/u_mid_fifo/rFull_s0/CLK |
10.994 | -0.064 | tSu | 1 | u_b2p_inst/u_mid_fifo/rFull_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 7 |
Arrival Clock Path Delay: | cell: 0.683, 64.539%; route: 0.375, 35.461% |
Arrival Data Path Delay: | cell: 2.743, 51.024%; route: 2.250, 41.860%; tC2Q: 0.382, 7.116% |
Required Clock Path Delay: | cell: 0.683, 64.539%; route: 0.375, 35.461% |
Path 2
Path Summary:Slack | 5.521 |
Data Arrival Time | 5.225 |
Data Required Time | 10.746 |
From | u_b2p_inst/wc_cnt_dec_9_s1 |
To | u_b2p_inst/mid_offset_0_s1 |
Launch Clk | I_BYTE_CLK[R] |
Latch Clk | I_BYTE_CLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | I_BYTE_CLK | |||
0.000 | 0.000 | tCL | RR | 1 | I_BYTE_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 162 | I_BYTE_CLK_ibuf/O |
1.058 | 0.375 | tNET | RR | 1 | u_b2p_inst/wc_cnt_dec_9_s1/CLK |
1.440 | 0.382 | tC2Q | RR | 4 | u_b2p_inst/wc_cnt_dec_9_s1/Q |
1.815 | 0.375 | tNET | RR | 1 | u_b2p_inst/n1149_s3/I0 |
2.341 | 0.526 | tINS | RR | 3 | u_b2p_inst/n1149_s3/F |
2.716 | 0.375 | tNET | RR | 1 | u_b2p_inst/mid_offset_3_s5/I2 |
3.178 | 0.461 | tINS | RR | 1 | u_b2p_inst/mid_offset_3_s5/F |
3.553 | 0.375 | tNET | RR | 1 | u_b2p_inst/mid_offset_3_s4/I2 |
4.014 | 0.461 | tINS | RR | 2 | u_b2p_inst/mid_offset_3_s4/F |
4.389 | 0.375 | tNET | RR | 1 | u_b2p_inst/mid_offset_1_s4/I2 |
4.850 | 0.461 | tINS | RR | 2 | u_b2p_inst/mid_offset_1_s4/F |
5.225 | 0.375 | tNET | RR | 1 | u_b2p_inst/mid_offset_0_s1/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | I_BYTE_CLK | |||
10.000 | 0.000 | tCL | RR | 1 | I_BYTE_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 162 | I_BYTE_CLK_ibuf/O |
11.057 | 0.375 | tNET | RR | 1 | u_b2p_inst/mid_offset_0_s1/CLK |
10.746 | -0.311 | tSu | 1 | u_b2p_inst/mid_offset_0_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.683, 64.539%; route: 0.375, 35.461% |
Arrival Data Path Delay: | cell: 1.910, 45.831%; route: 1.875, 44.991%; tC2Q: 0.382, 9.178% |
Required Clock Path Delay: | cell: 0.683, 64.539%; route: 0.375, 35.461% |
Path 3
Path Summary:Slack | 5.521 |
Data Arrival Time | 5.225 |
Data Required Time | 10.746 |
From | u_b2p_inst/wc_cnt_dec_9_s1 |
To | u_b2p_inst/mid_offset_1_s1 |
Launch Clk | I_BYTE_CLK[R] |
Latch Clk | I_BYTE_CLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | I_BYTE_CLK | |||
0.000 | 0.000 | tCL | RR | 1 | I_BYTE_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 162 | I_BYTE_CLK_ibuf/O |
1.058 | 0.375 | tNET | RR | 1 | u_b2p_inst/wc_cnt_dec_9_s1/CLK |
1.440 | 0.382 | tC2Q | RR | 4 | u_b2p_inst/wc_cnt_dec_9_s1/Q |
1.815 | 0.375 | tNET | RR | 1 | u_b2p_inst/n1149_s3/I0 |
2.341 | 0.526 | tINS | RR | 3 | u_b2p_inst/n1149_s3/F |
2.716 | 0.375 | tNET | RR | 1 | u_b2p_inst/mid_offset_3_s5/I2 |
3.178 | 0.461 | tINS | RR | 1 | u_b2p_inst/mid_offset_3_s5/F |
3.553 | 0.375 | tNET | RR | 1 | u_b2p_inst/mid_offset_3_s4/I2 |
4.014 | 0.461 | tINS | RR | 2 | u_b2p_inst/mid_offset_3_s4/F |
4.389 | 0.375 | tNET | RR | 1 | u_b2p_inst/mid_offset_1_s4/I2 |
4.850 | 0.461 | tINS | RR | 2 | u_b2p_inst/mid_offset_1_s4/F |
5.225 | 0.375 | tNET | RR | 1 | u_b2p_inst/mid_offset_1_s1/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | I_BYTE_CLK | |||
10.000 | 0.000 | tCL | RR | 1 | I_BYTE_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 162 | I_BYTE_CLK_ibuf/O |
11.057 | 0.375 | tNET | RR | 1 | u_b2p_inst/mid_offset_1_s1/CLK |
10.746 | -0.311 | tSu | 1 | u_b2p_inst/mid_offset_1_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.683, 64.539%; route: 0.375, 35.461% |
Arrival Data Path Delay: | cell: 1.910, 45.831%; route: 1.875, 44.991%; tC2Q: 0.382, 9.178% |
Required Clock Path Delay: | cell: 0.683, 64.539%; route: 0.375, 35.461% |
Path 4
Path Summary:Slack | 5.521 |
Data Arrival Time | 5.225 |
Data Required Time | 10.746 |
From | u_b2p_inst/wc_cnt_dec_9_s1 |
To | u_b2p_inst/mid_offset_3_s1 |
Launch Clk | I_BYTE_CLK[R] |
Latch Clk | I_BYTE_CLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | I_BYTE_CLK | |||
0.000 | 0.000 | tCL | RR | 1 | I_BYTE_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 162 | I_BYTE_CLK_ibuf/O |
1.058 | 0.375 | tNET | RR | 1 | u_b2p_inst/wc_cnt_dec_9_s1/CLK |
1.440 | 0.382 | tC2Q | RR | 4 | u_b2p_inst/wc_cnt_dec_9_s1/Q |
1.815 | 0.375 | tNET | RR | 1 | u_b2p_inst/n1149_s3/I0 |
2.341 | 0.526 | tINS | RR | 3 | u_b2p_inst/n1149_s3/F |
2.716 | 0.375 | tNET | RR | 1 | u_b2p_inst/mid_offset_3_s5/I2 |
3.178 | 0.461 | tINS | RR | 1 | u_b2p_inst/mid_offset_3_s5/F |
3.553 | 0.375 | tNET | RR | 1 | u_b2p_inst/mid_offset_3_s4/I2 |
4.014 | 0.461 | tINS | RR | 2 | u_b2p_inst/mid_offset_3_s4/F |
4.389 | 0.375 | tNET | RR | 1 | u_b2p_inst/mid_offset_3_s7/I2 |
4.850 | 0.461 | tINS | RR | 1 | u_b2p_inst/mid_offset_3_s7/F |
5.225 | 0.375 | tNET | RR | 1 | u_b2p_inst/mid_offset_3_s1/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | I_BYTE_CLK | |||
10.000 | 0.000 | tCL | RR | 1 | I_BYTE_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 162 | I_BYTE_CLK_ibuf/O |
11.057 | 0.375 | tNET | RR | 1 | u_b2p_inst/mid_offset_3_s1/CLK |
10.746 | -0.311 | tSu | 1 | u_b2p_inst/mid_offset_3_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.683, 64.539%; route: 0.375, 35.461% |
Arrival Data Path Delay: | cell: 1.910, 45.831%; route: 1.875, 44.991%; tC2Q: 0.382, 9.178% |
Required Clock Path Delay: | cell: 0.683, 64.539%; route: 0.375, 35.461% |
Path 5
Path Summary:Slack | 5.584 |
Data Arrival Time | 5.410 |
Data Required Time | 10.994 |
From | u_b2p_inst/wc_cnt_dec_1_s3 |
To | u_b2p_inst/wc_cnt_dec_15_s1 |
Launch Clk | I_BYTE_CLK[R] |
Latch Clk | I_BYTE_CLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | I_BYTE_CLK | |||
0.000 | 0.000 | tCL | RR | 1 | I_BYTE_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 162 | I_BYTE_CLK_ibuf/O |
1.058 | 0.375 | tNET | RR | 1 | u_b2p_inst/wc_cnt_dec_1_s3/CLK |
1.440 | 0.382 | tC2Q | RR | 6 | u_b2p_inst/wc_cnt_dec_1_s3/Q |
1.815 | 0.375 | tNET | RR | 1 | u_b2p_inst/n1157_s1/I0 |
2.341 | 0.526 | tINS | RR | 8 | u_b2p_inst/n1157_s1/F |
2.716 | 0.375 | tNET | RR | 1 | u_b2p_inst/n1149_s1/I1 |
3.233 | 0.516 | tINS | RR | 3 | u_b2p_inst/n1149_s1/F |
3.608 | 0.375 | tNET | RR | 1 | u_b2p_inst/n1147_s3/I0 |
4.134 | 0.526 | tINS | RR | 1 | u_b2p_inst/n1147_s3/F |
4.509 | 0.375 | tNET | RR | 1 | u_b2p_inst/n1147_s0/I0 |
5.035 | 0.526 | tINS | RR | 1 | u_b2p_inst/n1147_s0/F |
5.410 | 0.375 | tNET | RR | 1 | u_b2p_inst/wc_cnt_dec_15_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | I_BYTE_CLK | |||
10.000 | 0.000 | tCL | RR | 1 | I_BYTE_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 162 | I_BYTE_CLK_ibuf/O |
11.057 | 0.375 | tNET | RR | 1 | u_b2p_inst/wc_cnt_dec_15_s1/CLK |
10.994 | -0.064 | tSu | 1 | u_b2p_inst/wc_cnt_dec_15_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.683, 64.539%; route: 0.375, 35.461% |
Arrival Data Path Delay: | cell: 2.095, 48.133%; route: 1.875, 43.079%; tC2Q: 0.382, 8.788% |
Required Clock Path Delay: | cell: 0.683, 64.539%; route: 0.375, 35.461% |