Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | D:\Programs\Gowin\Gowin_V1.9.9.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v D:\Programs\Gowin\Gowin_V1.9.9.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v D:\Programs\Gowin\Gowin_V1.9.9.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v D:\Programs\Gowin\Gowin_V1.9.9.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v D:\Programs\Gowin\Gowin_V1.9.9.01_x64\IDE\data\ipcores\GAO\GW_CON\gw_con_top.v D:\Programs\Gowin\Gowin_V1.9.9.01_x64\IDE\data\ipcores\gw_jtag.v F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\DSI_to_LVDS_5a25\fpga_proj\impl\gao\gw_gao_top.v |
GowinSynthesis Constraints File | --- |
Tool Version | V1.9.9.01 (64-bit) |
Part Number | GW5A-LV25UG324ES |
Device | GW5A-25 |
Device Version | A |
Created Time | Wed Mar 6 18:49:18 2024 |
Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | gw_gao |
Synthesis Process | Running parser: CPU time = 0h 0m 0.296s, Elapsed time = 0h 0m 0.3s, Peak memory usage = 112.160MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 112.160MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.022s, Peak memory usage = 112.160MB Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 112.160MB Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.024s, Peak memory usage = 112.160MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 112.160MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 112.160MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 112.160MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 112.160MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.021s, Peak memory usage = 112.160MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 112.160MB Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 112.160MB Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 137.887MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.04s, Peak memory usage = 137.887MB Generate output files: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.05s, Peak memory usage = 137.887MB |
Total Time and Memory Usage | CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 137.887MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 32 |
I/O Buf | 32 |
    IBUF | 31 |
    OBUF | 1 |
Register | 359 |
    DFFRE | 1 |
    DFFPE | 36 |
    DFFCE | 322 |
LUT | 466 |
    LUT2 | 52 |
    LUT3 | 99 |
    LUT4 | 315 |
MUX | 1 |
    MUX16 | 1 |
ALU | 14 |
    ALU | 14 |
INV | 4 |
    INV | 4 |
BSRAM | 4 |
    SDPB | 4 |
Black Box | 1 |
    GW_JTAG | 1 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 492(478 LUT, 14 ALU) / 23040 | 3% |
Register | 359 / 23685 | 2% |
  --Register as Latch | 0 / 23685 | 0% |
  --Register as FF | 359 / 23685 | 2% |
BSRAM | 4 / 56 | 8% |
Timing
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|
pixel_clk | Base | 10.000 | 100.0 | 0.000 | 5.000 | pixel_clk_ibuf/I | ||
u_icon_top/n19_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 | u_icon_top/n19_s2/O | ||
u_la0_top/n15_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 | u_la0_top/n15_s2/O |
Max Frequency Summary:
No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | pixel_clk | 100.000(MHz) | 191.113(MHz) | 6 | TOP |
2 | u_icon_top/n19_6 | 100.000(MHz) | 1217.656(MHz) | 1 | TOP |
3 | u_la0_top/n15_6 | 100.000(MHz) | 1217.656(MHz) | 1 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | 4.767 |
Data Arrival Time | 6.226 |
Data Required Time | 10.994 |
From | u_la0_top/capture_window_sel_0_s3 |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_10_s0 |
Launch Clk | pixel_clk[R] |
Latch Clk | pixel_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | pixel_clk | |||
0.000 | 0.000 | tCL | RR | 1 | pixel_clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 126 | pixel_clk_ibuf/O |
1.058 | 0.375 | tNET | RR | 1 | u_la0_top/capture_window_sel_0_s3/CLK |
1.440 | 0.382 | tC2Q | RR | 15 | u_la0_top/capture_window_sel_0_s3/Q |
1.815 | 0.375 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_10_s20/I1 |
2.331 | 0.516 | tINS | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_10_s20/F |
2.706 | 0.375 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_10_s19/I1 |
3.223 | 0.516 | tINS | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_10_s19/F |
3.598 | 0.375 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_10_s16/I0 |
4.124 | 0.526 | tINS | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_10_s16/F |
4.499 | 0.375 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_10_s13/I1 |
5.015 | 0.516 | tINS | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_10_s13/F |
5.390 | 0.375 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_10_s11/I2 |
5.851 | 0.461 | tINS | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_10_s11/F |
6.226 | 0.375 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_10_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | pixel_clk | |||
10.000 | 0.000 | tCL | RR | 1 | pixel_clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 126 | pixel_clk_ibuf/O |
11.057 | 0.375 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_10_s0/CLK |
10.994 | -0.064 | tSu | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_10_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 6 |
Arrival Clock Path Delay: | cell: 0.683, 64.539%; route: 0.375, 35.461% |
Arrival Data Path Delay: | cell: 2.536, 49.069%; route: 2.250, 43.531%; tC2Q: 0.382, 7.400% |
Required Clock Path Delay: | cell: 0.683, 64.539%; route: 0.375, 35.461% |
Path 2
Path Summary:Slack | 5.265 |
Data Arrival Time | 5.729 |
Data Required Time | 10.994 |
From | u_la0_top/capture_window_sel_1_s1 |
To | u_la0_top/capture_window_sel_10_s1 |
Launch Clk | pixel_clk[R] |
Latch Clk | pixel_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | pixel_clk | |||
0.000 | 0.000 | tCL | RR | 1 | pixel_clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 126 | pixel_clk_ibuf/O |
1.058 | 0.375 | tNET | RR | 1 | u_la0_top/capture_window_sel_1_s1/CLK |
1.440 | 0.382 | tC2Q | RR | 13 | u_la0_top/capture_window_sel_1_s1/Q |
1.815 | 0.375 | tNET | RR | 1 | u_la0_top/n1791_s2/I0 |
2.341 | 0.526 | tINS | RR | 2 | u_la0_top/n1791_s2/F |
2.716 | 0.375 | tNET | RR | 1 | u_la0_top/n1788_s2/I3 |
2.979 | 0.262 | tINS | RR | 4 | u_la0_top/n1788_s2/F |
3.354 | 0.375 | tNET | RR | 1 | u_la0_top/n1785_s2/I3 |
3.616 | 0.262 | tINS | RR | 3 | u_la0_top/n1785_s2/F |
3.991 | 0.375 | tNET | RR | 1 | u_la0_top/n1783_s2/I2 |
4.452 | 0.461 | tINS | RR | 1 | u_la0_top/n1783_s2/F |
4.827 | 0.375 | tNET | RR | 1 | u_la0_top/n1783_s1/I0 |
5.354 | 0.526 | tINS | RR | 1 | u_la0_top/n1783_s1/F |
5.729 | 0.375 | tNET | RR | 1 | u_la0_top/capture_window_sel_10_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | pixel_clk | |||
10.000 | 0.000 | tCL | RR | 1 | pixel_clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 126 | pixel_clk_ibuf/O |
11.057 | 0.375 | tNET | RR | 1 | u_la0_top/capture_window_sel_10_s1/CLK |
10.994 | -0.064 | tSu | 1 | u_la0_top/capture_window_sel_10_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 6 |
Arrival Clock Path Delay: | cell: 0.683, 64.539%; route: 0.375, 35.461% |
Arrival Data Path Delay: | cell: 2.039, 43.645%; route: 2.250, 48.167%; tC2Q: 0.382, 8.188% |
Required Clock Path Delay: | cell: 0.683, 64.539%; route: 0.375, 35.461% |
Path 3
Path Summary:Slack | 5.391 |
Data Arrival Time | 5.355 |
Data Required Time | 10.746 |
From | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1 |
To | u_la0_top/u_ao_mem_ctrl/capture_loop_s1 |
Launch Clk | pixel_clk[R] |
Latch Clk | pixel_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | pixel_clk | |||
0.000 | 0.000 | tCL | RR | 1 | pixel_clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 126 | pixel_clk_ibuf/O |
1.058 | 0.375 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK |
1.440 | 0.382 | tC2Q | RR | 7 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/Q |
1.815 | 0.375 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/n354_s9/I0 |
2.341 | 0.526 | tINS | RR | 1 | u_la0_top/u_ao_mem_ctrl/n354_s9/F |
2.716 | 0.375 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/n354_s7/I0 |
3.242 | 0.526 | tINS | RR | 1 | u_la0_top/u_ao_mem_ctrl/n354_s7/F |
3.617 | 0.375 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/n354_s4/I2 |
4.079 | 0.461 | tINS | RR | 12 | u_la0_top/u_ao_mem_ctrl/n354_s4/F |
4.454 | 0.375 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_loop_s4/I0 |
4.980 | 0.526 | tINS | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_loop_s4/F |
5.355 | 0.375 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | pixel_clk | |||
10.000 | 0.000 | tCL | RR | 1 | pixel_clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 126 | pixel_clk_ibuf/O |
11.057 | 0.375 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK |
10.746 | -0.311 | tSu | 1 | u_la0_top/u_ao_mem_ctrl/capture_loop_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.683, 64.539%; route: 0.375, 35.461% |
Arrival Data Path Delay: | cell: 2.040, 47.469%; route: 1.875, 43.630%; tC2Q: 0.382, 8.901% |
Required Clock Path Delay: | cell: 0.683, 64.539%; route: 0.375, 35.461% |
Path 4
Path Summary:Slack | 5.594 |
Data Arrival Time | 5.400 |
Data Required Time | 10.994 |
From | u_la0_top/capture_window_sel_0_s3 |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_9_s0 |
Launch Clk | pixel_clk[R] |
Latch Clk | pixel_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | pixel_clk | |||
0.000 | 0.000 | tCL | RR | 1 | pixel_clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 126 | pixel_clk_ibuf/O |
1.058 | 0.375 | tNET | RR | 1 | u_la0_top/capture_window_sel_0_s3/CLK |
1.440 | 0.382 | tC2Q | RR | 15 | u_la0_top/capture_window_sel_0_s3/Q |
1.815 | 0.375 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s15/I1 |
2.331 | 0.516 | tINS | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s15/F |
2.706 | 0.375 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s14/I1 |
3.223 | 0.516 | tINS | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s14/F |
3.598 | 0.375 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s11/I0 |
4.124 | 0.526 | tINS | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s11/F |
4.499 | 0.375 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s10/I0 |
5.025 | 0.526 | tINS | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s10/F |
5.400 | 0.375 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_9_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | pixel_clk | |||
10.000 | 0.000 | tCL | RR | 1 | pixel_clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 126 | pixel_clk_ibuf/O |
11.057 | 0.375 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_9_s0/CLK |
10.994 | -0.064 | tSu | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_9_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.683, 64.539%; route: 0.375, 35.461% |
Arrival Data Path Delay: | cell: 2.085, 48.014%; route: 1.875, 43.178%; tC2Q: 0.382, 8.808% |
Required Clock Path Delay: | cell: 0.683, 64.539%; route: 0.375, 35.461% |
Path 5
Path Summary:Slack | 5.704 |
Data Arrival Time | 5.290 |
Data Required Time | 10.994 |
From | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1 |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5 |
Launch Clk | pixel_clk[R] |
Latch Clk | pixel_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | pixel_clk | |||
0.000 | 0.000 | tCL | RR | 1 | pixel_clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 126 | pixel_clk_ibuf/O |
1.058 | 0.375 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK |
1.440 | 0.382 | tC2Q | RR | 7 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/Q |
1.815 | 0.375 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/n354_s9/I0 |
2.341 | 0.526 | tINS | RR | 1 | u_la0_top/u_ao_mem_ctrl/n354_s9/F |
2.716 | 0.375 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/n354_s7/I0 |
3.242 | 0.526 | tINS | RR | 1 | u_la0_top/u_ao_mem_ctrl/n354_s7/F |
3.617 | 0.375 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/n354_s4/I2 |
4.079 | 0.461 | tINS | RR | 12 | u_la0_top/u_ao_mem_ctrl/n354_s4/F |
4.454 | 0.375 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/n364_s3/I2 |
4.915 | 0.461 | tINS | RR | 1 | u_la0_top/u_ao_mem_ctrl/n364_s3/F |
5.290 | 0.375 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | pixel_clk | |||
10.000 | 0.000 | tCL | RR | 1 | pixel_clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 126 | pixel_clk_ibuf/O |
11.057 | 0.375 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/CLK |
10.994 | -0.064 | tSu | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.683, 64.539%; route: 0.375, 35.461% |
Arrival Data Path Delay: | cell: 1.975, 46.663%; route: 1.875, 44.300%; tC2Q: 0.382, 9.037% |
Required Clock Path Delay: | cell: 0.683, 64.539%; route: 0.375, 35.461% |