Timing Messages

Report Title Timing Analysis Report
Design File E:\myWork\IP\releaseVerify\version\1.9.9.02\Gowin_DSI_RX_B2P_RefDesigns\csi_rx_demo_5a25\fpga_proj\impl\gwsynthesis\csi_rx_demo_5a25.vg
Physical Constraints File E:\myWork\IP\releaseVerify\version\1.9.9.02\Gowin_DSI_RX_B2P_RefDesigns\csi_rx_demo_5a25\fpga_proj\src\csi_demo.cst
Timing Constraint File E:\myWork\IP\releaseVerify\version\1.9.9.02\Gowin_DSI_RX_B2P_RefDesigns\csi_rx_demo_5a25\fpga_proj\src\csi_demo.sdc
Tool Version V1.9.9.02
Part Number GW5A-LV25UG324ES
Device GW5A-25
Device Version A
Created Time Tue Mar 19 16:48:29 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model Slow 0.855V 0C ES
Hold Delay Model Fast 0.945V 85C ES
Numbers of Paths Analyzed 3765
Numbers of Endpoints Analyzed 4837
Numbers of Falling Endpoints 10
Numbers of Setup Violated Endpoints 0
Numbers of Hold Violated Endpoints 0

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Objects
clk_50 Base 20.000 50.000 0.000 10.000 OSC_50M
byte_clk Base 15.000 66.667 0.000 7.500 byte_clk
pixel_clk Generated 7.500 133.333 0.000 3.750 byte_clk byte_clk lvds_pclk
tck_pad_i Base 50.000 20.000 0.000 25.000 tck_ibuf/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk_50 50.000(MHz) 149.673(MHz) 5 TOP
2 byte_clk 66.667(MHz) 126.843(MHz) 4 TOP
3 pixel_clk 133.333(MHz) 227.645(MHz) 3 TOP
4 tck_pad_i 20.000(MHz) 47.909(MHz) 7 TOP

Total Negative Slack Summary:

Clock Name Analysis Type Endpoints TNS Number of Endpoints
clk_50 Setup 0.000 0
clk_50 Hold 0.000 0
byte_clk Setup 0.000 0
byte_clk Hold 0.000 0
pixel_clk Setup 0.000 0
pixel_clk Hold 0.000 0
tck_pad_i Setup 0.000 0
tck_pad_i Hold 0.000 0

Timing Details

Path Slacks Table:

Setup Paths Table

Setup Paths Table[1]:

Report Command:report_timing -setup -from_clock [get_clocks {pixel_clk}] -max_paths 20 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 3.107 u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/DO[7] u_bayer_rgb/r_o_7_s0/D pixel_clk:[R] pixel_clk:[R] 7.500 -0.038 4.368
2 3.221 u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/DO[5] u_bayer_rgb/r_o_5_s0/D pixel_clk:[R] pixel_clk:[R] 7.500 -0.036 4.251
3 3.303 u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/DO[7] u_bayer_rgb/g_o_7_s0/D pixel_clk:[R] pixel_clk:[R] 7.500 -0.024 4.157
4 3.372 u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/DO[0] u_bayer_rgb/r_o_0_s0/D pixel_clk:[R] pixel_clk:[R] 7.500 -0.017 4.081
5 3.453 u_b2p/u_b2p_inst/u_mid_fifo/rWPtrRsync_5_s0/Q u_b2p/u_b2p_inst/u_mid_fifo/rEmpty_s0/D pixel_clk:[R] pixel_clk:[R] 7.500 -0.010 3.992
6 3.467 u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/DO[2] u_bayer_rgb/r_o_2_s0/D pixel_clk:[R] pixel_clk:[R] 7.500 -0.024 3.994
7 3.511 u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/DO[0] u_bayer_rgb/g_o_0_s0/D pixel_clk:[R] pixel_clk:[R] 7.500 -0.012 3.938
8 3.534 u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/DO[6] u_bayer_rgb/r_o_6_s0/D pixel_clk:[R] pixel_clk:[R] 7.500 -0.027 3.929
9 3.541 u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/DO[3] u_bayer_rgb/r_o_3_s0/D pixel_clk:[R] pixel_clk:[R] 7.500 -0.033 3.929
10 3.544 u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/DO[2] u_bayer_rgb/g_o_2_s0/D pixel_clk:[R] pixel_clk:[R] 7.500 -0.027 3.919
11 3.587 u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/DO[3] u_bayer_rgb/g_o_3_s0/D pixel_clk:[R] pixel_clk:[R] 7.500 -0.024 3.874
12 3.633 u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/DO[5] u_bayer_rgb/g_o_5_s0/D pixel_clk:[R] pixel_clk:[R] 7.500 -0.024 3.828
13 3.638 u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/DO[4] u_bayer_rgb/g_o_4_s0/D pixel_clk:[R] pixel_clk:[R] 7.500 -0.024 3.822
14 3.713 u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/DO[4] u_bayer_rgb/r_o_4_s0/D pixel_clk:[R] pixel_clk:[R] 7.500 -0.036 3.759
15 3.729 u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s/DO[7] u_b2p/u_b2p_inst/pixel_data_r_7_s0/D pixel_clk:[R] pixel_clk:[R] 7.500 0.014 3.692
16 3.790 u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/DO[1] u_bayer_rgb/g_o_1_s0/D pixel_clk:[R] pixel_clk:[R] 7.500 -0.024 3.670
17 3.842 u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/DO[1] u_bayer_rgb/r_o_1_s0/D pixel_clk:[R] pixel_clk:[R] 7.500 -0.024 3.619
18 3.907 u_b2p/u_b2p_inst/u_mid_fifo/rWPtrRsync_5_s0/Q u_b2p/u_b2p_inst/u_mid_fifo/rRdDiff_6_s0/D pixel_clk:[R] pixel_clk:[R] 7.500 0.015 3.514
19 3.912 u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s/DO[1] u_b2p/u_b2p_inst/pixel_data_r_1_s0/D pixel_clk:[R] pixel_clk:[R] 7.500 0.014 3.510
20 3.912 u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s/DO[3] u_b2p/u_b2p_inst/pixel_data_r_3_s0/D pixel_clk:[R] pixel_clk:[R] 7.500 0.014 3.510

Setup Paths Table[2]:

Report Command:report_timing -setup -from_clock [get_clocks {byte_clk}] -max_paths 20 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 7.116 odt_en_msk_s0/Q hsrx_cnt_0_s1/CE byte_clk:[R] byte_clk:[R] 15.000 0.000 7.572
2 7.320 odt_en_msk_s0/Q hsrx_cnt_1_s1/CE byte_clk:[R] byte_clk:[R] 15.000 -0.017 7.385
3 7.320 odt_en_msk_s0/Q hsrx_cnt_2_s1/CE byte_clk:[R] byte_clk:[R] 15.000 -0.017 7.385
4 7.320 odt_en_msk_s0/Q hsrx_cnt_3_s1/CE byte_clk:[R] byte_clk:[R] 15.000 -0.017 7.385
5 7.682 odt_en_msk_s0/Q hsrx_cnt_4_s3/D byte_clk:[R] byte_clk:[R] 15.000 -0.017 7.271
6 7.682 odt_en_msk_s0/Q hsrx_cnt_5_s7/D byte_clk:[R] byte_clk:[R] 15.000 -0.017 7.271
7 7.682 odt_en_msk_s0/Q hsrx_cnt_1_s1/D byte_clk:[R] byte_clk:[R] 15.000 -0.017 7.271
8 7.682 odt_en_msk_s0/Q hsrx_cnt_2_s1/D byte_clk:[R] byte_clk:[R] 15.000 -0.017 7.271
9 7.682 odt_en_msk_s0/Q hsrx_cnt_3_s1/D byte_clk:[R] byte_clk:[R] 15.000 -0.017 7.271
10 7.713 u_csi_rx/u_dsi_csi2/rHSel_0_s1/Q u_csi_rx/u_dsi_csi2/rHeader_6_s0/CE byte_clk:[R] byte_clk:[R] 15.000 0.015 6.961
11 7.713 u_csi_rx/u_dsi_csi2/rHSel_0_s1/Q u_csi_rx/u_dsi_csi2/rHeader_30_s0/CE byte_clk:[R] byte_clk:[R] 15.000 0.015 6.961
12 7.840 odt_en_msk_s0/Q hsrx_cnt_0_s1/D byte_clk:[R] byte_clk:[R] 15.000 0.000 7.096
13 8.495 u_csi_rx/u_dsi_csi2/rHSel_0_s1/Q u_csi_rx/u_dsi_csi2/rHeader_7_s0/CE byte_clk:[R] byte_clk:[R] 15.000 0.017 6.176
14 8.513 u_csi_rx/u_dsi_csi2/rHSel_0_s1/Q u_csi_rx/u_dsi_csi2/rHeader_14_s0/CE byte_clk:[R] byte_clk:[R] 15.000 0.001 6.175
15 8.513 u_csi_rx/u_dsi_csi2/rHSel_0_s1/Q u_csi_rx/u_dsi_csi2/rHeader_23_s0/CE byte_clk:[R] byte_clk:[R] 15.000 0.001 6.175
16 8.561 u_csi_rx/u_dsi_csi2/rHSel_0_s1/Q u_csi_rx/u_dsi_csi2/rHeader_2_s0/CE byte_clk:[R] byte_clk:[R] 15.000 -0.002 6.130
17 8.561 u_csi_rx/u_dsi_csi2/rHSel_0_s1/Q u_csi_rx/u_dsi_csi2/rHeader_3_s0/CE byte_clk:[R] byte_clk:[R] 15.000 -0.002 6.130
18 8.666 u_csi_rx/u_dsi_csi2/rHSel_0_s1/Q u_csi_rx/u_dsi_csi2/rHeader_31_s0/CE byte_clk:[R] byte_clk:[R] 15.000 0.010 6.013
19 8.676 u_csi_rx/u_dsi_csi2/rHSel_0_s1/Q u_csi_rx/u_dsi_csi2/rHeader_10_s0/CE byte_clk:[R] byte_clk:[R] 15.000 0.005 6.008
20 8.676 u_csi_rx/u_dsi_csi2/rHSel_0_s1/Q u_csi_rx/u_dsi_csi2/rHeader_11_s0/CE byte_clk:[R] byte_clk:[R] 15.000 0.005 6.008

Hold Paths Table

Hold Paths Table[1]:

Report Command:report_timing -hold -from_clock [get_clocks {pixel_clk}] -max_paths 20 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.076 u_bayer_rgb/data_tmp2_0_s0/Q u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/DI[0] pixel_clk:[R] pixel_clk:[R] 0.000 0.011 0.314
2 0.204 u_bayer_rgb/shift_line_inst0/shiftout_addr_5_s0/Q u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/ADB[8] pixel_clk:[R] pixel_clk:[R] 0.000 0.016 0.306
3 0.204 u_bayer_rgb/shift_line_inst0/shiftout_addr_4_s0/Q u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/ADB[7] pixel_clk:[R] pixel_clk:[R] 0.000 0.016 0.306
4 0.298 u_bayer_rgb/shift_line_inst0/shiftout_addr_3_s0/Q u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/ADB[6] pixel_clk:[R] pixel_clk:[R] 0.000 0.016 0.400
5 0.303 u_bayer_rgb/shift_line_inst0/shiftout_addr_9_s0/Q u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/ADB[12] pixel_clk:[R] pixel_clk:[R] 0.000 0.021 0.400
6 0.303 u_bayer_rgb/shift_line_inst0/shiftout_addr_7_s0/Q u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/ADB[10] pixel_clk:[R] pixel_clk:[R] 0.000 0.021 0.400
7 0.305 u_bayer_rgb/shift_line_inst0/shiftin_addr_7_s0/Q u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/ADA[10] pixel_clk:[R] pixel_clk:[R] 0.000 0.016 0.407
8 0.310 u_bayer_rgb/shift_line_inst0/shiftin_addr_1_s0/Q u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/ADA[4] pixel_clk:[R] pixel_clk:[R] 0.000 0.021 0.407
9 0.329 u_bayer_rgb/shift_line_inst0/shiftin_addr_10_s0/Q u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/ADA[13] pixel_clk:[R] pixel_clk:[R] 0.000 0.016 0.431
10 0.329 u_bayer_rgb/shift_line_inst0/shiftin_addr_3_s0/Q u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/ADA[6] pixel_clk:[R] pixel_clk:[R] 0.000 0.021 0.426
11 0.329 u_bayer_rgb/shift_line_inst0/shiftin_addr_2_s0/Q u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/ADA[5] pixel_clk:[R] pixel_clk:[R] 0.000 0.021 0.426
12 0.334 u_bayer_rgb/shift_line_inst0/shiftin_addr_5_s0/Q u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/ADA[8] pixel_clk:[R] pixel_clk:[R] 0.000 0.021 0.431
13 0.334 u_bayer_rgb/shift_line_inst0/shiftin_addr_4_s0/Q u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/ADA[7] pixel_clk:[R] pixel_clk:[R] 0.000 0.021 0.431
14 0.377 u_bayer_rgb/devcnt_5_s1/Q u_bayer_rgb/devcnt_5_s1/D pixel_clk:[R] pixel_clk:[R] 0.000 0.000 0.379
15 0.378 u_bayer_rgb/shift_line_inst0/shiftin_addr_0_s0/Q u_bayer_rgb/shift_line_inst0/shiftin_addr_0_s0/D pixel_clk:[R] pixel_clk:[R] 0.000 0.000 0.379
16 0.392 u_bayer_rgb/video_format_detect_inst/hcnt_0_s3/Q u_bayer_rgb/video_format_detect_inst/hcnt_0_s3/D pixel_clk:[R] pixel_clk:[R] 0.000 0.000 0.394
17 0.410 u_bayer_rgb/shift_line_inst0/shiftout_addr_2_s0/Q u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/ADB[5] pixel_clk:[R] pixel_clk:[R] 0.000 0.016 0.512
18 0.423 u_bayer_rgb/shift_line_inst0/shiftin_addr_9_s0/Q u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/ADA[12] pixel_clk:[R] pixel_clk:[R] 0.000 0.016 0.525
19 0.428 u_bayer_rgb/shift_line_inst0/shiftin_addr_6_s0/Q u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/ADA[9] pixel_clk:[R] pixel_clk:[R] 0.000 0.021 0.525
20 0.428 u_bayer_rgb/data_tmp2_2_s0/Q u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/DI[2] pixel_clk:[R] pixel_clk:[R] 0.000 0.014 0.664

Hold Paths Table[2]:

Report Command:report_timing -hold -from_clock [get_clocks {byte_clk}] -max_paths 20 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.063 u_hard_dphy/mipi_dphy_inst/D1LN_HSRXD[0] u_la0_top/u_ao_mem_ctrl/data_reg_dly_59_s0/D byte_clk:[R] byte_clk:[R] 0.000 0.000 0.064
2 0.063 u_hard_dphy/mipi_dphy_inst/D1LN_HSRXD[4] u_la0_top/u_ao_mem_ctrl/data_reg_dly_63_s0/D byte_clk:[R] byte_clk:[R] 0.000 0.000 0.064
3 0.063 u_hard_dphy/mipi_dphy_inst/D1LN_HSRXD[5] u_la0_top/u_ao_mem_ctrl/data_reg_dly_64_s0/D byte_clk:[R] byte_clk:[R] 0.000 0.000 0.064
4 0.063 u_hard_dphy/mipi_dphy_inst/D1LN_HSRXD[6] u_la0_top/u_ao_mem_ctrl/data_reg_dly_65_s0/D byte_clk:[R] byte_clk:[R] 0.000 0.000 0.064
5 0.063 u_hard_dphy/mipi_dphy_inst/D1LN_HSRXD[1] u_la0_top/u_ao_mem_ctrl/data_reg_dly_60_s0/D byte_clk:[R] byte_clk:[R] 0.000 0.000 0.064
6 0.063 u_hard_dphy/mipi_dphy_inst/D1LN_HSRXD[2] u_la0_top/u_ao_mem_ctrl/data_reg_dly_61_s0/D byte_clk:[R] byte_clk:[R] 0.000 0.000 0.064
7 0.063 u_hard_dphy/mipi_dphy_inst/D0LN_HSRXD[0] u_la0_top/u_ao_mem_ctrl/data_reg_dly_67_s0/D byte_clk:[R] byte_clk:[R] 0.000 0.000 0.064
8 0.063 u_hard_dphy/mipi_dphy_inst/D0LN_HSRXD[1] u_la0_top/u_ao_mem_ctrl/data_reg_dly_68_s0/D byte_clk:[R] byte_clk:[R] 0.000 0.000 0.064
9 0.063 u_hard_dphy/mipi_dphy_inst/D0LN_HSRXD[3] u_la0_top/u_ao_mem_ctrl/data_reg_dly_70_s0/D byte_clk:[R] byte_clk:[R] 0.000 0.000 0.064
10 0.063 u_hard_dphy/mipi_dphy_inst/D0LN_HSRXD[4] u_la0_top/u_ao_mem_ctrl/data_reg_dly_71_s0/D byte_clk:[R] byte_clk:[R] 0.000 0.000 0.064
11 0.175 u_la0_top/u_ao_mem_ctrl/data_reg_60_s0/Q u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/DI[6] byte_clk:[R] byte_clk:[R] 0.000 0.000 0.424
12 0.175 u_la0_top/u_ao_mem_ctrl/data_reg_59_s0/Q u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/DI[5] byte_clk:[R] byte_clk:[R] 0.000 0.000 0.424
13 0.254 u_b2p/u_b2p_inst/rBufD_2_s1/Q u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s/DI[2] byte_clk:[R] byte_clk:[R] 0.000 -0.018 0.520
14 0.271 u_la0_top/u_ao_mem_ctrl/data_reg_21_s0/Q u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[3] byte_clk:[R] byte_clk:[R] 0.000 0.000 0.520
15 0.297 u_hard_dphy/mipi_dphy_inst/D1LN_HSRXD[3] u_la0_top/u_ao_mem_ctrl/data_reg_dly_62_s0/D byte_clk:[R] byte_clk:[R] 0.000 0.000 0.064
16 0.297 u_hard_dphy/mipi_dphy_inst/D1LN_HSRXD[7] u_la0_top/u_ao_mem_ctrl/data_reg_dly_66_s0/D byte_clk:[R] byte_clk:[R] 0.000 0.000 0.064
17 0.297 u_hard_dphy/mipi_dphy_inst/D0LN_HSRXD[5] u_la0_top/u_ao_mem_ctrl/data_reg_dly_72_s0/D byte_clk:[R] byte_clk:[R] 0.000 0.000 0.064
18 0.297 u_hard_dphy/mipi_dphy_inst/D0LN_HSRXD[6] u_la0_top/u_ao_mem_ctrl/data_reg_dly_73_s0/D byte_clk:[R] byte_clk:[R] 0.000 0.000 0.064
19 0.297 u_hard_dphy/mipi_dphy_inst/D0LN_HSRXD[7] u_la0_top/u_ao_mem_ctrl/data_reg_dly_74_s0/D byte_clk:[R] byte_clk:[R] 0.000 0.000 0.064
20 0.297 u_hard_dphy/mipi_dphy_inst/D0LN_HSRXD_VLD u_la0_top/u_ao_mem_ctrl/data_reg_dly_75_s0/D byte_clk:[R] byte_clk:[R] 0.000 0.000 0.064

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 3.559 u_la0_top/rst_ao_s0/Q u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/CLEAR byte_clk:[F] byte_clk:[R] 7.500 0.000 3.594
2 3.559 u_la0_top/rst_ao_s0/Q u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR byte_clk:[F] byte_clk:[R] 7.500 0.000 3.594
3 3.559 u_la0_top/rst_ao_s0/Q u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR byte_clk:[F] byte_clk:[R] 7.500 0.000 3.594
4 3.559 u_la0_top/rst_ao_s0/Q u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/CLEAR byte_clk:[F] byte_clk:[R] 7.500 0.000 3.594
5 3.559 u_la0_top/rst_ao_s0/Q u_la0_top/u_ao_mem_ctrl/capture_length_zero_flag_s0/CLEAR byte_clk:[F] byte_clk:[R] 7.500 0.000 3.594
6 3.559 u_la0_top/rst_ao_s0/Q u_la0_top/capture_end_dly_s0/PRESET byte_clk:[F] byte_clk:[R] 7.500 0.000 3.594
7 3.559 u_la0_top/rst_ao_s0/Q u_la0_top/internal_reg_start_dly_0_s0/CLEAR byte_clk:[F] byte_clk:[R] 7.500 0.000 3.594
8 3.562 u_la0_top/rst_ao_s0/Q u_la0_top/u_ao_match_2/trig_dly_in_0_s0/CLEAR byte_clk:[F] byte_clk:[R] 7.500 0.000 3.590
9 3.562 u_la0_top/rst_ao_s0/Q u_la0_top/u_ao_match_2/trig_dly_in_1_s0/CLEAR byte_clk:[F] byte_clk:[R] 7.500 0.000 3.590
10 3.562 u_la0_top/rst_ao_s0/Q u_la0_top/u_ao_match_2/trig_dly_in_2_s0/CLEAR byte_clk:[F] byte_clk:[R] 7.500 0.000 3.590
11 3.562 u_la0_top/rst_ao_s0/Q u_la0_top/u_ao_match_2/trig_dly_in_3_s0/CLEAR byte_clk:[F] byte_clk:[R] 7.500 0.000 3.590
12 3.562 u_la0_top/rst_ao_s0/Q u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR byte_clk:[F] byte_clk:[R] 7.500 0.000 3.590
13 3.562 u_la0_top/rst_ao_s0/Q u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR byte_clk:[F] byte_clk:[R] 7.500 0.000 3.590
14 3.562 u_la0_top/rst_ao_s0/Q u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR byte_clk:[F] byte_clk:[R] 7.500 0.000 3.590
15 3.562 u_la0_top/rst_ao_s0/Q u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR byte_clk:[F] byte_clk:[R] 7.500 0.000 3.590
16 3.562 u_la0_top/rst_ao_s0/Q u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR byte_clk:[F] byte_clk:[R] 7.500 0.000 3.590
17 3.602 u_la0_top/rst_ao_s0/Q u_la0_top/capture_window_sel_3_s1/CLEAR byte_clk:[F] byte_clk:[R] 7.500 0.000 3.551
18 3.602 u_la0_top/rst_ao_s0/Q u_la0_top/trigger_seq_start_s1/CLEAR byte_clk:[F] byte_clk:[R] 7.500 0.000 3.551
19 3.602 u_la0_top/rst_ao_s0/Q u_la0_top/internal_reg_start_dly_1_s0/CLEAR byte_clk:[F] byte_clk:[R] 7.500 0.000 3.551
20 3.602 u_la0_top/rst_ao_s0/Q u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR byte_clk:[F] byte_clk:[R] 7.500 0.000 3.551
21 3.604 u_la0_top/rst_ao_s0/Q u_la0_top/triger_level_cnt_0_s3/CLEAR byte_clk:[F] byte_clk:[R] 7.500 0.000 3.548
22 3.604 u_la0_top/rst_ao_s0/Q u_la0_top/triger_s0/CLEAR byte_clk:[F] byte_clk:[R] 7.500 0.000 3.548
23 3.604 u_la0_top/rst_ao_s0/Q u_la0_top/start_reg_s0/CLEAR byte_clk:[F] byte_clk:[R] 7.500 0.000 3.548
24 3.605 u_la0_top/rst_ao_s0/Q u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR byte_clk:[F] byte_clk:[R] 7.500 0.000 3.547
25 3.605 u_la0_top/rst_ao_s0/Q u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR byte_clk:[F] byte_clk:[R] 7.500 0.000 3.547

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 1.639 u_ov5647_ctrl/resend_s0/Q u_ov5647_ctrl/I2C/busy_sr_0_s1/CLEAR clk_50:[R] clk_50:[R] 0.000 -0.018 1.468
2 1.639 u_ov5647_ctrl/resend_s0/Q u_ov5647_ctrl/I2C/busy_sr_1_s1/CLEAR clk_50:[R] clk_50:[R] 0.000 -0.018 1.468
3 1.639 u_ov5647_ctrl/resend_s0/Q u_ov5647_ctrl/I2C/busy_sr_2_s1/CLEAR clk_50:[R] clk_50:[R] 0.000 -0.020 1.470
4 1.639 u_ov5647_ctrl/resend_s0/Q u_ov5647_ctrl/I2C/data_sr_6_s1/PRESET clk_50:[R] clk_50:[R] 0.000 -0.017 1.467
5 1.639 u_ov5647_ctrl/resend_s0/Q u_ov5647_ctrl/I2C/data_sr_23_s1/PRESET clk_50:[R] clk_50:[R] 0.000 -0.017 1.467
6 1.639 u_ov5647_ctrl/resend_s0/Q u_ov5647_ctrl/I2C/data_sr_24_s1/PRESET clk_50:[R] clk_50:[R] 0.000 -0.017 1.467
7 1.639 u_ov5647_ctrl/resend_s0/Q u_ov5647_ctrl/I2C/data_sr_29_s1/PRESET clk_50:[R] clk_50:[R] 0.000 -0.017 1.467
8 1.639 u_ov5647_ctrl/resend_s0/Q u_ov5647_ctrl/I2C/data_sr_28_s1/PRESET clk_50:[R] clk_50:[R] 0.000 -0.015 1.465
9 1.640 u_ov5647_ctrl/resend_s0/Q u_ov5647_ctrl/I2C/busy_sr_4_s1/CLEAR clk_50:[R] clk_50:[R] 0.000 -0.042 1.494
10 1.640 u_ov5647_ctrl/resend_s0/Q u_ov5647_ctrl/I2C/busy_sr_5_s1/CLEAR clk_50:[R] clk_50:[R] 0.000 -0.042 1.494
11 1.640 u_ov5647_ctrl/resend_s0/Q u_ov5647_ctrl/I2C/busy_sr_6_s1/CLEAR clk_50:[R] clk_50:[R] 0.000 -0.042 1.494
12 1.640 u_ov5647_ctrl/resend_s0/Q u_ov5647_ctrl/I2C/busy_sr_7_s1/CLEAR clk_50:[R] clk_50:[R] 0.000 -0.042 1.494
13 1.640 u_ov5647_ctrl/resend_s0/Q u_ov5647_ctrl/I2C/busy_sr_8_s1/CLEAR clk_50:[R] clk_50:[R] 0.000 -0.042 1.494
14 1.640 u_ov5647_ctrl/resend_s0/Q u_ov5647_ctrl/I2C/busy_sr_9_s1/CLEAR clk_50:[R] clk_50:[R] 0.000 -0.042 1.494
15 1.640 u_ov5647_ctrl/resend_s0/Q u_ov5647_ctrl/I2C/busy_sr_10_s1/CLEAR clk_50:[R] clk_50:[R] 0.000 -0.042 1.494
16 1.640 u_ov5647_ctrl/resend_s0/Q u_ov5647_ctrl/I2C/busy_sr_12_s1/CLEAR clk_50:[R] clk_50:[R] 0.000 -0.040 1.492
17 1.640 u_ov5647_ctrl/resend_s0/Q u_ov5647_ctrl/I2C/busy_sr_13_s1/CLEAR clk_50:[R] clk_50:[R] 0.000 -0.040 1.492
18 1.640 u_ov5647_ctrl/resend_s0/Q u_ov5647_ctrl/I2C/busy_sr_14_s1/CLEAR clk_50:[R] clk_50:[R] 0.000 -0.040 1.492
19 1.640 u_ov5647_ctrl/resend_s0/Q u_ov5647_ctrl/I2C/busy_sr_20_s1/CLEAR clk_50:[R] clk_50:[R] 0.000 -0.040 1.492
20 1.640 u_ov5647_ctrl/resend_s0/Q u_ov5647_ctrl/I2C/busy_sr_26_s1/CLEAR clk_50:[R] clk_50:[R] 0.000 -0.040 1.492
21 1.640 u_ov5647_ctrl/resend_s0/Q u_ov5647_ctrl/I2C/busy_sr_27_s1/CLEAR clk_50:[R] clk_50:[R] 0.000 -0.040 1.492
22 1.640 u_ov5647_ctrl/resend_s0/Q u_ov5647_ctrl/I2C/busy_sr_28_s1/CLEAR clk_50:[R] clk_50:[R] 0.000 -0.040 1.492
23 1.644 u_ov5647_ctrl/resend_s0/Q u_ov5647_ctrl/I2C/busy_sr_30_s1/CLEAR clk_50:[R] clk_50:[R] 0.000 -0.013 1.468
24 1.644 u_ov5647_ctrl/resend_s0/Q u_ov5647_ctrl/I2C/data_sr_40_s1/PRESET clk_50:[R] clk_50:[R] 0.000 -0.013 1.468
25 1.644 u_ov5647_ctrl/resend_s0/Q u_ov5647_ctrl/I2C/data_sr_34_s1/PRESET clk_50:[R] clk_50:[R] 0.000 -0.013 1.468

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number Slack Actual Width Required Width Type Clock Objects
1 2.249 3.249 1.000 Low Pulse Width pixel_clk u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s
2 2.251 3.251 1.000 High Pulse Width pixel_clk u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s
3 2.253 3.253 1.000 Low Pulse Width pixel_clk u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s
4 2.253 3.253 1.000 Low Pulse Width pixel_clk u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s
5 2.256 3.256 1.000 High Pulse Width pixel_clk u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s
6 2.256 3.256 1.000 High Pulse Width pixel_clk u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s
7 2.994 3.244 0.250 Low Pulse Width pixel_clk u_bayer_rgb/devcnt_9_s1
8 2.994 3.244 0.250 Low Pulse Width pixel_clk u_bayer_rgb/devcnt_1_s1
9 2.994 3.244 0.250 Low Pulse Width pixel_clk u_bayer_rgb/video_format_detect_inst/hcnt_0_s3
10 2.994 3.244 0.250 Low Pulse Width pixel_clk u_bayer_rgb/devcnt_0_s1

Timing Report By Analysis Type:

Setup Analysis Report

Setup Analysis Report[1]:

Report Command:report_timing -setup -from_clock [get_clocks {pixel_clk}] -max_paths 20 -max_common_paths 1

Path1

Path Summary:

Slack 3.107
Data Arrival Time 5.237
Data Required Time 8.344
From u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s
To u_bayer_rgb/r_o_7_s0
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLLA_inst/CLKOUT1
0.869 0.869 tNET RR 8 BSRAM_R28[9] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/CLKB
3.129 2.260 tC2Q RR 2 BSRAM_R28[9] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/DO[7]
3.649 0.520 tNET RR 1 R24C33[3][A] u_bayer_rgb/n305_s2/I1
4.170 0.521 tINS RR 2 R24C33[3][A] u_bayer_rgb/n305_s2/F
4.710 0.540 tNET RR 1 R22C36[0][A] u_bayer_rgb/n297_s1/I0
5.237 0.526 tINS RR 1 R22C36[0][A] u_bayer_rgb/n297_s1/F
5.237 0.000 tNET RR 1 R22C36[0][A] u_bayer_rgb/r_o_7_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 pixel_clk
7.500 0.000 tCL RR 244 PLL_L[0] u_pll/PLLA_inst/CLKOUT1
8.408 0.908 tNET RR 1 R22C36[0][A] u_bayer_rgb/r_o_7_s0/CLK
8.344 -0.064 tSu 1 R22C36[0][A] u_bayer_rgb/r_o_7_s0

Path Statistics:

Clock Skew 0.038
Setup Relationship 7.500
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.869, 100.000%
Arrival Data Path Delay cell: 1.048, 23.984%; route: 1.060, 24.270%; tC2Q: 2.260, 51.746%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.908, 100.000%

Path2

Path Summary:

Slack 3.221
Data Arrival Time 5.120
Data Required Time 8.341
From u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s
To u_bayer_rgb/r_o_5_s0
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLLA_inst/CLKOUT1
0.869 0.869 tNET RR 8 BSRAM_R28[9] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/CLKB
3.129 2.260 tC2Q RR 2 BSRAM_R28[9] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/DO[5]
3.669 0.540 tNET RR 1 R25C34[3][B] u_bayer_rgb/n307_s2/I0
4.084 0.415 tINS RR 2 R25C34[3][B] u_bayer_rgb/n307_s2/F
4.604 0.520 tNET RR 1 R23C36[1][B] u_bayer_rgb/n299_s1/I0
5.120 0.516 tINS RR 1 R23C36[1][B] u_bayer_rgb/n299_s1/F
5.120 0.000 tNET RR 1 R23C36[1][B] u_bayer_rgb/r_o_5_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 pixel_clk
7.500 0.000 tCL RR 244 PLL_L[0] u_pll/PLLA_inst/CLKOUT1
8.405 0.905 tNET RR 1 R23C36[1][B] u_bayer_rgb/r_o_5_s0/CLK
8.341 -0.064 tSu 1 R23C36[1][B] u_bayer_rgb/r_o_5_s0

Path Statistics:

Clock Skew 0.036
Setup Relationship 7.500
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.869, 100.000%
Arrival Data Path Delay cell: 0.931, 21.905%; route: 1.060, 24.934%; tC2Q: 2.260, 53.161%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.905, 100.000%

Path3

Path Summary:

Slack 3.303
Data Arrival Time 5.027
Data Required Time 8.329
From u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s
To u_bayer_rgb/g_o_7_s0
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLLA_inst/CLKOUT1
0.869 0.869 tNET RR 8 BSRAM_R28[9] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/CLKB
3.129 2.260 tC2Q RR 2 BSRAM_R28[9] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/DO[7]
3.649 0.520 tNET RR 1 R24C33[3][A] u_bayer_rgb/n305_s2/I1
4.170 0.521 tINS RR 2 R24C33[3][A] u_bayer_rgb/n305_s2/F
4.500 0.330 tNET RR 1 R24C35[0][A] u_bayer_rgb/n305_s1/I1
5.027 0.526 tINS RR 1 R24C35[0][A] u_bayer_rgb/n305_s1/F
5.027 0.000 tNET RR 1 R24C35[0][A] u_bayer_rgb/g_o_7_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 pixel_clk
7.500 0.000 tCL RR 244 PLL_L[0] u_pll/PLLA_inst/CLKOUT1
8.393 0.893 tNET RR 1 R24C35[0][A] u_bayer_rgb/g_o_7_s0/CLK
8.329 -0.064 tSu 1 R24C35[0][A] u_bayer_rgb/g_o_7_s0

Path Statistics:

Clock Skew 0.024
Setup Relationship 7.500
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.869, 100.000%
Arrival Data Path Delay cell: 1.048, 25.195%; route: 0.850, 20.445%; tC2Q: 2.260, 54.360%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.893, 100.000%

Path4

Path Summary:

Slack 3.372
Data Arrival Time 4.950
Data Required Time 8.322
From u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s
To u_bayer_rgb/r_o_0_s0
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLLA_inst/CLKOUT1
0.869 0.869 tNET RR 8 BSRAM_R28[9] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/CLKB
3.129 2.260 tC2Q RR 2 BSRAM_R28[9] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/DO[0]
3.669 0.540 tNET RR 1 R25C33[2][A] u_bayer_rgb/n312_s2/I0
4.185 0.516 tINS RR 2 R25C33[2][A] u_bayer_rgb/n312_s2/F
4.535 0.350 tNET RR 1 R23C34[3][A] u_bayer_rgb/n304_s1/I0
4.950 0.415 tINS RR 1 R23C34[3][A] u_bayer_rgb/n304_s1/F
4.950 0.000 tNET RR 1 R23C34[3][A] u_bayer_rgb/r_o_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 pixel_clk
7.500 0.000 tCL RR 244 PLL_L[0] u_pll/PLLA_inst/CLKOUT1
8.386 0.886 tNET RR 1 R23C34[3][A] u_bayer_rgb/r_o_0_s0/CLK
8.322 -0.064 tSu 1 R23C34[3][A] u_bayer_rgb/r_o_0_s0

Path Statistics:

Clock Skew 0.017
Setup Relationship 7.500
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.869, 100.000%
Arrival Data Path Delay cell: 0.931, 22.818%; route: 0.890, 21.807%; tC2Q: 2.260, 55.375%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.886, 100.000%

Path5

Path Summary:

Slack 3.453
Data Arrival Time 4.850
Data Required Time 8.303
From u_b2p/u_b2p_inst/u_mid_fifo/rWPtrRsync_5_s0
To u_b2p/u_b2p_inst/u_mid_fifo/rEmpty_s0
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLLA_inst/CLKOUT1
0.857 0.857 tNET RR 1 R14C25[3][B] u_b2p/u_b2p_inst/u_mid_fifo/rWPtrRsync_5_s0/CLK
1.240 0.382 tC2Q RR 3 R14C25[3][B] u_b2p/u_b2p_inst/u_mid_fifo/rWPtrRsync_5_s0/Q
1.572 0.332 tNET RR 1 R15C25[3][B] u_b2p/u_b2p_inst/u_mid_fifo/wWPtrBinX_3_s0/I2
2.070 0.498 tINS RR 6 R15C25[3][B] u_b2p/u_b2p_inst/u_mid_fifo/wWPtrBinX_3_s0/F
2.275 0.205 tNET RR 1 R17C25[1][B] u_b2p/u_b2p_inst/u_mid_fifo/wWPtrBinX_0_s1/I3
2.801 0.526 tINS RR 2 R17C25[1][B] u_b2p/u_b2p_inst/u_mid_fifo/wWPtrBinX_0_s1/F
3.131 0.330 tNET RR 2 R17C26[0][A] u_b2p/u_b2p_inst/u_mid_fifo/n378_s0/I0
3.687 0.556 tINS RF 1 R17C26[0][A] u_b2p/u_b2p_inst/u_mid_fifo/n378_s0/COUT
3.687 0.000 tNET FF 2 R17C26[0][B] u_b2p/u_b2p_inst/u_mid_fifo/n379_s0/CIN
3.737 0.050 tINS FR 1 R17C26[0][B] u_b2p/u_b2p_inst/u_mid_fifo/n379_s0/COUT
3.737 0.000 tNET RR 2 R17C26[1][A] u_b2p/u_b2p_inst/u_mid_fifo/n380_s0/CIN
3.787 0.050 tINS RR 1 R17C26[1][A] u_b2p/u_b2p_inst/u_mid_fifo/n380_s0/COUT
3.787 0.000 tNET RR 2 R17C26[1][B] u_b2p/u_b2p_inst/u_mid_fifo/n381_s0/CIN
3.837 0.050 tINS RR 1 R17C26[1][B] u_b2p/u_b2p_inst/u_mid_fifo/n381_s0/COUT
3.837 0.000 tNET RR 2 R17C26[2][A] u_b2p/u_b2p_inst/u_mid_fifo/n382_s0/CIN
3.887 0.050 tINS RR 1 R17C26[2][A] u_b2p/u_b2p_inst/u_mid_fifo/n382_s0/COUT
3.887 0.000 tNET RR 2 R17C26[2][B] u_b2p/u_b2p_inst/u_mid_fifo/n383_s0/CIN
3.937 0.050 tINS RR 1 R17C26[2][B] u_b2p/u_b2p_inst/u_mid_fifo/n383_s0/COUT
3.937 0.000 tNET RR 2 R17C27[0][A] u_b2p/u_b2p_inst/u_mid_fifo/n384_s0/CIN
3.987 0.050 tINS RR 1 R17C27[0][A] u_b2p/u_b2p_inst/u_mid_fifo/n384_s0/COUT
4.388 0.401 tNET RR 1 R17C27[1][A] u_b2p/u_b2p_inst/u_mid_fifo/n386_s0/I3
4.850 0.461 tINS RR 1 R17C27[1][A] u_b2p/u_b2p_inst/u_mid_fifo/n386_s0/F
4.850 0.000 tNET RR 1 R17C27[1][A] u_b2p/u_b2p_inst/u_mid_fifo/rEmpty_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 pixel_clk
7.500 0.000 tCL RR 244 PLL_L[0] u_pll/PLLA_inst/CLKOUT1
8.367 0.867 tNET RR 1 R17C27[1][A] u_b2p/u_b2p_inst/u_mid_fifo/rEmpty_s0/CLK
8.303 -0.064 tSu 1 R17C27[1][A] u_b2p/u_b2p_inst/u_mid_fifo/rEmpty_s0

Path Statistics:

Clock Skew 0.010
Setup Relationship 7.500
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.857, 100.000%
Arrival Data Path Delay cell: 2.341, 58.641%; route: 1.269, 31.778%; tC2Q: 0.382, 9.580%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.867, 100.000%

Path6

Path Summary:

Slack 3.467
Data Arrival Time 4.863
Data Required Time 8.329
From u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s
To u_bayer_rgb/r_o_2_s0
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLLA_inst/CLKOUT1
0.869 0.869 tNET RR 8 BSRAM_R28[9] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/CLKB
3.129 2.260 tC2Q RR 2 BSRAM_R28[9] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/DO[2]
3.752 0.623 tNET RR 1 R24C35[3][B] u_bayer_rgb/n310_s2/I0
4.017 0.265 tINS RR 2 R24C35[3][B] u_bayer_rgb/n310_s2/F
4.347 0.330 tNET RR 1 R24C37[1][B] u_bayer_rgb/n302_s1/I0
4.863 0.516 tINS RR 1 R24C37[1][B] u_bayer_rgb/n302_s1/F
4.863 0.000 tNET RR 1 R24C37[1][B] u_bayer_rgb/r_o_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 pixel_clk
7.500 0.000 tCL RR 244 PLL_L[0] u_pll/PLLA_inst/CLKOUT1
8.393 0.893 tNET RR 1 R24C37[1][B] u_bayer_rgb/r_o_2_s0/CLK
8.329 -0.064 tSu 1 R24C37[1][B] u_bayer_rgb/r_o_2_s0

Path Statistics:

Clock Skew 0.024
Setup Relationship 7.500
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.869, 100.000%
Arrival Data Path Delay cell: 0.781, 19.562%; route: 0.952, 23.850%; tC2Q: 2.260, 56.588%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.893, 100.000%

Path7

Path Summary:

Slack 3.511
Data Arrival Time 4.807
Data Required Time 8.318
From u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s
To u_bayer_rgb/g_o_0_s0
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLLA_inst/CLKOUT1
0.869 0.869 tNET RR 8 BSRAM_R28[9] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/CLKB
3.129 2.260 tC2Q RR 2 BSRAM_R28[9] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/DO[0]
3.669 0.540 tNET RR 1 R25C33[2][A] u_bayer_rgb/n312_s2/I0
4.185 0.516 tINS RR 2 R25C33[2][A] u_bayer_rgb/n312_s2/F
4.345 0.160 tNET RR 1 R25C34[1][A] u_bayer_rgb/n312_s1/I1
4.807 0.461 tINS RR 1 R25C34[1][A] u_bayer_rgb/n312_s1/F
4.807 0.000 tNET RR 1 R25C34[1][A] u_bayer_rgb/g_o_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 pixel_clk
7.500 0.000 tCL RR 244 PLL_L[0] u_pll/PLLA_inst/CLKOUT1
8.381 0.881 tNET RR 1 R25C34[1][A] u_bayer_rgb/g_o_0_s0/CLK
8.318 -0.064 tSu 1 R25C34[1][A] u_bayer_rgb/g_o_0_s0

Path Statistics:

Clock Skew 0.012
Setup Relationship 7.500
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.869, 100.000%
Arrival Data Path Delay cell: 0.977, 24.825%; route: 0.700, 17.778%; tC2Q: 2.260, 57.397%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.881, 100.000%

Path8

Path Summary:

Slack 3.534
Data Arrival Time 4.798
Data Required Time 8.332
From u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s
To u_bayer_rgb/r_o_6_s0
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLLA_inst/CLKOUT1
0.869 0.869 tNET RR 8 BSRAM_R28[9] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/CLKB
3.129 2.260 tC2Q RR 2 BSRAM_R28[9] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/DO[6]
3.669 0.540 tNET RR 1 R25C35[3][A] u_bayer_rgb/n306_s2/I0
3.959 0.290 tINS RF 2 R25C35[3][A] u_bayer_rgb/n306_s2/F
4.337 0.377 tNET FF 1 R23C37[0][A] u_bayer_rgb/n298_s1/I0
4.798 0.461 tINS FR 1 R23C37[0][A] u_bayer_rgb/n298_s1/F
4.798 0.000 tNET RR 1 R23C37[0][A] u_bayer_rgb/r_o_6_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 pixel_clk
7.500 0.000 tCL RR 244 PLL_L[0] u_pll/PLLA_inst/CLKOUT1
8.396 0.896 tNET RR 1 R23C37[0][A] u_bayer_rgb/r_o_6_s0/CLK
8.332 -0.064 tSu 1 R23C37[0][A] u_bayer_rgb/r_o_6_s0

Path Statistics:

Clock Skew 0.027
Setup Relationship 7.500
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.869, 100.000%
Arrival Data Path Delay cell: 0.751, 19.122%; route: 0.918, 23.353%; tC2Q: 2.260, 57.525%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.896, 100.000%

Path9

Path Summary:

Slack 3.541
Data Arrival Time 4.798
Data Required Time 8.339
From u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s
To u_bayer_rgb/r_o_3_s0
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLLA_inst/CLKOUT1
0.869 0.869 tNET RR 8 BSRAM_R28[9] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/CLKB
3.129 2.260 tC2Q RR 2 BSRAM_R28[9] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/DO[3]
3.669 0.540 tNET RR 1 R25C34[0][A] u_bayer_rgb/n309_s2/I0
3.932 0.262 tINS RR 2 R25C34[0][A] u_bayer_rgb/n309_s2/F
4.282 0.350 tNET RR 1 R24C36[1][A] u_bayer_rgb/n301_s1/I0
4.798 0.516 tINS RR 1 R24C36[1][A] u_bayer_rgb/n301_s1/F
4.798 0.000 tNET RR 1 R24C36[1][A] u_bayer_rgb/r_o_3_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 pixel_clk
7.500 0.000 tCL RR 244 PLL_L[0] u_pll/PLLA_inst/CLKOUT1
8.403 0.902 tNET RR 1 R24C36[1][A] u_bayer_rgb/r_o_3_s0/CLK
8.339 -0.064 tSu 1 R24C36[1][A] u_bayer_rgb/r_o_3_s0

Path Statistics:

Clock Skew 0.033
Setup Relationship 7.500
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.869, 100.000%
Arrival Data Path Delay cell: 0.779, 19.822%; route: 0.890, 22.654%; tC2Q: 2.260, 57.525%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Path10

Path Summary:

Slack 3.544
Data Arrival Time 4.788
Data Required Time 8.332
From u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s
To u_bayer_rgb/g_o_2_s0
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLLA_inst/CLKOUT1
0.869 0.869 tNET RR 8 BSRAM_R28[9] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/CLKB
3.129 2.260 tC2Q RR 2 BSRAM_R28[9] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/DO[2]
3.752 0.623 tNET RR 1 R24C35[3][B] u_bayer_rgb/n310_s2/I0
4.042 0.290 tINS RF 2 R24C35[3][B] u_bayer_rgb/n310_s2/F
4.373 0.331 tNET FF 1 R23C37[3][A] u_bayer_rgb/n310_s1/I1
4.788 0.415 tINS FR 1 R23C37[3][A] u_bayer_rgb/n310_s1/F
4.788 0.000 tNET RR 1 R23C37[3][A] u_bayer_rgb/g_o_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 pixel_clk
7.500 0.000 tCL RR 244 PLL_L[0] u_pll/PLLA_inst/CLKOUT1
8.396 0.896 tNET RR 1 R23C37[3][A] u_bayer_rgb/g_o_2_s0/CLK
8.332 -0.064 tSu 1 R23C37[3][A] u_bayer_rgb/g_o_2_s0

Path Statistics:

Clock Skew 0.027
Setup Relationship 7.500
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.869, 100.000%
Arrival Data Path Delay cell: 0.705, 17.990%; route: 0.954, 24.338%; tC2Q: 2.260, 57.671%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.896, 100.000%

Path11

Path Summary:

Slack 3.587
Data Arrival Time 4.743
Data Required Time 8.329
From u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s
To u_bayer_rgb/g_o_3_s0
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLLA_inst/CLKOUT1
0.869 0.869 tNET RR 8 BSRAM_R28[9] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/CLKB
3.129 2.260 tC2Q RR 2 BSRAM_R28[9] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/DO[3]
3.669 0.540 tNET RR 1 R25C34[0][A] u_bayer_rgb/n309_s2/I0
3.932 0.262 tINS RR 2 R25C34[0][A] u_bayer_rgb/n309_s2/F
4.282 0.350 tNET RR 1 R24C35[2][A] u_bayer_rgb/n309_s1/I1
4.743 0.461 tINS RR 1 R24C35[2][A] u_bayer_rgb/n309_s1/F
4.743 0.000 tNET RR 1 R24C35[2][A] u_bayer_rgb/g_o_3_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 pixel_clk
7.500 0.000 tCL RR 244 PLL_L[0] u_pll/PLLA_inst/CLKOUT1
8.393 0.893 tNET RR 1 R24C35[2][A] u_bayer_rgb/g_o_3_s0/CLK
8.329 -0.064 tSu 1 R24C35[2][A] u_bayer_rgb/g_o_3_s0

Path Statistics:

Clock Skew 0.024
Setup Relationship 7.500
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.869, 100.000%
Arrival Data Path Delay cell: 0.724, 18.683%; route: 0.890, 22.975%; tC2Q: 2.260, 58.341%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.893, 100.000%

Path12

Path Summary:

Slack 3.633
Data Arrival Time 4.697
Data Required Time 8.329
From u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s
To u_bayer_rgb/g_o_5_s0
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLLA_inst/CLKOUT1
0.869 0.869 tNET RR 8 BSRAM_R28[9] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/CLKB
3.129 2.260 tC2Q RR 2 BSRAM_R28[9] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/DO[5]
3.669 0.540 tNET RR 1 R25C34[3][B] u_bayer_rgb/n307_s2/I0
4.084 0.415 tINS RR 2 R25C34[3][B] u_bayer_rgb/n307_s2/F
4.434 0.350 tNET RR 1 R24C35[1][A] u_bayer_rgb/n307_s1/I1
4.697 0.262 tINS RR 1 R24C35[1][A] u_bayer_rgb/n307_s1/F
4.697 0.000 tNET RR 1 R24C35[1][A] u_bayer_rgb/g_o_5_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 pixel_clk
7.500 0.000 tCL RR 244 PLL_L[0] u_pll/PLLA_inst/CLKOUT1
8.393 0.893 tNET RR 1 R24C35[1][A] u_bayer_rgb/g_o_5_s0/CLK
8.329 -0.064 tSu 1 R24C35[1][A] u_bayer_rgb/g_o_5_s0

Path Statistics:

Clock Skew 0.024
Setup Relationship 7.500
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.869, 100.000%
Arrival Data Path Delay cell: 0.678, 17.701%; route: 0.890, 23.253%; tC2Q: 2.260, 59.046%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.893, 100.000%

Path13

Path Summary:

Slack 3.638
Data Arrival Time 4.692
Data Required Time 8.329
From u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s
To u_bayer_rgb/g_o_4_s0
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLLA_inst/CLKOUT1
0.869 0.869 tNET RR 8 BSRAM_R28[9] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/CLKB
3.129 2.260 tC2Q RF 2 BSRAM_R28[9] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/DO[4]
3.600 0.471 tNET FF 1 R24C34[3][A] u_bayer_rgb/n308_s2/I0
4.015 0.415 tINS FR 2 R24C34[3][A] u_bayer_rgb/n308_s2/F
4.175 0.160 tNET RR 1 R24C35[1][B] u_bayer_rgb/n308_s1/I1
4.692 0.516 tINS RR 1 R24C35[1][B] u_bayer_rgb/n308_s1/F
4.692 0.000 tNET RR 1 R24C35[1][B] u_bayer_rgb/g_o_4_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 pixel_clk
7.500 0.000 tCL RR 244 PLL_L[0] u_pll/PLLA_inst/CLKOUT1
8.393 0.893 tNET RR 1 R24C35[1][B] u_bayer_rgb/g_o_4_s0/CLK
8.329 -0.064 tSu 1 R24C35[1][B] u_bayer_rgb/g_o_4_s0

Path Statistics:

Clock Skew 0.024
Setup Relationship 7.500
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.869, 100.000%
Arrival Data Path Delay cell: 0.931, 24.362%; route: 0.631, 16.514%; tC2Q: 2.260, 59.124%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.893, 100.000%

Path14

Path Summary:

Slack 3.713
Data Arrival Time 4.628
Data Required Time 8.341
From u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s
To u_bayer_rgb/r_o_4_s0
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLLA_inst/CLKOUT1
0.869 0.869 tNET RR 8 BSRAM_R28[9] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/CLKB
3.129 2.260 tC2Q RF 2 BSRAM_R28[9] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/DO[4]
3.600 0.471 tNET FF 1 R24C34[3][A] u_bayer_rgb/n308_s2/I0
4.015 0.415 tINS FR 2 R24C34[3][A] u_bayer_rgb/n308_s2/F
4.365 0.350 tNET RR 1 R23C36[0][B] u_bayer_rgb/n300_s1/I0
4.628 0.262 tINS RR 1 R23C36[0][B] u_bayer_rgb/n300_s1/F
4.628 0.000 tNET RR 1 R23C36[0][B] u_bayer_rgb/r_o_4_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 pixel_clk
7.500 0.000 tCL RR 244 PLL_L[0] u_pll/PLLA_inst/CLKOUT1
8.405 0.905 tNET RR 1 R23C36[0][B] u_bayer_rgb/r_o_4_s0/CLK
8.341 -0.064 tSu 1 R23C36[0][B] u_bayer_rgb/r_o_4_s0

Path Statistics:

Clock Skew 0.036
Setup Relationship 7.500
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.869, 100.000%
Arrival Data Path Delay cell: 0.678, 18.025%; route: 0.821, 21.849%; tC2Q: 2.260, 60.126%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.905, 100.000%

Path15

Path Summary:

Slack 3.729
Data Arrival Time 4.562
Data Required Time 8.291
From u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s
To u_b2p/u_b2p_inst/pixel_data_r_7_s0
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLLA_inst/CLKOUT1
0.869 0.869 tNET RR 16 BSRAM_R10[7] u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s/CLKB
3.129 2.260 tC2Q RR 1 BSRAM_R10[7] u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s/DO[7]
4.035 0.906 tNET RR 1 R12C28[2][A] u_b2p/u_b2p_inst/n5318_s3/I0
4.562 0.526 tINS RR 1 R12C28[2][A] u_b2p/u_b2p_inst/n5318_s3/F
4.562 0.000 tNET RR 1 R12C28[2][A] u_b2p/u_b2p_inst/pixel_data_r_7_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 pixel_clk
7.500 0.000 tCL RR 244 PLL_L[0] u_pll/PLLA_inst/CLKOUT1
8.355 0.855 tNET RR 1 R12C28[2][A] u_b2p/u_b2p_inst/pixel_data_r_7_s0/CLK
8.291 -0.064 tSu 1 R12C28[2][A] u_b2p/u_b2p_inst/pixel_data_r_7_s0

Path Statistics:

Clock Skew -0.014
Setup Relationship 7.500
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.869, 100.000%
Arrival Data Path Delay cell: 0.526, 14.252%; route: 0.906, 24.543%; tC2Q: 2.260, 61.205%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.855, 100.000%

Path16

Path Summary:

Slack 3.790
Data Arrival Time 4.539
Data Required Time 8.329
From u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s
To u_bayer_rgb/g_o_1_s0
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLLA_inst/CLKOUT1
0.869 0.869 tNET RR 8 BSRAM_R28[9] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/CLKB
3.129 2.260 tC2Q RF 2 BSRAM_R28[9] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/DO[1]
3.604 0.475 tNET FF 1 R24C34[3][B] u_bayer_rgb/n311_s2/I0
3.894 0.290 tINS FF 2 R24C34[3][B] u_bayer_rgb/n311_s2/F
4.042 0.147 tNET FF 1 R24C35[3][A] u_bayer_rgb/n311_s1/I1
4.539 0.498 tINS FR 1 R24C35[3][A] u_bayer_rgb/n311_s1/F
4.539 0.000 tNET RR 1 R24C35[3][A] u_bayer_rgb/g_o_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 pixel_clk
7.500 0.000 tCL RR 244 PLL_L[0] u_pll/PLLA_inst/CLKOUT1
8.393 0.893 tNET RR 1 R24C35[3][A] u_bayer_rgb/g_o_1_s0/CLK
8.329 -0.064 tSu 1 R24C35[3][A] u_bayer_rgb/g_o_1_s0

Path Statistics:

Clock Skew 0.024
Setup Relationship 7.500
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.869, 100.000%
Arrival Data Path Delay cell: 0.788, 21.458%; route: 0.622, 16.962%; tC2Q: 2.260, 61.580%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.893, 100.000%

Path17

Path Summary:

Slack 3.842
Data Arrival Time 4.488
Data Required Time 8.329
From u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s
To u_bayer_rgb/r_o_1_s0
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLLA_inst/CLKOUT1
0.869 0.869 tNET RR 8 BSRAM_R28[9] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/CLKB
3.129 2.260 tC2Q RF 2 BSRAM_R28[9] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/DO[1]
3.604 0.475 tNET FF 1 R24C34[3][B] u_bayer_rgb/n311_s2/I0
3.894 0.290 tINS FF 2 R24C34[3][B] u_bayer_rgb/n311_s2/F
4.225 0.331 tNET FF 1 R24C37[0][B] u_bayer_rgb/n303_s1/I0
4.488 0.262 tINS FR 1 R24C37[0][B] u_bayer_rgb/n303_s1/F
4.488 0.000 tNET RR 1 R24C37[0][B] u_bayer_rgb/r_o_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 pixel_clk
7.500 0.000 tCL RR 244 PLL_L[0] u_pll/PLLA_inst/CLKOUT1
8.393 0.893 tNET RR 1 R24C37[0][B] u_bayer_rgb/r_o_1_s0/CLK
8.329 -0.064 tSu 1 R24C37[0][B] u_bayer_rgb/r_o_1_s0

Path Statistics:

Clock Skew 0.024
Setup Relationship 7.500
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.869, 100.000%
Arrival Data Path Delay cell: 0.553, 15.268%; route: 0.806, 22.280%; tC2Q: 2.260, 62.452%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.893, 100.000%

Path18

Path Summary:

Slack 3.907
Data Arrival Time 4.371
Data Required Time 8.278
From u_b2p/u_b2p_inst/u_mid_fifo/rWPtrRsync_5_s0
To u_b2p/u_b2p_inst/u_mid_fifo/rRdDiff_6_s0
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLLA_inst/CLKOUT1
0.857 0.857 tNET RR 1 R14C25[3][B] u_b2p/u_b2p_inst/u_mid_fifo/rWPtrRsync_5_s0/CLK
1.240 0.382 tC2Q RR 3 R14C25[3][B] u_b2p/u_b2p_inst/u_mid_fifo/rWPtrRsync_5_s0/Q
1.572 0.332 tNET RR 1 R15C25[3][B] u_b2p/u_b2p_inst/u_mid_fifo/wWPtrBinX_3_s0/I2
2.070 0.498 tINS RR 6 R15C25[3][B] u_b2p/u_b2p_inst/u_mid_fifo/wWPtrBinX_3_s0/F
2.275 0.205 tNET RR 1 R17C25[1][B] u_b2p/u_b2p_inst/u_mid_fifo/wWPtrBinX_0_s1/I3
2.801 0.526 tINS RR 2 R17C25[1][B] u_b2p/u_b2p_inst/u_mid_fifo/wWPtrBinX_0_s1/F
3.321 0.520 tNET RR 2 R13C25[0][A] u_b2p/u_b2p_inst/u_mid_fifo/wRdDiff_0_s/I0
3.877 0.556 tINS RF 1 R13C25[0][A] u_b2p/u_b2p_inst/u_mid_fifo/wRdDiff_0_s/COUT
3.877 0.000 tNET FF 2 R13C25[0][B] u_b2p/u_b2p_inst/u_mid_fifo/wRdDiff_1_s/CIN
3.927 0.050 tINS FR 1 R13C25[0][B] u_b2p/u_b2p_inst/u_mid_fifo/wRdDiff_1_s/COUT
3.927 0.000 tNET RR 2 R13C25[1][A] u_b2p/u_b2p_inst/u_mid_fifo/wRdDiff_2_s/CIN
3.977 0.050 tINS RR 1 R13C25[1][A] u_b2p/u_b2p_inst/u_mid_fifo/wRdDiff_2_s/COUT
3.977 0.000 tNET RR 2 R13C25[1][B] u_b2p/u_b2p_inst/u_mid_fifo/wRdDiff_3_s/CIN
4.027 0.050 tINS RR 1 R13C25[1][B] u_b2p/u_b2p_inst/u_mid_fifo/wRdDiff_3_s/COUT
4.027 0.000 tNET RR 2 R13C25[2][A] u_b2p/u_b2p_inst/u_mid_fifo/wRdDiff_4_s/CIN
4.077 0.050 tINS RR 1 R13C25[2][A] u_b2p/u_b2p_inst/u_mid_fifo/wRdDiff_4_s/COUT
4.077 0.000 tNET RR 2 R13C25[2][B] u_b2p/u_b2p_inst/u_mid_fifo/wRdDiff_5_s/CIN
4.127 0.050 tINS RR 1 R13C25[2][B] u_b2p/u_b2p_inst/u_mid_fifo/wRdDiff_5_s/COUT
4.127 0.000 tNET RR 2 R13C26[0][A] u_b2p/u_b2p_inst/u_mid_fifo/wRdDiff_6_s/CIN
4.371 0.244 tINS RR 1 R13C26[0][A] u_b2p/u_b2p_inst/u_mid_fifo/wRdDiff_6_s/SUM
4.371 0.000 tNET RR 1 R13C26[0][A] u_b2p/u_b2p_inst/u_mid_fifo/rRdDiff_6_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 pixel_clk
7.500 0.000 tCL RR 244 PLL_L[0] u_pll/PLLA_inst/CLKOUT1
8.342 0.842 tNET RR 1 R13C26[0][A] u_b2p/u_b2p_inst/u_mid_fifo/rRdDiff_6_s0/CLK
8.278 -0.064 tSu 1 R13C26[0][A] u_b2p/u_b2p_inst/u_mid_fifo/rRdDiff_6_s0

Path Statistics:

Clock Skew -0.015
Setup Relationship 7.500
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.857, 100.000%
Arrival Data Path Delay cell: 2.074, 59.018%; route: 1.057, 30.096%; tC2Q: 0.382, 10.886%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.842, 100.000%

Path19

Path Summary:

Slack 3.912
Data Arrival Time 4.379
Data Required Time 8.291
From u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s
To u_b2p/u_b2p_inst/pixel_data_r_1_s0
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLLA_inst/CLKOUT1
0.869 0.869 tNET RR 16 BSRAM_R10[7] u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s/CLKB
3.129 2.260 tC2Q RR 1 BSRAM_R10[7] u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s/DO[1]
3.863 0.734 tNET RR 1 R12C28[1][A] u_b2p/u_b2p_inst/n5324_s1/I0
4.379 0.516 tINS RR 1 R12C28[1][A] u_b2p/u_b2p_inst/n5324_s1/F
4.379 0.000 tNET RR 1 R12C28[1][A] u_b2p/u_b2p_inst/pixel_data_r_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 pixel_clk
7.500 0.000 tCL RR 244 PLL_L[0] u_pll/PLLA_inst/CLKOUT1
8.355 0.855 tNET RR 1 R12C28[1][A] u_b2p/u_b2p_inst/pixel_data_r_1_s0/CLK
8.291 -0.064 tSu 1 R12C28[1][A] u_b2p/u_b2p_inst/pixel_data_r_1_s0

Path Statistics:

Clock Skew -0.014
Setup Relationship 7.500
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.869, 100.000%
Arrival Data Path Delay cell: 0.516, 14.708%; route: 0.734, 20.905%; tC2Q: 2.260, 64.387%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.855, 100.000%

Path20

Path Summary:

Slack 3.912
Data Arrival Time 4.379
Data Required Time 8.291
From u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s
To u_b2p/u_b2p_inst/pixel_data_r_3_s0
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLLA_inst/CLKOUT1
0.869 0.869 tNET RR 16 BSRAM_R10[7] u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s/CLKB
3.129 2.260 tC2Q RR 1 BSRAM_R10[7] u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s/DO[3]
3.863 0.734 tNET RR 1 R12C28[1][B] u_b2p/u_b2p_inst/n5322_s1/I0
4.379 0.516 tINS RR 1 R12C28[1][B] u_b2p/u_b2p_inst/n5322_s1/F
4.379 0.000 tNET RR 1 R12C28[1][B] u_b2p/u_b2p_inst/pixel_data_r_3_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 pixel_clk
7.500 0.000 tCL RR 244 PLL_L[0] u_pll/PLLA_inst/CLKOUT1
8.355 0.855 tNET RR 1 R12C28[1][B] u_b2p/u_b2p_inst/pixel_data_r_3_s0/CLK
8.291 -0.064 tSu 1 R12C28[1][B] u_b2p/u_b2p_inst/pixel_data_r_3_s0

Path Statistics:

Clock Skew -0.014
Setup Relationship 7.500
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.869, 100.000%
Arrival Data Path Delay cell: 0.516, 14.708%; route: 0.734, 20.905%; tC2Q: 2.260, 64.387%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.855, 100.000%

Setup Analysis Report[2]:

Report Command:report_timing -setup -from_clock [get_clocks {byte_clk}] -max_paths 20 -max_common_paths 1

Path1

Path Summary:

Slack 7.116
Data Arrival Time 8.408
Data Required Time 15.525
From odt_en_msk_s0
To hsrx_cnt_0_s1
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 681 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
0.836 0.836 tNET RR 1 R12C25[2][B] odt_en_msk_s0/CLK
1.218 0.382 tC2Q RR 5 R12C25[2][B] odt_en_msk_s0/Q
3.818 2.600 tNET RR 1 R26C2[2][A] odt_en_1_s0/I2
4.081 0.262 tINS RR 3 R26C2[2][A] odt_en_1_s0/F
5.905 1.824 tNET RR 1 R12C2[0][A] hsrx_cnt_5_s6/I3
6.366 0.461 tINS RR 7 R12C2[0][A] hsrx_cnt_5_s6/F
7.581 1.215 tNET RR 1 R11C25[3][B] hsrx_cnt_5_s8/I3
8.078 0.498 tINS RR 4 R11C25[3][B] hsrx_cnt_5_s8/F
8.408 0.330 tNET RR 1 R12C25[0][A] hsrx_cnt_0_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
15.836 0.836 tNET RR 1 R12C25[0][A] hsrx_cnt_0_s1/CLK
15.525 -0.311 tSu 1 R12C25[0][A] hsrx_cnt_0_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 15.000
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.836, 100.000%
Arrival Data Path Delay cell: 1.221, 16.127%; route: 5.969, 78.821%; tC2Q: 0.382, 5.051%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.836, 100.000%

Path2

Path Summary:

Slack 7.320
Data Arrival Time 8.221
Data Required Time 15.541
From odt_en_msk_s0
To hsrx_cnt_1_s1
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 681 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
0.836 0.836 tNET RR 1 R12C25[2][B] odt_en_msk_s0/CLK
1.218 0.382 tC2Q RR 5 R12C25[2][B] odt_en_msk_s0/Q
3.818 2.600 tNET RR 1 R26C2[2][A] odt_en_1_s0/I2
4.081 0.262 tINS RR 3 R26C2[2][A] odt_en_1_s0/F
5.905 1.824 tNET RR 1 R12C2[0][A] hsrx_cnt_5_s6/I3
6.366 0.461 tINS RR 7 R12C2[0][A] hsrx_cnt_5_s6/F
7.581 1.215 tNET RR 1 R11C25[3][B] hsrx_cnt_5_s8/I3
8.078 0.498 tINS RR 4 R11C25[3][B] hsrx_cnt_5_s8/F
8.221 0.142 tNET RR 1 R11C25[0][A] hsrx_cnt_1_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
15.852 0.852 tNET RR 1 R11C25[0][A] hsrx_cnt_1_s1/CLK
15.541 -0.311 tSu 1 R11C25[0][A] hsrx_cnt_1_s1

Path Statistics:

Clock Skew 0.017
Setup Relationship 15.000
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.836, 100.000%
Arrival Data Path Delay cell: 1.221, 16.537%; route: 5.781, 78.284%; tC2Q: 0.382, 5.179%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.852, 100.000%

Path3

Path Summary:

Slack 7.320
Data Arrival Time 8.221
Data Required Time 15.541
From odt_en_msk_s0
To hsrx_cnt_2_s1
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 681 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
0.836 0.836 tNET RR 1 R12C25[2][B] odt_en_msk_s0/CLK
1.218 0.382 tC2Q RR 5 R12C25[2][B] odt_en_msk_s0/Q
3.818 2.600 tNET RR 1 R26C2[2][A] odt_en_1_s0/I2
4.081 0.262 tINS RR 3 R26C2[2][A] odt_en_1_s0/F
5.905 1.824 tNET RR 1 R12C2[0][A] hsrx_cnt_5_s6/I3
6.366 0.461 tINS RR 7 R12C2[0][A] hsrx_cnt_5_s6/F
7.581 1.215 tNET RR 1 R11C25[3][B] hsrx_cnt_5_s8/I3
8.078 0.498 tINS RR 4 R11C25[3][B] hsrx_cnt_5_s8/F
8.221 0.142 tNET RR 1 R11C25[0][B] hsrx_cnt_2_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
15.852 0.852 tNET RR 1 R11C25[0][B] hsrx_cnt_2_s1/CLK
15.541 -0.311 tSu 1 R11C25[0][B] hsrx_cnt_2_s1

Path Statistics:

Clock Skew 0.017
Setup Relationship 15.000
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.836, 100.000%
Arrival Data Path Delay cell: 1.221, 16.537%; route: 5.781, 78.284%; tC2Q: 0.382, 5.179%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.852, 100.000%

Path4

Path Summary:

Slack 7.320
Data Arrival Time 8.221
Data Required Time 15.541
From odt_en_msk_s0
To hsrx_cnt_3_s1
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 681 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
0.836 0.836 tNET RR 1 R12C25[2][B] odt_en_msk_s0/CLK
1.218 0.382 tC2Q RR 5 R12C25[2][B] odt_en_msk_s0/Q
3.818 2.600 tNET RR 1 R26C2[2][A] odt_en_1_s0/I2
4.081 0.262 tINS RR 3 R26C2[2][A] odt_en_1_s0/F
5.905 1.824 tNET RR 1 R12C2[0][A] hsrx_cnt_5_s6/I3
6.366 0.461 tINS RR 7 R12C2[0][A] hsrx_cnt_5_s6/F
7.581 1.215 tNET RR 1 R11C25[3][B] hsrx_cnt_5_s8/I3
8.078 0.498 tINS RR 4 R11C25[3][B] hsrx_cnt_5_s8/F
8.221 0.142 tNET RR 1 R11C25[1][A] hsrx_cnt_3_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
15.852 0.852 tNET RR 1 R11C25[1][A] hsrx_cnt_3_s1/CLK
15.541 -0.311 tSu 1 R11C25[1][A] hsrx_cnt_3_s1

Path Statistics:

Clock Skew 0.017
Setup Relationship 15.000
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.836, 100.000%
Arrival Data Path Delay cell: 1.221, 16.537%; route: 5.781, 78.284%; tC2Q: 0.382, 5.179%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.852, 100.000%

Path5

Path Summary:

Slack 7.682
Data Arrival Time 8.107
Data Required Time 15.789
From odt_en_msk_s0
To hsrx_cnt_4_s3
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 681 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
0.836 0.836 tNET RR 1 R12C25[2][B] odt_en_msk_s0/CLK
1.218 0.382 tC2Q RR 5 R12C25[2][B] odt_en_msk_s0/Q
3.818 2.600 tNET RR 1 R26C2[2][A] odt_en_1_s0/I2
4.081 0.262 tINS RR 3 R26C2[2][A] odt_en_1_s0/F
5.905 1.824 tNET RR 1 R12C2[0][A] hsrx_cnt_5_s6/I3
6.366 0.461 tINS RR 7 R12C2[0][A] hsrx_cnt_5_s6/F
7.581 1.215 tNET RR 1 R11C25[2][B] n208_s4/I3
8.107 0.526 tINS RR 1 R11C25[2][B] n208_s4/F
8.107 0.000 tNET RR 1 R11C25[2][B] hsrx_cnt_4_s3/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
15.852 0.852 tNET RR 1 R11C25[2][B] hsrx_cnt_4_s3/CLK
15.789 -0.064 tSu 1 R11C25[2][B] hsrx_cnt_4_s3

Path Statistics:

Clock Skew 0.017
Setup Relationship 15.000
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.836, 100.000%
Arrival Data Path Delay cell: 1.250, 17.191%; route: 5.639, 77.549%; tC2Q: 0.382, 5.260%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.852, 100.000%

Path6

Path Summary:

Slack 7.682
Data Arrival Time 8.107
Data Required Time 15.789
From odt_en_msk_s0
To hsrx_cnt_5_s7
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 681 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
0.836 0.836 tNET RR 1 R12C25[2][B] odt_en_msk_s0/CLK
1.218 0.382 tC2Q RR 5 R12C25[2][B] odt_en_msk_s0/Q
3.818 2.600 tNET RR 1 R26C2[2][A] odt_en_1_s0/I2
4.081 0.262 tINS RR 3 R26C2[2][A] odt_en_1_s0/F
5.905 1.824 tNET RR 1 R12C2[0][A] hsrx_cnt_5_s6/I3
6.366 0.461 tINS RR 7 R12C2[0][A] hsrx_cnt_5_s6/F
7.581 1.215 tNET RR 1 R11C25[2][A] n207_s4/I3
8.107 0.526 tINS RR 1 R11C25[2][A] n207_s4/F
8.107 0.000 tNET RR 1 R11C25[2][A] hsrx_cnt_5_s7/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
15.852 0.852 tNET RR 1 R11C25[2][A] hsrx_cnt_5_s7/CLK
15.789 -0.064 tSu 1 R11C25[2][A] hsrx_cnt_5_s7

Path Statistics:

Clock Skew 0.017
Setup Relationship 15.000
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.836, 100.000%
Arrival Data Path Delay cell: 1.250, 17.191%; route: 5.639, 77.549%; tC2Q: 0.382, 5.260%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.852, 100.000%

Path7

Path Summary:

Slack 7.682
Data Arrival Time 8.107
Data Required Time 15.789
From odt_en_msk_s0
To hsrx_cnt_1_s1
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 681 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
0.836 0.836 tNET RR 1 R12C25[2][B] odt_en_msk_s0/CLK
1.218 0.382 tC2Q RR 5 R12C25[2][B] odt_en_msk_s0/Q
3.818 2.600 tNET RR 1 R26C2[2][A] odt_en_1_s0/I2
4.081 0.262 tINS RR 3 R26C2[2][A] odt_en_1_s0/F
5.905 1.824 tNET RR 1 R12C2[0][A] hsrx_cnt_5_s6/I3
6.366 0.461 tINS RR 7 R12C2[0][A] hsrx_cnt_5_s6/F
7.581 1.215 tNET RR 1 R11C25[0][A] n211_s2/I2
8.107 0.526 tINS RR 1 R11C25[0][A] n211_s2/F
8.107 0.000 tNET RR 1 R11C25[0][A] hsrx_cnt_1_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
15.852 0.852 tNET RR 1 R11C25[0][A] hsrx_cnt_1_s1/CLK
15.789 -0.064 tSu 1 R11C25[0][A] hsrx_cnt_1_s1

Path Statistics:

Clock Skew 0.017
Setup Relationship 15.000
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.836, 100.000%
Arrival Data Path Delay cell: 1.250, 17.191%; route: 5.639, 77.549%; tC2Q: 0.382, 5.260%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.852, 100.000%

Path8

Path Summary:

Slack 7.682
Data Arrival Time 8.107
Data Required Time 15.789
From odt_en_msk_s0
To hsrx_cnt_2_s1
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 681 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
0.836 0.836 tNET RR 1 R12C25[2][B] odt_en_msk_s0/CLK
1.218 0.382 tC2Q RR 5 R12C25[2][B] odt_en_msk_s0/Q
3.818 2.600 tNET RR 1 R26C2[2][A] odt_en_1_s0/I2
4.081 0.262 tINS RR 3 R26C2[2][A] odt_en_1_s0/F
5.905 1.824 tNET RR 1 R12C2[0][A] hsrx_cnt_5_s6/I3
6.366 0.461 tINS RR 7 R12C2[0][A] hsrx_cnt_5_s6/F
7.581 1.215 tNET RR 1 R11C25[0][B] n210_s2/I3
8.107 0.526 tINS RR 1 R11C25[0][B] n210_s2/F
8.107 0.000 tNET RR 1 R11C25[0][B] hsrx_cnt_2_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
15.852 0.852 tNET RR 1 R11C25[0][B] hsrx_cnt_2_s1/CLK
15.789 -0.064 tSu 1 R11C25[0][B] hsrx_cnt_2_s1

Path Statistics:

Clock Skew 0.017
Setup Relationship 15.000
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.836, 100.000%
Arrival Data Path Delay cell: 1.250, 17.191%; route: 5.639, 77.549%; tC2Q: 0.382, 5.260%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.852, 100.000%

Path9

Path Summary:

Slack 7.682
Data Arrival Time 8.107
Data Required Time 15.789
From odt_en_msk_s0
To hsrx_cnt_3_s1
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 681 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
0.836 0.836 tNET RR 1 R12C25[2][B] odt_en_msk_s0/CLK
1.218 0.382 tC2Q RR 5 R12C25[2][B] odt_en_msk_s0/Q
3.818 2.600 tNET RR 1 R26C2[2][A] odt_en_1_s0/I2
4.081 0.262 tINS RR 3 R26C2[2][A] odt_en_1_s0/F
5.905 1.824 tNET RR 1 R12C2[0][A] hsrx_cnt_5_s6/I3
6.366 0.461 tINS RR 7 R12C2[0][A] hsrx_cnt_5_s6/F
7.581 1.215 tNET RR 1 R11C25[1][A] n209_s1/I2
8.107 0.526 tINS RR 1 R11C25[1][A] n209_s1/F
8.107 0.000 tNET RR 1 R11C25[1][A] hsrx_cnt_3_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
15.852 0.852 tNET RR 1 R11C25[1][A] hsrx_cnt_3_s1/CLK
15.789 -0.064 tSu 1 R11C25[1][A] hsrx_cnt_3_s1

Path Statistics:

Clock Skew 0.017
Setup Relationship 15.000
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.836, 100.000%
Arrival Data Path Delay cell: 1.250, 17.191%; route: 5.639, 77.549%; tC2Q: 0.382, 5.260%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.852, 100.000%

Path10

Path Summary:

Slack 7.713
Data Arrival Time 7.862
Data Required Time 15.574
From u_csi_rx/u_dsi_csi2/rHSel_0_s1
To u_csi_rx/u_dsi_csi2/rHeader_6_s0
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 681 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
0.901 0.901 tNET RR 1 R21C22[1][B] u_csi_rx/u_dsi_csi2/rHSel_0_s1/CLK
1.283 0.382 tC2Q RR 41 R21C22[1][B] u_csi_rx/u_dsi_csi2/rHSel_0_s1/Q
3.414 2.131 tNET RR 1 R22C26[2][A] u_csi_rx/u_dsi_csi2/wHeader_1_s1/I2
3.941 0.526 tINS RR 2 R22C26[2][A] u_csi_rx/u_dsi_csi2/wHeader_1_s1/F
4.271 0.330 tNET RR 1 R22C28[3][A] u_csi_rx/u_dsi_csi2/n967_s4/I2
4.768 0.498 tINS RR 1 R22C28[3][A] u_csi_rx/u_dsi_csi2/n967_s4/F
5.096 0.327 tNET RR 1 R21C28[3][A] u_csi_rx/u_dsi_csi2/n967_s2/I1
5.617 0.521 tINS RR 3 R21C28[3][A] u_csi_rx/u_dsi_csi2/n967_s2/F
5.812 0.195 tNET RR 1 R21C27[3][A] u_csi_rx/u_dsi_csi2/n967_s1/I0
6.227 0.415 tINS RR 32 R21C27[3][A] u_csi_rx/u_dsi_csi2/n967_s1/F
7.862 1.635 tNET RR 1 R27C23[0][B] u_csi_rx/u_dsi_csi2/rHeader_6_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
15.886 0.886 tNET RR 1 R27C23[0][B] u_csi_rx/u_dsi_csi2/rHeader_6_s0/CLK
15.574 -0.311 tSu 1 R27C23[0][B] u_csi_rx/u_dsi_csi2/rHeader_6_s0

Path Statistics:

Clock Skew -0.015
Setup Relationship 15.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.901, 100.000%
Arrival Data Path Delay cell: 1.960, 28.156%; route: 4.619, 66.349%; tC2Q: 0.382, 5.495%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.886, 100.000%

Path11

Path Summary:

Slack 7.713
Data Arrival Time 7.862
Data Required Time 15.574
From u_csi_rx/u_dsi_csi2/rHSel_0_s1
To u_csi_rx/u_dsi_csi2/rHeader_30_s0
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 681 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
0.901 0.901 tNET RR 1 R21C22[1][B] u_csi_rx/u_dsi_csi2/rHSel_0_s1/CLK
1.283 0.382 tC2Q RR 41 R21C22[1][B] u_csi_rx/u_dsi_csi2/rHSel_0_s1/Q
3.414 2.131 tNET RR 1 R22C26[2][A] u_csi_rx/u_dsi_csi2/wHeader_1_s1/I2
3.941 0.526 tINS RR 2 R22C26[2][A] u_csi_rx/u_dsi_csi2/wHeader_1_s1/F
4.271 0.330 tNET RR 1 R22C28[3][A] u_csi_rx/u_dsi_csi2/n967_s4/I2
4.768 0.498 tINS RR 1 R22C28[3][A] u_csi_rx/u_dsi_csi2/n967_s4/F
5.096 0.327 tNET RR 1 R21C28[3][A] u_csi_rx/u_dsi_csi2/n967_s2/I1
5.617 0.521 tINS RR 3 R21C28[3][A] u_csi_rx/u_dsi_csi2/n967_s2/F
5.812 0.195 tNET RR 1 R21C27[3][A] u_csi_rx/u_dsi_csi2/n967_s1/I0
6.227 0.415 tINS RR 32 R21C27[3][A] u_csi_rx/u_dsi_csi2/n967_s1/F
7.862 1.635 tNET RR 1 R27C23[1][A] u_csi_rx/u_dsi_csi2/rHeader_30_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
15.886 0.886 tNET RR 1 R27C23[1][A] u_csi_rx/u_dsi_csi2/rHeader_30_s0/CLK
15.574 -0.311 tSu 1 R27C23[1][A] u_csi_rx/u_dsi_csi2/rHeader_30_s0

Path Statistics:

Clock Skew -0.015
Setup Relationship 15.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.901, 100.000%
Arrival Data Path Delay cell: 1.960, 28.156%; route: 4.619, 66.349%; tC2Q: 0.382, 5.495%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.886, 100.000%

Path12

Path Summary:

Slack 7.840
Data Arrival Time 7.932
Data Required Time 15.772
From odt_en_msk_s0
To hsrx_cnt_0_s1
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 681 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
0.836 0.836 tNET RR 1 R12C25[2][B] odt_en_msk_s0/CLK
1.218 0.382 tC2Q RR 5 R12C25[2][B] odt_en_msk_s0/Q
3.818 2.600 tNET RR 1 R26C2[2][A] odt_en_1_s0/I2
4.081 0.262 tINS RR 3 R26C2[2][A] odt_en_1_s0/F
5.905 1.824 tNET RR 1 R12C2[0][A] hsrx_cnt_5_s6/I3
6.366 0.461 tINS RR 7 R12C2[0][A] hsrx_cnt_5_s6/F
7.406 1.040 tNET RR 1 R12C25[0][A] n212_s2/I1
7.932 0.526 tINS RR 1 R12C25[0][A] n212_s2/F
7.932 0.000 tNET RR 1 R12C25[0][A] hsrx_cnt_0_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
15.836 0.836 tNET RR 1 R12C25[0][A] hsrx_cnt_0_s1/CLK
15.772 -0.064 tSu 1 R12C25[0][A] hsrx_cnt_0_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 15.000
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.836, 100.000%
Arrival Data Path Delay cell: 1.250, 17.615%; route: 5.464, 76.995%; tC2Q: 0.382, 5.390%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.836, 100.000%

Path13

Path Summary:

Slack 8.495
Data Arrival Time 7.077
Data Required Time 15.572
From u_csi_rx/u_dsi_csi2/rHSel_0_s1
To u_csi_rx/u_dsi_csi2/rHeader_7_s0
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 681 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
0.901 0.901 tNET RR 1 R21C22[1][B] u_csi_rx/u_dsi_csi2/rHSel_0_s1/CLK
1.283 0.382 tC2Q RR 41 R21C22[1][B] u_csi_rx/u_dsi_csi2/rHSel_0_s1/Q
3.414 2.131 tNET RR 1 R22C26[2][A] u_csi_rx/u_dsi_csi2/wHeader_1_s1/I2
3.941 0.526 tINS RR 2 R22C26[2][A] u_csi_rx/u_dsi_csi2/wHeader_1_s1/F
4.271 0.330 tNET RR 1 R22C28[3][A] u_csi_rx/u_dsi_csi2/n967_s4/I2
4.768 0.498 tINS RR 1 R22C28[3][A] u_csi_rx/u_dsi_csi2/n967_s4/F
5.096 0.327 tNET RR 1 R21C28[3][A] u_csi_rx/u_dsi_csi2/n967_s2/I1
5.617 0.521 tINS RR 3 R21C28[3][A] u_csi_rx/u_dsi_csi2/n967_s2/F
5.812 0.195 tNET RR 1 R21C27[3][A] u_csi_rx/u_dsi_csi2/n967_s1/I0
6.227 0.415 tINS RR 32 R21C27[3][A] u_csi_rx/u_dsi_csi2/n967_s1/F
7.077 0.850 tNET RR 1 R26C24[0][A] u_csi_rx/u_dsi_csi2/rHeader_7_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
15.883 0.883 tNET RR 1 R26C24[0][A] u_csi_rx/u_dsi_csi2/rHeader_7_s0/CLK
15.572 -0.311 tSu 1 R26C24[0][A] u_csi_rx/u_dsi_csi2/rHeader_7_s0

Path Statistics:

Clock Skew -0.017
Setup Relationship 15.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.901, 100.000%
Arrival Data Path Delay cell: 1.960, 31.734%; route: 3.834, 62.072%; tC2Q: 0.382, 6.193%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.883, 100.000%

Path14

Path Summary:

Slack 8.513
Data Arrival Time 7.076
Data Required Time 15.589
From u_csi_rx/u_dsi_csi2/rHSel_0_s1
To u_csi_rx/u_dsi_csi2/rHeader_14_s0
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 681 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
0.901 0.901 tNET RR 1 R21C22[1][B] u_csi_rx/u_dsi_csi2/rHSel_0_s1/CLK
1.283 0.382 tC2Q RR 41 R21C22[1][B] u_csi_rx/u_dsi_csi2/rHSel_0_s1/Q
3.414 2.131 tNET RR 1 R22C26[2][A] u_csi_rx/u_dsi_csi2/wHeader_1_s1/I2
3.941 0.526 tINS RR 2 R22C26[2][A] u_csi_rx/u_dsi_csi2/wHeader_1_s1/F
4.271 0.330 tNET RR 1 R22C28[3][A] u_csi_rx/u_dsi_csi2/n967_s4/I2
4.768 0.498 tINS RR 1 R22C28[3][A] u_csi_rx/u_dsi_csi2/n967_s4/F
5.096 0.327 tNET RR 1 R21C28[3][A] u_csi_rx/u_dsi_csi2/n967_s2/I1
5.617 0.521 tINS RR 3 R21C28[3][A] u_csi_rx/u_dsi_csi2/n967_s2/F
5.812 0.195 tNET RR 1 R21C27[3][A] u_csi_rx/u_dsi_csi2/n967_s1/I0
6.227 0.415 tINS RR 32 R21C27[3][A] u_csi_rx/u_dsi_csi2/n967_s1/F
7.076 0.849 tNET RR 1 R25C23[0][B] u_csi_rx/u_dsi_csi2/rHeader_14_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
15.900 0.900 tNET RR 1 R25C23[0][B] u_csi_rx/u_dsi_csi2/rHeader_14_s0/CLK
15.589 -0.311 tSu 1 R25C23[0][B] u_csi_rx/u_dsi_csi2/rHeader_14_s0

Path Statistics:

Clock Skew -0.001
Setup Relationship 15.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.901, 100.000%
Arrival Data Path Delay cell: 1.960, 31.741%; route: 3.832, 62.065%; tC2Q: 0.382, 6.194%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.900, 100.000%

Path15

Path Summary:

Slack 8.513
Data Arrival Time 7.076
Data Required Time 15.589
From u_csi_rx/u_dsi_csi2/rHSel_0_s1
To u_csi_rx/u_dsi_csi2/rHeader_23_s0
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 681 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
0.901 0.901 tNET RR 1 R21C22[1][B] u_csi_rx/u_dsi_csi2/rHSel_0_s1/CLK
1.283 0.382 tC2Q RR 41 R21C22[1][B] u_csi_rx/u_dsi_csi2/rHSel_0_s1/Q
3.414 2.131 tNET RR 1 R22C26[2][A] u_csi_rx/u_dsi_csi2/wHeader_1_s1/I2
3.941 0.526 tINS RR 2 R22C26[2][A] u_csi_rx/u_dsi_csi2/wHeader_1_s1/F
4.271 0.330 tNET RR 1 R22C28[3][A] u_csi_rx/u_dsi_csi2/n967_s4/I2
4.768 0.498 tINS RR 1 R22C28[3][A] u_csi_rx/u_dsi_csi2/n967_s4/F
5.096 0.327 tNET RR 1 R21C28[3][A] u_csi_rx/u_dsi_csi2/n967_s2/I1
5.617 0.521 tINS RR 3 R21C28[3][A] u_csi_rx/u_dsi_csi2/n967_s2/F
5.812 0.195 tNET RR 1 R21C27[3][A] u_csi_rx/u_dsi_csi2/n967_s1/I0
6.227 0.415 tINS RR 32 R21C27[3][A] u_csi_rx/u_dsi_csi2/n967_s1/F
7.076 0.849 tNET RR 1 R25C23[0][A] u_csi_rx/u_dsi_csi2/rHeader_23_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
15.900 0.900 tNET RR 1 R25C23[0][A] u_csi_rx/u_dsi_csi2/rHeader_23_s0/CLK
15.589 -0.311 tSu 1 R25C23[0][A] u_csi_rx/u_dsi_csi2/rHeader_23_s0

Path Statistics:

Clock Skew -0.001
Setup Relationship 15.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.901, 100.000%
Arrival Data Path Delay cell: 1.960, 31.741%; route: 3.832, 62.065%; tC2Q: 0.382, 6.194%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.900, 100.000%

Path16

Path Summary:

Slack 8.561
Data Arrival Time 7.031
Data Required Time 15.591
From u_csi_rx/u_dsi_csi2/rHSel_0_s1
To u_csi_rx/u_dsi_csi2/rHeader_2_s0
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 681 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
0.901 0.901 tNET RR 1 R21C22[1][B] u_csi_rx/u_dsi_csi2/rHSel_0_s1/CLK
1.283 0.382 tC2Q RR 41 R21C22[1][B] u_csi_rx/u_dsi_csi2/rHSel_0_s1/Q
3.414 2.131 tNET RR 1 R22C26[2][A] u_csi_rx/u_dsi_csi2/wHeader_1_s1/I2
3.941 0.526 tINS RR 2 R22C26[2][A] u_csi_rx/u_dsi_csi2/wHeader_1_s1/F
4.271 0.330 tNET RR 1 R22C28[3][A] u_csi_rx/u_dsi_csi2/n967_s4/I2
4.768 0.498 tINS RR 1 R22C28[3][A] u_csi_rx/u_dsi_csi2/n967_s4/F
5.096 0.327 tNET RR 1 R21C28[3][A] u_csi_rx/u_dsi_csi2/n967_s2/I1
5.617 0.521 tINS RR 3 R21C28[3][A] u_csi_rx/u_dsi_csi2/n967_s2/F
5.812 0.195 tNET RR 1 R21C27[3][A] u_csi_rx/u_dsi_csi2/n967_s1/I0
6.227 0.415 tINS RR 32 R21C27[3][A] u_csi_rx/u_dsi_csi2/n967_s1/F
7.031 0.804 tNET RR 1 R24C23[3][A] u_csi_rx/u_dsi_csi2/rHeader_2_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
15.903 0.902 tNET RR 1 R24C23[3][A] u_csi_rx/u_dsi_csi2/rHeader_2_s0/CLK
15.591 -0.311 tSu 1 R24C23[3][A] u_csi_rx/u_dsi_csi2/rHeader_2_s0

Path Statistics:

Clock Skew 0.002
Setup Relationship 15.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.901, 100.000%
Arrival Data Path Delay cell: 1.960, 31.974%; route: 3.787, 61.786%; tC2Q: 0.382, 6.240%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Path17

Path Summary:

Slack 8.561
Data Arrival Time 7.031
Data Required Time 15.591
From u_csi_rx/u_dsi_csi2/rHSel_0_s1
To u_csi_rx/u_dsi_csi2/rHeader_3_s0
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 681 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
0.901 0.901 tNET RR 1 R21C22[1][B] u_csi_rx/u_dsi_csi2/rHSel_0_s1/CLK
1.283 0.382 tC2Q RR 41 R21C22[1][B] u_csi_rx/u_dsi_csi2/rHSel_0_s1/Q
3.414 2.131 tNET RR 1 R22C26[2][A] u_csi_rx/u_dsi_csi2/wHeader_1_s1/I2
3.941 0.526 tINS RR 2 R22C26[2][A] u_csi_rx/u_dsi_csi2/wHeader_1_s1/F
4.271 0.330 tNET RR 1 R22C28[3][A] u_csi_rx/u_dsi_csi2/n967_s4/I2
4.768 0.498 tINS RR 1 R22C28[3][A] u_csi_rx/u_dsi_csi2/n967_s4/F
5.096 0.327 tNET RR 1 R21C28[3][A] u_csi_rx/u_dsi_csi2/n967_s2/I1
5.617 0.521 tINS RR 3 R21C28[3][A] u_csi_rx/u_dsi_csi2/n967_s2/F
5.812 0.195 tNET RR 1 R21C27[3][A] u_csi_rx/u_dsi_csi2/n967_s1/I0
6.227 0.415 tINS RR 32 R21C27[3][A] u_csi_rx/u_dsi_csi2/n967_s1/F
7.031 0.804 tNET RR 1 R24C23[2][B] u_csi_rx/u_dsi_csi2/rHeader_3_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
15.903 0.902 tNET RR 1 R24C23[2][B] u_csi_rx/u_dsi_csi2/rHeader_3_s0/CLK
15.591 -0.311 tSu 1 R24C23[2][B] u_csi_rx/u_dsi_csi2/rHeader_3_s0

Path Statistics:

Clock Skew 0.002
Setup Relationship 15.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.901, 100.000%
Arrival Data Path Delay cell: 1.960, 31.974%; route: 3.787, 61.786%; tC2Q: 0.382, 6.240%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Path18

Path Summary:

Slack 8.666
Data Arrival Time 6.913
Data Required Time 15.579
From u_csi_rx/u_dsi_csi2/rHSel_0_s1
To u_csi_rx/u_dsi_csi2/rHeader_31_s0
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 681 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
0.901 0.901 tNET RR 1 R21C22[1][B] u_csi_rx/u_dsi_csi2/rHSel_0_s1/CLK
1.283 0.382 tC2Q RR 41 R21C22[1][B] u_csi_rx/u_dsi_csi2/rHSel_0_s1/Q
3.414 2.131 tNET RR 1 R22C26[2][A] u_csi_rx/u_dsi_csi2/wHeader_1_s1/I2
3.941 0.526 tINS RR 2 R22C26[2][A] u_csi_rx/u_dsi_csi2/wHeader_1_s1/F
4.271 0.330 tNET RR 1 R22C28[3][A] u_csi_rx/u_dsi_csi2/n967_s4/I2
4.768 0.498 tINS RR 1 R22C28[3][A] u_csi_rx/u_dsi_csi2/n967_s4/F
5.096 0.327 tNET RR 1 R21C28[3][A] u_csi_rx/u_dsi_csi2/n967_s2/I1
5.617 0.521 tINS RR 3 R21C28[3][A] u_csi_rx/u_dsi_csi2/n967_s2/F
5.812 0.195 tNET RR 1 R21C27[3][A] u_csi_rx/u_dsi_csi2/n967_s1/I0
6.227 0.415 tINS RR 32 R21C27[3][A] u_csi_rx/u_dsi_csi2/n967_s1/F
6.913 0.686 tNET RR 1 R25C24[1][A] u_csi_rx/u_dsi_csi2/rHeader_31_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
15.891 0.891 tNET RR 1 R25C24[1][A] u_csi_rx/u_dsi_csi2/rHeader_31_s0/CLK
15.579 -0.311 tSu 1 R25C24[1][A] u_csi_rx/u_dsi_csi2/rHeader_31_s0

Path Statistics:

Clock Skew -0.010
Setup Relationship 15.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.901, 100.000%
Arrival Data Path Delay cell: 1.960, 32.599%; route: 3.670, 61.039%; tC2Q: 0.382, 6.362%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.891, 100.000%

Path19

Path Summary:

Slack 8.676
Data Arrival Time 6.908
Data Required Time 15.584
From u_csi_rx/u_dsi_csi2/rHSel_0_s1
To u_csi_rx/u_dsi_csi2/rHeader_10_s0
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 681 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
0.901 0.901 tNET RR 1 R21C22[1][B] u_csi_rx/u_dsi_csi2/rHSel_0_s1/CLK
1.283 0.382 tC2Q RR 41 R21C22[1][B] u_csi_rx/u_dsi_csi2/rHSel_0_s1/Q
3.414 2.131 tNET RR 1 R22C26[2][A] u_csi_rx/u_dsi_csi2/wHeader_1_s1/I2
3.941 0.526 tINS RR 2 R22C26[2][A] u_csi_rx/u_dsi_csi2/wHeader_1_s1/F
4.271 0.330 tNET RR 1 R22C28[3][A] u_csi_rx/u_dsi_csi2/n967_s4/I2
4.768 0.498 tINS RR 1 R22C28[3][A] u_csi_rx/u_dsi_csi2/n967_s4/F
5.096 0.327 tNET RR 1 R21C28[3][A] u_csi_rx/u_dsi_csi2/n967_s2/I1
5.617 0.521 tINS RR 3 R21C28[3][A] u_csi_rx/u_dsi_csi2/n967_s2/F
5.812 0.195 tNET RR 1 R21C27[3][A] u_csi_rx/u_dsi_csi2/n967_s1/I0
6.227 0.415 tINS RR 32 R21C27[3][A] u_csi_rx/u_dsi_csi2/n967_s1/F
6.908 0.681 tNET RR 1 R23C22[1][B] u_csi_rx/u_dsi_csi2/rHeader_10_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
15.896 0.896 tNET RR 1 R23C22[1][B] u_csi_rx/u_dsi_csi2/rHeader_10_s0/CLK
15.584 -0.311 tSu 1 R23C22[1][B] u_csi_rx/u_dsi_csi2/rHeader_10_s0

Path Statistics:

Clock Skew -0.005
Setup Relationship 15.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.901, 100.000%
Arrival Data Path Delay cell: 1.960, 32.626%; route: 3.665, 61.007%; tC2Q: 0.382, 6.367%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.896, 100.000%

Path20

Path Summary:

Slack 8.676
Data Arrival Time 6.908
Data Required Time 15.584
From u_csi_rx/u_dsi_csi2/rHSel_0_s1
To u_csi_rx/u_dsi_csi2/rHeader_11_s0
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 681 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
0.901 0.901 tNET RR 1 R21C22[1][B] u_csi_rx/u_dsi_csi2/rHSel_0_s1/CLK
1.283 0.382 tC2Q RR 41 R21C22[1][B] u_csi_rx/u_dsi_csi2/rHSel_0_s1/Q
3.414 2.131 tNET RR 1 R22C26[2][A] u_csi_rx/u_dsi_csi2/wHeader_1_s1/I2
3.941 0.526 tINS RR 2 R22C26[2][A] u_csi_rx/u_dsi_csi2/wHeader_1_s1/F
4.271 0.330 tNET RR 1 R22C28[3][A] u_csi_rx/u_dsi_csi2/n967_s4/I2
4.768 0.498 tINS RR 1 R22C28[3][A] u_csi_rx/u_dsi_csi2/n967_s4/F
5.096 0.327 tNET RR 1 R21C28[3][A] u_csi_rx/u_dsi_csi2/n967_s2/I1
5.617 0.521 tINS RR 3 R21C28[3][A] u_csi_rx/u_dsi_csi2/n967_s2/F
5.812 0.195 tNET RR 1 R21C27[3][A] u_csi_rx/u_dsi_csi2/n967_s1/I0
6.227 0.415 tINS RR 32 R21C27[3][A] u_csi_rx/u_dsi_csi2/n967_s1/F
6.908 0.681 tNET RR 1 R23C22[0][B] u_csi_rx/u_dsi_csi2/rHeader_11_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
15.896 0.896 tNET RR 1 R23C22[0][B] u_csi_rx/u_dsi_csi2/rHeader_11_s0/CLK
15.584 -0.311 tSu 1 R23C22[0][B] u_csi_rx/u_dsi_csi2/rHeader_11_s0

Path Statistics:

Clock Skew -0.005
Setup Relationship 15.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.901, 100.000%
Arrival Data Path Delay cell: 1.960, 32.626%; route: 3.665, 61.007%; tC2Q: 0.382, 6.367%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.896, 100.000%

Hold Analysis Report

Hold Analysis Report[1]:

Report Command:report_timing -hold -from_clock [get_clocks {pixel_clk}] -max_paths 20 -max_common_paths 1

Path1

Path Summary:

Slack 0.076
Data Arrival Time 0.698
Data Required Time 0.623
From u_bayer_rgb/data_tmp2_0_s0
To u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLLA_inst/CLKOUT1
0.385 0.385 tNET RR 1 R24C34[1][A] u_bayer_rgb/data_tmp2_0_s0/CLK
0.565 0.180 tC2Q RR 3 R24C34[1][A] u_bayer_rgb/data_tmp2_0_s0/Q
0.698 0.134 tNET RR 1 BSRAM_R28[9] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/DI[0]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLLA_inst/CLKOUT1
0.374 0.374 tNET RR 1 BSRAM_R28[9] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/CLKA
0.623 0.249 tHld 1 BSRAM_R28[9] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s

Path Statistics:

Clock Skew -0.011
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.385, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.134, 42.629%; tC2Q: 0.180, 57.371%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.374, 100.000%

Path2

Path Summary:

Slack 0.204
Data Arrival Time 0.691
Data Required Time 0.487
From u_bayer_rgb/shift_line_inst0/shiftout_addr_5_s0
To u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLLA_inst/CLKOUT1
0.385 0.385 tNET RR 1 R24C30[2][B] u_bayer_rgb/shift_line_inst0/shiftout_addr_5_s0/CLK
0.565 0.180 tC2Q RR 1 R24C30[2][B] u_bayer_rgb/shift_line_inst0/shiftout_addr_5_s0/Q
0.691 0.126 tNET RR 1 BSRAM_R28[9] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/ADB[8]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLLA_inst/CLKOUT1
0.369 0.369 tNET RR 1 BSRAM_R28[9] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/CLKB
0.487 0.118 tHld 1 BSRAM_R28[9] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s

Path Statistics:

Clock Skew -0.016
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.385, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.126, 41.224%; tC2Q: 0.180, 58.776%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.369, 100.000%

Path3

Path Summary:

Slack 0.204
Data Arrival Time 0.691
Data Required Time 0.487
From u_bayer_rgb/shift_line_inst0/shiftout_addr_4_s0
To u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLLA_inst/CLKOUT1
0.385 0.385 tNET RR 1 R24C30[2][A] u_bayer_rgb/shift_line_inst0/shiftout_addr_4_s0/CLK
0.565 0.180 tC2Q RR 1 R24C30[2][A] u_bayer_rgb/shift_line_inst0/shiftout_addr_4_s0/Q
0.691 0.126 tNET RR 1 BSRAM_R28[9] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/ADB[7]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLLA_inst/CLKOUT1
0.369 0.369 tNET RR 1 BSRAM_R28[9] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/CLKB
0.487 0.118 tHld 1 BSRAM_R28[9] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s

Path Statistics:

Clock Skew -0.016
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.385, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.126, 41.224%; tC2Q: 0.180, 58.776%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.369, 100.000%

Path4

Path Summary:

Slack 0.298
Data Arrival Time 0.785
Data Required Time 0.487
From u_bayer_rgb/shift_line_inst0/shiftout_addr_3_s0
To u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLLA_inst/CLKOUT1
0.385 0.385 tNET RR 1 R24C30[1][B] u_bayer_rgb/shift_line_inst0/shiftout_addr_3_s0/CLK
0.565 0.180 tC2Q RR 1 R24C30[1][B] u_bayer_rgb/shift_line_inst0/shiftout_addr_3_s0/Q
0.785 0.220 tNET RR 1 BSRAM_R28[9] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/ADB[6]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLLA_inst/CLKOUT1
0.369 0.369 tNET RR 1 BSRAM_R28[9] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/CLKB
0.487 0.118 tHld 1 BSRAM_R28[9] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s

Path Statistics:

Clock Skew -0.016
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.385, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.220, 55.000%; tC2Q: 0.180, 45.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.369, 100.000%

Path5

Path Summary:

Slack 0.303
Data Arrival Time 0.790
Data Required Time 0.487
From u_bayer_rgb/shift_line_inst0/shiftout_addr_9_s0
To u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLLA_inst/CLKOUT1
0.390 0.390 tNET RR 1 R24C31[1][B] u_bayer_rgb/shift_line_inst0/shiftout_addr_9_s0/CLK
0.570 0.180 tC2Q RR 1 R24C31[1][B] u_bayer_rgb/shift_line_inst0/shiftout_addr_9_s0/Q
0.790 0.220 tNET RR 1 BSRAM_R28[9] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/ADB[12]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLLA_inst/CLKOUT1
0.369 0.369 tNET RR 1 BSRAM_R28[9] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/CLKB
0.487 0.118 tHld 1 BSRAM_R28[9] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s

Path Statistics:

Clock Skew -0.021
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.390, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.220, 55.000%; tC2Q: 0.180, 45.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.369, 100.000%

Path6

Path Summary:

Slack 0.303
Data Arrival Time 0.790
Data Required Time 0.487
From u_bayer_rgb/shift_line_inst0/shiftout_addr_7_s0
To u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLLA_inst/CLKOUT1
0.390 0.390 tNET RR 1 R24C31[0][B] u_bayer_rgb/shift_line_inst0/shiftout_addr_7_s0/CLK
0.570 0.180 tC2Q RR 1 R24C31[0][B] u_bayer_rgb/shift_line_inst0/shiftout_addr_7_s0/Q
0.790 0.220 tNET RR 1 BSRAM_R28[9] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/ADB[10]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLLA_inst/CLKOUT1
0.369 0.369 tNET RR 1 BSRAM_R28[9] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/CLKB
0.487 0.118 tHld 1 BSRAM_R28[9] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s

Path Statistics:

Clock Skew -0.021
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.390, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.220, 55.000%; tC2Q: 0.180, 45.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.369, 100.000%

Path7

Path Summary:

Slack 0.305
Data Arrival Time 0.797
Data Required Time 0.492
From u_bayer_rgb/shift_line_inst0/shiftin_addr_7_s0
To u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLLA_inst/CLKOUT1
0.390 0.390 tNET RR 1 R24C33[0][A] u_bayer_rgb/shift_line_inst0/shiftin_addr_7_s0/CLK
0.570 0.180 tC2Q RR 3 R24C33[0][A] u_bayer_rgb/shift_line_inst0/shiftin_addr_7_s0/Q
0.797 0.227 tNET RR 1 BSRAM_R28[9] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/ADA[10]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLLA_inst/CLKOUT1
0.374 0.374 tNET RR 1 BSRAM_R28[9] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/CLKA
0.492 0.118 tHld 1 BSRAM_R28[9] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s

Path Statistics:

Clock Skew -0.016
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.390, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.227, 55.828%; tC2Q: 0.180, 44.172%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.374, 100.000%

Path8

Path Summary:

Slack 0.310
Data Arrival Time 0.802
Data Required Time 0.492
From u_bayer_rgb/shift_line_inst0/shiftin_addr_1_s0
To u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLLA_inst/CLKOUT1
0.395 0.395 tNET RR 1 R24C32[0][A] u_bayer_rgb/shift_line_inst0/shiftin_addr_1_s0/CLK
0.575 0.180 tC2Q RR 3 R24C32[0][A] u_bayer_rgb/shift_line_inst0/shiftin_addr_1_s0/Q
0.802 0.227 tNET RR 1 BSRAM_R28[9] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/ADA[4]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLLA_inst/CLKOUT1
0.374 0.374 tNET RR 1 BSRAM_R28[9] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/CLKA
0.492 0.118 tHld 1 BSRAM_R28[9] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s

Path Statistics:

Clock Skew -0.021
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.395, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.227, 55.828%; tC2Q: 0.180, 44.172%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.374, 100.000%

Path9

Path Summary:

Slack 0.329
Data Arrival Time 0.821
Data Required Time 0.492
From u_bayer_rgb/shift_line_inst0/shiftin_addr_10_s0
To u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLLA_inst/CLKOUT1
0.390 0.390 tNET RR 1 R24C33[1][B] u_bayer_rgb/shift_line_inst0/shiftin_addr_10_s0/CLK
0.570 0.180 tC2Q RR 3 R24C33[1][B] u_bayer_rgb/shift_line_inst0/shiftin_addr_10_s0/Q
0.821 0.251 tNET RR 1 BSRAM_R28[9] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/ADA[13]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLLA_inst/CLKOUT1
0.374 0.374 tNET RR 1 BSRAM_R28[9] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/CLKA
0.492 0.118 tHld 1 BSRAM_R28[9] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s

Path Statistics:

Clock Skew -0.016
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.390, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.251, 58.261%; tC2Q: 0.180, 41.739%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.374, 100.000%

Path10

Path Summary:

Slack 0.329
Data Arrival Time 0.821
Data Required Time 0.492
From u_bayer_rgb/shift_line_inst0/shiftin_addr_3_s0
To u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLLA_inst/CLKOUT1
0.395 0.395 tNET RR 1 R24C32[1][A] u_bayer_rgb/shift_line_inst0/shiftin_addr_3_s0/CLK
0.575 0.180 tC2Q RR 3 R24C32[1][A] u_bayer_rgb/shift_line_inst0/shiftin_addr_3_s0/Q
0.821 0.246 tNET RR 1 BSRAM_R28[9] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/ADA[6]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLLA_inst/CLKOUT1
0.374 0.374 tNET RR 1 BSRAM_R28[9] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/CLKA
0.492 0.118 tHld 1 BSRAM_R28[9] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s

Path Statistics:

Clock Skew -0.021
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.395, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.246, 57.771%; tC2Q: 0.180, 42.229%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.374, 100.000%

Path11

Path Summary:

Slack 0.329
Data Arrival Time 0.821
Data Required Time 0.492
From u_bayer_rgb/shift_line_inst0/shiftin_addr_2_s0
To u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLLA_inst/CLKOUT1
0.395 0.395 tNET RR 1 R24C32[0][B] u_bayer_rgb/shift_line_inst0/shiftin_addr_2_s0/CLK
0.575 0.180 tC2Q RR 3 R24C32[0][B] u_bayer_rgb/shift_line_inst0/shiftin_addr_2_s0/Q
0.821 0.246 tNET RR 1 BSRAM_R28[9] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/ADA[5]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLLA_inst/CLKOUT1
0.374 0.374 tNET RR 1 BSRAM_R28[9] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/CLKA
0.492 0.118 tHld 1 BSRAM_R28[9] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s

Path Statistics:

Clock Skew -0.021
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.395, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.246, 57.771%; tC2Q: 0.180, 42.229%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.374, 100.000%

Path12

Path Summary:

Slack 0.334
Data Arrival Time 0.826
Data Required Time 0.492
From u_bayer_rgb/shift_line_inst0/shiftin_addr_5_s0
To u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLLA_inst/CLKOUT1
0.395 0.395 tNET RR 1 R24C32[2][A] u_bayer_rgb/shift_line_inst0/shiftin_addr_5_s0/CLK
0.575 0.180 tC2Q RR 3 R24C32[2][A] u_bayer_rgb/shift_line_inst0/shiftin_addr_5_s0/Q
0.826 0.251 tNET RR 1 BSRAM_R28[9] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/ADA[8]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLLA_inst/CLKOUT1
0.374 0.374 tNET RR 1 BSRAM_R28[9] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/CLKA
0.492 0.118 tHld 1 BSRAM_R28[9] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s

Path Statistics:

Clock Skew -0.021
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.395, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.251, 58.261%; tC2Q: 0.180, 41.739%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.374, 100.000%

Path13

Path Summary:

Slack 0.334
Data Arrival Time 0.826
Data Required Time 0.492
From u_bayer_rgb/shift_line_inst0/shiftin_addr_4_s0
To u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLLA_inst/CLKOUT1
0.395 0.395 tNET RR 1 R24C32[1][B] u_bayer_rgb/shift_line_inst0/shiftin_addr_4_s0/CLK
0.575 0.180 tC2Q RR 3 R24C32[1][B] u_bayer_rgb/shift_line_inst0/shiftin_addr_4_s0/Q
0.826 0.251 tNET RR 1 BSRAM_R28[9] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/ADA[7]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLLA_inst/CLKOUT1
0.374 0.374 tNET RR 1 BSRAM_R28[9] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/CLKA
0.492 0.118 tHld 1 BSRAM_R28[9] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s

Path Statistics:

Clock Skew -0.021
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.395, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.251, 58.261%; tC2Q: 0.180, 41.739%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.374, 100.000%

Path14

Path Summary:

Slack 0.377
Data Arrival Time 0.771
Data Required Time 0.393
From u_bayer_rgb/devcnt_5_s1
To u_bayer_rgb/devcnt_5_s1
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLLA_inst/CLKOUT1
0.392 0.392 tNET RR 1 R23C33[1][A] u_bayer_rgb/devcnt_5_s1/CLK
0.568 0.176 tC2Q RF 4 R23C33[1][A] u_bayer_rgb/devcnt_5_s1/Q
0.579 0.011 tNET FF 1 R23C33[1][A] u_bayer_rgb/n95_s2/I3
0.771 0.191 tINS FF 1 R23C33[1][A] u_bayer_rgb/n95_s2/F
0.771 0.000 tNET FF 1 R23C33[1][A] u_bayer_rgb/devcnt_5_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLLA_inst/CLKOUT1
0.392 0.392 tNET RR 1 R23C33[1][A] u_bayer_rgb/devcnt_5_s1/CLK
0.393 0.001 tHld 1 R23C33[1][A] u_bayer_rgb/devcnt_5_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.392, 100.000%
Arrival Data Path Delay cell: 0.191, 50.495%; route: 0.011, 2.970%; tC2Q: 0.176, 46.535%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.392, 100.000%

Path15

Path Summary:

Slack 0.378
Data Arrival Time 0.766
Data Required Time 0.389
From u_bayer_rgb/shift_line_inst0/shiftin_addr_0_s0
To u_bayer_rgb/shift_line_inst0/shiftin_addr_0_s0
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLLA_inst/CLKOUT1
0.387 0.387 tNET RR 1 R25C33[0][A] u_bayer_rgb/shift_line_inst0/shiftin_addr_0_s0/CLK
0.564 0.176 tC2Q RF 4 R25C33[0][A] u_bayer_rgb/shift_line_inst0/shiftin_addr_0_s0/Q
0.575 0.011 tNET FF 1 R25C33[0][A] u_bayer_rgb/shift_line_inst0/n24_s2/I0
0.766 0.191 tINS FF 1 R25C33[0][A] u_bayer_rgb/shift_line_inst0/n24_s2/F
0.766 0.000 tNET FF 1 R25C33[0][A] u_bayer_rgb/shift_line_inst0/shiftin_addr_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLLA_inst/CLKOUT1
0.387 0.387 tNET RR 1 R25C33[0][A] u_bayer_rgb/shift_line_inst0/shiftin_addr_0_s0/CLK
0.389 0.001 tHld 1 R25C33[0][A] u_bayer_rgb/shift_line_inst0/shiftin_addr_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.387, 100.000%
Arrival Data Path Delay cell: 0.191, 50.495%; route: 0.011, 2.970%; tC2Q: 0.176, 46.535%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.387, 100.000%

Path16

Path Summary:

Slack 0.392
Data Arrival Time 0.793
Data Required Time 0.400
From u_bayer_rgb/video_format_detect_inst/hcnt_0_s3
To u_bayer_rgb/video_format_detect_inst/hcnt_0_s3
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLLA_inst/CLKOUT1
0.399 0.399 tNET RR 1 R22C28[1][A] u_bayer_rgb/video_format_detect_inst/hcnt_0_s3/CLK
0.579 0.180 tC2Q RR 6 R22C28[1][A] u_bayer_rgb/video_format_detect_inst/hcnt_0_s3/Q
0.602 0.023 tNET RR 1 R22C28[1][A] u_bayer_rgb/video_format_detect_inst/n49_s5/I2
0.793 0.191 tINS RF 1 R22C28[1][A] u_bayer_rgb/video_format_detect_inst/n49_s5/F
0.793 0.000 tNET FF 1 R22C28[1][A] u_bayer_rgb/video_format_detect_inst/hcnt_0_s3/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLLA_inst/CLKOUT1
0.399 0.399 tNET RR 1 R22C28[1][A] u_bayer_rgb/video_format_detect_inst/hcnt_0_s3/CLK
0.400 0.001 tHld 1 R22C28[1][A] u_bayer_rgb/video_format_detect_inst/hcnt_0_s3

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.399, 100.000%
Arrival Data Path Delay cell: 0.191, 48.571%; route: 0.023, 5.714%; tC2Q: 0.180, 45.714%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.399, 100.000%

Path17

Path Summary:

Slack 0.410
Data Arrival Time 0.897
Data Required Time 0.487
From u_bayer_rgb/shift_line_inst0/shiftout_addr_2_s0
To u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLLA_inst/CLKOUT1
0.385 0.385 tNET RR 1 R24C30[1][A] u_bayer_rgb/shift_line_inst0/shiftout_addr_2_s0/CLK
0.565 0.180 tC2Q RR 1 R24C30[1][A] u_bayer_rgb/shift_line_inst0/shiftout_addr_2_s0/Q
0.897 0.332 tNET RR 1 BSRAM_R28[9] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/ADB[5]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLLA_inst/CLKOUT1
0.369 0.369 tNET RR 1 BSRAM_R28[9] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/CLKB
0.487 0.118 tHld 1 BSRAM_R28[9] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s

Path Statistics:

Clock Skew -0.016
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.385, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.332, 64.878%; tC2Q: 0.180, 35.122%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.369, 100.000%

Path18

Path Summary:

Slack 0.423
Data Arrival Time 0.915
Data Required Time 0.492
From u_bayer_rgb/shift_line_inst0/shiftin_addr_9_s0
To u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLLA_inst/CLKOUT1
0.390 0.390 tNET RR 1 R24C33[1][A] u_bayer_rgb/shift_line_inst0/shiftin_addr_9_s0/CLK
0.570 0.180 tC2Q RR 3 R24C33[1][A] u_bayer_rgb/shift_line_inst0/shiftin_addr_9_s0/Q
0.915 0.345 tNET RR 1 BSRAM_R28[9] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/ADA[12]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLLA_inst/CLKOUT1
0.374 0.374 tNET RR 1 BSRAM_R28[9] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/CLKA
0.492 0.118 tHld 1 BSRAM_R28[9] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s

Path Statistics:

Clock Skew -0.016
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.390, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.345, 65.714%; tC2Q: 0.180, 34.286%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.374, 100.000%

Path19

Path Summary:

Slack 0.428
Data Arrival Time 0.920
Data Required Time 0.492
From u_bayer_rgb/shift_line_inst0/shiftin_addr_6_s0
To u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLLA_inst/CLKOUT1
0.395 0.395 tNET RR 1 R24C32[2][B] u_bayer_rgb/shift_line_inst0/shiftin_addr_6_s0/CLK
0.575 0.180 tC2Q RR 3 R24C32[2][B] u_bayer_rgb/shift_line_inst0/shiftin_addr_6_s0/Q
0.920 0.345 tNET RR 1 BSRAM_R28[9] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/ADA[9]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLLA_inst/CLKOUT1
0.374 0.374 tNET RR 1 BSRAM_R28[9] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/CLKA
0.492 0.118 tHld 1 BSRAM_R28[9] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s

Path Statistics:

Clock Skew -0.021
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.395, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.345, 65.714%; tC2Q: 0.180, 34.286%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.374, 100.000%

Path20

Path Summary:

Slack 0.428
Data Arrival Time 1.051
Data Required Time 0.623
From u_bayer_rgb/data_tmp2_2_s0
To u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLLA_inst/CLKOUT1
0.387 0.387 tNET RR 1 R25C35[0][B] u_bayer_rgb/data_tmp2_2_s0/CLK
0.567 0.180 tC2Q RR 3 R25C35[0][B] u_bayer_rgb/data_tmp2_2_s0/Q
1.051 0.484 tNET RR 1 BSRAM_R28[9] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/DI[2]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLLA_inst/CLKOUT1
0.374 0.374 tNET RR 1 BSRAM_R28[9] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/CLKA
0.623 0.249 tHld 1 BSRAM_R28[9] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s

Path Statistics:

Clock Skew -0.014
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.387, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.484, 72.881%; tC2Q: 0.180, 27.119%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.374, 100.000%

Hold Analysis Report[2]:

Report Command:report_timing -hold -from_clock [get_clocks {byte_clk}] -max_paths 20 -max_common_paths 1

Path1

Path Summary:

Slack 0.063
Data Arrival Time 0.064
Data Required Time 0.001
From u_hard_dphy/mipi_dphy_inst
To u_la0_top/u_ao_mem_ctrl/data_reg_dly_59_s0
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 681 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
0.064 0.064 tC2Q RF 2 - u_hard_dphy/mipi_dphy_inst/D1LN_HSRXD[0]
0.064 0.000 tNET FF 1 R8C12[1][B] u_la0_top/u_ao_mem_ctrl/data_reg_dly_59_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 1 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
0.000 0.000 tNET RR 1 R8C12[1][B] u_la0_top/u_ao_mem_ctrl/data_reg_dly_59_s0/CLK
0.001 0.001 tHld 1 R8C12[1][B] u_la0_top/u_ao_mem_ctrl/data_reg_dly_59_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.064, 100.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path2

Path Summary:

Slack 0.063
Data Arrival Time 0.064
Data Required Time 0.001
From u_hard_dphy/mipi_dphy_inst
To u_la0_top/u_ao_mem_ctrl/data_reg_dly_63_s0
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 681 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
0.064 0.064 tC2Q RF 2 - u_hard_dphy/mipi_dphy_inst/D1LN_HSRXD[4]
0.064 0.000 tNET FF 1 R11C10[1][B] u_la0_top/u_ao_mem_ctrl/data_reg_dly_63_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 1 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
0.000 0.000 tNET RR 1 R11C10[1][B] u_la0_top/u_ao_mem_ctrl/data_reg_dly_63_s0/CLK
0.001 0.001 tHld 1 R11C10[1][B] u_la0_top/u_ao_mem_ctrl/data_reg_dly_63_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.064, 100.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path3

Path Summary:

Slack 0.063
Data Arrival Time 0.064
Data Required Time 0.001
From u_hard_dphy/mipi_dphy_inst
To u_la0_top/u_ao_mem_ctrl/data_reg_dly_64_s0
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 681 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
0.064 0.064 tC2Q RF 2 - u_hard_dphy/mipi_dphy_inst/D1LN_HSRXD[5]
0.064 0.000 tNET FF 1 R11C10[2][B] u_la0_top/u_ao_mem_ctrl/data_reg_dly_64_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 1 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
0.000 0.000 tNET RR 1 R11C10[2][B] u_la0_top/u_ao_mem_ctrl/data_reg_dly_64_s0/CLK
0.001 0.001 tHld 1 R11C10[2][B] u_la0_top/u_ao_mem_ctrl/data_reg_dly_64_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.064, 100.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path4

Path Summary:

Slack 0.063
Data Arrival Time 0.064
Data Required Time 0.001
From u_hard_dphy/mipi_dphy_inst
To u_la0_top/u_ao_mem_ctrl/data_reg_dly_65_s0
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 681 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
0.064 0.064 tC2Q RF 2 - u_hard_dphy/mipi_dphy_inst/D1LN_HSRXD[6]
0.064 0.000 tNET FF 1 R9C12[3][B] u_la0_top/u_ao_mem_ctrl/data_reg_dly_65_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 1 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
0.000 0.000 tNET RR 1 R9C12[3][B] u_la0_top/u_ao_mem_ctrl/data_reg_dly_65_s0/CLK
0.001 0.001 tHld 1 R9C12[3][B] u_la0_top/u_ao_mem_ctrl/data_reg_dly_65_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.064, 100.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path5

Path Summary:

Slack 0.063
Data Arrival Time 0.064
Data Required Time 0.001
From u_hard_dphy/mipi_dphy_inst
To u_la0_top/u_ao_mem_ctrl/data_reg_dly_60_s0
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 681 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
0.064 0.064 tC2Q RF 2 - u_hard_dphy/mipi_dphy_inst/D1LN_HSRXD[1]
0.064 0.000 tNET FF 1 R8C12[2][B] u_la0_top/u_ao_mem_ctrl/data_reg_dly_60_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 1 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
0.000 0.000 tNET RR 1 R8C12[2][B] u_la0_top/u_ao_mem_ctrl/data_reg_dly_60_s0/CLK
0.001 0.001 tHld 1 R8C12[2][B] u_la0_top/u_ao_mem_ctrl/data_reg_dly_60_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.064, 100.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path6

Path Summary:

Slack 0.063
Data Arrival Time 0.064
Data Required Time 0.001
From u_hard_dphy/mipi_dphy_inst
To u_la0_top/u_ao_mem_ctrl/data_reg_dly_61_s0
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 681 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
0.064 0.064 tC2Q RF 2 - u_hard_dphy/mipi_dphy_inst/D1LN_HSRXD[2]
0.064 0.000 tNET FF 1 R4C5[1][B] u_la0_top/u_ao_mem_ctrl/data_reg_dly_61_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 1 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
0.000 0.000 tNET RR 1 R4C5[1][B] u_la0_top/u_ao_mem_ctrl/data_reg_dly_61_s0/CLK
0.001 0.001 tHld 1 R4C5[1][B] u_la0_top/u_ao_mem_ctrl/data_reg_dly_61_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.064, 100.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path7

Path Summary:

Slack 0.063
Data Arrival Time 0.064
Data Required Time 0.001
From u_hard_dphy/mipi_dphy_inst
To u_la0_top/u_ao_mem_ctrl/data_reg_dly_67_s0
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 681 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
0.064 0.064 tC2Q RF 2 - u_hard_dphy/mipi_dphy_inst/D0LN_HSRXD[0]
0.064 0.000 tNET FF 1 R9C12[0][B] u_la0_top/u_ao_mem_ctrl/data_reg_dly_67_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 1 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
0.000 0.000 tNET RR 1 R9C12[0][B] u_la0_top/u_ao_mem_ctrl/data_reg_dly_67_s0/CLK
0.001 0.001 tHld 1 R9C12[0][B] u_la0_top/u_ao_mem_ctrl/data_reg_dly_67_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.064, 100.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path8

Path Summary:

Slack 0.063
Data Arrival Time 0.064
Data Required Time 0.001
From u_hard_dphy/mipi_dphy_inst
To u_la0_top/u_ao_mem_ctrl/data_reg_dly_68_s0
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 681 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
0.064 0.064 tC2Q RF 2 - u_hard_dphy/mipi_dphy_inst/D0LN_HSRXD[1]
0.064 0.000 tNET FF 1 R9C12[1][B] u_la0_top/u_ao_mem_ctrl/data_reg_dly_68_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 1 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
0.000 0.000 tNET RR 1 R9C12[1][B] u_la0_top/u_ao_mem_ctrl/data_reg_dly_68_s0/CLK
0.001 0.001 tHld 1 R9C12[1][B] u_la0_top/u_ao_mem_ctrl/data_reg_dly_68_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.064, 100.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path9

Path Summary:

Slack 0.063
Data Arrival Time 0.064
Data Required Time 0.001
From u_hard_dphy/mipi_dphy_inst
To u_la0_top/u_ao_mem_ctrl/data_reg_dly_70_s0
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 681 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
0.064 0.064 tC2Q RF 2 - u_hard_dphy/mipi_dphy_inst/D0LN_HSRXD[3]
0.064 0.000 tNET FF 1 R9C12[2][B] u_la0_top/u_ao_mem_ctrl/data_reg_dly_70_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 1 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
0.000 0.000 tNET RR 1 R9C12[2][B] u_la0_top/u_ao_mem_ctrl/data_reg_dly_70_s0/CLK
0.001 0.001 tHld 1 R9C12[2][B] u_la0_top/u_ao_mem_ctrl/data_reg_dly_70_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.064, 100.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path10

Path Summary:

Slack 0.063
Data Arrival Time 0.064
Data Required Time 0.001
From u_hard_dphy/mipi_dphy_inst
To u_la0_top/u_ao_mem_ctrl/data_reg_dly_71_s0
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 681 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
0.064 0.064 tC2Q RF 2 - u_hard_dphy/mipi_dphy_inst/D0LN_HSRXD[4]
0.064 0.000 tNET FF 1 R12C8[0][B] u_la0_top/u_ao_mem_ctrl/data_reg_dly_71_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 1 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
0.000 0.000 tNET RR 1 R12C8[0][B] u_la0_top/u_ao_mem_ctrl/data_reg_dly_71_s0/CLK
0.001 0.001 tHld 1 R12C8[0][B] u_la0_top/u_ao_mem_ctrl/data_reg_dly_71_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.064, 100.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path11

Path Summary:

Slack 0.175
Data Arrival Time 0.424
Data Required Time 0.249
From u_la0_top/u_ao_mem_ctrl/data_reg_60_s0
To u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 681 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
0.000 0.000 tNET RR 1 R8C12[3][A] u_la0_top/u_ao_mem_ctrl/data_reg_60_s0/CLK
0.180 0.180 tC2Q RR 1 R8C12[3][A] u_la0_top/u_ao_mem_ctrl/data_reg_60_s0/Q
0.424 0.244 tNET RR 1 BSRAM_R10[3] u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/DI[6]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 1 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
0.000 0.000 tNET RR 1 BSRAM_R10[3] u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/CLKA
0.249 0.249 tHld 1 BSRAM_R10[3] u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.244, 57.522%; tC2Q: 0.180, 42.478%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path12

Path Summary:

Slack 0.175
Data Arrival Time 0.424
Data Required Time 0.249
From u_la0_top/u_ao_mem_ctrl/data_reg_59_s0
To u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 681 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
0.000 0.000 tNET RR 1 R8C12[2][A] u_la0_top/u_ao_mem_ctrl/data_reg_59_s0/CLK
0.180 0.180 tC2Q RR 1 R8C12[2][A] u_la0_top/u_ao_mem_ctrl/data_reg_59_s0/Q
0.424 0.244 tNET RR 1 BSRAM_R10[3] u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/DI[5]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 1 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
0.000 0.000 tNET RR 1 BSRAM_R10[3] u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/CLKA
0.249 0.249 tHld 1 BSRAM_R10[3] u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.244, 57.522%; tC2Q: 0.180, 42.478%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path13

Path Summary:

Slack 0.254
Data Arrival Time 0.871
Data Required Time 0.618
From u_b2p/u_b2p_inst/rBufD_2_s1
To u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 681 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
0.351 0.351 tNET RR 1 R12C26[0][A] u_b2p/u_b2p_inst/rBufD_2_s1/CLK
0.531 0.180 tC2Q RR 1 R12C26[0][A] u_b2p/u_b2p_inst/rBufD_2_s1/Q
0.871 0.340 tNET RR 1 BSRAM_R10[7] u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s/DI[2]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 1 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
0.369 0.369 tNET RR 1 BSRAM_R10[7] u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s/CLKA
0.618 0.249 tHld 1 BSRAM_R10[7] u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s

Path Statistics:

Clock Skew 0.018
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.351, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.340, 65.385%; tC2Q: 0.180, 34.615%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.369, 100.000%

Path14

Path Summary:

Slack 0.271
Data Arrival Time 0.520
Data Required Time 0.249
From u_la0_top/u_ao_mem_ctrl/data_reg_21_s0
To u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 681 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
0.000 0.000 tNET RR 1 R12C8[1][A] u_la0_top/u_ao_mem_ctrl/data_reg_21_s0/CLK
0.180 0.180 tC2Q RR 1 R12C8[1][A] u_la0_top/u_ao_mem_ctrl/data_reg_21_s0/Q
0.520 0.340 tNET RR 1 BSRAM_R10[1] u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[3]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 1 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
0.000 0.000 tNET RR 1 BSRAM_R10[1] u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA
0.249 0.249 tHld 1 BSRAM_R10[1] u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.340, 65.385%; tC2Q: 0.180, 34.615%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path15

Path Summary:

Slack 0.297
Data Arrival Time 0.064
Data Required Time -0.233
From u_hard_dphy/mipi_dphy_inst
To u_la0_top/u_ao_mem_ctrl/data_reg_dly_62_s0
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 681 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
0.064 0.064 tC2Q RF 2 - u_hard_dphy/mipi_dphy_inst/D1LN_HSRXD[3]
0.064 0.000 tNET FF 1 R6C3[2][A] u_la0_top/u_ao_mem_ctrl/data_reg_dly_62_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 1 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
0.000 0.000 tNET RR 1 R6C3[2][A] u_la0_top/u_ao_mem_ctrl/data_reg_dly_62_s0/CLK
-0.233 -0.233 tHld 1 R6C3[2][A] u_la0_top/u_ao_mem_ctrl/data_reg_dly_62_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.064, 100.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path16

Path Summary:

Slack 0.297
Data Arrival Time 0.064
Data Required Time -0.233
From u_hard_dphy/mipi_dphy_inst
To u_la0_top/u_ao_mem_ctrl/data_reg_dly_66_s0
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 681 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
0.064 0.064 tC2Q RF 2 - u_hard_dphy/mipi_dphy_inst/D1LN_HSRXD[7]
0.064 0.000 tNET FF 1 R7C2[0][A] u_la0_top/u_ao_mem_ctrl/data_reg_dly_66_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 1 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
0.000 0.000 tNET RR 1 R7C2[0][A] u_la0_top/u_ao_mem_ctrl/data_reg_dly_66_s0/CLK
-0.233 -0.233 tHld 1 R7C2[0][A] u_la0_top/u_ao_mem_ctrl/data_reg_dly_66_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.064, 100.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path17

Path Summary:

Slack 0.297
Data Arrival Time 0.064
Data Required Time -0.233
From u_hard_dphy/mipi_dphy_inst
To u_la0_top/u_ao_mem_ctrl/data_reg_dly_72_s0
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 681 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
0.064 0.064 tC2Q RF 2 - u_hard_dphy/mipi_dphy_inst/D0LN_HSRXD[5]
0.064 0.000 tNET FF 1 R7C2[0][B] u_la0_top/u_ao_mem_ctrl/data_reg_dly_72_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 1 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
0.000 0.000 tNET RR 1 R7C2[0][B] u_la0_top/u_ao_mem_ctrl/data_reg_dly_72_s0/CLK
-0.233 -0.233 tHld 1 R7C2[0][B] u_la0_top/u_ao_mem_ctrl/data_reg_dly_72_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.064, 100.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path18

Path Summary:

Slack 0.297
Data Arrival Time 0.064
Data Required Time -0.233
From u_hard_dphy/mipi_dphy_inst
To u_la0_top/u_ao_mem_ctrl/data_reg_dly_73_s0
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 681 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
0.064 0.064 tC2Q RF 2 - u_hard_dphy/mipi_dphy_inst/D0LN_HSRXD[6]
0.064 0.000 tNET FF 1 R7C2[2][A] u_la0_top/u_ao_mem_ctrl/data_reg_dly_73_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 1 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
0.000 0.000 tNET RR 1 R7C2[2][A] u_la0_top/u_ao_mem_ctrl/data_reg_dly_73_s0/CLK
-0.233 -0.233 tHld 1 R7C2[2][A] u_la0_top/u_ao_mem_ctrl/data_reg_dly_73_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.064, 100.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path19

Path Summary:

Slack 0.297
Data Arrival Time 0.064
Data Required Time -0.233
From u_hard_dphy/mipi_dphy_inst
To u_la0_top/u_ao_mem_ctrl/data_reg_dly_74_s0
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 681 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
0.064 0.064 tC2Q RF 2 - u_hard_dphy/mipi_dphy_inst/D0LN_HSRXD[7]
0.064 0.000 tNET FF 1 R7C2[2][B] u_la0_top/u_ao_mem_ctrl/data_reg_dly_74_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 1 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
0.000 0.000 tNET RR 1 R7C2[2][B] u_la0_top/u_ao_mem_ctrl/data_reg_dly_74_s0/CLK
-0.233 -0.233 tHld 1 R7C2[2][B] u_la0_top/u_ao_mem_ctrl/data_reg_dly_74_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.064, 100.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path20

Path Summary:

Slack 0.297
Data Arrival Time 0.064
Data Required Time -0.233
From u_hard_dphy/mipi_dphy_inst
To u_la0_top/u_ao_mem_ctrl/data_reg_dly_75_s0
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 681 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
0.064 0.064 tC2Q RF 2 - u_hard_dphy/mipi_dphy_inst/D0LN_HSRXD_VLD
0.064 0.000 tNET FF 1 R6C3[3][A] u_la0_top/u_ao_mem_ctrl/data_reg_dly_75_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 1 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
0.000 0.000 tNET RR 1 R6C3[3][A] u_la0_top/u_ao_mem_ctrl/data_reg_dly_75_s0/CLK
-0.233 -0.233 tHld 1 R6C3[3][A] u_la0_top/u_ao_mem_ctrl/data_reg_dly_75_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.064, 100.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 3.559
Data Arrival Time 11.094
Data Required Time 14.653
From u_la0_top/rst_ao_s0
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 byte_clk
7.500 0.000 tCL FF 681 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
7.500 0.000 tNET FF 1 R2C6[1][A] u_la0_top/rst_ao_s0/CLK
7.943 0.442 tC2Q FF 68 R2C6[1][A] u_la0_top/rst_ao_s0/Q
11.094 3.151 tNET FF 1 R2C11[2][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
15.000 0.000 tNET RR 1 R2C11[2][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/CLK
14.653 -0.347 tSu 1 R2C11[2][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5

Path Statistics:

Clock Skew 0.000
Setup Relationship 7.500
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.151, 87.687%; tC2Q: 0.442, 12.313%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path2

Path Summary:

Slack 3.559
Data Arrival Time 11.094
Data Required Time 14.653
From u_la0_top/rst_ao_s0
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 byte_clk
7.500 0.000 tCL FF 681 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
7.500 0.000 tNET FF 1 R2C6[1][A] u_la0_top/rst_ao_s0/CLK
7.943 0.442 tC2Q FF 68 R2C6[1][A] u_la0_top/rst_ao_s0/Q
11.094 3.151 tNET FF 1 R2C11[0][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
15.000 0.000 tNET RR 1 R2C11[0][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK
14.653 -0.347 tSu 1 R2C11[0][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 7.500
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.151, 87.687%; tC2Q: 0.442, 12.313%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path3

Path Summary:

Slack 3.559
Data Arrival Time 11.094
Data Required Time 14.653
From u_la0_top/rst_ao_s0
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 byte_clk
7.500 0.000 tCL FF 681 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
7.500 0.000 tNET FF 1 R2C6[1][A] u_la0_top/rst_ao_s0/CLK
7.943 0.442 tC2Q FF 68 R2C6[1][A] u_la0_top/rst_ao_s0/Q
11.094 3.151 tNET FF 1 R2C11[0][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
15.000 0.000 tNET RR 1 R2C11[0][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK
14.653 -0.347 tSu 1 R2C11[0][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 7.500
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.151, 87.687%; tC2Q: 0.442, 12.313%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path4

Path Summary:

Slack 3.559
Data Arrival Time 11.094
Data Required Time 14.653
From u_la0_top/rst_ao_s0
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 byte_clk
7.500 0.000 tCL FF 681 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
7.500 0.000 tNET FF 1 R2C6[1][A] u_la0_top/rst_ao_s0/CLK
7.943 0.442 tC2Q FF 68 R2C6[1][A] u_la0_top/rst_ao_s0/Q
11.094 3.151 tNET FF 1 R2C11[1][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
15.000 0.000 tNET RR 1 R2C11[1][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/CLK
14.653 -0.347 tSu 1 R2C11[1][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 7.500
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.151, 87.687%; tC2Q: 0.442, 12.313%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path5

Path Summary:

Slack 3.559
Data Arrival Time 11.094
Data Required Time 14.653
From u_la0_top/rst_ao_s0
To u_la0_top/u_ao_mem_ctrl/capture_length_zero_flag_s0
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 byte_clk
7.500 0.000 tCL FF 681 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
7.500 0.000 tNET FF 1 R2C6[1][A] u_la0_top/rst_ao_s0/CLK
7.943 0.442 tC2Q FF 68 R2C6[1][A] u_la0_top/rst_ao_s0/Q
11.094 3.151 tNET FF 1 R2C11[2][A] u_la0_top/u_ao_mem_ctrl/capture_length_zero_flag_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
15.000 0.000 tNET RR 1 R2C11[2][A] u_la0_top/u_ao_mem_ctrl/capture_length_zero_flag_s0/CLK
14.653 -0.347 tSu 1 R2C11[2][A] u_la0_top/u_ao_mem_ctrl/capture_length_zero_flag_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 7.500
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.151, 87.687%; tC2Q: 0.442, 12.313%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path6

Path Summary:

Slack 3.559
Data Arrival Time 11.094
Data Required Time 14.653
From u_la0_top/rst_ao_s0
To u_la0_top/capture_end_dly_s0
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 byte_clk
7.500 0.000 tCL FF 681 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
7.500 0.000 tNET FF 1 R2C6[1][A] u_la0_top/rst_ao_s0/CLK
7.943 0.442 tC2Q FF 68 R2C6[1][A] u_la0_top/rst_ao_s0/Q
11.094 3.151 tNET FF 1 R2C11[3][A] u_la0_top/capture_end_dly_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
15.000 0.000 tNET RR 1 R2C11[3][A] u_la0_top/capture_end_dly_s0/CLK
14.653 -0.347 tSu 1 R2C11[3][A] u_la0_top/capture_end_dly_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 7.500
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.151, 87.687%; tC2Q: 0.442, 12.313%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path7

Path Summary:

Slack 3.559
Data Arrival Time 11.094
Data Required Time 14.653
From u_la0_top/rst_ao_s0
To u_la0_top/internal_reg_start_dly_0_s0
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 byte_clk
7.500 0.000 tCL FF 681 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
7.500 0.000 tNET FF 1 R2C6[1][A] u_la0_top/rst_ao_s0/CLK
7.943 0.442 tC2Q FF 68 R2C6[1][A] u_la0_top/rst_ao_s0/Q
11.094 3.151 tNET FF 1 R2C11[3][B] u_la0_top/internal_reg_start_dly_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
15.000 0.000 tNET RR 1 R2C11[3][B] u_la0_top/internal_reg_start_dly_0_s0/CLK
14.653 -0.347 tSu 1 R2C11[3][B] u_la0_top/internal_reg_start_dly_0_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 7.500
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.151, 87.687%; tC2Q: 0.442, 12.313%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path8

Path Summary:

Slack 3.562
Data Arrival Time 11.090
Data Required Time 14.653
From u_la0_top/rst_ao_s0
To u_la0_top/u_ao_match_2/trig_dly_in_0_s0
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 byte_clk
7.500 0.000 tCL FF 681 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
7.500 0.000 tNET FF 1 R2C6[1][A] u_la0_top/rst_ao_s0/CLK
7.943 0.442 tC2Q FF 68 R2C6[1][A] u_la0_top/rst_ao_s0/Q
11.090 3.148 tNET FF 1 R3C10[3][B] u_la0_top/u_ao_match_2/trig_dly_in_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
15.000 0.000 tNET RR 1 R3C10[3][B] u_la0_top/u_ao_match_2/trig_dly_in_0_s0/CLK
14.653 -0.347 tSu 1 R3C10[3][B] u_la0_top/u_ao_match_2/trig_dly_in_0_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 7.500
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.148, 87.675%; tC2Q: 0.442, 12.325%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path9

Path Summary:

Slack 3.562
Data Arrival Time 11.090
Data Required Time 14.653
From u_la0_top/rst_ao_s0
To u_la0_top/u_ao_match_2/trig_dly_in_1_s0
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 byte_clk
7.500 0.000 tCL FF 681 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
7.500 0.000 tNET FF 1 R2C6[1][A] u_la0_top/rst_ao_s0/CLK
7.943 0.442 tC2Q FF 68 R2C6[1][A] u_la0_top/rst_ao_s0/Q
11.090 3.148 tNET FF 1 R3C10[2][A] u_la0_top/u_ao_match_2/trig_dly_in_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
15.000 0.000 tNET RR 1 R3C10[2][A] u_la0_top/u_ao_match_2/trig_dly_in_1_s0/CLK
14.653 -0.347 tSu 1 R3C10[2][A] u_la0_top/u_ao_match_2/trig_dly_in_1_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 7.500
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.148, 87.675%; tC2Q: 0.442, 12.325%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path10

Path Summary:

Slack 3.562
Data Arrival Time 11.090
Data Required Time 14.653
From u_la0_top/rst_ao_s0
To u_la0_top/u_ao_match_2/trig_dly_in_2_s0
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 byte_clk
7.500 0.000 tCL FF 681 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
7.500 0.000 tNET FF 1 R2C6[1][A] u_la0_top/rst_ao_s0/CLK
7.943 0.442 tC2Q FF 68 R2C6[1][A] u_la0_top/rst_ao_s0/Q
11.090 3.148 tNET FF 1 R3C10[2][B] u_la0_top/u_ao_match_2/trig_dly_in_2_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
15.000 0.000 tNET RR 1 R3C10[2][B] u_la0_top/u_ao_match_2/trig_dly_in_2_s0/CLK
14.653 -0.347 tSu 1 R3C10[2][B] u_la0_top/u_ao_match_2/trig_dly_in_2_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 7.500
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.148, 87.675%; tC2Q: 0.442, 12.325%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path11

Path Summary:

Slack 3.562
Data Arrival Time 11.090
Data Required Time 14.653
From u_la0_top/rst_ao_s0
To u_la0_top/u_ao_match_2/trig_dly_in_3_s0
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 byte_clk
7.500 0.000 tCL FF 681 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
7.500 0.000 tNET FF 1 R2C6[1][A] u_la0_top/rst_ao_s0/CLK
7.943 0.442 tC2Q FF 68 R2C6[1][A] u_la0_top/rst_ao_s0/Q
11.090 3.148 tNET FF 1 R3C10[3][A] u_la0_top/u_ao_match_2/trig_dly_in_3_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
15.000 0.000 tNET RR 1 R3C10[3][A] u_la0_top/u_ao_match_2/trig_dly_in_3_s0/CLK
14.653 -0.347 tSu 1 R3C10[3][A] u_la0_top/u_ao_match_2/trig_dly_in_3_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 7.500
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.148, 87.675%; tC2Q: 0.442, 12.325%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path12

Path Summary:

Slack 3.562
Data Arrival Time 11.090
Data Required Time 14.653
From u_la0_top/rst_ao_s0
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 byte_clk
7.500 0.000 tCL FF 681 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
7.500 0.000 tNET FF 1 R2C6[1][A] u_la0_top/rst_ao_s0/CLK
7.943 0.442 tC2Q FF 68 R2C6[1][A] u_la0_top/rst_ao_s0/Q
11.090 3.148 tNET FF 1 R3C10[0][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
15.000 0.000 tNET RR 1 R3C10[0][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK
14.653 -0.347 tSu 1 R3C10[0][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 7.500
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.148, 87.675%; tC2Q: 0.442, 12.325%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path13

Path Summary:

Slack 3.562
Data Arrival Time 11.090
Data Required Time 14.653
From u_la0_top/rst_ao_s0
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 byte_clk
7.500 0.000 tCL FF 681 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
7.500 0.000 tNET FF 1 R2C6[1][A] u_la0_top/rst_ao_s0/CLK
7.943 0.442 tC2Q FF 68 R2C6[1][A] u_la0_top/rst_ao_s0/Q
11.090 3.148 tNET FF 1 R3C10[0][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
15.000 0.000 tNET RR 1 R3C10[0][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
14.653 -0.347 tSu 1 R3C10[0][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 7.500
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.148, 87.675%; tC2Q: 0.442, 12.325%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path14

Path Summary:

Slack 3.562
Data Arrival Time 11.090
Data Required Time 14.653
From u_la0_top/rst_ao_s0
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 byte_clk
7.500 0.000 tCL FF 681 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
7.500 0.000 tNET FF 1 R2C6[1][A] u_la0_top/rst_ao_s0/CLK
7.943 0.442 tC2Q FF 68 R2C6[1][A] u_la0_top/rst_ao_s0/Q
11.090 3.148 tNET FF 1 R3C10[1][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
15.000 0.000 tNET RR 1 R3C10[1][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK
14.653 -0.347 tSu 1 R3C10[1][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 7.500
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.148, 87.675%; tC2Q: 0.442, 12.325%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path15

Path Summary:

Slack 3.562
Data Arrival Time 11.090
Data Required Time 14.653
From u_la0_top/rst_ao_s0
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 byte_clk
7.500 0.000 tCL FF 681 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
7.500 0.000 tNET FF 1 R2C6[1][A] u_la0_top/rst_ao_s0/CLK
7.943 0.442 tC2Q FF 68 R2C6[1][A] u_la0_top/rst_ao_s0/Q
11.090 3.148 tNET FF 1 R3C10[1][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
15.000 0.000 tNET RR 1 R3C10[1][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK
14.653 -0.347 tSu 1 R3C10[1][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 7.500
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.148, 87.675%; tC2Q: 0.442, 12.325%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path16

Path Summary:

Slack 3.562
Data Arrival Time 11.090
Data Required Time 14.653
From u_la0_top/rst_ao_s0
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 byte_clk
7.500 0.000 tCL FF 681 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
7.500 0.000 tNET FF 1 R2C6[1][A] u_la0_top/rst_ao_s0/CLK
7.943 0.442 tC2Q FF 68 R2C6[1][A] u_la0_top/rst_ao_s0/Q
11.090 3.148 tNET FF 1 R3C9[1][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
15.000 0.000 tNET RR 1 R3C9[1][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK
14.653 -0.347 tSu 1 R3C9[1][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 7.500
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.148, 87.675%; tC2Q: 0.442, 12.325%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path17

Path Summary:

Slack 3.602
Data Arrival Time 11.051
Data Required Time 14.653
From u_la0_top/rst_ao_s0
To u_la0_top/capture_window_sel_3_s1
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 byte_clk
7.500 0.000 tCL FF 681 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
7.500 0.000 tNET FF 1 R2C6[1][A] u_la0_top/rst_ao_s0/CLK
7.943 0.442 tC2Q FF 68 R2C6[1][A] u_la0_top/rst_ao_s0/Q
11.051 3.108 tNET FF 1 R2C7[0][A] u_la0_top/capture_window_sel_3_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
15.000 0.000 tNET RR 1 R2C7[0][A] u_la0_top/capture_window_sel_3_s1/CLK
14.653 -0.347 tSu 1 R2C7[0][A] u_la0_top/capture_window_sel_3_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 7.500
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.108, 87.537%; tC2Q: 0.442, 12.463%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path18

Path Summary:

Slack 3.602
Data Arrival Time 11.051
Data Required Time 14.653
From u_la0_top/rst_ao_s0
To u_la0_top/trigger_seq_start_s1
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 byte_clk
7.500 0.000 tCL FF 681 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
7.500 0.000 tNET FF 1 R2C6[1][A] u_la0_top/rst_ao_s0/CLK
7.943 0.442 tC2Q FF 68 R2C6[1][A] u_la0_top/rst_ao_s0/Q
11.051 3.108 tNET FF 1 R2C7[2][A] u_la0_top/trigger_seq_start_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
15.000 0.000 tNET RR 1 R2C7[2][A] u_la0_top/trigger_seq_start_s1/CLK
14.653 -0.347 tSu 1 R2C7[2][A] u_la0_top/trigger_seq_start_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 7.500
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.108, 87.537%; tC2Q: 0.442, 12.463%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path19

Path Summary:

Slack 3.602
Data Arrival Time 11.051
Data Required Time 14.653
From u_la0_top/rst_ao_s0
To u_la0_top/internal_reg_start_dly_1_s0
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 byte_clk
7.500 0.000 tCL FF 681 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
7.500 0.000 tNET FF 1 R2C6[1][A] u_la0_top/rst_ao_s0/CLK
7.943 0.442 tC2Q FF 68 R2C6[1][A] u_la0_top/rst_ao_s0/Q
11.051 3.108 tNET FF 1 R2C7[1][B] u_la0_top/internal_reg_start_dly_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
15.000 0.000 tNET RR 1 R2C7[1][B] u_la0_top/internal_reg_start_dly_1_s0/CLK
14.653 -0.347 tSu 1 R2C7[1][B] u_la0_top/internal_reg_start_dly_1_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 7.500
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.108, 87.537%; tC2Q: 0.442, 12.463%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path20

Path Summary:

Slack 3.602
Data Arrival Time 11.051
Data Required Time 14.653
From u_la0_top/rst_ao_s0
To u_la0_top/internal_reg_force_triger_syn_1_s0
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 byte_clk
7.500 0.000 tCL FF 681 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
7.500 0.000 tNET FF 1 R2C6[1][A] u_la0_top/rst_ao_s0/CLK
7.943 0.442 tC2Q FF 68 R2C6[1][A] u_la0_top/rst_ao_s0/Q
11.051 3.108 tNET FF 1 R2C7[1][A] u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
15.000 0.000 tNET RR 1 R2C7[1][A] u_la0_top/internal_reg_force_triger_syn_1_s0/CLK
14.653 -0.347 tSu 1 R2C7[1][A] u_la0_top/internal_reg_force_triger_syn_1_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 7.500
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.108, 87.537%; tC2Q: 0.442, 12.463%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path21

Path Summary:

Slack 3.604
Data Arrival Time 11.048
Data Required Time 14.653
From u_la0_top/rst_ao_s0
To u_la0_top/triger_level_cnt_0_s3
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 byte_clk
7.500 0.000 tCL FF 681 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
7.500 0.000 tNET FF 1 R2C6[1][A] u_la0_top/rst_ao_s0/CLK
7.943 0.442 tC2Q FF 68 R2C6[1][A] u_la0_top/rst_ao_s0/Q
11.048 3.106 tNET FF 1 R2C3[3][B] u_la0_top/triger_level_cnt_0_s3/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
15.000 0.000 tNET RR 1 R2C3[3][B] u_la0_top/triger_level_cnt_0_s3/CLK
14.653 -0.347 tSu 1 R2C3[3][B] u_la0_top/triger_level_cnt_0_s3

Path Statistics:

Clock Skew 0.000
Setup Relationship 7.500
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.106, 87.529%; tC2Q: 0.442, 12.471%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path22

Path Summary:

Slack 3.604
Data Arrival Time 11.048
Data Required Time 14.653
From u_la0_top/rst_ao_s0
To u_la0_top/triger_s0
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 byte_clk
7.500 0.000 tCL FF 681 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
7.500 0.000 tNET FF 1 R2C6[1][A] u_la0_top/rst_ao_s0/CLK
7.943 0.442 tC2Q FF 68 R2C6[1][A] u_la0_top/rst_ao_s0/Q
11.048 3.106 tNET FF 1 R2C3[3][A] u_la0_top/triger_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
15.000 0.000 tNET RR 1 R2C3[3][A] u_la0_top/triger_s0/CLK
14.653 -0.347 tSu 1 R2C3[3][A] u_la0_top/triger_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 7.500
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.106, 87.529%; tC2Q: 0.442, 12.471%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path23

Path Summary:

Slack 3.604
Data Arrival Time 11.048
Data Required Time 14.653
From u_la0_top/rst_ao_s0
To u_la0_top/start_reg_s0
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 byte_clk
7.500 0.000 tCL FF 681 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
7.500 0.000 tNET FF 1 R2C6[1][A] u_la0_top/rst_ao_s0/CLK
7.943 0.442 tC2Q FF 68 R2C6[1][A] u_la0_top/rst_ao_s0/Q
11.048 3.106 tNET FF 1 R2C3[2][B] u_la0_top/start_reg_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
15.000 0.000 tNET RR 1 R2C3[2][B] u_la0_top/start_reg_s0/CLK
14.653 -0.347 tSu 1 R2C3[2][B] u_la0_top/start_reg_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 7.500
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.106, 87.529%; tC2Q: 0.442, 12.471%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path24

Path Summary:

Slack 3.605
Data Arrival Time 11.047
Data Required Time 14.653
From u_la0_top/rst_ao_s0
To u_la0_top/u_ao_mem_ctrl/capture_loop_s1
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 byte_clk
7.500 0.000 tCL FF 681 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
7.500 0.000 tNET FF 1 R2C6[1][A] u_la0_top/rst_ao_s0/CLK
7.943 0.442 tC2Q FF 68 R2C6[1][A] u_la0_top/rst_ao_s0/Q
11.047 3.105 tNET FF 1 R2C12[1][A] u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
15.000 0.000 tNET RR 1 R2C12[1][A] u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK
14.653 -0.347 tSu 1 R2C12[1][A] u_la0_top/u_ao_mem_ctrl/capture_loop_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 7.500
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.105, 87.526%; tC2Q: 0.442, 12.474%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path25

Path Summary:

Slack 3.605
Data Arrival Time 11.047
Data Required Time 14.653
From u_la0_top/rst_ao_s0
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 byte_clk
7.500 0.000 tCL FF 681 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
7.500 0.000 tNET FF 1 R2C6[1][A] u_la0_top/rst_ao_s0/CLK
7.943 0.442 tC2Q FF 68 R2C6[1][A] u_la0_top/rst_ao_s0/Q
11.047 3.105 tNET FF 1 R2C12[0][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 - u_hard_dphy/mipi_dphy_inst/RX_CLK_O
15.000 0.000 tNET RR 1 R2C12[0][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
14.653 -0.347 tSu 1 R2C12[0][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 7.500
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.105, 87.526%; tC2Q: 0.442, 12.474%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 1.639
Data Arrival Time 2.504
Data Required Time 0.865
From u_ov5647_ctrl/resend_s0
To u_ov5647_ctrl/I2C/busy_sr_0_s1
Launch Clk clk_50:[R]
Latch Clk clk_50:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 1 IOB29[A] OSC_50M_ibuf/I
0.675 0.675 tINS RR 218 IOB29[A] OSC_50M_ibuf/O
1.035 0.360 tNET RR 1 R12C29[3][A] u_ov5647_ctrl/resend_s0/CLK
1.215 0.180 tC2Q RR 103 R12C29[3][A] u_ov5647_ctrl/resend_s0/Q
2.504 1.288 tNET RR 1 R17C29[1][B] u_ov5647_ctrl/I2C/busy_sr_0_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 1 IOB29[A] OSC_50M_ibuf/I
0.675 0.675 tINS RR 218 IOB29[A] OSC_50M_ibuf/O
1.054 0.378 tNET RR 1 R17C29[1][B] u_ov5647_ctrl/I2C/busy_sr_0_s1/CLK
0.865 -0.189 tHld 1 R17C29[1][B] u_ov5647_ctrl/I2C/busy_sr_0_s1

Path Statistics:

Clock Skew 0.018
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 65.234%; route: 0.360, 34.766%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.288, 87.742%; tC2Q: 0.180, 12.258%
Required Clock Path Delay cell: 0.675, 64.112%; route: 0.378, 35.888%

Path2

Path Summary:

Slack 1.639
Data Arrival Time 2.504
Data Required Time 0.865
From u_ov5647_ctrl/resend_s0
To u_ov5647_ctrl/I2C/busy_sr_1_s1
Launch Clk clk_50:[R]
Latch Clk clk_50:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 1 IOB29[A] OSC_50M_ibuf/I
0.675 0.675 tINS RR 218 IOB29[A] OSC_50M_ibuf/O
1.035 0.360 tNET RR 1 R12C29[3][A] u_ov5647_ctrl/resend_s0/CLK
1.215 0.180 tC2Q RR 103 R12C29[3][A] u_ov5647_ctrl/resend_s0/Q
2.504 1.288 tNET RR 1 R17C29[2][A] u_ov5647_ctrl/I2C/busy_sr_1_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 1 IOB29[A] OSC_50M_ibuf/I
0.675 0.675 tINS RR 218 IOB29[A] OSC_50M_ibuf/O
1.054 0.378 tNET RR 1 R17C29[2][A] u_ov5647_ctrl/I2C/busy_sr_1_s1/CLK
0.865 -0.189 tHld 1 R17C29[2][A] u_ov5647_ctrl/I2C/busy_sr_1_s1

Path Statistics:

Clock Skew 0.018
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 65.234%; route: 0.360, 34.766%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.288, 87.742%; tC2Q: 0.180, 12.258%
Required Clock Path Delay cell: 0.675, 64.112%; route: 0.378, 35.888%

Path3

Path Summary:

Slack 1.639
Data Arrival Time 2.505
Data Required Time 0.866
From u_ov5647_ctrl/resend_s0
To u_ov5647_ctrl/I2C/busy_sr_2_s1
Launch Clk clk_50:[R]
Latch Clk clk_50:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 1 IOB29[A] OSC_50M_ibuf/I
0.675 0.675 tINS RR 218 IOB29[A] OSC_50M_ibuf/O
1.035 0.360 tNET RR 1 R12C29[3][A] u_ov5647_ctrl/resend_s0/CLK
1.215 0.180 tC2Q RR 103 R12C29[3][A] u_ov5647_ctrl/resend_s0/Q
2.505 1.290 tNET RR 1 R18C29[0][B] u_ov5647_ctrl/I2C/busy_sr_2_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 1 IOB29[A] OSC_50M_ibuf/I
0.675 0.675 tINS RR 218 IOB29[A] OSC_50M_ibuf/O
1.055 0.380 tNET RR 1 R18C29[0][B] u_ov5647_ctrl/I2C/busy_sr_2_s1/CLK
0.866 -0.189 tHld 1 R18C29[0][B] u_ov5647_ctrl/I2C/busy_sr_2_s1

Path Statistics:

Clock Skew 0.020
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 65.234%; route: 0.360, 34.766%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.290, 87.755%; tC2Q: 0.180, 12.245%
Required Clock Path Delay cell: 0.675, 64.017%; route: 0.380, 35.983%

Path4

Path Summary:

Slack 1.639
Data Arrival Time 2.502
Data Required Time 0.863
From u_ov5647_ctrl/resend_s0
To u_ov5647_ctrl/I2C/data_sr_6_s1
Launch Clk clk_50:[R]
Latch Clk clk_50:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 1 IOB29[A] OSC_50M_ibuf/I
0.675 0.675 tINS RR 218 IOB29[A] OSC_50M_ibuf/O
1.035 0.360 tNET RR 1 R12C29[3][A] u_ov5647_ctrl/resend_s0/CLK
1.215 0.180 tC2Q RR 103 R12C29[3][A] u_ov5647_ctrl/resend_s0/Q
2.502 1.287 tNET RR 1 R16C29[1][B] u_ov5647_ctrl/I2C/data_sr_6_s1/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 1 IOB29[A] OSC_50M_ibuf/I
0.675 0.675 tINS RR 218 IOB29[A] OSC_50M_ibuf/O
1.052 0.377 tNET RR 1 R16C29[1][B] u_ov5647_ctrl/I2C/data_sr_6_s1/CLK
0.863 -0.189 tHld 1 R16C29[1][B] u_ov5647_ctrl/I2C/data_sr_6_s1

Path Statistics:

Clock Skew 0.017
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 65.234%; route: 0.360, 34.766%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.287, 87.729%; tC2Q: 0.180, 12.271%
Required Clock Path Delay cell: 0.675, 64.207%; route: 0.377, 35.793%

Path5

Path Summary:

Slack 1.639
Data Arrival Time 2.502
Data Required Time 0.863
From u_ov5647_ctrl/resend_s0
To u_ov5647_ctrl/I2C/data_sr_23_s1
Launch Clk clk_50:[R]
Latch Clk clk_50:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 1 IOB29[A] OSC_50M_ibuf/I
0.675 0.675 tINS RR 218 IOB29[A] OSC_50M_ibuf/O
1.035 0.360 tNET RR 1 R12C29[3][A] u_ov5647_ctrl/resend_s0/CLK
1.215 0.180 tC2Q RR 103 R12C29[3][A] u_ov5647_ctrl/resend_s0/Q
2.502 1.287 tNET RR 1 R16C29[2][B] u_ov5647_ctrl/I2C/data_sr_23_s1/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 1 IOB29[A] OSC_50M_ibuf/I
0.675 0.675 tINS RR 218 IOB29[A] OSC_50M_ibuf/O
1.052 0.377 tNET RR 1 R16C29[2][B] u_ov5647_ctrl/I2C/data_sr_23_s1/CLK
0.863 -0.189 tHld 1 R16C29[2][B] u_ov5647_ctrl/I2C/data_sr_23_s1

Path Statistics:

Clock Skew 0.017
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 65.234%; route: 0.360, 34.766%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.287, 87.729%; tC2Q: 0.180, 12.271%
Required Clock Path Delay cell: 0.675, 64.207%; route: 0.377, 35.793%

Path6

Path Summary:

Slack 1.639
Data Arrival Time 2.502
Data Required Time 0.863
From u_ov5647_ctrl/resend_s0
To u_ov5647_ctrl/I2C/data_sr_24_s1
Launch Clk clk_50:[R]
Latch Clk clk_50:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 1 IOB29[A] OSC_50M_ibuf/I
0.675 0.675 tINS RR 218 IOB29[A] OSC_50M_ibuf/O
1.035 0.360 tNET RR 1 R12C29[3][A] u_ov5647_ctrl/resend_s0/CLK
1.215 0.180 tC2Q RR 103 R12C29[3][A] u_ov5647_ctrl/resend_s0/Q
2.502 1.287 tNET RR 1 R16C29[0][A] u_ov5647_ctrl/I2C/data_sr_24_s1/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 1 IOB29[A] OSC_50M_ibuf/I
0.675 0.675 tINS RR 218 IOB29[A] OSC_50M_ibuf/O
1.052 0.377 tNET RR 1 R16C29[0][A] u_ov5647_ctrl/I2C/data_sr_24_s1/CLK
0.863 -0.189 tHld 1 R16C29[0][A] u_ov5647_ctrl/I2C/data_sr_24_s1

Path Statistics:

Clock Skew 0.017
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 65.234%; route: 0.360, 34.766%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.287, 87.729%; tC2Q: 0.180, 12.271%
Required Clock Path Delay cell: 0.675, 64.207%; route: 0.377, 35.793%

Path7

Path Summary:

Slack 1.639
Data Arrival Time 2.502
Data Required Time 0.863
From u_ov5647_ctrl/resend_s0
To u_ov5647_ctrl/I2C/data_sr_29_s1
Launch Clk clk_50:[R]
Latch Clk clk_50:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 1 IOB29[A] OSC_50M_ibuf/I
0.675 0.675 tINS RR 218 IOB29[A] OSC_50M_ibuf/O
1.035 0.360 tNET RR 1 R12C29[3][A] u_ov5647_ctrl/resend_s0/CLK
1.215 0.180 tC2Q RR 103 R12C29[3][A] u_ov5647_ctrl/resend_s0/Q
2.502 1.287 tNET RR 1 R16C29[3][A] u_ov5647_ctrl/I2C/data_sr_29_s1/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 1 IOB29[A] OSC_50M_ibuf/I
0.675 0.675 tINS RR 218 IOB29[A] OSC_50M_ibuf/O
1.052 0.377 tNET RR 1 R16C29[3][A] u_ov5647_ctrl/I2C/data_sr_29_s1/CLK
0.863 -0.189 tHld 1 R16C29[3][A] u_ov5647_ctrl/I2C/data_sr_29_s1

Path Statistics:

Clock Skew 0.017
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 65.234%; route: 0.360, 34.766%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.287, 87.729%; tC2Q: 0.180, 12.271%
Required Clock Path Delay cell: 0.675, 64.207%; route: 0.377, 35.793%

Path8

Path Summary:

Slack 1.639
Data Arrival Time 2.501
Data Required Time 0.862
From u_ov5647_ctrl/resend_s0
To u_ov5647_ctrl/I2C/data_sr_28_s1
Launch Clk clk_50:[R]
Latch Clk clk_50:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 1 IOB29[A] OSC_50M_ibuf/I
0.675 0.675 tINS RR 218 IOB29[A] OSC_50M_ibuf/O
1.035 0.360 tNET RR 1 R12C29[3][A] u_ov5647_ctrl/resend_s0/CLK
1.215 0.180 tC2Q RR 103 R12C29[3][A] u_ov5647_ctrl/resend_s0/Q
2.501 1.285 tNET RR 1 R15C29[0][A] u_ov5647_ctrl/I2C/data_sr_28_s1/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 1 IOB29[A] OSC_50M_ibuf/I
0.675 0.675 tINS RR 218 IOB29[A] OSC_50M_ibuf/O
1.051 0.375 tNET RR 1 R15C29[0][A] u_ov5647_ctrl/I2C/data_sr_28_s1/CLK
0.862 -0.189 tHld 1 R15C29[0][A] u_ov5647_ctrl/I2C/data_sr_28_s1

Path Statistics:

Clock Skew 0.015
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 65.234%; route: 0.360, 34.766%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.285, 87.716%; tC2Q: 0.180, 12.284%
Required Clock Path Delay cell: 0.675, 64.303%; route: 0.375, 35.697%

Path9

Path Summary:

Slack 1.640
Data Arrival Time 2.529
Data Required Time 0.889
From u_ov5647_ctrl/resend_s0
To u_ov5647_ctrl/I2C/busy_sr_4_s1
Launch Clk clk_50:[R]
Latch Clk clk_50:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 1 IOB29[A] OSC_50M_ibuf/I
0.675 0.675 tINS RR 218 IOB29[A] OSC_50M_ibuf/O
1.035 0.360 tNET RR 1 R12C29[3][A] u_ov5647_ctrl/resend_s0/CLK
1.215 0.180 tC2Q RR 103 R12C29[3][A] u_ov5647_ctrl/resend_s0/Q
2.529 1.314 tNET RR 1 R20C32[0][A] u_ov5647_ctrl/I2C/busy_sr_4_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 1 IOB29[A] OSC_50M_ibuf/I
0.675 0.675 tINS RR 218 IOB29[A] OSC_50M_ibuf/O
1.078 0.402 tNET RR 1 R20C32[0][A] u_ov5647_ctrl/I2C/busy_sr_4_s1/CLK
0.889 -0.189 tHld 1 R20C32[0][A] u_ov5647_ctrl/I2C/busy_sr_4_s1

Path Statistics:

Clock Skew 0.042
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 65.234%; route: 0.360, 34.766%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.314, 87.950%; tC2Q: 0.180, 12.050%
Required Clock Path Delay cell: 0.675, 62.681%; route: 0.402, 37.319%

Path10

Path Summary:

Slack 1.640
Data Arrival Time 2.529
Data Required Time 0.889
From u_ov5647_ctrl/resend_s0
To u_ov5647_ctrl/I2C/busy_sr_5_s1
Launch Clk clk_50:[R]
Latch Clk clk_50:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 1 IOB29[A] OSC_50M_ibuf/I
0.675 0.675 tINS RR 218 IOB29[A] OSC_50M_ibuf/O
1.035 0.360 tNET RR 1 R12C29[3][A] u_ov5647_ctrl/resend_s0/CLK
1.215 0.180 tC2Q RR 103 R12C29[3][A] u_ov5647_ctrl/resend_s0/Q
2.529 1.314 tNET RR 1 R20C32[0][B] u_ov5647_ctrl/I2C/busy_sr_5_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 1 IOB29[A] OSC_50M_ibuf/I
0.675 0.675 tINS RR 218 IOB29[A] OSC_50M_ibuf/O
1.078 0.402 tNET RR 1 R20C32[0][B] u_ov5647_ctrl/I2C/busy_sr_5_s1/CLK
0.889 -0.189 tHld 1 R20C32[0][B] u_ov5647_ctrl/I2C/busy_sr_5_s1

Path Statistics:

Clock Skew 0.042
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 65.234%; route: 0.360, 34.766%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.314, 87.950%; tC2Q: 0.180, 12.050%
Required Clock Path Delay cell: 0.675, 62.681%; route: 0.402, 37.319%

Path11

Path Summary:

Slack 1.640
Data Arrival Time 2.529
Data Required Time 0.889
From u_ov5647_ctrl/resend_s0
To u_ov5647_ctrl/I2C/busy_sr_6_s1
Launch Clk clk_50:[R]
Latch Clk clk_50:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 1 IOB29[A] OSC_50M_ibuf/I
0.675 0.675 tINS RR 218 IOB29[A] OSC_50M_ibuf/O
1.035 0.360 tNET RR 1 R12C29[3][A] u_ov5647_ctrl/resend_s0/CLK
1.215 0.180 tC2Q RR 103 R12C29[3][A] u_ov5647_ctrl/resend_s0/Q
2.529 1.314 tNET RR 1 R20C32[1][A] u_ov5647_ctrl/I2C/busy_sr_6_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 1 IOB29[A] OSC_50M_ibuf/I
0.675 0.675 tINS RR 218 IOB29[A] OSC_50M_ibuf/O
1.078 0.402 tNET RR 1 R20C32[1][A] u_ov5647_ctrl/I2C/busy_sr_6_s1/CLK
0.889 -0.189 tHld 1 R20C32[1][A] u_ov5647_ctrl/I2C/busy_sr_6_s1

Path Statistics:

Clock Skew 0.042
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 65.234%; route: 0.360, 34.766%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.314, 87.950%; tC2Q: 0.180, 12.050%
Required Clock Path Delay cell: 0.675, 62.681%; route: 0.402, 37.319%

Path12

Path Summary:

Slack 1.640
Data Arrival Time 2.529
Data Required Time 0.889
From u_ov5647_ctrl/resend_s0
To u_ov5647_ctrl/I2C/busy_sr_7_s1
Launch Clk clk_50:[R]
Latch Clk clk_50:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 1 IOB29[A] OSC_50M_ibuf/I
0.675 0.675 tINS RR 218 IOB29[A] OSC_50M_ibuf/O
1.035 0.360 tNET RR 1 R12C29[3][A] u_ov5647_ctrl/resend_s0/CLK
1.215 0.180 tC2Q RR 103 R12C29[3][A] u_ov5647_ctrl/resend_s0/Q
2.529 1.314 tNET RR 1 R20C32[1][B] u_ov5647_ctrl/I2C/busy_sr_7_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 1 IOB29[A] OSC_50M_ibuf/I
0.675 0.675 tINS RR 218 IOB29[A] OSC_50M_ibuf/O
1.078 0.402 tNET RR 1 R20C32[1][B] u_ov5647_ctrl/I2C/busy_sr_7_s1/CLK
0.889 -0.189 tHld 1 R20C32[1][B] u_ov5647_ctrl/I2C/busy_sr_7_s1

Path Statistics:

Clock Skew 0.042
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 65.234%; route: 0.360, 34.766%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.314, 87.950%; tC2Q: 0.180, 12.050%
Required Clock Path Delay cell: 0.675, 62.681%; route: 0.402, 37.319%

Path13

Path Summary:

Slack 1.640
Data Arrival Time 2.529
Data Required Time 0.889
From u_ov5647_ctrl/resend_s0
To u_ov5647_ctrl/I2C/busy_sr_8_s1
Launch Clk clk_50:[R]
Latch Clk clk_50:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 1 IOB29[A] OSC_50M_ibuf/I
0.675 0.675 tINS RR 218 IOB29[A] OSC_50M_ibuf/O
1.035 0.360 tNET RR 1 R12C29[3][A] u_ov5647_ctrl/resend_s0/CLK
1.215 0.180 tC2Q RR 103 R12C29[3][A] u_ov5647_ctrl/resend_s0/Q
2.529 1.314 tNET RR 1 R20C32[2][A] u_ov5647_ctrl/I2C/busy_sr_8_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 1 IOB29[A] OSC_50M_ibuf/I
0.675 0.675 tINS RR 218 IOB29[A] OSC_50M_ibuf/O
1.078 0.402 tNET RR 1 R20C32[2][A] u_ov5647_ctrl/I2C/busy_sr_8_s1/CLK
0.889 -0.189 tHld 1 R20C32[2][A] u_ov5647_ctrl/I2C/busy_sr_8_s1

Path Statistics:

Clock Skew 0.042
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 65.234%; route: 0.360, 34.766%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.314, 87.950%; tC2Q: 0.180, 12.050%
Required Clock Path Delay cell: 0.675, 62.681%; route: 0.402, 37.319%

Path14

Path Summary:

Slack 1.640
Data Arrival Time 2.529
Data Required Time 0.889
From u_ov5647_ctrl/resend_s0
To u_ov5647_ctrl/I2C/busy_sr_9_s1
Launch Clk clk_50:[R]
Latch Clk clk_50:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 1 IOB29[A] OSC_50M_ibuf/I
0.675 0.675 tINS RR 218 IOB29[A] OSC_50M_ibuf/O
1.035 0.360 tNET RR 1 R12C29[3][A] u_ov5647_ctrl/resend_s0/CLK
1.215 0.180 tC2Q RR 103 R12C29[3][A] u_ov5647_ctrl/resend_s0/Q
2.529 1.314 tNET RR 1 R20C32[2][B] u_ov5647_ctrl/I2C/busy_sr_9_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 1 IOB29[A] OSC_50M_ibuf/I
0.675 0.675 tINS RR 218 IOB29[A] OSC_50M_ibuf/O
1.078 0.402 tNET RR 1 R20C32[2][B] u_ov5647_ctrl/I2C/busy_sr_9_s1/CLK
0.889 -0.189 tHld 1 R20C32[2][B] u_ov5647_ctrl/I2C/busy_sr_9_s1

Path Statistics:

Clock Skew 0.042
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 65.234%; route: 0.360, 34.766%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.314, 87.950%; tC2Q: 0.180, 12.050%
Required Clock Path Delay cell: 0.675, 62.681%; route: 0.402, 37.319%

Path15

Path Summary:

Slack 1.640
Data Arrival Time 2.529
Data Required Time 0.889
From u_ov5647_ctrl/resend_s0
To u_ov5647_ctrl/I2C/busy_sr_10_s1
Launch Clk clk_50:[R]
Latch Clk clk_50:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 1 IOB29[A] OSC_50M_ibuf/I
0.675 0.675 tINS RR 218 IOB29[A] OSC_50M_ibuf/O
1.035 0.360 tNET RR 1 R12C29[3][A] u_ov5647_ctrl/resend_s0/CLK
1.215 0.180 tC2Q RR 103 R12C29[3][A] u_ov5647_ctrl/resend_s0/Q
2.529 1.314 tNET RR 1 R20C32[3][A] u_ov5647_ctrl/I2C/busy_sr_10_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 1 IOB29[A] OSC_50M_ibuf/I
0.675 0.675 tINS RR 218 IOB29[A] OSC_50M_ibuf/O
1.078 0.402 tNET RR 1 R20C32[3][A] u_ov5647_ctrl/I2C/busy_sr_10_s1/CLK
0.889 -0.189 tHld 1 R20C32[3][A] u_ov5647_ctrl/I2C/busy_sr_10_s1

Path Statistics:

Clock Skew 0.042
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 65.234%; route: 0.360, 34.766%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.314, 87.950%; tC2Q: 0.180, 12.050%
Required Clock Path Delay cell: 0.675, 62.681%; route: 0.402, 37.319%

Path16

Path Summary:

Slack 1.640
Data Arrival Time 2.527
Data Required Time 0.887
From u_ov5647_ctrl/resend_s0
To u_ov5647_ctrl/I2C/busy_sr_12_s1
Launch Clk clk_50:[R]
Latch Clk clk_50:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 1 IOB29[A] OSC_50M_ibuf/I
0.675 0.675 tINS RR 218 IOB29[A] OSC_50M_ibuf/O
1.035 0.360 tNET RR 1 R12C29[3][A] u_ov5647_ctrl/resend_s0/CLK
1.215 0.180 tC2Q RR 103 R12C29[3][A] u_ov5647_ctrl/resend_s0/Q
2.527 1.312 tNET RR 1 R21C32[2][A] u_ov5647_ctrl/I2C/busy_sr_12_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 1 IOB29[A] OSC_50M_ibuf/I
0.675 0.675 tINS RR 218 IOB29[A] OSC_50M_ibuf/O
1.076 0.400 tNET RR 1 R21C32[2][A] u_ov5647_ctrl/I2C/busy_sr_12_s1/CLK
0.887 -0.189 tHld 1 R21C32[2][A] u_ov5647_ctrl/I2C/busy_sr_12_s1

Path Statistics:

Clock Skew 0.040
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 65.234%; route: 0.360, 34.766%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.312, 87.932%; tC2Q: 0.180, 12.068%
Required Clock Path Delay cell: 0.675, 62.808%; route: 0.400, 37.192%

Path17

Path Summary:

Slack 1.640
Data Arrival Time 2.527
Data Required Time 0.887
From u_ov5647_ctrl/resend_s0
To u_ov5647_ctrl/I2C/busy_sr_13_s1
Launch Clk clk_50:[R]
Latch Clk clk_50:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 1 IOB29[A] OSC_50M_ibuf/I
0.675 0.675 tINS RR 218 IOB29[A] OSC_50M_ibuf/O
1.035 0.360 tNET RR 1 R12C29[3][A] u_ov5647_ctrl/resend_s0/CLK
1.215 0.180 tC2Q RR 103 R12C29[3][A] u_ov5647_ctrl/resend_s0/Q
2.527 1.312 tNET RR 1 R21C32[2][B] u_ov5647_ctrl/I2C/busy_sr_13_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 1 IOB29[A] OSC_50M_ibuf/I
0.675 0.675 tINS RR 218 IOB29[A] OSC_50M_ibuf/O
1.076 0.400 tNET RR 1 R21C32[2][B] u_ov5647_ctrl/I2C/busy_sr_13_s1/CLK
0.887 -0.189 tHld 1 R21C32[2][B] u_ov5647_ctrl/I2C/busy_sr_13_s1

Path Statistics:

Clock Skew 0.040
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 65.234%; route: 0.360, 34.766%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.312, 87.932%; tC2Q: 0.180, 12.068%
Required Clock Path Delay cell: 0.675, 62.808%; route: 0.400, 37.192%

Path18

Path Summary:

Slack 1.640
Data Arrival Time 2.527
Data Required Time 0.887
From u_ov5647_ctrl/resend_s0
To u_ov5647_ctrl/I2C/busy_sr_14_s1
Launch Clk clk_50:[R]
Latch Clk clk_50:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 1 IOB29[A] OSC_50M_ibuf/I
0.675 0.675 tINS RR 218 IOB29[A] OSC_50M_ibuf/O
1.035 0.360 tNET RR 1 R12C29[3][A] u_ov5647_ctrl/resend_s0/CLK
1.215 0.180 tC2Q RR 103 R12C29[3][A] u_ov5647_ctrl/resend_s0/Q
2.527 1.312 tNET RR 1 R21C32[3][A] u_ov5647_ctrl/I2C/busy_sr_14_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 1 IOB29[A] OSC_50M_ibuf/I
0.675 0.675 tINS RR 218 IOB29[A] OSC_50M_ibuf/O
1.076 0.400 tNET RR 1 R21C32[3][A] u_ov5647_ctrl/I2C/busy_sr_14_s1/CLK
0.887 -0.189 tHld 1 R21C32[3][A] u_ov5647_ctrl/I2C/busy_sr_14_s1

Path Statistics:

Clock Skew 0.040
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 65.234%; route: 0.360, 34.766%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.312, 87.932%; tC2Q: 0.180, 12.068%
Required Clock Path Delay cell: 0.675, 62.808%; route: 0.400, 37.192%

Path19

Path Summary:

Slack 1.640
Data Arrival Time 2.527
Data Required Time 0.887
From u_ov5647_ctrl/resend_s0
To u_ov5647_ctrl/I2C/busy_sr_20_s1
Launch Clk clk_50:[R]
Latch Clk clk_50:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 1 IOB29[A] OSC_50M_ibuf/I
0.675 0.675 tINS RR 218 IOB29[A] OSC_50M_ibuf/O
1.035 0.360 tNET RR 1 R12C29[3][A] u_ov5647_ctrl/resend_s0/CLK
1.215 0.180 tC2Q RR 103 R12C29[3][A] u_ov5647_ctrl/resend_s0/Q
2.527 1.312 tNET RR 1 R21C32[1][B] u_ov5647_ctrl/I2C/busy_sr_20_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 1 IOB29[A] OSC_50M_ibuf/I
0.675 0.675 tINS RR 218 IOB29[A] OSC_50M_ibuf/O
1.076 0.400 tNET RR 1 R21C32[1][B] u_ov5647_ctrl/I2C/busy_sr_20_s1/CLK
0.887 -0.189 tHld 1 R21C32[1][B] u_ov5647_ctrl/I2C/busy_sr_20_s1

Path Statistics:

Clock Skew 0.040
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 65.234%; route: 0.360, 34.766%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.312, 87.932%; tC2Q: 0.180, 12.068%
Required Clock Path Delay cell: 0.675, 62.808%; route: 0.400, 37.192%

Path20

Path Summary:

Slack 1.640
Data Arrival Time 2.527
Data Required Time 0.887
From u_ov5647_ctrl/resend_s0
To u_ov5647_ctrl/I2C/busy_sr_26_s1
Launch Clk clk_50:[R]
Latch Clk clk_50:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 1 IOB29[A] OSC_50M_ibuf/I
0.675 0.675 tINS RR 218 IOB29[A] OSC_50M_ibuf/O
1.035 0.360 tNET RR 1 R12C29[3][A] u_ov5647_ctrl/resend_s0/CLK
1.215 0.180 tC2Q RR 103 R12C29[3][A] u_ov5647_ctrl/resend_s0/Q
2.527 1.312 tNET RR 1 R21C32[0][A] u_ov5647_ctrl/I2C/busy_sr_26_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 1 IOB29[A] OSC_50M_ibuf/I
0.675 0.675 tINS RR 218 IOB29[A] OSC_50M_ibuf/O
1.076 0.400 tNET RR 1 R21C32[0][A] u_ov5647_ctrl/I2C/busy_sr_26_s1/CLK
0.887 -0.189 tHld 1 R21C32[0][A] u_ov5647_ctrl/I2C/busy_sr_26_s1

Path Statistics:

Clock Skew 0.040
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 65.234%; route: 0.360, 34.766%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.312, 87.932%; tC2Q: 0.180, 12.068%
Required Clock Path Delay cell: 0.675, 62.808%; route: 0.400, 37.192%

Path21

Path Summary:

Slack 1.640
Data Arrival Time 2.527
Data Required Time 0.887
From u_ov5647_ctrl/resend_s0
To u_ov5647_ctrl/I2C/busy_sr_27_s1
Launch Clk clk_50:[R]
Latch Clk clk_50:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 1 IOB29[A] OSC_50M_ibuf/I
0.675 0.675 tINS RR 218 IOB29[A] OSC_50M_ibuf/O
1.035 0.360 tNET RR 1 R12C29[3][A] u_ov5647_ctrl/resend_s0/CLK
1.215 0.180 tC2Q RR 103 R12C29[3][A] u_ov5647_ctrl/resend_s0/Q
2.527 1.312 tNET RR 1 R21C32[0][B] u_ov5647_ctrl/I2C/busy_sr_27_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 1 IOB29[A] OSC_50M_ibuf/I
0.675 0.675 tINS RR 218 IOB29[A] OSC_50M_ibuf/O
1.076 0.400 tNET RR 1 R21C32[0][B] u_ov5647_ctrl/I2C/busy_sr_27_s1/CLK
0.887 -0.189 tHld 1 R21C32[0][B] u_ov5647_ctrl/I2C/busy_sr_27_s1

Path Statistics:

Clock Skew 0.040
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 65.234%; route: 0.360, 34.766%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.312, 87.932%; tC2Q: 0.180, 12.068%
Required Clock Path Delay cell: 0.675, 62.808%; route: 0.400, 37.192%

Path22

Path Summary:

Slack 1.640
Data Arrival Time 2.527
Data Required Time 0.887
From u_ov5647_ctrl/resend_s0
To u_ov5647_ctrl/I2C/busy_sr_28_s1
Launch Clk clk_50:[R]
Latch Clk clk_50:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 1 IOB29[A] OSC_50M_ibuf/I
0.675 0.675 tINS RR 218 IOB29[A] OSC_50M_ibuf/O
1.035 0.360 tNET RR 1 R12C29[3][A] u_ov5647_ctrl/resend_s0/CLK
1.215 0.180 tC2Q RR 103 R12C29[3][A] u_ov5647_ctrl/resend_s0/Q
2.527 1.312 tNET RR 1 R21C32[1][A] u_ov5647_ctrl/I2C/busy_sr_28_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 1 IOB29[A] OSC_50M_ibuf/I
0.675 0.675 tINS RR 218 IOB29[A] OSC_50M_ibuf/O
1.076 0.400 tNET RR 1 R21C32[1][A] u_ov5647_ctrl/I2C/busy_sr_28_s1/CLK
0.887 -0.189 tHld 1 R21C32[1][A] u_ov5647_ctrl/I2C/busy_sr_28_s1

Path Statistics:

Clock Skew 0.040
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 65.234%; route: 0.360, 34.766%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.312, 87.932%; tC2Q: 0.180, 12.068%
Required Clock Path Delay cell: 0.675, 62.808%; route: 0.400, 37.192%

Path23

Path Summary:

Slack 1.644
Data Arrival Time 2.504
Data Required Time 0.860
From u_ov5647_ctrl/resend_s0
To u_ov5647_ctrl/I2C/busy_sr_30_s1
Launch Clk clk_50:[R]
Latch Clk clk_50:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 1 IOB29[A] OSC_50M_ibuf/I
0.675 0.675 tINS RR 218 IOB29[A] OSC_50M_ibuf/O
1.035 0.360 tNET RR 1 R12C29[3][A] u_ov5647_ctrl/resend_s0/CLK
1.215 0.180 tC2Q RR 103 R12C29[3][A] u_ov5647_ctrl/resend_s0/Q
2.504 1.288 tNET RR 1 R17C30[1][A] u_ov5647_ctrl/I2C/busy_sr_30_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 1 IOB29[A] OSC_50M_ibuf/I
0.675 0.675 tINS RR 218 IOB29[A] OSC_50M_ibuf/O
1.049 0.373 tNET RR 1 R17C30[1][A] u_ov5647_ctrl/I2C/busy_sr_30_s1/CLK
0.860 -0.189 tHld 1 R17C30[1][A] u_ov5647_ctrl/I2C/busy_sr_30_s1

Path Statistics:

Clock Skew 0.013
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 65.234%; route: 0.360, 34.766%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.288, 87.742%; tC2Q: 0.180, 12.258%
Required Clock Path Delay cell: 0.675, 64.418%; route: 0.373, 35.582%

Path24

Path Summary:

Slack 1.644
Data Arrival Time 2.504
Data Required Time 0.860
From u_ov5647_ctrl/resend_s0
To u_ov5647_ctrl/I2C/data_sr_40_s1
Launch Clk clk_50:[R]
Latch Clk clk_50:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 1 IOB29[A] OSC_50M_ibuf/I
0.675 0.675 tINS RR 218 IOB29[A] OSC_50M_ibuf/O
1.035 0.360 tNET RR 1 R12C29[3][A] u_ov5647_ctrl/resend_s0/CLK
1.215 0.180 tC2Q RR 103 R12C29[3][A] u_ov5647_ctrl/resend_s0/Q
2.504 1.288 tNET RR 1 R17C32[3][A] u_ov5647_ctrl/I2C/data_sr_40_s1/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 1 IOB29[A] OSC_50M_ibuf/I
0.675 0.675 tINS RR 218 IOB29[A] OSC_50M_ibuf/O
1.049 0.373 tNET RR 1 R17C32[3][A] u_ov5647_ctrl/I2C/data_sr_40_s1/CLK
0.860 -0.189 tHld 1 R17C32[3][A] u_ov5647_ctrl/I2C/data_sr_40_s1

Path Statistics:

Clock Skew 0.013
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 65.234%; route: 0.360, 34.766%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.288, 87.742%; tC2Q: 0.180, 12.258%
Required Clock Path Delay cell: 0.675, 64.418%; route: 0.373, 35.582%

Path25

Path Summary:

Slack 1.644
Data Arrival Time 2.504
Data Required Time 0.860
From u_ov5647_ctrl/resend_s0
To u_ov5647_ctrl/I2C/data_sr_34_s1
Launch Clk clk_50:[R]
Latch Clk clk_50:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 1 IOB29[A] OSC_50M_ibuf/I
0.675 0.675 tINS RR 218 IOB29[A] OSC_50M_ibuf/O
1.035 0.360 tNET RR 1 R12C29[3][A] u_ov5647_ctrl/resend_s0/CLK
1.215 0.180 tC2Q RR 103 R12C29[3][A] u_ov5647_ctrl/resend_s0/Q
2.504 1.288 tNET RR 1 R17C32[0][A] u_ov5647_ctrl/I2C/data_sr_34_s1/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 1 IOB29[A] OSC_50M_ibuf/I
0.675 0.675 tINS RR 218 IOB29[A] OSC_50M_ibuf/O
1.049 0.373 tNET RR 1 R17C32[0][A] u_ov5647_ctrl/I2C/data_sr_34_s1/CLK
0.860 -0.189 tHld 1 R17C32[0][A] u_ov5647_ctrl/I2C/data_sr_34_s1

Path Statistics:

Clock Skew 0.013
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 65.234%; route: 0.360, 34.766%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.288, 87.742%; tC2Q: 0.180, 12.258%
Required Clock Path Delay cell: 0.675, 64.418%; route: 0.373, 35.582%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack: 2.249
Actual Width: 3.249
Required Width: 1.000
Type: Low Pulse Width
Clock: pixel_clk
Objects: u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s

Late clock Path:

AT DELAY TYPE RF NODE
3.750 0.000 active clock edge time
3.750 0.000 pixel_clk
3.750 0.000 tCL FF u_pll/PLLA_inst/CLKOUT1
4.625 0.875 tNET FF u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/CLKA

Early clock Path:

AT DELAY TYPE RF NODE
7.500 0.000 active clock edge time
7.500 0.000 pixel_clk
7.500 0.000 tCL RR u_pll/PLLA_inst/CLKOUT1
7.874 0.374 tNET RR u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/CLKA

MPW2

MPW Summary:

Slack: 2.251
Actual Width: 3.251
Required Width: 1.000
Type: High Pulse Width
Clock: pixel_clk
Objects: u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR u_pll/PLLA_inst/CLKOUT1
0.878 0.878 tNET RR u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/CLKA

Early clock Path:

AT DELAY TYPE RF NODE
3.750 0.000 active clock edge time
3.750 0.000 pixel_clk
3.750 0.000 tCL FF u_pll/PLLA_inst/CLKOUT1
4.130 0.380 tNET FF u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/CLKA

MPW3

MPW Summary:

Slack: 2.253
Actual Width: 3.253
Required Width: 1.000
Type: Low Pulse Width
Clock: pixel_clk
Objects: u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s

Late clock Path:

AT DELAY TYPE RF NODE
3.750 0.000 active clock edge time
3.750 0.000 pixel_clk
3.750 0.000 tCL FF u_pll/PLLA_inst/CLKOUT1
4.615 0.865 tNET FF u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s/CLKB

Early clock Path:

AT DELAY TYPE RF NODE
7.500 0.000 active clock edge time
7.500 0.000 pixel_clk
7.500 0.000 tCL RR u_pll/PLLA_inst/CLKOUT1
7.869 0.369 tNET RR u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s/CLKB

MPW4

MPW Summary:

Slack: 2.253
Actual Width: 3.253
Required Width: 1.000
Type: Low Pulse Width
Clock: pixel_clk
Objects: u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s

Late clock Path:

AT DELAY TYPE RF NODE
3.750 0.000 active clock edge time
3.750 0.000 pixel_clk
3.750 0.000 tCL FF u_pll/PLLA_inst/CLKOUT1
4.615 0.865 tNET FF u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/CLKB

Early clock Path:

AT DELAY TYPE RF NODE
7.500 0.000 active clock edge time
7.500 0.000 pixel_clk
7.500 0.000 tCL RR u_pll/PLLA_inst/CLKOUT1
7.869 0.369 tNET RR u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/CLKB

MPW5

MPW Summary:

Slack: 2.256
Actual Width: 3.256
Required Width: 1.000
Type: High Pulse Width
Clock: pixel_clk
Objects: u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR u_pll/PLLA_inst/CLKOUT1
0.869 0.869 tNET RR u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/CLKB

Early clock Path:

AT DELAY TYPE RF NODE
3.750 0.000 active clock edge time
3.750 0.000 pixel_clk
3.750 0.000 tCL FF u_pll/PLLA_inst/CLKOUT1
4.125 0.375 tNET FF u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/CLKB

MPW6

MPW Summary:

Slack: 2.256
Actual Width: 3.256
Required Width: 1.000
Type: High Pulse Width
Clock: pixel_clk
Objects: u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR u_pll/PLLA_inst/CLKOUT1
0.869 0.869 tNET RR u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s/CLKB

Early clock Path:

AT DELAY TYPE RF NODE
3.750 0.000 active clock edge time
3.750 0.000 pixel_clk
3.750 0.000 tCL FF u_pll/PLLA_inst/CLKOUT1
4.125 0.375 tNET FF u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s/CLKB

MPW7

MPW Summary:

Slack: 2.994
Actual Width: 3.244
Required Width: 0.250
Type: Low Pulse Width
Clock: pixel_clk
Objects: u_bayer_rgb/devcnt_9_s1

Late clock Path:

AT DELAY TYPE RF NODE
3.750 0.000 active clock edge time
3.750 0.000 pixel_clk
3.750 0.000 tCL FF u_pll/PLLA_inst/CLKOUT1
4.655 0.905 tNET FF u_bayer_rgb/devcnt_9_s1/CLK

Early clock Path:

AT DELAY TYPE RF NODE
7.500 0.000 active clock edge time
7.500 0.000 pixel_clk
7.500 0.000 tCL RR u_pll/PLLA_inst/CLKOUT1
7.899 0.399 tNET RR u_bayer_rgb/devcnt_9_s1/CLK

MPW8

MPW Summary:

Slack: 2.994
Actual Width: 3.244
Required Width: 0.250
Type: Low Pulse Width
Clock: pixel_clk
Objects: u_bayer_rgb/devcnt_1_s1

Late clock Path:

AT DELAY TYPE RF NODE
3.750 0.000 active clock edge time
3.750 0.000 pixel_clk
3.750 0.000 tCL FF u_pll/PLLA_inst/CLKOUT1
4.655 0.905 tNET FF u_bayer_rgb/devcnt_1_s1/CLK

Early clock Path:

AT DELAY TYPE RF NODE
7.500 0.000 active clock edge time
7.500 0.000 pixel_clk
7.500 0.000 tCL RR u_pll/PLLA_inst/CLKOUT1
7.899 0.399 tNET RR u_bayer_rgb/devcnt_1_s1/CLK

MPW9

MPW Summary:

Slack: 2.994
Actual Width: 3.244
Required Width: 0.250
Type: Low Pulse Width
Clock: pixel_clk
Objects: u_bayer_rgb/video_format_detect_inst/hcnt_0_s3

Late clock Path:

AT DELAY TYPE RF NODE
3.750 0.000 active clock edge time
3.750 0.000 pixel_clk
3.750 0.000 tCL FF u_pll/PLLA_inst/CLKOUT1
4.655 0.905 tNET FF u_bayer_rgb/video_format_detect_inst/hcnt_0_s3/CLK

Early clock Path:

AT DELAY TYPE RF NODE
7.500 0.000 active clock edge time
7.500 0.000 pixel_clk
7.500 0.000 tCL RR u_pll/PLLA_inst/CLKOUT1
7.899 0.399 tNET RR u_bayer_rgb/video_format_detect_inst/hcnt_0_s3/CLK

MPW10

MPW Summary:

Slack: 2.994
Actual Width: 3.244
Required Width: 0.250
Type: Low Pulse Width
Clock: pixel_clk
Objects: u_bayer_rgb/devcnt_0_s1

Late clock Path:

AT DELAY TYPE RF NODE
3.750 0.000 active clock edge time
3.750 0.000 pixel_clk
3.750 0.000 tCL FF u_pll/PLLA_inst/CLKOUT1
4.655 0.905 tNET FF u_bayer_rgb/devcnt_0_s1/CLK

Early clock Path:

AT DELAY TYPE RF NODE
7.500 0.000 active clock edge time
7.500 0.000 pixel_clk
7.500 0.000 tCL RR u_pll/PLLA_inst/CLKOUT1
7.899 0.399 tNET RR u_bayer_rgb/devcnt_0_s1/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT NET NAME WORST SLACK MAX DELAY
681 byte_clk 7.116 0.913
244 lvds_pclk 3.107 0.908
218 OSC_50M_d 13.319 0.912
103 resend 15.277 2.547
85 busy_sr[40] 14.002 0.954
82 n268_3 13.319 3.241
56 address[3] 15.475 1.187
53 address[2] 15.758 1.822
53 address[4] 15.561 1.504
50 address[1] 15.867 0.979

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC ROUTE CONGESTIONS
R17C36 68.06%
R25C23 58.33%
R24C23 55.56%
R22C27 50.00%
R12C36 48.61%
R24C22 47.22%
R26C23 45.83%
R23C23 45.83%
R13C35 44.44%
R12C35 44.44%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type State Detail Command
TC_CLOCK Actived create_clock -name clk_50 -period 20 -waveform {0 10} [get_ports {OSC_50M}]
TC_CLOCK Actived create_clock -name byte_clk -period 15 -waveform {0 7.5} [get_nets {byte_clk}]
TC_GENERATED_CLOCK Actived create_generated_clock -name pixel_clk -source [get_nets {byte_clk}] -master_clock byte_clk -divide_by 1 -multiply_by 2 [get_nets {lvds_pclk}]
TC_CLOCK_GROUP Actived set_clock_groups -exclusive -group [get_clocks {pixel_clk}] -group [get_clocks {byte_clk}]
TC_CLOCK_GROUP Actived set_clock_groups -exclusive -group [get_clocks {pixel_clk}] -group [get_clocks {clk_50}]
TC_CLOCK_GROUP Actived set_clock_groups -exclusive -group [get_clocks {clk_50}] -group [get_clocks {byte_clk}]
TC_REPORT_TIMING Actived report_timing -setup -from_clock [get_clocks {pixel_clk}] -max_paths 20 -max_common_paths 1
TC_REPORT_TIMING Actived report_timing -setup -from_clock [get_clocks {byte_clk}] -max_paths 20 -max_common_paths 1
TC_REPORT_TIMING Actived report_timing -hold -from_clock [get_clocks {pixel_clk}] -max_paths 20 -max_common_paths 1
TC_REPORT_TIMING Actived report_timing -hold -from_clock [get_clocks {byte_clk}] -max_paths 20 -max_common_paths 1