Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Programs\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\MIPI_BYTE_TO_PIXEL\data\byte_to_pixel.v
D:\Programs\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\MIPI_BYTE_TO_PIXEL\data\byte_to_pixel_wrap.v
GowinSynthesis Constraints File ---
Tool Version V1.9.9.01 (64-bit)
Part Number GW5A-LV25MG121NC1/I0
Device GW5A-25
Device Version A
Created Time Wed Mar 6 16:54:18 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module Byte_to_Pixel_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.312s, Elapsed time = 0h 0m 0.304s, Peak memory usage = 117.270MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 117.270MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.019s, Peak memory usage = 117.270MB
    Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 117.270MB
    Optimizing Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.029s, Peak memory usage = 117.270MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 117.270MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 117.270MB
    Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 117.270MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 117.270MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.015s, Peak memory usage = 117.270MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 117.270MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 117.270MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.64s, Elapsed time = 0h 0m 0.647s, Peak memory usage = 141.207MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.053s, Peak memory usage = 141.207MB
Generate output files:
    CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.085s, Peak memory usage = 141.207MB
Total Time and Memory Usage CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 141.207MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 90
I/O Buf 90
    IBUF 63
    OBUF 27
Register 423
    DFFSE 2
    DFFRE 84
    DFFPE 9
    DFFCE 328
LUT 332
    LUT2 36
    LUT3 128
    LUT4 168
ALU 20
    ALU 20
INV 6
    INV 6
BSRAM 2
    SDPB 2

Resource Utilization Summary

Resource Usage Utilization
Logic 358(338 LUT, 20 ALU) / 23040 2%
Register 423 / 23280 2%
  --Register as Latch 0 / 23280 0%
  --Register as FF 423 / 23280 2%
BSRAM 2 / 56 4%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
I_BYTE_CLK Base 10.000 100.0 0.000 5.000 I_BYTE_CLK_ibuf/I
I_PIXEL_CLK Base 10.000 100.0 0.000 5.000 I_PIXEL_CLK_ibuf/I

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 I_BYTE_CLK 100.000(MHz) 190.840(MHz) 7 TOP
2 I_PIXEL_CLK 100.000(MHz) 225.925(MHz) 5 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 4.760
Data Arrival Time 6.234
Data Required Time 10.994
From u_b2p_inst/u_mid_fifo/rRPtrWsync_3_s0
To u_b2p_inst/u_mid_fifo/rFull_s0
Launch Clk I_BYTE_CLK[R]
Latch Clk I_BYTE_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_BYTE_CLK
0.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
0.683 0.683 tINS RR 335 I_BYTE_CLK_ibuf/O
1.058 0.375 tNET RR 1 u_b2p_inst/u_mid_fifo/rRPtrWsync_3_s0/CLK
1.440 0.382 tC2Q RR 1 u_b2p_inst/u_mid_fifo/rRPtrWsync_3_s0/Q
1.815 0.375 tNET RR 1 u_b2p_inst/u_mid_fifo/wRPtrBinX_3_s0/I0
2.341 0.526 tINS RR 5 u_b2p_inst/u_mid_fifo/wRPtrBinX_3_s0/F
2.716 0.375 tNET RR 1 u_b2p_inst/u_mid_fifo/wRPtrBinX_2_s0/I1
3.233 0.516 tINS RR 1 u_b2p_inst/u_mid_fifo/wRPtrBinX_2_s0/F
3.608 0.375 tNET RR 2 u_b2p_inst/u_mid_fifo/n401_s0/I1
4.170 0.562 tINS RF 1 u_b2p_inst/u_mid_fifo/n401_s0/COUT
4.170 0.000 tNET FF 2 u_b2p_inst/u_mid_fifo/n402_s0/CIN
4.220 0.050 tINS FR 1 u_b2p_inst/u_mid_fifo/n402_s0/COUT
4.220 0.000 tNET RR 2 u_b2p_inst/u_mid_fifo/n403_s0/CIN
4.270 0.050 tINS RR 1 u_b2p_inst/u_mid_fifo/n403_s0/COUT
4.270 0.000 tNET RR 2 u_b2p_inst/u_mid_fifo/n404_s0/CIN
4.320 0.050 tINS RR 1 u_b2p_inst/u_mid_fifo/n404_s0/COUT
4.695 0.375 tNET RR 1 u_b2p_inst/u_mid_fifo/n418_s8/I0
5.221 0.526 tINS RR 1 u_b2p_inst/u_mid_fifo/n418_s8/F
5.596 0.375 tNET RR 1 u_b2p_inst/u_mid_fifo/n418_s0/I3
5.859 0.262 tINS RR 1 u_b2p_inst/u_mid_fifo/n418_s0/F
6.234 0.375 tNET RR 1 u_b2p_inst/u_mid_fifo/rFull_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_BYTE_CLK
10.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
10.682 0.683 tINS RR 335 I_BYTE_CLK_ibuf/O
11.057 0.375 tNET RR 1 u_b2p_inst/u_mid_fifo/rFull_s0/CLK
10.994 -0.064 tSu 1 u_b2p_inst/u_mid_fifo/rFull_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.683, 64.539%; route: 0.375, 35.461%
Arrival Data Path Delay: cell: 2.544, 49.142%; route: 2.250, 43.468%; tC2Q: 0.382, 7.390%
Required Clock Path Delay: cell: 0.683, 64.539%; route: 0.375, 35.461%

Path 2

Path Summary:
Slack 5.356
Data Arrival Time 5.390
Data Required Time 10.746
From u_b2p_inst/u_dsi_sync_detec/rVSyncCnt_0_s2
To u_b2p_inst/u_dsi_sync_detec/rVSyncCnt_9_s0
Launch Clk I_BYTE_CLK[R]
Latch Clk I_BYTE_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_BYTE_CLK
0.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
0.683 0.683 tINS RR 335 I_BYTE_CLK_ibuf/O
1.058 0.375 tNET RR 1 u_b2p_inst/u_dsi_sync_detec/rVSyncCnt_0_s2/CLK
1.440 0.382 tC2Q RR 5 u_b2p_inst/u_dsi_sync_detec/rVSyncCnt_0_s2/Q
1.815 0.375 tNET RR 1 u_b2p_inst/u_dsi_sync_detec/n62_s3/I0
2.341 0.526 tINS RR 4 u_b2p_inst/u_dsi_sync_detec/n62_s3/F
2.716 0.375 tNET RR 1 u_b2p_inst/u_dsi_sync_detec/n57_s5/I1
3.233 0.516 tINS RR 4 u_b2p_inst/u_dsi_sync_detec/n57_s5/F
3.608 0.375 tNET RR 1 u_b2p_inst/u_dsi_sync_detec/n108_s8/I1
4.124 0.516 tINS RR 3 u_b2p_inst/u_dsi_sync_detec/n108_s8/F
4.499 0.375 tNET RR 1 u_b2p_inst/u_dsi_sync_detec/rVSyncCnt_8_s3/I1
5.015 0.516 tINS RR 9 u_b2p_inst/u_dsi_sync_detec/rVSyncCnt_8_s3/F
5.390 0.375 tNET RR 1 u_b2p_inst/u_dsi_sync_detec/rVSyncCnt_9_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_BYTE_CLK
10.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
10.682 0.683 tINS RR 335 I_BYTE_CLK_ibuf/O
11.057 0.375 tNET RR 1 u_b2p_inst/u_dsi_sync_detec/rVSyncCnt_9_s0/CLK
10.746 -0.311 tSu 1 u_b2p_inst/u_dsi_sync_detec/rVSyncCnt_9_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.683, 64.539%; route: 0.375, 35.461%
Arrival Data Path Delay: cell: 2.075, 47.893%; route: 1.875, 43.278%; tC2Q: 0.382, 8.829%
Required Clock Path Delay: cell: 0.683, 64.539%; route: 0.375, 35.461%

Path 3

Path Summary:
Slack 5.356
Data Arrival Time 5.390
Data Required Time 10.746
From u_b2p_inst/u_dsi_sync_detec/rVSyncCnt_0_s2
To u_b2p_inst/u_dsi_sync_detec/rVSyncCnt_1_s0
Launch Clk I_BYTE_CLK[R]
Latch Clk I_BYTE_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_BYTE_CLK
0.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
0.683 0.683 tINS RR 335 I_BYTE_CLK_ibuf/O
1.058 0.375 tNET RR 1 u_b2p_inst/u_dsi_sync_detec/rVSyncCnt_0_s2/CLK
1.440 0.382 tC2Q RR 5 u_b2p_inst/u_dsi_sync_detec/rVSyncCnt_0_s2/Q
1.815 0.375 tNET RR 1 u_b2p_inst/u_dsi_sync_detec/n62_s3/I0
2.341 0.526 tINS RR 4 u_b2p_inst/u_dsi_sync_detec/n62_s3/F
2.716 0.375 tNET RR 1 u_b2p_inst/u_dsi_sync_detec/n57_s5/I1
3.233 0.516 tINS RR 4 u_b2p_inst/u_dsi_sync_detec/n57_s5/F
3.608 0.375 tNET RR 1 u_b2p_inst/u_dsi_sync_detec/n108_s8/I1
4.124 0.516 tINS RR 3 u_b2p_inst/u_dsi_sync_detec/n108_s8/F
4.499 0.375 tNET RR 1 u_b2p_inst/u_dsi_sync_detec/rVSyncCnt_8_s3/I1
5.015 0.516 tINS RR 9 u_b2p_inst/u_dsi_sync_detec/rVSyncCnt_8_s3/F
5.390 0.375 tNET RR 1 u_b2p_inst/u_dsi_sync_detec/rVSyncCnt_1_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_BYTE_CLK
10.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
10.682 0.683 tINS RR 335 I_BYTE_CLK_ibuf/O
11.057 0.375 tNET RR 1 u_b2p_inst/u_dsi_sync_detec/rVSyncCnt_1_s0/CLK
10.746 -0.311 tSu 1 u_b2p_inst/u_dsi_sync_detec/rVSyncCnt_1_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.683, 64.539%; route: 0.375, 35.461%
Arrival Data Path Delay: cell: 2.075, 47.893%; route: 1.875, 43.278%; tC2Q: 0.382, 8.829%
Required Clock Path Delay: cell: 0.683, 64.539%; route: 0.375, 35.461%

Path 4

Path Summary:
Slack 5.356
Data Arrival Time 5.390
Data Required Time 10.746
From u_b2p_inst/u_dsi_sync_detec/rVSyncCnt_0_s2
To u_b2p_inst/u_dsi_sync_detec/rVSyncCnt_2_s0
Launch Clk I_BYTE_CLK[R]
Latch Clk I_BYTE_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_BYTE_CLK
0.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
0.683 0.683 tINS RR 335 I_BYTE_CLK_ibuf/O
1.058 0.375 tNET RR 1 u_b2p_inst/u_dsi_sync_detec/rVSyncCnt_0_s2/CLK
1.440 0.382 tC2Q RR 5 u_b2p_inst/u_dsi_sync_detec/rVSyncCnt_0_s2/Q
1.815 0.375 tNET RR 1 u_b2p_inst/u_dsi_sync_detec/n62_s3/I0
2.341 0.526 tINS RR 4 u_b2p_inst/u_dsi_sync_detec/n62_s3/F
2.716 0.375 tNET RR 1 u_b2p_inst/u_dsi_sync_detec/n57_s5/I1
3.233 0.516 tINS RR 4 u_b2p_inst/u_dsi_sync_detec/n57_s5/F
3.608 0.375 tNET RR 1 u_b2p_inst/u_dsi_sync_detec/n108_s8/I1
4.124 0.516 tINS RR 3 u_b2p_inst/u_dsi_sync_detec/n108_s8/F
4.499 0.375 tNET RR 1 u_b2p_inst/u_dsi_sync_detec/rVSyncCnt_8_s3/I1
5.015 0.516 tINS RR 9 u_b2p_inst/u_dsi_sync_detec/rVSyncCnt_8_s3/F
5.390 0.375 tNET RR 1 u_b2p_inst/u_dsi_sync_detec/rVSyncCnt_2_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_BYTE_CLK
10.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
10.682 0.683 tINS RR 335 I_BYTE_CLK_ibuf/O
11.057 0.375 tNET RR 1 u_b2p_inst/u_dsi_sync_detec/rVSyncCnt_2_s0/CLK
10.746 -0.311 tSu 1 u_b2p_inst/u_dsi_sync_detec/rVSyncCnt_2_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.683, 64.539%; route: 0.375, 35.461%
Arrival Data Path Delay: cell: 2.075, 47.893%; route: 1.875, 43.278%; tC2Q: 0.382, 8.829%
Required Clock Path Delay: cell: 0.683, 64.539%; route: 0.375, 35.461%

Path 5

Path Summary:
Slack 5.356
Data Arrival Time 5.390
Data Required Time 10.746
From u_b2p_inst/u_dsi_sync_detec/rVSyncCnt_0_s2
To u_b2p_inst/u_dsi_sync_detec/rVSyncCnt_3_s0
Launch Clk I_BYTE_CLK[R]
Latch Clk I_BYTE_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_BYTE_CLK
0.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
0.683 0.683 tINS RR 335 I_BYTE_CLK_ibuf/O
1.058 0.375 tNET RR 1 u_b2p_inst/u_dsi_sync_detec/rVSyncCnt_0_s2/CLK
1.440 0.382 tC2Q RR 5 u_b2p_inst/u_dsi_sync_detec/rVSyncCnt_0_s2/Q
1.815 0.375 tNET RR 1 u_b2p_inst/u_dsi_sync_detec/n62_s3/I0
2.341 0.526 tINS RR 4 u_b2p_inst/u_dsi_sync_detec/n62_s3/F
2.716 0.375 tNET RR 1 u_b2p_inst/u_dsi_sync_detec/n57_s5/I1
3.233 0.516 tINS RR 4 u_b2p_inst/u_dsi_sync_detec/n57_s5/F
3.608 0.375 tNET RR 1 u_b2p_inst/u_dsi_sync_detec/n108_s8/I1
4.124 0.516 tINS RR 3 u_b2p_inst/u_dsi_sync_detec/n108_s8/F
4.499 0.375 tNET RR 1 u_b2p_inst/u_dsi_sync_detec/rVSyncCnt_8_s3/I1
5.015 0.516 tINS RR 9 u_b2p_inst/u_dsi_sync_detec/rVSyncCnt_8_s3/F
5.390 0.375 tNET RR 1 u_b2p_inst/u_dsi_sync_detec/rVSyncCnt_3_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_BYTE_CLK
10.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
10.682 0.683 tINS RR 335 I_BYTE_CLK_ibuf/O
11.057 0.375 tNET RR 1 u_b2p_inst/u_dsi_sync_detec/rVSyncCnt_3_s0/CLK
10.746 -0.311 tSu 1 u_b2p_inst/u_dsi_sync_detec/rVSyncCnt_3_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.683, 64.539%; route: 0.375, 35.461%
Arrival Data Path Delay: cell: 2.075, 47.893%; route: 1.875, 43.278%; tC2Q: 0.382, 8.829%
Required Clock Path Delay: cell: 0.683, 64.539%; route: 0.375, 35.461%