Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | D:\Programs\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\MIPI_DSI_CSI2_RX\data\dsi_csi2_rx_wrap.v D:\Programs\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\MIPI_DSI_CSI2_RX\data\dsi_csi2_rx.v |
GowinSynthesis Constraints File | --- |
Tool Version | V1.9.9.01 (64-bit) |
Part Number | GW5AST-LV138FPG676AES |
Device | GW5AST-138 |
Device Version | B |
Created Time | Wed Mar 6 18:42:55 2024 |
Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | Dsi_Rx_Top |
Synthesis Process | Running parser: CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.177s, Peak memory usage = 109.477MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 109.477MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 109.477MB Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 109.477MB Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 109.477MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 109.477MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 109.477MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 109.477MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 109.477MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 109.477MB Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 109.477MB Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 109.477MB Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 134.211MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.027s, Peak memory usage = 134.211MB Generate output files: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.06s, Peak memory usage = 134.211MB |
Total Time and Memory Usage | CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 134.211MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 113 |
I/O Buf | 113 |
    IBUF | 41 |
    OBUF | 72 |
Register | 227 |
    DFFSE | 32 |
    DFFRE | 88 |
    DFFCE | 107 |
LUT | 277 |
    LUT2 | 13 |
    LUT3 | 137 |
    LUT4 | 127 |
ALU | 9 |
    ALU | 9 |
INV | 2 |
    INV | 2 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 288(279 LUT, 9 ALU) / 138240 | <1% |
Register | 227 / 139140 | <1% |
  --Register as Latch | 0 / 139140 | 0% |
  --Register as FF | 227 / 139140 | <1% |
BSRAM | 0 / 340 | 0% |
Timing
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|
I_BYTE_CLK | Base | 10.000 | 100.0 | 0.000 | 5.000 | I_BYTE_CLK_ibuf/I |
Max Frequency Summary:
No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | I_BYTE_CLK | 100.000(MHz) | 165.255(MHz) | 6 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | 3.949 |
Data Arrival Time | 6.835 |
Data Required Time | 10.784 |
From | u_dsi_csi2/rData_5_s0 |
To | u_dsi_csi2/rHeader_0_s0 |
Launch Clk | I_BYTE_CLK[R] |
Latch Clk | I_BYTE_CLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | I_BYTE_CLK | |||
0.000 | 0.000 | tCL | RR | 1 | I_BYTE_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 227 | I_BYTE_CLK_ibuf/O |
1.095 | 0.413 | tNET | RR | 1 | u_dsi_csi2/rData_5_s0/CLK |
1.477 | 0.382 | tC2Q | RR | 7 | u_dsi_csi2/rData_5_s0/Q |
1.890 | 0.413 | tNET | RR | 1 | u_dsi_csi2/wHeader_21_s1/I0 |
2.469 | 0.579 | tINS | RR | 2 | u_dsi_csi2/wHeader_21_s1/F |
2.881 | 0.413 | tNET | RR | 1 | u_dsi_csi2/wHeader_5_s0/I0 |
3.460 | 0.579 | tINS | RR | 5 | u_dsi_csi2/wHeader_5_s0/F |
3.872 | 0.413 | tNET | RR | 1 | u_dsi_csi2/n1188_s7/I0 |
4.451 | 0.579 | tINS | RR | 1 | u_dsi_csi2/n1188_s7/F |
4.864 | 0.413 | tNET | RR | 1 | u_dsi_csi2/n1188_s3/I0 |
5.443 | 0.579 | tINS | RR | 2 | u_dsi_csi2/n1188_s3/F |
5.855 | 0.413 | tNET | RR | 1 | u_dsi_csi2/n1188_s1/I1 |
6.423 | 0.567 | tINS | RR | 32 | u_dsi_csi2/n1188_s1/F |
6.835 | 0.413 | tNET | RR | 1 | u_dsi_csi2/rHeader_0_s0/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | I_BYTE_CLK | |||
10.000 | 0.000 | tCL | RR | 1 | I_BYTE_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 227 | I_BYTE_CLK_ibuf/O |
11.095 | 0.413 | tNET | RR | 1 | u_dsi_csi2/rHeader_0_s0/CLK |
10.784 | -0.311 | tSu | 1 | u_dsi_csi2/rHeader_0_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 6 |
Arrival Clock Path Delay: | cell: 0.683, 62.329%; route: 0.413, 37.671% |
Arrival Data Path Delay: | cell: 2.883, 50.218%; route: 2.475, 43.118%; tC2Q: 0.382, 6.664% |
Required Clock Path Delay: | cell: 0.683, 62.329%; route: 0.413, 37.671% |
Path 2
Path Summary:Slack | 3.949 |
Data Arrival Time | 6.835 |
Data Required Time | 10.784 |
From | u_dsi_csi2/rData_5_s0 |
To | u_dsi_csi2/rHeader_1_s0 |
Launch Clk | I_BYTE_CLK[R] |
Latch Clk | I_BYTE_CLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | I_BYTE_CLK | |||
0.000 | 0.000 | tCL | RR | 1 | I_BYTE_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 227 | I_BYTE_CLK_ibuf/O |
1.095 | 0.413 | tNET | RR | 1 | u_dsi_csi2/rData_5_s0/CLK |
1.477 | 0.382 | tC2Q | RR | 7 | u_dsi_csi2/rData_5_s0/Q |
1.890 | 0.413 | tNET | RR | 1 | u_dsi_csi2/wHeader_21_s1/I0 |
2.469 | 0.579 | tINS | RR | 2 | u_dsi_csi2/wHeader_21_s1/F |
2.881 | 0.413 | tNET | RR | 1 | u_dsi_csi2/wHeader_5_s0/I0 |
3.460 | 0.579 | tINS | RR | 5 | u_dsi_csi2/wHeader_5_s0/F |
3.872 | 0.413 | tNET | RR | 1 | u_dsi_csi2/n1188_s7/I0 |
4.451 | 0.579 | tINS | RR | 1 | u_dsi_csi2/n1188_s7/F |
4.864 | 0.413 | tNET | RR | 1 | u_dsi_csi2/n1188_s3/I0 |
5.443 | 0.579 | tINS | RR | 2 | u_dsi_csi2/n1188_s3/F |
5.855 | 0.413 | tNET | RR | 1 | u_dsi_csi2/n1188_s1/I1 |
6.423 | 0.567 | tINS | RR | 32 | u_dsi_csi2/n1188_s1/F |
6.835 | 0.413 | tNET | RR | 1 | u_dsi_csi2/rHeader_1_s0/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | I_BYTE_CLK | |||
10.000 | 0.000 | tCL | RR | 1 | I_BYTE_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 227 | I_BYTE_CLK_ibuf/O |
11.095 | 0.413 | tNET | RR | 1 | u_dsi_csi2/rHeader_1_s0/CLK |
10.784 | -0.311 | tSu | 1 | u_dsi_csi2/rHeader_1_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 6 |
Arrival Clock Path Delay: | cell: 0.683, 62.329%; route: 0.413, 37.671% |
Arrival Data Path Delay: | cell: 2.883, 50.218%; route: 2.475, 43.118%; tC2Q: 0.382, 6.664% |
Required Clock Path Delay: | cell: 0.683, 62.329%; route: 0.413, 37.671% |
Path 3
Path Summary:Slack | 3.949 |
Data Arrival Time | 6.835 |
Data Required Time | 10.784 |
From | u_dsi_csi2/rData_5_s0 |
To | u_dsi_csi2/rHeader_2_s0 |
Launch Clk | I_BYTE_CLK[R] |
Latch Clk | I_BYTE_CLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | I_BYTE_CLK | |||
0.000 | 0.000 | tCL | RR | 1 | I_BYTE_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 227 | I_BYTE_CLK_ibuf/O |
1.095 | 0.413 | tNET | RR | 1 | u_dsi_csi2/rData_5_s0/CLK |
1.477 | 0.382 | tC2Q | RR | 7 | u_dsi_csi2/rData_5_s0/Q |
1.890 | 0.413 | tNET | RR | 1 | u_dsi_csi2/wHeader_21_s1/I0 |
2.469 | 0.579 | tINS | RR | 2 | u_dsi_csi2/wHeader_21_s1/F |
2.881 | 0.413 | tNET | RR | 1 | u_dsi_csi2/wHeader_5_s0/I0 |
3.460 | 0.579 | tINS | RR | 5 | u_dsi_csi2/wHeader_5_s0/F |
3.872 | 0.413 | tNET | RR | 1 | u_dsi_csi2/n1188_s7/I0 |
4.451 | 0.579 | tINS | RR | 1 | u_dsi_csi2/n1188_s7/F |
4.864 | 0.413 | tNET | RR | 1 | u_dsi_csi2/n1188_s3/I0 |
5.443 | 0.579 | tINS | RR | 2 | u_dsi_csi2/n1188_s3/F |
5.855 | 0.413 | tNET | RR | 1 | u_dsi_csi2/n1188_s1/I1 |
6.423 | 0.567 | tINS | RR | 32 | u_dsi_csi2/n1188_s1/F |
6.835 | 0.413 | tNET | RR | 1 | u_dsi_csi2/rHeader_2_s0/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | I_BYTE_CLK | |||
10.000 | 0.000 | tCL | RR | 1 | I_BYTE_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 227 | I_BYTE_CLK_ibuf/O |
11.095 | 0.413 | tNET | RR | 1 | u_dsi_csi2/rHeader_2_s0/CLK |
10.784 | -0.311 | tSu | 1 | u_dsi_csi2/rHeader_2_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 6 |
Arrival Clock Path Delay: | cell: 0.683, 62.329%; route: 0.413, 37.671% |
Arrival Data Path Delay: | cell: 2.883, 50.218%; route: 2.475, 43.118%; tC2Q: 0.382, 6.664% |
Required Clock Path Delay: | cell: 0.683, 62.329%; route: 0.413, 37.671% |
Path 4
Path Summary:Slack | 3.949 |
Data Arrival Time | 6.835 |
Data Required Time | 10.784 |
From | u_dsi_csi2/rData_5_s0 |
To | u_dsi_csi2/rHeader_3_s0 |
Launch Clk | I_BYTE_CLK[R] |
Latch Clk | I_BYTE_CLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | I_BYTE_CLK | |||
0.000 | 0.000 | tCL | RR | 1 | I_BYTE_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 227 | I_BYTE_CLK_ibuf/O |
1.095 | 0.413 | tNET | RR | 1 | u_dsi_csi2/rData_5_s0/CLK |
1.477 | 0.382 | tC2Q | RR | 7 | u_dsi_csi2/rData_5_s0/Q |
1.890 | 0.413 | tNET | RR | 1 | u_dsi_csi2/wHeader_21_s1/I0 |
2.469 | 0.579 | tINS | RR | 2 | u_dsi_csi2/wHeader_21_s1/F |
2.881 | 0.413 | tNET | RR | 1 | u_dsi_csi2/wHeader_5_s0/I0 |
3.460 | 0.579 | tINS | RR | 5 | u_dsi_csi2/wHeader_5_s0/F |
3.872 | 0.413 | tNET | RR | 1 | u_dsi_csi2/n1188_s7/I0 |
4.451 | 0.579 | tINS | RR | 1 | u_dsi_csi2/n1188_s7/F |
4.864 | 0.413 | tNET | RR | 1 | u_dsi_csi2/n1188_s3/I0 |
5.443 | 0.579 | tINS | RR | 2 | u_dsi_csi2/n1188_s3/F |
5.855 | 0.413 | tNET | RR | 1 | u_dsi_csi2/n1188_s1/I1 |
6.423 | 0.567 | tINS | RR | 32 | u_dsi_csi2/n1188_s1/F |
6.835 | 0.413 | tNET | RR | 1 | u_dsi_csi2/rHeader_3_s0/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | I_BYTE_CLK | |||
10.000 | 0.000 | tCL | RR | 1 | I_BYTE_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 227 | I_BYTE_CLK_ibuf/O |
11.095 | 0.413 | tNET | RR | 1 | u_dsi_csi2/rHeader_3_s0/CLK |
10.784 | -0.311 | tSu | 1 | u_dsi_csi2/rHeader_3_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 6 |
Arrival Clock Path Delay: | cell: 0.683, 62.329%; route: 0.413, 37.671% |
Arrival Data Path Delay: | cell: 2.883, 50.218%; route: 2.475, 43.118%; tC2Q: 0.382, 6.664% |
Required Clock Path Delay: | cell: 0.683, 62.329%; route: 0.413, 37.671% |
Path 5
Path Summary:Slack | 3.949 |
Data Arrival Time | 6.835 |
Data Required Time | 10.784 |
From | u_dsi_csi2/rData_5_s0 |
To | u_dsi_csi2/rHeader_4_s0 |
Launch Clk | I_BYTE_CLK[R] |
Latch Clk | I_BYTE_CLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | I_BYTE_CLK | |||
0.000 | 0.000 | tCL | RR | 1 | I_BYTE_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 227 | I_BYTE_CLK_ibuf/O |
1.095 | 0.413 | tNET | RR | 1 | u_dsi_csi2/rData_5_s0/CLK |
1.477 | 0.382 | tC2Q | RR | 7 | u_dsi_csi2/rData_5_s0/Q |
1.890 | 0.413 | tNET | RR | 1 | u_dsi_csi2/wHeader_21_s1/I0 |
2.469 | 0.579 | tINS | RR | 2 | u_dsi_csi2/wHeader_21_s1/F |
2.881 | 0.413 | tNET | RR | 1 | u_dsi_csi2/wHeader_5_s0/I0 |
3.460 | 0.579 | tINS | RR | 5 | u_dsi_csi2/wHeader_5_s0/F |
3.872 | 0.413 | tNET | RR | 1 | u_dsi_csi2/n1188_s7/I0 |
4.451 | 0.579 | tINS | RR | 1 | u_dsi_csi2/n1188_s7/F |
4.864 | 0.413 | tNET | RR | 1 | u_dsi_csi2/n1188_s3/I0 |
5.443 | 0.579 | tINS | RR | 2 | u_dsi_csi2/n1188_s3/F |
5.855 | 0.413 | tNET | RR | 1 | u_dsi_csi2/n1188_s1/I1 |
6.423 | 0.567 | tINS | RR | 32 | u_dsi_csi2/n1188_s1/F |
6.835 | 0.413 | tNET | RR | 1 | u_dsi_csi2/rHeader_4_s0/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | I_BYTE_CLK | |||
10.000 | 0.000 | tCL | RR | 1 | I_BYTE_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 227 | I_BYTE_CLK_ibuf/O |
11.095 | 0.413 | tNET | RR | 1 | u_dsi_csi2/rHeader_4_s0/CLK |
10.784 | -0.311 | tSu | 1 | u_dsi_csi2/rHeader_4_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 6 |
Arrival Clock Path Delay: | cell: 0.683, 62.329%; route: 0.413, 37.671% |
Arrival Data Path Delay: | cell: 2.883, 50.218%; route: 2.475, 43.118%; tC2Q: 0.382, 6.664% |
Required Clock Path Delay: | cell: 0.683, 62.329%; route: 0.413, 37.671% |