Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\MIPI_DSI_CSI2_RX\data\dsi_csi2_rx_wrap.v
C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\MIPI_DSI_CSI2_RX\data\dsi_csi2_rx.v
GowinSynthesis Constraints File ---
Tool Version V1.9.9.02
Part Number GW5A-LV25UG324ES
Device GW5A-25
Device Version A
Created Time Tue Mar 19 16:48:05 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module CSI2_RX_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.178s, Peak memory usage = 106.227MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 106.227MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 106.227MB
    Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 106.227MB
    Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 106.227MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 106.227MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 106.227MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 106.227MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 106.227MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 106.227MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 106.227MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 106.227MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.875s, Elapsed time = 0h 0m 0.907s, Peak memory usage = 130.559MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.03s, Peak memory usage = 130.559MB
Generate output files:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.019s, Peak memory usage = 130.559MB
Total Time and Memory Usage CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 130.559MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 79
I/O Buf 79
    IBUF 25
    OBUF 54
Register 175
    DFFSE 16
    DFFRE 72
    DFFCE 87
LUT 187
    LUT2 18
    LUT3 64
    LUT4 105
ALU 9
    ALU 9
INV 2
    INV 2

Resource Utilization Summary

Resource Usage Utilization
Logic 198(189 LUT, 9 ALU) / 23040 <1%
Register 175 / 23685 <1%
  --Register as Latch 0 / 23685 0%
  --Register as FF 175 / 23685 <1%
BSRAM 0 / 56 0%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
I_BYTE_CLK Base 10.000 100.0 0.000 5.000 I_BYTE_CLK_ibuf/I

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 I_BYTE_CLK 100.000(MHz) 214.420(MHz) 5 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 5.336
Data Arrival Time 5.410
Data Required Time 10.746
From u_dsi_csi2/rDataReg_19_s0
To u_dsi_csi2/rHeader_0_s0
Launch Clk I_BYTE_CLK[R]
Latch Clk I_BYTE_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_BYTE_CLK
0.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
0.683 0.683 tINS RR 175 I_BYTE_CLK_ibuf/O
1.058 0.375 tNET RR 1 u_dsi_csi2/rDataReg_19_s0/CLK
1.440 0.382 tC2Q RR 6 u_dsi_csi2/rDataReg_19_s0/Q
1.815 0.375 tNET RR 1 u_dsi_csi2/wHeader_3_s1/I0
2.341 0.526 tINS RR 2 u_dsi_csi2/wHeader_3_s1/F
2.716 0.375 tNET RR 1 u_dsi_csi2/n967_s4/I0
3.242 0.526 tINS RR 1 u_dsi_csi2/n967_s4/F
3.617 0.375 tNET RR 1 u_dsi_csi2/n967_s2/I1
4.134 0.516 tINS RR 3 u_dsi_csi2/n967_s2/F
4.509 0.375 tNET RR 1 u_dsi_csi2/n967_s1/I0
5.035 0.526 tINS RR 32 u_dsi_csi2/n967_s1/F
5.410 0.375 tNET RR 1 u_dsi_csi2/rHeader_0_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_BYTE_CLK
10.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
10.682 0.683 tINS RR 175 I_BYTE_CLK_ibuf/O
11.057 0.375 tNET RR 1 u_dsi_csi2/rHeader_0_s0/CLK
10.746 -0.311 tSu 1 u_dsi_csi2/rHeader_0_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.683, 64.539%; route: 0.375, 35.461%
Arrival Data Path Delay: cell: 2.095, 48.133%; route: 1.875, 43.079%; tC2Q: 0.382, 8.788%
Required Clock Path Delay: cell: 0.683, 64.539%; route: 0.375, 35.461%

Path 2

Path Summary:
Slack 5.336
Data Arrival Time 5.410
Data Required Time 10.746
From u_dsi_csi2/rDataReg_19_s0
To u_dsi_csi2/rHeader_1_s0
Launch Clk I_BYTE_CLK[R]
Latch Clk I_BYTE_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_BYTE_CLK
0.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
0.683 0.683 tINS RR 175 I_BYTE_CLK_ibuf/O
1.058 0.375 tNET RR 1 u_dsi_csi2/rDataReg_19_s0/CLK
1.440 0.382 tC2Q RR 6 u_dsi_csi2/rDataReg_19_s0/Q
1.815 0.375 tNET RR 1 u_dsi_csi2/wHeader_3_s1/I0
2.341 0.526 tINS RR 2 u_dsi_csi2/wHeader_3_s1/F
2.716 0.375 tNET RR 1 u_dsi_csi2/n967_s4/I0
3.242 0.526 tINS RR 1 u_dsi_csi2/n967_s4/F
3.617 0.375 tNET RR 1 u_dsi_csi2/n967_s2/I1
4.134 0.516 tINS RR 3 u_dsi_csi2/n967_s2/F
4.509 0.375 tNET RR 1 u_dsi_csi2/n967_s1/I0
5.035 0.526 tINS RR 32 u_dsi_csi2/n967_s1/F
5.410 0.375 tNET RR 1 u_dsi_csi2/rHeader_1_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_BYTE_CLK
10.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
10.682 0.683 tINS RR 175 I_BYTE_CLK_ibuf/O
11.057 0.375 tNET RR 1 u_dsi_csi2/rHeader_1_s0/CLK
10.746 -0.311 tSu 1 u_dsi_csi2/rHeader_1_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.683, 64.539%; route: 0.375, 35.461%
Arrival Data Path Delay: cell: 2.095, 48.133%; route: 1.875, 43.079%; tC2Q: 0.382, 8.788%
Required Clock Path Delay: cell: 0.683, 64.539%; route: 0.375, 35.461%

Path 3

Path Summary:
Slack 5.336
Data Arrival Time 5.410
Data Required Time 10.746
From u_dsi_csi2/rDataReg_19_s0
To u_dsi_csi2/rHeader_2_s0
Launch Clk I_BYTE_CLK[R]
Latch Clk I_BYTE_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_BYTE_CLK
0.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
0.683 0.683 tINS RR 175 I_BYTE_CLK_ibuf/O
1.058 0.375 tNET RR 1 u_dsi_csi2/rDataReg_19_s0/CLK
1.440 0.382 tC2Q RR 6 u_dsi_csi2/rDataReg_19_s0/Q
1.815 0.375 tNET RR 1 u_dsi_csi2/wHeader_3_s1/I0
2.341 0.526 tINS RR 2 u_dsi_csi2/wHeader_3_s1/F
2.716 0.375 tNET RR 1 u_dsi_csi2/n967_s4/I0
3.242 0.526 tINS RR 1 u_dsi_csi2/n967_s4/F
3.617 0.375 tNET RR 1 u_dsi_csi2/n967_s2/I1
4.134 0.516 tINS RR 3 u_dsi_csi2/n967_s2/F
4.509 0.375 tNET RR 1 u_dsi_csi2/n967_s1/I0
5.035 0.526 tINS RR 32 u_dsi_csi2/n967_s1/F
5.410 0.375 tNET RR 1 u_dsi_csi2/rHeader_2_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_BYTE_CLK
10.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
10.682 0.683 tINS RR 175 I_BYTE_CLK_ibuf/O
11.057 0.375 tNET RR 1 u_dsi_csi2/rHeader_2_s0/CLK
10.746 -0.311 tSu 1 u_dsi_csi2/rHeader_2_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.683, 64.539%; route: 0.375, 35.461%
Arrival Data Path Delay: cell: 2.095, 48.133%; route: 1.875, 43.079%; tC2Q: 0.382, 8.788%
Required Clock Path Delay: cell: 0.683, 64.539%; route: 0.375, 35.461%

Path 4

Path Summary:
Slack 5.336
Data Arrival Time 5.410
Data Required Time 10.746
From u_dsi_csi2/rDataReg_19_s0
To u_dsi_csi2/rHeader_3_s0
Launch Clk I_BYTE_CLK[R]
Latch Clk I_BYTE_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_BYTE_CLK
0.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
0.683 0.683 tINS RR 175 I_BYTE_CLK_ibuf/O
1.058 0.375 tNET RR 1 u_dsi_csi2/rDataReg_19_s0/CLK
1.440 0.382 tC2Q RR 6 u_dsi_csi2/rDataReg_19_s0/Q
1.815 0.375 tNET RR 1 u_dsi_csi2/wHeader_3_s1/I0
2.341 0.526 tINS RR 2 u_dsi_csi2/wHeader_3_s1/F
2.716 0.375 tNET RR 1 u_dsi_csi2/n967_s4/I0
3.242 0.526 tINS RR 1 u_dsi_csi2/n967_s4/F
3.617 0.375 tNET RR 1 u_dsi_csi2/n967_s2/I1
4.134 0.516 tINS RR 3 u_dsi_csi2/n967_s2/F
4.509 0.375 tNET RR 1 u_dsi_csi2/n967_s1/I0
5.035 0.526 tINS RR 32 u_dsi_csi2/n967_s1/F
5.410 0.375 tNET RR 1 u_dsi_csi2/rHeader_3_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_BYTE_CLK
10.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
10.682 0.683 tINS RR 175 I_BYTE_CLK_ibuf/O
11.057 0.375 tNET RR 1 u_dsi_csi2/rHeader_3_s0/CLK
10.746 -0.311 tSu 1 u_dsi_csi2/rHeader_3_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.683, 64.539%; route: 0.375, 35.461%
Arrival Data Path Delay: cell: 2.095, 48.133%; route: 1.875, 43.079%; tC2Q: 0.382, 8.788%
Required Clock Path Delay: cell: 0.683, 64.539%; route: 0.375, 35.461%

Path 5

Path Summary:
Slack 5.336
Data Arrival Time 5.410
Data Required Time 10.746
From u_dsi_csi2/rDataReg_19_s0
To u_dsi_csi2/rHeader_4_s0
Launch Clk I_BYTE_CLK[R]
Latch Clk I_BYTE_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_BYTE_CLK
0.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
0.683 0.683 tINS RR 175 I_BYTE_CLK_ibuf/O
1.058 0.375 tNET RR 1 u_dsi_csi2/rDataReg_19_s0/CLK
1.440 0.382 tC2Q RR 6 u_dsi_csi2/rDataReg_19_s0/Q
1.815 0.375 tNET RR 1 u_dsi_csi2/wHeader_3_s1/I0
2.341 0.526 tINS RR 2 u_dsi_csi2/wHeader_3_s1/F
2.716 0.375 tNET RR 1 u_dsi_csi2/n967_s4/I0
3.242 0.526 tINS RR 1 u_dsi_csi2/n967_s4/F
3.617 0.375 tNET RR 1 u_dsi_csi2/n967_s2/I1
4.134 0.516 tINS RR 3 u_dsi_csi2/n967_s2/F
4.509 0.375 tNET RR 1 u_dsi_csi2/n967_s1/I0
5.035 0.526 tINS RR 32 u_dsi_csi2/n967_s1/F
5.410 0.375 tNET RR 1 u_dsi_csi2/rHeader_4_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_BYTE_CLK
10.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
10.682 0.683 tINS RR 175 I_BYTE_CLK_ibuf/O
11.057 0.375 tNET RR 1 u_dsi_csi2/rHeader_4_s0/CLK
10.746 -0.311 tSu 1 u_dsi_csi2/rHeader_4_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.683, 64.539%; route: 0.375, 35.461%
Arrival Data Path Delay: cell: 2.095, 48.133%; route: 1.875, 43.079%; tC2Q: 0.382, 8.788%
Required Clock Path Delay: cell: 0.683, 64.539%; route: 0.375, 35.461%