Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Gowin\Gowin_V1.9.9.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v
C:\Gowin\Gowin_V1.9.9.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v
C:\Gowin\Gowin_V1.9.9.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v
C:\Gowin\Gowin_V1.9.9.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v
C:\Gowin\Gowin_V1.9.9.01_x64\IDE\data\ipcores\GAO\GW_CON\gw_con_top_138.v
C:\Gowin\Gowin_V1.9.9.01_x64\IDE\data\ipcores\gw_jtag.v
E:\myWork\IP\releaseVerify\version\1.9.9.02\Gowin_DSI_RX_B2P_RefDesigns\csi_rx_demo_5a138\fpga_proj\impl\gao\gw_gao_top.v
GowinSynthesis Constraints File ---
Tool Version V1.9.9.01 (64-bit)
Part Number GW5AST-LV138FPG676AC1/I0
Device GW5AST-138
Device Version B
Created Time Thu Feb 29 14:47:25 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module gw_gao
Synthesis Process Running parser:
    CPU time = 0h 0m 0.375s, Elapsed time = 0h 0m 0.402s, Peak memory usage = 111.949MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 111.949MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.039s, Peak memory usage = 111.949MB
    Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.018s, Peak memory usage = 111.949MB
    Optimizing Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.046s, Peak memory usage = 111.949MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 111.949MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 111.949MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 111.949MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 111.949MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.033s, Peak memory usage = 111.949MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 111.949MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 111.949MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 139.500MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.053s, Peak memory usage = 139.500MB
Generate output files:
    CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.043s, Peak memory usage = 139.500MB
Total Time and Memory Usage CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 139.500MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 87
I/O Buf 87
    IBUF 86
    OBUF 1
Register 605
    DFFRE 1
    DFFPE 36
    DFFCE 568
LUT 547
    LUT2 81
    LUT3 122
    LUT4 344
MUX 1
    MUX16 1
ALU 14
    ALU 14
INV 4
    INV 4
BSRAM 10
    SDPX9B 10
Black Box 1
    GW_JTAG 1

Resource Utilization Summary

Resource Usage Utilization
Logic 573(559 LUT, 14 ALU) / 138240 <1%
Register 605 / 139140 <1%
  --Register as Latch 0 / 139140 0%
  --Register as FF 605 / 139140 <1%
BSRAM 10 / 340 3%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
byte_clk Base 10.000 100.0 0.000 5.000 byte_clk_ibuf/I
u_icon_top/n31_6 Base 10.000 100.0 0.000 5.000 u_icon_top/n31_s2/O
u_la0_top/n15_6 Base 10.000 100.0 0.000 5.000 u_la0_top/n15_s2/O

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 byte_clk 100.000(MHz) 177.620(MHz) 6 TOP
2 u_icon_top/n31_6 100.000(MHz) 476.758(MHz) 2 TOP
3 u_la0_top/n15_6 100.000(MHz) 1164.484(MHz) 1 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 4.370
Data Arrival Time 6.414
Data Required Time 10.784
From u_la0_top/u_ao_mem_ctrl/capture_length_2_s1
To u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
Launch Clk byte_clk[R]
Latch Clk byte_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 byte_clk
0.000 0.000 tCL RR 1 byte_clk_ibuf/I
0.683 0.683 tINS RR 254 byte_clk_ibuf/O
1.095 0.413 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLK
1.477 0.382 tC2Q RR 4 u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/Q
1.890 0.413 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n531_s2/I0
2.469 0.579 tINS RR 1 u_la0_top/u_ao_mem_ctrl/n531_s2/F
2.881 0.413 tNET RR 1 u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s6/I2
3.389 0.507 tINS RR 1 u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s6/F
3.801 0.413 tNET RR 1 u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s4/I3
4.090 0.289 tINS RR 2 u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s4/F
4.503 0.413 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s4/I0
5.081 0.579 tINS RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s4/F
5.494 0.413 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s3/I2
6.001 0.507 tINS RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s3/F
6.414 0.413 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 byte_clk
10.000 0.000 tCL RR 1 byte_clk_ibuf/I
10.682 0.683 tINS RR 254 byte_clk_ibuf/O
11.095 0.413 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
10.784 -0.311 tSu 1 u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.683, 62.329%; route: 0.413, 37.671%
Arrival Data Path Delay: cell: 2.461, 46.275%; route: 2.475, 46.533%; tC2Q: 0.382, 7.192%
Required Clock Path Delay: cell: 0.683, 62.329%; route: 0.413, 37.671%

Path 2

Path Summary:
Slack 4.940
Data Arrival Time 5.844
Data Required Time 10.784
From u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
To u_la0_top/u_ao_mem_ctrl/capture_loop_s1
Launch Clk byte_clk[R]
Latch Clk byte_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 byte_clk
0.000 0.000 tCL RR 1 byte_clk_ibuf/I
0.683 0.683 tINS RR 254 byte_clk_ibuf/O
1.095 0.413 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK
1.477 0.382 tC2Q RR 13 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/Q
1.890 0.413 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n629_s9/I0
2.469 0.579 tINS RR 1 u_la0_top/u_ao_mem_ctrl/n629_s9/F
2.881 0.413 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n629_s6/I0
3.460 0.579 tINS RR 1 u_la0_top/u_ao_mem_ctrl/n629_s6/F
3.872 0.413 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n629_s4/I1
4.440 0.567 tINS RR 12 u_la0_top/u_ao_mem_ctrl/n629_s4/F
4.852 0.413 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_loop_s4/I0
5.431 0.579 tINS RR 1 u_la0_top/u_ao_mem_ctrl/capture_loop_s4/F
5.844 0.413 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 byte_clk
10.000 0.000 tCL RR 1 byte_clk_ibuf/I
10.682 0.683 tINS RR 254 byte_clk_ibuf/O
11.095 0.413 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK
10.784 -0.311 tSu 1 u_la0_top/u_ao_mem_ctrl/capture_loop_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.683, 62.329%; route: 0.413, 37.671%
Arrival Data Path Delay: cell: 2.304, 48.513%; route: 2.063, 43.432%; tC2Q: 0.382, 8.055%
Required Clock Path Delay: cell: 0.683, 62.329%; route: 0.413, 37.671%

Path 3

Path Summary:
Slack 5.188
Data Arrival Time 5.844
Data Required Time 11.031
From u_la0_top/capture_window_sel_0_s3
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_10_s0
Launch Clk byte_clk[R]
Latch Clk byte_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 byte_clk
0.000 0.000 tCL RR 1 byte_clk_ibuf/I
0.683 0.683 tINS RR 254 byte_clk_ibuf/O
1.095 0.413 tNET RR 1 u_la0_top/capture_window_sel_0_s3/CLK
1.477 0.382 tC2Q RR 15 u_la0_top/capture_window_sel_0_s3/Q
1.890 0.413 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_10_s18/I1
2.457 0.567 tINS RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_10_s18/F
2.870 0.413 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_10_s15/I0
3.449 0.579 tINS RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_10_s15/F
3.861 0.413 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_10_s12/I0
4.440 0.579 tINS RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_10_s12/F
4.852 0.413 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_10_s11/I0
5.431 0.579 tINS RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_10_s11/F
5.844 0.413 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_10_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 byte_clk
10.000 0.000 tCL RR 1 byte_clk_ibuf/I
10.682 0.683 tINS RR 254 byte_clk_ibuf/O
11.095 0.413 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_10_s0/CLK
11.031 -0.064 tSu 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_10_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.683, 62.329%; route: 0.413, 37.671%
Arrival Data Path Delay: cell: 2.304, 48.513%; route: 2.063, 43.432%; tC2Q: 0.382, 8.055%
Required Clock Path Delay: cell: 0.683, 62.329%; route: 0.413, 37.671%

Path 4

Path Summary:
Slack 5.247
Data Arrival Time 5.784
Data Required Time 11.031
From u_la0_top/u_ao_mem_ctrl/capture_length_0_s1
To u_la0_top/u_ao_mem_ctrl/capture_length_10_s1
Launch Clk byte_clk[R]
Latch Clk byte_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 byte_clk
0.000 0.000 tCL RR 1 byte_clk_ibuf/I
0.683 0.683 tINS RR 254 byte_clk_ibuf/O
1.095 0.413 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLK
1.477 0.382 tC2Q RR 6 u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/Q
1.890 0.413 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n531_s4/I0
2.469 0.579 tINS RR 3 u_la0_top/u_ao_mem_ctrl/n531_s4/F
2.881 0.413 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n529_s1/I2
3.389 0.507 tINS RR 5 u_la0_top/u_ao_mem_ctrl/n529_s1/F
3.801 0.413 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n525_s1/I0
4.380 0.579 tINS RR 1 u_la0_top/u_ao_mem_ctrl/n525_s1/F
4.793 0.413 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n525_s4/I0
5.371 0.579 tINS RR 1 u_la0_top/u_ao_mem_ctrl/n525_s4/F
5.784 0.413 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_length_10_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 byte_clk
10.000 0.000 tCL RR 1 byte_clk_ibuf/I
10.682 0.683 tINS RR 254 byte_clk_ibuf/O
11.095 0.413 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_length_10_s1/CLK
11.031 -0.064 tSu 1 u_la0_top/u_ao_mem_ctrl/capture_length_10_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.683, 62.329%; route: 0.413, 37.671%
Arrival Data Path Delay: cell: 2.244, 47.854%; route: 2.063, 43.988%; tC2Q: 0.382, 8.158%
Required Clock Path Delay: cell: 0.683, 62.329%; route: 0.413, 37.671%

Path 5

Path Summary:
Slack 5.259
Data Arrival Time 5.773
Data Required Time 11.031
From u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5
Launch Clk byte_clk[R]
Latch Clk byte_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 byte_clk
0.000 0.000 tCL RR 1 byte_clk_ibuf/I
0.683 0.683 tINS RR 254 byte_clk_ibuf/O
1.095 0.413 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK
1.477 0.382 tC2Q RR 13 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/Q
1.890 0.413 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n629_s9/I0
2.469 0.579 tINS RR 1 u_la0_top/u_ao_mem_ctrl/n629_s9/F
2.881 0.413 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n629_s6/I0
3.460 0.579 tINS RR 1 u_la0_top/u_ao_mem_ctrl/n629_s6/F
3.872 0.413 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n629_s4/I1
4.440 0.567 tINS RR 12 u_la0_top/u_ao_mem_ctrl/n629_s4/F
4.852 0.413 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n639_s3/I2
5.360 0.507 tINS RR 1 u_la0_top/u_ao_mem_ctrl/n639_s3/F
5.773 0.413 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 byte_clk
10.000 0.000 tCL RR 1 byte_clk_ibuf/I
10.682 0.683 tINS RR 254 byte_clk_ibuf/O
11.095 0.413 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/CLK
11.031 -0.064 tSu 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.683, 62.329%; route: 0.413, 37.671%
Arrival Data Path Delay: cell: 2.233, 47.729%; route: 2.063, 44.094%; tC2Q: 0.382, 8.177%
Required Clock Path Delay: cell: 0.683, 62.329%; route: 0.413, 37.671%