Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | D:\Programs\Gowin\Gowin_V1.9.9Beta-6\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v D:\Programs\Gowin\Gowin_V1.9.9Beta-6\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v D:\Programs\Gowin\Gowin_V1.9.9Beta-6\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v D:\Programs\Gowin\Gowin_V1.9.9Beta-6\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v D:\Programs\Gowin\Gowin_V1.9.9Beta-6\IDE\data\ipcores\GAO\GW_CON\gw_con_top_138.v D:\Programs\Gowin\Gowin_V1.9.9Beta-6\IDE\data\ipcores\gw_jtag.v F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\DSI_to_LVDS_5a138\fpga_proj\impl\gao\gw_gao_top.v |
GowinSynthesis Constraints File | --- |
Version | V1.9.9 Beta-6 |
Part Number | GW5AST-LV138FPG676AC1/I0 |
Device | GW5AST-138 |
Device Version | B |
Created Time | Wed Oct 25 17:41:13 2023 |
Legal Announcement | Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | gw_gao |
Synthesis Process | Running parser: CPU time = 0h 0m 0.562s, Elapsed time = 0h 0m 0.557s, Peak memory usage = 45.297MB Running netlist conversion: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 45.297MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.035s, Peak memory usage = 45.297MB Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.017s, Peak memory usage = 45.297MB Optimizing Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.051s, Peak memory usage = 45.297MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 45.297MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 45.297MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 45.297MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 45.297MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.031s, Peak memory usage = 45.297MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 45.297MB Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 45.297MB Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 57.480MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.047s, Peak memory usage = 57.480MB Generate output files: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.099s, Peak memory usage = 57.480MB |
Total Time and Memory Usage | CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 57.480MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 110 |
I/O Buf | 110 |
    IBUF | 109 |
    OBUF | 1 |
Register | 643 |
    DFFPE | 36 |
    DFFCE | 607 |
LUT | 470 |
    LUT2 | 71 |
    LUT3 | 115 |
    LUT4 | 284 |
MUX | 1 |
    MUX16 | 1 |
ALU | 10 |
    ALU | 10 |
INV | 4 |
    INV | 4 |
BSRAM | 12 |
    SDPX9B | 12 |
Black Box | 1 |
    GW_JTAG | 1 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 492(482 LUT, 10 ALU) / 138240 | <1% |
Register | 643 / 139140 | <1% |
  --Register as Latch | 0 / 139140 | 0% |
  --Register as FF | 643 / 139140 | <1% |
BSRAM | 12 / 340 | 4% |
Timing
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|
byte_clk | Base | 10.000 | 100.0 | 0.000 | 5.000 | byte_clk_ibuf/I | ||
u_icon_top/n31_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 | u_icon_top/n31_s2/O | ||
u_la0_top/n15_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 | u_la0_top/n15_s2/O |
Max Frequency Summary:
No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | byte_clk | 100.0(MHz) | 238.5(MHz) | 6 | TOP |
2 | u_icon_top/n31_6 | 100.0(MHz) | 593.5(MHz) | 2 | TOP |
3 | u_la0_top/n15_6 | 100.0(MHz) | 1532.6(MHz) | 1 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | 5.806 |
Data Arrival Time | 5.019 |
Data Required Time | 10.825 |
From | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1 |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1 |
Launch Clk | byte_clk[R] |
Latch Clk | byte_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | byte_clk | |||
0.000 | 0.000 | tCL | RR | 1 | byte_clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 272 | byte_clk_ibuf/O |
0.889 | 0.206 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLK |
1.271 | 0.382 | tC2Q | RR | 18 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/Q |
1.477 | 0.206 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/n685_s2/I0 |
2.056 | 0.579 | tINS | RR | 4 | u_la0_top/u_ao_mem_ctrl/n685_s2/F |
2.263 | 0.206 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/n682_s2/I3 |
2.551 | 0.289 | tINS | RR | 3 | u_la0_top/u_ao_mem_ctrl/n682_s2/F |
2.757 | 0.206 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/n681_s3/I1 |
3.325 | 0.567 | tINS | RR | 2 | u_la0_top/u_ao_mem_ctrl/n681_s3/F |
3.531 | 0.206 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/n679_s4/I2 |
4.039 | 0.507 | tINS | RR | 1 | u_la0_top/u_ao_mem_ctrl/n679_s4/F |
4.245 | 0.206 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/n679_s2/I1 |
4.813 | 0.567 | tINS | RR | 1 | u_la0_top/u_ao_mem_ctrl/n679_s2/F |
5.019 | 0.206 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | byte_clk | |||
10.000 | 0.000 | tCL | RR | 1 | byte_clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 272 | byte_clk_ibuf/O |
10.889 | 0.206 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/CLK |
10.825 | -0.064 | tSu | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 6 |
Arrival Clock Path Delay: | cell: 0.683, 76.793%; route: 0.206, 23.207% |
Arrival Data Path Delay: | cell: 2.510, 60.774%; route: 1.237, 29.964%; tC2Q: 0.382, 9.262% |
Required Clock Path Delay: | cell: 0.683, 76.793%; route: 0.206, 23.207% |
Path 2
Path Summary:Slack | 5.960 |
Data Arrival Time | 4.617 |
Data Required Time | 10.578 |
From | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1 |
To | u_la0_top/u_ao_mem_ctrl/capture_loop_s1 |
Launch Clk | byte_clk[R] |
Latch Clk | byte_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | byte_clk | |||
0.000 | 0.000 | tCL | RR | 1 | byte_clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 272 | byte_clk_ibuf/O |
0.889 | 0.206 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK |
1.271 | 0.382 | tC2Q | RR | 15 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/Q |
1.477 | 0.206 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/n679_s9/I0 |
2.056 | 0.579 | tINS | RR | 1 | u_la0_top/u_ao_mem_ctrl/n679_s9/F |
2.263 | 0.206 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/n679_s7/I0 |
2.841 | 0.579 | tINS | RR | 2 | u_la0_top/u_ao_mem_ctrl/n679_s7/F |
3.047 | 0.206 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/n679_s5/I0 |
3.626 | 0.579 | tINS | RR | 11 | u_la0_top/u_ao_mem_ctrl/n679_s5/F |
3.832 | 0.206 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_loop_s4/I0 |
4.411 | 0.579 | tINS | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_loop_s4/F |
4.617 | 0.206 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | byte_clk | |||
10.000 | 0.000 | tCL | RR | 1 | byte_clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 272 | byte_clk_ibuf/O |
10.889 | 0.206 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK |
10.578 | -0.311 | tSu | 1 | u_la0_top/u_ao_mem_ctrl/capture_loop_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.683, 76.793%; route: 0.206, 23.207% |
Arrival Data Path Delay: | cell: 2.315, 62.085%; route: 1.031, 27.657%; tC2Q: 0.382, 10.258% |
Required Clock Path Delay: | cell: 0.683, 76.793%; route: 0.206, 23.207% |
Path 3
Path Summary:Slack | 6.279 |
Data Arrival Time | 4.546 |
Data Required Time | 10.825 |
From | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1 |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1 |
Launch Clk | byte_clk[R] |
Latch Clk | byte_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | byte_clk | |||
0.000 | 0.000 | tCL | RR | 1 | byte_clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 272 | byte_clk_ibuf/O |
0.889 | 0.206 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK |
1.271 | 0.382 | tC2Q | RR | 15 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/Q |
1.477 | 0.206 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/n679_s9/I0 |
2.056 | 0.579 | tINS | RR | 1 | u_la0_top/u_ao_mem_ctrl/n679_s9/F |
2.263 | 0.206 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/n679_s7/I0 |
2.841 | 0.579 | tINS | RR | 2 | u_la0_top/u_ao_mem_ctrl/n679_s7/F |
3.047 | 0.206 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/n679_s5/I0 |
3.626 | 0.579 | tINS | RR | 11 | u_la0_top/u_ao_mem_ctrl/n679_s5/F |
3.832 | 0.206 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/n688_s1/I2 |
4.340 | 0.507 | tINS | RR | 1 | u_la0_top/u_ao_mem_ctrl/n688_s1/F |
4.546 | 0.206 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | byte_clk | |||
10.000 | 0.000 | tCL | RR | 1 | byte_clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 272 | byte_clk_ibuf/O |
10.889 | 0.206 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK |
10.825 | -0.064 | tSu | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.683, 76.793%; route: 0.206, 23.207% |
Arrival Data Path Delay: | cell: 2.244, 61.347%; route: 1.031, 28.195%; tC2Q: 0.382, 10.458% |
Required Clock Path Delay: | cell: 0.683, 76.793%; route: 0.206, 23.207% |
Path 4
Path Summary:Slack | 6.279 |
Data Arrival Time | 4.546 |
Data Required Time | 10.825 |
From | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1 |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1 |
Launch Clk | byte_clk[R] |
Latch Clk | byte_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | byte_clk | |||
0.000 | 0.000 | tCL | RR | 1 | byte_clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 272 | byte_clk_ibuf/O |
0.889 | 0.206 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK |
1.271 | 0.382 | tC2Q | RR | 15 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/Q |
1.477 | 0.206 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/n679_s9/I0 |
2.056 | 0.579 | tINS | RR | 1 | u_la0_top/u_ao_mem_ctrl/n679_s9/F |
2.263 | 0.206 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/n679_s7/I0 |
2.841 | 0.579 | tINS | RR | 2 | u_la0_top/u_ao_mem_ctrl/n679_s7/F |
3.047 | 0.206 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/n679_s5/I0 |
3.626 | 0.579 | tINS | RR | 11 | u_la0_top/u_ao_mem_ctrl/n679_s5/F |
3.832 | 0.206 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/n686_s1/I2 |
4.340 | 0.507 | tINS | RR | 1 | u_la0_top/u_ao_mem_ctrl/n686_s1/F |
4.546 | 0.206 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | byte_clk | |||
10.000 | 0.000 | tCL | RR | 1 | byte_clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 272 | byte_clk_ibuf/O |
10.889 | 0.206 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK |
10.825 | -0.064 | tSu | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.683, 76.793%; route: 0.206, 23.207% |
Arrival Data Path Delay: | cell: 2.244, 61.347%; route: 1.031, 28.195%; tC2Q: 0.382, 10.458% |
Required Clock Path Delay: | cell: 0.683, 76.793%; route: 0.206, 23.207% |
Path 5
Path Summary:Slack | 6.279 |
Data Arrival Time | 4.546 |
Data Required Time | 10.825 |
From | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1 |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1 |
Launch Clk | byte_clk[R] |
Latch Clk | byte_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | byte_clk | |||
0.000 | 0.000 | tCL | RR | 1 | byte_clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 272 | byte_clk_ibuf/O |
0.889 | 0.206 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK |
1.271 | 0.382 | tC2Q | RR | 15 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/Q |
1.477 | 0.206 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/n679_s9/I0 |
2.056 | 0.579 | tINS | RR | 1 | u_la0_top/u_ao_mem_ctrl/n679_s9/F |
2.263 | 0.206 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/n679_s7/I0 |
2.841 | 0.579 | tINS | RR | 2 | u_la0_top/u_ao_mem_ctrl/n679_s7/F |
3.047 | 0.206 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/n679_s5/I0 |
3.626 | 0.579 | tINS | RR | 11 | u_la0_top/u_ao_mem_ctrl/n679_s5/F |
3.832 | 0.206 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/n685_s1/I2 |
4.340 | 0.507 | tINS | RR | 1 | u_la0_top/u_ao_mem_ctrl/n685_s1/F |
4.546 | 0.206 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | byte_clk | |||
10.000 | 0.000 | tCL | RR | 1 | byte_clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 272 | byte_clk_ibuf/O |
10.889 | 0.206 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK |
10.825 | -0.064 | tSu | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.683, 76.793%; route: 0.206, 23.207% |
Arrival Data Path Delay: | cell: 2.244, 61.347%; route: 1.031, 28.195%; tC2Q: 0.382, 10.458% |
Required Clock Path Delay: | cell: 0.683, 76.793%; route: 0.206, 23.207% |