Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Programs\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\MIPI_BYTE_TO_PIXEL\data\byte_to_pixel.v
D:\Programs\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\MIPI_BYTE_TO_PIXEL\data\byte_to_pixel_wrap.v
GowinSynthesis Constraints File ---
Tool Version V1.9.9.01 (64-bit)
Part Number GW2A-LV18QN88C7/I6
Device GW2A-18
Device Version C
Created Time Wed Mar 6 18:26:09 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module Byte_to_Pixel_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.211s, Peak memory usage = 109.172MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 109.172MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.019s, Peak memory usage = 109.172MB
    Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 109.172MB
    Optimizing Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.022s, Peak memory usage = 109.172MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 109.172MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 109.172MB
    Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 109.172MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 109.172MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 109.172MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 109.172MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 109.172MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.5s, Elapsed time = 0h 0m 0.558s, Peak memory usage = 136.172MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.057s, Peak memory usage = 136.172MB
Generate output files:
    CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.075s, Peak memory usage = 136.172MB
Total Time and Memory Usage CPU time = 0h 0m 0.917s, Elapsed time = 0h 0m 0.996s, Peak memory usage = 136.172MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 90
I/O Buf 90
    IBUF 63
    OBUF 27
Register 457
    DFF 12
    DFFE 48
    DFFS 2
    DFFR 7
    DFFRE 67
    DFFP 3
    DFFPE 6
    DFFC 62
    DFFCE 250
LUT 309
    LUT2 35
    LUT3 76
    LUT4 198
ALU 14
    ALU 14
SSRAM 12
    RAM16SDP4 12
INV 6
    INV 6

Resource Utilization Summary

Resource Usage Utilization
Logic 401(315 LUT, 14 ALU, 12 RAM16) / 20736 2%
Register 457 / 15750 3%
  --Register as Latch 0 / 15750 0%
  --Register as FF 457 / 15750 3%
BSRAM 0 / 46 0%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
I_BYTE_CLK Base 10.000 100.0 0.000 5.000 I_BYTE_CLK_ibuf/I
I_PIXEL_CLK Base 10.000 100.0 0.000 5.000 I_PIXEL_CLK_ibuf/I

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 I_BYTE_CLK 100.000(MHz) 138.298(MHz) 7 TOP
2 I_PIXEL_CLK 100.000(MHz) 166.396(MHz) 6 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 2.769
Data Arrival Time 8.490
Data Required Time 11.259
From u_b2p_inst/u_mid_fifo/rRPtrWsync_2_s0
To u_b2p_inst/u_mid_fifo/rFull_s0
Launch Clk I_BYTE_CLK[R]
Latch Clk I_BYTE_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_BYTE_CLK
0.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
0.853 0.853 tINS RR 339 I_BYTE_CLK_ibuf/O
1.303 0.450 tNET RR 1 u_b2p_inst/u_mid_fifo/rRPtrWsync_2_s0/CLK
1.593 0.290 tC2Q RF 2 u_b2p_inst/u_mid_fifo/rRPtrWsync_2_s0/Q
2.186 0.593 tNET FF 1 u_b2p_inst/u_mid_fifo/wRPtrBinX_1_s1/I1
2.879 0.694 tINS FF 2 u_b2p_inst/u_mid_fifo/wRPtrBinX_1_s1/F
3.472 0.593 tNET FF 1 u_b2p_inst/u_mid_fifo/wRPtrBinX_0_s0/I1
4.166 0.694 tINS FF 1 u_b2p_inst/u_mid_fifo/wRPtrBinX_0_s0/F
4.758 0.593 tNET FF 2 u_b2p_inst/u_mid_fifo/n343_s0/I1
5.471 0.712 tINS FR 1 u_b2p_inst/u_mid_fifo/n343_s0/COUT
5.471 0.000 tNET RR 2 u_b2p_inst/u_mid_fifo/n344_s0/CIN
5.515 0.044 tINS RF 1 u_b2p_inst/u_mid_fifo/n344_s0/COUT
5.515 0.000 tNET FF 2 u_b2p_inst/u_mid_fifo/n345_s0/CIN
5.559 0.044 tINS FF 1 u_b2p_inst/u_mid_fifo/n345_s0/COUT
5.559 0.000 tNET FF 2 u_b2p_inst/u_mid_fifo/n346_s0/CIN
5.603 0.044 tINS FF 1 u_b2p_inst/u_mid_fifo/n346_s0/COUT
6.195 0.593 tNET FF 1 u_b2p_inst/u_mid_fifo/n358_s3/I0
6.841 0.646 tINS FF 1 u_b2p_inst/u_mid_fifo/n358_s3/F
7.434 0.593 tNET FF 1 u_b2p_inst/u_mid_fifo/n358_s0/I3
7.898 0.464 tINS FF 1 u_b2p_inst/u_mid_fifo/n358_s0/F
8.490 0.593 tNET FF 1 u_b2p_inst/u_mid_fifo/rFull_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_BYTE_CLK
10.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
10.853 0.853 tINS RR 339 I_BYTE_CLK_ibuf/O
11.303 0.450 tNET RR 1 u_b2p_inst/u_mid_fifo/rFull_s0/CLK
11.259 -0.044 tSu 1 u_b2p_inst/u_mid_fifo/rFull_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.853, 65.468%; route: 0.450, 34.532%
Arrival Data Path Delay: cell: 3.342, 46.501%; route: 3.555, 49.464%; tC2Q: 0.290, 4.035%
Required Clock Path Delay: cell: 0.853, 65.468%; route: 0.450, 34.532%

Path 2

Path Summary:
Slack 3.976
Data Arrival Time 7.283
Data Required Time 11.259
From u_b2p_inst/wc_cnt_dec_6_s1
To u_b2p_inst/wc_cnt_dec_13_s1
Launch Clk I_BYTE_CLK[R]
Latch Clk I_BYTE_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_BYTE_CLK
0.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
0.853 0.853 tINS RR 339 I_BYTE_CLK_ibuf/O
1.303 0.450 tNET RR 1 u_b2p_inst/wc_cnt_dec_6_s1/CLK
1.593 0.290 tC2Q RF 3 u_b2p_inst/wc_cnt_dec_6_s1/Q
2.186 0.593 tNET FF 1 u_b2p_inst/n1191_s2/I1
2.879 0.694 tINS FF 4 u_b2p_inst/n1191_s2/F
3.472 0.593 tNET FF 1 u_b2p_inst/n1191_s1/I1
4.166 0.694 tINS FF 4 u_b2p_inst/n1191_s1/F
4.758 0.593 tNET FF 1 u_b2p_inst/n1190_s1/I1
5.452 0.694 tINS FF 1 u_b2p_inst/n1190_s1/F
6.044 0.593 tNET FF 1 u_b2p_inst/n1190_s0/I0
6.691 0.646 tINS FF 1 u_b2p_inst/n1190_s0/F
7.283 0.593 tNET FF 1 u_b2p_inst/wc_cnt_dec_13_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_BYTE_CLK
10.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
10.853 0.853 tINS RR 339 I_BYTE_CLK_ibuf/O
11.303 0.450 tNET RR 1 u_b2p_inst/wc_cnt_dec_13_s1/CLK
11.259 -0.044 tSu 1 u_b2p_inst/wc_cnt_dec_13_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.853, 65.468%; route: 0.450, 34.532%
Arrival Data Path Delay: cell: 2.728, 45.610%; route: 2.963, 49.541%; tC2Q: 0.290, 4.849%
Required Clock Path Delay: cell: 0.853, 65.468%; route: 0.450, 34.532%

Path 3

Path Summary:
Slack 3.976
Data Arrival Time 7.283
Data Required Time 11.259
From u_b2p_inst/u_dsi_sync_detec/rVSyncCnt_1_s0
To u_b2p_inst/u_dsi_sync_detec/rVSync_s0
Launch Clk I_BYTE_CLK[R]
Latch Clk I_BYTE_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_BYTE_CLK
0.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
0.853 0.853 tINS RR 339 I_BYTE_CLK_ibuf/O
1.303 0.450 tNET RR 1 u_b2p_inst/u_dsi_sync_detec/rVSyncCnt_1_s0/CLK
1.593 0.290 tC2Q RF 4 u_b2p_inst/u_dsi_sync_detec/rVSyncCnt_1_s0/Q
2.186 0.593 tNET FF 1 u_b2p_inst/u_dsi_sync_detec/n62_s3/I1
2.879 0.694 tINS FF 4 u_b2p_inst/u_dsi_sync_detec/n62_s3/F
3.472 0.593 tNET FF 1 u_b2p_inst/u_dsi_sync_detec/n57_s5/I1
4.166 0.694 tINS FF 4 u_b2p_inst/u_dsi_sync_detec/n57_s5/F
4.758 0.593 tNET FF 1 u_b2p_inst/u_dsi_sync_detec/n108_s5/I1
5.452 0.694 tINS FF 3 u_b2p_inst/u_dsi_sync_detec/n108_s5/F
6.044 0.593 tNET FF 1 u_b2p_inst/u_dsi_sync_detec/n108_s0/I0
6.691 0.646 tINS FF 1 u_b2p_inst/u_dsi_sync_detec/n108_s0/F
7.283 0.593 tNET FF 1 u_b2p_inst/u_dsi_sync_detec/rVSync_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_BYTE_CLK
10.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
10.853 0.853 tINS RR 339 I_BYTE_CLK_ibuf/O
11.303 0.450 tNET RR 1 u_b2p_inst/u_dsi_sync_detec/rVSync_s0/CLK
11.259 -0.044 tSu 1 u_b2p_inst/u_dsi_sync_detec/rVSync_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.853, 65.468%; route: 0.450, 34.532%
Arrival Data Path Delay: cell: 2.728, 45.610%; route: 2.963, 49.541%; tC2Q: 0.290, 4.849%
Required Clock Path Delay: cell: 0.853, 65.468%; route: 0.450, 34.532%

Path 4

Path Summary:
Slack 3.990
Data Arrival Time 7.269
Data Required Time 11.259
From u_b2p_inst/u_mid_fifo/rWPtrRsync_2_s0
To u_b2p_inst/u_mid_fifo/rEmpty_s0
Launch Clk I_PIXEL_CLK[R]
Latch Clk I_PIXEL_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_PIXEL_CLK
0.000 0.000 tCL RR 1 I_PIXEL_CLK_ibuf/I
0.853 0.853 tINS RR 130 I_PIXEL_CLK_ibuf/O
1.303 0.450 tNET RR 1 u_b2p_inst/u_mid_fifo/rWPtrRsync_2_s0/CLK
1.593 0.290 tC2Q RF 3 u_b2p_inst/u_mid_fifo/rWPtrRsync_2_s0/Q
2.186 0.593 tNET FF 1 u_b2p_inst/u_mid_fifo/wWPtrBinX_1_s1/I1
2.879 0.694 tINS FF 4 u_b2p_inst/u_mid_fifo/wWPtrBinX_1_s1/F
3.472 0.593 tNET FF 1 u_b2p_inst/u_mid_fifo/wWPtrBinX_0_s0/I1
4.166 0.694 tINS FF 2 u_b2p_inst/u_mid_fifo/wWPtrBinX_0_s0/F
4.758 0.593 tNET FF 2 u_b2p_inst/u_mid_fifo/n324_s0/I0
5.444 0.686 tINS FR 1 u_b2p_inst/u_mid_fifo/n324_s0/COUT
5.444 0.000 tNET RR 2 u_b2p_inst/u_mid_fifo/n325_s0/CIN
5.488 0.044 tINS RF 1 u_b2p_inst/u_mid_fifo/n325_s0/COUT
5.488 0.000 tNET FF 2 u_b2p_inst/u_mid_fifo/n326_s0/CIN
5.532 0.044 tINS FF 1 u_b2p_inst/u_mid_fifo/n326_s0/COUT
5.532 0.000 tNET FF 2 u_b2p_inst/u_mid_fifo/n327_s0/CIN
5.576 0.044 tINS FF 1 u_b2p_inst/u_mid_fifo/n327_s0/COUT
5.576 0.000 tNET FF 2 u_b2p_inst/u_mid_fifo/n328_s0/CIN
5.620 0.044 tINS FF 1 u_b2p_inst/u_mid_fifo/n328_s0/COUT
6.213 0.593 tNET FF 1 u_b2p_inst/u_mid_fifo/n330_s0/I3
6.677 0.464 tINS FF 1 u_b2p_inst/u_mid_fifo/n330_s0/F
7.269 0.593 tNET FF 1 u_b2p_inst/u_mid_fifo/rEmpty_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_PIXEL_CLK
10.000 0.000 tCL RR 1 I_PIXEL_CLK_ibuf/I
10.853 0.853 tINS RR 130 I_PIXEL_CLK_ibuf/O
11.303 0.450 tNET RR 1 u_b2p_inst/u_mid_fifo/rEmpty_s0/CLK
11.259 -0.044 tSu 1 u_b2p_inst/u_mid_fifo/rEmpty_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.853, 65.468%; route: 0.450, 34.532%
Arrival Data Path Delay: cell: 2.713, 45.483%; route: 2.963, 49.656%; tC2Q: 0.290, 4.861%
Required Clock Path Delay: cell: 0.853, 65.468%; route: 0.450, 34.532%

Path 5

Path Summary:
Slack 4.053
Data Arrival Time 7.207
Data Required Time 11.259
From u_b2p_inst/u_dsi_sync_detec/rVSyncCnt_1_s0
To u_b2p_inst/u_dsi_sync_detec/rVSyncCnt_9_s0
Launch Clk I_BYTE_CLK[R]
Latch Clk I_BYTE_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_BYTE_CLK
0.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
0.853 0.853 tINS RR 339 I_BYTE_CLK_ibuf/O
1.303 0.450 tNET RR 1 u_b2p_inst/u_dsi_sync_detec/rVSyncCnt_1_s0/CLK
1.593 0.290 tC2Q RF 4 u_b2p_inst/u_dsi_sync_detec/rVSyncCnt_1_s0/Q
2.186 0.593 tNET FF 1 u_b2p_inst/u_dsi_sync_detec/n62_s3/I1
2.879 0.694 tINS FF 4 u_b2p_inst/u_dsi_sync_detec/n62_s3/F
3.472 0.593 tNET FF 1 u_b2p_inst/u_dsi_sync_detec/n57_s5/I1
4.166 0.694 tINS FF 4 u_b2p_inst/u_dsi_sync_detec/n57_s5/F
4.758 0.593 tNET FF 1 u_b2p_inst/u_dsi_sync_detec/n108_s5/I1
5.452 0.694 tINS FF 3 u_b2p_inst/u_dsi_sync_detec/n108_s5/F
6.044 0.593 tNET FF 1 u_b2p_inst/u_dsi_sync_detec/rVSyncCnt_8_s3/I1
6.757 0.712 tINS FR 9 u_b2p_inst/u_dsi_sync_detec/rVSyncCnt_8_s3/F
7.207 0.450 tNET RR 1 u_b2p_inst/u_dsi_sync_detec/rVSyncCnt_9_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_BYTE_CLK
10.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
10.853 0.853 tINS RR 339 I_BYTE_CLK_ibuf/O
11.303 0.450 tNET RR 1 u_b2p_inst/u_dsi_sync_detec/rVSyncCnt_9_s0/CLK
11.259 -0.044 tSu 1 u_b2p_inst/u_dsi_sync_detec/rVSyncCnt_9_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.853, 65.468%; route: 0.450, 34.532%
Arrival Data Path Delay: cell: 2.794, 47.322%; route: 2.820, 47.766%; tC2Q: 0.290, 4.912%
Required Clock Path Delay: cell: 0.853, 65.468%; route: 0.450, 34.532%