Timing Messages
Report Title | Timing Analysis Report |
Design File | F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\DSI_to_LVDS_2a18\fpga_proj\impl\gwsynthesis\dsi_to_lvds.vg |
Physical Constraints File | F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\DSI_to_LVDS_2a18\fpga_proj\src\DK_START_Gw2A18_V2.cst |
Timing Constraint File | F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\DSI_to_LVDS_2a18\fpga_proj\src\dsi_to_lvds_osc.sdc |
Tool Version | V1.9.9.01 (64-bit) |
Part Number | GW2A-LV18PG256C8/I7 |
Device | GW2A-18 |
Device Version | C |
Created Time | Wed Mar 6 18:46:37 2024 |
Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved. |
Timing Summaries
STA Tool Run Summary:
Setup Delay Model | Slow 0.95V 85C C8/I7 |
Hold Delay Model | Fast 1.05V 0C C8/I7 |
Numbers of Paths Analyzed | 5563 |
Numbers of Endpoints Analyzed | 3727 |
Numbers of Falling Endpoints | 1 |
Numbers of Setup Violated Endpoints | 0 |
Numbers of Hold Violated Endpoints | 0 |
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Objects |
---|---|---|---|---|---|---|---|---|
mipi_clk | Base | 12.000 | 83.333 | 0.000 | 6.000 | HS_CLK_P | ||
clk_50 | Base | 20.000 | 50.000 | 0.000 | 10.000 | OSC_50M | ||
byte_clk | Base | 9.524 | 104.998 | 0.000 | 4.762 | byte_clk | ||
pixel_clk | Generated | 7.143 | 139.997 | 0.000 | 3.572 | byte_clk | byte_clk | pixel_clk |
lvds_pclk | Generated | 7.143 | 140.000 | 0.000 | 3.571 | OSC_50M | clk_50 | lvds_pclk |
u_pll_2/rpll_inst/CLKOUT.default_gen_clk | Generated | 2.041 | 490.000 | 0.000 | 1.020 | OSC_50M_ibuf/I | clk_50 | u_pll_2/rpll_inst/CLKOUT |
u_pll_2/rpll_inst/CLKOUTP.default_gen_clk | Generated | 2.041 | 490.000 | 0.000 | 1.020 | OSC_50M_ibuf/I | clk_50 | u_pll_2/rpll_inst/CLKOUTP |
u_pll_2/rpll_inst/CLKOUTD.default_gen_clk | Generated | 4.082 | 245.000 | 0.000 | 2.041 | OSC_50M_ibuf/I | clk_50 | u_pll_2/rpll_inst/CLKOUTD |
u_pll_2/rpll_inst/CLKOUTD3.default_gen_clk | Generated | 6.122 | 163.333 | 0.000 | 3.061 | OSC_50M_ibuf/I | clk_50 | u_pll_2/rpll_inst/CLKOUTD3 |
u_pll_1/rpll_inst/CLKOUTP.default_gen_clk | Generated | 7.143 | 139.997 | 0.000 | 3.572 | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT | byte_clk | u_pll_1/rpll_inst/CLKOUTP |
u_pll_1/rpll_inst/CLKOUTD.default_gen_clk | Generated | 14.286 | 69.999 | 0.000 | 7.143 | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT | byte_clk | u_pll_1/rpll_inst/CLKOUTD |
u_pll_1/rpll_inst/CLKOUTD3.default_gen_clk | Generated | 21.429 | 46.666 | 0.000 | 10.715 | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT | byte_clk | u_pll_1/rpll_inst/CLKOUTD3 |
Max Frequency Summary:
NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | mipi_clk | 83.333(MHz) | 95.429(MHz) | 2 | TOP |
2 | byte_clk | 104.998(MHz) | 156.521(MHz) | 7 | TOP |
3 | pixel_clk | 139.997(MHz) | 238.420(MHz) | 6 | TOP |
4 | lvds_pclk | 140.000(MHz) | 243.460(MHz) | 5 | TOP |
No timing paths to get frequency of clk_50!
No timing paths to get frequency of u_pll_2/rpll_inst/CLKOUT.default_gen_clk!
No timing paths to get frequency of u_pll_2/rpll_inst/CLKOUTP.default_gen_clk!
No timing paths to get frequency of u_pll_2/rpll_inst/CLKOUTD.default_gen_clk!
No timing paths to get frequency of u_pll_2/rpll_inst/CLKOUTD3.default_gen_clk!
No timing paths to get frequency of u_pll_1/rpll_inst/CLKOUTP.default_gen_clk!
No timing paths to get frequency of u_pll_1/rpll_inst/CLKOUTD.default_gen_clk!
No timing paths to get frequency of u_pll_1/rpll_inst/CLKOUTD3.default_gen_clk!
Total Negative Slack Summary:
Clock Name | Analysis Type | Endpoints TNS | Number of Endpoints |
---|---|---|---|
mipi_clk | Setup | 0.000 | 0 |
mipi_clk | Hold | 0.000 | 0 |
clk_50 | Setup | 0.000 | 0 |
clk_50 | Hold | 0.000 | 0 |
byte_clk | Setup | 0.000 | 0 |
byte_clk | Hold | 0.000 | 0 |
pixel_clk | Setup | 0.000 | 0 |
pixel_clk | Hold | 0.000 | 0 |
lvds_pclk | Setup | 0.000 | 0 |
lvds_pclk | Hold | 0.000 | 0 |
u_pll_2/rpll_inst/CLKOUT.default_gen_clk | Setup | 0.000 | 0 |
u_pll_2/rpll_inst/CLKOUT.default_gen_clk | Hold | 0.000 | 0 |
u_pll_2/rpll_inst/CLKOUTP.default_gen_clk | Setup | 0.000 | 0 |
u_pll_2/rpll_inst/CLKOUTP.default_gen_clk | Hold | 0.000 | 0 |
u_pll_2/rpll_inst/CLKOUTD.default_gen_clk | Setup | 0.000 | 0 |
u_pll_2/rpll_inst/CLKOUTD.default_gen_clk | Hold | 0.000 | 0 |
u_pll_2/rpll_inst/CLKOUTD3.default_gen_clk | Setup | 0.000 | 0 |
u_pll_2/rpll_inst/CLKOUTD3.default_gen_clk | Hold | 0.000 | 0 |
u_pll_1/rpll_inst/CLKOUTP.default_gen_clk | Setup | 0.000 | 0 |
u_pll_1/rpll_inst/CLKOUTP.default_gen_clk | Hold | 0.000 | 0 |
u_pll_1/rpll_inst/CLKOUTD.default_gen_clk | Setup | 0.000 | 0 |
u_pll_1/rpll_inst/CLKOUTD.default_gen_clk | Hold | 0.000 | 0 |
u_pll_1/rpll_inst/CLKOUTD3.default_gen_clk | Setup | 0.000 | 0 |
u_pll_1/rpll_inst/CLKOUTD3.default_gen_clk | Hold | 0.000 | 0 |
Timing Details
Path Slacks Table:
Setup Paths Table
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 0.761 | u_mipi_dphy/DPHY_RX_INST/u_idesx8/opensync_0_s0/Q | u_mipi_dphy/DPHY_RX_INST/u_idesx8/u_DHCEN/CE | mipi_clk:[R] | mipi_clk:[F] | 6.000 | 2.893 | 2.161 |
2 | 2.949 | u_b2p/u_b2p_inst/u_mid_fifo/rWPtrRsync_4_s0/Q | u_b2p/u_b2p_inst/u_mid_fifo/rEmpty_s0/D | pixel_clk:[R] | pixel_clk:[R] | 7.143 | 0.000 | 4.159 |
3 | 3.035 | u_extr/ohcnt_0_s0/Q | u_extr/ohcnt_0_s0/D | lvds_pclk:[R] | lvds_pclk:[R] | 7.143 | 0.000 | 4.072 |
4 | 3.069 | u_extr/ovcnt_1_s1/Q | u_extr/ohs_s0/D | lvds_pclk:[R] | lvds_pclk:[R] | 7.143 | 0.000 | 4.038 |
5 | 3.079 | u_extr/ohcnt_0_s0/Q | u_extr/ohcnt_3_s0/D | lvds_pclk:[R] | lvds_pclk:[R] | 7.143 | 0.000 | 4.029 |
6 | 3.080 | u_extr/ohs_s0/Q | u_extr/mem_data_mem_data_0_4_s/ADB[4] | lvds_pclk:[R] | lvds_pclk:[R] | 7.143 | 0.000 | 4.028 |
7 | 3.100 | u_extr/ohs_s0/Q | u_extr/mem_data_mem_data_0_1_s/ADB[9] | lvds_pclk:[R] | lvds_pclk:[R] | 7.143 | 0.000 | 4.009 |
8 | 3.135 | u_b2p/u_b2p_inst/u_mid_fifo/rRPtrWsync_1_s0/Q | u_b2p/u_b2p_inst/u_mid_fifo/rFull_s0/D | byte_clk:[R] | byte_clk:[R] | 9.524 | 0.000 | 6.354 |
9 | 3.137 | u_extr/ohs_s0/Q | u_extr/mem_data_mem_data_0_11_s/ADB[9] | lvds_pclk:[R] | lvds_pclk:[R] | 7.143 | 0.000 | 3.971 |
10 | 3.148 | u_extr/ohs_s0/Q | u_extr/mem_data_mem_data_0_0_s/ADB[4] | lvds_pclk:[R] | lvds_pclk:[R] | 7.143 | 0.000 | 3.960 |
11 | 3.168 | u_extr/ohs_s0/Q | u_extr/mem_data_mem_data_0_8_s/ADB[4] | lvds_pclk:[R] | lvds_pclk:[R] | 7.143 | 0.000 | 3.940 |
12 | 3.175 | u_extr/mem_data_mem_data_0_0_s/DO[0] | u_extr/mem_rqout_r_0_s0/D | lvds_pclk:[R] | lvds_pclk:[R] | 7.143 | 0.000 | 3.932 |
13 | 3.175 | u_extr/mem_data_mem_data_0_0_s/DO[1] | u_extr/mem_rqout_r_1_s0/D | lvds_pclk:[R] | lvds_pclk:[R] | 7.143 | 0.000 | 3.932 |
14 | 3.176 | u_extr/ohs_s0/Q | u_extr/mem_data_mem_data_0_11_s/ADB[4] | lvds_pclk:[R] | lvds_pclk:[R] | 7.143 | 0.000 | 3.932 |
15 | 3.176 | u_extr/ohs_s0/Q | u_extr/mem_data_mem_data_0_4_s/ADB[9] | lvds_pclk:[R] | lvds_pclk:[R] | 7.143 | 0.000 | 3.932 |
16 | 3.197 | u_extr/buf_ra_0_s0/Q | u_extr/mem_data_mem_data_0_4_s/ADB[10] | lvds_pclk:[R] | lvds_pclk:[R] | 7.143 | 0.000 | 3.911 |
17 | 3.197 | u_extr/buf_ra_0_s0/Q | u_extr/mem_data_mem_data_0_1_s/ADB[10] | lvds_pclk:[R] | lvds_pclk:[R] | 7.143 | 0.000 | 3.911 |
18 | 3.201 | u_extr/ohs_s0/Q | u_extr/mem_data_mem_data_0_3_s/ADB[4] | lvds_pclk:[R] | lvds_pclk:[R] | 7.143 | 0.000 | 3.907 |
19 | 3.204 | u_extr/ohs_s0/Q | u_extr/mem_data_mem_data_0_1_s/ADB[4] | lvds_pclk:[R] | lvds_pclk:[R] | 7.143 | 0.000 | 3.904 |
20 | 3.215 | u_extr/ohs_s0/Q | u_extr/mem_data_mem_data_0_4_s/ADB[11] | lvds_pclk:[R] | lvds_pclk:[R] | 7.143 | 0.000 | 3.894 |
21 | 3.215 | u_extr/ohs_s0/Q | u_extr/mem_data_mem_data_0_1_s/ADB[11] | lvds_pclk:[R] | lvds_pclk:[R] | 7.143 | 0.000 | 3.894 |
22 | 3.218 | u_extr/buf_ra_0_s0/Q | u_extr/mem_data_mem_data_0_0_s/ADB[10] | lvds_pclk:[R] | lvds_pclk:[R] | 7.143 | 0.000 | 3.891 |
23 | 3.234 | u_extr/ohs_s0/Q | u_extr/mem_data_mem_data_0_11_s/ADB[11] | lvds_pclk:[R] | lvds_pclk:[R] | 7.143 | 0.000 | 3.875 |
24 | 3.252 | u_extr/mem_data_mem_data_0_4_s/DO[1] | u_extr/mem_rqout_r_9_s0/D | lvds_pclk:[R] | lvds_pclk:[R] | 7.143 | 0.000 | 3.856 |
25 | 3.253 | u_extr/ohs_s0/Q | u_extr/mem_data_mem_data_0_4_s/ADB[8] | lvds_pclk:[R] | lvds_pclk:[R] | 7.143 | 0.000 | 3.855 |
Hold Paths Table
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 0.198 | u_extr/buf_wd_4_s0/Q | u_extr/mem_data_mem_data_0_2_s/DI[0] | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.000 | 0.447 |
2 | 0.215 | u_extr/buf_wa_9_s0/Q | u_extr/mem_data_mem_data_0_5_s/ADA[10] | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.000 | 0.333 |
3 | 0.225 | u_extr/buf_wd_11_s0/Q | u_extr/mem_data_mem_data_0_5_s/DI[1] | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.000 | 0.474 |
4 | 0.225 | u_extr/buf_wd_5_s0/Q | u_extr/mem_data_mem_data_0_2_s/DI[1] | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.000 | 0.474 |
5 | 0.318 | u_b2p/u_b2p_inst/u_mid_fifo/rRstRsync_s0/Q | u_b2p/u_b2p_inst/u_mid_fifo/rRdRst_s0/CE | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.000 | 0.329 |
6 | 0.318 | u_b2p/u_b2p_inst/u_mid_fifo/rRstWsync_s0/Q | u_b2p/u_b2p_inst/u_mid_fifo/rWrRst_s0/CE | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.329 |
7 | 0.323 | u_b2p/u_b2p_inst/mid_dv_s0/Q | u_b2p/u_b2p_inst/rBufD_22_s1/CE | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.334 |
8 | 0.323 | u_b2p/u_b2p_inst/mid_dv_s0/Q | u_b2p/u_b2p_inst/rBufD_28_s1/CE | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.334 |
9 | 0.326 | u_b2p/u_b2p_inst/u_align_forward/de_wor_r_s0/Q | u_b2p/u_b2p_inst/u_align_forward/data_o_reg_3_s0/CE | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.337 |
10 | 0.326 | u_b2p/u_b2p_inst/u_align_forward/de_wor_r_s0/Q | u_b2p/u_b2p_inst/u_align_forward/data_o_reg_8_s0/CE | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.337 |
11 | 0.326 | u_b2p/u_b2p_inst/u_align_forward/de_wor_r_s0/Q | u_b2p/u_b2p_inst/u_align_forward/data_o_reg_10_s0/CE | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.337 |
12 | 0.326 | u_b2p/u_b2p_inst/u_align_forward/de_wor_r_s0/Q | u_b2p/u_b2p_inst/u_align_forward/data_o_reg_16_s0/CE | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.337 |
13 | 0.326 | u_b2p/u_b2p_inst/u_align_forward/de_wor_r_s0/Q | u_b2p/u_b2p_inst/u_align_forward/data_o_reg_18_s0/CE | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.337 |
14 | 0.326 | u_b2p/u_b2p_inst/u_align_forward/de_wor_r_s0/Q | u_b2p/u_b2p_inst/u_align_forward/data_o_reg_26_s0/CE | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.337 |
15 | 0.329 | u_b2p/u_b2p_inst/u_align_forward/de_wor_r_s0/Q | u_b2p/u_b2p_inst/u_align_forward/data_o_reg_1_s0/CE | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.340 |
16 | 0.329 | u_b2p/u_b2p_inst/u_align_forward/de_wor_r_s0/Q | u_b2p/u_b2p_inst/u_align_forward/data_o_reg_9_s0/CE | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.340 |
17 | 0.329 | u_b2p/u_b2p_inst/u_align_forward/de_wor_r_s0/Q | u_b2p/u_b2p_inst/u_align_forward/data_o_reg_17_s0/CE | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.340 |
18 | 0.329 | u_b2p/u_b2p_inst/u_align_forward/de_wor_r_s0/Q | u_b2p/u_b2p_inst/u_align_forward/data_o_reg_25_s0/CE | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.340 |
19 | 0.332 | u_dsi_rx/u_dsi_csi2/rDataEn_s0/Q | u_dsi_rx/u_dsi_csi2/rDataReg_13_s0/CE | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.343 |
20 | 0.332 | u_b2p/u_b2p_inst/u_align_forward/de_wor_r_s0/Q | u_b2p/u_b2p_inst/u_align_forward/data_o_reg_0_s0/CE | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.343 |
21 | 0.335 | u_extr/iworking_s1/Q | u_extr/buf_wd_9_s0/RESET | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.000 | 0.346 |
22 | 0.335 | u_extr/iworking_s1/Q | u_extr/buf_wd_10_s0/RESET | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.000 | 0.346 |
23 | 0.335 | u_extr/iworking_s1/Q | u_extr/buf_wd_11_s0/RESET | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.000 | 0.346 |
24 | 0.335 | u_extr/iworking_s1/Q | u_extr/buf_wd_12_s0/RESET | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.000 | 0.346 |
25 | 0.337 | u_extr/buf_wa_1_s0/Q | u_extr/mem_data_mem_data_0_5_s/ADA[2] | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.000 | 0.455 |
Recovery Paths Table
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 7.192 | hsrx_en_s0/Q | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_cnt_0_s1/CLEAR | byte_clk:[R] | byte_clk:[R] | 9.524 | 0.000 | 2.297 |
2 | 7.192 | hsrx_en_s0/Q | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_cnt_1_s1/CLEAR | byte_clk:[R] | byte_clk:[R] | 9.524 | 0.000 | 2.297 |
3 | 7.192 | hsrx_en_s0/Q | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_cnt_0_s1/CLEAR | byte_clk:[R] | byte_clk:[R] | 9.524 | 0.000 | 2.297 |
4 | 7.192 | hsrx_en_s0/Q | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_cnt_1_s1/CLEAR | byte_clk:[R] | byte_clk:[R] | 9.524 | 0.000 | 2.297 |
5 | 7.192 | hsrx_en_s0/Q | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane1_cnt_0_s1/CLEAR | byte_clk:[R] | byte_clk:[R] | 9.524 | 0.000 | 2.297 |
6 | 7.192 | hsrx_en_s0/Q | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane1_cnt_1_s1/CLEAR | byte_clk:[R] | byte_clk:[R] | 9.524 | 0.000 | 2.297 |
7 | 7.192 | hsrx_en_s0/Q | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane0_cnt_0_s1/CLEAR | byte_clk:[R] | byte_clk:[R] | 9.524 | 0.000 | 2.297 |
8 | 7.192 | hsrx_en_s0/Q | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane0_cnt_1_s1/CLEAR | byte_clk:[R] | byte_clk:[R] | 9.524 | 0.000 | 2.297 |
9 | 7.192 | hsrx_en_s0/Q | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/q_in0_0_7_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 9.524 | 0.000 | 2.297 |
10 | 7.192 | hsrx_en_s0/Q | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_align_data_0_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 9.524 | 0.000 | 2.297 |
11 | 7.192 | hsrx_en_s0/Q | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_align_data_1_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 9.524 | 0.000 | 2.297 |
12 | 7.192 | hsrx_en_s0/Q | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_align_data_2_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 9.524 | 0.000 | 2.297 |
13 | 7.192 | hsrx_en_s0/Q | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_align_data_3_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 9.524 | 0.000 | 2.297 |
14 | 7.192 | hsrx_en_s0/Q | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_align_data_4_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 9.524 | 0.000 | 2.297 |
15 | 7.192 | hsrx_en_s0/Q | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_align_data_5_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 9.524 | 0.000 | 2.297 |
16 | 7.192 | hsrx_en_s0/Q | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_align_data_6_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 9.524 | 0.000 | 2.297 |
17 | 7.192 | hsrx_en_s0/Q | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_align_data_7_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 9.524 | 0.000 | 2.297 |
18 | 7.192 | hsrx_en_s0/Q | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_align_data_0_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 9.524 | 0.000 | 2.297 |
19 | 7.192 | hsrx_en_s0/Q | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_align_data_1_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 9.524 | 0.000 | 2.297 |
20 | 7.192 | hsrx_en_s0/Q | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_align_data_2_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 9.524 | 0.000 | 2.297 |
21 | 7.192 | hsrx_en_s0/Q | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_align_data_3_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 9.524 | 0.000 | 2.297 |
22 | 7.192 | hsrx_en_s0/Q | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_align_data_4_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 9.524 | 0.000 | 2.297 |
23 | 7.192 | hsrx_en_s0/Q | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_align_data_5_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 9.524 | 0.000 | 2.297 |
24 | 7.192 | hsrx_en_s0/Q | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_align_data_6_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 9.524 | 0.000 | 2.297 |
25 | 7.192 | hsrx_en_s0/Q | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_align_data_7_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 9.524 | 0.000 | 2.297 |
Removal Paths Table
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 1.581 | hsrx_en_s0/Q | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_cnt_0_s1/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 1.592 |
2 | 1.581 | hsrx_en_s0/Q | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_cnt_1_s1/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 1.592 |
3 | 1.581 | hsrx_en_s0/Q | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_cnt_0_s1/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 1.592 |
4 | 1.581 | hsrx_en_s0/Q | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_cnt_1_s1/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 1.592 |
5 | 1.581 | hsrx_en_s0/Q | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane1_cnt_0_s1/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 1.592 |
6 | 1.581 | hsrx_en_s0/Q | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane1_cnt_1_s1/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 1.592 |
7 | 1.581 | hsrx_en_s0/Q | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane0_cnt_0_s1/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 1.592 |
8 | 1.581 | hsrx_en_s0/Q | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane0_cnt_1_s1/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 1.592 |
9 | 1.581 | hsrx_en_s0/Q | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/q_in0_0_7_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 1.592 |
10 | 1.581 | hsrx_en_s0/Q | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_align_data_0_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 1.592 |
11 | 1.581 | hsrx_en_s0/Q | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_align_data_1_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 1.592 |
12 | 1.581 | hsrx_en_s0/Q | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_align_data_2_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 1.592 |
13 | 1.581 | hsrx_en_s0/Q | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_align_data_3_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 1.592 |
14 | 1.581 | hsrx_en_s0/Q | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_align_data_4_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 1.592 |
15 | 1.581 | hsrx_en_s0/Q | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_align_data_5_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 1.592 |
16 | 1.581 | hsrx_en_s0/Q | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_align_data_6_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 1.592 |
17 | 1.581 | hsrx_en_s0/Q | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_align_data_7_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 1.592 |
18 | 1.581 | hsrx_en_s0/Q | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_align_data_0_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 1.592 |
19 | 1.581 | hsrx_en_s0/Q | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_align_data_1_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 1.592 |
20 | 1.581 | hsrx_en_s0/Q | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_align_data_2_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 1.592 |
21 | 1.581 | hsrx_en_s0/Q | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_align_data_3_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 1.592 |
22 | 1.581 | hsrx_en_s0/Q | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_align_data_4_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 1.592 |
23 | 1.581 | hsrx_en_s0/Q | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_align_data_5_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 1.592 |
24 | 1.581 | hsrx_en_s0/Q | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_align_data_6_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 1.592 |
25 | 1.581 | hsrx_en_s0/Q | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_align_data_7_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 1.592 |
Minimum Pulse Width Table:
Number | Slack | Actual Width | Required Width | Type | Clock | Objects |
---|---|---|---|---|---|---|
1 | 1.808 | 2.808 | 1.000 | Low Pulse Width | lvds_pclk | u_extr/mem_rqout_r_23_s0 |
2 | 1.808 | 2.808 | 1.000 | Low Pulse Width | lvds_pclk | u_extr/mem_rqout_r_21_s0 |
3 | 1.808 | 2.808 | 1.000 | Low Pulse Width | lvds_pclk | u_extr/mem_rqout_r_17_s0 |
4 | 1.808 | 2.808 | 1.000 | Low Pulse Width | lvds_pclk | u_extr/mem_rqout_r_9_s0 |
5 | 1.808 | 2.808 | 1.000 | Low Pulse Width | lvds_pclk | u_extr/ohcnt_9_s0 |
6 | 1.808 | 2.808 | 1.000 | Low Pulse Width | lvds_pclk | u_extr/o_rgb_reg_21_s0 |
7 | 1.808 | 2.808 | 1.000 | Low Pulse Width | lvds_pclk | u_extr/o_rgb_reg_22_s0 |
8 | 1.808 | 2.808 | 1.000 | Low Pulse Width | lvds_pclk | u_extr/ohcnt_10_s0 |
9 | 1.808 | 2.808 | 1.000 | Low Pulse Width | lvds_pclk | u_extr/o_rgb_reg_23_s0 |
10 | 1.808 | 2.808 | 1.000 | Low Pulse Width | lvds_pclk | u_extr/o_de_reg_s0 |
Timing Report By Analysis Type:
Setup Analysis Report
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 0.761 |
Data Arrival Time | 7.543 |
Data Required Time | 8.303 |
From | u_mipi_dphy/DPHY_RX_INST/u_idesx8/opensync_0_s0 |
To | u_mipi_dphy/DPHY_RX_INST/u_idesx8/u_DHCEN |
Launch Clk | mipi_clk:[R] |
Latch Clk | mipi_clk:[F] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | mipi_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT24 | u_mipi_dphy/DPHY_RX_INST/U0_IB/I |
2.601 | 2.601 | tINS | RR | 5 | IOT24 | u_mipi_dphy/DPHY_RX_INST/U0_IB/O |
5.382 | 2.782 | tNET | RR | 1 | R17C25[1][A] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/opensync_0_s0/CLK |
5.614 | 0.232 | tC2Q | RF | 3 | R17C25[1][A] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/opensync_0_s0/Q |
6.575 | 0.960 | tNET | FF | 1 | R2C27[0][A] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/LUT4_0/I3 |
7.130 | 0.555 | tINS | FF | 1 | R2C27[0][A] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/LUT4_0/F |
7.543 | 0.413 | tNET | FF | 1 | - | u_mipi_dphy/DPHY_RX_INST/u_idesx8/u_DHCEN/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.000 | 6.000 | active clock edge time | ||||
6.000 | 0.000 | mipi_clk | ||||
6.000 | 0.000 | tCL | FF | 1 | IOT24 | u_mipi_dphy/DPHY_RX_INST/U0_IB/I |
8.489 | 2.489 | tINS | FF | 5 | IOT24 | u_mipi_dphy/DPHY_RX_INST/U0_IB/O |
8.489 | 0.000 | tNET | FF | 3 | - | u_mipi_dphy/DPHY_RX_INST/u_idesx8/u_DHCEN/CLKIN |
8.303 | -0.186 | tSu | 1 | - | u_mipi_dphy/DPHY_RX_INST/u_idesx8/u_DHCEN |
Path Statistics:
Clock Skew | -2.893 |
Setup Relationship | 6.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 2.601, 48.321%; route: 2.782, 51.679% |
Arrival Data Path Delay | cell: 0.555, 25.688%; route: 1.374, 63.574%; tC2Q: 0.232, 10.738% |
Required Clock Path Delay | cell: 2.489, 100.000%; route: 0.000, 0.000% |
Path2
Path Summary:
Slack | 2.949 |
Data Arrival Time | 6.431 |
Data Required Time | 9.379 |
From | u_b2p/u_b2p_inst/u_mid_fifo/rWPtrRsync_4_s0 |
To | u_b2p/u_b2p_inst/u_mid_fifo/rEmpty_s0 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 214 | PLL_L[0] | u_pll_1/rpll_inst/CLKOUT |
2.271 | 2.271 | tNET | RR | 1 | R39C23[1][A] | u_b2p/u_b2p_inst/u_mid_fifo/rWPtrRsync_4_s0/CLK |
2.503 | 0.232 | tC2Q | RF | 7 | R39C23[1][A] | u_b2p/u_b2p_inst/u_mid_fifo/rWPtrRsync_4_s0/Q |
3.191 | 0.688 | tNET | FF | 1 | R35C25[1][B] | u_b2p/u_b2p_inst/u_mid_fifo/wWPtrBinX_1_s1/I3 |
3.740 | 0.549 | tINS | FR | 4 | R35C25[1][B] | u_b2p/u_b2p_inst/u_mid_fifo/wWPtrBinX_1_s1/F |
3.916 | 0.175 | tNET | RR | 1 | R36C25[3][B] | u_b2p/u_b2p_inst/u_mid_fifo/wWPtrBinX_0_s0/I1 |
4.465 | 0.549 | tINS | RR | 2 | R36C25[3][B] | u_b2p/u_b2p_inst/u_mid_fifo/wWPtrBinX_0_s0/F |
4.638 | 0.174 | tNET | RR | 2 | R36C26[0][A] | u_b2p/u_b2p_inst/u_mid_fifo/n324_s0/I0 |
5.187 | 0.549 | tINS | RR | 1 | R36C26[0][A] | u_b2p/u_b2p_inst/u_mid_fifo/n324_s0/COUT |
5.187 | 0.000 | tNET | RR | 2 | R36C26[0][B] | u_b2p/u_b2p_inst/u_mid_fifo/n325_s0/CIN |
5.223 | 0.035 | tINS | RF | 1 | R36C26[0][B] | u_b2p/u_b2p_inst/u_mid_fifo/n325_s0/COUT |
5.223 | 0.000 | tNET | FF | 2 | R36C26[1][A] | u_b2p/u_b2p_inst/u_mid_fifo/n326_s0/CIN |
5.258 | 0.035 | tINS | FF | 1 | R36C26[1][A] | u_b2p/u_b2p_inst/u_mid_fifo/n326_s0/COUT |
5.258 | 0.000 | tNET | FF | 2 | R36C26[1][B] | u_b2p/u_b2p_inst/u_mid_fifo/n327_s0/CIN |
5.293 | 0.035 | tINS | FF | 1 | R36C26[1][B] | u_b2p/u_b2p_inst/u_mid_fifo/n327_s0/COUT |
5.293 | 0.000 | tNET | FF | 2 | R36C26[2][A] | u_b2p/u_b2p_inst/u_mid_fifo/n328_s0/CIN |
5.328 | 0.035 | tINS | FF | 1 | R36C26[2][A] | u_b2p/u_b2p_inst/u_mid_fifo/n328_s0/COUT |
5.969 | 0.640 | tNET | FF | 1 | R36C27[0][A] | u_b2p/u_b2p_inst/u_mid_fifo/n330_s0/I3 |
6.431 | 0.462 | tINS | FR | 1 | R36C27[0][A] | u_b2p/u_b2p_inst/u_mid_fifo/n330_s0/F |
6.431 | 0.000 | tNET | RR | 1 | R36C27[0][A] | u_b2p/u_b2p_inst/u_mid_fifo/rEmpty_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | pixel_clk | ||||
7.143 | 0.000 | tCL | RR | 214 | PLL_L[0] | u_pll_1/rpll_inst/CLKOUT |
9.414 | 2.271 | tNET | RR | 1 | R36C27[0][A] | u_b2p/u_b2p_inst/u_mid_fifo/rEmpty_s0/CLK |
9.379 | -0.035 | tSu | 1 | R36C27[0][A] | u_b2p/u_b2p_inst/u_mid_fifo/rEmpty_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 7.143 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 2.250, 54.091%; route: 1.677, 40.331%; tC2Q: 0.232, 5.578% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path3
Path Summary:
Slack | 3.035 |
Data Arrival Time | 6.344 |
Data Required Time | 9.379 |
From | u_extr/ohcnt_0_s0 |
To | u_extr/ohcnt_0_s0 |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 120 | RIGHTSIDE[0] | u_clk_div_3p5/CLKOUT |
2.271 | 2.271 | tNET | RR | 1 | R30C38[1][A] | u_extr/ohcnt_0_s0/CLK |
2.503 | 0.232 | tC2Q | RF | 6 | R30C38[1][A] | u_extr/ohcnt_0_s0/Q |
3.182 | 0.679 | tNET | FF | 1 | R33C39[2][A] | u_extr/n737_s2/I0 |
3.635 | 0.453 | tINS | FF | 8 | R33C39[2][A] | u_extr/n737_s2/F |
3.897 | 0.262 | tNET | FF | 1 | R33C37[1][B] | u_extr/n860_s4/I0 |
4.350 | 0.453 | tINS | FF | 4 | R33C37[1][B] | u_extr/n860_s4/F |
4.538 | 0.188 | tNET | FF | 1 | R34C37[1][A] | u_extr/n741_s3/I0 |
5.093 | 0.555 | tINS | FF | 11 | R34C37[1][A] | u_extr/n741_s3/F |
5.774 | 0.681 | tNET | FF | 1 | R30C38[1][A] | u_extr/n741_s2/I1 |
6.344 | 0.570 | tINS | FR | 1 | R30C38[1][A] | u_extr/n741_s2/F |
6.344 | 0.000 | tNET | RR | 1 | R30C38[1][A] | u_extr/ohcnt_0_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | lvds_pclk | ||||
7.143 | 0.000 | tCL | RR | 120 | RIGHTSIDE[0] | u_clk_div_3p5/CLKOUT |
9.414 | 2.271 | tNET | RR | 1 | R30C38[1][A] | u_extr/ohcnt_0_s0/CLK |
9.379 | -0.035 | tSu | 1 | R30C38[1][A] | u_extr/ohcnt_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 7.143 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 2.031, 49.872%; route: 1.809, 44.432%; tC2Q: 0.232, 5.697% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path4
Path Summary:
Slack | 3.069 |
Data Arrival Time | 6.310 |
Data Required Time | 9.379 |
From | u_extr/ovcnt_1_s1 |
To | u_extr/ohs_s0 |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 120 | RIGHTSIDE[0] | u_clk_div_3p5/CLKOUT |
2.271 | 2.271 | tNET | RR | 1 | R38C38[1][A] | u_extr/ovcnt_1_s1/CLK |
2.503 | 0.232 | tC2Q | RF | 6 | R38C38[1][A] | u_extr/ovcnt_1_s1/Q |
2.701 | 0.197 | tNET | FF | 1 | R38C39[1][B] | u_extr/n785_s3/I3 |
3.256 | 0.555 | tINS | FF | 8 | R38C39[1][B] | u_extr/n785_s3/F |
3.939 | 0.684 | tNET | FF | 1 | R35C38[2][B] | u_extr/n778_s3/I0 |
4.494 | 0.555 | tINS | FF | 2 | R35C38[2][B] | u_extr/n778_s3/F |
4.896 | 0.401 | tNET | FF | 1 | R35C39[2][B] | u_extr/n840_s4/I2 |
5.451 | 0.555 | tINS | FF | 1 | R35C39[2][B] | u_extr/n840_s4/F |
5.848 | 0.397 | tNET | FF | 1 | R33C39[1][A] | u_extr/n840_s1/I3 |
6.310 | 0.462 | tINS | FR | 1 | R33C39[1][A] | u_extr/n840_s1/F |
6.310 | 0.000 | tNET | RR | 1 | R33C39[1][A] | u_extr/ohs_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | lvds_pclk | ||||
7.143 | 0.000 | tCL | RR | 120 | RIGHTSIDE[0] | u_clk_div_3p5/CLKOUT |
9.414 | 2.271 | tNET | RR | 1 | R33C39[1][A] | u_extr/ohs_s0/CLK |
9.379 | -0.035 | tSu | 1 | R33C39[1][A] | u_extr/ohs_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 7.143 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 2.127, 52.669%; route: 1.679, 41.586%; tC2Q: 0.232, 5.745% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path5
Path Summary:
Slack | 3.079 |
Data Arrival Time | 6.300 |
Data Required Time | 9.379 |
From | u_extr/ohcnt_0_s0 |
To | u_extr/ohcnt_3_s0 |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 120 | RIGHTSIDE[0] | u_clk_div_3p5/CLKOUT |
2.271 | 2.271 | tNET | RR | 1 | R30C38[1][A] | u_extr/ohcnt_0_s0/CLK |
2.503 | 0.232 | tC2Q | RF | 6 | R30C38[1][A] | u_extr/ohcnt_0_s0/Q |
3.182 | 0.679 | tNET | FF | 1 | R33C39[2][A] | u_extr/n737_s2/I0 |
3.635 | 0.453 | tINS | FF | 8 | R33C39[2][A] | u_extr/n737_s2/F |
3.897 | 0.262 | tNET | FF | 1 | R33C37[1][B] | u_extr/n860_s4/I0 |
4.350 | 0.453 | tINS | FF | 4 | R33C37[1][B] | u_extr/n860_s4/F |
4.538 | 0.188 | tNET | FF | 1 | R34C37[1][A] | u_extr/n741_s3/I0 |
5.093 | 0.555 | tINS | FF | 11 | R34C37[1][A] | u_extr/n741_s3/F |
5.751 | 0.659 | tNET | FF | 1 | R33C39[0][B] | u_extr/n738_s1/I3 |
6.300 | 0.549 | tINS | FR | 1 | R33C39[0][B] | u_extr/n738_s1/F |
6.300 | 0.000 | tNET | RR | 1 | R33C39[0][B] | u_extr/ohcnt_3_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | lvds_pclk | ||||
7.143 | 0.000 | tCL | RR | 120 | RIGHTSIDE[0] | u_clk_div_3p5/CLKOUT |
9.414 | 2.271 | tNET | RR | 1 | R33C39[0][B] | u_extr/ohcnt_3_s0/CLK |
9.379 | -0.035 | tSu | 1 | R33C39[0][B] | u_extr/ohcnt_3_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 7.143 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 2.010, 49.888%; route: 1.787, 44.354%; tC2Q: 0.232, 5.758% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path6
Path Summary:
Slack | 3.080 |
Data Arrival Time | 6.299 |
Data Required Time | 9.380 |
From | u_extr/ohs_s0 |
To | u_extr/mem_data_mem_data_0_4_s |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 120 | RIGHTSIDE[0] | u_clk_div_3p5/CLKOUT |
2.271 | 2.271 | tNET | RR | 1 | R33C39[1][A] | u_extr/ohs_s0/CLK |
2.503 | 0.232 | tC2Q | RF | 4 | R33C39[1][A] | u_extr/ohs_s0/Q |
3.411 | 0.907 | tNET | FF | 1 | R30C36[3][A] | u_extr/n868_s1/I0 |
3.928 | 0.517 | tINS | FF | 20 | R30C36[3][A] | u_extr/n868_s1/F |
4.595 | 0.667 | tNET | FF | 1 | R31C35[1][B] | u_extr/buf_ra_c_3_s0/I1 |
4.966 | 0.371 | tINS | FF | 12 | R31C35[1][B] | u_extr/buf_ra_c_3_s0/F |
6.299 | 1.333 | tNET | FF | 1 | BSRAM_R10[10] | u_extr/mem_data_mem_data_0_4_s/ADB[4] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | lvds_pclk | ||||
7.143 | 0.000 | tCL | RR | 120 | RIGHTSIDE[0] | u_clk_div_3p5/CLKOUT |
9.414 | 2.271 | tNET | RR | 1 | BSRAM_R10[10] | u_extr/mem_data_mem_data_0_4_s/CLKB |
9.380 | -0.035 | tSu | 1 | BSRAM_R10[10] | u_extr/mem_data_mem_data_0_4_s |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 7.143 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 0.888, 22.046%; route: 2.908, 72.194%; tC2Q: 0.232, 5.760% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path7
Path Summary:
Slack | 3.100 |
Data Arrival Time | 6.280 |
Data Required Time | 9.380 |
From | u_extr/ohs_s0 |
To | u_extr/mem_data_mem_data_0_1_s |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 120 | RIGHTSIDE[0] | u_clk_div_3p5/CLKOUT |
2.271 | 2.271 | tNET | RR | 1 | R33C39[1][A] | u_extr/ohs_s0/CLK |
2.503 | 0.232 | tC2Q | RF | 4 | R33C39[1][A] | u_extr/ohs_s0/Q |
3.411 | 0.907 | tNET | FF | 1 | R30C36[3][A] | u_extr/n868_s1/I0 |
3.928 | 0.517 | tINS | FF | 20 | R30C36[3][A] | u_extr/n868_s1/F |
4.468 | 0.540 | tNET | FF | 1 | R33C36[3][A] | u_extr/buf_ra_c_8_s0/I2 |
5.023 | 0.555 | tINS | FF | 12 | R33C36[3][A] | u_extr/buf_ra_c_8_s0/F |
6.280 | 1.257 | tNET | FF | 1 | BSRAM_R28[7] | u_extr/mem_data_mem_data_0_1_s/ADB[9] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | lvds_pclk | ||||
7.143 | 0.000 | tCL | RR | 120 | RIGHTSIDE[0] | u_clk_div_3p5/CLKOUT |
9.414 | 2.271 | tNET | RR | 1 | BSRAM_R28[7] | u_extr/mem_data_mem_data_0_1_s/CLKB |
9.380 | -0.035 | tSu | 1 | BSRAM_R28[7] | u_extr/mem_data_mem_data_0_1_s |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 7.143 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 1.072, 26.743%; route: 2.705, 67.470%; tC2Q: 0.232, 5.788% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path8
Path Summary:
Slack | 3.135 |
Data Arrival Time | 8.625 |
Data Required Time | 11.760 |
From | u_b2p/u_b2p_inst/u_mid_fifo/rRPtrWsync_1_s0 |
To | u_b2p/u_b2p_inst/u_mid_fifo/rFull_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
2.271 | 2.271 | tNET | RR | 1 | R31C24[0][B] | u_b2p/u_b2p_inst/u_mid_fifo/rRPtrWsync_1_s0/CLK |
2.503 | 0.232 | tC2Q | RF | 3 | R31C24[0][B] | u_b2p/u_b2p_inst/u_mid_fifo/rRPtrWsync_1_s0/Q |
3.161 | 0.658 | tNET | FF | 1 | R34C26[3][B] | u_b2p/u_b2p_inst/u_mid_fifo/wRPtrBinX_1_s1/I0 |
3.623 | 0.462 | tINS | FR | 2 | R34C26[3][B] | u_b2p/u_b2p_inst/u_mid_fifo/wRPtrBinX_1_s1/F |
3.626 | 0.003 | tNET | RR | 1 | R34C26[3][A] | u_b2p/u_b2p_inst/u_mid_fifo/wRPtrBinX_0_s0/I1 |
4.143 | 0.517 | tINS | RF | 1 | R34C26[3][A] | u_b2p/u_b2p_inst/u_mid_fifo/wRPtrBinX_0_s0/F |
5.025 | 0.882 | tNET | FF | 2 | R35C26[0][B] | u_b2p/u_b2p_inst/u_mid_fifo/n343_s0/I1 |
5.595 | 0.570 | tINS | FR | 1 | R35C26[0][B] | u_b2p/u_b2p_inst/u_mid_fifo/n343_s0/COUT |
5.595 | 0.000 | tNET | RR | 2 | R35C26[1][A] | u_b2p/u_b2p_inst/u_mid_fifo/n344_s0/CIN |
5.631 | 0.035 | tINS | RF | 1 | R35C26[1][A] | u_b2p/u_b2p_inst/u_mid_fifo/n344_s0/COUT |
5.631 | 0.000 | tNET | FF | 2 | R35C26[1][B] | u_b2p/u_b2p_inst/u_mid_fifo/n345_s0/CIN |
5.666 | 0.035 | tINS | FF | 1 | R35C26[1][B] | u_b2p/u_b2p_inst/u_mid_fifo/n345_s0/COUT |
5.666 | 0.000 | tNET | FF | 2 | R35C26[2][A] | u_b2p/u_b2p_inst/u_mid_fifo/n346_s0/CIN |
5.701 | 0.035 | tINS | FF | 1 | R35C26[2][A] | u_b2p/u_b2p_inst/u_mid_fifo/n346_s0/COUT |
6.827 | 1.126 | tNET | FF | 1 | R38C26[2][A] | u_b2p/u_b2p_inst/u_mid_fifo/n358_s3/I0 |
7.198 | 0.371 | tINS | FF | 1 | R38C26[2][A] | u_b2p/u_b2p_inst/u_mid_fifo/n358_s3/F |
8.076 | 0.878 | tNET | FF | 1 | R38C26[2][B] | u_b2p/u_b2p_inst/u_mid_fifo/n358_s0/I3 |
8.625 | 0.549 | tINS | FR | 1 | R38C26[2][B] | u_b2p/u_b2p_inst/u_mid_fifo/n358_s0/F |
8.625 | 0.000 | tNET | RR | 1 | R38C26[2][B] | u_b2p/u_b2p_inst/u_mid_fifo/rFull_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.524 | 9.524 | active clock edge time | ||||
9.524 | 0.000 | byte_clk | ||||
9.524 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
11.795 | 2.271 | tNET | RR | 1 | R38C26[2][B] | u_b2p/u_b2p_inst/u_mid_fifo/rFull_s0/CLK |
11.760 | -0.035 | tSu | 1 | R38C26[2][B] | u_b2p/u_b2p_inst/u_mid_fifo/rFull_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 9.524 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 2.575, 40.520%; route: 3.547, 55.829%; tC2Q: 0.232, 3.651% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path9
Path Summary:
Slack | 3.137 |
Data Arrival Time | 6.243 |
Data Required Time | 9.380 |
From | u_extr/ohs_s0 |
To | u_extr/mem_data_mem_data_0_11_s |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 120 | RIGHTSIDE[0] | u_clk_div_3p5/CLKOUT |
2.271 | 2.271 | tNET | RR | 1 | R33C39[1][A] | u_extr/ohs_s0/CLK |
2.503 | 0.232 | tC2Q | RF | 4 | R33C39[1][A] | u_extr/ohs_s0/Q |
3.411 | 0.907 | tNET | FF | 1 | R30C36[3][A] | u_extr/n868_s1/I0 |
3.928 | 0.517 | tINS | FF | 20 | R30C36[3][A] | u_extr/n868_s1/F |
4.468 | 0.540 | tNET | FF | 1 | R33C36[3][A] | u_extr/buf_ra_c_8_s0/I2 |
5.023 | 0.555 | tINS | FF | 12 | R33C36[3][A] | u_extr/buf_ra_c_8_s0/F |
6.243 | 1.220 | tNET | FF | 1 | BSRAM_R28[13] | u_extr/mem_data_mem_data_0_11_s/ADB[9] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | lvds_pclk | ||||
7.143 | 0.000 | tCL | RR | 120 | RIGHTSIDE[0] | u_clk_div_3p5/CLKOUT |
9.414 | 2.271 | tNET | RR | 1 | BSRAM_R28[13] | u_extr/mem_data_mem_data_0_11_s/CLKB |
9.380 | -0.035 | tSu | 1 | BSRAM_R28[13] | u_extr/mem_data_mem_data_0_11_s |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 7.143 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 1.072, 26.993%; route: 2.667, 67.165%; tC2Q: 0.232, 5.842% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path10
Path Summary:
Slack | 3.148 |
Data Arrival Time | 6.232 |
Data Required Time | 9.380 |
From | u_extr/ohs_s0 |
To | u_extr/mem_data_mem_data_0_0_s |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 120 | RIGHTSIDE[0] | u_clk_div_3p5/CLKOUT |
2.271 | 2.271 | tNET | RR | 1 | R33C39[1][A] | u_extr/ohs_s0/CLK |
2.503 | 0.232 | tC2Q | RF | 4 | R33C39[1][A] | u_extr/ohs_s0/Q |
3.411 | 0.907 | tNET | FF | 1 | R30C36[3][A] | u_extr/n868_s1/I0 |
3.928 | 0.517 | tINS | FF | 20 | R30C36[3][A] | u_extr/n868_s1/F |
4.595 | 0.667 | tNET | FF | 1 | R31C35[1][B] | u_extr/buf_ra_c_3_s0/I1 |
4.966 | 0.371 | tINS | FF | 12 | R31C35[1][B] | u_extr/buf_ra_c_3_s0/F |
6.232 | 1.266 | tNET | FF | 1 | BSRAM_R28[6] | u_extr/mem_data_mem_data_0_0_s/ADB[4] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | lvds_pclk | ||||
7.143 | 0.000 | tCL | RR | 120 | RIGHTSIDE[0] | u_clk_div_3p5/CLKOUT |
9.414 | 2.271 | tNET | RR | 1 | BSRAM_R28[6] | u_extr/mem_data_mem_data_0_0_s/CLKB |
9.380 | -0.035 | tSu | 1 | BSRAM_R28[6] | u_extr/mem_data_mem_data_0_0_s |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 7.143 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 0.888, 22.423%; route: 2.840, 71.719%; tC2Q: 0.232, 5.858% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path11
Path Summary:
Slack | 3.168 |
Data Arrival Time | 6.211 |
Data Required Time | 9.380 |
From | u_extr/ohs_s0 |
To | u_extr/mem_data_mem_data_0_8_s |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 120 | RIGHTSIDE[0] | u_clk_div_3p5/CLKOUT |
2.271 | 2.271 | tNET | RR | 1 | R33C39[1][A] | u_extr/ohs_s0/CLK |
2.503 | 0.232 | tC2Q | RF | 4 | R33C39[1][A] | u_extr/ohs_s0/Q |
3.411 | 0.907 | tNET | FF | 1 | R30C36[3][A] | u_extr/n868_s1/I0 |
3.928 | 0.517 | tINS | FF | 20 | R30C36[3][A] | u_extr/n868_s1/F |
4.595 | 0.667 | tNET | FF | 1 | R31C35[1][B] | u_extr/buf_ra_c_3_s0/I1 |
4.966 | 0.371 | tINS | FF | 12 | R31C35[1][B] | u_extr/buf_ra_c_3_s0/F |
6.211 | 1.245 | tNET | FF | 1 | BSRAM_R46[11] | u_extr/mem_data_mem_data_0_8_s/ADB[4] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | lvds_pclk | ||||
7.143 | 0.000 | tCL | RR | 120 | RIGHTSIDE[0] | u_clk_div_3p5/CLKOUT |
9.414 | 2.271 | tNET | RR | 1 | BSRAM_R46[11] | u_extr/mem_data_mem_data_0_8_s/CLKB |
9.380 | -0.035 | tSu | 1 | BSRAM_R46[11] | u_extr/mem_data_mem_data_0_8_s |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 7.143 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 0.888, 22.538%; route: 2.820, 71.573%; tC2Q: 0.232, 5.888% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path12
Path Summary:
Slack | 3.175 |
Data Arrival Time | 6.204 |
Data Required Time | 9.379 |
From | u_extr/mem_data_mem_data_0_0_s |
To | u_extr/mem_rqout_r_0_s0 |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 120 | RIGHTSIDE[0] | u_clk_div_3p5/CLKOUT |
2.271 | 2.271 | tNET | RR | 2 | BSRAM_R28[6] | u_extr/mem_data_mem_data_0_0_s/CLKB |
4.531 | 2.260 | tC2Q | RF | 1 | BSRAM_R28[6] | u_extr/mem_data_mem_data_0_0_s/DO[0] |
6.204 | 1.672 | tNET | FF | 1 | R34C34[2][A] | u_extr/mem_rqout_r_0_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | lvds_pclk | ||||
7.143 | 0.000 | tCL | RR | 120 | RIGHTSIDE[0] | u_clk_div_3p5/CLKOUT |
9.414 | 2.271 | tNET | RR | 1 | R34C34[2][A] | u_extr/mem_rqout_r_0_s0/CLK |
9.379 | -0.035 | tSu | 1 | R34C34[2][A] | u_extr/mem_rqout_r_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 7.143 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.672, 42.529%; tC2Q: 2.260, 57.471% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path13
Path Summary:
Slack | 3.175 |
Data Arrival Time | 6.204 |
Data Required Time | 9.379 |
From | u_extr/mem_data_mem_data_0_0_s |
To | u_extr/mem_rqout_r_1_s0 |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 120 | RIGHTSIDE[0] | u_clk_div_3p5/CLKOUT |
2.271 | 2.271 | tNET | RR | 2 | BSRAM_R28[6] | u_extr/mem_data_mem_data_0_0_s/CLKB |
4.531 | 2.260 | tC2Q | RF | 1 | BSRAM_R28[6] | u_extr/mem_data_mem_data_0_0_s/DO[1] |
6.204 | 1.672 | tNET | FF | 1 | R34C34[2][B] | u_extr/mem_rqout_r_1_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | lvds_pclk | ||||
7.143 | 0.000 | tCL | RR | 120 | RIGHTSIDE[0] | u_clk_div_3p5/CLKOUT |
9.414 | 2.271 | tNET | RR | 1 | R34C34[2][B] | u_extr/mem_rqout_r_1_s0/CLK |
9.379 | -0.035 | tSu | 1 | R34C34[2][B] | u_extr/mem_rqout_r_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 7.143 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.672, 42.529%; tC2Q: 2.260, 57.471% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path14
Path Summary:
Slack | 3.176 |
Data Arrival Time | 6.203 |
Data Required Time | 9.380 |
From | u_extr/ohs_s0 |
To | u_extr/mem_data_mem_data_0_11_s |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 120 | RIGHTSIDE[0] | u_clk_div_3p5/CLKOUT |
2.271 | 2.271 | tNET | RR | 1 | R33C39[1][A] | u_extr/ohs_s0/CLK |
2.503 | 0.232 | tC2Q | RF | 4 | R33C39[1][A] | u_extr/ohs_s0/Q |
3.411 | 0.907 | tNET | FF | 1 | R30C36[3][A] | u_extr/n868_s1/I0 |
3.928 | 0.517 | tINS | FF | 20 | R30C36[3][A] | u_extr/n868_s1/F |
4.595 | 0.667 | tNET | FF | 1 | R31C35[1][B] | u_extr/buf_ra_c_3_s0/I1 |
4.966 | 0.371 | tINS | FF | 12 | R31C35[1][B] | u_extr/buf_ra_c_3_s0/F |
6.203 | 1.237 | tNET | FF | 1 | BSRAM_R28[13] | u_extr/mem_data_mem_data_0_11_s/ADB[4] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | lvds_pclk | ||||
7.143 | 0.000 | tCL | RR | 120 | RIGHTSIDE[0] | u_clk_div_3p5/CLKOUT |
9.414 | 2.271 | tNET | RR | 1 | BSRAM_R28[13] | u_extr/mem_data_mem_data_0_11_s/CLKB |
9.380 | -0.035 | tSu | 1 | BSRAM_R28[13] | u_extr/mem_data_mem_data_0_11_s |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 7.143 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 0.888, 22.583%; route: 2.812, 71.517%; tC2Q: 0.232, 5.900% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path15
Path Summary:
Slack | 3.176 |
Data Arrival Time | 6.203 |
Data Required Time | 9.380 |
From | u_extr/ohs_s0 |
To | u_extr/mem_data_mem_data_0_4_s |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 120 | RIGHTSIDE[0] | u_clk_div_3p5/CLKOUT |
2.271 | 2.271 | tNET | RR | 1 | R33C39[1][A] | u_extr/ohs_s0/CLK |
2.503 | 0.232 | tC2Q | RF | 4 | R33C39[1][A] | u_extr/ohs_s0/Q |
3.411 | 0.907 | tNET | FF | 1 | R30C36[3][A] | u_extr/n868_s1/I0 |
3.928 | 0.517 | tINS | FF | 20 | R30C36[3][A] | u_extr/n868_s1/F |
4.468 | 0.540 | tNET | FF | 1 | R33C36[3][A] | u_extr/buf_ra_c_8_s0/I2 |
5.023 | 0.555 | tINS | FF | 12 | R33C36[3][A] | u_extr/buf_ra_c_8_s0/F |
6.203 | 1.180 | tNET | FF | 1 | BSRAM_R10[10] | u_extr/mem_data_mem_data_0_4_s/ADB[9] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | lvds_pclk | ||||
7.143 | 0.000 | tCL | RR | 120 | RIGHTSIDE[0] | u_clk_div_3p5/CLKOUT |
9.414 | 2.271 | tNET | RR | 1 | BSRAM_R10[10] | u_extr/mem_data_mem_data_0_4_s/CLKB |
9.380 | -0.035 | tSu | 1 | BSRAM_R10[10] | u_extr/mem_data_mem_data_0_4_s |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 7.143 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 1.072, 27.264%; route: 2.628, 66.835%; tC2Q: 0.232, 5.900% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path16
Path Summary:
Slack | 3.197 |
Data Arrival Time | 6.182 |
Data Required Time | 9.380 |
From | u_extr/buf_ra_0_s0 |
To | u_extr/mem_data_mem_data_0_4_s |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 120 | RIGHTSIDE[0] | u_clk_div_3p5/CLKOUT |
2.271 | 2.271 | tNET | RR | 1 | R30C36[0][B] | u_extr/buf_ra_0_s0/CLK |
2.503 | 0.232 | tC2Q | RF | 8 | R30C36[0][B] | u_extr/buf_ra_0_s0/Q |
2.692 | 0.188 | tNET | FF | 1 | R31C36[2][B] | u_extr/n876_s4/I0 |
3.247 | 0.555 | tINS | FF | 5 | R31C36[2][B] | u_extr/n876_s4/F |
3.444 | 0.197 | tNET | FF | 1 | R32C36[3][B] | u_extr/n873_s4/I3 |
3.897 | 0.453 | tINS | FF | 7 | R32C36[3][B] | u_extr/n873_s4/F |
4.094 | 0.197 | tNET | FF | 1 | R33C36[1][A] | u_extr/buf_ra_c_10_s2/I1 |
4.556 | 0.462 | tINS | FR | 2 | R33C36[1][A] | u_extr/buf_ra_c_10_s2/F |
4.559 | 0.003 | tNET | RR | 1 | R33C36[3][B] | u_extr/buf_ra_c_9_s1/I3 |
4.930 | 0.371 | tINS | RF | 12 | R33C36[3][B] | u_extr/buf_ra_c_9_s1/F |
6.182 | 1.252 | tNET | FF | 1 | BSRAM_R10[10] | u_extr/mem_data_mem_data_0_4_s/ADB[10] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | lvds_pclk | ||||
7.143 | 0.000 | tCL | RR | 120 | RIGHTSIDE[0] | u_clk_div_3p5/CLKOUT |
9.414 | 2.271 | tNET | RR | 1 | BSRAM_R10[10] | u_extr/mem_data_mem_data_0_4_s/CLKB |
9.380 | -0.035 | tSu | 1 | BSRAM_R10[10] | u_extr/mem_data_mem_data_0_4_s |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 7.143 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 1.841, 47.073%; route: 1.838, 46.994%; tC2Q: 0.232, 5.932% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path17
Path Summary:
Slack | 3.197 |
Data Arrival Time | 6.182 |
Data Required Time | 9.380 |
From | u_extr/buf_ra_0_s0 |
To | u_extr/mem_data_mem_data_0_1_s |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 120 | RIGHTSIDE[0] | u_clk_div_3p5/CLKOUT |
2.271 | 2.271 | tNET | RR | 1 | R30C36[0][B] | u_extr/buf_ra_0_s0/CLK |
2.503 | 0.232 | tC2Q | RF | 8 | R30C36[0][B] | u_extr/buf_ra_0_s0/Q |
2.692 | 0.188 | tNET | FF | 1 | R31C36[2][B] | u_extr/n876_s4/I0 |
3.247 | 0.555 | tINS | FF | 5 | R31C36[2][B] | u_extr/n876_s4/F |
3.444 | 0.197 | tNET | FF | 1 | R32C36[3][B] | u_extr/n873_s4/I3 |
3.897 | 0.453 | tINS | FF | 7 | R32C36[3][B] | u_extr/n873_s4/F |
4.094 | 0.197 | tNET | FF | 1 | R33C36[1][A] | u_extr/buf_ra_c_10_s2/I1 |
4.556 | 0.462 | tINS | FR | 2 | R33C36[1][A] | u_extr/buf_ra_c_10_s2/F |
4.559 | 0.003 | tNET | RR | 1 | R33C36[3][B] | u_extr/buf_ra_c_9_s1/I3 |
4.930 | 0.371 | tINS | RF | 12 | R33C36[3][B] | u_extr/buf_ra_c_9_s1/F |
6.182 | 1.252 | tNET | FF | 1 | BSRAM_R28[7] | u_extr/mem_data_mem_data_0_1_s/ADB[10] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | lvds_pclk | ||||
7.143 | 0.000 | tCL | RR | 120 | RIGHTSIDE[0] | u_clk_div_3p5/CLKOUT |
9.414 | 2.271 | tNET | RR | 1 | BSRAM_R28[7] | u_extr/mem_data_mem_data_0_1_s/CLKB |
9.380 | -0.035 | tSu | 1 | BSRAM_R28[7] | u_extr/mem_data_mem_data_0_1_s |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 7.143 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 1.841, 47.073%; route: 1.838, 46.994%; tC2Q: 0.232, 5.932% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path18
Path Summary:
Slack | 3.201 |
Data Arrival Time | 6.178 |
Data Required Time | 9.380 |
From | u_extr/ohs_s0 |
To | u_extr/mem_data_mem_data_0_3_s |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 120 | RIGHTSIDE[0] | u_clk_div_3p5/CLKOUT |
2.271 | 2.271 | tNET | RR | 1 | R33C39[1][A] | u_extr/ohs_s0/CLK |
2.503 | 0.232 | tC2Q | RF | 4 | R33C39[1][A] | u_extr/ohs_s0/Q |
3.411 | 0.907 | tNET | FF | 1 | R30C36[3][A] | u_extr/n868_s1/I0 |
3.928 | 0.517 | tINS | FF | 20 | R30C36[3][A] | u_extr/n868_s1/F |
4.595 | 0.667 | tNET | FF | 1 | R31C35[1][B] | u_extr/buf_ra_c_3_s0/I1 |
4.966 | 0.371 | tINS | FF | 12 | R31C35[1][B] | u_extr/buf_ra_c_3_s0/F |
6.178 | 1.212 | tNET | FF | 1 | BSRAM_R46[9] | u_extr/mem_data_mem_data_0_3_s/ADB[4] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | lvds_pclk | ||||
7.143 | 0.000 | tCL | RR | 120 | RIGHTSIDE[0] | u_clk_div_3p5/CLKOUT |
9.414 | 2.271 | tNET | RR | 1 | BSRAM_R46[9] | u_extr/mem_data_mem_data_0_3_s/CLKB |
9.380 | -0.035 | tSu | 1 | BSRAM_R46[9] | u_extr/mem_data_mem_data_0_3_s |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 7.143 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 0.888, 22.729%; route: 2.787, 71.333%; tC2Q: 0.232, 5.938% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path19
Path Summary:
Slack | 3.204 |
Data Arrival Time | 6.175 |
Data Required Time | 9.380 |
From | u_extr/ohs_s0 |
To | u_extr/mem_data_mem_data_0_1_s |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 120 | RIGHTSIDE[0] | u_clk_div_3p5/CLKOUT |
2.271 | 2.271 | tNET | RR | 1 | R33C39[1][A] | u_extr/ohs_s0/CLK |
2.503 | 0.232 | tC2Q | RF | 4 | R33C39[1][A] | u_extr/ohs_s0/Q |
3.411 | 0.907 | tNET | FF | 1 | R30C36[3][A] | u_extr/n868_s1/I0 |
3.928 | 0.517 | tINS | FF | 20 | R30C36[3][A] | u_extr/n868_s1/F |
4.595 | 0.667 | tNET | FF | 1 | R31C35[1][B] | u_extr/buf_ra_c_3_s0/I1 |
4.966 | 0.371 | tINS | FF | 12 | R31C35[1][B] | u_extr/buf_ra_c_3_s0/F |
6.175 | 1.209 | tNET | FF | 1 | BSRAM_R28[7] | u_extr/mem_data_mem_data_0_1_s/ADB[4] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | lvds_pclk | ||||
7.143 | 0.000 | tCL | RR | 120 | RIGHTSIDE[0] | u_clk_div_3p5/CLKOUT |
9.414 | 2.271 | tNET | RR | 1 | BSRAM_R28[7] | u_extr/mem_data_mem_data_0_1_s/CLKB |
9.380 | -0.035 | tSu | 1 | BSRAM_R28[7] | u_extr/mem_data_mem_data_0_1_s |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 7.143 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 0.888, 22.746%; route: 2.784, 71.311%; tC2Q: 0.232, 5.943% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path20
Path Summary:
Slack | 3.215 |
Data Arrival Time | 6.165 |
Data Required Time | 9.380 |
From | u_extr/ohs_s0 |
To | u_extr/mem_data_mem_data_0_4_s |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 120 | RIGHTSIDE[0] | u_clk_div_3p5/CLKOUT |
2.271 | 2.271 | tNET | RR | 1 | R33C39[1][A] | u_extr/ohs_s0/CLK |
2.503 | 0.232 | tC2Q | RF | 4 | R33C39[1][A] | u_extr/ohs_s0/Q |
3.411 | 0.907 | tNET | FF | 1 | R30C36[3][A] | u_extr/n868_s1/I0 |
3.928 | 0.517 | tINS | FF | 20 | R30C36[3][A] | u_extr/n868_s1/F |
4.468 | 0.540 | tNET | FF | 1 | R33C36[1][B] | u_extr/buf_ra_c_10_s0/I2 |
4.985 | 0.517 | tINS | FF | 12 | R33C36[1][B] | u_extr/buf_ra_c_10_s0/F |
6.165 | 1.180 | tNET | FF | 1 | BSRAM_R10[10] | u_extr/mem_data_mem_data_0_4_s/ADB[11] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | lvds_pclk | ||||
7.143 | 0.000 | tCL | RR | 120 | RIGHTSIDE[0] | u_clk_div_3p5/CLKOUT |
9.414 | 2.271 | tNET | RR | 1 | BSRAM_R10[10] | u_extr/mem_data_mem_data_0_4_s/CLKB |
9.380 | -0.035 | tSu | 1 | BSRAM_R10[10] | u_extr/mem_data_mem_data_0_4_s |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 7.143 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 1.034, 26.556%; route: 2.628, 67.485%; tC2Q: 0.232, 5.958% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path21
Path Summary:
Slack | 3.215 |
Data Arrival Time | 6.165 |
Data Required Time | 9.380 |
From | u_extr/ohs_s0 |
To | u_extr/mem_data_mem_data_0_1_s |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 120 | RIGHTSIDE[0] | u_clk_div_3p5/CLKOUT |
2.271 | 2.271 | tNET | RR | 1 | R33C39[1][A] | u_extr/ohs_s0/CLK |
2.503 | 0.232 | tC2Q | RF | 4 | R33C39[1][A] | u_extr/ohs_s0/Q |
3.411 | 0.907 | tNET | FF | 1 | R30C36[3][A] | u_extr/n868_s1/I0 |
3.928 | 0.517 | tINS | FF | 20 | R30C36[3][A] | u_extr/n868_s1/F |
4.468 | 0.540 | tNET | FF | 1 | R33C36[1][B] | u_extr/buf_ra_c_10_s0/I2 |
4.985 | 0.517 | tINS | FF | 12 | R33C36[1][B] | u_extr/buf_ra_c_10_s0/F |
6.165 | 1.180 | tNET | FF | 1 | BSRAM_R28[7] | u_extr/mem_data_mem_data_0_1_s/ADB[11] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | lvds_pclk | ||||
7.143 | 0.000 | tCL | RR | 120 | RIGHTSIDE[0] | u_clk_div_3p5/CLKOUT |
9.414 | 2.271 | tNET | RR | 1 | BSRAM_R28[7] | u_extr/mem_data_mem_data_0_1_s/CLKB |
9.380 | -0.035 | tSu | 1 | BSRAM_R28[7] | u_extr/mem_data_mem_data_0_1_s |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 7.143 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 1.034, 26.556%; route: 2.628, 67.485%; tC2Q: 0.232, 5.958% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path22
Path Summary:
Slack | 3.218 |
Data Arrival Time | 6.162 |
Data Required Time | 9.380 |
From | u_extr/buf_ra_0_s0 |
To | u_extr/mem_data_mem_data_0_0_s |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 120 | RIGHTSIDE[0] | u_clk_div_3p5/CLKOUT |
2.271 | 2.271 | tNET | RR | 1 | R30C36[0][B] | u_extr/buf_ra_0_s0/CLK |
2.503 | 0.232 | tC2Q | RF | 8 | R30C36[0][B] | u_extr/buf_ra_0_s0/Q |
2.692 | 0.188 | tNET | FF | 1 | R31C36[2][B] | u_extr/n876_s4/I0 |
3.247 | 0.555 | tINS | FF | 5 | R31C36[2][B] | u_extr/n876_s4/F |
3.444 | 0.197 | tNET | FF | 1 | R32C36[3][B] | u_extr/n873_s4/I3 |
3.897 | 0.453 | tINS | FF | 7 | R32C36[3][B] | u_extr/n873_s4/F |
4.094 | 0.197 | tNET | FF | 1 | R33C36[1][A] | u_extr/buf_ra_c_10_s2/I1 |
4.556 | 0.462 | tINS | FR | 2 | R33C36[1][A] | u_extr/buf_ra_c_10_s2/F |
4.559 | 0.003 | tNET | RR | 1 | R33C36[3][B] | u_extr/buf_ra_c_9_s1/I3 |
4.930 | 0.371 | tINS | RF | 12 | R33C36[3][B] | u_extr/buf_ra_c_9_s1/F |
6.162 | 1.232 | tNET | FF | 1 | BSRAM_R28[6] | u_extr/mem_data_mem_data_0_0_s/ADB[10] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | lvds_pclk | ||||
7.143 | 0.000 | tCL | RR | 120 | RIGHTSIDE[0] | u_clk_div_3p5/CLKOUT |
9.414 | 2.271 | tNET | RR | 1 | BSRAM_R28[6] | u_extr/mem_data_mem_data_0_0_s/CLKB |
9.380 | -0.035 | tSu | 1 | BSRAM_R28[6] | u_extr/mem_data_mem_data_0_0_s |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 7.143 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 1.841, 47.320%; route: 1.818, 46.717%; tC2Q: 0.232, 5.963% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path23
Path Summary:
Slack | 3.234 |
Data Arrival Time | 6.146 |
Data Required Time | 9.380 |
From | u_extr/ohs_s0 |
To | u_extr/mem_data_mem_data_0_11_s |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 120 | RIGHTSIDE[0] | u_clk_div_3p5/CLKOUT |
2.271 | 2.271 | tNET | RR | 1 | R33C39[1][A] | u_extr/ohs_s0/CLK |
2.503 | 0.232 | tC2Q | RF | 4 | R33C39[1][A] | u_extr/ohs_s0/Q |
3.411 | 0.907 | tNET | FF | 1 | R30C36[3][A] | u_extr/n868_s1/I0 |
3.928 | 0.517 | tINS | FF | 20 | R30C36[3][A] | u_extr/n868_s1/F |
4.468 | 0.540 | tNET | FF | 1 | R33C36[1][B] | u_extr/buf_ra_c_10_s0/I2 |
4.985 | 0.517 | tINS | FF | 12 | R33C36[1][B] | u_extr/buf_ra_c_10_s0/F |
6.146 | 1.161 | tNET | FF | 1 | BSRAM_R28[13] | u_extr/mem_data_mem_data_0_11_s/ADB[11] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | lvds_pclk | ||||
7.143 | 0.000 | tCL | RR | 120 | RIGHTSIDE[0] | u_clk_div_3p5/CLKOUT |
9.414 | 2.271 | tNET | RR | 1 | BSRAM_R28[13] | u_extr/mem_data_mem_data_0_11_s/CLKB |
9.380 | -0.035 | tSu | 1 | BSRAM_R28[13] | u_extr/mem_data_mem_data_0_11_s |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 7.143 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 1.034, 26.687%; route: 2.609, 67.325%; tC2Q: 0.232, 5.988% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path24
Path Summary:
Slack | 3.252 |
Data Arrival Time | 6.127 |
Data Required Time | 9.379 |
From | u_extr/mem_data_mem_data_0_4_s |
To | u_extr/mem_rqout_r_9_s0 |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 120 | RIGHTSIDE[0] | u_clk_div_3p5/CLKOUT |
2.271 | 2.271 | tNET | RR | 2 | BSRAM_R10[10] | u_extr/mem_data_mem_data_0_4_s/CLKB |
4.531 | 2.260 | tC2Q | RF | 1 | BSRAM_R10[10] | u_extr/mem_data_mem_data_0_4_s/DO[1] |
6.127 | 1.596 | tNET | FF | 1 | R32C36[1][A] | u_extr/mem_rqout_r_9_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | lvds_pclk | ||||
7.143 | 0.000 | tCL | RR | 120 | RIGHTSIDE[0] | u_clk_div_3p5/CLKOUT |
9.414 | 2.271 | tNET | RR | 1 | R32C36[1][A] | u_extr/mem_rqout_r_9_s0/CLK |
9.379 | -0.035 | tSu | 1 | R32C36[1][A] | u_extr/mem_rqout_r_9_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 7.143 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.596, 41.386%; tC2Q: 2.260, 58.614% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path25
Path Summary:
Slack | 3.253 |
Data Arrival Time | 6.126 |
Data Required Time | 9.380 |
From | u_extr/ohs_s0 |
To | u_extr/mem_data_mem_data_0_4_s |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 120 | RIGHTSIDE[0] | u_clk_div_3p5/CLKOUT |
2.271 | 2.271 | tNET | RR | 1 | R33C39[1][A] | u_extr/ohs_s0/CLK |
2.503 | 0.232 | tC2Q | RF | 4 | R33C39[1][A] | u_extr/ohs_s0/Q |
3.411 | 0.907 | tNET | FF | 1 | R30C36[3][A] | u_extr/n868_s1/I0 |
3.928 | 0.517 | tINS | FF | 20 | R30C36[3][A] | u_extr/n868_s1/F |
4.352 | 0.425 | tNET | FF | 1 | R31C36[0][B] | u_extr/buf_ra_c_7_s0/I2 |
4.869 | 0.517 | tINS | FF | 12 | R31C36[0][B] | u_extr/buf_ra_c_7_s0/F |
6.126 | 1.257 | tNET | FF | 1 | BSRAM_R10[10] | u_extr/mem_data_mem_data_0_4_s/ADB[8] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | lvds_pclk | ||||
7.143 | 0.000 | tCL | RR | 120 | RIGHTSIDE[0] | u_clk_div_3p5/CLKOUT |
9.414 | 2.271 | tNET | RR | 1 | BSRAM_R10[10] | u_extr/mem_data_mem_data_0_4_s/CLKB |
9.380 | -0.035 | tSu | 1 | BSRAM_R10[10] | u_extr/mem_data_mem_data_0_4_s |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 7.143 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 1.034, 26.824%; route: 2.589, 67.158%; tC2Q: 0.232, 6.018% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Hold Analysis Report
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 0.198 |
Data Arrival Time | 1.958 |
Data Required Time | 1.760 |
From | u_extr/buf_wd_4_s0 |
To | u_extr/mem_data_mem_data_0_2_s |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 214 | PLL_L[0] | u_pll_1/rpll_inst/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R32C32[2][B] | u_extr/buf_wd_4_s0/CLK |
1.713 | 0.202 | tC2Q | RR | 1 | R32C32[2][B] | u_extr/buf_wd_4_s0/Q |
1.958 | 0.245 | tNET | RR | 1 | BSRAM_R28[8] | u_extr/mem_data_mem_data_0_2_s/DI[0] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 214 | PLL_L[0] | u_pll_1/rpll_inst/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | BSRAM_R28[8] | u_extr/mem_data_mem_data_0_2_s/CLKA |
1.760 | 0.249 | tHld | 1 | BSRAM_R28[8] | u_extr/mem_data_mem_data_0_2_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.245, 54.832%; tC2Q: 0.202, 45.168% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path2
Path Summary:
Slack | 0.215 |
Data Arrival Time | 1.844 |
Data Required Time | 1.629 |
From | u_extr/buf_wa_9_s0 |
To | u_extr/mem_data_mem_data_0_5_s |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 214 | PLL_L[0] | u_pll_1/rpll_inst/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R30C35[1][A] | u_extr/buf_wa_9_s0/CLK |
1.713 | 0.202 | tC2Q | RR | 13 | R30C35[1][A] | u_extr/buf_wa_9_s0/Q |
1.844 | 0.131 | tNET | RR | 1 | BSRAM_R28[9] | u_extr/mem_data_mem_data_0_5_s/ADA[10] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 214 | PLL_L[0] | u_pll_1/rpll_inst/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | BSRAM_R28[9] | u_extr/mem_data_mem_data_0_5_s/CLKA |
1.629 | 0.118 | tHld | 1 | BSRAM_R28[9] | u_extr/mem_data_mem_data_0_5_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.131, 39.258%; tC2Q: 0.202, 60.742% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path3
Path Summary:
Slack | 0.225 |
Data Arrival Time | 1.986 |
Data Required Time | 1.760 |
From | u_extr/buf_wd_11_s0 |
To | u_extr/mem_data_mem_data_0_5_s |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 214 | PLL_L[0] | u_pll_1/rpll_inst/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R34C35[1][A] | u_extr/buf_wd_11_s0/CLK |
1.713 | 0.202 | tC2Q | RR | 1 | R34C35[1][A] | u_extr/buf_wd_11_s0/Q |
1.986 | 0.272 | tNET | RR | 1 | BSRAM_R28[9] | u_extr/mem_data_mem_data_0_5_s/DI[1] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 214 | PLL_L[0] | u_pll_1/rpll_inst/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | BSRAM_R28[9] | u_extr/mem_data_mem_data_0_5_s/CLKA |
1.760 | 0.249 | tHld | 1 | BSRAM_R28[9] | u_extr/mem_data_mem_data_0_5_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.272, 57.427%; tC2Q: 0.202, 42.573% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path4
Path Summary:
Slack | 0.225 |
Data Arrival Time | 1.986 |
Data Required Time | 1.760 |
From | u_extr/buf_wd_5_s0 |
To | u_extr/mem_data_mem_data_0_2_s |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 214 | PLL_L[0] | u_pll_1/rpll_inst/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R32C32[2][A] | u_extr/buf_wd_5_s0/CLK |
1.713 | 0.202 | tC2Q | RR | 1 | R32C32[2][A] | u_extr/buf_wd_5_s0/Q |
1.986 | 0.272 | tNET | RR | 1 | BSRAM_R28[8] | u_extr/mem_data_mem_data_0_2_s/DI[1] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 214 | PLL_L[0] | u_pll_1/rpll_inst/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | BSRAM_R28[8] | u_extr/mem_data_mem_data_0_2_s/CLKA |
1.760 | 0.249 | tHld | 1 | BSRAM_R28[8] | u_extr/mem_data_mem_data_0_2_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.272, 57.427%; tC2Q: 0.202, 42.573% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path5
Path Summary:
Slack | 0.318 |
Data Arrival Time | 1.840 |
Data Required Time | 1.522 |
From | u_b2p/u_b2p_inst/u_mid_fifo/rRstRsync_s0 |
To | u_b2p/u_b2p_inst/u_mid_fifo/rRdRst_s0 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 214 | PLL_L[0] | u_pll_1/rpll_inst/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R36C27[1][A] | u_b2p/u_b2p_inst/u_mid_fifo/rRstRsync_s0/CLK |
1.713 | 0.202 | tC2Q | RR | 1 | R36C27[1][A] | u_b2p/u_b2p_inst/u_mid_fifo/rRstRsync_s0/Q |
1.840 | 0.127 | tNET | RR | 1 | R36C27[2][A] | u_b2p/u_b2p_inst/u_mid_fifo/rRdRst_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 214 | PLL_L[0] | u_pll_1/rpll_inst/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R36C27[2][A] | u_b2p/u_b2p_inst/u_mid_fifo/rRdRst_s0/CLK |
1.522 | 0.011 | tHld | 1 | R36C27[2][A] | u_b2p/u_b2p_inst/u_mid_fifo/rRdRst_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.127, 38.638%; tC2Q: 0.202, 61.362% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path6
Path Summary:
Slack | 0.318 |
Data Arrival Time | 1.840 |
Data Required Time | 1.522 |
From | u_b2p/u_b2p_inst/u_mid_fifo/rRstWsync_s0 |
To | u_b2p/u_b2p_inst/u_mid_fifo/rWrRst_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R34C27[1][A] | u_b2p/u_b2p_inst/u_mid_fifo/rRstWsync_s0/CLK |
1.713 | 0.202 | tC2Q | RR | 1 | R34C27[1][A] | u_b2p/u_b2p_inst/u_mid_fifo/rRstWsync_s0/Q |
1.840 | 0.127 | tNET | RR | 1 | R34C27[2][A] | u_b2p/u_b2p_inst/u_mid_fifo/rWrRst_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R34C27[2][A] | u_b2p/u_b2p_inst/u_mid_fifo/rWrRst_s0/CLK |
1.522 | 0.011 | tHld | 1 | R34C27[2][A] | u_b2p/u_b2p_inst/u_mid_fifo/rWrRst_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.127, 38.638%; tC2Q: 0.202, 61.362% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path7
Path Summary:
Slack | 0.323 |
Data Arrival Time | 1.845 |
Data Required Time | 1.522 |
From | u_b2p/u_b2p_inst/mid_dv_s0 |
To | u_b2p/u_b2p_inst/rBufD_22_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R32C19[2][A] | u_b2p/u_b2p_inst/mid_dv_s0/CLK |
1.713 | 0.202 | tC2Q | RR | 51 | R32C19[2][A] | u_b2p/u_b2p_inst/mid_dv_s0/Q |
1.845 | 0.132 | tNET | RR | 1 | R32C19[1][B] | u_b2p/u_b2p_inst/rBufD_22_s1/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R32C19[1][B] | u_b2p/u_b2p_inst/rBufD_22_s1/CLK |
1.522 | 0.011 | tHld | 1 | R32C19[1][B] | u_b2p/u_b2p_inst/rBufD_22_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.132, 39.536%; tC2Q: 0.202, 60.464% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path8
Path Summary:
Slack | 0.323 |
Data Arrival Time | 1.845 |
Data Required Time | 1.522 |
From | u_b2p/u_b2p_inst/mid_dv_s0 |
To | u_b2p/u_b2p_inst/rBufD_28_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R32C19[2][A] | u_b2p/u_b2p_inst/mid_dv_s0/CLK |
1.713 | 0.202 | tC2Q | RR | 51 | R32C19[2][A] | u_b2p/u_b2p_inst/mid_dv_s0/Q |
1.845 | 0.132 | tNET | RR | 1 | R32C19[1][A] | u_b2p/u_b2p_inst/rBufD_28_s1/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R32C19[1][A] | u_b2p/u_b2p_inst/rBufD_28_s1/CLK |
1.522 | 0.011 | tHld | 1 | R32C19[1][A] | u_b2p/u_b2p_inst/rBufD_28_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.132, 39.536%; tC2Q: 0.202, 60.464% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path9
Path Summary:
Slack | 0.326 |
Data Arrival Time | 1.849 |
Data Required Time | 1.522 |
From | u_b2p/u_b2p_inst/u_align_forward/de_wor_r_s0 |
To | u_b2p/u_b2p_inst/u_align_forward/data_o_reg_3_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R30C24[0][B] | u_b2p/u_b2p_inst/u_align_forward/de_wor_r_s0/CLK |
1.713 | 0.202 | tC2Q | RR | 37 | R30C24[0][B] | u_b2p/u_b2p_inst/u_align_forward/de_wor_r_s0/Q |
1.849 | 0.135 | tNET | RR | 1 | R30C23[0][A] | u_b2p/u_b2p_inst/u_align_forward/data_o_reg_3_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R30C23[0][A] | u_b2p/u_b2p_inst/u_align_forward/data_o_reg_3_s0/CLK |
1.522 | 0.011 | tHld | 1 | R30C23[0][A] | u_b2p/u_b2p_inst/u_align_forward/data_o_reg_3_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.135, 40.119%; tC2Q: 0.202, 59.881% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path10
Path Summary:
Slack | 0.326 |
Data Arrival Time | 1.849 |
Data Required Time | 1.522 |
From | u_b2p/u_b2p_inst/u_align_forward/de_wor_r_s0 |
To | u_b2p/u_b2p_inst/u_align_forward/data_o_reg_8_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R30C24[0][B] | u_b2p/u_b2p_inst/u_align_forward/de_wor_r_s0/CLK |
1.713 | 0.202 | tC2Q | RR | 37 | R30C24[0][B] | u_b2p/u_b2p_inst/u_align_forward/de_wor_r_s0/Q |
1.849 | 0.135 | tNET | RR | 1 | R30C23[2][B] | u_b2p/u_b2p_inst/u_align_forward/data_o_reg_8_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R30C23[2][B] | u_b2p/u_b2p_inst/u_align_forward/data_o_reg_8_s0/CLK |
1.522 | 0.011 | tHld | 1 | R30C23[2][B] | u_b2p/u_b2p_inst/u_align_forward/data_o_reg_8_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.135, 40.119%; tC2Q: 0.202, 59.881% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path11
Path Summary:
Slack | 0.326 |
Data Arrival Time | 1.849 |
Data Required Time | 1.522 |
From | u_b2p/u_b2p_inst/u_align_forward/de_wor_r_s0 |
To | u_b2p/u_b2p_inst/u_align_forward/data_o_reg_10_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R30C24[0][B] | u_b2p/u_b2p_inst/u_align_forward/de_wor_r_s0/CLK |
1.713 | 0.202 | tC2Q | RR | 37 | R30C24[0][B] | u_b2p/u_b2p_inst/u_align_forward/de_wor_r_s0/Q |
1.849 | 0.135 | tNET | RR | 1 | R30C23[2][A] | u_b2p/u_b2p_inst/u_align_forward/data_o_reg_10_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R30C23[2][A] | u_b2p/u_b2p_inst/u_align_forward/data_o_reg_10_s0/CLK |
1.522 | 0.011 | tHld | 1 | R30C23[2][A] | u_b2p/u_b2p_inst/u_align_forward/data_o_reg_10_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.135, 40.119%; tC2Q: 0.202, 59.881% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path12
Path Summary:
Slack | 0.326 |
Data Arrival Time | 1.849 |
Data Required Time | 1.522 |
From | u_b2p/u_b2p_inst/u_align_forward/de_wor_r_s0 |
To | u_b2p/u_b2p_inst/u_align_forward/data_o_reg_16_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R30C24[0][B] | u_b2p/u_b2p_inst/u_align_forward/de_wor_r_s0/CLK |
1.713 | 0.202 | tC2Q | RR | 37 | R30C24[0][B] | u_b2p/u_b2p_inst/u_align_forward/de_wor_r_s0/Q |
1.849 | 0.135 | tNET | RR | 1 | R30C23[1][B] | u_b2p/u_b2p_inst/u_align_forward/data_o_reg_16_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R30C23[1][B] | u_b2p/u_b2p_inst/u_align_forward/data_o_reg_16_s0/CLK |
1.522 | 0.011 | tHld | 1 | R30C23[1][B] | u_b2p/u_b2p_inst/u_align_forward/data_o_reg_16_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.135, 40.119%; tC2Q: 0.202, 59.881% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path13
Path Summary:
Slack | 0.326 |
Data Arrival Time | 1.849 |
Data Required Time | 1.522 |
From | u_b2p/u_b2p_inst/u_align_forward/de_wor_r_s0 |
To | u_b2p/u_b2p_inst/u_align_forward/data_o_reg_18_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R30C24[0][B] | u_b2p/u_b2p_inst/u_align_forward/de_wor_r_s0/CLK |
1.713 | 0.202 | tC2Q | RR | 37 | R30C24[0][B] | u_b2p/u_b2p_inst/u_align_forward/de_wor_r_s0/Q |
1.849 | 0.135 | tNET | RR | 1 | R30C23[1][A] | u_b2p/u_b2p_inst/u_align_forward/data_o_reg_18_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R30C23[1][A] | u_b2p/u_b2p_inst/u_align_forward/data_o_reg_18_s0/CLK |
1.522 | 0.011 | tHld | 1 | R30C23[1][A] | u_b2p/u_b2p_inst/u_align_forward/data_o_reg_18_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.135, 40.119%; tC2Q: 0.202, 59.881% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path14
Path Summary:
Slack | 0.326 |
Data Arrival Time | 1.849 |
Data Required Time | 1.522 |
From | u_b2p/u_b2p_inst/u_align_forward/de_wor_r_s0 |
To | u_b2p/u_b2p_inst/u_align_forward/data_o_reg_26_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R30C24[0][B] | u_b2p/u_b2p_inst/u_align_forward/de_wor_r_s0/CLK |
1.713 | 0.202 | tC2Q | RR | 37 | R30C24[0][B] | u_b2p/u_b2p_inst/u_align_forward/de_wor_r_s0/Q |
1.849 | 0.135 | tNET | RR | 1 | R30C23[0][B] | u_b2p/u_b2p_inst/u_align_forward/data_o_reg_26_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R30C23[0][B] | u_b2p/u_b2p_inst/u_align_forward/data_o_reg_26_s0/CLK |
1.522 | 0.011 | tHld | 1 | R30C23[0][B] | u_b2p/u_b2p_inst/u_align_forward/data_o_reg_26_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.135, 40.119%; tC2Q: 0.202, 59.881% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path15
Path Summary:
Slack | 0.329 |
Data Arrival Time | 1.852 |
Data Required Time | 1.522 |
From | u_b2p/u_b2p_inst/u_align_forward/de_wor_r_s0 |
To | u_b2p/u_b2p_inst/u_align_forward/data_o_reg_1_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R30C24[0][B] | u_b2p/u_b2p_inst/u_align_forward/de_wor_r_s0/CLK |
1.713 | 0.202 | tC2Q | RR | 37 | R30C24[0][B] | u_b2p/u_b2p_inst/u_align_forward/de_wor_r_s0/Q |
1.852 | 0.138 | tNET | RR | 1 | R30C24[2][B] | u_b2p/u_b2p_inst/u_align_forward/data_o_reg_1_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R30C24[2][B] | u_b2p/u_b2p_inst/u_align_forward/data_o_reg_1_s0/CLK |
1.522 | 0.011 | tHld | 1 | R30C24[2][B] | u_b2p/u_b2p_inst/u_align_forward/data_o_reg_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.138, 40.636%; tC2Q: 0.202, 59.364% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path16
Path Summary:
Slack | 0.329 |
Data Arrival Time | 1.852 |
Data Required Time | 1.522 |
From | u_b2p/u_b2p_inst/u_align_forward/de_wor_r_s0 |
To | u_b2p/u_b2p_inst/u_align_forward/data_o_reg_9_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R30C24[0][B] | u_b2p/u_b2p_inst/u_align_forward/de_wor_r_s0/CLK |
1.713 | 0.202 | tC2Q | RR | 37 | R30C24[0][B] | u_b2p/u_b2p_inst/u_align_forward/de_wor_r_s0/Q |
1.852 | 0.138 | tNET | RR | 1 | R30C24[2][A] | u_b2p/u_b2p_inst/u_align_forward/data_o_reg_9_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R30C24[2][A] | u_b2p/u_b2p_inst/u_align_forward/data_o_reg_9_s0/CLK |
1.522 | 0.011 | tHld | 1 | R30C24[2][A] | u_b2p/u_b2p_inst/u_align_forward/data_o_reg_9_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.138, 40.636%; tC2Q: 0.202, 59.364% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path17
Path Summary:
Slack | 0.329 |
Data Arrival Time | 1.852 |
Data Required Time | 1.522 |
From | u_b2p/u_b2p_inst/u_align_forward/de_wor_r_s0 |
To | u_b2p/u_b2p_inst/u_align_forward/data_o_reg_17_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R30C24[0][B] | u_b2p/u_b2p_inst/u_align_forward/de_wor_r_s0/CLK |
1.713 | 0.202 | tC2Q | RR | 37 | R30C24[0][B] | u_b2p/u_b2p_inst/u_align_forward/de_wor_r_s0/Q |
1.852 | 0.138 | tNET | RR | 1 | R30C24[1][B] | u_b2p/u_b2p_inst/u_align_forward/data_o_reg_17_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R30C24[1][B] | u_b2p/u_b2p_inst/u_align_forward/data_o_reg_17_s0/CLK |
1.522 | 0.011 | tHld | 1 | R30C24[1][B] | u_b2p/u_b2p_inst/u_align_forward/data_o_reg_17_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.138, 40.636%; tC2Q: 0.202, 59.364% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path18
Path Summary:
Slack | 0.329 |
Data Arrival Time | 1.852 |
Data Required Time | 1.522 |
From | u_b2p/u_b2p_inst/u_align_forward/de_wor_r_s0 |
To | u_b2p/u_b2p_inst/u_align_forward/data_o_reg_25_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R30C24[0][B] | u_b2p/u_b2p_inst/u_align_forward/de_wor_r_s0/CLK |
1.713 | 0.202 | tC2Q | RR | 37 | R30C24[0][B] | u_b2p/u_b2p_inst/u_align_forward/de_wor_r_s0/Q |
1.852 | 0.138 | tNET | RR | 1 | R30C24[1][A] | u_b2p/u_b2p_inst/u_align_forward/data_o_reg_25_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R30C24[1][A] | u_b2p/u_b2p_inst/u_align_forward/data_o_reg_25_s0/CLK |
1.522 | 0.011 | tHld | 1 | R30C24[1][A] | u_b2p/u_b2p_inst/u_align_forward/data_o_reg_25_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.138, 40.636%; tC2Q: 0.202, 59.364% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path19
Path Summary:
Slack | 0.332 |
Data Arrival Time | 1.854 |
Data Required Time | 1.522 |
From | u_dsi_rx/u_dsi_csi2/rDataEn_s0 |
To | u_dsi_rx/u_dsi_csi2/rDataReg_13_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R21C35[0][A] | u_dsi_rx/u_dsi_csi2/rDataEn_s0/CLK |
1.713 | 0.202 | tC2Q | RR | 47 | R21C35[0][A] | u_dsi_rx/u_dsi_csi2/rDataEn_s0/Q |
1.854 | 0.141 | tNET | RR | 1 | R21C35[2][A] | u_dsi_rx/u_dsi_csi2/rDataReg_13_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R21C35[2][A] | u_dsi_rx/u_dsi_csi2/rDataReg_13_s0/CLK |
1.522 | 0.011 | tHld | 1 | R21C35[2][A] | u_dsi_rx/u_dsi_csi2/rDataReg_13_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.141, 41.045%; tC2Q: 0.202, 58.955% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path20
Path Summary:
Slack | 0.332 |
Data Arrival Time | 1.855 |
Data Required Time | 1.522 |
From | u_b2p/u_b2p_inst/u_align_forward/de_wor_r_s0 |
To | u_b2p/u_b2p_inst/u_align_forward/data_o_reg_0_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R30C24[0][B] | u_b2p/u_b2p_inst/u_align_forward/de_wor_r_s0/CLK |
1.713 | 0.202 | tC2Q | RR | 37 | R30C24[0][B] | u_b2p/u_b2p_inst/u_align_forward/de_wor_r_s0/Q |
1.855 | 0.141 | tNET | RR | 1 | R30C22[2][A] | u_b2p/u_b2p_inst/u_align_forward/data_o_reg_0_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R30C22[2][A] | u_b2p/u_b2p_inst/u_align_forward/data_o_reg_0_s0/CLK |
1.522 | 0.011 | tHld | 1 | R30C22[2][A] | u_b2p/u_b2p_inst/u_align_forward/data_o_reg_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.141, 41.165%; tC2Q: 0.202, 58.835% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path21
Path Summary:
Slack | 0.335 |
Data Arrival Time | 1.858 |
Data Required Time | 1.522 |
From | u_extr/iworking_s1 |
To | u_extr/buf_wd_9_s0 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 214 | PLL_L[0] | u_pll_1/rpll_inst/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R34C35[2][A] | u_extr/iworking_s1/CLK |
1.713 | 0.202 | tC2Q | RR | 35 | R34C35[2][A] | u_extr/iworking_s1/Q |
1.858 | 0.144 | tNET | RR | 1 | R34C35[0][A] | u_extr/buf_wd_9_s0/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 214 | PLL_L[0] | u_pll_1/rpll_inst/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R34C35[0][A] | u_extr/buf_wd_9_s0/CLK |
1.522 | 0.011 | tHld | 1 | R34C35[0][A] | u_extr/buf_wd_9_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.144, 41.683%; tC2Q: 0.202, 58.317% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path22
Path Summary:
Slack | 0.335 |
Data Arrival Time | 1.858 |
Data Required Time | 1.522 |
From | u_extr/iworking_s1 |
To | u_extr/buf_wd_10_s0 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 214 | PLL_L[0] | u_pll_1/rpll_inst/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R34C35[2][A] | u_extr/iworking_s1/CLK |
1.713 | 0.202 | tC2Q | RR | 35 | R34C35[2][A] | u_extr/iworking_s1/Q |
1.858 | 0.144 | tNET | RR | 1 | R34C35[0][B] | u_extr/buf_wd_10_s0/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 214 | PLL_L[0] | u_pll_1/rpll_inst/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R34C35[0][B] | u_extr/buf_wd_10_s0/CLK |
1.522 | 0.011 | tHld | 1 | R34C35[0][B] | u_extr/buf_wd_10_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.144, 41.683%; tC2Q: 0.202, 58.317% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path23
Path Summary:
Slack | 0.335 |
Data Arrival Time | 1.858 |
Data Required Time | 1.522 |
From | u_extr/iworking_s1 |
To | u_extr/buf_wd_11_s0 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 214 | PLL_L[0] | u_pll_1/rpll_inst/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R34C35[2][A] | u_extr/iworking_s1/CLK |
1.713 | 0.202 | tC2Q | RR | 35 | R34C35[2][A] | u_extr/iworking_s1/Q |
1.858 | 0.144 | tNET | RR | 1 | R34C35[1][A] | u_extr/buf_wd_11_s0/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 214 | PLL_L[0] | u_pll_1/rpll_inst/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R34C35[1][A] | u_extr/buf_wd_11_s0/CLK |
1.522 | 0.011 | tHld | 1 | R34C35[1][A] | u_extr/buf_wd_11_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.144, 41.683%; tC2Q: 0.202, 58.317% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path24
Path Summary:
Slack | 0.335 |
Data Arrival Time | 1.858 |
Data Required Time | 1.522 |
From | u_extr/iworking_s1 |
To | u_extr/buf_wd_12_s0 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 214 | PLL_L[0] | u_pll_1/rpll_inst/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R34C35[2][A] | u_extr/iworking_s1/CLK |
1.713 | 0.202 | tC2Q | RR | 35 | R34C35[2][A] | u_extr/iworking_s1/Q |
1.858 | 0.144 | tNET | RR | 1 | R34C35[1][B] | u_extr/buf_wd_12_s0/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 214 | PLL_L[0] | u_pll_1/rpll_inst/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R34C35[1][B] | u_extr/buf_wd_12_s0/CLK |
1.522 | 0.011 | tHld | 1 | R34C35[1][B] | u_extr/buf_wd_12_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.144, 41.683%; tC2Q: 0.202, 58.317% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path25
Path Summary:
Slack | 0.337 |
Data Arrival Time | 1.966 |
Data Required Time | 1.629 |
From | u_extr/buf_wa_1_s0 |
To | u_extr/mem_data_mem_data_0_5_s |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 214 | PLL_L[0] | u_pll_1/rpll_inst/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R30C34[0][A] | u_extr/buf_wa_1_s0/CLK |
1.713 | 0.202 | tC2Q | RR | 13 | R30C34[0][A] | u_extr/buf_wa_1_s0/Q |
1.966 | 0.253 | tNET | RR | 1 | BSRAM_R28[9] | u_extr/mem_data_mem_data_0_5_s/ADA[2] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 214 | PLL_L[0] | u_pll_1/rpll_inst/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | BSRAM_R28[9] | u_extr/mem_data_mem_data_0_5_s/CLKA |
1.629 | 0.118 | tHld | 1 | BSRAM_R28[9] | u_extr/mem_data_mem_data_0_5_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.253, 55.615%; tC2Q: 0.202, 44.385% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Recovery Analysis Report
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 7.192 |
Data Arrival Time | 4.568 |
Data Required Time | 11.760 |
From | hsrx_en_s0 |
To | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_cnt_0_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
2.271 | 2.271 | tNET | RR | 1 | R17C18[2][A] | hsrx_en_s0/CLK |
2.503 | 0.232 | tC2Q | RF | 1 | R17C18[2][A] | hsrx_en_s0/Q |
2.656 | 0.153 | tNET | FF | 1 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/I1 |
3.211 | 0.555 | tINS | FF | 469 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/F |
4.568 | 1.357 | tNET | FF | 1 | R22C32[1][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_cnt_0_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.524 | 9.524 | active clock edge time | ||||
9.524 | 0.000 | byte_clk | ||||
9.524 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
11.795 | 2.271 | tNET | RR | 1 | R22C32[1][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_cnt_0_s1/CLK |
11.760 | -0.035 | tSu | 1 | R22C32[1][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_cnt_0_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 9.524 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 0.555, 24.164%; route: 1.510, 65.736%; tC2Q: 0.232, 10.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path2
Path Summary:
Slack | 7.192 |
Data Arrival Time | 4.568 |
Data Required Time | 11.760 |
From | hsrx_en_s0 |
To | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_cnt_1_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
2.271 | 2.271 | tNET | RR | 1 | R17C18[2][A] | hsrx_en_s0/CLK |
2.503 | 0.232 | tC2Q | RF | 1 | R17C18[2][A] | hsrx_en_s0/Q |
2.656 | 0.153 | tNET | FF | 1 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/I1 |
3.211 | 0.555 | tINS | FF | 469 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/F |
4.568 | 1.357 | tNET | FF | 1 | R22C32[1][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_cnt_1_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.524 | 9.524 | active clock edge time | ||||
9.524 | 0.000 | byte_clk | ||||
9.524 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
11.795 | 2.271 | tNET | RR | 1 | R22C32[1][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_cnt_1_s1/CLK |
11.760 | -0.035 | tSu | 1 | R22C32[1][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_cnt_1_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 9.524 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 0.555, 24.164%; route: 1.510, 65.736%; tC2Q: 0.232, 10.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path3
Path Summary:
Slack | 7.192 |
Data Arrival Time | 4.568 |
Data Required Time | 11.760 |
From | hsrx_en_s0 |
To | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_cnt_0_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
2.271 | 2.271 | tNET | RR | 1 | R17C18[2][A] | hsrx_en_s0/CLK |
2.503 | 0.232 | tC2Q | RF | 1 | R17C18[2][A] | hsrx_en_s0/Q |
2.656 | 0.153 | tNET | FF | 1 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/I1 |
3.211 | 0.555 | tINS | FF | 469 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/F |
4.568 | 1.357 | tNET | FF | 1 | R27C26[2][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_cnt_0_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.524 | 9.524 | active clock edge time | ||||
9.524 | 0.000 | byte_clk | ||||
9.524 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
11.795 | 2.271 | tNET | RR | 1 | R27C26[2][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_cnt_0_s1/CLK |
11.760 | -0.035 | tSu | 1 | R27C26[2][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_cnt_0_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 9.524 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 0.555, 24.164%; route: 1.510, 65.736%; tC2Q: 0.232, 10.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path4
Path Summary:
Slack | 7.192 |
Data Arrival Time | 4.568 |
Data Required Time | 11.760 |
From | hsrx_en_s0 |
To | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_cnt_1_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
2.271 | 2.271 | tNET | RR | 1 | R17C18[2][A] | hsrx_en_s0/CLK |
2.503 | 0.232 | tC2Q | RF | 1 | R17C18[2][A] | hsrx_en_s0/Q |
2.656 | 0.153 | tNET | FF | 1 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/I1 |
3.211 | 0.555 | tINS | FF | 469 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/F |
4.568 | 1.357 | tNET | FF | 1 | R27C29[0][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_cnt_1_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.524 | 9.524 | active clock edge time | ||||
9.524 | 0.000 | byte_clk | ||||
9.524 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
11.795 | 2.271 | tNET | RR | 1 | R27C29[0][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_cnt_1_s1/CLK |
11.760 | -0.035 | tSu | 1 | R27C29[0][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_cnt_1_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 9.524 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 0.555, 24.164%; route: 1.510, 65.736%; tC2Q: 0.232, 10.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path5
Path Summary:
Slack | 7.192 |
Data Arrival Time | 4.568 |
Data Required Time | 11.760 |
From | hsrx_en_s0 |
To | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane1_cnt_0_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
2.271 | 2.271 | tNET | RR | 1 | R17C18[2][A] | hsrx_en_s0/CLK |
2.503 | 0.232 | tC2Q | RF | 1 | R17C18[2][A] | hsrx_en_s0/Q |
2.656 | 0.153 | tNET | FF | 1 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/I1 |
3.211 | 0.555 | tINS | FF | 469 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/F |
4.568 | 1.357 | tNET | FF | 1 | R26C31[0][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane1_cnt_0_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.524 | 9.524 | active clock edge time | ||||
9.524 | 0.000 | byte_clk | ||||
9.524 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
11.795 | 2.271 | tNET | RR | 1 | R26C31[0][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane1_cnt_0_s1/CLK |
11.760 | -0.035 | tSu | 1 | R26C31[0][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane1_cnt_0_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 9.524 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 0.555, 24.164%; route: 1.510, 65.736%; tC2Q: 0.232, 10.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path6
Path Summary:
Slack | 7.192 |
Data Arrival Time | 4.568 |
Data Required Time | 11.760 |
From | hsrx_en_s0 |
To | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane1_cnt_1_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
2.271 | 2.271 | tNET | RR | 1 | R17C18[2][A] | hsrx_en_s0/CLK |
2.503 | 0.232 | tC2Q | RF | 1 | R17C18[2][A] | hsrx_en_s0/Q |
2.656 | 0.153 | tNET | FF | 1 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/I1 |
3.211 | 0.555 | tINS | FF | 469 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/F |
4.568 | 1.357 | tNET | FF | 1 | R26C31[0][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane1_cnt_1_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.524 | 9.524 | active clock edge time | ||||
9.524 | 0.000 | byte_clk | ||||
9.524 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
11.795 | 2.271 | tNET | RR | 1 | R26C31[0][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane1_cnt_1_s1/CLK |
11.760 | -0.035 | tSu | 1 | R26C31[0][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane1_cnt_1_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 9.524 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 0.555, 24.164%; route: 1.510, 65.736%; tC2Q: 0.232, 10.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path7
Path Summary:
Slack | 7.192 |
Data Arrival Time | 4.568 |
Data Required Time | 11.760 |
From | hsrx_en_s0 |
To | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane0_cnt_0_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
2.271 | 2.271 | tNET | RR | 1 | R17C18[2][A] | hsrx_en_s0/CLK |
2.503 | 0.232 | tC2Q | RF | 1 | R17C18[2][A] | hsrx_en_s0/Q |
2.656 | 0.153 | tNET | FF | 1 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/I1 |
3.211 | 0.555 | tINS | FF | 469 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/F |
4.568 | 1.357 | tNET | FF | 1 | R25C26[0][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane0_cnt_0_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.524 | 9.524 | active clock edge time | ||||
9.524 | 0.000 | byte_clk | ||||
9.524 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
11.795 | 2.271 | tNET | RR | 1 | R25C26[0][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane0_cnt_0_s1/CLK |
11.760 | -0.035 | tSu | 1 | R25C26[0][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane0_cnt_0_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 9.524 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 0.555, 24.164%; route: 1.510, 65.736%; tC2Q: 0.232, 10.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path8
Path Summary:
Slack | 7.192 |
Data Arrival Time | 4.568 |
Data Required Time | 11.760 |
From | hsrx_en_s0 |
To | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane0_cnt_1_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
2.271 | 2.271 | tNET | RR | 1 | R17C18[2][A] | hsrx_en_s0/CLK |
2.503 | 0.232 | tC2Q | RF | 1 | R17C18[2][A] | hsrx_en_s0/Q |
2.656 | 0.153 | tNET | FF | 1 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/I1 |
3.211 | 0.555 | tINS | FF | 469 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/F |
4.568 | 1.357 | tNET | FF | 1 | R25C26[0][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane0_cnt_1_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.524 | 9.524 | active clock edge time | ||||
9.524 | 0.000 | byte_clk | ||||
9.524 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
11.795 | 2.271 | tNET | RR | 1 | R25C26[0][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane0_cnt_1_s1/CLK |
11.760 | -0.035 | tSu | 1 | R25C26[0][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane0_cnt_1_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 9.524 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 0.555, 24.164%; route: 1.510, 65.736%; tC2Q: 0.232, 10.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path9
Path Summary:
Slack | 7.192 |
Data Arrival Time | 4.568 |
Data Required Time | 11.760 |
From | hsrx_en_s0 |
To | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/q_in0_0_7_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
2.271 | 2.271 | tNET | RR | 1 | R17C18[2][A] | hsrx_en_s0/CLK |
2.503 | 0.232 | tC2Q | RF | 1 | R17C18[2][A] | hsrx_en_s0/Q |
2.656 | 0.153 | tNET | FF | 1 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/I1 |
3.211 | 0.555 | tINS | FF | 469 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/F |
4.568 | 1.357 | tNET | FF | 1 | R18C19[1][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/q_in0_0_7_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.524 | 9.524 | active clock edge time | ||||
9.524 | 0.000 | byte_clk | ||||
9.524 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
11.795 | 2.271 | tNET | RR | 1 | R18C19[1][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/q_in0_0_7_s0/CLK |
11.760 | -0.035 | tSu | 1 | R18C19[1][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/q_in0_0_7_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 9.524 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 0.555, 24.164%; route: 1.510, 65.736%; tC2Q: 0.232, 10.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path10
Path Summary:
Slack | 7.192 |
Data Arrival Time | 4.568 |
Data Required Time | 11.760 |
From | hsrx_en_s0 |
To | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_align_data_0_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
2.271 | 2.271 | tNET | RR | 1 | R17C18[2][A] | hsrx_en_s0/CLK |
2.503 | 0.232 | tC2Q | RF | 1 | R17C18[2][A] | hsrx_en_s0/Q |
2.656 | 0.153 | tNET | FF | 1 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/I1 |
3.211 | 0.555 | tINS | FF | 469 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/F |
4.568 | 1.357 | tNET | FF | 1 | R22C29[1][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_align_data_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.524 | 9.524 | active clock edge time | ||||
9.524 | 0.000 | byte_clk | ||||
9.524 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
11.795 | 2.271 | tNET | RR | 1 | R22C29[1][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_align_data_0_s0/CLK |
11.760 | -0.035 | tSu | 1 | R22C29[1][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_align_data_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 9.524 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 0.555, 24.164%; route: 1.510, 65.736%; tC2Q: 0.232, 10.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path11
Path Summary:
Slack | 7.192 |
Data Arrival Time | 4.568 |
Data Required Time | 11.760 |
From | hsrx_en_s0 |
To | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_align_data_1_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
2.271 | 2.271 | tNET | RR | 1 | R17C18[2][A] | hsrx_en_s0/CLK |
2.503 | 0.232 | tC2Q | RF | 1 | R17C18[2][A] | hsrx_en_s0/Q |
2.656 | 0.153 | tNET | FF | 1 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/I1 |
3.211 | 0.555 | tINS | FF | 469 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/F |
4.568 | 1.357 | tNET | FF | 1 | R24C29[2][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_align_data_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.524 | 9.524 | active clock edge time | ||||
9.524 | 0.000 | byte_clk | ||||
9.524 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
11.795 | 2.271 | tNET | RR | 1 | R24C29[2][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_align_data_1_s0/CLK |
11.760 | -0.035 | tSu | 1 | R24C29[2][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_align_data_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 9.524 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 0.555, 24.164%; route: 1.510, 65.736%; tC2Q: 0.232, 10.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path12
Path Summary:
Slack | 7.192 |
Data Arrival Time | 4.568 |
Data Required Time | 11.760 |
From | hsrx_en_s0 |
To | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_align_data_2_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
2.271 | 2.271 | tNET | RR | 1 | R17C18[2][A] | hsrx_en_s0/CLK |
2.503 | 0.232 | tC2Q | RF | 1 | R17C18[2][A] | hsrx_en_s0/Q |
2.656 | 0.153 | tNET | FF | 1 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/I1 |
3.211 | 0.555 | tINS | FF | 469 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/F |
4.568 | 1.357 | tNET | FF | 1 | R22C29[0][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_align_data_2_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.524 | 9.524 | active clock edge time | ||||
9.524 | 0.000 | byte_clk | ||||
9.524 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
11.795 | 2.271 | tNET | RR | 1 | R22C29[0][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_align_data_2_s0/CLK |
11.760 | -0.035 | tSu | 1 | R22C29[0][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_align_data_2_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 9.524 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 0.555, 24.164%; route: 1.510, 65.736%; tC2Q: 0.232, 10.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path13
Path Summary:
Slack | 7.192 |
Data Arrival Time | 4.568 |
Data Required Time | 11.760 |
From | hsrx_en_s0 |
To | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_align_data_3_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
2.271 | 2.271 | tNET | RR | 1 | R17C18[2][A] | hsrx_en_s0/CLK |
2.503 | 0.232 | tC2Q | RF | 1 | R17C18[2][A] | hsrx_en_s0/Q |
2.656 | 0.153 | tNET | FF | 1 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/I1 |
3.211 | 0.555 | tINS | FF | 469 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/F |
4.568 | 1.357 | tNET | FF | 1 | R22C30[1][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_align_data_3_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.524 | 9.524 | active clock edge time | ||||
9.524 | 0.000 | byte_clk | ||||
9.524 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
11.795 | 2.271 | tNET | RR | 1 | R22C30[1][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_align_data_3_s0/CLK |
11.760 | -0.035 | tSu | 1 | R22C30[1][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_align_data_3_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 9.524 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 0.555, 24.164%; route: 1.510, 65.736%; tC2Q: 0.232, 10.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path14
Path Summary:
Slack | 7.192 |
Data Arrival Time | 4.568 |
Data Required Time | 11.760 |
From | hsrx_en_s0 |
To | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_align_data_4_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
2.271 | 2.271 | tNET | RR | 1 | R17C18[2][A] | hsrx_en_s0/CLK |
2.503 | 0.232 | tC2Q | RF | 1 | R17C18[2][A] | hsrx_en_s0/Q |
2.656 | 0.153 | tNET | FF | 1 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/I1 |
3.211 | 0.555 | tINS | FF | 469 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/F |
4.568 | 1.357 | tNET | FF | 1 | R24C30[2][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_align_data_4_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.524 | 9.524 | active clock edge time | ||||
9.524 | 0.000 | byte_clk | ||||
9.524 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
11.795 | 2.271 | tNET | RR | 1 | R24C30[2][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_align_data_4_s0/CLK |
11.760 | -0.035 | tSu | 1 | R24C30[2][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_align_data_4_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 9.524 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 0.555, 24.164%; route: 1.510, 65.736%; tC2Q: 0.232, 10.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path15
Path Summary:
Slack | 7.192 |
Data Arrival Time | 4.568 |
Data Required Time | 11.760 |
From | hsrx_en_s0 |
To | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_align_data_5_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
2.271 | 2.271 | tNET | RR | 1 | R17C18[2][A] | hsrx_en_s0/CLK |
2.503 | 0.232 | tC2Q | RF | 1 | R17C18[2][A] | hsrx_en_s0/Q |
2.656 | 0.153 | tNET | FF | 1 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/I1 |
3.211 | 0.555 | tINS | FF | 469 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/F |
4.568 | 1.357 | tNET | FF | 1 | R24C30[0][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_align_data_5_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.524 | 9.524 | active clock edge time | ||||
9.524 | 0.000 | byte_clk | ||||
9.524 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
11.795 | 2.271 | tNET | RR | 1 | R24C30[0][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_align_data_5_s0/CLK |
11.760 | -0.035 | tSu | 1 | R24C30[0][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_align_data_5_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 9.524 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 0.555, 24.164%; route: 1.510, 65.736%; tC2Q: 0.232, 10.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path16
Path Summary:
Slack | 7.192 |
Data Arrival Time | 4.568 |
Data Required Time | 11.760 |
From | hsrx_en_s0 |
To | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_align_data_6_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
2.271 | 2.271 | tNET | RR | 1 | R17C18[2][A] | hsrx_en_s0/CLK |
2.503 | 0.232 | tC2Q | RF | 1 | R17C18[2][A] | hsrx_en_s0/Q |
2.656 | 0.153 | tNET | FF | 1 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/I1 |
3.211 | 0.555 | tINS | FF | 469 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/F |
4.568 | 1.357 | tNET | FF | 1 | R22C31[0][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_align_data_6_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.524 | 9.524 | active clock edge time | ||||
9.524 | 0.000 | byte_clk | ||||
9.524 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
11.795 | 2.271 | tNET | RR | 1 | R22C31[0][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_align_data_6_s0/CLK |
11.760 | -0.035 | tSu | 1 | R22C31[0][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_align_data_6_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 9.524 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 0.555, 24.164%; route: 1.510, 65.736%; tC2Q: 0.232, 10.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path17
Path Summary:
Slack | 7.192 |
Data Arrival Time | 4.568 |
Data Required Time | 11.760 |
From | hsrx_en_s0 |
To | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_align_data_7_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
2.271 | 2.271 | tNET | RR | 1 | R17C18[2][A] | hsrx_en_s0/CLK |
2.503 | 0.232 | tC2Q | RF | 1 | R17C18[2][A] | hsrx_en_s0/Q |
2.656 | 0.153 | tNET | FF | 1 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/I1 |
3.211 | 0.555 | tINS | FF | 469 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/F |
4.568 | 1.357 | tNET | FF | 1 | R23C29[1][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_align_data_7_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.524 | 9.524 | active clock edge time | ||||
9.524 | 0.000 | byte_clk | ||||
9.524 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
11.795 | 2.271 | tNET | RR | 1 | R23C29[1][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_align_data_7_s0/CLK |
11.760 | -0.035 | tSu | 1 | R23C29[1][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_align_data_7_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 9.524 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 0.555, 24.164%; route: 1.510, 65.736%; tC2Q: 0.232, 10.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path18
Path Summary:
Slack | 7.192 |
Data Arrival Time | 4.568 |
Data Required Time | 11.760 |
From | hsrx_en_s0 |
To | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_align_data_0_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
2.271 | 2.271 | tNET | RR | 1 | R17C18[2][A] | hsrx_en_s0/CLK |
2.503 | 0.232 | tC2Q | RF | 1 | R17C18[2][A] | hsrx_en_s0/Q |
2.656 | 0.153 | tNET | FF | 1 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/I1 |
3.211 | 0.555 | tINS | FF | 469 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/F |
4.568 | 1.357 | tNET | FF | 1 | R27C26[1][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_align_data_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.524 | 9.524 | active clock edge time | ||||
9.524 | 0.000 | byte_clk | ||||
9.524 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
11.795 | 2.271 | tNET | RR | 1 | R27C26[1][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_align_data_0_s0/CLK |
11.760 | -0.035 | tSu | 1 | R27C26[1][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_align_data_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 9.524 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 0.555, 24.164%; route: 1.510, 65.736%; tC2Q: 0.232, 10.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path19
Path Summary:
Slack | 7.192 |
Data Arrival Time | 4.568 |
Data Required Time | 11.760 |
From | hsrx_en_s0 |
To | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_align_data_1_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
2.271 | 2.271 | tNET | RR | 1 | R17C18[2][A] | hsrx_en_s0/CLK |
2.503 | 0.232 | tC2Q | RF | 1 | R17C18[2][A] | hsrx_en_s0/Q |
2.656 | 0.153 | tNET | FF | 1 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/I1 |
3.211 | 0.555 | tINS | FF | 469 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/F |
4.568 | 1.357 | tNET | FF | 1 | R27C26[0][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_align_data_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.524 | 9.524 | active clock edge time | ||||
9.524 | 0.000 | byte_clk | ||||
9.524 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
11.795 | 2.271 | tNET | RR | 1 | R27C26[0][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_align_data_1_s0/CLK |
11.760 | -0.035 | tSu | 1 | R27C26[0][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_align_data_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 9.524 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 0.555, 24.164%; route: 1.510, 65.736%; tC2Q: 0.232, 10.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path20
Path Summary:
Slack | 7.192 |
Data Arrival Time | 4.568 |
Data Required Time | 11.760 |
From | hsrx_en_s0 |
To | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_align_data_2_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
2.271 | 2.271 | tNET | RR | 1 | R17C18[2][A] | hsrx_en_s0/CLK |
2.503 | 0.232 | tC2Q | RF | 1 | R17C18[2][A] | hsrx_en_s0/Q |
2.656 | 0.153 | tNET | FF | 1 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/I1 |
3.211 | 0.555 | tINS | FF | 469 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/F |
4.568 | 1.357 | tNET | FF | 1 | R27C27[0][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_align_data_2_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.524 | 9.524 | active clock edge time | ||||
9.524 | 0.000 | byte_clk | ||||
9.524 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
11.795 | 2.271 | tNET | RR | 1 | R27C27[0][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_align_data_2_s0/CLK |
11.760 | -0.035 | tSu | 1 | R27C27[0][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_align_data_2_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 9.524 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 0.555, 24.164%; route: 1.510, 65.736%; tC2Q: 0.232, 10.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path21
Path Summary:
Slack | 7.192 |
Data Arrival Time | 4.568 |
Data Required Time | 11.760 |
From | hsrx_en_s0 |
To | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_align_data_3_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
2.271 | 2.271 | tNET | RR | 1 | R17C18[2][A] | hsrx_en_s0/CLK |
2.503 | 0.232 | tC2Q | RF | 1 | R17C18[2][A] | hsrx_en_s0/Q |
2.656 | 0.153 | tNET | FF | 1 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/I1 |
3.211 | 0.555 | tINS | FF | 469 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/F |
4.568 | 1.357 | tNET | FF | 1 | R27C27[0][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_align_data_3_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.524 | 9.524 | active clock edge time | ||||
9.524 | 0.000 | byte_clk | ||||
9.524 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
11.795 | 2.271 | tNET | RR | 1 | R27C27[0][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_align_data_3_s0/CLK |
11.760 | -0.035 | tSu | 1 | R27C27[0][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_align_data_3_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 9.524 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 0.555, 24.164%; route: 1.510, 65.736%; tC2Q: 0.232, 10.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path22
Path Summary:
Slack | 7.192 |
Data Arrival Time | 4.568 |
Data Required Time | 11.760 |
From | hsrx_en_s0 |
To | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_align_data_4_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
2.271 | 2.271 | tNET | RR | 1 | R17C18[2][A] | hsrx_en_s0/CLK |
2.503 | 0.232 | tC2Q | RF | 1 | R17C18[2][A] | hsrx_en_s0/Q |
2.656 | 0.153 | tNET | FF | 1 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/I1 |
3.211 | 0.555 | tINS | FF | 469 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/F |
4.568 | 1.357 | tNET | FF | 1 | R27C29[0][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_align_data_4_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.524 | 9.524 | active clock edge time | ||||
9.524 | 0.000 | byte_clk | ||||
9.524 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
11.795 | 2.271 | tNET | RR | 1 | R27C29[0][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_align_data_4_s0/CLK |
11.760 | -0.035 | tSu | 1 | R27C29[0][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_align_data_4_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 9.524 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 0.555, 24.164%; route: 1.510, 65.736%; tC2Q: 0.232, 10.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path23
Path Summary:
Slack | 7.192 |
Data Arrival Time | 4.568 |
Data Required Time | 11.760 |
From | hsrx_en_s0 |
To | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_align_data_5_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
2.271 | 2.271 | tNET | RR | 1 | R17C18[2][A] | hsrx_en_s0/CLK |
2.503 | 0.232 | tC2Q | RF | 1 | R17C18[2][A] | hsrx_en_s0/Q |
2.656 | 0.153 | tNET | FF | 1 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/I1 |
3.211 | 0.555 | tINS | FF | 469 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/F |
4.568 | 1.357 | tNET | FF | 1 | R27C26[0][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_align_data_5_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.524 | 9.524 | active clock edge time | ||||
9.524 | 0.000 | byte_clk | ||||
9.524 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
11.795 | 2.271 | tNET | RR | 1 | R27C26[0][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_align_data_5_s0/CLK |
11.760 | -0.035 | tSu | 1 | R27C26[0][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_align_data_5_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 9.524 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 0.555, 24.164%; route: 1.510, 65.736%; tC2Q: 0.232, 10.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path24
Path Summary:
Slack | 7.192 |
Data Arrival Time | 4.568 |
Data Required Time | 11.760 |
From | hsrx_en_s0 |
To | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_align_data_6_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
2.271 | 2.271 | tNET | RR | 1 | R17C18[2][A] | hsrx_en_s0/CLK |
2.503 | 0.232 | tC2Q | RF | 1 | R17C18[2][A] | hsrx_en_s0/Q |
2.656 | 0.153 | tNET | FF | 1 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/I1 |
3.211 | 0.555 | tINS | FF | 469 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/F |
4.568 | 1.357 | tNET | FF | 1 | R27C28[2][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_align_data_6_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.524 | 9.524 | active clock edge time | ||||
9.524 | 0.000 | byte_clk | ||||
9.524 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
11.795 | 2.271 | tNET | RR | 1 | R27C28[2][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_align_data_6_s0/CLK |
11.760 | -0.035 | tSu | 1 | R27C28[2][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_align_data_6_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 9.524 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 0.555, 24.164%; route: 1.510, 65.736%; tC2Q: 0.232, 10.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path25
Path Summary:
Slack | 7.192 |
Data Arrival Time | 4.568 |
Data Required Time | 11.760 |
From | hsrx_en_s0 |
To | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_align_data_7_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
2.271 | 2.271 | tNET | RR | 1 | R17C18[2][A] | hsrx_en_s0/CLK |
2.503 | 0.232 | tC2Q | RF | 1 | R17C18[2][A] | hsrx_en_s0/Q |
2.656 | 0.153 | tNET | FF | 1 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/I1 |
3.211 | 0.555 | tINS | FF | 469 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/F |
4.568 | 1.357 | tNET | FF | 1 | R27C27[1][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_align_data_7_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.524 | 9.524 | active clock edge time | ||||
9.524 | 0.000 | byte_clk | ||||
9.524 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
11.795 | 2.271 | tNET | RR | 1 | R27C27[1][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_align_data_7_s0/CLK |
11.760 | -0.035 | tSu | 1 | R27C27[1][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_align_data_7_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 9.524 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 0.555, 24.164%; route: 1.510, 65.736%; tC2Q: 0.232, 10.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Removal Analysis Report
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 1.581 |
Data Arrival Time | 3.103 |
Data Required Time | 1.522 |
From | hsrx_en_s0 |
To | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_cnt_0_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R17C18[2][A] | hsrx_en_s0/CLK |
1.712 | 0.201 | tC2Q | RF | 1 | R17C18[2][A] | hsrx_en_s0/Q |
1.829 | 0.117 | tNET | FF | 1 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/I1 |
2.220 | 0.391 | tINS | FR | 469 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/F |
3.103 | 0.883 | tNET | RR | 1 | R22C32[1][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_cnt_0_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R22C32[1][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_cnt_0_s1/CLK |
1.522 | 0.011 | tHld | 1 | R22C32[1][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_cnt_0_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.391, 24.560%; route: 1.000, 62.814%; tC2Q: 0.201, 12.626% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path2
Path Summary:
Slack | 1.581 |
Data Arrival Time | 3.103 |
Data Required Time | 1.522 |
From | hsrx_en_s0 |
To | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_cnt_1_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R17C18[2][A] | hsrx_en_s0/CLK |
1.712 | 0.201 | tC2Q | RF | 1 | R17C18[2][A] | hsrx_en_s0/Q |
1.829 | 0.117 | tNET | FF | 1 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/I1 |
2.220 | 0.391 | tINS | FR | 469 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/F |
3.103 | 0.883 | tNET | RR | 1 | R22C32[1][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_cnt_1_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R22C32[1][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_cnt_1_s1/CLK |
1.522 | 0.011 | tHld | 1 | R22C32[1][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_cnt_1_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.391, 24.560%; route: 1.000, 62.814%; tC2Q: 0.201, 12.626% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path3
Path Summary:
Slack | 1.581 |
Data Arrival Time | 3.103 |
Data Required Time | 1.522 |
From | hsrx_en_s0 |
To | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_cnt_0_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R17C18[2][A] | hsrx_en_s0/CLK |
1.712 | 0.201 | tC2Q | RF | 1 | R17C18[2][A] | hsrx_en_s0/Q |
1.829 | 0.117 | tNET | FF | 1 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/I1 |
2.220 | 0.391 | tINS | FR | 469 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/F |
3.103 | 0.883 | tNET | RR | 1 | R27C26[2][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_cnt_0_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R27C26[2][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_cnt_0_s1/CLK |
1.522 | 0.011 | tHld | 1 | R27C26[2][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_cnt_0_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.391, 24.560%; route: 1.000, 62.814%; tC2Q: 0.201, 12.626% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path4
Path Summary:
Slack | 1.581 |
Data Arrival Time | 3.103 |
Data Required Time | 1.522 |
From | hsrx_en_s0 |
To | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_cnt_1_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R17C18[2][A] | hsrx_en_s0/CLK |
1.712 | 0.201 | tC2Q | RF | 1 | R17C18[2][A] | hsrx_en_s0/Q |
1.829 | 0.117 | tNET | FF | 1 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/I1 |
2.220 | 0.391 | tINS | FR | 469 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/F |
3.103 | 0.883 | tNET | RR | 1 | R27C29[0][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_cnt_1_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R27C29[0][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_cnt_1_s1/CLK |
1.522 | 0.011 | tHld | 1 | R27C29[0][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_cnt_1_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.391, 24.560%; route: 1.000, 62.814%; tC2Q: 0.201, 12.626% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path5
Path Summary:
Slack | 1.581 |
Data Arrival Time | 3.103 |
Data Required Time | 1.522 |
From | hsrx_en_s0 |
To | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane1_cnt_0_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R17C18[2][A] | hsrx_en_s0/CLK |
1.712 | 0.201 | tC2Q | RF | 1 | R17C18[2][A] | hsrx_en_s0/Q |
1.829 | 0.117 | tNET | FF | 1 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/I1 |
2.220 | 0.391 | tINS | FR | 469 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/F |
3.103 | 0.883 | tNET | RR | 1 | R26C31[0][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane1_cnt_0_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R26C31[0][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane1_cnt_0_s1/CLK |
1.522 | 0.011 | tHld | 1 | R26C31[0][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane1_cnt_0_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.391, 24.560%; route: 1.000, 62.814%; tC2Q: 0.201, 12.626% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path6
Path Summary:
Slack | 1.581 |
Data Arrival Time | 3.103 |
Data Required Time | 1.522 |
From | hsrx_en_s0 |
To | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane1_cnt_1_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R17C18[2][A] | hsrx_en_s0/CLK |
1.712 | 0.201 | tC2Q | RF | 1 | R17C18[2][A] | hsrx_en_s0/Q |
1.829 | 0.117 | tNET | FF | 1 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/I1 |
2.220 | 0.391 | tINS | FR | 469 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/F |
3.103 | 0.883 | tNET | RR | 1 | R26C31[0][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane1_cnt_1_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R26C31[0][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane1_cnt_1_s1/CLK |
1.522 | 0.011 | tHld | 1 | R26C31[0][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane1_cnt_1_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.391, 24.560%; route: 1.000, 62.814%; tC2Q: 0.201, 12.626% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path7
Path Summary:
Slack | 1.581 |
Data Arrival Time | 3.103 |
Data Required Time | 1.522 |
From | hsrx_en_s0 |
To | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane0_cnt_0_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R17C18[2][A] | hsrx_en_s0/CLK |
1.712 | 0.201 | tC2Q | RF | 1 | R17C18[2][A] | hsrx_en_s0/Q |
1.829 | 0.117 | tNET | FF | 1 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/I1 |
2.220 | 0.391 | tINS | FR | 469 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/F |
3.103 | 0.883 | tNET | RR | 1 | R25C26[0][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane0_cnt_0_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R25C26[0][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane0_cnt_0_s1/CLK |
1.522 | 0.011 | tHld | 1 | R25C26[0][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane0_cnt_0_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.391, 24.560%; route: 1.000, 62.814%; tC2Q: 0.201, 12.626% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path8
Path Summary:
Slack | 1.581 |
Data Arrival Time | 3.103 |
Data Required Time | 1.522 |
From | hsrx_en_s0 |
To | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane0_cnt_1_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R17C18[2][A] | hsrx_en_s0/CLK |
1.712 | 0.201 | tC2Q | RF | 1 | R17C18[2][A] | hsrx_en_s0/Q |
1.829 | 0.117 | tNET | FF | 1 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/I1 |
2.220 | 0.391 | tINS | FR | 469 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/F |
3.103 | 0.883 | tNET | RR | 1 | R25C26[0][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane0_cnt_1_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R25C26[0][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane0_cnt_1_s1/CLK |
1.522 | 0.011 | tHld | 1 | R25C26[0][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane0_cnt_1_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.391, 24.560%; route: 1.000, 62.814%; tC2Q: 0.201, 12.626% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path9
Path Summary:
Slack | 1.581 |
Data Arrival Time | 3.103 |
Data Required Time | 1.522 |
From | hsrx_en_s0 |
To | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/q_in0_0_7_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R17C18[2][A] | hsrx_en_s0/CLK |
1.712 | 0.201 | tC2Q | RF | 1 | R17C18[2][A] | hsrx_en_s0/Q |
1.829 | 0.117 | tNET | FF | 1 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/I1 |
2.220 | 0.391 | tINS | FR | 469 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/F |
3.103 | 0.883 | tNET | RR | 1 | R18C19[1][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/q_in0_0_7_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R18C19[1][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/q_in0_0_7_s0/CLK |
1.522 | 0.011 | tHld | 1 | R18C19[1][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/q_in0_0_7_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.391, 24.560%; route: 1.000, 62.814%; tC2Q: 0.201, 12.626% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path10
Path Summary:
Slack | 1.581 |
Data Arrival Time | 3.103 |
Data Required Time | 1.522 |
From | hsrx_en_s0 |
To | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_align_data_0_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R17C18[2][A] | hsrx_en_s0/CLK |
1.712 | 0.201 | tC2Q | RF | 1 | R17C18[2][A] | hsrx_en_s0/Q |
1.829 | 0.117 | tNET | FF | 1 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/I1 |
2.220 | 0.391 | tINS | FR | 469 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/F |
3.103 | 0.883 | tNET | RR | 1 | R22C29[1][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_align_data_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R22C29[1][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_align_data_0_s0/CLK |
1.522 | 0.011 | tHld | 1 | R22C29[1][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_align_data_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.391, 24.560%; route: 1.000, 62.814%; tC2Q: 0.201, 12.626% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path11
Path Summary:
Slack | 1.581 |
Data Arrival Time | 3.103 |
Data Required Time | 1.522 |
From | hsrx_en_s0 |
To | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_align_data_1_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R17C18[2][A] | hsrx_en_s0/CLK |
1.712 | 0.201 | tC2Q | RF | 1 | R17C18[2][A] | hsrx_en_s0/Q |
1.829 | 0.117 | tNET | FF | 1 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/I1 |
2.220 | 0.391 | tINS | FR | 469 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/F |
3.103 | 0.883 | tNET | RR | 1 | R24C29[2][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_align_data_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R24C29[2][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_align_data_1_s0/CLK |
1.522 | 0.011 | tHld | 1 | R24C29[2][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_align_data_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.391, 24.560%; route: 1.000, 62.814%; tC2Q: 0.201, 12.626% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path12
Path Summary:
Slack | 1.581 |
Data Arrival Time | 3.103 |
Data Required Time | 1.522 |
From | hsrx_en_s0 |
To | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_align_data_2_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R17C18[2][A] | hsrx_en_s0/CLK |
1.712 | 0.201 | tC2Q | RF | 1 | R17C18[2][A] | hsrx_en_s0/Q |
1.829 | 0.117 | tNET | FF | 1 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/I1 |
2.220 | 0.391 | tINS | FR | 469 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/F |
3.103 | 0.883 | tNET | RR | 1 | R22C29[0][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_align_data_2_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R22C29[0][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_align_data_2_s0/CLK |
1.522 | 0.011 | tHld | 1 | R22C29[0][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_align_data_2_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.391, 24.560%; route: 1.000, 62.814%; tC2Q: 0.201, 12.626% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path13
Path Summary:
Slack | 1.581 |
Data Arrival Time | 3.103 |
Data Required Time | 1.522 |
From | hsrx_en_s0 |
To | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_align_data_3_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R17C18[2][A] | hsrx_en_s0/CLK |
1.712 | 0.201 | tC2Q | RF | 1 | R17C18[2][A] | hsrx_en_s0/Q |
1.829 | 0.117 | tNET | FF | 1 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/I1 |
2.220 | 0.391 | tINS | FR | 469 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/F |
3.103 | 0.883 | tNET | RR | 1 | R22C30[1][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_align_data_3_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R22C30[1][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_align_data_3_s0/CLK |
1.522 | 0.011 | tHld | 1 | R22C30[1][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_align_data_3_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.391, 24.560%; route: 1.000, 62.814%; tC2Q: 0.201, 12.626% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path14
Path Summary:
Slack | 1.581 |
Data Arrival Time | 3.103 |
Data Required Time | 1.522 |
From | hsrx_en_s0 |
To | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_align_data_4_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R17C18[2][A] | hsrx_en_s0/CLK |
1.712 | 0.201 | tC2Q | RF | 1 | R17C18[2][A] | hsrx_en_s0/Q |
1.829 | 0.117 | tNET | FF | 1 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/I1 |
2.220 | 0.391 | tINS | FR | 469 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/F |
3.103 | 0.883 | tNET | RR | 1 | R24C30[2][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_align_data_4_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R24C30[2][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_align_data_4_s0/CLK |
1.522 | 0.011 | tHld | 1 | R24C30[2][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_align_data_4_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.391, 24.560%; route: 1.000, 62.814%; tC2Q: 0.201, 12.626% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path15
Path Summary:
Slack | 1.581 |
Data Arrival Time | 3.103 |
Data Required Time | 1.522 |
From | hsrx_en_s0 |
To | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_align_data_5_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R17C18[2][A] | hsrx_en_s0/CLK |
1.712 | 0.201 | tC2Q | RF | 1 | R17C18[2][A] | hsrx_en_s0/Q |
1.829 | 0.117 | tNET | FF | 1 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/I1 |
2.220 | 0.391 | tINS | FR | 469 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/F |
3.103 | 0.883 | tNET | RR | 1 | R24C30[0][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_align_data_5_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R24C30[0][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_align_data_5_s0/CLK |
1.522 | 0.011 | tHld | 1 | R24C30[0][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_align_data_5_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.391, 24.560%; route: 1.000, 62.814%; tC2Q: 0.201, 12.626% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path16
Path Summary:
Slack | 1.581 |
Data Arrival Time | 3.103 |
Data Required Time | 1.522 |
From | hsrx_en_s0 |
To | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_align_data_6_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R17C18[2][A] | hsrx_en_s0/CLK |
1.712 | 0.201 | tC2Q | RF | 1 | R17C18[2][A] | hsrx_en_s0/Q |
1.829 | 0.117 | tNET | FF | 1 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/I1 |
2.220 | 0.391 | tINS | FR | 469 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/F |
3.103 | 0.883 | tNET | RR | 1 | R22C31[0][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_align_data_6_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R22C31[0][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_align_data_6_s0/CLK |
1.522 | 0.011 | tHld | 1 | R22C31[0][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_align_data_6_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.391, 24.560%; route: 1.000, 62.814%; tC2Q: 0.201, 12.626% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path17
Path Summary:
Slack | 1.581 |
Data Arrival Time | 3.103 |
Data Required Time | 1.522 |
From | hsrx_en_s0 |
To | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_align_data_7_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R17C18[2][A] | hsrx_en_s0/CLK |
1.712 | 0.201 | tC2Q | RF | 1 | R17C18[2][A] | hsrx_en_s0/Q |
1.829 | 0.117 | tNET | FF | 1 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/I1 |
2.220 | 0.391 | tINS | FR | 469 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/F |
3.103 | 0.883 | tNET | RR | 1 | R23C29[1][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_align_data_7_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R23C29[1][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_align_data_7_s0/CLK |
1.522 | 0.011 | tHld | 1 | R23C29[1][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane3_align_data_7_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.391, 24.560%; route: 1.000, 62.814%; tC2Q: 0.201, 12.626% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path18
Path Summary:
Slack | 1.581 |
Data Arrival Time | 3.103 |
Data Required Time | 1.522 |
From | hsrx_en_s0 |
To | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_align_data_0_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R17C18[2][A] | hsrx_en_s0/CLK |
1.712 | 0.201 | tC2Q | RF | 1 | R17C18[2][A] | hsrx_en_s0/Q |
1.829 | 0.117 | tNET | FF | 1 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/I1 |
2.220 | 0.391 | tINS | FR | 469 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/F |
3.103 | 0.883 | tNET | RR | 1 | R27C26[1][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_align_data_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R27C26[1][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_align_data_0_s0/CLK |
1.522 | 0.011 | tHld | 1 | R27C26[1][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_align_data_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.391, 24.560%; route: 1.000, 62.814%; tC2Q: 0.201, 12.626% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path19
Path Summary:
Slack | 1.581 |
Data Arrival Time | 3.103 |
Data Required Time | 1.522 |
From | hsrx_en_s0 |
To | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_align_data_1_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R17C18[2][A] | hsrx_en_s0/CLK |
1.712 | 0.201 | tC2Q | RF | 1 | R17C18[2][A] | hsrx_en_s0/Q |
1.829 | 0.117 | tNET | FF | 1 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/I1 |
2.220 | 0.391 | tINS | FR | 469 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/F |
3.103 | 0.883 | tNET | RR | 1 | R27C26[0][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_align_data_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R27C26[0][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_align_data_1_s0/CLK |
1.522 | 0.011 | tHld | 1 | R27C26[0][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_align_data_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.391, 24.560%; route: 1.000, 62.814%; tC2Q: 0.201, 12.626% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path20
Path Summary:
Slack | 1.581 |
Data Arrival Time | 3.103 |
Data Required Time | 1.522 |
From | hsrx_en_s0 |
To | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_align_data_2_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R17C18[2][A] | hsrx_en_s0/CLK |
1.712 | 0.201 | tC2Q | RF | 1 | R17C18[2][A] | hsrx_en_s0/Q |
1.829 | 0.117 | tNET | FF | 1 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/I1 |
2.220 | 0.391 | tINS | FR | 469 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/F |
3.103 | 0.883 | tNET | RR | 1 | R27C27[0][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_align_data_2_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R27C27[0][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_align_data_2_s0/CLK |
1.522 | 0.011 | tHld | 1 | R27C27[0][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_align_data_2_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.391, 24.560%; route: 1.000, 62.814%; tC2Q: 0.201, 12.626% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path21
Path Summary:
Slack | 1.581 |
Data Arrival Time | 3.103 |
Data Required Time | 1.522 |
From | hsrx_en_s0 |
To | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_align_data_3_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R17C18[2][A] | hsrx_en_s0/CLK |
1.712 | 0.201 | tC2Q | RF | 1 | R17C18[2][A] | hsrx_en_s0/Q |
1.829 | 0.117 | tNET | FF | 1 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/I1 |
2.220 | 0.391 | tINS | FR | 469 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/F |
3.103 | 0.883 | tNET | RR | 1 | R27C27[0][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_align_data_3_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R27C27[0][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_align_data_3_s0/CLK |
1.522 | 0.011 | tHld | 1 | R27C27[0][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_align_data_3_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.391, 24.560%; route: 1.000, 62.814%; tC2Q: 0.201, 12.626% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path22
Path Summary:
Slack | 1.581 |
Data Arrival Time | 3.103 |
Data Required Time | 1.522 |
From | hsrx_en_s0 |
To | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_align_data_4_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R17C18[2][A] | hsrx_en_s0/CLK |
1.712 | 0.201 | tC2Q | RF | 1 | R17C18[2][A] | hsrx_en_s0/Q |
1.829 | 0.117 | tNET | FF | 1 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/I1 |
2.220 | 0.391 | tINS | FR | 469 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/F |
3.103 | 0.883 | tNET | RR | 1 | R27C29[0][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_align_data_4_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R27C29[0][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_align_data_4_s0/CLK |
1.522 | 0.011 | tHld | 1 | R27C29[0][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_align_data_4_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.391, 24.560%; route: 1.000, 62.814%; tC2Q: 0.201, 12.626% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path23
Path Summary:
Slack | 1.581 |
Data Arrival Time | 3.103 |
Data Required Time | 1.522 |
From | hsrx_en_s0 |
To | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_align_data_5_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R17C18[2][A] | hsrx_en_s0/CLK |
1.712 | 0.201 | tC2Q | RF | 1 | R17C18[2][A] | hsrx_en_s0/Q |
1.829 | 0.117 | tNET | FF | 1 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/I1 |
2.220 | 0.391 | tINS | FR | 469 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/F |
3.103 | 0.883 | tNET | RR | 1 | R27C26[0][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_align_data_5_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R27C26[0][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_align_data_5_s0/CLK |
1.522 | 0.011 | tHld | 1 | R27C26[0][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_align_data_5_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.391, 24.560%; route: 1.000, 62.814%; tC2Q: 0.201, 12.626% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path24
Path Summary:
Slack | 1.581 |
Data Arrival Time | 3.103 |
Data Required Time | 1.522 |
From | hsrx_en_s0 |
To | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_align_data_6_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R17C18[2][A] | hsrx_en_s0/CLK |
1.712 | 0.201 | tC2Q | RF | 1 | R17C18[2][A] | hsrx_en_s0/Q |
1.829 | 0.117 | tNET | FF | 1 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/I1 |
2.220 | 0.391 | tINS | FR | 469 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/F |
3.103 | 0.883 | tNET | RR | 1 | R27C28[2][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_align_data_6_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R27C28[2][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_align_data_6_s0/CLK |
1.522 | 0.011 | tHld | 1 | R27C28[2][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_align_data_6_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.391, 24.560%; route: 1.000, 62.814%; tC2Q: 0.201, 12.626% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path25
Path Summary:
Slack | 1.581 |
Data Arrival Time | 3.103 |
Data Required Time | 1.522 |
From | hsrx_en_s0 |
To | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_align_data_7_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R17C18[2][A] | hsrx_en_s0/CLK |
1.712 | 0.201 | tC2Q | RF | 1 | R17C18[2][A] | hsrx_en_s0/Q |
1.829 | 0.117 | tNET | FF | 1 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/I1 |
2.220 | 0.391 | tINS | FR | 469 | R17C18[3][B] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/n22_s1/F |
3.103 | 0.883 | tNET | RR | 1 | R27C27[1][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_align_data_7_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1041 | TOPSIDE[0] | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
1.511 | 1.511 | tNET | RR | 1 | R27C27[1][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_align_data_7_s0/CLK |
1.522 | 0.011 | tHld | 1 | R27C27[1][A] | u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/lane2_align_data_7_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.391, 24.560%; route: 1.000, 62.814%; tC2Q: 0.201, 12.626% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Minimum Pulse Width Report:
Report Command:report_min_pulse_width -nworst 10 -detail
MPW1
MPW Summary:
Slack: | 1.808 |
Actual Width: | 2.808 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | lvds_pclk |
Objects: | u_extr/mem_rqout_r_23_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
3.571 | 0.000 | active clock edge time | ||
3.571 | 0.000 | lvds_pclk | ||
3.571 | 0.000 | tCL | FF | u_clk_div_3p5/CLKOUT |
5.846 | 2.274 | tNET | FF | u_extr/mem_rqout_r_23_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
7.143 | 0.000 | active clock edge time | ||
7.143 | 0.000 | lvds_pclk | ||
7.143 | 0.000 | tCL | RR | u_clk_div_3p5/CLKOUT |
8.654 | 1.511 | tNET | RR | u_extr/mem_rqout_r_23_s0/CLK |
MPW2
MPW Summary:
Slack: | 1.808 |
Actual Width: | 2.808 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | lvds_pclk |
Objects: | u_extr/mem_rqout_r_21_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
3.571 | 0.000 | active clock edge time | ||
3.571 | 0.000 | lvds_pclk | ||
3.571 | 0.000 | tCL | FF | u_clk_div_3p5/CLKOUT |
5.846 | 2.274 | tNET | FF | u_extr/mem_rqout_r_21_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
7.143 | 0.000 | active clock edge time | ||
7.143 | 0.000 | lvds_pclk | ||
7.143 | 0.000 | tCL | RR | u_clk_div_3p5/CLKOUT |
8.654 | 1.511 | tNET | RR | u_extr/mem_rqout_r_21_s0/CLK |
MPW3
MPW Summary:
Slack: | 1.808 |
Actual Width: | 2.808 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | lvds_pclk |
Objects: | u_extr/mem_rqout_r_17_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
3.571 | 0.000 | active clock edge time | ||
3.571 | 0.000 | lvds_pclk | ||
3.571 | 0.000 | tCL | FF | u_clk_div_3p5/CLKOUT |
5.846 | 2.274 | tNET | FF | u_extr/mem_rqout_r_17_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
7.143 | 0.000 | active clock edge time | ||
7.143 | 0.000 | lvds_pclk | ||
7.143 | 0.000 | tCL | RR | u_clk_div_3p5/CLKOUT |
8.654 | 1.511 | tNET | RR | u_extr/mem_rqout_r_17_s0/CLK |
MPW4
MPW Summary:
Slack: | 1.808 |
Actual Width: | 2.808 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | lvds_pclk |
Objects: | u_extr/mem_rqout_r_9_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
3.571 | 0.000 | active clock edge time | ||
3.571 | 0.000 | lvds_pclk | ||
3.571 | 0.000 | tCL | FF | u_clk_div_3p5/CLKOUT |
5.846 | 2.274 | tNET | FF | u_extr/mem_rqout_r_9_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
7.143 | 0.000 | active clock edge time | ||
7.143 | 0.000 | lvds_pclk | ||
7.143 | 0.000 | tCL | RR | u_clk_div_3p5/CLKOUT |
8.654 | 1.511 | tNET | RR | u_extr/mem_rqout_r_9_s0/CLK |
MPW5
MPW Summary:
Slack: | 1.808 |
Actual Width: | 2.808 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | lvds_pclk |
Objects: | u_extr/ohcnt_9_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
3.571 | 0.000 | active clock edge time | ||
3.571 | 0.000 | lvds_pclk | ||
3.571 | 0.000 | tCL | FF | u_clk_div_3p5/CLKOUT |
5.846 | 2.274 | tNET | FF | u_extr/ohcnt_9_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
7.143 | 0.000 | active clock edge time | ||
7.143 | 0.000 | lvds_pclk | ||
7.143 | 0.000 | tCL | RR | u_clk_div_3p5/CLKOUT |
8.654 | 1.511 | tNET | RR | u_extr/ohcnt_9_s0/CLK |
MPW6
MPW Summary:
Slack: | 1.808 |
Actual Width: | 2.808 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | lvds_pclk |
Objects: | u_extr/o_rgb_reg_21_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
3.571 | 0.000 | active clock edge time | ||
3.571 | 0.000 | lvds_pclk | ||
3.571 | 0.000 | tCL | FF | u_clk_div_3p5/CLKOUT |
5.846 | 2.274 | tNET | FF | u_extr/o_rgb_reg_21_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
7.143 | 0.000 | active clock edge time | ||
7.143 | 0.000 | lvds_pclk | ||
7.143 | 0.000 | tCL | RR | u_clk_div_3p5/CLKOUT |
8.654 | 1.511 | tNET | RR | u_extr/o_rgb_reg_21_s0/CLK |
MPW7
MPW Summary:
Slack: | 1.808 |
Actual Width: | 2.808 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | lvds_pclk |
Objects: | u_extr/o_rgb_reg_22_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
3.571 | 0.000 | active clock edge time | ||
3.571 | 0.000 | lvds_pclk | ||
3.571 | 0.000 | tCL | FF | u_clk_div_3p5/CLKOUT |
5.846 | 2.274 | tNET | FF | u_extr/o_rgb_reg_22_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
7.143 | 0.000 | active clock edge time | ||
7.143 | 0.000 | lvds_pclk | ||
7.143 | 0.000 | tCL | RR | u_clk_div_3p5/CLKOUT |
8.654 | 1.511 | tNET | RR | u_extr/o_rgb_reg_22_s0/CLK |
MPW8
MPW Summary:
Slack: | 1.808 |
Actual Width: | 2.808 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | lvds_pclk |
Objects: | u_extr/ohcnt_10_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
3.571 | 0.000 | active clock edge time | ||
3.571 | 0.000 | lvds_pclk | ||
3.571 | 0.000 | tCL | FF | u_clk_div_3p5/CLKOUT |
5.846 | 2.274 | tNET | FF | u_extr/ohcnt_10_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
7.143 | 0.000 | active clock edge time | ||
7.143 | 0.000 | lvds_pclk | ||
7.143 | 0.000 | tCL | RR | u_clk_div_3p5/CLKOUT |
8.654 | 1.511 | tNET | RR | u_extr/ohcnt_10_s0/CLK |
MPW9
MPW Summary:
Slack: | 1.808 |
Actual Width: | 2.808 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | lvds_pclk |
Objects: | u_extr/o_rgb_reg_23_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
3.571 | 0.000 | active clock edge time | ||
3.571 | 0.000 | lvds_pclk | ||
3.571 | 0.000 | tCL | FF | u_clk_div_3p5/CLKOUT |
5.846 | 2.274 | tNET | FF | u_extr/o_rgb_reg_23_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
7.143 | 0.000 | active clock edge time | ||
7.143 | 0.000 | lvds_pclk | ||
7.143 | 0.000 | tCL | RR | u_clk_div_3p5/CLKOUT |
8.654 | 1.511 | tNET | RR | u_extr/o_rgb_reg_23_s0/CLK |
MPW10
MPW Summary:
Slack: | 1.808 |
Actual Width: | 2.808 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | lvds_pclk |
Objects: | u_extr/o_de_reg_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
3.571 | 0.000 | active clock edge time | ||
3.571 | 0.000 | lvds_pclk | ||
3.571 | 0.000 | tCL | FF | u_clk_div_3p5/CLKOUT |
5.846 | 2.274 | tNET | FF | u_extr/o_de_reg_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
7.143 | 0.000 | active clock edge time | ||
7.143 | 0.000 | lvds_pclk | ||
7.143 | 0.000 | tCL | RR | u_clk_div_3p5/CLKOUT |
8.654 | 1.511 | tNET | RR | u_extr/o_de_reg_s0/CLK |
High Fanout Nets Report:
Report Command:report_high_fanout_nets -max_nets 10
FANOUT | NET NAME | WORST SLACK | MAX DELAY |
---|---|---|---|
1041 | byte_clk | 3.135 | 2.274 |
469 | n22_5 | 7.192 | 1.357 |
214 | pixel_clk | 2.949 | 2.274 |
120 | lvds_pclk | 3.035 | 2.274 |
97 | mid_offset[0] | 7.176 | 1.507 |
96 | n1393_9 | 6.237 | 1.348 |
80 | shift_en | 5.442 | 2.292 |
59 | wBufRd | 3.838 | 1.202 |
51 | mid_dv | 6.989 | 1.453 |
49 | mid_offset_1_11 | 6.300 | 1.128 |
Route Congestions Report:
Report Command:report_route_congestion -max_grids 10
GRID LOC | ROUTE CONGESTIONS |
---|---|
R22C34 | 86.11% |
R27C19 | 84.72% |
R18C29 | 84.72% |
R38C37 | 84.72% |
R22C30 | 84.72% |
R23C20 | 84.72% |
R30C35 | 84.72% |
R18C19 | 83.33% |
R30C34 | 83.33% |
R26C25 | 81.94% |
Timing Exceptions Report:
Setup Analysis Report
Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Hold Analysis Report
Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Recovery Analysis Report
Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Removal Analysis Report
Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Timing Constraints Report:
SDC Command Type | State | Detail Command |
---|---|---|
TC_CLOCK | Actived | create_clock -name mipi_clk -period 12 -waveform {0 6} [get_ports {HS_CLK_P}] |
TC_CLOCK | Actived | create_clock -name clk_50 -period 20 -waveform {0 10} [get_ports {OSC_50M}] |
TC_CLOCK | Actived | create_clock -name byte_clk -period 9.524 -waveform {0 4.762} [get_nets {byte_clk}] |
TC_GENERATED_CLOCK | Actived | create_generated_clock -name pixel_clk -source [get_nets {byte_clk}] -master_clock byte_clk -divide_by 3 -multiply_by 4 [get_nets {pixel_clk}] |
TC_GENERATED_CLOCK | Actived | create_generated_clock -name lvds_pclk -source [get_ports {OSC_50M}] -master_clock clk_50 -divide_by 5 -multiply_by 14 [get_nets {lvds_pclk}] |
TC_CLOCK_GROUP | Actived | set_clock_groups -exclusive -group [get_clocks {pixel_clk}] -group [get_clocks {byte_clk}] -group [get_clocks {clk_50}] -group [get_clocks {lvds_pclk}] -group [get_clocks {mipi_clk}] |