Hierarchy Module Resource

MODULE NAME REG NUMBER ALU NUMBER LUT NUMBER DSP NUMBER BSRAM NUMBER SSRAM NUMBER
Dsi2Lvds_Top (F:/mySrc/MIPI_modular_IP/Ref_Design/Saved/DSI_to_LVDS_5a25/fpga_proj/src/top.v) 79 25 31 - - -
    |--u_dphy_rx (F:/mySrc/MIPI_modular_IP/Ref_Design/Saved/DSI_to_LVDS_5a25/fpga_proj/src/top.v) - - 1 - - -
    |--u_dsi_rx (F:/mySrc/MIPI_modular_IP/Ref_Design/Saved/DSI_to_LVDS_5a25/fpga_proj/src/top.v) 216 9 279 - - -
    |--u_pll_1 (F:/mySrc/MIPI_modular_IP/Ref_Design/Saved/DSI_to_LVDS_5a25/fpga_proj/src/top.v) - - - - - -
    |--u_pll_50m (F:/mySrc/MIPI_modular_IP/Ref_Design/Saved/DSI_to_LVDS_5a25/fpga_proj/src/top.v) - - - - - -
    |--u_b2p (F:/mySrc/MIPI_modular_IP/Ref_Design/Saved/DSI_to_LVDS_5a25/fpga_proj/src/top.v) 423 20 338 - 2 -
    |--u_extr (F:/mySrc/MIPI_modular_IP/Ref_Design/Saved/DSI_to_LVDS_5a25/fpga_proj/src/top.v) 186 25 159 - 12 -
    |--u_lvds_tx_left (F:/mySrc/MIPI_modular_IP/Ref_Design/Saved/DSI_to_LVDS_5a25/fpga_proj/src/top.v) - - - - - -
        |--LVDS_71_Tx (F:/mySrc/MIPI_modular_IP/Ref_Design/Saved/DSI_to_LVDS_5a25/fpga_proj/src/lvds_tx/lvds_7_to_1_tx.v) 1 - - - - -
    |--gw_gao_inst_0 (F:/mySrc/MIPI_modular_IP/Ref_Design/Saved/DSI_to_LVDS_5a25/fpga_proj/impl/gwsynthesis/RTL_GAO/gw_gao_top.v) 359 14 452 - 4 -