Synthesis Messages

Report Title GowinSynthesis Report
Design File F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\DSI_to_LVDS_5a138\fpga_proj\src\byte_to_pixel\byte_to_pixel.v
F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\DSI_to_LVDS_5a138\fpga_proj\src\dpi_extractor.v
F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\DSI_to_LVDS_5a138\fpga_proj\src\dsi_rx\dsi_rx_top.v
F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\DSI_to_LVDS_5a138\fpga_proj\src\gowin_mipi_dphy\gowin_mipi_dphy_rx.v
F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\DSI_to_LVDS_5a138\fpga_proj\src\gowin_pll\gowin_pll_in_105m.v
F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\DSI_to_LVDS_5a138\fpga_proj\src\gowin_pll\gowin_pll_in_50m.v
F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\DSI_to_LVDS_5a138\fpga_proj\src\lvds_tx\ip_gddr71tx.v
F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\DSI_to_LVDS_5a138\fpga_proj\src\lvds_tx\lvds_7_to_1_tx.v
F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\DSI_to_LVDS_5a138\fpga_proj\src\top.v
D:\Programs\Gowin\Gowin_V1.9.9.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v
D:\Programs\Gowin\Gowin_V1.9.9.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v
D:\Programs\Gowin\Gowin_V1.9.9.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v
D:\Programs\Gowin\Gowin_V1.9.9.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v
D:\Programs\Gowin\Gowin_V1.9.9.01_x64\IDE\data\ipcores\GAO\GW_CON\gw_con_top_138.v
D:\Programs\Gowin\Gowin_V1.9.9.01_x64\IDE\data\ipcores\gw_jtag.v
F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\DSI_to_LVDS_5a138\fpga_proj\impl\gwsynthesis\RTL_GAO\gw_gao_top.v
GowinSynthesis Constraints File ---
Tool Version V1.9.9.01 (64-bit)
Part Number GW5AST-LV138FPG676AC1/I0
Device GW5AST-138
Device Version B
Created Time Wed Mar 6 18:51:37 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module Dsi2Lvds_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.531s, Elapsed time = 0h 0m 0.504s, Peak memory usage = 1521.582MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.057s, Peak memory usage = 1521.582MB
    Optimizing Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.03s, Peak memory usage = 1521.582MB
    Optimizing Phase 2: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.115s, Peak memory usage = 1521.582MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.042s, Peak memory usage = 1521.582MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 1521.582MB
    Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 1521.582MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 1521.582MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.089s, Peak memory usage = 1521.582MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.021s, Peak memory usage = 1521.582MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 1521.582MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 1521.582MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.096s, Peak memory usage = 1521.582MB
Generate output files:
    CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.106s, Peak memory usage = 1521.582MB
Total Time and Memory Usage CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 1521.582MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 29
I/O Buf 14
    IBUF 5
    OBUF 4
    TLVDS_OBUF 5
Register 1234
    DFFSE 36
    DFFRE 286
    DFFPE 46
    DFFCE 866
LUT 1170
    LUT2 138
    LUT3 339
    LUT4 693
MUX 1
    MUX16 1
ALU 93
    ALU 93
INV 20
    INV 20
IOLOGIC 5
    OVIDEO 5
BSRAM 18
    SDPB 18
CLOCK 3
    PLL 2
    DHCE 1
Black Box 2
    GW_JTAG 1
MIPI_DPHY_RX 1

Resource Utilization Summary

Resource Usage Utilization
Logic 1291(1198 LUT, 93 ALU) / 138240 <1%
Register 1234 / 139140 <1%
  --Register as Latch 0 / 139140 0%
  --Register as FF 1234 / 139140 <1%
BSRAM 18 / 340 6%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
OSC_50M Base 20.000 50.0 0.000 10.000 OSC_50M_ibuf/I
gw_gao_inst_0/u_icon_top/n31_6 Base 10.000 100.0 0.000 5.000 gw_gao_inst_0/u_icon_top/n31_s2/O
gw_gao_inst_0/u_la0_top/n15_6 Base 10.000 100.0 0.000 5.000 gw_gao_inst_0/u_la0_top/n15_s2/O
u_pll_50m/PLL_inst/CLKOUT0.default_gen_clk Generated 2.105 475.0 0.000 1.053 OSC_50M_ibuf/I OSC_50M u_pll_50m/PLL_inst/CLKOUT0
u_pll_50m/PLL_inst/CLKOUT1.default_gen_clk Generated 7.368 135.7 0.000 3.684 OSC_50M_ibuf/I OSC_50M u_pll_50m/PLL_inst/CLKOUT1

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 gw_gao_inst_0/u_icon_top/n31_6 100.000(MHz) 1164.484(MHz) 1 TOP
2 gw_gao_inst_0/u_la0_top/n15_6 100.000(MHz) 1164.484(MHz) 1 TOP
3 u_pll_50m/PLL_inst/CLKOUT1.default_gen_clk 135.714(MHz) 174.216(MHz) 6 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 1.628
Data Arrival Time 6.783
Data Required Time 8.411
From u_extr/buf_ra_0_s0
To u_extr/buf_ra_10_s8
Launch Clk u_pll_50m/PLL_inst/CLKOUT1.default_gen_clk[R]
Latch Clk u_pll_50m/PLL_inst/CLKOUT1.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 u_pll_50m/PLL_inst/CLKOUT1.default_gen_clk
1.003 1.003 tCL RR 165 u_pll_50m/PLL_inst/CLKOUT1
1.415 0.413 tNET RR 1 u_extr/buf_ra_0_s0/CLK
1.798 0.382 tC2Q RR 8 u_extr/buf_ra_0_s0/Q
2.210 0.413 tNET RR 1 u_extr/n882_s4/I0
2.789 0.579 tINS RR 5 u_extr/n882_s4/F
3.201 0.413 tNET RR 1 u_extr/n880_s4/I2
3.709 0.507 tINS RR 3 u_extr/n880_s4/F
4.122 0.413 tNET RR 1 u_extr/n877_s4/I3
4.410 0.289 tINS RR 3 u_extr/n877_s4/F
4.823 0.413 tNET RR 1 u_extr/n876_s2/I1
5.390 0.567 tINS RR 3 u_extr/n876_s2/F
5.803 0.413 tNET RR 1 u_extr/buf_ra_10_s11/I1
6.370 0.567 tINS RR 1 u_extr/buf_ra_10_s11/F
6.783 0.413 tNET RR 1 u_extr/buf_ra_10_s8/RESET
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
7.368 0.000 u_pll_50m/PLL_inst/CLKOUT1.default_gen_clk
8.371 1.003 tCL RR 165 u_pll_50m/PLL_inst/CLKOUT1
8.784 0.413 tNET RR 1 u_extr/buf_ra_10_s8/CLK
8.411 -0.373 tSu 1 u_extr/buf_ra_10_s8
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 7.368
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 2.510, 46.763%; route: 2.475, 46.111%; tC2Q: 0.382, 7.126%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 2

Path Summary:
Slack 1.767
Data Arrival Time 6.953
Data Required Time 8.720
From u_extr/ohcnt_0_s0
To u_extr/ohcnt_9_s0
Launch Clk u_pll_50m/PLL_inst/CLKOUT1.default_gen_clk[R]
Latch Clk u_pll_50m/PLL_inst/CLKOUT1.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 u_pll_50m/PLL_inst/CLKOUT1.default_gen_clk
1.003 1.003 tCL RR 165 u_pll_50m/PLL_inst/CLKOUT1
1.415 0.413 tNET RR 1 u_extr/ohcnt_0_s0/CLK
1.798 0.382 tC2Q RR 6 u_extr/ohcnt_0_s0/Q
2.210 0.413 tNET RR 1 u_extr/n738_s2/I0
2.789 0.579 tINS RR 3 u_extr/n738_s2/F
3.201 0.413 tNET RR 1 u_extr/n736_s2/I2
3.709 0.507 tINS RR 4 u_extr/n736_s2/F
4.122 0.413 tNET RR 1 u_extr/n734_s2/I2
4.629 0.507 tINS RR 4 u_extr/n734_s2/F
5.042 0.413 tNET RR 1 u_extr/n732_s2/I2
5.549 0.507 tINS RR 1 u_extr/n732_s2/F
5.962 0.413 tNET RR 1 u_extr/n732_s1/I0
6.540 0.579 tINS RR 1 u_extr/n732_s1/F
6.953 0.413 tNET RR 1 u_extr/ohcnt_9_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
7.368 0.000 u_pll_50m/PLL_inst/CLKOUT1.default_gen_clk
8.371 1.003 tCL RR 165 u_pll_50m/PLL_inst/CLKOUT1
8.784 0.413 tNET RR 1 u_extr/ohcnt_9_s0/CLK
8.720 -0.064 tSu 1 u_extr/ohcnt_9_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 7.368
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 2.680, 48.398%; route: 2.475, 44.695%; tC2Q: 0.382, 6.907%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 3

Path Summary:
Slack 1.915
Data Arrival Time 6.805
Data Required Time 8.720
From u_extr/ovcnt_4_s1
To u_extr/ovcnt_14_s1
Launch Clk u_pll_50m/PLL_inst/CLKOUT1.default_gen_clk[R]
Latch Clk u_pll_50m/PLL_inst/CLKOUT1.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 u_pll_50m/PLL_inst/CLKOUT1.default_gen_clk
1.003 1.003 tCL RR 165 u_pll_50m/PLL_inst/CLKOUT1
1.415 0.413 tNET RR 1 u_extr/ovcnt_4_s1/CLK
1.798 0.382 tC2Q RR 7 u_extr/ovcnt_4_s1/Q
2.210 0.413 tNET RR 1 u_extr/n787_s4/I0
2.789 0.579 tINS RR 1 u_extr/n787_s4/F
3.201 0.413 tNET RR 1 u_extr/n787_s3/I0
3.780 0.579 tINS RR 5 u_extr/n787_s3/F
4.193 0.413 tNET RR 1 u_extr/n783_s3/I3
4.482 0.289 tINS RR 6 u_extr/n783_s3/F
4.894 0.413 tNET RR 1 u_extr/n781_s3/I2
5.402 0.507 tINS RR 1 u_extr/n781_s3/F
5.814 0.413 tNET RR 1 u_extr/n781_s4/I0
6.393 0.579 tINS RR 1 u_extr/n781_s4/F
6.805 0.413 tNET RR 1 u_extr/ovcnt_14_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
7.368 0.000 u_pll_50m/PLL_inst/CLKOUT1.default_gen_clk
8.371 1.003 tCL RR 165 u_pll_50m/PLL_inst/CLKOUT1
8.784 0.413 tNET RR 1 u_extr/ovcnt_14_s1/CLK
8.720 -0.064 tSu 1 u_extr/ovcnt_14_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 7.368
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 2.532, 46.986%; route: 2.475, 45.918%; tC2Q: 0.382, 7.096%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 4

Path Summary:
Slack 1.966
Data Arrival Time 6.783
Data Required Time 8.749
From u_extr/buf_ra_0_s0
To u_extr/mem_data_mem_data_0_11_s
Launch Clk u_pll_50m/PLL_inst/CLKOUT1.default_gen_clk[R]
Latch Clk u_pll_50m/PLL_inst/CLKOUT1.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 u_pll_50m/PLL_inst/CLKOUT1.default_gen_clk
1.003 1.003 tCL RR 165 u_pll_50m/PLL_inst/CLKOUT1
1.415 0.413 tNET RR 1 u_extr/buf_ra_0_s0/CLK
1.798 0.382 tC2Q RR 8 u_extr/buf_ra_0_s0/Q
2.210 0.413 tNET RR 1 u_extr/n882_s4/I0
2.789 0.579 tINS RR 5 u_extr/n882_s4/F
3.201 0.413 tNET RR 1 u_extr/n880_s4/I2
3.709 0.507 tINS RR 3 u_extr/n880_s4/F
4.122 0.413 tNET RR 1 u_extr/n877_s4/I3
4.410 0.289 tINS RR 3 u_extr/n877_s4/F
4.823 0.413 tNET RR 1 u_extr/n876_s2/I1
5.390 0.567 tINS RR 3 u_extr/n876_s2/F
5.803 0.413 tNET RR 1 u_extr/buf_ra_c_10_s0/I1
6.370 0.567 tINS RR 12 u_extr/buf_ra_c_10_s0/F
6.783 0.413 tNET RR 1 u_extr/mem_data_mem_data_0_11_s/ADB[11]
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
7.368 0.000 u_pll_50m/PLL_inst/CLKOUT1.default_gen_clk
8.371 1.003 tCL RR 165 u_pll_50m/PLL_inst/CLKOUT1
8.784 0.413 tNET RR 1 u_extr/mem_data_mem_data_0_11_s/CLKB
8.749 -0.035 tSu 1 u_extr/mem_data_mem_data_0_11_s
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 7.368
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 2.510, 46.763%; route: 2.475, 46.111%; tC2Q: 0.382, 7.126%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 5

Path Summary:
Slack 1.966
Data Arrival Time 6.783
Data Required Time 8.749
From u_extr/buf_ra_0_s0
To u_extr/mem_data_mem_data_0_10_s
Launch Clk u_pll_50m/PLL_inst/CLKOUT1.default_gen_clk[R]
Latch Clk u_pll_50m/PLL_inst/CLKOUT1.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 u_pll_50m/PLL_inst/CLKOUT1.default_gen_clk
1.003 1.003 tCL RR 165 u_pll_50m/PLL_inst/CLKOUT1
1.415 0.413 tNET RR 1 u_extr/buf_ra_0_s0/CLK
1.798 0.382 tC2Q RR 8 u_extr/buf_ra_0_s0/Q
2.210 0.413 tNET RR 1 u_extr/n882_s4/I0
2.789 0.579 tINS RR 5 u_extr/n882_s4/F
3.201 0.413 tNET RR 1 u_extr/n880_s4/I2
3.709 0.507 tINS RR 3 u_extr/n880_s4/F
4.122 0.413 tNET RR 1 u_extr/n877_s4/I3
4.410 0.289 tINS RR 3 u_extr/n877_s4/F
4.823 0.413 tNET RR 1 u_extr/n876_s2/I1
5.390 0.567 tINS RR 3 u_extr/n876_s2/F
5.803 0.413 tNET RR 1 u_extr/buf_ra_c_10_s0/I1
6.370 0.567 tINS RR 12 u_extr/buf_ra_c_10_s0/F
6.783 0.413 tNET RR 1 u_extr/mem_data_mem_data_0_10_s/ADB[11]
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
7.368 0.000 u_pll_50m/PLL_inst/CLKOUT1.default_gen_clk
8.371 1.003 tCL RR 165 u_pll_50m/PLL_inst/CLKOUT1
8.784 0.413 tNET RR 1 u_extr/mem_data_mem_data_0_10_s/CLKB
8.749 -0.035 tSu 1 u_extr/mem_data_mem_data_0_10_s
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 7.368
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 2.510, 46.763%; route: 2.475, 46.111%; tC2Q: 0.382, 7.126%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%