Timing Messages

Report Title Timing Analysis Report
Design File E:\myWork\IP\releaseVerify\version\1.9.9.02\Gowin_DSI_RX_B2P_RefDesigns\csi_rx_demo_5a138\fpga_proj\impl\gwsynthesis\csi_rx_demo_5a138.vg
Physical Constraints File E:\myWork\IP\releaseVerify\version\1.9.9.02\Gowin_DSI_RX_B2P_RefDesigns\csi_rx_demo_5a138\fpga_proj\src\csi_rx_demo.cst
Timing Constraint File E:\myWork\IP\releaseVerify\version\1.9.9.02\Gowin_DSI_RX_B2P_RefDesigns\csi_rx_demo_5a138\fpga_proj\src\csi_rx_demo.sdc
Tool Version V1.9.9.02
Part Number GW5AST-LV138FPG676AC1/I0
Device GW5AST-138
Device Version B
Created Time Tue Mar 19 15:24:51 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model Slow 0.855V 0C C1/I0
Hold Delay Model Fast 0.945V 85C C1/I0
Numbers of Paths Analyzed 3735
Numbers of Endpoints Analyzed 4819
Numbers of Falling Endpoints 10
Numbers of Setup Violated Endpoints 0
Numbers of Hold Violated Endpoints 0

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Objects
clk_50 Base 20.000 50.000 0.000 10.000 clk_50m
byte_clk Base 15.000 66.667 0.000 7.500 byte_clk
pixel_clk Generated 7.500 133.333 0.000 3.750 byte_clk byte_clk lvds_pclk
tck_pad_i Base 50.000 20.000 0.000 25.000 tck_ibuf/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk_50 50.000(MHz) 89.767(MHz) 5 TOP
2 byte_clk 66.667(MHz) 68.210(MHz) 2 TOP
3 pixel_clk 133.333(MHz) 194.754(MHz) 4 TOP
4 tck_pad_i 20.000(MHz) 33.455(MHz) 6 TOP

Total Negative Slack Summary:

Clock Name Analysis Type Endpoints TNS Number of Endpoints
clk_50 Setup 0.000 0
clk_50 Hold 0.000 0
byte_clk Setup 0.000 0
byte_clk Hold 0.000 0
pixel_clk Setup 0.000 0
pixel_clk Hold 0.000 0
tck_pad_i Setup 0.000 0
tck_pad_i Hold 0.000 0

Timing Details

Path Slacks Table:

Setup Paths Table

Setup Paths Table[1]:

Report Command:report_timing -setup -from_clock [get_clocks {pixel_clk}] -max_paths 20 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 2.365 u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/DO[6] u_bayer_rgb/r_o_6_s0/D pixel_clk:[R] pixel_clk:[R] 7.500 -0.009 5.080
2 2.370 u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/DO[5] u_bayer_rgb/r_o_5_s0/D pixel_clk:[R] pixel_clk:[R] 7.500 0.010 5.056
3 2.402 u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/DO[4] u_bayer_rgb/r_o_4_s0/D pixel_clk:[R] pixel_clk:[R] 7.500 0.010 5.025
4 2.403 u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/DO[7] u_bayer_rgb/g_o_7_s0/D pixel_clk:[R] pixel_clk:[R] 7.500 -0.009 5.043
5 2.424 u_b2p/u_b2p_inst/u_mid_fifo/rWPtrRsync_6_s0/Q u_b2p/u_b2p_inst/u_mid_fifo/rEmpty_s0/D pixel_clk:[R] pixel_clk:[R] 7.500 -0.034 5.046
6 2.435 u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/DO[7] u_bayer_rgb/r_o_7_s0/D pixel_clk:[R] pixel_clk:[R] 7.500 0.012 4.990
7 2.502 u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/DO[2] u_bayer_rgb/r_o_2_s0/D pixel_clk:[R] pixel_clk:[R] 7.500 0.002 4.932
8 2.538 u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/DO[0] u_bayer_rgb/r_o_0_s0/D pixel_clk:[R] pixel_clk:[R] 7.500 -0.009 4.908
9 2.667 u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/DO[3] u_bayer_rgb/r_o_3_s0/D pixel_clk:[R] pixel_clk:[R] 7.500 0.002 4.767
10 2.705 u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/DO[1] u_bayer_rgb/r_o_1_s0/D pixel_clk:[R] pixel_clk:[R] 7.500 0.010 4.721
11 2.713 u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/DO[6] u_bayer_rgb/g_o_6_s0/D pixel_clk:[R] pixel_clk:[R] 7.500 0.000 4.722
12 2.883 u_bayer_rgb/devcnt_8_s1/Q u_bayer_rgb/devcnt_14_s1/D pixel_clk:[R] pixel_clk:[R] 7.500 -0.009 4.563
13 2.883 u_bayer_rgb/devcnt_8_s1/Q u_bayer_rgb/devcnt_15_s1/D pixel_clk:[R] pixel_clk:[R] 7.500 -0.009 4.563
14 2.931 u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/DO[1] u_bayer_rgb/g_o_1_s0/D pixel_clk:[R] pixel_clk:[R] 7.500 0.000 4.505
15 2.936 u_bayer_rgb/video_format_detect_inst/vd_hres_reg_3_s0/Q u_bayer_rgb/shift_line_inst0/shiftout_addr_9_s0/D pixel_clk:[R] pixel_clk:[R] 7.500 -0.009 4.510
16 2.938 u_bayer_rgb/video_format_detect_inst/vd_hres_reg_3_s0/Q u_bayer_rgb/shift_line_inst0/shiftout_addr_10_s0/D pixel_clk:[R] pixel_clk:[R] 7.500 -0.009 4.508
17 3.017 u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/DO[2] u_bayer_rgb/g_o_2_s0/D pixel_clk:[R] pixel_clk:[R] 7.500 0.002 4.418
18 3.125 u_b2p/u_b2p_inst/u_mid_fifo/rRPtrBin_1_s0/Q u_b2p/u_b2p_inst/u_mid_fifo/rRPtrGray_5_s0/D pixel_clk:[R] pixel_clk:[R] 7.500 0.017 4.294
19 3.135 u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/DO[5] u_bayer_rgb/g_o_5_s0/D pixel_clk:[R] pixel_clk:[R] 7.500 -0.007 4.309
20 3.154 u_bayer_rgb/video_format_detect_inst/vd_hres_reg_3_s0/Q u_bayer_rgb/shift_line_inst0/shiftout_addr_8_s0/D pixel_clk:[R] pixel_clk:[R] 7.500 -0.009 4.291

Setup Paths Table[2]:

Report Command:report_timing -setup -from_clock [get_clocks {byte_clk}] -max_paths 20 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.339 u_la0_top/capture_end_dly_s0/Q u_la0_top/capture_window_sel_5_s1/CE byte_clk:[R] byte_clk:[R] 15.000 0.000 14.349
2 0.339 u_la0_top/capture_end_dly_s0/Q u_la0_top/capture_window_sel_6_s1/CE byte_clk:[R] byte_clk:[R] 15.000 0.000 14.349
3 0.339 u_la0_top/capture_end_dly_s0/Q u_la0_top/capture_window_sel_7_s1/CE byte_clk:[R] byte_clk:[R] 15.000 0.000 14.349
4 0.339 u_la0_top/capture_end_dly_s0/Q u_la0_top/capture_window_sel_8_s1/CE byte_clk:[R] byte_clk:[R] 15.000 0.000 14.349
5 0.339 u_la0_top/capture_end_dly_s0/Q u_la0_top/capture_window_sel_9_s1/CE byte_clk:[R] byte_clk:[R] 15.000 0.000 14.349
6 0.346 u_la0_top/capture_end_dly_s0/Q u_la0_top/capture_window_sel_10_s1/CE byte_clk:[R] byte_clk:[R] 15.000 0.000 14.342
7 0.477 u_la0_top/capture_end_dly_s0/Q u_la0_top/capture_window_sel_1_s1/CE byte_clk:[R] byte_clk:[R] 15.000 0.000 14.212
8 0.477 u_la0_top/capture_end_dly_s0/Q u_la0_top/capture_window_sel_2_s1/CE byte_clk:[R] byte_clk:[R] 15.000 0.000 14.212
9 0.477 u_la0_top/capture_end_dly_s0/Q u_la0_top/capture_window_sel_3_s1/CE byte_clk:[R] byte_clk:[R] 15.000 0.000 14.212
10 0.477 u_la0_top/capture_end_dly_s0/Q u_la0_top/capture_window_sel_4_s1/CE byte_clk:[R] byte_clk:[R] 15.000 0.000 14.212
11 2.962 odt_en_msk_s0/Q hsrx_cnt_0_s1/CE byte_clk:[R] byte_clk:[R] 15.000 -0.139 11.866
12 2.962 odt_en_msk_s0/Q hsrx_cnt_1_s1/CE byte_clk:[R] byte_clk:[R] 15.000 -0.139 11.866
13 2.962 odt_en_msk_s0/Q hsrx_cnt_2_s1/CE byte_clk:[R] byte_clk:[R] 15.000 -0.139 11.866
14 2.962 odt_en_msk_s0/Q hsrx_cnt_3_s1/CE byte_clk:[R] byte_clk:[R] 15.000 -0.139 11.866
15 3.037 odt_en_msk_s0/Q hsrx_cnt_1_s1/D byte_clk:[R] byte_clk:[R] 15.000 -0.139 12.039
16 3.151 odt_en_msk_s0/Q hsrx_cnt_3_s1/D byte_clk:[R] byte_clk:[R] 15.000 -0.139 11.925
17 3.161 odt_en_msk_s0/Q hsrx_cnt_4_s3/D byte_clk:[R] byte_clk:[R] 15.000 -0.130 11.905
18 3.221 odt_en_msk_s0/Q hsrx_cnt_5_s7/D byte_clk:[R] byte_clk:[R] 15.000 -0.130 11.845
19 3.574 odt_en_msk_s0/Q hsrx_cnt_0_s1/D byte_clk:[R] byte_clk:[R] 15.000 -0.139 11.501
20 3.574 odt_en_msk_s0/Q hsrx_cnt_2_s1/D byte_clk:[R] byte_clk:[R] 15.000 -0.139 11.501

Hold Paths Table

Hold Paths Table[1]:

Report Command:report_timing -hold -from_clock [get_clocks {pixel_clk}] -max_paths 20 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.374 u_bayer_rgb/video_format_detect_inst/hcnt_6_s3/Q u_bayer_rgb/video_format_detect_inst/hcnt_6_s3/D pixel_clk:[R] pixel_clk:[R] 0.000 0.000 0.375
2 0.374 u_bayer_rgb/video_format_detect_inst/hcnt_10_s1/Q u_bayer_rgb/video_format_detect_inst/hcnt_10_s1/D pixel_clk:[R] pixel_clk:[R] 0.000 0.000 0.375
3 0.374 u_bayer_rgb/dehcnt_0_s3/Q u_bayer_rgb/dehcnt_0_s3/D pixel_clk:[R] pixel_clk:[R] 0.000 0.000 0.375
4 0.374 u_bayer_rgb/devcnt_1_s1/Q u_bayer_rgb/devcnt_1_s1/D pixel_clk:[R] pixel_clk:[R] 0.000 0.000 0.375
5 0.374 u_bayer_rgb/devcnt_15_s1/Q u_bayer_rgb/devcnt_15_s1/D pixel_clk:[R] pixel_clk:[R] 0.000 0.000 0.375
6 0.377 u_bayer_rgb/shift_line_inst0/shiftin_addr_0_s0/Q u_bayer_rgb/shift_line_inst0/shiftin_addr_0_s0/D pixel_clk:[R] pixel_clk:[R] 0.000 0.000 0.379
7 0.377 u_bayer_rgb/video_format_detect_inst/hcnt_7_s3/Q u_bayer_rgb/video_format_detect_inst/hcnt_7_s3/D pixel_clk:[R] pixel_clk:[R] 0.000 0.000 0.379
8 0.377 u_bayer_rgb/video_format_detect_inst/hcnt_8_s1/Q u_bayer_rgb/video_format_detect_inst/hcnt_8_s1/D pixel_clk:[R] pixel_clk:[R] 0.000 0.000 0.379
9 0.377 u_bayer_rgb/devcnt_4_s1/Q u_bayer_rgb/devcnt_4_s1/D pixel_clk:[R] pixel_clk:[R] 0.000 0.000 0.379
10 0.377 u_bayer_rgb/devcnt_5_s1/Q u_bayer_rgb/devcnt_5_s1/D pixel_clk:[R] pixel_clk:[R] 0.000 0.000 0.379
11 0.377 u_bayer_rgb/devcnt_7_s1/Q u_bayer_rgb/devcnt_7_s1/D pixel_clk:[R] pixel_clk:[R] 0.000 0.000 0.379
12 0.377 u_b2p/u_b2p_inst/out_cnt_0_s3/Q u_b2p/u_b2p_inst/out_cnt_0_s3/D pixel_clk:[R] pixel_clk:[R] 0.000 0.000 0.379
13 0.381 u_bayer_rgb/devcnt_11_s1/Q u_bayer_rgb/devcnt_11_s1/D pixel_clk:[R] pixel_clk:[R] 0.000 0.000 0.382
14 0.389 u_bayer_rgb/devcnt_0_s1/Q u_bayer_rgb/devcnt_0_s1/D pixel_clk:[R] pixel_clk:[R] 0.000 0.000 0.390
15 0.444 u_bayer_rgb/devcnt_6_s1/Q u_bayer_rgb/devcnt_6_s1/D pixel_clk:[R] pixel_clk:[R] 0.000 0.000 0.445
16 0.449 u_bayer_rgb/video_format_detect_inst/vd_hres_2_s0/Q u_bayer_rgb/video_format_detect_inst/vd_hres_reg_2_s0/D pixel_clk:[R] pixel_clk:[R] 0.000 0.000 0.450
17 0.449 u_bayer_rgb/video_format_detect_inst/vd_hres_5_s0/Q u_bayer_rgb/video_format_detect_inst/vd_hres_reg_5_s0/D pixel_clk:[R] pixel_clk:[R] 0.000 0.000 0.450
18 0.449 u_bayer_rgb/b_o_1_s0/Q pxl_b_r_1_s0/D pixel_clk:[R] pixel_clk:[R] 0.000 0.000 0.450
19 0.449 u_bayer_rgb/g_o_5_s0/Q pxl_g_r_5_s0/D pixel_clk:[R] pixel_clk:[R] 0.000 0.000 0.450
20 0.449 u_bayer_rgb/de_tmp3_s0/Q u_bayer_rgb/de_o_s0/D pixel_clk:[R] pixel_clk:[R] 0.000 0.000 0.450

Hold Paths Table[2]:

Report Command:report_timing -hold -from_clock [get_clocks {byte_clk}] -max_paths 20 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.263 u_la0_top/u_ao_mem_ctrl/data_reg_54_s0/Q u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/DI[0] byte_clk:[R] byte_clk:[R] 0.000 0.000 0.512
2 0.266 u_b2p/u_b2p_inst/rBufD_8_s1/Q u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s/DI[8] byte_clk:[R] byte_clk:[R] 0.000 0.030 0.485
3 0.266 u_b2p/u_b2p_inst/rBufD_7_s1/Q u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s/DI[7] byte_clk:[R] byte_clk:[R] 0.000 0.030 0.485
4 0.266 u_b2p/u_b2p_inst/rBufD_6_s1/Q u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s/DI[6] byte_clk:[R] byte_clk:[R] 0.000 0.030 0.485
5 0.294 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/Q u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/ADA[4] byte_clk:[R] byte_clk:[R] 0.000 0.000 0.412
6 0.295 u_la0_top/u_ao_mem_ctrl/data_reg_60_s0/Q u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/DI[6] byte_clk:[R] byte_clk:[R] 0.000 0.000 0.544
7 0.305 u_la0_top/u_ao_mem_ctrl/data_reg_22_s0/Q u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[4] byte_clk:[R] byte_clk:[R] 0.000 0.000 0.554
8 0.310 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/Q u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/ADA[7] byte_clk:[R] byte_clk:[R] 0.000 0.000 0.428
9 0.310 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/Q u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/ADA[6] byte_clk:[R] byte_clk:[R] 0.000 0.000 0.428
10 0.319 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/Q u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/ADA[5] byte_clk:[R] byte_clk:[R] 0.000 0.000 0.438
11 0.323 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/Q u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/ADA[4] byte_clk:[R] byte_clk:[R] 0.000 0.000 0.441
12 0.345 u_la0_top/u_ao_mem_ctrl/data_reg_23_s0/Q u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[5] byte_clk:[R] byte_clk:[R] 0.000 0.000 0.594
13 0.367 u_la0_top/u_ao_mem_ctrl/data_reg_59_s0/Q u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/DI[5] byte_clk:[R] byte_clk:[R] 0.000 0.000 0.616
14 0.367 u_la0_top/u_ao_mem_ctrl/data_reg_57_s0/Q u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/DI[3] byte_clk:[R] byte_clk:[R] 0.000 0.000 0.616
15 0.367 u_la0_top/u_ao_mem_ctrl/data_reg_56_s0/Q u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/DI[2] byte_clk:[R] byte_clk:[R] 0.000 0.000 0.616
16 0.374 u_b2p/u_b2p_inst/wc_cnt_dec_5_s1/Q u_b2p/u_b2p_inst/wc_cnt_dec_5_s1/D byte_clk:[R] byte_clk:[R] 0.000 0.000 0.375
17 0.374 u_b2p/u_b2p_inst/wc_cnt_dec_8_s1/Q u_b2p/u_b2p_inst/wc_cnt_dec_8_s1/D byte_clk:[R] byte_clk:[R] 0.000 0.000 0.375
18 0.374 u_csi_rx/u_dsi_csi2/rWcCnt_10_s0/Q u_csi_rx/u_dsi_csi2/rWcCnt_10_s0/D byte_clk:[R] byte_clk:[R] 0.000 0.000 0.375
19 0.374 hsrx_cnt_1_s1/Q hsrx_cnt_1_s1/D byte_clk:[R] byte_clk:[R] 0.000 0.000 0.375
20 0.374 hsrx_cnt_3_s1/Q hsrx_cnt_3_s1/D byte_clk:[R] byte_clk:[R] 0.000 0.000 0.375

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 1.993 u_la0_top/rst_ao_s0/Q u_la0_top/triger_level_cnt_2_s1/CLEAR byte_clk:[F] byte_clk:[R] 7.500 0.000 5.160
2 2.029 u_la0_top/rst_ao_s0/Q u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR byte_clk:[F] byte_clk:[R] 7.500 0.000 5.123
3 2.029 u_la0_top/rst_ao_s0/Q u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR byte_clk:[F] byte_clk:[R] 7.500 0.000 5.123
4 2.029 u_la0_top/rst_ao_s0/Q u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR byte_clk:[F] byte_clk:[R] 7.500 0.000 5.123
5 2.065 u_la0_top/rst_ao_s0/Q u_la0_top/u_ao_match_2/trig_dly_in_5_s0/CLEAR byte_clk:[F] byte_clk:[R] 7.500 0.000 5.088
6 2.065 u_la0_top/rst_ao_s0/Q u_la0_top/u_ao_match_1/trig_dly_in_0_s0/CLEAR byte_clk:[F] byte_clk:[R] 7.500 0.000 5.088
7 2.065 u_la0_top/rst_ao_s0/Q u_la0_top/u_ao_match_0/trig_dly_0_s0/CLEAR byte_clk:[F] byte_clk:[R] 7.500 0.000 5.088
8 2.065 u_la0_top/rst_ao_s0/Q u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR byte_clk:[F] byte_clk:[R] 7.500 0.000 5.088
9 2.065 u_la0_top/rst_ao_s0/Q u_la0_top/u_ao_mem_ctrl/capture_length_10_s1/CLEAR byte_clk:[F] byte_clk:[R] 7.500 0.000 5.088
10 2.087 u_la0_top/rst_ao_s0/Q u_la0_top/capture_window_sel_10_s1/CLEAR byte_clk:[F] byte_clk:[R] 7.500 0.000 5.065
11 2.087 u_la0_top/rst_ao_s0/Q u_la0_top/internal_reg_start_dly_1_s0/CLEAR byte_clk:[F] byte_clk:[R] 7.500 0.000 5.065
12 2.087 u_la0_top/rst_ao_s0/Q u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR byte_clk:[F] byte_clk:[R] 7.500 0.000 5.065
13 2.090 u_la0_top/rst_ao_s0/Q u_la0_top/capture_window_sel_5_s1/CLEAR byte_clk:[F] byte_clk:[R] 7.500 0.000 5.063
14 2.090 u_la0_top/rst_ao_s0/Q u_la0_top/capture_window_sel_6_s1/CLEAR byte_clk:[F] byte_clk:[R] 7.500 0.000 5.063
15 2.090 u_la0_top/rst_ao_s0/Q u_la0_top/capture_window_sel_7_s1/CLEAR byte_clk:[F] byte_clk:[R] 7.500 0.000 5.063
16 2.090 u_la0_top/rst_ao_s0/Q u_la0_top/capture_window_sel_8_s1/CLEAR byte_clk:[F] byte_clk:[R] 7.500 0.000 5.063
17 2.090 u_la0_top/rst_ao_s0/Q u_la0_top/capture_window_sel_9_s1/CLEAR byte_clk:[F] byte_clk:[R] 7.500 0.000 5.063
18 2.090 u_la0_top/rst_ao_s0/Q u_la0_top/triger_level_cnt_3_s1/CLEAR byte_clk:[F] byte_clk:[R] 7.500 0.000 5.063
19 2.092 u_la0_top/rst_ao_s0/Q u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR byte_clk:[F] byte_clk:[R] 7.500 0.000 5.061
20 2.092 u_la0_top/rst_ao_s0/Q u_la0_top/triger_level_cnt_0_s1/CLEAR byte_clk:[F] byte_clk:[R] 7.500 0.000 5.060
21 2.092 u_la0_top/rst_ao_s0/Q u_la0_top/triger_level_cnt_1_s1/CLEAR byte_clk:[F] byte_clk:[R] 7.500 0.000 5.060
22 2.099 u_la0_top/rst_ao_s0/Q u_la0_top/u_ao_match_2/match_bitwise_pre_reg_5_s0/CLEAR byte_clk:[F] byte_clk:[R] 7.500 0.000 5.054
23 2.099 u_la0_top/rst_ao_s0/Q u_la0_top/u_ao_match_2/trig_dly_in_0_s0/CLEAR byte_clk:[F] byte_clk:[R] 7.500 0.000 5.054
24 2.099 u_la0_top/rst_ao_s0/Q u_la0_top/u_ao_match_2/trig_dly_in_1_s0/CLEAR byte_clk:[F] byte_clk:[R] 7.500 0.000 5.054
25 2.099 u_la0_top/rst_ao_s0/Q u_la0_top/u_ao_match_2/trig_dly_in_2_s0/CLEAR byte_clk:[F] byte_clk:[R] 7.500 0.000 5.054

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.611 u_ov5647_ctrl/resend_s0/Q u_ov5647_ctrl/I2C/data_sr_40_s1/PRESET clk_50:[R] clk_50:[R] 0.000 -0.010 0.433
2 0.611 u_ov5647_ctrl/resend_s0/Q u_ov5647_ctrl/I2C/data_sr_0_s1/PRESET clk_50:[R] clk_50:[R] 0.000 -0.010 0.433
3 0.611 u_ov5647_ctrl/resend_s0/Q u_ov5647_ctrl/I2C/data_sr_1_s1/PRESET clk_50:[R] clk_50:[R] 0.000 -0.010 0.433
4 0.611 u_ov5647_ctrl/resend_s0/Q u_ov5647_ctrl/I2C/data_sr_2_s1/PRESET clk_50:[R] clk_50:[R] 0.000 -0.010 0.433
5 0.611 u_ov5647_ctrl/resend_s0/Q u_ov5647_ctrl/I2C/data_sr_31_s1/PRESET clk_50:[R] clk_50:[R] 0.000 -0.010 0.433
6 0.611 u_ov5647_ctrl/resend_s0/Q u_ov5647_ctrl/I2C/data_sr_32_s1/PRESET clk_50:[R] clk_50:[R] 0.000 -0.010 0.433
7 0.611 u_ov5647_ctrl/resend_s0/Q u_ov5647_ctrl/I2C/data_sr_33_s1/PRESET clk_50:[R] clk_50:[R] 0.000 -0.010 0.433
8 0.611 u_ov5647_ctrl/resend_s0/Q u_ov5647_ctrl/I2C/data_sr_34_s1/PRESET clk_50:[R] clk_50:[R] 0.000 -0.010 0.433
9 0.616 u_ov5647_ctrl/resend_s0/Q u_ov5647_ctrl/I2C/data_sr_35_s1/PRESET clk_50:[R] clk_50:[R] 0.000 -0.005 0.433
10 0.616 u_ov5647_ctrl/resend_s0/Q u_ov5647_ctrl/I2C/data_sr_36_s1/PRESET clk_50:[R] clk_50:[R] 0.000 -0.005 0.433
11 0.616 u_ov5647_ctrl/resend_s0/Q u_ov5647_ctrl/I2C/data_sr_37_s1/PRESET clk_50:[R] clk_50:[R] 0.000 -0.005 0.433
12 0.616 u_ov5647_ctrl/resend_s0/Q u_ov5647_ctrl/I2C/data_sr_38_s1/PRESET clk_50:[R] clk_50:[R] 0.000 -0.005 0.433
13 0.616 u_ov5647_ctrl/resend_s0/Q u_ov5647_ctrl/I2C/data_sr_39_s1/PRESET clk_50:[R] clk_50:[R] 0.000 -0.005 0.433
14 0.618 u_ov5647_ctrl/resend_s0/Q u_ov5647_ctrl/I2C/busy_sr_14_s1/CLEAR clk_50:[R] clk_50:[R] 0.000 -0.003 0.433
15 0.618 u_ov5647_ctrl/resend_s0/Q u_ov5647_ctrl/I2C/busy_sr_15_s1/CLEAR clk_50:[R] clk_50:[R] 0.000 -0.003 0.433
16 0.618 u_ov5647_ctrl/resend_s0/Q u_ov5647_ctrl/I2C/busy_sr_16_s1/CLEAR clk_50:[R] clk_50:[R] 0.000 -0.003 0.433
17 0.618 u_ov5647_ctrl/resend_s0/Q u_ov5647_ctrl/I2C/busy_sr_17_s1/CLEAR clk_50:[R] clk_50:[R] 0.000 -0.003 0.433
18 0.618 u_ov5647_ctrl/resend_s0/Q u_ov5647_ctrl/I2C/busy_sr_18_s1/CLEAR clk_50:[R] clk_50:[R] 0.000 -0.003 0.433
19 0.618 u_ov5647_ctrl/resend_s0/Q u_ov5647_ctrl/I2C/busy_sr_19_s1/CLEAR clk_50:[R] clk_50:[R] 0.000 -0.003 0.433
20 0.756 u_ov5647_ctrl/resend_s0/Q u_ov5647_ctrl/I2C/busy_sr_31_s1/CLEAR clk_50:[R] clk_50:[R] 0.000 -0.005 0.572
21 0.756 u_ov5647_ctrl/resend_s0/Q u_ov5647_ctrl/I2C/busy_sr_32_s1/CLEAR clk_50:[R] clk_50:[R] 0.000 -0.005 0.572
22 0.756 u_ov5647_ctrl/resend_s0/Q u_ov5647_ctrl/I2C/busy_sr_33_s1/CLEAR clk_50:[R] clk_50:[R] 0.000 -0.005 0.572
23 0.756 u_ov5647_ctrl/resend_s0/Q u_ov5647_ctrl/I2C/busy_sr_34_s1/CLEAR clk_50:[R] clk_50:[R] 0.000 -0.005 0.572
24 0.756 u_ov5647_ctrl/resend_s0/Q u_ov5647_ctrl/I2C/busy_sr_35_s1/CLEAR clk_50:[R] clk_50:[R] 0.000 -0.005 0.572
25 0.756 u_ov5647_ctrl/resend_s0/Q u_ov5647_ctrl/I2C/busy_sr_36_s1/CLEAR clk_50:[R] clk_50:[R] 0.000 -0.005 0.572

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number Slack Actual Width Required Width Type Clock Objects
1 1.531 2.531 1.000 High Pulse Width pixel_clk u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s
2 1.579 2.579 1.000 High Pulse Width pixel_clk u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s
3 1.583 2.583 1.000 High Pulse Width pixel_clk u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s
4 1.584 2.584 1.000 Low Pulse Width pixel_clk u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s
5 1.628 2.628 1.000 Low Pulse Width pixel_clk u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s
6 1.632 2.632 1.000 Low Pulse Width pixel_clk u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s
7 2.277 2.527 0.250 High Pulse Width pixel_clk u_b2p/u_b2p_inst/u_mid_fifo/rRstRsync_s0
8 2.277 2.527 0.250 High Pulse Width pixel_clk u_b2p/u_b2p_inst/u_mid_fifo/rRdClr_s0
9 2.277 2.527 0.250 High Pulse Width pixel_clk u_b2p/u_b2p_inst/u_mid_fifo/rRdRst_s0
10 2.280 2.530 0.250 High Pulse Width pixel_clk u_b2p/u_b2p_inst/pixel_data_r_1_s0

Timing Report By Analysis Type:

Setup Analysis Report

Setup Analysis Report[1]:

Report Command:report_timing -setup -from_clock [get_clocks {pixel_clk}] -max_paths 20 -max_common_paths 1

Path1

Path Summary:

Slack 2.365
Data Arrival Time 7.728
Data Required Time 10.093
From u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s
To u_bayer_rgb/r_o_6_s0
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLL_inst/CLKOUT1
2.648 2.648 tNET RR 8 BSRAM_R46[25][A] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/CLKB
4.908 2.260 tC2Q RR 3 BSRAM_R46[25][A] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/DO[6]
6.118 1.210 tNET RR 1 R53C111[1][B] u_bayer_rgb/n298_s3/I1
6.697 0.579 tINS RR 1 R53C111[1][B] u_bayer_rgb/n298_s3/F
6.699 0.003 tNET RR 1 R53C111[2][A] u_bayer_rgb/n298_s2/I3
7.267 0.567 tINS RR 1 R53C111[2][A] u_bayer_rgb/n298_s2/F
7.439 0.172 tNET RR 1 R54C111[0][B] u_bayer_rgb/n298_s1/I1
7.728 0.289 tINS RR 1 R54C111[0][B] u_bayer_rgb/n298_s1/F
7.728 0.000 tNET RR 1 R54C111[0][B] u_bayer_rgb/r_o_6_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 pixel_clk
7.500 0.000 tCL RR 244 PLL_L[0] u_pll/PLL_inst/CLKOUT1
10.157 2.657 tNET RR 1 R54C111[0][B] u_bayer_rgb/r_o_6_s0/CLK
10.093 -0.064 tSu 1 R54C111[0][B] u_bayer_rgb/r_o_6_s0

Path Statistics:

Clock Skew 0.009
Setup Relationship 7.500
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.648, 100.000%
Arrival Data Path Delay cell: 1.435, 28.248%; route: 1.385, 27.264%; tC2Q: 2.260, 44.488%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.657, 100.000%

Path2

Path Summary:

Slack 2.370
Data Arrival Time 7.704
Data Required Time 10.074
From u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s
To u_bayer_rgb/r_o_5_s0
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLL_inst/CLKOUT1
2.648 2.648 tNET RR 8 BSRAM_R46[25][A] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/CLKB
4.908 2.260 tC2Q RF 3 BSRAM_R46[25][A] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/DO[5]
5.968 1.060 tNET FF 1 R53C111[2][B] u_bayer_rgb/n299_s3/I0
6.257 0.289 tINS FR 1 R53C111[2][B] u_bayer_rgb/n299_s3/F
6.429 0.172 tNET RR 1 R53C110[1][B] u_bayer_rgb/n299_s2/I3
6.718 0.289 tINS RR 1 R53C110[1][B] u_bayer_rgb/n299_s2/F
7.137 0.419 tNET RR 1 R54C109[1][A] u_bayer_rgb/n299_s1/I1
7.704 0.567 tINS RR 1 R54C109[1][A] u_bayer_rgb/n299_s1/F
7.704 0.000 tNET RR 1 R54C109[1][A] u_bayer_rgb/r_o_5_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 pixel_clk
7.500 0.000 tCL RR 244 PLL_L[0] u_pll/PLL_inst/CLKOUT1
10.138 2.638 tNET RR 1 R54C109[1][A] u_bayer_rgb/r_o_5_s0/CLK
10.074 -0.064 tSu 1 R54C109[1][A] u_bayer_rgb/r_o_5_s0

Path Statistics:

Clock Skew -0.010
Setup Relationship 7.500
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.648, 100.000%
Arrival Data Path Delay cell: 1.145, 22.645%; route: 1.651, 32.658%; tC2Q: 2.260, 44.697%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.638, 100.000%

Path3

Path Summary:

Slack 2.402
Data Arrival Time 7.673
Data Required Time 10.074
From u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s
To u_bayer_rgb/r_o_4_s0
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLL_inst/CLKOUT1
2.648 2.648 tNET RR 8 BSRAM_R46[25][A] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/CLKB
4.908 2.260 tC2Q RF 3 BSRAM_R46[25][A] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/DO[4]
6.194 1.286 tNET FF 1 R53C109[1][A] u_bayer_rgb/n300_s3/I1
6.702 0.507 tINS FR 1 R53C109[1][A] u_bayer_rgb/n300_s3/F
6.704 0.003 tNET RR 1 R53C109[0][B] u_bayer_rgb/n300_s2/I3
6.993 0.289 tINS RR 1 R53C109[0][B] u_bayer_rgb/n300_s2/F
7.165 0.172 tNET RR 1 R54C109[1][B] u_bayer_rgb/n300_s1/I1
7.673 0.507 tINS RR 1 R54C109[1][B] u_bayer_rgb/n300_s1/F
7.673 0.000 tNET RR 1 R54C109[1][B] u_bayer_rgb/r_o_4_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 pixel_clk
7.500 0.000 tCL RR 244 PLL_L[0] u_pll/PLL_inst/CLKOUT1
10.138 2.638 tNET RR 1 R54C109[1][B] u_bayer_rgb/r_o_4_s0/CLK
10.074 -0.064 tSu 1 R54C109[1][B] u_bayer_rgb/r_o_4_s0

Path Statistics:

Clock Skew -0.010
Setup Relationship 7.500
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.648, 100.000%
Arrival Data Path Delay cell: 1.304, 25.945%; route: 1.461, 29.080%; tC2Q: 2.260, 44.975%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.638, 100.000%

Path4

Path Summary:

Slack 2.403
Data Arrival Time 7.690
Data Required Time 10.093
From u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s
To u_bayer_rgb/g_o_7_s0
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLL_inst/CLKOUT1
2.648 2.648 tNET RR 8 BSRAM_R46[25][A] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/CLKB
4.908 2.260 tC2Q RF 3 BSRAM_R46[25][A] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/DO[7]
6.162 1.254 tNET FF 1 R53C114[1][B] u_bayer_rgb/n305_s3/I0
6.450 0.289 tINS FR 1 R53C114[1][B] u_bayer_rgb/n305_s3/F
6.453 0.003 tNET RR 1 R53C114[0][A] u_bayer_rgb/n305_s2/I0
7.020 0.567 tINS RR 1 R53C114[0][A] u_bayer_rgb/n305_s2/F
7.402 0.381 tNET RR 1 R54C115[1][A] u_bayer_rgb/n305_s1/I1
7.690 0.289 tINS RR 1 R54C115[1][A] u_bayer_rgb/n305_s1/F
7.690 0.000 tNET RR 1 R54C115[1][A] u_bayer_rgb/g_o_7_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 pixel_clk
7.500 0.000 tCL RR 244 PLL_L[0] u_pll/PLL_inst/CLKOUT1
10.157 2.657 tNET RR 1 R54C115[1][A] u_bayer_rgb/g_o_7_s0/CLK
10.093 -0.064 tSu 1 R54C115[1][A] u_bayer_rgb/g_o_7_s0

Path Statistics:

Clock Skew 0.009
Setup Relationship 7.500
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.648, 100.000%
Arrival Data Path Delay cell: 1.145, 22.707%; route: 1.638, 32.474%; tC2Q: 2.260, 44.819%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.657, 100.000%

Path5

Path Summary:

Slack 2.424
Data Arrival Time 7.742
Data Required Time 10.167
From u_b2p/u_b2p_inst/u_mid_fifo/rWPtrRsync_6_s0
To u_b2p/u_b2p_inst/u_mid_fifo/rEmpty_s0
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLL_inst/CLKOUT1
2.696 2.696 tNET RR 1 R54C84[0][A] u_b2p/u_b2p_inst/u_mid_fifo/rWPtrRsync_6_s0/CLK
3.079 0.382 tC2Q RR 6 R54C84[0][A] u_b2p/u_b2p_inst/u_mid_fifo/rWPtrRsync_6_s0/Q
4.928 1.849 tNET RR 1 R54C87[3][B] u_b2p/u_b2p_inst/u_mid_fifo/wWPtrBinX_5_s0/I1
5.219 0.291 tINS RR 3 R54C87[3][B] u_b2p/u_b2p_inst/u_mid_fifo/wWPtrBinX_5_s0/F
6.144 0.925 tNET RR 1 R56C90[2][A] u_b2p/u_b2p_inst/u_mid_fifo/n386_s4/I3
6.651 0.507 tINS RR 1 R56C90[2][A] u_b2p/u_b2p_inst/u_mid_fifo/n386_s4/F
6.654 0.003 tNET RR 1 R56C90[2][B] u_b2p/u_b2p_inst/u_mid_fifo/n386_s2/I0
7.161 0.507 tINS RR 1 R56C90[2][B] u_b2p/u_b2p_inst/u_mid_fifo/n386_s2/F
7.164 0.003 tNET RR 1 R56C90[0][A] u_b2p/u_b2p_inst/u_mid_fifo/n386_s0/I1
7.743 0.579 tINS RR 1 R56C90[0][A] u_b2p/u_b2p_inst/u_mid_fifo/n386_s0/F
7.743 0.000 tNET RR 1 R56C90[0][A] u_b2p/u_b2p_inst/u_mid_fifo/rEmpty_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 pixel_clk
7.500 0.000 tCL RR 244 PLL_L[0] u_pll/PLL_inst/CLKOUT1
10.231 2.731 tNET RR 1 R56C90[0][A] u_b2p/u_b2p_inst/u_mid_fifo/rEmpty_s0/CLK
10.167 -0.064 tSu 1 R56C90[0][A] u_b2p/u_b2p_inst/u_mid_fifo/rEmpty_s0

Path Statistics:

Clock Skew 0.034
Setup Relationship 7.500
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.696, 100.000%
Arrival Data Path Delay cell: 1.885, 37.354%; route: 2.779, 55.066%; tC2Q: 0.382, 7.580%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.731, 100.000%

Path6

Path Summary:

Slack 2.435
Data Arrival Time 7.638
Data Required Time 10.072
From u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s
To u_bayer_rgb/r_o_7_s0
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLL_inst/CLKOUT1
2.648 2.648 tNET RR 8 BSRAM_R46[25][A] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/CLKB
4.908 2.260 tC2Q RR 3 BSRAM_R46[25][A] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/DO[7]
6.093 1.185 tNET RR 1 R53C112[1][B] u_bayer_rgb/n297_s3/I0
6.600 0.507 tINS RR 1 R53C112[1][B] u_bayer_rgb/n297_s3/F
6.603 0.003 tNET RR 1 R53C112[3][A] u_bayer_rgb/n297_s2/I3
7.177 0.574 tINS RR 1 R53C112[3][A] u_bayer_rgb/n297_s2/F
7.349 0.172 tNET RR 1 R53C113[1][B] u_bayer_rgb/n297_s1/I1
7.638 0.289 tINS RR 1 R53C113[1][B] u_bayer_rgb/n297_s1/F
7.638 0.000 tNET RR 1 R53C113[1][B] u_bayer_rgb/r_o_7_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 pixel_clk
7.500 0.000 tCL RR 244 PLL_L[0] u_pll/PLL_inst/CLKOUT1
10.136 2.636 tNET RR 1 R53C113[1][B] u_bayer_rgb/r_o_7_s0/CLK
10.072 -0.064 tSu 1 R53C113[1][B] u_bayer_rgb/r_o_7_s0

Path Statistics:

Clock Skew -0.012
Setup Relationship 7.500
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.648, 100.000%
Arrival Data Path Delay cell: 1.370, 27.455%; route: 1.360, 27.255%; tC2Q: 2.260, 45.291%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.636, 100.000%

Path7

Path Summary:

Slack 2.502
Data Arrival Time 7.580
Data Required Time 10.082
From u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s
To u_bayer_rgb/r_o_2_s0
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLL_inst/CLKOUT1
2.648 2.648 tNET RR 8 BSRAM_R46[25][A] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/CLKB
4.908 2.260 tC2Q RR 3 BSRAM_R46[25][A] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/DO[2]
6.360 1.453 tNET RR 1 R53C108[3][A] u_bayer_rgb/n302_s3/I1
6.679 0.319 tINS RF 1 R53C108[3][A] u_bayer_rgb/n302_s3/F
6.684 0.005 tNET FF 1 R53C108[3][B] u_bayer_rgb/n302_s2/I3
7.140 0.456 tINS FR 1 R53C108[3][B] u_bayer_rgb/n302_s2/F
7.292 0.151 tNET RR 1 R53C108[2][A] u_bayer_rgb/n302_s1/I1
7.580 0.289 tINS RR 1 R53C108[2][A] u_bayer_rgb/n302_s1/F
7.580 0.000 tNET RR 1 R53C108[2][A] u_bayer_rgb/r_o_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 pixel_clk
7.500 0.000 tCL RR 244 PLL_L[0] u_pll/PLL_inst/CLKOUT1
10.146 2.646 tNET RR 1 R53C108[2][A] u_bayer_rgb/r_o_2_s0/CLK
10.082 -0.064 tSu 1 R53C108[2][A] u_bayer_rgb/r_o_2_s0

Path Statistics:

Clock Skew -0.002
Setup Relationship 7.500
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.648, 100.000%
Arrival Data Path Delay cell: 1.064, 21.566%; route: 1.609, 32.615%; tC2Q: 2.260, 45.819%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.646, 100.000%

Path8

Path Summary:

Slack 2.538
Data Arrival Time 7.555
Data Required Time 10.093
From u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s
To u_bayer_rgb/r_o_0_s0
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLL_inst/CLKOUT1
2.648 2.648 tNET RR 8 BSRAM_R46[25][A] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/CLKB
4.908 2.260 tC2Q RR 3 BSRAM_R46[25][A] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/DO[0]
6.179 1.271 tNET RR 1 R54C110[3][A] u_bayer_rgb/n304_s3/I1
6.635 0.456 tINS RR 1 R54C110[3][A] u_bayer_rgb/n304_s3/F
6.638 0.003 tNET RR 1 R54C110[3][B] u_bayer_rgb/n304_s2/I3
7.094 0.456 tINS RR 1 R54C110[3][B] u_bayer_rgb/n304_s2/F
7.267 0.172 tNET RR 1 R54C111[2][A] u_bayer_rgb/n304_s1/I1
7.555 0.289 tINS RR 1 R54C111[2][A] u_bayer_rgb/n304_s1/F
7.555 0.000 tNET RR 1 R54C111[2][A] u_bayer_rgb/r_o_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 pixel_clk
7.500 0.000 tCL RR 244 PLL_L[0] u_pll/PLL_inst/CLKOUT1
10.157 2.657 tNET RR 1 R54C111[2][A] u_bayer_rgb/r_o_0_s0/CLK
10.093 -0.064 tSu 1 R54C111[2][A] u_bayer_rgb/r_o_0_s0

Path Statistics:

Clock Skew 0.009
Setup Relationship 7.500
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.648, 100.000%
Arrival Data Path Delay cell: 1.201, 24.478%; route: 1.446, 29.470%; tC2Q: 2.260, 46.052%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.657, 100.000%

Path9

Path Summary:

Slack 2.667
Data Arrival Time 7.415
Data Required Time 10.082
From u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s
To u_bayer_rgb/r_o_3_s0
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLL_inst/CLKOUT1
2.648 2.648 tNET RR 8 BSRAM_R46[25][A] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/CLKB
4.908 2.260 tC2Q RR 3 BSRAM_R46[25][A] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/DO[3]
6.155 1.248 tNET RR 1 R53C109[2][A] u_bayer_rgb/n301_s3/I0
6.663 0.507 tINS RR 1 R53C109[2][A] u_bayer_rgb/n301_s3/F
6.835 0.172 tNET RR 1 R53C108[0][A] u_bayer_rgb/n301_s2/I3
7.124 0.289 tINS RR 1 R53C108[0][A] u_bayer_rgb/n301_s2/F
7.127 0.003 tNET RR 1 R53C108[0][B] u_bayer_rgb/n301_s1/I1
7.415 0.289 tINS RR 1 R53C108[0][B] u_bayer_rgb/n301_s1/F
7.415 0.000 tNET RR 1 R53C108[0][B] u_bayer_rgb/r_o_3_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 pixel_clk
7.500 0.000 tCL RR 244 PLL_L[0] u_pll/PLL_inst/CLKOUT1
10.146 2.646 tNET RR 1 R53C108[0][B] u_bayer_rgb/r_o_3_s0/CLK
10.082 -0.064 tSu 1 R53C108[0][B] u_bayer_rgb/r_o_3_s0

Path Statistics:

Clock Skew -0.002
Setup Relationship 7.500
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.648, 100.000%
Arrival Data Path Delay cell: 1.085, 22.758%; route: 1.423, 29.837%; tC2Q: 2.260, 47.404%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.646, 100.000%

Path10

Path Summary:

Slack 2.705
Data Arrival Time 7.369
Data Required Time 10.074
From u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s
To u_bayer_rgb/r_o_1_s0
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLL_inst/CLKOUT1
2.648 2.648 tNET RR 8 BSRAM_R46[25][A] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/CLKB
4.908 2.260 tC2Q RF 3 BSRAM_R46[25][A] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/DO[1]
5.960 1.053 tNET FF 1 R54C114[2][B] u_bayer_rgb/n303_s3/I0
6.249 0.289 tINS FR 1 R54C114[2][B] u_bayer_rgb/n303_s3/F
6.422 0.172 tNET RR 1 R54C113[0][B] u_bayer_rgb/n303_s2/I3
6.929 0.507 tINS RR 1 R54C113[0][B] u_bayer_rgb/n303_s2/F
7.080 0.151 tNET RR 1 R54C113[0][A] u_bayer_rgb/n303_s1/I1
7.369 0.289 tINS RR 1 R54C113[0][A] u_bayer_rgb/n303_s1/F
7.369 0.000 tNET RR 1 R54C113[0][A] u_bayer_rgb/r_o_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 pixel_clk
7.500 0.000 tCL RR 244 PLL_L[0] u_pll/PLL_inst/CLKOUT1
10.138 2.638 tNET RR 1 R54C113[0][A] u_bayer_rgb/r_o_1_s0/CLK
10.074 -0.064 tSu 1 R54C113[0][A] u_bayer_rgb/r_o_1_s0

Path Statistics:

Clock Skew -0.010
Setup Relationship 7.500
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.648, 100.000%
Arrival Data Path Delay cell: 1.085, 22.981%; route: 1.376, 29.150%; tC2Q: 2.260, 47.869%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.638, 100.000%

Path11

Path Summary:

Slack 2.713
Data Arrival Time 7.370
Data Required Time 10.084
From u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s
To u_bayer_rgb/g_o_6_s0
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLL_inst/CLKOUT1
2.648 2.648 tNET RR 8 BSRAM_R46[25][A] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/CLKB
4.908 2.260 tC2Q RR 3 BSRAM_R46[25][A] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/DO[6]
6.153 1.245 tNET RR 1 R53C113[3][B] u_bayer_rgb/n306_s2/I0
6.700 0.548 tINS RR 1 R53C113[3][B] u_bayer_rgb/n306_s2/F
7.082 0.381 tNET RR 1 R54C114[0][A] u_bayer_rgb/n306_s1/I3
7.370 0.289 tINS RR 1 R54C114[0][A] u_bayer_rgb/n306_s1/F
7.370 0.000 tNET RR 1 R54C114[0][A] u_bayer_rgb/g_o_6_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 pixel_clk
7.500 0.000 tCL RR 244 PLL_L[0] u_pll/PLL_inst/CLKOUT1
10.148 2.648 tNET RR 1 R54C114[0][A] u_bayer_rgb/g_o_6_s0/CLK
10.084 -0.064 tSu 1 R54C114[0][A] u_bayer_rgb/g_o_6_s0

Path Statistics:

Clock Skew -0.000
Setup Relationship 7.500
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.648, 100.000%
Arrival Data Path Delay cell: 0.836, 17.708%; route: 1.626, 34.436%; tC2Q: 2.260, 47.856%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.648, 100.000%

Path12

Path Summary:

Slack 2.883
Data Arrival Time 7.210
Data Required Time 10.093
From u_bayer_rgb/devcnt_8_s1
To u_bayer_rgb/devcnt_14_s1
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLL_inst/CLKOUT1
2.648 2.648 tNET RR 1 R54C126[3][A] u_bayer_rgb/devcnt_8_s1/CLK
3.030 0.382 tC2Q RR 5 R54C126[3][A] u_bayer_rgb/devcnt_8_s1/Q
4.800 1.770 tNET RR 1 R53C127[3][B] u_bayer_rgb/n90_s4/I1
5.374 0.574 tINS RR 2 R53C127[3][B] u_bayer_rgb/n90_s4/F
5.379 0.005 tNET RR 1 R53C127[0][B] u_bayer_rgb/n86_s4/I2
5.958 0.579 tINS RR 1 R53C127[0][B] u_bayer_rgb/n86_s4/F
5.960 0.003 tNET RR 1 R53C127[0][A] u_bayer_rgb/n86_s3/I0
6.528 0.567 tINS RR 2 R53C127[0][A] u_bayer_rgb/n86_s3/F
6.703 0.175 tNET RR 1 R54C127[2][B] u_bayer_rgb/n86_s5/I3
7.210 0.507 tINS RR 1 R54C127[2][B] u_bayer_rgb/n86_s5/F
7.210 0.000 tNET RR 1 R54C127[2][B] u_bayer_rgb/devcnt_14_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 pixel_clk
7.500 0.000 tCL RR 244 PLL_L[0] u_pll/PLL_inst/CLKOUT1
10.157 2.657 tNET RR 1 R54C127[2][B] u_bayer_rgb/devcnt_14_s1/CLK
10.093 -0.064 tSu 1 R54C127[2][B] u_bayer_rgb/devcnt_14_s1

Path Statistics:

Clock Skew 0.009
Setup Relationship 7.500
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.648, 100.000%
Arrival Data Path Delay cell: 2.227, 48.822%; route: 1.953, 42.795%; tC2Q: 0.382, 8.384%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.657, 100.000%

Path13

Path Summary:

Slack 2.883
Data Arrival Time 7.210
Data Required Time 10.093
From u_bayer_rgb/devcnt_8_s1
To u_bayer_rgb/devcnt_15_s1
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLL_inst/CLKOUT1
2.648 2.648 tNET RR 1 R54C126[3][A] u_bayer_rgb/devcnt_8_s1/CLK
3.030 0.382 tC2Q RR 5 R54C126[3][A] u_bayer_rgb/devcnt_8_s1/Q
4.800 1.770 tNET RR 1 R53C127[3][B] u_bayer_rgb/n90_s4/I1
5.374 0.574 tINS RR 2 R53C127[3][B] u_bayer_rgb/n90_s4/F
5.379 0.005 tNET RR 1 R53C127[0][B] u_bayer_rgb/n86_s4/I2
5.958 0.579 tINS RR 1 R53C127[0][B] u_bayer_rgb/n86_s4/F
5.960 0.003 tNET RR 1 R53C127[0][A] u_bayer_rgb/n86_s3/I0
6.528 0.567 tINS RR 2 R53C127[0][A] u_bayer_rgb/n86_s3/F
6.703 0.175 tNET RR 1 R54C127[0][A] u_bayer_rgb/n85_s2/I1
7.210 0.507 tINS RR 1 R54C127[0][A] u_bayer_rgb/n85_s2/F
7.210 0.000 tNET RR 1 R54C127[0][A] u_bayer_rgb/devcnt_15_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 pixel_clk
7.500 0.000 tCL RR 244 PLL_L[0] u_pll/PLL_inst/CLKOUT1
10.157 2.657 tNET RR 1 R54C127[0][A] u_bayer_rgb/devcnt_15_s1/CLK
10.093 -0.064 tSu 1 R54C127[0][A] u_bayer_rgb/devcnt_15_s1

Path Statistics:

Clock Skew 0.009
Setup Relationship 7.500
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.648, 100.000%
Arrival Data Path Delay cell: 2.227, 48.822%; route: 1.953, 42.795%; tC2Q: 0.382, 8.384%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.657, 100.000%

Path14

Path Summary:

Slack 2.931
Data Arrival Time 7.153
Data Required Time 10.084
From u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s
To u_bayer_rgb/g_o_1_s0
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLL_inst/CLKOUT1
2.648 2.648 tNET RR 8 BSRAM_R46[25][A] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/CLKB
4.908 2.260 tC2Q RR 3 BSRAM_R46[25][A] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/DO[1]
6.095 1.188 tNET RR 1 R54C114[3][A] u_bayer_rgb/n311_s2/I0
6.643 0.548 tINS RR 1 R54C114[3][A] u_bayer_rgb/n311_s2/F
6.645 0.003 tNET RR 1 R54C114[1][A] u_bayer_rgb/n311_s1/I3
7.153 0.507 tINS RR 1 R54C114[1][A] u_bayer_rgb/n311_s1/F
7.153 0.000 tNET RR 1 R54C114[1][A] u_bayer_rgb/g_o_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 pixel_clk
7.500 0.000 tCL RR 244 PLL_L[0] u_pll/PLL_inst/CLKOUT1
10.148 2.648 tNET RR 1 R54C114[1][A] u_bayer_rgb/g_o_1_s0/CLK
10.084 -0.064 tSu 1 R54C114[1][A] u_bayer_rgb/g_o_1_s0

Path Statistics:

Clock Skew -0.000
Setup Relationship 7.500
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.648, 100.000%
Arrival Data Path Delay cell: 1.055, 23.418%; route: 1.190, 26.415%; tC2Q: 2.260, 50.166%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.648, 100.000%

Path15

Path Summary:

Slack 2.936
Data Arrival Time 7.156
Data Required Time 10.091
From u_bayer_rgb/video_format_detect_inst/vd_hres_reg_3_s0
To u_bayer_rgb/shift_line_inst0/shiftout_addr_9_s0
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLL_inst/CLKOUT1
2.646 2.646 tNET RR 1 R53C98[1][A] u_bayer_rgb/video_format_detect_inst/vd_hres_reg_3_s0/CLK
3.028 0.382 tC2Q RR 3 R53C98[1][A] u_bayer_rgb/video_format_detect_inst/vd_hres_reg_3_s0/Q
3.476 0.448 tNET RR 1 R53C101[3][B] u_bayer_rgb/shift_line_inst0/n54_s5/I2
4.049 0.574 tINS RR 4 R53C101[3][B] u_bayer_rgb/shift_line_inst0/n54_s5/F
4.059 0.010 tNET RR 1 R53C101[3][A] u_bayer_rgb/shift_line_inst0/n51_s5/I3
4.607 0.548 tINS RR 3 R53C101[3][A] u_bayer_rgb/shift_line_inst0/n51_s5/F
4.614 0.008 tNET RR 1 R53C101[2][A] u_bayer_rgb/shift_line_inst0/n51_s4/I1
5.122 0.507 tINS RR 1 R53C101[2][A] u_bayer_rgb/shift_line_inst0/n51_s4/F
6.314 1.192 tNET RR 2 R53C119[1][A] u_bayer_rgb/shift_line_inst0/n73_s/I1
6.859 0.545 tINS RR 1 R53C119[1][A] u_bayer_rgb/shift_line_inst0/n73_s/COUT
6.859 0.000 tNET RR 2 R53C119[1][B] u_bayer_rgb/shift_line_inst0/n72_s/CIN
7.156 0.296 tINS RR 1 R53C119[1][B] u_bayer_rgb/shift_line_inst0/n72_s/SUM
7.156 0.000 tNET RR 1 R53C119[1][B] u_bayer_rgb/shift_line_inst0/shiftout_addr_9_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 pixel_clk
7.500 0.000 tCL RR 244 PLL_L[0] u_pll/PLL_inst/CLKOUT1
10.155 2.655 tNET RR 1 R53C119[1][B] u_bayer_rgb/shift_line_inst0/shiftout_addr_9_s0/CLK
10.091 -0.064 tSu 1 R53C119[1][B] u_bayer_rgb/shift_line_inst0/shiftout_addr_9_s0

Path Statistics:

Clock Skew 0.009
Setup Relationship 7.500
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.646, 100.000%
Arrival Data Path Delay cell: 2.470, 54.767%; route: 1.658, 36.752%; tC2Q: 0.382, 8.481%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.655, 100.000%

Path16

Path Summary:

Slack 2.938
Data Arrival Time 7.153
Data Required Time 10.091
From u_bayer_rgb/video_format_detect_inst/vd_hres_reg_3_s0
To u_bayer_rgb/shift_line_inst0/shiftout_addr_10_s0
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLL_inst/CLKOUT1
2.646 2.646 tNET RR 1 R53C98[1][A] u_bayer_rgb/video_format_detect_inst/vd_hres_reg_3_s0/CLK
3.028 0.382 tC2Q RR 3 R53C98[1][A] u_bayer_rgb/video_format_detect_inst/vd_hres_reg_3_s0/Q
3.476 0.448 tNET RR 1 R53C101[3][B] u_bayer_rgb/shift_line_inst0/n54_s5/I2
4.049 0.574 tINS RR 4 R53C101[3][B] u_bayer_rgb/shift_line_inst0/n54_s5/F
4.059 0.010 tNET RR 1 R53C101[3][A] u_bayer_rgb/shift_line_inst0/n51_s5/I3
4.607 0.548 tINS RR 3 R53C101[3][A] u_bayer_rgb/shift_line_inst0/n51_s5/F
4.614 0.008 tNET RR 1 R53C101[2][A] u_bayer_rgb/shift_line_inst0/n51_s4/I1
5.122 0.507 tINS RR 1 R53C101[2][A] u_bayer_rgb/shift_line_inst0/n51_s4/F
6.314 1.192 tNET RR 2 R53C119[1][A] u_bayer_rgb/shift_line_inst0/n73_s/I1
6.859 0.545 tINS RR 1 R53C119[1][A] u_bayer_rgb/shift_line_inst0/n73_s/COUT
6.859 0.000 tNET RR 2 R53C119[1][B] u_bayer_rgb/shift_line_inst0/n72_s/CIN
6.909 0.050 tINS RR 1 R53C119[1][B] u_bayer_rgb/shift_line_inst0/n72_s/COUT
6.909 0.000 tNET RR 2 R53C119[2][A] u_bayer_rgb/shift_line_inst0/n71_s/CIN
7.153 0.244 tINS RR 1 R53C119[2][A] u_bayer_rgb/shift_line_inst0/n71_s/SUM
7.153 0.000 tNET RR 1 R53C119[2][A] u_bayer_rgb/shift_line_inst0/shiftout_addr_10_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 pixel_clk
7.500 0.000 tCL RR 244 PLL_L[0] u_pll/PLL_inst/CLKOUT1
10.155 2.655 tNET RR 1 R53C119[2][A] u_bayer_rgb/shift_line_inst0/shiftout_addr_10_s0/CLK
10.091 -0.064 tSu 1 R53C119[2][A] u_bayer_rgb/shift_line_inst0/shiftout_addr_10_s0

Path Statistics:

Clock Skew 0.009
Setup Relationship 7.500
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.646, 100.000%
Arrival Data Path Delay cell: 2.467, 54.742%; route: 1.658, 36.772%; tC2Q: 0.382, 8.486%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.655, 100.000%

Path17

Path Summary:

Slack 3.017
Data Arrival Time 7.065
Data Required Time 10.082
From u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s
To u_bayer_rgb/g_o_2_s0
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLL_inst/CLKOUT1
2.648 2.648 tNET RR 8 BSRAM_R46[25][A] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/CLKB
4.908 2.260 tC2Q RF 3 BSRAM_R46[25][A] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/DO[2]
6.163 1.255 tNET FF 1 R53C114[3][B] u_bayer_rgb/n310_s2/I0
6.482 0.319 tINS FF 1 R53C114[3][B] u_bayer_rgb/n310_s2/F
6.487 0.005 tNET FF 1 R53C114[1][A] u_bayer_rgb/n310_s1/I3
7.065 0.579 tINS FR 1 R53C114[1][A] u_bayer_rgb/n310_s1/F
7.065 0.000 tNET RR 1 R53C114[1][A] u_bayer_rgb/g_o_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 pixel_clk
7.500 0.000 tCL RR 244 PLL_L[0] u_pll/PLL_inst/CLKOUT1
10.146 2.646 tNET RR 1 R53C114[1][A] u_bayer_rgb/g_o_2_s0/CLK
10.082 -0.064 tSu 1 R53C114[1][A] u_bayer_rgb/g_o_2_s0

Path Statistics:

Clock Skew -0.002
Setup Relationship 7.500
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.648, 100.000%
Arrival Data Path Delay cell: 0.898, 20.317%; route: 1.260, 28.523%; tC2Q: 2.260, 51.160%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.646, 100.000%

Path18

Path Summary:

Slack 3.125
Data Arrival Time 7.015
Data Required Time 10.140
From u_b2p/u_b2p_inst/u_mid_fifo/rRPtrBin_1_s0
To u_b2p/u_b2p_inst/u_mid_fifo/rRPtrGray_5_s0
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLL_inst/CLKOUT1
2.721 2.721 tNET RR 1 R56C89[2][A] u_b2p/u_b2p_inst/u_mid_fifo/rRPtrBin_1_s0/CLK
3.104 0.382 tC2Q RR 11 R56C89[2][A] u_b2p/u_b2p_inst/u_mid_fifo/rRPtrBin_1_s0/Q
4.297 1.194 tNET RR 1 R54C87[2][A] u_b2p/u_b2p_inst/u_mid_fifo/wRPtrBinNext_4_s4/I1
4.876 0.579 tINS RR 8 R54C87[2][A] u_b2p/u_b2p_inst/u_mid_fifo/wRPtrBinNext_4_s4/F
5.267 0.391 tNET RR 1 R54C90[3][B] u_b2p/u_b2p_inst/u_mid_fifo/wRPtrBinNext_6_s2/I2
5.841 0.574 tINS RR 4 R54C90[3][B] u_b2p/u_b2p_inst/u_mid_fifo/wRPtrBinNext_6_s2/F
6.436 0.595 tNET RR 1 R53C87[0][B] u_b2p/u_b2p_inst/u_mid_fifo/wRPtrGrayNext_5_s1/I3
7.015 0.579 tINS RR 1 R53C87[0][B] u_b2p/u_b2p_inst/u_mid_fifo/wRPtrGrayNext_5_s1/F
7.015 0.000 tNET RR 1 R53C87[0][B] u_b2p/u_b2p_inst/u_mid_fifo/rRPtrGray_5_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 pixel_clk
7.500 0.000 tCL RR 244 PLL_L[0] u_pll/PLL_inst/CLKOUT1
10.204 2.704 tNET RR 1 R53C87[0][B] u_b2p/u_b2p_inst/u_mid_fifo/rRPtrGray_5_s0/CLK
10.140 -0.064 tSu 1 R53C87[0][B] u_b2p/u_b2p_inst/u_mid_fifo/rRPtrGray_5_s0

Path Statistics:

Clock Skew -0.017
Setup Relationship 7.500
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.721, 100.000%
Arrival Data Path Delay cell: 1.731, 40.320%; route: 2.180, 50.771%; tC2Q: 0.382, 8.908%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.704, 100.000%

Path19

Path Summary:

Slack 3.135
Data Arrival Time 6.957
Data Required Time 10.091
From u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s
To u_bayer_rgb/g_o_5_s0
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLL_inst/CLKOUT1
2.648 2.648 tNET RR 8 BSRAM_R46[25][A] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/CLKB
4.908 2.260 tC2Q RR 3 BSRAM_R46[25][A] u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/DO[5]
6.098 1.190 tNET RR 1 R53C115[0][A] u_bayer_rgb/n307_s2/I0
6.665 0.567 tINS RR 1 R53C115[0][A] u_bayer_rgb/n307_s2/F
6.668 0.003 tNET RR 1 R53C115[1][B] u_bayer_rgb/n307_s1/I3
6.957 0.289 tINS RR 1 R53C115[1][B] u_bayer_rgb/n307_s1/F
6.957 0.000 tNET RR 1 R53C115[1][B] u_bayer_rgb/g_o_5_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 pixel_clk
7.500 0.000 tCL RR 244 PLL_L[0] u_pll/PLL_inst/CLKOUT1
10.155 2.655 tNET RR 1 R53C115[1][B] u_bayer_rgb/g_o_5_s0/CLK
10.091 -0.064 tSu 1 R53C115[1][B] u_bayer_rgb/g_o_5_s0

Path Statistics:

Clock Skew 0.007
Setup Relationship 7.500
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.648, 100.000%
Arrival Data Path Delay cell: 0.856, 19.872%; route: 1.193, 27.676%; tC2Q: 2.260, 52.451%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.655, 100.000%

Path20

Path Summary:

Slack 3.154
Data Arrival Time 6.937
Data Required Time 10.091
From u_bayer_rgb/video_format_detect_inst/vd_hres_reg_3_s0
To u_bayer_rgb/shift_line_inst0/shiftout_addr_8_s0
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLL_inst/CLKOUT1
2.646 2.646 tNET RR 1 R53C98[1][A] u_bayer_rgb/video_format_detect_inst/vd_hres_reg_3_s0/CLK
3.028 0.382 tC2Q RR 3 R53C98[1][A] u_bayer_rgb/video_format_detect_inst/vd_hres_reg_3_s0/Q
3.476 0.448 tNET RR 1 R53C101[3][B] u_bayer_rgb/shift_line_inst0/n54_s5/I2
4.049 0.574 tINS RR 4 R53C101[3][B] u_bayer_rgb/shift_line_inst0/n54_s5/F
4.059 0.010 tNET RR 1 R53C101[3][A] u_bayer_rgb/shift_line_inst0/n51_s5/I3
4.607 0.548 tINS RR 3 R53C101[3][A] u_bayer_rgb/shift_line_inst0/n51_s5/F
4.614 0.008 tNET RR 1 R53C101[2][A] u_bayer_rgb/shift_line_inst0/n51_s4/I1
5.122 0.507 tINS RR 1 R53C101[2][A] u_bayer_rgb/shift_line_inst0/n51_s4/F
6.314 1.192 tNET RR 2 R53C119[1][A] u_bayer_rgb/shift_line_inst0/n73_s/I1
6.937 0.623 tINS RR 1 R53C119[1][A] u_bayer_rgb/shift_line_inst0/n73_s/SUM
6.937 0.000 tNET RR 1 R53C119[1][A] u_bayer_rgb/shift_line_inst0/shiftout_addr_8_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 pixel_clk
7.500 0.000 tCL RR 244 PLL_L[0] u_pll/PLL_inst/CLKOUT1
10.155 2.655 tNET RR 1 R53C119[1][A] u_bayer_rgb/shift_line_inst0/shiftout_addr_8_s0/CLK
10.091 -0.064 tSu 1 R53C119[1][A] u_bayer_rgb/shift_line_inst0/shiftout_addr_8_s0

Path Statistics:

Clock Skew 0.009
Setup Relationship 7.500
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.646, 100.000%
Arrival Data Path Delay cell: 2.251, 52.461%; route: 1.658, 38.625%; tC2Q: 0.382, 8.913%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.655, 100.000%

Setup Analysis Report[2]:

Report Command:report_timing -setup -from_clock [get_clocks {byte_clk}] -max_paths 20 -max_common_paths 1

Path1

Path Summary:

Slack 0.339
Data Arrival Time 14.349
Data Required Time 14.689
From u_la0_top/capture_end_dly_s0
To u_la0_top/capture_window_sel_5_s1
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 625 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
0.000 0.000 tNET RR 1 R4C11[2][B] u_la0_top/capture_end_dly_s0/CLK
0.382 0.382 tC2Q RR 3 R4C11[2][B] u_la0_top/capture_end_dly_s0/Q
2.595 2.213 tNET RR 1 R8C8[0][A] u_la0_top/capture_window_sel_10_s5/I1
3.174 0.579 tINS RR 10 R8C8[0][A] u_la0_top/capture_window_sel_10_s5/F
14.349 11.176 tNET RR 1 R4C3[3][A] u_la0_top/capture_window_sel_5_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
15.000 0.000 tNET RR 1 R4C3[3][A] u_la0_top/capture_window_sel_5_s1/CLK
14.689 -0.311 tSu 1 R4C3[3][A] u_la0_top/capture_window_sel_5_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 15.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.579, 4.033%; route: 13.388, 93.301%; tC2Q: 0.382, 2.666%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path2

Path Summary:

Slack 0.339
Data Arrival Time 14.349
Data Required Time 14.689
From u_la0_top/capture_end_dly_s0
To u_la0_top/capture_window_sel_6_s1
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 625 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
0.000 0.000 tNET RR 1 R4C11[2][B] u_la0_top/capture_end_dly_s0/CLK
0.382 0.382 tC2Q RR 3 R4C11[2][B] u_la0_top/capture_end_dly_s0/Q
2.595 2.213 tNET RR 1 R8C8[0][A] u_la0_top/capture_window_sel_10_s5/I1
3.174 0.579 tINS RR 10 R8C8[0][A] u_la0_top/capture_window_sel_10_s5/F
14.349 11.176 tNET RR 1 R4C3[2][B] u_la0_top/capture_window_sel_6_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
15.000 0.000 tNET RR 1 R4C3[2][B] u_la0_top/capture_window_sel_6_s1/CLK
14.689 -0.311 tSu 1 R4C3[2][B] u_la0_top/capture_window_sel_6_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 15.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.579, 4.033%; route: 13.388, 93.301%; tC2Q: 0.382, 2.666%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path3

Path Summary:

Slack 0.339
Data Arrival Time 14.349
Data Required Time 14.689
From u_la0_top/capture_end_dly_s0
To u_la0_top/capture_window_sel_7_s1
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 625 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
0.000 0.000 tNET RR 1 R4C11[2][B] u_la0_top/capture_end_dly_s0/CLK
0.382 0.382 tC2Q RR 3 R4C11[2][B] u_la0_top/capture_end_dly_s0/Q
2.595 2.213 tNET RR 1 R8C8[0][A] u_la0_top/capture_window_sel_10_s5/I1
3.174 0.579 tINS RR 10 R8C8[0][A] u_la0_top/capture_window_sel_10_s5/F
14.349 11.176 tNET RR 1 R4C3[2][A] u_la0_top/capture_window_sel_7_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
15.000 0.000 tNET RR 1 R4C3[2][A] u_la0_top/capture_window_sel_7_s1/CLK
14.689 -0.311 tSu 1 R4C3[2][A] u_la0_top/capture_window_sel_7_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 15.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.579, 4.033%; route: 13.388, 93.301%; tC2Q: 0.382, 2.666%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path4

Path Summary:

Slack 0.339
Data Arrival Time 14.349
Data Required Time 14.689
From u_la0_top/capture_end_dly_s0
To u_la0_top/capture_window_sel_8_s1
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 625 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
0.000 0.000 tNET RR 1 R4C11[2][B] u_la0_top/capture_end_dly_s0/CLK
0.382 0.382 tC2Q RR 3 R4C11[2][B] u_la0_top/capture_end_dly_s0/Q
2.595 2.213 tNET RR 1 R8C8[0][A] u_la0_top/capture_window_sel_10_s5/I1
3.174 0.579 tINS RR 10 R8C8[0][A] u_la0_top/capture_window_sel_10_s5/F
14.349 11.176 tNET RR 1 R4C3[0][B] u_la0_top/capture_window_sel_8_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
15.000 0.000 tNET RR 1 R4C3[0][B] u_la0_top/capture_window_sel_8_s1/CLK
14.689 -0.311 tSu 1 R4C3[0][B] u_la0_top/capture_window_sel_8_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 15.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.579, 4.033%; route: 13.388, 93.301%; tC2Q: 0.382, 2.666%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path5

Path Summary:

Slack 0.339
Data Arrival Time 14.349
Data Required Time 14.689
From u_la0_top/capture_end_dly_s0
To u_la0_top/capture_window_sel_9_s1
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 625 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
0.000 0.000 tNET RR 1 R4C11[2][B] u_la0_top/capture_end_dly_s0/CLK
0.382 0.382 tC2Q RR 3 R4C11[2][B] u_la0_top/capture_end_dly_s0/Q
2.595 2.213 tNET RR 1 R8C8[0][A] u_la0_top/capture_window_sel_10_s5/I1
3.174 0.579 tINS RR 10 R8C8[0][A] u_la0_top/capture_window_sel_10_s5/F
14.349 11.176 tNET RR 1 R4C3[0][A] u_la0_top/capture_window_sel_9_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
15.000 0.000 tNET RR 1 R4C3[0][A] u_la0_top/capture_window_sel_9_s1/CLK
14.689 -0.311 tSu 1 R4C3[0][A] u_la0_top/capture_window_sel_9_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 15.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.579, 4.033%; route: 13.388, 93.301%; tC2Q: 0.382, 2.666%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path6

Path Summary:

Slack 0.346
Data Arrival Time 14.342
Data Required Time 14.689
From u_la0_top/capture_end_dly_s0
To u_la0_top/capture_window_sel_10_s1
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 625 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
0.000 0.000 tNET RR 1 R4C11[2][B] u_la0_top/capture_end_dly_s0/CLK
0.382 0.382 tC2Q RR 3 R4C11[2][B] u_la0_top/capture_end_dly_s0/Q
2.595 2.213 tNET RR 1 R8C8[0][A] u_la0_top/capture_window_sel_10_s5/I1
3.174 0.579 tINS RR 10 R8C8[0][A] u_la0_top/capture_window_sel_10_s5/F
14.342 11.169 tNET RR 1 R3C8[0][A] u_la0_top/capture_window_sel_10_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
15.000 0.000 tNET RR 1 R3C8[0][A] u_la0_top/capture_window_sel_10_s1/CLK
14.689 -0.311 tSu 1 R3C8[0][A] u_la0_top/capture_window_sel_10_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 15.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.579, 4.035%; route: 13.381, 93.298%; tC2Q: 0.382, 2.667%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path7

Path Summary:

Slack 0.477
Data Arrival Time 14.212
Data Required Time 14.689
From u_la0_top/capture_end_dly_s0
To u_la0_top/capture_window_sel_1_s1
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 625 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
0.000 0.000 tNET RR 1 R4C11[2][B] u_la0_top/capture_end_dly_s0/CLK
0.382 0.382 tC2Q RR 3 R4C11[2][B] u_la0_top/capture_end_dly_s0/Q
2.595 2.213 tNET RR 1 R8C8[0][A] u_la0_top/capture_window_sel_10_s5/I1
3.174 0.579 tINS RR 10 R8C8[0][A] u_la0_top/capture_window_sel_10_s5/F
14.212 11.038 tNET RR 1 R7C8[2][B] u_la0_top/capture_window_sel_1_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
15.000 0.000 tNET RR 1 R7C8[2][B] u_la0_top/capture_window_sel_1_s1/CLK
14.689 -0.311 tSu 1 R7C8[2][B] u_la0_top/capture_window_sel_1_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 15.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.579, 4.072%; route: 13.250, 93.236%; tC2Q: 0.382, 2.691%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path8

Path Summary:

Slack 0.477
Data Arrival Time 14.212
Data Required Time 14.689
From u_la0_top/capture_end_dly_s0
To u_la0_top/capture_window_sel_2_s1
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 625 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
0.000 0.000 tNET RR 1 R4C11[2][B] u_la0_top/capture_end_dly_s0/CLK
0.382 0.382 tC2Q RR 3 R4C11[2][B] u_la0_top/capture_end_dly_s0/Q
2.595 2.213 tNET RR 1 R8C8[0][A] u_la0_top/capture_window_sel_10_s5/I1
3.174 0.579 tINS RR 10 R8C8[0][A] u_la0_top/capture_window_sel_10_s5/F
14.212 11.038 tNET RR 1 R7C8[2][A] u_la0_top/capture_window_sel_2_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
15.000 0.000 tNET RR 1 R7C8[2][A] u_la0_top/capture_window_sel_2_s1/CLK
14.689 -0.311 tSu 1 R7C8[2][A] u_la0_top/capture_window_sel_2_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 15.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.579, 4.072%; route: 13.250, 93.236%; tC2Q: 0.382, 2.691%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path9

Path Summary:

Slack 0.477
Data Arrival Time 14.212
Data Required Time 14.689
From u_la0_top/capture_end_dly_s0
To u_la0_top/capture_window_sel_3_s1
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 625 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
0.000 0.000 tNET RR 1 R4C11[2][B] u_la0_top/capture_end_dly_s0/CLK
0.382 0.382 tC2Q RR 3 R4C11[2][B] u_la0_top/capture_end_dly_s0/Q
2.595 2.213 tNET RR 1 R8C8[0][A] u_la0_top/capture_window_sel_10_s5/I1
3.174 0.579 tINS RR 10 R8C8[0][A] u_la0_top/capture_window_sel_10_s5/F
14.212 11.038 tNET RR 1 R7C8[1][B] u_la0_top/capture_window_sel_3_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
15.000 0.000 tNET RR 1 R7C8[1][B] u_la0_top/capture_window_sel_3_s1/CLK
14.689 -0.311 tSu 1 R7C8[1][B] u_la0_top/capture_window_sel_3_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 15.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.579, 4.072%; route: 13.250, 93.236%; tC2Q: 0.382, 2.691%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path10

Path Summary:

Slack 0.477
Data Arrival Time 14.212
Data Required Time 14.689
From u_la0_top/capture_end_dly_s0
To u_la0_top/capture_window_sel_4_s1
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 625 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
0.000 0.000 tNET RR 1 R4C11[2][B] u_la0_top/capture_end_dly_s0/CLK
0.382 0.382 tC2Q RR 3 R4C11[2][B] u_la0_top/capture_end_dly_s0/Q
2.595 2.213 tNET RR 1 R8C8[0][A] u_la0_top/capture_window_sel_10_s5/I1
3.174 0.579 tINS RR 10 R8C8[0][A] u_la0_top/capture_window_sel_10_s5/F
14.212 11.038 tNET RR 1 R7C8[1][A] u_la0_top/capture_window_sel_4_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
15.000 0.000 tNET RR 1 R7C8[1][A] u_la0_top/capture_window_sel_4_s1/CLK
14.689 -0.311 tSu 1 R7C8[1][A] u_la0_top/capture_window_sel_4_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 15.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.579, 4.072%; route: 13.250, 93.236%; tC2Q: 0.382, 2.691%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path11

Path Summary:

Slack 2.962
Data Arrival Time 17.935
Data Required Time 20.897
From odt_en_msk_s0
To hsrx_cnt_0_s1
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 625 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
6.069 6.069 tNET RR 1 R36C36[3][B] odt_en_msk_s0/CLK
6.436 0.368 tC2Q RF 5 R36C36[3][B] odt_en_msk_s0/Q
10.148 3.711 tNET FF 1 R2C3[0][A] odt_en_1_s0/I2
10.436 0.289 tINS FR 2 R2C3[0][A] odt_en_1_s0/F
12.085 1.649 tNET RR 1 R18C17[0][B] hsrx_cnt_5_s6/I3
12.344 0.259 tINS RF 7 R18C17[0][B] hsrx_cnt_5_s6/F
17.281 4.938 tNET FF 1 R57C55[1][B] hsrx_cnt_5_s8/I3
17.570 0.289 tINS FR 4 R57C55[1][B] hsrx_cnt_5_s8/F
17.935 0.365 tNET RR 1 R57C54[2][B] hsrx_cnt_0_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
21.208 6.208 tNET RR 1 R57C54[2][B] hsrx_cnt_0_s1/CLK
20.897 -0.311 tSu 1 R57C54[2][B] hsrx_cnt_0_s1

Path Statistics:

Clock Skew 0.139
Setup Relationship 15.000
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 6.069, 100.000%
Arrival Data Path Delay cell: 0.836, 7.047%; route: 10.663, 89.856%; tC2Q: 0.368, 3.097%
Required Clock Path Delay cell: 0.000, 0.000%; route: 6.208, 100.000%

Path12

Path Summary:

Slack 2.962
Data Arrival Time 17.935
Data Required Time 20.897
From odt_en_msk_s0
To hsrx_cnt_1_s1
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 625 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
6.069 6.069 tNET RR 1 R36C36[3][B] odt_en_msk_s0/CLK
6.436 0.368 tC2Q RF 5 R36C36[3][B] odt_en_msk_s0/Q
10.148 3.711 tNET FF 1 R2C3[0][A] odt_en_1_s0/I2
10.436 0.289 tINS FR 2 R2C3[0][A] odt_en_1_s0/F
12.085 1.649 tNET RR 1 R18C17[0][B] hsrx_cnt_5_s6/I3
12.344 0.259 tINS RF 7 R18C17[0][B] hsrx_cnt_5_s6/F
17.281 4.938 tNET FF 1 R57C55[1][B] hsrx_cnt_5_s8/I3
17.570 0.289 tINS FR 4 R57C55[1][B] hsrx_cnt_5_s8/F
17.935 0.365 tNET RR 1 R57C54[0][A] hsrx_cnt_1_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
21.208 6.208 tNET RR 1 R57C54[0][A] hsrx_cnt_1_s1/CLK
20.897 -0.311 tSu 1 R57C54[0][A] hsrx_cnt_1_s1

Path Statistics:

Clock Skew 0.139
Setup Relationship 15.000
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 6.069, 100.000%
Arrival Data Path Delay cell: 0.836, 7.047%; route: 10.663, 89.856%; tC2Q: 0.368, 3.097%
Required Clock Path Delay cell: 0.000, 0.000%; route: 6.208, 100.000%

Path13

Path Summary:

Slack 2.962
Data Arrival Time 17.935
Data Required Time 20.897
From odt_en_msk_s0
To hsrx_cnt_2_s1
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 625 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
6.069 6.069 tNET RR 1 R36C36[3][B] odt_en_msk_s0/CLK
6.436 0.368 tC2Q RF 5 R36C36[3][B] odt_en_msk_s0/Q
10.148 3.711 tNET FF 1 R2C3[0][A] odt_en_1_s0/I2
10.436 0.289 tINS FR 2 R2C3[0][A] odt_en_1_s0/F
12.085 1.649 tNET RR 1 R18C17[0][B] hsrx_cnt_5_s6/I3
12.344 0.259 tINS RF 7 R18C17[0][B] hsrx_cnt_5_s6/F
17.281 4.938 tNET FF 1 R57C55[1][B] hsrx_cnt_5_s8/I3
17.570 0.289 tINS FR 4 R57C55[1][B] hsrx_cnt_5_s8/F
17.935 0.365 tNET RR 1 R57C54[0][B] hsrx_cnt_2_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
21.208 6.208 tNET RR 1 R57C54[0][B] hsrx_cnt_2_s1/CLK
20.897 -0.311 tSu 1 R57C54[0][B] hsrx_cnt_2_s1

Path Statistics:

Clock Skew 0.139
Setup Relationship 15.000
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 6.069, 100.000%
Arrival Data Path Delay cell: 0.836, 7.047%; route: 10.663, 89.856%; tC2Q: 0.368, 3.097%
Required Clock Path Delay cell: 0.000, 0.000%; route: 6.208, 100.000%

Path14

Path Summary:

Slack 2.962
Data Arrival Time 17.935
Data Required Time 20.897
From odt_en_msk_s0
To hsrx_cnt_3_s1
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 625 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
6.069 6.069 tNET RR 1 R36C36[3][B] odt_en_msk_s0/CLK
6.436 0.368 tC2Q RF 5 R36C36[3][B] odt_en_msk_s0/Q
10.148 3.711 tNET FF 1 R2C3[0][A] odt_en_1_s0/I2
10.436 0.289 tINS FR 2 R2C3[0][A] odt_en_1_s0/F
12.085 1.649 tNET RR 1 R18C17[0][B] hsrx_cnt_5_s6/I3
12.344 0.259 tINS RF 7 R18C17[0][B] hsrx_cnt_5_s6/F
17.281 4.938 tNET FF 1 R57C55[1][B] hsrx_cnt_5_s8/I3
17.570 0.289 tINS FR 4 R57C55[1][B] hsrx_cnt_5_s8/F
17.935 0.365 tNET RR 1 R57C54[1][A] hsrx_cnt_3_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
21.208 6.208 tNET RR 1 R57C54[1][A] hsrx_cnt_3_s1/CLK
20.897 -0.311 tSu 1 R57C54[1][A] hsrx_cnt_3_s1

Path Statistics:

Clock Skew 0.139
Setup Relationship 15.000
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 6.069, 100.000%
Arrival Data Path Delay cell: 0.836, 7.047%; route: 10.663, 89.856%; tC2Q: 0.368, 3.097%
Required Clock Path Delay cell: 0.000, 0.000%; route: 6.208, 100.000%

Path15

Path Summary:

Slack 3.037
Data Arrival Time 18.108
Data Required Time 21.144
From odt_en_msk_s0
To hsrx_cnt_1_s1
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 625 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
6.069 6.069 tNET RR 1 R36C36[3][B] odt_en_msk_s0/CLK
6.436 0.368 tC2Q RF 5 R36C36[3][B] odt_en_msk_s0/Q
10.148 3.711 tNET FF 1 R2C3[0][A] odt_en_1_s0/I2
10.436 0.289 tINS FR 2 R2C3[0][A] odt_en_1_s0/F
12.085 1.649 tNET RR 1 R18C17[0][B] hsrx_cnt_5_s6/I3
12.374 0.289 tINS RR 7 R18C17[0][B] hsrx_cnt_5_s6/F
17.529 5.155 tNET RR 1 R57C54[0][A] n233_s1/I2
18.108 0.579 tINS RR 1 R57C54[0][A] n233_s1/F
18.108 0.000 tNET RR 1 R57C54[0][A] hsrx_cnt_1_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
21.208 6.208 tNET RR 1 R57C54[0][A] hsrx_cnt_1_s1/CLK
21.144 -0.064 tSu 1 R57C54[0][A] hsrx_cnt_1_s1

Path Statistics:

Clock Skew 0.139
Setup Relationship 15.000
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 6.069, 100.000%
Arrival Data Path Delay cell: 1.156, 9.604%; route: 10.515, 87.343%; tC2Q: 0.368, 3.053%
Required Clock Path Delay cell: 0.000, 0.000%; route: 6.208, 100.000%

Path16

Path Summary:

Slack 3.151
Data Arrival Time 17.994
Data Required Time 21.144
From odt_en_msk_s0
To hsrx_cnt_3_s1
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 625 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
6.069 6.069 tNET RR 1 R36C36[3][B] odt_en_msk_s0/CLK
6.436 0.368 tC2Q RF 5 R36C36[3][B] odt_en_msk_s0/Q
10.148 3.711 tNET FF 1 R2C3[0][A] odt_en_1_s0/I2
10.436 0.289 tINS FR 2 R2C3[0][A] odt_en_1_s0/F
12.085 1.649 tNET RR 1 R18C17[0][B] hsrx_cnt_5_s6/I3
12.374 0.289 tINS RR 7 R18C17[0][B] hsrx_cnt_5_s6/F
17.415 5.041 tNET RR 1 R57C54[1][A] n231_s1/I2
17.994 0.579 tINS RR 1 R57C54[1][A] n231_s1/F
17.994 0.000 tNET RR 1 R57C54[1][A] hsrx_cnt_3_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
21.208 6.208 tNET RR 1 R57C54[1][A] hsrx_cnt_3_s1/CLK
21.144 -0.064 tSu 1 R57C54[1][A] hsrx_cnt_3_s1

Path Statistics:

Clock Skew 0.139
Setup Relationship 15.000
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 6.069, 100.000%
Arrival Data Path Delay cell: 1.156, 9.696%; route: 10.401, 87.222%; tC2Q: 0.368, 3.082%
Required Clock Path Delay cell: 0.000, 0.000%; route: 6.208, 100.000%

Path17

Path Summary:

Slack 3.161
Data Arrival Time 17.974
Data Required Time 21.135
From odt_en_msk_s0
To hsrx_cnt_4_s3
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 625 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
6.069 6.069 tNET RR 1 R36C36[3][B] odt_en_msk_s0/CLK
6.436 0.368 tC2Q RF 5 R36C36[3][B] odt_en_msk_s0/Q
10.148 3.711 tNET FF 1 R2C3[0][A] odt_en_1_s0/I2
10.436 0.289 tINS FR 2 R2C3[0][A] odt_en_1_s0/F
12.085 1.649 tNET RR 1 R18C17[0][B] hsrx_cnt_5_s6/I3
12.374 0.289 tINS RR 7 R18C17[0][B] hsrx_cnt_5_s6/F
17.406 5.033 tNET RR 1 R57C55[2][A] n230_s4/I3
17.974 0.567 tINS RR 1 R57C55[2][A] n230_s4/F
17.974 0.000 tNET RR 1 R57C55[2][A] hsrx_cnt_4_s3/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
21.199 6.199 tNET RR 1 R57C55[2][A] hsrx_cnt_4_s3/CLK
21.135 -0.064 tSu 1 R57C55[2][A] hsrx_cnt_4_s3

Path Statistics:

Clock Skew 0.130
Setup Relationship 15.000
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 6.069, 100.000%
Arrival Data Path Delay cell: 1.145, 9.618%; route: 10.392, 87.295%; tC2Q: 0.368, 3.087%
Required Clock Path Delay cell: 0.000, 0.000%; route: 6.199, 100.000%

Path18

Path Summary:

Slack 3.221
Data Arrival Time 17.914
Data Required Time 21.135
From odt_en_msk_s0
To hsrx_cnt_5_s7
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 625 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
6.069 6.069 tNET RR 1 R36C36[3][B] odt_en_msk_s0/CLK
6.436 0.368 tC2Q RF 5 R36C36[3][B] odt_en_msk_s0/Q
10.148 3.711 tNET FF 1 R2C3[0][A] odt_en_1_s0/I2
10.436 0.289 tINS FR 2 R2C3[0][A] odt_en_1_s0/F
12.085 1.649 tNET RR 1 R18C17[0][B] hsrx_cnt_5_s6/I3
12.374 0.289 tINS RR 7 R18C17[0][B] hsrx_cnt_5_s6/F
17.406 5.033 tNET RR 1 R57C55[2][B] n229_s4/I3
17.914 0.507 tINS RR 1 R57C55[2][B] n229_s4/F
17.914 0.000 tNET RR 1 R57C55[2][B] hsrx_cnt_5_s7/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
21.199 6.199 tNET RR 1 R57C55[2][B] hsrx_cnt_5_s7/CLK
21.135 -0.064 tSu 1 R57C55[2][B] hsrx_cnt_5_s7

Path Statistics:

Clock Skew 0.130
Setup Relationship 15.000
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 6.069, 100.000%
Arrival Data Path Delay cell: 1.085, 9.160%; route: 10.392, 87.737%; tC2Q: 0.368, 3.103%
Required Clock Path Delay cell: 0.000, 0.000%; route: 6.199, 100.000%

Path19

Path Summary:

Slack 3.574
Data Arrival Time 17.570
Data Required Time 21.144
From odt_en_msk_s0
To hsrx_cnt_0_s1
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 625 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
6.069 6.069 tNET RR 1 R36C36[3][B] odt_en_msk_s0/CLK
6.436 0.368 tC2Q RF 5 R36C36[3][B] odt_en_msk_s0/Q
10.148 3.711 tNET FF 1 R2C3[0][A] odt_en_1_s0/I2
10.436 0.289 tINS FR 2 R2C3[0][A] odt_en_1_s0/F
12.085 1.649 tNET RR 1 R18C17[0][B] hsrx_cnt_5_s6/I3
12.344 0.259 tINS RF 7 R18C17[0][B] hsrx_cnt_5_s6/F
17.281 4.938 tNET FF 1 R57C54[2][B] n234_s2/I1
17.570 0.289 tINS FR 1 R57C54[2][B] n234_s2/F
17.570 0.000 tNET RR 1 R57C54[2][B] hsrx_cnt_0_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
21.208 6.208 tNET RR 1 R57C54[2][B] hsrx_cnt_0_s1/CLK
21.144 -0.064 tSu 1 R57C54[2][B] hsrx_cnt_0_s1

Path Statistics:

Clock Skew 0.139
Setup Relationship 15.000
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 6.069, 100.000%
Arrival Data Path Delay cell: 0.836, 7.271%; route: 10.298, 89.534%; tC2Q: 0.368, 3.195%
Required Clock Path Delay cell: 0.000, 0.000%; route: 6.208, 100.000%

Path20

Path Summary:

Slack 3.574
Data Arrival Time 17.570
Data Required Time 21.144
From odt_en_msk_s0
To hsrx_cnt_2_s1
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 625 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
6.069 6.069 tNET RR 1 R36C36[3][B] odt_en_msk_s0/CLK
6.436 0.368 tC2Q RF 5 R36C36[3][B] odt_en_msk_s0/Q
10.148 3.711 tNET FF 1 R2C3[0][A] odt_en_1_s0/I2
10.436 0.289 tINS FR 2 R2C3[0][A] odt_en_1_s0/F
12.085 1.649 tNET RR 1 R18C17[0][B] hsrx_cnt_5_s6/I3
12.344 0.259 tINS RF 7 R18C17[0][B] hsrx_cnt_5_s6/F
17.281 4.938 tNET FF 1 R57C54[0][B] n232_s2/I3
17.570 0.289 tINS FR 1 R57C54[0][B] n232_s2/F
17.570 0.000 tNET RR 1 R57C54[0][B] hsrx_cnt_2_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
21.208 6.208 tNET RR 1 R57C54[0][B] hsrx_cnt_2_s1/CLK
21.144 -0.064 tSu 1 R57C54[0][B] hsrx_cnt_2_s1

Path Statistics:

Clock Skew 0.139
Setup Relationship 15.000
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 6.069, 100.000%
Arrival Data Path Delay cell: 0.836, 7.271%; route: 10.298, 89.534%; tC2Q: 0.368, 3.195%
Required Clock Path Delay cell: 0.000, 0.000%; route: 6.208, 100.000%

Hold Analysis Report

Hold Analysis Report[1]:

Report Command:report_timing -hold -from_clock [get_clocks {pixel_clk}] -max_paths 20 -max_common_paths 1

Path1

Path Summary:

Slack 0.374
Data Arrival Time 1.621
Data Required Time 1.247
From u_bayer_rgb/video_format_detect_inst/hcnt_6_s3
To u_bayer_rgb/video_format_detect_inst/hcnt_6_s3
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLL_inst/CLKOUT1
1.246 1.246 tNET RR 1 R54C95[1][A] u_bayer_rgb/video_format_detect_inst/hcnt_6_s3/CLK
1.422 0.176 tC2Q RF 3 R54C95[1][A] u_bayer_rgb/video_format_detect_inst/hcnt_6_s3/Q
1.430 0.008 tNET FF 1 R54C95[1][A] u_bayer_rgb/video_format_detect_inst/n43_s6/I2
1.621 0.191 tINS FF 1 R54C95[1][A] u_bayer_rgb/video_format_detect_inst/n43_s6/F
1.621 0.000 tNET FF 1 R54C95[1][A] u_bayer_rgb/video_format_detect_inst/hcnt_6_s3/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLL_inst/CLKOUT1
1.246 1.246 tNET RR 1 R54C95[1][A] u_bayer_rgb/video_format_detect_inst/hcnt_6_s3/CLK
1.247 0.001 tHld 1 R54C95[1][A] u_bayer_rgb/video_format_detect_inst/hcnt_6_s3

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.246, 100.000%
Arrival Data Path Delay cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.246, 100.000%

Path2

Path Summary:

Slack 0.374
Data Arrival Time 1.614
Data Required Time 1.241
From u_bayer_rgb/video_format_detect_inst/hcnt_10_s1
To u_bayer_rgb/video_format_detect_inst/hcnt_10_s1
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLL_inst/CLKOUT1
1.239 1.239 tNET RR 1 R53C96[0][A] u_bayer_rgb/video_format_detect_inst/hcnt_10_s1/CLK
1.416 0.176 tC2Q RF 2 R53C96[0][A] u_bayer_rgb/video_format_detect_inst/hcnt_10_s1/Q
1.423 0.008 tNET FF 1 R53C96[0][A] u_bayer_rgb/video_format_detect_inst/n39_s2/I3
1.614 0.191 tINS FF 1 R53C96[0][A] u_bayer_rgb/video_format_detect_inst/n39_s2/F
1.614 0.000 tNET FF 1 R53C96[0][A] u_bayer_rgb/video_format_detect_inst/hcnt_10_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLL_inst/CLKOUT1
1.239 1.239 tNET RR 1 R53C96[0][A] u_bayer_rgb/video_format_detect_inst/hcnt_10_s1/CLK
1.241 0.001 tHld 1 R53C96[0][A] u_bayer_rgb/video_format_detect_inst/hcnt_10_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.239, 100.000%
Arrival Data Path Delay cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.239, 100.000%

Path3

Path Summary:

Slack 0.374
Data Arrival Time 1.621
Data Required Time 1.247
From u_bayer_rgb/dehcnt_0_s3
To u_bayer_rgb/dehcnt_0_s3
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLL_inst/CLKOUT1
1.246 1.246 tNET RR 1 R54C99[0][A] u_bayer_rgb/dehcnt_0_s3/CLK
1.422 0.176 tC2Q RF 2 R54C99[0][A] u_bayer_rgb/dehcnt_0_s3/Q
1.430 0.008 tNET FF 1 R54C99[0][A] u_bayer_rgb/n172_s5/I0
1.621 0.191 tINS FF 1 R54C99[0][A] u_bayer_rgb/n172_s5/F
1.621 0.000 tNET FF 1 R54C99[0][A] u_bayer_rgb/dehcnt_0_s3/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLL_inst/CLKOUT1
1.246 1.246 tNET RR 1 R54C99[0][A] u_bayer_rgb/dehcnt_0_s3/CLK
1.247 0.001 tHld 1 R54C99[0][A] u_bayer_rgb/dehcnt_0_s3

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.246, 100.000%
Arrival Data Path Delay cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.246, 100.000%

Path4

Path Summary:

Slack 0.374
Data Arrival Time 1.616
Data Required Time 1.242
From u_bayer_rgb/devcnt_1_s1
To u_bayer_rgb/devcnt_1_s1
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLL_inst/CLKOUT1
1.241 1.241 tNET RR 1 R54C124[0][A] u_bayer_rgb/devcnt_1_s1/CLK
1.417 0.176 tC2Q RF 5 R54C124[0][A] u_bayer_rgb/devcnt_1_s1/Q
1.425 0.008 tNET FF 1 R54C124[0][A] u_bayer_rgb/n99_s3/I2
1.616 0.191 tINS FF 1 R54C124[0][A] u_bayer_rgb/n99_s3/F
1.616 0.000 tNET FF 1 R54C124[0][A] u_bayer_rgb/devcnt_1_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLL_inst/CLKOUT1
1.241 1.241 tNET RR 1 R54C124[0][A] u_bayer_rgb/devcnt_1_s1/CLK
1.242 0.001 tHld 1 R54C124[0][A] u_bayer_rgb/devcnt_1_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.241, 100.000%
Arrival Data Path Delay cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.241, 100.000%

Path5

Path Summary:

Slack 0.374
Data Arrival Time 1.621
Data Required Time 1.247
From u_bayer_rgb/devcnt_15_s1
To u_bayer_rgb/devcnt_15_s1
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLL_inst/CLKOUT1
1.246 1.246 tNET RR 1 R54C127[0][A] u_bayer_rgb/devcnt_15_s1/CLK
1.422 0.176 tC2Q RF 2 R54C127[0][A] u_bayer_rgb/devcnt_15_s1/Q
1.430 0.008 tNET FF 1 R54C127[0][A] u_bayer_rgb/n85_s2/I3
1.621 0.191 tINS FF 1 R54C127[0][A] u_bayer_rgb/n85_s2/F
1.621 0.000 tNET FF 1 R54C127[0][A] u_bayer_rgb/devcnt_15_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLL_inst/CLKOUT1
1.246 1.246 tNET RR 1 R54C127[0][A] u_bayer_rgb/devcnt_15_s1/CLK
1.247 0.001 tHld 1 R54C127[0][A] u_bayer_rgb/devcnt_15_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.246, 100.000%
Arrival Data Path Delay cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.246, 100.000%

Path6

Path Summary:

Slack 0.377
Data Arrival Time 1.611
Data Required Time 1.234
From u_bayer_rgb/shift_line_inst0/shiftin_addr_0_s0
To u_bayer_rgb/shift_line_inst0/shiftin_addr_0_s0
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLL_inst/CLKOUT1
1.232 1.232 tNET RR 1 R47C118[0][A] u_bayer_rgb/shift_line_inst0/shiftin_addr_0_s0/CLK
1.409 0.176 tC2Q RF 4 R47C118[0][A] u_bayer_rgb/shift_line_inst0/shiftin_addr_0_s0/Q
1.420 0.011 tNET FF 1 R47C118[0][A] u_bayer_rgb/shift_line_inst0/n24_s2/I0
1.611 0.191 tINS FF 1 R47C118[0][A] u_bayer_rgb/shift_line_inst0/n24_s2/F
1.611 0.000 tNET FF 1 R47C118[0][A] u_bayer_rgb/shift_line_inst0/shiftin_addr_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLL_inst/CLKOUT1
1.232 1.232 tNET RR 1 R47C118[0][A] u_bayer_rgb/shift_line_inst0/shiftin_addr_0_s0/CLK
1.234 0.001 tHld 1 R47C118[0][A] u_bayer_rgb/shift_line_inst0/shiftin_addr_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.232, 100.000%
Arrival Data Path Delay cell: 0.191, 50.495%; route: 0.011, 2.970%; tC2Q: 0.176, 46.535%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.232, 100.000%

Path7

Path Summary:

Slack 0.377
Data Arrival Time 1.618
Data Required Time 1.241
From u_bayer_rgb/video_format_detect_inst/hcnt_7_s3
To u_bayer_rgb/video_format_detect_inst/hcnt_7_s3
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLL_inst/CLKOUT1
1.239 1.239 tNET RR 1 R53C96[1][A] u_bayer_rgb/video_format_detect_inst/hcnt_7_s3/CLK
1.416 0.176 tC2Q RF 4 R53C96[1][A] u_bayer_rgb/video_format_detect_inst/hcnt_7_s3/Q
1.427 0.011 tNET FF 1 R53C96[1][A] u_bayer_rgb/video_format_detect_inst/n42_s6/I2
1.618 0.191 tINS FF 1 R53C96[1][A] u_bayer_rgb/video_format_detect_inst/n42_s6/F
1.618 0.000 tNET FF 1 R53C96[1][A] u_bayer_rgb/video_format_detect_inst/hcnt_7_s3/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLL_inst/CLKOUT1
1.239 1.239 tNET RR 1 R53C96[1][A] u_bayer_rgb/video_format_detect_inst/hcnt_7_s3/CLK
1.241 0.001 tHld 1 R53C96[1][A] u_bayer_rgb/video_format_detect_inst/hcnt_7_s3

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.239, 100.000%
Arrival Data Path Delay cell: 0.191, 50.495%; route: 0.011, 2.970%; tC2Q: 0.176, 46.535%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.239, 100.000%

Path8

Path Summary:

Slack 0.377
Data Arrival Time 1.620
Data Required Time 1.242
From u_bayer_rgb/video_format_detect_inst/hcnt_8_s1
To u_bayer_rgb/video_format_detect_inst/hcnt_8_s1
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLL_inst/CLKOUT1
1.241 1.241 tNET RR 1 R54C96[0][A] u_bayer_rgb/video_format_detect_inst/hcnt_8_s1/CLK
1.417 0.176 tC2Q RF 3 R54C96[0][A] u_bayer_rgb/video_format_detect_inst/hcnt_8_s1/Q
1.428 0.011 tNET FF 1 R54C96[0][A] u_bayer_rgb/video_format_detect_inst/n41_s2/I3
1.620 0.191 tINS FF 1 R54C96[0][A] u_bayer_rgb/video_format_detect_inst/n41_s2/F
1.620 0.000 tNET FF 1 R54C96[0][A] u_bayer_rgb/video_format_detect_inst/hcnt_8_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLL_inst/CLKOUT1
1.241 1.241 tNET RR 1 R54C96[0][A] u_bayer_rgb/video_format_detect_inst/hcnt_8_s1/CLK
1.242 0.001 tHld 1 R54C96[0][A] u_bayer_rgb/video_format_detect_inst/hcnt_8_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.241, 100.000%
Arrival Data Path Delay cell: 0.191, 50.495%; route: 0.011, 2.970%; tC2Q: 0.176, 46.535%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.241, 100.000%

Path9

Path Summary:

Slack 0.377
Data Arrival Time 1.615
Data Required Time 1.237
From u_bayer_rgb/devcnt_4_s1
To u_bayer_rgb/devcnt_4_s1
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLL_inst/CLKOUT1
1.236 1.236 tNET RR 1 R54C125[1][A] u_bayer_rgb/devcnt_4_s1/CLK
1.412 0.176 tC2Q RF 5 R54C125[1][A] u_bayer_rgb/devcnt_4_s1/Q
1.423 0.011 tNET FF 1 R54C125[1][A] u_bayer_rgb/n96_s4/I2
1.615 0.191 tINS FF 1 R54C125[1][A] u_bayer_rgb/n96_s4/F
1.615 0.000 tNET FF 1 R54C125[1][A] u_bayer_rgb/devcnt_4_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLL_inst/CLKOUT1
1.236 1.236 tNET RR 1 R54C125[1][A] u_bayer_rgb/devcnt_4_s1/CLK
1.237 0.001 tHld 1 R54C125[1][A] u_bayer_rgb/devcnt_4_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.236, 100.000%
Arrival Data Path Delay cell: 0.191, 50.495%; route: 0.011, 2.970%; tC2Q: 0.176, 46.535%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.236, 100.000%

Path10

Path Summary:

Slack 0.377
Data Arrival Time 1.620
Data Required Time 1.242
From u_bayer_rgb/devcnt_5_s1
To u_bayer_rgb/devcnt_5_s1
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLL_inst/CLKOUT1
1.241 1.241 tNET RR 1 R54C126[0][A] u_bayer_rgb/devcnt_5_s1/CLK
1.417 0.176 tC2Q RF 4 R54C126[0][A] u_bayer_rgb/devcnt_5_s1/Q
1.428 0.011 tNET FF 1 R54C126[0][A] u_bayer_rgb/n95_s2/I3
1.620 0.191 tINS FF 1 R54C126[0][A] u_bayer_rgb/n95_s2/F
1.620 0.000 tNET FF 1 R54C126[0][A] u_bayer_rgb/devcnt_5_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLL_inst/CLKOUT1
1.241 1.241 tNET RR 1 R54C126[0][A] u_bayer_rgb/devcnt_5_s1/CLK
1.242 0.001 tHld 1 R54C126[0][A] u_bayer_rgb/devcnt_5_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.241, 100.000%
Arrival Data Path Delay cell: 0.191, 50.495%; route: 0.011, 2.970%; tC2Q: 0.176, 46.535%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.241, 100.000%

Path11

Path Summary:

Slack 0.377
Data Arrival Time 1.620
Data Required Time 1.242
From u_bayer_rgb/devcnt_7_s1
To u_bayer_rgb/devcnt_7_s1
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLL_inst/CLKOUT1
1.241 1.241 tNET RR 1 R54C126[1][A] u_bayer_rgb/devcnt_7_s1/CLK
1.417 0.176 tC2Q RF 6 R54C126[1][A] u_bayer_rgb/devcnt_7_s1/Q
1.428 0.011 tNET FF 1 R54C126[1][A] u_bayer_rgb/n93_s4/I2
1.620 0.191 tINS FF 1 R54C126[1][A] u_bayer_rgb/n93_s4/F
1.620 0.000 tNET FF 1 R54C126[1][A] u_bayer_rgb/devcnt_7_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLL_inst/CLKOUT1
1.241 1.241 tNET RR 1 R54C126[1][A] u_bayer_rgb/devcnt_7_s1/CLK
1.242 0.001 tHld 1 R54C126[1][A] u_bayer_rgb/devcnt_7_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.241, 100.000%
Arrival Data Path Delay cell: 0.191, 50.495%; route: 0.011, 2.970%; tC2Q: 0.176, 46.535%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.241, 100.000%

Path12

Path Summary:

Slack 0.377
Data Arrival Time 1.646
Data Required Time 1.269
From u_b2p/u_b2p_inst/out_cnt_0_s3
To u_b2p/u_b2p_inst/out_cnt_0_s3
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLL_inst/CLKOUT1
1.267 1.267 tNET RR 1 R57C90[0][A] u_b2p/u_b2p_inst/out_cnt_0_s3/CLK
1.444 0.176 tC2Q RF 6 R57C90[0][A] u_b2p/u_b2p_inst/out_cnt_0_s3/Q
1.455 0.011 tNET FF 1 R57C90[0][A] u_b2p/u_b2p_inst/n1907_s9/I0
1.646 0.191 tINS FF 1 R57C90[0][A] u_b2p/u_b2p_inst/n1907_s9/F
1.646 0.000 tNET FF 1 R57C90[0][A] u_b2p/u_b2p_inst/out_cnt_0_s3/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLL_inst/CLKOUT1
1.267 1.267 tNET RR 1 R57C90[0][A] u_b2p/u_b2p_inst/out_cnt_0_s3/CLK
1.269 0.001 tHld 1 R57C90[0][A] u_b2p/u_b2p_inst/out_cnt_0_s3

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.267, 100.000%
Arrival Data Path Delay cell: 0.191, 50.495%; route: 0.011, 2.970%; tC2Q: 0.176, 46.535%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.267, 100.000%

Path13

Path Summary:

Slack 0.381
Data Arrival Time 1.628
Data Required Time 1.247
From u_bayer_rgb/devcnt_11_s1
To u_bayer_rgb/devcnt_11_s1
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLL_inst/CLKOUT1
1.246 1.246 tNET RR 1 R54C127[1][A] u_bayer_rgb/devcnt_11_s1/CLK
1.422 0.176 tC2Q RF 4 R54C127[1][A] u_bayer_rgb/devcnt_11_s1/Q
1.437 0.015 tNET FF 1 R54C127[1][A] u_bayer_rgb/n89_s2/I3
1.628 0.191 tINS FF 1 R54C127[1][A] u_bayer_rgb/n89_s2/F
1.628 0.000 tNET FF 1 R54C127[1][A] u_bayer_rgb/devcnt_11_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLL_inst/CLKOUT1
1.246 1.246 tNET RR 1 R54C127[1][A] u_bayer_rgb/devcnt_11_s1/CLK
1.247 0.001 tHld 1 R54C127[1][A] u_bayer_rgb/devcnt_11_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.246, 100.000%
Arrival Data Path Delay cell: 0.191, 50.000%; route: 0.015, 3.922%; tC2Q: 0.176, 46.078%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.246, 100.000%

Path14

Path Summary:

Slack 0.389
Data Arrival Time 1.636
Data Required Time 1.247
From u_bayer_rgb/devcnt_0_s1
To u_bayer_rgb/devcnt_0_s1
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLL_inst/CLKOUT1
1.246 1.246 tNET RR 1 R54C123[0][A] u_bayer_rgb/devcnt_0_s1/CLK
1.426 0.180 tC2Q RR 6 R54C123[0][A] u_bayer_rgb/devcnt_0_s1/Q
1.445 0.019 tNET RR 1 R54C123[0][A] u_bayer_rgb/n100_s3/I0
1.636 0.191 tINS RF 1 R54C123[0][A] u_bayer_rgb/n100_s3/F
1.636 0.000 tNET FF 1 R54C123[0][A] u_bayer_rgb/devcnt_0_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLL_inst/CLKOUT1
1.246 1.246 tNET RR 1 R54C123[0][A] u_bayer_rgb/devcnt_0_s1/CLK
1.247 0.001 tHld 1 R54C123[0][A] u_bayer_rgb/devcnt_0_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.246, 100.000%
Arrival Data Path Delay cell: 0.191, 49.038%; route: 0.019, 4.808%; tC2Q: 0.180, 46.154%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.246, 100.000%

Path15

Path Summary:

Slack 0.444
Data Arrival Time 1.681
Data Required Time 1.237
From u_bayer_rgb/devcnt_6_s1
To u_bayer_rgb/devcnt_6_s1
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLL_inst/CLKOUT1
1.236 1.236 tNET RR 1 R54C125[2][A] u_bayer_rgb/devcnt_6_s1/CLK
1.412 0.176 tC2Q RF 3 R54C125[2][A] u_bayer_rgb/devcnt_6_s1/Q
1.423 0.011 tNET FF 1 R54C125[2][A] u_bayer_rgb/n94_s4/I3
1.681 0.257 tINS FF 1 R54C125[2][A] u_bayer_rgb/n94_s4/F
1.681 0.000 tNET FF 1 R54C125[2][A] u_bayer_rgb/devcnt_6_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLL_inst/CLKOUT1
1.236 1.236 tNET RR 1 R54C125[2][A] u_bayer_rgb/devcnt_6_s1/CLK
1.237 0.001 tHld 1 R54C125[2][A] u_bayer_rgb/devcnt_6_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.236, 100.000%
Arrival Data Path Delay cell: 0.257, 57.865%; route: 0.011, 2.528%; tC2Q: 0.176, 39.607%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.236, 100.000%

Path16

Path Summary:

Slack 0.449
Data Arrival Time 1.691
Data Required Time 1.242
From u_bayer_rgb/video_format_detect_inst/vd_hres_2_s0
To u_bayer_rgb/video_format_detect_inst/vd_hres_reg_2_s0
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLL_inst/CLKOUT1
1.241 1.241 tNET RR 1 R54C100[2][B] u_bayer_rgb/video_format_detect_inst/vd_hres_2_s0/CLK
1.417 0.176 tC2Q RF 1 R54C100[2][B] u_bayer_rgb/video_format_detect_inst/vd_hres_2_s0/Q
1.691 0.274 tNET FF 1 R54C100[1][B] u_bayer_rgb/video_format_detect_inst/vd_hres_reg_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLL_inst/CLKOUT1
1.241 1.241 tNET RR 1 R54C100[1][B] u_bayer_rgb/video_format_detect_inst/vd_hres_reg_2_s0/CLK
1.242 0.001 tHld 1 R54C100[1][B] u_bayer_rgb/video_format_detect_inst/vd_hres_reg_2_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.241, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.274, 60.833%; tC2Q: 0.176, 39.167%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.241, 100.000%

Path17

Path Summary:

Slack 0.449
Data Arrival Time 1.691
Data Required Time 1.242
From u_bayer_rgb/video_format_detect_inst/vd_hres_5_s0
To u_bayer_rgb/video_format_detect_inst/vd_hres_reg_5_s0
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLL_inst/CLKOUT1
1.241 1.241 tNET RR 1 R54C100[2][A] u_bayer_rgb/video_format_detect_inst/vd_hres_5_s0/CLK
1.417 0.176 tC2Q RF 1 R54C100[2][A] u_bayer_rgb/video_format_detect_inst/vd_hres_5_s0/Q
1.691 0.274 tNET FF 1 R54C100[1][A] u_bayer_rgb/video_format_detect_inst/vd_hres_reg_5_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLL_inst/CLKOUT1
1.241 1.241 tNET RR 1 R54C100[1][A] u_bayer_rgb/video_format_detect_inst/vd_hres_reg_5_s0/CLK
1.242 0.001 tHld 1 R54C100[1][A] u_bayer_rgb/video_format_detect_inst/vd_hres_reg_5_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.241, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.274, 60.833%; tC2Q: 0.176, 39.167%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.241, 100.000%

Path18

Path Summary:

Slack 0.449
Data Arrival Time 1.691
Data Required Time 1.242
From u_bayer_rgb/b_o_1_s0
To pxl_b_r_1_s0
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLL_inst/CLKOUT1
1.241 1.241 tNET RR 1 R54C112[3][A] u_bayer_rgb/b_o_1_s0/CLK
1.417 0.176 tC2Q RF 1 R54C112[3][A] u_bayer_rgb/b_o_1_s0/Q
1.691 0.274 tNET FF 1 R54C112[0][A] pxl_b_r_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLL_inst/CLKOUT1
1.241 1.241 tNET RR 1 R54C112[0][A] pxl_b_r_1_s0/CLK
1.242 0.001 tHld 1 R54C112[0][A] pxl_b_r_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.241, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.274, 60.833%; tC2Q: 0.176, 39.167%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.241, 100.000%

Path19

Path Summary:

Slack 0.449
Data Arrival Time 1.694
Data Required Time 1.246
From u_bayer_rgb/g_o_5_s0
To pxl_g_r_5_s0
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLL_inst/CLKOUT1
1.244 1.244 tNET RR 1 R53C115[1][B] u_bayer_rgb/g_o_5_s0/CLK
1.421 0.176 tC2Q RF 1 R53C115[1][B] u_bayer_rgb/g_o_5_s0/Q
1.694 0.274 tNET FF 1 R53C115[2][A] pxl_g_r_5_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLL_inst/CLKOUT1
1.244 1.244 tNET RR 1 R53C115[2][A] pxl_g_r_5_s0/CLK
1.246 0.001 tHld 1 R53C115[2][A] pxl_g_r_5_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.244, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.274, 60.833%; tC2Q: 0.176, 39.167%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.244, 100.000%

Path20

Path Summary:

Slack 0.449
Data Arrival Time 1.696
Data Required Time 1.247
From u_bayer_rgb/de_tmp3_s0
To u_bayer_rgb/de_o_s0
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLL_inst/CLKOUT1
1.246 1.246 tNET RR 1 R54C107[3][A] u_bayer_rgb/de_tmp3_s0/CLK
1.422 0.176 tC2Q RF 1 R54C107[3][A] u_bayer_rgb/de_tmp3_s0/Q
1.696 0.274 tNET FF 1 R54C107[1][A] u_bayer_rgb/de_o_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 244 PLL_L[0] u_pll/PLL_inst/CLKOUT1
1.246 1.246 tNET RR 1 R54C107[1][A] u_bayer_rgb/de_o_s0/CLK
1.247 0.001 tHld 1 R54C107[1][A] u_bayer_rgb/de_o_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.246, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.274, 60.833%; tC2Q: 0.176, 39.167%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.246, 100.000%

Hold Analysis Report[2]:

Report Command:report_timing -hold -from_clock [get_clocks {byte_clk}] -max_paths 20 -max_common_paths 1

Path1

Path Summary:

Slack 0.263
Data Arrival Time 0.512
Data Required Time 0.249
From u_la0_top/u_ao_mem_ctrl/data_reg_54_s0
To u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 625 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
0.000 0.000 tNET RR 1 R7C6[2][B] u_la0_top/u_ao_mem_ctrl/data_reg_54_s0/CLK
0.180 0.180 tC2Q RR 1 R7C6[2][B] u_la0_top/u_ao_mem_ctrl/data_reg_54_s0/Q
0.512 0.332 tNET RR 1 BSRAM_R10[1][B] u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/DI[0]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 1 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
0.000 0.000 tNET RR 1 BSRAM_R10[1][B] u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/CLKA
0.249 0.249 tHld 1 BSRAM_R10[1][B] u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.332, 64.878%; tC2Q: 0.180, 35.122%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path2

Path Summary:

Slack 0.266
Data Arrival Time 3.698
Data Required Time 3.433
From u_b2p/u_b2p_inst/rBufD_8_s1
To u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 625 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
3.213 3.213 tNET RR 1 R56C86[3][A] u_b2p/u_b2p_inst/rBufD_8_s1/CLK
3.393 0.180 tC2Q RR 1 R56C86[3][A] u_b2p/u_b2p_inst/rBufD_8_s1/Q
3.698 0.305 tNET RR 1 BSRAM_R64[18][A] u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s/DI[8]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 1 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
3.184 3.184 tNET RR 1 BSRAM_R64[18][A] u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s/CLKA
3.433 0.249 tHld 1 BSRAM_R64[18][A] u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s

Path Statistics:

Clock Skew -0.030
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.213, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.305, 62.887%; tC2Q: 0.180, 37.113%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path3

Path Summary:

Slack 0.266
Data Arrival Time 3.698
Data Required Time 3.433
From u_b2p/u_b2p_inst/rBufD_7_s1
To u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 625 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
3.213 3.213 tNET RR 1 R56C84[1][B] u_b2p/u_b2p_inst/rBufD_7_s1/CLK
3.393 0.180 tC2Q RR 1 R56C84[1][B] u_b2p/u_b2p_inst/rBufD_7_s1/Q
3.698 0.305 tNET RR 1 BSRAM_R64[18][A] u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s/DI[7]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 1 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
3.184 3.184 tNET RR 1 BSRAM_R64[18][A] u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s/CLKA
3.433 0.249 tHld 1 BSRAM_R64[18][A] u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s

Path Statistics:

Clock Skew -0.030
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.213, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.305, 62.887%; tC2Q: 0.180, 37.113%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path4

Path Summary:

Slack 0.266
Data Arrival Time 3.698
Data Required Time 3.433
From u_b2p/u_b2p_inst/rBufD_6_s1
To u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 625 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
3.213 3.213 tNET RR 1 R56C84[0][B] u_b2p/u_b2p_inst/rBufD_6_s1/CLK
3.393 0.180 tC2Q RR 1 R56C84[0][B] u_b2p/u_b2p_inst/rBufD_6_s1/Q
3.698 0.305 tNET RR 1 BSRAM_R64[18][A] u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s/DI[6]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 1 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
3.184 3.184 tNET RR 1 BSRAM_R64[18][A] u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s/CLKA
3.433 0.249 tHld 1 BSRAM_R64[18][A] u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s

Path Statistics:

Clock Skew -0.030
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.213, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.305, 62.887%; tC2Q: 0.180, 37.113%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path5

Path Summary:

Slack 0.294
Data Arrival Time 0.412
Data Required Time 0.118
From u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
To u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 625 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
0.000 0.000 tNET RR 1 R6C10[0][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
0.180 0.180 tC2Q RR 15 R6C10[0][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/Q
0.412 0.233 tNET RR 1 BSRAM_R10[1][B] u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/ADA[4]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 1 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
0.000 0.000 tNET RR 1 BSRAM_R10[1][B] u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/CLKA
0.118 0.118 tHld 1 BSRAM_R10[1][B] u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.233, 56.364%; tC2Q: 0.180, 43.636%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path6

Path Summary:

Slack 0.295
Data Arrival Time 0.544
Data Required Time 0.249
From u_la0_top/u_ao_mem_ctrl/data_reg_60_s0
To u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 625 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
0.000 0.000 tNET RR 1 R8C5[2][B] u_la0_top/u_ao_mem_ctrl/data_reg_60_s0/CLK
0.180 0.180 tC2Q RR 1 R8C5[2][B] u_la0_top/u_ao_mem_ctrl/data_reg_60_s0/Q
0.544 0.364 tNET RR 1 BSRAM_R10[1][B] u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/DI[6]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 1 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
0.000 0.000 tNET RR 1 BSRAM_R10[1][B] u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/CLKA
0.249 0.249 tHld 1 BSRAM_R10[1][B] u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.364, 66.897%; tC2Q: 0.180, 33.103%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path7

Path Summary:

Slack 0.305
Data Arrival Time 0.554
Data Required Time 0.249
From u_la0_top/u_ao_mem_ctrl/data_reg_22_s0
To u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 625 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
0.000 0.000 tNET RR 1 R9C13[2][B] u_la0_top/u_ao_mem_ctrl/data_reg_22_s0/CLK
0.180 0.180 tC2Q RR 1 R9C13[2][B] u_la0_top/u_ao_mem_ctrl/data_reg_22_s0/Q
0.554 0.374 tNET RR 1 BSRAM_R10[1][A] u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[4]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 1 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
0.000 0.000 tNET RR 1 BSRAM_R10[1][A] u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA
0.249 0.249 tHld 1 BSRAM_R10[1][A] u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.374, 67.494%; tC2Q: 0.180, 32.506%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path8

Path Summary:

Slack 0.310
Data Arrival Time 0.428
Data Required Time 0.118
From u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
To u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 625 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
0.000 0.000 tNET RR 1 R6C10[1][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
0.180 0.180 tC2Q RR 15 R6C10[1][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/Q
0.428 0.248 tNET RR 1 BSRAM_R10[1][B] u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/ADA[7]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 1 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
0.000 0.000 tNET RR 1 BSRAM_R10[1][B] u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/CLKA
0.118 0.118 tHld 1 BSRAM_R10[1][B] u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.248, 57.895%; tC2Q: 0.180, 42.105%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path9

Path Summary:

Slack 0.310
Data Arrival Time 0.428
Data Required Time 0.118
From u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
To u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 625 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
0.000 0.000 tNET RR 1 R6C10[1][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK
0.180 0.180 tC2Q RR 13 R6C10[1][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/Q
0.428 0.248 tNET RR 1 BSRAM_R10[1][B] u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/ADA[6]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 1 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
0.000 0.000 tNET RR 1 BSRAM_R10[1][B] u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/CLKA
0.118 0.118 tHld 1 BSRAM_R10[1][B] u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.248, 57.895%; tC2Q: 0.180, 42.105%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path10

Path Summary:

Slack 0.319
Data Arrival Time 0.438
Data Required Time 0.118
From u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1
To u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 625 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
0.000 0.000 tNET RR 1 R6C10[0][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK
0.180 0.180 tC2Q RR 14 R6C10[0][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/Q
0.438 0.257 tNET RR 1 BSRAM_R10[1][B] u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/ADA[5]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 1 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
0.000 0.000 tNET RR 1 BSRAM_R10[1][B] u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/CLKA
0.118 0.118 tHld 1 BSRAM_R10[1][B] u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.257, 58.857%; tC2Q: 0.180, 41.143%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path11

Path Summary:

Slack 0.323
Data Arrival Time 0.441
Data Required Time 0.118
From u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
To u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 625 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
0.000 0.000 tNET RR 1 R6C10[0][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
0.180 0.180 tC2Q RR 15 R6C10[0][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/Q
0.441 0.261 tNET RR 1 BSRAM_R10[1][A] u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/ADA[4]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 1 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
0.000 0.000 tNET RR 1 BSRAM_R10[1][A] u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA
0.118 0.118 tHld 1 BSRAM_R10[1][A] u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.261, 59.207%; tC2Q: 0.180, 40.793%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path12

Path Summary:

Slack 0.345
Data Arrival Time 0.594
Data Required Time 0.249
From u_la0_top/u_ao_mem_ctrl/data_reg_23_s0
To u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 625 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
0.000 0.000 tNET RR 1 R7C6[0][A] u_la0_top/u_ao_mem_ctrl/data_reg_23_s0/CLK
0.180 0.180 tC2Q RR 1 R7C6[0][A] u_la0_top/u_ao_mem_ctrl/data_reg_23_s0/Q
0.594 0.414 tNET RR 1 BSRAM_R10[1][A] u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[5]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 1 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
0.000 0.000 tNET RR 1 BSRAM_R10[1][A] u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA
0.249 0.249 tHld 1 BSRAM_R10[1][A] u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.414, 69.684%; tC2Q: 0.180, 30.316%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path13

Path Summary:

Slack 0.367
Data Arrival Time 0.616
Data Required Time 0.249
From u_la0_top/u_ao_mem_ctrl/data_reg_59_s0
To u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 625 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
0.000 0.000 tNET RR 1 R8C5[2][A] u_la0_top/u_ao_mem_ctrl/data_reg_59_s0/CLK
0.180 0.180 tC2Q RR 1 R8C5[2][A] u_la0_top/u_ao_mem_ctrl/data_reg_59_s0/Q
0.616 0.436 tNET RR 1 BSRAM_R10[1][B] u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/DI[5]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 1 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
0.000 0.000 tNET RR 1 BSRAM_R10[1][B] u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/CLKA
0.249 0.249 tHld 1 BSRAM_R10[1][B] u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.436, 70.791%; tC2Q: 0.180, 29.209%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path14

Path Summary:

Slack 0.367
Data Arrival Time 0.616
Data Required Time 0.249
From u_la0_top/u_ao_mem_ctrl/data_reg_57_s0
To u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 625 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
0.000 0.000 tNET RR 1 R8C5[1][B] u_la0_top/u_ao_mem_ctrl/data_reg_57_s0/CLK
0.180 0.180 tC2Q RR 1 R8C5[1][B] u_la0_top/u_ao_mem_ctrl/data_reg_57_s0/Q
0.616 0.436 tNET RR 1 BSRAM_R10[1][B] u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/DI[3]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 1 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
0.000 0.000 tNET RR 1 BSRAM_R10[1][B] u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/CLKA
0.249 0.249 tHld 1 BSRAM_R10[1][B] u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.436, 70.791%; tC2Q: 0.180, 29.209%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path15

Path Summary:

Slack 0.367
Data Arrival Time 0.616
Data Required Time 0.249
From u_la0_top/u_ao_mem_ctrl/data_reg_56_s0
To u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 625 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
0.000 0.000 tNET RR 1 R8C5[1][A] u_la0_top/u_ao_mem_ctrl/data_reg_56_s0/CLK
0.180 0.180 tC2Q RR 1 R8C5[1][A] u_la0_top/u_ao_mem_ctrl/data_reg_56_s0/Q
0.616 0.436 tNET RR 1 BSRAM_R10[1][B] u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/DI[2]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 1 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
0.000 0.000 tNET RR 1 BSRAM_R10[1][B] u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/CLKA
0.249 0.249 tHld 1 BSRAM_R10[1][B] u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.436, 70.791%; tC2Q: 0.180, 29.209%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path16

Path Summary:

Slack 0.374
Data Arrival Time 3.588
Data Required Time 3.215
From u_b2p/u_b2p_inst/wc_cnt_dec_5_s1
To u_b2p/u_b2p_inst/wc_cnt_dec_5_s1
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 625 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
3.213 3.213 tNET RR 1 R56C78[0][A] u_b2p/u_b2p_inst/wc_cnt_dec_5_s1/CLK
3.390 0.176 tC2Q RF 5 R56C78[0][A] u_b2p/u_b2p_inst/wc_cnt_dec_5_s1/Q
3.397 0.008 tNET FF 1 R56C78[0][A] u_b2p/u_b2p_inst/n1157_s0/I1
3.588 0.191 tINS FF 1 R56C78[0][A] u_b2p/u_b2p_inst/n1157_s0/F
3.588 0.000 tNET FF 1 R56C78[0][A] u_b2p/u_b2p_inst/wc_cnt_dec_5_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 1 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
3.213 3.213 tNET RR 1 R56C78[0][A] u_b2p/u_b2p_inst/wc_cnt_dec_5_s1/CLK
3.215 0.001 tHld 1 R56C78[0][A] u_b2p/u_b2p_inst/wc_cnt_dec_5_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.213, 100.000%
Arrival Data Path Delay cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.213, 100.000%

Path17

Path Summary:

Slack 0.374
Data Arrival Time 3.581
Data Required Time 3.208
From u_b2p/u_b2p_inst/wc_cnt_dec_8_s1
To u_b2p/u_b2p_inst/wc_cnt_dec_8_s1
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 625 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
3.206 3.206 tNET RR 1 R57C79[1][A] u_b2p/u_b2p_inst/wc_cnt_dec_8_s1/CLK
3.383 0.176 tC2Q RF 2 R57C79[1][A] u_b2p/u_b2p_inst/wc_cnt_dec_8_s1/Q
3.390 0.008 tNET FF 1 R57C79[1][A] u_b2p/u_b2p_inst/n1154_s0/I1
3.581 0.191 tINS FF 1 R57C79[1][A] u_b2p/u_b2p_inst/n1154_s0/F
3.581 0.000 tNET FF 1 R57C79[1][A] u_b2p/u_b2p_inst/wc_cnt_dec_8_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 1 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
3.206 3.206 tNET RR 1 R57C79[1][A] u_b2p/u_b2p_inst/wc_cnt_dec_8_s1/CLK
3.208 0.001 tHld 1 R57C79[1][A] u_b2p/u_b2p_inst/wc_cnt_dec_8_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.206, 100.000%
Arrival Data Path Delay cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.206, 100.000%

Path18

Path Summary:

Slack 0.374
Data Arrival Time 3.583
Data Required Time 3.210
From u_csi_rx/u_dsi_csi2/rWcCnt_10_s0
To u_csi_rx/u_dsi_csi2/rWcCnt_10_s0
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 625 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
3.208 3.208 tNET RR 1 R56C71[0][A] u_csi_rx/u_dsi_csi2/rWcCnt_10_s0/CLK
3.385 0.176 tC2Q RF 5 R56C71[0][A] u_csi_rx/u_dsi_csi2/rWcCnt_10_s0/Q
3.392 0.008 tNET FF 1 R56C71[0][A] u_csi_rx/u_dsi_csi2/n600_s1/I2
3.583 0.191 tINS FF 1 R56C71[0][A] u_csi_rx/u_dsi_csi2/n600_s1/F
3.583 0.000 tNET FF 1 R56C71[0][A] u_csi_rx/u_dsi_csi2/rWcCnt_10_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 1 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
3.208 3.208 tNET RR 1 R56C71[0][A] u_csi_rx/u_dsi_csi2/rWcCnt_10_s0/CLK
3.210 0.001 tHld 1 R56C71[0][A] u_csi_rx/u_dsi_csi2/rWcCnt_10_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.208, 100.000%
Arrival Data Path Delay cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.208, 100.000%

Path19

Path Summary:

Slack 0.374
Data Arrival Time 3.586
Data Required Time 3.213
From hsrx_cnt_1_s1
To hsrx_cnt_1_s1
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 625 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
3.211 3.211 tNET RR 1 R57C54[0][A] hsrx_cnt_1_s1/CLK
3.388 0.176 tC2Q RF 4 R57C54[0][A] hsrx_cnt_1_s1/Q
3.395 0.008 tNET FF 1 R57C54[0][A] n233_s1/I1
3.586 0.191 tINS FF 1 R57C54[0][A] n233_s1/F
3.586 0.000 tNET FF 1 R57C54[0][A] hsrx_cnt_1_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 1 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
3.211 3.211 tNET RR 1 R57C54[0][A] hsrx_cnt_1_s1/CLK
3.213 0.001 tHld 1 R57C54[0][A] hsrx_cnt_1_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.211, 100.000%
Arrival Data Path Delay cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.211, 100.000%

Path20

Path Summary:

Slack 0.374
Data Arrival Time 3.586
Data Required Time 3.213
From hsrx_cnt_3_s1
To hsrx_cnt_3_s1
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 625 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
3.211 3.211 tNET RR 1 R57C54[1][A] hsrx_cnt_3_s1/CLK
3.388 0.176 tC2Q RF 2 R57C54[1][A] hsrx_cnt_3_s1/Q
3.395 0.008 tNET FF 1 R57C54[1][A] n231_s1/I1
3.586 0.191 tINS FF 1 R57C54[1][A] n231_s1/F
3.586 0.000 tNET FF 1 R57C54[1][A] hsrx_cnt_3_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 1 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
3.211 3.211 tNET RR 1 R57C54[1][A] hsrx_cnt_3_s1/CLK
3.213 0.001 tHld 1 R57C54[1][A] hsrx_cnt_3_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.211, 100.000%
Arrival Data Path Delay cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.211, 100.000%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 1.993
Data Arrival Time 12.660
Data Required Time 14.653
From u_la0_top/rst_ao_s0
To u_la0_top/triger_level_cnt_2_s1
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 byte_clk
7.500 0.000 tCL FF 625 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
7.500 0.000 tNET FF 1 R3C8[1][A] u_la0_top/rst_ao_s0/CLK
7.943 0.442 tC2Q FF 73 R3C8[1][A] u_la0_top/rst_ao_s0/Q
12.660 4.717 tNET FF 1 R6C2[2][A] u_la0_top/triger_level_cnt_2_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
15.000 0.000 tNET RR 1 R6C2[2][A] u_la0_top/triger_level_cnt_2_s1/CLK
14.653 -0.347 tSu 1 R6C2[2][A] u_la0_top/triger_level_cnt_2_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 7.500
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 4.717, 91.424%; tC2Q: 0.442, 8.576%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path2

Path Summary:

Slack 2.029
Data Arrival Time 12.623
Data Required Time 14.653
From u_la0_top/rst_ao_s0
To u_la0_top/u_ao_mem_ctrl/capture_length_5_s1
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 byte_clk
7.500 0.000 tCL FF 625 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
7.500 0.000 tNET FF 1 R3C8[1][A] u_la0_top/rst_ao_s0/CLK
7.943 0.442 tC2Q FF 73 R3C8[1][A] u_la0_top/rst_ao_s0/Q
12.623 4.681 tNET FF 1 R8C6[1][A] u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
15.000 0.000 tNET RR 1 R8C6[1][A] u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLK
14.653 -0.347 tSu 1 R8C6[1][A] u_la0_top/u_ao_mem_ctrl/capture_length_5_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 7.500
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 4.681, 91.363%; tC2Q: 0.442, 8.637%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path3

Path Summary:

Slack 2.029
Data Arrival Time 12.623
Data Required Time 14.653
From u_la0_top/rst_ao_s0
To u_la0_top/u_ao_mem_ctrl/capture_length_6_s1
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 byte_clk
7.500 0.000 tCL FF 625 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
7.500 0.000 tNET FF 1 R3C8[1][A] u_la0_top/rst_ao_s0/CLK
7.943 0.442 tC2Q FF 73 R3C8[1][A] u_la0_top/rst_ao_s0/Q
12.623 4.681 tNET FF 1 R8C6[1][B] u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
15.000 0.000 tNET RR 1 R8C6[1][B] u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLK
14.653 -0.347 tSu 1 R8C6[1][B] u_la0_top/u_ao_mem_ctrl/capture_length_6_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 7.500
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 4.681, 91.363%; tC2Q: 0.442, 8.637%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path4

Path Summary:

Slack 2.029
Data Arrival Time 12.623
Data Required Time 14.653
From u_la0_top/rst_ao_s0
To u_la0_top/u_ao_mem_ctrl/capture_length_7_s1
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 byte_clk
7.500 0.000 tCL FF 625 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
7.500 0.000 tNET FF 1 R3C8[1][A] u_la0_top/rst_ao_s0/CLK
7.943 0.442 tC2Q FF 73 R3C8[1][A] u_la0_top/rst_ao_s0/Q
12.623 4.681 tNET FF 1 R8C6[2][A] u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
15.000 0.000 tNET RR 1 R8C6[2][A] u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLK
14.653 -0.347 tSu 1 R8C6[2][A] u_la0_top/u_ao_mem_ctrl/capture_length_7_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 7.500
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 4.681, 91.363%; tC2Q: 0.442, 8.637%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path5

Path Summary:

Slack 2.065
Data Arrival Time 12.588
Data Required Time 14.653
From u_la0_top/rst_ao_s0
To u_la0_top/u_ao_match_2/trig_dly_in_5_s0
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 byte_clk
7.500 0.000 tCL FF 625 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
7.500 0.000 tNET FF 1 R3C8[1][A] u_la0_top/rst_ao_s0/CLK
7.943 0.442 tC2Q FF 73 R3C8[1][A] u_la0_top/rst_ao_s0/Q
12.588 4.645 tNET FF 1 R5C9[1][A] u_la0_top/u_ao_match_2/trig_dly_in_5_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
15.000 0.000 tNET RR 1 R5C9[1][A] u_la0_top/u_ao_match_2/trig_dly_in_5_s0/CLK
14.653 -0.347 tSu 1 R5C9[1][A] u_la0_top/u_ao_match_2/trig_dly_in_5_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 7.500
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 4.645, 91.303%; tC2Q: 0.442, 8.697%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path6

Path Summary:

Slack 2.065
Data Arrival Time 12.588
Data Required Time 14.653
From u_la0_top/rst_ao_s0
To u_la0_top/u_ao_match_1/trig_dly_in_0_s0
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 byte_clk
7.500 0.000 tCL FF 625 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
7.500 0.000 tNET FF 1 R3C8[1][A] u_la0_top/rst_ao_s0/CLK
7.943 0.442 tC2Q FF 73 R3C8[1][A] u_la0_top/rst_ao_s0/Q
12.588 4.645 tNET FF 1 R5C9[0][A] u_la0_top/u_ao_match_1/trig_dly_in_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
15.000 0.000 tNET RR 1 R5C9[0][A] u_la0_top/u_ao_match_1/trig_dly_in_0_s0/CLK
14.653 -0.347 tSu 1 R5C9[0][A] u_la0_top/u_ao_match_1/trig_dly_in_0_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 7.500
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 4.645, 91.303%; tC2Q: 0.442, 8.697%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path7

Path Summary:

Slack 2.065
Data Arrival Time 12.588
Data Required Time 14.653
From u_la0_top/rst_ao_s0
To u_la0_top/u_ao_match_0/trig_dly_0_s0
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 byte_clk
7.500 0.000 tCL FF 625 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
7.500 0.000 tNET FF 1 R3C8[1][A] u_la0_top/rst_ao_s0/CLK
7.943 0.442 tC2Q FF 73 R3C8[1][A] u_la0_top/rst_ao_s0/Q
12.588 4.645 tNET FF 1 R5C9[0][B] u_la0_top/u_ao_match_0/trig_dly_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
15.000 0.000 tNET RR 1 R5C9[0][B] u_la0_top/u_ao_match_0/trig_dly_0_s0/CLK
14.653 -0.347 tSu 1 R5C9[0][B] u_la0_top/u_ao_match_0/trig_dly_0_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 7.500
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 4.645, 91.303%; tC2Q: 0.442, 8.697%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path8

Path Summary:

Slack 2.065
Data Arrival Time 12.588
Data Required Time 14.653
From u_la0_top/rst_ao_s0
To u_la0_top/u_ao_mem_ctrl/capture_length_9_s1
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 byte_clk
7.500 0.000 tCL FF 625 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
7.500 0.000 tNET FF 1 R3C8[1][A] u_la0_top/rst_ao_s0/CLK
7.943 0.442 tC2Q FF 73 R3C8[1][A] u_la0_top/rst_ao_s0/Q
12.588 4.645 tNET FF 1 R5C9[2][A] u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
15.000 0.000 tNET RR 1 R5C9[2][A] u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLK
14.653 -0.347 tSu 1 R5C9[2][A] u_la0_top/u_ao_mem_ctrl/capture_length_9_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 7.500
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 4.645, 91.303%; tC2Q: 0.442, 8.697%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path9

Path Summary:

Slack 2.065
Data Arrival Time 12.588
Data Required Time 14.653
From u_la0_top/rst_ao_s0
To u_la0_top/u_ao_mem_ctrl/capture_length_10_s1
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 byte_clk
7.500 0.000 tCL FF 625 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
7.500 0.000 tNET FF 1 R3C8[1][A] u_la0_top/rst_ao_s0/CLK
7.943 0.442 tC2Q FF 73 R3C8[1][A] u_la0_top/rst_ao_s0/Q
12.588 4.645 tNET FF 1 R5C9[2][B] u_la0_top/u_ao_mem_ctrl/capture_length_10_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
15.000 0.000 tNET RR 1 R5C9[2][B] u_la0_top/u_ao_mem_ctrl/capture_length_10_s1/CLK
14.653 -0.347 tSu 1 R5C9[2][B] u_la0_top/u_ao_mem_ctrl/capture_length_10_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 7.500
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 4.645, 91.303%; tC2Q: 0.442, 8.697%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path10

Path Summary:

Slack 2.087
Data Arrival Time 12.565
Data Required Time 14.653
From u_la0_top/rst_ao_s0
To u_la0_top/capture_window_sel_10_s1
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 byte_clk
7.500 0.000 tCL FF 625 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
7.500 0.000 tNET FF 1 R3C8[1][A] u_la0_top/rst_ao_s0/CLK
7.943 0.442 tC2Q FF 73 R3C8[1][A] u_la0_top/rst_ao_s0/Q
12.565 4.623 tNET FF 1 R3C8[0][A] u_la0_top/capture_window_sel_10_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
15.000 0.000 tNET RR 1 R3C8[0][A] u_la0_top/capture_window_sel_10_s1/CLK
14.653 -0.347 tSu 1 R3C8[0][A] u_la0_top/capture_window_sel_10_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 7.500
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 4.623, 91.264%; tC2Q: 0.442, 8.736%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path11

Path Summary:

Slack 2.087
Data Arrival Time 12.565
Data Required Time 14.653
From u_la0_top/rst_ao_s0
To u_la0_top/internal_reg_start_dly_1_s0
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 byte_clk
7.500 0.000 tCL FF 625 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
7.500 0.000 tNET FF 1 R3C8[1][A] u_la0_top/rst_ao_s0/CLK
7.943 0.442 tC2Q FF 73 R3C8[1][A] u_la0_top/rst_ao_s0/Q
12.565 4.623 tNET FF 1 R3C9[1][A] u_la0_top/internal_reg_start_dly_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
15.000 0.000 tNET RR 1 R3C9[1][A] u_la0_top/internal_reg_start_dly_1_s0/CLK
14.653 -0.347 tSu 1 R3C9[1][A] u_la0_top/internal_reg_start_dly_1_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 7.500
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 4.623, 91.264%; tC2Q: 0.442, 8.736%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path12

Path Summary:

Slack 2.087
Data Arrival Time 12.565
Data Required Time 14.653
From u_la0_top/rst_ao_s0
To u_la0_top/internal_reg_force_triger_syn_0_s0
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 byte_clk
7.500 0.000 tCL FF 625 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
7.500 0.000 tNET FF 1 R3C8[1][A] u_la0_top/rst_ao_s0/CLK
7.943 0.442 tC2Q FF 73 R3C8[1][A] u_la0_top/rst_ao_s0/Q
12.565 4.623 tNET FF 1 R3C9[1][B] u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
15.000 0.000 tNET RR 1 R3C9[1][B] u_la0_top/internal_reg_force_triger_syn_0_s0/CLK
14.653 -0.347 tSu 1 R3C9[1][B] u_la0_top/internal_reg_force_triger_syn_0_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 7.500
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 4.623, 91.264%; tC2Q: 0.442, 8.736%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path13

Path Summary:

Slack 2.090
Data Arrival Time 12.563
Data Required Time 14.653
From u_la0_top/rst_ao_s0
To u_la0_top/capture_window_sel_5_s1
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 byte_clk
7.500 0.000 tCL FF 625 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
7.500 0.000 tNET FF 1 R3C8[1][A] u_la0_top/rst_ao_s0/CLK
7.943 0.442 tC2Q FF 73 R3C8[1][A] u_la0_top/rst_ao_s0/Q
12.563 4.620 tNET FF 1 R4C3[3][A] u_la0_top/capture_window_sel_5_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
15.000 0.000 tNET RR 1 R4C3[3][A] u_la0_top/capture_window_sel_5_s1/CLK
14.653 -0.347 tSu 1 R4C3[3][A] u_la0_top/capture_window_sel_5_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 7.500
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 4.620, 91.259%; tC2Q: 0.442, 8.741%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path14

Path Summary:

Slack 2.090
Data Arrival Time 12.563
Data Required Time 14.653
From u_la0_top/rst_ao_s0
To u_la0_top/capture_window_sel_6_s1
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 byte_clk
7.500 0.000 tCL FF 625 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
7.500 0.000 tNET FF 1 R3C8[1][A] u_la0_top/rst_ao_s0/CLK
7.943 0.442 tC2Q FF 73 R3C8[1][A] u_la0_top/rst_ao_s0/Q
12.563 4.620 tNET FF 1 R4C3[2][B] u_la0_top/capture_window_sel_6_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
15.000 0.000 tNET RR 1 R4C3[2][B] u_la0_top/capture_window_sel_6_s1/CLK
14.653 -0.347 tSu 1 R4C3[2][B] u_la0_top/capture_window_sel_6_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 7.500
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 4.620, 91.259%; tC2Q: 0.442, 8.741%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path15

Path Summary:

Slack 2.090
Data Arrival Time 12.563
Data Required Time 14.653
From u_la0_top/rst_ao_s0
To u_la0_top/capture_window_sel_7_s1
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 byte_clk
7.500 0.000 tCL FF 625 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
7.500 0.000 tNET FF 1 R3C8[1][A] u_la0_top/rst_ao_s0/CLK
7.943 0.442 tC2Q FF 73 R3C8[1][A] u_la0_top/rst_ao_s0/Q
12.563 4.620 tNET FF 1 R4C3[2][A] u_la0_top/capture_window_sel_7_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
15.000 0.000 tNET RR 1 R4C3[2][A] u_la0_top/capture_window_sel_7_s1/CLK
14.653 -0.347 tSu 1 R4C3[2][A] u_la0_top/capture_window_sel_7_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 7.500
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 4.620, 91.259%; tC2Q: 0.442, 8.741%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path16

Path Summary:

Slack 2.090
Data Arrival Time 12.563
Data Required Time 14.653
From u_la0_top/rst_ao_s0
To u_la0_top/capture_window_sel_8_s1
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 byte_clk
7.500 0.000 tCL FF 625 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
7.500 0.000 tNET FF 1 R3C8[1][A] u_la0_top/rst_ao_s0/CLK
7.943 0.442 tC2Q FF 73 R3C8[1][A] u_la0_top/rst_ao_s0/Q
12.563 4.620 tNET FF 1 R4C3[0][B] u_la0_top/capture_window_sel_8_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
15.000 0.000 tNET RR 1 R4C3[0][B] u_la0_top/capture_window_sel_8_s1/CLK
14.653 -0.347 tSu 1 R4C3[0][B] u_la0_top/capture_window_sel_8_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 7.500
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 4.620, 91.259%; tC2Q: 0.442, 8.741%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path17

Path Summary:

Slack 2.090
Data Arrival Time 12.563
Data Required Time 14.653
From u_la0_top/rst_ao_s0
To u_la0_top/capture_window_sel_9_s1
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 byte_clk
7.500 0.000 tCL FF 625 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
7.500 0.000 tNET FF 1 R3C8[1][A] u_la0_top/rst_ao_s0/CLK
7.943 0.442 tC2Q FF 73 R3C8[1][A] u_la0_top/rst_ao_s0/Q
12.563 4.620 tNET FF 1 R4C3[0][A] u_la0_top/capture_window_sel_9_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
15.000 0.000 tNET RR 1 R4C3[0][A] u_la0_top/capture_window_sel_9_s1/CLK
14.653 -0.347 tSu 1 R4C3[0][A] u_la0_top/capture_window_sel_9_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 7.500
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 4.620, 91.259%; tC2Q: 0.442, 8.741%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path18

Path Summary:

Slack 2.090
Data Arrival Time 12.563
Data Required Time 14.653
From u_la0_top/rst_ao_s0
To u_la0_top/triger_level_cnt_3_s1
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 byte_clk
7.500 0.000 tCL FF 625 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
7.500 0.000 tNET FF 1 R3C8[1][A] u_la0_top/rst_ao_s0/CLK
7.943 0.442 tC2Q FF 73 R3C8[1][A] u_la0_top/rst_ao_s0/Q
12.563 4.620 tNET FF 1 R4C3[1][A] u_la0_top/triger_level_cnt_3_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
15.000 0.000 tNET RR 1 R4C3[1][A] u_la0_top/triger_level_cnt_3_s1/CLK
14.653 -0.347 tSu 1 R4C3[1][A] u_la0_top/triger_level_cnt_3_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 7.500
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 4.620, 91.259%; tC2Q: 0.442, 8.741%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path19

Path Summary:

Slack 2.092
Data Arrival Time 12.561
Data Required Time 14.653
From u_la0_top/rst_ao_s0
To u_la0_top/u_ao_mem_ctrl/capture_loop_s1
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 byte_clk
7.500 0.000 tCL FF 625 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
7.500 0.000 tNET FF 1 R3C8[1][A] u_la0_top/rst_ao_s0/CLK
7.943 0.442 tC2Q FF 73 R3C8[1][A] u_la0_top/rst_ao_s0/Q
12.561 4.618 tNET FF 1 R5C11[0][A] u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
15.000 0.000 tNET RR 1 R5C11[0][A] u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK
14.653 -0.347 tSu 1 R5C11[0][A] u_la0_top/u_ao_mem_ctrl/capture_loop_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 7.500
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 4.618, 91.257%; tC2Q: 0.442, 8.743%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path20

Path Summary:

Slack 2.092
Data Arrival Time 12.560
Data Required Time 14.653
From u_la0_top/rst_ao_s0
To u_la0_top/triger_level_cnt_0_s1
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 byte_clk
7.500 0.000 tCL FF 625 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
7.500 0.000 tNET FF 1 R3C8[1][A] u_la0_top/rst_ao_s0/CLK
7.943 0.442 tC2Q FF 73 R3C8[1][A] u_la0_top/rst_ao_s0/Q
12.560 4.618 tNET FF 1 R3C3[3][B] u_la0_top/triger_level_cnt_0_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
15.000 0.000 tNET RR 1 R3C3[3][B] u_la0_top/triger_level_cnt_0_s1/CLK
14.653 -0.347 tSu 1 R3C3[3][B] u_la0_top/triger_level_cnt_0_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 7.500
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 4.618, 91.255%; tC2Q: 0.442, 8.745%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path21

Path Summary:

Slack 2.092
Data Arrival Time 12.560
Data Required Time 14.653
From u_la0_top/rst_ao_s0
To u_la0_top/triger_level_cnt_1_s1
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 byte_clk
7.500 0.000 tCL FF 625 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
7.500 0.000 tNET FF 1 R3C8[1][A] u_la0_top/rst_ao_s0/CLK
7.943 0.442 tC2Q FF 73 R3C8[1][A] u_la0_top/rst_ao_s0/Q
12.560 4.618 tNET FF 1 R3C3[3][A] u_la0_top/triger_level_cnt_1_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
15.000 0.000 tNET RR 1 R3C3[3][A] u_la0_top/triger_level_cnt_1_s1/CLK
14.653 -0.347 tSu 1 R3C3[3][A] u_la0_top/triger_level_cnt_1_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 7.500
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 4.618, 91.255%; tC2Q: 0.442, 8.745%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path22

Path Summary:

Slack 2.099
Data Arrival Time 12.554
Data Required Time 14.653
From u_la0_top/rst_ao_s0
To u_la0_top/u_ao_match_2/match_bitwise_pre_reg_5_s0
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 byte_clk
7.500 0.000 tCL FF 625 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
7.500 0.000 tNET FF 1 R3C8[1][A] u_la0_top/rst_ao_s0/CLK
7.943 0.442 tC2Q FF 73 R3C8[1][A] u_la0_top/rst_ao_s0/Q
12.554 4.611 tNET FF 1 R2C13[0][A] u_la0_top/u_ao_match_2/match_bitwise_pre_reg_5_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
15.000 0.000 tNET RR 1 R2C13[0][A] u_la0_top/u_ao_match_2/match_bitwise_pre_reg_5_s0/CLK
14.653 -0.347 tSu 1 R2C13[0][A] u_la0_top/u_ao_match_2/match_bitwise_pre_reg_5_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 7.500
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 4.611, 91.244%; tC2Q: 0.442, 8.756%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path23

Path Summary:

Slack 2.099
Data Arrival Time 12.554
Data Required Time 14.653
From u_la0_top/rst_ao_s0
To u_la0_top/u_ao_match_2/trig_dly_in_0_s0
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 byte_clk
7.500 0.000 tCL FF 625 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
7.500 0.000 tNET FF 1 R3C8[1][A] u_la0_top/rst_ao_s0/CLK
7.943 0.442 tC2Q FF 73 R3C8[1][A] u_la0_top/rst_ao_s0/Q
12.554 4.611 tNET FF 1 R2C13[0][B] u_la0_top/u_ao_match_2/trig_dly_in_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
15.000 0.000 tNET RR 1 R2C13[0][B] u_la0_top/u_ao_match_2/trig_dly_in_0_s0/CLK
14.653 -0.347 tSu 1 R2C13[0][B] u_la0_top/u_ao_match_2/trig_dly_in_0_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 7.500
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 4.611, 91.244%; tC2Q: 0.442, 8.756%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path24

Path Summary:

Slack 2.099
Data Arrival Time 12.554
Data Required Time 14.653
From u_la0_top/rst_ao_s0
To u_la0_top/u_ao_match_2/trig_dly_in_1_s0
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 byte_clk
7.500 0.000 tCL FF 625 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
7.500 0.000 tNET FF 1 R3C8[1][A] u_la0_top/rst_ao_s0/CLK
7.943 0.442 tC2Q FF 73 R3C8[1][A] u_la0_top/rst_ao_s0/Q
12.554 4.611 tNET FF 1 R2C13[1][A] u_la0_top/u_ao_match_2/trig_dly_in_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
15.000 0.000 tNET RR 1 R2C13[1][A] u_la0_top/u_ao_match_2/trig_dly_in_1_s0/CLK
14.653 -0.347 tSu 1 R2C13[1][A] u_la0_top/u_ao_match_2/trig_dly_in_1_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 7.500
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 4.611, 91.244%; tC2Q: 0.442, 8.756%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path25

Path Summary:

Slack 2.099
Data Arrival Time 12.554
Data Required Time 14.653
From u_la0_top/rst_ao_s0
To u_la0_top/u_ao_match_2/trig_dly_in_2_s0
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 byte_clk
7.500 0.000 tCL FF 625 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
7.500 0.000 tNET FF 1 R3C8[1][A] u_la0_top/rst_ao_s0/CLK
7.943 0.442 tC2Q FF 73 R3C8[1][A] u_la0_top/rst_ao_s0/Q
12.554 4.611 tNET FF 1 R2C13[1][B] u_la0_top/u_ao_match_2/trig_dly_in_2_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 byte_clk
15.000 0.000 tCL RR 1 QUAD[0] u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O
15.000 0.000 tNET RR 1 R2C13[1][B] u_la0_top/u_ao_match_2/trig_dly_in_2_s0/CLK
14.653 -0.347 tSu 1 R2C13[1][B] u_la0_top/u_ao_match_2/trig_dly_in_2_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 7.500
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 4.611, 91.244%; tC2Q: 0.442, 8.756%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 0.611
Data Arrival Time 1.736
Data Required Time 1.125
From u_ov5647_ctrl/resend_s0
To u_ov5647_ctrl/I2C/data_sr_40_s1
Launch Clk clk_50:[R]
Latch Clk clk_50:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 218 LEFTSIDE[0] uut_div4/CLKOUT
1.303 1.303 tNET RR 1 R56C98[1][A] u_ov5647_ctrl/resend_s0/CLK
1.483 0.180 tC2Q RR 103 R56C98[1][A] u_ov5647_ctrl/resend_s0/Q
1.736 0.252 tNET RR 1 R56C100[3][B] u_ov5647_ctrl/I2C/data_sr_40_s1/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 218 LEFTSIDE[0] uut_div4/CLKOUT
1.313 1.313 tNET RR 1 R56C100[3][B] u_ov5647_ctrl/I2C/data_sr_40_s1/CLK
1.125 -0.189 tHld 1 R56C100[3][B] u_ov5647_ctrl/I2C/data_sr_40_s1

Path Statistics:

Clock Skew 0.010
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.303, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.252, 58.382%; tC2Q: 0.180, 41.618%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.313, 100.000%

Path2

Path Summary:

Slack 0.611
Data Arrival Time 1.736
Data Required Time 1.125
From u_ov5647_ctrl/resend_s0
To u_ov5647_ctrl/I2C/data_sr_0_s1
Launch Clk clk_50:[R]
Latch Clk clk_50:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 218 LEFTSIDE[0] uut_div4/CLKOUT
1.303 1.303 tNET RR 1 R56C98[1][A] u_ov5647_ctrl/resend_s0/CLK
1.483 0.180 tC2Q RR 103 R56C98[1][A] u_ov5647_ctrl/resend_s0/Q
1.736 0.252 tNET RR 1 R56C100[2][B] u_ov5647_ctrl/I2C/data_sr_0_s1/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 218 LEFTSIDE[0] uut_div4/CLKOUT
1.313 1.313 tNET RR 1 R56C100[2][B] u_ov5647_ctrl/I2C/data_sr_0_s1/CLK
1.125 -0.189 tHld 1 R56C100[2][B] u_ov5647_ctrl/I2C/data_sr_0_s1

Path Statistics:

Clock Skew 0.010
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.303, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.252, 58.382%; tC2Q: 0.180, 41.618%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.313, 100.000%

Path3

Path Summary:

Slack 0.611
Data Arrival Time 1.736
Data Required Time 1.125
From u_ov5647_ctrl/resend_s0
To u_ov5647_ctrl/I2C/data_sr_1_s1
Launch Clk clk_50:[R]
Latch Clk clk_50:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 218 LEFTSIDE[0] uut_div4/CLKOUT
1.303 1.303 tNET RR 1 R56C98[1][A] u_ov5647_ctrl/resend_s0/CLK
1.483 0.180 tC2Q RR 103 R56C98[1][A] u_ov5647_ctrl/resend_s0/Q
1.736 0.252 tNET RR 1 R56C100[3][A] u_ov5647_ctrl/I2C/data_sr_1_s1/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 218 LEFTSIDE[0] uut_div4/CLKOUT
1.313 1.313 tNET RR 1 R56C100[3][A] u_ov5647_ctrl/I2C/data_sr_1_s1/CLK
1.125 -0.189 tHld 1 R56C100[3][A] u_ov5647_ctrl/I2C/data_sr_1_s1

Path Statistics:

Clock Skew 0.010
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.303, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.252, 58.382%; tC2Q: 0.180, 41.618%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.313, 100.000%

Path4

Path Summary:

Slack 0.611
Data Arrival Time 1.736
Data Required Time 1.125
From u_ov5647_ctrl/resend_s0
To u_ov5647_ctrl/I2C/data_sr_2_s1
Launch Clk clk_50:[R]
Latch Clk clk_50:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 218 LEFTSIDE[0] uut_div4/CLKOUT
1.303 1.303 tNET RR 1 R56C98[1][A] u_ov5647_ctrl/resend_s0/CLK
1.483 0.180 tC2Q RR 103 R56C98[1][A] u_ov5647_ctrl/resend_s0/Q
1.736 0.252 tNET RR 1 R56C100[2][A] u_ov5647_ctrl/I2C/data_sr_2_s1/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 218 LEFTSIDE[0] uut_div4/CLKOUT
1.313 1.313 tNET RR 1 R56C100[2][A] u_ov5647_ctrl/I2C/data_sr_2_s1/CLK
1.125 -0.189 tHld 1 R56C100[2][A] u_ov5647_ctrl/I2C/data_sr_2_s1

Path Statistics:

Clock Skew 0.010
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.303, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.252, 58.382%; tC2Q: 0.180, 41.618%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.313, 100.000%

Path5

Path Summary:

Slack 0.611
Data Arrival Time 1.736
Data Required Time 1.125
From u_ov5647_ctrl/resend_s0
To u_ov5647_ctrl/I2C/data_sr_31_s1
Launch Clk clk_50:[R]
Latch Clk clk_50:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 218 LEFTSIDE[0] uut_div4/CLKOUT
1.303 1.303 tNET RR 1 R56C98[1][A] u_ov5647_ctrl/resend_s0/CLK
1.483 0.180 tC2Q RR 103 R56C98[1][A] u_ov5647_ctrl/resend_s0/Q
1.736 0.252 tNET RR 1 R56C100[1][B] u_ov5647_ctrl/I2C/data_sr_31_s1/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 218 LEFTSIDE[0] uut_div4/CLKOUT
1.313 1.313 tNET RR 1 R56C100[1][B] u_ov5647_ctrl/I2C/data_sr_31_s1/CLK
1.125 -0.189 tHld 1 R56C100[1][B] u_ov5647_ctrl/I2C/data_sr_31_s1

Path Statistics:

Clock Skew 0.010
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.303, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.252, 58.382%; tC2Q: 0.180, 41.618%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.313, 100.000%

Path6

Path Summary:

Slack 0.611
Data Arrival Time 1.736
Data Required Time 1.125
From u_ov5647_ctrl/resend_s0
To u_ov5647_ctrl/I2C/data_sr_32_s1
Launch Clk clk_50:[R]
Latch Clk clk_50:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 218 LEFTSIDE[0] uut_div4/CLKOUT
1.303 1.303 tNET RR 1 R56C98[1][A] u_ov5647_ctrl/resend_s0/CLK
1.483 0.180 tC2Q RR 103 R56C98[1][A] u_ov5647_ctrl/resend_s0/Q
1.736 0.252 tNET RR 1 R56C100[0][A] u_ov5647_ctrl/I2C/data_sr_32_s1/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 218 LEFTSIDE[0] uut_div4/CLKOUT
1.313 1.313 tNET RR 1 R56C100[0][A] u_ov5647_ctrl/I2C/data_sr_32_s1/CLK
1.125 -0.189 tHld 1 R56C100[0][A] u_ov5647_ctrl/I2C/data_sr_32_s1

Path Statistics:

Clock Skew 0.010
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.303, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.252, 58.382%; tC2Q: 0.180, 41.618%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.313, 100.000%

Path7

Path Summary:

Slack 0.611
Data Arrival Time 1.736
Data Required Time 1.125
From u_ov5647_ctrl/resend_s0
To u_ov5647_ctrl/I2C/data_sr_33_s1
Launch Clk clk_50:[R]
Latch Clk clk_50:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 218 LEFTSIDE[0] uut_div4/CLKOUT
1.303 1.303 tNET RR 1 R56C98[1][A] u_ov5647_ctrl/resend_s0/CLK
1.483 0.180 tC2Q RR 103 R56C98[1][A] u_ov5647_ctrl/resend_s0/Q
1.736 0.252 tNET RR 1 R56C100[0][B] u_ov5647_ctrl/I2C/data_sr_33_s1/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 218 LEFTSIDE[0] uut_div4/CLKOUT
1.313 1.313 tNET RR 1 R56C100[0][B] u_ov5647_ctrl/I2C/data_sr_33_s1/CLK
1.125 -0.189 tHld 1 R56C100[0][B] u_ov5647_ctrl/I2C/data_sr_33_s1

Path Statistics:

Clock Skew 0.010
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.303, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.252, 58.382%; tC2Q: 0.180, 41.618%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.313, 100.000%

Path8

Path Summary:

Slack 0.611
Data Arrival Time 1.736
Data Required Time 1.125
From u_ov5647_ctrl/resend_s0
To u_ov5647_ctrl/I2C/data_sr_34_s1
Launch Clk clk_50:[R]
Latch Clk clk_50:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 218 LEFTSIDE[0] uut_div4/CLKOUT
1.303 1.303 tNET RR 1 R56C98[1][A] u_ov5647_ctrl/resend_s0/CLK
1.483 0.180 tC2Q RR 103 R56C98[1][A] u_ov5647_ctrl/resend_s0/Q
1.736 0.252 tNET RR 1 R56C100[1][A] u_ov5647_ctrl/I2C/data_sr_34_s1/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 218 LEFTSIDE[0] uut_div4/CLKOUT
1.313 1.313 tNET RR 1 R56C100[1][A] u_ov5647_ctrl/I2C/data_sr_34_s1/CLK
1.125 -0.189 tHld 1 R56C100[1][A] u_ov5647_ctrl/I2C/data_sr_34_s1

Path Statistics:

Clock Skew 0.010
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.303, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.252, 58.382%; tC2Q: 0.180, 41.618%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.313, 100.000%

Path9

Path Summary:

Slack 0.616
Data Arrival Time 1.736
Data Required Time 1.120
From u_ov5647_ctrl/resend_s0
To u_ov5647_ctrl/I2C/data_sr_35_s1
Launch Clk clk_50:[R]
Latch Clk clk_50:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 218 LEFTSIDE[0] uut_div4/CLKOUT
1.303 1.303 tNET RR 1 R56C98[1][A] u_ov5647_ctrl/resend_s0/CLK
1.483 0.180 tC2Q RR 103 R56C98[1][A] u_ov5647_ctrl/resend_s0/Q
1.736 0.252 tNET RR 1 R56C99[0][B] u_ov5647_ctrl/I2C/data_sr_35_s1/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 218 LEFTSIDE[0] uut_div4/CLKOUT
1.308 1.308 tNET RR 1 R56C99[0][B] u_ov5647_ctrl/I2C/data_sr_35_s1/CLK
1.120 -0.189 tHld 1 R56C99[0][B] u_ov5647_ctrl/I2C/data_sr_35_s1

Path Statistics:

Clock Skew 0.005
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.303, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.252, 58.382%; tC2Q: 0.180, 41.618%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.308, 100.000%

Path10

Path Summary:

Slack 0.616
Data Arrival Time 1.736
Data Required Time 1.120
From u_ov5647_ctrl/resend_s0
To u_ov5647_ctrl/I2C/data_sr_36_s1
Launch Clk clk_50:[R]
Latch Clk clk_50:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 218 LEFTSIDE[0] uut_div4/CLKOUT
1.303 1.303 tNET RR 1 R56C98[1][A] u_ov5647_ctrl/resend_s0/CLK
1.483 0.180 tC2Q RR 103 R56C98[1][A] u_ov5647_ctrl/resend_s0/Q
1.736 0.252 tNET RR 1 R56C99[0][A] u_ov5647_ctrl/I2C/data_sr_36_s1/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 218 LEFTSIDE[0] uut_div4/CLKOUT
1.308 1.308 tNET RR 1 R56C99[0][A] u_ov5647_ctrl/I2C/data_sr_36_s1/CLK
1.120 -0.189 tHld 1 R56C99[0][A] u_ov5647_ctrl/I2C/data_sr_36_s1

Path Statistics:

Clock Skew 0.005
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.303, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.252, 58.382%; tC2Q: 0.180, 41.618%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.308, 100.000%

Path11

Path Summary:

Slack 0.616
Data Arrival Time 1.736
Data Required Time 1.120
From u_ov5647_ctrl/resend_s0
To u_ov5647_ctrl/I2C/data_sr_37_s1
Launch Clk clk_50:[R]
Latch Clk clk_50:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 218 LEFTSIDE[0] uut_div4/CLKOUT
1.303 1.303 tNET RR 1 R56C98[1][A] u_ov5647_ctrl/resend_s0/CLK
1.483 0.180 tC2Q RR 103 R56C98[1][A] u_ov5647_ctrl/resend_s0/Q
1.736 0.252 tNET RR 1 R56C99[1][B] u_ov5647_ctrl/I2C/data_sr_37_s1/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 218 LEFTSIDE[0] uut_div4/CLKOUT
1.308 1.308 tNET RR 1 R56C99[1][B] u_ov5647_ctrl/I2C/data_sr_37_s1/CLK
1.120 -0.189 tHld 1 R56C99[1][B] u_ov5647_ctrl/I2C/data_sr_37_s1

Path Statistics:

Clock Skew 0.005
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.303, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.252, 58.382%; tC2Q: 0.180, 41.618%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.308, 100.000%

Path12

Path Summary:

Slack 0.616
Data Arrival Time 1.736
Data Required Time 1.120
From u_ov5647_ctrl/resend_s0
To u_ov5647_ctrl/I2C/data_sr_38_s1
Launch Clk clk_50:[R]
Latch Clk clk_50:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 218 LEFTSIDE[0] uut_div4/CLKOUT
1.303 1.303 tNET RR 1 R56C98[1][A] u_ov5647_ctrl/resend_s0/CLK
1.483 0.180 tC2Q RR 103 R56C98[1][A] u_ov5647_ctrl/resend_s0/Q
1.736 0.252 tNET RR 1 R56C99[2][A] u_ov5647_ctrl/I2C/data_sr_38_s1/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 218 LEFTSIDE[0] uut_div4/CLKOUT
1.308 1.308 tNET RR 1 R56C99[2][A] u_ov5647_ctrl/I2C/data_sr_38_s1/CLK
1.120 -0.189 tHld 1 R56C99[2][A] u_ov5647_ctrl/I2C/data_sr_38_s1

Path Statistics:

Clock Skew 0.005
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.303, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.252, 58.382%; tC2Q: 0.180, 41.618%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.308, 100.000%

Path13

Path Summary:

Slack 0.616
Data Arrival Time 1.736
Data Required Time 1.120
From u_ov5647_ctrl/resend_s0
To u_ov5647_ctrl/I2C/data_sr_39_s1
Launch Clk clk_50:[R]
Latch Clk clk_50:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 218 LEFTSIDE[0] uut_div4/CLKOUT
1.303 1.303 tNET RR 1 R56C98[1][A] u_ov5647_ctrl/resend_s0/CLK
1.483 0.180 tC2Q RR 103 R56C98[1][A] u_ov5647_ctrl/resend_s0/Q
1.736 0.252 tNET RR 1 R56C99[1][A] u_ov5647_ctrl/I2C/data_sr_39_s1/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 218 LEFTSIDE[0] uut_div4/CLKOUT
1.308 1.308 tNET RR 1 R56C99[1][A] u_ov5647_ctrl/I2C/data_sr_39_s1/CLK
1.120 -0.189 tHld 1 R56C99[1][A] u_ov5647_ctrl/I2C/data_sr_39_s1

Path Statistics:

Clock Skew 0.005
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.303, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.252, 58.382%; tC2Q: 0.180, 41.618%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.308, 100.000%

Path14

Path Summary:

Slack 0.618
Data Arrival Time 1.736
Data Required Time 1.117
From u_ov5647_ctrl/resend_s0
To u_ov5647_ctrl/I2C/busy_sr_14_s1
Launch Clk clk_50:[R]
Latch Clk clk_50:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 218 LEFTSIDE[0] uut_div4/CLKOUT
1.303 1.303 tNET RR 1 R56C98[1][A] u_ov5647_ctrl/resend_s0/CLK
1.483 0.180 tC2Q RR 103 R56C98[1][A] u_ov5647_ctrl/resend_s0/Q
1.736 0.252 tNET RR 1 R57C99[0][A] u_ov5647_ctrl/I2C/busy_sr_14_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 218 LEFTSIDE[0] uut_div4/CLKOUT
1.306 1.306 tNET RR 1 R57C99[0][A] u_ov5647_ctrl/I2C/busy_sr_14_s1/CLK
1.117 -0.189 tHld 1 R57C99[0][A] u_ov5647_ctrl/I2C/busy_sr_14_s1

Path Statistics:

Clock Skew 0.003
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.303, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.252, 58.382%; tC2Q: 0.180, 41.618%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.306, 100.000%

Path15

Path Summary:

Slack 0.618
Data Arrival Time 1.736
Data Required Time 1.117
From u_ov5647_ctrl/resend_s0
To u_ov5647_ctrl/I2C/busy_sr_15_s1
Launch Clk clk_50:[R]
Latch Clk clk_50:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 218 LEFTSIDE[0] uut_div4/CLKOUT
1.303 1.303 tNET RR 1 R56C98[1][A] u_ov5647_ctrl/resend_s0/CLK
1.483 0.180 tC2Q RR 103 R56C98[1][A] u_ov5647_ctrl/resend_s0/Q
1.736 0.252 tNET RR 1 R57C99[0][B] u_ov5647_ctrl/I2C/busy_sr_15_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 218 LEFTSIDE[0] uut_div4/CLKOUT
1.306 1.306 tNET RR 1 R57C99[0][B] u_ov5647_ctrl/I2C/busy_sr_15_s1/CLK
1.117 -0.189 tHld 1 R57C99[0][B] u_ov5647_ctrl/I2C/busy_sr_15_s1

Path Statistics:

Clock Skew 0.003
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.303, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.252, 58.382%; tC2Q: 0.180, 41.618%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.306, 100.000%

Path16

Path Summary:

Slack 0.618
Data Arrival Time 1.736
Data Required Time 1.117
From u_ov5647_ctrl/resend_s0
To u_ov5647_ctrl/I2C/busy_sr_16_s1
Launch Clk clk_50:[R]
Latch Clk clk_50:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 218 LEFTSIDE[0] uut_div4/CLKOUT
1.303 1.303 tNET RR 1 R56C98[1][A] u_ov5647_ctrl/resend_s0/CLK
1.483 0.180 tC2Q RR 103 R56C98[1][A] u_ov5647_ctrl/resend_s0/Q
1.736 0.252 tNET RR 1 R57C99[1][A] u_ov5647_ctrl/I2C/busy_sr_16_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 218 LEFTSIDE[0] uut_div4/CLKOUT
1.306 1.306 tNET RR 1 R57C99[1][A] u_ov5647_ctrl/I2C/busy_sr_16_s1/CLK
1.117 -0.189 tHld 1 R57C99[1][A] u_ov5647_ctrl/I2C/busy_sr_16_s1

Path Statistics:

Clock Skew 0.003
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.303, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.252, 58.382%; tC2Q: 0.180, 41.618%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.306, 100.000%

Path17

Path Summary:

Slack 0.618
Data Arrival Time 1.736
Data Required Time 1.117
From u_ov5647_ctrl/resend_s0
To u_ov5647_ctrl/I2C/busy_sr_17_s1
Launch Clk clk_50:[R]
Latch Clk clk_50:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 218 LEFTSIDE[0] uut_div4/CLKOUT
1.303 1.303 tNET RR 1 R56C98[1][A] u_ov5647_ctrl/resend_s0/CLK
1.483 0.180 tC2Q RR 103 R56C98[1][A] u_ov5647_ctrl/resend_s0/Q
1.736 0.252 tNET RR 1 R57C99[1][B] u_ov5647_ctrl/I2C/busy_sr_17_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 218 LEFTSIDE[0] uut_div4/CLKOUT
1.306 1.306 tNET RR 1 R57C99[1][B] u_ov5647_ctrl/I2C/busy_sr_17_s1/CLK
1.117 -0.189 tHld 1 R57C99[1][B] u_ov5647_ctrl/I2C/busy_sr_17_s1

Path Statistics:

Clock Skew 0.003
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.303, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.252, 58.382%; tC2Q: 0.180, 41.618%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.306, 100.000%

Path18

Path Summary:

Slack 0.618
Data Arrival Time 1.736
Data Required Time 1.117
From u_ov5647_ctrl/resend_s0
To u_ov5647_ctrl/I2C/busy_sr_18_s1
Launch Clk clk_50:[R]
Latch Clk clk_50:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 218 LEFTSIDE[0] uut_div4/CLKOUT
1.303 1.303 tNET RR 1 R56C98[1][A] u_ov5647_ctrl/resend_s0/CLK
1.483 0.180 tC2Q RR 103 R56C98[1][A] u_ov5647_ctrl/resend_s0/Q
1.736 0.252 tNET RR 1 R57C99[2][A] u_ov5647_ctrl/I2C/busy_sr_18_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 218 LEFTSIDE[0] uut_div4/CLKOUT
1.306 1.306 tNET RR 1 R57C99[2][A] u_ov5647_ctrl/I2C/busy_sr_18_s1/CLK
1.117 -0.189 tHld 1 R57C99[2][A] u_ov5647_ctrl/I2C/busy_sr_18_s1

Path Statistics:

Clock Skew 0.003
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.303, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.252, 58.382%; tC2Q: 0.180, 41.618%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.306, 100.000%

Path19

Path Summary:

Slack 0.618
Data Arrival Time 1.736
Data Required Time 1.117
From u_ov5647_ctrl/resend_s0
To u_ov5647_ctrl/I2C/busy_sr_19_s1
Launch Clk clk_50:[R]
Latch Clk clk_50:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 218 LEFTSIDE[0] uut_div4/CLKOUT
1.303 1.303 tNET RR 1 R56C98[1][A] u_ov5647_ctrl/resend_s0/CLK
1.483 0.180 tC2Q RR 103 R56C98[1][A] u_ov5647_ctrl/resend_s0/Q
1.736 0.252 tNET RR 1 R57C99[2][B] u_ov5647_ctrl/I2C/busy_sr_19_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 218 LEFTSIDE[0] uut_div4/CLKOUT
1.306 1.306 tNET RR 1 R57C99[2][B] u_ov5647_ctrl/I2C/busy_sr_19_s1/CLK
1.117 -0.189 tHld 1 R57C99[2][B] u_ov5647_ctrl/I2C/busy_sr_19_s1

Path Statistics:

Clock Skew 0.003
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.303, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.252, 58.382%; tC2Q: 0.180, 41.618%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.306, 100.000%

Path20

Path Summary:

Slack 0.756
Data Arrival Time 1.876
Data Required Time 1.120
From u_ov5647_ctrl/resend_s0
To u_ov5647_ctrl/I2C/busy_sr_31_s1
Launch Clk clk_50:[R]
Latch Clk clk_50:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 218 LEFTSIDE[0] uut_div4/CLKOUT
1.303 1.303 tNET RR 1 R56C98[1][A] u_ov5647_ctrl/resend_s0/CLK
1.483 0.180 tC2Q RR 103 R56C98[1][A] u_ov5647_ctrl/resend_s0/Q
1.876 0.392 tNET RR 1 R56C101[0][A] u_ov5647_ctrl/I2C/busy_sr_31_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 218 LEFTSIDE[0] uut_div4/CLKOUT
1.308 1.308 tNET RR 1 R56C101[0][A] u_ov5647_ctrl/I2C/busy_sr_31_s1/CLK
1.120 -0.189 tHld 1 R56C101[0][A] u_ov5647_ctrl/I2C/busy_sr_31_s1

Path Statistics:

Clock Skew 0.005
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.303, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.392, 68.559%; tC2Q: 0.180, 31.441%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.308, 100.000%

Path21

Path Summary:

Slack 0.756
Data Arrival Time 1.876
Data Required Time 1.120
From u_ov5647_ctrl/resend_s0
To u_ov5647_ctrl/I2C/busy_sr_32_s1
Launch Clk clk_50:[R]
Latch Clk clk_50:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 218 LEFTSIDE[0] uut_div4/CLKOUT
1.303 1.303 tNET RR 1 R56C98[1][A] u_ov5647_ctrl/resend_s0/CLK
1.483 0.180 tC2Q RR 103 R56C98[1][A] u_ov5647_ctrl/resend_s0/Q
1.876 0.392 tNET RR 1 R56C101[0][B] u_ov5647_ctrl/I2C/busy_sr_32_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 218 LEFTSIDE[0] uut_div4/CLKOUT
1.308 1.308 tNET RR 1 R56C101[0][B] u_ov5647_ctrl/I2C/busy_sr_32_s1/CLK
1.120 -0.189 tHld 1 R56C101[0][B] u_ov5647_ctrl/I2C/busy_sr_32_s1

Path Statistics:

Clock Skew 0.005
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.303, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.392, 68.559%; tC2Q: 0.180, 31.441%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.308, 100.000%

Path22

Path Summary:

Slack 0.756
Data Arrival Time 1.876
Data Required Time 1.120
From u_ov5647_ctrl/resend_s0
To u_ov5647_ctrl/I2C/busy_sr_33_s1
Launch Clk clk_50:[R]
Latch Clk clk_50:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 218 LEFTSIDE[0] uut_div4/CLKOUT
1.303 1.303 tNET RR 1 R56C98[1][A] u_ov5647_ctrl/resend_s0/CLK
1.483 0.180 tC2Q RR 103 R56C98[1][A] u_ov5647_ctrl/resend_s0/Q
1.876 0.392 tNET RR 1 R56C101[1][A] u_ov5647_ctrl/I2C/busy_sr_33_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 218 LEFTSIDE[0] uut_div4/CLKOUT
1.308 1.308 tNET RR 1 R56C101[1][A] u_ov5647_ctrl/I2C/busy_sr_33_s1/CLK
1.120 -0.189 tHld 1 R56C101[1][A] u_ov5647_ctrl/I2C/busy_sr_33_s1

Path Statistics:

Clock Skew 0.005
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.303, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.392, 68.559%; tC2Q: 0.180, 31.441%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.308, 100.000%

Path23

Path Summary:

Slack 0.756
Data Arrival Time 1.876
Data Required Time 1.120
From u_ov5647_ctrl/resend_s0
To u_ov5647_ctrl/I2C/busy_sr_34_s1
Launch Clk clk_50:[R]
Latch Clk clk_50:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 218 LEFTSIDE[0] uut_div4/CLKOUT
1.303 1.303 tNET RR 1 R56C98[1][A] u_ov5647_ctrl/resend_s0/CLK
1.483 0.180 tC2Q RR 103 R56C98[1][A] u_ov5647_ctrl/resend_s0/Q
1.876 0.392 tNET RR 1 R56C101[1][B] u_ov5647_ctrl/I2C/busy_sr_34_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 218 LEFTSIDE[0] uut_div4/CLKOUT
1.308 1.308 tNET RR 1 R56C101[1][B] u_ov5647_ctrl/I2C/busy_sr_34_s1/CLK
1.120 -0.189 tHld 1 R56C101[1][B] u_ov5647_ctrl/I2C/busy_sr_34_s1

Path Statistics:

Clock Skew 0.005
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.303, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.392, 68.559%; tC2Q: 0.180, 31.441%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.308, 100.000%

Path24

Path Summary:

Slack 0.756
Data Arrival Time 1.876
Data Required Time 1.120
From u_ov5647_ctrl/resend_s0
To u_ov5647_ctrl/I2C/busy_sr_35_s1
Launch Clk clk_50:[R]
Latch Clk clk_50:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 218 LEFTSIDE[0] uut_div4/CLKOUT
1.303 1.303 tNET RR 1 R56C98[1][A] u_ov5647_ctrl/resend_s0/CLK
1.483 0.180 tC2Q RR 103 R56C98[1][A] u_ov5647_ctrl/resend_s0/Q
1.876 0.392 tNET RR 1 R56C101[2][A] u_ov5647_ctrl/I2C/busy_sr_35_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 218 LEFTSIDE[0] uut_div4/CLKOUT
1.308 1.308 tNET RR 1 R56C101[2][A] u_ov5647_ctrl/I2C/busy_sr_35_s1/CLK
1.120 -0.189 tHld 1 R56C101[2][A] u_ov5647_ctrl/I2C/busy_sr_35_s1

Path Statistics:

Clock Skew 0.005
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.303, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.392, 68.559%; tC2Q: 0.180, 31.441%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.308, 100.000%

Path25

Path Summary:

Slack 0.756
Data Arrival Time 1.876
Data Required Time 1.120
From u_ov5647_ctrl/resend_s0
To u_ov5647_ctrl/I2C/busy_sr_36_s1
Launch Clk clk_50:[R]
Latch Clk clk_50:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 218 LEFTSIDE[0] uut_div4/CLKOUT
1.303 1.303 tNET RR 1 R56C98[1][A] u_ov5647_ctrl/resend_s0/CLK
1.483 0.180 tC2Q RR 103 R56C98[1][A] u_ov5647_ctrl/resend_s0/Q
1.876 0.392 tNET RR 1 R56C101[2][B] u_ov5647_ctrl/I2C/busy_sr_36_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_50
0.000 0.000 tCL RR 218 LEFTSIDE[0] uut_div4/CLKOUT
1.308 1.308 tNET RR 1 R56C101[2][B] u_ov5647_ctrl/I2C/busy_sr_36_s1/CLK
1.120 -0.189 tHld 1 R56C101[2][B] u_ov5647_ctrl/I2C/busy_sr_36_s1

Path Statistics:

Clock Skew 0.005
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.303, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.392, 68.559%; tC2Q: 0.180, 31.441%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.308, 100.000%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack: 1.531
Actual Width: 2.531
Required Width: 1.000
Type: High Pulse Width
Clock: pixel_clk
Objects: u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR u_pll/PLL_inst/CLKOUT1
2.706 2.706 tNET RR u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s/CLKB

Early clock Path:

AT DELAY TYPE RF NODE
3.750 0.000 active clock edge time
3.750 0.000 pixel_clk
3.750 0.000 tCL FF u_pll/PLL_inst/CLKOUT1
5.237 1.487 tNET FF u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s/CLKB

MPW2

MPW Summary:

Slack: 1.579
Actual Width: 2.579
Required Width: 1.000
Type: High Pulse Width
Clock: pixel_clk
Objects: u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR u_pll/PLL_inst/CLKOUT1
2.657 2.657 tNET RR u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/CLKA

Early clock Path:

AT DELAY TYPE RF NODE
3.750 0.000 active clock edge time
3.750 0.000 pixel_clk
3.750 0.000 tCL FF u_pll/PLL_inst/CLKOUT1
5.236 1.486 tNET FF u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/CLKA

MPW3

MPW Summary:

Slack: 1.583
Actual Width: 2.583
Required Width: 1.000
Type: High Pulse Width
Clock: pixel_clk
Objects: u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR u_pll/PLL_inst/CLKOUT1
2.648 2.648 tNET RR u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/CLKB

Early clock Path:

AT DELAY TYPE RF NODE
3.750 0.000 active clock edge time
3.750 0.000 pixel_clk
3.750 0.000 tCL FF u_pll/PLL_inst/CLKOUT1
5.231 1.481 tNET FF u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/CLKB

MPW4

MPW Summary:

Slack: 1.584
Actual Width: 2.584
Required Width: 1.000
Type: Low Pulse Width
Clock: pixel_clk
Objects: u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s

Late clock Path:

AT DELAY TYPE RF NODE
3.750 0.000 active clock edge time
3.750 0.000 pixel_clk
3.750 0.000 tCL FF u_pll/PLL_inst/CLKOUT1
6.161 2.411 tNET FF u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s/CLKB

Early clock Path:

AT DELAY TYPE RF NODE
7.500 0.000 active clock edge time
7.500 0.000 pixel_clk
7.500 0.000 tCL RR u_pll/PLL_inst/CLKOUT1
8.745 1.245 tNET RR u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s/CLKB

MPW5

MPW Summary:

Slack: 1.628
Actual Width: 2.628
Required Width: 1.000
Type: Low Pulse Width
Clock: pixel_clk
Objects: u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s

Late clock Path:

AT DELAY TYPE RF NODE
3.750 0.000 active clock edge time
3.750 0.000 pixel_clk
3.750 0.000 tCL FF u_pll/PLL_inst/CLKOUT1
6.116 2.366 tNET FF u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/CLKA

Early clock Path:

AT DELAY TYPE RF NODE
7.500 0.000 active clock edge time
7.500 0.000 pixel_clk
7.500 0.000 tCL RR u_pll/PLL_inst/CLKOUT1
8.744 1.244 tNET RR u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/CLKA

MPW6

MPW Summary:

Slack: 1.632
Actual Width: 2.632
Required Width: 1.000
Type: Low Pulse Width
Clock: pixel_clk
Objects: u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s

Late clock Path:

AT DELAY TYPE RF NODE
3.750 0.000 active clock edge time
3.750 0.000 pixel_clk
3.750 0.000 tCL FF u_pll/PLL_inst/CLKOUT1
6.107 2.357 tNET FF u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/CLKB

Early clock Path:

AT DELAY TYPE RF NODE
7.500 0.000 active clock edge time
7.500 0.000 pixel_clk
7.500 0.000 tCL RR u_pll/PLL_inst/CLKOUT1
8.739 1.239 tNET RR u_bayer_rgb/shift_line_inst0/ram_line_inst/ram_ram_0_0_s/CLKB

MPW7

MPW Summary:

Slack: 2.277
Actual Width: 2.527
Required Width: 0.250
Type: High Pulse Width
Clock: pixel_clk
Objects: u_b2p/u_b2p_inst/u_mid_fifo/rRstRsync_s0

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR u_pll/PLL_inst/CLKOUT1
2.740 2.740 tNET RR u_b2p/u_b2p_inst/u_mid_fifo/rRstRsync_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
3.750 0.000 active clock edge time
3.750 0.000 pixel_clk
3.750 0.000 tCL FF u_pll/PLL_inst/CLKOUT1
5.267 1.518 tNET FF u_b2p/u_b2p_inst/u_mid_fifo/rRstRsync_s0/CLK

MPW8

MPW Summary:

Slack: 2.277
Actual Width: 2.527
Required Width: 0.250
Type: High Pulse Width
Clock: pixel_clk
Objects: u_b2p/u_b2p_inst/u_mid_fifo/rRdClr_s0

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR u_pll/PLL_inst/CLKOUT1
2.737 2.737 tNET RR u_b2p/u_b2p_inst/u_mid_fifo/rRdClr_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
3.750 0.000 active clock edge time
3.750 0.000 pixel_clk
3.750 0.000 tCL FF u_pll/PLL_inst/CLKOUT1
5.265 1.515 tNET FF u_b2p/u_b2p_inst/u_mid_fifo/rRdClr_s0/CLK

MPW9

MPW Summary:

Slack: 2.277
Actual Width: 2.527
Required Width: 0.250
Type: High Pulse Width
Clock: pixel_clk
Objects: u_b2p/u_b2p_inst/u_mid_fifo/rRdRst_s0

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR u_pll/PLL_inst/CLKOUT1
2.740 2.740 tNET RR u_b2p/u_b2p_inst/u_mid_fifo/rRdRst_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
3.750 0.000 active clock edge time
3.750 0.000 pixel_clk
3.750 0.000 tCL FF u_pll/PLL_inst/CLKOUT1
5.267 1.518 tNET FF u_b2p/u_b2p_inst/u_mid_fifo/rRdRst_s0/CLK

MPW10

MPW Summary:

Slack: 2.280
Actual Width: 2.530
Required Width: 0.250
Type: High Pulse Width
Clock: pixel_clk
Objects: u_b2p/u_b2p_inst/pixel_data_r_1_s0

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR u_pll/PLL_inst/CLKOUT1
2.713 2.713 tNET RR u_b2p/u_b2p_inst/pixel_data_r_1_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
3.750 0.000 active clock edge time
3.750 0.000 pixel_clk
3.750 0.000 tCL FF u_pll/PLL_inst/CLKOUT1
5.243 1.493 tNET FF u_b2p/u_b2p_inst/pixel_data_r_1_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT NET NAME WORST SLACK MAX DELAY
625 byte_clk 2.962 6.220
244 lvds_pclk 2.365 2.740
218 clk_50m 8.860 2.976
103 resend 13.600 3.536
82 n268_3 12.207 3.048
74 busy_sr[40] 14.153 2.205
57 address[2] 13.759 2.301
54 address[1] 14.053 2.444
49 address[4] 13.787 2.807
49 rDataEn 9.978 2.200

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC ROUTE CONGESTIONS
R54C63 47.22%
R54C65 47.22%
R53C113 44.44%
R54C88 44.44%
R54C127 43.06%
R54C66 41.67%
R54C62 41.67%
R56C66 40.28%
R54C61 37.50%
R56C60 37.50%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type State Detail Command
TC_CLOCK Actived create_clock -name clk_50 -period 20 -waveform {0 10} [get_nets {clk_50m}]
TC_CLOCK Actived create_clock -name byte_clk -period 15 -waveform {0 7.5} [get_nets {byte_clk}]
TC_GENERATED_CLOCK Actived create_generated_clock -name pixel_clk -source [get_nets {byte_clk}] -master_clock byte_clk -divide_by 1 -multiply_by 2 [get_nets {lvds_pclk}]
TC_CLOCK_GROUP Actived set_clock_groups -exclusive -group [get_clocks {pixel_clk}] -group [get_clocks {byte_clk}]
TC_CLOCK_GROUP Actived set_clock_groups -exclusive -group [get_clocks {pixel_clk}] -group [get_clocks {clk_50}]
TC_CLOCK_GROUP Actived set_clock_groups -exclusive -group [get_clocks {clk_50}] -group [get_clocks {byte_clk}]
TC_REPORT_TIMING Actived report_timing -setup -from_clock [get_clocks {pixel_clk}] -max_paths 20 -max_common_paths 1
TC_REPORT_TIMING Actived report_timing -setup -from_clock [get_clocks {byte_clk}] -max_paths 20 -max_common_paths 1
TC_REPORT_TIMING Actived report_timing -hold -from_clock [get_clocks {pixel_clk}] -max_paths 20 -max_common_paths 1
TC_REPORT_TIMING Actived report_timing -hold -from_clock [get_clocks {byte_clk}] -max_paths 20 -max_common_paths 1