Hierarchy Module Resource

MODULE NAME REG NUMBER ALU NUMBER LUT NUMBER DSP NUMBER BSRAM NUMBER SSRAM NUMBER
Dsi2Lvds_Top (F:/mySrc/MIPI_modular_IP/Ref_Design/Saved/DSI_to_LVDS_2a18/fpga_proj/src/top.v) 12 - 15 - - -
    |--u_mipi_dphy (F:/mySrc/MIPI_modular_IP/Ref_Design/Saved/DSI_to_LVDS_2a18/fpga_proj/src/top.v) 473 - 467 - - -
    |--u_dsi_rx (F:/mySrc/MIPI_modular_IP/Ref_Design/Saved/DSI_to_LVDS_2a18/fpga_proj/src/top.v) 216 9 266 - - -
    |--u_pll_1 (F:/mySrc/MIPI_modular_IP/Ref_Design/Saved/DSI_to_LVDS_2a18/fpga_proj/src/top.v) - - - - - -
    |--u_pll_2 (F:/mySrc/MIPI_modular_IP/Ref_Design/Saved/DSI_to_LVDS_2a18/fpga_proj/src/top.v) - - - - - -
    |--u_b2p (F:/mySrc/MIPI_modular_IP/Ref_Design/Saved/DSI_to_LVDS_2a18/fpga_proj/src/top.v) 457 14 315 - - 12
    |--u_extr (F:/mySrc/MIPI_modular_IP/Ref_Design/Saved/DSI_to_LVDS_2a18/fpga_proj/src/top.v) 174 25 153 - 12 -
    |--u_lvds_tx_left (F:/mySrc/MIPI_modular_IP/Ref_Design/Saved/DSI_to_LVDS_2a18/fpga_proj/src/top.v) - - - - - -
        |--LVDS_71_Tx (F:/mySrc/MIPI_modular_IP/Ref_Design/Saved/DSI_to_LVDS_2a18/fpga_proj/src/lvds_tx/lvds_7_to_1_tx.v) 1 - - - - -