Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\DSI_to_LVDS_5a25\fpga_proj\src\byte_to_pixel\byte_to_pixel.v F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\DSI_to_LVDS_5a25\fpga_proj\src\dpi_extractor.v F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\DSI_to_LVDS_5a25\fpga_proj\src\dsi_rx\dsi_rx_top.v F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\DSI_to_LVDS_5a25\fpga_proj\src\gowin_mipi_dphy\gowin_mipi_dphy.v F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\DSI_to_LVDS_5a25\fpga_proj\src\gowin_pll\gowin_pll_in_105m.v F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\DSI_to_LVDS_5a25\fpga_proj\src\gowin_pll\gowin_pll_in_50m.v F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\DSI_to_LVDS_5a25\fpga_proj\src\lvds_tx\ip_gddr71tx.v F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\DSI_to_LVDS_5a25\fpga_proj\src\lvds_tx\lvds_7_to_1_tx.v F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\DSI_to_LVDS_5a25\fpga_proj\src\top.v D:\Programs\Gowin\Gowin_V1.9.9.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v D:\Programs\Gowin\Gowin_V1.9.9.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v D:\Programs\Gowin\Gowin_V1.9.9.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v D:\Programs\Gowin\Gowin_V1.9.9.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v D:\Programs\Gowin\Gowin_V1.9.9.01_x64\IDE\data\ipcores\GAO\GW_CON\gw_con_top.v D:\Programs\Gowin\Gowin_V1.9.9.01_x64\IDE\data\ipcores\gw_jtag.v F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\DSI_to_LVDS_5a25\fpga_proj\impl\gwsynthesis\RTL_GAO\gw_gao_top.v |
GowinSynthesis Constraints File | --- |
Tool Version | V1.9.9.01 (64-bit) |
Part Number | GW5A-LV25UG324ES |
Device | GW5A-25 |
Device Version | A |
Created Time | Wed Mar 6 18:50:02 2024 |
Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | Dsi2Lvds_Top |
Synthesis Process | Running parser: CPU time = 0h 0m 0.515s, Elapsed time = 0h 0m 0.511s, Peak memory usage = 607.168MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.06s, Peak memory usage = 607.168MB Optimizing Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.033s, Peak memory usage = 607.168MB Optimizing Phase 2: CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.195s, Peak memory usage = 607.168MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.049s, Peak memory usage = 607.168MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 607.168MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 607.168MB Inferring Phase 3: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 607.168MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.099s, Peak memory usage = 607.168MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.024s, Peak memory usage = 607.168MB Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 607.168MB Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 607.168MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.109s, Peak memory usage = 607.168MB Generate output files: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.12s, Peak memory usage = 607.168MB |
Total Time and Memory Usage | CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 607.168MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 29 |
I/O Buf | 14 |
    IBUF | 5 |
    OBUF | 4 |
    TLVDS_OBUF | 5 |
Register | 1264 |
    DFFSE | 36 |
    DFFRE | 286 |
    DFFPE | 46 |
    DFFCE | 896 |
LUT | 1232 |
    LUT2 | 113 |
    LUT3 | 451 |
    LUT4 | 668 |
MUX | 1 |
    MUX16 | 1 |
ALU | 93 |
    ALU | 93 |
INV | 20 |
    INV | 20 |
IOLOGIC | 5 |
    OVIDEO | 5 |
BSRAM | 18 |
    SDPB | 18 |
CLOCK | 3 |
    DHCE | 1 |
    PLLA | 2 |
Black Box | 2 |
    GW_JTAG | 1 |
MIPI_DPHY | 1 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 1353(1260 LUT, 93 ALU) / 23040 | 6% |
Register | 1264 / 23685 | 6% |
  --Register as Latch | 0 / 23685 | 0% |
  --Register as FF | 1264 / 23685 | 6% |
BSRAM | 18 / 56 | 33% |
Timing
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|
OSC_50M | Base | 20.000 | 50.0 | 0.000 | 10.000 | OSC_50M_ibuf/I | ||
gw_gao_inst_0/u_icon_top/n19_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 | gw_gao_inst_0/u_icon_top/n19_s2/O | ||
gw_gao_inst_0/u_la0_top/n15_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 | gw_gao_inst_0/u_la0_top/n15_s2/O | ||
u_pll_50m/PLLA_inst/CLKOUT0.default_gen_clk | Generated | 2.105 | 475.0 | 0.000 | 1.053 | OSC_50M_ibuf/I | OSC_50M | u_pll_50m/PLLA_inst/CLKOUT0 |
u_pll_50m/PLLA_inst/CLKOUT1.default_gen_clk | Generated | 7.368 | 135.7 | 0.000 | 3.684 | OSC_50M_ibuf/I | OSC_50M | u_pll_50m/PLLA_inst/CLKOUT1 |
Max Frequency Summary:
No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | gw_gao_inst_0/u_icon_top/n19_6 | 100.000(MHz) | 1217.656(MHz) | 1 | TOP |
2 | gw_gao_inst_0/u_la0_top/n15_6 | 100.000(MHz) | 1217.656(MHz) | 1 | TOP |
3 | u_pll_50m/PLLA_inst/CLKOUT1.default_gen_clk | 135.714(MHz) | 168.492(MHz) | 7 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | 1.433 |
Data Arrival Time | 7.230 |
Data Required Time | 8.664 |
From | u_extr/ovcnt_2_s1 |
To | u_extr/ovcnt_12_s1 |
Launch Clk | u_pll_50m/PLLA_inst/CLKOUT1.default_gen_clk[R] |
Latch Clk | u_pll_50m/PLLA_inst/CLKOUT1.default_gen_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | u_pll_50m/PLLA_inst/CLKOUT1.default_gen_clk | |||
0.984 | 0.984 | tCL | RR | 165 | u_pll_50m/PLLA_inst/CLKOUT1 |
1.359 | 0.375 | tNET | RR | 1 | u_extr/ovcnt_2_s1/CLK |
1.741 | 0.382 | tC2Q | RR | 7 | u_extr/ovcnt_2_s1/Q |
2.116 | 0.375 | tNET | RR | 1 | u_extr/n792_s3/I0 |
2.643 | 0.526 | tINS | RR | 3 | u_extr/n792_s3/F |
3.018 | 0.375 | tNET | RR | 1 | u_extr/n789_s3/I3 |
3.280 | 0.262 | tINS | RR | 3 | u_extr/n789_s3/F |
3.655 | 0.375 | tNET | RR | 1 | u_extr/n788_s3/I1 |
4.171 | 0.516 | tINS | RR | 3 | u_extr/n788_s3/F |
4.546 | 0.375 | tNET | RR | 1 | u_extr/n785_s4/I1 |
5.063 | 0.516 | tINS | RR | 5 | u_extr/n785_s4/F |
5.438 | 0.375 | tNET | RR | 1 | u_extr/n783_s5/I0 |
5.964 | 0.526 | tINS | RR | 2 | u_extr/n783_s5/F |
6.339 | 0.375 | tNET | RR | 1 | u_extr/n783_s6/I1 |
6.855 | 0.516 | tINS | RR | 1 | u_extr/n783_s6/F |
7.230 | 0.375 | tNET | RR | 1 | u_extr/ovcnt_12_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
7.368 | 0.000 | u_pll_50m/PLLA_inst/CLKOUT1.default_gen_clk | |||
8.352 | 0.984 | tCL | RR | 165 | u_pll_50m/PLLA_inst/CLKOUT1 |
8.727 | 0.375 | tNET | RR | 1 | u_extr/ovcnt_12_s1/CLK |
8.664 | -0.064 | tSu | 1 | u_extr/ovcnt_12_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 7.368 |
Logic Level: | 7 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Arrival Data Path Delay: | cell: 2.864, 48.776%; route: 2.625, 44.709%; tC2Q: 0.382, 6.515% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 2
Path Summary:Slack | 1.433 |
Data Arrival Time | 7.230 |
Data Required Time | 8.664 |
From | u_extr/ovcnt_2_s1 |
To | u_extr/ohs_s0 |
Launch Clk | u_pll_50m/PLLA_inst/CLKOUT1.default_gen_clk[R] |
Latch Clk | u_pll_50m/PLLA_inst/CLKOUT1.default_gen_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | u_pll_50m/PLLA_inst/CLKOUT1.default_gen_clk | |||
0.984 | 0.984 | tCL | RR | 165 | u_pll_50m/PLLA_inst/CLKOUT1 |
1.359 | 0.375 | tNET | RR | 1 | u_extr/ovcnt_2_s1/CLK |
1.741 | 0.382 | tC2Q | RR | 7 | u_extr/ovcnt_2_s1/Q |
2.116 | 0.375 | tNET | RR | 1 | u_extr/n792_s3/I0 |
2.643 | 0.526 | tINS | RR | 3 | u_extr/n792_s3/F |
3.018 | 0.375 | tNET | RR | 1 | u_extr/n789_s3/I3 |
3.280 | 0.262 | tINS | RR | 3 | u_extr/n789_s3/F |
3.655 | 0.375 | tNET | RR | 1 | u_extr/n788_s3/I1 |
4.171 | 0.516 | tINS | RR | 3 | u_extr/n788_s3/F |
4.546 | 0.375 | tNET | RR | 1 | u_extr/n785_s4/I1 |
5.063 | 0.516 | tINS | RR | 5 | u_extr/n785_s4/F |
5.438 | 0.375 | tNET | RR | 1 | u_extr/n783_s5/I0 |
5.964 | 0.526 | tINS | RR | 2 | u_extr/n783_s5/F |
6.339 | 0.375 | tNET | RR | 1 | u_extr/n846_s1/I1 |
6.855 | 0.516 | tINS | RR | 1 | u_extr/n846_s1/F |
7.230 | 0.375 | tNET | RR | 1 | u_extr/ohs_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
7.368 | 0.000 | u_pll_50m/PLLA_inst/CLKOUT1.default_gen_clk | |||
8.352 | 0.984 | tCL | RR | 165 | u_pll_50m/PLLA_inst/CLKOUT1 |
8.727 | 0.375 | tNET | RR | 1 | u_extr/ohs_s0/CLK |
8.664 | -0.064 | tSu | 1 | u_extr/ohs_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 7.368 |
Logic Level: | 7 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Arrival Data Path Delay: | cell: 2.864, 48.776%; route: 2.625, 44.709%; tC2Q: 0.382, 6.515% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 3
Path Summary:Slack | 1.498 |
Data Arrival Time | 7.165 |
Data Required Time | 8.664 |
From | u_extr/ovcnt_2_s1 |
To | u_extr/ovcnt_14_s1 |
Launch Clk | u_pll_50m/PLLA_inst/CLKOUT1.default_gen_clk[R] |
Latch Clk | u_pll_50m/PLLA_inst/CLKOUT1.default_gen_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | u_pll_50m/PLLA_inst/CLKOUT1.default_gen_clk | |||
0.984 | 0.984 | tCL | RR | 165 | u_pll_50m/PLLA_inst/CLKOUT1 |
1.359 | 0.375 | tNET | RR | 1 | u_extr/ovcnt_2_s1/CLK |
1.741 | 0.382 | tC2Q | RR | 7 | u_extr/ovcnt_2_s1/Q |
2.116 | 0.375 | tNET | RR | 1 | u_extr/n792_s3/I0 |
2.643 | 0.526 | tINS | RR | 3 | u_extr/n792_s3/F |
3.018 | 0.375 | tNET | RR | 1 | u_extr/n789_s3/I3 |
3.280 | 0.262 | tINS | RR | 3 | u_extr/n789_s3/F |
3.655 | 0.375 | tNET | RR | 1 | u_extr/n788_s3/I1 |
4.171 | 0.516 | tINS | RR | 3 | u_extr/n788_s3/F |
4.546 | 0.375 | tNET | RR | 1 | u_extr/n785_s4/I1 |
5.063 | 0.516 | tINS | RR | 5 | u_extr/n785_s4/F |
5.438 | 0.375 | tNET | RR | 1 | u_extr/n781_s3/I2 |
5.899 | 0.461 | tINS | RR | 2 | u_extr/n781_s3/F |
6.274 | 0.375 | tNET | RR | 1 | u_extr/n781_s4/I1 |
6.790 | 0.516 | tINS | RR | 1 | u_extr/n781_s4/F |
7.165 | 0.375 | tNET | RR | 1 | u_extr/ovcnt_14_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
7.368 | 0.000 | u_pll_50m/PLLA_inst/CLKOUT1.default_gen_clk | |||
8.352 | 0.984 | tCL | RR | 165 | u_pll_50m/PLLA_inst/CLKOUT1 |
8.727 | 0.375 | tNET | RR | 1 | u_extr/ovcnt_14_s1/CLK |
8.664 | -0.064 | tSu | 1 | u_extr/ovcnt_14_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 7.368 |
Logic Level: | 7 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Arrival Data Path Delay: | cell: 2.799, 48.202%; route: 2.625, 45.210%; tC2Q: 0.382, 6.588% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 4
Path Summary:Slack | 1.498 |
Data Arrival Time | 7.165 |
Data Required Time | 8.664 |
From | u_extr/ovcnt_2_s1 |
To | u_extr/ovcnt_15_s1 |
Launch Clk | u_pll_50m/PLLA_inst/CLKOUT1.default_gen_clk[R] |
Latch Clk | u_pll_50m/PLLA_inst/CLKOUT1.default_gen_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | u_pll_50m/PLLA_inst/CLKOUT1.default_gen_clk | |||
0.984 | 0.984 | tCL | RR | 165 | u_pll_50m/PLLA_inst/CLKOUT1 |
1.359 | 0.375 | tNET | RR | 1 | u_extr/ovcnt_2_s1/CLK |
1.741 | 0.382 | tC2Q | RR | 7 | u_extr/ovcnt_2_s1/Q |
2.116 | 0.375 | tNET | RR | 1 | u_extr/n792_s3/I0 |
2.643 | 0.526 | tINS | RR | 3 | u_extr/n792_s3/F |
3.018 | 0.375 | tNET | RR | 1 | u_extr/n789_s3/I3 |
3.280 | 0.262 | tINS | RR | 3 | u_extr/n789_s3/F |
3.655 | 0.375 | tNET | RR | 1 | u_extr/n788_s3/I1 |
4.171 | 0.516 | tINS | RR | 3 | u_extr/n788_s3/F |
4.546 | 0.375 | tNET | RR | 1 | u_extr/n785_s4/I1 |
5.063 | 0.516 | tINS | RR | 5 | u_extr/n785_s4/F |
5.438 | 0.375 | tNET | RR | 1 | u_extr/n781_s3/I2 |
5.899 | 0.461 | tINS | RR | 2 | u_extr/n781_s3/F |
6.274 | 0.375 | tNET | RR | 1 | u_extr/n780_s2/I1 |
6.790 | 0.516 | tINS | RR | 1 | u_extr/n780_s2/F |
7.165 | 0.375 | tNET | RR | 1 | u_extr/ovcnt_15_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
7.368 | 0.000 | u_pll_50m/PLLA_inst/CLKOUT1.default_gen_clk | |||
8.352 | 0.984 | tCL | RR | 165 | u_pll_50m/PLLA_inst/CLKOUT1 |
8.727 | 0.375 | tNET | RR | 1 | u_extr/ovcnt_15_s1/CLK |
8.664 | -0.064 | tSu | 1 | u_extr/ovcnt_15_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 7.368 |
Logic Level: | 7 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Arrival Data Path Delay: | cell: 2.799, 48.202%; route: 2.625, 45.210%; tC2Q: 0.382, 6.588% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 5
Path Summary:Slack | 2.081 |
Data Arrival Time | 6.274 |
Data Required Time | 8.355 |
From | u_extr/buf_ra_0_s0 |
To | u_extr/buf_ra_10_s8 |
Launch Clk | u_pll_50m/PLLA_inst/CLKOUT1.default_gen_clk[R] |
Latch Clk | u_pll_50m/PLLA_inst/CLKOUT1.default_gen_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | u_pll_50m/PLLA_inst/CLKOUT1.default_gen_clk | |||
0.984 | 0.984 | tCL | RR | 165 | u_pll_50m/PLLA_inst/CLKOUT1 |
1.359 | 0.375 | tNET | RR | 1 | u_extr/buf_ra_0_s0/CLK |
1.741 | 0.382 | tC2Q | RR | 8 | u_extr/buf_ra_0_s0/Q |
2.116 | 0.375 | tNET | RR | 1 | u_extr/n882_s4/I0 |
2.643 | 0.526 | tINS | RR | 5 | u_extr/n882_s4/F |
3.018 | 0.375 | tNET | RR | 1 | u_extr/n879_s4/I3 |
3.280 | 0.262 | tINS | RR | 5 | u_extr/n879_s4/F |
3.655 | 0.375 | tNET | RR | 1 | u_extr/n878_s4/I1 |
4.171 | 0.516 | tINS | RR | 1 | u_extr/n878_s4/F |
4.546 | 0.375 | tNET | RR | 1 | u_extr/n876_s2/I2 |
5.008 | 0.461 | tINS | RR | 3 | u_extr/n876_s2/F |
5.383 | 0.375 | tNET | RR | 1 | u_extr/buf_ra_10_s11/I1 |
5.899 | 0.516 | tINS | RR | 1 | u_extr/buf_ra_10_s11/F |
6.274 | 0.375 | tNET | RR | 1 | u_extr/buf_ra_10_s8/RESET |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
7.368 | 0.000 | u_pll_50m/PLLA_inst/CLKOUT1.default_gen_clk | |||
8.352 | 0.984 | tCL | RR | 165 | u_pll_50m/PLLA_inst/CLKOUT1 |
8.727 | 0.375 | tNET | RR | 1 | u_extr/buf_ra_10_s8/CLK |
8.355 | -0.373 | tSu | 1 | u_extr/buf_ra_10_s8 |
Clock Skew: | 0.000 |
Setup Relationship: | 7.368 |
Logic Level: | 6 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Arrival Data Path Delay: | cell: 2.283, 46.440%; route: 2.250, 45.778%; tC2Q: 0.382, 7.782% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |