Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\MIPI_BYTE_TO_PIXEL\data\byte_to_pixel.v C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\MIPI_BYTE_TO_PIXEL\data\byte_to_pixel_wrap.v |
GowinSynthesis Constraints File | --- |
Tool Version | V1.9.9.02 |
Part Number | GW5AT-LV138PG676AC1/I0 |
Device | GW5AT-138 |
Device Version | B |
Created Time | Tue Mar 19 15:22:46 2024 |
Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | Byte_to_Pixel_Top |
Synthesis Process | Running parser: CPU time = 0h 0m 0.296s, Elapsed time = 0h 0m 0.331s, Peak memory usage = 112.121MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 112.121MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 112.121MB Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 112.121MB Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 112.121MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 112.121MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 112.121MB Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 112.121MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 112.121MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 112.121MB Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 112.121MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 112.121MB Tech-Mapping Phase 3: CPU time = 0h 0m 0.468s, Elapsed time = 0h 0m 0.541s, Peak memory usage = 135.125MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.052s, Peak memory usage = 135.125MB Generate output files: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.026s, Peak memory usage = 135.125MB |
Total Time and Memory Usage | CPU time = 0h 0m 0.87s, Elapsed time = 0h 0m 1s, Peak memory usage = 135.125MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 55 |
I/O Buf | 55 |
    IBUF | 45 |
    OBUF | 10 |
Register | 207 |
    DFFSE | 2 |
    DFFRE | 52 |
    DFFPE | 7 |
    DFFCE | 146 |
LUT | 137 |
    LUT2 | 23 |
    LUT3 | 37 |
    LUT4 | 77 |
ALU | 20 |
    ALU | 20 |
INV | 6 |
    INV | 6 |
BSRAM | 1 |
    SDPB | 1 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 163(143 LUT, 20 ALU) / 138240 | <1% |
Register | 207 / 139140 | <1% |
  --Register as Latch | 0 / 139140 | 0% |
  --Register as FF | 207 / 139140 | <1% |
BSRAM | 1 / 340 | <1% |
Timing
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|
I_BYTE_CLK | Base | 10.000 | 100.0 | 0.000 | 5.000 | I_BYTE_CLK_ibuf/I | ||
I_PIXEL_CLK | Base | 10.000 | 100.0 | 0.000 | 5.000 | I_PIXEL_CLK_ibuf/I |
Max Frequency Summary:
No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | I_BYTE_CLK | 100.000(MHz) | 169.384(MHz) | 7 | TOP |
2 | I_PIXEL_CLK | 100.000(MHz) | 208.279(MHz) | 5 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | 4.096 |
Data Arrival Time | 6.935 |
Data Required Time | 11.031 |
From | u_b2p_inst/u_mid_fifo/rRPtrWsync_3_s0 |
To | u_b2p_inst/u_mid_fifo/rFull_s0 |
Launch Clk | I_BYTE_CLK[R] |
Latch Clk | I_BYTE_CLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | I_BYTE_CLK | |||
0.000 | 0.000 | tCL | RR | 1 | I_BYTE_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 162 | I_BYTE_CLK_ibuf/O |
1.095 | 0.413 | tNET | RR | 1 | u_b2p_inst/u_mid_fifo/rRPtrWsync_3_s0/CLK |
1.477 | 0.382 | tC2Q | RR | 2 | u_b2p_inst/u_mid_fifo/rRPtrWsync_3_s0/Q |
1.890 | 0.413 | tNET | RR | 1 | u_b2p_inst/u_mid_fifo/wRPtrBinX_3_s0/I0 |
2.469 | 0.579 | tINS | RR | 5 | u_b2p_inst/u_mid_fifo/wRPtrBinX_3_s0/F |
2.881 | 0.413 | tNET | RR | 1 | u_b2p_inst/u_mid_fifo/wRPtrBinX_2_s0/I1 |
3.449 | 0.567 | tINS | RR | 1 | u_b2p_inst/u_mid_fifo/wRPtrBinX_2_s0/F |
3.861 | 0.413 | tNET | RR | 2 | u_b2p_inst/u_mid_fifo/n401_s0/I1 |
4.461 | 0.600 | tINS | RF | 1 | u_b2p_inst/u_mid_fifo/n401_s0/COUT |
4.461 | 0.000 | tNET | FF | 2 | u_b2p_inst/u_mid_fifo/n402_s0/CIN |
4.511 | 0.050 | tINS | FR | 1 | u_b2p_inst/u_mid_fifo/n402_s0/COUT |
4.511 | 0.000 | tNET | RR | 2 | u_b2p_inst/u_mid_fifo/n403_s0/CIN |
4.561 | 0.050 | tINS | RR | 1 | u_b2p_inst/u_mid_fifo/n403_s0/COUT |
4.561 | 0.000 | tNET | RR | 2 | u_b2p_inst/u_mid_fifo/n404_s0/CIN |
4.611 | 0.050 | tINS | RR | 1 | u_b2p_inst/u_mid_fifo/n404_s0/COUT |
5.024 | 0.413 | tNET | RR | 1 | u_b2p_inst/u_mid_fifo/n418_s3/I0 |
5.603 | 0.579 | tINS | RR | 1 | u_b2p_inst/u_mid_fifo/n418_s3/F |
6.015 | 0.413 | tNET | RR | 1 | u_b2p_inst/u_mid_fifo/n418_s0/I2 |
6.523 | 0.507 | tINS | RR | 1 | u_b2p_inst/u_mid_fifo/n418_s0/F |
6.935 | 0.413 | tNET | RR | 1 | u_b2p_inst/u_mid_fifo/rFull_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | I_BYTE_CLK | |||
10.000 | 0.000 | tCL | RR | 1 | I_BYTE_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 162 | I_BYTE_CLK_ibuf/O |
11.095 | 0.413 | tNET | RR | 1 | u_b2p_inst/u_mid_fifo/rFull_s0/CLK |
11.031 | -0.064 | tSu | 1 | u_b2p_inst/u_mid_fifo/rFull_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 7 |
Arrival Clock Path Delay: | cell: 0.683, 62.329%; route: 0.413, 37.671% |
Arrival Data Path Delay: | cell: 2.982, 51.070%; route: 2.475, 42.380%; tC2Q: 0.382, 6.550% |
Required Clock Path Delay: | cell: 0.683, 62.329%; route: 0.413, 37.671% |
Path 2
Path Summary:Slack | 5.143 |
Data Arrival Time | 5.641 |
Data Required Time | 10.784 |
From | u_b2p_inst/wc_cnt_dec_9_s1 |
To | u_b2p_inst/mid_offset_0_s1 |
Launch Clk | I_BYTE_CLK[R] |
Latch Clk | I_BYTE_CLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | I_BYTE_CLK | |||
0.000 | 0.000 | tCL | RR | 1 | I_BYTE_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 162 | I_BYTE_CLK_ibuf/O |
1.095 | 0.413 | tNET | RR | 1 | u_b2p_inst/wc_cnt_dec_9_s1/CLK |
1.477 | 0.382 | tC2Q | RR | 4 | u_b2p_inst/wc_cnt_dec_9_s1/Q |
1.890 | 0.413 | tNET | RR | 1 | u_b2p_inst/n1149_s3/I0 |
2.469 | 0.579 | tINS | RR | 3 | u_b2p_inst/n1149_s3/F |
2.881 | 0.413 | tNET | RR | 1 | u_b2p_inst/mid_offset_3_s5/I2 |
3.389 | 0.507 | tINS | RR | 1 | u_b2p_inst/mid_offset_3_s5/F |
3.801 | 0.413 | tNET | RR | 1 | u_b2p_inst/mid_offset_3_s4/I2 |
4.309 | 0.507 | tINS | RR | 2 | u_b2p_inst/mid_offset_3_s4/F |
4.721 | 0.413 | tNET | RR | 1 | u_b2p_inst/mid_offset_1_s4/I2 |
5.229 | 0.507 | tINS | RR | 2 | u_b2p_inst/mid_offset_1_s4/F |
5.641 | 0.413 | tNET | RR | 1 | u_b2p_inst/mid_offset_0_s1/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | I_BYTE_CLK | |||
10.000 | 0.000 | tCL | RR | 1 | I_BYTE_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 162 | I_BYTE_CLK_ibuf/O |
11.095 | 0.413 | tNET | RR | 1 | u_b2p_inst/mid_offset_0_s1/CLK |
10.784 | -0.311 | tSu | 1 | u_b2p_inst/mid_offset_0_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.683, 62.329%; route: 0.413, 37.671% |
Arrival Data Path Delay: | cell: 2.101, 46.219%; route: 2.063, 45.367%; tC2Q: 0.382, 8.414% |
Required Clock Path Delay: | cell: 0.683, 62.329%; route: 0.413, 37.671% |
Path 3
Path Summary:Slack | 5.143 |
Data Arrival Time | 5.641 |
Data Required Time | 10.784 |
From | u_b2p_inst/wc_cnt_dec_9_s1 |
To | u_b2p_inst/mid_offset_1_s1 |
Launch Clk | I_BYTE_CLK[R] |
Latch Clk | I_BYTE_CLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | I_BYTE_CLK | |||
0.000 | 0.000 | tCL | RR | 1 | I_BYTE_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 162 | I_BYTE_CLK_ibuf/O |
1.095 | 0.413 | tNET | RR | 1 | u_b2p_inst/wc_cnt_dec_9_s1/CLK |
1.477 | 0.382 | tC2Q | RR | 4 | u_b2p_inst/wc_cnt_dec_9_s1/Q |
1.890 | 0.413 | tNET | RR | 1 | u_b2p_inst/n1149_s3/I0 |
2.469 | 0.579 | tINS | RR | 3 | u_b2p_inst/n1149_s3/F |
2.881 | 0.413 | tNET | RR | 1 | u_b2p_inst/mid_offset_3_s5/I2 |
3.389 | 0.507 | tINS | RR | 1 | u_b2p_inst/mid_offset_3_s5/F |
3.801 | 0.413 | tNET | RR | 1 | u_b2p_inst/mid_offset_3_s4/I2 |
4.309 | 0.507 | tINS | RR | 2 | u_b2p_inst/mid_offset_3_s4/F |
4.721 | 0.413 | tNET | RR | 1 | u_b2p_inst/mid_offset_1_s4/I2 |
5.229 | 0.507 | tINS | RR | 2 | u_b2p_inst/mid_offset_1_s4/F |
5.641 | 0.413 | tNET | RR | 1 | u_b2p_inst/mid_offset_1_s1/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | I_BYTE_CLK | |||
10.000 | 0.000 | tCL | RR | 1 | I_BYTE_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 162 | I_BYTE_CLK_ibuf/O |
11.095 | 0.413 | tNET | RR | 1 | u_b2p_inst/mid_offset_1_s1/CLK |
10.784 | -0.311 | tSu | 1 | u_b2p_inst/mid_offset_1_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.683, 62.329%; route: 0.413, 37.671% |
Arrival Data Path Delay: | cell: 2.101, 46.219%; route: 2.063, 45.367%; tC2Q: 0.382, 8.414% |
Required Clock Path Delay: | cell: 0.683, 62.329%; route: 0.413, 37.671% |
Path 4
Path Summary:Slack | 5.143 |
Data Arrival Time | 5.641 |
Data Required Time | 10.784 |
From | u_b2p_inst/wc_cnt_dec_9_s1 |
To | u_b2p_inst/mid_offset_3_s1 |
Launch Clk | I_BYTE_CLK[R] |
Latch Clk | I_BYTE_CLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | I_BYTE_CLK | |||
0.000 | 0.000 | tCL | RR | 1 | I_BYTE_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 162 | I_BYTE_CLK_ibuf/O |
1.095 | 0.413 | tNET | RR | 1 | u_b2p_inst/wc_cnt_dec_9_s1/CLK |
1.477 | 0.382 | tC2Q | RR | 4 | u_b2p_inst/wc_cnt_dec_9_s1/Q |
1.890 | 0.413 | tNET | RR | 1 | u_b2p_inst/n1149_s3/I0 |
2.469 | 0.579 | tINS | RR | 3 | u_b2p_inst/n1149_s3/F |
2.881 | 0.413 | tNET | RR | 1 | u_b2p_inst/mid_offset_3_s5/I2 |
3.389 | 0.507 | tINS | RR | 1 | u_b2p_inst/mid_offset_3_s5/F |
3.801 | 0.413 | tNET | RR | 1 | u_b2p_inst/mid_offset_3_s4/I2 |
4.309 | 0.507 | tINS | RR | 2 | u_b2p_inst/mid_offset_3_s4/F |
4.721 | 0.413 | tNET | RR | 1 | u_b2p_inst/mid_offset_3_s7/I2 |
5.229 | 0.507 | tINS | RR | 1 | u_b2p_inst/mid_offset_3_s7/F |
5.641 | 0.413 | tNET | RR | 1 | u_b2p_inst/mid_offset_3_s1/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | I_BYTE_CLK | |||
10.000 | 0.000 | tCL | RR | 1 | I_BYTE_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 162 | I_BYTE_CLK_ibuf/O |
11.095 | 0.413 | tNET | RR | 1 | u_b2p_inst/mid_offset_3_s1/CLK |
10.784 | -0.311 | tSu | 1 | u_b2p_inst/mid_offset_3_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.683, 62.329%; route: 0.413, 37.671% |
Arrival Data Path Delay: | cell: 2.101, 46.219%; route: 2.063, 45.367%; tC2Q: 0.382, 8.414% |
Required Clock Path Delay: | cell: 0.683, 62.329%; route: 0.413, 37.671% |
Path 5
Path Summary:Slack | 5.188 |
Data Arrival Time | 5.844 |
Data Required Time | 11.031 |
From | u_b2p_inst/wc_cnt_dec_1_s3 |
To | u_b2p_inst/wc_cnt_dec_15_s1 |
Launch Clk | I_BYTE_CLK[R] |
Latch Clk | I_BYTE_CLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | I_BYTE_CLK | |||
0.000 | 0.000 | tCL | RR | 1 | I_BYTE_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 162 | I_BYTE_CLK_ibuf/O |
1.095 | 0.413 | tNET | RR | 1 | u_b2p_inst/wc_cnt_dec_1_s3/CLK |
1.477 | 0.382 | tC2Q | RR | 6 | u_b2p_inst/wc_cnt_dec_1_s3/Q |
1.890 | 0.413 | tNET | RR | 1 | u_b2p_inst/n1157_s1/I0 |
2.469 | 0.579 | tINS | RR | 8 | u_b2p_inst/n1157_s1/F |
2.881 | 0.413 | tNET | RR | 1 | u_b2p_inst/n1149_s1/I1 |
3.449 | 0.567 | tINS | RR | 3 | u_b2p_inst/n1149_s1/F |
3.861 | 0.413 | tNET | RR | 1 | u_b2p_inst/n1147_s3/I0 |
4.440 | 0.579 | tINS | RR | 1 | u_b2p_inst/n1147_s3/F |
4.852 | 0.413 | tNET | RR | 1 | u_b2p_inst/n1147_s0/I0 |
5.431 | 0.579 | tINS | RR | 1 | u_b2p_inst/n1147_s0/F |
5.844 | 0.413 | tNET | RR | 1 | u_b2p_inst/wc_cnt_dec_15_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | I_BYTE_CLK | |||
10.000 | 0.000 | tCL | RR | 1 | I_BYTE_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 162 | I_BYTE_CLK_ibuf/O |
11.095 | 0.413 | tNET | RR | 1 | u_b2p_inst/wc_cnt_dec_15_s1/CLK |
11.031 | -0.064 | tSu | 1 | u_b2p_inst/wc_cnt_dec_15_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.683, 62.329%; route: 0.413, 37.671% |
Arrival Data Path Delay: | cell: 2.304, 48.513%; route: 2.063, 43.432%; tC2Q: 0.382, 8.055% |
Required Clock Path Delay: | cell: 0.683, 62.329%; route: 0.413, 37.671% |