Report Title |
Power Analysis Report |
Design File |
F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\DSI_to_LVDS_2a18\fpga_proj\impl\gwsynthesis\dsi_to_lvds.vg |
Physical Constraints File |
F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\DSI_to_LVDS_2a18\fpga_proj\src\DK_START_Gw2A18_V2.cst |
Timing Constraints File |
F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\DSI_to_LVDS_2a18\fpga_proj\src\dsi_to_lvds_osc.sdc |
Tool Version |
V1.9.9.01 (64-bit) |
Part Number |
GW2A-LV18PG256C8/I7 |
Device |
GW2A-18 |
Device Version |
C |
Created Time |
Wed Mar 6 18:46:36 2024
|
Legal Announcement |
Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved. |
Total Power (mW) |
428.409 |
Quiescent Power (mW) |
92.094 |
Dynamic Power (mW) |
336.316 |
Junction Temperature |
38.718 |
Theta JA |
32.020 |
Max Allowed Ambient Temperature |
71.282 |
Default IO Toggle Rate |
0.125 |
Default Remain Toggle Rate |
0.125 |
Use Vectorless Estimation |
false |
Filter Glitches |
false |
Related Vcd File |
|
Related Saif File |
|
Use Custom Theta JA |
false |
Air Flow |
LFM_0 |
Heat Sink |
None |
Use Custom Theta SA |
false |
Board Thermal Model |
None |
Use Custom Theta JB |
false |
Ambient Temperature |
25.000
|
Voltage Source |
Voltage |
Dynamic Current(mA) |
Quiescent Current(mA) |
Power(mW) |
VCC |
1.000 |
296.649 |
61.518 |
358.167 |
VCCX |
2.500 |
2.408 |
11.364 |
34.429 |
VCCIO12 |
1.200 |
0.138 |
0.214 |
0.423 |
VCCIO25 |
2.500 |
13.393 |
0.764 |
35.391 |
Block Type |
Total Power(mW) |
Static Power(mW) |
Average Toggle Rate(millions of transitions/sec) |
Logic |
2.604 |
NA |
14.208 |
IO |
45.733
| 3.341
| 38.095
|
BSRAM |
225.286
| NA |
NA |
PLL |
65.899
| NA |
NA |
Hierarchy Entity |
Total Power(mW) |
Block Dynamic Power(mW) |
Dsi2Lvds_Top |
293.789 |
293.789(293.767) |
Dsi2Lvds_Top/u_b2p/ |
0.797 |
0.797(0.797) |
Dsi2Lvds_Top/u_b2p/u_b2p_inst/ |
0.797 |
0.797(0.472) |
Dsi2Lvds_Top/u_b2p/u_b2p_inst/u_align_forward/ |
0.048 |
0.048(0.000) |
Dsi2Lvds_Top/u_b2p/u_b2p_inst/u_dsi_sync_detec/ |
0.052 |
0.052(0.000) |
Dsi2Lvds_Top/u_b2p/u_b2p_inst/u_hs_adj/ |
0.093 |
0.093(0.000) |
Dsi2Lvds_Top/u_b2p/u_b2p_inst/u_mid_fifo/ |
0.281 |
0.281(0.105) |
Dsi2Lvds_Top/u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/ |
0.105 |
0.105(0.000) |
Dsi2Lvds_Top/u_dsi_rx/ |
0.439 |
0.439(0.439) |
Dsi2Lvds_Top/u_dsi_rx/u_dsi_csi2/ |
0.439 |
0.439(0.000) |
Dsi2Lvds_Top/u_extr/ |
225.887 |
225.887(0.000) |
Dsi2Lvds_Top/u_lvds_tx_left/ |
0.001 |
0.001(0.001) |
Dsi2Lvds_Top/u_lvds_tx_left/LVDS_71_Tx/ |
0.001 |
0.001(0.000) |
Dsi2Lvds_Top/u_mipi_dphy/ |
0.744 |
0.744(0.744) |
Dsi2Lvds_Top/u_mipi_dphy/DPHY_RX_INST/ |
0.744 |
0.744(0.744) |
Dsi2Lvds_Top/u_mipi_dphy/DPHY_RX_INST/u_Aligner/ |
0.740 |
0.740(0.740) |
Dsi2Lvds_Top/u_mipi_dphy/DPHY_RX_INST/u_Aligner/ln0/ |
0.247 |
0.247(0.000) |
Dsi2Lvds_Top/u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd0/ |
0.124 |
0.124(0.000) |
Dsi2Lvds_Top/u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd1/ |
0.121 |
0.121(0.000) |
Dsi2Lvds_Top/u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd2/ |
0.125 |
0.125(0.000) |
Dsi2Lvds_Top/u_mipi_dphy/DPHY_RX_INST/u_Aligner/wd3/ |
0.124 |
0.124(0.000) |
Dsi2Lvds_Top/u_mipi_dphy/DPHY_RX_INST/u_idesx8/ |
0.003 |
0.003(0.000) |
Dsi2Lvds_Top/u_pll_1/ |
14.644 |
14.644(0.000) |
Dsi2Lvds_Top/u_pll_2/ |
51.255 |
51.255(0.000) |
Clock Domain |
Clock Frequency(Mhz) |
Total Dynamic Power(mW) |
byte_clk |
104.998 |
16.290 |
pixel_clk |
139.997 |
113.421 |
lvds_pclk |
140.000 |
112.915 |
NO CLOCK DOMAIN |
0.000 |
0.000 |
mipi_clk |
83.333 |
0.009 |
u_pll_2/rpll_inst/CLKOUT.default_gen_clk |
490.000 |
0.033 |
clk_50 |
50.000 |
51.255 |