Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | D:\Programs\Gowin\Gowin_V1.9.9Beta-4\IDE\ipcore\MIPI_RX_Advance\data\DPHY_RX.vp D:\Programs\Gowin\Gowin_V1.9.9Beta-4\IDE\ipcore\MIPI_RX_Advance\data\DPHY_RX_TOP.v |
GowinSynthesis Constraints File | --- |
Version | V1.9.9 Beta-4 |
Part Number | GW2A-LV18QN88A6 |
Device | GW2A-18 |
Device Version | C |
Created Time | Tue Sep 26 17:17:29 2023 |
Legal Announcement | Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | MIPI_RX_PHY |
Synthesis Process | Running parser: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.188s, Peak memory usage = 36.988MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 36.988MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 36.988MB Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 36.988MB Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 36.988MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 36.988MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 36.988MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 36.988MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 36.988MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.017s, Peak memory usage = 36.988MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 36.988MB Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 36.988MB Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 51.551MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.052s, Peak memory usage = 51.551MB Generate output files: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.1s, Peak memory usage = 51.551MB |
Total Time and Memory Usage | CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 51.551MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 80 |
I/O Buf | 73 |
    IBUF | 2 |
    OBUF | 66 |
    TLVDS_IBUF | 5 |
Register | 473 |
    DFFPE | 1 |
    DFFC | 425 |
    DFFCE | 47 |
LUT | 466 |
    LUT2 | 27 |
    LUT3 | 56 |
    LUT4 | 383 |
INV | 1 |
    INV | 1 |
IOLOGIC | 8 |
    IDES8 | 4 |
    IODELAY | 4 |
CLOCK | 2 |
    CLKDIV | 1 |
    DHCEN | 1 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 467(467 LUT, 0 ALU) / 20736 | 3% |
Register | 473 / 15750 | 4% |
  --Register as Latch | 0 / 15750 | 0% |
  --Register as FF | 473 / 15750 | 4% |
BSRAM | 0 / 46 | 0% |
Timing
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|
HS_CLK_P | Base | 10.000 | 100.0 | 0.000 | 5.000 | DPHY_RX_INST/U0_IB/I | ||
DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT.default_gen_clk | Generated | 40.000 | 25.0 | 0.000 | 20.000 | DPHY_RX_INST/U0_IB/I | HS_CLK_P | DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
Max Frequency Summary:
No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | HS_CLK_P | 100.0(MHz) | 389.7(MHz) | 2 | TOP |
2 | DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT.default_gen_clk | 25.0(MHz) | 347.2(MHz) | 4 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | 3.717 |
Data Arrival Time | 2.021 |
Data Required Time | 5.739 |
From | DPHY_RX_INST/u_idesx8/opensync_1_s0 |
To | DPHY_RX_INST/u_idesx8/u_DHCEN |
Launch Clk | HS_CLK_P[F] |
Latch Clk | HS_CLK_P[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | HS_CLK_P | |||
0.000 | 0.000 | tCL | RR | 1 | DPHY_RX_INST/U0_IB/I |
0.683 | 0.683 | tINS | RR | 5 | DPHY_RX_INST/U0_IB/O |
0.863 | 0.180 | tNET | RR | 1 | DPHY_RX_INST/u_idesx8/opensync_1_s0/CLK |
1.095 | 0.232 | tC2Q | RF | 2 | DPHY_RX_INST/u_idesx8/opensync_1_s0/Q |
1.332 | 0.237 | tNET | FF | 1 | DPHY_RX_INST/u_idesx8/LUT4_0/I2 |
1.785 | 0.453 | tINS | FF | 1 | DPHY_RX_INST/u_idesx8/LUT4_0/F |
2.022 | 0.237 | tNET | FF | 1 | DPHY_RX_INST/u_idesx8/u_DHCEN/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
5.000 | 0.000 | HS_CLK_P | |||
5.000 | 0.000 | tCL | FF | 1 | DPHY_RX_INST/U0_IB/I |
5.688 | 0.688 | tINS | FF | 5 | DPHY_RX_INST/U0_IB/O |
5.924 | 0.237 | tNET | FF | 3 | DPHY_RX_INST/u_idesx8/u_DHCEN/CLKIN |
5.739 | -0.186 | tSu | 1 | DPHY_RX_INST/u_idesx8/u_DHCEN |
Clock Skew: | 0.062 |
Setup Relationship: | 5.000 |
Logic Level: | 2 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 0.453, 39.085%; route: 0.474, 40.898%; tC2Q: 0.232, 20.017% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 2
Path Summary:Slack | 8.854 |
Data Arrival Time | 1.974 |
Data Required Time | 10.828 |
From | DPHY_RX_INST/u_idesx8/opensync_3_s0 |
To | DPHY_RX_INST/u_idesx8/opensync_0_s0 |
Launch Clk | HS_CLK_P[R] |
Latch Clk | HS_CLK_P[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | HS_CLK_P | |||
0.000 | 0.000 | tCL | RR | 1 | DPHY_RX_INST/U0_IB/I |
0.683 | 0.683 | tINS | RR | 5 | DPHY_RX_INST/U0_IB/O |
0.863 | 0.180 | tNET | RR | 1 | DPHY_RX_INST/u_idesx8/opensync_3_s0/CLK |
1.095 | 0.232 | tC2Q | RF | 2 | DPHY_RX_INST/u_idesx8/opensync_3_s0/Q |
1.332 | 0.237 | tNET | FF | 1 | DPHY_RX_INST/u_idesx8/LUT4_1/I2 |
1.794 | 0.462 | tINS | FR | 4 | DPHY_RX_INST/u_idesx8/LUT4_1/F |
1.974 | 0.180 | tNET | RR | 1 | DPHY_RX_INST/u_idesx8/opensync_0_s0/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | HS_CLK_P | |||
10.000 | 0.000 | tCL | RR | 1 | DPHY_RX_INST/U0_IB/I |
10.682 | 0.683 | tINS | RR | 5 | DPHY_RX_INST/U0_IB/O |
10.863 | 0.180 | tNET | RR | 1 | DPHY_RX_INST/u_idesx8/opensync_0_s0/CLK |
10.828 | -0.035 | tSu | 1 | DPHY_RX_INST/u_idesx8/opensync_0_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 2 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 0.462, 41.584%; route: 0.417, 37.534%; tC2Q: 0.232, 20.882% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 3
Path Summary:Slack | 8.854 |
Data Arrival Time | 1.974 |
Data Required Time | 10.828 |
From | DPHY_RX_INST/u_idesx8/opensync_3_s0 |
To | DPHY_RX_INST/u_idesx8/opensync_3_s0 |
Launch Clk | HS_CLK_P[R] |
Latch Clk | HS_CLK_P[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | HS_CLK_P | |||
0.000 | 0.000 | tCL | RR | 1 | DPHY_RX_INST/U0_IB/I |
0.683 | 0.683 | tINS | RR | 5 | DPHY_RX_INST/U0_IB/O |
0.863 | 0.180 | tNET | RR | 1 | DPHY_RX_INST/u_idesx8/opensync_3_s0/CLK |
1.095 | 0.232 | tC2Q | RF | 2 | DPHY_RX_INST/u_idesx8/opensync_3_s0/Q |
1.332 | 0.237 | tNET | FF | 1 | DPHY_RX_INST/u_idesx8/LUT4_1/I2 |
1.794 | 0.462 | tINS | FR | 4 | DPHY_RX_INST/u_idesx8/LUT4_1/F |
1.974 | 0.180 | tNET | RR | 1 | DPHY_RX_INST/u_idesx8/opensync_3_s0/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | HS_CLK_P | |||
10.000 | 0.000 | tCL | RR | 1 | DPHY_RX_INST/U0_IB/I |
10.682 | 0.683 | tINS | RR | 5 | DPHY_RX_INST/U0_IB/O |
10.863 | 0.180 | tNET | RR | 1 | DPHY_RX_INST/u_idesx8/opensync_3_s0/CLK |
10.828 | -0.035 | tSu | 1 | DPHY_RX_INST/u_idesx8/opensync_3_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 2 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 0.462, 41.584%; route: 0.417, 37.534%; tC2Q: 0.232, 20.882% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 4
Path Summary:Slack | 8.854 |
Data Arrival Time | 1.974 |
Data Required Time | 10.828 |
From | DPHY_RX_INST/u_idesx8/opensync_3_s0 |
To | DPHY_RX_INST/u_idesx8/opensync_1_s0 |
Launch Clk | HS_CLK_P[R] |
Latch Clk | HS_CLK_P[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | HS_CLK_P | |||
0.000 | 0.000 | tCL | RR | 1 | DPHY_RX_INST/U0_IB/I |
0.683 | 0.683 | tINS | RR | 5 | DPHY_RX_INST/U0_IB/O |
0.863 | 0.180 | tNET | RR | 1 | DPHY_RX_INST/u_idesx8/opensync_3_s0/CLK |
1.095 | 0.232 | tC2Q | RF | 2 | DPHY_RX_INST/u_idesx8/opensync_3_s0/Q |
1.332 | 0.237 | tNET | FF | 1 | DPHY_RX_INST/u_idesx8/LUT4_1/I2 |
1.794 | 0.462 | tINS | FR | 4 | DPHY_RX_INST/u_idesx8/LUT4_1/F |
1.974 | 0.180 | tNET | RR | 1 | DPHY_RX_INST/u_idesx8/opensync_1_s0/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | HS_CLK_P | |||
10.000 | 0.000 | tCL | RR | 1 | DPHY_RX_INST/U0_IB/I |
10.682 | 0.683 | tINS | RR | 5 | DPHY_RX_INST/U0_IB/O |
10.863 | 0.180 | tNET | RR | 1 | DPHY_RX_INST/u_idesx8/opensync_1_s0/CLK |
10.828 | -0.035 | tSu | 1 | DPHY_RX_INST/u_idesx8/opensync_1_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 2 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 0.462, 41.584%; route: 0.417, 37.534%; tC2Q: 0.232, 20.882% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 5
Path Summary:Slack | 8.854 |
Data Arrival Time | 1.974 |
Data Required Time | 10.828 |
From | DPHY_RX_INST/u_idesx8/opensync_3_s0 |
To | DPHY_RX_INST/u_idesx8/opensync_2_s0 |
Launch Clk | HS_CLK_P[R] |
Latch Clk | HS_CLK_P[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | HS_CLK_P | |||
0.000 | 0.000 | tCL | RR | 1 | DPHY_RX_INST/U0_IB/I |
0.683 | 0.683 | tINS | RR | 5 | DPHY_RX_INST/U0_IB/O |
0.863 | 0.180 | tNET | RR | 1 | DPHY_RX_INST/u_idesx8/opensync_3_s0/CLK |
1.095 | 0.232 | tC2Q | RF | 2 | DPHY_RX_INST/u_idesx8/opensync_3_s0/Q |
1.332 | 0.237 | tNET | FF | 1 | DPHY_RX_INST/u_idesx8/LUT4_1/I2 |
1.794 | 0.462 | tINS | FR | 4 | DPHY_RX_INST/u_idesx8/LUT4_1/F |
1.974 | 0.180 | tNET | RR | 1 | DPHY_RX_INST/u_idesx8/opensync_2_s0/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | HS_CLK_P | |||
10.000 | 0.000 | tCL | RR | 1 | DPHY_RX_INST/U0_IB/I |
10.682 | 0.683 | tINS | RR | 5 | DPHY_RX_INST/U0_IB/O |
10.863 | 0.180 | tNET | RR | 1 | DPHY_RX_INST/u_idesx8/opensync_2_s0/CLK |
10.828 | -0.035 | tSu | 1 | DPHY_RX_INST/u_idesx8/opensync_2_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 2 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 0.462, 41.584%; route: 0.417, 37.534%; tC2Q: 0.232, 20.882% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |