Timing Messages
Report Title | Timing Analysis Report |
Design File | F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\DSI_to_LVDS_5a138\fpga_proj\impl\gwsynthesis\DSI_to_LVDS_5a138.vg |
Physical Constraints File | F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\DSI_to_LVDS_5a138\fpga_proj\src\dsI_to_lvds.cst |
Timing Constraint File | F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\DSI_to_LVDS_5a138\fpga_proj\src\dsi_to_lvds_osc.sdc |
Tool Version | V1.9.9.01 (64-bit) |
Part Number | GW5AST-LV138FPG676AC1/I0 |
Device | GW5AST-138 |
Device Version | B |
Created Time | Wed Mar 6 18:52:07 2024 |
Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved. |
Timing Summaries
STA Tool Run Summary:
Setup Delay Model | Slow 0.855V 0C C1/I0 |
Hold Delay Model | Fast 0.945V 85C C1/I0 |
Numbers of Paths Analyzed | 4780 |
Numbers of Endpoints Analyzed | 4481 |
Numbers of Falling Endpoints | 3 |
Numbers of Setup Violated Endpoints | 0 |
Numbers of Hold Violated Endpoints | 0 |
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Objects |
---|---|---|---|---|---|---|---|---|
clk_50 | Base | 20.000 | 50.000 | 0.000 | 10.000 | OSC_50M | ||
byte_clk | Base | 9.524 | 104.998 | 0.000 | 4.762 | byte_clk | ||
pixel_clk | Generated | 7.143 | 139.997 | 0.000 | 3.572 | byte_clk | byte_clk | pixel_clk |
lvds_pclk | Generated | 7.368 | 135.714 | 0.000 | 3.684 | OSC_50M | clk_50 | lvds_pclk |
tck_pad_i | Base | 50.000 | 20.000 | 0.000 | 25.000 | gw_gao_inst_0/tck_ibuf/I | ||
u_pll_50m/PLL_inst/CLKOUT0.default_gen_clk | Generated | 2.105 | 475.000 | 0.000 | 1.053 | OSC_50M_ibuf/I | clk_50 | u_pll_50m/PLL_inst/CLKOUT0 |
Max Frequency Summary:
NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | byte_clk | 104.998(MHz) | 107.260(MHz) | 2 | TOP |
2 | pixel_clk | 139.997(MHz) | 163.465(MHz) | 5 | TOP |
3 | lvds_pclk | 135.714(MHz) | 143.318(MHz) | 6 | TOP |
4 | tck_pad_i | 20.000(MHz) | 125.855(MHz) | 6 | TOP |
No timing paths to get frequency of clk_50!
No timing paths to get frequency of u_pll_50m/PLL_inst/CLKOUT0.default_gen_clk!
Total Negative Slack Summary:
Clock Name | Analysis Type | Endpoints TNS | Number of Endpoints |
---|---|---|---|
clk_50 | Setup | 0.000 | 0 |
clk_50 | Hold | 0.000 | 0 |
byte_clk | Setup | 0.000 | 0 |
byte_clk | Hold | 0.000 | 0 |
pixel_clk | Setup | 0.000 | 0 |
pixel_clk | Hold | 0.000 | 0 |
lvds_pclk | Setup | 0.000 | 0 |
lvds_pclk | Hold | 0.000 | 0 |
tck_pad_i | Setup | 0.000 | 0 |
tck_pad_i | Hold | 0.000 | 0 |
u_pll_50m/PLL_inst/CLKOUT0.default_gen_clk | Setup | 0.000 | 0 |
u_pll_50m/PLL_inst/CLKOUT0.default_gen_clk | Hold | 0.000 | 0 |
Timing Details
Path Slacks Table:
Setup Paths Table
Setup Paths Table[1]:
Report Command:report_timing -setup -from_clock [get_clocks {pixel_clk}] -max_paths 20 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 1.025 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/D | pixel_clk:[R] | pixel_clk:[R] | 7.143 | 0.004 | 6.050 |
2 | 1.136 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/D | pixel_clk:[R] | pixel_clk:[R] | 7.143 | 0.013 | 5.930 |
3 | 1.647 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/D | pixel_clk:[R] | pixel_clk:[R] | 7.143 | 0.000 | 5.433 |
4 | 1.647 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/D | pixel_clk:[R] | pixel_clk:[R] | 7.143 | 0.000 | 5.433 |
5 | 1.747 | u_b2p/u_b2p_inst/u_hs_adj/rQout_s1/Q | u_extr/pixel_cnt_1_s0/RESET | pixel_clk:[R] | pixel_clk:[R] | 7.143 | 0.106 | 4.918 |
6 | 1.747 | u_b2p/u_b2p_inst/u_hs_adj/rQout_s1/Q | u_extr/pixel_cnt_2_s0/RESET | pixel_clk:[R] | pixel_clk:[R] | 7.143 | 0.106 | 4.918 |
7 | 1.747 | u_b2p/u_b2p_inst/u_hs_adj/rQout_s1/Q | u_extr/pixel_cnt_3_s0/RESET | pixel_clk:[R] | pixel_clk:[R] | 7.143 | 0.106 | 4.918 |
8 | 1.747 | u_b2p/u_b2p_inst/u_hs_adj/rQout_s1/Q | u_extr/pixel_cnt_4_s0/RESET | pixel_clk:[R] | pixel_clk:[R] | 7.143 | 0.106 | 4.918 |
9 | 1.747 | u_b2p/u_b2p_inst/u_hs_adj/rQout_s1/Q | u_extr/pixel_cnt_5_s0/RESET | pixel_clk:[R] | pixel_clk:[R] | 7.143 | 0.106 | 4.918 |
10 | 1.747 | u_b2p/u_b2p_inst/u_hs_adj/rQout_s1/Q | u_extr/pixel_cnt_6_s0/RESET | pixel_clk:[R] | pixel_clk:[R] | 7.143 | 0.106 | 4.918 |
11 | 1.881 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/D | pixel_clk:[R] | pixel_clk:[R] | 7.143 | 0.009 | 5.189 |
12 | 1.881 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/D | pixel_clk:[R] | pixel_clk:[R] | 7.143 | 0.009 | 5.189 |
13 | 1.967 | gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/Q | gw_gao_inst_0/u_la0_top/start_reg_s0/D | pixel_clk:[R] | pixel_clk:[R] | 7.143 | -0.017 | 5.129 |
14 | 2.088 | u_b2p/u_b2p_inst/u_hs_adj/rQout_s1/Q | u_extr/iact_line_s0/D | pixel_clk:[R] | pixel_clk:[R] | 7.143 | 0.092 | 4.899 |
15 | 2.100 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/D | pixel_clk:[R] | pixel_clk:[R] | 7.143 | 0.011 | 4.968 |
16 | 2.106 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/D | pixel_clk:[R] | pixel_clk:[R] | 7.143 | -0.016 | 4.989 |
17 | 2.112 | u_b2p/u_b2p_inst/u_hs_adj/rQout_s1/Q | u_extr/buf_wa_1_s0/RESET | pixel_clk:[R] | pixel_clk:[R] | 7.143 | 0.104 | 4.555 |
18 | 2.112 | u_b2p/u_b2p_inst/u_hs_adj/rQout_s1/Q | u_extr/buf_wa_2_s0/RESET | pixel_clk:[R] | pixel_clk:[R] | 7.143 | 0.104 | 4.555 |
19 | 2.112 | u_b2p/u_b2p_inst/u_hs_adj/rQout_s1/Q | u_extr/buf_wa_3_s0/RESET | pixel_clk:[R] | pixel_clk:[R] | 7.143 | 0.104 | 4.555 |
20 | 2.112 | u_b2p/u_b2p_inst/u_hs_adj/rQout_s1/Q | u_extr/buf_wa_4_s0/RESET | pixel_clk:[R] | pixel_clk:[R] | 7.143 | 0.104 | 4.555 |
Setup Paths Table[2]:
Report Command:report_timing -setup -from_clock [get_clocks {byte_clk}] -max_paths 20 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 0.201 | hsrx_en_msk_s0/Q | byte_ready_s0/D | byte_clk:[R] | byte_clk:[R] | 9.524 | 0.068 | 9.197 |
2 | 0.382 | u_dsi_rx/u_dsi_csi2/rData_3_s0/Q | u_dsi_rx/u_dsi_csi2/rHeader_7_s0/CE | byte_clk:[R] | byte_clk:[R] | 9.524 | 0.013 | 8.818 |
3 | 0.810 | u_dsi_rx/u_dsi_csi2/rData_3_s0/Q | u_dsi_rx/u_dsi_csi2/rHeader_13_s0/CE | byte_clk:[R] | byte_clk:[R] | 9.524 | 0.015 | 8.387 |
4 | 0.810 | u_dsi_rx/u_dsi_csi2/rData_3_s0/Q | u_dsi_rx/u_dsi_csi2/rHeader_14_s0/CE | byte_clk:[R] | byte_clk:[R] | 9.524 | 0.015 | 8.387 |
5 | 0.810 | u_dsi_rx/u_dsi_csi2/rData_3_s0/Q | u_dsi_rx/u_dsi_csi2/rHeader_17_s0/CE | byte_clk:[R] | byte_clk:[R] | 9.524 | 0.015 | 8.387 |
6 | 0.810 | u_dsi_rx/u_dsi_csi2/rData_3_s0/Q | u_dsi_rx/u_dsi_csi2/rHeader_20_s0/CE | byte_clk:[R] | byte_clk:[R] | 9.524 | 0.015 | 8.387 |
7 | 0.810 | u_dsi_rx/u_dsi_csi2/rData_3_s0/Q | u_dsi_rx/u_dsi_csi2/rHeader_22_s0/CE | byte_clk:[R] | byte_clk:[R] | 9.524 | 0.015 | 8.387 |
8 | 0.822 | u_dsi_rx/u_dsi_csi2/rData_3_s0/Q | u_dsi_rx/u_dsi_csi2/rHeader_18_s0/CE | byte_clk:[R] | byte_clk:[R] | 9.524 | 0.006 | 8.385 |
9 | 0.822 | u_dsi_rx/u_dsi_csi2/rData_3_s0/Q | u_dsi_rx/u_dsi_csi2/rHeader_19_s0/CE | byte_clk:[R] | byte_clk:[R] | 9.524 | 0.006 | 8.385 |
10 | 1.021 | u_dsi_rx/u_dsi_csi2/rData_3_s0/Q | u_dsi_rx/u_dsi_csi2/rHeader_21_s0/CE | byte_clk:[R] | byte_clk:[R] | 9.524 | 0.013 | 8.179 |
11 | 1.021 | u_dsi_rx/u_dsi_csi2/rData_3_s0/Q | u_dsi_rx/u_dsi_csi2/rHeader_23_s0/CE | byte_clk:[R] | byte_clk:[R] | 9.524 | 0.013 | 8.179 |
12 | 1.036 | u_dsi_rx/u_dsi_csi2/rData_3_s0/Q | u_dsi_rx/u_dsi_csi2/rHeader_6_s0/CE | byte_clk:[R] | byte_clk:[R] | 9.524 | 0.006 | 8.171 |
13 | 1.042 | u_dsi_rx/u_dsi_csi2/rData_3_s0/Q | u_dsi_rx/u_dsi_csi2/rHeader_27_s0/CE | byte_clk:[R] | byte_clk:[R] | 9.524 | -0.006 | 8.176 |
14 | 1.042 | u_dsi_rx/u_dsi_csi2/rData_3_s0/Q | u_dsi_rx/u_dsi_csi2/rHeader_29_s0/CE | byte_clk:[R] | byte_clk:[R] | 9.524 | -0.006 | 8.176 |
15 | 1.247 | u_dsi_rx/u_dsi_csi2/rData_3_s0/Q | u_dsi_rx/u_dsi_csi2/rHeader_24_s0/CE | byte_clk:[R] | byte_clk:[R] | 9.524 | 0.004 | 7.963 |
16 | 1.247 | u_dsi_rx/u_dsi_csi2/rData_3_s0/Q | u_dsi_rx/u_dsi_csi2/rHeader_26_s0/CE | byte_clk:[R] | byte_clk:[R] | 9.524 | 0.004 | 7.963 |
17 | 1.247 | u_dsi_rx/u_dsi_csi2/rData_3_s0/Q | u_dsi_rx/u_dsi_csi2/rHeader_28_s0/CE | byte_clk:[R] | byte_clk:[R] | 9.524 | 0.004 | 7.963 |
18 | 1.247 | u_dsi_rx/u_dsi_csi2/rData_3_s0/Q | u_dsi_rx/u_dsi_csi2/rHeader_31_s0/CE | byte_clk:[R] | byte_clk:[R] | 9.524 | 0.004 | 7.963 |
19 | 1.423 | u_dsi_rx/u_dsi_csi2/rData_3_s0/Q | u_dsi_rx/u_dsi_csi2/rHeader_11_s0/CE | byte_clk:[R] | byte_clk:[R] | 9.524 | 0.015 | 7.775 |
20 | 1.602 | u_dsi_rx/u_dsi_csi2/rData_3_s0/Q | u_dsi_rx/u_dsi_csi2/rHeader_25_s0/CE | byte_clk:[R] | byte_clk:[R] | 9.524 | -0.040 | 7.651 |
Setup Paths Table[3]:
Report Command:report_timing -setup -from_clock [get_clocks {lvds_pclk}] -max_paths 20 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 0.391 | u_extr/buf_ra_1_s0/Q | u_extr/mem_data_mem_data_0_1_s/ADB[10] | lvds_pclk:[R] | lvds_pclk:[R] | 7.368 | -0.002 | 6.945 |
2 | 0.394 | u_extr/buf_ra_1_s0/Q | u_extr/mem_data_mem_data_0_7_s/ADB[11] | lvds_pclk:[R] | lvds_pclk:[R] | 7.368 | 0.007 | 6.933 |
3 | 0.426 | u_extr/buf_ra_1_s0/Q | u_extr/mem_data_mem_data_0_2_s/ADB[5] | lvds_pclk:[R] | lvds_pclk:[R] | 7.368 | -0.002 | 6.910 |
4 | 0.582 | u_extr/buf_ra_1_s0/Q | u_extr/mem_data_mem_data_0_4_s/ADB[11] | lvds_pclk:[R] | lvds_pclk:[R] | 7.368 | -0.012 | 6.764 |
5 | 0.630 | u_extr/buf_ra_1_s0/Q | u_extr/mem_data_mem_data_0_0_s/ADB[11] | lvds_pclk:[R] | lvds_pclk:[R] | 7.368 | 0.007 | 6.696 |
6 | 0.710 | u_extr/buf_ra_1_s0/Q | u_extr/mem_data_mem_data_0_9_s/ADB[11] | lvds_pclk:[R] | lvds_pclk:[R] | 7.368 | -0.002 | 6.626 |
7 | 0.722 | u_extr/buf_ra_1_s0/Q | u_extr/mem_data_mem_data_0_11_s/ADB[11] | lvds_pclk:[R] | lvds_pclk:[R] | 7.368 | -0.012 | 6.624 |
8 | 0.725 | u_extr/buf_ra_1_s0/Q | u_extr/mem_data_mem_data_0_1_s/ADB[11] | lvds_pclk:[R] | lvds_pclk:[R] | 7.368 | -0.002 | 6.611 |
9 | 0.746 | u_extr/oworking_s0/Q | u_extr/mem_data_mem_data_0_9_s/ADB[4] | lvds_pclk:[R] | lvds_pclk:[R] | 7.368 | 0.034 | 6.554 |
10 | 0.750 | u_extr/buf_ra_1_s0/Q | u_extr/mem_data_mem_data_0_10_s/ADB[11] | lvds_pclk:[R] | lvds_pclk:[R] | 7.368 | -0.002 | 6.586 |
11 | 0.751 | u_extr/buf_ra_1_s0/Q | u_extr/mem_data_mem_data_0_6_s/ADB[5] | lvds_pclk:[R] | lvds_pclk:[R] | 7.368 | -0.002 | 6.585 |
12 | 0.778 | u_extr/buf_ra_1_s0/Q | u_extr/mem_data_mem_data_0_8_s/ADB[11] | lvds_pclk:[R] | lvds_pclk:[R] | 7.368 | 0.007 | 6.549 |
13 | 0.802 | u_extr/buf_ra_1_s0/Q | u_extr/mem_data_mem_data_0_2_s/ADB[11] | lvds_pclk:[R] | lvds_pclk:[R] | 7.368 | -0.002 | 6.534 |
14 | 0.860 | u_extr/buf_ra_1_s0/Q | u_extr/mem_data_mem_data_0_2_s/ADB[7] | lvds_pclk:[R] | lvds_pclk:[R] | 7.368 | -0.002 | 6.476 |
15 | 0.931 | u_extr/buf_ra_1_s0/Q | u_extr/mem_data_mem_data_0_5_s/ADB[11] | lvds_pclk:[R] | lvds_pclk:[R] | 7.368 | -0.002 | 6.405 |
16 | 0.931 | u_extr/o_rgb_reg_13_s0/Q | u_lvds_tx_left/LVDS_71_Tx/u_ODDR71_B1/D4 | lvds_pclk:[R] | lvds_pclk:[R] | 7.368 | 0.008 | 6.261 |
17 | 0.934 | u_extr/o_rgb_reg_12_s0/Q | u_lvds_tx_left/LVDS_71_Tx/u_ODDR71_B1/D5 | lvds_pclk:[R] | lvds_pclk:[R] | 7.368 | 0.008 | 6.261 |
18 | 0.946 | u_extr/buf_ra_1_s0/Q | u_extr/mem_data_mem_data_0_9_s/ADB[10] | lvds_pclk:[R] | lvds_pclk:[R] | 7.368 | -0.002 | 6.390 |
19 | 0.955 | u_extr/buf_ra_1_s0/Q | u_extr/mem_data_mem_data_0_2_s/ADB[10] | lvds_pclk:[R] | lvds_pclk:[R] | 7.368 | -0.002 | 6.381 |
20 | 0.955 | u_extr/ovcnt_1_s1/Q | u_extr/ohs_s0/D | lvds_pclk:[R] | lvds_pclk:[R] | 7.368 | 0.009 | 6.340 |
Hold Paths Table
Hold Paths Table[1]:
Report Command:report_timing -hold -from_clock [get_clocks {pixel_clk}] -max_paths 20 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 0.266 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_24_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[0] | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.030 | 0.485 |
2 | 0.268 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_10_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[2] | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.030 | 0.487 |
3 | 0.276 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_15_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[7] | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.040 | 0.485 |
4 | 0.276 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_14_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[6] | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.040 | 0.485 |
5 | 0.311 | u_extr/buf_wd_7_s0/Q | u_extr/mem_data_mem_data_0_3_s/DI[1] | pixel_clk:[R] | pixel_clk:[R] | 0.000 | -0.001 | 0.561 |
6 | 0.311 | u_extr/buf_wd_1_s0/Q | u_extr/mem_data_mem_data_0_0_s/DI[1] | pixel_clk:[R] | pixel_clk:[R] | 0.000 | -0.001 | 0.561 |
7 | 0.311 | u_extr/buf_wd_0_s0/Q | u_extr/mem_data_mem_data_0_0_s/DI[0] | pixel_clk:[R] | pixel_clk:[R] | 0.000 | -0.001 | 0.561 |
8 | 0.359 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_26_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[2] | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.030 | 0.579 |
9 | 0.359 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_25_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[1] | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.030 | 0.579 |
10 | 0.374 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/D | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.000 | 0.375 |
11 | 0.374 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_10_s1/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_10_s1/D | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.000 | 0.375 |
12 | 0.374 | gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/D | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.000 | 0.375 |
13 | 0.374 | gw_gao_inst_0/u_la0_top/capture_window_sel_10_s1/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_10_s1/D | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.000 | 0.375 |
14 | 0.374 | gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/Q | gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/D | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.000 | 0.375 |
15 | 0.374 | u_b2p/u_b2p_inst/u_hs_adj/rECnt_1_s1/Q | u_b2p/u_b2p_inst/u_hs_adj/rECnt_1_s1/D | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.000 | 0.375 |
16 | 0.374 | u_b2p/u_b2p_inst/u_hs_adj/rECnt_5_s1/Q | u_b2p/u_b2p_inst/u_hs_adj/rECnt_5_s1/D | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.000 | 0.375 |
17 | 0.374 | u_b2p/u_b2p_inst/u_hs_adj/rSCnt_5_s1/Q | u_b2p/u_b2p_inst/u_hs_adj/rSCnt_5_s1/D | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.000 | 0.375 |
18 | 0.375 | u_extr/buf_wd_5_s0/Q | u_extr/mem_data_mem_data_0_2_s/DI[1] | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.028 | 0.596 |
19 | 0.377 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/D | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.000 | 0.379 |
20 | 0.377 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/D | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.000 | 0.379 |
Hold Paths Table[2]:
Report Command:report_timing -hold -from_clock [get_clocks {byte_clk}] -max_paths 20 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 0.235 | u_b2p/u_b2p_inst/rBufD_11_s1/Q | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s/DI[11] | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.030 | 0.454 |
2 | 0.266 | u_b2p/u_b2p_inst/rBufD_3_s1/Q | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s/DI[3] | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.030 | 0.485 |
3 | 0.314 | u_b2p/u_b2p_inst/rBufD_6_s1/Q | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s/DI[6] | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.030 | 0.534 |
4 | 0.321 | u_b2p/u_b2p_inst/rBufD_44_s1/Q | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_1_s/DI[12] | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.030 | 0.540 |
5 | 0.355 | u_b2p/u_b2p_inst/rBufD_24_s1/Q | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s/DI[24] | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.030 | 0.574 |
6 | 0.374 | u_b2p/u_b2p_inst/u_mid_fifo/rWPtrGray_0_s1/Q | u_b2p/u_b2p_inst/u_mid_fifo/rWPtrGray_0_s1/D | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.375 |
7 | 0.374 | u_b2p/u_b2p_inst/u_dsi_sync_detec/rVSync_s0/Q | u_b2p/u_b2p_inst/u_dsi_sync_detec/rVSync_s0/D | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.375 |
8 | 0.374 | u_b2p/u_b2p_inst/wc_cnt_dec_3_s1/Q | u_b2p/u_b2p_inst/wc_cnt_dec_3_s1/D | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.375 |
9 | 0.374 | u_b2p/u_b2p_inst/wc_cnt_dec_7_s1/Q | u_b2p/u_b2p_inst/wc_cnt_dec_7_s1/D | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.375 |
10 | 0.374 | u_b2p/u_b2p_inst/wc_cnt_dec_9_s1/Q | u_b2p/u_b2p_inst/wc_cnt_dec_9_s1/D | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.375 |
11 | 0.374 | u_b2p/u_b2p_inst/wc_cnt_dec_11_s1/Q | u_b2p/u_b2p_inst/wc_cnt_dec_11_s1/D | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.375 |
12 | 0.374 | u_b2p/u_b2p_inst/wc_cnt_dec_13_s1/Q | u_b2p/u_b2p_inst/wc_cnt_dec_13_s1/D | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.375 |
13 | 0.374 | u_b2p/u_b2p_inst/wc_cnt_dec_15_s1/Q | u_b2p/u_b2p_inst/wc_cnt_dec_15_s1/D | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.375 |
14 | 0.374 | u_dsi_rx/u_dsi_csi2/rWcCntP_0_s3/Q | u_dsi_rx/u_dsi_csi2/rWcCntP_0_s3/D | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.375 |
15 | 0.374 | u_dsi_rx/u_dsi_csi2/rDSel_0_s3/Q | u_dsi_rx/u_dsi_csi2/rDSel_0_s3/D | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.375 |
16 | 0.374 | hsrx_cnt_0_s1/Q | hsrx_cnt_0_s1/D | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.375 |
17 | 0.374 | hsrx_cnt_1_s1/Q | hsrx_cnt_1_s1/D | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.375 |
18 | 0.375 | u_b2p/u_b2p_inst/rBufD_25_s1/Q | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s/DI[25] | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.027 | 0.596 |
19 | 0.378 | u_b2p/u_b2p_inst/wc_cnt_dec_1_s3/Q | u_b2p/u_b2p_inst/wc_cnt_dec_1_s3/D | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.379 |
20 | 0.378 | u_b2p/u_b2p_inst/wc_cnt_dec_5_s1/Q | u_b2p/u_b2p_inst/wc_cnt_dec_5_s1/D | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.379 |
Hold Paths Table[3]:
Report Command:report_timing -hold -from_clock [get_clocks {lvds_pclk}] -max_paths 20 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 0.204 | u_lvds_tx_left/LVDS_71_Tx/scuba_vhi_s0/Q | u_lvds_tx_left/LVDS_71_Tx/u_ODDR71_C/D6 | lvds_pclk:[R] | lvds_pclk:[R] | 0.000 | -0.004 | 0.304 |
2 | 0.204 | u_lvds_tx_left/LVDS_71_Tx/scuba_vhi_s0/Q | u_lvds_tx_left/LVDS_71_Tx/u_ODDR71_C/D0 | lvds_pclk:[R] | lvds_pclk:[R] | 0.000 | -0.004 | 0.304 |
3 | 0.219 | u_lvds_tx_left/LVDS_71_Tx/scuba_vhi_s0/Q | u_lvds_tx_left/LVDS_71_Tx/u_ODDR71_C/D5 | lvds_pclk:[R] | lvds_pclk:[R] | 0.000 | -0.004 | 0.306 |
4 | 0.219 | u_lvds_tx_left/LVDS_71_Tx/scuba_vhi_s0/Q | u_lvds_tx_left/LVDS_71_Tx/u_ODDR71_C/D1 | lvds_pclk:[R] | lvds_pclk:[R] | 0.000 | -0.004 | 0.306 |
5 | 0.374 | u_extr/buf_ra_12_s13/Q | u_extr/buf_ra_12_s13/D | lvds_pclk:[R] | lvds_pclk:[R] | 0.000 | 0.000 | 0.375 |
6 | 0.374 | u_extr/ovcnt_14_s1/Q | u_extr/ovcnt_14_s1/D | lvds_pclk:[R] | lvds_pclk:[R] | 0.000 | 0.000 | 0.375 |
7 | 0.374 | u_extr/ovcnt_15_s1/Q | u_extr/ovcnt_15_s1/D | lvds_pclk:[R] | lvds_pclk:[R] | 0.000 | 0.000 | 0.375 |
8 | 0.374 | u_extr/buf_ra_9_s0/Q | u_extr/buf_ra_9_s0/D | lvds_pclk:[R] | lvds_pclk:[R] | 0.000 | 0.000 | 0.375 |
9 | 0.374 | u_extr/ohcnt_1_s0/Q | u_extr/ohcnt_1_s0/D | lvds_pclk:[R] | lvds_pclk:[R] | 0.000 | 0.000 | 0.375 |
10 | 0.374 | frame_2_s0/Q | frame_2_s0/D | lvds_pclk:[R] | lvds_pclk:[R] | 0.000 | 0.000 | 0.375 |
11 | 0.377 | u_extr/ovcnt_4_s1/Q | u_extr/ovcnt_4_s1/D | lvds_pclk:[R] | lvds_pclk:[R] | 0.000 | 0.000 | 0.379 |
12 | 0.377 | u_extr/ovcnt_5_s1/Q | u_extr/ovcnt_5_s1/D | lvds_pclk:[R] | lvds_pclk:[R] | 0.000 | 0.000 | 0.379 |
13 | 0.377 | u_extr/ovcnt_11_s1/Q | u_extr/ovcnt_11_s1/D | lvds_pclk:[R] | lvds_pclk:[R] | 0.000 | 0.000 | 0.379 |
14 | 0.377 | u_extr/ovcnt_12_s1/Q | u_extr/ovcnt_12_s1/D | lvds_pclk:[R] | lvds_pclk:[R] | 0.000 | 0.000 | 0.379 |
15 | 0.377 | u_extr/ohcnt_4_s0/Q | u_extr/ohcnt_4_s0/D | lvds_pclk:[R] | lvds_pclk:[R] | 0.000 | 0.000 | 0.379 |
16 | 0.377 | u_extr/ohcnt_5_s0/Q | u_extr/ohcnt_5_s0/D | lvds_pclk:[R] | lvds_pclk:[R] | 0.000 | 0.000 | 0.379 |
17 | 0.377 | u_extr/ohcnt_6_s0/Q | u_extr/ohcnt_6_s0/D | lvds_pclk:[R] | lvds_pclk:[R] | 0.000 | 0.000 | 0.379 |
18 | 0.381 | u_extr/ovcnt_0_s3/Q | u_extr/ovcnt_0_s3/D | lvds_pclk:[R] | lvds_pclk:[R] | 0.000 | 0.000 | 0.382 |
19 | 0.381 | u_extr/ovcnt_10_s1/Q | u_extr/ovcnt_10_s1/D | lvds_pclk:[R] | lvds_pclk:[R] | 0.000 | 0.000 | 0.382 |
20 | 0.381 | u_extr/buf_ra_4_s0/Q | u_extr/buf_ra_4_s0/D | lvds_pclk:[R] | lvds_pclk:[R] | 0.000 | 0.000 | 0.382 |
Recovery Paths Table
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 0.349 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_match_1/trig_dly_0_s0/CLEAR | pixel_clk:[F] | pixel_clk:[R] | 3.572 | -0.354 | 3.229 |
2 | 0.554 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_match_1/match_sep_s0/CLEAR | pixel_clk:[F] | pixel_clk:[R] | 3.572 | -0.358 | 3.028 |
3 | 0.554 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_match_1/trig_dly_in_0_s0/CLEAR | pixel_clk:[F] | pixel_clk:[R] | 3.572 | -0.358 | 3.028 |
4 | 0.771 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_0_s0/CLEAR | pixel_clk:[F] | pixel_clk:[R] | 3.572 | -0.356 | 2.809 |
5 | 0.954 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR | pixel_clk:[F] | pixel_clk:[R] | 3.572 | -0.337 | 2.608 |
6 | 0.954 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_0_s0/CLEAR | pixel_clk:[F] | pixel_clk:[R] | 3.572 | -0.337 | 2.608 |
7 | 0.954 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR | pixel_clk:[F] | pixel_clk:[R] | 3.572 | -0.337 | 2.608 |
8 | 1.087 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR | pixel_clk:[F] | pixel_clk:[R] | 3.572 | -0.358 | 2.495 |
9 | 1.087 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR | pixel_clk:[F] | pixel_clk:[R] | 3.572 | -0.358 | 2.495 |
10 | 1.191 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR | pixel_clk:[F] | pixel_clk:[R] | 3.572 | -0.335 | 2.369 |
11 | 1.191 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR | pixel_clk:[F] | pixel_clk:[R] | 3.572 | -0.335 | 2.369 |
12 | 1.200 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR | pixel_clk:[F] | pixel_clk:[R] | 3.572 | -0.356 | 2.380 |
13 | 1.200 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR | pixel_clk:[F] | pixel_clk:[R] | 3.572 | -0.345 | 2.369 |
14 | 1.200 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR | pixel_clk:[F] | pixel_clk:[R] | 3.572 | -0.345 | 2.369 |
15 | 1.200 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_10_s1/CLEAR | pixel_clk:[F] | pixel_clk:[R] | 3.572 | -0.345 | 2.369 |
16 | 1.254 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s1/CLEAR | pixel_clk:[F] | pixel_clk:[R] | 3.572 | -0.383 | 2.352 |
17 | 1.277 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/CLEAR | pixel_clk:[F] | pixel_clk:[R] | 3.572 | -0.373 | 2.320 |
18 | 1.391 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR | pixel_clk:[F] | pixel_clk:[R] | 3.572 | -0.337 | 2.170 |
19 | 1.401 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR | pixel_clk:[F] | pixel_clk:[R] | 3.572 | -0.347 | 2.170 |
20 | 1.442 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/CLEAR | pixel_clk:[F] | pixel_clk:[R] | 3.572 | -0.354 | 2.136 |
21 | 1.442 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLEAR | pixel_clk:[F] | pixel_clk:[R] | 3.572 | -0.354 | 2.136 |
22 | 1.442 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_10_s1/CLEAR | pixel_clk:[F] | pixel_clk:[R] | 3.572 | -0.354 | 2.136 |
23 | 1.444 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR | pixel_clk:[F] | pixel_clk:[R] | 3.572 | -0.345 | 2.125 |
24 | 1.444 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR | pixel_clk:[F] | pixel_clk:[R] | 3.572 | -0.345 | 2.125 |
25 | 1.444 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR | pixel_clk:[F] | pixel_clk:[R] | 3.572 | -0.345 | 2.125 |
Removal Paths Table
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 4.536 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR | pixel_clk:[F] | pixel_clk:[R] | -3.572 | 0.280 | 0.495 |
2 | 4.536 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLEAR | pixel_clk:[F] | pixel_clk:[R] | -3.572 | 0.280 | 0.495 |
3 | 4.536 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/triger_s0/CLEAR | pixel_clk:[F] | pixel_clk:[R] | -3.572 | 0.280 | 0.495 |
4 | 4.612 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR | pixel_clk:[F] | pixel_clk:[R] | -3.572 | 0.283 | 0.569 |
5 | 4.612 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR | pixel_clk:[F] | pixel_clk:[R] | -3.572 | 0.283 | 0.569 |
6 | 4.846 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR | pixel_clk:[F] | pixel_clk:[R] | -3.572 | 0.303 | 0.783 |
7 | 5.048 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR | pixel_clk:[F] | pixel_clk:[R] | -3.572 | 0.308 | 0.980 |
8 | 5.048 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR | pixel_clk:[F] | pixel_clk:[R] | -3.572 | 0.308 | 0.980 |
9 | 5.050 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR | pixel_clk:[F] | pixel_clk:[R] | -3.572 | 0.309 | 0.980 |
10 | 5.057 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLEAR | pixel_clk:[F] | pixel_clk:[R] | -3.572 | 0.308 | 0.989 |
11 | 5.057 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLEAR | pixel_clk:[F] | pixel_clk:[R] | -3.572 | 0.308 | 0.989 |
12 | 5.057 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLEAR | pixel_clk:[F] | pixel_clk:[R] | -3.572 | 0.308 | 0.989 |
13 | 5.057 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET | pixel_clk:[F] | pixel_clk:[R] | -3.572 | 0.308 | 0.989 |
14 | 5.058 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLEAR | pixel_clk:[F] | pixel_clk:[R] | -3.572 | 0.309 | 0.989 |
15 | 5.058 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLEAR | pixel_clk:[F] | pixel_clk:[R] | -3.572 | 0.309 | 0.989 |
16 | 5.171 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR | pixel_clk:[F] | pixel_clk:[R] | -3.572 | 0.311 | 1.100 |
17 | 5.174 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR | pixel_clk:[F] | pixel_clk:[R] | -3.572 | 0.313 | 1.101 |
18 | 5.174 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLEAR | pixel_clk:[F] | pixel_clk:[R] | -3.572 | 0.313 | 1.101 |
19 | 5.174 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR | pixel_clk:[F] | pixel_clk:[R] | -3.572 | 0.313 | 1.101 |
20 | 5.174 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLEAR | pixel_clk:[F] | pixel_clk:[R] | -3.572 | 0.313 | 1.101 |
21 | 5.187 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR | pixel_clk:[F] | pixel_clk:[R] | -3.572 | 0.308 | 1.119 |
22 | 5.188 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR | pixel_clk:[F] | pixel_clk:[R] | -3.572 | 0.304 | 1.124 |
23 | 5.188 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR | pixel_clk:[F] | pixel_clk:[R] | -3.572 | 0.304 | 1.124 |
24 | 5.188 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/start_reg_s0/CLEAR | pixel_clk:[F] | pixel_clk:[R] | -3.572 | 0.304 | 1.124 |
25 | 5.188 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLEAR | pixel_clk:[F] | pixel_clk:[R] | -3.572 | 0.304 | 1.124 |
Minimum Pulse Width Table:
Number | Slack | Actual Width | Required Width | Type | Clock | Objects |
---|---|---|---|---|---|---|
1 | 1.189 | 2.189 | 1.000 | Low Pulse Width | byte_clk | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_1_s |
2 | 1.193 | 2.193 | 1.000 | Low Pulse Width | byte_clk | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s |
3 | 1.197 | 2.197 | 1.000 | High Pulse Width | pixel_clk | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_1_s |
4 | 1.201 | 2.201 | 1.000 | High Pulse Width | pixel_clk | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s |
5 | 1.244 | 2.244 | 1.000 | High Pulse Width | pixel_clk | u_extr/mem_data_mem_data_0_5_s |
6 | 1.244 | 2.244 | 1.000 | High Pulse Width | pixel_clk | u_extr/mem_data_mem_data_0_6_s |
7 | 1.248 | 2.248 | 1.000 | High Pulse Width | pixel_clk | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s |
8 | 1.248 | 2.248 | 1.000 | High Pulse Width | pixel_clk | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s |
9 | 1.248 | 2.248 | 1.000 | High Pulse Width | pixel_clk | u_extr/mem_data_mem_data_0_0_s |
10 | 1.248 | 2.248 | 1.000 | High Pulse Width | pixel_clk | u_extr/mem_data_mem_data_0_7_s |
Timing Report By Analysis Type:
Setup Analysis Report
Setup Analysis Report[1]:
Report Command:report_timing -setup -from_clock [get_clocks {pixel_clk}] -max_paths 20 -max_common_paths 1
Path1
Path Summary:
Slack | 1.025 |
Data Arrival Time | 8.946 |
Data Required Time | 9.971 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
2.896 | 2.896 | tNET | RR | 1 | R54C94[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK |
3.278 | 0.382 | tC2Q | RR | 8 | R54C94[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/Q |
4.672 | 1.394 | tNET | RR | 1 | R57C101[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n354_s10/I0 |
5.251 | 0.579 | tINS | RR | 1 | R57C101[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n354_s10/F |
5.253 | 0.003 | tNET | RR | 1 | R57C101[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n354_s6/I1 |
5.761 | 0.507 | tINS | RR | 1 | R57C101[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n354_s6/F |
5.763 | 0.003 | tNET | RR | 1 | R57C101[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n354_s4/I2 |
6.311 | 0.548 | tINS | RR | 12 | R57C101[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n354_s4/F |
8.378 | 2.067 | tNET | RR | 1 | R52C98[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n354_s2/I3 |
8.946 | 0.567 | tINS | RR | 1 | R52C98[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n354_s2/F |
8.946 | 0.000 | tNET | RR | 1 | R52C98[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | pixel_clk | ||||
7.143 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
10.035 | 2.892 | tNET | RR | 1 | R52C98[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/CLK |
9.971 | -0.064 | tSu | 1 | R52C98[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1 |
Path Statistics:
Clock Skew | -0.004 |
Setup Relationship | 7.143 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.896, 100.000% |
Arrival Data Path Delay | cell: 2.201, 36.384%; route: 3.466, 57.293%; tC2Q: 0.382, 6.322% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.892, 100.000% |
Path2
Path Summary:
Slack | 1.136 |
Data Arrival Time | 8.826 |
Data Required Time | 9.962 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
2.896 | 2.896 | tNET | RR | 1 | R54C94[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK |
3.278 | 0.382 | tC2Q | RR | 8 | R54C94[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/Q |
4.672 | 1.394 | tNET | RR | 1 | R57C101[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n354_s10/I0 |
5.251 | 0.579 | tINS | RR | 1 | R57C101[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n354_s10/F |
5.253 | 0.003 | tNET | RR | 1 | R57C101[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n354_s6/I1 |
5.761 | 0.507 | tINS | RR | 1 | R57C101[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n354_s6/F |
5.763 | 0.003 | tNET | RR | 1 | R57C101[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n354_s4/I2 |
6.311 | 0.548 | tINS | RR | 12 | R57C101[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n354_s4/F |
8.318 | 2.007 | tNET | RR | 1 | R52C93[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n356_s1/I3 |
8.826 | 0.507 | tINS | RR | 1 | R52C93[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n356_s1/F |
8.826 | 0.000 | tNET | RR | 1 | R52C93[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | pixel_clk | ||||
7.143 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
10.026 | 2.883 | tNET | RR | 1 | R52C93[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK |
9.962 | -0.064 | tSu | 1 | R52C93[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1 |
Path Statistics:
Clock Skew | -0.013 |
Setup Relationship | 7.143 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.896, 100.000% |
Arrival Data Path Delay | cell: 2.141, 36.109%; route: 3.406, 57.441%; tC2Q: 0.382, 6.450% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.883, 100.000% |
Path3
Path Summary:
Slack | 1.647 |
Data Arrival Time | 8.328 |
Data Required Time | 9.975 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
2.896 | 2.896 | tNET | RR | 1 | R54C94[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK |
3.278 | 0.382 | tC2Q | RR | 8 | R54C94[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/Q |
4.672 | 1.394 | tNET | RR | 1 | R57C101[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n354_s10/I0 |
5.251 | 0.579 | tINS | RR | 1 | R57C101[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n354_s10/F |
5.253 | 0.003 | tNET | RR | 1 | R57C101[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n354_s6/I1 |
5.761 | 0.507 | tINS | RR | 1 | R57C101[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n354_s6/F |
5.763 | 0.003 | tNET | RR | 1 | R57C101[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n354_s4/I2 |
6.311 | 0.548 | tINS | RR | 12 | R57C101[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n354_s4/F |
7.749 | 1.439 | tNET | RR | 1 | R54C94[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n358_s1/I3 |
8.328 | 0.579 | tINS | RR | 1 | R54C94[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n358_s1/F |
8.328 | 0.000 | tNET | RR | 1 | R54C94[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | pixel_clk | ||||
7.143 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
10.039 | 2.896 | tNET | RR | 1 | R54C94[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK |
9.975 | -0.064 | tSu | 1 | R54C94[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 7.143 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.896, 100.000% |
Arrival Data Path Delay | cell: 2.213, 40.727%; route: 2.838, 52.232%; tC2Q: 0.382, 7.041% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.896, 100.000% |
Path4
Path Summary:
Slack | 1.647 |
Data Arrival Time | 8.328 |
Data Required Time | 9.975 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
2.896 | 2.896 | tNET | RR | 1 | R54C94[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK |
3.278 | 0.382 | tC2Q | RR | 8 | R54C94[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/Q |
4.672 | 1.394 | tNET | RR | 1 | R57C101[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n354_s10/I0 |
5.251 | 0.579 | tINS | RR | 1 | R57C101[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n354_s10/F |
5.253 | 0.003 | tNET | RR | 1 | R57C101[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n354_s6/I1 |
5.761 | 0.507 | tINS | RR | 1 | R57C101[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n354_s6/F |
5.763 | 0.003 | tNET | RR | 1 | R57C101[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n354_s4/I2 |
6.311 | 0.548 | tINS | RR | 12 | R57C101[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n354_s4/F |
7.749 | 1.439 | tNET | RR | 1 | R54C94[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n355_s1/I3 |
8.328 | 0.579 | tINS | RR | 1 | R54C94[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n355_s1/F |
8.328 | 0.000 | tNET | RR | 1 | R54C94[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | pixel_clk | ||||
7.143 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
10.039 | 2.896 | tNET | RR | 1 | R54C94[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK |
9.975 | -0.064 | tSu | 1 | R54C94[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 7.143 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.896, 100.000% |
Arrival Data Path Delay | cell: 2.213, 40.727%; route: 2.838, 52.232%; tC2Q: 0.382, 7.041% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.896, 100.000% |
Path5
Path Summary:
Slack | 1.747 |
Data Arrival Time | 7.896 |
Data Required Time | 9.644 |
From | u_b2p/u_b2p_inst/u_hs_adj/rQout_s1 |
To | u_extr/pixel_cnt_1_s0 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
2.979 | 2.979 | tNET | RR | 1 | R56C70[1][A] | u_b2p/u_b2p_inst/u_hs_adj/rQout_s1/CLK |
3.361 | 0.382 | tC2Q | RR | 7 | R56C70[1][A] | u_b2p/u_b2p_inst/u_hs_adj/rQout_s1/Q |
6.094 | 2.733 | tNET | RR | 1 | R56C121[3][B] | u_extr/n94_s1/I0 |
6.550 | 0.456 | tINS | RR | 27 | R56C121[3][B] | u_extr/n94_s1/F |
7.896 | 1.346 | tNET | RR | 1 | R52C120[0][A] | u_extr/pixel_cnt_1_s0/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | pixel_clk | ||||
7.143 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
10.016 | 2.873 | tNET | RR | 1 | R52C120[0][A] | u_extr/pixel_cnt_1_s0/CLK |
9.644 | -0.373 | tSu | 1 | R52C120[0][A] | u_extr/pixel_cnt_1_s0 |
Path Statistics:
Clock Skew | -0.106 |
Setup Relationship | 7.143 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.979, 100.000% |
Arrival Data Path Delay | cell: 0.456, 9.278%; route: 4.079, 82.944%; tC2Q: 0.382, 7.778% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.873, 100.000% |
Path6
Path Summary:
Slack | 1.747 |
Data Arrival Time | 7.896 |
Data Required Time | 9.644 |
From | u_b2p/u_b2p_inst/u_hs_adj/rQout_s1 |
To | u_extr/pixel_cnt_2_s0 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
2.979 | 2.979 | tNET | RR | 1 | R56C70[1][A] | u_b2p/u_b2p_inst/u_hs_adj/rQout_s1/CLK |
3.361 | 0.382 | tC2Q | RR | 7 | R56C70[1][A] | u_b2p/u_b2p_inst/u_hs_adj/rQout_s1/Q |
6.094 | 2.733 | tNET | RR | 1 | R56C121[3][B] | u_extr/n94_s1/I0 |
6.550 | 0.456 | tINS | RR | 27 | R56C121[3][B] | u_extr/n94_s1/F |
7.896 | 1.346 | tNET | RR | 1 | R52C120[0][B] | u_extr/pixel_cnt_2_s0/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | pixel_clk | ||||
7.143 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
10.016 | 2.873 | tNET | RR | 1 | R52C120[0][B] | u_extr/pixel_cnt_2_s0/CLK |
9.644 | -0.373 | tSu | 1 | R52C120[0][B] | u_extr/pixel_cnt_2_s0 |
Path Statistics:
Clock Skew | -0.106 |
Setup Relationship | 7.143 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.979, 100.000% |
Arrival Data Path Delay | cell: 0.456, 9.278%; route: 4.079, 82.944%; tC2Q: 0.382, 7.778% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.873, 100.000% |
Path7
Path Summary:
Slack | 1.747 |
Data Arrival Time | 7.896 |
Data Required Time | 9.644 |
From | u_b2p/u_b2p_inst/u_hs_adj/rQout_s1 |
To | u_extr/pixel_cnt_3_s0 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
2.979 | 2.979 | tNET | RR | 1 | R56C70[1][A] | u_b2p/u_b2p_inst/u_hs_adj/rQout_s1/CLK |
3.361 | 0.382 | tC2Q | RR | 7 | R56C70[1][A] | u_b2p/u_b2p_inst/u_hs_adj/rQout_s1/Q |
6.094 | 2.733 | tNET | RR | 1 | R56C121[3][B] | u_extr/n94_s1/I0 |
6.550 | 0.456 | tINS | RR | 27 | R56C121[3][B] | u_extr/n94_s1/F |
7.896 | 1.346 | tNET | RR | 1 | R52C120[1][A] | u_extr/pixel_cnt_3_s0/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | pixel_clk | ||||
7.143 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
10.016 | 2.873 | tNET | RR | 1 | R52C120[1][A] | u_extr/pixel_cnt_3_s0/CLK |
9.644 | -0.373 | tSu | 1 | R52C120[1][A] | u_extr/pixel_cnt_3_s0 |
Path Statistics:
Clock Skew | -0.106 |
Setup Relationship | 7.143 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.979, 100.000% |
Arrival Data Path Delay | cell: 0.456, 9.278%; route: 4.079, 82.944%; tC2Q: 0.382, 7.778% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.873, 100.000% |
Path8
Path Summary:
Slack | 1.747 |
Data Arrival Time | 7.896 |
Data Required Time | 9.644 |
From | u_b2p/u_b2p_inst/u_hs_adj/rQout_s1 |
To | u_extr/pixel_cnt_4_s0 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
2.979 | 2.979 | tNET | RR | 1 | R56C70[1][A] | u_b2p/u_b2p_inst/u_hs_adj/rQout_s1/CLK |
3.361 | 0.382 | tC2Q | RR | 7 | R56C70[1][A] | u_b2p/u_b2p_inst/u_hs_adj/rQout_s1/Q |
6.094 | 2.733 | tNET | RR | 1 | R56C121[3][B] | u_extr/n94_s1/I0 |
6.550 | 0.456 | tINS | RR | 27 | R56C121[3][B] | u_extr/n94_s1/F |
7.896 | 1.346 | tNET | RR | 1 | R52C120[1][B] | u_extr/pixel_cnt_4_s0/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | pixel_clk | ||||
7.143 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
10.016 | 2.873 | tNET | RR | 1 | R52C120[1][B] | u_extr/pixel_cnt_4_s0/CLK |
9.644 | -0.373 | tSu | 1 | R52C120[1][B] | u_extr/pixel_cnt_4_s0 |
Path Statistics:
Clock Skew | -0.106 |
Setup Relationship | 7.143 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.979, 100.000% |
Arrival Data Path Delay | cell: 0.456, 9.278%; route: 4.079, 82.944%; tC2Q: 0.382, 7.778% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.873, 100.000% |
Path9
Path Summary:
Slack | 1.747 |
Data Arrival Time | 7.896 |
Data Required Time | 9.644 |
From | u_b2p/u_b2p_inst/u_hs_adj/rQout_s1 |
To | u_extr/pixel_cnt_5_s0 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
2.979 | 2.979 | tNET | RR | 1 | R56C70[1][A] | u_b2p/u_b2p_inst/u_hs_adj/rQout_s1/CLK |
3.361 | 0.382 | tC2Q | RR | 7 | R56C70[1][A] | u_b2p/u_b2p_inst/u_hs_adj/rQout_s1/Q |
6.094 | 2.733 | tNET | RR | 1 | R56C121[3][B] | u_extr/n94_s1/I0 |
6.550 | 0.456 | tINS | RR | 27 | R56C121[3][B] | u_extr/n94_s1/F |
7.896 | 1.346 | tNET | RR | 1 | R52C120[2][A] | u_extr/pixel_cnt_5_s0/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | pixel_clk | ||||
7.143 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
10.016 | 2.873 | tNET | RR | 1 | R52C120[2][A] | u_extr/pixel_cnt_5_s0/CLK |
9.644 | -0.373 | tSu | 1 | R52C120[2][A] | u_extr/pixel_cnt_5_s0 |
Path Statistics:
Clock Skew | -0.106 |
Setup Relationship | 7.143 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.979, 100.000% |
Arrival Data Path Delay | cell: 0.456, 9.278%; route: 4.079, 82.944%; tC2Q: 0.382, 7.778% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.873, 100.000% |
Path10
Path Summary:
Slack | 1.747 |
Data Arrival Time | 7.896 |
Data Required Time | 9.644 |
From | u_b2p/u_b2p_inst/u_hs_adj/rQout_s1 |
To | u_extr/pixel_cnt_6_s0 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
2.979 | 2.979 | tNET | RR | 1 | R56C70[1][A] | u_b2p/u_b2p_inst/u_hs_adj/rQout_s1/CLK |
3.361 | 0.382 | tC2Q | RR | 7 | R56C70[1][A] | u_b2p/u_b2p_inst/u_hs_adj/rQout_s1/Q |
6.094 | 2.733 | tNET | RR | 1 | R56C121[3][B] | u_extr/n94_s1/I0 |
6.550 | 0.456 | tINS | RR | 27 | R56C121[3][B] | u_extr/n94_s1/F |
7.896 | 1.346 | tNET | RR | 1 | R52C120[2][B] | u_extr/pixel_cnt_6_s0/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | pixel_clk | ||||
7.143 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
10.016 | 2.873 | tNET | RR | 1 | R52C120[2][B] | u_extr/pixel_cnt_6_s0/CLK |
9.644 | -0.373 | tSu | 1 | R52C120[2][B] | u_extr/pixel_cnt_6_s0 |
Path Statistics:
Clock Skew | -0.106 |
Setup Relationship | 7.143 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.979, 100.000% |
Arrival Data Path Delay | cell: 0.456, 9.278%; route: 4.079, 82.944%; tC2Q: 0.382, 7.778% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.873, 100.000% |
Path11
Path Summary:
Slack | 1.881 |
Data Arrival Time | 8.084 |
Data Required Time | 9.965 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
2.896 | 2.896 | tNET | RR | 1 | R54C94[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK |
3.278 | 0.382 | tC2Q | RR | 8 | R54C94[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/Q |
4.672 | 1.394 | tNET | RR | 1 | R57C101[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n354_s10/I0 |
5.251 | 0.579 | tINS | RR | 1 | R57C101[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n354_s10/F |
5.253 | 0.003 | tNET | RR | 1 | R57C101[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n354_s6/I1 |
5.761 | 0.507 | tINS | RR | 1 | R57C101[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n354_s6/F |
5.763 | 0.003 | tNET | RR | 1 | R57C101[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n354_s4/I2 |
6.311 | 0.548 | tINS | RR | 12 | R57C101[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n354_s4/F |
7.577 | 1.266 | tNET | RR | 1 | R54C93[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n360_s1/I3 |
8.084 | 0.507 | tINS | RR | 1 | R54C93[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n360_s1/F |
8.084 | 0.000 | tNET | RR | 1 | R54C93[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | pixel_clk | ||||
7.143 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
10.029 | 2.886 | tNET | RR | 1 | R54C93[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK |
9.965 | -0.064 | tSu | 1 | R54C93[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1 |
Path Statistics:
Clock Skew | -0.009 |
Setup Relationship | 7.143 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.896, 100.000% |
Arrival Data Path Delay | cell: 2.141, 41.267%; route: 2.665, 51.361%; tC2Q: 0.382, 7.372% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.886, 100.000% |
Path12
Path Summary:
Slack | 1.881 |
Data Arrival Time | 8.084 |
Data Required Time | 9.965 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
2.896 | 2.896 | tNET | RR | 1 | R54C94[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK |
3.278 | 0.382 | tC2Q | RR | 8 | R54C94[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/Q |
4.672 | 1.394 | tNET | RR | 1 | R57C101[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n354_s10/I0 |
5.251 | 0.579 | tINS | RR | 1 | R57C101[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n354_s10/F |
5.253 | 0.003 | tNET | RR | 1 | R57C101[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n354_s6/I1 |
5.761 | 0.507 | tINS | RR | 1 | R57C101[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n354_s6/F |
5.763 | 0.003 | tNET | RR | 1 | R57C101[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n354_s4/I2 |
6.311 | 0.548 | tINS | RR | 12 | R57C101[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n354_s4/F |
7.577 | 1.266 | tNET | RR | 1 | R54C93[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n359_s1/I3 |
8.084 | 0.507 | tINS | RR | 1 | R54C93[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n359_s1/F |
8.084 | 0.000 | tNET | RR | 1 | R54C93[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | pixel_clk | ||||
7.143 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
10.029 | 2.886 | tNET | RR | 1 | R54C93[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK |
9.965 | -0.064 | tSu | 1 | R54C93[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1 |
Path Statistics:
Clock Skew | -0.009 |
Setup Relationship | 7.143 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.896, 100.000% |
Arrival Data Path Delay | cell: 2.141, 41.267%; route: 2.665, 51.361%; tC2Q: 0.382, 7.372% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.886, 100.000% |
Path13
Path Summary:
Slack | 1.967 |
Data Arrival Time | 8.006 |
Data Required Time | 9.973 |
From | gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3 |
To | gw_gao_inst_0/u_la0_top/start_reg_s0 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
2.877 | 2.877 | tNET | RR | 1 | R54C96[3][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLK |
3.244 | 0.368 | tC2Q | RF | 15 | R54C96[3][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/Q |
4.826 | 1.581 | tNET | FF | 2 | R56C99[0][A] | gw_gao_inst_0/u_la0_top/n1693_s22/I1 |
5.371 | 0.545 | tINS | FR | 1 | R56C99[0][A] | gw_gao_inst_0/u_la0_top/n1693_s22/COUT |
5.371 | 0.000 | tNET | RR | 2 | R56C99[0][B] | gw_gao_inst_0/u_la0_top/n1693_s23/CIN |
5.421 | 0.050 | tINS | RR | 1 | R56C99[0][B] | gw_gao_inst_0/u_la0_top/n1693_s23/COUT |
5.421 | 0.000 | tNET | RR | 2 | R56C99[1][A] | gw_gao_inst_0/u_la0_top/n1693_s24/CIN |
5.471 | 0.050 | tINS | RR | 1 | R56C99[1][A] | gw_gao_inst_0/u_la0_top/n1693_s24/COUT |
5.471 | 0.000 | tNET | RR | 2 | R56C99[1][B] | gw_gao_inst_0/u_la0_top/n1693_s25/CIN |
5.521 | 0.050 | tINS | RR | 1 | R56C99[1][B] | gw_gao_inst_0/u_la0_top/n1693_s25/COUT |
5.521 | 0.000 | tNET | RR | 2 | R56C99[2][A] | gw_gao_inst_0/u_la0_top/n1693_s26/CIN |
5.571 | 0.050 | tINS | RR | 1 | R56C99[2][A] | gw_gao_inst_0/u_la0_top/n1693_s26/COUT |
5.571 | 0.000 | tNET | RR | 2 | R56C99[2][B] | gw_gao_inst_0/u_la0_top/n1693_s27/CIN |
5.621 | 0.050 | tINS | RR | 1 | R56C99[2][B] | gw_gao_inst_0/u_la0_top/n1693_s27/COUT |
5.621 | 0.000 | tNET | RR | 2 | R56C100[0][A] | gw_gao_inst_0/u_la0_top/n1693_s28/CIN |
5.671 | 0.050 | tINS | RR | 1 | R56C100[0][A] | gw_gao_inst_0/u_la0_top/n1693_s28/COUT |
5.671 | 0.000 | tNET | RR | 2 | R56C100[0][B] | gw_gao_inst_0/u_la0_top/n1693_s29/CIN |
5.721 | 0.050 | tINS | RR | 1 | R56C100[0][B] | gw_gao_inst_0/u_la0_top/n1693_s29/COUT |
5.721 | 0.000 | tNET | RR | 2 | R56C100[1][A] | gw_gao_inst_0/u_la0_top/n1693_s30/CIN |
5.771 | 0.050 | tINS | RR | 1 | R56C100[1][A] | gw_gao_inst_0/u_la0_top/n1693_s30/COUT |
5.771 | 0.000 | tNET | RR | 2 | R56C100[1][B] | gw_gao_inst_0/u_la0_top/n1693_s31/CIN |
5.821 | 0.050 | tINS | RR | 2 | R56C100[1][B] | gw_gao_inst_0/u_la0_top/n1693_s31/COUT |
6.818 | 0.998 | tNET | RR | 1 | R54C98[0][A] | gw_gao_inst_0/u_la0_top/start_reg1_s1/I2 |
7.326 | 0.507 | tINS | RR | 1 | R54C98[0][A] | gw_gao_inst_0/u_la0_top/start_reg1_s1/F |
7.498 | 0.172 | tNET | RR | 1 | R53C98[2][A] | gw_gao_inst_0/u_la0_top/start_reg1_s0/I1 |
8.006 | 0.507 | tINS | RR | 1 | R53C98[2][A] | gw_gao_inst_0/u_la0_top/start_reg1_s0/F |
8.006 | 0.000 | tNET | RR | 1 | R53C98[2][A] | gw_gao_inst_0/u_la0_top/start_reg_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | pixel_clk | ||||
7.143 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
10.037 | 2.894 | tNET | RR | 1 | R53C98[2][A] | gw_gao_inst_0/u_la0_top/start_reg_s0/CLK |
9.973 | -0.064 | tSu | 1 | R53C98[2][A] | gw_gao_inst_0/u_la0_top/start_reg_s0 |
Path Statistics:
Clock Skew | 0.017 |
Setup Relationship | 7.143 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.877, 100.000% |
Arrival Data Path Delay | cell: 2.010, 39.191%; route: 2.751, 53.644%; tC2Q: 0.368, 7.165% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.894, 100.000% |
Path14
Path Summary:
Slack | 2.088 |
Data Arrival Time | 7.878 |
Data Required Time | 9.965 |
From | u_b2p/u_b2p_inst/u_hs_adj/rQout_s1 |
To | u_extr/iact_line_s0 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
2.979 | 2.979 | tNET | RR | 1 | R56C70[1][A] | u_b2p/u_b2p_inst/u_hs_adj/rQout_s1/CLK |
3.361 | 0.382 | tC2Q | RR | 7 | R56C70[1][A] | u_b2p/u_b2p_inst/u_hs_adj/rQout_s1/Q |
6.638 | 3.276 | tNET | RR | 1 | R54C121[0][A] | u_extr/n200_s1/I1 |
7.145 | 0.507 | tINS | RR | 3 | R54C121[0][A] | u_extr/n200_s1/F |
7.299 | 0.154 | tNET | RR | 1 | R54C121[0][B] | u_extr/n163_s0/I3 |
7.878 | 0.579 | tINS | RR | 1 | R54C121[0][B] | u_extr/n163_s0/F |
7.878 | 0.000 | tNET | RR | 1 | R54C121[0][B] | u_extr/iact_line_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | pixel_clk | ||||
7.143 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
10.029 | 2.886 | tNET | RR | 1 | R54C121[0][B] | u_extr/iact_line_s0/CLK |
9.965 | -0.064 | tSu | 1 | R54C121[0][B] | u_extr/iact_line_s0 |
Path Statistics:
Clock Skew | -0.092 |
Setup Relationship | 7.143 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.979, 100.000% |
Arrival Data Path Delay | cell: 1.086, 22.174%; route: 3.430, 70.018%; tC2Q: 0.382, 7.808% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.886, 100.000% |
Path15
Path Summary:
Slack | 2.100 |
Data Arrival Time | 7.863 |
Data Required Time | 9.964 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
2.896 | 2.896 | tNET | RR | 1 | R54C94[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK |
3.278 | 0.382 | tC2Q | RR | 8 | R54C94[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/Q |
4.672 | 1.394 | tNET | RR | 1 | R57C101[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n354_s10/I0 |
5.251 | 0.579 | tINS | RR | 1 | R57C101[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n354_s10/F |
5.253 | 0.003 | tNET | RR | 1 | R57C101[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n354_s6/I1 |
5.761 | 0.507 | tINS | RR | 1 | R57C101[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n354_s6/F |
5.763 | 0.003 | tNET | RR | 1 | R57C101[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n354_s4/I2 |
6.311 | 0.548 | tINS | RR | 12 | R57C101[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n354_s4/F |
7.574 | 1.264 | tNET | RR | 1 | R53C93[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n357_s1/I3 |
7.863 | 0.289 | tINS | RR | 1 | R53C93[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n357_s1/F |
7.863 | 0.000 | tNET | RR | 1 | R53C93[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | pixel_clk | ||||
7.143 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
10.027 | 2.884 | tNET | RR | 1 | R53C93[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK |
9.964 | -0.064 | tSu | 1 | R53C93[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1 |
Path Statistics:
Clock Skew | -0.011 |
Setup Relationship | 7.143 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.896, 100.000% |
Arrival Data Path Delay | cell: 1.923, 38.702%; route: 2.663, 53.598%; tC2Q: 0.382, 7.700% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.884, 100.000% |
Path16
Path Summary:
Slack | 2.106 |
Data Arrival Time | 7.884 |
Data Required Time | 9.991 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
2.896 | 2.896 | tNET | RR | 1 | R54C94[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK |
3.278 | 0.382 | tC2Q | RR | 8 | R54C94[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/Q |
4.672 | 1.394 | tNET | RR | 1 | R57C101[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n354_s10/I0 |
5.251 | 0.579 | tINS | RR | 1 | R57C101[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n354_s10/F |
5.253 | 0.003 | tNET | RR | 1 | R57C101[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n354_s6/I1 |
5.761 | 0.507 | tINS | RR | 1 | R57C101[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n354_s6/F |
5.763 | 0.003 | tNET | RR | 1 | R57C101[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n354_s4/I2 |
6.311 | 0.548 | tINS | RR | 12 | R57C101[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n354_s4/F |
7.306 | 0.995 | tNET | RR | 1 | R56C96[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n364_s3/I2 |
7.884 | 0.579 | tINS | RR | 1 | R56C96[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n364_s3/F |
7.884 | 0.000 | tNET | RR | 1 | R56C96[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | pixel_clk | ||||
7.143 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
10.054 | 2.911 | tNET | RR | 1 | R56C96[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/CLK |
9.991 | -0.064 | tSu | 1 | R56C96[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5 |
Path Statistics:
Clock Skew | 0.016 |
Setup Relationship | 7.143 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.896, 100.000% |
Arrival Data Path Delay | cell: 2.213, 44.350%; route: 2.394, 47.983%; tC2Q: 0.382, 7.667% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.911, 100.000% |
Path17
Path Summary:
Slack | 2.112 |
Data Arrival Time | 7.534 |
Data Required Time | 9.646 |
From | u_b2p/u_b2p_inst/u_hs_adj/rQout_s1 |
To | u_extr/buf_wa_1_s0 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
2.979 | 2.979 | tNET | RR | 1 | R56C70[1][A] | u_b2p/u_b2p_inst/u_hs_adj/rQout_s1/CLK |
3.361 | 0.382 | tC2Q | RR | 7 | R56C70[1][A] | u_b2p/u_b2p_inst/u_hs_adj/rQout_s1/Q |
6.094 | 2.733 | tNET | RR | 1 | R56C121[3][B] | u_extr/n94_s1/I0 |
6.550 | 0.456 | tINS | RR | 27 | R56C121[3][B] | u_extr/n94_s1/F |
7.534 | 0.984 | tNET | RR | 1 | R53C120[0][A] | u_extr/buf_wa_1_s0/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | pixel_clk | ||||
7.143 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
10.018 | 2.875 | tNET | RR | 1 | R53C120[0][A] | u_extr/buf_wa_1_s0/CLK |
9.646 | -0.373 | tSu | 1 | R53C120[0][A] | u_extr/buf_wa_1_s0 |
Path Statistics:
Clock Skew | -0.104 |
Setup Relationship | 7.143 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.979, 100.000% |
Arrival Data Path Delay | cell: 0.456, 10.016%; route: 3.716, 81.586%; tC2Q: 0.382, 8.397% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.875, 100.000% |
Path18
Path Summary:
Slack | 2.112 |
Data Arrival Time | 7.534 |
Data Required Time | 9.646 |
From | u_b2p/u_b2p_inst/u_hs_adj/rQout_s1 |
To | u_extr/buf_wa_2_s0 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
2.979 | 2.979 | tNET | RR | 1 | R56C70[1][A] | u_b2p/u_b2p_inst/u_hs_adj/rQout_s1/CLK |
3.361 | 0.382 | tC2Q | RR | 7 | R56C70[1][A] | u_b2p/u_b2p_inst/u_hs_adj/rQout_s1/Q |
6.094 | 2.733 | tNET | RR | 1 | R56C121[3][B] | u_extr/n94_s1/I0 |
6.550 | 0.456 | tINS | RR | 27 | R56C121[3][B] | u_extr/n94_s1/F |
7.534 | 0.984 | tNET | RR | 1 | R53C120[0][B] | u_extr/buf_wa_2_s0/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | pixel_clk | ||||
7.143 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
10.018 | 2.875 | tNET | RR | 1 | R53C120[0][B] | u_extr/buf_wa_2_s0/CLK |
9.646 | -0.373 | tSu | 1 | R53C120[0][B] | u_extr/buf_wa_2_s0 |
Path Statistics:
Clock Skew | -0.104 |
Setup Relationship | 7.143 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.979, 100.000% |
Arrival Data Path Delay | cell: 0.456, 10.016%; route: 3.716, 81.586%; tC2Q: 0.382, 8.397% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.875, 100.000% |
Path19
Path Summary:
Slack | 2.112 |
Data Arrival Time | 7.534 |
Data Required Time | 9.646 |
From | u_b2p/u_b2p_inst/u_hs_adj/rQout_s1 |
To | u_extr/buf_wa_3_s0 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
2.979 | 2.979 | tNET | RR | 1 | R56C70[1][A] | u_b2p/u_b2p_inst/u_hs_adj/rQout_s1/CLK |
3.361 | 0.382 | tC2Q | RR | 7 | R56C70[1][A] | u_b2p/u_b2p_inst/u_hs_adj/rQout_s1/Q |
6.094 | 2.733 | tNET | RR | 1 | R56C121[3][B] | u_extr/n94_s1/I0 |
6.550 | 0.456 | tINS | RR | 27 | R56C121[3][B] | u_extr/n94_s1/F |
7.534 | 0.984 | tNET | RR | 1 | R53C120[1][A] | u_extr/buf_wa_3_s0/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | pixel_clk | ||||
7.143 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
10.018 | 2.875 | tNET | RR | 1 | R53C120[1][A] | u_extr/buf_wa_3_s0/CLK |
9.646 | -0.373 | tSu | 1 | R53C120[1][A] | u_extr/buf_wa_3_s0 |
Path Statistics:
Clock Skew | -0.104 |
Setup Relationship | 7.143 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.979, 100.000% |
Arrival Data Path Delay | cell: 0.456, 10.016%; route: 3.716, 81.586%; tC2Q: 0.382, 8.397% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.875, 100.000% |
Path20
Path Summary:
Slack | 2.112 |
Data Arrival Time | 7.534 |
Data Required Time | 9.646 |
From | u_b2p/u_b2p_inst/u_hs_adj/rQout_s1 |
To | u_extr/buf_wa_4_s0 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
2.979 | 2.979 | tNET | RR | 1 | R56C70[1][A] | u_b2p/u_b2p_inst/u_hs_adj/rQout_s1/CLK |
3.361 | 0.382 | tC2Q | RR | 7 | R56C70[1][A] | u_b2p/u_b2p_inst/u_hs_adj/rQout_s1/Q |
6.094 | 2.733 | tNET | RR | 1 | R56C121[3][B] | u_extr/n94_s1/I0 |
6.550 | 0.456 | tINS | RR | 27 | R56C121[3][B] | u_extr/n94_s1/F |
7.534 | 0.984 | tNET | RR | 1 | R53C120[1][B] | u_extr/buf_wa_4_s0/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | pixel_clk | ||||
7.143 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
10.018 | 2.875 | tNET | RR | 1 | R53C120[1][B] | u_extr/buf_wa_4_s0/CLK |
9.646 | -0.373 | tSu | 1 | R53C120[1][B] | u_extr/buf_wa_4_s0 |
Path Statistics:
Clock Skew | -0.104 |
Setup Relationship | 7.143 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.979, 100.000% |
Arrival Data Path Delay | cell: 0.456, 10.016%; route: 3.716, 81.586%; tC2Q: 0.382, 8.397% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.875, 100.000% |
Setup Analysis Report[2]:
Report Command:report_timing -setup -from_clock [get_clocks {byte_clk}] -max_paths 20 -max_common_paths 1
Path1
Path Summary:
Slack | 0.201 |
Data Arrival Time | 15.369 |
Data Required Time | 15.570 |
From | hsrx_en_msk_s0 |
To | byte_ready_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 578 | QUAD[0] | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
6.171 | 6.171 | tNET | RR | 1 | R56C129[1][A] | hsrx_en_msk_s0/CLK |
6.554 | 0.382 | tC2Q | RR | 1 | R56C129[1][A] | hsrx_en_msk_s0/Q |
13.666 | 7.112 | tNET | RR | 1 | R20C29[3][B] | n162_s0/I1 |
13.985 | 0.319 | tINS | RF | 1 | R20C29[3][B] | n162_s0/F |
15.369 | 1.384 | tNET | FF | 1 | R20C10[3][B] | byte_ready_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.524 | 9.524 | active clock edge time | ||||
9.524 | 0.000 | byte_clk | ||||
9.524 | 0.000 | tCL | RR | 578 | QUAD[0] | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
15.627 | 6.103 | tNET | RR | 1 | R20C10[3][B] | byte_ready_s0/CLK |
15.570 | -0.058 | tSu | 1 | R20C10[3][B] | byte_ready_s0 |
Path Statistics:
Clock Skew | -0.068 |
Setup Relationship | 9.524 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 6.171, 100.000% |
Arrival Data Path Delay | cell: 0.319, 3.466%; route: 8.496, 92.376%; tC2Q: 0.382, 4.159% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 6.103, 100.000% |
Path2
Path Summary:
Slack | 0.382 |
Data Arrival Time | 14.997 |
Data Required Time | 15.380 |
From | u_dsi_rx/u_dsi_csi2/rData_3_s0 |
To | u_dsi_rx/u_dsi_csi2/rHeader_7_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 578 | QUAD[0] | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
6.180 | 6.180 | tNET | RR | 1 | R51C53[0][B] | u_dsi_rx/u_dsi_csi2/rData_3_s0/CLK |
6.563 | 0.382 | tC2Q | RR | 7 | R51C53[0][B] | u_dsi_rx/u_dsi_csi2/rData_3_s0/Q |
7.999 | 1.436 | tNET | RR | 1 | R53C54[0][A] | u_dsi_rx/u_dsi_csi2/wHeader_19_s1/I0 |
8.578 | 0.579 | tINS | RR | 2 | R53C54[0][A] | u_dsi_rx/u_dsi_csi2/wHeader_19_s1/F |
8.753 | 0.175 | tNET | RR | 1 | R54C54[3][B] | u_dsi_rx/u_dsi_csi2/wHeader_3_s0/I0 |
9.044 | 0.291 | tINS | RR | 5 | R54C54[3][B] | u_dsi_rx/u_dsi_csi2/wHeader_3_s0/F |
10.435 | 1.391 | tNET | RR | 1 | R56C55[2][B] | u_dsi_rx/u_dsi_csi2/n1188_s8/I2 |
11.003 | 0.567 | tINS | RR | 1 | R56C55[2][B] | u_dsi_rx/u_dsi_csi2/n1188_s8/F |
11.005 | 0.003 | tNET | RR | 1 | R56C55[1][B] | u_dsi_rx/u_dsi_csi2/n1188_s4/I1 |
11.584 | 0.579 | tINS | RR | 2 | R56C55[1][B] | u_dsi_rx/u_dsi_csi2/n1188_s4/F |
12.369 | 0.785 | tNET | RR | 1 | R56C66[3][B] | u_dsi_rx/u_dsi_csi2/n1188_s1/I2 |
12.825 | 0.456 | tINS | RR | 32 | R56C66[3][B] | u_dsi_rx/u_dsi_csi2/n1188_s1/F |
14.998 | 2.173 | tNET | RR | 1 | R54C55[0][A] | u_dsi_rx/u_dsi_csi2/rHeader_7_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.524 | 9.524 | active clock edge time | ||||
9.524 | 0.000 | byte_clk | ||||
9.524 | 0.000 | tCL | RR | 578 | QUAD[0] | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
15.691 | 6.167 | tNET | RR | 1 | R54C55[0][A] | u_dsi_rx/u_dsi_csi2/rHeader_7_s0/CLK |
15.380 | -0.311 | tSu | 1 | R54C55[0][A] | u_dsi_rx/u_dsi_csi2/rHeader_7_s0 |
Path Statistics:
Clock Skew | -0.013 |
Setup Relationship | 9.524 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 6.180, 100.000% |
Arrival Data Path Delay | cell: 2.473, 28.041%; route: 5.963, 67.621%; tC2Q: 0.382, 4.338% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 6.167, 100.000% |
Path3
Path Summary:
Slack | 0.810 |
Data Arrival Time | 14.568 |
Data Required Time | 15.378 |
From | u_dsi_rx/u_dsi_csi2/rData_3_s0 |
To | u_dsi_rx/u_dsi_csi2/rHeader_13_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 578 | QUAD[0] | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
6.180 | 6.180 | tNET | RR | 1 | R51C53[0][B] | u_dsi_rx/u_dsi_csi2/rData_3_s0/CLK |
6.563 | 0.382 | tC2Q | RR | 7 | R51C53[0][B] | u_dsi_rx/u_dsi_csi2/rData_3_s0/Q |
7.999 | 1.436 | tNET | RR | 1 | R53C54[0][A] | u_dsi_rx/u_dsi_csi2/wHeader_19_s1/I0 |
8.578 | 0.579 | tINS | RR | 2 | R53C54[0][A] | u_dsi_rx/u_dsi_csi2/wHeader_19_s1/F |
8.753 | 0.175 | tNET | RR | 1 | R54C54[3][B] | u_dsi_rx/u_dsi_csi2/wHeader_3_s0/I0 |
9.044 | 0.291 | tINS | RR | 5 | R54C54[3][B] | u_dsi_rx/u_dsi_csi2/wHeader_3_s0/F |
10.435 | 1.391 | tNET | RR | 1 | R56C55[2][B] | u_dsi_rx/u_dsi_csi2/n1188_s8/I2 |
11.003 | 0.567 | tINS | RR | 1 | R56C55[2][B] | u_dsi_rx/u_dsi_csi2/n1188_s8/F |
11.005 | 0.003 | tNET | RR | 1 | R56C55[1][B] | u_dsi_rx/u_dsi_csi2/n1188_s4/I1 |
11.584 | 0.579 | tINS | RR | 2 | R56C55[1][B] | u_dsi_rx/u_dsi_csi2/n1188_s4/F |
12.369 | 0.785 | tNET | RR | 1 | R56C66[3][B] | u_dsi_rx/u_dsi_csi2/n1188_s1/I2 |
12.825 | 0.456 | tINS | RR | 32 | R56C66[3][B] | u_dsi_rx/u_dsi_csi2/n1188_s1/F |
14.568 | 1.743 | tNET | RR | 1 | R53C63[1][A] | u_dsi_rx/u_dsi_csi2/rHeader_13_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.524 | 9.524 | active clock edge time | ||||
9.524 | 0.000 | byte_clk | ||||
9.524 | 0.000 | tCL | RR | 578 | QUAD[0] | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
15.689 | 6.165 | tNET | RR | 1 | R53C63[1][A] | u_dsi_rx/u_dsi_csi2/rHeader_13_s0/CLK |
15.378 | -0.311 | tSu | 1 | R53C63[1][A] | u_dsi_rx/u_dsi_csi2/rHeader_13_s0 |
Path Statistics:
Clock Skew | -0.015 |
Setup Relationship | 9.524 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 6.180, 100.000% |
Arrival Data Path Delay | cell: 2.473, 29.478%; route: 5.533, 65.961%; tC2Q: 0.382, 4.560% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 6.165, 100.000% |
Path4
Path Summary:
Slack | 0.810 |
Data Arrival Time | 14.568 |
Data Required Time | 15.378 |
From | u_dsi_rx/u_dsi_csi2/rData_3_s0 |
To | u_dsi_rx/u_dsi_csi2/rHeader_14_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 578 | QUAD[0] | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
6.180 | 6.180 | tNET | RR | 1 | R51C53[0][B] | u_dsi_rx/u_dsi_csi2/rData_3_s0/CLK |
6.563 | 0.382 | tC2Q | RR | 7 | R51C53[0][B] | u_dsi_rx/u_dsi_csi2/rData_3_s0/Q |
7.999 | 1.436 | tNET | RR | 1 | R53C54[0][A] | u_dsi_rx/u_dsi_csi2/wHeader_19_s1/I0 |
8.578 | 0.579 | tINS | RR | 2 | R53C54[0][A] | u_dsi_rx/u_dsi_csi2/wHeader_19_s1/F |
8.753 | 0.175 | tNET | RR | 1 | R54C54[3][B] | u_dsi_rx/u_dsi_csi2/wHeader_3_s0/I0 |
9.044 | 0.291 | tINS | RR | 5 | R54C54[3][B] | u_dsi_rx/u_dsi_csi2/wHeader_3_s0/F |
10.435 | 1.391 | tNET | RR | 1 | R56C55[2][B] | u_dsi_rx/u_dsi_csi2/n1188_s8/I2 |
11.003 | 0.567 | tINS | RR | 1 | R56C55[2][B] | u_dsi_rx/u_dsi_csi2/n1188_s8/F |
11.005 | 0.003 | tNET | RR | 1 | R56C55[1][B] | u_dsi_rx/u_dsi_csi2/n1188_s4/I1 |
11.584 | 0.579 | tINS | RR | 2 | R56C55[1][B] | u_dsi_rx/u_dsi_csi2/n1188_s4/F |
12.369 | 0.785 | tNET | RR | 1 | R56C66[3][B] | u_dsi_rx/u_dsi_csi2/n1188_s1/I2 |
12.825 | 0.456 | tINS | RR | 32 | R56C66[3][B] | u_dsi_rx/u_dsi_csi2/n1188_s1/F |
14.568 | 1.743 | tNET | RR | 1 | R53C63[2][A] | u_dsi_rx/u_dsi_csi2/rHeader_14_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.524 | 9.524 | active clock edge time | ||||
9.524 | 0.000 | byte_clk | ||||
9.524 | 0.000 | tCL | RR | 578 | QUAD[0] | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
15.689 | 6.165 | tNET | RR | 1 | R53C63[2][A] | u_dsi_rx/u_dsi_csi2/rHeader_14_s0/CLK |
15.378 | -0.311 | tSu | 1 | R53C63[2][A] | u_dsi_rx/u_dsi_csi2/rHeader_14_s0 |
Path Statistics:
Clock Skew | -0.015 |
Setup Relationship | 9.524 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 6.180, 100.000% |
Arrival Data Path Delay | cell: 2.473, 29.478%; route: 5.533, 65.961%; tC2Q: 0.382, 4.560% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 6.165, 100.000% |
Path5
Path Summary:
Slack | 0.810 |
Data Arrival Time | 14.568 |
Data Required Time | 15.378 |
From | u_dsi_rx/u_dsi_csi2/rData_3_s0 |
To | u_dsi_rx/u_dsi_csi2/rHeader_17_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 578 | QUAD[0] | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
6.180 | 6.180 | tNET | RR | 1 | R51C53[0][B] | u_dsi_rx/u_dsi_csi2/rData_3_s0/CLK |
6.563 | 0.382 | tC2Q | RR | 7 | R51C53[0][B] | u_dsi_rx/u_dsi_csi2/rData_3_s0/Q |
7.999 | 1.436 | tNET | RR | 1 | R53C54[0][A] | u_dsi_rx/u_dsi_csi2/wHeader_19_s1/I0 |
8.578 | 0.579 | tINS | RR | 2 | R53C54[0][A] | u_dsi_rx/u_dsi_csi2/wHeader_19_s1/F |
8.753 | 0.175 | tNET | RR | 1 | R54C54[3][B] | u_dsi_rx/u_dsi_csi2/wHeader_3_s0/I0 |
9.044 | 0.291 | tINS | RR | 5 | R54C54[3][B] | u_dsi_rx/u_dsi_csi2/wHeader_3_s0/F |
10.435 | 1.391 | tNET | RR | 1 | R56C55[2][B] | u_dsi_rx/u_dsi_csi2/n1188_s8/I2 |
11.003 | 0.567 | tINS | RR | 1 | R56C55[2][B] | u_dsi_rx/u_dsi_csi2/n1188_s8/F |
11.005 | 0.003 | tNET | RR | 1 | R56C55[1][B] | u_dsi_rx/u_dsi_csi2/n1188_s4/I1 |
11.584 | 0.579 | tINS | RR | 2 | R56C55[1][B] | u_dsi_rx/u_dsi_csi2/n1188_s4/F |
12.369 | 0.785 | tNET | RR | 1 | R56C66[3][B] | u_dsi_rx/u_dsi_csi2/n1188_s1/I2 |
12.825 | 0.456 | tINS | RR | 32 | R56C66[3][B] | u_dsi_rx/u_dsi_csi2/n1188_s1/F |
14.568 | 1.743 | tNET | RR | 1 | R53C63[1][B] | u_dsi_rx/u_dsi_csi2/rHeader_17_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.524 | 9.524 | active clock edge time | ||||
9.524 | 0.000 | byte_clk | ||||
9.524 | 0.000 | tCL | RR | 578 | QUAD[0] | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
15.689 | 6.165 | tNET | RR | 1 | R53C63[1][B] | u_dsi_rx/u_dsi_csi2/rHeader_17_s0/CLK |
15.378 | -0.311 | tSu | 1 | R53C63[1][B] | u_dsi_rx/u_dsi_csi2/rHeader_17_s0 |
Path Statistics:
Clock Skew | -0.015 |
Setup Relationship | 9.524 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 6.180, 100.000% |
Arrival Data Path Delay | cell: 2.473, 29.478%; route: 5.533, 65.961%; tC2Q: 0.382, 4.560% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 6.165, 100.000% |
Path6
Path Summary:
Slack | 0.810 |
Data Arrival Time | 14.568 |
Data Required Time | 15.378 |
From | u_dsi_rx/u_dsi_csi2/rData_3_s0 |
To | u_dsi_rx/u_dsi_csi2/rHeader_20_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 578 | QUAD[0] | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
6.180 | 6.180 | tNET | RR | 1 | R51C53[0][B] | u_dsi_rx/u_dsi_csi2/rData_3_s0/CLK |
6.563 | 0.382 | tC2Q | RR | 7 | R51C53[0][B] | u_dsi_rx/u_dsi_csi2/rData_3_s0/Q |
7.999 | 1.436 | tNET | RR | 1 | R53C54[0][A] | u_dsi_rx/u_dsi_csi2/wHeader_19_s1/I0 |
8.578 | 0.579 | tINS | RR | 2 | R53C54[0][A] | u_dsi_rx/u_dsi_csi2/wHeader_19_s1/F |
8.753 | 0.175 | tNET | RR | 1 | R54C54[3][B] | u_dsi_rx/u_dsi_csi2/wHeader_3_s0/I0 |
9.044 | 0.291 | tINS | RR | 5 | R54C54[3][B] | u_dsi_rx/u_dsi_csi2/wHeader_3_s0/F |
10.435 | 1.391 | tNET | RR | 1 | R56C55[2][B] | u_dsi_rx/u_dsi_csi2/n1188_s8/I2 |
11.003 | 0.567 | tINS | RR | 1 | R56C55[2][B] | u_dsi_rx/u_dsi_csi2/n1188_s8/F |
11.005 | 0.003 | tNET | RR | 1 | R56C55[1][B] | u_dsi_rx/u_dsi_csi2/n1188_s4/I1 |
11.584 | 0.579 | tINS | RR | 2 | R56C55[1][B] | u_dsi_rx/u_dsi_csi2/n1188_s4/F |
12.369 | 0.785 | tNET | RR | 1 | R56C66[3][B] | u_dsi_rx/u_dsi_csi2/n1188_s1/I2 |
12.825 | 0.456 | tINS | RR | 32 | R56C66[3][B] | u_dsi_rx/u_dsi_csi2/n1188_s1/F |
14.568 | 1.743 | tNET | RR | 1 | R53C63[2][B] | u_dsi_rx/u_dsi_csi2/rHeader_20_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.524 | 9.524 | active clock edge time | ||||
9.524 | 0.000 | byte_clk | ||||
9.524 | 0.000 | tCL | RR | 578 | QUAD[0] | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
15.689 | 6.165 | tNET | RR | 1 | R53C63[2][B] | u_dsi_rx/u_dsi_csi2/rHeader_20_s0/CLK |
15.378 | -0.311 | tSu | 1 | R53C63[2][B] | u_dsi_rx/u_dsi_csi2/rHeader_20_s0 |
Path Statistics:
Clock Skew | -0.015 |
Setup Relationship | 9.524 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 6.180, 100.000% |
Arrival Data Path Delay | cell: 2.473, 29.478%; route: 5.533, 65.961%; tC2Q: 0.382, 4.560% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 6.165, 100.000% |
Path7
Path Summary:
Slack | 0.810 |
Data Arrival Time | 14.568 |
Data Required Time | 15.378 |
From | u_dsi_rx/u_dsi_csi2/rData_3_s0 |
To | u_dsi_rx/u_dsi_csi2/rHeader_22_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 578 | QUAD[0] | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
6.180 | 6.180 | tNET | RR | 1 | R51C53[0][B] | u_dsi_rx/u_dsi_csi2/rData_3_s0/CLK |
6.563 | 0.382 | tC2Q | RR | 7 | R51C53[0][B] | u_dsi_rx/u_dsi_csi2/rData_3_s0/Q |
7.999 | 1.436 | tNET | RR | 1 | R53C54[0][A] | u_dsi_rx/u_dsi_csi2/wHeader_19_s1/I0 |
8.578 | 0.579 | tINS | RR | 2 | R53C54[0][A] | u_dsi_rx/u_dsi_csi2/wHeader_19_s1/F |
8.753 | 0.175 | tNET | RR | 1 | R54C54[3][B] | u_dsi_rx/u_dsi_csi2/wHeader_3_s0/I0 |
9.044 | 0.291 | tINS | RR | 5 | R54C54[3][B] | u_dsi_rx/u_dsi_csi2/wHeader_3_s0/F |
10.435 | 1.391 | tNET | RR | 1 | R56C55[2][B] | u_dsi_rx/u_dsi_csi2/n1188_s8/I2 |
11.003 | 0.567 | tINS | RR | 1 | R56C55[2][B] | u_dsi_rx/u_dsi_csi2/n1188_s8/F |
11.005 | 0.003 | tNET | RR | 1 | R56C55[1][B] | u_dsi_rx/u_dsi_csi2/n1188_s4/I1 |
11.584 | 0.579 | tINS | RR | 2 | R56C55[1][B] | u_dsi_rx/u_dsi_csi2/n1188_s4/F |
12.369 | 0.785 | tNET | RR | 1 | R56C66[3][B] | u_dsi_rx/u_dsi_csi2/n1188_s1/I2 |
12.825 | 0.456 | tINS | RR | 32 | R56C66[3][B] | u_dsi_rx/u_dsi_csi2/n1188_s1/F |
14.568 | 1.743 | tNET | RR | 1 | R53C63[3][A] | u_dsi_rx/u_dsi_csi2/rHeader_22_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.524 | 9.524 | active clock edge time | ||||
9.524 | 0.000 | byte_clk | ||||
9.524 | 0.000 | tCL | RR | 578 | QUAD[0] | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
15.689 | 6.165 | tNET | RR | 1 | R53C63[3][A] | u_dsi_rx/u_dsi_csi2/rHeader_22_s0/CLK |
15.378 | -0.311 | tSu | 1 | R53C63[3][A] | u_dsi_rx/u_dsi_csi2/rHeader_22_s0 |
Path Statistics:
Clock Skew | -0.015 |
Setup Relationship | 9.524 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 6.180, 100.000% |
Arrival Data Path Delay | cell: 2.473, 29.478%; route: 5.533, 65.961%; tC2Q: 0.382, 4.560% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 6.165, 100.000% |
Path8
Path Summary:
Slack | 0.822 |
Data Arrival Time | 14.565 |
Data Required Time | 15.387 |
From | u_dsi_rx/u_dsi_csi2/rData_3_s0 |
To | u_dsi_rx/u_dsi_csi2/rHeader_18_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 578 | QUAD[0] | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
6.180 | 6.180 | tNET | RR | 1 | R51C53[0][B] | u_dsi_rx/u_dsi_csi2/rData_3_s0/CLK |
6.563 | 0.382 | tC2Q | RR | 7 | R51C53[0][B] | u_dsi_rx/u_dsi_csi2/rData_3_s0/Q |
7.999 | 1.436 | tNET | RR | 1 | R53C54[0][A] | u_dsi_rx/u_dsi_csi2/wHeader_19_s1/I0 |
8.578 | 0.579 | tINS | RR | 2 | R53C54[0][A] | u_dsi_rx/u_dsi_csi2/wHeader_19_s1/F |
8.753 | 0.175 | tNET | RR | 1 | R54C54[3][B] | u_dsi_rx/u_dsi_csi2/wHeader_3_s0/I0 |
9.044 | 0.291 | tINS | RR | 5 | R54C54[3][B] | u_dsi_rx/u_dsi_csi2/wHeader_3_s0/F |
10.435 | 1.391 | tNET | RR | 1 | R56C55[2][B] | u_dsi_rx/u_dsi_csi2/n1188_s8/I2 |
11.003 | 0.567 | tINS | RR | 1 | R56C55[2][B] | u_dsi_rx/u_dsi_csi2/n1188_s8/F |
11.005 | 0.003 | tNET | RR | 1 | R56C55[1][B] | u_dsi_rx/u_dsi_csi2/n1188_s4/I1 |
11.584 | 0.579 | tINS | RR | 2 | R56C55[1][B] | u_dsi_rx/u_dsi_csi2/n1188_s4/F |
12.369 | 0.785 | tNET | RR | 1 | R56C66[3][B] | u_dsi_rx/u_dsi_csi2/n1188_s1/I2 |
12.825 | 0.456 | tINS | RR | 32 | R56C66[3][B] | u_dsi_rx/u_dsi_csi2/n1188_s1/F |
14.565 | 1.740 | tNET | RR | 1 | R53C64[1][B] | u_dsi_rx/u_dsi_csi2/rHeader_18_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.524 | 9.524 | active clock edge time | ||||
9.524 | 0.000 | byte_clk | ||||
9.524 | 0.000 | tCL | RR | 578 | QUAD[0] | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
15.698 | 6.174 | tNET | RR | 1 | R53C64[1][B] | u_dsi_rx/u_dsi_csi2/rHeader_18_s0/CLK |
15.387 | -0.311 | tSu | 1 | R53C64[1][B] | u_dsi_rx/u_dsi_csi2/rHeader_18_s0 |
Path Statistics:
Clock Skew | -0.006 |
Setup Relationship | 9.524 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 6.180, 100.000% |
Arrival Data Path Delay | cell: 2.473, 29.487%; route: 5.530, 65.951%; tC2Q: 0.382, 4.562% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 6.174, 100.000% |
Path9
Path Summary:
Slack | 0.822 |
Data Arrival Time | 14.565 |
Data Required Time | 15.387 |
From | u_dsi_rx/u_dsi_csi2/rData_3_s0 |
To | u_dsi_rx/u_dsi_csi2/rHeader_19_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 578 | QUAD[0] | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
6.180 | 6.180 | tNET | RR | 1 | R51C53[0][B] | u_dsi_rx/u_dsi_csi2/rData_3_s0/CLK |
6.563 | 0.382 | tC2Q | RR | 7 | R51C53[0][B] | u_dsi_rx/u_dsi_csi2/rData_3_s0/Q |
7.999 | 1.436 | tNET | RR | 1 | R53C54[0][A] | u_dsi_rx/u_dsi_csi2/wHeader_19_s1/I0 |
8.578 | 0.579 | tINS | RR | 2 | R53C54[0][A] | u_dsi_rx/u_dsi_csi2/wHeader_19_s1/F |
8.753 | 0.175 | tNET | RR | 1 | R54C54[3][B] | u_dsi_rx/u_dsi_csi2/wHeader_3_s0/I0 |
9.044 | 0.291 | tINS | RR | 5 | R54C54[3][B] | u_dsi_rx/u_dsi_csi2/wHeader_3_s0/F |
10.435 | 1.391 | tNET | RR | 1 | R56C55[2][B] | u_dsi_rx/u_dsi_csi2/n1188_s8/I2 |
11.003 | 0.567 | tINS | RR | 1 | R56C55[2][B] | u_dsi_rx/u_dsi_csi2/n1188_s8/F |
11.005 | 0.003 | tNET | RR | 1 | R56C55[1][B] | u_dsi_rx/u_dsi_csi2/n1188_s4/I1 |
11.584 | 0.579 | tINS | RR | 2 | R56C55[1][B] | u_dsi_rx/u_dsi_csi2/n1188_s4/F |
12.369 | 0.785 | tNET | RR | 1 | R56C66[3][B] | u_dsi_rx/u_dsi_csi2/n1188_s1/I2 |
12.825 | 0.456 | tINS | RR | 32 | R56C66[3][B] | u_dsi_rx/u_dsi_csi2/n1188_s1/F |
14.565 | 1.740 | tNET | RR | 1 | R53C64[1][A] | u_dsi_rx/u_dsi_csi2/rHeader_19_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.524 | 9.524 | active clock edge time | ||||
9.524 | 0.000 | byte_clk | ||||
9.524 | 0.000 | tCL | RR | 578 | QUAD[0] | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
15.698 | 6.174 | tNET | RR | 1 | R53C64[1][A] | u_dsi_rx/u_dsi_csi2/rHeader_19_s0/CLK |
15.387 | -0.311 | tSu | 1 | R53C64[1][A] | u_dsi_rx/u_dsi_csi2/rHeader_19_s0 |
Path Statistics:
Clock Skew | -0.006 |
Setup Relationship | 9.524 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 6.180, 100.000% |
Arrival Data Path Delay | cell: 2.473, 29.487%; route: 5.530, 65.951%; tC2Q: 0.382, 4.562% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 6.174, 100.000% |
Path10
Path Summary:
Slack | 1.021 |
Data Arrival Time | 14.359 |
Data Required Time | 15.380 |
From | u_dsi_rx/u_dsi_csi2/rData_3_s0 |
To | u_dsi_rx/u_dsi_csi2/rHeader_21_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 578 | QUAD[0] | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
6.180 | 6.180 | tNET | RR | 1 | R51C53[0][B] | u_dsi_rx/u_dsi_csi2/rData_3_s0/CLK |
6.563 | 0.382 | tC2Q | RR | 7 | R51C53[0][B] | u_dsi_rx/u_dsi_csi2/rData_3_s0/Q |
7.999 | 1.436 | tNET | RR | 1 | R53C54[0][A] | u_dsi_rx/u_dsi_csi2/wHeader_19_s1/I0 |
8.578 | 0.579 | tINS | RR | 2 | R53C54[0][A] | u_dsi_rx/u_dsi_csi2/wHeader_19_s1/F |
8.753 | 0.175 | tNET | RR | 1 | R54C54[3][B] | u_dsi_rx/u_dsi_csi2/wHeader_3_s0/I0 |
9.044 | 0.291 | tINS | RR | 5 | R54C54[3][B] | u_dsi_rx/u_dsi_csi2/wHeader_3_s0/F |
10.435 | 1.391 | tNET | RR | 1 | R56C55[2][B] | u_dsi_rx/u_dsi_csi2/n1188_s8/I2 |
11.003 | 0.567 | tINS | RR | 1 | R56C55[2][B] | u_dsi_rx/u_dsi_csi2/n1188_s8/F |
11.005 | 0.003 | tNET | RR | 1 | R56C55[1][B] | u_dsi_rx/u_dsi_csi2/n1188_s4/I1 |
11.584 | 0.579 | tINS | RR | 2 | R56C55[1][B] | u_dsi_rx/u_dsi_csi2/n1188_s4/F |
12.369 | 0.785 | tNET | RR | 1 | R56C66[3][B] | u_dsi_rx/u_dsi_csi2/n1188_s1/I2 |
12.825 | 0.456 | tINS | RR | 32 | R56C66[3][B] | u_dsi_rx/u_dsi_csi2/n1188_s1/F |
14.359 | 1.534 | tNET | RR | 1 | R54C63[0][A] | u_dsi_rx/u_dsi_csi2/rHeader_21_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.524 | 9.524 | active clock edge time | ||||
9.524 | 0.000 | byte_clk | ||||
9.524 | 0.000 | tCL | RR | 578 | QUAD[0] | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
15.691 | 6.167 | tNET | RR | 1 | R54C63[0][A] | u_dsi_rx/u_dsi_csi2/rHeader_21_s0/CLK |
15.380 | -0.311 | tSu | 1 | R54C63[0][A] | u_dsi_rx/u_dsi_csi2/rHeader_21_s0 |
Path Statistics:
Clock Skew | -0.013 |
Setup Relationship | 9.524 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 6.180, 100.000% |
Arrival Data Path Delay | cell: 2.473, 30.231%; route: 5.324, 65.092%; tC2Q: 0.382, 4.677% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 6.167, 100.000% |
Path11
Path Summary:
Slack | 1.021 |
Data Arrival Time | 14.359 |
Data Required Time | 15.380 |
From | u_dsi_rx/u_dsi_csi2/rData_3_s0 |
To | u_dsi_rx/u_dsi_csi2/rHeader_23_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 578 | QUAD[0] | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
6.180 | 6.180 | tNET | RR | 1 | R51C53[0][B] | u_dsi_rx/u_dsi_csi2/rData_3_s0/CLK |
6.563 | 0.382 | tC2Q | RR | 7 | R51C53[0][B] | u_dsi_rx/u_dsi_csi2/rData_3_s0/Q |
7.999 | 1.436 | tNET | RR | 1 | R53C54[0][A] | u_dsi_rx/u_dsi_csi2/wHeader_19_s1/I0 |
8.578 | 0.579 | tINS | RR | 2 | R53C54[0][A] | u_dsi_rx/u_dsi_csi2/wHeader_19_s1/F |
8.753 | 0.175 | tNET | RR | 1 | R54C54[3][B] | u_dsi_rx/u_dsi_csi2/wHeader_3_s0/I0 |
9.044 | 0.291 | tINS | RR | 5 | R54C54[3][B] | u_dsi_rx/u_dsi_csi2/wHeader_3_s0/F |
10.435 | 1.391 | tNET | RR | 1 | R56C55[2][B] | u_dsi_rx/u_dsi_csi2/n1188_s8/I2 |
11.003 | 0.567 | tINS | RR | 1 | R56C55[2][B] | u_dsi_rx/u_dsi_csi2/n1188_s8/F |
11.005 | 0.003 | tNET | RR | 1 | R56C55[1][B] | u_dsi_rx/u_dsi_csi2/n1188_s4/I1 |
11.584 | 0.579 | tINS | RR | 2 | R56C55[1][B] | u_dsi_rx/u_dsi_csi2/n1188_s4/F |
12.369 | 0.785 | tNET | RR | 1 | R56C66[3][B] | u_dsi_rx/u_dsi_csi2/n1188_s1/I2 |
12.825 | 0.456 | tINS | RR | 32 | R56C66[3][B] | u_dsi_rx/u_dsi_csi2/n1188_s1/F |
14.359 | 1.534 | tNET | RR | 1 | R54C63[1][A] | u_dsi_rx/u_dsi_csi2/rHeader_23_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.524 | 9.524 | active clock edge time | ||||
9.524 | 0.000 | byte_clk | ||||
9.524 | 0.000 | tCL | RR | 578 | QUAD[0] | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
15.691 | 6.167 | tNET | RR | 1 | R54C63[1][A] | u_dsi_rx/u_dsi_csi2/rHeader_23_s0/CLK |
15.380 | -0.311 | tSu | 1 | R54C63[1][A] | u_dsi_rx/u_dsi_csi2/rHeader_23_s0 |
Path Statistics:
Clock Skew | -0.013 |
Setup Relationship | 9.524 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 6.180, 100.000% |
Arrival Data Path Delay | cell: 2.473, 30.231%; route: 5.324, 65.092%; tC2Q: 0.382, 4.677% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 6.167, 100.000% |
Path12
Path Summary:
Slack | 1.036 |
Data Arrival Time | 14.351 |
Data Required Time | 15.387 |
From | u_dsi_rx/u_dsi_csi2/rData_3_s0 |
To | u_dsi_rx/u_dsi_csi2/rHeader_6_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 578 | QUAD[0] | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
6.180 | 6.180 | tNET | RR | 1 | R51C53[0][B] | u_dsi_rx/u_dsi_csi2/rData_3_s0/CLK |
6.563 | 0.382 | tC2Q | RR | 7 | R51C53[0][B] | u_dsi_rx/u_dsi_csi2/rData_3_s0/Q |
7.999 | 1.436 | tNET | RR | 1 | R53C54[0][A] | u_dsi_rx/u_dsi_csi2/wHeader_19_s1/I0 |
8.578 | 0.579 | tINS | RR | 2 | R53C54[0][A] | u_dsi_rx/u_dsi_csi2/wHeader_19_s1/F |
8.753 | 0.175 | tNET | RR | 1 | R54C54[3][B] | u_dsi_rx/u_dsi_csi2/wHeader_3_s0/I0 |
9.044 | 0.291 | tINS | RR | 5 | R54C54[3][B] | u_dsi_rx/u_dsi_csi2/wHeader_3_s0/F |
10.435 | 1.391 | tNET | RR | 1 | R56C55[2][B] | u_dsi_rx/u_dsi_csi2/n1188_s8/I2 |
11.003 | 0.567 | tINS | RR | 1 | R56C55[2][B] | u_dsi_rx/u_dsi_csi2/n1188_s8/F |
11.005 | 0.003 | tNET | RR | 1 | R56C55[1][B] | u_dsi_rx/u_dsi_csi2/n1188_s4/I1 |
11.584 | 0.579 | tINS | RR | 2 | R56C55[1][B] | u_dsi_rx/u_dsi_csi2/n1188_s4/F |
12.369 | 0.785 | tNET | RR | 1 | R56C66[3][B] | u_dsi_rx/u_dsi_csi2/n1188_s1/I2 |
12.825 | 0.456 | tINS | RR | 32 | R56C66[3][B] | u_dsi_rx/u_dsi_csi2/n1188_s1/F |
14.351 | 1.526 | tNET | RR | 1 | R53C62[0][A] | u_dsi_rx/u_dsi_csi2/rHeader_6_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.524 | 9.524 | active clock edge time | ||||
9.524 | 0.000 | byte_clk | ||||
9.524 | 0.000 | tCL | RR | 578 | QUAD[0] | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
15.698 | 6.174 | tNET | RR | 1 | R53C62[0][A] | u_dsi_rx/u_dsi_csi2/rHeader_6_s0/CLK |
15.387 | -0.311 | tSu | 1 | R53C62[0][A] | u_dsi_rx/u_dsi_csi2/rHeader_6_s0 |
Path Statistics:
Clock Skew | -0.006 |
Setup Relationship | 9.524 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 6.180, 100.000% |
Arrival Data Path Delay | cell: 2.473, 30.259%; route: 5.316, 65.060%; tC2Q: 0.382, 4.681% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 6.174, 100.000% |
Path13
Path Summary:
Slack | 1.042 |
Data Arrival Time | 14.356 |
Data Required Time | 15.398 |
From | u_dsi_rx/u_dsi_csi2/rData_3_s0 |
To | u_dsi_rx/u_dsi_csi2/rHeader_27_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 578 | QUAD[0] | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
6.180 | 6.180 | tNET | RR | 1 | R51C53[0][B] | u_dsi_rx/u_dsi_csi2/rData_3_s0/CLK |
6.563 | 0.382 | tC2Q | RR | 7 | R51C53[0][B] | u_dsi_rx/u_dsi_csi2/rData_3_s0/Q |
7.999 | 1.436 | tNET | RR | 1 | R53C54[0][A] | u_dsi_rx/u_dsi_csi2/wHeader_19_s1/I0 |
8.578 | 0.579 | tINS | RR | 2 | R53C54[0][A] | u_dsi_rx/u_dsi_csi2/wHeader_19_s1/F |
8.753 | 0.175 | tNET | RR | 1 | R54C54[3][B] | u_dsi_rx/u_dsi_csi2/wHeader_3_s0/I0 |
9.044 | 0.291 | tINS | RR | 5 | R54C54[3][B] | u_dsi_rx/u_dsi_csi2/wHeader_3_s0/F |
10.435 | 1.391 | tNET | RR | 1 | R56C55[2][B] | u_dsi_rx/u_dsi_csi2/n1188_s8/I2 |
11.003 | 0.567 | tINS | RR | 1 | R56C55[2][B] | u_dsi_rx/u_dsi_csi2/n1188_s8/F |
11.005 | 0.003 | tNET | RR | 1 | R56C55[1][B] | u_dsi_rx/u_dsi_csi2/n1188_s4/I1 |
11.584 | 0.579 | tINS | RR | 2 | R56C55[1][B] | u_dsi_rx/u_dsi_csi2/n1188_s4/F |
12.369 | 0.785 | tNET | RR | 1 | R56C66[3][B] | u_dsi_rx/u_dsi_csi2/n1188_s1/I2 |
12.825 | 0.456 | tINS | RR | 32 | R56C66[3][B] | u_dsi_rx/u_dsi_csi2/n1188_s1/F |
14.356 | 1.531 | tNET | RR | 1 | R54C61[2][B] | u_dsi_rx/u_dsi_csi2/rHeader_27_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.524 | 9.524 | active clock edge time | ||||
9.524 | 0.000 | byte_clk | ||||
9.524 | 0.000 | tCL | RR | 578 | QUAD[0] | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
15.710 | 6.186 | tNET | RR | 1 | R54C61[2][B] | u_dsi_rx/u_dsi_csi2/rHeader_27_s0/CLK |
15.398 | -0.311 | tSu | 1 | R54C61[2][B] | u_dsi_rx/u_dsi_csi2/rHeader_27_s0 |
Path Statistics:
Clock Skew | 0.006 |
Setup Relationship | 9.524 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 6.180, 100.000% |
Arrival Data Path Delay | cell: 2.473, 30.240%; route: 5.321, 65.082%; tC2Q: 0.382, 4.678% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 6.186, 100.000% |
Path14
Path Summary:
Slack | 1.042 |
Data Arrival Time | 14.356 |
Data Required Time | 15.398 |
From | u_dsi_rx/u_dsi_csi2/rData_3_s0 |
To | u_dsi_rx/u_dsi_csi2/rHeader_29_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 578 | QUAD[0] | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
6.180 | 6.180 | tNET | RR | 1 | R51C53[0][B] | u_dsi_rx/u_dsi_csi2/rData_3_s0/CLK |
6.563 | 0.382 | tC2Q | RR | 7 | R51C53[0][B] | u_dsi_rx/u_dsi_csi2/rData_3_s0/Q |
7.999 | 1.436 | tNET | RR | 1 | R53C54[0][A] | u_dsi_rx/u_dsi_csi2/wHeader_19_s1/I0 |
8.578 | 0.579 | tINS | RR | 2 | R53C54[0][A] | u_dsi_rx/u_dsi_csi2/wHeader_19_s1/F |
8.753 | 0.175 | tNET | RR | 1 | R54C54[3][B] | u_dsi_rx/u_dsi_csi2/wHeader_3_s0/I0 |
9.044 | 0.291 | tINS | RR | 5 | R54C54[3][B] | u_dsi_rx/u_dsi_csi2/wHeader_3_s0/F |
10.435 | 1.391 | tNET | RR | 1 | R56C55[2][B] | u_dsi_rx/u_dsi_csi2/n1188_s8/I2 |
11.003 | 0.567 | tINS | RR | 1 | R56C55[2][B] | u_dsi_rx/u_dsi_csi2/n1188_s8/F |
11.005 | 0.003 | tNET | RR | 1 | R56C55[1][B] | u_dsi_rx/u_dsi_csi2/n1188_s4/I1 |
11.584 | 0.579 | tINS | RR | 2 | R56C55[1][B] | u_dsi_rx/u_dsi_csi2/n1188_s4/F |
12.369 | 0.785 | tNET | RR | 1 | R56C66[3][B] | u_dsi_rx/u_dsi_csi2/n1188_s1/I2 |
12.825 | 0.456 | tINS | RR | 32 | R56C66[3][B] | u_dsi_rx/u_dsi_csi2/n1188_s1/F |
14.356 | 1.531 | tNET | RR | 1 | R54C61[1][A] | u_dsi_rx/u_dsi_csi2/rHeader_29_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.524 | 9.524 | active clock edge time | ||||
9.524 | 0.000 | byte_clk | ||||
9.524 | 0.000 | tCL | RR | 578 | QUAD[0] | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
15.710 | 6.186 | tNET | RR | 1 | R54C61[1][A] | u_dsi_rx/u_dsi_csi2/rHeader_29_s0/CLK |
15.398 | -0.311 | tSu | 1 | R54C61[1][A] | u_dsi_rx/u_dsi_csi2/rHeader_29_s0 |
Path Statistics:
Clock Skew | 0.006 |
Setup Relationship | 9.524 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 6.180, 100.000% |
Arrival Data Path Delay | cell: 2.473, 30.240%; route: 5.321, 65.082%; tC2Q: 0.382, 4.678% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 6.186, 100.000% |
Path15
Path Summary:
Slack | 1.247 |
Data Arrival Time | 14.142 |
Data Required Time | 15.389 |
From | u_dsi_rx/u_dsi_csi2/rData_3_s0 |
To | u_dsi_rx/u_dsi_csi2/rHeader_24_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 578 | QUAD[0] | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
6.180 | 6.180 | tNET | RR | 1 | R51C53[0][B] | u_dsi_rx/u_dsi_csi2/rData_3_s0/CLK |
6.563 | 0.382 | tC2Q | RR | 7 | R51C53[0][B] | u_dsi_rx/u_dsi_csi2/rData_3_s0/Q |
7.999 | 1.436 | tNET | RR | 1 | R53C54[0][A] | u_dsi_rx/u_dsi_csi2/wHeader_19_s1/I0 |
8.578 | 0.579 | tINS | RR | 2 | R53C54[0][A] | u_dsi_rx/u_dsi_csi2/wHeader_19_s1/F |
8.753 | 0.175 | tNET | RR | 1 | R54C54[3][B] | u_dsi_rx/u_dsi_csi2/wHeader_3_s0/I0 |
9.044 | 0.291 | tINS | RR | 5 | R54C54[3][B] | u_dsi_rx/u_dsi_csi2/wHeader_3_s0/F |
10.435 | 1.391 | tNET | RR | 1 | R56C55[2][B] | u_dsi_rx/u_dsi_csi2/n1188_s8/I2 |
11.003 | 0.567 | tINS | RR | 1 | R56C55[2][B] | u_dsi_rx/u_dsi_csi2/n1188_s8/F |
11.005 | 0.003 | tNET | RR | 1 | R56C55[1][B] | u_dsi_rx/u_dsi_csi2/n1188_s4/I1 |
11.584 | 0.579 | tINS | RR | 2 | R56C55[1][B] | u_dsi_rx/u_dsi_csi2/n1188_s4/F |
12.369 | 0.785 | tNET | RR | 1 | R56C66[3][B] | u_dsi_rx/u_dsi_csi2/n1188_s1/I2 |
12.825 | 0.456 | tINS | RR | 32 | R56C66[3][B] | u_dsi_rx/u_dsi_csi2/n1188_s1/F |
14.143 | 1.317 | tNET | RR | 1 | R54C62[3][A] | u_dsi_rx/u_dsi_csi2/rHeader_24_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.524 | 9.524 | active clock edge time | ||||
9.524 | 0.000 | byte_clk | ||||
9.524 | 0.000 | tCL | RR | 578 | QUAD[0] | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
15.700 | 6.176 | tNET | RR | 1 | R54C62[3][A] | u_dsi_rx/u_dsi_csi2/rHeader_24_s0/CLK |
15.389 | -0.311 | tSu | 1 | R54C62[3][A] | u_dsi_rx/u_dsi_csi2/rHeader_24_s0 |
Path Statistics:
Clock Skew | -0.004 |
Setup Relationship | 9.524 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 6.180, 100.000% |
Arrival Data Path Delay | cell: 2.473, 31.052%; route: 5.108, 64.144%; tC2Q: 0.382, 4.804% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 6.176, 100.000% |
Path16
Path Summary:
Slack | 1.247 |
Data Arrival Time | 14.142 |
Data Required Time | 15.389 |
From | u_dsi_rx/u_dsi_csi2/rData_3_s0 |
To | u_dsi_rx/u_dsi_csi2/rHeader_26_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 578 | QUAD[0] | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
6.180 | 6.180 | tNET | RR | 1 | R51C53[0][B] | u_dsi_rx/u_dsi_csi2/rData_3_s0/CLK |
6.563 | 0.382 | tC2Q | RR | 7 | R51C53[0][B] | u_dsi_rx/u_dsi_csi2/rData_3_s0/Q |
7.999 | 1.436 | tNET | RR | 1 | R53C54[0][A] | u_dsi_rx/u_dsi_csi2/wHeader_19_s1/I0 |
8.578 | 0.579 | tINS | RR | 2 | R53C54[0][A] | u_dsi_rx/u_dsi_csi2/wHeader_19_s1/F |
8.753 | 0.175 | tNET | RR | 1 | R54C54[3][B] | u_dsi_rx/u_dsi_csi2/wHeader_3_s0/I0 |
9.044 | 0.291 | tINS | RR | 5 | R54C54[3][B] | u_dsi_rx/u_dsi_csi2/wHeader_3_s0/F |
10.435 | 1.391 | tNET | RR | 1 | R56C55[2][B] | u_dsi_rx/u_dsi_csi2/n1188_s8/I2 |
11.003 | 0.567 | tINS | RR | 1 | R56C55[2][B] | u_dsi_rx/u_dsi_csi2/n1188_s8/F |
11.005 | 0.003 | tNET | RR | 1 | R56C55[1][B] | u_dsi_rx/u_dsi_csi2/n1188_s4/I1 |
11.584 | 0.579 | tINS | RR | 2 | R56C55[1][B] | u_dsi_rx/u_dsi_csi2/n1188_s4/F |
12.369 | 0.785 | tNET | RR | 1 | R56C66[3][B] | u_dsi_rx/u_dsi_csi2/n1188_s1/I2 |
12.825 | 0.456 | tINS | RR | 32 | R56C66[3][B] | u_dsi_rx/u_dsi_csi2/n1188_s1/F |
14.143 | 1.317 | tNET | RR | 1 | R54C62[0][A] | u_dsi_rx/u_dsi_csi2/rHeader_26_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.524 | 9.524 | active clock edge time | ||||
9.524 | 0.000 | byte_clk | ||||
9.524 | 0.000 | tCL | RR | 578 | QUAD[0] | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
15.700 | 6.176 | tNET | RR | 1 | R54C62[0][A] | u_dsi_rx/u_dsi_csi2/rHeader_26_s0/CLK |
15.389 | -0.311 | tSu | 1 | R54C62[0][A] | u_dsi_rx/u_dsi_csi2/rHeader_26_s0 |
Path Statistics:
Clock Skew | -0.004 |
Setup Relationship | 9.524 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 6.180, 100.000% |
Arrival Data Path Delay | cell: 2.473, 31.052%; route: 5.108, 64.144%; tC2Q: 0.382, 4.804% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 6.176, 100.000% |
Path17
Path Summary:
Slack | 1.247 |
Data Arrival Time | 14.142 |
Data Required Time | 15.389 |
From | u_dsi_rx/u_dsi_csi2/rData_3_s0 |
To | u_dsi_rx/u_dsi_csi2/rHeader_28_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 578 | QUAD[0] | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
6.180 | 6.180 | tNET | RR | 1 | R51C53[0][B] | u_dsi_rx/u_dsi_csi2/rData_3_s0/CLK |
6.563 | 0.382 | tC2Q | RR | 7 | R51C53[0][B] | u_dsi_rx/u_dsi_csi2/rData_3_s0/Q |
7.999 | 1.436 | tNET | RR | 1 | R53C54[0][A] | u_dsi_rx/u_dsi_csi2/wHeader_19_s1/I0 |
8.578 | 0.579 | tINS | RR | 2 | R53C54[0][A] | u_dsi_rx/u_dsi_csi2/wHeader_19_s1/F |
8.753 | 0.175 | tNET | RR | 1 | R54C54[3][B] | u_dsi_rx/u_dsi_csi2/wHeader_3_s0/I0 |
9.044 | 0.291 | tINS | RR | 5 | R54C54[3][B] | u_dsi_rx/u_dsi_csi2/wHeader_3_s0/F |
10.435 | 1.391 | tNET | RR | 1 | R56C55[2][B] | u_dsi_rx/u_dsi_csi2/n1188_s8/I2 |
11.003 | 0.567 | tINS | RR | 1 | R56C55[2][B] | u_dsi_rx/u_dsi_csi2/n1188_s8/F |
11.005 | 0.003 | tNET | RR | 1 | R56C55[1][B] | u_dsi_rx/u_dsi_csi2/n1188_s4/I1 |
11.584 | 0.579 | tINS | RR | 2 | R56C55[1][B] | u_dsi_rx/u_dsi_csi2/n1188_s4/F |
12.369 | 0.785 | tNET | RR | 1 | R56C66[3][B] | u_dsi_rx/u_dsi_csi2/n1188_s1/I2 |
12.825 | 0.456 | tINS | RR | 32 | R56C66[3][B] | u_dsi_rx/u_dsi_csi2/n1188_s1/F |
14.143 | 1.317 | tNET | RR | 1 | R54C62[0][B] | u_dsi_rx/u_dsi_csi2/rHeader_28_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.524 | 9.524 | active clock edge time | ||||
9.524 | 0.000 | byte_clk | ||||
9.524 | 0.000 | tCL | RR | 578 | QUAD[0] | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
15.700 | 6.176 | tNET | RR | 1 | R54C62[0][B] | u_dsi_rx/u_dsi_csi2/rHeader_28_s0/CLK |
15.389 | -0.311 | tSu | 1 | R54C62[0][B] | u_dsi_rx/u_dsi_csi2/rHeader_28_s0 |
Path Statistics:
Clock Skew | -0.004 |
Setup Relationship | 9.524 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 6.180, 100.000% |
Arrival Data Path Delay | cell: 2.473, 31.052%; route: 5.108, 64.144%; tC2Q: 0.382, 4.804% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 6.176, 100.000% |
Path18
Path Summary:
Slack | 1.247 |
Data Arrival Time | 14.142 |
Data Required Time | 15.389 |
From | u_dsi_rx/u_dsi_csi2/rData_3_s0 |
To | u_dsi_rx/u_dsi_csi2/rHeader_31_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 578 | QUAD[0] | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
6.180 | 6.180 | tNET | RR | 1 | R51C53[0][B] | u_dsi_rx/u_dsi_csi2/rData_3_s0/CLK |
6.563 | 0.382 | tC2Q | RR | 7 | R51C53[0][B] | u_dsi_rx/u_dsi_csi2/rData_3_s0/Q |
7.999 | 1.436 | tNET | RR | 1 | R53C54[0][A] | u_dsi_rx/u_dsi_csi2/wHeader_19_s1/I0 |
8.578 | 0.579 | tINS | RR | 2 | R53C54[0][A] | u_dsi_rx/u_dsi_csi2/wHeader_19_s1/F |
8.753 | 0.175 | tNET | RR | 1 | R54C54[3][B] | u_dsi_rx/u_dsi_csi2/wHeader_3_s0/I0 |
9.044 | 0.291 | tINS | RR | 5 | R54C54[3][B] | u_dsi_rx/u_dsi_csi2/wHeader_3_s0/F |
10.435 | 1.391 | tNET | RR | 1 | R56C55[2][B] | u_dsi_rx/u_dsi_csi2/n1188_s8/I2 |
11.003 | 0.567 | tINS | RR | 1 | R56C55[2][B] | u_dsi_rx/u_dsi_csi2/n1188_s8/F |
11.005 | 0.003 | tNET | RR | 1 | R56C55[1][B] | u_dsi_rx/u_dsi_csi2/n1188_s4/I1 |
11.584 | 0.579 | tINS | RR | 2 | R56C55[1][B] | u_dsi_rx/u_dsi_csi2/n1188_s4/F |
12.369 | 0.785 | tNET | RR | 1 | R56C66[3][B] | u_dsi_rx/u_dsi_csi2/n1188_s1/I2 |
12.825 | 0.456 | tINS | RR | 32 | R56C66[3][B] | u_dsi_rx/u_dsi_csi2/n1188_s1/F |
14.143 | 1.317 | tNET | RR | 1 | R54C62[2][A] | u_dsi_rx/u_dsi_csi2/rHeader_31_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.524 | 9.524 | active clock edge time | ||||
9.524 | 0.000 | byte_clk | ||||
9.524 | 0.000 | tCL | RR | 578 | QUAD[0] | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
15.700 | 6.176 | tNET | RR | 1 | R54C62[2][A] | u_dsi_rx/u_dsi_csi2/rHeader_31_s0/CLK |
15.389 | -0.311 | tSu | 1 | R54C62[2][A] | u_dsi_rx/u_dsi_csi2/rHeader_31_s0 |
Path Statistics:
Clock Skew | -0.004 |
Setup Relationship | 9.524 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 6.180, 100.000% |
Arrival Data Path Delay | cell: 2.473, 31.052%; route: 5.108, 64.144%; tC2Q: 0.382, 4.804% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 6.176, 100.000% |
Path19
Path Summary:
Slack | 1.423 |
Data Arrival Time | 13.955 |
Data Required Time | 15.378 |
From | u_dsi_rx/u_dsi_csi2/rData_3_s0 |
To | u_dsi_rx/u_dsi_csi2/rHeader_11_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 578 | QUAD[0] | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
6.180 | 6.180 | tNET | RR | 1 | R51C53[0][B] | u_dsi_rx/u_dsi_csi2/rData_3_s0/CLK |
6.563 | 0.382 | tC2Q | RR | 7 | R51C53[0][B] | u_dsi_rx/u_dsi_csi2/rData_3_s0/Q |
7.999 | 1.436 | tNET | RR | 1 | R53C54[0][A] | u_dsi_rx/u_dsi_csi2/wHeader_19_s1/I0 |
8.578 | 0.579 | tINS | RR | 2 | R53C54[0][A] | u_dsi_rx/u_dsi_csi2/wHeader_19_s1/F |
8.753 | 0.175 | tNET | RR | 1 | R54C54[3][B] | u_dsi_rx/u_dsi_csi2/wHeader_3_s0/I0 |
9.044 | 0.291 | tINS | RR | 5 | R54C54[3][B] | u_dsi_rx/u_dsi_csi2/wHeader_3_s0/F |
10.435 | 1.391 | tNET | RR | 1 | R56C55[2][B] | u_dsi_rx/u_dsi_csi2/n1188_s8/I2 |
11.003 | 0.567 | tINS | RR | 1 | R56C55[2][B] | u_dsi_rx/u_dsi_csi2/n1188_s8/F |
11.005 | 0.003 | tNET | RR | 1 | R56C55[1][B] | u_dsi_rx/u_dsi_csi2/n1188_s4/I1 |
11.584 | 0.579 | tINS | RR | 2 | R56C55[1][B] | u_dsi_rx/u_dsi_csi2/n1188_s4/F |
12.369 | 0.785 | tNET | RR | 1 | R56C66[3][B] | u_dsi_rx/u_dsi_csi2/n1188_s1/I2 |
12.825 | 0.456 | tINS | RR | 32 | R56C66[3][B] | u_dsi_rx/u_dsi_csi2/n1188_s1/F |
13.955 | 1.130 | tNET | RR | 1 | R53C67[0][B] | u_dsi_rx/u_dsi_csi2/rHeader_11_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.524 | 9.524 | active clock edge time | ||||
9.524 | 0.000 | byte_clk | ||||
9.524 | 0.000 | tCL | RR | 578 | QUAD[0] | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
15.689 | 6.165 | tNET | RR | 1 | R53C67[0][B] | u_dsi_rx/u_dsi_csi2/rHeader_11_s0/CLK |
15.378 | -0.311 | tSu | 1 | R53C67[0][B] | u_dsi_rx/u_dsi_csi2/rHeader_11_s0 |
Path Statistics:
Clock Skew | -0.015 |
Setup Relationship | 9.524 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 6.180, 100.000% |
Arrival Data Path Delay | cell: 2.473, 31.801%; route: 4.920, 63.280%; tC2Q: 0.382, 4.920% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 6.165, 100.000% |
Path20
Path Summary:
Slack | 1.602 |
Data Arrival Time | 13.831 |
Data Required Time | 15.433 |
From | u_dsi_rx/u_dsi_csi2/rData_3_s0 |
To | u_dsi_rx/u_dsi_csi2/rHeader_25_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 578 | QUAD[0] | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
6.180 | 6.180 | tNET | RR | 1 | R51C53[0][B] | u_dsi_rx/u_dsi_csi2/rData_3_s0/CLK |
6.563 | 0.382 | tC2Q | RR | 7 | R51C53[0][B] | u_dsi_rx/u_dsi_csi2/rData_3_s0/Q |
7.999 | 1.436 | tNET | RR | 1 | R53C54[0][A] | u_dsi_rx/u_dsi_csi2/wHeader_19_s1/I0 |
8.578 | 0.579 | tINS | RR | 2 | R53C54[0][A] | u_dsi_rx/u_dsi_csi2/wHeader_19_s1/F |
8.753 | 0.175 | tNET | RR | 1 | R54C54[3][B] | u_dsi_rx/u_dsi_csi2/wHeader_3_s0/I0 |
9.044 | 0.291 | tINS | RR | 5 | R54C54[3][B] | u_dsi_rx/u_dsi_csi2/wHeader_3_s0/F |
10.435 | 1.391 | tNET | RR | 1 | R56C55[2][B] | u_dsi_rx/u_dsi_csi2/n1188_s8/I2 |
11.003 | 0.567 | tINS | RR | 1 | R56C55[2][B] | u_dsi_rx/u_dsi_csi2/n1188_s8/F |
11.005 | 0.003 | tNET | RR | 1 | R56C55[1][B] | u_dsi_rx/u_dsi_csi2/n1188_s4/I1 |
11.584 | 0.579 | tINS | RR | 2 | R56C55[1][B] | u_dsi_rx/u_dsi_csi2/n1188_s4/F |
12.369 | 0.785 | tNET | RR | 1 | R56C66[3][B] | u_dsi_rx/u_dsi_csi2/n1188_s1/I2 |
12.825 | 0.456 | tINS | RR | 32 | R56C66[3][B] | u_dsi_rx/u_dsi_csi2/n1188_s1/F |
13.831 | 1.006 | tNET | RR | 1 | R56C61[1][B] | u_dsi_rx/u_dsi_csi2/rHeader_25_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.524 | 9.524 | active clock edge time | ||||
9.524 | 0.000 | byte_clk | ||||
9.524 | 0.000 | tCL | RR | 578 | QUAD[0] | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
15.744 | 6.220 | tNET | RR | 1 | R56C61[1][B] | u_dsi_rx/u_dsi_csi2/rHeader_25_s0/CLK |
15.433 | -0.311 | tSu | 1 | R56C61[1][B] | u_dsi_rx/u_dsi_csi2/rHeader_25_s0 |
Path Statistics:
Clock Skew | 0.040 |
Setup Relationship | 9.524 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 6.180, 100.000% |
Arrival Data Path Delay | cell: 2.473, 32.315%; route: 4.796, 62.686%; tC2Q: 0.382, 4.999% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 6.220, 100.000% |
Setup Analysis Report[3]:
Report Command:report_timing -setup -from_clock [get_clocks {lvds_pclk}] -max_paths 20 -max_common_paths 1
Path1
Path Summary:
Slack | 0.391 |
Data Arrival Time | 9.604 |
Data Required Time | 9.995 |
From | u_extr/buf_ra_1_s0 |
To | u_extr/mem_data_mem_data_0_1_s |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_R[3] | u_pll_50m/PLL_inst/CLKOUT1 |
2.659 | 2.659 | tNET | RR | 1 | R53C123[2][A] | u_extr/buf_ra_1_s0/CLK |
3.042 | 0.382 | tC2Q | RR | 5 | R53C123[2][A] | u_extr/buf_ra_1_s0/Q |
3.973 | 0.931 | tNET | RR | 1 | R56C124[3][B] | u_extr/n882_s4/I1 |
4.521 | 0.548 | tINS | RR | 5 | R56C124[3][B] | u_extr/n882_s4/F |
4.539 | 0.019 | tNET | RR | 1 | R56C124[2][B] | u_extr/n880_s4/I2 |
5.118 | 0.579 | tINS | RR | 3 | R56C124[2][B] | u_extr/n880_s4/F |
5.296 | 0.177 | tNET | RR | 1 | R56C123[3][A] | u_extr/n877_s4/I3 |
5.869 | 0.574 | tINS | RR | 3 | R56C123[3][A] | u_extr/n877_s4/F |
5.874 | 0.005 | tNET | RR | 1 | R56C123[2][A] | u_extr/buf_ra_9_s11/I2 |
6.382 | 0.507 | tINS | RR | 2 | R56C123[2][A] | u_extr/buf_ra_9_s11/F |
6.557 | 0.175 | tNET | RR | 1 | R57C123[3][B] | u_extr/buf_ra_c_9_s1/I0 |
6.848 | 0.291 | tINS | RR | 12 | R57C123[3][B] | u_extr/buf_ra_c_9_s1/F |
9.604 | 2.756 | tNET | RR | 1 | BSRAM_R46[24] | u_extr/mem_data_mem_data_0_1_s/ADB[10] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.368 | 7.368 | active clock edge time | ||||
7.368 | 0.000 | lvds_pclk | ||||
7.368 | 0.000 | tCL | RR | 165 | PLL_R[3] | u_pll_50m/PLL_inst/CLKOUT1 |
10.030 | 2.662 | tNET | RR | 1 | BSRAM_R46[24] | u_extr/mem_data_mem_data_0_1_s/CLKB |
9.995 | -0.035 | tSu | 1 | BSRAM_R46[24] | u_extr/mem_data_mem_data_0_1_s |
Path Statistics:
Clock Skew | 0.002 |
Setup Relationship | 7.368 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.659, 100.000% |
Arrival Data Path Delay | cell: 2.499, 35.979%; route: 4.064, 58.513%; tC2Q: 0.382, 5.508% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.662, 100.000% |
Path2
Path Summary:
Slack | 0.394 |
Data Arrival Time | 9.592 |
Data Required Time | 9.986 |
From | u_extr/buf_ra_1_s0 |
To | u_extr/mem_data_mem_data_0_7_s |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_R[3] | u_pll_50m/PLL_inst/CLKOUT1 |
2.659 | 2.659 | tNET | RR | 1 | R53C123[2][A] | u_extr/buf_ra_1_s0/CLK |
3.042 | 0.382 | tC2Q | RR | 5 | R53C123[2][A] | u_extr/buf_ra_1_s0/Q |
3.973 | 0.931 | tNET | RR | 1 | R56C124[3][B] | u_extr/n882_s4/I1 |
4.521 | 0.548 | tINS | RR | 5 | R56C124[3][B] | u_extr/n882_s4/F |
4.539 | 0.019 | tNET | RR | 1 | R56C124[2][B] | u_extr/n880_s4/I2 |
5.118 | 0.579 | tINS | RR | 3 | R56C124[2][B] | u_extr/n880_s4/F |
5.296 | 0.177 | tNET | RR | 1 | R56C123[3][A] | u_extr/n877_s4/I3 |
5.869 | 0.574 | tINS | RR | 3 | R56C123[3][A] | u_extr/n877_s4/F |
6.047 | 0.177 | tNET | RR | 1 | R56C122[3][B] | u_extr/n876_s2/I1 |
6.621 | 0.574 | tINS | RR | 3 | R56C122[3][B] | u_extr/n876_s2/F |
7.377 | 0.756 | tNET | RR | 1 | R54C122[3][B] | u_extr/buf_ra_c_10_s0/I1 |
7.924 | 0.548 | tINS | RR | 12 | R54C122[3][B] | u_extr/buf_ra_c_10_s0/F |
9.592 | 1.667 | tNET | RR | 1 | BSRAM_R46[26] | u_extr/mem_data_mem_data_0_7_s/ADB[11] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.368 | 7.368 | active clock edge time | ||||
7.368 | 0.000 | lvds_pclk | ||||
7.368 | 0.000 | tCL | RR | 165 | PLL_R[3] | u_pll_50m/PLL_inst/CLKOUT1 |
10.021 | 2.652 | tNET | RR | 1 | BSRAM_R46[26] | u_extr/mem_data_mem_data_0_7_s/CLKB |
9.986 | -0.035 | tSu | 1 | BSRAM_R46[26] | u_extr/mem_data_mem_data_0_7_s |
Path Statistics:
Clock Skew | -0.007 |
Setup Relationship | 7.368 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.659, 100.000% |
Arrival Data Path Delay | cell: 2.821, 40.696%; route: 3.729, 53.787%; tC2Q: 0.382, 5.517% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.652, 100.000% |
Path3
Path Summary:
Slack | 0.426 |
Data Arrival Time | 9.569 |
Data Required Time | 9.995 |
From | u_extr/buf_ra_1_s0 |
To | u_extr/mem_data_mem_data_0_2_s |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_R[3] | u_pll_50m/PLL_inst/CLKOUT1 |
2.659 | 2.659 | tNET | RR | 1 | R53C123[2][A] | u_extr/buf_ra_1_s0/CLK |
3.042 | 0.382 | tC2Q | RR | 5 | R53C123[2][A] | u_extr/buf_ra_1_s0/Q |
3.973 | 0.931 | tNET | RR | 1 | R56C124[3][B] | u_extr/n882_s4/I1 |
4.521 | 0.548 | tINS | RR | 5 | R56C124[3][B] | u_extr/n882_s4/F |
5.289 | 0.769 | tNET | RR | 1 | R53C124[3][A] | u_extr/buf_ra_4_s12/I2 |
5.863 | 0.574 | tINS | RR | 2 | R53C124[3][A] | u_extr/buf_ra_4_s12/F |
5.868 | 0.005 | tNET | RR | 1 | R53C124[2][B] | u_extr/buf_ra_c_4_s1/I0 |
6.376 | 0.507 | tINS | RR | 12 | R53C124[2][B] | u_extr/buf_ra_c_4_s1/F |
9.569 | 3.194 | tNET | RR | 1 | BSRAM_R64[24] | u_extr/mem_data_mem_data_0_2_s/ADB[5] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.368 | 7.368 | active clock edge time | ||||
7.368 | 0.000 | lvds_pclk | ||||
7.368 | 0.000 | tCL | RR | 165 | PLL_R[3] | u_pll_50m/PLL_inst/CLKOUT1 |
10.030 | 2.662 | tNET | RR | 1 | BSRAM_R64[24] | u_extr/mem_data_mem_data_0_2_s/CLKB |
9.995 | -0.035 | tSu | 1 | BSRAM_R64[24] | u_extr/mem_data_mem_data_0_2_s |
Path Statistics:
Clock Skew | 0.002 |
Setup Relationship | 7.368 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.659, 100.000% |
Arrival Data Path Delay | cell: 1.629, 23.571%; route: 4.899, 70.894%; tC2Q: 0.382, 5.535% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.662, 100.000% |
Path4
Path Summary:
Slack | 0.582 |
Data Arrival Time | 9.423 |
Data Required Time | 10.005 |
From | u_extr/buf_ra_1_s0 |
To | u_extr/mem_data_mem_data_0_4_s |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_R[3] | u_pll_50m/PLL_inst/CLKOUT1 |
2.659 | 2.659 | tNET | RR | 1 | R53C123[2][A] | u_extr/buf_ra_1_s0/CLK |
3.042 | 0.382 | tC2Q | RR | 5 | R53C123[2][A] | u_extr/buf_ra_1_s0/Q |
3.973 | 0.931 | tNET | RR | 1 | R56C124[3][B] | u_extr/n882_s4/I1 |
4.521 | 0.548 | tINS | RR | 5 | R56C124[3][B] | u_extr/n882_s4/F |
4.539 | 0.019 | tNET | RR | 1 | R56C124[2][B] | u_extr/n880_s4/I2 |
5.118 | 0.579 | tINS | RR | 3 | R56C124[2][B] | u_extr/n880_s4/F |
5.296 | 0.177 | tNET | RR | 1 | R56C123[3][A] | u_extr/n877_s4/I3 |
5.869 | 0.574 | tINS | RR | 3 | R56C123[3][A] | u_extr/n877_s4/F |
6.047 | 0.177 | tNET | RR | 1 | R56C122[3][B] | u_extr/n876_s2/I1 |
6.621 | 0.574 | tINS | RR | 3 | R56C122[3][B] | u_extr/n876_s2/F |
7.377 | 0.756 | tNET | RR | 1 | R54C122[3][B] | u_extr/buf_ra_c_10_s0/I1 |
7.924 | 0.548 | tINS | RR | 12 | R54C122[3][B] | u_extr/buf_ra_c_10_s0/F |
9.423 | 1.499 | tNET | RR | 1 | BSRAM_R64[25][A] | u_extr/mem_data_mem_data_0_4_s/ADB[11] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.368 | 7.368 | active clock edge time | ||||
7.368 | 0.000 | lvds_pclk | ||||
7.368 | 0.000 | tCL | RR | 165 | PLL_R[3] | u_pll_50m/PLL_inst/CLKOUT1 |
10.039 | 2.671 | tNET | RR | 1 | BSRAM_R64[25][A] | u_extr/mem_data_mem_data_0_4_s/CLKB |
10.005 | -0.035 | tSu | 1 | BSRAM_R64[25][A] | u_extr/mem_data_mem_data_0_4_s |
Path Statistics:
Clock Skew | 0.012 |
Setup Relationship | 7.368 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.659, 100.000% |
Arrival Data Path Delay | cell: 2.821, 41.711%; route: 3.560, 52.634%; tC2Q: 0.382, 5.655% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.671, 100.000% |
Path5
Path Summary:
Slack | 0.630 |
Data Arrival Time | 9.356 |
Data Required Time | 9.986 |
From | u_extr/buf_ra_1_s0 |
To | u_extr/mem_data_mem_data_0_0_s |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_R[3] | u_pll_50m/PLL_inst/CLKOUT1 |
2.659 | 2.659 | tNET | RR | 1 | R53C123[2][A] | u_extr/buf_ra_1_s0/CLK |
3.042 | 0.382 | tC2Q | RR | 5 | R53C123[2][A] | u_extr/buf_ra_1_s0/Q |
3.973 | 0.931 | tNET | RR | 1 | R56C124[3][B] | u_extr/n882_s4/I1 |
4.521 | 0.548 | tINS | RR | 5 | R56C124[3][B] | u_extr/n882_s4/F |
4.539 | 0.019 | tNET | RR | 1 | R56C124[2][B] | u_extr/n880_s4/I2 |
5.118 | 0.579 | tINS | RR | 3 | R56C124[2][B] | u_extr/n880_s4/F |
5.296 | 0.177 | tNET | RR | 1 | R56C123[3][A] | u_extr/n877_s4/I3 |
5.869 | 0.574 | tINS | RR | 3 | R56C123[3][A] | u_extr/n877_s4/F |
6.047 | 0.177 | tNET | RR | 1 | R56C122[3][B] | u_extr/n876_s2/I1 |
6.621 | 0.574 | tINS | RR | 3 | R56C122[3][B] | u_extr/n876_s2/F |
7.377 | 0.756 | tNET | RR | 1 | R54C122[3][B] | u_extr/buf_ra_c_10_s0/I1 |
7.924 | 0.548 | tINS | RR | 12 | R54C122[3][B] | u_extr/buf_ra_c_10_s0/F |
9.356 | 1.431 | tNET | RR | 1 | BSRAM_R46[23][B] | u_extr/mem_data_mem_data_0_0_s/ADB[11] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.368 | 7.368 | active clock edge time | ||||
7.368 | 0.000 | lvds_pclk | ||||
7.368 | 0.000 | tCL | RR | 165 | PLL_R[3] | u_pll_50m/PLL_inst/CLKOUT1 |
10.021 | 2.652 | tNET | RR | 1 | BSRAM_R46[23][B] | u_extr/mem_data_mem_data_0_0_s/CLKB |
9.986 | -0.035 | tSu | 1 | BSRAM_R46[23][B] | u_extr/mem_data_mem_data_0_0_s |
Path Statistics:
Clock Skew | -0.007 |
Setup Relationship | 7.368 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.659, 100.000% |
Arrival Data Path Delay | cell: 2.821, 42.132%; route: 3.493, 52.156%; tC2Q: 0.382, 5.712% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.652, 100.000% |
Path6
Path Summary:
Slack | 0.710 |
Data Arrival Time | 9.286 |
Data Required Time | 9.995 |
From | u_extr/buf_ra_1_s0 |
To | u_extr/mem_data_mem_data_0_9_s |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_R[3] | u_pll_50m/PLL_inst/CLKOUT1 |
2.659 | 2.659 | tNET | RR | 1 | R53C123[2][A] | u_extr/buf_ra_1_s0/CLK |
3.042 | 0.382 | tC2Q | RR | 5 | R53C123[2][A] | u_extr/buf_ra_1_s0/Q |
3.973 | 0.931 | tNET | RR | 1 | R56C124[3][B] | u_extr/n882_s4/I1 |
4.521 | 0.548 | tINS | RR | 5 | R56C124[3][B] | u_extr/n882_s4/F |
4.539 | 0.019 | tNET | RR | 1 | R56C124[2][B] | u_extr/n880_s4/I2 |
5.118 | 0.579 | tINS | RR | 3 | R56C124[2][B] | u_extr/n880_s4/F |
5.296 | 0.177 | tNET | RR | 1 | R56C123[3][A] | u_extr/n877_s4/I3 |
5.869 | 0.574 | tINS | RR | 3 | R56C123[3][A] | u_extr/n877_s4/F |
6.047 | 0.177 | tNET | RR | 1 | R56C122[3][B] | u_extr/n876_s2/I1 |
6.621 | 0.574 | tINS | RR | 3 | R56C122[3][B] | u_extr/n876_s2/F |
7.377 | 0.756 | tNET | RR | 1 | R54C122[3][B] | u_extr/buf_ra_c_10_s0/I1 |
7.924 | 0.548 | tINS | RR | 12 | R54C122[3][B] | u_extr/buf_ra_c_10_s0/F |
9.286 | 1.361 | tNET | RR | 1 | BSRAM_R46[27][A] | u_extr/mem_data_mem_data_0_9_s/ADB[11] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.368 | 7.368 | active clock edge time | ||||
7.368 | 0.000 | lvds_pclk | ||||
7.368 | 0.000 | tCL | RR | 165 | PLL_R[3] | u_pll_50m/PLL_inst/CLKOUT1 |
10.030 | 2.662 | tNET | RR | 1 | BSRAM_R46[27][A] | u_extr/mem_data_mem_data_0_9_s/CLKB |
9.995 | -0.035 | tSu | 1 | BSRAM_R46[27][A] | u_extr/mem_data_mem_data_0_9_s |
Path Statistics:
Clock Skew | 0.002 |
Setup Relationship | 7.368 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.659, 100.000% |
Arrival Data Path Delay | cell: 2.821, 42.577%; route: 3.423, 51.651%; tC2Q: 0.382, 5.772% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.662, 100.000% |
Path7
Path Summary:
Slack | 0.722 |
Data Arrival Time | 9.283 |
Data Required Time | 10.005 |
From | u_extr/buf_ra_1_s0 |
To | u_extr/mem_data_mem_data_0_11_s |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_R[3] | u_pll_50m/PLL_inst/CLKOUT1 |
2.659 | 2.659 | tNET | RR | 1 | R53C123[2][A] | u_extr/buf_ra_1_s0/CLK |
3.042 | 0.382 | tC2Q | RR | 5 | R53C123[2][A] | u_extr/buf_ra_1_s0/Q |
3.973 | 0.931 | tNET | RR | 1 | R56C124[3][B] | u_extr/n882_s4/I1 |
4.521 | 0.548 | tINS | RR | 5 | R56C124[3][B] | u_extr/n882_s4/F |
4.539 | 0.019 | tNET | RR | 1 | R56C124[2][B] | u_extr/n880_s4/I2 |
5.118 | 0.579 | tINS | RR | 3 | R56C124[2][B] | u_extr/n880_s4/F |
5.296 | 0.177 | tNET | RR | 1 | R56C123[3][A] | u_extr/n877_s4/I3 |
5.869 | 0.574 | tINS | RR | 3 | R56C123[3][A] | u_extr/n877_s4/F |
6.047 | 0.177 | tNET | RR | 1 | R56C122[3][B] | u_extr/n876_s2/I1 |
6.621 | 0.574 | tINS | RR | 3 | R56C122[3][B] | u_extr/n876_s2/F |
7.377 | 0.756 | tNET | RR | 1 | R54C122[3][B] | u_extr/buf_ra_c_10_s0/I1 |
7.924 | 0.548 | tINS | RR | 12 | R54C122[3][B] | u_extr/buf_ra_c_10_s0/F |
9.283 | 1.359 | tNET | RR | 1 | BSRAM_R46[27][B] | u_extr/mem_data_mem_data_0_11_s/ADB[11] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.368 | 7.368 | active clock edge time | ||||
7.368 | 0.000 | lvds_pclk | ||||
7.368 | 0.000 | tCL | RR | 165 | PLL_R[3] | u_pll_50m/PLL_inst/CLKOUT1 |
10.039 | 2.671 | tNET | RR | 1 | BSRAM_R46[27][B] | u_extr/mem_data_mem_data_0_11_s/CLKB |
10.005 | -0.035 | tSu | 1 | BSRAM_R46[27][B] | u_extr/mem_data_mem_data_0_11_s |
Path Statistics:
Clock Skew | 0.012 |
Setup Relationship | 7.368 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.659, 100.000% |
Arrival Data Path Delay | cell: 2.821, 42.593%; route: 3.420, 51.632%; tC2Q: 0.382, 5.775% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.671, 100.000% |
Path8
Path Summary:
Slack | 0.725 |
Data Arrival Time | 9.271 |
Data Required Time | 9.995 |
From | u_extr/buf_ra_1_s0 |
To | u_extr/mem_data_mem_data_0_1_s |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_R[3] | u_pll_50m/PLL_inst/CLKOUT1 |
2.659 | 2.659 | tNET | RR | 1 | R53C123[2][A] | u_extr/buf_ra_1_s0/CLK |
3.042 | 0.382 | tC2Q | RR | 5 | R53C123[2][A] | u_extr/buf_ra_1_s0/Q |
3.973 | 0.931 | tNET | RR | 1 | R56C124[3][B] | u_extr/n882_s4/I1 |
4.521 | 0.548 | tINS | RR | 5 | R56C124[3][B] | u_extr/n882_s4/F |
4.539 | 0.019 | tNET | RR | 1 | R56C124[2][B] | u_extr/n880_s4/I2 |
5.118 | 0.579 | tINS | RR | 3 | R56C124[2][B] | u_extr/n880_s4/F |
5.296 | 0.177 | tNET | RR | 1 | R56C123[3][A] | u_extr/n877_s4/I3 |
5.869 | 0.574 | tINS | RR | 3 | R56C123[3][A] | u_extr/n877_s4/F |
6.047 | 0.177 | tNET | RR | 1 | R56C122[3][B] | u_extr/n876_s2/I1 |
6.621 | 0.574 | tINS | RR | 3 | R56C122[3][B] | u_extr/n876_s2/F |
7.377 | 0.756 | tNET | RR | 1 | R54C122[3][B] | u_extr/buf_ra_c_10_s0/I1 |
7.924 | 0.548 | tINS | RR | 12 | R54C122[3][B] | u_extr/buf_ra_c_10_s0/F |
9.271 | 1.346 | tNET | RR | 1 | BSRAM_R46[24] | u_extr/mem_data_mem_data_0_1_s/ADB[11] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.368 | 7.368 | active clock edge time | ||||
7.368 | 0.000 | lvds_pclk | ||||
7.368 | 0.000 | tCL | RR | 165 | PLL_R[3] | u_pll_50m/PLL_inst/CLKOUT1 |
10.030 | 2.662 | tNET | RR | 1 | BSRAM_R46[24] | u_extr/mem_data_mem_data_0_1_s/CLKB |
9.995 | -0.035 | tSu | 1 | BSRAM_R46[24] | u_extr/mem_data_mem_data_0_1_s |
Path Statistics:
Clock Skew | 0.002 |
Setup Relationship | 7.368 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.659, 100.000% |
Arrival Data Path Delay | cell: 2.821, 42.673%; route: 3.408, 51.541%; tC2Q: 0.382, 5.786% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.662, 100.000% |
Path9
Path Summary:
Slack | 0.746 |
Data Arrival Time | 9.249 |
Data Required Time | 9.995 |
From | u_extr/oworking_s0 |
To | u_extr/mem_data_mem_data_0_9_s |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_R[3] | u_pll_50m/PLL_inst/CLKOUT1 |
2.696 | 2.696 | tNET | RR | 1 | R56C125[1][A] | u_extr/oworking_s0/CLK |
3.078 | 0.382 | tC2Q | RR | 30 | R56C125[1][A] | u_extr/oworking_s0/Q |
3.704 | 0.626 | tNET | RR | 1 | R57C124[3][B] | u_extr/buf_ra_0_s11/I1 |
4.278 | 0.574 | tINS | RR | 17 | R57C124[3][B] | u_extr/buf_ra_0_s11/F |
5.796 | 1.518 | tNET | RR | 1 | R54C124[3][B] | u_extr/buf_ra_c_3_s1/I3 |
6.369 | 0.574 | tINS | RR | 12 | R54C124[3][B] | u_extr/buf_ra_c_3_s1/F |
9.249 | 2.880 | tNET | RR | 1 | BSRAM_R46[27][A] | u_extr/mem_data_mem_data_0_9_s/ADB[4] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.368 | 7.368 | active clock edge time | ||||
7.368 | 0.000 | lvds_pclk | ||||
7.368 | 0.000 | tCL | RR | 165 | PLL_R[3] | u_pll_50m/PLL_inst/CLKOUT1 |
10.030 | 2.662 | tNET | RR | 1 | BSRAM_R46[27][A] | u_extr/mem_data_mem_data_0_9_s/CLKB |
9.995 | -0.035 | tSu | 1 | BSRAM_R46[27][A] | u_extr/mem_data_mem_data_0_9_s |
Path Statistics:
Clock Skew | -0.034 |
Setup Relationship | 7.368 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.696, 100.000% |
Arrival Data Path Delay | cell: 1.148, 17.509%; route: 5.024, 76.655%; tC2Q: 0.382, 5.836% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.662, 100.000% |
Path10
Path Summary:
Slack | 0.750 |
Data Arrival Time | 9.246 |
Data Required Time | 9.995 |
From | u_extr/buf_ra_1_s0 |
To | u_extr/mem_data_mem_data_0_10_s |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_R[3] | u_pll_50m/PLL_inst/CLKOUT1 |
2.659 | 2.659 | tNET | RR | 1 | R53C123[2][A] | u_extr/buf_ra_1_s0/CLK |
3.042 | 0.382 | tC2Q | RR | 5 | R53C123[2][A] | u_extr/buf_ra_1_s0/Q |
3.973 | 0.931 | tNET | RR | 1 | R56C124[3][B] | u_extr/n882_s4/I1 |
4.521 | 0.548 | tINS | RR | 5 | R56C124[3][B] | u_extr/n882_s4/F |
4.539 | 0.019 | tNET | RR | 1 | R56C124[2][B] | u_extr/n880_s4/I2 |
5.118 | 0.579 | tINS | RR | 3 | R56C124[2][B] | u_extr/n880_s4/F |
5.296 | 0.177 | tNET | RR | 1 | R56C123[3][A] | u_extr/n877_s4/I3 |
5.869 | 0.574 | tINS | RR | 3 | R56C123[3][A] | u_extr/n877_s4/F |
6.047 | 0.177 | tNET | RR | 1 | R56C122[3][B] | u_extr/n876_s2/I1 |
6.621 | 0.574 | tINS | RR | 3 | R56C122[3][B] | u_extr/n876_s2/F |
7.377 | 0.756 | tNET | RR | 1 | R54C122[3][B] | u_extr/buf_ra_c_10_s0/I1 |
7.924 | 0.548 | tINS | RR | 12 | R54C122[3][B] | u_extr/buf_ra_c_10_s0/F |
9.246 | 1.321 | tNET | RR | 1 | BSRAM_R64[27][A] | u_extr/mem_data_mem_data_0_10_s/ADB[11] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.368 | 7.368 | active clock edge time | ||||
7.368 | 0.000 | lvds_pclk | ||||
7.368 | 0.000 | tCL | RR | 165 | PLL_R[3] | u_pll_50m/PLL_inst/CLKOUT1 |
10.030 | 2.662 | tNET | RR | 1 | BSRAM_R64[27][A] | u_extr/mem_data_mem_data_0_10_s/CLKB |
9.995 | -0.035 | tSu | 1 | BSRAM_R64[27][A] | u_extr/mem_data_mem_data_0_10_s |
Path Statistics:
Clock Skew | 0.002 |
Setup Relationship | 7.368 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.659, 100.000% |
Arrival Data Path Delay | cell: 2.821, 42.835%; route: 3.383, 51.357%; tC2Q: 0.382, 5.808% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.662, 100.000% |
Path11
Path Summary:
Slack | 0.751 |
Data Arrival Time | 9.244 |
Data Required Time | 9.995 |
From | u_extr/buf_ra_1_s0 |
To | u_extr/mem_data_mem_data_0_6_s |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_R[3] | u_pll_50m/PLL_inst/CLKOUT1 |
2.659 | 2.659 | tNET | RR | 1 | R53C123[2][A] | u_extr/buf_ra_1_s0/CLK |
3.042 | 0.382 | tC2Q | RR | 5 | R53C123[2][A] | u_extr/buf_ra_1_s0/Q |
3.973 | 0.931 | tNET | RR | 1 | R56C124[3][B] | u_extr/n882_s4/I1 |
4.521 | 0.548 | tINS | RR | 5 | R56C124[3][B] | u_extr/n882_s4/F |
5.289 | 0.769 | tNET | RR | 1 | R53C124[3][A] | u_extr/buf_ra_4_s12/I2 |
5.863 | 0.574 | tINS | RR | 2 | R53C124[3][A] | u_extr/buf_ra_4_s12/F |
5.868 | 0.005 | tNET | RR | 1 | R53C124[2][B] | u_extr/buf_ra_c_4_s1/I0 |
6.376 | 0.507 | tINS | RR | 12 | R53C124[2][B] | u_extr/buf_ra_c_4_s1/F |
9.244 | 2.869 | tNET | RR | 1 | BSRAM_R64[25][B] | u_extr/mem_data_mem_data_0_6_s/ADB[5] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.368 | 7.368 | active clock edge time | ||||
7.368 | 0.000 | lvds_pclk | ||||
7.368 | 0.000 | tCL | RR | 165 | PLL_R[3] | u_pll_50m/PLL_inst/CLKOUT1 |
10.030 | 2.662 | tNET | RR | 1 | BSRAM_R64[25][B] | u_extr/mem_data_mem_data_0_6_s/CLKB |
9.995 | -0.035 | tSu | 1 | BSRAM_R64[25][B] | u_extr/mem_data_mem_data_0_6_s |
Path Statistics:
Clock Skew | 0.002 |
Setup Relationship | 7.368 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.659, 100.000% |
Arrival Data Path Delay | cell: 1.629, 24.734%; route: 4.574, 69.457%; tC2Q: 0.382, 5.809% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.662, 100.000% |
Path12
Path Summary:
Slack | 0.778 |
Data Arrival Time | 9.208 |
Data Required Time | 9.986 |
From | u_extr/buf_ra_1_s0 |
To | u_extr/mem_data_mem_data_0_8_s |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_R[3] | u_pll_50m/PLL_inst/CLKOUT1 |
2.659 | 2.659 | tNET | RR | 1 | R53C123[2][A] | u_extr/buf_ra_1_s0/CLK |
3.042 | 0.382 | tC2Q | RR | 5 | R53C123[2][A] | u_extr/buf_ra_1_s0/Q |
3.973 | 0.931 | tNET | RR | 1 | R56C124[3][B] | u_extr/n882_s4/I1 |
4.521 | 0.548 | tINS | RR | 5 | R56C124[3][B] | u_extr/n882_s4/F |
4.539 | 0.019 | tNET | RR | 1 | R56C124[2][B] | u_extr/n880_s4/I2 |
5.118 | 0.579 | tINS | RR | 3 | R56C124[2][B] | u_extr/n880_s4/F |
5.296 | 0.177 | tNET | RR | 1 | R56C123[3][A] | u_extr/n877_s4/I3 |
5.869 | 0.574 | tINS | RR | 3 | R56C123[3][A] | u_extr/n877_s4/F |
6.047 | 0.177 | tNET | RR | 1 | R56C122[3][B] | u_extr/n876_s2/I1 |
6.621 | 0.574 | tINS | RR | 3 | R56C122[3][B] | u_extr/n876_s2/F |
7.377 | 0.756 | tNET | RR | 1 | R54C122[3][B] | u_extr/buf_ra_c_10_s0/I1 |
7.924 | 0.548 | tINS | RR | 12 | R54C122[3][B] | u_extr/buf_ra_c_10_s0/F |
9.208 | 1.284 | tNET | RR | 1 | BSRAM_R64[26] | u_extr/mem_data_mem_data_0_8_s/ADB[11] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.368 | 7.368 | active clock edge time | ||||
7.368 | 0.000 | lvds_pclk | ||||
7.368 | 0.000 | tCL | RR | 165 | PLL_R[3] | u_pll_50m/PLL_inst/CLKOUT1 |
10.021 | 2.652 | tNET | RR | 1 | BSRAM_R64[26] | u_extr/mem_data_mem_data_0_8_s/CLKB |
9.986 | -0.035 | tSu | 1 | BSRAM_R64[26] | u_extr/mem_data_mem_data_0_8_s |
Path Statistics:
Clock Skew | -0.007 |
Setup Relationship | 7.368 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.659, 100.000% |
Arrival Data Path Delay | cell: 2.821, 43.081%; route: 3.345, 51.078%; tC2Q: 0.382, 5.841% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.652, 100.000% |
Path13
Path Summary:
Slack | 0.802 |
Data Arrival Time | 9.193 |
Data Required Time | 9.995 |
From | u_extr/buf_ra_1_s0 |
To | u_extr/mem_data_mem_data_0_2_s |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_R[3] | u_pll_50m/PLL_inst/CLKOUT1 |
2.659 | 2.659 | tNET | RR | 1 | R53C123[2][A] | u_extr/buf_ra_1_s0/CLK |
3.042 | 0.382 | tC2Q | RR | 5 | R53C123[2][A] | u_extr/buf_ra_1_s0/Q |
3.973 | 0.931 | tNET | RR | 1 | R56C124[3][B] | u_extr/n882_s4/I1 |
4.521 | 0.548 | tINS | RR | 5 | R56C124[3][B] | u_extr/n882_s4/F |
4.539 | 0.019 | tNET | RR | 1 | R56C124[2][B] | u_extr/n880_s4/I2 |
5.118 | 0.579 | tINS | RR | 3 | R56C124[2][B] | u_extr/n880_s4/F |
5.296 | 0.177 | tNET | RR | 1 | R56C123[3][A] | u_extr/n877_s4/I3 |
5.869 | 0.574 | tINS | RR | 3 | R56C123[3][A] | u_extr/n877_s4/F |
6.047 | 0.177 | tNET | RR | 1 | R56C122[3][B] | u_extr/n876_s2/I1 |
6.621 | 0.574 | tINS | RR | 3 | R56C122[3][B] | u_extr/n876_s2/F |
7.377 | 0.756 | tNET | RR | 1 | R54C122[3][B] | u_extr/buf_ra_c_10_s0/I1 |
7.924 | 0.548 | tINS | RR | 12 | R54C122[3][B] | u_extr/buf_ra_c_10_s0/F |
9.193 | 1.269 | tNET | RR | 1 | BSRAM_R64[24] | u_extr/mem_data_mem_data_0_2_s/ADB[11] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.368 | 7.368 | active clock edge time | ||||
7.368 | 0.000 | lvds_pclk | ||||
7.368 | 0.000 | tCL | RR | 165 | PLL_R[3] | u_pll_50m/PLL_inst/CLKOUT1 |
10.030 | 2.662 | tNET | RR | 1 | BSRAM_R64[24] | u_extr/mem_data_mem_data_0_2_s/CLKB |
9.995 | -0.035 | tSu | 1 | BSRAM_R64[24] | u_extr/mem_data_mem_data_0_2_s |
Path Statistics:
Clock Skew | 0.002 |
Setup Relationship | 7.368 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.659, 100.000% |
Arrival Data Path Delay | cell: 2.821, 43.180%; route: 3.330, 50.966%; tC2Q: 0.382, 5.854% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.662, 100.000% |
Path14
Path Summary:
Slack | 0.860 |
Data Arrival Time | 9.136 |
Data Required Time | 9.995 |
From | u_extr/buf_ra_1_s0 |
To | u_extr/mem_data_mem_data_0_2_s |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_R[3] | u_pll_50m/PLL_inst/CLKOUT1 |
2.659 | 2.659 | tNET | RR | 1 | R53C123[2][A] | u_extr/buf_ra_1_s0/CLK |
3.042 | 0.382 | tC2Q | RR | 5 | R53C123[2][A] | u_extr/buf_ra_1_s0/Q |
3.973 | 0.931 | tNET | RR | 1 | R56C124[3][B] | u_extr/n882_s4/I1 |
4.521 | 0.548 | tINS | RR | 5 | R56C124[3][B] | u_extr/n882_s4/F |
4.539 | 0.019 | tNET | RR | 1 | R56C124[3][A] | u_extr/n880_s5/I3 |
5.087 | 0.548 | tINS | RR | 2 | R56C124[3][A] | u_extr/n880_s5/F |
6.051 | 0.964 | tNET | RR | 1 | R53C122[0][A] | u_extr/buf_ra_6_s11/I1 |
6.558 | 0.507 | tINS | RR | 2 | R53C122[0][A] | u_extr/buf_ra_6_s11/F |
6.733 | 0.175 | tNET | RR | 1 | R53C123[3][A] | u_extr/buf_ra_c_6_s1/I0 |
7.024 | 0.291 | tINS | RR | 12 | R53C123[3][A] | u_extr/buf_ra_c_6_s1/F |
9.136 | 2.111 | tNET | RR | 1 | BSRAM_R64[24] | u_extr/mem_data_mem_data_0_2_s/ADB[7] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.368 | 7.368 | active clock edge time | ||||
7.368 | 0.000 | lvds_pclk | ||||
7.368 | 0.000 | tCL | RR | 165 | PLL_R[3] | u_pll_50m/PLL_inst/CLKOUT1 |
10.030 | 2.662 | tNET | RR | 1 | BSRAM_R64[24] | u_extr/mem_data_mem_data_0_2_s/CLKB |
9.995 | -0.035 | tSu | 1 | BSRAM_R64[24] | u_extr/mem_data_mem_data_0_2_s |
Path Statistics:
Clock Skew | 0.002 |
Setup Relationship | 7.368 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.659, 100.000% |
Arrival Data Path Delay | cell: 1.894, 29.241%; route: 4.200, 64.852%; tC2Q: 0.382, 5.906% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.662, 100.000% |
Path15
Path Summary:
Slack | 0.931 |
Data Arrival Time | 9.064 |
Data Required Time | 9.995 |
From | u_extr/buf_ra_1_s0 |
To | u_extr/mem_data_mem_data_0_5_s |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_R[3] | u_pll_50m/PLL_inst/CLKOUT1 |
2.659 | 2.659 | tNET | RR | 1 | R53C123[2][A] | u_extr/buf_ra_1_s0/CLK |
3.042 | 0.382 | tC2Q | RR | 5 | R53C123[2][A] | u_extr/buf_ra_1_s0/Q |
3.973 | 0.931 | tNET | RR | 1 | R56C124[3][B] | u_extr/n882_s4/I1 |
4.521 | 0.548 | tINS | RR | 5 | R56C124[3][B] | u_extr/n882_s4/F |
4.539 | 0.019 | tNET | RR | 1 | R56C124[2][B] | u_extr/n880_s4/I2 |
5.118 | 0.579 | tINS | RR | 3 | R56C124[2][B] | u_extr/n880_s4/F |
5.296 | 0.177 | tNET | RR | 1 | R56C123[3][A] | u_extr/n877_s4/I3 |
5.869 | 0.574 | tINS | RR | 3 | R56C123[3][A] | u_extr/n877_s4/F |
6.047 | 0.177 | tNET | RR | 1 | R56C122[3][B] | u_extr/n876_s2/I1 |
6.621 | 0.574 | tINS | RR | 3 | R56C122[3][B] | u_extr/n876_s2/F |
7.377 | 0.756 | tNET | RR | 1 | R54C122[3][B] | u_extr/buf_ra_c_10_s0/I1 |
7.924 | 0.548 | tINS | RR | 12 | R54C122[3][B] | u_extr/buf_ra_c_10_s0/F |
9.064 | 1.140 | tNET | RR | 1 | BSRAM_R46[25][B] | u_extr/mem_data_mem_data_0_5_s/ADB[11] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.368 | 7.368 | active clock edge time | ||||
7.368 | 0.000 | lvds_pclk | ||||
7.368 | 0.000 | tCL | RR | 165 | PLL_R[3] | u_pll_50m/PLL_inst/CLKOUT1 |
10.030 | 2.662 | tNET | RR | 1 | BSRAM_R46[25][B] | u_extr/mem_data_mem_data_0_5_s/CLKB |
9.995 | -0.035 | tSu | 1 | BSRAM_R46[25][B] | u_extr/mem_data_mem_data_0_5_s |
Path Statistics:
Clock Skew | 0.002 |
Setup Relationship | 7.368 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.659, 100.000% |
Arrival Data Path Delay | cell: 2.821, 44.048%; route: 3.201, 49.980%; tC2Q: 0.382, 5.972% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.662, 100.000% |
Path16
Path Summary:
Slack | 0.931 |
Data Arrival Time | 8.921 |
Data Required Time | 9.852 |
From | u_extr/o_rgb_reg_13_s0 |
To | u_lvds_tx_left/LVDS_71_Tx/u_ODDR71_B1 |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_R[3] | u_pll_50m/PLL_inst/CLKOUT1 |
2.659 | 2.659 | tNET | RR | 1 | R53C129[1][A] | u_extr/o_rgb_reg_13_s0/CLK |
3.027 | 0.368 | tC2Q | RF | 1 | R53C129[1][A] | u_extr/o_rgb_reg_13_s0/Q |
8.921 | 5.894 | tNET | FF | 1 | IOR4[A] | u_lvds_tx_left/LVDS_71_Tx/u_ODDR71_B1/D4 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.368 | 7.368 | active clock edge time | ||||
7.368 | 0.000 | lvds_pclk | ||||
7.368 | 0.000 | tCL | RR | 165 | PLL_R[3] | u_pll_50m/PLL_inst/CLKOUT1 |
10.020 | 2.651 | tNET | RR | 1 | IOR4[A] | u_lvds_tx_left/LVDS_71_Tx/u_ODDR71_B1/PCLK |
9.852 | -0.168 | tSu | 1 | IOR4[A] | u_lvds_tx_left/LVDS_71_Tx/u_ODDR71_B1 |
Path Statistics:
Clock Skew | -0.008 |
Setup Relationship | 7.368 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.659, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 5.894, 94.131%; tC2Q: 0.368, 5.869% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.651, 100.000% |
Path17
Path Summary:
Slack | 0.934 |
Data Arrival Time | 8.921 |
Data Required Time | 9.855 |
From | u_extr/o_rgb_reg_12_s0 |
To | u_lvds_tx_left/LVDS_71_Tx/u_ODDR71_B1 |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_R[3] | u_pll_50m/PLL_inst/CLKOUT1 |
2.659 | 2.659 | tNET | RR | 1 | R53C129[1][B] | u_extr/o_rgb_reg_12_s0/CLK |
3.027 | 0.368 | tC2Q | RF | 1 | R53C129[1][B] | u_extr/o_rgb_reg_12_s0/Q |
8.921 | 5.894 | tNET | FF | 1 | IOR4[A] | u_lvds_tx_left/LVDS_71_Tx/u_ODDR71_B1/D5 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.368 | 7.368 | active clock edge time | ||||
7.368 | 0.000 | lvds_pclk | ||||
7.368 | 0.000 | tCL | RR | 165 | PLL_R[3] | u_pll_50m/PLL_inst/CLKOUT1 |
10.020 | 2.651 | tNET | RR | 1 | IOR4[A] | u_lvds_tx_left/LVDS_71_Tx/u_ODDR71_B1/PCLK |
9.855 | -0.165 | tSu | 1 | IOR4[A] | u_lvds_tx_left/LVDS_71_Tx/u_ODDR71_B1 |
Path Statistics:
Clock Skew | -0.008 |
Setup Relationship | 7.368 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.659, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 5.894, 94.131%; tC2Q: 0.368, 5.869% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.651, 100.000% |
Path18
Path Summary:
Slack | 0.946 |
Data Arrival Time | 9.049 |
Data Required Time | 9.995 |
From | u_extr/buf_ra_1_s0 |
To | u_extr/mem_data_mem_data_0_9_s |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_R[3] | u_pll_50m/PLL_inst/CLKOUT1 |
2.659 | 2.659 | tNET | RR | 1 | R53C123[2][A] | u_extr/buf_ra_1_s0/CLK |
3.042 | 0.382 | tC2Q | RR | 5 | R53C123[2][A] | u_extr/buf_ra_1_s0/Q |
3.973 | 0.931 | tNET | RR | 1 | R56C124[3][B] | u_extr/n882_s4/I1 |
4.521 | 0.548 | tINS | RR | 5 | R56C124[3][B] | u_extr/n882_s4/F |
4.539 | 0.019 | tNET | RR | 1 | R56C124[2][B] | u_extr/n880_s4/I2 |
5.118 | 0.579 | tINS | RR | 3 | R56C124[2][B] | u_extr/n880_s4/F |
5.296 | 0.177 | tNET | RR | 1 | R56C123[3][A] | u_extr/n877_s4/I3 |
5.869 | 0.574 | tINS | RR | 3 | R56C123[3][A] | u_extr/n877_s4/F |
5.874 | 0.005 | tNET | RR | 1 | R56C123[2][A] | u_extr/buf_ra_9_s11/I2 |
6.382 | 0.507 | tINS | RR | 2 | R56C123[2][A] | u_extr/buf_ra_9_s11/F |
6.557 | 0.175 | tNET | RR | 1 | R57C123[3][B] | u_extr/buf_ra_c_9_s1/I0 |
6.848 | 0.291 | tINS | RR | 12 | R57C123[3][B] | u_extr/buf_ra_c_9_s1/F |
9.049 | 2.201 | tNET | RR | 1 | BSRAM_R46[27][A] | u_extr/mem_data_mem_data_0_9_s/ADB[10] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.368 | 7.368 | active clock edge time | ||||
7.368 | 0.000 | lvds_pclk | ||||
7.368 | 0.000 | tCL | RR | 165 | PLL_R[3] | u_pll_50m/PLL_inst/CLKOUT1 |
10.030 | 2.662 | tNET | RR | 1 | BSRAM_R46[27][A] | u_extr/mem_data_mem_data_0_9_s/CLKB |
9.995 | -0.035 | tSu | 1 | BSRAM_R46[27][A] | u_extr/mem_data_mem_data_0_9_s |
Path Statistics:
Clock Skew | 0.002 |
Setup Relationship | 7.368 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.659, 100.000% |
Arrival Data Path Delay | cell: 2.499, 39.104%; route: 3.509, 54.910%; tC2Q: 0.382, 5.986% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.662, 100.000% |
Path19
Path Summary:
Slack | 0.955 |
Data Arrival Time | 9.041 |
Data Required Time | 9.995 |
From | u_extr/buf_ra_1_s0 |
To | u_extr/mem_data_mem_data_0_2_s |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_R[3] | u_pll_50m/PLL_inst/CLKOUT1 |
2.659 | 2.659 | tNET | RR | 1 | R53C123[2][A] | u_extr/buf_ra_1_s0/CLK |
3.042 | 0.382 | tC2Q | RR | 5 | R53C123[2][A] | u_extr/buf_ra_1_s0/Q |
3.973 | 0.931 | tNET | RR | 1 | R56C124[3][B] | u_extr/n882_s4/I1 |
4.521 | 0.548 | tINS | RR | 5 | R56C124[3][B] | u_extr/n882_s4/F |
4.539 | 0.019 | tNET | RR | 1 | R56C124[2][B] | u_extr/n880_s4/I2 |
5.118 | 0.579 | tINS | RR | 3 | R56C124[2][B] | u_extr/n880_s4/F |
5.296 | 0.177 | tNET | RR | 1 | R56C123[3][A] | u_extr/n877_s4/I3 |
5.869 | 0.574 | tINS | RR | 3 | R56C123[3][A] | u_extr/n877_s4/F |
5.874 | 0.005 | tNET | RR | 1 | R56C123[2][A] | u_extr/buf_ra_9_s11/I2 |
6.382 | 0.507 | tINS | RR | 2 | R56C123[2][A] | u_extr/buf_ra_9_s11/F |
6.557 | 0.175 | tNET | RR | 1 | R57C123[3][B] | u_extr/buf_ra_c_9_s1/I0 |
6.848 | 0.291 | tINS | RR | 12 | R57C123[3][B] | u_extr/buf_ra_c_9_s1/F |
9.041 | 2.193 | tNET | RR | 1 | BSRAM_R64[24] | u_extr/mem_data_mem_data_0_2_s/ADB[10] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.368 | 7.368 | active clock edge time | ||||
7.368 | 0.000 | lvds_pclk | ||||
7.368 | 0.000 | tCL | RR | 165 | PLL_R[3] | u_pll_50m/PLL_inst/CLKOUT1 |
10.030 | 2.662 | tNET | RR | 1 | BSRAM_R64[24] | u_extr/mem_data_mem_data_0_2_s/CLKB |
9.995 | -0.035 | tSu | 1 | BSRAM_R64[24] | u_extr/mem_data_mem_data_0_2_s |
Path Statistics:
Clock Skew | 0.002 |
Setup Relationship | 7.368 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.659, 100.000% |
Arrival Data Path Delay | cell: 2.499, 39.158%; route: 3.500, 54.848%; tC2Q: 0.382, 5.994% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.662, 100.000% |
Path20
Path Summary:
Slack | 0.955 |
Data Arrival Time | 9.033 |
Data Required Time | 9.988 |
From | u_extr/ovcnt_1_s1 |
To | u_extr/ohs_s0 |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_R[3] | u_pll_50m/PLL_inst/CLKOUT1 |
2.693 | 2.693 | tNET | RR | 1 | R57C131[0][B] | u_extr/ovcnt_1_s1/CLK |
3.076 | 0.382 | tC2Q | RR | 6 | R57C131[0][B] | u_extr/ovcnt_1_s1/Q |
3.571 | 0.495 | tNET | RR | 1 | R56C130[2][B] | u_extr/n793_s3/I1 |
4.149 | 0.579 | tINS | RR | 1 | R56C130[2][B] | u_extr/n793_s3/F |
4.568 | 0.419 | tNET | RR | 1 | R56C127[3][B] | u_extr/n787_s3/I3 |
5.142 | 0.574 | tINS | RR | 5 | R56C127[3][B] | u_extr/n787_s3/F |
6.071 | 0.929 | tNET | RR | 1 | R54C125[3][A] | u_extr/n783_s3/I3 |
6.644 | 0.574 | tINS | RR | 6 | R54C125[3][A] | u_extr/n783_s3/F |
7.993 | 1.349 | tNET | RR | 1 | R56C126[1][A] | u_extr/n846_s3/I2 |
8.572 | 0.579 | tINS | RR | 1 | R56C126[1][A] | u_extr/n846_s3/F |
8.744 | 0.172 | tNET | RR | 1 | R57C126[2][B] | u_extr/n846_s1/I3 |
9.033 | 0.289 | tINS | RR | 1 | R57C126[2][B] | u_extr/n846_s1/F |
9.033 | 0.000 | tNET | RR | 1 | R57C126[2][B] | u_extr/ohs_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.368 | 7.368 | active clock edge time | ||||
7.368 | 0.000 | lvds_pclk | ||||
7.368 | 0.000 | tCL | RR | 165 | PLL_R[3] | u_pll_50m/PLL_inst/CLKOUT1 |
10.052 | 2.684 | tNET | RR | 1 | R57C126[2][B] | u_extr/ohs_s0/CLK |
9.988 | -0.064 | tSu | 1 | R57C126[2][B] | u_extr/ohs_s0 |
Path Statistics:
Clock Skew | -0.009 |
Setup Relationship | 7.368 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.693, 100.000% |
Arrival Data Path Delay | cell: 2.594, 40.911%; route: 3.364, 53.056%; tC2Q: 0.382, 6.033% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.684, 100.000% |
Hold Analysis Report
Hold Analysis Report[1]:
Report Command:report_timing -hold -from_clock [get_clocks {pixel_clk}] -max_paths 20 -max_common_paths 1
Path1
Path Summary:
Slack | 0.266 |
Data Arrival Time | 1.793 |
Data Required Time | 1.528 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_24_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
1.308 | 1.308 | tNET | RR | 1 | R56C93[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_24_s0/CLK |
1.488 | 0.180 | tC2Q | RR | 1 | R56C93[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_24_s0/Q |
1.793 | 0.305 | tNET | RR | 1 | BSRAM_R64[19][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[0] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
1.279 | 1.279 | tNET | RR | 1 | BSRAM_R64[19][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA |
1.528 | 0.249 | tHld | 1 | BSRAM_R64[19][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s |
Path Statistics:
Clock Skew | -0.030 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.308, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.305, 62.887%; tC2Q: 0.180, 37.113% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.279, 100.000% |
Path2
Path Summary:
Slack | 0.268 |
Data Arrival Time | 1.791 |
Data Required Time | 1.523 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_10_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
1.303 | 1.303 | tNET | RR | 1 | R56C96[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_10_s0/CLK |
1.483 | 0.180 | tC2Q | RR | 1 | R56C96[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_10_s0/Q |
1.791 | 0.307 | tNET | RR | 1 | BSRAM_R64[19][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[2] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
1.274 | 1.274 | tNET | RR | 1 | BSRAM_R64[19][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA |
1.523 | 0.249 | tHld | 1 | BSRAM_R64[19][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Path Statistics:
Clock Skew | -0.030 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.303, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.307, 63.077%; tC2Q: 0.180, 36.923% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.274, 100.000% |
Path3
Path Summary:
Slack | 0.276 |
Data Arrival Time | 1.798 |
Data Required Time | 1.523 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_15_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
1.313 | 1.313 | tNET | RR | 1 | R56C94[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_15_s0/CLK |
1.493 | 0.180 | tC2Q | RR | 1 | R56C94[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_15_s0/Q |
1.798 | 0.305 | tNET | RR | 1 | BSRAM_R64[19][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[7] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
1.274 | 1.274 | tNET | RR | 1 | BSRAM_R64[19][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA |
1.523 | 0.249 | tHld | 1 | BSRAM_R64[19][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Path Statistics:
Clock Skew | -0.040 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.313, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.305, 62.887%; tC2Q: 0.180, 37.113% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.274, 100.000% |
Path4
Path Summary:
Slack | 0.276 |
Data Arrival Time | 1.798 |
Data Required Time | 1.523 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_14_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
1.313 | 1.313 | tNET | RR | 1 | R56C94[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_14_s0/CLK |
1.493 | 0.180 | tC2Q | RR | 1 | R56C94[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_14_s0/Q |
1.798 | 0.305 | tNET | RR | 1 | BSRAM_R64[19][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[6] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
1.274 | 1.274 | tNET | RR | 1 | BSRAM_R64[19][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA |
1.523 | 0.249 | tHld | 1 | BSRAM_R64[19][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Path Statistics:
Clock Skew | -0.040 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.313, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.305, 62.887%; tC2Q: 0.180, 37.113% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.274, 100.000% |
Path5
Path Summary:
Slack | 0.311 |
Data Arrival Time | 1.839 |
Data Required Time | 1.528 |
From | u_extr/buf_wd_7_s0 |
To | u_extr/mem_data_mem_data_0_3_s |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
1.278 | 1.278 | tNET | RR | 1 | R52C119[0][A] | u_extr/buf_wd_7_s0/CLK |
1.458 | 0.180 | tC2Q | RR | 1 | R52C119[0][A] | u_extr/buf_wd_7_s0/Q |
1.839 | 0.381 | tNET | RR | 1 | BSRAM_R46[25][A] | u_extr/mem_data_mem_data_0_3_s/DI[1] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
1.279 | 1.279 | tNET | RR | 1 | BSRAM_R46[25][A] | u_extr/mem_data_mem_data_0_3_s/CLKA |
1.528 | 0.249 | tHld | 1 | BSRAM_R46[25][A] | u_extr/mem_data_mem_data_0_3_s |
Path Statistics:
Clock Skew | 0.001 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.278, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.381, 67.929%; tC2Q: 0.180, 32.071% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.279, 100.000% |
Path6
Path Summary:
Slack | 0.311 |
Data Arrival Time | 1.839 |
Data Required Time | 1.528 |
From | u_extr/buf_wd_1_s0 |
To | u_extr/mem_data_mem_data_0_0_s |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
1.278 | 1.278 | tNET | RR | 1 | R52C113[0][A] | u_extr/buf_wd_1_s0/CLK |
1.458 | 0.180 | tC2Q | RR | 1 | R52C113[0][A] | u_extr/buf_wd_1_s0/Q |
1.839 | 0.381 | tNET | RR | 1 | BSRAM_R46[23][B] | u_extr/mem_data_mem_data_0_0_s/DI[1] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
1.279 | 1.279 | tNET | RR | 1 | BSRAM_R46[23][B] | u_extr/mem_data_mem_data_0_0_s/CLKA |
1.528 | 0.249 | tHld | 1 | BSRAM_R46[23][B] | u_extr/mem_data_mem_data_0_0_s |
Path Statistics:
Clock Skew | 0.001 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.278, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.381, 67.929%; tC2Q: 0.180, 32.071% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.279, 100.000% |
Path7
Path Summary:
Slack | 0.311 |
Data Arrival Time | 1.839 |
Data Required Time | 1.528 |
From | u_extr/buf_wd_0_s0 |
To | u_extr/mem_data_mem_data_0_0_s |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
1.278 | 1.278 | tNET | RR | 1 | R52C113[0][B] | u_extr/buf_wd_0_s0/CLK |
1.458 | 0.180 | tC2Q | RR | 1 | R52C113[0][B] | u_extr/buf_wd_0_s0/Q |
1.839 | 0.381 | tNET | RR | 1 | BSRAM_R46[23][B] | u_extr/mem_data_mem_data_0_0_s/DI[0] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
1.279 | 1.279 | tNET | RR | 1 | BSRAM_R46[23][B] | u_extr/mem_data_mem_data_0_0_s/CLKA |
1.528 | 0.249 | tHld | 1 | BSRAM_R46[23][B] | u_extr/mem_data_mem_data_0_0_s |
Path Statistics:
Clock Skew | 0.001 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.278, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.381, 67.929%; tC2Q: 0.180, 32.071% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.279, 100.000% |
Path8
Path Summary:
Slack | 0.359 |
Data Arrival Time | 1.887 |
Data Required Time | 1.528 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_26_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
1.308 | 1.308 | tNET | RR | 1 | R56C93[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_26_s0/CLK |
1.488 | 0.180 | tC2Q | RR | 1 | R56C93[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_26_s0/Q |
1.887 | 0.399 | tNET | RR | 1 | BSRAM_R64[19][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[2] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
1.279 | 1.279 | tNET | RR | 1 | BSRAM_R64[19][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA |
1.528 | 0.249 | tHld | 1 | BSRAM_R64[19][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s |
Path Statistics:
Clock Skew | -0.030 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.308, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.399, 68.898%; tC2Q: 0.180, 31.102% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.279, 100.000% |
Path9
Path Summary:
Slack | 0.359 |
Data Arrival Time | 1.887 |
Data Required Time | 1.528 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_25_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
1.308 | 1.308 | tNET | RR | 1 | R56C93[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_25_s0/CLK |
1.488 | 0.180 | tC2Q | RR | 1 | R56C93[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_25_s0/Q |
1.887 | 0.399 | tNET | RR | 1 | BSRAM_R64[19][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[1] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
1.279 | 1.279 | tNET | RR | 1 | BSRAM_R64[19][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA |
1.528 | 0.249 | tHld | 1 | BSRAM_R64[19][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s |
Path Statistics:
Clock Skew | -0.030 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.308, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.399, 68.898%; tC2Q: 0.180, 31.102% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.279, 100.000% |
Path10
Path Summary:
Slack | 0.374 |
Data Arrival Time | 1.653 |
Data Required Time | 1.279 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
1.278 | 1.278 | tNET | RR | 1 | R52C99[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLK |
1.454 | 0.176 | tC2Q | RF | 4 | R52C99[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/Q |
1.462 | 0.008 | tNET | FF | 1 | R52C99[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n258_s0/I2 |
1.653 | 0.191 | tINS | FF | 1 | R52C99[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n258_s0/F |
1.653 | 0.000 | tNET | FF | 1 | R52C99[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
1.278 | 1.278 | tNET | RR | 1 | R52C99[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLK |
1.279 | 0.001 | tHld | 1 | R52C99[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.278, 100.000% |
Arrival Data Path Delay | cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.278, 100.000% |
Path11
Path Summary:
Slack | 0.374 |
Data Arrival Time | 1.653 |
Data Required Time | 1.279 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_10_s1 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_10_s1 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
1.278 | 1.278 | tNET | RR | 1 | R52C101[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_10_s1/CLK |
1.454 | 0.176 | tC2Q | RF | 2 | R52C101[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_10_s1/Q |
1.462 | 0.008 | tNET | FF | 1 | R52C101[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n250_s0/I2 |
1.653 | 0.191 | tINS | FF | 1 | R52C101[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n250_s0/F |
1.653 | 0.000 | tNET | FF | 1 | R52C101[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_10_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
1.278 | 1.278 | tNET | RR | 1 | R52C101[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_10_s1/CLK |
1.279 | 0.001 | tHld | 1 | R52C101[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_10_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.278, 100.000% |
Arrival Data Path Delay | cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.278, 100.000% |
Path12
Path Summary:
Slack | 0.374 |
Data Arrival Time | 1.656 |
Data Required Time | 1.282 |
From | gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
1.281 | 1.281 | tNET | RR | 1 | R54C97[0][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLK |
1.457 | 0.176 | tC2Q | RF | 5 | R54C97[0][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/Q |
1.465 | 0.008 | tNET | FF | 1 | R54C97[0][A] | gw_gao_inst_0/u_la0_top/n1785_s3/I0 |
1.656 | 0.191 | tINS | FF | 1 | R54C97[0][A] | gw_gao_inst_0/u_la0_top/n1785_s3/F |
1.656 | 0.000 | tNET | FF | 1 | R54C97[0][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
1.281 | 1.281 | tNET | RR | 1 | R54C97[0][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLK |
1.282 | 0.001 | tHld | 1 | R54C97[0][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.281, 100.000% |
Arrival Data Path Delay | cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.281, 100.000% |
Path13
Path Summary:
Slack | 0.374 |
Data Arrival Time | 1.658 |
Data Required Time | 1.284 |
From | gw_gao_inst_0/u_la0_top/capture_window_sel_10_s1 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_10_s1 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
1.283 | 1.283 | tNET | RR | 1 | R52C98[1][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_10_s1/CLK |
1.459 | 0.176 | tC2Q | RF | 3 | R52C98[1][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_10_s1/Q |
1.467 | 0.008 | tNET | FF | 1 | R52C98[1][A] | gw_gao_inst_0/u_la0_top/n1783_s1/I1 |
1.658 | 0.191 | tINS | FF | 1 | R52C98[1][A] | gw_gao_inst_0/u_la0_top/n1783_s1/F |
1.658 | 0.000 | tNET | FF | 1 | R52C98[1][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_10_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
1.283 | 1.283 | tNET | RR | 1 | R52C98[1][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_10_s1/CLK |
1.284 | 0.001 | tHld | 1 | R52C98[1][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_10_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.283, 100.000% |
Arrival Data Path Delay | cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.283, 100.000% |
Path14
Path Summary:
Slack | 0.374 |
Data Arrival Time | 1.654 |
Data Required Time | 1.281 |
From | gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1 |
To | gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
1.279 | 1.279 | tNET | RR | 1 | R53C99[0][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLK |
1.456 | 0.176 | tC2Q | RF | 4 | R53C99[0][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/Q |
1.463 | 0.008 | tNET | FF | 1 | R53C99[0][A] | gw_gao_inst_0/u_la0_top/n1742_s1/I1 |
1.654 | 0.191 | tINS | FF | 1 | R53C99[0][A] | gw_gao_inst_0/u_la0_top/n1742_s1/F |
1.654 | 0.000 | tNET | FF | 1 | R53C99[0][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
1.279 | 1.279 | tNET | RR | 1 | R53C99[0][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLK |
1.281 | 0.001 | tHld | 1 | R53C99[0][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.279, 100.000% |
Arrival Data Path Delay | cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.279, 100.000% |
Path15
Path Summary:
Slack | 0.374 |
Data Arrival Time | 1.678 |
Data Required Time | 1.304 |
From | u_b2p/u_b2p_inst/u_hs_adj/rECnt_1_s1 |
To | u_b2p/u_b2p_inst/u_hs_adj/rECnt_1_s1 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
1.303 | 1.303 | tNET | RR | 1 | R57C72[1][A] | u_b2p/u_b2p_inst/u_hs_adj/rECnt_1_s1/CLK |
1.479 | 0.176 | tC2Q | RF | 5 | R57C72[1][A] | u_b2p/u_b2p_inst/u_hs_adj/rECnt_1_s1/Q |
1.486 | 0.008 | tNET | FF | 1 | R57C72[1][A] | u_b2p/u_b2p_inst/u_hs_adj/n94_s3/I3 |
1.678 | 0.191 | tINS | FF | 1 | R57C72[1][A] | u_b2p/u_b2p_inst/u_hs_adj/n94_s3/F |
1.678 | 0.000 | tNET | FF | 1 | R57C72[1][A] | u_b2p/u_b2p_inst/u_hs_adj/rECnt_1_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
1.303 | 1.303 | tNET | RR | 1 | R57C72[1][A] | u_b2p/u_b2p_inst/u_hs_adj/rECnt_1_s1/CLK |
1.304 | 0.001 | tHld | 1 | R57C72[1][A] | u_b2p/u_b2p_inst/u_hs_adj/rECnt_1_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.303, 100.000% |
Arrival Data Path Delay | cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.303, 100.000% |
Path16
Path Summary:
Slack | 0.374 |
Data Arrival Time | 1.657 |
Data Required Time | 1.283 |
From | u_b2p/u_b2p_inst/u_hs_adj/rECnt_5_s1 |
To | u_b2p/u_b2p_inst/u_hs_adj/rECnt_5_s1 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
1.282 | 1.282 | tNET | RR | 1 | R54C71[0][A] | u_b2p/u_b2p_inst/u_hs_adj/rECnt_5_s1/CLK |
1.458 | 0.176 | tC2Q | RF | 4 | R54C71[0][A] | u_b2p/u_b2p_inst/u_hs_adj/rECnt_5_s1/Q |
1.466 | 0.008 | tNET | FF | 1 | R54C71[0][A] | u_b2p/u_b2p_inst/u_hs_adj/n90_s2/I3 |
1.657 | 0.191 | tINS | FF | 1 | R54C71[0][A] | u_b2p/u_b2p_inst/u_hs_adj/n90_s2/F |
1.657 | 0.000 | tNET | FF | 1 | R54C71[0][A] | u_b2p/u_b2p_inst/u_hs_adj/rECnt_5_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
1.282 | 1.282 | tNET | RR | 1 | R54C71[0][A] | u_b2p/u_b2p_inst/u_hs_adj/rECnt_5_s1/CLK |
1.283 | 0.001 | tHld | 1 | R54C71[0][A] | u_b2p/u_b2p_inst/u_hs_adj/rECnt_5_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.282, 100.000% |
Arrival Data Path Delay | cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.282, 100.000% |
Path17
Path Summary:
Slack | 0.374 |
Data Arrival Time | 1.682 |
Data Required Time | 1.309 |
From | u_b2p/u_b2p_inst/u_hs_adj/rSCnt_5_s1 |
To | u_b2p/u_b2p_inst/u_hs_adj/rSCnt_5_s1 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
1.307 | 1.307 | tNET | RR | 1 | R57C71[0][A] | u_b2p/u_b2p_inst/u_hs_adj/rSCnt_5_s1/CLK |
1.484 | 0.176 | tC2Q | RF | 4 | R57C71[0][A] | u_b2p/u_b2p_inst/u_hs_adj/rSCnt_5_s1/Q |
1.491 | 0.008 | tNET | FF | 1 | R57C71[0][A] | u_b2p/u_b2p_inst/u_hs_adj/n56_s2/I3 |
1.682 | 0.191 | tINS | FF | 1 | R57C71[0][A] | u_b2p/u_b2p_inst/u_hs_adj/n56_s2/F |
1.682 | 0.000 | tNET | FF | 1 | R57C71[0][A] | u_b2p/u_b2p_inst/u_hs_adj/rSCnt_5_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
1.307 | 1.307 | tNET | RR | 1 | R57C71[0][A] | u_b2p/u_b2p_inst/u_hs_adj/rSCnt_5_s1/CLK |
1.309 | 0.001 | tHld | 1 | R57C71[0][A] | u_b2p/u_b2p_inst/u_hs_adj/rSCnt_5_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.307, 100.000% |
Arrival Data Path Delay | cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.307, 100.000% |
Path18
Path Summary:
Slack | 0.375 |
Data Arrival Time | 1.898 |
Data Required Time | 1.523 |
From | u_extr/buf_wd_5_s0 |
To | u_extr/mem_data_mem_data_0_2_s |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
1.302 | 1.302 | tNET | RR | 1 | R59C113[3][A] | u_extr/buf_wd_5_s0/CLK |
1.482 | 0.180 | tC2Q | RR | 1 | R59C113[3][A] | u_extr/buf_wd_5_s0/Q |
1.898 | 0.416 | tNET | RR | 1 | BSRAM_R64[24] | u_extr/mem_data_mem_data_0_2_s/DI[1] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
1.274 | 1.274 | tNET | RR | 1 | BSRAM_R64[24] | u_extr/mem_data_mem_data_0_2_s/CLKA |
1.523 | 0.249 | tHld | 1 | BSRAM_R64[24] | u_extr/mem_data_mem_data_0_2_s |
Path Statistics:
Clock Skew | -0.028 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.302, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.416, 69.811%; tC2Q: 0.180, 30.189% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.274, 100.000% |
Path19
Path Summary:
Slack | 0.377 |
Data Arrival Time | 1.662 |
Data Required Time | 1.284 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
1.283 | 1.283 | tNET | RR | 1 | R52C98[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/CLK |
1.459 | 0.176 | tC2Q | RF | 6 | R52C98[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/Q |
1.470 | 0.011 | tNET | FF | 1 | R52C98[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n354_s2/I2 |
1.662 | 0.191 | tINS | FF | 1 | R52C98[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n354_s2/F |
1.662 | 0.000 | tNET | FF | 1 | R52C98[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
1.283 | 1.283 | tNET | RR | 1 | R52C98[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/CLK |
1.284 | 0.001 | tHld | 1 | R52C98[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.283, 100.000% |
Arrival Data Path Delay | cell: 0.191, 50.495%; route: 0.011, 2.970%; tC2Q: 0.176, 46.535% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.283, 100.000% |
Path20
Path Summary:
Slack | 0.377 |
Data Arrival Time | 1.657 |
Data Required Time | 1.279 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
1.278 | 1.278 | tNET | RR | 1 | R52C99[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLK |
1.454 | 0.176 | tC2Q | RF | 5 | R52C99[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/Q |
1.465 | 0.011 | tNET | FF | 1 | R52C99[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n256_s0/I1 |
1.657 | 0.191 | tINS | FF | 1 | R52C99[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n256_s0/F |
1.657 | 0.000 | tNET | FF | 1 | R52C99[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
1.278 | 1.278 | tNET | RR | 1 | R52C99[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLK |
1.279 | 0.001 | tHld | 1 | R52C99[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.278, 100.000% |
Arrival Data Path Delay | cell: 0.191, 50.495%; route: 0.011, 2.970%; tC2Q: 0.176, 46.535% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.278, 100.000% |
Hold Analysis Report[2]:
Report Command:report_timing -hold -from_clock [get_clocks {byte_clk}] -max_paths 20 -max_common_paths 1
Path1
Path Summary:
Slack | 0.235 |
Data Arrival Time | 3.668 |
Data Required Time | 3.433 |
From | u_b2p/u_b2p_inst/rBufD_11_s1 |
To | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 578 | QUAD[0] | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
3.214 | 3.214 | tNET | RR | 1 | R58C85[0][B] | u_b2p/u_b2p_inst/rBufD_11_s1/CLK |
3.394 | 0.180 | tC2Q | RR | 1 | R58C85[0][B] | u_b2p/u_b2p_inst/rBufD_11_s1/Q |
3.668 | 0.274 | tNET | RR | 1 | BSRAM_R64[18][A] | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s/DI[11] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 578 | QUAD[0] | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
3.184 | 3.184 | tNET | RR | 1 | BSRAM_R64[18][A] | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s/CLKA |
3.433 | 0.249 | tHld | 1 | BSRAM_R64[18][A] | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s |
Path Statistics:
Clock Skew | -0.030 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.214, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.274, 60.331%; tC2Q: 0.180, 39.669% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.184, 100.000% |
Path2
Path Summary:
Slack | 0.266 |
Data Arrival Time | 3.698 |
Data Required Time | 3.433 |
From | u_b2p/u_b2p_inst/rBufD_3_s1 |
To | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 578 | QUAD[0] | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
3.213 | 3.213 | tNET | RR | 1 | R56C86[3][A] | u_b2p/u_b2p_inst/rBufD_3_s1/CLK |
3.393 | 0.180 | tC2Q | RR | 1 | R56C86[3][A] | u_b2p/u_b2p_inst/rBufD_3_s1/Q |
3.698 | 0.305 | tNET | RR | 1 | BSRAM_R64[18][A] | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s/DI[3] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 578 | QUAD[0] | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
3.184 | 3.184 | tNET | RR | 1 | BSRAM_R64[18][A] | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s/CLKA |
3.433 | 0.249 | tHld | 1 | BSRAM_R64[18][A] | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s |
Path Statistics:
Clock Skew | -0.030 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.213, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.305, 62.887%; tC2Q: 0.180, 37.113% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.184, 100.000% |
Path3
Path Summary:
Slack | 0.314 |
Data Arrival Time | 3.747 |
Data Required Time | 3.433 |
From | u_b2p/u_b2p_inst/rBufD_6_s1 |
To | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 578 | QUAD[0] | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
3.213 | 3.213 | tNET | RR | 1 | R56C86[0][B] | u_b2p/u_b2p_inst/rBufD_6_s1/CLK |
3.393 | 0.180 | tC2Q | RR | 1 | R56C86[0][B] | u_b2p/u_b2p_inst/rBufD_6_s1/Q |
3.747 | 0.354 | tNET | RR | 1 | BSRAM_R64[18][A] | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s/DI[6] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 578 | QUAD[0] | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
3.184 | 3.184 | tNET | RR | 1 | BSRAM_R64[18][A] | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s/CLKA |
3.433 | 0.249 | tHld | 1 | BSRAM_R64[18][A] | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s |
Path Statistics:
Clock Skew | -0.030 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.213, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.354, 66.276%; tC2Q: 0.180, 33.724% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.184, 100.000% |
Path4
Path Summary:
Slack | 0.321 |
Data Arrival Time | 3.758 |
Data Required Time | 3.438 |
From | u_b2p/u_b2p_inst/rBufD_44_s1 |
To | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_1_s |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 578 | QUAD[0] | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
3.218 | 3.218 | tNET | RR | 1 | R56C85[0][A] | u_b2p/u_b2p_inst/rBufD_44_s1/CLK |
3.398 | 0.180 | tC2Q | RR | 1 | R56C85[0][A] | u_b2p/u_b2p_inst/rBufD_44_s1/Q |
3.758 | 0.360 | tNET | RR | 1 | BSRAM_R64[18][B] | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_1_s/DI[12] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 578 | QUAD[0] | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
3.189 | 3.189 | tNET | RR | 1 | BSRAM_R64[18][B] | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_1_s/CLKA |
3.438 | 0.249 | tHld | 1 | BSRAM_R64[18][B] | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_1_s |
Path Statistics:
Clock Skew | -0.030 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.218, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.360, 66.667%; tC2Q: 0.180, 33.333% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.189, 100.000% |
Path5
Path Summary:
Slack | 0.355 |
Data Arrival Time | 3.788 |
Data Required Time | 3.433 |
From | u_b2p/u_b2p_inst/rBufD_24_s1 |
To | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 578 | QUAD[0] | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
3.214 | 3.214 | tNET | RR | 1 | R58C85[0][A] | u_b2p/u_b2p_inst/rBufD_24_s1/CLK |
3.394 | 0.180 | tC2Q | RR | 1 | R58C85[0][A] | u_b2p/u_b2p_inst/rBufD_24_s1/Q |
3.788 | 0.394 | tNET | RR | 1 | BSRAM_R64[18][A] | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s/DI[24] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 578 | QUAD[0] | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
3.184 | 3.184 | tNET | RR | 1 | BSRAM_R64[18][A] | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s/CLKA |
3.433 | 0.249 | tHld | 1 | BSRAM_R64[18][A] | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s |
Path Statistics:
Clock Skew | -0.030 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.214, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.394, 68.627%; tC2Q: 0.180, 31.373% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.184, 100.000% |
Path6
Path Summary:
Slack | 0.374 |
Data Arrival Time | 3.558 |
Data Required Time | 3.184 |
From | u_b2p/u_b2p_inst/u_mid_fifo/rWPtrGray_0_s1 |
To | u_b2p/u_b2p_inst/u_mid_fifo/rWPtrGray_0_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 578 | QUAD[0] | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
3.183 | 3.183 | tNET | RR | 1 | R52C84[0][A] | u_b2p/u_b2p_inst/u_mid_fifo/rWPtrGray_0_s1/CLK |
3.359 | 0.176 | tC2Q | RF | 2 | R52C84[0][A] | u_b2p/u_b2p_inst/u_mid_fifo/rWPtrGray_0_s1/Q |
3.367 | 0.008 | tNET | FF | 1 | R52C84[0][A] | u_b2p/u_b2p_inst/u_mid_fifo/wWPtrGrayNext_0_s3/I0 |
3.558 | 0.191 | tINS | FF | 1 | R52C84[0][A] | u_b2p/u_b2p_inst/u_mid_fifo/wWPtrGrayNext_0_s3/F |
3.558 | 0.000 | tNET | FF | 1 | R52C84[0][A] | u_b2p/u_b2p_inst/u_mid_fifo/rWPtrGray_0_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 578 | QUAD[0] | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
3.183 | 3.183 | tNET | RR | 1 | R52C84[0][A] | u_b2p/u_b2p_inst/u_mid_fifo/rWPtrGray_0_s1/CLK |
3.184 | 0.001 | tHld | 1 | R52C84[0][A] | u_b2p/u_b2p_inst/u_mid_fifo/rWPtrGray_0_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.183, 100.000% |
Arrival Data Path Delay | cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.183, 100.000% |
Path7
Path Summary:
Slack | 0.374 |
Data Arrival Time | 3.561 |
Data Required Time | 3.187 |
From | u_b2p/u_b2p_inst/u_dsi_sync_detec/rVSync_s0 |
To | u_b2p/u_b2p_inst/u_dsi_sync_detec/rVSync_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 578 | QUAD[0] | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
3.186 | 3.186 | tNET | RR | 1 | R54C70[0][A] | u_b2p/u_b2p_inst/u_dsi_sync_detec/rVSync_s0/CLK |
3.362 | 0.176 | tC2Q | RF | 2 | R54C70[0][A] | u_b2p/u_b2p_inst/u_dsi_sync_detec/rVSync_s0/Q |
3.370 | 0.008 | tNET | FF | 1 | R54C70[0][A] | u_b2p/u_b2p_inst/u_dsi_sync_detec/n57_s0/I1 |
3.561 | 0.191 | tINS | FF | 1 | R54C70[0][A] | u_b2p/u_b2p_inst/u_dsi_sync_detec/n57_s0/F |
3.561 | 0.000 | tNET | FF | 1 | R54C70[0][A] | u_b2p/u_b2p_inst/u_dsi_sync_detec/rVSync_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 578 | QUAD[0] | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
3.186 | 3.186 | tNET | RR | 1 | R54C70[0][A] | u_b2p/u_b2p_inst/u_dsi_sync_detec/rVSync_s0/CLK |
3.187 | 0.001 | tHld | 1 | R54C70[0][A] | u_b2p/u_b2p_inst/u_dsi_sync_detec/rVSync_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.186, 100.000% |
Arrival Data Path Delay | cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.186, 100.000% |
Path8
Path Summary:
Slack | 0.374 |
Data Arrival Time | 3.558 |
Data Required Time | 3.184 |
From | u_b2p/u_b2p_inst/wc_cnt_dec_3_s1 |
To | u_b2p/u_b2p_inst/wc_cnt_dec_3_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 578 | QUAD[0] | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
3.183 | 3.183 | tNET | RR | 1 | R52C72[1][A] | u_b2p/u_b2p_inst/wc_cnt_dec_3_s1/CLK |
3.359 | 0.176 | tC2Q | RF | 4 | R52C72[1][A] | u_b2p/u_b2p_inst/wc_cnt_dec_3_s1/Q |
3.367 | 0.008 | tNET | FF | 1 | R52C72[1][A] | u_b2p/u_b2p_inst/n1200_s0/I2 |
3.558 | 0.191 | tINS | FF | 1 | R52C72[1][A] | u_b2p/u_b2p_inst/n1200_s0/F |
3.558 | 0.000 | tNET | FF | 1 | R52C72[1][A] | u_b2p/u_b2p_inst/wc_cnt_dec_3_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 578 | QUAD[0] | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
3.183 | 3.183 | tNET | RR | 1 | R52C72[1][A] | u_b2p/u_b2p_inst/wc_cnt_dec_3_s1/CLK |
3.184 | 0.001 | tHld | 1 | R52C72[1][A] | u_b2p/u_b2p_inst/wc_cnt_dec_3_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.183, 100.000% |
Arrival Data Path Delay | cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.183, 100.000% |
Path9
Path Summary:
Slack | 0.374 |
Data Arrival Time | 3.553 |
Data Required Time | 3.179 |
From | u_b2p/u_b2p_inst/wc_cnt_dec_7_s1 |
To | u_b2p/u_b2p_inst/wc_cnt_dec_7_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 578 | QUAD[0] | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
3.178 | 3.178 | tNET | RR | 1 | R52C71[0][A] | u_b2p/u_b2p_inst/wc_cnt_dec_7_s1/CLK |
3.354 | 0.176 | tC2Q | RF | 5 | R52C71[0][A] | u_b2p/u_b2p_inst/wc_cnt_dec_7_s1/Q |
3.362 | 0.008 | tNET | FF | 1 | R52C71[0][A] | u_b2p/u_b2p_inst/n1196_s0/I2 |
3.553 | 0.191 | tINS | FF | 1 | R52C71[0][A] | u_b2p/u_b2p_inst/n1196_s0/F |
3.553 | 0.000 | tNET | FF | 1 | R52C71[0][A] | u_b2p/u_b2p_inst/wc_cnt_dec_7_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 578 | QUAD[0] | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
3.178 | 3.178 | tNET | RR | 1 | R52C71[0][A] | u_b2p/u_b2p_inst/wc_cnt_dec_7_s1/CLK |
3.179 | 0.001 | tHld | 1 | R52C71[0][A] | u_b2p/u_b2p_inst/wc_cnt_dec_7_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.178, 100.000% |
Arrival Data Path Delay | cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.178, 100.000% |
Path10
Path Summary:
Slack | 0.374 |
Data Arrival Time | 3.563 |
Data Required Time | 3.189 |
From | u_b2p/u_b2p_inst/wc_cnt_dec_9_s1 |
To | u_b2p/u_b2p_inst/wc_cnt_dec_9_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 578 | QUAD[0] | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
3.188 | 3.188 | tNET | RR | 1 | R52C73[1][A] | u_b2p/u_b2p_inst/wc_cnt_dec_9_s1/CLK |
3.364 | 0.176 | tC2Q | RF | 3 | R52C73[1][A] | u_b2p/u_b2p_inst/wc_cnt_dec_9_s1/Q |
3.372 | 0.008 | tNET | FF | 1 | R52C73[1][A] | u_b2p/u_b2p_inst/n1194_s0/I2 |
3.563 | 0.191 | tINS | FF | 1 | R52C73[1][A] | u_b2p/u_b2p_inst/n1194_s0/F |
3.563 | 0.000 | tNET | FF | 1 | R52C73[1][A] | u_b2p/u_b2p_inst/wc_cnt_dec_9_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 578 | QUAD[0] | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
3.188 | 3.188 | tNET | RR | 1 | R52C73[1][A] | u_b2p/u_b2p_inst/wc_cnt_dec_9_s1/CLK |
3.189 | 0.001 | tHld | 1 | R52C73[1][A] | u_b2p/u_b2p_inst/wc_cnt_dec_9_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.188, 100.000% |
Arrival Data Path Delay | cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.188, 100.000% |
Path11
Path Summary:
Slack | 0.374 |
Data Arrival Time | 3.558 |
Data Required Time | 3.184 |
From | u_b2p/u_b2p_inst/wc_cnt_dec_11_s1 |
To | u_b2p/u_b2p_inst/wc_cnt_dec_11_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 578 | QUAD[0] | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
3.183 | 3.183 | tNET | RR | 1 | R52C74[1][A] | u_b2p/u_b2p_inst/wc_cnt_dec_11_s1/CLK |
3.359 | 0.176 | tC2Q | RF | 2 | R52C74[1][A] | u_b2p/u_b2p_inst/wc_cnt_dec_11_s1/Q |
3.367 | 0.008 | tNET | FF | 1 | R52C74[1][A] | u_b2p/u_b2p_inst/n1192_s0/I2 |
3.558 | 0.191 | tINS | FF | 1 | R52C74[1][A] | u_b2p/u_b2p_inst/n1192_s0/F |
3.558 | 0.000 | tNET | FF | 1 | R52C74[1][A] | u_b2p/u_b2p_inst/wc_cnt_dec_11_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 578 | QUAD[0] | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
3.183 | 3.183 | tNET | RR | 1 | R52C74[1][A] | u_b2p/u_b2p_inst/wc_cnt_dec_11_s1/CLK |
3.184 | 0.001 | tHld | 1 | R52C74[1][A] | u_b2p/u_b2p_inst/wc_cnt_dec_11_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.183, 100.000% |
Arrival Data Path Delay | cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.183, 100.000% |
Path12
Path Summary:
Slack | 0.374 |
Data Arrival Time | 3.553 |
Data Required Time | 3.179 |
From | u_b2p/u_b2p_inst/wc_cnt_dec_13_s1 |
To | u_b2p/u_b2p_inst/wc_cnt_dec_13_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 578 | QUAD[0] | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
3.178 | 3.178 | tNET | RR | 1 | R52C75[1][A] | u_b2p/u_b2p_inst/wc_cnt_dec_13_s1/CLK |
3.354 | 0.176 | tC2Q | RF | 4 | R52C75[1][A] | u_b2p/u_b2p_inst/wc_cnt_dec_13_s1/Q |
3.362 | 0.008 | tNET | FF | 1 | R52C75[1][A] | u_b2p/u_b2p_inst/n1190_s0/I2 |
3.553 | 0.191 | tINS | FF | 1 | R52C75[1][A] | u_b2p/u_b2p_inst/n1190_s0/F |
3.553 | 0.000 | tNET | FF | 1 | R52C75[1][A] | u_b2p/u_b2p_inst/wc_cnt_dec_13_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 578 | QUAD[0] | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
3.178 | 3.178 | tNET | RR | 1 | R52C75[1][A] | u_b2p/u_b2p_inst/wc_cnt_dec_13_s1/CLK |
3.179 | 0.001 | tHld | 1 | R52C75[1][A] | u_b2p/u_b2p_inst/wc_cnt_dec_13_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.178, 100.000% |
Arrival Data Path Delay | cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.178, 100.000% |
Path13
Path Summary:
Slack | 0.374 |
Data Arrival Time | 3.553 |
Data Required Time | 3.179 |
From | u_b2p/u_b2p_inst/wc_cnt_dec_15_s1 |
To | u_b2p/u_b2p_inst/wc_cnt_dec_15_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 578 | QUAD[0] | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
3.178 | 3.178 | tNET | RR | 1 | R52C75[0][A] | u_b2p/u_b2p_inst/wc_cnt_dec_15_s1/CLK |
3.354 | 0.176 | tC2Q | RF | 2 | R52C75[0][A] | u_b2p/u_b2p_inst/wc_cnt_dec_15_s1/Q |
3.362 | 0.008 | tNET | FF | 1 | R52C75[0][A] | u_b2p/u_b2p_inst/n1188_s0/I2 |
3.553 | 0.191 | tINS | FF | 1 | R52C75[0][A] | u_b2p/u_b2p_inst/n1188_s0/F |
3.553 | 0.000 | tNET | FF | 1 | R52C75[0][A] | u_b2p/u_b2p_inst/wc_cnt_dec_15_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 578 | QUAD[0] | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
3.178 | 3.178 | tNET | RR | 1 | R52C75[0][A] | u_b2p/u_b2p_inst/wc_cnt_dec_15_s1/CLK |
3.179 | 0.001 | tHld | 1 | R52C75[0][A] | u_b2p/u_b2p_inst/wc_cnt_dec_15_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.178, 100.000% |
Arrival Data Path Delay | cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.178, 100.000% |
Path14
Path Summary:
Slack | 0.374 |
Data Arrival Time | 3.593 |
Data Required Time | 3.220 |
From | u_dsi_rx/u_dsi_csi2/rWcCntP_0_s3 |
To | u_dsi_rx/u_dsi_csi2/rWcCntP_0_s3 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 578 | QUAD[0] | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
3.218 | 3.218 | tNET | RR | 1 | R56C69[1][A] | u_dsi_rx/u_dsi_csi2/rWcCntP_0_s3/CLK |
3.395 | 0.176 | tC2Q | RF | 2 | R56C69[1][A] | u_dsi_rx/u_dsi_csi2/rWcCntP_0_s3/Q |
3.402 | 0.008 | tNET | FF | 1 | R56C69[1][A] | u_dsi_rx/u_dsi_csi2/n779_s3/I2 |
3.593 | 0.191 | tINS | FF | 1 | R56C69[1][A] | u_dsi_rx/u_dsi_csi2/n779_s3/F |
3.593 | 0.000 | tNET | FF | 1 | R56C69[1][A] | u_dsi_rx/u_dsi_csi2/rWcCntP_0_s3/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 578 | QUAD[0] | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
3.218 | 3.218 | tNET | RR | 1 | R56C69[1][A] | u_dsi_rx/u_dsi_csi2/rWcCntP_0_s3/CLK |
3.220 | 0.001 | tHld | 1 | R56C69[1][A] | u_dsi_rx/u_dsi_csi2/rWcCntP_0_s3 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.218, 100.000% |
Arrival Data Path Delay | cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.218, 100.000% |
Path15
Path Summary:
Slack | 0.374 |
Data Arrival Time | 3.554 |
Data Required Time | 3.181 |
From | u_dsi_rx/u_dsi_csi2/rDSel_0_s3 |
To | u_dsi_rx/u_dsi_csi2/rDSel_0_s3 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 578 | QUAD[0] | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
3.179 | 3.179 | tNET | RR | 1 | R53C63[0][A] | u_dsi_rx/u_dsi_csi2/rDSel_0_s3/CLK |
3.356 | 0.176 | tC2Q | RF | 4 | R53C63[0][A] | u_dsi_rx/u_dsi_csi2/rDSel_0_s3/Q |
3.363 | 0.008 | tNET | FF | 1 | R53C63[0][A] | u_dsi_rx/u_dsi_csi2/n638_s3/I2 |
3.554 | 0.191 | tINS | FF | 1 | R53C63[0][A] | u_dsi_rx/u_dsi_csi2/n638_s3/F |
3.554 | 0.000 | tNET | FF | 1 | R53C63[0][A] | u_dsi_rx/u_dsi_csi2/rDSel_0_s3/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 578 | QUAD[0] | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
3.179 | 3.179 | tNET | RR | 1 | R53C63[0][A] | u_dsi_rx/u_dsi_csi2/rDSel_0_s3/CLK |
3.181 | 0.001 | tHld | 1 | R53C63[0][A] | u_dsi_rx/u_dsi_csi2/rDSel_0_s3 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.179, 100.000% |
Arrival Data Path Delay | cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.179, 100.000% |
Path16
Path Summary:
Slack | 0.374 |
Data Arrival Time | 3.587 |
Data Required Time | 3.213 |
From | hsrx_cnt_0_s1 |
To | hsrx_cnt_0_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 578 | QUAD[0] | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
3.212 | 3.212 | tNET | RR | 1 | R56C128[0][A] | hsrx_cnt_0_s1/CLK |
3.388 | 0.176 | tC2Q | RF | 5 | R56C128[0][A] | hsrx_cnt_0_s1/Q |
3.396 | 0.008 | tNET | FF | 1 | R56C128[0][A] | n58_s3/I0 |
3.587 | 0.191 | tINS | FF | 1 | R56C128[0][A] | n58_s3/F |
3.587 | 0.000 | tNET | FF | 1 | R56C128[0][A] | hsrx_cnt_0_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 578 | QUAD[0] | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
3.212 | 3.212 | tNET | RR | 1 | R56C128[0][A] | hsrx_cnt_0_s1/CLK |
3.213 | 0.001 | tHld | 1 | R56C128[0][A] | hsrx_cnt_0_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.212, 100.000% |
Arrival Data Path Delay | cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.212, 100.000% |
Path17
Path Summary:
Slack | 0.374 |
Data Arrival Time | 3.587 |
Data Required Time | 3.213 |
From | hsrx_cnt_1_s1 |
To | hsrx_cnt_1_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 578 | QUAD[0] | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
3.212 | 3.212 | tNET | RR | 1 | R56C128[1][A] | hsrx_cnt_1_s1/CLK |
3.388 | 0.176 | tC2Q | RF | 4 | R56C128[1][A] | hsrx_cnt_1_s1/Q |
3.396 | 0.008 | tNET | FF | 1 | R56C128[1][A] | n57_s1/I2 |
3.587 | 0.191 | tINS | FF | 1 | R56C128[1][A] | n57_s1/F |
3.587 | 0.000 | tNET | FF | 1 | R56C128[1][A] | hsrx_cnt_1_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 578 | QUAD[0] | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
3.212 | 3.212 | tNET | RR | 1 | R56C128[1][A] | hsrx_cnt_1_s1/CLK |
3.213 | 0.001 | tHld | 1 | R56C128[1][A] | hsrx_cnt_1_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.212, 100.000% |
Arrival Data Path Delay | cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.212, 100.000% |
Path18
Path Summary:
Slack | 0.375 |
Data Arrival Time | 3.808 |
Data Required Time | 3.433 |
From | u_b2p/u_b2p_inst/rBufD_25_s1 |
To | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 578 | QUAD[0] | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
3.211 | 3.211 | tNET | RR | 1 | R57C86[0][A] | u_b2p/u_b2p_inst/rBufD_25_s1/CLK |
3.391 | 0.180 | tC2Q | RR | 1 | R57C86[0][A] | u_b2p/u_b2p_inst/rBufD_25_s1/Q |
3.808 | 0.416 | tNET | RR | 1 | BSRAM_R64[18][A] | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s/DI[25] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 578 | QUAD[0] | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
3.184 | 3.184 | tNET | RR | 1 | BSRAM_R64[18][A] | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s/CLKA |
3.433 | 0.249 | tHld | 1 | BSRAM_R64[18][A] | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s |
Path Statistics:
Clock Skew | -0.027 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.211, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.416, 69.811%; tC2Q: 0.180, 30.189% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.184, 100.000% |
Path19
Path Summary:
Slack | 0.378 |
Data Arrival Time | 3.563 |
Data Required Time | 3.186 |
From | u_b2p/u_b2p_inst/wc_cnt_dec_1_s3 |
To | u_b2p/u_b2p_inst/wc_cnt_dec_1_s3 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 578 | QUAD[0] | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
3.184 | 3.184 | tNET | RR | 1 | R53C74[0][A] | u_b2p/u_b2p_inst/wc_cnt_dec_1_s3/CLK |
3.361 | 0.176 | tC2Q | RF | 7 | R53C74[0][A] | u_b2p/u_b2p_inst/wc_cnt_dec_1_s3/Q |
3.372 | 0.011 | tNET | FF | 1 | R53C74[0][A] | u_b2p/u_b2p_inst/n1202_s2/I0 |
3.563 | 0.191 | tINS | FF | 1 | R53C74[0][A] | u_b2p/u_b2p_inst/n1202_s2/F |
3.563 | 0.000 | tNET | FF | 1 | R53C74[0][A] | u_b2p/u_b2p_inst/wc_cnt_dec_1_s3/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 578 | QUAD[0] | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
3.184 | 3.184 | tNET | RR | 1 | R53C74[0][A] | u_b2p/u_b2p_inst/wc_cnt_dec_1_s3/CLK |
3.186 | 0.001 | tHld | 1 | R53C74[0][A] | u_b2p/u_b2p_inst/wc_cnt_dec_1_s3 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.184, 100.000% |
Arrival Data Path Delay | cell: 0.191, 50.495%; route: 0.011, 2.970%; tC2Q: 0.176, 46.535% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.184, 100.000% |
Path20
Path Summary:
Slack | 0.378 |
Data Arrival Time | 3.562 |
Data Required Time | 3.184 |
From | u_b2p/u_b2p_inst/wc_cnt_dec_5_s1 |
To | u_b2p/u_b2p_inst/wc_cnt_dec_5_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 578 | QUAD[0] | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
3.183 | 3.183 | tNET | RR | 1 | R52C72[0][A] | u_b2p/u_b2p_inst/wc_cnt_dec_5_s1/CLK |
3.359 | 0.176 | tC2Q | RF | 4 | R52C72[0][A] | u_b2p/u_b2p_inst/wc_cnt_dec_5_s1/Q |
3.370 | 0.011 | tNET | FF | 1 | R52C72[0][A] | u_b2p/u_b2p_inst/n1198_s0/I2 |
3.562 | 0.191 | tINS | FF | 1 | R52C72[0][A] | u_b2p/u_b2p_inst/n1198_s0/F |
3.562 | 0.000 | tNET | FF | 1 | R52C72[0][A] | u_b2p/u_b2p_inst/wc_cnt_dec_5_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 578 | QUAD[0] | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
3.183 | 3.183 | tNET | RR | 1 | R52C72[0][A] | u_b2p/u_b2p_inst/wc_cnt_dec_5_s1/CLK |
3.184 | 0.001 | tHld | 1 | R52C72[0][A] | u_b2p/u_b2p_inst/wc_cnt_dec_5_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 3.183, 100.000% |
Arrival Data Path Delay | cell: 0.191, 50.495%; route: 0.011, 2.970%; tC2Q: 0.176, 46.535% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 3.183, 100.000% |
Hold Analysis Report[3]:
Report Command:report_timing -hold -from_clock [get_clocks {lvds_pclk}] -max_paths 20 -max_common_paths 1
Path1
Path Summary:
Slack | 0.204 |
Data Arrival Time | 1.536 |
Data Required Time | 1.331 |
From | u_lvds_tx_left/LVDS_71_Tx/scuba_vhi_s0 |
To | u_lvds_tx_left/LVDS_71_Tx/u_ODDR71_C |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_R[3] | u_pll_50m/PLL_inst/CLKOUT1 |
1.232 | 1.232 | tNET | RR | 1 | R49C181[0][A] | u_lvds_tx_left/LVDS_71_Tx/scuba_vhi_s0/CLK |
1.412 | 0.180 | tC2Q | RR | 4 | R49C181[0][A] | u_lvds_tx_left/LVDS_71_Tx/scuba_vhi_s0/Q |
1.536 | 0.124 | tNET | RR | 1 | IOR49[A] | u_lvds_tx_left/LVDS_71_Tx/u_ODDR71_C/D6 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_R[3] | u_pll_50m/PLL_inst/CLKOUT1 |
1.236 | 1.236 | tNET | RR | 1 | IOR49[A] | u_lvds_tx_left/LVDS_71_Tx/u_ODDR71_C/PCLK |
1.331 | 0.095 | tHld | 1 | IOR49[A] | u_lvds_tx_left/LVDS_71_Tx/u_ODDR71_C |
Path Statistics:
Clock Skew | 0.004 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.232, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.124, 40.741%; tC2Q: 0.180, 59.259% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.236, 100.000% |
Path2
Path Summary:
Slack | 0.204 |
Data Arrival Time | 1.536 |
Data Required Time | 1.331 |
From | u_lvds_tx_left/LVDS_71_Tx/scuba_vhi_s0 |
To | u_lvds_tx_left/LVDS_71_Tx/u_ODDR71_C |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_R[3] | u_pll_50m/PLL_inst/CLKOUT1 |
1.232 | 1.232 | tNET | RR | 1 | R49C181[0][A] | u_lvds_tx_left/LVDS_71_Tx/scuba_vhi_s0/CLK |
1.412 | 0.180 | tC2Q | RR | 4 | R49C181[0][A] | u_lvds_tx_left/LVDS_71_Tx/scuba_vhi_s0/Q |
1.536 | 0.124 | tNET | RR | 1 | IOR49[A] | u_lvds_tx_left/LVDS_71_Tx/u_ODDR71_C/D0 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_R[3] | u_pll_50m/PLL_inst/CLKOUT1 |
1.236 | 1.236 | tNET | RR | 1 | IOR49[A] | u_lvds_tx_left/LVDS_71_Tx/u_ODDR71_C/PCLK |
1.331 | 0.095 | tHld | 1 | IOR49[A] | u_lvds_tx_left/LVDS_71_Tx/u_ODDR71_C |
Path Statistics:
Clock Skew | 0.004 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.232, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.124, 40.741%; tC2Q: 0.180, 59.259% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.236, 100.000% |
Path3
Path Summary:
Slack | 0.219 |
Data Arrival Time | 1.538 |
Data Required Time | 1.319 |
From | u_lvds_tx_left/LVDS_71_Tx/scuba_vhi_s0 |
To | u_lvds_tx_left/LVDS_71_Tx/u_ODDR71_C |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_R[3] | u_pll_50m/PLL_inst/CLKOUT1 |
1.232 | 1.232 | tNET | RR | 1 | R49C181[0][A] | u_lvds_tx_left/LVDS_71_Tx/scuba_vhi_s0/CLK |
1.412 | 0.180 | tC2Q | RR | 4 | R49C181[0][A] | u_lvds_tx_left/LVDS_71_Tx/scuba_vhi_s0/Q |
1.538 | 0.126 | tNET | RR | 1 | IOR49[A] | u_lvds_tx_left/LVDS_71_Tx/u_ODDR71_C/D5 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_R[3] | u_pll_50m/PLL_inst/CLKOUT1 |
1.236 | 1.236 | tNET | RR | 1 | IOR49[A] | u_lvds_tx_left/LVDS_71_Tx/u_ODDR71_C/PCLK |
1.319 | 0.083 | tHld | 1 | IOR49[A] | u_lvds_tx_left/LVDS_71_Tx/u_ODDR71_C |
Path Statistics:
Clock Skew | 0.004 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.232, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.126, 41.224%; tC2Q: 0.180, 58.776% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.236, 100.000% |
Path4
Path Summary:
Slack | 0.219 |
Data Arrival Time | 1.538 |
Data Required Time | 1.319 |
From | u_lvds_tx_left/LVDS_71_Tx/scuba_vhi_s0 |
To | u_lvds_tx_left/LVDS_71_Tx/u_ODDR71_C |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_R[3] | u_pll_50m/PLL_inst/CLKOUT1 |
1.232 | 1.232 | tNET | RR | 1 | R49C181[0][A] | u_lvds_tx_left/LVDS_71_Tx/scuba_vhi_s0/CLK |
1.412 | 0.180 | tC2Q | RR | 4 | R49C181[0][A] | u_lvds_tx_left/LVDS_71_Tx/scuba_vhi_s0/Q |
1.538 | 0.126 | tNET | RR | 1 | IOR49[A] | u_lvds_tx_left/LVDS_71_Tx/u_ODDR71_C/D1 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_R[3] | u_pll_50m/PLL_inst/CLKOUT1 |
1.236 | 1.236 | tNET | RR | 1 | IOR49[A] | u_lvds_tx_left/LVDS_71_Tx/u_ODDR71_C/PCLK |
1.319 | 0.083 | tHld | 1 | IOR49[A] | u_lvds_tx_left/LVDS_71_Tx/u_ODDR71_C |
Path Statistics:
Clock Skew | 0.004 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.232, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.126, 41.224%; tC2Q: 0.180, 58.776% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.236, 100.000% |
Path5
Path Summary:
Slack | 0.374 |
Data Arrival Time | 1.630 |
Data Required Time | 1.256 |
From | u_extr/buf_ra_12_s13 |
To | u_extr/buf_ra_12_s13 |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_R[3] | u_pll_50m/PLL_inst/CLKOUT1 |
1.255 | 1.255 | tNET | RR | 1 | R54C128[1][A] | u_extr/buf_ra_12_s13/CLK |
1.431 | 0.176 | tC2Q | RF | 2 | R54C128[1][A] | u_extr/buf_ra_12_s13/Q |
1.438 | 0.008 | tNET | FF | 1 | R54C128[1][A] | u_extr/n926_s4/I0 |
1.630 | 0.191 | tINS | FF | 1 | R54C128[1][A] | u_extr/n926_s4/F |
1.630 | 0.000 | tNET | FF | 1 | R54C128[1][A] | u_extr/buf_ra_12_s13/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_R[3] | u_pll_50m/PLL_inst/CLKOUT1 |
1.255 | 1.255 | tNET | RR | 1 | R54C128[1][A] | u_extr/buf_ra_12_s13/CLK |
1.256 | 0.001 | tHld | 1 | R54C128[1][A] | u_extr/buf_ra_12_s13 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.255, 100.000% |
Arrival Data Path Delay | cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.255, 100.000% |
Path6
Path Summary:
Slack | 0.374 |
Data Arrival Time | 1.645 |
Data Required Time | 1.271 |
From | u_extr/ovcnt_14_s1 |
To | u_extr/ovcnt_14_s1 |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_R[3] | u_pll_50m/PLL_inst/CLKOUT1 |
1.270 | 1.270 | tNET | RR | 1 | R57C126[0][A] | u_extr/ovcnt_14_s1/CLK |
1.446 | 0.176 | tC2Q | RF | 4 | R57C126[0][A] | u_extr/ovcnt_14_s1/Q |
1.454 | 0.008 | tNET | FF | 1 | R57C126[0][A] | u_extr/n781_s4/I1 |
1.645 | 0.191 | tINS | FF | 1 | R57C126[0][A] | u_extr/n781_s4/F |
1.645 | 0.000 | tNET | FF | 1 | R57C126[0][A] | u_extr/ovcnt_14_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_R[3] | u_pll_50m/PLL_inst/CLKOUT1 |
1.270 | 1.270 | tNET | RR | 1 | R57C126[0][A] | u_extr/ovcnt_14_s1/CLK |
1.271 | 0.001 | tHld | 1 | R57C126[0][A] | u_extr/ovcnt_14_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.270, 100.000% |
Arrival Data Path Delay | cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.270, 100.000% |
Path7
Path Summary:
Slack | 0.374 |
Data Arrival Time | 1.645 |
Data Required Time | 1.271 |
From | u_extr/ovcnt_15_s1 |
To | u_extr/ovcnt_15_s1 |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_R[3] | u_pll_50m/PLL_inst/CLKOUT1 |
1.270 | 1.270 | tNET | RR | 1 | R57C126[1][A] | u_extr/ovcnt_15_s1/CLK |
1.446 | 0.176 | tC2Q | RF | 3 | R57C126[1][A] | u_extr/ovcnt_15_s1/Q |
1.454 | 0.008 | tNET | FF | 1 | R57C126[1][A] | u_extr/n780_s4/I1 |
1.645 | 0.191 | tINS | FF | 1 | R57C126[1][A] | u_extr/n780_s4/F |
1.645 | 0.000 | tNET | FF | 1 | R57C126[1][A] | u_extr/ovcnt_15_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_R[3] | u_pll_50m/PLL_inst/CLKOUT1 |
1.270 | 1.270 | tNET | RR | 1 | R57C126[1][A] | u_extr/ovcnt_15_s1/CLK |
1.271 | 0.001 | tHld | 1 | R57C126[1][A] | u_extr/ovcnt_15_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.270, 100.000% |
Arrival Data Path Delay | cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.270, 100.000% |
Path8
Path Summary:
Slack | 0.374 |
Data Arrival Time | 1.647 |
Data Required Time | 1.273 |
From | u_extr/buf_ra_9_s0 |
To | u_extr/buf_ra_9_s0 |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_R[3] | u_pll_50m/PLL_inst/CLKOUT1 |
1.272 | 1.272 | tNET | RR | 1 | R56C122[1][A] | u_extr/buf_ra_9_s0/CLK |
1.448 | 0.176 | tC2Q | RF | 3 | R56C122[1][A] | u_extr/buf_ra_9_s0/Q |
1.456 | 0.008 | tNET | FF | 1 | R56C122[1][A] | u_extr/n877_s3/I0 |
1.647 | 0.191 | tINS | FF | 1 | R56C122[1][A] | u_extr/n877_s3/F |
1.647 | 0.000 | tNET | FF | 1 | R56C122[1][A] | u_extr/buf_ra_9_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_R[3] | u_pll_50m/PLL_inst/CLKOUT1 |
1.272 | 1.272 | tNET | RR | 1 | R56C122[1][A] | u_extr/buf_ra_9_s0/CLK |
1.273 | 0.001 | tHld | 1 | R56C122[1][A] | u_extr/buf_ra_9_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.272, 100.000% |
Arrival Data Path Delay | cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.272, 100.000% |
Path9
Path Summary:
Slack | 0.374 |
Data Arrival Time | 1.652 |
Data Required Time | 1.278 |
From | u_extr/ohcnt_1_s0 |
To | u_extr/ohcnt_1_s0 |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_R[3] | u_pll_50m/PLL_inst/CLKOUT1 |
1.277 | 1.277 | tNET | RR | 1 | R56C127[0][A] | u_extr/ohcnt_1_s0/CLK |
1.453 | 0.176 | tC2Q | RF | 5 | R56C127[0][A] | u_extr/ohcnt_1_s0/Q |
1.461 | 0.008 | tNET | FF | 1 | R56C127[0][A] | u_extr/n740_s1/I1 |
1.652 | 0.191 | tINS | FF | 1 | R56C127[0][A] | u_extr/n740_s1/F |
1.652 | 0.000 | tNET | FF | 1 | R56C127[0][A] | u_extr/ohcnt_1_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_R[3] | u_pll_50m/PLL_inst/CLKOUT1 |
1.277 | 1.277 | tNET | RR | 1 | R56C127[0][A] | u_extr/ohcnt_1_s0/CLK |
1.278 | 0.001 | tHld | 1 | R56C127[0][A] | u_extr/ohcnt_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.277, 100.000% |
Arrival Data Path Delay | cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.277, 100.000% |
Path10
Path Summary:
Slack | 0.374 |
Data Arrival Time | 1.645 |
Data Required Time | 1.271 |
From | frame_2_s0 |
To | frame_2_s0 |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_R[3] | u_pll_50m/PLL_inst/CLKOUT1 |
1.270 | 1.270 | tNET | RR | 1 | R57C130[1][A] | frame_2_s0/CLK |
1.446 | 0.176 | tC2Q | RF | 3 | R57C130[1][A] | frame_2_s0/Q |
1.454 | 0.008 | tNET | FF | 1 | R57C130[1][A] | n385_s2/I3 |
1.645 | 0.191 | tINS | FF | 1 | R57C130[1][A] | n385_s2/F |
1.645 | 0.000 | tNET | FF | 1 | R57C130[1][A] | frame_2_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_R[3] | u_pll_50m/PLL_inst/CLKOUT1 |
1.270 | 1.270 | tNET | RR | 1 | R57C130[1][A] | frame_2_s0/CLK |
1.271 | 0.001 | tHld | 1 | R57C130[1][A] | frame_2_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.270, 100.000% |
Arrival Data Path Delay | cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.270, 100.000% |
Path11
Path Summary:
Slack | 0.377 |
Data Arrival Time | 1.656 |
Data Required Time | 1.278 |
From | u_extr/ovcnt_4_s1 |
To | u_extr/ovcnt_4_s1 |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_R[3] | u_pll_50m/PLL_inst/CLKOUT1 |
1.277 | 1.277 | tNET | RR | 1 | R56C127[1][A] | u_extr/ovcnt_4_s1/CLK |
1.453 | 0.176 | tC2Q | RF | 7 | R56C127[1][A] | u_extr/ovcnt_4_s1/Q |
1.465 | 0.011 | tNET | FF | 1 | R56C127[1][A] | u_extr/n791_s2/I2 |
1.656 | 0.191 | tINS | FF | 1 | R56C127[1][A] | u_extr/n791_s2/F |
1.656 | 0.000 | tNET | FF | 1 | R56C127[1][A] | u_extr/ovcnt_4_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_R[3] | u_pll_50m/PLL_inst/CLKOUT1 |
1.277 | 1.277 | tNET | RR | 1 | R56C127[1][A] | u_extr/ovcnt_4_s1/CLK |
1.278 | 0.001 | tHld | 1 | R56C127[1][A] | u_extr/ovcnt_4_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.277, 100.000% |
Arrival Data Path Delay | cell: 0.191, 50.495%; route: 0.011, 2.970%; tC2Q: 0.176, 46.535% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.277, 100.000% |
Path12
Path Summary:
Slack | 0.377 |
Data Arrival Time | 1.651 |
Data Required Time | 1.273 |
From | u_extr/ovcnt_5_s1 |
To | u_extr/ovcnt_5_s1 |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_R[3] | u_pll_50m/PLL_inst/CLKOUT1 |
1.272 | 1.272 | tNET | RR | 1 | R56C126[0][A] | u_extr/ovcnt_5_s1/CLK |
1.448 | 0.176 | tC2Q | RF | 6 | R56C126[0][A] | u_extr/ovcnt_5_s1/Q |
1.460 | 0.011 | tNET | FF | 1 | R56C126[0][A] | u_extr/n790_s4/I1 |
1.651 | 0.191 | tINS | FF | 1 | R56C126[0][A] | u_extr/n790_s4/F |
1.651 | 0.000 | tNET | FF | 1 | R56C126[0][A] | u_extr/ovcnt_5_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_R[3] | u_pll_50m/PLL_inst/CLKOUT1 |
1.272 | 1.272 | tNET | RR | 1 | R56C126[0][A] | u_extr/ovcnt_5_s1/CLK |
1.273 | 0.001 | tHld | 1 | R56C126[0][A] | u_extr/ovcnt_5_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.272, 100.000% |
Arrival Data Path Delay | cell: 0.191, 50.495%; route: 0.011, 2.970%; tC2Q: 0.176, 46.535% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.272, 100.000% |
Path13
Path Summary:
Slack | 0.377 |
Data Arrival Time | 1.628 |
Data Required Time | 1.251 |
From | u_extr/ovcnt_11_s1 |
To | u_extr/ovcnt_11_s1 |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_R[3] | u_pll_50m/PLL_inst/CLKOUT1 |
1.250 | 1.250 | tNET | RR | 1 | R54C125[0][A] | u_extr/ovcnt_11_s1/CLK |
1.426 | 0.176 | tC2Q | RF | 5 | R54C125[0][A] | u_extr/ovcnt_11_s1/Q |
1.437 | 0.011 | tNET | FF | 1 | R54C125[0][A] | u_extr/n784_s4/I1 |
1.628 | 0.191 | tINS | FF | 1 | R54C125[0][A] | u_extr/n784_s4/F |
1.628 | 0.000 | tNET | FF | 1 | R54C125[0][A] | u_extr/ovcnt_11_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_R[3] | u_pll_50m/PLL_inst/CLKOUT1 |
1.250 | 1.250 | tNET | RR | 1 | R54C125[0][A] | u_extr/ovcnt_11_s1/CLK |
1.251 | 0.001 | tHld | 1 | R54C125[0][A] | u_extr/ovcnt_11_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.250, 100.000% |
Arrival Data Path Delay | cell: 0.191, 50.495%; route: 0.011, 2.970%; tC2Q: 0.176, 46.535% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.250, 100.000% |
Path14
Path Summary:
Slack | 0.377 |
Data Arrival Time | 1.656 |
Data Required Time | 1.278 |
From | u_extr/ovcnt_12_s1 |
To | u_extr/ovcnt_12_s1 |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_R[3] | u_pll_50m/PLL_inst/CLKOUT1 |
1.277 | 1.277 | tNET | RR | 1 | R56C125[0][A] | u_extr/ovcnt_12_s1/CLK |
1.453 | 0.176 | tC2Q | RF | 6 | R56C125[0][A] | u_extr/ovcnt_12_s1/Q |
1.465 | 0.011 | tNET | FF | 1 | R56C125[0][A] | u_extr/n783_s5/I0 |
1.656 | 0.191 | tINS | FF | 1 | R56C125[0][A] | u_extr/n783_s5/F |
1.656 | 0.000 | tNET | FF | 1 | R56C125[0][A] | u_extr/ovcnt_12_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_R[3] | u_pll_50m/PLL_inst/CLKOUT1 |
1.277 | 1.277 | tNET | RR | 1 | R56C125[0][A] | u_extr/ovcnt_12_s1/CLK |
1.278 | 0.001 | tHld | 1 | R56C125[0][A] | u_extr/ovcnt_12_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.277, 100.000% |
Arrival Data Path Delay | cell: 0.191, 50.495%; route: 0.011, 2.970%; tC2Q: 0.176, 46.535% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.277, 100.000% |
Path15
Path Summary:
Slack | 0.377 |
Data Arrival Time | 1.628 |
Data Required Time | 1.251 |
From | u_extr/ohcnt_4_s0 |
To | u_extr/ohcnt_4_s0 |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_R[3] | u_pll_50m/PLL_inst/CLKOUT1 |
1.250 | 1.250 | tNET | RR | 1 | R54C127[0][A] | u_extr/ohcnt_4_s0/CLK |
1.426 | 0.176 | tC2Q | RF | 4 | R54C127[0][A] | u_extr/ohcnt_4_s0/Q |
1.437 | 0.011 | tNET | FF | 1 | R54C127[0][A] | u_extr/n737_s1/I2 |
1.628 | 0.191 | tINS | FF | 1 | R54C127[0][A] | u_extr/n737_s1/F |
1.628 | 0.000 | tNET | FF | 1 | R54C127[0][A] | u_extr/ohcnt_4_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_R[3] | u_pll_50m/PLL_inst/CLKOUT1 |
1.250 | 1.250 | tNET | RR | 1 | R54C127[0][A] | u_extr/ohcnt_4_s0/CLK |
1.251 | 0.001 | tHld | 1 | R54C127[0][A] | u_extr/ohcnt_4_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.250, 100.000% |
Arrival Data Path Delay | cell: 0.191, 50.495%; route: 0.011, 2.970%; tC2Q: 0.176, 46.535% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.250, 100.000% |
Path16
Path Summary:
Slack | 0.377 |
Data Arrival Time | 1.628 |
Data Required Time | 1.251 |
From | u_extr/ohcnt_5_s0 |
To | u_extr/ohcnt_5_s0 |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_R[3] | u_pll_50m/PLL_inst/CLKOUT1 |
1.250 | 1.250 | tNET | RR | 1 | R54C131[1][A] | u_extr/ohcnt_5_s0/CLK |
1.426 | 0.176 | tC2Q | RF | 5 | R54C131[1][A] | u_extr/ohcnt_5_s0/Q |
1.437 | 0.011 | tNET | FF | 1 | R54C131[1][A] | u_extr/n736_s1/I0 |
1.628 | 0.191 | tINS | FF | 1 | R54C131[1][A] | u_extr/n736_s1/F |
1.628 | 0.000 | tNET | FF | 1 | R54C131[1][A] | u_extr/ohcnt_5_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_R[3] | u_pll_50m/PLL_inst/CLKOUT1 |
1.250 | 1.250 | tNET | RR | 1 | R54C131[1][A] | u_extr/ohcnt_5_s0/CLK |
1.251 | 0.001 | tHld | 1 | R54C131[1][A] | u_extr/ohcnt_5_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.250, 100.000% |
Arrival Data Path Delay | cell: 0.191, 50.495%; route: 0.011, 2.970%; tC2Q: 0.176, 46.535% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.250, 100.000% |
Path17
Path Summary:
Slack | 0.377 |
Data Arrival Time | 1.628 |
Data Required Time | 1.251 |
From | u_extr/ohcnt_6_s0 |
To | u_extr/ohcnt_6_s0 |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_R[3] | u_pll_50m/PLL_inst/CLKOUT1 |
1.250 | 1.250 | tNET | RR | 1 | R54C131[0][A] | u_extr/ohcnt_6_s0/CLK |
1.426 | 0.176 | tC2Q | RF | 4 | R54C131[0][A] | u_extr/ohcnt_6_s0/Q |
1.437 | 0.011 | tNET | FF | 1 | R54C131[0][A] | u_extr/n735_s1/I2 |
1.628 | 0.191 | tINS | FF | 1 | R54C131[0][A] | u_extr/n735_s1/F |
1.628 | 0.000 | tNET | FF | 1 | R54C131[0][A] | u_extr/ohcnt_6_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_R[3] | u_pll_50m/PLL_inst/CLKOUT1 |
1.250 | 1.250 | tNET | RR | 1 | R54C131[0][A] | u_extr/ohcnt_6_s0/CLK |
1.251 | 0.001 | tHld | 1 | R54C131[0][A] | u_extr/ohcnt_6_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.250, 100.000% |
Arrival Data Path Delay | cell: 0.191, 50.495%; route: 0.011, 2.970%; tC2Q: 0.176, 46.535% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.250, 100.000% |
Path18
Path Summary:
Slack | 0.381 |
Data Arrival Time | 1.660 |
Data Required Time | 1.278 |
From | u_extr/ovcnt_0_s3 |
To | u_extr/ovcnt_0_s3 |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_R[3] | u_pll_50m/PLL_inst/CLKOUT1 |
1.277 | 1.277 | tNET | RR | 1 | R56C131[1][A] | u_extr/ovcnt_0_s3/CLK |
1.453 | 0.176 | tC2Q | RF | 7 | R56C131[1][A] | u_extr/ovcnt_0_s3/Q |
1.468 | 0.015 | tNET | FF | 1 | R56C131[1][A] | u_extr/n795_s6/I0 |
1.660 | 0.191 | tINS | FF | 1 | R56C131[1][A] | u_extr/n795_s6/F |
1.660 | 0.000 | tNET | FF | 1 | R56C131[1][A] | u_extr/ovcnt_0_s3/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_R[3] | u_pll_50m/PLL_inst/CLKOUT1 |
1.277 | 1.277 | tNET | RR | 1 | R56C131[1][A] | u_extr/ovcnt_0_s3/CLK |
1.278 | 0.001 | tHld | 1 | R56C131[1][A] | u_extr/ovcnt_0_s3 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.277, 100.000% |
Arrival Data Path Delay | cell: 0.191, 50.000%; route: 0.015, 3.922%; tC2Q: 0.176, 46.078% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.277, 100.000% |
Path19
Path Summary:
Slack | 0.381 |
Data Arrival Time | 1.627 |
Data Required Time | 1.246 |
From | u_extr/ovcnt_10_s1 |
To | u_extr/ovcnt_10_s1 |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_R[3] | u_pll_50m/PLL_inst/CLKOUT1 |
1.245 | 1.245 | tNET | RR | 1 | R54C126[0][A] | u_extr/ovcnt_10_s1/CLK |
1.421 | 0.176 | tC2Q | RF | 6 | R54C126[0][A] | u_extr/ovcnt_10_s1/Q |
1.436 | 0.015 | tNET | FF | 1 | R54C126[0][A] | u_extr/n785_s4/I1 |
1.627 | 0.191 | tINS | FF | 1 | R54C126[0][A] | u_extr/n785_s4/F |
1.627 | 0.000 | tNET | FF | 1 | R54C126[0][A] | u_extr/ovcnt_10_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_R[3] | u_pll_50m/PLL_inst/CLKOUT1 |
1.245 | 1.245 | tNET | RR | 1 | R54C126[0][A] | u_extr/ovcnt_10_s1/CLK |
1.246 | 0.001 | tHld | 1 | R54C126[0][A] | u_extr/ovcnt_10_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.245, 100.000% |
Arrival Data Path Delay | cell: 0.191, 50.000%; route: 0.015, 3.922%; tC2Q: 0.176, 46.078% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.245, 100.000% |
Path20
Path Summary:
Slack | 0.381 |
Data Arrival Time | 1.665 |
Data Required Time | 1.283 |
From | u_extr/buf_ra_4_s0 |
To | u_extr/buf_ra_4_s0 |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_R[3] | u_pll_50m/PLL_inst/CLKOUT1 |
1.282 | 1.282 | tNET | RR | 1 | R56C124[1][A] | u_extr/buf_ra_4_s0/CLK |
1.458 | 0.176 | tC2Q | RF | 5 | R56C124[1][A] | u_extr/buf_ra_4_s0/Q |
1.473 | 0.015 | tNET | FF | 1 | R56C124[1][A] | u_extr/n882_s3/I0 |
1.665 | 0.191 | tINS | FF | 1 | R56C124[1][A] | u_extr/n882_s3/F |
1.665 | 0.000 | tNET | FF | 1 | R56C124[1][A] | u_extr/buf_ra_4_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_R[3] | u_pll_50m/PLL_inst/CLKOUT1 |
1.282 | 1.282 | tNET | RR | 1 | R56C124[1][A] | u_extr/buf_ra_4_s0/CLK |
1.283 | 0.001 | tHld | 1 | R56C124[1][A] | u_extr/buf_ra_4_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.282, 100.000% |
Arrival Data Path Delay | cell: 0.191, 50.000%; route: 0.015, 3.922%; tC2Q: 0.176, 46.078% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.282, 100.000% |
Recovery Analysis Report
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 0.349 |
Data Arrival Time | 9.338 |
Data Required Time | 9.687 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_match_1/trig_dly_0_s0 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
6.109 | 2.538 | tNET | FF | 1 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.552 | 0.442 | tC2Q | FF | 61 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
9.338 | 2.786 | tNET | FF | 1 | R52C106[0][A] | gw_gao_inst_0/u_la0_top/u_ao_match_1/trig_dly_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | pixel_clk | ||||
7.143 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
10.035 | 2.892 | tNET | RR | 1 | R52C106[0][A] | gw_gao_inst_0/u_la0_top/u_ao_match_1/trig_dly_0_s0/CLK |
9.687 | -0.347 | tSu | 1 | R52C106[0][A] | gw_gao_inst_0/u_la0_top/u_ao_match_1/trig_dly_0_s0 |
Path Statistics:
Clock Skew | 0.354 |
Setup Relationship | 3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.538, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.786, 86.295%; tC2Q: 0.442, 13.705% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.892, 100.000% |
Path2
Path Summary:
Slack | 0.554 |
Data Arrival Time | 9.137 |
Data Required Time | 9.691 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_match_1/match_sep_s0 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
6.109 | 2.538 | tNET | FF | 1 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.552 | 0.442 | tC2Q | FF | 61 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
9.137 | 2.585 | tNET | FF | 1 | R54C106[1][A] | gw_gao_inst_0/u_la0_top/u_ao_match_1/match_sep_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | pixel_clk | ||||
7.143 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
10.039 | 2.896 | tNET | RR | 1 | R54C106[1][A] | gw_gao_inst_0/u_la0_top/u_ao_match_1/match_sep_s0/CLK |
9.691 | -0.347 | tSu | 1 | R54C106[1][A] | gw_gao_inst_0/u_la0_top/u_ao_match_1/match_sep_s0 |
Path Statistics:
Clock Skew | 0.358 |
Setup Relationship | 3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.538, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.585, 85.384%; tC2Q: 0.442, 14.616% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.896, 100.000% |
Path3
Path Summary:
Slack | 0.554 |
Data Arrival Time | 9.137 |
Data Required Time | 9.691 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_match_1/trig_dly_in_0_s0 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
6.109 | 2.538 | tNET | FF | 1 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.552 | 0.442 | tC2Q | FF | 61 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
9.137 | 2.585 | tNET | FF | 1 | R54C106[2][A] | gw_gao_inst_0/u_la0_top/u_ao_match_1/trig_dly_in_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | pixel_clk | ||||
7.143 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
10.039 | 2.896 | tNET | RR | 1 | R54C106[2][A] | gw_gao_inst_0/u_la0_top/u_ao_match_1/trig_dly_in_0_s0/CLK |
9.691 | -0.347 | tSu | 1 | R54C106[2][A] | gw_gao_inst_0/u_la0_top/u_ao_match_1/trig_dly_in_0_s0 |
Path Statistics:
Clock Skew | 0.358 |
Setup Relationship | 3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.538, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.585, 85.384%; tC2Q: 0.442, 14.616% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.896, 100.000% |
Path4
Path Summary:
Slack | 0.771 |
Data Arrival Time | 8.918 |
Data Required Time | 9.689 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_0_s0 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
6.109 | 2.538 | tNET | FF | 1 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.552 | 0.442 | tC2Q | FF | 61 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
8.918 | 2.366 | tNET | FF | 1 | R53C106[0][A] | gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | pixel_clk | ||||
7.143 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
10.037 | 2.894 | tNET | RR | 1 | R53C106[0][A] | gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_0_s0/CLK |
9.689 | -0.347 | tSu | 1 | R53C106[0][A] | gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_0_s0 |
Path Statistics:
Clock Skew | 0.356 |
Setup Relationship | 3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.538, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.366, 84.246%; tC2Q: 0.442, 15.754% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.894, 100.000% |
Path5
Path Summary:
Slack | 0.954 |
Data Arrival Time | 8.717 |
Data Required Time | 9.671 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
6.109 | 2.538 | tNET | FF | 1 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.552 | 0.442 | tC2Q | FF | 61 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
8.717 | 2.165 | tNET | FF | 1 | R53C104[2][B] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | pixel_clk | ||||
7.143 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
10.018 | 2.875 | tNET | RR | 1 | R53C104[2][B] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLK |
9.671 | -0.347 | tSu | 1 | R53C104[2][B] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0 |
Path Statistics:
Clock Skew | 0.337 |
Setup Relationship | 3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.538, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.165, 83.030%; tC2Q: 0.442, 16.970% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.875, 100.000% |
Path6
Path Summary:
Slack | 0.954 |
Data Arrival Time | 8.717 |
Data Required Time | 9.671 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_0_s0 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
6.109 | 2.538 | tNET | FF | 1 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.552 | 0.442 | tC2Q | FF | 61 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
8.717 | 2.165 | tNET | FF | 1 | R53C104[1][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | pixel_clk | ||||
7.143 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
10.018 | 2.875 | tNET | RR | 1 | R53C104[1][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_0_s0/CLK |
9.671 | -0.347 | tSu | 1 | R53C104[1][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_0_s0 |
Path Statistics:
Clock Skew | 0.337 |
Setup Relationship | 3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.538, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.165, 83.030%; tC2Q: 0.442, 16.970% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.875, 100.000% |
Path7
Path Summary:
Slack | 0.954 |
Data Arrival Time | 8.717 |
Data Required Time | 9.671 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
6.109 | 2.538 | tNET | FF | 1 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.552 | 0.442 | tC2Q | FF | 61 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
8.717 | 2.165 | tNET | FF | 1 | R53C104[2][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | pixel_clk | ||||
7.143 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
10.018 | 2.875 | tNET | RR | 1 | R53C104[2][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLK |
9.671 | -0.347 | tSu | 1 | R53C104[2][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0 |
Path Statistics:
Clock Skew | 0.337 |
Setup Relationship | 3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.538, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.165, 83.030%; tC2Q: 0.442, 16.970% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.875, 100.000% |
Path8
Path Summary:
Slack | 1.087 |
Data Arrival Time | 8.604 |
Data Required Time | 9.691 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
6.109 | 2.538 | tNET | FF | 1 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.552 | 0.442 | tC2Q | FF | 61 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
8.604 | 2.053 | tNET | FF | 1 | R54C94[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | pixel_clk | ||||
7.143 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
10.039 | 2.896 | tNET | RR | 1 | R54C94[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK |
9.691 | -0.347 | tSu | 1 | R54C94[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1 |
Path Statistics:
Clock Skew | 0.358 |
Setup Relationship | 3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.538, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.053, 82.265%; tC2Q: 0.442, 17.735% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.896, 100.000% |
Path9
Path Summary:
Slack | 1.087 |
Data Arrival Time | 8.604 |
Data Required Time | 9.691 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
6.109 | 2.538 | tNET | FF | 1 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.552 | 0.442 | tC2Q | FF | 61 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
8.604 | 2.053 | tNET | FF | 1 | R54C94[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | pixel_clk | ||||
7.143 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
10.039 | 2.896 | tNET | RR | 1 | R54C94[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK |
9.691 | -0.347 | tSu | 1 | R54C94[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1 |
Path Statistics:
Clock Skew | 0.358 |
Setup Relationship | 3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.538, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.053, 82.265%; tC2Q: 0.442, 17.735% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.896, 100.000% |
Path10
Path Summary:
Slack | 1.191 |
Data Arrival Time | 8.478 |
Data Required Time | 9.669 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
6.109 | 2.538 | tNET | FF | 1 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.552 | 0.442 | tC2Q | FF | 61 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
8.478 | 1.926 | tNET | FF | 1 | R52C100[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | pixel_clk | ||||
7.143 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
10.016 | 2.873 | tNET | RR | 1 | R52C100[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLK |
9.669 | -0.347 | tSu | 1 | R52C100[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1 |
Path Statistics:
Clock Skew | 0.335 |
Setup Relationship | 3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.538, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.926, 81.319%; tC2Q: 0.442, 18.681% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.873, 100.000% |
Path11
Path Summary:
Slack | 1.191 |
Data Arrival Time | 8.478 |
Data Required Time | 9.669 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
6.109 | 2.538 | tNET | FF | 1 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.552 | 0.442 | tC2Q | FF | 61 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
8.478 | 1.926 | tNET | FF | 1 | R52C100[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | pixel_clk | ||||
7.143 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
10.016 | 2.873 | tNET | RR | 1 | R52C100[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLK |
9.669 | -0.347 | tSu | 1 | R52C100[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1 |
Path Statistics:
Clock Skew | 0.335 |
Setup Relationship | 3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.538, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.926, 81.319%; tC2Q: 0.442, 18.681% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.873, 100.000% |
Path12
Path Summary:
Slack | 1.200 |
Data Arrival Time | 8.489 |
Data Required Time | 9.689 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
6.109 | 2.538 | tNET | FF | 1 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.552 | 0.442 | tC2Q | FF | 61 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
8.489 | 1.938 | tNET | FF | 1 | R53C102[2][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | pixel_clk | ||||
7.143 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
10.037 | 2.894 | tNET | RR | 1 | R53C102[2][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLK |
9.689 | -0.347 | tSu | 1 | R53C102[2][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0 |
Path Statistics:
Clock Skew | 0.356 |
Setup Relationship | 3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.538, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.938, 81.408%; tC2Q: 0.442, 18.592% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.894, 100.000% |
Path13
Path Summary:
Slack | 1.200 |
Data Arrival Time | 8.478 |
Data Required Time | 9.678 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
6.109 | 2.538 | tNET | FF | 1 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.552 | 0.442 | tC2Q | FF | 61 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
8.478 | 1.926 | tNET | FF | 1 | R52C101[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | pixel_clk | ||||
7.143 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
10.026 | 2.883 | tNET | RR | 1 | R52C101[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLK |
9.678 | -0.347 | tSu | 1 | R52C101[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1 |
Path Statistics:
Clock Skew | 0.345 |
Setup Relationship | 3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.538, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.926, 81.319%; tC2Q: 0.442, 18.681% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.883, 100.000% |
Path14
Path Summary:
Slack | 1.200 |
Data Arrival Time | 8.478 |
Data Required Time | 9.678 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
6.109 | 2.538 | tNET | FF | 1 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.552 | 0.442 | tC2Q | FF | 61 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
8.478 | 1.926 | tNET | FF | 1 | R52C101[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | pixel_clk | ||||
7.143 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
10.026 | 2.883 | tNET | RR | 1 | R52C101[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLK |
9.678 | -0.347 | tSu | 1 | R52C101[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1 |
Path Statistics:
Clock Skew | 0.345 |
Setup Relationship | 3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.538, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.926, 81.319%; tC2Q: 0.442, 18.681% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.883, 100.000% |
Path15
Path Summary:
Slack | 1.200 |
Data Arrival Time | 8.478 |
Data Required Time | 9.678 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_10_s1 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
6.109 | 2.538 | tNET | FF | 1 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.552 | 0.442 | tC2Q | FF | 61 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
8.478 | 1.926 | tNET | FF | 1 | R52C101[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_10_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | pixel_clk | ||||
7.143 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
10.026 | 2.883 | tNET | RR | 1 | R52C101[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_10_s1/CLK |
9.678 | -0.347 | tSu | 1 | R52C101[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_10_s1 |
Path Statistics:
Clock Skew | 0.345 |
Setup Relationship | 3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.538, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.926, 81.319%; tC2Q: 0.442, 18.681% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.883, 100.000% |
Path16
Path Summary:
Slack | 1.254 |
Data Arrival Time | 8.462 |
Data Required Time | 9.716 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s1 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
6.109 | 2.538 | tNET | FF | 1 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.552 | 0.442 | tC2Q | FF | 61 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
8.462 | 1.910 | tNET | FF | 1 | R56C99[3][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | pixel_clk | ||||
7.143 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
10.064 | 2.921 | tNET | RR | 1 | R56C99[3][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s1/CLK |
9.716 | -0.347 | tSu | 1 | R56C99[3][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s1 |
Path Statistics:
Clock Skew | 0.383 |
Setup Relationship | 3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.538, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.910, 81.190%; tC2Q: 0.442, 18.810% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.921, 100.000% |
Path17
Path Summary:
Slack | 1.277 |
Data Arrival Time | 8.429 |
Data Required Time | 9.707 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
6.109 | 2.538 | tNET | FF | 1 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.552 | 0.442 | tC2Q | FF | 61 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
8.429 | 1.878 | tNET | FF | 1 | R56C96[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | pixel_clk | ||||
7.143 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
10.054 | 2.911 | tNET | RR | 1 | R56C96[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/CLK |
9.707 | -0.347 | tSu | 1 | R56C96[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5 |
Path Statistics:
Clock Skew | 0.373 |
Setup Relationship | 3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.538, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.878, 80.927%; tC2Q: 0.442, 19.073% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.911, 100.000% |
Path18
Path Summary:
Slack | 1.391 |
Data Arrival Time | 8.279 |
Data Required Time | 9.671 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
6.109 | 2.538 | tNET | FF | 1 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.552 | 0.442 | tC2Q | FF | 61 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
8.279 | 1.727 | tNET | FF | 1 | R53C100[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | pixel_clk | ||||
7.143 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
10.018 | 2.875 | tNET | RR | 1 | R53C100[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLK |
9.671 | -0.347 | tSu | 1 | R53C100[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1 |
Path Statistics:
Clock Skew | 0.337 |
Setup Relationship | 3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.538, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.727, 79.608%; tC2Q: 0.442, 20.392% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.875, 100.000% |
Path19
Path Summary:
Slack | 1.401 |
Data Arrival Time | 8.279 |
Data Required Time | 9.680 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
6.109 | 2.538 | tNET | FF | 1 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.552 | 0.442 | tC2Q | FF | 61 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
8.279 | 1.727 | tNET | FF | 1 | R53C101[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | pixel_clk | ||||
7.143 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
10.027 | 2.884 | tNET | RR | 1 | R53C101[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLK |
9.680 | -0.347 | tSu | 1 | R53C101[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1 |
Path Statistics:
Clock Skew | 0.347 |
Setup Relationship | 3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.538, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.727, 79.608%; tC2Q: 0.442, 20.392% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.884, 100.000% |
Path20
Path Summary:
Slack | 1.442 |
Data Arrival Time | 8.246 |
Data Required Time | 9.687 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
6.109 | 2.538 | tNET | FF | 1 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.552 | 0.442 | tC2Q | FF | 61 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
8.246 | 1.694 | tNET | FF | 1 | R52C98[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | pixel_clk | ||||
7.143 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
10.035 | 2.892 | tNET | RR | 1 | R52C98[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/CLK |
9.687 | -0.347 | tSu | 1 | R52C98[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1 |
Path Statistics:
Clock Skew | 0.354 |
Setup Relationship | 3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.538, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.694, 79.286%; tC2Q: 0.442, 20.714% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.892, 100.000% |
Path21
Path Summary:
Slack | 1.442 |
Data Arrival Time | 8.246 |
Data Required Time | 9.687 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
6.109 | 2.538 | tNET | FF | 1 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.552 | 0.442 | tC2Q | FF | 61 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
8.246 | 1.694 | tNET | FF | 1 | R52C98[1][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | pixel_clk | ||||
7.143 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
10.035 | 2.892 | tNET | RR | 1 | R52C98[1][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLK |
9.687 | -0.347 | tSu | 1 | R52C98[1][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1 |
Path Statistics:
Clock Skew | 0.354 |
Setup Relationship | 3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.538, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.694, 79.286%; tC2Q: 0.442, 20.714% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.892, 100.000% |
Path22
Path Summary:
Slack | 1.442 |
Data Arrival Time | 8.246 |
Data Required Time | 9.687 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_10_s1 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
6.109 | 2.538 | tNET | FF | 1 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.552 | 0.442 | tC2Q | FF | 61 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
8.246 | 1.694 | tNET | FF | 1 | R52C98[1][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_10_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | pixel_clk | ||||
7.143 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
10.035 | 2.892 | tNET | RR | 1 | R52C98[1][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_10_s1/CLK |
9.687 | -0.347 | tSu | 1 | R52C98[1][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_10_s1 |
Path Statistics:
Clock Skew | 0.354 |
Setup Relationship | 3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.538, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.694, 79.286%; tC2Q: 0.442, 20.714% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.892, 100.000% |
Path23
Path Summary:
Slack | 1.444 |
Data Arrival Time | 8.234 |
Data Required Time | 9.678 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
6.109 | 2.538 | tNET | FF | 1 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.552 | 0.442 | tC2Q | FF | 61 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
8.234 | 1.683 | tNET | FF | 1 | R52C99[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | pixel_clk | ||||
7.143 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
10.026 | 2.883 | tNET | RR | 1 | R52C99[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLK |
9.678 | -0.347 | tSu | 1 | R52C99[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1 |
Path Statistics:
Clock Skew | 0.345 |
Setup Relationship | 3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.538, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.683, 79.176%; tC2Q: 0.442, 20.824% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.883, 100.000% |
Path24
Path Summary:
Slack | 1.444 |
Data Arrival Time | 8.234 |
Data Required Time | 9.678 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
6.109 | 2.538 | tNET | FF | 1 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.552 | 0.442 | tC2Q | FF | 61 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
8.234 | 1.683 | tNET | FF | 1 | R52C99[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | pixel_clk | ||||
7.143 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
10.026 | 2.883 | tNET | RR | 1 | R52C99[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLK |
9.678 | -0.347 | tSu | 1 | R52C99[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1 |
Path Statistics:
Clock Skew | 0.345 |
Setup Relationship | 3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.538, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.683, 79.176%; tC2Q: 0.442, 20.824% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.883, 100.000% |
Path25
Path Summary:
Slack | 1.444 |
Data Arrival Time | 8.234 |
Data Required Time | 9.678 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
6.109 | 2.538 | tNET | FF | 1 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.552 | 0.442 | tC2Q | FF | 61 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
8.234 | 1.683 | tNET | FF | 1 | R52C99[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | pixel_clk | ||||
7.143 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
10.026 | 2.883 | tNET | RR | 1 | R52C99[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLK |
9.678 | -0.347 | tSu | 1 | R52C99[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1 |
Path Statistics:
Clock Skew | 0.345 |
Setup Relationship | 3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.538, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.683, 79.176%; tC2Q: 0.442, 20.824% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.883, 100.000% |
Removal Analysis Report
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 4.536 |
Data Arrival Time | 5.655 |
Data Required Time | 1.120 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
5.160 | 1.589 | tNET | FF | 1 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
5.358 | 0.198 | tC2Q | FR | 61 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
5.655 | 0.297 | tNET | RR | 1 | R56C101[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
1.308 | 1.308 | tNET | RR | 1 | R56C101[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK |
1.120 | -0.189 | tHld | 1 | R56C101[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1 |
Path Statistics:
Clock Skew | -0.280 |
Hold Relationship | -3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.589, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.297, 60.101%; tC2Q: 0.198, 39.899% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.308, 100.000% |
Path2
Path Summary:
Slack | 4.536 |
Data Arrival Time | 5.655 |
Data Required Time | 1.120 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/trigger_seq_start_s1 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
5.160 | 1.589 | tNET | FF | 1 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
5.358 | 0.198 | tC2Q | FR | 61 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
5.655 | 0.297 | tNET | RR | 1 | R56C101[1][A] | gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
1.308 | 1.308 | tNET | RR | 1 | R56C101[1][A] | gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLK |
1.120 | -0.189 | tHld | 1 | R56C101[1][A] | gw_gao_inst_0/u_la0_top/trigger_seq_start_s1 |
Path Statistics:
Clock Skew | -0.280 |
Hold Relationship | -3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.589, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.297, 60.101%; tC2Q: 0.198, 39.899% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.308, 100.000% |
Path3
Path Summary:
Slack | 4.536 |
Data Arrival Time | 5.655 |
Data Required Time | 1.120 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/triger_s0 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
5.160 | 1.589 | tNET | FF | 1 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
5.358 | 0.198 | tC2Q | FR | 61 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
5.655 | 0.297 | tNET | RR | 1 | R56C101[0][A] | gw_gao_inst_0/u_la0_top/triger_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
1.308 | 1.308 | tNET | RR | 1 | R56C101[0][A] | gw_gao_inst_0/u_la0_top/triger_s0/CLK |
1.120 | -0.189 | tHld | 1 | R56C101[0][A] | gw_gao_inst_0/u_la0_top/triger_s0 |
Path Statistics:
Clock Skew | -0.280 |
Hold Relationship | -3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.589, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.297, 60.101%; tC2Q: 0.198, 39.899% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.308, 100.000% |
Path4
Path Summary:
Slack | 4.612 |
Data Arrival Time | 5.729 |
Data Required Time | 1.117 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
5.160 | 1.589 | tNET | FF | 1 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
5.358 | 0.198 | tC2Q | FR | 61 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
5.729 | 0.371 | tNET | RR | 1 | R57C103[0][A] | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
1.306 | 1.306 | tNET | RR | 1 | R57C103[0][A] | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLK |
1.117 | -0.189 | tHld | 1 | R57C103[0][A] | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0 |
Path Statistics:
Clock Skew | -0.283 |
Hold Relationship | -3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.589, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.371, 65.275%; tC2Q: 0.198, 34.725% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.306, 100.000% |
Path5
Path Summary:
Slack | 4.612 |
Data Arrival Time | 5.729 |
Data Required Time | 1.117 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
5.160 | 1.589 | tNET | FF | 1 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
5.358 | 0.198 | tC2Q | FR | 61 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
5.729 | 0.371 | tNET | RR | 1 | R57C103[1][A] | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
1.306 | 1.306 | tNET | RR | 1 | R57C103[1][A] | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLK |
1.117 | -0.189 | tHld | 1 | R57C103[1][A] | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0 |
Path Statistics:
Clock Skew | -0.283 |
Hold Relationship | -3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.589, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.371, 65.275%; tC2Q: 0.198, 34.725% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.306, 100.000% |
Path6
Path Summary:
Slack | 4.846 |
Data Arrival Time | 5.943 |
Data Required Time | 1.097 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
5.160 | 1.589 | tNET | FF | 1 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
5.358 | 0.198 | tC2Q | FR | 61 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
5.943 | 0.585 | tNET | RR | 1 | R54C102[2][B] | gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
1.286 | 1.286 | tNET | RR | 1 | R54C102[2][B] | gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLK |
1.097 | -0.189 | tHld | 1 | R54C102[2][B] | gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1 |
Path Statistics:
Clock Skew | -0.303 |
Hold Relationship | -3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.589, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.585, 74.760%; tC2Q: 0.198, 25.240% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.286, 100.000% |
Path7
Path Summary:
Slack | 5.048 |
Data Arrival Time | 6.140 |
Data Required Time | 1.092 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
5.160 | 1.589 | tNET | FF | 1 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
5.358 | 0.198 | tC2Q | FR | 61 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.140 | 0.783 | tNET | RR | 1 | R54C93[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
1.281 | 1.281 | tNET | RR | 1 | R54C93[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK |
1.092 | -0.189 | tHld | 1 | R54C93[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1 |
Path Statistics:
Clock Skew | -0.308 |
Hold Relationship | -3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.589, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.783, 79.847%; tC2Q: 0.198, 20.153% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.281, 100.000% |
Path8
Path Summary:
Slack | 5.048 |
Data Arrival Time | 6.140 |
Data Required Time | 1.092 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
5.160 | 1.589 | tNET | FF | 1 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
5.358 | 0.198 | tC2Q | FR | 61 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.140 | 0.783 | tNET | RR | 1 | R54C93[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
1.281 | 1.281 | tNET | RR | 1 | R54C93[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK |
1.092 | -0.189 | tHld | 1 | R54C93[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1 |
Path Statistics:
Clock Skew | -0.308 |
Hold Relationship | -3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.589, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.783, 79.847%; tC2Q: 0.198, 20.153% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.281, 100.000% |
Path9
Path Summary:
Slack | 5.050 |
Data Arrival Time | 6.140 |
Data Required Time | 1.091 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
5.160 | 1.589 | tNET | FF | 1 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
5.358 | 0.198 | tC2Q | FR | 61 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.140 | 0.783 | tNET | RR | 1 | R53C93[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
1.279 | 1.279 | tNET | RR | 1 | R53C93[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK |
1.091 | -0.189 | tHld | 1 | R53C93[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1 |
Path Statistics:
Clock Skew | -0.309 |
Hold Relationship | -3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.589, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.783, 79.847%; tC2Q: 0.198, 20.153% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.279, 100.000% |
Path10
Path Summary:
Slack | 5.057 |
Data Arrival Time | 6.149 |
Data Required Time | 1.092 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
5.160 | 1.589 | tNET | FF | 1 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
5.358 | 0.198 | tC2Q | FR | 61 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.149 | 0.791 | tNET | RR | 1 | R54C97[1][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
1.281 | 1.281 | tNET | RR | 1 | R54C97[1][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLK |
1.092 | -0.189 | tHld | 1 | R54C97[1][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1 |
Path Statistics:
Clock Skew | -0.308 |
Hold Relationship | -3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.589, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.791, 80.025%; tC2Q: 0.198, 19.975% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.281, 100.000% |
Path11
Path Summary:
Slack | 5.057 |
Data Arrival Time | 6.149 |
Data Required Time | 1.092 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
5.160 | 1.589 | tNET | FF | 1 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
5.358 | 0.198 | tC2Q | FR | 61 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.149 | 0.791 | tNET | RR | 1 | R54C97[1][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
1.281 | 1.281 | tNET | RR | 1 | R54C97[1][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLK |
1.092 | -0.189 | tHld | 1 | R54C97[1][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1 |
Path Statistics:
Clock Skew | -0.308 |
Hold Relationship | -3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.589, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.791, 80.025%; tC2Q: 0.198, 19.975% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.281, 100.000% |
Path12
Path Summary:
Slack | 5.057 |
Data Arrival Time | 6.149 |
Data Required Time | 1.092 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
5.160 | 1.589 | tNET | FF | 1 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
5.358 | 0.198 | tC2Q | FR | 61 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.149 | 0.791 | tNET | RR | 1 | R54C97[0][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
1.281 | 1.281 | tNET | RR | 1 | R54C97[0][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLK |
1.092 | -0.189 | tHld | 1 | R54C97[0][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1 |
Path Statistics:
Clock Skew | -0.308 |
Hold Relationship | -3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.589, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.791, 80.025%; tC2Q: 0.198, 19.975% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.281, 100.000% |
Path13
Path Summary:
Slack | 5.057 |
Data Arrival Time | 6.149 |
Data Required Time | 1.092 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_end_dly_s0 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
5.160 | 1.589 | tNET | FF | 1 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
5.358 | 0.198 | tC2Q | FR | 61 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.149 | 0.791 | tNET | RR | 1 | R54C97[2][A] | gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
1.281 | 1.281 | tNET | RR | 1 | R54C97[2][A] | gw_gao_inst_0/u_la0_top/capture_end_dly_s0/CLK |
1.092 | -0.189 | tHld | 1 | R54C97[2][A] | gw_gao_inst_0/u_la0_top/capture_end_dly_s0 |
Path Statistics:
Clock Skew | -0.308 |
Hold Relationship | -3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.589, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.791, 80.025%; tC2Q: 0.198, 19.975% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.281, 100.000% |
Path14
Path Summary:
Slack | 5.058 |
Data Arrival Time | 6.149 |
Data Required Time | 1.091 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
5.160 | 1.589 | tNET | FF | 1 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
5.358 | 0.198 | tC2Q | FR | 61 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.149 | 0.791 | tNET | RR | 1 | R53C97[1][B] | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
1.279 | 1.279 | tNET | RR | 1 | R53C97[1][B] | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLK |
1.091 | -0.189 | tHld | 1 | R53C97[1][B] | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0 |
Path Statistics:
Clock Skew | -0.309 |
Hold Relationship | -3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.589, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.791, 80.025%; tC2Q: 0.198, 19.975% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.279, 100.000% |
Path15
Path Summary:
Slack | 5.058 |
Data Arrival Time | 6.149 |
Data Required Time | 1.091 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
5.160 | 1.589 | tNET | FF | 1 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
5.358 | 0.198 | tC2Q | FR | 61 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.149 | 0.791 | tNET | RR | 1 | R53C97[1][A] | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
1.279 | 1.279 | tNET | RR | 1 | R53C97[1][A] | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLK |
1.091 | -0.189 | tHld | 1 | R53C97[1][A] | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0 |
Path Statistics:
Clock Skew | -0.309 |
Hold Relationship | -3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.589, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.791, 80.025%; tC2Q: 0.198, 19.975% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.279, 100.000% |
Path16
Path Summary:
Slack | 5.171 |
Data Arrival Time | 6.260 |
Data Required Time | 1.089 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
5.160 | 1.589 | tNET | FF | 1 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
5.358 | 0.198 | tC2Q | FR | 61 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.260 | 0.903 | tNET | RR | 1 | R52C93[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
1.278 | 1.278 | tNET | RR | 1 | R52C93[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK |
1.089 | -0.189 | tHld | 1 | R52C93[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1 |
Path Statistics:
Clock Skew | -0.311 |
Hold Relationship | -3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.589, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.903, 82.045%; tC2Q: 0.198, 17.955% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.278, 100.000% |
Path17
Path Summary:
Slack | 5.174 |
Data Arrival Time | 6.261 |
Data Required Time | 1.087 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
5.160 | 1.589 | tNET | FF | 1 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
5.358 | 0.198 | tC2Q | FR | 61 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.261 | 0.904 | tNET | RR | 1 | R54C96[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
1.276 | 1.276 | tNET | RR | 1 | R54C96[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK |
1.087 | -0.189 | tHld | 1 | R54C96[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1 |
Path Statistics:
Clock Skew | -0.313 |
Hold Relationship | -3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.589, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.904, 82.066%; tC2Q: 0.198, 17.934% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.276, 100.000% |
Path18
Path Summary:
Slack | 5.174 |
Data Arrival Time | 6.261 |
Data Required Time | 1.087 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
5.160 | 1.589 | tNET | FF | 1 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
5.358 | 0.198 | tC2Q | FR | 61 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.261 | 0.904 | tNET | RR | 1 | R54C96[3][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
1.276 | 1.276 | tNET | RR | 1 | R54C96[3][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLK |
1.087 | -0.189 | tHld | 1 | R54C96[3][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3 |
Path Statistics:
Clock Skew | -0.313 |
Hold Relationship | -3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.589, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.904, 82.066%; tC2Q: 0.198, 17.934% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.276, 100.000% |
Path19
Path Summary:
Slack | 5.174 |
Data Arrival Time | 6.261 |
Data Required Time | 1.087 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
5.160 | 1.589 | tNET | FF | 1 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
5.358 | 0.198 | tC2Q | FR | 61 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.261 | 0.904 | tNET | RR | 1 | R54C96[0][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
1.276 | 1.276 | tNET | RR | 1 | R54C96[0][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLK |
1.087 | -0.189 | tHld | 1 | R54C96[0][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1 |
Path Statistics:
Clock Skew | -0.313 |
Hold Relationship | -3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.589, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.904, 82.066%; tC2Q: 0.198, 17.934% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.276, 100.000% |
Path20
Path Summary:
Slack | 5.174 |
Data Arrival Time | 6.261 |
Data Required Time | 1.087 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
5.160 | 1.589 | tNET | FF | 1 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
5.358 | 0.198 | tC2Q | FR | 61 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.261 | 0.904 | tNET | RR | 1 | R54C96[0][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
1.276 | 1.276 | tNET | RR | 1 | R54C96[0][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLK |
1.087 | -0.189 | tHld | 1 | R54C96[0][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1 |
Path Statistics:
Clock Skew | -0.313 |
Hold Relationship | -3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.589, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.904, 82.066%; tC2Q: 0.198, 17.934% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.276, 100.000% |
Path21
Path Summary:
Slack | 5.187 |
Data Arrival Time | 6.279 |
Data Required Time | 1.092 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
5.160 | 1.589 | tNET | FF | 1 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
5.358 | 0.198 | tC2Q | FR | 61 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.279 | 0.921 | tNET | RR | 1 | R54C99[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
1.281 | 1.281 | tNET | RR | 1 | R54C99[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLK |
1.092 | -0.189 | tHld | 1 | R54C99[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1 |
Path Statistics:
Clock Skew | -0.308 |
Hold Relationship | -3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.589, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.921, 82.346%; tC2Q: 0.198, 17.654% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.281, 100.000% |
Path22
Path Summary:
Slack | 5.188 |
Data Arrival Time | 6.284 |
Data Required Time | 1.096 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
5.160 | 1.589 | tNET | FF | 1 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
5.358 | 0.198 | tC2Q | FR | 61 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.284 | 0.926 | tNET | RR | 1 | R53C98[0][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
1.284 | 1.284 | tNET | RR | 1 | R53C98[0][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLK |
1.096 | -0.189 | tHld | 1 | R53C98[0][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1 |
Path Statistics:
Clock Skew | -0.304 |
Hold Relationship | -3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.589, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.926, 82.425%; tC2Q: 0.198, 17.575% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.284, 100.000% |
Path23
Path Summary:
Slack | 5.188 |
Data Arrival Time | 6.284 |
Data Required Time | 1.096 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
5.160 | 1.589 | tNET | FF | 1 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
5.358 | 0.198 | tC2Q | FR | 61 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.284 | 0.926 | tNET | RR | 1 | R53C98[0][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
1.284 | 1.284 | tNET | RR | 1 | R53C98[0][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLK |
1.096 | -0.189 | tHld | 1 | R53C98[0][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1 |
Path Statistics:
Clock Skew | -0.304 |
Hold Relationship | -3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.589, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.926, 82.425%; tC2Q: 0.198, 17.575% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.284, 100.000% |
Path24
Path Summary:
Slack | 5.188 |
Data Arrival Time | 6.284 |
Data Required Time | 1.096 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/start_reg_s0 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
5.160 | 1.589 | tNET | FF | 1 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
5.358 | 0.198 | tC2Q | FR | 61 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.284 | 0.926 | tNET | RR | 1 | R53C98[2][A] | gw_gao_inst_0/u_la0_top/start_reg_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
1.284 | 1.284 | tNET | RR | 1 | R53C98[2][A] | gw_gao_inst_0/u_la0_top/start_reg_s0/CLK |
1.096 | -0.189 | tHld | 1 | R53C98[2][A] | gw_gao_inst_0/u_la0_top/start_reg_s0 |
Path Statistics:
Clock Skew | -0.304 |
Hold Relationship | -3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.589, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.926, 82.425%; tC2Q: 0.198, 17.575% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.284, 100.000% |
Path25
Path Summary:
Slack | 5.188 |
Data Arrival Time | 6.284 |
Data Required Time | 1.096 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
5.160 | 1.589 | tNET | FF | 1 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
5.358 | 0.198 | tC2Q | FR | 61 | R58C101[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.284 | 0.926 | tNET | RR | 1 | R53C98[1][A] | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 293 | PLL_L[0] | u_pll_1/PLL_inst/CLKOUT1 |
1.284 | 1.284 | tNET | RR | 1 | R53C98[1][A] | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLK |
1.096 | -0.189 | tHld | 1 | R53C98[1][A] | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0 |
Path Statistics:
Clock Skew | -0.304 |
Hold Relationship | -3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.589, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.926, 82.425%; tC2Q: 0.198, 17.575% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.284, 100.000% |
Minimum Pulse Width Report:
Report Command:report_min_pulse_width -nworst 10 -detail
MPW1
MPW Summary:
Slack: | 1.189 |
Actual Width: | 2.189 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | byte_clk |
Objects: | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_1_s |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
4.762 | 0.000 | active clock edge time | ||
4.762 | 0.000 | byte_clk | ||
4.762 | 0.000 | tCL | FF | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
10.524 | 5.762 | tNET | FF | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_1_s/CLKA |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
9.524 | 0.000 | active clock edge time | ||
9.524 | 0.000 | byte_clk | ||
9.524 | 0.000 | tCL | RR | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
12.713 | 3.189 | tNET | RR | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_1_s/CLKA |
MPW2
MPW Summary:
Slack: | 1.193 |
Actual Width: | 2.193 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | byte_clk |
Objects: | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
4.762 | 0.000 | active clock edge time | ||
4.762 | 0.000 | byte_clk | ||
4.762 | 0.000 | tCL | FF | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
10.515 | 5.753 | tNET | FF | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s/CLKA |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
9.524 | 0.000 | active clock edge time | ||
9.524 | 0.000 | byte_clk | ||
9.524 | 0.000 | tCL | RR | u_dphy_rx/mipi_dphy_rx_inst/RX_CLK_O |
12.708 | 3.184 | tNET | RR | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s/CLKA |
MPW3
MPW Summary:
Slack: | 1.197 |
Actual Width: | 2.197 |
Required Width: | 1.000 |
Type: | High Pulse Width |
Clock: | pixel_clk |
Objects: | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_1_s |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||
0.000 | 0.000 | pixel_clk | ||
0.000 | 0.000 | tCL | RR | u_pll_1/PLL_inst/CLKOUT1 |
2.945 | 2.945 | tNET | RR | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_1_s/CLKB |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
3.572 | 0.000 | active clock edge time | ||
3.572 | 0.000 | pixel_clk | ||
3.572 | 0.000 | tCL | FF | u_pll_1/PLL_inst/CLKOUT1 |
5.141 | 1.570 | tNET | FF | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_1_s/CLKB |
MPW4
MPW Summary:
Slack: | 1.201 |
Actual Width: | 2.201 |
Required Width: | 1.000 |
Type: | High Pulse Width |
Clock: | pixel_clk |
Objects: | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||
0.000 | 0.000 | pixel_clk | ||
0.000 | 0.000 | tCL | RR | u_pll_1/PLL_inst/CLKOUT1 |
2.935 | 2.935 | tNET | RR | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s/CLKB |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
3.572 | 0.000 | active clock edge time | ||
3.572 | 0.000 | pixel_clk | ||
3.572 | 0.000 | tCL | FF | u_pll_1/PLL_inst/CLKOUT1 |
5.136 | 1.565 | tNET | FF | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s/CLKB |
MPW5
MPW Summary:
Slack: | 1.244 |
Actual Width: | 2.244 |
Required Width: | 1.000 |
Type: | High Pulse Width |
Clock: | pixel_clk |
Objects: | u_extr/mem_data_mem_data_0_5_s |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||
0.000 | 0.000 | pixel_clk | ||
0.000 | 0.000 | tCL | RR | u_pll_1/PLL_inst/CLKOUT1 |
2.896 | 2.896 | tNET | RR | u_extr/mem_data_mem_data_0_5_s/CLKA |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
3.572 | 0.000 | active clock edge time | ||
3.572 | 0.000 | pixel_clk | ||
3.572 | 0.000 | tCL | FF | u_pll_1/PLL_inst/CLKOUT1 |
5.140 | 1.568 | tNET | FF | u_extr/mem_data_mem_data_0_5_s/CLKA |
MPW6
MPW Summary:
Slack: | 1.244 |
Actual Width: | 2.244 |
Required Width: | 1.000 |
Type: | High Pulse Width |
Clock: | pixel_clk |
Objects: | u_extr/mem_data_mem_data_0_6_s |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||
0.000 | 0.000 | pixel_clk | ||
0.000 | 0.000 | tCL | RR | u_pll_1/PLL_inst/CLKOUT1 |
2.896 | 2.896 | tNET | RR | u_extr/mem_data_mem_data_0_6_s/CLKA |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
3.572 | 0.000 | active clock edge time | ||
3.572 | 0.000 | pixel_clk | ||
3.572 | 0.000 | tCL | FF | u_pll_1/PLL_inst/CLKOUT1 |
5.140 | 1.568 | tNET | FF | u_extr/mem_data_mem_data_0_6_s/CLKA |
MPW7
MPW Summary:
Slack: | 1.248 |
Actual Width: | 2.248 |
Required Width: | 1.000 |
Type: | High Pulse Width |
Clock: | pixel_clk |
Objects: | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||
0.000 | 0.000 | pixel_clk | ||
0.000 | 0.000 | tCL | RR | u_pll_1/PLL_inst/CLKOUT1 |
2.887 | 2.887 | tNET | RR | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
3.572 | 0.000 | active clock edge time | ||
3.572 | 0.000 | pixel_clk | ||
3.572 | 0.000 | tCL | FF | u_pll_1/PLL_inst/CLKOUT1 |
5.135 | 1.563 | tNET | FF | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA |
MPW8
MPW Summary:
Slack: | 1.248 |
Actual Width: | 2.248 |
Required Width: | 1.000 |
Type: | High Pulse Width |
Clock: | pixel_clk |
Objects: | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||
0.000 | 0.000 | pixel_clk | ||
0.000 | 0.000 | tCL | RR | u_pll_1/PLL_inst/CLKOUT1 |
2.887 | 2.887 | tNET | RR | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
3.572 | 0.000 | active clock edge time | ||
3.572 | 0.000 | pixel_clk | ||
3.572 | 0.000 | tCL | FF | u_pll_1/PLL_inst/CLKOUT1 |
5.135 | 1.563 | tNET | FF | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA |
MPW9
MPW Summary:
Slack: | 1.248 |
Actual Width: | 2.248 |
Required Width: | 1.000 |
Type: | High Pulse Width |
Clock: | pixel_clk |
Objects: | u_extr/mem_data_mem_data_0_0_s |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||
0.000 | 0.000 | pixel_clk | ||
0.000 | 0.000 | tCL | RR | u_pll_1/PLL_inst/CLKOUT1 |
2.887 | 2.887 | tNET | RR | u_extr/mem_data_mem_data_0_0_s/CLKA |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
3.572 | 0.000 | active clock edge time | ||
3.572 | 0.000 | pixel_clk | ||
3.572 | 0.000 | tCL | FF | u_pll_1/PLL_inst/CLKOUT1 |
5.135 | 1.563 | tNET | FF | u_extr/mem_data_mem_data_0_0_s/CLKA |
MPW10
MPW Summary:
Slack: | 1.248 |
Actual Width: | 2.248 |
Required Width: | 1.000 |
Type: | High Pulse Width |
Clock: | pixel_clk |
Objects: | u_extr/mem_data_mem_data_0_7_s |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||
0.000 | 0.000 | pixel_clk | ||
0.000 | 0.000 | tCL | RR | u_pll_1/PLL_inst/CLKOUT1 |
2.887 | 2.887 | tNET | RR | u_extr/mem_data_mem_data_0_7_s/CLKA |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
3.572 | 0.000 | active clock edge time | ||
3.572 | 0.000 | pixel_clk | ||
3.572 | 0.000 | tCL | FF | u_pll_1/PLL_inst/CLKOUT1 |
5.135 | 1.563 | tNET | FF | u_extr/mem_data_mem_data_0_7_s/CLKA |
High Fanout Nets Report:
Report Command:report_high_fanout_nets -max_nets 10
FANOUT | NET NAME | WORST SLACK | MAX DELAY |
---|---|---|---|
578 | byte_clk | 0.201 | 6.229 |
293 | pixel_clk | 1.025 | 2.988 |
240 | control0[0] | 42.054 | 8.050 |
165 | lvds_pclk | 0.391 | 2.705 |
97 | mid_offset[0] | 6.278 | 2.200 |
96 | n1393_9 | 6.082 | 1.801 |
80 | shift_en | 5.525 | 2.548 |
61 | rst_ao | 0.349 | 2.792 |
57 | buf_rd | 0.891 | 2.860 |
51 | mid_dv | 5.853 | 1.901 |
Route Congestions Report:
Report Command:report_route_congestion -max_grids 10
GRID LOC | ROUTE CONGESTIONS |
---|---|
R54C104 | 65.28% |
R54C96 | 63.89% |
R52C60 | 62.50% |
R56C89 | 62.50% |
R54C108 | 61.11% |
R54C66 | 59.72% |
R54C111 | 59.72% |
R54C103 | 58.33% |
R52C59 | 58.33% |
R52C52 | 58.33% |
Timing Exceptions Report:
Setup Analysis Report
Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Hold Analysis Report
Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Recovery Analysis Report
Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Removal Analysis Report
Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Timing Constraints Report:
SDC Command Type | State | Detail Command |
---|---|---|
TC_CLOCK | Actived | create_clock -name clk_50 -period 20 -waveform {0 10} [get_ports {OSC_50M}] |
TC_CLOCK | Actived | create_clock -name byte_clk -period 9.524 -waveform {0 4.762} [get_nets {byte_clk}] |
TC_GENERATED_CLOCK | Actived | create_generated_clock -name pixel_clk -source [get_nets {byte_clk}] -master_clock byte_clk -divide_by 3 -multiply_by 4 [get_nets {pixel_clk}] |
TC_GENERATED_CLOCK | Actived | create_generated_clock -name lvds_pclk -source [get_ports {OSC_50M}] -master_clock clk_50 -divide_by 7 -multiply_by 19 [get_nets {lvds_pclk}] |
TC_CLOCK_GROUP | Actived | set_clock_groups -exclusive -group [get_clocks {pixel_clk}] -group [get_clocks {byte_clk}] |
TC_CLOCK_GROUP | Actived | set_clock_groups -exclusive -group [get_clocks {pixel_clk}] -group [get_clocks {lvds_pclk}] |
TC_CLOCK_GROUP | Actived | set_clock_groups -exclusive -group [get_clocks {byte_clk}] -group [get_clocks {lvds_pclk}] |
TC_REPORT_TIMING | Actived | report_timing -setup -from_clock [get_clocks {pixel_clk}] -max_paths 20 -max_common_paths 1 |
TC_REPORT_TIMING | Actived | report_timing -setup -from_clock [get_clocks {byte_clk}] -max_paths 20 -max_common_paths 1 |
TC_REPORT_TIMING | Actived | report_timing -setup -from_clock [get_clocks {lvds_pclk}] -max_paths 20 -max_common_paths 1 |
TC_REPORT_TIMING | Actived | report_timing -hold -from_clock [get_clocks {pixel_clk}] -max_paths 20 -max_common_paths 1 |
TC_REPORT_TIMING | Actived | report_timing -hold -from_clock [get_clocks {byte_clk}] -max_paths 20 -max_common_paths 1 |
TC_REPORT_TIMING | Actived | report_timing -hold -from_clock [get_clocks {lvds_pclk}] -max_paths 20 -max_common_paths 1 |