Timing Messages
Report Title | Timing Analysis Report |
Design File | F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\DSI_to_LVDS_5a25\fpga_proj\impl\gwsynthesis\DSI_to_LVDS_5a25.vg |
Physical Constraints File | F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\DSI_to_LVDS_5a25\fpga_proj\src\dk_ug324_v1p1.cst |
Timing Constraint File | F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\DSI_to_LVDS_5a25\fpga_proj\src\dsi_to_lvds_osc.sdc |
Tool Version | V1.9.9.01 (64-bit) |
Part Number | GW5A-LV25UG324ES |
Device | GW5A-25 |
Device Version | A |
Created Time | Wed Mar 6 18:50:11 2024 |
Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved. |
Timing Summaries
STA Tool Run Summary:
Setup Delay Model | Slow 0.855V 0C ES |
Hold Delay Model | Fast 0.945V 85C ES |
Numbers of Paths Analyzed | 4883 |
Numbers of Endpoints Analyzed | 4571 |
Numbers of Falling Endpoints | 3 |
Numbers of Setup Violated Endpoints | 0 |
Numbers of Hold Violated Endpoints | 0 |
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Objects |
---|---|---|---|---|---|---|---|---|
clk_50 | Base | 20.000 | 50.000 | 0.000 | 10.000 | OSC_50M | ||
byte_clk | Base | 9.524 | 104.998 | 0.000 | 4.762 | byte_clk | ||
pixel_clk | Generated | 7.143 | 139.997 | 0.000 | 3.572 | byte_clk | byte_clk | pixel_clk |
lvds_pclk | Generated | 7.368 | 135.714 | 0.000 | 3.684 | OSC_50M | clk_50 | lvds_pclk |
tck_pad_i | Base | 50.000 | 20.000 | 0.000 | 25.000 | gw_gao_inst_0/tck_ibuf/I | ||
u_pll_50m/PLLA_inst/CLKOUT0.default_gen_clk | Generated | 2.105 | 475.000 | 0.000 | 1.053 | OSC_50M_ibuf/I | clk_50 | u_pll_50m/PLLA_inst/CLKOUT0 |
Max Frequency Summary:
NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | byte_clk | 104.998(MHz) | 135.893(MHz) | 6 | TOP |
2 | pixel_clk | 139.997(MHz) | 200.150(MHz) | 6 | TOP |
3 | lvds_pclk | 135.714(MHz) | 162.231(MHz) | 6 | TOP |
4 | tck_pad_i | 20.000(MHz) | 129.100(MHz) | 6 | TOP |
No timing paths to get frequency of clk_50!
No timing paths to get frequency of u_pll_50m/PLLA_inst/CLKOUT0.default_gen_clk!
Total Negative Slack Summary:
Clock Name | Analysis Type | Endpoints TNS | Number of Endpoints |
---|---|---|---|
clk_50 | Setup | 0.000 | 0 |
clk_50 | Hold | 0.000 | 0 |
byte_clk | Setup | 0.000 | 0 |
byte_clk | Hold | 0.000 | 0 |
pixel_clk | Setup | 0.000 | 0 |
pixel_clk | Hold | 0.000 | 0 |
lvds_pclk | Setup | 0.000 | 0 |
lvds_pclk | Hold | 0.000 | 0 |
tck_pad_i | Setup | 0.000 | 0 |
tck_pad_i | Hold | 0.000 | 0 |
u_pll_50m/PLLA_inst/CLKOUT0.default_gen_clk | Setup | 0.000 | 0 |
u_pll_50m/PLLA_inst/CLKOUT0.default_gen_clk | Hold | 0.000 | 0 |
Timing Details
Path Slacks Table:
Setup Paths Table
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 1.204 | u_extr/buf_ra_0_s0/Q | u_extr/mem_data_mem_data_0_0_s/ADB[9] | lvds_pclk:[R] | lvds_pclk:[R] | 7.368 | -0.012 | 6.141 |
2 | 1.258 | u_extr/buf_ra_0_s0/Q | u_extr/mem_data_mem_data_0_11_s/ADB[11] | lvds_pclk:[R] | lvds_pclk:[R] | 7.368 | -0.012 | 6.088 |
3 | 1.266 | u_extr/buf_rd_s0/Q | u_extr/mem_data_mem_data_0_6_s/ADB[13] | lvds_pclk:[R] | lvds_pclk:[R] | 7.368 | 0.014 | 6.054 |
4 | 1.279 | u_extr/buf_ra_0_s0/Q | u_extr/mem_data_mem_data_0_6_s/ADB[11] | lvds_pclk:[R] | lvds_pclk:[R] | 7.368 | -0.012 | 6.066 |
5 | 1.293 | u_extr/buf_ra_0_s0/Q | u_extr/mem_data_mem_data_0_8_s/ADB[9] | lvds_pclk:[R] | lvds_pclk:[R] | 7.368 | -0.021 | 6.062 |
6 | 1.350 | u_extr/buf_ra_0_s0/Q | u_extr/mem_data_mem_data_0_7_s/ADB[10] | lvds_pclk:[R] | lvds_pclk:[R] | 7.368 | -0.021 | 6.005 |
7 | 1.364 | u_extr/buf_ra_0_s0/Q | u_extr/mem_data_mem_data_0_10_s/ADB[11] | lvds_pclk:[R] | lvds_pclk:[R] | 7.368 | -0.002 | 5.972 |
8 | 1.374 | u_extr/buf_ra_0_s0/Q | u_extr/mem_data_mem_data_0_6_s/ADB[10] | lvds_pclk:[R] | lvds_pclk:[R] | 7.368 | -0.012 | 5.971 |
9 | 1.388 | u_extr/buf_ra_0_s0/Q | u_extr/mem_data_mem_data_0_6_s/ADB[7] | lvds_pclk:[R] | lvds_pclk:[R] | 7.368 | -0.012 | 5.957 |
10 | 1.393 | u_extr/buf_ra_0_s0/Q | u_extr/mem_data_mem_data_0_4_s/ADB[9] | lvds_pclk:[R] | lvds_pclk:[R] | 7.368 | -0.002 | 5.944 |
11 | 1.398 | u_extr/buf_ra_0_s0/Q | u_extr/mem_data_mem_data_0_8_s/ADB[10] | lvds_pclk:[R] | lvds_pclk:[R] | 7.368 | -0.021 | 5.957 |
12 | 1.402 | u_extr/buf_ra_0_s0/Q | u_extr/mem_data_mem_data_0_6_s/ADB[9] | lvds_pclk:[R] | lvds_pclk:[R] | 7.368 | -0.012 | 5.944 |
13 | 1.408 | u_extr/buf_rd_s0/Q | u_extr/mem_data_mem_data_0_0_s/ADB[12] | lvds_pclk:[R] | lvds_pclk:[R] | 7.368 | 0.014 | 5.911 |
14 | 1.413 | u_extr/buf_ra_0_s0/Q | u_extr/mem_data_mem_data_0_8_s/ADB[7] | lvds_pclk:[R] | lvds_pclk:[R] | 7.368 | -0.021 | 5.942 |
15 | 1.414 | u_extr/buf_ra_0_s0/Q | u_extr/mem_data_mem_data_0_5_s/ADB[7] | lvds_pclk:[R] | lvds_pclk:[R] | 7.368 | -0.012 | 5.931 |
16 | 1.446 | u_extr/buf_ra_0_s0/Q | u_extr/mem_data_mem_data_0_1_s/ADB[11] | lvds_pclk:[R] | lvds_pclk:[R] | 7.368 | -0.021 | 5.909 |
17 | 1.482 | u_extr/buf_ra_0_s0/Q | u_extr/mem_data_mem_data_0_0_s/ADB[11] | lvds_pclk:[R] | lvds_pclk:[R] | 7.368 | -0.012 | 5.864 |
18 | 1.499 | u_extr/buf_ra_0_s0/Q | u_extr/mem_data_mem_data_0_4_s/ADB[10] | lvds_pclk:[R] | lvds_pclk:[R] | 7.368 | -0.002 | 5.838 |
19 | 1.522 | u_extr/buf_ra_0_s0/Q | u_extr/mem_data_mem_data_0_5_s/ADB[9] | lvds_pclk:[R] | lvds_pclk:[R] | 7.368 | -0.012 | 5.824 |
20 | 1.560 | u_extr/oworking_s0/Q | u_extr/mem_data_mem_data_0_3_s/ADB[3] | lvds_pclk:[R] | lvds_pclk:[R] | 7.368 | 0.026 | 5.748 |
21 | 1.592 | u_extr/buf_ra_0_s0/Q | u_extr/mem_data_mem_data_0_2_s/ADB[11] | lvds_pclk:[R] | lvds_pclk:[R] | 7.368 | -0.012 | 5.754 |
22 | 1.604 | u_extr/buf_ra_0_s0/Q | u_extr/mem_data_mem_data_0_4_s/ADB[11] | lvds_pclk:[R] | lvds_pclk:[R] | 7.368 | -0.002 | 5.732 |
23 | 1.604 | u_extr/buf_ra_0_s0/Q | u_extr/mem_data_mem_data_0_3_s/ADB[10] | lvds_pclk:[R] | lvds_pclk:[R] | 7.368 | -0.002 | 5.732 |
24 | 1.638 | u_extr/buf_rd_s0/Q | u_extr/mem_data_mem_data_0_11_s/ADB[13] | lvds_pclk:[R] | lvds_pclk:[R] | 7.368 | 0.014 | 5.681 |
25 | 1.648 | u_extr/buf_ra_0_s0/Q | u_extr/mem_data_mem_data_0_8_s/ADB[11] | lvds_pclk:[R] | lvds_pclk:[R] | 7.368 | -0.021 | 5.707 |
Hold Paths Table
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 0.175 | u_b2p/u_b2p_inst/rBufD_40_s1/Q | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_1_s/DI[8] | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.008 | 0.416 |
2 | 0.175 | u_b2p/u_b2p_inst/rBufD_32_s1/Q | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_1_s/DI[0] | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.008 | 0.416 |
3 | 0.176 | u_b2p/u_b2p_inst/rBufD_5_s1/Q | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s/DI[5] | byte_clk:[R] | byte_clk:[R] | 0.000 | -0.004 | 0.429 |
4 | 0.190 | u_b2p/u_b2p_inst/rBufD_0_s1/Q | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s/DI[0] | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.002 | 0.436 |
5 | 0.198 | gw_gao_inst_0/u_la0_top/address_counter_1_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/ADB[4] | tck_pad_i:[R] | tck_pad_i:[R] | 0.000 | 0.006 | 0.310 |
6 | 0.204 | u_extr/o_hs_reg_s0/Q | u_lvds_tx_left/LVDS_71_Tx/u_ODDR71_B2/D2 | lvds_pclk:[R] | lvds_pclk:[R] | 0.000 | 0.003 | 0.296 |
7 | 0.207 | u_lvds_tx_left/LVDS_71_Tx/scuba_vhi_s0/Q | u_lvds_tx_left/LVDS_71_Tx/u_ODDR71_C/D6 | lvds_pclk:[R] | lvds_pclk:[R] | 0.000 | -0.002 | 0.304 |
8 | 0.209 | u_lvds_tx_left/LVDS_71_Tx/scuba_vhi_s0/Q | u_lvds_tx_left/LVDS_71_Tx/u_ODDR71_C/D0 | lvds_pclk:[R] | lvds_pclk:[R] | 0.000 | -0.002 | 0.306 |
9 | 0.212 | u_extr/o_rgb_reg_4_s0/Q | u_lvds_tx_left/LVDS_71_Tx/u_ODDR71_B0/D4 | lvds_pclk:[R] | lvds_pclk:[R] | 0.000 | 0.003 | 0.304 |
10 | 0.216 | u_extr/o_rgb_reg_3_s0/Q | u_lvds_tx_left/LVDS_71_Tx/u_ODDR71_B0/D5 | lvds_pclk:[R] | lvds_pclk:[R] | 0.000 | 0.003 | 0.296 |
11 | 0.216 | u_extr/o_rgb_reg_18_s0/Q | u_lvds_tx_left/LVDS_71_Tx/u_ODDR71_B1/D1 | lvds_pclk:[R] | lvds_pclk:[R] | 0.000 | 0.003 | 0.296 |
12 | 0.219 | u_lvds_tx_left/LVDS_71_Tx/scuba_vhi_s0/Q | u_lvds_tx_left/LVDS_71_Tx/u_ODDR71_C/D1 | lvds_pclk:[R] | lvds_pclk:[R] | 0.000 | -0.002 | 0.304 |
13 | 0.221 | u_lvds_tx_left/LVDS_71_Tx/scuba_vhi_s0/Q | u_lvds_tx_left/LVDS_71_Tx/u_ODDR71_C/D5 | lvds_pclk:[R] | lvds_pclk:[R] | 0.000 | -0.002 | 0.306 |
14 | 0.231 | u_b2p/u_b2p_inst/rBufD_6_s1/Q | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s/DI[6] | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.001 | 0.479 |
15 | 0.238 | u_b2p/u_b2p_inst/rBufD_21_s1/Q | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s/DI[21] | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.001 | 0.486 |
16 | 0.251 | u_b2p/u_b2p_inst/rBufD_24_s1/Q | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s/DI[24] | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.002 | 0.498 |
17 | 0.263 | u_extr/buf_wd_18_s0/Q | u_extr/mem_data_mem_data_0_9_s/DI[0] | pixel_clk:[R] | pixel_clk:[R] | 0.000 | -0.006 | 0.519 |
18 | 0.264 | u_extr/buf_wd_14_s0/Q | u_extr/mem_data_mem_data_0_7_s/DI[0] | pixel_clk:[R] | pixel_clk:[R] | 0.000 | -0.006 | 0.519 |
19 | 0.264 | u_extr/buf_wd_10_s0/Q | u_extr/mem_data_mem_data_0_5_s/DI[0] | pixel_clk:[R] | pixel_clk:[R] | 0.000 | -0.006 | 0.519 |
20 | 0.265 | u_extr/buf_wd_19_s0/Q | u_extr/mem_data_mem_data_0_9_s/DI[1] | pixel_clk:[R] | pixel_clk:[R] | 0.000 | -0.006 | 0.520 |
21 | 0.265 | u_extr/buf_wd_15_s0/Q | u_extr/mem_data_mem_data_0_7_s/DI[1] | pixel_clk:[R] | pixel_clk:[R] | 0.000 | -0.006 | 0.520 |
22 | 0.265 | u_extr/buf_wd_11_s0/Q | u_extr/mem_data_mem_data_0_5_s/DI[1] | pixel_clk:[R] | pixel_clk:[R] | 0.000 | -0.006 | 0.520 |
23 | 0.266 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_15_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[7] | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.030 | 0.485 |
24 | 0.294 | u_b2p/u_b2p_inst/rBufD_45_s1/Q | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_1_s/DI[13] | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.006 | 0.536 |
25 | 0.295 | u_b2p/u_b2p_inst/rBufD_31_s1/Q | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s/DI[31] | byte_clk:[R] | byte_clk:[R] | 0.000 | -0.004 | 0.548 |
Recovery Paths Table
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 1.148 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR | pixel_clk:[F] | pixel_clk:[R] | 3.572 | -0.039 | 2.115 |
2 | 1.518 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR | pixel_clk:[F] | pixel_clk:[R] | 3.572 | -0.041 | 1.747 |
3 | 1.518 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR | pixel_clk:[F] | pixel_clk:[R] | 3.572 | -0.041 | 1.747 |
4 | 1.518 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR | pixel_clk:[F] | pixel_clk:[R] | 3.572 | -0.041 | 1.747 |
5 | 1.518 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR | pixel_clk:[F] | pixel_clk:[R] | 3.572 | -0.041 | 1.747 |
6 | 1.527 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/CLEAR | pixel_clk:[F] | pixel_clk:[R] | 3.572 | -0.051 | 1.747 |
7 | 1.527 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR | pixel_clk:[F] | pixel_clk:[R] | 3.572 | -0.051 | 1.747 |
8 | 1.527 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR | pixel_clk:[F] | pixel_clk:[R] | 3.572 | -0.051 | 1.747 |
9 | 1.560 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR | pixel_clk:[F] | pixel_clk:[R] | 3.572 | -0.029 | 1.694 |
10 | 1.560 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLEAR | pixel_clk:[F] | pixel_clk:[R] | 3.572 | -0.029 | 1.694 |
11 | 1.696 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR | pixel_clk:[F] | pixel_clk:[R] | 3.572 | -0.019 | 1.548 |
12 | 1.698 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR | pixel_clk:[F] | pixel_clk:[R] | 3.572 | -0.022 | 1.548 |
13 | 1.698 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_0_s0/CLEAR | pixel_clk:[F] | pixel_clk:[R] | 3.572 | -0.022 | 1.548 |
14 | 1.707 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_match_1/trig_dly_0_s0/CLEAR | pixel_clk:[F] | pixel_clk:[R] | 3.572 | -0.031 | 1.548 |
15 | 1.734 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET | pixel_clk:[F] | pixel_clk:[R] | 3.572 | -0.039 | 1.529 |
16 | 1.737 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR | pixel_clk:[F] | pixel_clk:[R] | 3.572 | -0.041 | 1.529 |
17 | 1.737 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR | pixel_clk:[F] | pixel_clk:[R] | 3.572 | -0.041 | 1.529 |
18 | 1.737 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR | pixel_clk:[F] | pixel_clk:[R] | 3.572 | -0.041 | 1.529 |
19 | 1.737 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR | pixel_clk:[F] | pixel_clk:[R] | 3.572 | -0.041 | 1.529 |
20 | 1.743 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR | pixel_clk:[F] | pixel_clk:[R] | 3.572 | -0.032 | 1.513 |
21 | 1.743 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR | pixel_clk:[F] | pixel_clk:[R] | 3.572 | -0.032 | 1.513 |
22 | 1.743 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR | pixel_clk:[F] | pixel_clk:[R] | 3.572 | -0.032 | 1.513 |
23 | 1.743 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/CLEAR | pixel_clk:[F] | pixel_clk:[R] | 3.572 | -0.032 | 1.513 |
24 | 1.746 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLEAR | pixel_clk:[F] | pixel_clk:[R] | 3.572 | -0.032 | 1.510 |
25 | 1.746 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLEAR | pixel_clk:[F] | pixel_clk:[R] | 3.572 | -0.032 | 1.510 |
Removal Paths Table
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 4.227 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR | pixel_clk:[F] | pixel_clk:[R] | -3.572 | -0.002 | 0.469 |
2 | 4.227 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR | pixel_clk:[F] | pixel_clk:[R] | -3.572 | -0.002 | 0.469 |
3 | 4.227 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_10_s1/CLEAR | pixel_clk:[F] | pixel_clk:[R] | -3.572 | -0.002 | 0.469 |
4 | 4.227 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET | pixel_clk:[F] | pixel_clk:[R] | -3.572 | -0.002 | 0.469 |
5 | 4.227 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLEAR | pixel_clk:[F] | pixel_clk:[R] | -3.572 | 0.003 | 0.464 |
6 | 4.227 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR | pixel_clk:[F] | pixel_clk:[R] | -3.572 | 0.003 | 0.464 |
7 | 4.227 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLEAR | pixel_clk:[F] | pixel_clk:[R] | -3.572 | 0.003 | 0.464 |
8 | 4.227 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLEAR | pixel_clk:[F] | pixel_clk:[R] | -3.572 | 0.003 | 0.464 |
9 | 4.232 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR | pixel_clk:[F] | pixel_clk:[R] | -3.572 | 0.003 | 0.469 |
10 | 4.232 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR | pixel_clk:[F] | pixel_clk:[R] | -3.572 | 0.003 | 0.469 |
11 | 4.232 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR | pixel_clk:[F] | pixel_clk:[R] | -3.572 | 0.003 | 0.469 |
12 | 4.510 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_match_1/match_sep_s0/CLEAR | pixel_clk:[F] | pixel_clk:[R] | -3.572 | -0.019 | 0.769 |
13 | 4.510 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_0_s0/CLEAR | pixel_clk:[F] | pixel_clk:[R] | -3.572 | -0.019 | 0.769 |
14 | 4.510 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR | pixel_clk:[F] | pixel_clk:[R] | -3.572 | -0.019 | 0.769 |
15 | 4.510 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR | pixel_clk:[F] | pixel_clk:[R] | -3.572 | -0.019 | 0.769 |
16 | 4.515 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s1/CLEAR | pixel_clk:[F] | pixel_clk:[R] | -3.572 | -0.014 | 0.769 |
17 | 4.515 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR | pixel_clk:[F] | pixel_clk:[R] | -3.572 | -0.014 | 0.769 |
18 | 4.515 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLEAR | pixel_clk:[F] | pixel_clk:[R] | -3.572 | -0.014 | 0.769 |
19 | 4.515 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR | pixel_clk:[F] | pixel_clk:[R] | -3.572 | -0.014 | 0.769 |
20 | 4.519 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_match_1/trig_dly_in_0_s0/CLEAR | pixel_clk:[F] | pixel_clk:[R] | -3.572 | -0.025 | 0.784 |
21 | 4.519 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR | pixel_clk:[F] | pixel_clk:[R] | -3.572 | -0.025 | 0.784 |
22 | 4.539 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLEAR | pixel_clk:[F] | pixel_clk:[R] | -3.572 | -0.025 | 0.804 |
23 | 4.542 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLEAR | pixel_clk:[F] | pixel_clk:[R] | -3.572 | -0.023 | 0.804 |
24 | 4.633 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_match_1/trig_dly_0_s0/CLEAR | pixel_clk:[F] | pixel_clk:[R] | -3.572 | -0.016 | 0.889 |
25 | 4.640 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR | pixel_clk:[F] | pixel_clk:[R] | -3.572 | -0.009 | 0.889 |
Minimum Pulse Width Table:
Number | Slack | Actual Width | Required Width | Type | Clock | Objects |
---|---|---|---|---|---|---|
1 | 1.863 | 2.863 | 1.000 | Low Pulse Width | lvds_pclk | u_extr/mem_data_mem_data_0_1_s |
2 | 1.863 | 2.863 | 1.000 | Low Pulse Width | lvds_pclk | u_extr/mem_data_mem_data_0_7_s |
3 | 1.863 | 2.863 | 1.000 | Low Pulse Width | lvds_pclk | u_extr/mem_data_mem_data_0_8_s |
4 | 1.865 | 2.865 | 1.000 | High Pulse Width | lvds_pclk | u_extr/mem_data_mem_data_0_1_s |
5 | 1.865 | 2.865 | 1.000 | High Pulse Width | lvds_pclk | u_extr/mem_data_mem_data_0_7_s |
6 | 1.865 | 2.865 | 1.000 | High Pulse Width | lvds_pclk | u_extr/mem_data_mem_data_0_8_s |
7 | 1.868 | 2.868 | 1.000 | Low Pulse Width | lvds_pclk | u_extr/mem_data_mem_data_0_9_s |
8 | 1.868 | 2.868 | 1.000 | Low Pulse Width | lvds_pclk | u_extr/mem_data_mem_data_0_11_s |
9 | 1.868 | 2.868 | 1.000 | Low Pulse Width | lvds_pclk | u_extr/mem_data_mem_data_0_0_s |
10 | 1.868 | 2.868 | 1.000 | Low Pulse Width | lvds_pclk | u_extr/mem_data_mem_data_0_2_s |
Timing Report By Analysis Type:
Setup Analysis Report
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 1.204 |
Data Arrival Time | 7.513 |
Data Required Time | 8.718 |
From | u_extr/buf_ra_0_s0 |
To | u_extr/mem_data_mem_data_0_0_s |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_B | u_pll_50m/PLLA_inst/CLKOUT1 |
1.372 | 1.372 | tNET | RR | 1 | R14C20[0][B] | u_extr/buf_ra_0_s0/CLK |
1.740 | 0.368 | tC2Q | RF | 8 | R14C20[0][B] | u_extr/buf_ra_0_s0/Q |
2.233 | 0.494 | tNET | FF | 1 | R13C24[3][B] | u_extr/n882_s4/I0 |
2.731 | 0.498 | tINS | FR | 5 | R13C24[3][B] | u_extr/n882_s4/F |
3.086 | 0.355 | tNET | RR | 1 | R14C23[3][B] | u_extr/n879_s4/I3 |
3.583 | 0.498 | tINS | RR | 5 | R14C23[3][B] | u_extr/n879_s4/F |
3.783 | 0.200 | tNET | RR | 1 | R14C21[2][A] | u_extr/n878_s5/I2 |
4.310 | 0.526 | tINS | RR | 2 | R14C21[2][A] | u_extr/n878_s5/F |
4.470 | 0.160 | tNET | RR | 1 | R14C22[2][B] | u_extr/buf_ra_8_s11/I1 |
4.732 | 0.262 | tINS | RR | 2 | R14C22[2][B] | u_extr/buf_ra_8_s11/F |
4.737 | 0.005 | tNET | RR | 1 | R14C22[3][A] | u_extr/buf_ra_c_8_s1/I0 |
5.235 | 0.498 | tINS | RR | 12 | R14C22[3][A] | u_extr/buf_ra_c_8_s1/F |
7.513 | 2.279 | tNET | RR | 1 | BSRAM_R10[2] | u_extr/mem_data_mem_data_0_0_s/ADB[9] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.368 | 7.368 | active clock edge time | ||||
7.368 | 0.000 | lvds_pclk | ||||
7.368 | 0.000 | tCL | RR | 165 | PLL_B | u_pll_50m/PLLA_inst/CLKOUT1 |
8.752 | 1.384 | tNET | RR | 1 | BSRAM_R10[2] | u_extr/mem_data_mem_data_0_0_s/CLKB |
8.718 | -0.035 | tSu | 1 | BSRAM_R10[2] | u_extr/mem_data_mem_data_0_0_s |
Path Statistics:
Clock Skew | 0.012 |
Setup Relationship | 7.368 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.372, 100.000% |
Arrival Data Path Delay | cell: 2.281, 37.146%; route: 3.493, 56.870%; tC2Q: 0.368, 5.984% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.384, 100.000% |
Path2
Path Summary:
Slack | 1.258 |
Data Arrival Time | 7.460 |
Data Required Time | 8.718 |
From | u_extr/buf_ra_0_s0 |
To | u_extr/mem_data_mem_data_0_11_s |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_B | u_pll_50m/PLLA_inst/CLKOUT1 |
1.372 | 1.372 | tNET | RR | 1 | R14C20[0][B] | u_extr/buf_ra_0_s0/CLK |
1.740 | 0.368 | tC2Q | RF | 8 | R14C20[0][B] | u_extr/buf_ra_0_s0/Q |
2.233 | 0.494 | tNET | FF | 1 | R13C24[3][B] | u_extr/n882_s4/I0 |
2.731 | 0.498 | tINS | FR | 5 | R13C24[3][B] | u_extr/n882_s4/F |
3.086 | 0.355 | tNET | RR | 1 | R14C23[3][B] | u_extr/n879_s4/I3 |
3.583 | 0.498 | tINS | RR | 5 | R14C23[3][B] | u_extr/n879_s4/F |
3.783 | 0.200 | tNET | RR | 1 | R14C21[3][A] | u_extr/n878_s4/I1 |
4.281 | 0.498 | tINS | RR | 1 | R14C21[3][A] | u_extr/n878_s4/F |
4.283 | 0.003 | tNET | RR | 1 | R14C21[2][B] | u_extr/n876_s2/I2 |
4.745 | 0.461 | tINS | RR | 3 | R14C21[2][B] | u_extr/n876_s2/F |
5.132 | 0.387 | tNET | RR | 1 | R13C23[2][B] | u_extr/buf_ra_c_10_s1/I1 |
5.648 | 0.516 | tINS | RR | 12 | R13C23[2][B] | u_extr/buf_ra_c_10_s1/F |
7.460 | 1.811 | tNET | RR | 1 | BSRAM_R10[10] | u_extr/mem_data_mem_data_0_11_s/ADB[11] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.368 | 7.368 | active clock edge time | ||||
7.368 | 0.000 | lvds_pclk | ||||
7.368 | 0.000 | tCL | RR | 165 | PLL_B | u_pll_50m/PLLA_inst/CLKOUT1 |
8.752 | 1.384 | tNET | RR | 1 | BSRAM_R10[10] | u_extr/mem_data_mem_data_0_11_s/CLKB |
8.718 | -0.035 | tSu | 1 | BSRAM_R10[10] | u_extr/mem_data_mem_data_0_11_s |
Path Statistics:
Clock Skew | 0.012 |
Setup Relationship | 7.368 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.372, 100.000% |
Arrival Data Path Delay | cell: 2.470, 40.575%; route: 3.250, 53.388%; tC2Q: 0.368, 6.037% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.384, 100.000% |
Path3
Path Summary:
Slack | 1.266 |
Data Arrival Time | 7.452 |
Data Required Time | 8.718 |
From | u_extr/buf_rd_s0 |
To | u_extr/mem_data_mem_data_0_6_s |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_B | u_pll_50m/PLLA_inst/CLKOUT1 |
1.398 | 1.398 | tNET | RR | 1 | R8C22[3][A] | u_extr/buf_rd_s0/CLK |
1.781 | 0.382 | tC2Q | RR | 58 | R8C22[3][A] | u_extr/buf_rd_s0/Q |
3.130 | 1.349 | tNET | RR | 1 | R13C19[3][B] | u_extr/n924_s1/I0 |
3.651 | 0.521 | tINS | RR | 1 | R13C19[3][B] | u_extr/n924_s1/F |
3.653 | 0.003 | tNET | RR | 1 | R13C19[3][A] | u_extr/buf_ra_12_s12/I3 |
4.151 | 0.498 | tINS | RR | 2 | R13C19[3][A] | u_extr/buf_ra_12_s12/F |
4.311 | 0.160 | tNET | RR | 1 | R14C19[3][B] | u_extr/buf_ra_c_12_s1/I0 |
4.832 | 0.521 | tINS | RR | 12 | R14C19[3][B] | u_extr/buf_ra_c_12_s1/F |
7.452 | 2.620 | tNET | RR | 1 | BSRAM_R28[6] | u_extr/mem_data_mem_data_0_6_s/ADB[13] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.368 | 7.368 | active clock edge time | ||||
7.368 | 0.000 | lvds_pclk | ||||
7.368 | 0.000 | tCL | RR | 165 | PLL_B | u_pll_50m/PLLA_inst/CLKOUT1 |
8.752 | 1.384 | tNET | RR | 1 | BSRAM_R28[6] | u_extr/mem_data_mem_data_0_6_s/CLKB |
8.718 | -0.035 | tSu | 1 | BSRAM_R28[6] | u_extr/mem_data_mem_data_0_6_s |
Path Statistics:
Clock Skew | -0.014 |
Setup Relationship | 7.368 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.398, 100.000% |
Arrival Data Path Delay | cell: 1.540, 25.439%; route: 4.131, 68.243%; tC2Q: 0.382, 6.318% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.384, 100.000% |
Path4
Path Summary:
Slack | 1.279 |
Data Arrival Time | 7.438 |
Data Required Time | 8.718 |
From | u_extr/buf_ra_0_s0 |
To | u_extr/mem_data_mem_data_0_6_s |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_B | u_pll_50m/PLLA_inst/CLKOUT1 |
1.372 | 1.372 | tNET | RR | 1 | R14C20[0][B] | u_extr/buf_ra_0_s0/CLK |
1.740 | 0.368 | tC2Q | RF | 8 | R14C20[0][B] | u_extr/buf_ra_0_s0/Q |
2.233 | 0.494 | tNET | FF | 1 | R13C24[3][B] | u_extr/n882_s4/I0 |
2.731 | 0.498 | tINS | FR | 5 | R13C24[3][B] | u_extr/n882_s4/F |
3.086 | 0.355 | tNET | RR | 1 | R14C23[3][B] | u_extr/n879_s4/I3 |
3.583 | 0.498 | tINS | RR | 5 | R14C23[3][B] | u_extr/n879_s4/F |
3.783 | 0.200 | tNET | RR | 1 | R14C21[3][A] | u_extr/n878_s4/I1 |
4.281 | 0.498 | tINS | RR | 1 | R14C21[3][A] | u_extr/n878_s4/F |
4.283 | 0.003 | tNET | RR | 1 | R14C21[2][B] | u_extr/n876_s2/I2 |
4.745 | 0.461 | tINS | RR | 3 | R14C21[2][B] | u_extr/n876_s2/F |
5.132 | 0.387 | tNET | RR | 1 | R13C23[2][B] | u_extr/buf_ra_c_10_s1/I1 |
5.648 | 0.516 | tINS | RR | 12 | R13C23[2][B] | u_extr/buf_ra_c_10_s1/F |
7.438 | 1.790 | tNET | RR | 1 | BSRAM_R28[6] | u_extr/mem_data_mem_data_0_6_s/ADB[11] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.368 | 7.368 | active clock edge time | ||||
7.368 | 0.000 | lvds_pclk | ||||
7.368 | 0.000 | tCL | RR | 165 | PLL_B | u_pll_50m/PLLA_inst/CLKOUT1 |
8.752 | 1.384 | tNET | RR | 1 | BSRAM_R28[6] | u_extr/mem_data_mem_data_0_6_s/CLKB |
8.718 | -0.035 | tSu | 1 | BSRAM_R28[6] | u_extr/mem_data_mem_data_0_6_s |
Path Statistics:
Clock Skew | 0.012 |
Setup Relationship | 7.368 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.372, 100.000% |
Arrival Data Path Delay | cell: 2.470, 40.717%; route: 3.229, 53.225%; tC2Q: 0.368, 6.058% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.384, 100.000% |
Path5
Path Summary:
Slack | 1.293 |
Data Arrival Time | 7.435 |
Data Required Time | 8.727 |
From | u_extr/buf_ra_0_s0 |
To | u_extr/mem_data_mem_data_0_8_s |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_B | u_pll_50m/PLLA_inst/CLKOUT1 |
1.372 | 1.372 | tNET | RR | 1 | R14C20[0][B] | u_extr/buf_ra_0_s0/CLK |
1.740 | 0.368 | tC2Q | RF | 8 | R14C20[0][B] | u_extr/buf_ra_0_s0/Q |
2.233 | 0.494 | tNET | FF | 1 | R13C24[3][B] | u_extr/n882_s4/I0 |
2.731 | 0.498 | tINS | FR | 5 | R13C24[3][B] | u_extr/n882_s4/F |
3.086 | 0.355 | tNET | RR | 1 | R14C23[3][B] | u_extr/n879_s4/I3 |
3.583 | 0.498 | tINS | RR | 5 | R14C23[3][B] | u_extr/n879_s4/F |
3.783 | 0.200 | tNET | RR | 1 | R14C21[2][A] | u_extr/n878_s5/I2 |
4.310 | 0.526 | tINS | RR | 2 | R14C21[2][A] | u_extr/n878_s5/F |
4.470 | 0.160 | tNET | RR | 1 | R14C22[2][B] | u_extr/buf_ra_8_s11/I1 |
4.732 | 0.262 | tINS | RR | 2 | R14C22[2][B] | u_extr/buf_ra_8_s11/F |
4.737 | 0.005 | tNET | RR | 1 | R14C22[3][A] | u_extr/buf_ra_c_8_s1/I0 |
5.235 | 0.498 | tINS | RR | 12 | R14C22[3][A] | u_extr/buf_ra_c_8_s1/F |
7.435 | 2.200 | tNET | RR | 1 | BSRAM_R28[7] | u_extr/mem_data_mem_data_0_8_s/ADB[9] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.368 | 7.368 | active clock edge time | ||||
7.368 | 0.000 | lvds_pclk | ||||
7.368 | 0.000 | tCL | RR | 165 | PLL_B | u_pll_50m/PLLA_inst/CLKOUT1 |
8.762 | 1.393 | tNET | RR | 1 | BSRAM_R28[7] | u_extr/mem_data_mem_data_0_8_s/CLKB |
8.727 | -0.035 | tSu | 1 | BSRAM_R28[7] | u_extr/mem_data_mem_data_0_8_s |
Path Statistics:
Clock Skew | 0.021 |
Setup Relationship | 7.368 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.372, 100.000% |
Arrival Data Path Delay | cell: 2.281, 37.629%; route: 3.414, 56.309%; tC2Q: 0.368, 6.062% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.393, 100.000% |
Path6
Path Summary:
Slack | 1.350 |
Data Arrival Time | 7.377 |
Data Required Time | 8.727 |
From | u_extr/buf_ra_0_s0 |
To | u_extr/mem_data_mem_data_0_7_s |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_B | u_pll_50m/PLLA_inst/CLKOUT1 |
1.372 | 1.372 | tNET | RR | 1 | R14C20[0][B] | u_extr/buf_ra_0_s0/CLK |
1.740 | 0.368 | tC2Q | RF | 8 | R14C20[0][B] | u_extr/buf_ra_0_s0/Q |
2.233 | 0.494 | tNET | FF | 1 | R13C24[3][B] | u_extr/n882_s4/I0 |
2.731 | 0.498 | tINS | FR | 5 | R13C24[3][B] | u_extr/n882_s4/F |
3.086 | 0.355 | tNET | RR | 1 | R14C23[3][B] | u_extr/n879_s4/I3 |
3.583 | 0.498 | tINS | RR | 5 | R14C23[3][B] | u_extr/n879_s4/F |
3.938 | 0.355 | tNET | RR | 1 | R14C21[3][B] | u_extr/n877_s4/I2 |
4.353 | 0.415 | tINS | RR | 3 | R14C21[3][B] | u_extr/n877_s4/F |
4.706 | 0.352 | tNET | RR | 1 | R13C22[3][A] | u_extr/buf_ra_c_9_s1/I1 |
5.227 | 0.521 | tINS | RR | 12 | R13C22[3][A] | u_extr/buf_ra_c_9_s1/F |
7.377 | 2.150 | tNET | RR | 1 | BSRAM_R10[7] | u_extr/mem_data_mem_data_0_7_s/ADB[10] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.368 | 7.368 | active clock edge time | ||||
7.368 | 0.000 | lvds_pclk | ||||
7.368 | 0.000 | tCL | RR | 165 | PLL_B | u_pll_50m/PLLA_inst/CLKOUT1 |
8.762 | 1.393 | tNET | RR | 1 | BSRAM_R10[7] | u_extr/mem_data_mem_data_0_7_s/CLKB |
8.727 | -0.035 | tSu | 1 | BSRAM_R10[7] | u_extr/mem_data_mem_data_0_7_s |
Path Statistics:
Clock Skew | 0.021 |
Setup Relationship | 7.368 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.372, 100.000% |
Arrival Data Path Delay | cell: 1.931, 32.161%; route: 3.706, 61.719%; tC2Q: 0.368, 6.120% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.393, 100.000% |
Path7
Path Summary:
Slack | 1.364 |
Data Arrival Time | 7.345 |
Data Required Time | 8.708 |
From | u_extr/buf_ra_0_s0 |
To | u_extr/mem_data_mem_data_0_10_s |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_B | u_pll_50m/PLLA_inst/CLKOUT1 |
1.372 | 1.372 | tNET | RR | 1 | R14C20[0][B] | u_extr/buf_ra_0_s0/CLK |
1.740 | 0.368 | tC2Q | RF | 8 | R14C20[0][B] | u_extr/buf_ra_0_s0/Q |
2.233 | 0.494 | tNET | FF | 1 | R13C24[3][B] | u_extr/n882_s4/I0 |
2.731 | 0.498 | tINS | FR | 5 | R13C24[3][B] | u_extr/n882_s4/F |
3.086 | 0.355 | tNET | RR | 1 | R14C23[3][B] | u_extr/n879_s4/I3 |
3.583 | 0.498 | tINS | RR | 5 | R14C23[3][B] | u_extr/n879_s4/F |
3.783 | 0.200 | tNET | RR | 1 | R14C21[3][A] | u_extr/n878_s4/I1 |
4.281 | 0.498 | tINS | RR | 1 | R14C21[3][A] | u_extr/n878_s4/F |
4.283 | 0.003 | tNET | RR | 1 | R14C21[2][B] | u_extr/n876_s2/I2 |
4.745 | 0.461 | tINS | RR | 3 | R14C21[2][B] | u_extr/n876_s2/F |
5.132 | 0.387 | tNET | RR | 1 | R13C23[2][B] | u_extr/buf_ra_c_10_s1/I1 |
5.648 | 0.516 | tINS | RR | 12 | R13C23[2][B] | u_extr/buf_ra_c_10_s1/F |
7.345 | 1.696 | tNET | RR | 1 | BSRAM_R10[9] | u_extr/mem_data_mem_data_0_10_s/ADB[11] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.368 | 7.368 | active clock edge time | ||||
7.368 | 0.000 | lvds_pclk | ||||
7.368 | 0.000 | tCL | RR | 165 | PLL_B | u_pll_50m/PLLA_inst/CLKOUT1 |
8.743 | 1.375 | tNET | RR | 1 | BSRAM_R10[9] | u_extr/mem_data_mem_data_0_10_s/CLKB |
8.708 | -0.035 | tSu | 1 | BSRAM_R10[9] | u_extr/mem_data_mem_data_0_10_s |
Path Statistics:
Clock Skew | 0.002 |
Setup Relationship | 7.368 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.372, 100.000% |
Arrival Data Path Delay | cell: 2.470, 41.356%; route: 3.135, 52.491%; tC2Q: 0.368, 6.153% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.375, 100.000% |
Path8
Path Summary:
Slack | 1.374 |
Data Arrival Time | 7.343 |
Data Required Time | 8.718 |
From | u_extr/buf_ra_0_s0 |
To | u_extr/mem_data_mem_data_0_6_s |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_B | u_pll_50m/PLLA_inst/CLKOUT1 |
1.372 | 1.372 | tNET | RR | 1 | R14C20[0][B] | u_extr/buf_ra_0_s0/CLK |
1.740 | 0.368 | tC2Q | RF | 8 | R14C20[0][B] | u_extr/buf_ra_0_s0/Q |
2.233 | 0.494 | tNET | FF | 1 | R13C24[3][B] | u_extr/n882_s4/I0 |
2.731 | 0.498 | tINS | FR | 5 | R13C24[3][B] | u_extr/n882_s4/F |
3.086 | 0.355 | tNET | RR | 1 | R14C23[3][B] | u_extr/n879_s4/I3 |
3.583 | 0.498 | tINS | RR | 5 | R14C23[3][B] | u_extr/n879_s4/F |
3.938 | 0.355 | tNET | RR | 1 | R14C21[3][B] | u_extr/n877_s4/I2 |
4.353 | 0.415 | tINS | RR | 3 | R14C21[3][B] | u_extr/n877_s4/F |
4.706 | 0.352 | tNET | RR | 1 | R13C22[3][A] | u_extr/buf_ra_c_9_s1/I1 |
5.227 | 0.521 | tINS | RR | 12 | R13C22[3][A] | u_extr/buf_ra_c_9_s1/F |
7.343 | 2.116 | tNET | RR | 1 | BSRAM_R28[6] | u_extr/mem_data_mem_data_0_6_s/ADB[10] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.368 | 7.368 | active clock edge time | ||||
7.368 | 0.000 | lvds_pclk | ||||
7.368 | 0.000 | tCL | RR | 165 | PLL_B | u_pll_50m/PLLA_inst/CLKOUT1 |
8.752 | 1.384 | tNET | RR | 1 | BSRAM_R28[6] | u_extr/mem_data_mem_data_0_6_s/CLKB |
8.718 | -0.035 | tSu | 1 | BSRAM_R28[6] | u_extr/mem_data_mem_data_0_6_s |
Path Statistics:
Clock Skew | 0.012 |
Setup Relationship | 7.368 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.372, 100.000% |
Arrival Data Path Delay | cell: 1.931, 32.342%; route: 3.673, 61.503%; tC2Q: 0.368, 6.154% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.384, 100.000% |
Path9
Path Summary:
Slack | 1.388 |
Data Arrival Time | 7.330 |
Data Required Time | 8.718 |
From | u_extr/buf_ra_0_s0 |
To | u_extr/mem_data_mem_data_0_6_s |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_B | u_pll_50m/PLLA_inst/CLKOUT1 |
1.372 | 1.372 | tNET | RR | 1 | R14C20[0][B] | u_extr/buf_ra_0_s0/CLK |
1.740 | 0.368 | tC2Q | RF | 8 | R14C20[0][B] | u_extr/buf_ra_0_s0/Q |
2.233 | 0.494 | tNET | FF | 1 | R13C24[3][B] | u_extr/n882_s4/I0 |
2.731 | 0.498 | tINS | FR | 5 | R13C24[3][B] | u_extr/n882_s4/F |
3.086 | 0.355 | tNET | RR | 1 | R14C23[3][A] | u_extr/n880_s3/I2 |
3.583 | 0.498 | tINS | RR | 3 | R14C23[3][A] | u_extr/n880_s3/F |
4.151 | 0.567 | tNET | RR | 1 | R15C20[3][A] | u_extr/buf_ra_c_6_s1/I1 |
4.672 | 0.521 | tINS | RR | 12 | R15C20[3][A] | u_extr/buf_ra_c_6_s1/F |
7.330 | 2.657 | tNET | RR | 1 | BSRAM_R28[6] | u_extr/mem_data_mem_data_0_6_s/ADB[7] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.368 | 7.368 | active clock edge time | ||||
7.368 | 0.000 | lvds_pclk | ||||
7.368 | 0.000 | tCL | RR | 165 | PLL_B | u_pll_50m/PLLA_inst/CLKOUT1 |
8.752 | 1.384 | tNET | RR | 1 | BSRAM_R28[6] | u_extr/mem_data_mem_data_0_6_s/CLKB |
8.718 | -0.035 | tSu | 1 | BSRAM_R28[6] | u_extr/mem_data_mem_data_0_6_s |
Path Statistics:
Clock Skew | 0.012 |
Setup Relationship | 7.368 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.372, 100.000% |
Arrival Data Path Delay | cell: 1.516, 25.451%; route: 4.074, 68.380%; tC2Q: 0.368, 6.169% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.384, 100.000% |
Path10
Path Summary:
Slack | 1.393 |
Data Arrival Time | 7.316 |
Data Required Time | 8.708 |
From | u_extr/buf_ra_0_s0 |
To | u_extr/mem_data_mem_data_0_4_s |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_B | u_pll_50m/PLLA_inst/CLKOUT1 |
1.372 | 1.372 | tNET | RR | 1 | R14C20[0][B] | u_extr/buf_ra_0_s0/CLK |
1.740 | 0.368 | tC2Q | RF | 8 | R14C20[0][B] | u_extr/buf_ra_0_s0/Q |
2.233 | 0.494 | tNET | FF | 1 | R13C24[3][B] | u_extr/n882_s4/I0 |
2.731 | 0.498 | tINS | FR | 5 | R13C24[3][B] | u_extr/n882_s4/F |
3.086 | 0.355 | tNET | RR | 1 | R14C23[3][B] | u_extr/n879_s4/I3 |
3.583 | 0.498 | tINS | RR | 5 | R14C23[3][B] | u_extr/n879_s4/F |
3.783 | 0.200 | tNET | RR | 1 | R14C21[2][A] | u_extr/n878_s5/I2 |
4.310 | 0.526 | tINS | RR | 2 | R14C21[2][A] | u_extr/n878_s5/F |
4.470 | 0.160 | tNET | RR | 1 | R14C22[2][B] | u_extr/buf_ra_8_s11/I1 |
4.732 | 0.262 | tINS | RR | 2 | R14C22[2][B] | u_extr/buf_ra_8_s11/F |
4.737 | 0.005 | tNET | RR | 1 | R14C22[3][A] | u_extr/buf_ra_c_8_s1/I0 |
5.235 | 0.498 | tINS | RR | 12 | R14C22[3][A] | u_extr/buf_ra_c_8_s1/F |
7.316 | 2.081 | tNET | RR | 1 | BSRAM_R28[5] | u_extr/mem_data_mem_data_0_4_s/ADB[9] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.368 | 7.368 | active clock edge time | ||||
7.368 | 0.000 | lvds_pclk | ||||
7.368 | 0.000 | tCL | RR | 165 | PLL_B | u_pll_50m/PLLA_inst/CLKOUT1 |
8.743 | 1.375 | tNET | RR | 1 | BSRAM_R28[5] | u_extr/mem_data_mem_data_0_4_s/CLKB |
8.708 | -0.035 | tSu | 1 | BSRAM_R28[5] | u_extr/mem_data_mem_data_0_4_s |
Path Statistics:
Clock Skew | 0.002 |
Setup Relationship | 7.368 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.372, 100.000% |
Arrival Data Path Delay | cell: 2.281, 38.381%; route: 3.295, 55.436%; tC2Q: 0.368, 6.183% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.375, 100.000% |
Path11
Path Summary:
Slack | 1.398 |
Data Arrival Time | 7.330 |
Data Required Time | 8.727 |
From | u_extr/buf_ra_0_s0 |
To | u_extr/mem_data_mem_data_0_8_s |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_B | u_pll_50m/PLLA_inst/CLKOUT1 |
1.372 | 1.372 | tNET | RR | 1 | R14C20[0][B] | u_extr/buf_ra_0_s0/CLK |
1.740 | 0.368 | tC2Q | RF | 8 | R14C20[0][B] | u_extr/buf_ra_0_s0/Q |
2.233 | 0.494 | tNET | FF | 1 | R13C24[3][B] | u_extr/n882_s4/I0 |
2.731 | 0.498 | tINS | FR | 5 | R13C24[3][B] | u_extr/n882_s4/F |
3.086 | 0.355 | tNET | RR | 1 | R14C23[3][B] | u_extr/n879_s4/I3 |
3.583 | 0.498 | tINS | RR | 5 | R14C23[3][B] | u_extr/n879_s4/F |
3.938 | 0.355 | tNET | RR | 1 | R14C21[3][B] | u_extr/n877_s4/I2 |
4.353 | 0.415 | tINS | RR | 3 | R14C21[3][B] | u_extr/n877_s4/F |
4.706 | 0.352 | tNET | RR | 1 | R13C22[3][A] | u_extr/buf_ra_c_9_s1/I1 |
5.227 | 0.521 | tINS | RR | 12 | R13C22[3][A] | u_extr/buf_ra_c_9_s1/F |
7.330 | 2.102 | tNET | RR | 1 | BSRAM_R28[7] | u_extr/mem_data_mem_data_0_8_s/ADB[10] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.368 | 7.368 | active clock edge time | ||||
7.368 | 0.000 | lvds_pclk | ||||
7.368 | 0.000 | tCL | RR | 165 | PLL_B | u_pll_50m/PLLA_inst/CLKOUT1 |
8.762 | 1.393 | tNET | RR | 1 | BSRAM_R28[7] | u_extr/mem_data_mem_data_0_8_s/CLKB |
8.727 | -0.035 | tSu | 1 | BSRAM_R28[7] | u_extr/mem_data_mem_data_0_8_s |
Path Statistics:
Clock Skew | 0.021 |
Setup Relationship | 7.368 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.372, 100.000% |
Arrival Data Path Delay | cell: 1.931, 32.417%; route: 3.659, 61.414%; tC2Q: 0.368, 6.169% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.393, 100.000% |
Path12
Path Summary:
Slack | 1.402 |
Data Arrival Time | 7.316 |
Data Required Time | 8.718 |
From | u_extr/buf_ra_0_s0 |
To | u_extr/mem_data_mem_data_0_6_s |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_B | u_pll_50m/PLLA_inst/CLKOUT1 |
1.372 | 1.372 | tNET | RR | 1 | R14C20[0][B] | u_extr/buf_ra_0_s0/CLK |
1.740 | 0.368 | tC2Q | RF | 8 | R14C20[0][B] | u_extr/buf_ra_0_s0/Q |
2.233 | 0.494 | tNET | FF | 1 | R13C24[3][B] | u_extr/n882_s4/I0 |
2.731 | 0.498 | tINS | FR | 5 | R13C24[3][B] | u_extr/n882_s4/F |
3.086 | 0.355 | tNET | RR | 1 | R14C23[3][B] | u_extr/n879_s4/I3 |
3.583 | 0.498 | tINS | RR | 5 | R14C23[3][B] | u_extr/n879_s4/F |
3.783 | 0.200 | tNET | RR | 1 | R14C21[2][A] | u_extr/n878_s5/I2 |
4.310 | 0.526 | tINS | RR | 2 | R14C21[2][A] | u_extr/n878_s5/F |
4.470 | 0.160 | tNET | RR | 1 | R14C22[2][B] | u_extr/buf_ra_8_s11/I1 |
4.732 | 0.262 | tINS | RR | 2 | R14C22[2][B] | u_extr/buf_ra_8_s11/F |
4.737 | 0.005 | tNET | RR | 1 | R14C22[3][A] | u_extr/buf_ra_c_8_s1/I0 |
5.235 | 0.498 | tINS | RR | 12 | R14C22[3][A] | u_extr/buf_ra_c_8_s1/F |
7.316 | 2.081 | tNET | RR | 1 | BSRAM_R28[6] | u_extr/mem_data_mem_data_0_6_s/ADB[9] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.368 | 7.368 | active clock edge time | ||||
7.368 | 0.000 | lvds_pclk | ||||
7.368 | 0.000 | tCL | RR | 165 | PLL_B | u_pll_50m/PLLA_inst/CLKOUT1 |
8.752 | 1.384 | tNET | RR | 1 | BSRAM_R28[6] | u_extr/mem_data_mem_data_0_6_s/CLKB |
8.718 | -0.035 | tSu | 1 | BSRAM_R28[6] | u_extr/mem_data_mem_data_0_6_s |
Path Statistics:
Clock Skew | 0.012 |
Setup Relationship | 7.368 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.372, 100.000% |
Arrival Data Path Delay | cell: 2.281, 38.381%; route: 3.295, 55.436%; tC2Q: 0.368, 6.183% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.384, 100.000% |
Path13
Path Summary:
Slack | 1.408 |
Data Arrival Time | 7.310 |
Data Required Time | 8.718 |
From | u_extr/buf_rd_s0 |
To | u_extr/mem_data_mem_data_0_0_s |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_B | u_pll_50m/PLLA_inst/CLKOUT1 |
1.398 | 1.398 | tNET | RR | 1 | R8C22[3][A] | u_extr/buf_rd_s0/CLK |
1.781 | 0.382 | tC2Q | RR | 58 | R8C22[3][A] | u_extr/buf_rd_s0/Q |
3.130 | 1.349 | tNET | RR | 1 | R13C19[2][A] | u_extr/buf_ra_11_s13/I2 |
3.646 | 0.516 | tINS | RR | 2 | R13C19[2][A] | u_extr/buf_ra_11_s13/F |
3.651 | 0.005 | tNET | RR | 1 | R13C19[1][B] | u_extr/buf_ra_c_11_s1/I0 |
4.112 | 0.461 | tINS | RR | 12 | R13C19[1][B] | u_extr/buf_ra_c_11_s1/F |
7.310 | 3.197 | tNET | RR | 1 | BSRAM_R10[2] | u_extr/mem_data_mem_data_0_0_s/ADB[12] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.368 | 7.368 | active clock edge time | ||||
7.368 | 0.000 | lvds_pclk | ||||
7.368 | 0.000 | tCL | RR | 165 | PLL_B | u_pll_50m/PLLA_inst/CLKOUT1 |
8.752 | 1.384 | tNET | RR | 1 | BSRAM_R10[2] | u_extr/mem_data_mem_data_0_0_s/CLKB |
8.718 | -0.035 | tSu | 1 | BSRAM_R10[2] | u_extr/mem_data_mem_data_0_0_s |
Path Statistics:
Clock Skew | -0.014 |
Setup Relationship | 7.368 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.398, 100.000% |
Arrival Data Path Delay | cell: 0.977, 16.536%; route: 4.551, 76.993%; tC2Q: 0.382, 6.471% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.384, 100.000% |
Path14
Path Summary:
Slack | 1.413 |
Data Arrival Time | 7.315 |
Data Required Time | 8.727 |
From | u_extr/buf_ra_0_s0 |
To | u_extr/mem_data_mem_data_0_8_s |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_B | u_pll_50m/PLLA_inst/CLKOUT1 |
1.372 | 1.372 | tNET | RR | 1 | R14C20[0][B] | u_extr/buf_ra_0_s0/CLK |
1.740 | 0.368 | tC2Q | RF | 8 | R14C20[0][B] | u_extr/buf_ra_0_s0/Q |
2.233 | 0.494 | tNET | FF | 1 | R13C24[3][B] | u_extr/n882_s4/I0 |
2.731 | 0.498 | tINS | FR | 5 | R13C24[3][B] | u_extr/n882_s4/F |
3.086 | 0.355 | tNET | RR | 1 | R14C23[3][A] | u_extr/n880_s3/I2 |
3.583 | 0.498 | tINS | RR | 3 | R14C23[3][A] | u_extr/n880_s3/F |
4.151 | 0.567 | tNET | RR | 1 | R15C20[3][A] | u_extr/buf_ra_c_6_s1/I1 |
4.672 | 0.521 | tINS | RR | 12 | R15C20[3][A] | u_extr/buf_ra_c_6_s1/F |
7.315 | 2.642 | tNET | RR | 1 | BSRAM_R28[7] | u_extr/mem_data_mem_data_0_8_s/ADB[7] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.368 | 7.368 | active clock edge time | ||||
7.368 | 0.000 | lvds_pclk | ||||
7.368 | 0.000 | tCL | RR | 165 | PLL_B | u_pll_50m/PLLA_inst/CLKOUT1 |
8.762 | 1.393 | tNET | RR | 1 | BSRAM_R28[7] | u_extr/mem_data_mem_data_0_8_s/CLKB |
8.727 | -0.035 | tSu | 1 | BSRAM_R28[7] | u_extr/mem_data_mem_data_0_8_s |
Path Statistics:
Clock Skew | 0.021 |
Setup Relationship | 7.368 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.372, 100.000% |
Arrival Data Path Delay | cell: 1.516, 25.515%; route: 4.059, 68.300%; tC2Q: 0.368, 6.184% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.393, 100.000% |
Path15
Path Summary:
Slack | 1.414 |
Data Arrival Time | 7.303 |
Data Required Time | 8.718 |
From | u_extr/buf_ra_0_s0 |
To | u_extr/mem_data_mem_data_0_5_s |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_B | u_pll_50m/PLLA_inst/CLKOUT1 |
1.372 | 1.372 | tNET | RR | 1 | R14C20[0][B] | u_extr/buf_ra_0_s0/CLK |
1.740 | 0.368 | tC2Q | RF | 8 | R14C20[0][B] | u_extr/buf_ra_0_s0/Q |
2.233 | 0.494 | tNET | FF | 1 | R13C24[3][B] | u_extr/n882_s4/I0 |
2.731 | 0.498 | tINS | FR | 5 | R13C24[3][B] | u_extr/n882_s4/F |
3.086 | 0.355 | tNET | RR | 1 | R14C23[3][A] | u_extr/n880_s3/I2 |
3.583 | 0.498 | tINS | RR | 3 | R14C23[3][A] | u_extr/n880_s3/F |
4.151 | 0.567 | tNET | RR | 1 | R15C20[3][A] | u_extr/buf_ra_c_6_s1/I1 |
4.672 | 0.521 | tINS | RR | 12 | R15C20[3][A] | u_extr/buf_ra_c_6_s1/F |
7.303 | 2.631 | tNET | RR | 1 | BSRAM_R10[6] | u_extr/mem_data_mem_data_0_5_s/ADB[7] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.368 | 7.368 | active clock edge time | ||||
7.368 | 0.000 | lvds_pclk | ||||
7.368 | 0.000 | tCL | RR | 165 | PLL_B | u_pll_50m/PLLA_inst/CLKOUT1 |
8.752 | 1.384 | tNET | RR | 1 | BSRAM_R10[6] | u_extr/mem_data_mem_data_0_5_s/CLKB |
8.718 | -0.035 | tSu | 1 | BSRAM_R10[6] | u_extr/mem_data_mem_data_0_5_s |
Path Statistics:
Clock Skew | 0.012 |
Setup Relationship | 7.368 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.372, 100.000% |
Arrival Data Path Delay | cell: 1.516, 25.564%; route: 4.047, 68.240%; tC2Q: 0.368, 6.196% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.384, 100.000% |
Path16
Path Summary:
Slack | 1.446 |
Data Arrival Time | 7.281 |
Data Required Time | 8.727 |
From | u_extr/buf_ra_0_s0 |
To | u_extr/mem_data_mem_data_0_1_s |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_B | u_pll_50m/PLLA_inst/CLKOUT1 |
1.372 | 1.372 | tNET | RR | 1 | R14C20[0][B] | u_extr/buf_ra_0_s0/CLK |
1.740 | 0.368 | tC2Q | RF | 8 | R14C20[0][B] | u_extr/buf_ra_0_s0/Q |
2.233 | 0.494 | tNET | FF | 1 | R13C24[3][B] | u_extr/n882_s4/I0 |
2.731 | 0.498 | tINS | FR | 5 | R13C24[3][B] | u_extr/n882_s4/F |
3.086 | 0.355 | tNET | RR | 1 | R14C23[3][B] | u_extr/n879_s4/I3 |
3.583 | 0.498 | tINS | RR | 5 | R14C23[3][B] | u_extr/n879_s4/F |
3.783 | 0.200 | tNET | RR | 1 | R14C21[3][A] | u_extr/n878_s4/I1 |
4.281 | 0.498 | tINS | RR | 1 | R14C21[3][A] | u_extr/n878_s4/F |
4.283 | 0.003 | tNET | RR | 1 | R14C21[2][B] | u_extr/n876_s2/I2 |
4.745 | 0.461 | tINS | RR | 3 | R14C21[2][B] | u_extr/n876_s2/F |
5.132 | 0.387 | tNET | RR | 1 | R13C23[2][B] | u_extr/buf_ra_c_10_s1/I1 |
5.648 | 0.516 | tINS | RR | 12 | R13C23[2][B] | u_extr/buf_ra_c_10_s1/F |
7.281 | 1.633 | tNET | RR | 1 | BSRAM_R10[3] | u_extr/mem_data_mem_data_0_1_s/ADB[11] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.368 | 7.368 | active clock edge time | ||||
7.368 | 0.000 | lvds_pclk | ||||
7.368 | 0.000 | tCL | RR | 165 | PLL_B | u_pll_50m/PLLA_inst/CLKOUT1 |
8.762 | 1.393 | tNET | RR | 1 | BSRAM_R10[3] | u_extr/mem_data_mem_data_0_1_s/CLKB |
8.727 | -0.035 | tSu | 1 | BSRAM_R10[3] | u_extr/mem_data_mem_data_0_1_s |
Path Statistics:
Clock Skew | 0.021 |
Setup Relationship | 7.368 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.372, 100.000% |
Arrival Data Path Delay | cell: 2.470, 41.802%; route: 3.071, 51.978%; tC2Q: 0.368, 6.220% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.393, 100.000% |
Path17
Path Summary:
Slack | 1.482 |
Data Arrival Time | 7.236 |
Data Required Time | 8.718 |
From | u_extr/buf_ra_0_s0 |
To | u_extr/mem_data_mem_data_0_0_s |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_B | u_pll_50m/PLLA_inst/CLKOUT1 |
1.372 | 1.372 | tNET | RR | 1 | R14C20[0][B] | u_extr/buf_ra_0_s0/CLK |
1.740 | 0.368 | tC2Q | RF | 8 | R14C20[0][B] | u_extr/buf_ra_0_s0/Q |
2.233 | 0.494 | tNET | FF | 1 | R13C24[3][B] | u_extr/n882_s4/I0 |
2.731 | 0.498 | tINS | FR | 5 | R13C24[3][B] | u_extr/n882_s4/F |
3.086 | 0.355 | tNET | RR | 1 | R14C23[3][B] | u_extr/n879_s4/I3 |
3.583 | 0.498 | tINS | RR | 5 | R14C23[3][B] | u_extr/n879_s4/F |
3.783 | 0.200 | tNET | RR | 1 | R14C21[3][A] | u_extr/n878_s4/I1 |
4.281 | 0.498 | tINS | RR | 1 | R14C21[3][A] | u_extr/n878_s4/F |
4.283 | 0.003 | tNET | RR | 1 | R14C21[2][B] | u_extr/n876_s2/I2 |
4.745 | 0.461 | tINS | RR | 3 | R14C21[2][B] | u_extr/n876_s2/F |
5.132 | 0.387 | tNET | RR | 1 | R13C23[2][B] | u_extr/buf_ra_c_10_s1/I1 |
5.648 | 0.516 | tINS | RR | 12 | R13C23[2][B] | u_extr/buf_ra_c_10_s1/F |
7.236 | 1.587 | tNET | RR | 1 | BSRAM_R10[2] | u_extr/mem_data_mem_data_0_0_s/ADB[11] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.368 | 7.368 | active clock edge time | ||||
7.368 | 0.000 | lvds_pclk | ||||
7.368 | 0.000 | tCL | RR | 165 | PLL_B | u_pll_50m/PLLA_inst/CLKOUT1 |
8.752 | 1.384 | tNET | RR | 1 | BSRAM_R10[2] | u_extr/mem_data_mem_data_0_0_s/CLKB |
8.718 | -0.035 | tSu | 1 | BSRAM_R10[2] | u_extr/mem_data_mem_data_0_0_s |
Path Statistics:
Clock Skew | 0.012 |
Setup Relationship | 7.368 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.372, 100.000% |
Arrival Data Path Delay | cell: 2.470, 42.123%; route: 3.026, 51.609%; tC2Q: 0.368, 6.267% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.384, 100.000% |
Path18
Path Summary:
Slack | 1.499 |
Data Arrival Time | 7.210 |
Data Required Time | 8.708 |
From | u_extr/buf_ra_0_s0 |
To | u_extr/mem_data_mem_data_0_4_s |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_B | u_pll_50m/PLLA_inst/CLKOUT1 |
1.372 | 1.372 | tNET | RR | 1 | R14C20[0][B] | u_extr/buf_ra_0_s0/CLK |
1.740 | 0.368 | tC2Q | RF | 8 | R14C20[0][B] | u_extr/buf_ra_0_s0/Q |
2.233 | 0.494 | tNET | FF | 1 | R13C24[3][B] | u_extr/n882_s4/I0 |
2.731 | 0.498 | tINS | FR | 5 | R13C24[3][B] | u_extr/n882_s4/F |
3.086 | 0.355 | tNET | RR | 1 | R14C23[3][B] | u_extr/n879_s4/I3 |
3.583 | 0.498 | tINS | RR | 5 | R14C23[3][B] | u_extr/n879_s4/F |
3.938 | 0.355 | tNET | RR | 1 | R14C21[3][B] | u_extr/n877_s4/I2 |
4.353 | 0.415 | tINS | RR | 3 | R14C21[3][B] | u_extr/n877_s4/F |
4.706 | 0.352 | tNET | RR | 1 | R13C22[3][A] | u_extr/buf_ra_c_9_s1/I1 |
5.227 | 0.521 | tINS | RR | 12 | R13C22[3][A] | u_extr/buf_ra_c_9_s1/F |
7.210 | 1.983 | tNET | RR | 1 | BSRAM_R28[5] | u_extr/mem_data_mem_data_0_4_s/ADB[10] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.368 | 7.368 | active clock edge time | ||||
7.368 | 0.000 | lvds_pclk | ||||
7.368 | 0.000 | tCL | RR | 165 | PLL_B | u_pll_50m/PLLA_inst/CLKOUT1 |
8.743 | 1.375 | tNET | RR | 1 | BSRAM_R28[5] | u_extr/mem_data_mem_data_0_4_s/CLKB |
8.708 | -0.035 | tSu | 1 | BSRAM_R28[5] | u_extr/mem_data_mem_data_0_4_s |
Path Statistics:
Clock Skew | 0.002 |
Setup Relationship | 7.368 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.372, 100.000% |
Arrival Data Path Delay | cell: 1.931, 33.084%; route: 3.539, 60.621%; tC2Q: 0.368, 6.296% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.375, 100.000% |
Path19
Path Summary:
Slack | 1.522 |
Data Arrival Time | 7.196 |
Data Required Time | 8.718 |
From | u_extr/buf_ra_0_s0 |
To | u_extr/mem_data_mem_data_0_5_s |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_B | u_pll_50m/PLLA_inst/CLKOUT1 |
1.372 | 1.372 | tNET | RR | 1 | R14C20[0][B] | u_extr/buf_ra_0_s0/CLK |
1.740 | 0.368 | tC2Q | RF | 8 | R14C20[0][B] | u_extr/buf_ra_0_s0/Q |
2.233 | 0.494 | tNET | FF | 1 | R13C24[3][B] | u_extr/n882_s4/I0 |
2.731 | 0.498 | tINS | FR | 5 | R13C24[3][B] | u_extr/n882_s4/F |
3.086 | 0.355 | tNET | RR | 1 | R14C23[3][B] | u_extr/n879_s4/I3 |
3.583 | 0.498 | tINS | RR | 5 | R14C23[3][B] | u_extr/n879_s4/F |
3.783 | 0.200 | tNET | RR | 1 | R14C21[2][A] | u_extr/n878_s5/I2 |
4.310 | 0.526 | tINS | RR | 2 | R14C21[2][A] | u_extr/n878_s5/F |
4.470 | 0.160 | tNET | RR | 1 | R14C22[2][B] | u_extr/buf_ra_8_s11/I1 |
4.732 | 0.262 | tINS | RR | 2 | R14C22[2][B] | u_extr/buf_ra_8_s11/F |
4.737 | 0.005 | tNET | RR | 1 | R14C22[3][A] | u_extr/buf_ra_c_8_s1/I0 |
5.235 | 0.498 | tINS | RR | 12 | R14C22[3][A] | u_extr/buf_ra_c_8_s1/F |
7.196 | 1.961 | tNET | RR | 1 | BSRAM_R10[6] | u_extr/mem_data_mem_data_0_5_s/ADB[9] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.368 | 7.368 | active clock edge time | ||||
7.368 | 0.000 | lvds_pclk | ||||
7.368 | 0.000 | tCL | RR | 165 | PLL_B | u_pll_50m/PLLA_inst/CLKOUT1 |
8.752 | 1.384 | tNET | RR | 1 | BSRAM_R10[6] | u_extr/mem_data_mem_data_0_5_s/CLKB |
8.718 | -0.035 | tSu | 1 | BSRAM_R10[6] | u_extr/mem_data_mem_data_0_5_s |
Path Statistics:
Clock Skew | 0.012 |
Setup Relationship | 7.368 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.372, 100.000% |
Arrival Data Path Delay | cell: 2.281, 39.171%; route: 3.175, 54.518%; tC2Q: 0.368, 6.310% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.384, 100.000% |
Path20
Path Summary:
Slack | 1.560 |
Data Arrival Time | 7.148 |
Data Required Time | 8.708 |
From | u_extr/oworking_s0 |
To | u_extr/mem_data_mem_data_0_3_s |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_B | u_pll_50m/PLLA_inst/CLKOUT1 |
1.401 | 1.401 | tNET | RR | 1 | R9C23[2][B] | u_extr/oworking_s0/CLK |
1.783 | 0.382 | tC2Q | RR | 27 | R9C23[2][B] | u_extr/oworking_s0/Q |
3.103 | 1.320 | tNET | RR | 1 | R14C20[3][B] | u_extr/buf_ra_0_s11/I1 |
3.624 | 0.521 | tINS | RR | 18 | R14C20[3][B] | u_extr/buf_ra_0_s11/F |
4.442 | 0.817 | tNET | RR | 1 | R13C23[3][B] | u_extr/buf_ra_c_2_s1/I3 |
4.963 | 0.521 | tINS | RR | 12 | R13C23[3][B] | u_extr/buf_ra_c_2_s1/F |
7.148 | 2.185 | tNET | RR | 1 | BSRAM_R10[5] | u_extr/mem_data_mem_data_0_3_s/ADB[3] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.368 | 7.368 | active clock edge time | ||||
7.368 | 0.000 | lvds_pclk | ||||
7.368 | 0.000 | tCL | RR | 165 | PLL_B | u_pll_50m/PLLA_inst/CLKOUT1 |
8.743 | 1.375 | tNET | RR | 1 | BSRAM_R10[5] | u_extr/mem_data_mem_data_0_3_s/CLKB |
8.708 | -0.035 | tSu | 1 | BSRAM_R10[5] | u_extr/mem_data_mem_data_0_3_s |
Path Statistics:
Clock Skew | -0.026 |
Setup Relationship | 7.368 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.401, 100.000% |
Arrival Data Path Delay | cell: 1.043, 18.138%; route: 4.323, 75.207%; tC2Q: 0.382, 6.655% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.375, 100.000% |
Path21
Path Summary:
Slack | 1.592 |
Data Arrival Time | 7.126 |
Data Required Time | 8.718 |
From | u_extr/buf_ra_0_s0 |
To | u_extr/mem_data_mem_data_0_2_s |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_B | u_pll_50m/PLLA_inst/CLKOUT1 |
1.372 | 1.372 | tNET | RR | 1 | R14C20[0][B] | u_extr/buf_ra_0_s0/CLK |
1.740 | 0.368 | tC2Q | RF | 8 | R14C20[0][B] | u_extr/buf_ra_0_s0/Q |
2.233 | 0.494 | tNET | FF | 1 | R13C24[3][B] | u_extr/n882_s4/I0 |
2.731 | 0.498 | tINS | FR | 5 | R13C24[3][B] | u_extr/n882_s4/F |
3.086 | 0.355 | tNET | RR | 1 | R14C23[3][B] | u_extr/n879_s4/I3 |
3.583 | 0.498 | tINS | RR | 5 | R14C23[3][B] | u_extr/n879_s4/F |
3.783 | 0.200 | tNET | RR | 1 | R14C21[3][A] | u_extr/n878_s4/I1 |
4.281 | 0.498 | tINS | RR | 1 | R14C21[3][A] | u_extr/n878_s4/F |
4.283 | 0.003 | tNET | RR | 1 | R14C21[2][B] | u_extr/n876_s2/I2 |
4.745 | 0.461 | tINS | RR | 3 | R14C21[2][B] | u_extr/n876_s2/F |
5.132 | 0.387 | tNET | RR | 1 | R13C23[2][B] | u_extr/buf_ra_c_10_s1/I1 |
5.648 | 0.516 | tINS | RR | 12 | R13C23[2][B] | u_extr/buf_ra_c_10_s1/F |
7.126 | 1.477 | tNET | RR | 1 | BSRAM_R10[4] | u_extr/mem_data_mem_data_0_2_s/ADB[11] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.368 | 7.368 | active clock edge time | ||||
7.368 | 0.000 | lvds_pclk | ||||
7.368 | 0.000 | tCL | RR | 165 | PLL_B | u_pll_50m/PLLA_inst/CLKOUT1 |
8.752 | 1.384 | tNET | RR | 1 | BSRAM_R10[4] | u_extr/mem_data_mem_data_0_2_s/CLKB |
8.718 | -0.035 | tSu | 1 | BSRAM_R10[4] | u_extr/mem_data_mem_data_0_2_s |
Path Statistics:
Clock Skew | 0.012 |
Setup Relationship | 7.368 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.372, 100.000% |
Arrival Data Path Delay | cell: 2.470, 42.929%; route: 2.916, 50.684%; tC2Q: 0.368, 6.387% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.384, 100.000% |
Path22
Path Summary:
Slack | 1.604 |
Data Arrival Time | 7.105 |
Data Required Time | 8.708 |
From | u_extr/buf_ra_0_s0 |
To | u_extr/mem_data_mem_data_0_4_s |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_B | u_pll_50m/PLLA_inst/CLKOUT1 |
1.372 | 1.372 | tNET | RR | 1 | R14C20[0][B] | u_extr/buf_ra_0_s0/CLK |
1.740 | 0.368 | tC2Q | RF | 8 | R14C20[0][B] | u_extr/buf_ra_0_s0/Q |
2.233 | 0.494 | tNET | FF | 1 | R13C24[3][B] | u_extr/n882_s4/I0 |
2.731 | 0.498 | tINS | FR | 5 | R13C24[3][B] | u_extr/n882_s4/F |
3.086 | 0.355 | tNET | RR | 1 | R14C23[3][B] | u_extr/n879_s4/I3 |
3.583 | 0.498 | tINS | RR | 5 | R14C23[3][B] | u_extr/n879_s4/F |
3.783 | 0.200 | tNET | RR | 1 | R14C21[3][A] | u_extr/n878_s4/I1 |
4.281 | 0.498 | tINS | RR | 1 | R14C21[3][A] | u_extr/n878_s4/F |
4.283 | 0.003 | tNET | RR | 1 | R14C21[2][B] | u_extr/n876_s2/I2 |
4.745 | 0.461 | tINS | RR | 3 | R14C21[2][B] | u_extr/n876_s2/F |
5.132 | 0.387 | tNET | RR | 1 | R13C23[2][B] | u_extr/buf_ra_c_10_s1/I1 |
5.648 | 0.516 | tINS | RR | 12 | R13C23[2][B] | u_extr/buf_ra_c_10_s1/F |
7.105 | 1.456 | tNET | RR | 1 | BSRAM_R28[5] | u_extr/mem_data_mem_data_0_4_s/ADB[11] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.368 | 7.368 | active clock edge time | ||||
7.368 | 0.000 | lvds_pclk | ||||
7.368 | 0.000 | tCL | RR | 165 | PLL_B | u_pll_50m/PLLA_inst/CLKOUT1 |
8.743 | 1.375 | tNET | RR | 1 | BSRAM_R28[5] | u_extr/mem_data_mem_data_0_4_s/CLKB |
8.708 | -0.035 | tSu | 1 | BSRAM_R28[5] | u_extr/mem_data_mem_data_0_4_s |
Path Statistics:
Clock Skew | 0.002 |
Setup Relationship | 7.368 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.372, 100.000% |
Arrival Data Path Delay | cell: 2.470, 43.088%; route: 2.895, 50.502%; tC2Q: 0.368, 6.411% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.375, 100.000% |
Path23
Path Summary:
Slack | 1.604 |
Data Arrival Time | 7.105 |
Data Required Time | 8.708 |
From | u_extr/buf_ra_0_s0 |
To | u_extr/mem_data_mem_data_0_3_s |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_B | u_pll_50m/PLLA_inst/CLKOUT1 |
1.372 | 1.372 | tNET | RR | 1 | R14C20[0][B] | u_extr/buf_ra_0_s0/CLK |
1.740 | 0.368 | tC2Q | RF | 8 | R14C20[0][B] | u_extr/buf_ra_0_s0/Q |
2.233 | 0.494 | tNET | FF | 1 | R13C24[3][B] | u_extr/n882_s4/I0 |
2.731 | 0.498 | tINS | FR | 5 | R13C24[3][B] | u_extr/n882_s4/F |
3.086 | 0.355 | tNET | RR | 1 | R14C23[3][B] | u_extr/n879_s4/I3 |
3.583 | 0.498 | tINS | RR | 5 | R14C23[3][B] | u_extr/n879_s4/F |
3.938 | 0.355 | tNET | RR | 1 | R14C21[3][B] | u_extr/n877_s4/I2 |
4.353 | 0.415 | tINS | RR | 3 | R14C21[3][B] | u_extr/n877_s4/F |
4.706 | 0.352 | tNET | RR | 1 | R13C22[3][A] | u_extr/buf_ra_c_9_s1/I1 |
5.227 | 0.521 | tINS | RR | 12 | R13C22[3][A] | u_extr/buf_ra_c_9_s1/F |
7.105 | 1.878 | tNET | RR | 1 | BSRAM_R10[5] | u_extr/mem_data_mem_data_0_3_s/ADB[10] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.368 | 7.368 | active clock edge time | ||||
7.368 | 0.000 | lvds_pclk | ||||
7.368 | 0.000 | tCL | RR | 165 | PLL_B | u_pll_50m/PLLA_inst/CLKOUT1 |
8.743 | 1.375 | tNET | RR | 1 | BSRAM_R10[5] | u_extr/mem_data_mem_data_0_3_s/CLKB |
8.708 | -0.035 | tSu | 1 | BSRAM_R10[5] | u_extr/mem_data_mem_data_0_3_s |
Path Statistics:
Clock Skew | 0.002 |
Setup Relationship | 7.368 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.372, 100.000% |
Arrival Data Path Delay | cell: 1.931, 33.689%; route: 3.434, 59.900%; tC2Q: 0.368, 6.411% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.375, 100.000% |
Path24
Path Summary:
Slack | 1.638 |
Data Arrival Time | 7.080 |
Data Required Time | 8.718 |
From | u_extr/buf_rd_s0 |
To | u_extr/mem_data_mem_data_0_11_s |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_B | u_pll_50m/PLLA_inst/CLKOUT1 |
1.398 | 1.398 | tNET | RR | 1 | R8C22[3][A] | u_extr/buf_rd_s0/CLK |
1.781 | 0.382 | tC2Q | RR | 58 | R8C22[3][A] | u_extr/buf_rd_s0/Q |
3.130 | 1.349 | tNET | RR | 1 | R13C19[3][B] | u_extr/n924_s1/I0 |
3.651 | 0.521 | tINS | RR | 1 | R13C19[3][B] | u_extr/n924_s1/F |
3.653 | 0.003 | tNET | RR | 1 | R13C19[3][A] | u_extr/buf_ra_12_s12/I3 |
4.151 | 0.498 | tINS | RR | 2 | R13C19[3][A] | u_extr/buf_ra_12_s12/F |
4.311 | 0.160 | tNET | RR | 1 | R14C19[3][B] | u_extr/buf_ra_c_12_s1/I0 |
4.832 | 0.521 | tINS | RR | 12 | R14C19[3][B] | u_extr/buf_ra_c_12_s1/F |
7.080 | 2.248 | tNET | RR | 1 | BSRAM_R10[10] | u_extr/mem_data_mem_data_0_11_s/ADB[13] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.368 | 7.368 | active clock edge time | ||||
7.368 | 0.000 | lvds_pclk | ||||
7.368 | 0.000 | tCL | RR | 165 | PLL_B | u_pll_50m/PLLA_inst/CLKOUT1 |
8.752 | 1.384 | tNET | RR | 1 | BSRAM_R10[10] | u_extr/mem_data_mem_data_0_11_s/CLKB |
8.718 | -0.035 | tSu | 1 | BSRAM_R10[10] | u_extr/mem_data_mem_data_0_11_s |
Path Statistics:
Clock Skew | -0.014 |
Setup Relationship | 7.368 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.398, 100.000% |
Arrival Data Path Delay | cell: 1.540, 27.107%; route: 3.759, 66.161%; tC2Q: 0.382, 6.733% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.384, 100.000% |
Path25
Path Summary:
Slack | 1.648 |
Data Arrival Time | 7.080 |
Data Required Time | 8.727 |
From | u_extr/buf_ra_0_s0 |
To | u_extr/mem_data_mem_data_0_8_s |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_B | u_pll_50m/PLLA_inst/CLKOUT1 |
1.372 | 1.372 | tNET | RR | 1 | R14C20[0][B] | u_extr/buf_ra_0_s0/CLK |
1.740 | 0.368 | tC2Q | RF | 8 | R14C20[0][B] | u_extr/buf_ra_0_s0/Q |
2.233 | 0.494 | tNET | FF | 1 | R13C24[3][B] | u_extr/n882_s4/I0 |
2.731 | 0.498 | tINS | FR | 5 | R13C24[3][B] | u_extr/n882_s4/F |
3.086 | 0.355 | tNET | RR | 1 | R14C23[3][B] | u_extr/n879_s4/I3 |
3.583 | 0.498 | tINS | RR | 5 | R14C23[3][B] | u_extr/n879_s4/F |
3.783 | 0.200 | tNET | RR | 1 | R14C21[3][A] | u_extr/n878_s4/I1 |
4.281 | 0.498 | tINS | RR | 1 | R14C21[3][A] | u_extr/n878_s4/F |
4.283 | 0.003 | tNET | RR | 1 | R14C21[2][B] | u_extr/n876_s2/I2 |
4.745 | 0.461 | tINS | RR | 3 | R14C21[2][B] | u_extr/n876_s2/F |
5.132 | 0.387 | tNET | RR | 1 | R13C23[2][B] | u_extr/buf_ra_c_10_s1/I1 |
5.648 | 0.516 | tINS | RR | 12 | R13C23[2][B] | u_extr/buf_ra_c_10_s1/F |
7.080 | 1.431 | tNET | RR | 1 | BSRAM_R28[7] | u_extr/mem_data_mem_data_0_8_s/ADB[11] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.368 | 7.368 | active clock edge time | ||||
7.368 | 0.000 | lvds_pclk | ||||
7.368 | 0.000 | tCL | RR | 165 | PLL_B | u_pll_50m/PLLA_inst/CLKOUT1 |
8.762 | 1.393 | tNET | RR | 1 | BSRAM_R28[7] | u_extr/mem_data_mem_data_0_8_s/CLKB |
8.727 | -0.035 | tSu | 1 | BSRAM_R28[7] | u_extr/mem_data_mem_data_0_8_s |
Path Statistics:
Clock Skew | 0.021 |
Setup Relationship | 7.368 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.372, 100.000% |
Arrival Data Path Delay | cell: 2.470, 43.276%; route: 2.870, 50.285%; tC2Q: 0.368, 6.439% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.393, 100.000% |
Hold Analysis Report
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 0.175 |
Data Arrival Time | 0.793 |
Data Required Time | 0.618 |
From | u_b2p/u_b2p_inst/rBufD_40_s1 |
To | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_1_s |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 598 | - | u_dphy_rx/mipi_dphy_inst/RX_CLK_O |
0.376 | 0.376 | tNET | RR | 1 | R8C40[0][A] | u_b2p/u_b2p_inst/rBufD_40_s1/CLK |
0.556 | 0.180 | tC2Q | RR | 1 | R8C40[0][A] | u_b2p/u_b2p_inst/rBufD_40_s1/Q |
0.793 | 0.236 | tNET | RR | 1 | BSRAM_R10[12] | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_1_s/DI[8] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 598 | - | u_dphy_rx/mipi_dphy_inst/RX_CLK_O |
0.369 | 0.369 | tNET | RR | 1 | BSRAM_R10[12] | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_1_s/CLKA |
0.618 | 0.249 | tHld | 1 | BSRAM_R10[12] | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_1_s |
Path Statistics:
Clock Skew | -0.008 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.376, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.236, 56.757%; tC2Q: 0.180, 43.243% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.369, 100.000% |
Path2
Path Summary:
Slack | 0.175 |
Data Arrival Time | 0.793 |
Data Required Time | 0.618 |
From | u_b2p/u_b2p_inst/rBufD_32_s1 |
To | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_1_s |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 598 | - | u_dphy_rx/mipi_dphy_inst/RX_CLK_O |
0.376 | 0.376 | tNET | RR | 1 | R8C40[0][B] | u_b2p/u_b2p_inst/rBufD_32_s1/CLK |
0.556 | 0.180 | tC2Q | RR | 1 | R8C40[0][B] | u_b2p/u_b2p_inst/rBufD_32_s1/Q |
0.793 | 0.236 | tNET | RR | 1 | BSRAM_R10[12] | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_1_s/DI[0] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 598 | - | u_dphy_rx/mipi_dphy_inst/RX_CLK_O |
0.369 | 0.369 | tNET | RR | 1 | BSRAM_R10[12] | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_1_s/CLKA |
0.618 | 0.249 | tHld | 1 | BSRAM_R10[12] | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_1_s |
Path Statistics:
Clock Skew | -0.008 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.376, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.236, 56.757%; tC2Q: 0.180, 43.243% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.369, 100.000% |
Path3
Path Summary:
Slack | 0.176 |
Data Arrival Time | 0.799 |
Data Required Time | 0.623 |
From | u_b2p/u_b2p_inst/rBufD_5_s1 |
To | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 598 | - | u_dphy_rx/mipi_dphy_inst/RX_CLK_O |
0.370 | 0.370 | tNET | RR | 1 | R9C36[1][A] | u_b2p/u_b2p_inst/rBufD_5_s1/CLK |
0.550 | 0.180 | tC2Q | RR | 1 | R9C36[1][A] | u_b2p/u_b2p_inst/rBufD_5_s1/Q |
0.799 | 0.249 | tNET | RR | 1 | BSRAM_R10[11] | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s/DI[5] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 598 | - | u_dphy_rx/mipi_dphy_inst/RX_CLK_O |
0.374 | 0.374 | tNET | RR | 1 | BSRAM_R10[11] | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s/CLKA |
0.623 | 0.249 | tHld | 1 | BSRAM_R10[11] | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s |
Path Statistics:
Clock Skew | 0.004 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.370, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.249, 58.017%; tC2Q: 0.180, 41.983% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.374, 100.000% |
Path4
Path Summary:
Slack | 0.190 |
Data Arrival Time | 0.812 |
Data Required Time | 0.623 |
From | u_b2p/u_b2p_inst/rBufD_0_s1 |
To | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 598 | - | u_dphy_rx/mipi_dphy_inst/RX_CLK_O |
0.376 | 0.376 | tNET | RR | 1 | R8C36[1][A] | u_b2p/u_b2p_inst/rBufD_0_s1/CLK |
0.556 | 0.180 | tC2Q | RR | 1 | R8C36[1][A] | u_b2p/u_b2p_inst/rBufD_0_s1/Q |
0.812 | 0.256 | tNET | RR | 1 | BSRAM_R10[11] | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s/DI[0] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 598 | - | u_dphy_rx/mipi_dphy_inst/RX_CLK_O |
0.374 | 0.374 | tNET | RR | 1 | BSRAM_R10[11] | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s/CLKA |
0.623 | 0.249 | tHld | 1 | BSRAM_R10[11] | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s |
Path Statistics:
Clock Skew | -0.002 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.376, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.256, 58.739%; tC2Q: 0.180, 41.261% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.374, 100.000% |
Path5
Path Summary:
Slack | 0.198 |
Data Arrival Time | 2.855 |
Data Required Time | 2.656 |
From | gw_gao_inst_0/u_la0_top/address_counter_1_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Launch Clk | tck_pad_i:[R] |
Latch Clk | tck_pad_i:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
0.675 | 0.675 | tINS | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
1.351 | 0.675 | tINS | RR | 240 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
2.545 | 1.194 | tNET | RR | 1 | R27C33[2][A] | gw_gao_inst_0/u_la0_top/address_counter_1_s0/CLK |
2.725 | 0.180 | tC2Q | RR | 8 | R27C33[2][A] | gw_gao_inst_0/u_la0_top/address_counter_1_s0/Q |
2.855 | 0.130 | tNET | RR | 1 | BSRAM_R28[9] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/ADB[4] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
0.675 | 0.675 | tINS | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
1.351 | 0.675 | tINS | RR | 240 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
2.538 | 1.187 | tNET | RR | 1 | BSRAM_R28[9] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKB |
2.656 | 0.118 | tHld | 1 | BSRAM_R28[9] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Path Statistics:
Clock Skew | -0.006 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 1.351, 53.090%; route: 1.194, 46.910% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.130, 41.935%; tC2Q: 0.180, 58.065% |
Required Clock Path Delay | cell: 1.351, 53.220%; route: 1.187, 46.780% |
Path6
Path Summary:
Slack | 0.204 |
Data Arrival Time | 0.895 |
Data Required Time | 0.691 |
From | u_extr/o_hs_reg_s0 |
To | u_lvds_tx_left/LVDS_71_Tx/u_ODDR71_B2 |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_B | u_pll_50m/PLLA_inst/CLKOUT1 |
0.598 | 0.598 | tNET | RR | 1 | R2C15[0][B] | u_extr/o_hs_reg_s0/CLK |
0.778 | 0.180 | tC2Q | RR | 1 | R2C15[0][B] | u_extr/o_hs_reg_s0/Q |
0.895 | 0.116 | tNET | RR | 1 | IOT15[A] | u_lvds_tx_left/LVDS_71_Tx/u_ODDR71_B2/D2 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_B | u_pll_50m/PLLA_inst/CLKOUT1 |
0.596 | 0.596 | tNET | RR | 1 | IOT15[A] | u_lvds_tx_left/LVDS_71_Tx/u_ODDR71_B2/PCLK |
0.691 | 0.095 | tHld | 1 | IOT15[A] | u_lvds_tx_left/LVDS_71_Tx/u_ODDR71_B2 |
Path Statistics:
Clock Skew | -0.003 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.598, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.116, 39.241%; tC2Q: 0.180, 60.759% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.596, 100.000% |
Path7
Path Summary:
Slack | 0.207 |
Data Arrival Time | 0.892 |
Data Required Time | 0.686 |
From | u_lvds_tx_left/LVDS_71_Tx/scuba_vhi_s0 |
To | u_lvds_tx_left/LVDS_71_Tx/u_ODDR71_C |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_B | u_pll_50m/PLLA_inst/CLKOUT1 |
0.588 | 0.588 | tNET | RR | 1 | R2C17[0][A] | u_lvds_tx_left/LVDS_71_Tx/scuba_vhi_s0/CLK |
0.768 | 0.180 | tC2Q | RR | 4 | R2C17[0][A] | u_lvds_tx_left/LVDS_71_Tx/scuba_vhi_s0/Q |
0.892 | 0.124 | tNET | RR | 1 | IOT17[A] | u_lvds_tx_left/LVDS_71_Tx/u_ODDR71_C/D6 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_B | u_pll_50m/PLLA_inst/CLKOUT1 |
0.591 | 0.591 | tNET | RR | 1 | IOT17[A] | u_lvds_tx_left/LVDS_71_Tx/u_ODDR71_C/PCLK |
0.686 | 0.095 | tHld | 1 | IOT17[A] | u_lvds_tx_left/LVDS_71_Tx/u_ODDR71_C |
Path Statistics:
Clock Skew | 0.002 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.588, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.124, 40.741%; tC2Q: 0.180, 59.259% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.591, 100.000% |
Path8
Path Summary:
Slack | 0.209 |
Data Arrival Time | 0.895 |
Data Required Time | 0.686 |
From | u_lvds_tx_left/LVDS_71_Tx/scuba_vhi_s0 |
To | u_lvds_tx_left/LVDS_71_Tx/u_ODDR71_C |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_B | u_pll_50m/PLLA_inst/CLKOUT1 |
0.588 | 0.588 | tNET | RR | 1 | R2C17[0][A] | u_lvds_tx_left/LVDS_71_Tx/scuba_vhi_s0/CLK |
0.768 | 0.180 | tC2Q | RR | 4 | R2C17[0][A] | u_lvds_tx_left/LVDS_71_Tx/scuba_vhi_s0/Q |
0.895 | 0.126 | tNET | RR | 1 | IOT17[A] | u_lvds_tx_left/LVDS_71_Tx/u_ODDR71_C/D0 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_B | u_pll_50m/PLLA_inst/CLKOUT1 |
0.591 | 0.591 | tNET | RR | 1 | IOT17[A] | u_lvds_tx_left/LVDS_71_Tx/u_ODDR71_C/PCLK |
0.686 | 0.095 | tHld | 1 | IOT17[A] | u_lvds_tx_left/LVDS_71_Tx/u_ODDR71_C |
Path Statistics:
Clock Skew | 0.002 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.588, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.126, 41.224%; tC2Q: 0.180, 58.776% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.591, 100.000% |
Path9
Path Summary:
Slack | 0.212 |
Data Arrival Time | 0.902 |
Data Required Time | 0.691 |
From | u_extr/o_rgb_reg_4_s0 |
To | u_lvds_tx_left/LVDS_71_Tx/u_ODDR71_B0 |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_B | u_pll_50m/PLLA_inst/CLKOUT1 |
0.598 | 0.598 | tNET | RR | 1 | R2C23[1][A] | u_extr/o_rgb_reg_4_s0/CLK |
0.778 | 0.180 | tC2Q | RR | 1 | R2C23[1][A] | u_extr/o_rgb_reg_4_s0/Q |
0.902 | 0.124 | tNET | RR | 1 | IOT23[A] | u_lvds_tx_left/LVDS_71_Tx/u_ODDR71_B0/D4 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_B | u_pll_50m/PLLA_inst/CLKOUT1 |
0.596 | 0.596 | tNET | RR | 1 | IOT23[A] | u_lvds_tx_left/LVDS_71_Tx/u_ODDR71_B0/PCLK |
0.691 | 0.095 | tHld | 1 | IOT23[A] | u_lvds_tx_left/LVDS_71_Tx/u_ODDR71_B0 |
Path Statistics:
Clock Skew | -0.003 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.598, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.124, 40.741%; tC2Q: 0.180, 59.259% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.596, 100.000% |
Path10
Path Summary:
Slack | 0.216 |
Data Arrival Time | 0.895 |
Data Required Time | 0.679 |
From | u_extr/o_rgb_reg_3_s0 |
To | u_lvds_tx_left/LVDS_71_Tx/u_ODDR71_B0 |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_B | u_pll_50m/PLLA_inst/CLKOUT1 |
0.598 | 0.598 | tNET | RR | 1 | R2C23[1][B] | u_extr/o_rgb_reg_3_s0/CLK |
0.778 | 0.180 | tC2Q | RR | 1 | R2C23[1][B] | u_extr/o_rgb_reg_3_s0/Q |
0.895 | 0.116 | tNET | RR | 1 | IOT23[A] | u_lvds_tx_left/LVDS_71_Tx/u_ODDR71_B0/D5 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_B | u_pll_50m/PLLA_inst/CLKOUT1 |
0.596 | 0.596 | tNET | RR | 1 | IOT23[A] | u_lvds_tx_left/LVDS_71_Tx/u_ODDR71_B0/PCLK |
0.679 | 0.083 | tHld | 1 | IOT23[A] | u_lvds_tx_left/LVDS_71_Tx/u_ODDR71_B0 |
Path Statistics:
Clock Skew | -0.003 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.598, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.116, 39.241%; tC2Q: 0.180, 60.759% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.596, 100.000% |
Path11
Path Summary:
Slack | 0.216 |
Data Arrival Time | 0.895 |
Data Required Time | 0.679 |
From | u_extr/o_rgb_reg_18_s0 |
To | u_lvds_tx_left/LVDS_71_Tx/u_ODDR71_B1 |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_B | u_pll_50m/PLLA_inst/CLKOUT1 |
0.598 | 0.598 | tNET | RR | 1 | R2C19[0][A] | u_extr/o_rgb_reg_18_s0/CLK |
0.778 | 0.180 | tC2Q | RR | 1 | R2C19[0][A] | u_extr/o_rgb_reg_18_s0/Q |
0.895 | 0.116 | tNET | RR | 1 | IOT19[A] | u_lvds_tx_left/LVDS_71_Tx/u_ODDR71_B1/D1 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_B | u_pll_50m/PLLA_inst/CLKOUT1 |
0.596 | 0.596 | tNET | RR | 1 | IOT19[A] | u_lvds_tx_left/LVDS_71_Tx/u_ODDR71_B1/PCLK |
0.679 | 0.083 | tHld | 1 | IOT19[A] | u_lvds_tx_left/LVDS_71_Tx/u_ODDR71_B1 |
Path Statistics:
Clock Skew | -0.003 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.598, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.116, 39.241%; tC2Q: 0.180, 60.759% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.596, 100.000% |
Path12
Path Summary:
Slack | 0.219 |
Data Arrival Time | 0.892 |
Data Required Time | 0.674 |
From | u_lvds_tx_left/LVDS_71_Tx/scuba_vhi_s0 |
To | u_lvds_tx_left/LVDS_71_Tx/u_ODDR71_C |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_B | u_pll_50m/PLLA_inst/CLKOUT1 |
0.588 | 0.588 | tNET | RR | 1 | R2C17[0][A] | u_lvds_tx_left/LVDS_71_Tx/scuba_vhi_s0/CLK |
0.768 | 0.180 | tC2Q | RR | 4 | R2C17[0][A] | u_lvds_tx_left/LVDS_71_Tx/scuba_vhi_s0/Q |
0.892 | 0.124 | tNET | RR | 1 | IOT17[A] | u_lvds_tx_left/LVDS_71_Tx/u_ODDR71_C/D1 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_B | u_pll_50m/PLLA_inst/CLKOUT1 |
0.591 | 0.591 | tNET | RR | 1 | IOT17[A] | u_lvds_tx_left/LVDS_71_Tx/u_ODDR71_C/PCLK |
0.674 | 0.083 | tHld | 1 | IOT17[A] | u_lvds_tx_left/LVDS_71_Tx/u_ODDR71_C |
Path Statistics:
Clock Skew | 0.002 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.588, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.124, 40.741%; tC2Q: 0.180, 59.259% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.591, 100.000% |
Path13
Path Summary:
Slack | 0.221 |
Data Arrival Time | 0.895 |
Data Required Time | 0.674 |
From | u_lvds_tx_left/LVDS_71_Tx/scuba_vhi_s0 |
To | u_lvds_tx_left/LVDS_71_Tx/u_ODDR71_C |
Launch Clk | lvds_pclk:[R] |
Latch Clk | lvds_pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_B | u_pll_50m/PLLA_inst/CLKOUT1 |
0.588 | 0.588 | tNET | RR | 1 | R2C17[0][A] | u_lvds_tx_left/LVDS_71_Tx/scuba_vhi_s0/CLK |
0.768 | 0.180 | tC2Q | RR | 4 | R2C17[0][A] | u_lvds_tx_left/LVDS_71_Tx/scuba_vhi_s0/Q |
0.895 | 0.126 | tNET | RR | 1 | IOT17[A] | u_lvds_tx_left/LVDS_71_Tx/u_ODDR71_C/D5 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | lvds_pclk | ||||
0.000 | 0.000 | tCL | RR | 165 | PLL_B | u_pll_50m/PLLA_inst/CLKOUT1 |
0.591 | 0.591 | tNET | RR | 1 | IOT17[A] | u_lvds_tx_left/LVDS_71_Tx/u_ODDR71_C/PCLK |
0.674 | 0.083 | tHld | 1 | IOT17[A] | u_lvds_tx_left/LVDS_71_Tx/u_ODDR71_C |
Path Statistics:
Clock Skew | 0.002 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.588, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.126, 41.224%; tC2Q: 0.180, 58.776% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.591, 100.000% |
Path14
Path Summary:
Slack | 0.231 |
Data Arrival Time | 0.854 |
Data Required Time | 0.623 |
From | u_b2p/u_b2p_inst/rBufD_6_s1 |
To | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 598 | - | u_dphy_rx/mipi_dphy_inst/RX_CLK_O |
0.375 | 0.375 | tNET | RR | 1 | R9C37[0][A] | u_b2p/u_b2p_inst/rBufD_6_s1/CLK |
0.555 | 0.180 | tC2Q | RR | 1 | R9C37[0][A] | u_b2p/u_b2p_inst/rBufD_6_s1/Q |
0.854 | 0.299 | tNET | RR | 1 | BSRAM_R10[11] | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s/DI[6] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 598 | - | u_dphy_rx/mipi_dphy_inst/RX_CLK_O |
0.374 | 0.374 | tNET | RR | 1 | BSRAM_R10[11] | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s/CLKA |
0.623 | 0.249 | tHld | 1 | BSRAM_R10[11] | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s |
Path Statistics:
Clock Skew | -0.001 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.299, 62.402%; tC2Q: 0.180, 37.598% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.374, 100.000% |
Path15
Path Summary:
Slack | 0.238 |
Data Arrival Time | 0.861 |
Data Required Time | 0.623 |
From | u_b2p/u_b2p_inst/rBufD_21_s1 |
To | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 598 | - | u_dphy_rx/mipi_dphy_inst/RX_CLK_O |
0.375 | 0.375 | tNET | RR | 1 | R9C37[1][A] | u_b2p/u_b2p_inst/rBufD_21_s1/CLK |
0.555 | 0.180 | tC2Q | RR | 1 | R9C37[1][A] | u_b2p/u_b2p_inst/rBufD_21_s1/Q |
0.861 | 0.306 | tNET | RR | 1 | BSRAM_R10[11] | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s/DI[21] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 598 | - | u_dphy_rx/mipi_dphy_inst/RX_CLK_O |
0.374 | 0.374 | tNET | RR | 1 | BSRAM_R10[11] | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s/CLKA |
0.623 | 0.249 | tHld | 1 | BSRAM_R10[11] | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s |
Path Statistics:
Clock Skew | -0.001 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.306, 62.982%; tC2Q: 0.180, 37.018% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.374, 100.000% |
Path16
Path Summary:
Slack | 0.251 |
Data Arrival Time | 0.874 |
Data Required Time | 0.623 |
From | u_b2p/u_b2p_inst/rBufD_24_s1 |
To | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 598 | - | u_dphy_rx/mipi_dphy_inst/RX_CLK_O |
0.376 | 0.376 | tNET | RR | 1 | R8C32[1][A] | u_b2p/u_b2p_inst/rBufD_24_s1/CLK |
0.556 | 0.180 | tC2Q | RR | 1 | R8C32[1][A] | u_b2p/u_b2p_inst/rBufD_24_s1/Q |
0.874 | 0.317 | tNET | RR | 1 | BSRAM_R10[11] | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s/DI[24] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 598 | - | u_dphy_rx/mipi_dphy_inst/RX_CLK_O |
0.374 | 0.374 | tNET | RR | 1 | BSRAM_R10[11] | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s/CLKA |
0.623 | 0.249 | tHld | 1 | BSRAM_R10[11] | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s |
Path Statistics:
Clock Skew | -0.002 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.376, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.317, 63.819%; tC2Q: 0.180, 36.181% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.374, 100.000% |
Path17
Path Summary:
Slack | 0.263 |
Data Arrival Time | 0.886 |
Data Required Time | 0.623 |
From | u_extr/buf_wd_18_s0 |
To | u_extr/mem_data_mem_data_0_9_s |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
0.368 | 0.368 | tNET | RR | 1 | R11C29[0][A] | u_extr/buf_wd_18_s0/CLK |
0.548 | 0.180 | tC2Q | RR | 1 | R11C29[0][A] | u_extr/buf_wd_18_s0/Q |
0.886 | 0.339 | tNET | RR | 1 | BSRAM_R10[8] | u_extr/mem_data_mem_data_0_9_s/DI[0] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
0.374 | 0.374 | tNET | RR | 1 | BSRAM_R10[8] | u_extr/mem_data_mem_data_0_9_s/CLKA |
0.623 | 0.249 | tHld | 1 | BSRAM_R10[8] | u_extr/mem_data_mem_data_0_9_s |
Path Statistics:
Clock Skew | 0.006 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.368, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.339, 65.301%; tC2Q: 0.180, 34.699% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.374, 100.000% |
Path18
Path Summary:
Slack | 0.264 |
Data Arrival Time | 0.881 |
Data Required Time | 0.618 |
From | u_extr/buf_wd_14_s0 |
To | u_extr/mem_data_mem_data_0_7_s |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
0.363 | 0.363 | tNET | RR | 1 | R11C26[0][B] | u_extr/buf_wd_14_s0/CLK |
0.543 | 0.180 | tC2Q | RR | 1 | R11C26[0][B] | u_extr/buf_wd_14_s0/Q |
0.881 | 0.339 | tNET | RR | 1 | BSRAM_R10[7] | u_extr/mem_data_mem_data_0_7_s/DI[0] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
0.369 | 0.369 | tNET | RR | 1 | BSRAM_R10[7] | u_extr/mem_data_mem_data_0_7_s/CLKA |
0.618 | 0.249 | tHld | 1 | BSRAM_R10[7] | u_extr/mem_data_mem_data_0_7_s |
Path Statistics:
Clock Skew | 0.006 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.363, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.339, 65.301%; tC2Q: 0.180, 34.699% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.369, 100.000% |
Path19
Path Summary:
Slack | 0.264 |
Data Arrival Time | 0.876 |
Data Required Time | 0.613 |
From | u_extr/buf_wd_10_s0 |
To | u_extr/mem_data_mem_data_0_5_s |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
0.358 | 0.358 | tNET | RR | 1 | R11C23[1][B] | u_extr/buf_wd_10_s0/CLK |
0.538 | 0.180 | tC2Q | RR | 1 | R11C23[1][B] | u_extr/buf_wd_10_s0/Q |
0.876 | 0.339 | tNET | RR | 1 | BSRAM_R10[6] | u_extr/mem_data_mem_data_0_5_s/DI[0] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
0.364 | 0.364 | tNET | RR | 1 | BSRAM_R10[6] | u_extr/mem_data_mem_data_0_5_s/CLKA |
0.613 | 0.249 | tHld | 1 | BSRAM_R10[6] | u_extr/mem_data_mem_data_0_5_s |
Path Statistics:
Clock Skew | 0.006 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.358, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.339, 65.301%; tC2Q: 0.180, 34.699% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.364, 100.000% |
Path20
Path Summary:
Slack | 0.265 |
Data Arrival Time | 0.888 |
Data Required Time | 0.623 |
From | u_extr/buf_wd_19_s0 |
To | u_extr/mem_data_mem_data_0_9_s |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
0.368 | 0.368 | tNET | RR | 1 | R11C29[1][A] | u_extr/buf_wd_19_s0/CLK |
0.548 | 0.180 | tC2Q | RR | 1 | R11C29[1][A] | u_extr/buf_wd_19_s0/Q |
0.888 | 0.340 | tNET | RR | 1 | BSRAM_R10[8] | u_extr/mem_data_mem_data_0_9_s/DI[1] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
0.374 | 0.374 | tNET | RR | 1 | BSRAM_R10[8] | u_extr/mem_data_mem_data_0_9_s/CLKA |
0.623 | 0.249 | tHld | 1 | BSRAM_R10[8] | u_extr/mem_data_mem_data_0_9_s |
Path Statistics:
Clock Skew | 0.006 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.368, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.340, 65.385%; tC2Q: 0.180, 34.615% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.374, 100.000% |
Path21
Path Summary:
Slack | 0.265 |
Data Arrival Time | 0.883 |
Data Required Time | 0.618 |
From | u_extr/buf_wd_15_s0 |
To | u_extr/mem_data_mem_data_0_7_s |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
0.363 | 0.363 | tNET | RR | 1 | R11C26[0][A] | u_extr/buf_wd_15_s0/CLK |
0.543 | 0.180 | tC2Q | RR | 1 | R11C26[0][A] | u_extr/buf_wd_15_s0/Q |
0.883 | 0.340 | tNET | RR | 1 | BSRAM_R10[7] | u_extr/mem_data_mem_data_0_7_s/DI[1] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
0.369 | 0.369 | tNET | RR | 1 | BSRAM_R10[7] | u_extr/mem_data_mem_data_0_7_s/CLKA |
0.618 | 0.249 | tHld | 1 | BSRAM_R10[7] | u_extr/mem_data_mem_data_0_7_s |
Path Statistics:
Clock Skew | 0.006 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.363, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.340, 65.385%; tC2Q: 0.180, 34.615% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.369, 100.000% |
Path22
Path Summary:
Slack | 0.265 |
Data Arrival Time | 0.878 |
Data Required Time | 0.613 |
From | u_extr/buf_wd_11_s0 |
To | u_extr/mem_data_mem_data_0_5_s |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
0.358 | 0.358 | tNET | RR | 1 | R11C23[1][A] | u_extr/buf_wd_11_s0/CLK |
0.538 | 0.180 | tC2Q | RR | 1 | R11C23[1][A] | u_extr/buf_wd_11_s0/Q |
0.878 | 0.340 | tNET | RR | 1 | BSRAM_R10[6] | u_extr/mem_data_mem_data_0_5_s/DI[1] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
0.364 | 0.364 | tNET | RR | 1 | BSRAM_R10[6] | u_extr/mem_data_mem_data_0_5_s/CLKA |
0.613 | 0.249 | tHld | 1 | BSRAM_R10[6] | u_extr/mem_data_mem_data_0_5_s |
Path Statistics:
Clock Skew | 0.006 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.358, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.340, 65.385%; tC2Q: 0.180, 34.615% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.364, 100.000% |
Path23
Path Summary:
Slack | 0.266 |
Data Arrival Time | 0.883 |
Data Required Time | 0.618 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_15_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
0.398 | 0.398 | tNET | RR | 1 | R20C30[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_15_s0/CLK |
0.578 | 0.180 | tC2Q | RR | 1 | R20C30[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_15_s0/Q |
0.883 | 0.305 | tNET | RR | 1 | BSRAM_R28[9] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[7] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
0.369 | 0.369 | tNET | RR | 1 | BSRAM_R28[9] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA |
0.618 | 0.249 | tHld | 1 | BSRAM_R28[9] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Path Statistics:
Clock Skew | -0.030 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.398, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.305, 62.887%; tC2Q: 0.180, 37.113% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.369, 100.000% |
Path24
Path Summary:
Slack | 0.294 |
Data Arrival Time | 0.911 |
Data Required Time | 0.618 |
From | u_b2p/u_b2p_inst/rBufD_45_s1 |
To | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_1_s |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 598 | - | u_dphy_rx/mipi_dphy_inst/RX_CLK_O |
0.375 | 0.375 | tNET | RR | 1 | R9C39[2][A] | u_b2p/u_b2p_inst/rBufD_45_s1/CLK |
0.555 | 0.180 | tC2Q | RR | 1 | R9C39[2][A] | u_b2p/u_b2p_inst/rBufD_45_s1/Q |
0.911 | 0.356 | tNET | RR | 1 | BSRAM_R10[12] | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_1_s/DI[13] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 598 | - | u_dphy_rx/mipi_dphy_inst/RX_CLK_O |
0.369 | 0.369 | tNET | RR | 1 | BSRAM_R10[12] | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_1_s/CLKA |
0.618 | 0.249 | tHld | 1 | BSRAM_R10[12] | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_1_s |
Path Statistics:
Clock Skew | -0.006 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.356, 66.434%; tC2Q: 0.180, 33.566% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.369, 100.000% |
Path25
Path Summary:
Slack | 0.295 |
Data Arrival Time | 0.918 |
Data Required Time | 0.623 |
From | u_b2p/u_b2p_inst/rBufD_31_s1 |
To | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 598 | - | u_dphy_rx/mipi_dphy_inst/RX_CLK_O |
0.370 | 0.370 | tNET | RR | 1 | R9C36[2][A] | u_b2p/u_b2p_inst/rBufD_31_s1/CLK |
0.550 | 0.180 | tC2Q | RR | 1 | R9C36[2][A] | u_b2p/u_b2p_inst/rBufD_31_s1/Q |
0.918 | 0.368 | tNET | RR | 1 | BSRAM_R10[11] | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s/DI[31] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 598 | - | u_dphy_rx/mipi_dphy_inst/RX_CLK_O |
0.374 | 0.374 | tNET | RR | 1 | BSRAM_R10[11] | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s/CLKA |
0.623 | 0.249 | tHld | 1 | BSRAM_R10[11] | u_b2p/u_b2p_inst/u_mid_fifo/u_dpram/mBsram_mBsram_0_0_s |
Path Statistics:
Clock Skew | 0.004 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.370, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.368, 67.123%; tC2Q: 0.180, 32.877% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.374, 100.000% |
Recovery Analysis Report
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 1.148 |
Data Arrival Time | 6.548 |
Data Required Time | 7.696 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
4.433 | 0.862 | tNET | FF | 1 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
4.876 | 0.442 | tC2Q | FF | 61 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.548 | 1.673 | tNET | FF | 1 | R21C32[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | pixel_clk | ||||
7.143 | 0.000 | tCL | RR | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
8.044 | 0.901 | tNET | RR | 1 | R21C32[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK |
7.696 | -0.347 | tSu | 1 | R21C32[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1 |
Path Statistics:
Clock Skew | 0.039 |
Setup Relationship | 3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.862, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.673, 79.078%; tC2Q: 0.442, 20.922% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.901, 100.000% |
Path2
Path Summary:
Slack | 1.518 |
Data Arrival Time | 6.181 |
Data Required Time | 7.699 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
4.433 | 0.862 | tNET | FF | 1 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
4.876 | 0.442 | tC2Q | FF | 61 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.181 | 1.305 | tNET | FF | 1 | R20C32[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | pixel_clk | ||||
7.143 | 0.000 | tCL | RR | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
8.046 | 0.903 | tNET | RR | 1 | R20C32[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK |
7.699 | -0.347 | tSu | 1 | R20C32[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1 |
Path Statistics:
Clock Skew | 0.041 |
Setup Relationship | 3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.862, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.305, 74.678%; tC2Q: 0.442, 25.322% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.903, 100.000% |
Path3
Path Summary:
Slack | 1.518 |
Data Arrival Time | 6.181 |
Data Required Time | 7.699 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
4.433 | 0.862 | tNET | FF | 1 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
4.876 | 0.442 | tC2Q | FF | 61 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.181 | 1.305 | tNET | FF | 1 | R20C32[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | pixel_clk | ||||
7.143 | 0.000 | tCL | RR | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
8.046 | 0.903 | tNET | RR | 1 | R20C32[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK |
7.699 | -0.347 | tSu | 1 | R20C32[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1 |
Path Statistics:
Clock Skew | 0.041 |
Setup Relationship | 3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.862, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.305, 74.678%; tC2Q: 0.442, 25.322% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.903, 100.000% |
Path4
Path Summary:
Slack | 1.518 |
Data Arrival Time | 6.181 |
Data Required Time | 7.699 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
4.433 | 0.862 | tNET | FF | 1 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
4.876 | 0.442 | tC2Q | FF | 61 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.181 | 1.305 | tNET | FF | 1 | R20C32[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | pixel_clk | ||||
7.143 | 0.000 | tCL | RR | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
8.046 | 0.903 | tNET | RR | 1 | R20C32[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK |
7.699 | -0.347 | tSu | 1 | R20C32[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1 |
Path Statistics:
Clock Skew | 0.041 |
Setup Relationship | 3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.862, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.305, 74.678%; tC2Q: 0.442, 25.322% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.903, 100.000% |
Path5
Path Summary:
Slack | 1.518 |
Data Arrival Time | 6.181 |
Data Required Time | 7.699 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
4.433 | 0.862 | tNET | FF | 1 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
4.876 | 0.442 | tC2Q | FF | 61 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.181 | 1.305 | tNET | FF | 1 | R20C32[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | pixel_clk | ||||
7.143 | 0.000 | tCL | RR | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
8.046 | 0.903 | tNET | RR | 1 | R20C32[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK |
7.699 | -0.347 | tSu | 1 | R20C32[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1 |
Path Statistics:
Clock Skew | 0.041 |
Setup Relationship | 3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.862, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.305, 74.678%; tC2Q: 0.442, 25.322% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.903, 100.000% |
Path6
Path Summary:
Slack | 1.527 |
Data Arrival Time | 6.181 |
Data Required Time | 7.708 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
4.433 | 0.862 | tNET | FF | 1 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
4.876 | 0.442 | tC2Q | FF | 61 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.181 | 1.305 | tNET | FF | 1 | R20C33[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | pixel_clk | ||||
7.143 | 0.000 | tCL | RR | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
8.056 | 0.913 | tNET | RR | 1 | R20C33[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/CLK |
7.708 | -0.347 | tSu | 1 | R20C33[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5 |
Path Statistics:
Clock Skew | 0.051 |
Setup Relationship | 3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.862, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.305, 74.678%; tC2Q: 0.442, 25.322% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.913, 100.000% |
Path7
Path Summary:
Slack | 1.527 |
Data Arrival Time | 6.181 |
Data Required Time | 7.708 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
4.433 | 0.862 | tNET | FF | 1 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
4.876 | 0.442 | tC2Q | FF | 61 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.181 | 1.305 | tNET | FF | 1 | R20C33[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | pixel_clk | ||||
7.143 | 0.000 | tCL | RR | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
8.056 | 0.913 | tNET | RR | 1 | R20C33[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK |
7.708 | -0.347 | tSu | 1 | R20C33[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1 |
Path Statistics:
Clock Skew | 0.051 |
Setup Relationship | 3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.862, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.305, 74.678%; tC2Q: 0.442, 25.322% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.913, 100.000% |
Path8
Path Summary:
Slack | 1.527 |
Data Arrival Time | 6.181 |
Data Required Time | 7.708 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
4.433 | 0.862 | tNET | FF | 1 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
4.876 | 0.442 | tC2Q | FF | 61 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.181 | 1.305 | tNET | FF | 1 | R20C33[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | pixel_clk | ||||
7.143 | 0.000 | tCL | RR | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
8.056 | 0.913 | tNET | RR | 1 | R20C33[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK |
7.708 | -0.347 | tSu | 1 | R20C33[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1 |
Path Statistics:
Clock Skew | 0.051 |
Setup Relationship | 3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.862, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.305, 74.678%; tC2Q: 0.442, 25.322% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.913, 100.000% |
Path9
Path Summary:
Slack | 1.560 |
Data Arrival Time | 6.127 |
Data Required Time | 7.687 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
4.433 | 0.862 | tNET | FF | 1 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
4.876 | 0.442 | tC2Q | FF | 61 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.127 | 1.251 | tNET | FF | 1 | R21C39[1][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | pixel_clk | ||||
7.143 | 0.000 | tCL | RR | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
8.034 | 0.891 | tNET | RR | 1 | R21C39[1][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLK |
7.687 | -0.347 | tSu | 1 | R21C39[1][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1 |
Path Statistics:
Clock Skew | 0.029 |
Setup Relationship | 3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.862, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.251, 73.875%; tC2Q: 0.442, 26.125% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.891, 100.000% |
Path10
Path Summary:
Slack | 1.560 |
Data Arrival Time | 6.127 |
Data Required Time | 7.687 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
4.433 | 0.862 | tNET | FF | 1 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
4.876 | 0.442 | tC2Q | FF | 61 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.127 | 1.251 | tNET | FF | 1 | R21C39[1][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | pixel_clk | ||||
7.143 | 0.000 | tCL | RR | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
8.034 | 0.891 | tNET | RR | 1 | R21C39[1][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLK |
7.687 | -0.347 | tSu | 1 | R21C39[1][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1 |
Path Statistics:
Clock Skew | 0.029 |
Setup Relationship | 3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.862, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.251, 73.875%; tC2Q: 0.442, 26.125% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.891, 100.000% |
Path11
Path Summary:
Slack | 1.696 |
Data Arrival Time | 5.981 |
Data Required Time | 7.677 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
4.433 | 0.862 | tNET | FF | 1 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
4.876 | 0.442 | tC2Q | FF | 61 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
5.981 | 1.105 | tNET | FF | 1 | R25C31[0][B] | gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | pixel_clk | ||||
7.143 | 0.000 | tCL | RR | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
8.024 | 0.881 | tNET | RR | 1 | R25C31[0][B] | gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLK |
7.677 | -0.347 | tSu | 1 | R25C31[0][B] | gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1 |
Path Statistics:
Clock Skew | 0.019 |
Setup Relationship | 3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.862, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.105, 71.411%; tC2Q: 0.442, 28.589% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.881, 100.000% |
Path12
Path Summary:
Slack | 1.698 |
Data Arrival Time | 5.981 |
Data Required Time | 7.679 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
4.433 | 0.862 | tNET | FF | 1 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
4.876 | 0.442 | tC2Q | FF | 61 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
5.981 | 1.105 | tNET | FF | 1 | R26C28[0][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | pixel_clk | ||||
7.143 | 0.000 | tCL | RR | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
8.026 | 0.883 | tNET | RR | 1 | R26C28[0][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLK |
7.679 | -0.347 | tSu | 1 | R26C28[0][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0 |
Path Statistics:
Clock Skew | 0.022 |
Setup Relationship | 3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.862, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.105, 71.411%; tC2Q: 0.442, 28.589% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.883, 100.000% |
Path13
Path Summary:
Slack | 1.698 |
Data Arrival Time | 5.981 |
Data Required Time | 7.679 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_0_s0 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
4.433 | 0.862 | tNET | FF | 1 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
4.876 | 0.442 | tC2Q | FF | 61 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
5.981 | 1.105 | tNET | FF | 1 | R26C28[0][B] | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | pixel_clk | ||||
7.143 | 0.000 | tCL | RR | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
8.026 | 0.883 | tNET | RR | 1 | R26C28[0][B] | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_0_s0/CLK |
7.679 | -0.347 | tSu | 1 | R26C28[0][B] | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_0_s0 |
Path Statistics:
Clock Skew | 0.022 |
Setup Relationship | 3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.862, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.105, 71.411%; tC2Q: 0.442, 28.589% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.883, 100.000% |
Path14
Path Summary:
Slack | 1.707 |
Data Arrival Time | 5.981 |
Data Required Time | 7.689 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_match_1/trig_dly_0_s0 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
4.433 | 0.862 | tNET | FF | 1 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
4.876 | 0.442 | tC2Q | FF | 61 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
5.981 | 1.105 | tNET | FF | 1 | R24C28[1][A] | gw_gao_inst_0/u_la0_top/u_ao_match_1/trig_dly_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | pixel_clk | ||||
7.143 | 0.000 | tCL | RR | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
8.036 | 0.893 | tNET | RR | 1 | R24C28[1][A] | gw_gao_inst_0/u_la0_top/u_ao_match_1/trig_dly_0_s0/CLK |
7.689 | -0.347 | tSu | 1 | R24C28[1][A] | gw_gao_inst_0/u_la0_top/u_ao_match_1/trig_dly_0_s0 |
Path Statistics:
Clock Skew | 0.031 |
Setup Relationship | 3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.862, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.105, 71.411%; tC2Q: 0.442, 28.589% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.893, 100.000% |
Path15
Path Summary:
Slack | 1.734 |
Data Arrival Time | 5.962 |
Data Required Time | 7.696 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
4.433 | 0.862 | tNET | FF | 1 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
4.876 | 0.442 | tC2Q | FF | 61 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
5.962 | 1.086 | tNET | FF | 1 | R21C36[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | pixel_clk | ||||
7.143 | 0.000 | tCL | RR | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
8.044 | 0.901 | tNET | RR | 1 | R21C36[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/CLK |
7.696 | -0.347 | tSu | 1 | R21C36[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1 |
Path Statistics:
Clock Skew | 0.039 |
Setup Relationship | 3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.862, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.086, 71.055%; tC2Q: 0.442, 28.945% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.901, 100.000% |
Path16
Path Summary:
Slack | 1.737 |
Data Arrival Time | 5.962 |
Data Required Time | 7.699 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
4.433 | 0.862 | tNET | FF | 1 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
4.876 | 0.442 | tC2Q | FF | 61 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
5.962 | 1.086 | tNET | FF | 1 | R20C36[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | pixel_clk | ||||
7.143 | 0.000 | tCL | RR | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
8.046 | 0.903 | tNET | RR | 1 | R20C36[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLK |
7.699 | -0.347 | tSu | 1 | R20C36[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1 |
Path Statistics:
Clock Skew | 0.041 |
Setup Relationship | 3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.862, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.086, 71.055%; tC2Q: 0.442, 28.945% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.903, 100.000% |
Path17
Path Summary:
Slack | 1.737 |
Data Arrival Time | 5.962 |
Data Required Time | 7.699 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
4.433 | 0.862 | tNET | FF | 1 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
4.876 | 0.442 | tC2Q | FF | 61 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
5.962 | 1.086 | tNET | FF | 1 | R20C36[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | pixel_clk | ||||
7.143 | 0.000 | tCL | RR | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
8.046 | 0.903 | tNET | RR | 1 | R20C36[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLK |
7.699 | -0.347 | tSu | 1 | R20C36[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1 |
Path Statistics:
Clock Skew | 0.041 |
Setup Relationship | 3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.862, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.086, 71.055%; tC2Q: 0.442, 28.945% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.903, 100.000% |
Path18
Path Summary:
Slack | 1.737 |
Data Arrival Time | 5.962 |
Data Required Time | 7.699 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
4.433 | 0.862 | tNET | FF | 1 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
4.876 | 0.442 | tC2Q | FF | 61 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
5.962 | 1.086 | tNET | FF | 1 | R20C36[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | pixel_clk | ||||
7.143 | 0.000 | tCL | RR | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
8.046 | 0.903 | tNET | RR | 1 | R20C36[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLK |
7.699 | -0.347 | tSu | 1 | R20C36[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1 |
Path Statistics:
Clock Skew | 0.041 |
Setup Relationship | 3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.862, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.086, 71.055%; tC2Q: 0.442, 28.945% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.903, 100.000% |
Path19
Path Summary:
Slack | 1.737 |
Data Arrival Time | 5.962 |
Data Required Time | 7.699 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
4.433 | 0.862 | tNET | FF | 1 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
4.876 | 0.442 | tC2Q | FF | 61 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
5.962 | 1.086 | tNET | FF | 1 | R20C36[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | pixel_clk | ||||
7.143 | 0.000 | tCL | RR | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
8.046 | 0.903 | tNET | RR | 1 | R20C36[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLK |
7.699 | -0.347 | tSu | 1 | R20C36[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1 |
Path Statistics:
Clock Skew | 0.041 |
Setup Relationship | 3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.862, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.086, 71.055%; tC2Q: 0.442, 28.945% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.903, 100.000% |
Path20
Path Summary:
Slack | 1.743 |
Data Arrival Time | 5.946 |
Data Required Time | 7.689 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
4.433 | 0.862 | tNET | FF | 1 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
4.876 | 0.442 | tC2Q | FF | 61 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
5.946 | 1.070 | tNET | FF | 1 | R20C35[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | pixel_clk | ||||
7.143 | 0.000 | tCL | RR | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
8.037 | 0.894 | tNET | RR | 1 | R20C35[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK |
7.689 | -0.347 | tSu | 1 | R20C35[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1 |
Path Statistics:
Clock Skew | 0.032 |
Setup Relationship | 3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.862, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.070, 70.744%; tC2Q: 0.442, 29.256% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.894, 100.000% |
Path21
Path Summary:
Slack | 1.743 |
Data Arrival Time | 5.946 |
Data Required Time | 7.689 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
4.433 | 0.862 | tNET | FF | 1 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
4.876 | 0.442 | tC2Q | FF | 61 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
5.946 | 1.070 | tNET | FF | 1 | R20C35[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | pixel_clk | ||||
7.143 | 0.000 | tCL | RR | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
8.037 | 0.894 | tNET | RR | 1 | R20C35[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK |
7.689 | -0.347 | tSu | 1 | R20C35[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1 |
Path Statistics:
Clock Skew | 0.032 |
Setup Relationship | 3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.862, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.070, 70.744%; tC2Q: 0.442, 29.256% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.894, 100.000% |
Path22
Path Summary:
Slack | 1.743 |
Data Arrival Time | 5.946 |
Data Required Time | 7.689 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
4.433 | 0.862 | tNET | FF | 1 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
4.876 | 0.442 | tC2Q | FF | 61 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
5.946 | 1.070 | tNET | FF | 1 | R20C35[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | pixel_clk | ||||
7.143 | 0.000 | tCL | RR | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
8.037 | 0.894 | tNET | RR | 1 | R20C35[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK |
7.689 | -0.347 | tSu | 1 | R20C35[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1 |
Path Statistics:
Clock Skew | 0.032 |
Setup Relationship | 3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.862, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.070, 70.744%; tC2Q: 0.442, 29.256% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.894, 100.000% |
Path23
Path Summary:
Slack | 1.743 |
Data Arrival Time | 5.946 |
Data Required Time | 7.689 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
4.433 | 0.862 | tNET | FF | 1 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
4.876 | 0.442 | tC2Q | FF | 61 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
5.946 | 1.070 | tNET | FF | 1 | R20C35[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | pixel_clk | ||||
7.143 | 0.000 | tCL | RR | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
8.037 | 0.894 | tNET | RR | 1 | R20C35[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/CLK |
7.689 | -0.347 | tSu | 1 | R20C35[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1 |
Path Statistics:
Clock Skew | 0.032 |
Setup Relationship | 3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.862, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.070, 70.744%; tC2Q: 0.442, 29.256% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.894, 100.000% |
Path24
Path Summary:
Slack | 1.746 |
Data Arrival Time | 5.943 |
Data Required Time | 7.689 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
4.433 | 0.862 | tNET | FF | 1 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
4.876 | 0.442 | tC2Q | FF | 61 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
5.943 | 1.067 | tNET | FF | 1 | R20C39[2][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | pixel_clk | ||||
7.143 | 0.000 | tCL | RR | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
8.037 | 0.894 | tNET | RR | 1 | R20C39[2][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLK |
7.689 | -0.347 | tSu | 1 | R20C39[2][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1 |
Path Statistics:
Clock Skew | 0.032 |
Setup Relationship | 3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.862, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.067, 70.695%; tC2Q: 0.442, 29.305% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.894, 100.000% |
Path25
Path Summary:
Slack | 1.746 |
Data Arrival Time | 5.943 |
Data Required Time | 7.689 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
4.433 | 0.862 | tNET | FF | 1 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
4.876 | 0.442 | tC2Q | FF | 61 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
5.943 | 1.067 | tNET | FF | 1 | R20C39[2][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | pixel_clk | ||||
7.143 | 0.000 | tCL | RR | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
8.037 | 0.894 | tNET | RR | 1 | R20C39[2][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLK |
7.689 | -0.347 | tSu | 1 | R20C39[2][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1 |
Path Statistics:
Clock Skew | 0.032 |
Setup Relationship | 3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.862, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.067, 70.695%; tC2Q: 0.442, 29.305% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.894, 100.000% |
Removal Analysis Report
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 4.227 |
Data Arrival Time | 4.414 |
Data Required Time | 0.187 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
3.945 | 0.374 | tNET | FF | 1 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
4.143 | 0.198 | tC2Q | FR | 61 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
4.414 | 0.271 | tNET | RR | 1 | R18C37[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
0.376 | 0.376 | tNET | RR | 1 | R18C37[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLK |
0.187 | -0.189 | tHld | 1 | R18C37[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1 |
Path Statistics:
Clock Skew | 0.002 |
Hold Relationship | -3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.374, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.271, 57.867%; tC2Q: 0.198, 42.133% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.376, 100.000% |
Path2
Path Summary:
Slack | 4.227 |
Data Arrival Time | 4.414 |
Data Required Time | 0.187 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
3.945 | 0.374 | tNET | FF | 1 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
4.143 | 0.198 | tC2Q | FR | 61 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
4.414 | 0.271 | tNET | RR | 1 | R18C37[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
0.376 | 0.376 | tNET | RR | 1 | R18C37[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLK |
0.187 | -0.189 | tHld | 1 | R18C37[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1 |
Path Statistics:
Clock Skew | 0.002 |
Hold Relationship | -3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.374, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.271, 57.867%; tC2Q: 0.198, 42.133% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.376, 100.000% |
Path3
Path Summary:
Slack | 4.227 |
Data Arrival Time | 4.414 |
Data Required Time | 0.187 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_10_s1 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
3.945 | 0.374 | tNET | FF | 1 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
4.143 | 0.198 | tC2Q | FR | 61 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
4.414 | 0.271 | tNET | RR | 1 | R18C37[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_10_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
0.376 | 0.376 | tNET | RR | 1 | R18C37[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_10_s1/CLK |
0.187 | -0.189 | tHld | 1 | R18C37[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_10_s1 |
Path Statistics:
Clock Skew | 0.002 |
Hold Relationship | -3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.374, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.271, 57.867%; tC2Q: 0.198, 42.133% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.376, 100.000% |
Path4
Path Summary:
Slack | 4.227 |
Data Arrival Time | 4.414 |
Data Required Time | 0.187 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_end_dly_s0 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
3.945 | 0.374 | tNET | FF | 1 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
4.143 | 0.198 | tC2Q | FR | 61 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
4.414 | 0.271 | tNET | RR | 1 | R18C37[0][B] | gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
0.376 | 0.376 | tNET | RR | 1 | R18C37[0][B] | gw_gao_inst_0/u_la0_top/capture_end_dly_s0/CLK |
0.187 | -0.189 | tHld | 1 | R18C37[0][B] | gw_gao_inst_0/u_la0_top/capture_end_dly_s0 |
Path Statistics:
Clock Skew | 0.002 |
Hold Relationship | -3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.374, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.271, 57.867%; tC2Q: 0.198, 42.133% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.376, 100.000% |
Path5
Path Summary:
Slack | 4.227 |
Data Arrival Time | 4.409 |
Data Required Time | 0.182 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
3.945 | 0.374 | tNET | FF | 1 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
4.143 | 0.198 | tC2Q | FR | 61 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
4.409 | 0.266 | tNET | RR | 1 | R18C38[2][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
0.371 | 0.371 | tNET | RR | 1 | R18C38[2][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLK |
0.182 | -0.189 | tHld | 1 | R18C38[2][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3 |
Path Statistics:
Clock Skew | -0.003 |
Hold Relationship | -3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.374, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.266, 57.412%; tC2Q: 0.198, 42.588% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.371, 100.000% |
Path6
Path Summary:
Slack | 4.227 |
Data Arrival Time | 4.409 |
Data Required Time | 0.182 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
3.945 | 0.374 | tNET | FF | 1 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
4.143 | 0.198 | tC2Q | FR | 61 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
4.409 | 0.266 | tNET | RR | 1 | R18C38[0][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
0.371 | 0.371 | tNET | RR | 1 | R18C38[0][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLK |
0.182 | -0.189 | tHld | 1 | R18C38[0][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1 |
Path Statistics:
Clock Skew | -0.003 |
Hold Relationship | -3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.374, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.266, 57.412%; tC2Q: 0.198, 42.588% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.371, 100.000% |
Path7
Path Summary:
Slack | 4.227 |
Data Arrival Time | 4.409 |
Data Required Time | 0.182 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
3.945 | 0.374 | tNET | FF | 1 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
4.143 | 0.198 | tC2Q | FR | 61 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
4.409 | 0.266 | tNET | RR | 1 | R18C38[1][A] | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
0.371 | 0.371 | tNET | RR | 1 | R18C38[1][A] | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLK |
0.182 | -0.189 | tHld | 1 | R18C38[1][A] | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0 |
Path Statistics:
Clock Skew | -0.003 |
Hold Relationship | -3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.374, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.266, 57.412%; tC2Q: 0.198, 42.588% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.371, 100.000% |
Path8
Path Summary:
Slack | 4.227 |
Data Arrival Time | 4.409 |
Data Required Time | 0.182 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
3.945 | 0.374 | tNET | FF | 1 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
4.143 | 0.198 | tC2Q | FR | 61 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
4.409 | 0.266 | tNET | RR | 1 | R18C38[1][B] | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
0.371 | 0.371 | tNET | RR | 1 | R18C38[1][B] | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLK |
0.182 | -0.189 | tHld | 1 | R18C38[1][B] | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0 |
Path Statistics:
Clock Skew | -0.003 |
Hold Relationship | -3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.374, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.266, 57.412%; tC2Q: 0.198, 42.588% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.371, 100.000% |
Path9
Path Summary:
Slack | 4.232 |
Data Arrival Time | 4.414 |
Data Required Time | 0.182 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
3.945 | 0.374 | tNET | FF | 1 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
4.143 | 0.198 | tC2Q | FR | 61 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
4.414 | 0.271 | tNET | RR | 1 | R18C36[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
0.371 | 0.371 | tNET | RR | 1 | R18C36[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLK |
0.182 | -0.189 | tHld | 1 | R18C36[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1 |
Path Statistics:
Clock Skew | -0.003 |
Hold Relationship | -3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.374, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.271, 57.867%; tC2Q: 0.198, 42.133% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.371, 100.000% |
Path10
Path Summary:
Slack | 4.232 |
Data Arrival Time | 4.414 |
Data Required Time | 0.182 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
3.945 | 0.374 | tNET | FF | 1 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
4.143 | 0.198 | tC2Q | FR | 61 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
4.414 | 0.271 | tNET | RR | 1 | R18C36[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
0.371 | 0.371 | tNET | RR | 1 | R18C36[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLK |
0.182 | -0.189 | tHld | 1 | R18C36[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1 |
Path Statistics:
Clock Skew | -0.003 |
Hold Relationship | -3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.374, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.271, 57.867%; tC2Q: 0.198, 42.133% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.371, 100.000% |
Path11
Path Summary:
Slack | 4.232 |
Data Arrival Time | 4.414 |
Data Required Time | 0.182 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
3.945 | 0.374 | tNET | FF | 1 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
4.143 | 0.198 | tC2Q | FR | 61 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
4.414 | 0.271 | tNET | RR | 1 | R18C36[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
0.371 | 0.371 | tNET | RR | 1 | R18C36[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLK |
0.182 | -0.189 | tHld | 1 | R18C36[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1 |
Path Statistics:
Clock Skew | -0.003 |
Hold Relationship | -3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.374, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.271, 57.867%; tC2Q: 0.198, 42.133% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.371, 100.000% |
Path12
Path Summary:
Slack | 4.510 |
Data Arrival Time | 4.714 |
Data Required Time | 0.204 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_match_1/match_sep_s0 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
3.945 | 0.374 | tNET | FF | 1 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
4.143 | 0.198 | tC2Q | FR | 61 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
4.714 | 0.571 | tNET | RR | 1 | R25C29[2][A] | gw_gao_inst_0/u_la0_top/u_ao_match_1/match_sep_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
0.392 | 0.392 | tNET | RR | 1 | R25C29[2][A] | gw_gao_inst_0/u_la0_top/u_ao_match_1/match_sep_s0/CLK |
0.204 | -0.189 | tHld | 1 | R25C29[2][A] | gw_gao_inst_0/u_la0_top/u_ao_match_1/match_sep_s0 |
Path Statistics:
Clock Skew | 0.019 |
Hold Relationship | -3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.374, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.571, 74.309%; tC2Q: 0.198, 25.691% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.392, 100.000% |
Path13
Path Summary:
Slack | 4.510 |
Data Arrival Time | 4.714 |
Data Required Time | 0.204 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_0_s0 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
3.945 | 0.374 | tNET | FF | 1 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
4.143 | 0.198 | tC2Q | FR | 61 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
4.714 | 0.571 | tNET | RR | 1 | R25C29[1][B] | gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
0.392 | 0.392 | tNET | RR | 1 | R25C29[1][B] | gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_0_s0/CLK |
0.204 | -0.189 | tHld | 1 | R25C29[1][B] | gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_0_s0 |
Path Statistics:
Clock Skew | 0.019 |
Hold Relationship | -3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.374, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.571, 74.309%; tC2Q: 0.198, 25.691% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.392, 100.000% |
Path14
Path Summary:
Slack | 4.510 |
Data Arrival Time | 4.714 |
Data Required Time | 0.204 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
3.945 | 0.374 | tNET | FF | 1 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
4.143 | 0.198 | tC2Q | FR | 61 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
4.714 | 0.571 | tNET | RR | 1 | R25C29[1][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
0.392 | 0.392 | tNET | RR | 1 | R25C29[1][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLK |
0.204 | -0.189 | tHld | 1 | R25C29[1][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0 |
Path Statistics:
Clock Skew | 0.019 |
Hold Relationship | -3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.374, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.571, 74.309%; tC2Q: 0.198, 25.691% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.392, 100.000% |
Path15
Path Summary:
Slack | 4.510 |
Data Arrival Time | 4.714 |
Data Required Time | 0.204 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
3.945 | 0.374 | tNET | FF | 1 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
4.143 | 0.198 | tC2Q | FR | 61 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
4.714 | 0.571 | tNET | RR | 1 | R25C29[2][B] | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
0.392 | 0.392 | tNET | RR | 1 | R25C29[2][B] | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLK |
0.204 | -0.189 | tHld | 1 | R25C29[2][B] | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0 |
Path Statistics:
Clock Skew | 0.019 |
Hold Relationship | -3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.374, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.571, 74.309%; tC2Q: 0.198, 25.691% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.392, 100.000% |
Path16
Path Summary:
Slack | 4.515 |
Data Arrival Time | 4.714 |
Data Required Time | 0.199 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s1 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
3.945 | 0.374 | tNET | FF | 1 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
4.143 | 0.198 | tC2Q | FR | 61 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
4.714 | 0.571 | tNET | RR | 1 | R25C30[0][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
0.387 | 0.387 | tNET | RR | 1 | R25C30[0][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s1/CLK |
0.199 | -0.189 | tHld | 1 | R25C30[0][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s1 |
Path Statistics:
Clock Skew | 0.014 |
Hold Relationship | -3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.374, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.571, 74.309%; tC2Q: 0.198, 25.691% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.387, 100.000% |
Path17
Path Summary:
Slack | 4.515 |
Data Arrival Time | 4.714 |
Data Required Time | 0.199 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
3.945 | 0.374 | tNET | FF | 1 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
4.143 | 0.198 | tC2Q | FR | 61 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
4.714 | 0.571 | tNET | RR | 1 | R25C30[0][B] | gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
0.387 | 0.387 | tNET | RR | 1 | R25C30[0][B] | gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLK |
0.199 | -0.189 | tHld | 1 | R25C30[0][B] | gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1 |
Path Statistics:
Clock Skew | 0.014 |
Hold Relationship | -3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.374, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.571, 74.309%; tC2Q: 0.198, 25.691% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.387, 100.000% |
Path18
Path Summary:
Slack | 4.515 |
Data Arrival Time | 4.714 |
Data Required Time | 0.199 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
3.945 | 0.374 | tNET | FF | 1 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
4.143 | 0.198 | tC2Q | FR | 61 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
4.714 | 0.571 | tNET | RR | 1 | R25C30[1][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
0.387 | 0.387 | tNET | RR | 1 | R25C30[1][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLK |
0.199 | -0.189 | tHld | 1 | R25C30[1][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1 |
Path Statistics:
Clock Skew | 0.014 |
Hold Relationship | -3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.374, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.571, 74.309%; tC2Q: 0.198, 25.691% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.387, 100.000% |
Path19
Path Summary:
Slack | 4.515 |
Data Arrival Time | 4.714 |
Data Required Time | 0.199 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
3.945 | 0.374 | tNET | FF | 1 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
4.143 | 0.198 | tC2Q | FR | 61 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
4.714 | 0.571 | tNET | RR | 1 | R25C30[2][A] | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
0.387 | 0.387 | tNET | RR | 1 | R25C30[2][A] | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLK |
0.199 | -0.189 | tHld | 1 | R25C30[2][A] | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0 |
Path Statistics:
Clock Skew | 0.014 |
Hold Relationship | -3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.374, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.571, 74.309%; tC2Q: 0.198, 25.691% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.387, 100.000% |
Path20
Path Summary:
Slack | 4.519 |
Data Arrival Time | 4.729 |
Data Required Time | 0.210 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_match_1/trig_dly_in_0_s0 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
3.945 | 0.374 | tNET | FF | 1 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
4.143 | 0.198 | tC2Q | FR | 61 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
4.729 | 0.586 | tNET | RR | 1 | R20C28[1][A] | gw_gao_inst_0/u_la0_top/u_ao_match_1/trig_dly_in_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
0.398 | 0.398 | tNET | RR | 1 | R20C28[1][A] | gw_gao_inst_0/u_la0_top/u_ao_match_1/trig_dly_in_0_s0/CLK |
0.210 | -0.189 | tHld | 1 | R20C28[1][A] | gw_gao_inst_0/u_la0_top/u_ao_match_1/trig_dly_in_0_s0 |
Path Statistics:
Clock Skew | 0.025 |
Hold Relationship | -3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.374, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.586, 74.801%; tC2Q: 0.198, 25.199% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.398, 100.000% |
Path21
Path Summary:
Slack | 4.519 |
Data Arrival Time | 4.729 |
Data Required Time | 0.210 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
3.945 | 0.374 | tNET | FF | 1 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
4.143 | 0.198 | tC2Q | FR | 61 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
4.729 | 0.586 | tNET | RR | 1 | R20C28[1][B] | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
0.398 | 0.398 | tNET | RR | 1 | R20C28[1][B] | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLK |
0.210 | -0.189 | tHld | 1 | R20C28[1][B] | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0 |
Path Statistics:
Clock Skew | 0.025 |
Hold Relationship | -3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.374, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.586, 74.801%; tC2Q: 0.198, 25.199% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.398, 100.000% |
Path22
Path Summary:
Slack | 4.539 |
Data Arrival Time | 4.749 |
Data Required Time | 0.210 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
3.945 | 0.374 | tNET | FF | 1 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
4.143 | 0.198 | tC2Q | FR | 61 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
4.749 | 0.606 | tNET | RR | 1 | R20C38[0][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
0.398 | 0.398 | tNET | RR | 1 | R20C38[0][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLK |
0.210 | -0.189 | tHld | 1 | R20C38[0][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1 |
Path Statistics:
Clock Skew | 0.025 |
Hold Relationship | -3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.374, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.606, 75.428%; tC2Q: 0.198, 24.572% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.398, 100.000% |
Path23
Path Summary:
Slack | 4.542 |
Data Arrival Time | 4.749 |
Data Required Time | 0.208 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/trigger_seq_start_s1 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
3.945 | 0.374 | tNET | FF | 1 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
4.143 | 0.198 | tC2Q | FR | 61 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
4.749 | 0.606 | tNET | RR | 1 | R21C38[0][B] | gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
0.396 | 0.396 | tNET | RR | 1 | R21C38[0][B] | gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLK |
0.208 | -0.189 | tHld | 1 | R21C38[0][B] | gw_gao_inst_0/u_la0_top/trigger_seq_start_s1 |
Path Statistics:
Clock Skew | 0.023 |
Hold Relationship | -3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.374, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.606, 75.428%; tC2Q: 0.198, 24.572% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.396, 100.000% |
Path24
Path Summary:
Slack | 4.633 |
Data Arrival Time | 4.834 |
Data Required Time | 0.201 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_match_1/trig_dly_0_s0 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
3.945 | 0.374 | tNET | FF | 1 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
4.143 | 0.198 | tC2Q | FR | 61 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
4.834 | 0.691 | tNET | RR | 1 | R24C28[1][A] | gw_gao_inst_0/u_la0_top/u_ao_match_1/trig_dly_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
0.390 | 0.390 | tNET | RR | 1 | R24C28[1][A] | gw_gao_inst_0/u_la0_top/u_ao_match_1/trig_dly_0_s0/CLK |
0.201 | -0.189 | tHld | 1 | R24C28[1][A] | gw_gao_inst_0/u_la0_top/u_ao_match_1/trig_dly_0_s0 |
Path Statistics:
Clock Skew | 0.016 |
Hold Relationship | -3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.374, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.691, 77.778%; tC2Q: 0.198, 22.222% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.390, 100.000% |
Path25
Path Summary:
Slack | 4.640 |
Data Arrival Time | 4.834 |
Data Required Time | 0.194 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1 |
Launch Clk | pixel_clk:[F] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.572 | 3.572 | active clock edge time | ||||
3.572 | 0.000 | pixel_clk | ||||
3.572 | 0.000 | tCL | FF | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
3.945 | 0.374 | tNET | FF | 1 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
4.143 | 0.198 | tC2Q | FR | 61 | R17C38[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
4.834 | 0.691 | tNET | RR | 1 | R25C31[0][B] | gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 303 | PLL_L[0] | u_pll_1/PLLA_inst/CLKOUT1 |
0.382 | 0.382 | tNET | RR | 1 | R25C31[0][B] | gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLK |
0.194 | -0.189 | tHld | 1 | R25C31[0][B] | gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1 |
Path Statistics:
Clock Skew | 0.009 |
Hold Relationship | -3.572 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.374, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.691, 77.778%; tC2Q: 0.198, 22.222% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.382, 100.000% |
Minimum Pulse Width Report:
Report Command:report_min_pulse_width -nworst 10 -detail
MPW1
MPW Summary:
Slack: | 1.863 |
Actual Width: | 2.863 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | lvds_pclk |
Objects: | u_extr/mem_data_mem_data_0_1_s |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
3.684 | 0.000 | active clock edge time | ||
3.684 | 0.000 | lvds_pclk | ||
3.684 | 0.000 | tCL | FF | u_pll_50m/PLLA_inst/CLKOUT1 |
5.074 | 1.390 | tNET | FF | u_extr/mem_data_mem_data_0_1_s/CLKB |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
7.368 | 0.000 | active clock edge time | ||
7.368 | 0.000 | lvds_pclk | ||
7.368 | 0.000 | tCL | RR | u_pll_50m/PLLA_inst/CLKOUT1 |
7.937 | 0.569 | tNET | RR | u_extr/mem_data_mem_data_0_1_s/CLKB |
MPW2
MPW Summary:
Slack: | 1.863 |
Actual Width: | 2.863 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | lvds_pclk |
Objects: | u_extr/mem_data_mem_data_0_7_s |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
3.684 | 0.000 | active clock edge time | ||
3.684 | 0.000 | lvds_pclk | ||
3.684 | 0.000 | tCL | FF | u_pll_50m/PLLA_inst/CLKOUT1 |
5.074 | 1.390 | tNET | FF | u_extr/mem_data_mem_data_0_7_s/CLKB |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
7.368 | 0.000 | active clock edge time | ||
7.368 | 0.000 | lvds_pclk | ||
7.368 | 0.000 | tCL | RR | u_pll_50m/PLLA_inst/CLKOUT1 |
7.937 | 0.569 | tNET | RR | u_extr/mem_data_mem_data_0_7_s/CLKB |
MPW3
MPW Summary:
Slack: | 1.863 |
Actual Width: | 2.863 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | lvds_pclk |
Objects: | u_extr/mem_data_mem_data_0_8_s |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
3.684 | 0.000 | active clock edge time | ||
3.684 | 0.000 | lvds_pclk | ||
3.684 | 0.000 | tCL | FF | u_pll_50m/PLLA_inst/CLKOUT1 |
5.074 | 1.390 | tNET | FF | u_extr/mem_data_mem_data_0_8_s/CLKB |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
7.368 | 0.000 | active clock edge time | ||
7.368 | 0.000 | lvds_pclk | ||
7.368 | 0.000 | tCL | RR | u_pll_50m/PLLA_inst/CLKOUT1 |
7.937 | 0.569 | tNET | RR | u_extr/mem_data_mem_data_0_8_s/CLKB |
MPW4
MPW Summary:
Slack: | 1.865 |
Actual Width: | 2.865 |
Required Width: | 1.000 |
Type: | High Pulse Width |
Clock: | lvds_pclk |
Objects: | u_extr/mem_data_mem_data_0_1_s |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||
0.000 | 0.000 | lvds_pclk | ||
0.000 | 0.000 | tCL | RR | u_pll_50m/PLLA_inst/CLKOUT1 |
1.393 | 1.393 | tNET | RR | u_extr/mem_data_mem_data_0_1_s/CLKB |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
3.684 | 0.000 | active clock edge time | ||
3.684 | 0.000 | lvds_pclk | ||
3.684 | 0.000 | tCL | FF | u_pll_50m/PLLA_inst/CLKOUT1 |
4.259 | 0.575 | tNET | FF | u_extr/mem_data_mem_data_0_1_s/CLKB |
MPW5
MPW Summary:
Slack: | 1.865 |
Actual Width: | 2.865 |
Required Width: | 1.000 |
Type: | High Pulse Width |
Clock: | lvds_pclk |
Objects: | u_extr/mem_data_mem_data_0_7_s |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||
0.000 | 0.000 | lvds_pclk | ||
0.000 | 0.000 | tCL | RR | u_pll_50m/PLLA_inst/CLKOUT1 |
1.393 | 1.393 | tNET | RR | u_extr/mem_data_mem_data_0_7_s/CLKB |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
3.684 | 0.000 | active clock edge time | ||
3.684 | 0.000 | lvds_pclk | ||
3.684 | 0.000 | tCL | FF | u_pll_50m/PLLA_inst/CLKOUT1 |
4.259 | 0.575 | tNET | FF | u_extr/mem_data_mem_data_0_7_s/CLKB |
MPW6
MPW Summary:
Slack: | 1.865 |
Actual Width: | 2.865 |
Required Width: | 1.000 |
Type: | High Pulse Width |
Clock: | lvds_pclk |
Objects: | u_extr/mem_data_mem_data_0_8_s |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||
0.000 | 0.000 | lvds_pclk | ||
0.000 | 0.000 | tCL | RR | u_pll_50m/PLLA_inst/CLKOUT1 |
1.393 | 1.393 | tNET | RR | u_extr/mem_data_mem_data_0_8_s/CLKB |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
3.684 | 0.000 | active clock edge time | ||
3.684 | 0.000 | lvds_pclk | ||
3.684 | 0.000 | tCL | FF | u_pll_50m/PLLA_inst/CLKOUT1 |
4.259 | 0.575 | tNET | FF | u_extr/mem_data_mem_data_0_8_s/CLKB |
MPW7
MPW Summary:
Slack: | 1.868 |
Actual Width: | 2.868 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | lvds_pclk |
Objects: | u_extr/mem_data_mem_data_0_9_s |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
3.684 | 0.000 | active clock edge time | ||
3.684 | 0.000 | lvds_pclk | ||
3.684 | 0.000 | tCL | FF | u_pll_50m/PLLA_inst/CLKOUT1 |
5.065 | 1.380 | tNET | FF | u_extr/mem_data_mem_data_0_9_s/CLKB |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
7.368 | 0.000 | active clock edge time | ||
7.368 | 0.000 | lvds_pclk | ||
7.368 | 0.000 | tCL | RR | u_pll_50m/PLLA_inst/CLKOUT1 |
7.932 | 0.564 | tNET | RR | u_extr/mem_data_mem_data_0_9_s/CLKB |
MPW8
MPW Summary:
Slack: | 1.868 |
Actual Width: | 2.868 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | lvds_pclk |
Objects: | u_extr/mem_data_mem_data_0_11_s |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
3.684 | 0.000 | active clock edge time | ||
3.684 | 0.000 | lvds_pclk | ||
3.684 | 0.000 | tCL | FF | u_pll_50m/PLLA_inst/CLKOUT1 |
5.065 | 1.380 | tNET | FF | u_extr/mem_data_mem_data_0_11_s/CLKB |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
7.368 | 0.000 | active clock edge time | ||
7.368 | 0.000 | lvds_pclk | ||
7.368 | 0.000 | tCL | RR | u_pll_50m/PLLA_inst/CLKOUT1 |
7.932 | 0.564 | tNET | RR | u_extr/mem_data_mem_data_0_11_s/CLKB |
MPW9
MPW Summary:
Slack: | 1.868 |
Actual Width: | 2.868 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | lvds_pclk |
Objects: | u_extr/mem_data_mem_data_0_0_s |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
3.684 | 0.000 | active clock edge time | ||
3.684 | 0.000 | lvds_pclk | ||
3.684 | 0.000 | tCL | FF | u_pll_50m/PLLA_inst/CLKOUT1 |
5.065 | 1.380 | tNET | FF | u_extr/mem_data_mem_data_0_0_s/CLKB |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
7.368 | 0.000 | active clock edge time | ||
7.368 | 0.000 | lvds_pclk | ||
7.368 | 0.000 | tCL | RR | u_pll_50m/PLLA_inst/CLKOUT1 |
7.932 | 0.564 | tNET | RR | u_extr/mem_data_mem_data_0_0_s/CLKB |
MPW10
MPW Summary:
Slack: | 1.868 |
Actual Width: | 2.868 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | lvds_pclk |
Objects: | u_extr/mem_data_mem_data_0_2_s |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
3.684 | 0.000 | active clock edge time | ||
3.684 | 0.000 | lvds_pclk | ||
3.684 | 0.000 | tCL | FF | u_pll_50m/PLLA_inst/CLKOUT1 |
5.065 | 1.380 | tNET | FF | u_extr/mem_data_mem_data_0_2_s/CLKB |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
7.368 | 0.000 | active clock edge time | ||
7.368 | 0.000 | lvds_pclk | ||
7.368 | 0.000 | tCL | RR | u_pll_50m/PLLA_inst/CLKOUT1 |
7.932 | 0.564 | tNET | RR | u_extr/mem_data_mem_data_0_2_s/CLKB |
High Fanout Nets Report:
Report Command:report_high_fanout_nets -max_nets 10
FANOUT | NET NAME | WORST SLACK | MAX DELAY |
---|---|---|---|
598 | byte_clk | 2.165 | 0.924 |
303 | pixel_clk | 2.147 | 0.913 |
240 | control0[0] | 42.254 | 2.385 |
165 | lvds_pclk | 1.204 | 1.430 |
96 | n1393_9 | 6.299 | 1.560 |
81 | shift_en | 3.667 | 2.476 |
61 | rst_ao | 1.148 | 1.710 |
58 | buf_rd | 1.266 | 2.316 |
51 | mid_dv | 6.064 | 1.943 |
49 | mid_data_47_5 | 6.094 | 1.916 |
Route Congestions Report:
Report Command:report_route_congestion -max_grids 10
GRID LOC | ROUTE CONGESTIONS |
---|---|
R12C31 | 63.89% |
R11C31 | 51.39% |
R12C35 | 50.00% |
R14C20 | 48.61% |
R25C23 | 48.61% |
R23C21 | 44.44% |
R9C23 | 44.44% |
R12C32 | 44.44% |
R16C29 | 44.44% |
R15C35 | 44.44% |
Timing Exceptions Report:
Setup Analysis Report
Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Hold Analysis Report
Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Recovery Analysis Report
Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Removal Analysis Report
Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Timing Constraints Report:
SDC Command Type | State | Detail Command |
---|---|---|
TC_CLOCK | Actived | create_clock -name clk_50 -period 20 -waveform {0 10} [get_ports {OSC_50M}] |
TC_CLOCK | Actived | create_clock -name byte_clk -period 9.524 -waveform {0 4.762} [get_nets {byte_clk}] |
TC_GENERATED_CLOCK | Actived | create_generated_clock -name pixel_clk -source [get_nets {byte_clk}] -master_clock byte_clk -divide_by 3 -multiply_by 4 [get_nets {pixel_clk}] |
TC_GENERATED_CLOCK | Actived | create_generated_clock -name lvds_pclk -source [get_ports {OSC_50M}] -master_clock clk_50 -divide_by 7 -multiply_by 19 [get_nets {lvds_pclk}] |
TC_CLOCK_GROUP | Actived | set_clock_groups -exclusive -group [get_clocks {pixel_clk}] -group [get_clocks {byte_clk}] |
TC_CLOCK_GROUP | Actived | set_clock_groups -exclusive -group [get_clocks {pixel_clk}] -group [get_clocks {lvds_pclk}] |
TC_CLOCK_GROUP | Actived | set_clock_groups -exclusive -group [get_clocks {byte_clk}] -group [get_clocks {lvds_pclk}] |