Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\EDP_ENCODE\data\edp_encoder_top.v
D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\EDP_ENCODE\data\edp_encoder_wrapper.v
GowinSynthesis Constraints File ---
Tool Version V1.9.9.03 (64-bit)
Part Number GW5AST-LV138FPG676AES
Device GW5AST-138
Device Version B
Created Time Mon May 6 15:16:36 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module EDP_Encoder_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.531s, Elapsed time = 0h 0m 0.617s, Peak memory usage = 118.059MB
Running netlist conversion:
    CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.064s, Peak memory usage = 118.059MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.234s, Elapsed time = 0h 0m 0.226s, Peak memory usage = 118.059MB
    Optimizing Phase 1: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.149s, Peak memory usage = 118.059MB
    Optimizing Phase 2: CPU time = 0h 0m 0.312s, Elapsed time = 0h 0m 0.323s, Peak memory usage = 118.059MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.136s, Peak memory usage = 118.059MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 118.059MB
    Inferring Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.036s, Peak memory usage = 118.059MB
    Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.015s, Peak memory usage = 118.059MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.312s, Elapsed time = 0h 0m 0.311s, Peak memory usage = 118.059MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.074s, Peak memory usage = 118.059MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.065s, Peak memory usage = 118.059MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 15s, Elapsed time = 0h 0m 15s, Peak memory usage = 141.598MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.359s, Elapsed time = 0h 0m 0.392s, Peak memory usage = 141.598MB
Generate output files:
    CPU time = 0h 0m 0.406s, Elapsed time = 0h 0m 0.397s, Peak memory usage = 145.273MB
Total Time and Memory Usage CPU time = 0h 0m 17s, Elapsed time = 0h 0m 17s, Peak memory usage = 145.273MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 499
I/O Buf 470
    IBUF 326
    OBUF 144
Register 2195
    DFFSE 116
    DFFRE 100
    DFFPE 8
    DFFCE 1971
LUT 3302
    LUT2 446
    LUT3 923
    LUT4 1933
ALU 129
    ALU 129
INV 7
    INV 7
BSRAM 16
    SDPB 16

Resource Utilization Summary

Resource Usage Utilization
Logic 3438(3309 LUT, 129 ALU) / 138240 3%
Register 2195 / 139140 2%
  --Register as Latch 0 / 139140 0%
  --Register as FF 2195 / 139140 2%
BSRAM 16 / 340 5%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
I_ls_clk Base 10.000 100.0 0.000 5.000 I_ls_clk_ibuf/I
I_strm_clk Base 10.000 100.0 0.000 5.000 I_strm_clk_ibuf/I

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 I_ls_clk 100.000(MHz) 107.181(MHz) 11 TOP
2 I_strm_clk 100.000(MHz) 127.004(MHz) 9 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 0.670
Data Arrival Time 9.679
Data Required Time 10.349
From edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/tx_syn_gen_inst/V_cnt_0_s3
To edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/data_1_24_s0
Launch Clk I_ls_clk[R]
Latch Clk I_ls_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_ls_clk
0.000 0.000 tCL RR 1 I_ls_clk_ibuf/I
0.000 0.000 tINS RR 1738 I_ls_clk_ibuf/O
0.413 0.413 tNET RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/tx_syn_gen_inst/V_cnt_0_s3/CLK
0.795 0.382 tC2Q RR 8 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/tx_syn_gen_inst/V_cnt_0_s3/Q
1.207 0.413 tNET RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n954_s0/I0
1.803 0.595 tINS RF 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n954_s0/COUT
1.803 0.000 tNET FF 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n955_s0/CIN
1.852 0.050 tINS FR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n955_s0/COUT
1.852 0.000 tNET RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n956_s0/CIN
1.902 0.050 tINS RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n956_s0/COUT
1.902 0.000 tNET RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n957_s0/CIN
1.952 0.050 tINS RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n957_s0/COUT
1.952 0.000 tNET RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n958_s0/CIN
2.002 0.050 tINS RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n958_s0/COUT
2.002 0.000 tNET RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n959_s0/CIN
2.052 0.050 tINS RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n959_s0/COUT
2.052 0.000 tNET RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n960_s0/CIN
2.102 0.050 tINS RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n960_s0/COUT
2.102 0.000 tNET RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n961_s0/CIN
2.152 0.050 tINS RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n961_s0/COUT
2.152 0.000 tNET RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n962_s0/CIN
2.202 0.050 tINS RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n962_s0/COUT
2.202 0.000 tNET RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n963_s0/CIN
2.252 0.050 tINS RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n963_s0/COUT
2.252 0.000 tNET RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n964_s0/CIN
2.302 0.050 tINS RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n964_s0/COUT
2.302 0.000 tNET RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n965_s0/CIN
2.352 0.050 tINS RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n965_s0/COUT
2.352 0.000 tNET RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n966_s0/CIN
2.402 0.050 tINS RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n966_s0/COUT
2.402 0.000 tNET RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n967_s0/CIN
2.452 0.050 tINS RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n967_s0/COUT
2.452 0.000 tNET RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n968_s0/CIN
2.502 0.050 tINS RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n968_s0/COUT
2.502 0.000 tNET RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n969_s0/CIN
2.552 0.050 tINS RR 9 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n969_s0/COUT
2.965 0.413 tNET RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n7534_s15/I0
3.544 0.579 tINS RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n7534_s15/F
3.956 0.413 tNET RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n7534_s8/I2
4.464 0.507 tINS RR 12 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n7534_s8/F
4.876 0.413 tNET RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/kd_1_0_s9/I2
5.384 0.507 tINS RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/kd_1_0_s9/F
5.796 0.413 tNET RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/kd_1_0_s8/I2
6.304 0.507 tINS RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/kd_1_0_s8/F
6.716 0.413 tNET RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/kd_1_24_s4/I0
7.295 0.579 tINS RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/kd_1_24_s4/F
7.707 0.413 tNET RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/kd_1_24_s2/I0
8.286 0.579 tINS RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/kd_1_24_s2/F
8.699 0.413 tNET RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/kd_1_24_s1/I1
9.266 0.567 tINS RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/kd_1_24_s1/F
9.679 0.413 tNET RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/data_1_24_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_ls_clk
10.000 0.000 tCL RR 1 I_ls_clk_ibuf/I
10.000 0.000 tINS RR 1738 I_ls_clk_ibuf/O
10.413 0.413 tNET RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/data_1_24_s0/CLK
10.349 -0.064 tSu 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/data_1_24_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 11
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 5.171, 55.807%; route: 3.712, 40.065%; tC2Q: 0.382, 4.128%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 2

Path Summary:
Slack 0.670
Data Arrival Time 9.679
Data Required Time 10.349
From edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/tx_syn_gen_inst/V_cnt_0_s3
To edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/data_0_1_s0
Launch Clk I_ls_clk[R]
Latch Clk I_ls_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_ls_clk
0.000 0.000 tCL RR 1 I_ls_clk_ibuf/I
0.000 0.000 tINS RR 1738 I_ls_clk_ibuf/O
0.413 0.413 tNET RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/tx_syn_gen_inst/V_cnt_0_s3/CLK
0.795 0.382 tC2Q RR 8 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/tx_syn_gen_inst/V_cnt_0_s3/Q
1.207 0.413 tNET RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n954_s0/I0
1.803 0.595 tINS RF 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n954_s0/COUT
1.803 0.000 tNET FF 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n955_s0/CIN
1.852 0.050 tINS FR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n955_s0/COUT
1.852 0.000 tNET RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n956_s0/CIN
1.902 0.050 tINS RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n956_s0/COUT
1.902 0.000 tNET RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n957_s0/CIN
1.952 0.050 tINS RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n957_s0/COUT
1.952 0.000 tNET RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n958_s0/CIN
2.002 0.050 tINS RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n958_s0/COUT
2.002 0.000 tNET RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n959_s0/CIN
2.052 0.050 tINS RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n959_s0/COUT
2.052 0.000 tNET RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n960_s0/CIN
2.102 0.050 tINS RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n960_s0/COUT
2.102 0.000 tNET RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n961_s0/CIN
2.152 0.050 tINS RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n961_s0/COUT
2.152 0.000 tNET RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n962_s0/CIN
2.202 0.050 tINS RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n962_s0/COUT
2.202 0.000 tNET RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n963_s0/CIN
2.252 0.050 tINS RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n963_s0/COUT
2.252 0.000 tNET RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n964_s0/CIN
2.302 0.050 tINS RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n964_s0/COUT
2.302 0.000 tNET RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n965_s0/CIN
2.352 0.050 tINS RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n965_s0/COUT
2.352 0.000 tNET RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n966_s0/CIN
2.402 0.050 tINS RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n966_s0/COUT
2.402 0.000 tNET RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n967_s0/CIN
2.452 0.050 tINS RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n967_s0/COUT
2.452 0.000 tNET RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n968_s0/CIN
2.502 0.050 tINS RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n968_s0/COUT
2.502 0.000 tNET RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n969_s0/CIN
2.552 0.050 tINS RR 9 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n969_s0/COUT
2.965 0.413 tNET RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n7534_s15/I0
3.544 0.579 tINS RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n7534_s15/F
3.956 0.413 tNET RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n7534_s8/I2
4.464 0.507 tINS RR 12 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n7534_s8/F
4.876 0.413 tNET RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/kd_1_5_s9/I2
5.384 0.507 tINS RR 3 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/kd_1_5_s9/F
5.796 0.413 tNET RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/kd_0_1_s8/I2
6.304 0.507 tINS RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/kd_0_1_s8/F
6.716 0.413 tNET RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/kd_0_1_s5/I0
7.295 0.579 tINS RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/kd_0_1_s5/F
7.707 0.413 tNET RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/kd_0_1_s3/I0
8.286 0.579 tINS RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/kd_0_1_s3/F
8.699 0.413 tNET RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/kd_0_1_s2/I1
9.266 0.567 tINS RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/kd_0_1_s2/F
9.679 0.413 tNET RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/data_0_1_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_ls_clk
10.000 0.000 tCL RR 1 I_ls_clk_ibuf/I
10.000 0.000 tINS RR 1738 I_ls_clk_ibuf/O
10.413 0.413 tNET RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/data_0_1_s0/CLK
10.349 -0.064 tSu 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/data_0_1_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 11
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 5.171, 55.807%; route: 3.712, 40.065%; tC2Q: 0.382, 4.128%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 3

Path Summary:
Slack 0.670
Data Arrival Time 9.679
Data Required Time 10.349
From edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/tx_syn_gen_inst/V_cnt_0_s3
To edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/data_0_25_s0
Launch Clk I_ls_clk[R]
Latch Clk I_ls_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_ls_clk
0.000 0.000 tCL RR 1 I_ls_clk_ibuf/I
0.000 0.000 tINS RR 1738 I_ls_clk_ibuf/O
0.413 0.413 tNET RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/tx_syn_gen_inst/V_cnt_0_s3/CLK
0.795 0.382 tC2Q RR 8 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/tx_syn_gen_inst/V_cnt_0_s3/Q
1.207 0.413 tNET RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n954_s0/I0
1.803 0.595 tINS RF 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n954_s0/COUT
1.803 0.000 tNET FF 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n955_s0/CIN
1.852 0.050 tINS FR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n955_s0/COUT
1.852 0.000 tNET RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n956_s0/CIN
1.902 0.050 tINS RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n956_s0/COUT
1.902 0.000 tNET RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n957_s0/CIN
1.952 0.050 tINS RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n957_s0/COUT
1.952 0.000 tNET RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n958_s0/CIN
2.002 0.050 tINS RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n958_s0/COUT
2.002 0.000 tNET RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n959_s0/CIN
2.052 0.050 tINS RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n959_s0/COUT
2.052 0.000 tNET RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n960_s0/CIN
2.102 0.050 tINS RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n960_s0/COUT
2.102 0.000 tNET RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n961_s0/CIN
2.152 0.050 tINS RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n961_s0/COUT
2.152 0.000 tNET RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n962_s0/CIN
2.202 0.050 tINS RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n962_s0/COUT
2.202 0.000 tNET RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n963_s0/CIN
2.252 0.050 tINS RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n963_s0/COUT
2.252 0.000 tNET RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n964_s0/CIN
2.302 0.050 tINS RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n964_s0/COUT
2.302 0.000 tNET RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n965_s0/CIN
2.352 0.050 tINS RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n965_s0/COUT
2.352 0.000 tNET RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n966_s0/CIN
2.402 0.050 tINS RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n966_s0/COUT
2.402 0.000 tNET RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n967_s0/CIN
2.452 0.050 tINS RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n967_s0/COUT
2.452 0.000 tNET RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n968_s0/CIN
2.502 0.050 tINS RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n968_s0/COUT
2.502 0.000 tNET RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n969_s0/CIN
2.552 0.050 tINS RR 9 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n969_s0/COUT
2.965 0.413 tNET RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n7534_s15/I0
3.544 0.579 tINS RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n7534_s15/F
3.956 0.413 tNET RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n7534_s8/I2
4.464 0.507 tINS RR 12 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n7534_s8/F
4.876 0.413 tNET RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/kd_1_5_s9/I2
5.384 0.507 tINS RR 3 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/kd_1_5_s9/F
5.796 0.413 tNET RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/kd_0_1_s8/I2
6.304 0.507 tINS RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/kd_0_1_s8/F
6.716 0.413 tNET RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/kd_0_1_s5/I0
7.295 0.579 tINS RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/kd_0_1_s5/F
7.707 0.413 tNET RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/kd_0_25_s2/I0
8.286 0.579 tINS RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/kd_0_25_s2/F
8.699 0.413 tNET RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/kd_0_25_s1/I1
9.266 0.567 tINS RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/kd_0_25_s1/F
9.679 0.413 tNET RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/data_0_25_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_ls_clk
10.000 0.000 tCL RR 1 I_ls_clk_ibuf/I
10.000 0.000 tINS RR 1738 I_ls_clk_ibuf/O
10.413 0.413 tNET RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/data_0_25_s0/CLK
10.349 -0.064 tSu 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/data_0_25_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 11
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 5.171, 55.807%; route: 3.712, 40.065%; tC2Q: 0.382, 4.128%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 4

Path Summary:
Slack 0.741
Data Arrival Time 9.608
Data Required Time 10.349
From edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/tx_syn_gen_inst/V_cnt_0_s3
To edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/data_0_29_s0
Launch Clk I_ls_clk[R]
Latch Clk I_ls_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_ls_clk
0.000 0.000 tCL RR 1 I_ls_clk_ibuf/I
0.000 0.000 tINS RR 1738 I_ls_clk_ibuf/O
0.413 0.413 tNET RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/tx_syn_gen_inst/V_cnt_0_s3/CLK
0.795 0.382 tC2Q RR 8 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/tx_syn_gen_inst/V_cnt_0_s3/Q
1.207 0.413 tNET RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n954_s0/I0
1.803 0.595 tINS RF 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n954_s0/COUT
1.803 0.000 tNET FF 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n955_s0/CIN
1.852 0.050 tINS FR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n955_s0/COUT
1.852 0.000 tNET RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n956_s0/CIN
1.902 0.050 tINS RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n956_s0/COUT
1.902 0.000 tNET RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n957_s0/CIN
1.952 0.050 tINS RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n957_s0/COUT
1.952 0.000 tNET RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n958_s0/CIN
2.002 0.050 tINS RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n958_s0/COUT
2.002 0.000 tNET RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n959_s0/CIN
2.052 0.050 tINS RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n959_s0/COUT
2.052 0.000 tNET RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n960_s0/CIN
2.102 0.050 tINS RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n960_s0/COUT
2.102 0.000 tNET RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n961_s0/CIN
2.152 0.050 tINS RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n961_s0/COUT
2.152 0.000 tNET RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n962_s0/CIN
2.202 0.050 tINS RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n962_s0/COUT
2.202 0.000 tNET RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n963_s0/CIN
2.252 0.050 tINS RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n963_s0/COUT
2.252 0.000 tNET RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n964_s0/CIN
2.302 0.050 tINS RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n964_s0/COUT
2.302 0.000 tNET RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n965_s0/CIN
2.352 0.050 tINS RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n965_s0/COUT
2.352 0.000 tNET RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n966_s0/CIN
2.402 0.050 tINS RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n966_s0/COUT
2.402 0.000 tNET RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n967_s0/CIN
2.452 0.050 tINS RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n967_s0/COUT
2.452 0.000 tNET RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n968_s0/CIN
2.502 0.050 tINS RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n968_s0/COUT
2.502 0.000 tNET RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n969_s0/CIN
2.552 0.050 tINS RR 9 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n969_s0/COUT
2.965 0.413 tNET RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n7534_s15/I0
3.544 0.579 tINS RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n7534_s15/F
3.956 0.413 tNET RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n7534_s8/I2
4.464 0.507 tINS RR 12 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n7534_s8/F
4.876 0.413 tNET RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/kd_1_5_s9/I2
5.384 0.507 tINS RR 3 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/kd_1_5_s9/F
5.796 0.413 tNET RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/kd_0_5_s7/I2
6.304 0.507 tINS RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/kd_0_5_s7/F
6.716 0.413 tNET RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/kd_0_29_s5/I0
7.295 0.579 tINS RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/kd_0_29_s5/F
7.707 0.413 tNET RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/kd_0_29_s2/I2
8.215 0.507 tINS RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/kd_0_29_s2/F
8.627 0.413 tNET RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/kd_0_29_s1/I1
9.195 0.567 tINS RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/kd_0_29_s1/F
9.608 0.413 tNET RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/data_0_29_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_ls_clk
10.000 0.000 tCL RR 1 I_ls_clk_ibuf/I
10.000 0.000 tINS RR 1738 I_ls_clk_ibuf/O
10.413 0.413 tNET RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/data_0_29_s0/CLK
10.349 -0.064 tSu 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/data_0_29_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 11
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 5.100, 55.465%; route: 3.712, 40.375%; tC2Q: 0.382, 4.160%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 5

Path Summary:
Slack 0.752
Data Arrival Time 9.596
Data Required Time 10.349
From edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/tx_syn_gen_inst/V_cnt_0_s3
To edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/data_1_5_s0
Launch Clk I_ls_clk[R]
Latch Clk I_ls_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_ls_clk
0.000 0.000 tCL RR 1 I_ls_clk_ibuf/I
0.000 0.000 tINS RR 1738 I_ls_clk_ibuf/O
0.413 0.413 tNET RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/tx_syn_gen_inst/V_cnt_0_s3/CLK
0.795 0.382 tC2Q RR 8 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/tx_syn_gen_inst/V_cnt_0_s3/Q
1.207 0.413 tNET RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n954_s0/I0
1.803 0.595 tINS RF 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n954_s0/COUT
1.803 0.000 tNET FF 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n955_s0/CIN
1.852 0.050 tINS FR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n955_s0/COUT
1.852 0.000 tNET RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n956_s0/CIN
1.902 0.050 tINS RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n956_s0/COUT
1.902 0.000 tNET RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n957_s0/CIN
1.952 0.050 tINS RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n957_s0/COUT
1.952 0.000 tNET RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n958_s0/CIN
2.002 0.050 tINS RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n958_s0/COUT
2.002 0.000 tNET RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n959_s0/CIN
2.052 0.050 tINS RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n959_s0/COUT
2.052 0.000 tNET RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n960_s0/CIN
2.102 0.050 tINS RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n960_s0/COUT
2.102 0.000 tNET RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n961_s0/CIN
2.152 0.050 tINS RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n961_s0/COUT
2.152 0.000 tNET RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n962_s0/CIN
2.202 0.050 tINS RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n962_s0/COUT
2.202 0.000 tNET RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n963_s0/CIN
2.252 0.050 tINS RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n963_s0/COUT
2.252 0.000 tNET RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n964_s0/CIN
2.302 0.050 tINS RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n964_s0/COUT
2.302 0.000 tNET RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n965_s0/CIN
2.352 0.050 tINS RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n965_s0/COUT
2.352 0.000 tNET RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n966_s0/CIN
2.402 0.050 tINS RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n966_s0/COUT
2.402 0.000 tNET RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n967_s0/CIN
2.452 0.050 tINS RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n967_s0/COUT
2.452 0.000 tNET RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n968_s0/CIN
2.502 0.050 tINS RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n968_s0/COUT
2.502 0.000 tNET RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n969_s0/CIN
2.552 0.050 tINS RR 9 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n969_s0/COUT
2.965 0.413 tNET RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n7534_s15/I0
3.544 0.579 tINS RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n7534_s15/F
3.956 0.413 tNET RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n7534_s8/I2
4.464 0.507 tINS RR 12 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/n7534_s8/F
4.876 0.413 tNET RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/kd_1_5_s9/I2
5.384 0.507 tINS RR 3 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/kd_1_5_s9/F
5.796 0.413 tNET RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/kd_1_5_s7/I2
6.304 0.507 tINS RR 2 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/kd_1_5_s7/F
6.716 0.413 tNET RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/kd_1_5_s6/I1
7.284 0.567 tINS RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/kd_1_5_s6/F
7.696 0.413 tNET RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/kd_1_5_s3/I2
8.204 0.507 tINS RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/kd_1_5_s3/F
8.616 0.413 tNET RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/kd_1_5_s2/I1
9.184 0.567 tINS RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/kd_1_5_s2/F
9.596 0.413 tNET RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/data_1_5_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_ls_clk
10.000 0.000 tCL RR 1 I_ls_clk_ibuf/I
10.000 0.000 tINS RR 1738 I_ls_clk_ibuf/O
10.413 0.413 tNET RR 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/data_1_5_s0/CLK
10.349 -0.064 tSu 1 edp_encoder_wrapper_inst/tx_ms_packer_inst/tx_ms_packer40_inst/data_1_5_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 11
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 5.089, 55.410%; route: 3.712, 40.425%; tC2Q: 0.382, 4.165%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%