Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\EDP_RX_DESTEER\data\edp_rx_desteer_top.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\EDP_RX_DESTEER\data\rx_desteer_wrapper.v |
GowinSynthesis Constraints File | --- |
Tool Version | V1.9.9.03 (64-bit) |
Part Number | GW5AST-LV138FPG676AES |
Device | GW5AST-138 |
Device Version | B |
Created Time | Mon May 6 15:16:53 2024 |
Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | EDP_RX_Desteer_Top |
Synthesis Process | Running parser: CPU time = 0h 0m 0.39s, Elapsed time = 0h 0m 0.398s, Peak memory usage = 102.648MB Running netlist conversion: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.028s, Peak memory usage = 102.648MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.089s, Peak memory usage = 102.648MB Optimizing Phase 1: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.066s, Peak memory usage = 102.648MB Optimizing Phase 2: CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.218s, Peak memory usage = 102.648MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.134s, Peak memory usage = 102.648MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 102.648MB Inferring Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.023s, Peak memory usage = 102.648MB Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 102.648MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.143s, Peak memory usage = 102.648MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.023s, Peak memory usage = 102.648MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.021s, Peak memory usage = 102.648MB Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 131.074MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.108s, Peak memory usage = 131.074MB Generate output files: CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.181s, Peak memory usage = 131.074MB |
Total Time and Memory Usage | CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 131.074MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 458 |
I/O Buf | 455 |
    IBUF | 324 |
    OBUF | 131 |
Register | 558 |
    DFFPE | 13 |
    DFFCE | 545 |
LUT | 1013 |
    LUT2 | 122 |
    LUT3 | 289 |
    LUT4 | 602 |
ALU | 266 |
    ALU | 266 |
INV | 19 |
    INV | 19 |
BSRAM | 48 |
    SDPB | 48 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 1298(1032 LUT, 266 ALU) / 138240 | <1% |
Register | 558 / 139140 | <1% |
  --Register as Latch | 0 / 139140 | 0% |
  --Register as FF | 558 / 139140 | <1% |
BSRAM | 48 / 340 | 15% |
Timing
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|
I_strm_clk | Base | 10.000 | 100.0 | 0.000 | 5.000 | I_strm_clk_ibuf/I | ||
I_ls_clk | Base | 10.000 | 100.0 | 0.000 | 5.000 | I_ls_clk_ibuf/I |
Max Frequency Summary:
No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | I_strm_clk | 100.000(MHz) | 122.549(MHz) | 10 | TOP |
2 | I_ls_clk | 100.000(MHz) | 148.976(MHz) | 7 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | 1.840 |
Data Arrival Time | 8.509 |
Data Required Time | 10.349 |
From | rx_desteer_wrapper_inst/rx_fifo_lb_wrapper_inst/rx_fifo_lb_inst2/Empty_s0 |
To | rx_desteer_wrapper_inst/rx_fifo_lb_wrapper_inst/rx_fifo_lb_inst2/Empty_s0 |
Launch Clk | I_strm_clk[R] |
Latch Clk | I_strm_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | I_strm_clk | |||
0.000 | 0.000 | tCL | RR | 1 | I_strm_clk_ibuf/I |
0.000 | 0.000 | tINS | RR | 396 | I_strm_clk_ibuf/O |
0.413 | 0.413 | tNET | RR | 1 | rx_desteer_wrapper_inst/rx_fifo_lb_wrapper_inst/rx_fifo_lb_inst2/Empty_s0/CLK |
0.795 | 0.382 | tC2Q | RR | 4 | rx_desteer_wrapper_inst/rx_fifo_lb_wrapper_inst/rx_fifo_lb_inst2/Empty_s0/Q |
1.207 | 0.413 | tNET | RR | 1 | rx_desteer_wrapper_inst/rx_fifo_lb_wrapper_inst/rx_fifo_lb_inst2/rbin_num_next_2_s4/I0 |
1.786 | 0.579 | tINS | RR | 7 | rx_desteer_wrapper_inst/rx_fifo_lb_wrapper_inst/rx_fifo_lb_inst2/rbin_num_next_2_s4/F |
2.199 | 0.413 | tNET | RR | 1 | rx_desteer_wrapper_inst/rx_fifo_lb_wrapper_inst/rx_fifo_lb_inst2/rbin_num_next_5_s4/I3 |
2.487 | 0.289 | tINS | RR | 7 | rx_desteer_wrapper_inst/rx_fifo_lb_wrapper_inst/rx_fifo_lb_inst2/rbin_num_next_5_s4/F |
2.900 | 0.413 | tNET | RR | 1 | rx_desteer_wrapper_inst/rx_fifo_lb_wrapper_inst/rx_fifo_lb_inst2/rbin_num_next_8_s4/I3 |
3.189 | 0.289 | tINS | RR | 7 | rx_desteer_wrapper_inst/rx_fifo_lb_wrapper_inst/rx_fifo_lb_inst2/rbin_num_next_8_s4/F |
3.601 | 0.413 | tNET | RR | 1 | rx_desteer_wrapper_inst/rx_fifo_lb_wrapper_inst/rx_fifo_lb_inst2/rbin_num_next_9_s4/I1 |
4.169 | 0.567 | tINS | RR | 2 | rx_desteer_wrapper_inst/rx_fifo_lb_wrapper_inst/rx_fifo_lb_inst2/rbin_num_next_9_s4/F |
4.581 | 0.413 | tNET | RR | 1 | rx_desteer_wrapper_inst/rx_fifo_lb_wrapper_inst/rx_fifo_lb_inst2/rbin_num_next_11_s3/I2 |
5.089 | 0.507 | tINS | RR | 3 | rx_desteer_wrapper_inst/rx_fifo_lb_wrapper_inst/rx_fifo_lb_inst2/rbin_num_next_11_s3/F |
5.501 | 0.413 | tNET | RR | 1 | rx_desteer_wrapper_inst/rx_fifo_lb_wrapper_inst/rx_fifo_lb_inst2/Small.rgraynext_9_s0/I1 |
6.069 | 0.567 | tINS | RR | 2 | rx_desteer_wrapper_inst/rx_fifo_lb_wrapper_inst/rx_fifo_lb_inst2/Small.rgraynext_9_s0/F |
6.481 | 0.413 | tNET | RR | 2 | rx_desteer_wrapper_inst/rx_fifo_lb_wrapper_inst/rx_fifo_lb_inst2/n550_s0/I0 |
7.076 | 0.595 | tINS | RF | 1 | rx_desteer_wrapper_inst/rx_fifo_lb_wrapper_inst/rx_fifo_lb_inst2/n550_s0/COUT |
7.076 | 0.000 | tNET | FF | 2 | rx_desteer_wrapper_inst/rx_fifo_lb_wrapper_inst/rx_fifo_lb_inst2/n551_s0/CIN |
7.126 | 0.050 | tINS | FR | 1 | rx_desteer_wrapper_inst/rx_fifo_lb_wrapper_inst/rx_fifo_lb_inst2/n551_s0/COUT |
7.126 | 0.000 | tNET | RR | 2 | rx_desteer_wrapper_inst/rx_fifo_lb_wrapper_inst/rx_fifo_lb_inst2/n552_s0/CIN |
7.176 | 0.050 | tINS | RR | 1 | rx_desteer_wrapper_inst/rx_fifo_lb_wrapper_inst/rx_fifo_lb_inst2/n552_s0/COUT |
7.589 | 0.413 | tNET | RR | 1 | rx_desteer_wrapper_inst/rx_fifo_lb_wrapper_inst/rx_fifo_lb_inst2/rempty_val_s1/I2 |
8.096 | 0.507 | tINS | RR | 1 | rx_desteer_wrapper_inst/rx_fifo_lb_wrapper_inst/rx_fifo_lb_inst2/rempty_val_s1/F |
8.509 | 0.413 | tNET | RR | 1 | rx_desteer_wrapper_inst/rx_fifo_lb_wrapper_inst/rx_fifo_lb_inst2/Empty_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | I_strm_clk | |||
10.000 | 0.000 | tCL | RR | 1 | I_strm_clk_ibuf/I |
10.000 | 0.000 | tINS | RR | 396 | I_strm_clk_ibuf/O |
10.413 | 0.413 | tNET | RR | 1 | rx_desteer_wrapper_inst/rx_fifo_lb_wrapper_inst/rx_fifo_lb_inst2/Empty_s0/CLK |
10.349 | -0.064 | tSu | 1 | rx_desteer_wrapper_inst/rx_fifo_lb_wrapper_inst/rx_fifo_lb_inst2/Empty_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 10 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Arrival Data Path Delay: | cell: 4.001, 49.421%; route: 3.712, 45.855%; tC2Q: 0.382, 4.724% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 2
Path Summary:Slack | 1.900 |
Data Arrival Time | 8.449 |
Data Required Time | 10.349 |
From | rx_desteer_wrapper_inst/rx_fifo_lb_wrapper_inst/rx_fifo_lb_inst3/Empty_s0 |
To | rx_desteer_wrapper_inst/rx_fifo_lb_wrapper_inst/rx_fifo_lb_inst3/Empty_s0 |
Launch Clk | I_strm_clk[R] |
Latch Clk | I_strm_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | I_strm_clk | |||
0.000 | 0.000 | tCL | RR | 1 | I_strm_clk_ibuf/I |
0.000 | 0.000 | tINS | RR | 396 | I_strm_clk_ibuf/O |
0.413 | 0.413 | tNET | RR | 1 | rx_desteer_wrapper_inst/rx_fifo_lb_wrapper_inst/rx_fifo_lb_inst3/Empty_s0/CLK |
0.795 | 0.382 | tC2Q | RR | 4 | rx_desteer_wrapper_inst/rx_fifo_lb_wrapper_inst/rx_fifo_lb_inst3/Empty_s0/Q |
1.207 | 0.413 | tNET | RR | 1 | rx_desteer_wrapper_inst/rx_fifo_lb_wrapper_inst/rx_fifo_lb_inst3/rbin_num_next_2_s4/I0 |
1.786 | 0.579 | tINS | RR | 7 | rx_desteer_wrapper_inst/rx_fifo_lb_wrapper_inst/rx_fifo_lb_inst3/rbin_num_next_2_s4/F |
2.199 | 0.413 | tNET | RR | 1 | rx_desteer_wrapper_inst/rx_fifo_lb_wrapper_inst/rx_fifo_lb_inst3/rbin_num_next_5_s4/I3 |
2.487 | 0.289 | tINS | RR | 7 | rx_desteer_wrapper_inst/rx_fifo_lb_wrapper_inst/rx_fifo_lb_inst3/rbin_num_next_5_s4/F |
2.900 | 0.413 | tNET | RR | 1 | rx_desteer_wrapper_inst/rx_fifo_lb_wrapper_inst/rx_fifo_lb_inst3/rbin_num_next_7_s4/I2 |
3.408 | 0.507 | tINS | RR | 5 | rx_desteer_wrapper_inst/rx_fifo_lb_wrapper_inst/rx_fifo_lb_inst3/rbin_num_next_7_s4/F |
3.820 | 0.413 | tNET | RR | 1 | rx_desteer_wrapper_inst/rx_fifo_lb_wrapper_inst/rx_fifo_lb_inst3/rbin_num_next_10_s4/I3 |
4.109 | 0.289 | tINS | RR | 7 | rx_desteer_wrapper_inst/rx_fifo_lb_wrapper_inst/rx_fifo_lb_inst3/rbin_num_next_10_s4/F |
4.521 | 0.413 | tNET | RR | 1 | rx_desteer_wrapper_inst/rx_fifo_lb_wrapper_inst/rx_fifo_lb_inst3/rbin_num_next_11_s3/I1 |
5.089 | 0.567 | tINS | RR | 2 | rx_desteer_wrapper_inst/rx_fifo_lb_wrapper_inst/rx_fifo_lb_inst3/rbin_num_next_11_s3/F |
5.501 | 0.413 | tNET | RR | 1 | rx_desteer_wrapper_inst/rx_fifo_lb_wrapper_inst/rx_fifo_lb_inst3/Small.rgraynext_9_s1/I2 |
6.009 | 0.507 | tINS | RR | 2 | rx_desteer_wrapper_inst/rx_fifo_lb_wrapper_inst/rx_fifo_lb_inst3/Small.rgraynext_9_s1/F |
6.421 | 0.413 | tNET | RR | 2 | rx_desteer_wrapper_inst/rx_fifo_lb_wrapper_inst/rx_fifo_lb_inst3/n550_s0/I0 |
7.016 | 0.595 | tINS | RF | 1 | rx_desteer_wrapper_inst/rx_fifo_lb_wrapper_inst/rx_fifo_lb_inst3/n550_s0/COUT |
7.016 | 0.000 | tNET | FF | 2 | rx_desteer_wrapper_inst/rx_fifo_lb_wrapper_inst/rx_fifo_lb_inst3/n551_s0/CIN |
7.066 | 0.050 | tINS | FR | 1 | rx_desteer_wrapper_inst/rx_fifo_lb_wrapper_inst/rx_fifo_lb_inst3/n551_s0/COUT |
7.066 | 0.000 | tNET | RR | 2 | rx_desteer_wrapper_inst/rx_fifo_lb_wrapper_inst/rx_fifo_lb_inst3/n552_s0/CIN |
7.116 | 0.050 | tINS | RR | 1 | rx_desteer_wrapper_inst/rx_fifo_lb_wrapper_inst/rx_fifo_lb_inst3/n552_s0/COUT |
7.529 | 0.413 | tNET | RR | 1 | rx_desteer_wrapper_inst/rx_fifo_lb_wrapper_inst/rx_fifo_lb_inst3/rempty_val_s1/I2 |
8.036 | 0.507 | tINS | RR | 1 | rx_desteer_wrapper_inst/rx_fifo_lb_wrapper_inst/rx_fifo_lb_inst3/rempty_val_s1/F |
8.449 | 0.413 | tNET | RR | 1 | rx_desteer_wrapper_inst/rx_fifo_lb_wrapper_inst/rx_fifo_lb_inst3/Empty_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | I_strm_clk | |||
10.000 | 0.000 | tCL | RR | 1 | I_strm_clk_ibuf/I |
10.000 | 0.000 | tINS | RR | 396 | I_strm_clk_ibuf/O |
10.413 | 0.413 | tNET | RR | 1 | rx_desteer_wrapper_inst/rx_fifo_lb_wrapper_inst/rx_fifo_lb_inst3/Empty_s0/CLK |
10.349 | -0.064 | tSu | 1 | rx_desteer_wrapper_inst/rx_fifo_lb_wrapper_inst/rx_fifo_lb_inst3/Empty_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 10 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Arrival Data Path Delay: | cell: 3.941, 49.043%; route: 3.712, 46.197%; tC2Q: 0.382, 4.760% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 3
Path Summary:Slack | 2.285 |
Data Arrival Time | 8.064 |
Data Required Time | 10.349 |
From | rx_desteer_wrapper_inst/rx_desteering_inst/rx_framesyn_linefull_gen_inst/H_cnt_0_s0 |
To | rx_desteer_wrapper_inst/rx_desteering_inst/rx_framesyn_linefull_gen_inst/H_cnt_1_s0 |
Launch Clk | I_strm_clk[R] |
Latch Clk | I_strm_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | I_strm_clk | |||
0.000 | 0.000 | tCL | RR | 1 | I_strm_clk_ibuf/I |
0.000 | 0.000 | tINS | RR | 396 | I_strm_clk_ibuf/O |
0.413 | 0.413 | tNET | RR | 1 | rx_desteer_wrapper_inst/rx_desteering_inst/rx_framesyn_linefull_gen_inst/H_cnt_0_s0/CLK |
0.795 | 0.382 | tC2Q | RR | 11 | rx_desteer_wrapper_inst/rx_desteering_inst/rx_framesyn_linefull_gen_inst/H_cnt_0_s0/Q |
1.207 | 0.413 | tNET | RR | 1 | rx_desteer_wrapper_inst/rx_desteering_inst/rx_framesyn_linefull_gen_inst/n212_s37/I0 |
1.786 | 0.579 | tINS | RR | 1 | rx_desteer_wrapper_inst/rx_desteering_inst/rx_framesyn_linefull_gen_inst/n212_s37/F |
2.199 | 0.413 | tNET | RR | 1 | rx_desteer_wrapper_inst/rx_desteering_inst/rx_framesyn_linefull_gen_inst/n212_s30/I1 |
2.766 | 0.567 | tINS | RR | 1 | rx_desteer_wrapper_inst/rx_desteering_inst/rx_framesyn_linefull_gen_inst/n212_s30/F |
3.179 | 0.413 | tNET | RR | 1 | rx_desteer_wrapper_inst/rx_desteering_inst/rx_framesyn_linefull_gen_inst/n212_s18/I2 |
3.686 | 0.507 | tINS | RR | 1 | rx_desteer_wrapper_inst/rx_desteering_inst/rx_framesyn_linefull_gen_inst/n212_s18/F |
4.099 | 0.413 | tNET | RR | 1 | rx_desteer_wrapper_inst/rx_desteering_inst/rx_framesyn_linefull_gen_inst/n212_s10/I0 |
4.678 | 0.579 | tINS | RR | 1 | rx_desteer_wrapper_inst/rx_desteering_inst/rx_framesyn_linefull_gen_inst/n212_s10/F |
5.090 | 0.413 | tNET | RR | 1 | rx_desteer_wrapper_inst/rx_desteering_inst/rx_framesyn_linefull_gen_inst/n212_s4/I0 |
5.669 | 0.579 | tINS | RR | 9 | rx_desteer_wrapper_inst/rx_desteering_inst/rx_framesyn_linefull_gen_inst/n212_s4/F |
6.081 | 0.413 | tNET | RR | 1 | rx_desteer_wrapper_inst/rx_desteering_inst/rx_framesyn_linefull_gen_inst/V_cnt_15_s4/I0 |
6.660 | 0.579 | tINS | RR | 10 | rx_desteer_wrapper_inst/rx_desteering_inst/rx_framesyn_linefull_gen_inst/V_cnt_15_s4/F |
7.073 | 0.413 | tNET | RR | 1 | rx_desteer_wrapper_inst/rx_desteering_inst/rx_framesyn_linefull_gen_inst/n226_s2/I0 |
7.651 | 0.579 | tINS | RR | 1 | rx_desteer_wrapper_inst/rx_desteering_inst/rx_framesyn_linefull_gen_inst/n226_s2/F |
8.064 | 0.413 | tNET | RR | 1 | rx_desteer_wrapper_inst/rx_desteering_inst/rx_framesyn_linefull_gen_inst/H_cnt_1_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | I_strm_clk | |||
10.000 | 0.000 | tCL | RR | 1 | I_strm_clk_ibuf/I |
10.000 | 0.000 | tINS | RR | 396 | I_strm_clk_ibuf/O |
10.413 | 0.413 | tNET | RR | 1 | rx_desteer_wrapper_inst/rx_desteering_inst/rx_framesyn_linefull_gen_inst/H_cnt_1_s0/CLK |
10.349 | -0.064 | tSu | 1 | rx_desteer_wrapper_inst/rx_desteering_inst/rx_framesyn_linefull_gen_inst/H_cnt_1_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 8 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Arrival Data Path Delay: | cell: 3.969, 51.871%; route: 3.300, 43.130%; tC2Q: 0.382, 4.999% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 4
Path Summary:Slack | 2.285 |
Data Arrival Time | 8.064 |
Data Required Time | 10.349 |
From | rx_desteer_wrapper_inst/rx_desteering_inst/rx_framesyn_linefull_gen_inst/H_cnt_0_s0 |
To | rx_desteer_wrapper_inst/rx_desteering_inst/rx_framesyn_linefull_gen_inst/H_cnt_3_s0 |
Launch Clk | I_strm_clk[R] |
Latch Clk | I_strm_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | I_strm_clk | |||
0.000 | 0.000 | tCL | RR | 1 | I_strm_clk_ibuf/I |
0.000 | 0.000 | tINS | RR | 396 | I_strm_clk_ibuf/O |
0.413 | 0.413 | tNET | RR | 1 | rx_desteer_wrapper_inst/rx_desteering_inst/rx_framesyn_linefull_gen_inst/H_cnt_0_s0/CLK |
0.795 | 0.382 | tC2Q | RR | 11 | rx_desteer_wrapper_inst/rx_desteering_inst/rx_framesyn_linefull_gen_inst/H_cnt_0_s0/Q |
1.207 | 0.413 | tNET | RR | 1 | rx_desteer_wrapper_inst/rx_desteering_inst/rx_framesyn_linefull_gen_inst/n212_s37/I0 |
1.786 | 0.579 | tINS | RR | 1 | rx_desteer_wrapper_inst/rx_desteering_inst/rx_framesyn_linefull_gen_inst/n212_s37/F |
2.199 | 0.413 | tNET | RR | 1 | rx_desteer_wrapper_inst/rx_desteering_inst/rx_framesyn_linefull_gen_inst/n212_s30/I1 |
2.766 | 0.567 | tINS | RR | 1 | rx_desteer_wrapper_inst/rx_desteering_inst/rx_framesyn_linefull_gen_inst/n212_s30/F |
3.179 | 0.413 | tNET | RR | 1 | rx_desteer_wrapper_inst/rx_desteering_inst/rx_framesyn_linefull_gen_inst/n212_s18/I2 |
3.686 | 0.507 | tINS | RR | 1 | rx_desteer_wrapper_inst/rx_desteering_inst/rx_framesyn_linefull_gen_inst/n212_s18/F |
4.099 | 0.413 | tNET | RR | 1 | rx_desteer_wrapper_inst/rx_desteering_inst/rx_framesyn_linefull_gen_inst/n212_s10/I0 |
4.678 | 0.579 | tINS | RR | 1 | rx_desteer_wrapper_inst/rx_desteering_inst/rx_framesyn_linefull_gen_inst/n212_s10/F |
5.090 | 0.413 | tNET | RR | 1 | rx_desteer_wrapper_inst/rx_desteering_inst/rx_framesyn_linefull_gen_inst/n212_s4/I0 |
5.669 | 0.579 | tINS | RR | 9 | rx_desteer_wrapper_inst/rx_desteering_inst/rx_framesyn_linefull_gen_inst/n212_s4/F |
6.081 | 0.413 | tNET | RR | 1 | rx_desteer_wrapper_inst/rx_desteering_inst/rx_framesyn_linefull_gen_inst/V_cnt_15_s4/I0 |
6.660 | 0.579 | tINS | RR | 10 | rx_desteer_wrapper_inst/rx_desteering_inst/rx_framesyn_linefull_gen_inst/V_cnt_15_s4/F |
7.073 | 0.413 | tNET | RR | 1 | rx_desteer_wrapper_inst/rx_desteering_inst/rx_framesyn_linefull_gen_inst/n224_s2/I0 |
7.651 | 0.579 | tINS | RR | 1 | rx_desteer_wrapper_inst/rx_desteering_inst/rx_framesyn_linefull_gen_inst/n224_s2/F |
8.064 | 0.413 | tNET | RR | 1 | rx_desteer_wrapper_inst/rx_desteering_inst/rx_framesyn_linefull_gen_inst/H_cnt_3_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | I_strm_clk | |||
10.000 | 0.000 | tCL | RR | 1 | I_strm_clk_ibuf/I |
10.000 | 0.000 | tINS | RR | 396 | I_strm_clk_ibuf/O |
10.413 | 0.413 | tNET | RR | 1 | rx_desteer_wrapper_inst/rx_desteering_inst/rx_framesyn_linefull_gen_inst/H_cnt_3_s0/CLK |
10.349 | -0.064 | tSu | 1 | rx_desteer_wrapper_inst/rx_desteering_inst/rx_framesyn_linefull_gen_inst/H_cnt_3_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 8 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Arrival Data Path Delay: | cell: 3.969, 51.871%; route: 3.300, 43.130%; tC2Q: 0.382, 4.999% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 5
Path Summary:Slack | 2.285 |
Data Arrival Time | 8.064 |
Data Required Time | 10.349 |
From | rx_desteer_wrapper_inst/rx_desteering_inst/rx_framesyn_linefull_gen_inst/H_cnt_0_s0 |
To | rx_desteer_wrapper_inst/rx_desteering_inst/rx_framesyn_linefull_gen_inst/H_cnt_4_s0 |
Launch Clk | I_strm_clk[R] |
Latch Clk | I_strm_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | I_strm_clk | |||
0.000 | 0.000 | tCL | RR | 1 | I_strm_clk_ibuf/I |
0.000 | 0.000 | tINS | RR | 396 | I_strm_clk_ibuf/O |
0.413 | 0.413 | tNET | RR | 1 | rx_desteer_wrapper_inst/rx_desteering_inst/rx_framesyn_linefull_gen_inst/H_cnt_0_s0/CLK |
0.795 | 0.382 | tC2Q | RR | 11 | rx_desteer_wrapper_inst/rx_desteering_inst/rx_framesyn_linefull_gen_inst/H_cnt_0_s0/Q |
1.207 | 0.413 | tNET | RR | 1 | rx_desteer_wrapper_inst/rx_desteering_inst/rx_framesyn_linefull_gen_inst/n212_s37/I0 |
1.786 | 0.579 | tINS | RR | 1 | rx_desteer_wrapper_inst/rx_desteering_inst/rx_framesyn_linefull_gen_inst/n212_s37/F |
2.199 | 0.413 | tNET | RR | 1 | rx_desteer_wrapper_inst/rx_desteering_inst/rx_framesyn_linefull_gen_inst/n212_s30/I1 |
2.766 | 0.567 | tINS | RR | 1 | rx_desteer_wrapper_inst/rx_desteering_inst/rx_framesyn_linefull_gen_inst/n212_s30/F |
3.179 | 0.413 | tNET | RR | 1 | rx_desteer_wrapper_inst/rx_desteering_inst/rx_framesyn_linefull_gen_inst/n212_s18/I2 |
3.686 | 0.507 | tINS | RR | 1 | rx_desteer_wrapper_inst/rx_desteering_inst/rx_framesyn_linefull_gen_inst/n212_s18/F |
4.099 | 0.413 | tNET | RR | 1 | rx_desteer_wrapper_inst/rx_desteering_inst/rx_framesyn_linefull_gen_inst/n212_s10/I0 |
4.678 | 0.579 | tINS | RR | 1 | rx_desteer_wrapper_inst/rx_desteering_inst/rx_framesyn_linefull_gen_inst/n212_s10/F |
5.090 | 0.413 | tNET | RR | 1 | rx_desteer_wrapper_inst/rx_desteering_inst/rx_framesyn_linefull_gen_inst/n212_s4/I0 |
5.669 | 0.579 | tINS | RR | 9 | rx_desteer_wrapper_inst/rx_desteering_inst/rx_framesyn_linefull_gen_inst/n212_s4/F |
6.081 | 0.413 | tNET | RR | 1 | rx_desteer_wrapper_inst/rx_desteering_inst/rx_framesyn_linefull_gen_inst/V_cnt_15_s4/I0 |
6.660 | 0.579 | tINS | RR | 10 | rx_desteer_wrapper_inst/rx_desteering_inst/rx_framesyn_linefull_gen_inst/V_cnt_15_s4/F |
7.073 | 0.413 | tNET | RR | 1 | rx_desteer_wrapper_inst/rx_desteering_inst/rx_framesyn_linefull_gen_inst/n223_s2/I0 |
7.651 | 0.579 | tINS | RR | 1 | rx_desteer_wrapper_inst/rx_desteering_inst/rx_framesyn_linefull_gen_inst/n223_s2/F |
8.064 | 0.413 | tNET | RR | 1 | rx_desteer_wrapper_inst/rx_desteering_inst/rx_framesyn_linefull_gen_inst/H_cnt_4_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | I_strm_clk | |||
10.000 | 0.000 | tCL | RR | 1 | I_strm_clk_ibuf/I |
10.000 | 0.000 | tINS | RR | 396 | I_strm_clk_ibuf/O |
10.413 | 0.413 | tNET | RR | 1 | rx_desteer_wrapper_inst/rx_desteering_inst/rx_framesyn_linefull_gen_inst/H_cnt_4_s0/CLK |
10.349 | -0.064 | tSu | 1 | rx_desteer_wrapper_inst/rx_desteering_inst/rx_framesyn_linefull_gen_inst/H_cnt_4_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 8 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Arrival Data Path Delay: | cell: 3.969, 51.871%; route: 3.300, 43.130%; tC2Q: 0.382, 4.999% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |