Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\EDP_DECODE\data\edp_decoder_top.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\EDP_DECODE\data\edp_decoder_wrapper.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.9.03 (64-bit) |
| Part Number | GW5AST-LV138FPG676AES |
| Device | GW5AST-138 |
| Device Version | B |
| Created Time | Mon May 6 15:16:06 2024 |
| Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | EDP_Decoder_Top |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.578s, Elapsed time = 0h 0m 0.665s, Peak memory usage = 123.016MB Running netlist conversion: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.072s, Peak memory usage = 123.016MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.296s, Elapsed time = 0h 0m 0.305s, Peak memory usage = 123.016MB Optimizing Phase 1: CPU time = 0h 0m 0.296s, Elapsed time = 0h 0m 0.295s, Peak memory usage = 123.016MB Optimizing Phase 2: CPU time = 0h 0m 0.375s, Elapsed time = 0h 0m 0.375s, Peak memory usage = 123.016MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.143s, Peak memory usage = 123.016MB Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 123.016MB Inferring Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.046s, Peak memory usage = 123.016MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 123.016MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.375s, Elapsed time = 0h 0m 0.366s, Peak memory usage = 123.016MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.095s, Peak memory usage = 123.016MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.074s, Peak memory usage = 123.016MB Tech-Mapping Phase 3: CPU time = 0h 0m 9s, Elapsed time = 0h 0m 9s, Peak memory usage = 149.727MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.562s, Elapsed time = 0h 0m 0.584s, Peak memory usage = 149.727MB Generate output files: CPU time = 0h 0m 0.531s, Elapsed time = 0h 0m 0.567s, Peak memory usage = 163.559MB |
| Total Time and Memory Usage | CPU time = 0h 0m 12s, Elapsed time = 0h 0m 12s, Peak memory usage = 163.559MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 562 |
| I/O Buf | 562 |
| IBUF | 148 |
| OBUF | 414 |
| Register | 3149 |
| DFFSE | 116 |
| DFFRE | 100 |
| DFFPE | 14 |
| DFFCE | 2919 |
| LUT | 4492 |
| LUT2 | 315 |
| LUT3 | 1449 |
| LUT4 | 2728 |
| INV | 4 |
| INV | 4 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 4496(4496 LUT, 0 ALU) / 138240 | 4% |
| Register | 3149 / 139140 | 3% |
| --Register as Latch | 0 / 139140 | 0% |
| --Register as FF | 3149 / 139140 | 3% |
| BSRAM | 0 / 340 | 0% |
Timing
Clock Summary:
| Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|
| I_ls_clk | Base | 10.000 | 100.0 | 0.000 | 5.000 | I_ls_clk_ibuf/I |
Max Frequency Summary:
| No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | I_ls_clk | 100.000(MHz) | 163.901(MHz) | 6 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 3.899 |
| Data Arrival Time | 6.141 |
| Data Required Time | 10.040 |
| From | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/I_data_d3_9_s1 |
| To | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/sr16_2_0_s0 |
| Launch Clk | I_ls_clk[R] |
| Latch Clk | I_ls_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | I_ls_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | I_ls_clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 3149 | I_ls_clk_ibuf/O |
| 0.413 | 0.413 | tNET | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/I_data_d3_9_s1/CLK |
| 0.795 | 0.382 | tC2Q | RR | 4 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/I_data_d3_9_s1/Q |
| 1.207 | 0.413 | tNET | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/n2281_s25/I0 |
| 1.786 | 0.579 | tINS | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/n2281_s25/F |
| 2.199 | 0.413 | tNET | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/n2281_s12/I1 |
| 2.766 | 0.567 | tINS | RR | 2 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/n2281_s12/F |
| 3.179 | 0.413 | tNET | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/n2281_s4/I1 |
| 3.746 | 0.567 | tINS | RR | 3 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/n2281_s4/F |
| 4.159 | 0.413 | tNET | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/n2281_s2/I0 |
| 4.738 | 0.579 | tINS | RR | 4 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/n2281_s2/F |
| 5.150 | 0.413 | tNET | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/n2297_s13/I0 |
| 5.729 | 0.579 | tINS | RR | 15 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/n2297_s13/F |
| 6.141 | 0.413 | tNET | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/sr16_2_0_s0/SET |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | I_ls_clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | I_ls_clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 3149 | I_ls_clk_ibuf/O |
| 10.413 | 0.413 | tNET | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/sr16_2_0_s0/CLK |
| 10.040 | -0.373 | tSu | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/sr16_2_0_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 2.871, 50.120%; route: 2.475, 43.203%; tC2Q: 0.382, 6.677% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 2
Path Summary:| Slack | 3.899 |
| Data Arrival Time | 6.141 |
| Data Required Time | 10.040 |
| From | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/I_data_d3_9_s1 |
| To | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/sr16_2_1_s0 |
| Launch Clk | I_ls_clk[R] |
| Latch Clk | I_ls_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | I_ls_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | I_ls_clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 3149 | I_ls_clk_ibuf/O |
| 0.413 | 0.413 | tNET | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/I_data_d3_9_s1/CLK |
| 0.795 | 0.382 | tC2Q | RR | 4 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/I_data_d3_9_s1/Q |
| 1.207 | 0.413 | tNET | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/n2281_s25/I0 |
| 1.786 | 0.579 | tINS | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/n2281_s25/F |
| 2.199 | 0.413 | tNET | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/n2281_s12/I1 |
| 2.766 | 0.567 | tINS | RR | 2 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/n2281_s12/F |
| 3.179 | 0.413 | tNET | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/n2281_s4/I1 |
| 3.746 | 0.567 | tINS | RR | 3 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/n2281_s4/F |
| 4.159 | 0.413 | tNET | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/n2281_s2/I0 |
| 4.738 | 0.579 | tINS | RR | 4 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/n2281_s2/F |
| 5.150 | 0.413 | tNET | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/n2297_s13/I0 |
| 5.729 | 0.579 | tINS | RR | 15 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/n2297_s13/F |
| 6.141 | 0.413 | tNET | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/sr16_2_1_s0/SET |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | I_ls_clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | I_ls_clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 3149 | I_ls_clk_ibuf/O |
| 10.413 | 0.413 | tNET | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/sr16_2_1_s0/CLK |
| 10.040 | -0.373 | tSu | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/sr16_2_1_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 2.871, 50.120%; route: 2.475, 43.203%; tC2Q: 0.382, 6.677% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 3
Path Summary:| Slack | 3.899 |
| Data Arrival Time | 6.141 |
| Data Required Time | 10.040 |
| From | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/I_data_d3_9_s1 |
| To | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/sr16_2_2_s0 |
| Launch Clk | I_ls_clk[R] |
| Latch Clk | I_ls_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | I_ls_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | I_ls_clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 3149 | I_ls_clk_ibuf/O |
| 0.413 | 0.413 | tNET | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/I_data_d3_9_s1/CLK |
| 0.795 | 0.382 | tC2Q | RR | 4 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/I_data_d3_9_s1/Q |
| 1.207 | 0.413 | tNET | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/n2281_s25/I0 |
| 1.786 | 0.579 | tINS | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/n2281_s25/F |
| 2.199 | 0.413 | tNET | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/n2281_s12/I1 |
| 2.766 | 0.567 | tINS | RR | 2 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/n2281_s12/F |
| 3.179 | 0.413 | tNET | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/n2281_s4/I1 |
| 3.746 | 0.567 | tINS | RR | 3 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/n2281_s4/F |
| 4.159 | 0.413 | tNET | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/n2281_s2/I0 |
| 4.738 | 0.579 | tINS | RR | 4 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/n2281_s2/F |
| 5.150 | 0.413 | tNET | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/n2297_s13/I0 |
| 5.729 | 0.579 | tINS | RR | 15 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/n2297_s13/F |
| 6.141 | 0.413 | tNET | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/sr16_2_2_s0/SET |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | I_ls_clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | I_ls_clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 3149 | I_ls_clk_ibuf/O |
| 10.413 | 0.413 | tNET | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/sr16_2_2_s0/CLK |
| 10.040 | -0.373 | tSu | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/sr16_2_2_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 2.871, 50.120%; route: 2.475, 43.203%; tC2Q: 0.382, 6.677% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 4
Path Summary:| Slack | 3.899 |
| Data Arrival Time | 6.141 |
| Data Required Time | 10.040 |
| From | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/I_data_d3_9_s1 |
| To | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/sr16_2_3_s0 |
| Launch Clk | I_ls_clk[R] |
| Latch Clk | I_ls_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | I_ls_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | I_ls_clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 3149 | I_ls_clk_ibuf/O |
| 0.413 | 0.413 | tNET | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/I_data_d3_9_s1/CLK |
| 0.795 | 0.382 | tC2Q | RR | 4 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/I_data_d3_9_s1/Q |
| 1.207 | 0.413 | tNET | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/n2281_s25/I0 |
| 1.786 | 0.579 | tINS | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/n2281_s25/F |
| 2.199 | 0.413 | tNET | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/n2281_s12/I1 |
| 2.766 | 0.567 | tINS | RR | 2 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/n2281_s12/F |
| 3.179 | 0.413 | tNET | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/n2281_s4/I1 |
| 3.746 | 0.567 | tINS | RR | 3 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/n2281_s4/F |
| 4.159 | 0.413 | tNET | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/n2281_s2/I0 |
| 4.738 | 0.579 | tINS | RR | 4 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/n2281_s2/F |
| 5.150 | 0.413 | tNET | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/n2297_s13/I0 |
| 5.729 | 0.579 | tINS | RR | 15 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/n2297_s13/F |
| 6.141 | 0.413 | tNET | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/sr16_2_3_s0/RESET |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | I_ls_clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | I_ls_clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 3149 | I_ls_clk_ibuf/O |
| 10.413 | 0.413 | tNET | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/sr16_2_3_s0/CLK |
| 10.040 | -0.373 | tSu | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/sr16_2_3_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 2.871, 50.120%; route: 2.475, 43.203%; tC2Q: 0.382, 6.677% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 5
Path Summary:| Slack | 3.899 |
| Data Arrival Time | 6.141 |
| Data Required Time | 10.040 |
| From | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/I_data_d3_9_s1 |
| To | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/sr16_2_4_s0 |
| Launch Clk | I_ls_clk[R] |
| Latch Clk | I_ls_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | I_ls_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | I_ls_clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 3149 | I_ls_clk_ibuf/O |
| 0.413 | 0.413 | tNET | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/I_data_d3_9_s1/CLK |
| 0.795 | 0.382 | tC2Q | RR | 4 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/I_data_d3_9_s1/Q |
| 1.207 | 0.413 | tNET | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/n2281_s25/I0 |
| 1.786 | 0.579 | tINS | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/n2281_s25/F |
| 2.199 | 0.413 | tNET | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/n2281_s12/I1 |
| 2.766 | 0.567 | tINS | RR | 2 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/n2281_s12/F |
| 3.179 | 0.413 | tNET | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/n2281_s4/I1 |
| 3.746 | 0.567 | tINS | RR | 3 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/n2281_s4/F |
| 4.159 | 0.413 | tNET | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/n2281_s2/I0 |
| 4.738 | 0.579 | tINS | RR | 4 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/n2281_s2/F |
| 5.150 | 0.413 | tNET | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/n2297_s13/I0 |
| 5.729 | 0.579 | tINS | RR | 15 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/n2297_s13/F |
| 6.141 | 0.413 | tNET | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/sr16_2_4_s0/SET |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | I_ls_clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | I_ls_clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 3149 | I_ls_clk_ibuf/O |
| 10.413 | 0.413 | tNET | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/sr16_2_4_s0/CLK |
| 10.040 | -0.373 | tSu | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble40_inst/sr16_2_4_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 2.871, 50.120%; route: 2.475, 43.203%; tC2Q: 0.382, 6.677% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |