Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | D:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\PSRAM\data\PSRAM_TOP.v D:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\PSRAM\data\psram_code.v |
GowinSynthesis Constraints File | --- |
Tool Version | V1.9.9.01 (64-bit) |
Part Number | GW1NSR-LV4CMG64PC7/I6 |
Device | GW1NSR-4C |
Created Time | Mon Feb 19 10:19:08 2024 |
Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | PSRAM_Memory_Interface_Top |
Synthesis Process | Running parser: CPU time = 0h 0m 0.343s, Elapsed time = 0h 0m 0.436s, Peak memory usage = 106.867MB Running netlist conversion: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.02s, Peak memory usage = 106.867MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.071s, Peak memory usage = 106.867MB Optimizing Phase 1: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.051s, Peak memory usage = 106.867MB Optimizing Phase 2: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.071s, Peak memory usage = 106.867MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.035s, Peak memory usage = 106.867MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 106.867MB Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 106.867MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 106.867MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.129s, Peak memory usage = 106.867MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.023s, Peak memory usage = 106.867MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.015s, Peak memory usage = 106.867MB Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 136.113MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.176s, Peak memory usage = 136.113MB Generate output files: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.241s, Peak memory usage = 136.113MB |
Total Time and Memory Usage | CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 136.113MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 166 |
Embedded Port | 26 |
I/O Buf | 191 |
    IBUF | 99 |
    OBUF | 73 |
    IOBUF | 18 |
    ELVDS_OBUF | 1 |
Register | 1136 |
    DFFE | 464 |
    DFFRE | 112 |
    DFFP | 2 |
    DFFPE | 8 |
    DFFC | 318 |
    DFFCE | 232 |
LUT | 1304 |
    LUT2 | 233 |
    LUT3 | 625 |
    LUT4 | 446 |
ALU | 46 |
    ALU | 46 |
INV | 5 |
    INV | 5 |
IOLOGIC | 58 |
    IDES4 | 16 |
    OSER4 | 23 |
    IODELAY | 19 |
CLOCK | 2 |
    CLKDIV | 1 |
    DHCEN | 1 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 1355(1309 LUT, 46 ALU) / 4608 | 30% |
Register | 1136 / 3699 | 31% |
  --Register as Latch | 0 / 3699 | 0% |
  --Register as FF | 1136 / 3699 | 31% |
BSRAM | 0 / 10 | 0% |
Timing
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|
memory_clk | Base | 20.000 | 50.0 | 0.000 | 10.000 | memory_clk_ibuf/I | ||
clk | Base | 20.000 | 50.0 | 0.000 | 10.000 | clk_ibuf/I | ||
u_psram_top/clkdiv/CLKOUT.default_gen_clk | Generated | 40.000 | 25.0 | 0.000 | 20.000 | memory_clk_ibuf/I | memory_clk | u_psram_top/clkdiv/CLKOUT |
Max Frequency Summary:
No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | clk | 50.000(MHz) | 113.288(MHz) | 6 | TOP |
2 | u_psram_top/clkdiv/CLKOUT.default_gen_clk | 25.000(MHz) | 111.408(MHz) | 6 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | 8.906 |
Data Arrival Time | 2.317 |
Data Required Time | 11.223 |
From | u_psram_top/u_psram_sync/cs_memsync_4_s0 |
To | u_psram_top/u_dqce_clk_x2p |
Launch Clk | clk[F] |
Latch Clk | memory_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.728 | 0.728 | tINS | RR | 31 | clk_ibuf/O |
1.266 | 0.538 | tNET | RR | 1 | u_psram_top/u_psram_sync/cs_memsync_4_s0/CLK |
1.605 | 0.340 | tC2Q | RF | 8 | u_psram_top/u_psram_sync/cs_memsync_4_s0/Q |
2.317 | 0.711 | tNET | FF | 1 | u_psram_top/u_dqce_clk_x2p/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | memory_clk | |||
10.000 | 0.000 | tCL | FF | 1 | memory_clk_ibuf/I |
10.729 | 0.729 | tINS | FF | 1 | memory_clk_ibuf/O |
11.441 | 0.711 | tNET | FF | 3 | u_psram_top/u_dqce_clk_x2p/CLKIN |
11.411 | -0.030 | tUnc | u_psram_top/u_dqce_clk_x2p | ||
11.223 | -0.188 | tSu | 1 | u_psram_top/u_dqce_clk_x2p |
Clock Skew: | 0.175 |
Setup Relationship: | 10.000 |
Logic Level: | 1 |
Arrival Clock Path Delay: | cell: 0.728, 57.491%; route: 0.538, 42.509% |
Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.711, 67.685%; tC2Q: 0.340, 32.315% |
Required Clock Path Delay: | cell: 0.728, 57.491%; route: 0.538, 42.509% |
Path 2
Path Summary:Slack | 11.173 |
Data Arrival Time | 9.796 |
Data Required Time | 20.969 |
From | u_psram_top/u_psram_sync/count_1_s0 |
To | u_psram_top/u_psram_sync/count_0_s0 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.728 | 0.728 | tINS | RR | 31 | clk_ibuf/O |
1.266 | 0.538 | tNET | RR | 1 | u_psram_top/u_psram_sync/count_1_s0/CLK |
1.605 | 0.340 | tC2Q | RF | 6 | u_psram_top/u_psram_sync/count_1_s0/Q |
2.317 | 0.711 | tNET | FF | 1 | u_psram_top/u_psram_sync/n327_s13/I1 |
3.131 | 0.814 | tINS | FF | 6 | u_psram_top/u_psram_sync/n327_s13/F |
3.842 | 0.711 | tNET | FF | 1 | u_psram_top/u_psram_sync/n349_s8/I0 |
4.607 | 0.765 | tINS | FF | 1 | u_psram_top/u_psram_sync/n349_s8/F |
5.318 | 0.711 | tNET | FF | 1 | u_psram_top/u_psram_sync/n349_s6/I0 |
6.083 | 0.765 | tINS | FF | 3 | u_psram_top/u_psram_sync/n349_s6/F |
6.794 | 0.711 | tNET | FF | 1 | u_psram_top/u_psram_sync/n390_s4/I0 |
7.559 | 0.765 | tINS | FF | 3 | u_psram_top/u_psram_sync/n390_s4/F |
8.270 | 0.711 | tNET | FF | 1 | u_psram_top/u_psram_sync/n390_s3/I1 |
9.085 | 0.814 | tINS | FF | 1 | u_psram_top/u_psram_sync/n390_s3/F |
9.796 | 0.711 | tNET | FF | 1 | u_psram_top/u_psram_sync/count_0_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
20.000 | 0.000 | clk | |||
20.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
20.728 | 0.728 | tINS | RR | 31 | clk_ibuf/O |
21.266 | 0.538 | tNET | RR | 1 | u_psram_top/u_psram_sync/count_0_s0/CLK |
20.969 | -0.296 | tSu | 1 | u_psram_top/u_psram_sync/count_0_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 20.000 |
Logic Level: | 6 |
Arrival Clock Path Delay: | cell: 0.728, 57.491%; route: 0.538, 42.509% |
Arrival Data Path Delay: | cell: 3.923, 45.985%; route: 4.268, 50.034%; tC2Q: 0.340, 3.981% |
Required Clock Path Delay: | cell: 0.728, 57.491%; route: 0.538, 42.509% |
Path 3
Path Summary:Slack | 11.229 |
Data Arrival Time | 9.740 |
Data Required Time | 20.969 |
From | u_psram_top/u_psram_sync/lock_cnt_1_s3 |
To | u_psram_top/u_psram_sync/lock_cnt_12_s3 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.728 | 0.728 | tINS | RR | 31 | clk_ibuf/O |
1.266 | 0.538 | tNET | RR | 1 | u_psram_top/u_psram_sync/lock_cnt_1_s3/CLK |
1.605 | 0.340 | tC2Q | RF | 5 | u_psram_top/u_psram_sync/lock_cnt_1_s3/Q |
2.317 | 0.711 | tNET | FF | 1 | u_psram_top/u_psram_sync/n47_s2/I1 |
3.131 | 0.814 | tINS | FF | 4 | u_psram_top/u_psram_sync/n47_s2/F |
3.842 | 0.711 | tNET | FF | 1 | u_psram_top/u_psram_sync/n44_s3/I1 |
4.657 | 0.814 | tINS | FF | 3 | u_psram_top/u_psram_sync/n44_s3/F |
5.368 | 0.711 | tNET | FF | 1 | u_psram_top/u_psram_sync/n43_s2/I1 |
6.182 | 0.814 | tINS | FF | 4 | u_psram_top/u_psram_sync/n43_s2/F |
6.894 | 0.711 | tNET | FF | 1 | u_psram_top/u_psram_sync/n39_s2/I2 |
7.503 | 0.609 | tINS | FF | 4 | u_psram_top/u_psram_sync/n39_s2/F |
8.214 | 0.711 | tNET | FF | 1 | u_psram_top/u_psram_sync/n39_s5/I1 |
9.028 | 0.814 | tINS | FF | 1 | u_psram_top/u_psram_sync/n39_s5/F |
9.740 | 0.711 | tNET | FF | 1 | u_psram_top/u_psram_sync/lock_cnt_12_s3/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
20.000 | 0.000 | clk | |||
20.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
20.728 | 0.728 | tINS | RR | 31 | clk_ibuf/O |
21.266 | 0.538 | tNET | RR | 1 | u_psram_top/u_psram_sync/lock_cnt_12_s3/CLK |
20.969 | -0.296 | tSu | 1 | u_psram_top/u_psram_sync/lock_cnt_12_s3 |
Clock Skew: | 0.000 |
Setup Relationship: | 20.000 |
Logic Level: | 6 |
Arrival Clock Path Delay: | cell: 0.728, 57.491%; route: 0.538, 42.509% |
Arrival Data Path Delay: | cell: 3.867, 45.627%; route: 4.268, 50.365%; tC2Q: 0.340, 4.008% |
Required Clock Path Delay: | cell: 0.728, 57.491%; route: 0.538, 42.509% |
Path 4
Path Summary:Slack | 11.229 |
Data Arrival Time | 9.740 |
Data Required Time | 20.969 |
From | u_psram_top/u_psram_sync/lock_cnt_1_s3 |
To | u_psram_top/u_psram_sync/lock_cnt_13_s1 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.728 | 0.728 | tINS | RR | 31 | clk_ibuf/O |
1.266 | 0.538 | tNET | RR | 1 | u_psram_top/u_psram_sync/lock_cnt_1_s3/CLK |
1.605 | 0.340 | tC2Q | RF | 5 | u_psram_top/u_psram_sync/lock_cnt_1_s3/Q |
2.317 | 0.711 | tNET | FF | 1 | u_psram_top/u_psram_sync/n47_s2/I1 |
3.131 | 0.814 | tINS | FF | 4 | u_psram_top/u_psram_sync/n47_s2/F |
3.842 | 0.711 | tNET | FF | 1 | u_psram_top/u_psram_sync/n44_s3/I1 |
4.657 | 0.814 | tINS | FF | 3 | u_psram_top/u_psram_sync/n44_s3/F |
5.368 | 0.711 | tNET | FF | 1 | u_psram_top/u_psram_sync/n43_s2/I1 |
6.182 | 0.814 | tINS | FF | 4 | u_psram_top/u_psram_sync/n43_s2/F |
6.894 | 0.711 | tNET | FF | 1 | u_psram_top/u_psram_sync/n39_s2/I2 |
7.503 | 0.609 | tINS | FF | 4 | u_psram_top/u_psram_sync/n39_s2/F |
8.214 | 0.711 | tNET | FF | 1 | u_psram_top/u_psram_sync/n38_s1/I1 |
9.028 | 0.814 | tINS | FF | 1 | u_psram_top/u_psram_sync/n38_s1/F |
9.740 | 0.711 | tNET | FF | 1 | u_psram_top/u_psram_sync/lock_cnt_13_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
20.000 | 0.000 | clk | |||
20.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
20.728 | 0.728 | tINS | RR | 31 | clk_ibuf/O |
21.266 | 0.538 | tNET | RR | 1 | u_psram_top/u_psram_sync/lock_cnt_13_s1/CLK |
20.969 | -0.296 | tSu | 1 | u_psram_top/u_psram_sync/lock_cnt_13_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 20.000 |
Logic Level: | 6 |
Arrival Clock Path Delay: | cell: 0.728, 57.491%; route: 0.538, 42.509% |
Arrival Data Path Delay: | cell: 3.867, 45.627%; route: 4.268, 50.365%; tC2Q: 0.340, 4.008% |
Required Clock Path Delay: | cell: 0.728, 57.491%; route: 0.538, 42.509% |
Path 5
Path Summary:Slack | 11.279 |
Data Arrival Time | 9.690 |
Data Required Time | 20.969 |
From | u_psram_top/u_psram_sync/lock_cnt_1_s3 |
To | u_psram_top/u_psram_sync/lock_cnt_14_s1 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.728 | 0.728 | tINS | RR | 31 | clk_ibuf/O |
1.266 | 0.538 | tNET | RR | 1 | u_psram_top/u_psram_sync/lock_cnt_1_s3/CLK |
1.605 | 0.340 | tC2Q | RF | 5 | u_psram_top/u_psram_sync/lock_cnt_1_s3/Q |
2.317 | 0.711 | tNET | FF | 1 | u_psram_top/u_psram_sync/n47_s2/I1 |
3.131 | 0.814 | tINS | FF | 4 | u_psram_top/u_psram_sync/n47_s2/F |
3.842 | 0.711 | tNET | FF | 1 | u_psram_top/u_psram_sync/n44_s3/I1 |
4.657 | 0.814 | tINS | FF | 3 | u_psram_top/u_psram_sync/n44_s3/F |
5.368 | 0.711 | tNET | FF | 1 | u_psram_top/u_psram_sync/n43_s2/I1 |
6.182 | 0.814 | tINS | FF | 4 | u_psram_top/u_psram_sync/n43_s2/F |
6.894 | 0.711 | tNET | FF | 1 | u_psram_top/u_psram_sync/n39_s2/I2 |
7.503 | 0.609 | tINS | FF | 4 | u_psram_top/u_psram_sync/n39_s2/F |
8.214 | 0.711 | tNET | FF | 1 | u_psram_top/u_psram_sync/n37_s1/I0 |
8.979 | 0.765 | tINS | FF | 1 | u_psram_top/u_psram_sync/n37_s1/F |
9.690 | 0.711 | tNET | FF | 1 | u_psram_top/u_psram_sync/lock_cnt_14_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
20.000 | 0.000 | clk | |||
20.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
20.728 | 0.728 | tINS | RR | 31 | clk_ibuf/O |
21.266 | 0.538 | tNET | RR | 1 | u_psram_top/u_psram_sync/lock_cnt_14_s1/CLK |
20.969 | -0.296 | tSu | 1 | u_psram_top/u_psram_sync/lock_cnt_14_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 20.000 |
Logic Level: | 6 |
Arrival Clock Path Delay: | cell: 0.728, 57.491%; route: 0.538, 42.509% |
Arrival Data Path Delay: | cell: 3.817, 45.306%; route: 4.268, 50.663%; tC2Q: 0.340, 4.031% |
Required Clock Path Delay: | cell: 0.728, 57.491%; route: 0.538, 42.509% |