Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\HYPERRAM_EMB\data\HPRAM_TOP.v
D:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\HYPERRAM_EMB\data\hpram_code_166.v
GowinSynthesis Constraints File ---
Tool Version V1.9.9.01 (64-bit)
Part Number GW1NSR-LV4CQN48PC7/I6
Device GW1NSR-4C
Created Time Mon Feb 19 10:51:57 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module HyperRAM_Memory_Interface_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.25s, Peak memory usage = 101.207MB
Running netlist conversion:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 101.207MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.036s, Peak memory usage = 101.207MB
    Optimizing Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.024s, Peak memory usage = 101.207MB
    Optimizing Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.038s, Peak memory usage = 101.207MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.024s, Peak memory usage = 101.207MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 101.207MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 101.207MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 101.207MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.052s, Peak memory usage = 101.207MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 101.207MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 101.207MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.906s, Elapsed time = 0h 0m 0.98s, Peak memory usage = 130.367MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.084s, Peak memory usage = 130.367MB
Generate output files:
    CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.052s, Peak memory usage = 130.367MB
Total Time and Memory Usage CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 130.367MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 99
Embedded Port 13
I/O Buf 112
    IBUF 64
    OBUF 39
    IOBUF 9
Register 357
    DFF 1
    DFFP 3
    DFFPE 3
    DFFC 194
    DFFCE 156
LUT 566
    LUT2 192
    LUT3 185
    LUT4 189
ALU 31
    ALU 31
INV 7
    INV 7
IOLOGIC 30
    IDES4 8
    OSER4 12
    IODELAY 10
BSRAM 1
    SDPX9B 1
CLOCK 2
    CLKDIV 1
    DHCEN 1

Resource Utilization Summary

Resource Usage Utilization
Logic 604(573 LUT, 31 ALU) / 4608 14%
Register 357 / 3609 10%
  --Register as Latch 0 / 3609 0%
  --Register as FF 357 / 3609 10%
BSRAM 1 / 10 10%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
memory_clk Base 20.000 50.0 0.000 10.000 memory_clk_ibuf/I
clk Base 20.000 50.0 0.000 10.000 clk_ibuf/I
u_hpram_top/clkdiv/CLKOUT.default_gen_clk Generated 40.000 25.0 0.000 20.000 memory_clk_ibuf/I memory_clk u_hpram_top/clkdiv/CLKOUT

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 50.000(MHz) 138.026(MHz) 5 TOP
2 u_hpram_top/clkdiv/CLKOUT.default_gen_clk 25.000(MHz) 142.051(MHz) 5 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 8.906
Data Arrival Time 2.317
Data Required Time 11.223
From u_hpram_top/u_hpram_sync/cs_memsync_4_s0
To u_hpram_top/u_dqce_clk_x2p
Launch Clk clk[F]
Latch Clk memory_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.728 0.728 tINS RR 31 clk_ibuf/O
1.266 0.538 tNET RR 1 u_hpram_top/u_hpram_sync/cs_memsync_4_s0/CLK
1.605 0.340 tC2Q RF 7 u_hpram_top/u_hpram_sync/cs_memsync_4_s0/Q
2.317 0.711 tNET FF 1 u_hpram_top/u_dqce_clk_x2p/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 memory_clk
10.000 0.000 tCL FF 1 memory_clk_ibuf/I
10.729 0.729 tINS FF 1 memory_clk_ibuf/O
11.441 0.711 tNET FF 3 u_hpram_top/u_dqce_clk_x2p/CLKIN
11.411 -0.030 tUnc u_hpram_top/u_dqce_clk_x2p
11.223 -0.188 tSu 1 u_hpram_top/u_dqce_clk_x2p
Path Statistics:
Clock Skew: 0.175
Setup Relationship: 10.000
Logic Level: 1
Arrival Clock Path Delay: cell: 0.728, 57.491%; route: 0.538, 42.509%
Arrival Data Path Delay: cell: 0.000, 0.000%; route: 0.711, 67.685%; tC2Q: 0.340, 32.315%
Required Clock Path Delay: cell: 0.728, 57.491%; route: 0.538, 42.509%

Path 2

Path Summary:
Slack 12.755
Data Arrival Time 8.214
Data Required Time 20.969
From u_hpram_top/u_hpram_sync/lock_d2_s0
To u_hpram_top/u_hpram_sync/count_1_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.728 0.728 tINS RR 31 clk_ibuf/O
1.266 0.538 tNET RR 1 u_hpram_top/u_hpram_sync/lock_d2_s0/CLK
1.605 0.340 tC2Q RF 3 u_hpram_top/u_hpram_sync/lock_d2_s0/Q
2.317 0.711 tNET FF 1 u_hpram_top/u_hpram_sync/n389_s5/I1
3.131 0.814 tINS FF 1 u_hpram_top/u_hpram_sync/n389_s5/F
3.842 0.711 tNET FF 1 u_hpram_top/u_hpram_sync/n389_s4/I1
4.657 0.814 tINS FF 2 u_hpram_top/u_hpram_sync/n389_s4/F
5.368 0.711 tNET FF 1 u_hpram_top/u_hpram_sync/n388_s3/I1
6.182 0.814 tINS FF 2 u_hpram_top/u_hpram_sync/n388_s3/F
6.894 0.711 tNET FF 1 u_hpram_top/u_hpram_sync/n388_s2/I2
7.503 0.609 tINS FF 1 u_hpram_top/u_hpram_sync/n388_s2/F
8.214 0.711 tNET FF 1 u_hpram_top/u_hpram_sync/count_1_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.728 0.728 tINS RR 31 clk_ibuf/O
21.266 0.538 tNET RR 1 u_hpram_top/u_hpram_sync/count_1_s0/CLK
20.969 -0.296 tSu 1 u_hpram_top/u_hpram_sync/count_1_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.728, 57.491%; route: 0.538, 42.509%
Arrival Data Path Delay: cell: 3.052, 43.925%; route: 3.557, 51.187%; tC2Q: 0.340, 4.888%
Required Clock Path Delay: cell: 0.728, 57.491%; route: 0.538, 42.509%

Path 3

Path Summary:
Slack 12.755
Data Arrival Time 8.214
Data Required Time 20.969
From u_hpram_top/u_hpram_sync/cs_memsync_5_s0
To u_hpram_top/u_hpram_sync/cs_memsync_0_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.728 0.728 tINS RR 31 clk_ibuf/O
1.266 0.538 tNET RR 1 u_hpram_top/u_hpram_sync/cs_memsync_5_s0/CLK
1.605 0.340 tC2Q RF 7 u_hpram_top/u_hpram_sync/cs_memsync_5_s0/Q
2.317 0.711 tNET FF 1 u_hpram_top/u_hpram_sync/n348_s12/I1
3.131 0.814 tINS FF 5 u_hpram_top/u_hpram_sync/n348_s12/F
3.842 0.711 tNET FF 1 u_hpram_top/u_hpram_sync/n304_s14/I1
4.657 0.814 tINS FF 4 u_hpram_top/u_hpram_sync/n304_s14/F
5.368 0.711 tNET FF 1 u_hpram_top/u_hpram_sync/n337_s14/I2
5.977 0.609 tINS FF 1 u_hpram_top/u_hpram_sync/n337_s14/F
6.688 0.711 tNET FF 1 u_hpram_top/u_hpram_sync/n337_s12/I1
7.503 0.814 tINS FF 1 u_hpram_top/u_hpram_sync/n337_s12/F
8.214 0.711 tNET FF 1 u_hpram_top/u_hpram_sync/cs_memsync_0_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.728 0.728 tINS RR 31 clk_ibuf/O
21.266 0.538 tNET RR 1 u_hpram_top/u_hpram_sync/cs_memsync_0_s0/CLK
20.969 -0.296 tSu 1 u_hpram_top/u_hpram_sync/cs_memsync_0_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.728, 57.491%; route: 0.538, 42.509%
Arrival Data Path Delay: cell: 3.052, 43.925%; route: 3.557, 51.187%; tC2Q: 0.340, 4.888%
Required Clock Path Delay: cell: 0.728, 57.491%; route: 0.538, 42.509%

Path 4

Path Summary:
Slack 12.854
Data Arrival Time 8.115
Data Required Time 20.969
From u_hpram_top/u_hpram_sync/count_1_s0
To u_hpram_top/u_hpram_sync/flag_0_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.728 0.728 tINS RR 31 clk_ibuf/O
1.266 0.538 tNET RR 1 u_hpram_top/u_hpram_sync/count_1_s0/CLK
1.605 0.340 tC2Q RF 6 u_hpram_top/u_hpram_sync/count_1_s0/Q
2.317 0.711 tNET FF 1 u_hpram_top/u_hpram_sync/n304_s13/I1
3.131 0.814 tINS FF 6 u_hpram_top/u_hpram_sync/n304_s13/F
3.842 0.711 tNET FF 1 u_hpram_top/u_hpram_sync/n359_s9/I0
4.607 0.765 tINS FF 1 u_hpram_top/u_hpram_sync/n359_s9/F
5.318 0.711 tNET FF 1 u_hpram_top/u_hpram_sync/n359_s8/I0
6.083 0.765 tINS FF 1 u_hpram_top/u_hpram_sync/n359_s8/F
6.794 0.711 tNET FF 1 u_hpram_top/u_hpram_sync/n359_s6/I2
7.403 0.609 tINS FF 1 u_hpram_top/u_hpram_sync/n359_s6/F
8.115 0.711 tNET FF 1 u_hpram_top/u_hpram_sync/flag_0_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.728 0.728 tINS RR 31 clk_ibuf/O
21.266 0.538 tNET RR 1 u_hpram_top/u_hpram_sync/flag_0_s0/CLK
20.969 -0.296 tSu 1 u_hpram_top/u_hpram_sync/flag_0_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.728, 57.491%; route: 0.538, 42.509%
Arrival Data Path Delay: cell: 2.953, 43.112%; route: 3.557, 51.929%; tC2Q: 0.340, 4.959%
Required Clock Path Delay: cell: 0.728, 57.491%; route: 0.538, 42.509%

Path 5

Path Summary:
Slack 12.900
Data Arrival Time 8.069
Data Required Time 20.969
From u_hpram_top/u_hpram_sync/lock_d2_s0
To u_hpram_top/u_hpram_sync/count_2_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.728 0.728 tINS RR 31 clk_ibuf/O
1.266 0.538 tNET RR 1 u_hpram_top/u_hpram_sync/lock_d2_s0/CLK
1.605 0.340 tC2Q RF 3 u_hpram_top/u_hpram_sync/lock_d2_s0/Q
2.317 0.711 tNET FF 1 u_hpram_top/u_hpram_sync/n389_s5/I1
3.131 0.814 tINS FF 1 u_hpram_top/u_hpram_sync/n389_s5/F
3.842 0.711 tNET FF 1 u_hpram_top/u_hpram_sync/n389_s4/I1
4.657 0.814 tINS FF 2 u_hpram_top/u_hpram_sync/n389_s4/F
5.368 0.711 tNET FF 1 u_hpram_top/u_hpram_sync/n388_s3/I1
6.182 0.814 tINS FF 2 u_hpram_top/u_hpram_sync/n388_s3/F
6.894 0.711 tNET FF 1 u_hpram_top/u_hpram_sync/n387_s4/I3
7.358 0.464 tINS FF 1 u_hpram_top/u_hpram_sync/n387_s4/F
8.069 0.711 tNET FF 1 u_hpram_top/u_hpram_sync/count_2_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.728 0.728 tINS RR 31 clk_ibuf/O
21.266 0.538 tNET RR 1 u_hpram_top/u_hpram_sync/count_2_s0/CLK
20.969 -0.296 tSu 1 u_hpram_top/u_hpram_sync/count_2_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.728, 57.491%; route: 0.538, 42.509%
Arrival Data Path Delay: cell: 2.907, 42.728%; route: 3.557, 52.280%; tC2Q: 0.340, 4.992%
Required Clock Path Delay: cell: 0.728, 57.491%; route: 0.538, 42.509%