Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\gowin_empu_gw1ns4\data\gowin_empu.v
D:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\gowin_empu_gw1ns4\data\gowin_empu_top.v
GowinSynthesis Constraints File ---
Tool Version V1.9.9.01 (64-bit)
Part Number GW1NSR-LV4CQN48GC7/I6
Device GW1NSR-4C
Created Time Mon Feb 19 10:24:07 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module Gowin_EMPU_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.165s, Peak memory usage = 101.066MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 101.066MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.021s, Peak memory usage = 101.066MB
    Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 101.066MB
    Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.015s, Peak memory usage = 101.066MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 101.066MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 101.066MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 101.066MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 101.066MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.014s, Peak memory usage = 101.066MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 101.066MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 101.066MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.828s, Elapsed time = 0h 0m 0.883s, Peak memory usage = 129.199MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.052s, Peak memory usage = 129.199MB
Generate output files:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.024s, Peak memory usage = 129.199MB
Total Time and Memory Usage CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 129.199MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 6
I/O Buf 6
    IBUF 3
    OBUF 1
    IOBUF 2
Register 173
    DFF 1
    DFFE 1
    DFFR 1
    DFFRE 14
    DFFP 5
    DFFPE 24
    DFFC 44
    DFFCE 83
LUT 315
    LUT2 52
    LUT3 83
    LUT4 180
INV 6
    INV 6
BSRAM 4
    SDPB 4
User Flash 1
    FLASH256K 1
EMCU 1

Resource Utilization Summary

Resource Usage Utilization
Logic 321(321 LUT, 0 ALU) / 4608 7%
Register 173 / 3570 5%
  --Register as Latch 0 / 3570 0%
  --Register as FF 173 / 3570 5%
BSRAM 4 / 10 40%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
sys_clk Base 20.000 50.0 0.000 10.000 sys_clk_ibuf/I

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 sys_clk 50.000(MHz) 134.223(MHz) 5 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 12.550
Data Arrival Time 8.419
Data Required Time 20.969
From Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_apb2_i2c/byte_controller/bit_controller/cnt_6_s1
To Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_apb2_i2c/byte_controller/bit_controller/cnt_13_s1
Launch Clk sys_clk[R]
Latch Clk sys_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 sys_clk_ibuf/I
0.728 0.728 tINS RR 181 sys_clk_ibuf/O
1.266 0.538 tNET RR 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_apb2_i2c/byte_controller/bit_controller/cnt_6_s1/CLK
1.605 0.340 tC2Q RF 3 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_apb2_i2c/byte_controller/bit_controller/cnt_6_s1/Q
2.317 0.711 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_apb2_i2c/byte_controller/bit_controller/n26_s4/I1
3.131 0.814 tINS FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_apb2_i2c/byte_controller/bit_controller/n26_s4/F
3.842 0.711 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_apb2_i2c/byte_controller/bit_controller/n26_s1/I1
4.657 0.814 tINS FF 5 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_apb2_i2c/byte_controller/bit_controller/n26_s1/F
5.368 0.711 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_apb2_i2c/byte_controller/bit_controller/n46_s1/I1
6.182 0.814 tINS FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_apb2_i2c/byte_controller/bit_controller/n46_s1/F
6.894 0.711 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_apb2_i2c/byte_controller/bit_controller/n46_s0/I1
7.708 0.814 tINS FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_apb2_i2c/byte_controller/bit_controller/n46_s0/F
8.419 0.711 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_apb2_i2c/byte_controller/bit_controller/cnt_13_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 sys_clk
20.000 0.000 tCL RR 1 sys_clk_ibuf/I
20.728 0.728 tINS RR 181 sys_clk_ibuf/O
21.266 0.538 tNET RR 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_apb2_i2c/byte_controller/bit_controller/cnt_13_s1/CLK
20.969 -0.296 tSu 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_apb2_i2c/byte_controller/bit_controller/cnt_13_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.728, 57.491%; route: 0.538, 42.509%
Arrival Data Path Delay: cell: 3.257, 45.534%; route: 3.557, 49.719%; tC2Q: 0.340, 4.747%
Required Clock Path Delay: cell: 0.728, 57.491%; route: 0.538, 42.509%

Path 2

Path Summary:
Slack 12.599
Data Arrival Time 8.370
Data Required Time 20.969
From Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_apb2_i2c/byte_controller/bit_controller/c_state_5_s1
To Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_apb2_i2c/byte_controller/bit_controller/sda_oen_s1
Launch Clk sys_clk[R]
Latch Clk sys_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 sys_clk_ibuf/I
0.728 0.728 tINS RR 181 sys_clk_ibuf/O
1.266 0.538 tNET RR 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_apb2_i2c/byte_controller/bit_controller/c_state_5_s1/CLK
1.605 0.340 tC2Q RF 5 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_apb2_i2c/byte_controller/bit_controller/c_state_5_s1/Q
2.317 0.711 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_apb2_i2c/byte_controller/bit_controller/n351_s5/I1
3.131 0.814 tINS FF 4 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_apb2_i2c/byte_controller/bit_controller/n351_s5/F
3.842 0.711 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_apb2_i2c/byte_controller/bit_controller/n338_s4/I1
4.657 0.814 tINS FF 7 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_apb2_i2c/byte_controller/bit_controller/n338_s4/F
5.368 0.711 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_apb2_i2c/byte_controller/bit_controller/n354_s2/I1
6.182 0.814 tINS FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_apb2_i2c/byte_controller/bit_controller/n354_s2/F
6.894 0.711 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_apb2_i2c/byte_controller/bit_controller/n354_s1/I0
7.658 0.765 tINS FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_apb2_i2c/byte_controller/bit_controller/n354_s1/F
8.370 0.711 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_apb2_i2c/byte_controller/bit_controller/sda_oen_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 sys_clk
20.000 0.000 tCL RR 1 sys_clk_ibuf/I
20.728 0.728 tINS RR 181 sys_clk_ibuf/O
21.266 0.538 tNET RR 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_apb2_i2c/byte_controller/bit_controller/sda_oen_s1/CLK
20.969 -0.296 tSu 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_apb2_i2c/byte_controller/bit_controller/sda_oen_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.728, 57.491%; route: 0.538, 42.509%
Arrival Data Path Delay: cell: 3.208, 45.153%; route: 3.557, 50.066%; tC2Q: 0.340, 4.781%
Required Clock Path Delay: cell: 0.728, 57.491%; route: 0.538, 42.509%

Path 3

Path Summary:
Slack 12.599
Data Arrival Time 8.370
Data Required Time 20.969
From Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_apb2_i2c/byte_controller/bit_controller/filter_cnt_1_s0
To Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_apb2_i2c/byte_controller/bit_controller/filter_cnt_7_s0
Launch Clk sys_clk[R]
Latch Clk sys_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 sys_clk_ibuf/I
0.728 0.728 tINS RR 181 sys_clk_ibuf/O
1.266 0.538 tNET RR 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_apb2_i2c/byte_controller/bit_controller/filter_cnt_1_s0/CLK
1.605 0.340 tC2Q RF 4 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_apb2_i2c/byte_controller/bit_controller/filter_cnt_1_s0/Q
2.317 0.711 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_apb2_i2c/byte_controller/bit_controller/n105_s2/I1
3.131 0.814 tINS FF 5 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_apb2_i2c/byte_controller/bit_controller/n105_s2/F
3.842 0.711 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_apb2_i2c/byte_controller/bit_controller/n105_s0/I1
4.657 0.814 tINS FF 17 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_apb2_i2c/byte_controller/bit_controller/n105_s0/F
5.368 0.711 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_apb2_i2c/byte_controller/bit_controller/n159_s2/I1
6.182 0.814 tINS FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_apb2_i2c/byte_controller/bit_controller/n159_s2/F
6.894 0.711 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_apb2_i2c/byte_controller/bit_controller/n159_s1/I0
7.658 0.765 tINS FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_apb2_i2c/byte_controller/bit_controller/n159_s1/F
8.370 0.711 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_apb2_i2c/byte_controller/bit_controller/filter_cnt_7_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 sys_clk
20.000 0.000 tCL RR 1 sys_clk_ibuf/I
20.728 0.728 tINS RR 181 sys_clk_ibuf/O
21.266 0.538 tNET RR 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_apb2_i2c/byte_controller/bit_controller/filter_cnt_7_s0/CLK
20.969 -0.296 tSu 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_apb2_i2c/byte_controller/bit_controller/filter_cnt_7_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.728, 57.491%; route: 0.538, 42.509%
Arrival Data Path Delay: cell: 3.208, 45.153%; route: 3.557, 50.066%; tC2Q: 0.340, 4.781%
Required Clock Path Delay: cell: 0.728, 57.491%; route: 0.538, 42.509%

Path 4

Path Summary:
Slack 12.599
Data Arrival Time 8.370
Data Required Time 20.969
From Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_apb2_i2c/byte_controller/c_state_1_s0
To Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_apb2_i2c/byte_controller/core_txd_s0
Launch Clk sys_clk[R]
Latch Clk sys_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 sys_clk_ibuf/I
0.728 0.728 tINS RR 181 sys_clk_ibuf/O
1.266 0.538 tNET RR 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_apb2_i2c/byte_controller/c_state_1_s0/CLK
1.605 0.340 tC2Q RF 11 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_apb2_i2c/byte_controller/c_state_1_s0/Q
2.317 0.711 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_apb2_i2c/byte_controller/n211_s6/I1
3.131 0.814 tINS FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_apb2_i2c/byte_controller/n211_s6/F
3.842 0.711 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_apb2_i2c/byte_controller/n211_s5/I0
4.607 0.765 tINS FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_apb2_i2c/byte_controller/n211_s5/F
5.318 0.711 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_apb2_i2c/byte_controller/n211_s4/I1
6.133 0.814 tINS FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_apb2_i2c/byte_controller/n211_s4/F
6.844 0.711 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_apb2_i2c/byte_controller/n211_s2/I1
7.658 0.814 tINS FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_apb2_i2c/byte_controller/n211_s2/F
8.370 0.711 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_apb2_i2c/byte_controller/core_txd_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 sys_clk
20.000 0.000 tCL RR 1 sys_clk_ibuf/I
20.728 0.728 tINS RR 181 sys_clk_ibuf/O
21.266 0.538 tNET RR 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_apb2_i2c/byte_controller/core_txd_s0/CLK
20.969 -0.296 tSu 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_apb2_i2c/byte_controller/core_txd_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.728, 57.491%; route: 0.538, 42.509%
Arrival Data Path Delay: cell: 3.208, 45.153%; route: 3.557, 50.066%; tC2Q: 0.340, 4.781%
Required Clock Path Delay: cell: 0.728, 57.491%; route: 0.538, 42.509%

Path 5

Path Summary:
Slack 12.599
Data Arrival Time 8.370
Data Required Time 20.969
From Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_apb2_i2c/cr_7_s1
To Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_apb2_i2c/byte_controller/core_cmd_1_s0
Launch Clk sys_clk[R]
Latch Clk sys_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 sys_clk_ibuf/I
0.728 0.728 tINS RR 181 sys_clk_ibuf/O
1.266 0.538 tNET RR 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_apb2_i2c/cr_7_s1/CLK
1.605 0.340 tC2Q RF 5 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_apb2_i2c/cr_7_s1/Q
2.317 0.711 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_apb2_i2c/byte_controller/n217_s5/I1
3.131 0.814 tINS FF 3 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_apb2_i2c/byte_controller/n217_s5/F
3.842 0.711 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_apb2_i2c/byte_controller/n215_s6/I1
4.657 0.814 tINS FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_apb2_i2c/byte_controller/n215_s6/F
5.368 0.711 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_apb2_i2c/byte_controller/n215_s5/I1
6.182 0.814 tINS FF 2 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_apb2_i2c/byte_controller/n215_s5/F
6.894 0.711 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_apb2_i2c/byte_controller/n209_s2/I0
7.658 0.765 tINS FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_apb2_i2c/byte_controller/n209_s2/F
8.370 0.711 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_apb2_i2c/byte_controller/core_cmd_1_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 sys_clk
20.000 0.000 tCL RR 1 sys_clk_ibuf/I
20.728 0.728 tINS RR 181 sys_clk_ibuf/O
21.266 0.538 tNET RR 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_apb2_i2c/byte_controller/core_cmd_1_s0/CLK
20.969 -0.296 tSu 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_apb2_i2c/byte_controller/core_cmd_1_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.728, 57.491%; route: 0.538, 42.509%
Arrival Data Path Delay: cell: 3.208, 45.153%; route: 3.557, 50.066%; tC2Q: 0.340, 4.781%
Required Clock Path Delay: cell: 0.728, 57.491%; route: 0.538, 42.509%