Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\HYPERRAM\data\HPRAM_TOP.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\HYPERRAM\data\hpram_code_1N2A.v |
GowinSynthesis Constraints File | --- |
Tool Version | V1.9.11.02 (64-bit) |
Part Number | GW1NSR-LV4CQN48PC7/I6 |
Device | GW1NSR-4C |
Created Time | Thu May 15 11:03:59 2025 |
Legal Announcement | Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | HyperRAM_Memory_Interface_Top |
Synthesis Process | Running parser: CPU time = 0h 0m 0.234s, Elapsed time = 0h 0m 0.308s, Peak memory usage = 63.789MB Running netlist conversion: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 63.789MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.05s, Peak memory usage = 63.789MB Optimizing Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.029s, Peak memory usage = 63.789MB Optimizing Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.048s, Peak memory usage = 63.789MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 63.789MB Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 63.789MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 63.789MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 63.789MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.061s, Peak memory usage = 63.789MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 63.789MB Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 63.789MB Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 93.832MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.158s, Peak memory usage = 93.832MB Generate output files: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.053s, Peak memory usage = 93.832MB |
Total Time and Memory Usage | CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 93.832MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 99 |
Embedded Port | 13 |
I/O Buf | 112 |
    IBUF | 64 |
    OBUF | 39 |
    IOBUF | 9 |
Register | 351 |
    DFF | 1 |
    DFFP | 3 |
    DFFPE | 3 |
    DFFC | 177 |
    DFFCE | 167 |
LUT | 584 |
    LUT2 | 165 |
    LUT3 | 134 |
    LUT4 | 285 |
ALU | 31 |
    ALU | 31 |
INV | 7 |
    INV | 7 |
IOLOGIC | 30 |
    IDES4 | 8 |
    OSER4 | 12 |
    IODELAY | 10 |
BSRAM | 1 |
    SDPX9B | 1 |
CLOCK | 2 |
    CLKDIV | 1 |
    DHCEN | 1 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 622(591 LUT, 31 ALU) / 4608 | 14% |
Register | 351 / 3612 | 10% |
  --Register as Latch | 0 / 3612 | 0% |
  --Register as FF | 351 / 3612 | 10% |
BSRAM | 1 / 10 | 10% |
Timing
Clock Summary:
NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|---|
1 | memory_clk | Base | 20.000 | 50.000 | 0.000 | 10.000 | memory_clk_ibuf/I | ||
2 | clk | Base | 20.000 | 50.000 | 0.000 | 10.000 | clk_ibuf/I | ||
3 | u_hpram_top/clkdiv/CLKOUT.default_gen_clk | Generated | 40.000 | 25.000 | 0.000 | 20.000 | memory_clk_ibuf/I | memory_clk | u_hpram_top/clkdiv/CLKOUT |
Max Frequency Summary:
NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | clk | 50.000(MHz) | 134.223(MHz) | 5 | TOP |
2 | u_hpram_top/clkdiv/CLKOUT.default_gen_clk | 25.000(MHz) | 138.026(MHz) | 5 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | 8.904 |
Data Arrival Time | 1.589 |
Data Required Time | 10.493 |
From | u_hpram_top/u_hpram_sync/cs_memsync_4_s0 |
To | u_hpram_top/u_dqce_clk_x2p |
Launch Clk | clk[F] |
Latch Clk | memory_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.000 | 0.000 | tINS | RR | 31 | clk_ibuf/O |
0.538 | 0.538 | tNET | RR | 1 | u_hpram_top/u_hpram_sync/cs_memsync_4_s0/CLK |
0.878 | 0.340 | tC2Q | RF | 7 | u_hpram_top/u_hpram_sync/cs_memsync_4_s0/Q |
1.589 | 0.711 | tNET | FF | 1 | u_hpram_top/u_dqce_clk_x2p/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | memory_clk | |||
10.000 | 0.000 | tCL | FF | 1 | memory_clk_ibuf/I |
10.000 | 0.000 | tINS | FF | 1 | memory_clk_ibuf/O |
10.711 | 0.711 | tNET | FF | 3 | u_hpram_top/u_dqce_clk_x2p/CLKIN |
10.681 | -0.030 | tUnc | u_hpram_top/u_dqce_clk_x2p | ||
10.493 | -0.188 | tSu | 1 | u_hpram_top/u_dqce_clk_x2p |
Clock Skew: | 0.173 |
Setup Relationship: | 10.000 |
Logic Level: | 1 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.538, 100.000% |
Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.711, 67.685%; tC2Q: 0.340, 32.315% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.538, 100.000% |
Path 2
Path Summary:Slack | 12.550 |
Data Arrival Time | 7.692 |
Data Required Time | 20.242 |
From | u_hpram_top/u_hpram_sync/lock_cnt_1_s3 |
To | u_hpram_top/u_hpram_sync/lock_cnt_10_s3 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.000 | 0.000 | tINS | RR | 31 | clk_ibuf/O |
0.538 | 0.538 | tNET | RR | 1 | u_hpram_top/u_hpram_sync/lock_cnt_1_s3/CLK |
0.878 | 0.340 | tC2Q | RF | 5 | u_hpram_top/u_hpram_sync/lock_cnt_1_s3/Q |
1.589 | 0.711 | tNET | FF | 1 | u_hpram_top/u_hpram_sync/n47_s2/I1 |
2.403 | 0.814 | tINS | FF | 4 | u_hpram_top/u_hpram_sync/n47_s2/F |
3.115 | 0.711 | tNET | FF | 1 | u_hpram_top/u_hpram_sync/n44_s3/I1 |
3.929 | 0.814 | tINS | FF | 6 | u_hpram_top/u_hpram_sync/n44_s3/F |
4.640 | 0.711 | tNET | FF | 1 | u_hpram_top/u_hpram_sync/n41_s3/I1 |
5.455 | 0.814 | tINS | FF | 2 | u_hpram_top/u_hpram_sync/n41_s3/F |
6.166 | 0.711 | tNET | FF | 1 | u_hpram_top/u_hpram_sync/n41_s6/I1 |
6.980 | 0.814 | tINS | FF | 1 | u_hpram_top/u_hpram_sync/n41_s6/F |
7.692 | 0.711 | tNET | FF | 1 | u_hpram_top/u_hpram_sync/lock_cnt_10_s3/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
20.000 | 0.000 | clk | |||
20.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
20.000 | 0.000 | tINS | RR | 31 | clk_ibuf/O |
20.538 | 0.538 | tNET | RR | 1 | u_hpram_top/u_hpram_sync/lock_cnt_10_s3/CLK |
20.242 | -0.296 | tSu | 1 | u_hpram_top/u_hpram_sync/lock_cnt_10_s3 |
Clock Skew: | 0.000 |
Setup Relationship: | 20.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.538, 100.000% |
Arrival Data Path Delay: | cell: 3.257, 45.534%; route: 3.557, 49.719%; tC2Q: 0.340, 4.747% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.538, 100.000% |
Path 3
Path Summary:Slack | 12.550 |
Data Arrival Time | 7.692 |
Data Required Time | 20.242 |
From | u_hpram_top/u_hpram_sync/lock_cnt_1_s3 |
To | u_hpram_top/u_hpram_sync/lock_cnt_11_s1 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.000 | 0.000 | tINS | RR | 31 | clk_ibuf/O |
0.538 | 0.538 | tNET | RR | 1 | u_hpram_top/u_hpram_sync/lock_cnt_1_s3/CLK |
0.878 | 0.340 | tC2Q | RF | 5 | u_hpram_top/u_hpram_sync/lock_cnt_1_s3/Q |
1.589 | 0.711 | tNET | FF | 1 | u_hpram_top/u_hpram_sync/n47_s2/I1 |
2.403 | 0.814 | tINS | FF | 4 | u_hpram_top/u_hpram_sync/n47_s2/F |
3.115 | 0.711 | tNET | FF | 1 | u_hpram_top/u_hpram_sync/n44_s3/I1 |
3.929 | 0.814 | tINS | FF | 6 | u_hpram_top/u_hpram_sync/n44_s3/F |
4.640 | 0.711 | tNET | FF | 1 | u_hpram_top/u_hpram_sync/n41_s3/I1 |
5.455 | 0.814 | tINS | FF | 2 | u_hpram_top/u_hpram_sync/n41_s3/F |
6.166 | 0.711 | tNET | FF | 1 | u_hpram_top/u_hpram_sync/n40_s1/I1 |
6.980 | 0.814 | tINS | FF | 1 | u_hpram_top/u_hpram_sync/n40_s1/F |
7.692 | 0.711 | tNET | FF | 1 | u_hpram_top/u_hpram_sync/lock_cnt_11_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
20.000 | 0.000 | clk | |||
20.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
20.000 | 0.000 | tINS | RR | 31 | clk_ibuf/O |
20.538 | 0.538 | tNET | RR | 1 | u_hpram_top/u_hpram_sync/lock_cnt_11_s1/CLK |
20.242 | -0.296 | tSu | 1 | u_hpram_top/u_hpram_sync/lock_cnt_11_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 20.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.538, 100.000% |
Arrival Data Path Delay: | cell: 3.257, 45.534%; route: 3.557, 49.719%; tC2Q: 0.340, 4.747% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.538, 100.000% |
Path 4
Path Summary:Slack | 12.649 |
Data Arrival Time | 7.593 |
Data Required Time | 20.242 |
From | u_hpram_top/u_hpram_sync/cs_memsync_0_s0 |
To | u_hpram_top/u_hpram_sync/cs_memsync_5_s0 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.000 | 0.000 | tINS | RR | 31 | clk_ibuf/O |
0.538 | 0.538 | tNET | RR | 1 | u_hpram_top/u_hpram_sync/cs_memsync_0_s0/CLK |
0.878 | 0.340 | tC2Q | RF | 6 | u_hpram_top/u_hpram_sync/cs_memsync_0_s0/Q |
1.589 | 0.711 | tNET | FF | 1 | u_hpram_top/u_hpram_sync/flag_d_1_s19/I1 |
2.403 | 0.814 | tINS | FF | 2 | u_hpram_top/u_hpram_sync/flag_d_1_s19/F |
3.115 | 0.711 | tNET | FF | 1 | u_hpram_top/u_hpram_sync/ns_memsync_3_s14/I0 |
3.879 | 0.765 | tINS | FF | 3 | u_hpram_top/u_hpram_sync/ns_memsync_3_s14/F |
4.591 | 0.711 | tNET | FF | 1 | u_hpram_top/u_hpram_sync/ns_memsync_5_s13/I1 |
5.405 | 0.814 | tINS | FF | 1 | u_hpram_top/u_hpram_sync/ns_memsync_5_s13/F |
6.116 | 0.711 | tNET | FF | 1 | u_hpram_top/u_hpram_sync/ns_memsync_5_s12/I0 |
6.881 | 0.765 | tINS | FF | 1 | u_hpram_top/u_hpram_sync/ns_memsync_5_s12/F |
7.593 | 0.711 | tNET | FF | 1 | u_hpram_top/u_hpram_sync/cs_memsync_5_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
20.000 | 0.000 | clk | |||
20.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
20.000 | 0.000 | tINS | RR | 31 | clk_ibuf/O |
20.538 | 0.538 | tNET | RR | 1 | u_hpram_top/u_hpram_sync/cs_memsync_5_s0/CLK |
20.242 | -0.296 | tSu | 1 | u_hpram_top/u_hpram_sync/cs_memsync_5_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 20.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.538, 100.000% |
Arrival Data Path Delay: | cell: 3.158, 44.767%; route: 3.557, 50.419%; tC2Q: 0.340, 4.814% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.538, 100.000% |
Path 5
Path Summary:Slack | 12.755 |
Data Arrival Time | 7.487 |
Data Required Time | 20.242 |
From | u_hpram_top/u_hpram_sync/lock_cnt_1_s3 |
To | u_hpram_top/u_hpram_sync/lock_cnt_13_s3 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.000 | 0.000 | tINS | RR | 31 | clk_ibuf/O |
0.538 | 0.538 | tNET | RR | 1 | u_hpram_top/u_hpram_sync/lock_cnt_1_s3/CLK |
0.878 | 0.340 | tC2Q | RF | 5 | u_hpram_top/u_hpram_sync/lock_cnt_1_s3/Q |
1.589 | 0.711 | tNET | FF | 1 | u_hpram_top/u_hpram_sync/n47_s2/I1 |
2.403 | 0.814 | tINS | FF | 4 | u_hpram_top/u_hpram_sync/n47_s2/F |
3.115 | 0.711 | tNET | FF | 1 | u_hpram_top/u_hpram_sync/n44_s3/I1 |
3.929 | 0.814 | tINS | FF | 6 | u_hpram_top/u_hpram_sync/n44_s3/F |
4.640 | 0.711 | tNET | FF | 1 | u_hpram_top/u_hpram_sync/n38_s2/I2 |
5.249 | 0.609 | tINS | FF | 3 | u_hpram_top/u_hpram_sync/n38_s2/F |
5.961 | 0.711 | tNET | FF | 1 | u_hpram_top/u_hpram_sync/n38_s5/I1 |
6.775 | 0.814 | tINS | FF | 1 | u_hpram_top/u_hpram_sync/n38_s5/F |
7.487 | 0.711 | tNET | FF | 1 | u_hpram_top/u_hpram_sync/lock_cnt_13_s3/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
20.000 | 0.000 | clk | |||
20.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
20.000 | 0.000 | tINS | RR | 31 | clk_ibuf/O |
20.538 | 0.538 | tNET | RR | 1 | u_hpram_top/u_hpram_sync/lock_cnt_13_s3/CLK |
20.242 | -0.296 | tSu | 1 | u_hpram_top/u_hpram_sync/lock_cnt_13_s3 |
Clock Skew: | 0.000 |
Setup Relationship: | 20.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.538, 100.000% |
Arrival Data Path Delay: | cell: 3.052, 43.925%; route: 3.557, 51.187%; tC2Q: 0.340, 4.888% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.538, 100.000% |