Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\PSRAM_HS\data\PSRAM_TOP.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\PSRAM_HS\data\psram_code.v
GowinSynthesis Constraints File ---
Tool Version V1.9.11.02 (64-bit)
Part Number GW1NSR-LV4CMG64PC7/I6
Device GW1NSR-4C
Created Time Thu May 15 13:45:22 2025
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module PSRAM_Memory_Interface_HS_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.296s, Elapsed time = 0h 0m 0.368s, Peak memory usage = 68.969MB
Running netlist conversion:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.018s, Peak memory usage = 68.969MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.082s, Peak memory usage = 68.969MB
    Optimizing Phase 1: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.059s, Peak memory usage = 68.969MB
    Optimizing Phase 2: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.094s, Peak memory usage = 68.969MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.04s, Peak memory usage = 68.969MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 68.969MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 68.969MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 68.969MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.085s, Peak memory usage = 68.969MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.015s, Peak memory usage = 68.969MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 68.969MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 99.398MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.209s, Peak memory usage = 99.398MB
Generate output files:
    CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.09s, Peak memory usage = 99.398MB
Total Time and Memory Usage CPU time = 0h 0m 1s, Elapsed time = 0h 0m 2s, Peak memory usage = 99.398MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 166
Embedded Port 26
I/O Buf 191
    IBUF 99
    OBUF 73
    IOBUF 18
    ELVDS_OBUF 1
Register 456
    DFF 1
    DFFP 3
    DFFPE 6
    DFFC 232
    DFFCE 214
LUT 880
    LUT2 216
    LUT3 331
    LUT4 333
ALU 42
    ALU 42
INV 6
    INV 6
IOLOGIC 58
    IDES4 16
    OSER4 23
    IODELAY 19
BSRAM 2
    SDPX9B 2
CLOCK 2
    CLKDIV 1
    DHCEN 1

Resource Utilization Summary

Resource Usage Utilization
Logic 928(886 LUT, 42 ALU) / 4608 21%
Register 456 / 3702 13%
  --Register as Latch 0 / 3702 0%
  --Register as FF 456 / 3702 13%
BSRAM 2 / 10 20%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 memory_clk Base 20.000 50.000 0.000 10.000 memory_clk_ibuf/I
2 clk Base 20.000 50.000 0.000 10.000 clk_ibuf/I
3 u_psram_top/clkdiv/CLKOUT.default_gen_clk Generated 40.000 25.000 0.000 20.000 memory_clk_ibuf/I memory_clk u_psram_top/clkdiv/CLKOUT

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 50.000(MHz) 140.850(MHz) 5 TOP
2 u_psram_top/clkdiv/CLKOUT.default_gen_clk 25.000(MHz) 134.223(MHz) 5 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 8.904
Data Arrival Time 1.589
Data Required Time 10.493
From u_psram_top/u_psram_sync/cs_memsync_4_s0
To u_psram_top/u_dqce_clk_x2p
Launch Clk clk[F]
Latch Clk memory_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 31 clk_ibuf/O
0.538 0.538 tNET RR 1 u_psram_top/u_psram_sync/cs_memsync_4_s0/CLK
0.878 0.340 tC2Q RF 7 u_psram_top/u_psram_sync/cs_memsync_4_s0/Q
1.589 0.711 tNET FF 1 u_psram_top/u_dqce_clk_x2p/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 memory_clk
10.000 0.000 tCL FF 1 memory_clk_ibuf/I
10.000 0.000 tINS FF 1 memory_clk_ibuf/O
10.711 0.711 tNET FF 3 u_psram_top/u_dqce_clk_x2p/CLKIN
10.681 -0.030 tUnc u_psram_top/u_dqce_clk_x2p
10.493 -0.188 tSu 1 u_psram_top/u_dqce_clk_x2p
Path Statistics:
Clock Skew: 0.173
Setup Relationship: 10.000
Logic Level: 1
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 0.000, 0.000%; route: 0.711, 67.685%; tC2Q: 0.340, 32.315%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 2

Path Summary:
Slack 12.900
Data Arrival Time 7.341
Data Required Time 20.242
From u_psram_top/u_psram_sync/lock_cnt_1_s3
To u_psram_top/u_psram_sync/lock_cnt_13_s3
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 31 clk_ibuf/O
0.538 0.538 tNET RR 1 u_psram_top/u_psram_sync/lock_cnt_1_s3/CLK
0.878 0.340 tC2Q RF 5 u_psram_top/u_psram_sync/lock_cnt_1_s3/Q
1.589 0.711 tNET FF 1 u_psram_top/u_psram_sync/n47_s2/I1
2.403 0.814 tINS FF 4 u_psram_top/u_psram_sync/n47_s2/F
3.115 0.711 tNET FF 1 u_psram_top/u_psram_sync/n44_s2/I3
3.579 0.464 tINS FF 6 u_psram_top/u_psram_sync/n44_s2/F
4.290 0.711 tNET FF 1 u_psram_top/u_psram_sync/n38_s2/I1
5.104 0.814 tINS FF 1 u_psram_top/u_psram_sync/n38_s2/F
5.816 0.711 tNET FF 1 u_psram_top/u_psram_sync/n38_s5/I1
6.630 0.814 tINS FF 1 u_psram_top/u_psram_sync/n38_s5/F
7.341 0.711 tNET FF 1 u_psram_top/u_psram_sync/lock_cnt_13_s3/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 31 clk_ibuf/O
20.538 0.538 tNET RR 1 u_psram_top/u_psram_sync/lock_cnt_13_s3/CLK
20.242 -0.296 tSu 1 u_psram_top/u_psram_sync/lock_cnt_13_s3
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 2.907, 42.728%; route: 3.557, 52.280%; tC2Q: 0.340, 4.992%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 3

Path Summary:
Slack 12.900
Data Arrival Time 7.341
Data Required Time 20.242
From u_psram_top/u_psram_sync/cs_memsync_5_s0
To u_psram_top/u_psram_sync/flag_1_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 31 clk_ibuf/O
0.538 0.538 tNET RR 1 u_psram_top/u_psram_sync/cs_memsync_5_s0/CLK
0.878 0.340 tC2Q RF 6 u_psram_top/u_psram_sync/cs_memsync_5_s0/Q
1.589 0.711 tNET FF 1 u_psram_top/u_psram_sync/n326_s13/I1
2.403 0.814 tINS FF 4 u_psram_top/u_psram_sync/n326_s13/F
3.115 0.711 tNET FF 1 u_psram_top/u_psram_sync/n348_s11/I1
3.929 0.814 tINS FF 1 u_psram_top/u_psram_sync/n348_s11/F
4.640 0.711 tNET FF 1 u_psram_top/u_psram_sync/n348_s7/I3
5.104 0.464 tINS FF 2 u_psram_top/u_psram_sync/n348_s7/F
5.816 0.711 tNET FF 1 u_psram_top/u_psram_sync/n348_s5/I1
6.630 0.814 tINS FF 1 u_psram_top/u_psram_sync/n348_s5/F
7.341 0.711 tNET FF 1 u_psram_top/u_psram_sync/flag_1_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 31 clk_ibuf/O
20.538 0.538 tNET RR 1 u_psram_top/u_psram_sync/flag_1_s0/CLK
20.242 -0.296 tSu 1 u_psram_top/u_psram_sync/flag_1_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 2.907, 42.728%; route: 3.557, 52.280%; tC2Q: 0.340, 4.992%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 4

Path Summary:
Slack 13.105
Data Arrival Time 7.136
Data Required Time 20.242
From u_psram_top/u_psram_sync/lock_cnt_1_s3
To u_psram_top/u_psram_sync/lock_cnt_9_s3
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 31 clk_ibuf/O
0.538 0.538 tNET RR 1 u_psram_top/u_psram_sync/lock_cnt_1_s3/CLK
0.878 0.340 tC2Q RF 5 u_psram_top/u_psram_sync/lock_cnt_1_s3/Q
1.589 0.711 tNET FF 1 u_psram_top/u_psram_sync/n47_s2/I1
2.403 0.814 tINS FF 4 u_psram_top/u_psram_sync/n47_s2/F
3.115 0.711 tNET FF 1 u_psram_top/u_psram_sync/n44_s2/I3
3.579 0.464 tINS FF 6 u_psram_top/u_psram_sync/n44_s2/F
4.290 0.711 tNET FF 1 u_psram_top/u_psram_sync/n42_s2/I2
4.899 0.609 tINS FF 3 u_psram_top/u_psram_sync/n42_s2/F
5.610 0.711 tNET FF 1 u_psram_top/u_psram_sync/n42_s5/I1
6.425 0.814 tINS FF 1 u_psram_top/u_psram_sync/n42_s5/F
7.136 0.711 tNET FF 1 u_psram_top/u_psram_sync/lock_cnt_9_s3/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 31 clk_ibuf/O
20.538 0.538 tNET RR 1 u_psram_top/u_psram_sync/lock_cnt_9_s3/CLK
20.242 -0.296 tSu 1 u_psram_top/u_psram_sync/lock_cnt_9_s3
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 2.702, 40.946%; route: 3.557, 53.907%; tC2Q: 0.340, 5.147%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 5

Path Summary:
Slack 13.105
Data Arrival Time 7.136
Data Required Time 20.242
From u_psram_top/u_psram_sync/lock_cnt_1_s3
To u_psram_top/u_psram_sync/lock_cnt_14_s3
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 31 clk_ibuf/O
0.538 0.538 tNET RR 1 u_psram_top/u_psram_sync/lock_cnt_1_s3/CLK
0.878 0.340 tC2Q RF 5 u_psram_top/u_psram_sync/lock_cnt_1_s3/Q
1.589 0.711 tNET FF 1 u_psram_top/u_psram_sync/n47_s2/I1
2.403 0.814 tINS FF 4 u_psram_top/u_psram_sync/n47_s2/F
3.115 0.711 tNET FF 1 u_psram_top/u_psram_sync/n44_s2/I3
3.579 0.464 tINS FF 6 u_psram_top/u_psram_sync/n44_s2/F
4.290 0.711 tNET FF 1 u_psram_top/u_psram_sync/n37_s2/I2
4.899 0.609 tINS FF 2 u_psram_top/u_psram_sync/n37_s2/F
5.610 0.711 tNET FF 1 u_psram_top/u_psram_sync/n37_s5/I1
6.425 0.814 tINS FF 1 u_psram_top/u_psram_sync/n37_s5/F
7.136 0.711 tNET FF 1 u_psram_top/u_psram_sync/lock_cnt_14_s3/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 31 clk_ibuf/O
20.538 0.538 tNET RR 1 u_psram_top/u_psram_sync/lock_cnt_14_s3/CLK
20.242 -0.296 tSu 1 u_psram_top/u_psram_sync/lock_cnt_14_s3
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 2.702, 40.946%; route: 3.557, 53.907%; tC2Q: 0.340, 5.147%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%