Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\ahb_def_slave.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\BusMatrix.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\can.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\can_top.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_adder.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_ahb.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_alu_dec.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_core.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_ctl.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_ctl_add3.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_ahb_dec.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_ahb_mux.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_bp.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_ctl.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_define.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_dw.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_mtx.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_mtx_dbg.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_mtx_sys.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_rom_tb.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_sys.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_tcm.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_undefs.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_decoder.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_defs.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dp.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_excpt.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_fetch.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_fns.vh D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_matrix_check_fns.vh D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_mem_ctl.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_multiplier.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_multiply_shift.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_mux4.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_nvic.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_nvic_ahb.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_nvic_ahb_os.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_nvic_defs.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_nvic_main.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_nvic_pri_lvl.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_nvic_pri_num.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_nvic_tree.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_nvic_undefs.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_reg_bank.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_shifter.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_undefs.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_ethmac_miim_wrapper.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_ethmac_rx_buffer_to_ahb.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_ethmac_rx_to_buffer.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_ethmac_rx_wrapper.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_ethmac_sdp_wrapper_32bit.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_ethmac_tx_wrapper.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_ethmac_wrapper.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_gpio.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_ahbif_ctrl.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_arbiter.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_async_fifo_clr.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_config.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_const.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_ctrl.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_eilmif_ctrl.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_fifo.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_gck.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_pad_lib.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_reg.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_regif.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_regif_ctrl.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_spiif.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_sync.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_sync_l2l.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_sync_p2p.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_to_iop.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_dualtimers.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_dualtimers_defs.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_dualtimers_frc.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_spi.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_timer.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_autocorrelation.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_balancefilter.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_collector.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_crngt_to_trng.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_dx_inv_chain.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_dx_trng_top.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_dxm_ff.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_dxm_interrupt_low.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_dxm_mux.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_dxm_mux_clk.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_dxm_sync.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_ehr.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_entropy_gen.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_gtech_models.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_lfsr_new.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_line.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_noise_gen.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_pmf_table.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_prng_top_wrap.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_reg_file.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_rng_engine.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_rng_misc.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_rng_top.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_rng_top_wrap_unconnected.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_rosc.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_rst_logic.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_sample_cntr.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_slave_bus_ifc.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_sync.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_tests_misc.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_top.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_uart.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_watchdog.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_watchdog_defs.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_watchdog_frc.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_iop_gpio.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\CortexM1Dbg.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\CortexM1DbgIntegration.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\CortexM1DbgIntegrationWrapper.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\dapahbap.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPAhbApAhbSync.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPAhbApDapSync.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPAhbApDefs.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPAhbApMst.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPAhbApSlv.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPAhbApSyn.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPDecMux.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPDpApbDefs.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPDpApbSync.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPDpEnSync.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPDpIMux.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPDpSync.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPJtagDpDefs.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPJtagDpProtocol.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPSwDpApbIf.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPSwDpDefs.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPSwDpProtocol.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPSwDpSync.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\dapswjdp.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPSwjDpDefs.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPSwjWatcher.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\ddr3_1_4code_hs.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\ddr3_to_ahb_top.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DDR3_TOP.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\dtcmdbg.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\eth_mac.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\eth_mac_top.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\Gowin_EMPU_M1_top.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\GowinAhbExt.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\GowinCM1AhbExt.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\GowinCM1AhbExtWrapper.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\gw_ahb_psram.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\gw_apb_i2c.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\gw_apb_int_wrapper.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\gw_apb_sd.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\gw_gpio.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\InputStage.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\itcmdbg.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\MatrixDecodeS0.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\MatrixDecodeS1.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\MatrixDecodeS2.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\OutputArb1.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\OutputArb2.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\OutputArb3.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\OutputStage1.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\OutputStage2.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\OutputStage3.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\p_sse050_interconnect_f0_ahb_to_apb.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\p_sse050_interconnect_f0_apb_slave_mux.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\psram_code.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\PSRAM_TOP.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\rng_addr_params.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\rng_cc_params.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\rng_params.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\Rtc.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\RtcApbif.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\RtcControl.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\RtcCounter.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\RtcInterrupt.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\RtcParams.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\RtcRevAnd.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\RtcSynctoPCLK.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\RtcUpdate.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\sse050_int_apb_decoder.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\sse050_integration_peripherals.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\sync_p2p.v F:\EMB_pub\embedded\arm\cortex_m1\bootload\rls\bootload\ref_design\FPGA_RefDesign\gowin_empu_m1\src\gowin_empu_m1\temp\gw_empu_m1\cm1_option_defs.v F:\EMB_pub\embedded\arm\cortex_m1\bootload\rls\bootload\ref_design\FPGA_RefDesign\gowin_empu_m1\src\gowin_empu_m1\temp\gw_empu_m1\ahb_option_defs.v F:\EMB_pub\embedded\arm\cortex_m1\bootload\rls\bootload\ref_design\FPGA_RefDesign\gowin_empu_m1\src\gowin_empu_m1\temp\gw_empu_m1\parameter.vh F:\EMB_pub\embedded\arm\cortex_m1\bootload\rls\bootload\ref_design\FPGA_RefDesign\gowin_empu_m1\src\gowin_empu_m1\temp\gw_empu_m1\triple_speed_mac_param.v F:\EMB_pub\embedded\arm\cortex_m1\bootload\rls\bootload\ref_design\FPGA_RefDesign\gowin_empu_m1\src\gowin_empu_m1\temp\gw_empu_m1\triple_speed_mac_define.v F:\EMB_pub\embedded\arm\cortex_m1\bootload\rls\bootload\ref_design\FPGA_RefDesign\gowin_empu_m1\src\gowin_empu_m1\temp\gw_empu_m1\DDR3_define.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.11.02 (64-bit) |
| Part Number | GW5A-LV25UG324C2/I1 |
| Device | GW5A-25 |
| Device Version | A |
| Created Time | Wed May 21 18:04:42 2025 |
| Legal Announcement | Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | Gowin_EMPU_M1_Top |
| Synthesis Process | Running parser: CPU time = 0h 0m 5s, Elapsed time = 0h 0m 8s, Peak memory usage = 181.852MB Running netlist conversion: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.158s, Peak memory usage = 181.852MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 181.852MB Optimizing Phase 1: CPU time = 0h 0m 0.39s, Elapsed time = 0h 0m 0.425s, Peak memory usage = 181.852MB Optimizing Phase 2: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 181.852MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.75s, Elapsed time = 0h 0m 0.843s, Peak memory usage = 181.852MB Inferring Phase 1: CPU time = 0h 0m 0.609s, Elapsed time = 0h 0m 0.671s, Peak memory usage = 181.852MB Inferring Phase 2: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.087s, Peak memory usage = 181.852MB Inferring Phase 3: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.037s, Peak memory usage = 181.852MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 181.852MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.437s, Elapsed time = 0h 0m 0.428s, Peak memory usage = 181.852MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.531s, Elapsed time = 0h 0m 0.544s, Peak memory usage = 181.852MB Tech-Mapping Phase 3: CPU time = 0h 0m 31s, Elapsed time = 0h 0m 32s, Peak memory usage = 181.852MB Tech-Mapping Phase 4: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 181.852MB Generate output files: CPU time = 0h 0m 0.796s, Elapsed time = 0h 0m 2s, Peak memory usage = 204.004MB |
| Total Time and Memory Usage | CPU time = 0h 0m 43s, Elapsed time = 0h 0m 49s, Peak memory usage = 204.004MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 31 |
| I/O Buf | 31 |
| IBUF | 5 |
| OBUF | 3 |
| IOBUF | 23 |
| Register | 3937 |
| DFFSE | 1 |
| DFFRE | 808 |
| DFFPE | 142 |
| DFFCE | 2984 |
| DLCE | 2 |
| LUT | 7724 |
| LUT2 | 629 |
| LUT3 | 2554 |
| LUT4 | 4541 |
| ALU | 282 |
| ALU | 282 |
| INV | 27 |
| INV | 27 |
| DSP | |
| MULT27X36 | 2 |
| BSRAM | 32 |
| DPB | 32 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 8033(7751 LUT, 282 ALU) / 23040 | 35% |
| Register | 3937 / 23685 | 17% |
| --Register as Latch | 2 / 23685 | <1% |
| --Register as FF | 3935 / 23685 | 17% |
| BSRAM | 32 / 56 | 58% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | HCLK | Base | 10.000 | 100.000 | 0.000 | 5.000 | HCLK_ibuf/I | ||
| 2 | JTAG_9 | Base | 10.000 | 100.000 | 0.000 | 5.000 | JTAG_9_ibuf/I | ||
| 3 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_w_clk_slv_20 | Base | 10.000 | 100.000 | 0.000 | 5.000 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_w_clk_slv_s9/F |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | HCLK | 100.000(MHz) | 79.302(MHz) | 21 | TOP |
| 2 | JTAG_9 | 100.000(MHz) | 125.298(MHz) | 12 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | -4.184 |
| Data Arrival Time | 9.422 |
| Data Required Time | 5.238 |
| From | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/slave_cmd_6_s3 |
| To | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_out_slv_r_1_s2 |
| Launch Clk | HCLK[F] |
| Latch Clk | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_w_clk_slv_20[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | HCLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 3803 | HCLK_ibuf/O |
| 0.300 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/slave_cmd_6_s3/CLK |
| 0.606 | 0.306 | tC2Q | RR | 7 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/slave_cmd_6_s3/Q |
| 0.906 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_trans_end_sclk_Z_s3/I0 |
| 1.327 | 0.421 | tINS | RR | 5 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_trans_end_sclk_Z_s3/F |
| 1.627 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_trans_end_sclk_Z_s1/I0 |
| 2.048 | 0.421 | tINS | RR | 10 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_trans_end_sclk_Z_s1/F |
| 2.348 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_word_len_0_s4/I0 |
| 2.769 | 0.421 | tINS | RR | 4 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_word_len_0_s4/F |
| 3.069 | 0.300 | tNET | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1232_s/I0 |
| 3.514 | 0.445 | tINS | RF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1232_s/COUT |
| 3.514 | 0.000 | tNET | FF | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1231_s/CIN |
| 3.709 | 0.195 | tINS | FR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1231_s/SUM |
| 4.009 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/tx_ptr_1_s0/I0 |
| 4.430 | 0.421 | tINS | RR | 24 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/tx_ptr_1_s0/F |
| 4.730 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1250_s43/I2 |
| 5.099 | 0.369 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1250_s43/F |
| 5.399 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1250_s35/I1 |
| 5.508 | 0.109 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1250_s35/O |
| 5.808 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1250_s31/I1 |
| 5.877 | 0.069 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1250_s31/O |
| 6.177 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1250_s29/I1 |
| 6.246 | 0.069 | tINS | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1250_s29/O |
| 6.546 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n363_s7/I0 |
| 6.967 | 0.421 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n363_s7/F |
| 7.267 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n363_s3/I1 |
| 7.680 | 0.413 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n363_s3/F |
| 7.980 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n363_s1/I0 |
| 8.401 | 0.421 | tINS | RR | 4 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n363_s1/F |
| 8.701 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n363_s0/I0 |
| 9.122 | 0.421 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n363_s0/F |
| 9.422 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_out_slv_r_1_s2/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 5.000 | 0.000 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_w_clk_slv_20 | |||
| 5.000 | 0.000 | tCL | FF | 11 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_w_clk_slv_s9/F |
| 5.280 | 0.280 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_out_slv_r_1_s2/CLK |
| 5.245 | -0.035 | tUnc | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_out_slv_r_1_s2 | ||
| 5.238 | -0.007 | tSu | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_out_slv_r_1_s2 |
| Clock Skew: | -0.020 |
| Setup Relationship: | 5.000 |
| Logic Level: | 13 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
| Arrival Data Path Delay: | cell: 4.616, 50.602%; route: 4.200, 46.043%; tC2Q: 0.306, 3.355% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
Path 2
Path Summary:| Slack | -4.132 |
| Data Arrival Time | 9.370 |
| Data Required Time | 5.238 |
| From | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/slave_cmd_6_s3 |
| To | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_out_slv_r_0_s2 |
| Launch Clk | HCLK[F] |
| Latch Clk | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_w_clk_slv_20[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | HCLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 3803 | HCLK_ibuf/O |
| 0.300 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/slave_cmd_6_s3/CLK |
| 0.606 | 0.306 | tC2Q | RR | 7 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/slave_cmd_6_s3/Q |
| 0.906 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_trans_end_sclk_Z_s3/I0 |
| 1.327 | 0.421 | tINS | RR | 5 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_trans_end_sclk_Z_s3/F |
| 1.627 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_trans_end_sclk_Z_s1/I0 |
| 2.048 | 0.421 | tINS | RR | 10 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_trans_end_sclk_Z_s1/F |
| 2.348 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_word_len_0_s4/I0 |
| 2.769 | 0.421 | tINS | RR | 4 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_word_len_0_s4/F |
| 3.069 | 0.300 | tNET | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1232_s/I0 |
| 3.514 | 0.445 | tINS | RF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1232_s/COUT |
| 3.514 | 0.000 | tNET | FF | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1231_s/CIN |
| 3.709 | 0.195 | tINS | FR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1231_s/SUM |
| 4.009 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/tx_ptr_1_s0/I0 |
| 4.430 | 0.421 | tINS | RR | 24 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/tx_ptr_1_s0/F |
| 4.730 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1250_s43/I2 |
| 5.099 | 0.369 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1250_s43/F |
| 5.399 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1250_s35/I1 |
| 5.508 | 0.109 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1250_s35/O |
| 5.808 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1250_s31/I1 |
| 5.877 | 0.069 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1250_s31/O |
| 6.177 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1250_s29/I1 |
| 6.246 | 0.069 | tINS | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1250_s29/O |
| 6.546 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n363_s7/I0 |
| 6.967 | 0.421 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n363_s7/F |
| 7.267 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n363_s3/I1 |
| 7.680 | 0.413 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n363_s3/F |
| 7.980 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n363_s1/I0 |
| 8.401 | 0.421 | tINS | RR | 4 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n363_s1/F |
| 8.701 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n366_s2/I2 |
| 9.070 | 0.369 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n366_s2/F |
| 9.370 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_out_slv_r_0_s2/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 5.000 | 0.000 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_w_clk_slv_20 | |||
| 5.000 | 0.000 | tCL | FF | 11 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_w_clk_slv_s9/F |
| 5.280 | 0.280 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_out_slv_r_0_s2/CLK |
| 5.245 | -0.035 | tUnc | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_out_slv_r_0_s2 | ||
| 5.238 | -0.007 | tSu | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_out_slv_r_0_s2 |
| Clock Skew: | -0.020 |
| Setup Relationship: | 5.000 |
| Logic Level: | 13 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
| Arrival Data Path Delay: | cell: 4.564, 50.319%; route: 4.200, 46.307%; tC2Q: 0.306, 3.374% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
Path 3
Path Summary:| Slack | -2.610 |
| Data Arrival Time | 12.859 |
| Data Required Time | 10.249 |
| From | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/slave_cmd_6_s3 |
| To | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_0_s1 |
| Launch Clk | HCLK[R] |
| Latch Clk | HCLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | HCLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 3803 | HCLK_ibuf/O |
| 0.300 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/slave_cmd_6_s3/CLK |
| 0.606 | 0.306 | tC2Q | RR | 7 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/slave_cmd_6_s3/Q |
| 0.906 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/spi_quad_Z_s6/I0 |
| 1.327 | 0.421 | tINS | RR | 4 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/spi_quad_Z_s6/F |
| 1.627 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n562_s6/I0 |
| 2.048 | 0.421 | tINS | RR | 4 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n562_s6/F |
| 2.348 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_wr_num_0_s2/I0 |
| 2.769 | 0.421 | tINS | RR | 12 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_wr_num_0_s2/F |
| 3.069 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_wr_num_0_s1/I2 |
| 3.438 | 0.369 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_wr_num_0_s1/F |
| 3.738 | 0.300 | tNET | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n388_s0/I1 |
| 4.188 | 0.450 | tINS | RF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n388_s0/COUT |
| 4.188 | 0.000 | tNET | FF | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n389_s0/CIN |
| 4.228 | 0.040 | tINS | FR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n389_s0/COUT |
| 4.228 | 0.000 | tNET | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n390_s0/CIN |
| 4.268 | 0.040 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n390_s0/COUT |
| 4.268 | 0.000 | tNET | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n391_s0/CIN |
| 4.308 | 0.040 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n391_s0/COUT |
| 4.308 | 0.000 | tNET | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n392_s0/CIN |
| 4.348 | 0.040 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n392_s0/COUT |
| 4.348 | 0.000 | tNET | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n393_s0/CIN |
| 4.388 | 0.040 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n393_s0/COUT |
| 4.388 | 0.000 | tNET | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n394_s0/CIN |
| 4.428 | 0.040 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n394_s0/COUT |
| 4.428 | 0.000 | tNET | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n395_s0/CIN |
| 4.468 | 0.040 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n395_s0/COUT |
| 4.468 | 0.000 | tNET | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n396_s0/CIN |
| 4.508 | 0.040 | tINS | RR | 5 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n396_s0/COUT |
| 4.808 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n583_s16/I0 |
| 5.229 | 0.421 | tINS | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n583_s16/F |
| 5.529 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n583_s14/I2 |
| 5.898 | 0.369 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n583_s14/F |
| 6.198 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n583_s11/I1 |
| 6.611 | 0.413 | tINS | RR | 3 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n583_s11/F |
| 6.911 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_3_s10/I2 |
| 7.280 | 0.369 | tINS | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_3_s10/F |
| 7.580 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_0_s43/I3 |
| 7.790 | 0.210 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_0_s43/F |
| 8.090 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_0_s15/I2 |
| 8.459 | 0.369 | tINS | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_0_s15/F |
| 8.759 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_0_s5/I2 |
| 9.128 | 0.369 | tINS | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_0_s5/F |
| 9.428 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_0_s2/I2 |
| 9.797 | 0.369 | tINS | RR | 11 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_0_s2/F |
| 10.097 | 0.300 | tNET | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n9_s0/I1 |
| 10.547 | 0.450 | tINS | RF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n9_s0/COUT |
| 10.547 | 0.000 | tNET | FF | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n10_s0/CIN |
| 10.587 | 0.040 | tINS | FR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n10_s0/COUT |
| 10.587 | 0.000 | tNET | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n11_s0/CIN |
| 10.627 | 0.040 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n11_s0/COUT |
| 10.627 | 0.000 | tNET | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n12_s0/CIN |
| 10.667 | 0.040 | tINS | RR | 10 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n12_s0/COUT |
| 10.967 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_8_s9/I2 |
| 11.336 | 0.369 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_8_s9/F |
| 11.636 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_8_s6/I3 |
| 11.846 | 0.210 | tINS | RR | 10 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_8_s6/F |
| 12.146 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n497_s2/I1 |
| 12.559 | 0.413 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n497_s2/F |
| 12.859 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_0_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | HCLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 3803 | HCLK_ibuf/O |
| 10.300 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_0_s1/CLK |
| 10.249 | -0.051 | tSu | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_0_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 21 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
| Arrival Data Path Delay: | cell: 6.853, 54.567%; route: 5.400, 42.997%; tC2Q: 0.306, 2.436% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
Path 4
Path Summary:| Slack | -2.605 |
| Data Arrival Time | 12.656 |
| Data Required Time | 10.051 |
| From | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/slave_cmd_6_s3 |
| To | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_0_s1 |
| Launch Clk | HCLK[R] |
| Latch Clk | HCLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | HCLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 3803 | HCLK_ibuf/O |
| 0.300 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/slave_cmd_6_s3/CLK |
| 0.606 | 0.306 | tC2Q | RR | 7 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/slave_cmd_6_s3/Q |
| 0.906 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/spi_quad_Z_s6/I0 |
| 1.327 | 0.421 | tINS | RR | 4 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/spi_quad_Z_s6/F |
| 1.627 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n562_s6/I0 |
| 2.048 | 0.421 | tINS | RR | 4 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n562_s6/F |
| 2.348 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_wr_num_0_s2/I0 |
| 2.769 | 0.421 | tINS | RR | 12 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_wr_num_0_s2/F |
| 3.069 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_wr_num_0_s1/I2 |
| 3.438 | 0.369 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_wr_num_0_s1/F |
| 3.738 | 0.300 | tNET | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n388_s0/I1 |
| 4.188 | 0.450 | tINS | RF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n388_s0/COUT |
| 4.188 | 0.000 | tNET | FF | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n389_s0/CIN |
| 4.228 | 0.040 | tINS | FR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n389_s0/COUT |
| 4.228 | 0.000 | tNET | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n390_s0/CIN |
| 4.268 | 0.040 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n390_s0/COUT |
| 4.268 | 0.000 | tNET | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n391_s0/CIN |
| 4.308 | 0.040 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n391_s0/COUT |
| 4.308 | 0.000 | tNET | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n392_s0/CIN |
| 4.348 | 0.040 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n392_s0/COUT |
| 4.348 | 0.000 | tNET | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n393_s0/CIN |
| 4.388 | 0.040 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n393_s0/COUT |
| 4.388 | 0.000 | tNET | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n394_s0/CIN |
| 4.428 | 0.040 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n394_s0/COUT |
| 4.428 | 0.000 | tNET | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n395_s0/CIN |
| 4.468 | 0.040 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n395_s0/COUT |
| 4.468 | 0.000 | tNET | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n396_s0/CIN |
| 4.508 | 0.040 | tINS | RR | 5 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n396_s0/COUT |
| 4.808 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n583_s16/I0 |
| 5.229 | 0.421 | tINS | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n583_s16/F |
| 5.529 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n583_s14/I2 |
| 5.898 | 0.369 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n583_s14/F |
| 6.198 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n583_s11/I1 |
| 6.611 | 0.413 | tINS | RR | 3 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n583_s11/F |
| 6.911 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_3_s10/I2 |
| 7.280 | 0.369 | tINS | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_3_s10/F |
| 7.580 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_0_s43/I3 |
| 7.790 | 0.210 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_0_s43/F |
| 8.090 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_0_s15/I2 |
| 8.459 | 0.369 | tINS | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_0_s15/F |
| 8.759 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_0_s5/I2 |
| 9.128 | 0.369 | tINS | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_0_s5/F |
| 9.428 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_0_s2/I2 |
| 9.797 | 0.369 | tINS | RR | 11 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_0_s2/F |
| 10.097 | 0.300 | tNET | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n9_s0/I1 |
| 10.547 | 0.450 | tINS | RF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n9_s0/COUT |
| 10.547 | 0.000 | tNET | FF | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n10_s0/CIN |
| 10.587 | 0.040 | tINS | FR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n10_s0/COUT |
| 10.587 | 0.000 | tNET | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n11_s0/CIN |
| 10.627 | 0.040 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n11_s0/COUT |
| 10.627 | 0.000 | tNET | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n12_s0/CIN |
| 10.667 | 0.040 | tINS | RR | 10 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n12_s0/COUT |
| 10.967 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_8_s9/I2 |
| 11.336 | 0.369 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_8_s9/F |
| 11.636 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_8_s6/I3 |
| 11.846 | 0.210 | tINS | RR | 10 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_8_s6/F |
| 12.146 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_8_s3/I3 |
| 12.356 | 0.210 | tINS | RR | 9 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_8_s3/F |
| 12.656 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_0_s1/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | HCLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 3803 | HCLK_ibuf/O |
| 10.300 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_0_s1/CLK |
| 10.051 | -0.249 | tSu | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_0_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 21 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
| Arrival Data Path Delay: | cell: 6.650, 53.820%; route: 5.400, 43.703%; tC2Q: 0.306, 2.477% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
Path 5
Path Summary:| Slack | -2.605 |
| Data Arrival Time | 12.656 |
| Data Required Time | 10.051 |
| From | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/slave_cmd_6_s3 |
| To | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_1_s1 |
| Launch Clk | HCLK[R] |
| Latch Clk | HCLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | HCLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 3803 | HCLK_ibuf/O |
| 0.300 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/slave_cmd_6_s3/CLK |
| 0.606 | 0.306 | tC2Q | RR | 7 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/slave_cmd_6_s3/Q |
| 0.906 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/spi_quad_Z_s6/I0 |
| 1.327 | 0.421 | tINS | RR | 4 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/spi_quad_Z_s6/F |
| 1.627 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n562_s6/I0 |
| 2.048 | 0.421 | tINS | RR | 4 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n562_s6/F |
| 2.348 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_wr_num_0_s2/I0 |
| 2.769 | 0.421 | tINS | RR | 12 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_wr_num_0_s2/F |
| 3.069 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_wr_num_0_s1/I2 |
| 3.438 | 0.369 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_wr_num_0_s1/F |
| 3.738 | 0.300 | tNET | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n388_s0/I1 |
| 4.188 | 0.450 | tINS | RF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n388_s0/COUT |
| 4.188 | 0.000 | tNET | FF | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n389_s0/CIN |
| 4.228 | 0.040 | tINS | FR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n389_s0/COUT |
| 4.228 | 0.000 | tNET | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n390_s0/CIN |
| 4.268 | 0.040 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n390_s0/COUT |
| 4.268 | 0.000 | tNET | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n391_s0/CIN |
| 4.308 | 0.040 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n391_s0/COUT |
| 4.308 | 0.000 | tNET | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n392_s0/CIN |
| 4.348 | 0.040 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n392_s0/COUT |
| 4.348 | 0.000 | tNET | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n393_s0/CIN |
| 4.388 | 0.040 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n393_s0/COUT |
| 4.388 | 0.000 | tNET | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n394_s0/CIN |
| 4.428 | 0.040 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n394_s0/COUT |
| 4.428 | 0.000 | tNET | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n395_s0/CIN |
| 4.468 | 0.040 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n395_s0/COUT |
| 4.468 | 0.000 | tNET | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n396_s0/CIN |
| 4.508 | 0.040 | tINS | RR | 5 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n396_s0/COUT |
| 4.808 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n583_s16/I0 |
| 5.229 | 0.421 | tINS | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n583_s16/F |
| 5.529 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n583_s14/I2 |
| 5.898 | 0.369 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n583_s14/F |
| 6.198 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n583_s11/I1 |
| 6.611 | 0.413 | tINS | RR | 3 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n583_s11/F |
| 6.911 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_3_s10/I2 |
| 7.280 | 0.369 | tINS | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_3_s10/F |
| 7.580 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_0_s43/I3 |
| 7.790 | 0.210 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_0_s43/F |
| 8.090 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_0_s15/I2 |
| 8.459 | 0.369 | tINS | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_0_s15/F |
| 8.759 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_0_s5/I2 |
| 9.128 | 0.369 | tINS | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_0_s5/F |
| 9.428 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_0_s2/I2 |
| 9.797 | 0.369 | tINS | RR | 11 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_0_s2/F |
| 10.097 | 0.300 | tNET | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n9_s0/I1 |
| 10.547 | 0.450 | tINS | RF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n9_s0/COUT |
| 10.547 | 0.000 | tNET | FF | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n10_s0/CIN |
| 10.587 | 0.040 | tINS | FR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n10_s0/COUT |
| 10.587 | 0.000 | tNET | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n11_s0/CIN |
| 10.627 | 0.040 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n11_s0/COUT |
| 10.627 | 0.000 | tNET | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n12_s0/CIN |
| 10.667 | 0.040 | tINS | RR | 10 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n12_s0/COUT |
| 10.967 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_8_s9/I2 |
| 11.336 | 0.369 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_8_s9/F |
| 11.636 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_8_s6/I3 |
| 11.846 | 0.210 | tINS | RR | 10 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_8_s6/F |
| 12.146 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_8_s3/I3 |
| 12.356 | 0.210 | tINS | RR | 9 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_8_s3/F |
| 12.656 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_1_s1/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | HCLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 3803 | HCLK_ibuf/O |
| 10.300 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_1_s1/CLK |
| 10.051 | -0.249 | tSu | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_1_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 21 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
| Arrival Data Path Delay: | cell: 6.650, 53.820%; route: 5.400, 43.703%; tC2Q: 0.306, 2.477% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |