Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\ahb_def_slave.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\BusMatrix.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\can.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\can_top.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_adder.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_ahb.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_alu_dec.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_core.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_ctl.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_ctl_add3.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_ahb_dec.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_ahb_mux.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_bp.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_ctl.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_define.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_dw.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_mtx.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_mtx_dbg.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_mtx_sys.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_rom_tb.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_sys.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_tcm.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_undefs.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_decoder.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_defs.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dp.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_excpt.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_fetch.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_fns.vh D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_matrix_check_fns.vh D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_mem_ctl.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_multiplier.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_multiply_shift.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_mux4.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_nvic.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_nvic_ahb.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_nvic_ahb_os.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_nvic_defs.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_nvic_main.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_nvic_pri_lvl.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_nvic_pri_num.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_nvic_tree.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_nvic_undefs.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_reg_bank.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_shifter.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_undefs.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_ethmac_miim_wrapper.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_ethmac_rx_buffer_to_ahb.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_ethmac_rx_to_buffer.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_ethmac_rx_wrapper.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_ethmac_sdp_wrapper_32bit.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_ethmac_tx_wrapper.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_ethmac_wrapper.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_gpio.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_ahbif_ctrl.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_arbiter.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_async_fifo_clr.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_config.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_const.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_ctrl.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_eilmif_ctrl.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_fifo.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_gck.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_pad_lib.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_reg.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_regif.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_regif_ctrl.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_spiif.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_sync.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_sync_l2l.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_sync_p2p.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_to_iop.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_dualtimers.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_dualtimers_defs.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_dualtimers_frc.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_spi.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_timer.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_autocorrelation.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_balancefilter.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_collector.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_crngt_to_trng.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_dx_inv_chain.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_dx_trng_top.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_dxm_ff.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_dxm_interrupt_low.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_dxm_mux.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_dxm_mux_clk.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_dxm_sync.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_ehr.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_entropy_gen.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_gtech_models.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_lfsr_new.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_line.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_noise_gen.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_pmf_table.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_prng_top_wrap.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_reg_file.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_rng_engine.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_rng_misc.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_rng_top.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_rng_top_wrap_unconnected.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_rosc.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_rst_logic.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_sample_cntr.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_slave_bus_ifc.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_sync.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_tests_misc.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_top.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_uart.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_watchdog.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_watchdog_defs.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_watchdog_frc.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_iop_gpio.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\CortexM1Dbg.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\CortexM1DbgIntegration.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\CortexM1DbgIntegrationWrapper.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\dapahbap.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPAhbApAhbSync.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPAhbApDapSync.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPAhbApDefs.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPAhbApMst.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPAhbApSlv.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPAhbApSyn.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPDecMux.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPDpApbDefs.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPDpApbSync.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPDpEnSync.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPDpIMux.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPDpSync.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPJtagDpDefs.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPJtagDpProtocol.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPSwDpApbIf.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPSwDpDefs.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPSwDpProtocol.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPSwDpSync.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\dapswjdp.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPSwjDpDefs.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPSwjWatcher.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\ddr3_1_4code_hs.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\ddr3_to_ahb_top.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DDR3_TOP.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\dtcmdbg.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\eth_mac.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\eth_mac_top.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\Gowin_EMPU_M1_top.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\GowinAhbExt.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\GowinCM1AhbExt.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\GowinCM1AhbExtWrapper.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\gw_ahb_psram.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\gw_apb_i2c.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\gw_apb_int_wrapper.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\gw_apb_sd.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\gw_gpio.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\InputStage.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\itcmdbg.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\MatrixDecodeS0.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\MatrixDecodeS1.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\MatrixDecodeS2.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\OutputArb1.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\OutputArb2.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\OutputArb3.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\OutputStage1.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\OutputStage2.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\OutputStage3.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\p_sse050_interconnect_f0_ahb_to_apb.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\p_sse050_interconnect_f0_apb_slave_mux.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\psram_code.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\PSRAM_TOP.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\rng_addr_params.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\rng_cc_params.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\rng_params.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\Rtc.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\RtcApbif.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\RtcControl.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\RtcCounter.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\RtcInterrupt.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\RtcParams.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\RtcRevAnd.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\RtcSynctoPCLK.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\RtcUpdate.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\sse050_int_apb_decoder.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\sse050_integration_peripherals.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\sync_p2p.v F:\EMB_pub\embedded\arm\cortex_m1\ref_design\2.3\FPGA_RefDesign\DK_START_GW5A25_V2.0\gowin_empu_m1\cm1_ddr3_demo\src\gowin_empu_m1\temp\gw_empu_m1\cm1_option_defs.v F:\EMB_pub\embedded\arm\cortex_m1\ref_design\2.3\FPGA_RefDesign\DK_START_GW5A25_V2.0\gowin_empu_m1\cm1_ddr3_demo\src\gowin_empu_m1\temp\gw_empu_m1\ahb_option_defs.v F:\EMB_pub\embedded\arm\cortex_m1\ref_design\2.3\FPGA_RefDesign\DK_START_GW5A25_V2.0\gowin_empu_m1\cm1_ddr3_demo\src\gowin_empu_m1\temp\gw_empu_m1\parameter.vh F:\EMB_pub\embedded\arm\cortex_m1\ref_design\2.3\FPGA_RefDesign\DK_START_GW5A25_V2.0\gowin_empu_m1\cm1_ddr3_demo\src\gowin_empu_m1\temp\gw_empu_m1\triple_speed_mac_param.v F:\EMB_pub\embedded\arm\cortex_m1\ref_design\2.3\FPGA_RefDesign\DK_START_GW5A25_V2.0\gowin_empu_m1\cm1_ddr3_demo\src\gowin_empu_m1\temp\gw_empu_m1\triple_speed_mac_define.v F:\EMB_pub\embedded\arm\cortex_m1\ref_design\2.3\FPGA_RefDesign\DK_START_GW5A25_V2.0\gowin_empu_m1\cm1_ddr3_demo\src\gowin_empu_m1\temp\gw_empu_m1\DDR3_define.v |
GowinSynthesis Constraints File | --- |
Tool Version | V1.9.11.02 (64-bit) |
Part Number | GW5A-LV25UG324C2/I1 |
Device | GW5A-25 |
Device Version | A |
Created Time | Thu May 22 16:18:41 2025 |
Legal Announcement | Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | Gowin_EMPU_M1_Top |
Synthesis Process | Running parser: CPU time = 0h 0m 6s, Elapsed time = 0h 0m 6s, Peak memory usage = 228.293MB Running netlist conversion: CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.208s, Peak memory usage = 228.293MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 228.293MB Optimizing Phase 1: CPU time = 0h 0m 0.875s, Elapsed time = 0h 0m 0.893s, Peak memory usage = 228.293MB Optimizing Phase 2: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 228.293MB Running inference: Inferring Phase 0: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 228.293MB Inferring Phase 1: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 228.293MB Inferring Phase 2: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.153s, Peak memory usage = 228.293MB Inferring Phase 3: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.061s, Peak memory usage = 228.293MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 228.293MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.625s, Elapsed time = 0h 0m 0.653s, Peak memory usage = 228.293MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.921s, Elapsed time = 0h 0m 0.918s, Peak memory usage = 228.293MB Tech-Mapping Phase 3: CPU time = 0h 0m 34s, Elapsed time = 0h 0m 34s, Peak memory usage = 228.293MB Tech-Mapping Phase 4: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 228.293MB Generate output files: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 264.039MB |
Total Time and Memory Usage | CPU time = 0h 0m 51s, Elapsed time = 0h 0m 51s, Peak memory usage = 264.039MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 68 |
I/O Buf | 65 |
    IBUF | 8 |
    OBUF | 29 |
    TBUF | 2 |
    IOBUF | 23 |
    ELVDS_OBUF | 1 |
    ELVDS_IOBUF | 2 |
Register | 7303 |
    DFFSE | 2 |
    DFFRE | 1057 |
    DFFPE | 207 |
    DFFCE | 6035 |
    DLCE | 2 |
LUT | 9261 |
    LUT2 | 760 |
    LUT3 | 3440 |
    LUT4 | 5061 |
ALU | 406 |
    ALU | 406 |
INV | 35 |
    INV | 35 |
IOLOGIC | 76 |
    IDES8_MEM | 16 |
    OSER8 | 24 |
    OSER8_MEM | 20 |
    IODELAY | 16 |
DSP | |
    MULT27X36 | 2 |
BSRAM | 40 |
    SDPB | 8 |
    DPB | 32 |
CLOCK | 4 |
    CLKDIV | 1 |
    DQS | 2 |
    DDRDLL | 1 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 9702(9296 LUT, 406 ALU) / 23040 | 43% |
Register | 7303 / 23685 | 31% |
  --Register as Latch | 2 / 23685 | <1% |
  --Register as FF | 7301 / 23685 | 31% |
BSRAM | 40 / 56 | 72% |
Timing
Clock Summary:
NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|---|
1 | DDR_MEM_CLK_I | Base | 10.000 | 100.000 | 0.000 | 5.000 | DDR_MEM_CLK_I_ibuf/I | ||
2 | HCLK | Base | 10.000 | 100.000 | 0.000 | 5.000 | HCLK_ibuf/I | ||
3 | JTAG_9 | Base | 10.000 | 100.000 | 0.000 | 5.000 | JTAG_9_ibuf/I | ||
4 | DDR_CLK_I | Base | 10.000 | 100.000 | 0.000 | 5.000 | DDR_CLK_I_ibuf/I | ||
5 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_w_clk_slv_20 | Base | 10.000 | 100.000 | 0.000 | 5.000 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_w_clk_slv_s9/F | ||
6 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb_ddr3/u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | Generated | 40.000 | 25.000 | 0.000 | 20.000 | DDR_MEM_CLK_I_ibuf/I | DDR_MEM_CLK_I | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb_ddr3/u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
Max Frequency Summary:
NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | DDR_MEM_CLK_I | 100.000(MHz) | 1394.296(MHz) | 1 | TOP |
2 | HCLK | 100.000(MHz) | 82.420(MHz) | 20 | TOP |
3 | JTAG_9 | 100.000(MHz) | 147.016(MHz) | 10 | TOP |
4 | DDR_CLK_I | 100.000(MHz) | 263.992(MHz) | 6 | TOP |
5 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb_ddr3/u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | 25.000(MHz) | 216.450(MHz) | 3 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | -4.176 |
Data Arrival Time | 9.414 |
Data Required Time | 5.238 |
From | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/slave_cmd_3_s1 |
To | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_out_slv_r_1_s2 |
Launch Clk | HCLK[F] |
Latch Clk | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_w_clk_slv_20[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | HCLK | |||
0.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
0.000 | 0.000 | tINS | RR | 3724 | HCLK_ibuf/O |
0.300 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/slave_cmd_3_s1/CLK |
0.606 | 0.306 | tC2Q | RR | 5 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/slave_cmd_3_s1/Q |
0.906 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/slave_cmd_wr_sclk_Z_s2/I0 |
1.327 | 0.421 | tINS | RR | 8 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/slave_cmd_wr_sclk_Z_s2/F |
1.627 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_word_len_4_s8/I0 |
2.048 | 0.421 | tINS | RR | 8 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_word_len_4_s8/F |
2.348 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_word_len_0_s4/I1 |
2.761 | 0.413 | tINS | RR | 4 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_word_len_0_s4/F |
3.061 | 0.300 | tNET | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1232_s/I0 |
3.506 | 0.445 | tINS | RF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1232_s/COUT |
3.506 | 0.000 | tNET | FF | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1231_s/CIN |
3.701 | 0.195 | tINS | FR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1231_s/SUM |
4.001 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/tx_ptr_1_s0/I0 |
4.422 | 0.421 | tINS | RR | 24 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/tx_ptr_1_s0/F |
4.722 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1250_s43/I2 |
5.091 | 0.369 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1250_s43/F |
5.391 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1250_s35/I1 |
5.500 | 0.109 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1250_s35/O |
5.800 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1250_s31/I1 |
5.869 | 0.069 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1250_s31/O |
6.169 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1250_s29/I1 |
6.238 | 0.069 | tINS | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1250_s29/O |
6.538 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n363_s7/I0 |
6.959 | 0.421 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n363_s7/F |
7.259 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n363_s3/I1 |
7.672 | 0.413 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n363_s3/F |
7.972 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n363_s1/I0 |
8.393 | 0.421 | tINS | RR | 4 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n363_s1/F |
8.693 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n363_s0/I0 |
9.114 | 0.421 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n363_s0/F |
9.414 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_out_slv_r_1_s2/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
5.000 | 0.000 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_w_clk_slv_20 | |||
5.000 | 0.000 | tCL | FF | 11 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_w_clk_slv_s9/F |
5.280 | 0.280 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_out_slv_r_1_s2/CLK |
5.245 | -0.035 | tUnc | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_out_slv_r_1_s2 | ||
5.238 | -0.007 | tSu | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_out_slv_r_1_s2 |
Clock Skew: | -0.020 |
Setup Relationship: | 5.000 |
Logic Level: | 13 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
Arrival Data Path Delay: | cell: 4.608, 50.560%; route: 4.200, 46.083%; tC2Q: 0.306, 3.357% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
Path 2
Path Summary:Slack | -4.124 |
Data Arrival Time | 9.362 |
Data Required Time | 5.238 |
From | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/slave_cmd_3_s1 |
To | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_out_slv_r_0_s2 |
Launch Clk | HCLK[F] |
Latch Clk | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_w_clk_slv_20[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | HCLK | |||
0.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
0.000 | 0.000 | tINS | RR | 3724 | HCLK_ibuf/O |
0.300 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/slave_cmd_3_s1/CLK |
0.606 | 0.306 | tC2Q | RR | 5 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/slave_cmd_3_s1/Q |
0.906 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/slave_cmd_wr_sclk_Z_s2/I0 |
1.327 | 0.421 | tINS | RR | 8 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/slave_cmd_wr_sclk_Z_s2/F |
1.627 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_word_len_4_s8/I0 |
2.048 | 0.421 | tINS | RR | 8 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_word_len_4_s8/F |
2.348 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_word_len_0_s4/I1 |
2.761 | 0.413 | tINS | RR | 4 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_word_len_0_s4/F |
3.061 | 0.300 | tNET | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1232_s/I0 |
3.506 | 0.445 | tINS | RF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1232_s/COUT |
3.506 | 0.000 | tNET | FF | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1231_s/CIN |
3.701 | 0.195 | tINS | FR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1231_s/SUM |
4.001 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/tx_ptr_1_s0/I0 |
4.422 | 0.421 | tINS | RR | 24 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/tx_ptr_1_s0/F |
4.722 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1250_s43/I2 |
5.091 | 0.369 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1250_s43/F |
5.391 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1250_s35/I1 |
5.500 | 0.109 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1250_s35/O |
5.800 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1250_s31/I1 |
5.869 | 0.069 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1250_s31/O |
6.169 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1250_s29/I1 |
6.238 | 0.069 | tINS | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1250_s29/O |
6.538 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n363_s7/I0 |
6.959 | 0.421 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n363_s7/F |
7.259 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n363_s3/I1 |
7.672 | 0.413 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n363_s3/F |
7.972 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n363_s1/I0 |
8.393 | 0.421 | tINS | RR | 4 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n363_s1/F |
8.693 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n366_s2/I2 |
9.062 | 0.369 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n366_s2/F |
9.362 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_out_slv_r_0_s2/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
5.000 | 0.000 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_w_clk_slv_20 | |||
5.000 | 0.000 | tCL | FF | 11 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_w_clk_slv_s9/F |
5.280 | 0.280 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_out_slv_r_0_s2/CLK |
5.245 | -0.035 | tUnc | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_out_slv_r_0_s2 | ||
5.238 | -0.007 | tSu | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_out_slv_r_0_s2 |
Clock Skew: | -0.020 |
Setup Relationship: | 5.000 |
Logic Level: | 13 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
Arrival Data Path Delay: | cell: 4.556, 50.276%; route: 4.200, 46.347%; tC2Q: 0.306, 3.377% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
Path 3
Path Summary:Slack | -2.133 |
Data Arrival Time | 12.382 |
Data Required Time | 10.249 |
From | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_reg/spi_master_r_s3 |
To | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_0_s1 |
Launch Clk | HCLK[R] |
Latch Clk | HCLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | HCLK | |||
0.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
0.000 | 0.000 | tINS | RR | 3724 | HCLK_ibuf/O |
0.300 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_reg/spi_master_r_s3/CLK |
0.606 | 0.306 | tC2Q | RR | 88 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_reg/spi_master_r_s3/Q |
0.906 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_wr_num_0_s3/I0 |
1.327 | 0.421 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_wr_num_0_s3/F |
1.627 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_wr_num_0_s2/I2 |
1.996 | 0.369 | tINS | RR | 16 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_wr_num_0_s2/F |
2.296 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_wr_num_0_s1/I2 |
2.665 | 0.369 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_wr_num_0_s1/F |
2.965 | 0.300 | tNET | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n388_s0/I1 |
3.415 | 0.450 | tINS | RF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n388_s0/COUT |
3.415 | 0.000 | tNET | FF | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n389_s0/CIN |
3.455 | 0.040 | tINS | FR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n389_s0/COUT |
3.455 | 0.000 | tNET | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n390_s0/CIN |
3.495 | 0.040 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n390_s0/COUT |
3.495 | 0.000 | tNET | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n391_s0/CIN |
3.535 | 0.040 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n391_s0/COUT |
3.535 | 0.000 | tNET | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n392_s0/CIN |
3.575 | 0.040 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n392_s0/COUT |
3.575 | 0.000 | tNET | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n393_s0/CIN |
3.615 | 0.040 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n393_s0/COUT |
3.615 | 0.000 | tNET | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n394_s0/CIN |
3.655 | 0.040 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n394_s0/COUT |
3.655 | 0.000 | tNET | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n395_s0/CIN |
3.695 | 0.040 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n395_s0/COUT |
3.695 | 0.000 | tNET | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n396_s0/CIN |
3.735 | 0.040 | tINS | RR | 4 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n396_s0/COUT |
4.035 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n583_s13/I0 |
4.456 | 0.421 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n583_s13/F |
4.756 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n583_s11/I0 |
5.177 | 0.421 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n583_s11/F |
5.477 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n583_s8/I1 |
5.890 | 0.413 | tINS | RR | 5 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n583_s8/F |
6.190 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_3_s9/I0 |
6.611 | 0.421 | tINS | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_3_s9/F |
6.911 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_0_s16/I0 |
7.332 | 0.421 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_0_s16/F |
7.632 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_0_s8/I0 |
8.053 | 0.421 | tINS | RR | 3 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_0_s8/F |
8.353 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_0_s4/I3 |
8.563 | 0.210 | tINS | RR | 9 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_0_s4/F |
8.863 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_0_s2/I1 |
9.276 | 0.413 | tINS | RR | 68 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_0_s2/F |
9.576 | 0.300 | tNET | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n9_s0/I1 |
10.026 | 0.450 | tINS | RF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n9_s0/COUT |
10.026 | 0.000 | tNET | FF | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n10_s0/CIN |
10.066 | 0.040 | tINS | FR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n10_s0/COUT |
10.066 | 0.000 | tNET | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n11_s0/CIN |
10.106 | 0.040 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n11_s0/COUT |
10.106 | 0.000 | tNET | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n12_s0/CIN |
10.146 | 0.040 | tINS | RR | 11 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n12_s0/COUT |
10.446 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_8_s9/I1 |
10.859 | 0.413 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_8_s9/F |
11.159 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_8_s6/I3 |
11.369 | 0.210 | tINS | RR | 10 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_8_s6/F |
11.669 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n497_s2/I1 |
12.082 | 0.413 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n497_s2/F |
12.382 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_0_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | HCLK | |||
10.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
10.000 | 0.000 | tINS | RR | 3724 | HCLK_ibuf/O |
10.300 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_0_s1/CLK |
10.249 | -0.051 | tSu | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_0_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 20 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
Arrival Data Path Delay: | cell: 6.676, 55.255%; route: 5.100, 42.212%; tC2Q: 0.306, 2.533% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
Path 4
Path Summary:Slack | -2.128 |
Data Arrival Time | 12.179 |
Data Required Time | 10.051 |
From | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_reg/spi_master_r_s3 |
To | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_0_s1 |
Launch Clk | HCLK[R] |
Latch Clk | HCLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | HCLK | |||
0.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
0.000 | 0.000 | tINS | RR | 3724 | HCLK_ibuf/O |
0.300 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_reg/spi_master_r_s3/CLK |
0.606 | 0.306 | tC2Q | RR | 88 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_reg/spi_master_r_s3/Q |
0.906 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_wr_num_0_s3/I0 |
1.327 | 0.421 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_wr_num_0_s3/F |
1.627 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_wr_num_0_s2/I2 |
1.996 | 0.369 | tINS | RR | 16 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_wr_num_0_s2/F |
2.296 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_wr_num_0_s1/I2 |
2.665 | 0.369 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_wr_num_0_s1/F |
2.965 | 0.300 | tNET | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n388_s0/I1 |
3.415 | 0.450 | tINS | RF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n388_s0/COUT |
3.415 | 0.000 | tNET | FF | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n389_s0/CIN |
3.455 | 0.040 | tINS | FR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n389_s0/COUT |
3.455 | 0.000 | tNET | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n390_s0/CIN |
3.495 | 0.040 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n390_s0/COUT |
3.495 | 0.000 | tNET | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n391_s0/CIN |
3.535 | 0.040 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n391_s0/COUT |
3.535 | 0.000 | tNET | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n392_s0/CIN |
3.575 | 0.040 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n392_s0/COUT |
3.575 | 0.000 | tNET | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n393_s0/CIN |
3.615 | 0.040 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n393_s0/COUT |
3.615 | 0.000 | tNET | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n394_s0/CIN |
3.655 | 0.040 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n394_s0/COUT |
3.655 | 0.000 | tNET | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n395_s0/CIN |
3.695 | 0.040 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n395_s0/COUT |
3.695 | 0.000 | tNET | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n396_s0/CIN |
3.735 | 0.040 | tINS | RR | 4 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n396_s0/COUT |
4.035 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n583_s13/I0 |
4.456 | 0.421 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n583_s13/F |
4.756 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n583_s11/I0 |
5.177 | 0.421 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n583_s11/F |
5.477 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n583_s8/I1 |
5.890 | 0.413 | tINS | RR | 5 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n583_s8/F |
6.190 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_3_s9/I0 |
6.611 | 0.421 | tINS | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_3_s9/F |
6.911 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_0_s16/I0 |
7.332 | 0.421 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_0_s16/F |
7.632 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_0_s8/I0 |
8.053 | 0.421 | tINS | RR | 3 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_0_s8/F |
8.353 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_0_s4/I3 |
8.563 | 0.210 | tINS | RR | 9 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_0_s4/F |
8.863 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_0_s2/I1 |
9.276 | 0.413 | tINS | RR | 68 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_0_s2/F |
9.576 | 0.300 | tNET | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n9_s0/I1 |
10.026 | 0.450 | tINS | RF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n9_s0/COUT |
10.026 | 0.000 | tNET | FF | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n10_s0/CIN |
10.066 | 0.040 | tINS | FR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n10_s0/COUT |
10.066 | 0.000 | tNET | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n11_s0/CIN |
10.106 | 0.040 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n11_s0/COUT |
10.106 | 0.000 | tNET | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n12_s0/CIN |
10.146 | 0.040 | tINS | RR | 11 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n12_s0/COUT |
10.446 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_8_s9/I1 |
10.859 | 0.413 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_8_s9/F |
11.159 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_8_s6/I3 |
11.369 | 0.210 | tINS | RR | 10 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_8_s6/F |
11.669 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_8_s3/I3 |
11.879 | 0.210 | tINS | RR | 9 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_8_s3/F |
12.179 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_0_s1/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | HCLK | |||
10.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
10.000 | 0.000 | tINS | RR | 3724 | HCLK_ibuf/O |
10.300 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_0_s1/CLK |
10.051 | -0.249 | tSu | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_0_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 20 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
Arrival Data Path Delay: | cell: 6.473, 54.491%; route: 5.100, 42.933%; tC2Q: 0.306, 2.576% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
Path 5
Path Summary:Slack | -2.128 |
Data Arrival Time | 12.179 |
Data Required Time | 10.051 |
From | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_reg/spi_master_r_s3 |
To | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_1_s1 |
Launch Clk | HCLK[R] |
Latch Clk | HCLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | HCLK | |||
0.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
0.000 | 0.000 | tINS | RR | 3724 | HCLK_ibuf/O |
0.300 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_reg/spi_master_r_s3/CLK |
0.606 | 0.306 | tC2Q | RR | 88 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_reg/spi_master_r_s3/Q |
0.906 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_wr_num_0_s3/I0 |
1.327 | 0.421 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_wr_num_0_s3/F |
1.627 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_wr_num_0_s2/I2 |
1.996 | 0.369 | tINS | RR | 16 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_wr_num_0_s2/F |
2.296 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_wr_num_0_s1/I2 |
2.665 | 0.369 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_wr_num_0_s1/F |
2.965 | 0.300 | tNET | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n388_s0/I1 |
3.415 | 0.450 | tINS | RF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n388_s0/COUT |
3.415 | 0.000 | tNET | FF | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n389_s0/CIN |
3.455 | 0.040 | tINS | FR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n389_s0/COUT |
3.455 | 0.000 | tNET | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n390_s0/CIN |
3.495 | 0.040 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n390_s0/COUT |
3.495 | 0.000 | tNET | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n391_s0/CIN |
3.535 | 0.040 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n391_s0/COUT |
3.535 | 0.000 | tNET | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n392_s0/CIN |
3.575 | 0.040 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n392_s0/COUT |
3.575 | 0.000 | tNET | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n393_s0/CIN |
3.615 | 0.040 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n393_s0/COUT |
3.615 | 0.000 | tNET | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n394_s0/CIN |
3.655 | 0.040 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n394_s0/COUT |
3.655 | 0.000 | tNET | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n395_s0/CIN |
3.695 | 0.040 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n395_s0/COUT |
3.695 | 0.000 | tNET | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n396_s0/CIN |
3.735 | 0.040 | tINS | RR | 4 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n396_s0/COUT |
4.035 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n583_s13/I0 |
4.456 | 0.421 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n583_s13/F |
4.756 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n583_s11/I0 |
5.177 | 0.421 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n583_s11/F |
5.477 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n583_s8/I1 |
5.890 | 0.413 | tINS | RR | 5 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n583_s8/F |
6.190 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_3_s9/I0 |
6.611 | 0.421 | tINS | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_3_s9/F |
6.911 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_0_s16/I0 |
7.332 | 0.421 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_0_s16/F |
7.632 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_0_s8/I0 |
8.053 | 0.421 | tINS | RR | 3 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_0_s8/F |
8.353 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_0_s4/I3 |
8.563 | 0.210 | tINS | RR | 9 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_0_s4/F |
8.863 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_0_s2/I1 |
9.276 | 0.413 | tINS | RR | 68 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_0_s2/F |
9.576 | 0.300 | tNET | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n9_s0/I1 |
10.026 | 0.450 | tINS | RF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n9_s0/COUT |
10.026 | 0.000 | tNET | FF | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n10_s0/CIN |
10.066 | 0.040 | tINS | FR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n10_s0/COUT |
10.066 | 0.000 | tNET | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n11_s0/CIN |
10.106 | 0.040 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n11_s0/COUT |
10.106 | 0.000 | tNET | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n12_s0/CIN |
10.146 | 0.040 | tINS | RR | 11 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n12_s0/COUT |
10.446 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_8_s9/I1 |
10.859 | 0.413 | tINS | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_8_s9/F |
11.159 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_8_s6/I3 |
11.369 | 0.210 | tINS | RR | 10 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_8_s6/F |
11.669 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_8_s3/I3 |
11.879 | 0.210 | tINS | RR | 9 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_8_s3/F |
12.179 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_1_s1/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | HCLK | |||
10.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
10.000 | 0.000 | tINS | RR | 3724 | HCLK_ibuf/O |
10.300 | 0.300 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_1_s1/CLK |
10.051 | -0.249 | tSu | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_1_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 20 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |
Arrival Data Path Delay: | cell: 6.473, 54.491%; route: 5.100, 42.933%; tC2Q: 0.306, 2.576% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.300, 100.000% |