Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\ahb_def_slave.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\BusMatrix.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\can.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\can_top.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_adder.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_ahb.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_alu_dec.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_core.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_ctl.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_ctl_add3.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_ahb_dec.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_ahb_mux.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_bp.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_ctl.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_define.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_dw.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_mtx.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_mtx_dbg.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_mtx_sys.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_rom_tb.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_sys.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_tcm.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_undefs.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_decoder.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_defs.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dp.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_excpt.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_fetch.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_fns.vh
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_matrix_check_fns.vh
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_mem_ctl.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_multiplier.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_multiply_shift.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_mux4.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_nvic.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_nvic_ahb.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_nvic_ahb_os.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_nvic_defs.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_nvic_main.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_nvic_pri_lvl.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_nvic_pri_num.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_nvic_tree.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_nvic_undefs.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_reg_bank.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_shifter.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_undefs.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_ethmac_miim_wrapper.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_ethmac_rx_buffer_to_ahb.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_ethmac_rx_to_buffer.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_ethmac_rx_wrapper.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_ethmac_sdp_wrapper_32bit.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_ethmac_tx_wrapper.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_ethmac_wrapper.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_gpio.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_ahbif_ctrl.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_arbiter.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_async_fifo_clr.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_config.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_const.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_ctrl.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_eilmif_ctrl.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_fifo.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_gck.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_pad_lib.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_reg.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_regif.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_regif_ctrl.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_spiif.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_sync.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_sync_l2l.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_sync_p2p.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_to_iop.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_dualtimers.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_dualtimers_defs.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_dualtimers_frc.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_spi.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_timer.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_autocorrelation.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_balancefilter.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_collector.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_crngt_to_trng.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_dx_inv_chain.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_dx_trng_top.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_dxm_ff.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_dxm_interrupt_low.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_dxm_mux.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_dxm_mux_clk.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_dxm_sync.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_ehr.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_entropy_gen.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_gtech_models.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_lfsr_new.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_line.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_noise_gen.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_pmf_table.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_prng_top_wrap.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_reg_file.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_rng_engine.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_rng_misc.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_rng_top.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_rng_top_wrap_unconnected.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_rosc.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_rst_logic.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_sample_cntr.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_slave_bus_ifc.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_sync.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_tests_misc.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_top.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_uart.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_watchdog.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_watchdog_defs.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_watchdog_frc.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_iop_gpio.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\CortexM1Dbg.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\CortexM1DbgIntegration.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\CortexM1DbgIntegrationWrapper.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\dapahbap.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPAhbApAhbSync.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPAhbApDapSync.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPAhbApDefs.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPAhbApMst.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPAhbApSlv.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPAhbApSyn.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPDecMux.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPDpApbDefs.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPDpApbSync.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPDpEnSync.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPDpIMux.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPDpSync.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPJtagDpDefs.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPJtagDpProtocol.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPSwDpApbIf.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPSwDpDefs.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPSwDpProtocol.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPSwDpSync.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\dapswjdp.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPSwjDpDefs.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPSwjWatcher.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\ddr3_1_4code_hs.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\ddr3_to_ahb_top.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DDR3_TOP.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\dtcmdbg.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\eth_mac.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\eth_mac_top.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\Gowin_EMPU_M1_top.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\GowinAhbExt.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\GowinCM1AhbExt.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\GowinCM1AhbExtWrapper.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\gw_ahb_psram.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\gw_apb_i2c.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\gw_apb_int_wrapper.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\gw_apb_sd.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\gw_gpio.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\InputStage.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\itcmdbg.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\MatrixDecodeS0.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\MatrixDecodeS1.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\MatrixDecodeS2.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\OutputArb1.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\OutputArb2.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\OutputArb3.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\OutputStage1.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\OutputStage2.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\OutputStage3.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\p_sse050_interconnect_f0_ahb_to_apb.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\p_sse050_interconnect_f0_apb_slave_mux.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\psram_code.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\PSRAM_TOP.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\rng_addr_params.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\rng_cc_params.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\rng_params.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\Rtc.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\RtcApbif.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\RtcControl.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\RtcCounter.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\RtcInterrupt.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\RtcParams.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\RtcRevAnd.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\RtcSynctoPCLK.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\RtcUpdate.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\sse050_int_apb_decoder.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\sse050_integration_peripherals.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\sync_p2p.v
F:\EMB_pub\embedded\arm\cortex_m1\tool\make_hex\rls\make_hex\ref_design\FPGA_RefDesign\gowin_empu_m1\src\gowin_empu_m1\temp\gw_empu_m1\cm1_option_defs.v
F:\EMB_pub\embedded\arm\cortex_m1\tool\make_hex\rls\make_hex\ref_design\FPGA_RefDesign\gowin_empu_m1\src\gowin_empu_m1\temp\gw_empu_m1\ahb_option_defs.v
F:\EMB_pub\embedded\arm\cortex_m1\tool\make_hex\rls\make_hex\ref_design\FPGA_RefDesign\gowin_empu_m1\src\gowin_empu_m1\temp\gw_empu_m1\parameter.vh
F:\EMB_pub\embedded\arm\cortex_m1\tool\make_hex\rls\make_hex\ref_design\FPGA_RefDesign\gowin_empu_m1\src\gowin_empu_m1\temp\gw_empu_m1\triple_speed_mac_param.v
F:\EMB_pub\embedded\arm\cortex_m1\tool\make_hex\rls\make_hex\ref_design\FPGA_RefDesign\gowin_empu_m1\src\gowin_empu_m1\temp\gw_empu_m1\triple_speed_mac_define.v
F:\EMB_pub\embedded\arm\cortex_m1\tool\make_hex\rls\make_hex\ref_design\FPGA_RefDesign\gowin_empu_m1\src\gowin_empu_m1\temp\gw_empu_m1\DDR3_define.v
GowinSynthesis Constraints File ---
Tool Version V1.9.11.02 (64-bit)
Part Number GW5A-LV25UG324C2/I1
Device GW5A-25
Device Version A
Created Time Thu May 22 14:54:25 2025
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module Gowin_EMPU_M1_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 5s, Elapsed time = 0h 0m 5s, Peak memory usage = 171.004MB
Running netlist conversion:
    CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.12s, Peak memory usage = 171.004MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.968s, Elapsed time = 0h 0m 0.976s, Peak memory usage = 171.004MB
    Optimizing Phase 1: CPU time = 0h 0m 0.312s, Elapsed time = 0h 0m 0.313s, Peak memory usage = 171.004MB
    Optimizing Phase 2: CPU time = 0h 0m 0.953s, Elapsed time = 0h 0m 0.942s, Peak memory usage = 171.004MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.515s, Elapsed time = 0h 0m 0.523s, Peak memory usage = 171.004MB
    Inferring Phase 1: CPU time = 0h 0m 0.437s, Elapsed time = 0h 0m 0.429s, Peak memory usage = 171.004MB
    Inferring Phase 2: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.068s, Peak memory usage = 171.004MB
    Inferring Phase 3: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.028s, Peak memory usage = 171.004MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 171.004MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.343s, Elapsed time = 0h 0m 0.351s, Peak memory usage = 171.004MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.406s, Elapsed time = 0h 0m 0.393s, Peak memory usage = 171.004MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 28s, Elapsed time = 0h 0m 28s, Peak memory usage = 171.004MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.859s, Elapsed time = 0h 0m 0.931s, Peak memory usage = 171.004MB
Generate output files:
    CPU time = 0h 0m 0.75s, Elapsed time = 0h 0m 0.743s, Peak memory usage = 180.555MB
Total Time and Memory Usage CPU time = 0h 0m 39s, Elapsed time = 0h 0m 39s, Peak memory usage = 180.555MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 25
I/O Buf 25
    IBUF 5
    OBUF 3
    IOBUF 17
Register 3142
    DFFSE 1
    DFFRE 548
    DFFPE 109
    DFFCE 2484
LUT 6296
    LUT2 508
    LUT3 2129
    LUT4 3659
ALU 155
    ALU 155
INV 20
    INV 20
DSP
    MULT27X36 2
BSRAM 32
    DPB 32

Resource Utilization Summary

Resource Usage Utilization
Logic 6471(6316 LUT, 155 ALU) / 23040 29%
Register 3142 / 23685 14%
  --Register as Latch 0 / 23685 0%
  --Register as FF 3142 / 23685 14%
BSRAM 32 / 56 58%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 HCLK Base 10.000 100.000 0.000 5.000 HCLK_ibuf/I
2 JTAG_9 Base 10.000 100.000 0.000 5.000 JTAG_9_ibuf/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 HCLK 100.000(MHz) 95.978(MHz) 15 TOP
2 JTAG_9 100.000(MHz) 157.431(MHz) 9 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack -0.419
Data Arrival Time 10.668
Data Required Time 10.249
From M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_RAMREG_7_G[2]_s1
To M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_mem_ctl/biu_commit_reg_s0
Launch Clk HCLK[R]
Latch Clk HCLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 HCLK
0.000 0.000 tCL RR 1 HCLK_ibuf/I
0.000 0.000 tINS RR 3018 HCLK_ibuf/O
0.300 0.300 tNET RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_RAMREG_7_G[2]_s1/CLK
0.606 0.306 tC2Q RR 2 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_RAMREG_7_G[2]_s1/Q
0.906 0.300 tNET RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_RAMOUT_30_G[0]_s15/I0
1.327 0.421 tINS RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_RAMOUT_30_G[0]_s15/F
1.627 0.300 tNET RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_RAMOUT_30_G[0]_s7/I1
1.736 0.109 tINS RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_RAMOUT_30_G[0]_s7/O
2.036 0.300 tNET RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_RAMOUT_30_G[0]_s3/I1
2.105 0.069 tINS RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_RAMOUT_30_G[0]_s3/O
2.405 0.300 tNET RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_RAMOUT_30_G[0]_s1/I1
2.474 0.069 tINS RR 7 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_RAMOUT_30_G[0]_s1/O
2.774 0.300 tNET RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/au_b_int_2_s2/I0
3.195 0.421 tINS RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/au_b_int_2_s2/F
3.495 0.300 tNET RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/au_b_int_2_s1/I1
3.908 0.413 tINS RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/au_b_int_2_s1/F
4.208 0.300 tNET RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/I1
4.621 0.413 tINS RR 2 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/F
4.921 0.300 tNET RR 2 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/I1
5.371 0.450 tINS RF 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/COUT
5.371 0.000 tNET FF 2 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/CIN
5.411 0.040 tINS FR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/COUT
5.411 0.000 tNET RR 2 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/CIN
5.451 0.040 tINS RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/COUT
5.451 0.000 tNET RR 2 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/CIN
5.491 0.040 tINS RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/COUT
5.491 0.000 tNET RR 2 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/CIN
5.531 0.040 tINS RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/COUT
5.531 0.000 tNET RR 2 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/CIN
5.571 0.040 tINS RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/COUT
5.571 0.000 tNET RR 2 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/CIN
5.611 0.040 tINS RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/COUT
5.611 0.000 tNET RR 2 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/CIN
5.651 0.040 tINS RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/COUT
5.651 0.000 tNET RR 2 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/CIN
5.691 0.040 tINS RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/COUT
5.691 0.000 tNET RR 2 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/CIN
5.731 0.040 tINS RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/COUT
5.731 0.000 tNET RR 2 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/CIN
5.771 0.040 tINS RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/COUT
5.771 0.000 tNET RR 2 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/CIN
5.811 0.040 tINS RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/COUT
5.811 0.000 tNET RR 2 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/CIN
5.851 0.040 tINS RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/COUT
5.851 0.000 tNET RR 2 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/CIN
5.891 0.040 tINS RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/COUT
5.891 0.000 tNET RR 2 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/CIN
5.931 0.040 tINS RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/COUT
5.931 0.000 tNET RR 2 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/CIN
5.971 0.040 tINS RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/COUT
5.971 0.000 tNET RR 2 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/CIN
6.011 0.040 tINS RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/COUT
6.011 0.000 tNET RR 2 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_19_s/CIN
6.206 0.195 tINS RR 4 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_19_s/SUM
6.506 0.300 tNET RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s6/I0
6.927 0.421 tINS RR 2 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s6/F
7.227 0.300 tNET RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_itcm_sel_s5/I1
7.640 0.413 tINS RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_itcm_sel_s5/F
7.940 0.300 tNET RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_itcm_sel_s4/I2
8.309 0.369 tINS RR 2 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_itcm_sel_s4/F
8.609 0.300 tNET RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/biu_commit_Z_s7/I0
9.030 0.421 tINS RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/biu_commit_Z_s7/F
9.330 0.300 tNET RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/biu_commit_Z_s2/I2
9.699 0.369 tINS RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/biu_commit_Z_s2/F
9.999 0.300 tNET RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/biu_commit_Z_s/I2
10.368 0.369 tINS RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_alu_dec/biu_commit_Z_s/F
10.668 0.300 tNET RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_mem_ctl/biu_commit_reg_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 HCLK
10.000 0.000 tCL RR 1 HCLK_ibuf/I
10.000 0.000 tINS RR 3018 HCLK_ibuf/O
10.300 0.300 tNET RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_mem_ctl/biu_commit_reg_s0/CLK
10.249 -0.051 tSu 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_dp/u_mem_ctl/biu_commit_reg_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 15
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%
Arrival Data Path Delay: cell: 5.562, 53.646%; route: 4.500, 43.403%; tC2Q: 0.306, 2.951%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%

Path 2

Path Summary:
Slack 0.084
Data Arrival Time 10.130
Data Required Time 10.214
From M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwDpProtocol/ApBankSel_1_s0
To M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_1_s0
Launch Clk JTAG_9[R]
Latch Clk HCLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 JTAG_9
0.000 0.000 tCL RR 1 JTAG_9_ibuf/I
0.587 0.587 tINS RR 190 JTAG_9_ibuf/O
0.887 0.300 tNET RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwDpProtocol/ApBankSel_1_s0/CLK
1.193 0.306 tC2Q RR 3 M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwDpProtocol/ApBankSel_1_s0/Q
1.493 0.300 tNET RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/CswSwWrEn_s3/I0
1.914 0.421 tINS RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/CswSwWrEn_s3/F
2.214 0.300 tNET RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/CswSwWrEn_s2/I0
2.635 0.421 tINS RR 7 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/CswSwWrEn_s2/F
2.935 0.300 tNET RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s28/I0
3.356 0.421 tINS RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s28/F
3.656 0.300 tNET RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s25/I0
4.077 0.421 tINS RR 2 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s25/F
4.377 0.300 tNET RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_0_s25/I0
4.798 0.421 tINS RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_0_s25/F
5.098 0.300 tNET RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_0_s24/I2
5.467 0.369 tINS RR 5 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_0_s24/F
5.767 0.300 tNET RR 2 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n363_s0/I1
6.217 0.450 tINS RF 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n363_s0/COUT
6.217 0.000 tNET FF 2 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n364_s0/CIN
6.257 0.040 tINS FR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n364_s0/COUT
6.257 0.000 tNET RR 2 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n365_s0/CIN
6.297 0.040 tINS RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n365_s0/COUT
6.297 0.000 tNET RR 2 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n366_s0/CIN
6.337 0.040 tINS RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n366_s0/COUT
6.637 0.300 tNET RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s2/I2
7.006 0.369 tINS RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s2/F
7.306 0.300 tNET RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s1/I1
7.719 0.413 tINS RR 21 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s1/F
8.019 0.300 tNET RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_2_s1/I0
8.440 0.421 tINS RR 19 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_2_s1/F
8.740 0.300 tNET RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_1_s2/I0
9.161 0.421 tINS RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_1_s2/F
9.461 0.300 tNET RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_1_s0/I2
9.830 0.369 tINS RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_1_s0/F
10.130 0.300 tNET RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_1_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 HCLK
10.000 0.000 tCL RR 1 HCLK_ibuf/I
10.000 0.000 tINS RR 3018 HCLK_ibuf/O
10.300 0.300 tNET RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_1_s0/CLK
10.265 -0.035 tUnc M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_1_s0
10.214 -0.051 tSu 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_1_s0
Path Statistics:
Clock Skew: -0.587
Setup Relationship: 10.000
Logic Level: 14
Arrival Clock Path Delay: cell: 0.587, 66.176%; route: 0.300, 33.824%
Arrival Data Path Delay: cell: 5.037, 54.495%; route: 3.900, 42.194%; tC2Q: 0.306, 3.311%
Required Clock Path Delay: cell: 0.587, 66.176%; route: 0.300, 33.824%

Path 3

Path Summary:
Slack 0.084
Data Arrival Time 10.130
Data Required Time 10.214
From M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwDpProtocol/ApBankSel_1_s0
To M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_4_s0
Launch Clk JTAG_9[R]
Latch Clk HCLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 JTAG_9
0.000 0.000 tCL RR 1 JTAG_9_ibuf/I
0.587 0.587 tINS RR 190 JTAG_9_ibuf/O
0.887 0.300 tNET RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwDpProtocol/ApBankSel_1_s0/CLK
1.193 0.306 tC2Q RR 3 M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwDpProtocol/ApBankSel_1_s0/Q
1.493 0.300 tNET RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/CswSwWrEn_s3/I0
1.914 0.421 tINS RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/CswSwWrEn_s3/F
2.214 0.300 tNET RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/CswSwWrEn_s2/I0
2.635 0.421 tINS RR 7 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/CswSwWrEn_s2/F
2.935 0.300 tNET RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s28/I0
3.356 0.421 tINS RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s28/F
3.656 0.300 tNET RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s25/I0
4.077 0.421 tINS RR 2 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s25/F
4.377 0.300 tNET RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_0_s25/I0
4.798 0.421 tINS RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_0_s25/F
5.098 0.300 tNET RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_0_s24/I2
5.467 0.369 tINS RR 5 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_0_s24/F
5.767 0.300 tNET RR 2 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n363_s0/I1
6.217 0.450 tINS RF 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n363_s0/COUT
6.217 0.000 tNET FF 2 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n364_s0/CIN
6.257 0.040 tINS FR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n364_s0/COUT
6.257 0.000 tNET RR 2 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n365_s0/CIN
6.297 0.040 tINS RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n365_s0/COUT
6.297 0.000 tNET RR 2 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n366_s0/CIN
6.337 0.040 tINS RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n366_s0/COUT
6.637 0.300 tNET RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s2/I2
7.006 0.369 tINS RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s2/F
7.306 0.300 tNET RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s1/I1
7.719 0.413 tINS RR 21 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s1/F
8.019 0.300 tNET RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_2_s1/I0
8.440 0.421 tINS RR 19 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_2_s1/F
8.740 0.300 tNET RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_4_s1/I0
9.161 0.421 tINS RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_4_s1/F
9.461 0.300 tNET RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_4_s0/I2
9.830 0.369 tINS RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_4_s0/F
10.130 0.300 tNET RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_4_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 HCLK
10.000 0.000 tCL RR 1 HCLK_ibuf/I
10.000 0.000 tINS RR 3018 HCLK_ibuf/O
10.300 0.300 tNET RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_4_s0/CLK
10.265 -0.035 tUnc M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_4_s0
10.214 -0.051 tSu 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_4_s0
Path Statistics:
Clock Skew: -0.587
Setup Relationship: 10.000
Logic Level: 14
Arrival Clock Path Delay: cell: 0.587, 66.176%; route: 0.300, 33.824%
Arrival Data Path Delay: cell: 5.037, 54.495%; route: 3.900, 42.194%; tC2Q: 0.306, 3.311%
Required Clock Path Delay: cell: 0.587, 66.176%; route: 0.300, 33.824%

Path 4

Path Summary:
Slack 0.084
Data Arrival Time 10.130
Data Required Time 10.214
From M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwDpProtocol/ApBankSel_1_s0
To M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_5_s0
Launch Clk JTAG_9[R]
Latch Clk HCLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 JTAG_9
0.000 0.000 tCL RR 1 JTAG_9_ibuf/I
0.587 0.587 tINS RR 190 JTAG_9_ibuf/O
0.887 0.300 tNET RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwDpProtocol/ApBankSel_1_s0/CLK
1.193 0.306 tC2Q RR 3 M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwDpProtocol/ApBankSel_1_s0/Q
1.493 0.300 tNET RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/CswSwWrEn_s3/I0
1.914 0.421 tINS RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/CswSwWrEn_s3/F
2.214 0.300 tNET RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/CswSwWrEn_s2/I0
2.635 0.421 tINS RR 7 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/CswSwWrEn_s2/F
2.935 0.300 tNET RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s28/I0
3.356 0.421 tINS RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s28/F
3.656 0.300 tNET RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s25/I0
4.077 0.421 tINS RR 2 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s25/F
4.377 0.300 tNET RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_0_s25/I0
4.798 0.421 tINS RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_0_s25/F
5.098 0.300 tNET RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_0_s24/I2
5.467 0.369 tINS RR 5 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_0_s24/F
5.767 0.300 tNET RR 2 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n363_s0/I1
6.217 0.450 tINS RF 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n363_s0/COUT
6.217 0.000 tNET FF 2 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n364_s0/CIN
6.257 0.040 tINS FR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n364_s0/COUT
6.257 0.000 tNET RR 2 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n365_s0/CIN
6.297 0.040 tINS RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n365_s0/COUT
6.297 0.000 tNET RR 2 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n366_s0/CIN
6.337 0.040 tINS RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n366_s0/COUT
6.637 0.300 tNET RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s2/I2
7.006 0.369 tINS RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s2/F
7.306 0.300 tNET RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s1/I1
7.719 0.413 tINS RR 21 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s1/F
8.019 0.300 tNET RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_2_s1/I0
8.440 0.421 tINS RR 19 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_2_s1/F
8.740 0.300 tNET RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_5_s1/I0
9.161 0.421 tINS RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_5_s1/F
9.461 0.300 tNET RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_5_s0/I2
9.830 0.369 tINS RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_5_s0/F
10.130 0.300 tNET RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_5_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 HCLK
10.000 0.000 tCL RR 1 HCLK_ibuf/I
10.000 0.000 tINS RR 3018 HCLK_ibuf/O
10.300 0.300 tNET RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_5_s0/CLK
10.265 -0.035 tUnc M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_5_s0
10.214 -0.051 tSu 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_5_s0
Path Statistics:
Clock Skew: -0.587
Setup Relationship: 10.000
Logic Level: 14
Arrival Clock Path Delay: cell: 0.587, 66.176%; route: 0.300, 33.824%
Arrival Data Path Delay: cell: 5.037, 54.495%; route: 3.900, 42.194%; tC2Q: 0.306, 3.311%
Required Clock Path Delay: cell: 0.587, 66.176%; route: 0.300, 33.824%

Path 5

Path Summary:
Slack 0.084
Data Arrival Time 10.130
Data Required Time 10.214
From M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwDpProtocol/ApBankSel_1_s0
To M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_6_s0
Launch Clk JTAG_9[R]
Latch Clk HCLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 JTAG_9
0.000 0.000 tCL RR 1 JTAG_9_ibuf/I
0.587 0.587 tINS RR 190 JTAG_9_ibuf/O
0.887 0.300 tNET RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwDpProtocol/ApBankSel_1_s0/CLK
1.193 0.306 tC2Q RR 3 M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwDpProtocol/ApBankSel_1_s0/Q
1.493 0.300 tNET RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/CswSwWrEn_s3/I0
1.914 0.421 tINS RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/CswSwWrEn_s3/F
2.214 0.300 tNET RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/CswSwWrEn_s2/I0
2.635 0.421 tINS RR 7 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/CswSwWrEn_s2/F
2.935 0.300 tNET RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s28/I0
3.356 0.421 tINS RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s28/F
3.656 0.300 tNET RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s25/I0
4.077 0.421 tINS RR 2 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s25/F
4.377 0.300 tNET RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_0_s25/I0
4.798 0.421 tINS RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_0_s25/F
5.098 0.300 tNET RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_0_s24/I2
5.467 0.369 tINS RR 5 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_0_s24/F
5.767 0.300 tNET RR 2 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n363_s0/I1
6.217 0.450 tINS RF 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n363_s0/COUT
6.217 0.000 tNET FF 2 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n364_s0/CIN
6.257 0.040 tINS FR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n364_s0/COUT
6.257 0.000 tNET RR 2 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n365_s0/CIN
6.297 0.040 tINS RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n365_s0/COUT
6.297 0.000 tNET RR 2 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n366_s0/CIN
6.337 0.040 tINS RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n366_s0/COUT
6.637 0.300 tNET RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s2/I2
7.006 0.369 tINS RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s2/F
7.306 0.300 tNET RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s1/I1
7.719 0.413 tINS RR 21 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s1/F
8.019 0.300 tNET RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_2_s1/I0
8.440 0.421 tINS RR 19 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_2_s1/F
8.740 0.300 tNET RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_6_s1/I0
9.161 0.421 tINS RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_6_s1/F
9.461 0.300 tNET RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_6_s0/I2
9.830 0.369 tINS RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_6_s0/F
10.130 0.300 tNET RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_6_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 HCLK
10.000 0.000 tCL RR 1 HCLK_ibuf/I
10.000 0.000 tINS RR 3018 HCLK_ibuf/O
10.300 0.300 tNET RR 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_6_s0/CLK
10.265 -0.035 tUnc M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_6_s0
10.214 -0.051 tSu 1 M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_6_s0
Path Statistics:
Clock Skew: -0.587
Setup Relationship: 10.000
Logic Level: 14
Arrival Clock Path Delay: cell: 0.587, 66.176%; route: 0.300, 33.824%
Arrival Data Path Delay: cell: 5.037, 54.495%; route: 3.900, 42.194%; tC2Q: 0.306, 3.311%
Required Clock Path Delay: cell: 0.587, 66.176%; route: 0.300, 33.824%