Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\ahb_def_slave.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\BusMatrix.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\can.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\can_top.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_adder.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_ahb.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_alu_dec.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_core.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_ctl.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_ctl_add3.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_decoder.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_defs.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_dp.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_excpt.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_fetch.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_fns.vh D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_mem_ctl.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_multiplier.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_multiply_shift.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_mux4.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_nvic.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_nvic_ahb.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_nvic_ahb_os.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_nvic_defs.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_nvic_main.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_nvic_pri_lvl.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_nvic_pri_num.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_nvic_tree.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_nvic_undefs.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_reg_bank.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_shifter.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_undef_check.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_undefs.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_ethmac_miim_wrapper.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_ethmac_rx_buffer_to_ahb.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_ethmac_rx_to_buffer.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_ethmac_rx_wrapper.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_ethmac_sdp_wrapper_32bit.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_ethmac_tx_wrapper.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_ethmac_wrapper.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_gpio.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_ahbif_ctrl.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_arbiter.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_async_fifo_clr.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_config.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_const.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_ctrl.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_eilmif_ctrl.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_fifo.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_gck.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_pad_lib.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_reg.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_regif.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_regif_ctrl.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_spiif.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_sync.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_sync_l2l.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_sync_p2p.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_to_iop.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_dualtimers.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_dualtimers_defs.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_dualtimers_frc.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_spi.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_timer.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_autocorrelation.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_balancefilter.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_collector.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_crngt_to_trng.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_dx_inv_chain.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_dx_trng_top.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_dxm_ff.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_dxm_interrupt_low.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_dxm_mux.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_dxm_mux_clk.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_dxm_sync.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_ehr.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_entropy_gen.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_gtech_models.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_lfsr_new.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_line.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_noise_gen.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_pmf_table.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_prng_top_wrap.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_reg_file.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_rng_engine.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_rng_misc.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_rng_top.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_rng_top_wrap_unconnected.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_rosc.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_rst_logic.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_sample_cntr.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_slave_bus_ifc.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_sync.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_tests_misc.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_top.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_uart.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_watchdog.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_watchdog_defs.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_watchdog_frc.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_iop_gpio.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\CortexM1.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\CortexM1Integration.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\CortexM1IntegrationWrapper.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\ddr3_1_4code_hs.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\ddr3_to_ahb_top.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\DDR3_TOP.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\dtcm.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\eth_mac.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\eth_mac_top.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\Gowin_EMPU_M1_top.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\GowinAhbExt.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\GowinCM1AhbExt.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\GowinCM1AhbExtWrapper.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\gw_ahb_psram.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\gw_apb_i2c.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\gw_apb_int_wrapper.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\gw_apb_sd.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\gw_gpio.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\InputStage.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\itcm.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\MatrixDecodeS0.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\MatrixDecodeS1.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\MatrixDecodeS2.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\OutputArb1.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\OutputArb2.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\OutputArb3.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\OutputStage1.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\OutputStage2.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\OutputStage3.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\p_sse050_interconnect_f0_ahb_to_apb.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\p_sse050_interconnect_f0_apb_slave_mux.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\psram_code.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\PSRAM_TOP.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\rng_addr_params.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\rng_cc_params.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\rng_params.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\Rtc.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\RtcApbif.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\RtcControl.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\RtcCounter.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\RtcInterrupt.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\RtcParams.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\RtcRevAnd.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\RtcSynctoPCLK.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\RtcUpdate.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\sse050_int_apb_decoder.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\sse050_integration_peripherals.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\sync_p2p.v F:\EMB_pub\embedded\arm\cortex_m1\ref_design\2.3\FPGA_RefDesign\DK_START_GW1N9_V2.1\cm1_demo\src\gowin_empu_m1\temp\gw_empu_m1\cm1_option_defs.v F:\EMB_pub\embedded\arm\cortex_m1\ref_design\2.3\FPGA_RefDesign\DK_START_GW1N9_V2.1\cm1_demo\src\gowin_empu_m1\temp\gw_empu_m1\ahb_option_defs.v F:\EMB_pub\embedded\arm\cortex_m1\ref_design\2.3\FPGA_RefDesign\DK_START_GW1N9_V2.1\cm1_demo\src\gowin_empu_m1\temp\gw_empu_m1\parameter.vh F:\EMB_pub\embedded\arm\cortex_m1\ref_design\2.3\FPGA_RefDesign\DK_START_GW1N9_V2.1\cm1_demo\src\gowin_empu_m1\temp\gw_empu_m1\triple_speed_mac_param.v F:\EMB_pub\embedded\arm\cortex_m1\ref_design\2.3\FPGA_RefDesign\DK_START_GW1N9_V2.1\cm1_demo\src\gowin_empu_m1\temp\gw_empu_m1\triple_speed_mac_define.v F:\EMB_pub\embedded\arm\cortex_m1\ref_design\2.3\FPGA_RefDesign\DK_START_GW1N9_V2.1\cm1_demo\src\gowin_empu_m1\temp\gw_empu_m1\DDR3_define.v |
GowinSynthesis Constraints File | --- |
Tool Version | V1.9.11.02 (64-bit) |
Part Number | GW1N-LV9LQ144C6/I5 |
Device | GW1N-9 |
Device Version | C |
Created Time | Thu May 22 17:24:38 2025 |
Legal Announcement | Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | Gowin_EMPU_M1_Top |
Synthesis Process | Running parser: CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s, Peak memory usage = 135.375MB Running netlist conversion: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.072s, Peak memory usage = 135.375MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.531s, Elapsed time = 0h 0m 0.535s, Peak memory usage = 135.375MB Optimizing Phase 1: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.14s, Peak memory usage = 135.375MB Optimizing Phase 2: CPU time = 0h 0m 0.437s, Elapsed time = 0h 0m 0.438s, Peak memory usage = 135.375MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.281s, Elapsed time = 0h 0m 0.275s, Peak memory usage = 135.375MB Inferring Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.033s, Peak memory usage = 135.375MB Inferring Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.032s, Peak memory usage = 135.375MB Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 135.375MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.484s, Elapsed time = 0h 0m 0.503s, Peak memory usage = 135.375MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.122s, Peak memory usage = 135.375MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.187s, Elapsed time = 0h 0m 0.185s, Peak memory usage = 135.375MB Tech-Mapping Phase 3: CPU time = 0h 0m 17s, Elapsed time = 0h 0m 17s, Peak memory usage = 137.695MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.421s, Elapsed time = 0h 0m 0.494s, Peak memory usage = 137.695MB Generate output files: CPU time = 0h 0m 0.328s, Elapsed time = 0h 0m 0.372s, Peak memory usage = 137.695MB |
Total Time and Memory Usage | CPU time = 0h 0m 24s, Elapsed time = 0h 0m 24s, Peak memory usage = 137.695MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 21 |
I/O Buf | 21 |
    IBUF | 3 |
    OBUF | 2 |
    IOBUF | 16 |
Register | 1462 |
    DFF | 10 |
    DFFSE | 1 |
    DFFR | 3 |
    DFFRE | 1 |
    DFFP | 22 |
    DFFPE | 70 |
    DFFC | 308 |
    DFFCE | 1047 |
LUT | 3663 |
    LUT2 | 392 |
    LUT3 | 1031 |
    LUT4 | 2240 |
ALU | 43 |
    ALU | 43 |
SSRAM | 20 |
    RAM16S4 | 4 |
    RAM16SDP4 | 16 |
INV | 19 |
    INV | 19 |
DSP | |
    MULT36X36 | 1 |
BSRAM | 24 |
    SP | 24 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 3845(3682 LUT, 43 ALU, 20 RAM16) / 8640 | 45% |
Register | 1462 / 6843 | 22% |
  --Register as Latch | 0 / 6843 | 0% |
  --Register as FF | 1462 / 6843 | 22% |
BSRAM | 24 / 26 | 93% |
Timing
Clock Summary:
NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|---|
1 | HCLK | Base | 20.000 | 50.000 | 0.000 | 10.000 | HCLK_ibuf/I |
Max Frequency Summary:
NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | HCLK | 50.000(MHz) | 42.222(MHz) | 15 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | -3.684 |
Data Arrival Time | 24.010 |
Data Required Time | 20.326 |
From | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_3_s0 |
To | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/biu_commit_reg_s0 |
Launch Clk | HCLK[R] |
Latch Clk | HCLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | HCLK | |||
0.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
0.000 | 0.000 | tINS | RR | 1507 | HCLK_ibuf/O |
0.726 | 0.726 | tNET | RR | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_3_s0/CLK |
1.184 | 0.458 | tC2Q | RF | 8 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_3_s0/Q |
2.144 | 0.960 | tNET | FF | 4 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/RAD[3] |
2.404 | 0.259 | tINS | FF | 7 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/DO[2] |
3.364 | 0.960 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/I0 |
4.396 | 1.032 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/F |
5.356 | 0.960 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/I1 |
6.455 | 1.099 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/F |
7.415 | 0.960 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/I1 |
8.514 | 1.099 | tINS | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/F |
9.474 | 0.960 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/I1 |
10.519 | 1.045 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/COUT |
10.519 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/CIN |
10.576 | 0.057 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/COUT |
10.576 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/CIN |
10.633 | 0.057 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/COUT |
10.633 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/CIN |
10.690 | 0.057 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/COUT |
10.690 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/CIN |
10.747 | 0.057 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/COUT |
10.747 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/CIN |
10.804 | 0.057 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/COUT |
10.804 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/CIN |
10.861 | 0.057 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/COUT |
10.861 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/CIN |
10.918 | 0.057 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/COUT |
10.918 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/CIN |
10.975 | 0.057 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/COUT |
10.975 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/CIN |
11.032 | 0.057 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/COUT |
11.032 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/CIN |
11.089 | 0.057 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/COUT |
11.089 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/CIN |
11.146 | 0.057 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/COUT |
11.146 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/CIN |
11.203 | 0.057 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/COUT |
11.203 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/CIN |
11.260 | 0.057 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/COUT |
11.260 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/CIN |
11.317 | 0.057 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/COUT |
11.317 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/CIN |
11.374 | 0.057 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/COUT |
11.374 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/CIN |
11.431 | 0.057 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/COUT |
11.431 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_19_s/CIN |
11.488 | 0.057 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_19_s/COUT |
11.488 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_20_s/CIN |
11.545 | 0.057 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_20_s/COUT |
11.545 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_21_s/CIN |
11.602 | 0.057 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_21_s/COUT |
11.602 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_22_s/CIN |
11.659 | 0.057 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_22_s/COUT |
11.659 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_23_s/CIN |
11.716 | 0.057 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_23_s/COUT |
11.716 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_24_s/CIN |
11.773 | 0.057 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_24_s/COUT |
11.773 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_25_s/CIN |
11.830 | 0.057 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_25_s/COUT |
11.830 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_26_s/CIN |
12.393 | 0.563 | tINS | FF | 4 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_26_s/SUM |
13.353 | 0.960 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s5/I1 |
14.452 | 1.099 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s5/F |
15.412 | 0.960 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s1/I3 |
16.038 | 0.626 | tINS | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s1/F |
16.998 | 0.960 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_itcm_sel_s4/I2 |
17.820 | 0.822 | tINS | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_itcm_sel_s4/F |
18.780 | 0.960 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_itcm_sel_s2/I3 |
19.406 | 0.626 | tINS | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_itcm_sel_s2/F |
20.366 | 0.960 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/biu_commit_Z_s3/I1 |
21.465 | 1.099 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/biu_commit_Z_s3/F |
22.424 | 0.960 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/biu_commit_Z_s/I3 |
23.050 | 0.626 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/biu_commit_Z_s/F |
24.010 | 0.960 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/biu_commit_reg_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
20.000 | 0.000 | HCLK | |||
20.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
20.000 | 0.000 | tINS | RR | 1507 | HCLK_ibuf/O |
20.726 | 0.726 | tNET | RR | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/biu_commit_reg_s0/CLK |
20.326 | -0.400 | tSu | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/biu_commit_reg_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 20.000 |
Logic Level: | 15 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Arrival Data Path Delay: | cell: 11.306, 48.557%; route: 11.520, 49.475%; tC2Q: 0.458, 1.968% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Path 2
Path Summary:Slack | -1.625 |
Data Arrival Time | 21.951 |
Data Required Time | 20.326 |
From | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_3_s0 |
To | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/dtcm_sel_s0 |
Launch Clk | HCLK[R] |
Latch Clk | HCLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | HCLK | |||
0.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
0.000 | 0.000 | tINS | RR | 1507 | HCLK_ibuf/O |
0.726 | 0.726 | tNET | RR | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_3_s0/CLK |
1.184 | 0.458 | tC2Q | RF | 8 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_3_s0/Q |
2.144 | 0.960 | tNET | FF | 4 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/RAD[3] |
2.404 | 0.259 | tINS | FF | 7 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/DO[2] |
3.364 | 0.960 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/I0 |
4.396 | 1.032 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/F |
5.356 | 0.960 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/I1 |
6.455 | 1.099 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/F |
7.415 | 0.960 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/I1 |
8.514 | 1.099 | tINS | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/F |
9.474 | 0.960 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/I1 |
10.519 | 1.045 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/COUT |
10.519 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/CIN |
10.576 | 0.057 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/COUT |
10.576 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/CIN |
10.633 | 0.057 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/COUT |
10.633 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/CIN |
10.690 | 0.057 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/COUT |
10.690 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/CIN |
10.747 | 0.057 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/COUT |
10.747 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/CIN |
10.804 | 0.057 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/COUT |
10.804 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/CIN |
10.861 | 0.057 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/COUT |
10.861 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/CIN |
10.918 | 0.057 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/COUT |
10.918 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/CIN |
10.975 | 0.057 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/COUT |
10.975 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/CIN |
11.032 | 0.057 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/COUT |
11.032 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/CIN |
11.089 | 0.057 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/COUT |
11.089 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/CIN |
11.146 | 0.057 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/COUT |
11.146 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/CIN |
11.203 | 0.057 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/COUT |
11.203 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/CIN |
11.260 | 0.057 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/COUT |
11.260 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/CIN |
11.317 | 0.057 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/COUT |
11.317 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/CIN |
11.374 | 0.057 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/COUT |
11.374 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/CIN |
11.431 | 0.057 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/COUT |
11.431 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_19_s/CIN |
11.488 | 0.057 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_19_s/COUT |
11.488 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_20_s/CIN |
11.545 | 0.057 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_20_s/COUT |
11.545 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_21_s/CIN |
11.602 | 0.057 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_21_s/COUT |
11.602 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_22_s/CIN |
11.659 | 0.057 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_22_s/COUT |
11.659 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_23_s/CIN |
11.716 | 0.057 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_23_s/COUT |
11.716 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_24_s/CIN |
11.773 | 0.057 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_24_s/COUT |
11.773 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_25_s/CIN |
11.830 | 0.057 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_25_s/COUT |
11.830 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_26_s/CIN |
12.393 | 0.563 | tINS | FF | 4 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_26_s/SUM |
13.353 | 0.960 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s5/I1 |
14.452 | 1.099 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s5/F |
15.412 | 0.960 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s1/I3 |
16.038 | 0.626 | tINS | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s1/F |
16.998 | 0.960 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_itcm_sel_s4/I2 |
17.820 | 0.822 | tINS | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_itcm_sel_s4/F |
18.780 | 0.960 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_dtcm_sel_s2/I3 |
19.406 | 0.626 | tINS | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_dtcm_sel_s2/F |
20.366 | 0.960 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_dtcm_sel_s1/I3 |
20.992 | 0.626 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_dtcm_sel_s1/F |
21.951 | 0.960 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/dtcm_sel_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
20.000 | 0.000 | HCLK | |||
20.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
20.000 | 0.000 | tINS | RR | 1507 | HCLK_ibuf/O |
20.726 | 0.726 | tNET | RR | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/dtcm_sel_s0/CLK |
20.326 | -0.400 | tSu | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/dtcm_sel_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 20.000 |
Logic Level: | 14 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Arrival Data Path Delay: | cell: 10.207, 48.089%; route: 10.560, 49.752%; tC2Q: 0.458, 2.159% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Path 3
Path Summary:Slack | -1.625 |
Data Arrival Time | 21.951 |
Data Required Time | 20.326 |
From | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_3_s0 |
To | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/itcm_sel_s0 |
Launch Clk | HCLK[R] |
Latch Clk | HCLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | HCLK | |||
0.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
0.000 | 0.000 | tINS | RR | 1507 | HCLK_ibuf/O |
0.726 | 0.726 | tNET | RR | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_3_s0/CLK |
1.184 | 0.458 | tC2Q | RF | 8 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_3_s0/Q |
2.144 | 0.960 | tNET | FF | 4 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/RAD[3] |
2.404 | 0.259 | tINS | FF | 7 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/DO[2] |
3.364 | 0.960 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/I0 |
4.396 | 1.032 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/F |
5.356 | 0.960 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/I1 |
6.455 | 1.099 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/F |
7.415 | 0.960 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/I1 |
8.514 | 1.099 | tINS | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/F |
9.474 | 0.960 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/I1 |
10.519 | 1.045 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/COUT |
10.519 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/CIN |
10.576 | 0.057 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/COUT |
10.576 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/CIN |
10.633 | 0.057 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/COUT |
10.633 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/CIN |
10.690 | 0.057 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/COUT |
10.690 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/CIN |
10.747 | 0.057 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/COUT |
10.747 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/CIN |
10.804 | 0.057 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/COUT |
10.804 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/CIN |
10.861 | 0.057 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/COUT |
10.861 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/CIN |
10.918 | 0.057 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/COUT |
10.918 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/CIN |
10.975 | 0.057 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/COUT |
10.975 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/CIN |
11.032 | 0.057 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/COUT |
11.032 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/CIN |
11.089 | 0.057 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/COUT |
11.089 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/CIN |
11.146 | 0.057 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/COUT |
11.146 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/CIN |
11.203 | 0.057 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/COUT |
11.203 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/CIN |
11.260 | 0.057 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/COUT |
11.260 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/CIN |
11.317 | 0.057 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/COUT |
11.317 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/CIN |
11.374 | 0.057 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/COUT |
11.374 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/CIN |
11.431 | 0.057 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/COUT |
11.431 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_19_s/CIN |
11.488 | 0.057 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_19_s/COUT |
11.488 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_20_s/CIN |
11.545 | 0.057 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_20_s/COUT |
11.545 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_21_s/CIN |
11.602 | 0.057 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_21_s/COUT |
11.602 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_22_s/CIN |
11.659 | 0.057 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_22_s/COUT |
11.659 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_23_s/CIN |
11.716 | 0.057 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_23_s/COUT |
11.716 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_24_s/CIN |
11.773 | 0.057 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_24_s/COUT |
11.773 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_25_s/CIN |
11.830 | 0.057 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_25_s/COUT |
11.830 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_26_s/CIN |
12.393 | 0.563 | tINS | FF | 4 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_26_s/SUM |
13.353 | 0.960 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s5/I1 |
14.452 | 1.099 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s5/F |
15.412 | 0.960 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s1/I3 |
16.038 | 0.626 | tINS | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s1/F |
16.998 | 0.960 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_itcm_sel_s4/I2 |
17.820 | 0.822 | tINS | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_itcm_sel_s4/F |
18.780 | 0.960 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_itcm_sel_s2/I3 |
19.406 | 0.626 | tINS | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_itcm_sel_s2/F |
20.366 | 0.960 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_itcm_sel_s1/I3 |
20.992 | 0.626 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_itcm_sel_s1/F |
21.951 | 0.960 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/itcm_sel_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
20.000 | 0.000 | HCLK | |||
20.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
20.000 | 0.000 | tINS | RR | 1507 | HCLK_ibuf/O |
20.726 | 0.726 | tNET | RR | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/itcm_sel_s0/CLK |
20.326 | -0.400 | tSu | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/itcm_sel_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 20.000 |
Logic Level: | 14 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Arrival Data Path Delay: | cell: 10.207, 48.089%; route: 10.560, 49.752%; tC2Q: 0.458, 2.159% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Path 4
Path Summary:Slack | -1.120 |
Data Arrival Time | 21.446 |
Data Required Time | 20.326 |
From | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_3_s0 |
To | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/z_flag_mux_s0 |
Launch Clk | HCLK[R] |
Latch Clk | HCLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | HCLK | |||
0.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
0.000 | 0.000 | tINS | RR | 1507 | HCLK_ibuf/O |
0.726 | 0.726 | tNET | RR | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_3_s0/CLK |
1.184 | 0.458 | tC2Q | RF | 8 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_3_s0/Q |
2.144 | 0.960 | tNET | FF | 4 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_5_s0/RAD[3] |
2.404 | 0.259 | tINS | FF | 3 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_5_s0/DO[0] |
3.364 | 0.960 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_20_s2/I0 |
4.396 | 1.032 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_20_s2/F |
5.356 | 0.960 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_20_s1/I1 |
6.455 | 1.099 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_20_s1/F |
7.415 | 0.960 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_20_s0/I1 |
8.514 | 1.099 | tINS | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_20_s0/F |
9.474 | 0.960 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_rf1_mux/rf1_mux_out_20_s6/I2 |
10.295 | 0.822 | tINS | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_rf1_mux/rf1_mux_out_20_s6/F |
11.255 | 0.960 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/n1629_s12/I1 |
12.354 | 1.099 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/n1629_s12/F |
13.314 | 0.960 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/n1629_s7/I1 |
14.413 | 1.099 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/n1629_s7/F |
15.373 | 0.960 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/n1629_s4/I1 |
16.472 | 1.099 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/n1629_s4/F |
17.432 | 0.960 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/nxt_z_flag_mux_s9/I2 |
18.254 | 0.822 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/nxt_z_flag_mux_s9/F |
19.214 | 0.960 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/nxt_z_flag_mux_s6/I1 |
19.363 | 0.149 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/nxt_z_flag_mux_s6/O |
20.323 | 0.960 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/nxt_z_flag_mux_s3/I0 |
20.486 | 0.163 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/nxt_z_flag_mux_s3/O |
21.446 | 0.960 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/z_flag_mux_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
20.000 | 0.000 | HCLK | |||
20.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
20.000 | 0.000 | tINS | RR | 1507 | HCLK_ibuf/O |
20.726 | 0.726 | tNET | RR | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/z_flag_mux_s0/CLK |
20.326 | -0.400 | tSu | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/z_flag_mux_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 20.000 |
Logic Level: | 10 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Arrival Data Path Delay: | cell: 8.742, 42.191%; route: 11.520, 55.597%; tC2Q: 0.458, 2.212% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Path 5
Path Summary:Slack | 1.035 |
Data Arrival Time | 19.291 |
Data Required Time | 20.326 |
From | M1_inst/u_CortexM1Integration/u_cortexm1/u_ahb/HADDR_25_s0 |
To | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uInputStage0/PendTranReg_s1 |
Launch Clk | HCLK[R] |
Latch Clk | HCLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | HCLK | |||
0.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
0.000 | 0.000 | tINS | RR | 1507 | HCLK_ibuf/O |
0.726 | 0.726 | tNET | RR | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_ahb/HADDR_25_s0/CLK |
1.184 | 0.458 | tC2Q | RF | 3 | M1_inst/u_CortexM1Integration/u_cortexm1/u_ahb/HADDR_25_s0/Q |
2.144 | 0.960 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage14/uOutputArb/NoPortNext_s7/I1 |
3.243 | 1.099 | tINS | FF | 8 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage14/uOutputArb/NoPortNext_s7/F |
4.203 | 0.960 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage11/uOutputArb/NoPortNext_s3/I1 |
5.302 | 1.099 | tINS | FF | 6 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage11/uOutputArb/NoPortNext_s3/F |
6.262 | 0.960 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uMatrixDecodeS0/AddrOutPort_2_s2/I1 |
7.361 | 1.099 | tINS | FF | 3 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uMatrixDecodeS0/AddrOutPort_2_s2/F |
8.321 | 0.960 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uMatrixDecodeS0/AddrOutPort_0_s4/I0 |
9.353 | 1.032 | tINS | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uMatrixDecodeS0/AddrOutPort_0_s4/F |
10.313 | 0.960 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uMatrixDecodeS0/AddrOutPort_0_s1/I2 |
11.135 | 0.822 | tINS | FF | 11 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uMatrixDecodeS0/AddrOutPort_0_s1/F |
12.095 | 0.960 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage8/Active0to8_s13/I2 |
12.917 | 0.822 | tINS | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage8/Active0to8_s13/F |
13.877 | 0.960 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage8/Active0to8_s5/I1 |
14.026 | 0.149 | tINS | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage8/Active0to8_s5/O |
14.986 | 0.960 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage8/Active0to8_s1/I1 |
15.149 | 0.163 | tINS | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage8/Active0to8_s1/O |
16.109 | 0.960 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage8/Active0to8_s/I1 |
16.272 | 0.163 | tINS | FF | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage8/Active0to8_s/O |
17.232 | 0.960 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uInputStage0/n115_s0/I1 |
18.331 | 1.099 | tINS | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uInputStage0/n115_s0/F |
19.291 | 0.960 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uInputStage0/PendTranReg_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
20.000 | 0.000 | HCLK | |||
20.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
20.000 | 0.000 | tINS | RR | 1507 | HCLK_ibuf/O |
20.726 | 0.726 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uInputStage0/PendTranReg_s1/CLK |
20.326 | -0.400 | tSu | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uInputStage0/PendTranReg_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 20.000 |
Logic Level: | 9 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Arrival Data Path Delay: | cell: 7.547, 40.651%; route: 10.560, 56.880%; tC2Q: 0.458, 2.469% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |