Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\ahb_def_slave.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\BusMatrix.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\can.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\can_top.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_adder.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_ahb.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_alu_dec.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_core.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_ctl.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_ctl_add3.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_ahb_dec.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_ahb_mux.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_bp.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_ctl.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_define.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_dw.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_mtx.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_mtx_dbg.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_mtx_sys.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_rom_tb.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_sys.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_tcm.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_undefs.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_decoder.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_defs.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dp.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_excpt.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_fetch.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_fns.vh
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_matrix_check_fns.vh
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_mem_ctl.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_multiplier.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_multiply_shift.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_mux4.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_nvic.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_nvic_ahb.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_nvic_ahb_os.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_nvic_defs.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_nvic_main.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_nvic_pri_lvl.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_nvic_pri_num.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_nvic_tree.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_nvic_undefs.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_reg_bank.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_shifter.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_undefs.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_ethmac_miim_wrapper.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_ethmac_rx_buffer_to_ahb.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_ethmac_rx_to_buffer.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_ethmac_rx_wrapper.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_ethmac_sdp_wrapper_32bit.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_ethmac_tx_wrapper.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_ethmac_wrapper.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_gpio.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_ahbif_ctrl.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_arbiter.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_async_fifo_clr.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_config.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_const.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_ctrl.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_eilmif_ctrl.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_fifo.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_gck.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_pad_lib.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_reg.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_regif.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_regif_ctrl.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_spiif.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_sync.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_sync_l2l.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_sync_p2p.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_to_iop.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_dualtimers.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_dualtimers_defs.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_dualtimers_frc.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_spi.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_timer.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_autocorrelation.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_balancefilter.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_collector.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_crngt_to_trng.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_dx_inv_chain.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_dx_trng_top.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_dxm_ff.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_dxm_interrupt_low.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_dxm_mux.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_dxm_mux_clk.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_dxm_sync.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_ehr.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_entropy_gen.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_gtech_models.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_lfsr_new.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_line.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_noise_gen.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_pmf_table.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_prng_top_wrap.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_reg_file.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_rng_engine.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_rng_misc.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_rng_top.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_rng_top_wrap_unconnected.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_rosc.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_rst_logic.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_sample_cntr.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_slave_bus_ifc.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_sync.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_tests_misc.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_top.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_uart.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_watchdog.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_watchdog_defs.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_watchdog_frc.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_iop_gpio.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\CortexM1Dbg.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\CortexM1DbgIntegration.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\CortexM1DbgIntegrationWrapper.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\dapahbap.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPAhbApAhbSync.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPAhbApDapSync.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPAhbApDefs.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPAhbApMst.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPAhbApSlv.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPAhbApSyn.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPDecMux.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPDpApbDefs.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPDpApbSync.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPDpEnSync.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPDpIMux.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPDpSync.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPJtagDpDefs.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPJtagDpProtocol.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPSwDpApbIf.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPSwDpDefs.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPSwDpProtocol.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPSwDpSync.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\dapswjdp.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPSwjDpDefs.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPSwjWatcher.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\ddr3_1_4code_hs.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\ddr3_to_ahb_top.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DDR3_TOP.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\dtcmdbg.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\eth_mac.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\eth_mac_top.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\Gowin_EMPU_M1_top.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\GowinAhbExt.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\GowinCM1AhbExt.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\GowinCM1AhbExtWrapper.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\gw_ahb_psram.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\gw_apb_i2c.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\gw_apb_int_wrapper.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\gw_apb_sd.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\gw_gpio.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\InputStage.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\itcmdbg_2ac.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\MatrixDecodeS0.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\MatrixDecodeS1.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\MatrixDecodeS2.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\OutputArb1.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\OutputArb2.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\OutputArb3.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\OutputStage1.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\OutputStage2.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\OutputStage3.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\p_sse050_interconnect_f0_ahb_to_apb.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\p_sse050_interconnect_f0_apb_slave_mux.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\psram_code.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\PSRAM_TOP.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\rng_addr_params.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\rng_cc_params.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\rng_params.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\Rtc.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\RtcApbif.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\RtcControl.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\RtcCounter.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\RtcInterrupt.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\RtcParams.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\RtcRevAnd.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\RtcSynctoPCLK.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\RtcUpdate.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\sse050_int_apb_decoder.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\sse050_integration_peripherals.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\sync_p2p.v
F:\EMB_pub\embedded\arm\cortex_m1\solution\2.3\SD_SPI_IF_v1\ref_design\FPGA_RefDesign\DK_START_GW2A55_V1.3\gowin_empu_m1\src\gowin_empu_m1\temp\gw_empu_m1\cm1_option_defs.v
F:\EMB_pub\embedded\arm\cortex_m1\solution\2.3\SD_SPI_IF_v1\ref_design\FPGA_RefDesign\DK_START_GW2A55_V1.3\gowin_empu_m1\src\gowin_empu_m1\temp\gw_empu_m1\ahb_option_defs.v
F:\EMB_pub\embedded\arm\cortex_m1\solution\2.3\SD_SPI_IF_v1\ref_design\FPGA_RefDesign\DK_START_GW2A55_V1.3\gowin_empu_m1\src\gowin_empu_m1\temp\gw_empu_m1\parameter.vh
F:\EMB_pub\embedded\arm\cortex_m1\solution\2.3\SD_SPI_IF_v1\ref_design\FPGA_RefDesign\DK_START_GW2A55_V1.3\gowin_empu_m1\src\gowin_empu_m1\temp\gw_empu_m1\triple_speed_mac_param.v
F:\EMB_pub\embedded\arm\cortex_m1\solution\2.3\SD_SPI_IF_v1\ref_design\FPGA_RefDesign\DK_START_GW2A55_V1.3\gowin_empu_m1\src\gowin_empu_m1\temp\gw_empu_m1\triple_speed_mac_define.v
F:\EMB_pub\embedded\arm\cortex_m1\solution\2.3\SD_SPI_IF_v1\ref_design\FPGA_RefDesign\DK_START_GW2A55_V1.3\gowin_empu_m1\src\gowin_empu_m1\temp\gw_empu_m1\DDR3_define.v
GowinSynthesis Constraints File ---
Tool Version V1.9.11.02 (64-bit)
Part Number GW2A-LV55PG484C8/I7
Device GW2A-55
Device Version C
Created Time Fri May 23 14:43:22 2025
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module Gowin_EMPU_M1_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 5s, Elapsed time = 0h 0m 5s, Peak memory usage = 173.770MB
Running netlist conversion:
    CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.143s, Peak memory usage = 173.770MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 173.770MB
    Optimizing Phase 1: CPU time = 0h 0m 0.406s, Elapsed time = 0h 0m 0.408s, Peak memory usage = 173.770MB
    Optimizing Phase 2: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 173.770MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.765s, Elapsed time = 0h 0m 0.754s, Peak memory usage = 173.770MB
    Inferring Phase 1: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.078s, Peak memory usage = 173.770MB
    Inferring Phase 2: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.095s, Peak memory usage = 173.770MB
    Inferring Phase 3: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.03s, Peak memory usage = 173.770MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 173.770MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.296s, Elapsed time = 0h 0m 0.291s, Peak memory usage = 173.770MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.5s, Elapsed time = 0h 0m 0.491s, Peak memory usage = 173.770MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 30s, Elapsed time = 0h 0m 31s, Peak memory usage = 173.770MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.968s, Elapsed time = 0h 0m 1s, Peak memory usage = 173.770MB
Generate output files:
    CPU time = 0h 0m 0.796s, Elapsed time = 0h 0m 0.854s, Peak memory usage = 184.688MB
Total Time and Memory Usage CPU time = 0h 0m 42s, Elapsed time = 0h 0m 43s, Peak memory usage = 184.688MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 34
I/O Buf 34
    IBUF 5
    OBUF 6
    IOBUF 23
Register 3160
    DFF 95
    DFFE 32
    DFFSE 1
    DFFR 3
    DFFRE 1
    DFFP 37
    DFFPE 100
    DFFC 617
    DFFCE 2265
    DFFNPE 7
    DL 1
    DLN 1
LUT 7082
    LUT2 630
    LUT3 2022
    LUT4 4430
ALU 276
    ALU 276
SSRAM 36
    RAM16S4 4
    RAM16SDP4 32
INV 27
    INV 27
DSP
    MULT36X36 1
BSRAM 64
    DPB 64

Resource Utilization Summary

Resource Usage Utilization
Logic 7601(7109 LUT, 276 ALU, 36 RAM16) / 54720 14%
Register 3160 / 42000 8%
  --Register as Latch 2 / 42000 <1%
  --Register as FF 3158 / 42000 8%
BSRAM 64 / 140 46%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 HCLK Base 10.000 100.000 0.000 5.000 HCLK_ibuf/I
2 JTAG_9 Base 10.000 100.000 0.000 5.000 JTAG_9_ibuf/I
3 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_w_clk_slv_20 Base 10.000 100.000 0.000 5.000 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_w_clk_slv_s9/F

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 HCLK 100.000(MHz) 60.208(MHz) 20 TOP
2 JTAG_9 100.000(MHz) 107.377(MHz) 10 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack -7.931
Data Arrival Time 13.335
Data Required Time 5.404
From u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/slave_cmd_5_s3
To u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_out_slv_r_1_s2
Launch Clk HCLK[F]
Latch Clk u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_w_clk_slv_20[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 HCLK
0.000 0.000 tCL RR 1 HCLK_ibuf/I
0.000 0.000 tINS RR 3126 HCLK_ibuf/O
0.360 0.360 tNET RR 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/slave_cmd_5_s3/CLK
0.592 0.232 tC2Q RF 6 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/slave_cmd_5_s3/Q
1.066 0.474 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_trans_end_sclk_Z_s3/I1
1.621 0.555 tINS FF 5 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_trans_end_sclk_Z_s3/F
2.095 0.474 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_word_len_3_s6/I1
2.650 0.555 tINS FF 7 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_word_len_3_s6/F
3.124 0.474 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_word_len_0_s5/I1
3.679 0.555 tINS FF 4 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_word_len_0_s5/F
4.153 0.474 tNET FF 2 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1232_s/I0
4.702 0.549 tINS FR 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1232_s/COUT
4.702 0.000 tNET RR 2 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1231_s/CIN
5.172 0.470 tINS RF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1231_s/SUM
5.646 0.474 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/tx_ptr_1_s0/I0
6.163 0.517 tINS FF 24 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/tx_ptr_1_s0/F
6.637 0.474 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1251_s43/I2
7.090 0.453 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1251_s43/F
7.564 0.474 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1251_s35/I1
7.667 0.103 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1251_s35/O
8.141 0.474 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1251_s31/I1
8.244 0.103 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1251_s31/O
8.718 0.474 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1251_s29/I1
8.821 0.103 tINS FF 2 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1251_s29/O
9.295 0.474 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n363_s7/I1
9.850 0.555 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n363_s7/F
10.324 0.474 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n363_s3/I1
10.879 0.555 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n363_s3/F
11.353 0.474 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n363_s1/I0
11.870 0.517 tINS FF 4 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n363_s1/F
12.344 0.474 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n363_s8/I0
12.861 0.517 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n363_s8/F
13.335 0.474 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_out_slv_r_1_s2/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
5.000 0.000 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_w_clk_slv_20
5.000 0.000 tCL FF 11 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_w_clk_slv_s9/F
5.474 0.474 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_out_slv_r_1_s2/CLK
5.439 -0.035 tUnc u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_out_slv_r_1_s2
5.404 -0.035 tSu 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_out_slv_r_1_s2
Path Statistics:
Clock Skew: 0.114
Setup Relationship: 5.000
Logic Level: 13
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%
Arrival Data Path Delay: cell: 6.107, 47.067%; route: 6.636, 51.145%; tC2Q: 0.232, 1.788%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%

Path 2

Path Summary:
Slack -7.785
Data Arrival Time 13.189
Data Required Time 5.404
From u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/slave_cmd_5_s3
To u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_out_slv_r_0_s2
Launch Clk HCLK[F]
Latch Clk u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_w_clk_slv_20[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 HCLK
0.000 0.000 tCL RR 1 HCLK_ibuf/I
0.000 0.000 tINS RR 3126 HCLK_ibuf/O
0.360 0.360 tNET RR 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/slave_cmd_5_s3/CLK
0.592 0.232 tC2Q RF 6 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/slave_cmd_5_s3/Q
1.066 0.474 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_trans_end_sclk_Z_s3/I1
1.621 0.555 tINS FF 5 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_trans_end_sclk_Z_s3/F
2.095 0.474 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_word_len_3_s6/I1
2.650 0.555 tINS FF 7 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_word_len_3_s6/F
3.124 0.474 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_word_len_0_s5/I1
3.679 0.555 tINS FF 4 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_word_len_0_s5/F
4.153 0.474 tNET FF 2 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1232_s/I0
4.702 0.549 tINS FR 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1232_s/COUT
4.702 0.000 tNET RR 2 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1231_s/CIN
5.172 0.470 tINS RF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1231_s/SUM
5.646 0.474 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/tx_ptr_1_s0/I0
6.163 0.517 tINS FF 24 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/tx_ptr_1_s0/F
6.637 0.474 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1251_s43/I2
7.090 0.453 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1251_s43/F
7.564 0.474 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1251_s35/I1
7.667 0.103 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1251_s35/O
8.141 0.474 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1251_s31/I1
8.244 0.103 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1251_s31/O
8.718 0.474 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1251_s29/I1
8.821 0.103 tINS FF 2 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1251_s29/O
9.295 0.474 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n363_s7/I1
9.850 0.555 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n363_s7/F
10.324 0.474 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n363_s3/I1
10.879 0.555 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n363_s3/F
11.353 0.474 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n363_s1/I0
11.870 0.517 tINS FF 4 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n363_s1/F
12.344 0.474 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n366_s3/I3
12.715 0.371 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n366_s3/F
13.189 0.474 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_out_slv_r_0_s2/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
5.000 0.000 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_w_clk_slv_20
5.000 0.000 tCL FF 11 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_w_clk_slv_s9/F
5.474 0.474 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_out_slv_r_0_s2/CLK
5.439 -0.035 tUnc u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_out_slv_r_0_s2
5.404 -0.035 tSu 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_out_slv_r_0_s2
Path Statistics:
Clock Skew: 0.114
Setup Relationship: 5.000
Logic Level: 13
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%
Arrival Data Path Delay: cell: 5.961, 46.465%; route: 6.636, 51.727%; tC2Q: 0.232, 1.808%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%

Path 3

Path Summary:
Slack -6.609
Data Arrival Time 16.934
Data Required Time 10.325
From u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/slave_cmd_2_s3
To u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_0_s1
Launch Clk HCLK[R]
Latch Clk HCLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 HCLK
0.000 0.000 tCL RR 1 HCLK_ibuf/I
0.000 0.000 tINS RR 3126 HCLK_ibuf/O
0.360 0.360 tNET RR 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/slave_cmd_2_s3/CLK
0.592 0.232 tC2Q RF 5 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/slave_cmd_2_s3/Q
1.066 0.474 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_wr_num_0_s3/I1
1.621 0.555 tINS FF 3 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_wr_num_0_s3/F
2.095 0.474 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_wr_num_0_s2/I1
2.650 0.555 tINS FF 3 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_wr_num_0_s2/F
3.124 0.474 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_wr_num_0_s1/I1
3.679 0.555 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_wr_num_0_s1/F
4.153 0.474 tNET FF 2 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n388_s0/I1
4.723 0.570 tINS FR 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n388_s0/COUT
4.723 0.000 tNET RR 2 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n389_s0/CIN
4.758 0.035 tINS RF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n389_s0/COUT
4.758 0.000 tNET FF 2 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n390_s0/CIN
4.793 0.035 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n390_s0/COUT
4.793 0.000 tNET FF 2 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n391_s0/CIN
4.829 0.035 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n391_s0/COUT
4.829 0.000 tNET FF 2 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n392_s0/CIN
4.864 0.035 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n392_s0/COUT
4.864 0.000 tNET FF 2 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n393_s0/CIN
4.899 0.035 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n393_s0/COUT
4.899 0.000 tNET FF 2 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n394_s0/CIN
4.934 0.035 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n394_s0/COUT
4.934 0.000 tNET FF 2 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n395_s0/CIN
4.969 0.035 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n395_s0/COUT
4.969 0.000 tNET FF 2 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n396_s0/CIN
5.005 0.035 tINS FF 3 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n396_s0/COUT
5.479 0.474 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n583_s13/I1
6.034 0.555 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n583_s13/F
6.508 0.474 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n583_s11/I3
6.879 0.371 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n583_s11/F
7.353 0.474 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n583_s8/I1
7.908 0.555 tINS FF 3 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n583_s8/F
8.382 0.474 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_1_s34/I2
8.835 0.453 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_1_s34/F
9.309 0.474 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_1_s25/I3
9.680 0.371 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_1_s25/F
10.154 0.474 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_1_s16/I0
10.671 0.517 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_1_s16/F
11.145 0.474 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_1_s6/I2
11.598 0.453 tINS FF 7 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_1_s6/F
12.072 0.474 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_1_s2/I3
12.443 0.371 tINS FF 11 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_1_s2/F
12.917 0.474 tNET FF 2 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n10_s0/I1
13.487 0.570 tINS FR 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n10_s0/COUT
13.487 0.000 tNET RR 2 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n11_s0/CIN
13.522 0.035 tINS RF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n11_s0/COUT
13.522 0.000 tNET FF 2 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n12_s0/CIN
13.557 0.035 tINS FF 11 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n12_s0/COUT
14.031 0.474 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_8_s7/I1
14.586 0.555 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_8_s7/F
15.060 0.474 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_8_s5/I3
15.431 0.371 tINS FF 10 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_8_s5/F
15.905 0.474 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n497_s2/I1
16.460 0.555 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n497_s2/F
16.934 0.474 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_0_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 HCLK
10.000 0.000 tCL RR 1 HCLK_ibuf/I
10.000 0.000 tINS RR 3126 HCLK_ibuf/O
10.360 0.360 tNET RR 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_0_s1/CLK
10.325 -0.035 tSu 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_0_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 20
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%
Arrival Data Path Delay: cell: 8.284, 49.982%; route: 8.058, 48.618%; tC2Q: 0.232, 1.400%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%

Path 4

Path Summary:
Slack -6.568
Data Arrival Time 16.893
Data Required Time 10.325
From u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/slave_cmd_2_s3
To u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_fifo/u_spi_txfifo/empty_s0
Launch Clk HCLK[R]
Latch Clk HCLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 HCLK
0.000 0.000 tCL RR 1 HCLK_ibuf/I
0.000 0.000 tINS RR 3126 HCLK_ibuf/O
0.360 0.360 tNET RR 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/slave_cmd_2_s3/CLK
0.592 0.232 tC2Q RF 5 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/slave_cmd_2_s3/Q
1.066 0.474 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_wr_num_0_s3/I1
1.621 0.555 tINS FF 3 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_wr_num_0_s3/F
2.095 0.474 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_wr_num_0_s2/I1
2.650 0.555 tINS FF 3 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_wr_num_0_s2/F
3.124 0.474 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_wr_num_0_s1/I1
3.679 0.555 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_wr_num_0_s1/F
4.153 0.474 tNET FF 2 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n388_s0/I1
4.723 0.570 tINS FR 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n388_s0/COUT
4.723 0.000 tNET RR 2 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n389_s0/CIN
4.758 0.035 tINS RF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n389_s0/COUT
4.758 0.000 tNET FF 2 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n390_s0/CIN
4.793 0.035 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n390_s0/COUT
4.793 0.000 tNET FF 2 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n391_s0/CIN
4.829 0.035 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n391_s0/COUT
4.829 0.000 tNET FF 2 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n392_s0/CIN
4.864 0.035 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n392_s0/COUT
4.864 0.000 tNET FF 2 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n393_s0/CIN
4.899 0.035 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n393_s0/COUT
4.899 0.000 tNET FF 2 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n394_s0/CIN
4.934 0.035 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n394_s0/COUT
4.934 0.000 tNET FF 2 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n395_s0/CIN
4.969 0.035 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n395_s0/COUT
4.969 0.000 tNET FF 2 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n396_s0/CIN
5.005 0.035 tINS FF 3 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n396_s0/COUT
5.479 0.474 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n583_s13/I1
6.034 0.555 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n583_s13/F
6.508 0.474 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n583_s11/I3
6.879 0.371 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n583_s11/F
7.353 0.474 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n583_s8/I1
7.908 0.555 tINS FF 3 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n583_s8/F
8.382 0.474 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_1_s34/I2
8.835 0.453 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_1_s34/F
9.309 0.474 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_1_s25/I3
9.680 0.371 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_1_s25/F
10.154 0.474 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_1_s16/I0
10.671 0.517 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_1_s16/F
11.145 0.474 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_1_s6/I2
11.598 0.453 tINS FF 7 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_1_s6/F
12.072 0.474 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_fifo/u_spi_txfifo/next_gray_rd_ptr_0_s2/I1
12.627 0.555 tINS FF 33 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_fifo/u_spi_txfifo/next_gray_rd_ptr_0_s2/F
13.101 0.474 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_fifo/u_spi_txfifo/next_gray_rd_ptr_1_s1/I3
13.472 0.371 tINS FF 2 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_fifo/u_spi_txfifo/next_gray_rd_ptr_1_s1/F
13.946 0.474 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_fifo/u_spi_txfifo/next_gray_rd_ptr_1_s0/I2
14.399 0.453 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_fifo/u_spi_txfifo/next_gray_rd_ptr_1_s0/F
14.873 0.474 tNET FF 2 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_fifo/u_spi_txfifo/n329_s0/I0
15.390 0.517 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_fifo/u_spi_txfifo/n329_s0/COUT
15.864 0.474 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_fifo/u_spi_txfifo/n332_s2/I1
16.419 0.555 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_fifo/u_spi_txfifo/n332_s2/F
16.893 0.474 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_fifo/u_spi_txfifo/empty_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 HCLK
10.000 0.000 tCL RR 1 HCLK_ibuf/I
10.000 0.000 tINS RR 3126 HCLK_ibuf/O
10.360 0.360 tNET RR 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_fifo/u_spi_txfifo/empty_s0/CLK
10.325 -0.035 tSu 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_fifo/u_spi_txfifo/empty_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 19
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%
Arrival Data Path Delay: cell: 8.243, 49.857%; route: 8.058, 48.740%; tC2Q: 0.232, 1.403%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%

Path 5

Path Summary:
Slack -6.507
Data Arrival Time 16.832
Data Required Time 10.325
From u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/slave_cmd_2_s3
To u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_1_s1
Launch Clk HCLK[R]
Latch Clk HCLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 HCLK
0.000 0.000 tCL RR 1 HCLK_ibuf/I
0.000 0.000 tINS RR 3126 HCLK_ibuf/O
0.360 0.360 tNET RR 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/slave_cmd_2_s3/CLK
0.592 0.232 tC2Q RF 5 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/slave_cmd_2_s3/Q
1.066 0.474 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_wr_num_0_s3/I1
1.621 0.555 tINS FF 3 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_wr_num_0_s3/F
2.095 0.474 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_wr_num_0_s2/I1
2.650 0.555 tINS FF 3 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_wr_num_0_s2/F
3.124 0.474 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_wr_num_0_s1/I1
3.679 0.555 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_wr_num_0_s1/F
4.153 0.474 tNET FF 2 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n388_s0/I1
4.723 0.570 tINS FR 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n388_s0/COUT
4.723 0.000 tNET RR 2 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n389_s0/CIN
4.758 0.035 tINS RF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n389_s0/COUT
4.758 0.000 tNET FF 2 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n390_s0/CIN
4.793 0.035 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n390_s0/COUT
4.793 0.000 tNET FF 2 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n391_s0/CIN
4.829 0.035 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n391_s0/COUT
4.829 0.000 tNET FF 2 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n392_s0/CIN
4.864 0.035 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n392_s0/COUT
4.864 0.000 tNET FF 2 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n393_s0/CIN
4.899 0.035 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n393_s0/COUT
4.899 0.000 tNET FF 2 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n394_s0/CIN
4.934 0.035 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n394_s0/COUT
4.934 0.000 tNET FF 2 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n395_s0/CIN
4.969 0.035 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n395_s0/COUT
4.969 0.000 tNET FF 2 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n396_s0/CIN
5.005 0.035 tINS FF 3 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n396_s0/COUT
5.479 0.474 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n583_s13/I1
6.034 0.555 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n583_s13/F
6.508 0.474 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n583_s11/I3
6.879 0.371 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n583_s11/F
7.353 0.474 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n583_s8/I1
7.908 0.555 tINS FF 3 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n583_s8/F
8.382 0.474 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_1_s34/I2
8.835 0.453 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_1_s34/F
9.309 0.474 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_1_s25/I3
9.680 0.371 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_1_s25/F
10.154 0.474 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_1_s16/I0
10.671 0.517 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_1_s16/F
11.145 0.474 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_1_s6/I2
11.598 0.453 tINS FF 7 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_1_s6/F
12.072 0.474 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_1_s2/I3
12.443 0.371 tINS FF 11 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_1_s2/F
12.917 0.474 tNET FF 2 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n10_s0/I1
13.487 0.570 tINS FR 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n10_s0/COUT
13.487 0.000 tNET RR 2 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n11_s0/CIN
13.522 0.035 tINS RF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n11_s0/COUT
13.522 0.000 tNET FF 2 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n12_s0/CIN
13.557 0.035 tINS FF 11 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n12_s0/COUT
14.031 0.474 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_8_s7/I1
14.586 0.555 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_8_s7/F
15.060 0.474 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_8_s5/I3
15.431 0.371 tINS FF 10 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_8_s5/F
15.905 0.474 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n496_s2/I2
16.358 0.453 tINS FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n496_s2/F
16.832 0.474 tNET FF 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_1_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 HCLK
10.000 0.000 tCL RR 1 HCLK_ibuf/I
10.000 0.000 tINS RR 3126 HCLK_ibuf/O
10.360 0.360 tNET RR 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_1_s1/CLK
10.325 -0.035 tSu 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_1_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 20
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%
Arrival Data Path Delay: cell: 8.182, 49.673%; route: 8.058, 48.919%; tC2Q: 0.232, 1.408%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%