Synthesis Messages

Report Title GowinSynthesis Report
Design File E:\IP_Release\EasyCDR\1.2\ref_design\Gowin_EasyCDR_RefDesign_Exceed_1Gbps\project\src\easycdr\easycdr.v
E:\IP_Release\EasyCDR\1.2\ref_design\Gowin_EasyCDR_RefDesign_Exceed_1Gbps\project\src\motivation_response.v
E:\IP_Release\EasyCDR\1.2\ref_design\Gowin_EasyCDR_RefDesign_Exceed_1Gbps\project\src\pll_hclk\pll_hclk.v
E:\IP_Release\EasyCDR\1.2\ref_design\Gowin_EasyCDR_RefDesign_Exceed_1Gbps\project\src\pll_hclk_tx\pll_hclk_tx.v
E:\IP_Release\EasyCDR\1.2\ref_design\Gowin_EasyCDR_RefDesign_Exceed_1Gbps\project\src\top.v
D:\Gowin\Gowin_V1.9.9.03_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v
D:\Gowin\Gowin_V1.9.9.03_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v
D:\Gowin\Gowin_V1.9.9.03_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v
D:\Gowin\Gowin_V1.9.9.03_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v
D:\Gowin\Gowin_V1.9.9.03_x64\IDE\data\ipcores\GAO\GW_CON\gw_con_top.v
D:\Gowin\Gowin_V1.9.9.03_x64\IDE\data\ipcores\gw_jtag.v
E:\IP_Release\EasyCDR\1.2\ref_design\Gowin_EasyCDR_RefDesign_Exceed_1Gbps\project\impl\gwsynthesis\RTL_GAO\gw_gao_top.v
GowinSynthesis Constraints File ---
Tool Version V1.9.9.03 (64-bit)
Part Number GW5A-LV25UG324ES
Device GW5A-25
Device Version A
Created Time Tue Apr 30 14:41:05 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.625s, Elapsed time = 0h 0m 0.536s, Peak memory usage = 531.555MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.049s, Peak memory usage = 531.555MB
    Optimizing Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.026s, Peak memory usage = 531.555MB
    Optimizing Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.055s, Peak memory usage = 531.555MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.02s, Peak memory usage = 531.555MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 531.555MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 531.555MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 531.555MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.041s, Peak memory usage = 531.555MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 531.555MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 531.555MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 531.555MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.057s, Peak memory usage = 531.555MB
Generate output files:
    CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.081s, Peak memory usage = 531.555MB
Total Time and Memory Usage CPU time = 0h 0m 2s, Elapsed time = 0h 0m 1s, Peak memory usage = 531.555MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 14
I/O Buf 12
    IBUF 6
    OBUF 4
    TLVDS_IBUF 1
    ELVDS_OBUF 1
Register 789
    DFFRE 2
    DFFPE 57
    DFFCE 730
LUT 968
    LUT2 100
    LUT3 293
    LUT4 575
MUX 1
    MUX16 1
ALU 13
    ALU 13
INV 11
    INV 11
IOLOGIC 2
    OSER8 1
    OSIDES64 1
BSRAM 3
    SDPB 3
CLOCK 8
    CLKDIV 2
    DHCE 4
    PLLA 2
Black Box 1
    GW_JTAG 1

Resource Utilization Summary

Resource Usage Utilization
Logic 1000(987 LUT, 13 ALU) / 23040 5%
Register 789 / 23685 4%
  --Register as Latch 0 / 23685 0%
  --Register as FF 789 / 23685 4%
BSRAM 3 / 56 6%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
board_clk Base 20.000 50.0 0.000 10.000 board_clk_ibuf/I
u_motivation_response/u_pll_hclk_tx/PLLA_inst/CLKOUT0.default_gen_clk Generated 1.667 600.0 0.000 0.833 board_clk_ibuf/I board_clk u_motivation_response/u_pll_hclk_tx/PLLA_inst/CLKOUT0
u_motivation_response/u_pll_hclk/PLLA_inst/CLKOUT0.default_gen_clk Generated 3.333 300.0 0.000 1.667 board_clk_ibuf/I board_clk u_motivation_response/u_pll_hclk/PLLA_inst/CLKOUT0
u_motivation_response/u_pll_hclk/PLLA_inst/CLKOUT1.default_gen_clk Generated 3.333 300.0 0.000 1.667 board_clk_ibuf/I board_clk u_motivation_response/u_pll_hclk/PLLA_inst/CLKOUT1
u_motivation_response/u_pll_hclk/PLLA_inst/CLKOUT2.default_gen_clk Generated 3.333 300.0 0.000 1.667 board_clk_ibuf/I board_clk u_motivation_response/u_pll_hclk/PLLA_inst/CLKOUT2
u_motivation_response/u_pll_hclk/PLLA_inst/CLKOUT3.default_gen_clk Generated 3.333 300.0 0.000 1.667 board_clk_ibuf/I board_clk u_motivation_response/u_pll_hclk/PLLA_inst/CLKOUT3
u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT.default_gen_clk Generated 6.667 150.0 0.000 3.333 u_motivation_response/u_pll_hclk_tx/PLLA_inst/CLKOUT0 u_motivation_response/u_pll_hclk_tx/PLLA_inst/CLKOUT0.default_gen_clk u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT
u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT.default_gen_clk Generated 13.333 75.0 0.000 6.667 u_motivation_response/u_pll_hclk/PLLA_inst/CLKOUT0 u_motivation_response/u_pll_hclk/PLLA_inst/CLKOUT0.default_gen_clk u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 board_clk 50.000(MHz) 382.592(MHz) 3 TOP
2 u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT.default_gen_clk 150.000(MHz) 580.552(MHz) 2 TOP
3 u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT.default_gen_clk 75.000(MHz) 188.058(MHz) 6 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 0.949
Data Arrival Time 1.132
Data Required Time 2.081
From u_EasyCDR_Top/u_easycdr/u_share_logic/cen_s0
To u_EasyCDR_Top/u_easycdr/u_share_logic/dhcen_625m_270
Launch Clk board_clk[F]
Latch Clk u_motivation_response/u_pll_hclk/PLLA_inst/CLKOUT3.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 board_clk
0.000 0.000 tCL RR 1 board_clk_ibuf/I
0.000 0.000 tINS RR 12 board_clk_ibuf/O
0.375 0.375 tNET RR 1 u_EasyCDR_Top/u_easycdr/u_share_logic/cen_s0/CLK
0.757 0.382 tC2Q RR 4 u_EasyCDR_Top/u_easycdr/u_share_logic/cen_s0/Q
1.132 0.375 tNET RR 1 u_EasyCDR_Top/u_easycdr/u_share_logic/dhcen_625m_270/CEN
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
1.667 0.000 u_motivation_response/u_pll_hclk/PLLA_inst/CLKOUT3.default_gen_clk
1.948 0.281 tCL FF 1 u_motivation_response/u_pll_hclk/PLLA_inst/CLKOUT3
2.298 0.350 tNET FF 3 u_EasyCDR_Top/u_easycdr/u_share_logic/dhcen_625m_270/CLKIN
2.263 -0.035 tUnc u_EasyCDR_Top/u_easycdr/u_share_logic/dhcen_625m_270
2.081 -0.182 tSu 1 u_EasyCDR_Top/u_easycdr/u_share_logic/dhcen_625m_270
Path Statistics:
Clock Skew: 0.257
Setup Relationship: 1.667
Logic Level: 1
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 0.000, 0.000%; route: 0.375, 49.505%; tC2Q: 0.382, 50.495%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 2

Path Summary:
Slack 0.949
Data Arrival Time 1.132
Data Required Time 2.081
From u_EasyCDR_Top/u_easycdr/u_share_logic/cen_s0
To u_EasyCDR_Top/u_easycdr/u_share_logic/dhcen_625m_180
Launch Clk board_clk[F]
Latch Clk u_motivation_response/u_pll_hclk/PLLA_inst/CLKOUT2.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 board_clk
0.000 0.000 tCL RR 1 board_clk_ibuf/I
0.000 0.000 tINS RR 12 board_clk_ibuf/O
0.375 0.375 tNET RR 1 u_EasyCDR_Top/u_easycdr/u_share_logic/cen_s0/CLK
0.757 0.382 tC2Q RR 4 u_EasyCDR_Top/u_easycdr/u_share_logic/cen_s0/Q
1.132 0.375 tNET RR 1 u_EasyCDR_Top/u_easycdr/u_share_logic/dhcen_625m_180/CEN
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
1.667 0.000 u_motivation_response/u_pll_hclk/PLLA_inst/CLKOUT2.default_gen_clk
1.948 0.281 tCL FF 1 u_motivation_response/u_pll_hclk/PLLA_inst/CLKOUT2
2.298 0.350 tNET FF 3 u_EasyCDR_Top/u_easycdr/u_share_logic/dhcen_625m_180/CLKIN
2.263 -0.035 tUnc u_EasyCDR_Top/u_easycdr/u_share_logic/dhcen_625m_180
2.081 -0.182 tSu 1 u_EasyCDR_Top/u_easycdr/u_share_logic/dhcen_625m_180
Path Statistics:
Clock Skew: 0.257
Setup Relationship: 1.667
Logic Level: 1
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 0.000, 0.000%; route: 0.375, 49.505%; tC2Q: 0.382, 50.495%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 3

Path Summary:
Slack 0.949
Data Arrival Time 1.132
Data Required Time 2.081
From u_EasyCDR_Top/u_easycdr/u_share_logic/cen_s0
To u_EasyCDR_Top/u_easycdr/u_share_logic/dhcen_625m_90
Launch Clk board_clk[F]
Latch Clk u_motivation_response/u_pll_hclk/PLLA_inst/CLKOUT1.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 board_clk
0.000 0.000 tCL RR 1 board_clk_ibuf/I
0.000 0.000 tINS RR 12 board_clk_ibuf/O
0.375 0.375 tNET RR 1 u_EasyCDR_Top/u_easycdr/u_share_logic/cen_s0/CLK
0.757 0.382 tC2Q RR 4 u_EasyCDR_Top/u_easycdr/u_share_logic/cen_s0/Q
1.132 0.375 tNET RR 1 u_EasyCDR_Top/u_easycdr/u_share_logic/dhcen_625m_90/CEN
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
1.667 0.000 u_motivation_response/u_pll_hclk/PLLA_inst/CLKOUT1.default_gen_clk
1.948 0.281 tCL FF 1 u_motivation_response/u_pll_hclk/PLLA_inst/CLKOUT1
2.298 0.350 tNET FF 3 u_EasyCDR_Top/u_easycdr/u_share_logic/dhcen_625m_90/CLKIN
2.263 -0.035 tUnc u_EasyCDR_Top/u_easycdr/u_share_logic/dhcen_625m_90
2.081 -0.182 tSu 1 u_EasyCDR_Top/u_easycdr/u_share_logic/dhcen_625m_90
Path Statistics:
Clock Skew: 0.257
Setup Relationship: 1.667
Logic Level: 1
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 0.000, 0.000%; route: 0.375, 49.505%; tC2Q: 0.382, 50.495%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 4

Path Summary:
Slack 0.949
Data Arrival Time 1.132
Data Required Time 2.081
From u_EasyCDR_Top/u_easycdr/u_share_logic/cen_s0
To u_EasyCDR_Top/u_easycdr/u_share_logic/dhcen_625m_0
Launch Clk board_clk[F]
Latch Clk u_motivation_response/u_pll_hclk/PLLA_inst/CLKOUT0.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 board_clk
0.000 0.000 tCL RR 1 board_clk_ibuf/I
0.000 0.000 tINS RR 12 board_clk_ibuf/O
0.375 0.375 tNET RR 1 u_EasyCDR_Top/u_easycdr/u_share_logic/cen_s0/CLK
0.757 0.382 tC2Q RR 4 u_EasyCDR_Top/u_easycdr/u_share_logic/cen_s0/Q
1.132 0.375 tNET RR 1 u_EasyCDR_Top/u_easycdr/u_share_logic/dhcen_625m_0/CEN
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
1.667 0.000 u_motivation_response/u_pll_hclk/PLLA_inst/CLKOUT0.default_gen_clk
1.948 0.281 tCL FF 1 u_motivation_response/u_pll_hclk/PLLA_inst/CLKOUT0
2.298 0.350 tNET FF 3 u_EasyCDR_Top/u_easycdr/u_share_logic/dhcen_625m_0/CLKIN
2.263 -0.035 tUnc u_EasyCDR_Top/u_easycdr/u_share_logic/dhcen_625m_0
2.081 -0.182 tSu 1 u_EasyCDR_Top/u_easycdr/u_share_logic/dhcen_625m_0
Path Statistics:
Clock Skew: 0.257
Setup Relationship: 1.667
Logic Level: 1
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 0.000, 0.000%; route: 0.375, 49.505%; tC2Q: 0.382, 50.495%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 5

Path Summary:
Slack 4.944
Data Arrival Time 2.396
Data Required Time 7.340
From u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_8_s0
To u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_tmp_0_s0
Launch Clk u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT.default_gen_clk[R]
Latch Clk u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT.default_gen_clk
0.362 0.362 tCL RR 26 u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT
0.737 0.375 tNET RR 1 u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_8_s0/CLK
1.120 0.382 tC2Q RR 2 u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_8_s0/Q
1.495 0.375 tNET RR 1 u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_8_cal_0_s0/I0
2.021 0.526 tINS RR 2 u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_8_cal_0_s0/F
2.396 0.375 tNET RR 1 u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_tmp_0_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
6.667 0.000 u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT.default_gen_clk
7.029 0.362 tCL RR 26 u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT
7.404 0.375 tNET RR 1 u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_tmp_0_s0/CLK
7.340 -0.064 tSu 1 u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_tmp_0_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 6.667
Logic Level: 2
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 0.526, 31.726%; route: 0.750, 45.214%; tC2Q: 0.382, 23.060%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%