Timing Messages

Report Title Timing Analysis Report
Design File E:\IP_Release\EasyCDR\1.2\ref_design\Gowin_EasyCDR_RefDesign_Exceed_1Gbps\project\impl\gwsynthesis\fpga_project.vg
Physical Constraints File E:\IP_Release\EasyCDR\1.2\ref_design\Gowin_EasyCDR_RefDesign_Exceed_1Gbps\project\src\fpga_project.cst
Timing Constraint File E:\IP_Release\EasyCDR\1.2\ref_design\Gowin_EasyCDR_RefDesign_Exceed_1Gbps\project\src\fpga_project.sdc
Tool Version V1.9.9.03 (64-bit)
Part Number GW5A-LV25UG324ES
Device GW5A-25
Device Version A
Created Time Tue Apr 30 14:46:34 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model Slow 0.855V 0C ES
Hold Delay Model Fast 0.945V 85C ES
Numbers of Paths Analyzed 3314
Numbers of Endpoints Analyzed 2524
Numbers of Falling Endpoints 3
Numbers of Setup Violated Endpoints 0
Numbers of Hold Violated Endpoints 0

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Objects
tck_pad Base 50.000 20.000 0.000 25.000 tck_pad_i
board_clk Base 20.000 50.000 0.000 10.000 gowin_ibuf_board_clk/I
hclk_0_rx Generated 3.333 300.000 0.000 1.667 gowin_ibuf_board_clk/I board_clk u_motivation_response/u_pll_hclk/PLLA_inst/CLKOUT0
hclk_180_rx Generated 3.333 300.000 1.667 0.000 gowin_ibuf_board_clk/I board_clk u_motivation_response/u_pll_hclk/PLLA_inst/CLKOUT2
hclk_90_rx Generated 3.333 300.000 0.833 2.500 gowin_ibuf_board_clk/I board_clk u_motivation_response/u_pll_hclk/PLLA_inst/CLKOUT1
hclk_0_tx Generated 1.667 600.000 0.000 0.833 gowin_ibuf_board_clk/I board_clk u_motivation_response/u_pll_hclk_tx/PLLA_inst/CLKOUT0
pclk_rx Generated 13.333 75.000 0.000 6.667 u_motivation_response/u_pll_hclk/PLLA_inst/CLKOUT0 hclk_0_rx u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
hclk_270_rx Generated 3.333 300.000 2.500 0.833 gowin_ibuf_board_clk/I board_clk u_motivation_response/u_pll_hclk/PLLA_inst/CLKOUT3
pclk_tx Generated 6.667 150.000 0.000 3.333 u_motivation_response/u_pll_hclk_tx/PLLA_inst/CLKOUT0 hclk_0_tx u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 tck_pad 20.000(MHz) 116.874(MHz) 5 TOP
2 board_clk 50.000(MHz) 562.984(MHz) 3 TOP
3 pclk_rx 75.000(MHz) 130.288(MHz) 6 TOP
4 pclk_tx 150.000(MHz) 378.430(MHz) 2 TOP

No timing paths to get frequency of hclk_0_rx!

No timing paths to get frequency of hclk_180_rx!

No timing paths to get frequency of hclk_90_rx!

No timing paths to get frequency of hclk_0_tx!

No timing paths to get frequency of hclk_270_rx!

Total Negative Slack Summary:

Clock Name Analysis Type Endpoints TNS Number of Endpoints
tck_pad Setup 0.000 0
tck_pad Hold 0.000 0
board_clk Setup 0.000 0
board_clk Hold 0.000 0
hclk_0_rx Setup 0.000 0
hclk_0_rx Hold 0.000 0
hclk_180_rx Setup 0.000 0
hclk_180_rx Hold 0.000 0
hclk_90_rx Setup 0.000 0
hclk_90_rx Hold 0.000 0
hclk_0_tx Setup 0.000 0
hclk_0_tx Hold 0.000 0
pclk_rx Setup 0.000 0
pclk_rx Hold 0.000 0
hclk_270_rx Setup 0.000 0
hclk_270_rx Hold 0.000 0
pclk_tx Setup 0.000 0
pclk_tx Hold 0.000 0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 4.024 u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_8_s0/Q u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_tmp_5_s0/D pclk_tx:[R] pclk_tx:[R] 6.667 0.000 2.579
2 4.081 u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_1_s1/Q u_motivation_response/u_tx_module_top/u_OSER8/D1 pclk_tx:[R] pclk_tx:[R] 6.667 -0.034 2.455
3 4.205 u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_8_s0/Q u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_tmp_0_s0/D pclk_tx:[R] pclk_tx:[R] 6.667 0.009 2.389
4 4.358 u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_5_s1/Q u_motivation_response/u_tx_module_top/u_OSER8/D5 pclk_tx:[R] pclk_tx:[R] 6.667 -0.020 2.164
5 4.404 u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_4_s0/Q u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_3_s0/D pclk_tx:[R] pclk_tx:[R] 6.667 0.000 2.199
6 4.440 u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_7_s2/Q u_motivation_response/u_tx_module_top/u_OSER8/D7 pclk_tx:[R] pclk_tx:[R] 6.667 -0.020 2.081
7 4.458 u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_2_s0/Q u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_tmp_2_s0/D pclk_tx:[R] pclk_tx:[R] 6.667 -0.005 2.150
8 4.470 u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_0_s1/Q u_motivation_response/u_tx_module_top/u_OSER8/D0 pclk_tx:[R] pclk_tx:[R] 6.667 -0.020 2.049
9 4.497 u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_6_s1/Q u_motivation_response/u_tx_module_top/u_OSER8/D6 pclk_tx:[R] pclk_tx:[R] 6.667 -0.020 2.021
10 4.526 u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_4_s1/Q u_motivation_response/u_tx_module_top/u_OSER8/D4 pclk_tx:[R] pclk_tx:[R] 6.667 -0.029 2.003
11 4.551 u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_8_s0/Q u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_2_s0/D pclk_tx:[R] pclk_tx:[R] 6.667 0.014 2.037
12 4.611 u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_2_s1/Q u_motivation_response/u_tx_module_top/u_OSER8/D2 pclk_tx:[R] pclk_tx:[R] 6.667 -0.029 1.918
13 4.614 u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_3_s1/Q u_motivation_response/u_tx_module_top/u_OSER8/D3 pclk_tx:[R] pclk_tx:[R] 6.667 -0.029 1.918
14 4.619 u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_7_s0/Q u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_tmp_6_s0/D pclk_tx:[R] pclk_tx:[R] 6.667 -0.024 2.007
15 4.622 u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_6_s0/Q u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_0_s0/D pclk_tx:[R] pclk_tx:[R] 6.667 -0.014 1.995
16 4.625 u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_6_s0/Q u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_tmp_7_s0/D pclk_tx:[R] pclk_tx:[R] 6.667 -0.014 1.993
17 4.660 u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_1_s0/Q u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_tmp_3_s0/D pclk_tx:[R] pclk_tx:[R] 6.667 -0.005 1.947
18 4.732 u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_8_s0/Q u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_7_s0/D pclk_tx:[R] pclk_tx:[R] 6.667 0.024 1.847
19 4.779 u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_2_s0/Q u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_5_s0/D pclk_tx:[R] pclk_tx:[R] 6.667 0.000 1.824
20 4.957 u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_4_s0/Q u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_tmp_4_s0/D pclk_tx:[R] pclk_tx:[R] 6.667 -0.014 1.660
21 5.144 u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_7_s0/Q u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_tmp_1_s0/D pclk_tx:[R] pclk_tx:[R] 6.667 -0.009 1.469
22 5.146 u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_7_s0/Q u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_1_s0/D pclk_tx:[R] pclk_tx:[R] 6.667 -0.009 1.466
23 5.146 u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_7_s0/Q u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_6_s0/D pclk_tx:[R] pclk_tx:[R] 6.667 -0.009 1.466
24 5.187 u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_1_s0/Q u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_4_s0/D pclk_tx:[R] pclk_tx:[R] 6.667 0.009 1.406
25 5.658 u_EasyCDR_Top/u_easycdr/u_easycdr_64/u_gearbox_15_16_17_to_20/remained_cnt_1_s1/Q u_EasyCDR_Top/u_easycdr/u_easycdr_64/u_gearbox_15_16_17_to_20/o_dout_6_s0/D pclk_rx:[R] pclk_rx:[R] 13.333 0.015 7.597

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.100 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_23_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[7] pclk_rx:[R] pclk_rx:[R] 0.000 0.014 0.335
2 0.104 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_0_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[0] pclk_rx:[R] pclk_rx:[R] 0.000 0.018 0.335
3 0.108 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_4_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[4] pclk_rx:[R] pclk_rx:[R] 0.000 0.016 0.341
4 0.108 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_3_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[3] pclk_rx:[R] pclk_rx:[R] 0.000 0.016 0.341
5 0.150 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_2_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[2] pclk_rx:[R] pclk_rx:[R] 0.000 0.018 0.381
6 0.155 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_18_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[2] pclk_rx:[R] pclk_rx:[R] 0.000 0.016 0.388
7 0.155 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_17_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[1] pclk_rx:[R] pclk_rx:[R] 0.000 0.016 0.388
8 0.159 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_20_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[4] pclk_rx:[R] pclk_rx:[R] 0.000 0.020 0.388
9 0.209 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_8_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[8] pclk_rx:[R] pclk_rx:[R] 0.000 0.020 0.438
10 0.230 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_19_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[3] pclk_rx:[R] pclk_rx:[R] 0.000 0.016 0.463
11 0.234 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_22_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[6] pclk_rx:[R] pclk_rx:[R] 0.000 0.020 0.463
12 0.251 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_14_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[14] pclk_rx:[R] pclk_rx:[R] 0.000 0.022 0.478
13 0.275 u_motivation_response/u_prbs_inspector/dat_corr_cnt_3_s1/Q u_motivation_response/u_prbs_inspector/dat_corr_cnt_3_s1/D pclk_rx:[R] pclk_rx:[R] 0.000 0.000 0.300
14 0.275 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/D pclk_rx:[R] pclk_rx:[R] 0.000 0.000 0.300
15 0.275 u_EasyCDR_Top/u_easycdr/u_share_logic/delay_cnt_1_s0/Q u_EasyCDR_Top/u_easycdr/u_share_logic/delay_cnt_1_s0/D board_clk:[R] board_clk:[R] 0.000 0.000 0.300
16 0.275 gw_gao_inst_0/u_la0_top/word_count_7_s0/Q gw_gao_inst_0/u_la0_top/word_count_7_s0/D tck_pad:[R] tck_pad:[R] 0.000 0.000 0.300
17 0.278 gw_gao_inst_0/u_la0_top/word_count_0_s0/Q gw_gao_inst_0/u_la0_top/word_count_0_s0/D tck_pad:[R] tck_pad:[R] 0.000 0.000 0.303
18 0.278 gw_gao_inst_0/u_la0_top/word_count_4_s0/Q gw_gao_inst_0/u_la0_top/word_count_4_s0/D tck_pad:[R] tck_pad:[R] 0.000 0.000 0.303
19 0.278 gw_gao_inst_0/u_la0_top/word_count_10_s0/Q gw_gao_inst_0/u_la0_top/word_count_10_s0/D tck_pad:[R] tck_pad:[R] 0.000 0.000 0.303
20 0.278 gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/Q gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/D pclk_rx:[R] pclk_rx:[R] 0.000 0.000 0.303
21 0.278 gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/Q gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/D pclk_rx:[R] pclk_rx:[R] 0.000 0.000 0.303
22 0.278 gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/Q gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/D pclk_rx:[R] pclk_rx:[R] 0.000 0.000 0.303
23 0.278 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/D pclk_rx:[R] pclk_rx:[R] 0.000 0.000 0.303
24 0.278 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/D pclk_rx:[R] pclk_rx:[R] 0.000 0.000 0.303
25 0.278 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/D pclk_rx:[R] pclk_rx:[R] 0.000 0.000 0.303

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 3.595 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR pclk_rx:[F] pclk_rx:[R] 6.667 0.013 2.711
2 3.732 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR pclk_rx:[F] pclk_rx:[R] 6.667 0.003 2.584
3 3.781 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s1/CLEAR pclk_rx:[F] pclk_rx:[R] 6.667 0.011 2.528
4 4.025 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR pclk_rx:[F] pclk_rx:[R] 6.667 0.002 2.293
5 4.025 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLEAR pclk_rx:[F] pclk_rx:[R] 6.667 0.002 2.293
6 4.025 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR pclk_rx:[F] pclk_rx:[R] 6.667 0.002 2.293
7 4.163 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR pclk_rx:[F] pclk_rx:[R] 6.667 -0.023 2.180
8 4.376 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_0_s0/CLEAR pclk_rx:[F] pclk_rx:[R] 6.667 0.013 1.930
9 4.376 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_1/trig_dly_in_0_s0/CLEAR pclk_rx:[F] pclk_rx:[R] 6.667 0.013 1.930
10 4.496 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR pclk_rx:[F] pclk_rx:[R] 6.667 0.003 1.820
11 4.496 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR pclk_rx:[F] pclk_rx:[R] 6.667 0.003 1.820
12 4.496 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0/CLEAR pclk_rx:[F] pclk_rx:[R] 6.667 0.003 1.820
13 4.496 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_1_s0/CLEAR pclk_rx:[F] pclk_rx:[R] 6.667 0.003 1.820
14 4.502 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET pclk_rx:[F] pclk_rx:[R] 6.667 -0.025 1.843
15 4.502 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR pclk_rx:[F] pclk_rx:[R] 6.667 -0.025 1.843
16 4.502 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR pclk_rx:[F] pclk_rx:[R] 6.667 -0.025 1.843
17 4.502 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR pclk_rx:[F] pclk_rx:[R] 6.667 -0.025 1.843
18 4.505 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_1/match_sep_s0/CLEAR pclk_rx:[F] pclk_rx:[R] 6.667 -0.006 1.820
19 4.509 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR pclk_rx:[F] pclk_rx:[R] 6.667 -0.033 1.843
20 4.509 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR pclk_rx:[F] pclk_rx:[R] 6.667 -0.033 1.843
21 4.510 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET pclk_rx:[F] pclk_rx:[R] 6.667 -0.016 1.825
22 4.593 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLEAR pclk_rx:[F] pclk_rx:[R] 6.667 -0.028 1.754
23 4.593 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR pclk_rx:[F] pclk_rx:[R] 6.667 -0.028 1.754
24 4.593 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR pclk_rx:[F] pclk_rx:[R] 6.667 -0.028 1.754
25 4.670 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR pclk_rx:[F] pclk_rx:[R] 6.667 0.013 1.636

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.303 u_EasyCDR_Top/u_easycdr/u_share_logic/rst_n_s0/Q u_EasyCDR_Top/u_easycdr/u_share_logic/delay_cnt_0_s0/CLEAR board_clk:[R] board_clk:[R] 0.000 0.000 0.250
2 0.303 u_EasyCDR_Top/u_easycdr/u_share_logic/rst_n_s0/Q u_EasyCDR_Top/u_easycdr/u_share_logic/delay_cnt_1_s0/CLEAR board_clk:[R] board_clk:[R] 0.000 0.000 0.250
3 0.303 u_EasyCDR_Top/u_easycdr/u_share_logic/rst_n_s0/Q u_EasyCDR_Top/u_easycdr/u_share_logic/delay_cnt_2_s0/CLEAR board_clk:[R] board_clk:[R] 0.000 0.000 0.250
4 0.303 u_EasyCDR_Top/u_easycdr/u_share_logic/rst_n_s0/Q u_EasyCDR_Top/u_easycdr/u_share_logic/delay_cnt_3_s0/CLEAR board_clk:[R] board_clk:[R] 0.000 0.000 0.250
5 0.307 u_EasyCDR_Top/u_easycdr/u_share_logic/rst_n_s0/Q u_EasyCDR_Top/u_easycdr/u_share_logic/cen_s0/PRESET board_clk:[R] board_clk:[R] 0.000 0.004 0.250
6 0.307 u_EasyCDR_Top/u_easycdr/u_share_logic/rst_n_s0/Q u_EasyCDR_Top/u_easycdr/u_share_logic/reset_o_s0/PRESET board_clk:[R] board_clk:[R] 0.000 0.004 0.250
7 0.515 u_EasyCDR_Top/u_easycdr/u_share_logic/rst_n_s0/Q u_EasyCDR_Top/u_easycdr/u_share_logic/resetn_s0/CLEAR board_clk:[R] board_clk:[R] 0.000 -0.019 0.481
8 6.969 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLEAR pclk_rx:[F] pclk_rx:[R] -6.667 0.004 0.245
9 6.969 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLEAR pclk_rx:[F] pclk_rx:[R] -6.667 0.004 0.245
10 7.079 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR pclk_rx:[F] pclk_rx:[R] -6.667 0.000 0.359
11 7.079 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLEAR pclk_rx:[F] pclk_rx:[R] -6.667 0.000 0.359
12 7.079 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLEAR pclk_rx:[F] pclk_rx:[R] -6.667 0.000 0.359
13 7.084 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLEAR pclk_rx:[F] pclk_rx:[R] -6.667 -0.001 0.365
14 7.084 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLEAR pclk_rx:[F] pclk_rx:[R] -6.667 -0.001 0.365
15 7.084 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLEAR pclk_rx:[F] pclk_rx:[R] -6.667 -0.001 0.365
16 7.084 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLEAR pclk_rx:[F] pclk_rx:[R] -6.667 -0.001 0.365
17 7.084 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLEAR pclk_rx:[F] pclk_rx:[R] -6.667 -0.001 0.365
18 7.146 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR pclk_rx:[F] pclk_rx:[R] -6.667 -0.007 0.433
19 7.146 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR pclk_rx:[F] pclk_rx:[R] -6.667 -0.007 0.433
20 7.152 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLEAR pclk_rx:[F] pclk_rx:[R] -6.667 -0.005 0.437
21 7.154 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/triger_s0/CLEAR pclk_rx:[F] pclk_rx:[R] -6.667 0.000 0.434
22 7.156 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR pclk_rx:[F] pclk_rx:[R] -6.667 -0.004 0.440
23 7.156 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR pclk_rx:[F] pclk_rx:[R] -6.667 -0.004 0.440
24 7.156 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLEAR pclk_rx:[F] pclk_rx:[R] -6.667 -0.004 0.440
25 7.156 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/start_reg_s0/CLEAR pclk_rx:[F] pclk_rx:[R] -6.667 -0.004 0.440

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number Slack Actual Width Required Width Type Clock Objects
1 2.257 2.507 0.250 Low Pulse Width pclk_tx u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_0_s0
2 2.257 2.507 0.250 Low Pulse Width pclk_tx u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_tmp_7_s0
3 2.257 2.507 0.250 Low Pulse Width pclk_tx u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_tmp_6_s0
4 2.257 2.507 0.250 Low Pulse Width pclk_tx u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_tmp_5_s0
5 2.257 2.507 0.250 Low Pulse Width pclk_tx u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_7_s2
6 2.257 2.507 0.250 Low Pulse Width pclk_tx u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_6_s1
7 2.257 2.507 0.250 Low Pulse Width pclk_tx u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_0_s1
8 2.257 2.507 0.250 Low Pulse Width pclk_tx u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_8_s0
9 2.257 2.507 0.250 Low Pulse Width pclk_tx u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_5_s1
10 2.257 2.507 0.250 High Pulse Width pclk_tx u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_0_s1

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 4.024
Data Arrival Time 3.896
Data Required Time 7.920
From u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_8_s0
To u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_tmp_5_s0
Launch Clk pclk_tx:[R]
Latch Clk pclk_tx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_tx
0.000 0.000 tCL RR 26 TOPSIDE[1] u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT
1.317 1.317 tNET RR 1 R9C35[3][A] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_8_s0/CLK
1.700 0.382 tC2Q RR 2 R9C35[3][A] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_8_s0/Q
2.436 0.736 tNET RR 1 R11C36[1][A] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_8_cal_5_s0/I0
2.897 0.461 tINS RR 2 R11C36[1][A] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_8_cal_5_s0/F
3.896 0.999 tNET RR 1 R9C35[0][B] u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_tmp_5_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 pclk_tx
6.667 0.000 tCL RR 26 TOPSIDE[1] u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT
7.984 1.317 tNET RR 1 R9C35[0][B] u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_tmp_5_s0/CLK
7.920 -0.064 tSu 1 R9C35[0][B] u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_tmp_5_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 6.667
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.317, 100.000%
Arrival Data Path Delay cell: 0.461, 17.887%; route: 1.735, 67.281%; tC2Q: 0.382, 14.833%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.317, 100.000%

Path2

Path Summary:

Slack 4.081
Data Arrival Time 3.758
Data Required Time 7.839
From u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_1_s1
To u_motivation_response/u_tx_module_top/u_OSER8
Launch Clk pclk_tx:[R]
Latch Clk pclk_tx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_tx
0.000 0.000 tCL RR 26 TOPSIDE[1] u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT
1.303 1.303 tNET RR 1 R11C35[2][B] u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_1_s1/CLK
1.686 0.382 tC2Q RR 1 R11C35[2][B] u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_1_s1/Q
3.758 2.073 tNET RR 1 IOT56[A] u_motivation_response/u_tx_module_top/u_OSER8/D1

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 pclk_tx
6.667 0.000 tCL RR 26 TOPSIDE[1] u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT
8.004 1.337 tNET RR 1 IOT56[A] u_motivation_response/u_tx_module_top/u_OSER8/PCLK
7.839 -0.165 tSu 1 IOT56[A] u_motivation_response/u_tx_module_top/u_OSER8

Path Statistics:

Clock Skew 0.034
Setup Relationship 6.667
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.303, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.073, 84.420%; tC2Q: 0.382, 15.580%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.337, 100.000%

Path3

Path Summary:

Slack 4.205
Data Arrival Time 3.706
Data Required Time 7.911
From u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_8_s0
To u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_tmp_0_s0
Launch Clk pclk_tx:[R]
Latch Clk pclk_tx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_tx
0.000 0.000 tCL RR 26 TOPSIDE[1] u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT
1.317 1.317 tNET RR 1 R9C35[3][A] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_8_s0/CLK
1.700 0.382 tC2Q RR 2 R9C35[3][A] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_8_s0/Q
2.436 0.736 tNET RR 1 R11C36[0][A] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_8_cal_0_s0/I0
2.897 0.461 tINS RR 2 R11C36[0][A] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_8_cal_0_s0/F
3.706 0.809 tNET RR 1 R9C36[0][B] u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_tmp_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 pclk_tx
6.667 0.000 tCL RR 26 TOPSIDE[1] u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT
7.975 1.308 tNET RR 1 R9C36[0][B] u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_tmp_0_s0/CLK
7.911 -0.064 tSu 1 R9C36[0][B] u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_tmp_0_s0

Path Statistics:

Clock Skew -0.009
Setup Relationship 6.667
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.317, 100.000%
Arrival Data Path Delay cell: 0.461, 19.309%; route: 1.545, 64.678%; tC2Q: 0.382, 16.013%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.308, 100.000%

Path4

Path Summary:

Slack 4.358
Data Arrival Time 3.481
Data Required Time 7.839
From u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_5_s1
To u_motivation_response/u_tx_module_top/u_OSER8
Launch Clk pclk_tx:[R]
Latch Clk pclk_tx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_tx
0.000 0.000 tCL RR 26 TOPSIDE[1] u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT
1.317 1.317 tNET RR 1 R9C35[0][A] u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_5_s1/CLK
1.700 0.382 tC2Q RR 1 R9C35[0][A] u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_5_s1/Q
3.481 1.781 tNET RR 1 IOT56[A] u_motivation_response/u_tx_module_top/u_OSER8/D5

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 pclk_tx
6.667 0.000 tCL RR 26 TOPSIDE[1] u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT
8.004 1.337 tNET RR 1 IOT56[A] u_motivation_response/u_tx_module_top/u_OSER8/PCLK
7.839 -0.165 tSu 1 IOT56[A] u_motivation_response/u_tx_module_top/u_OSER8

Path Statistics:

Clock Skew 0.020
Setup Relationship 6.667
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.317, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.781, 82.322%; tC2Q: 0.382, 17.678%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.337, 100.000%

Path5

Path Summary:

Slack 4.404
Data Arrival Time 3.492
Data Required Time 7.897
From u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_4_s0
To u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_3_s0
Launch Clk pclk_tx:[R]
Latch Clk pclk_tx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_tx
0.000 0.000 tCL RR 26 TOPSIDE[1] u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT
1.294 1.294 tNET RR 1 R11C36[2][A] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_4_s0/CLK
1.676 0.382 tC2Q RR 3 R11C36[2][A] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_4_s0/Q
2.222 0.546 tNET RR 1 R9C36[0][A] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_8_cal_4_s0/I0
2.684 0.461 tINS RR 2 R9C36[0][A] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_8_cal_4_s0/F
3.492 0.809 tNET RR 1 R11C36[0][B] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_3_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 pclk_tx
6.667 0.000 tCL RR 26 TOPSIDE[1] u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT
7.960 1.294 tNET RR 1 R11C36[0][B] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_3_s0/CLK
7.897 -0.064 tSu 1 R11C36[0][B] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_3_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 6.667
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.294, 100.000%
Arrival Data Path Delay cell: 0.461, 20.978%; route: 1.355, 61.626%; tC2Q: 0.382, 17.396%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.294, 100.000%

Path6

Path Summary:

Slack 4.440
Data Arrival Time 3.399
Data Required Time 7.839
From u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_7_s2
To u_motivation_response/u_tx_module_top/u_OSER8
Launch Clk pclk_tx:[R]
Latch Clk pclk_tx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_tx
0.000 0.000 tCL RR 26 TOPSIDE[1] u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT
1.317 1.317 tNET RR 1 R9C35[2][A] u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_7_s2/CLK
1.700 0.382 tC2Q RR 1 R9C35[2][A] u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_7_s2/Q
3.399 1.699 tNET RR 1 IOT56[A] u_motivation_response/u_tx_module_top/u_OSER8/D7

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 pclk_tx
6.667 0.000 tCL RR 26 TOPSIDE[1] u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT
8.004 1.337 tNET RR 1 IOT56[A] u_motivation_response/u_tx_module_top/u_OSER8/PCLK
7.839 -0.165 tSu 1 IOT56[A] u_motivation_response/u_tx_module_top/u_OSER8

Path Statistics:

Clock Skew 0.020
Setup Relationship 6.667
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.317, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.699, 81.622%; tC2Q: 0.382, 18.378%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.337, 100.000%

Path7

Path Summary:

Slack 4.458
Data Arrival Time 3.453
Data Required Time 7.911
From u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_2_s0
To u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_tmp_2_s0
Launch Clk pclk_tx:[R]
Latch Clk pclk_tx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_tx
0.000 0.000 tCL RR 26 TOPSIDE[1] u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT
1.303 1.303 tNET RR 1 R11C35[1][B] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_2_s0/CLK
1.686 0.382 tC2Q RR 3 R11C35[1][B] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_2_s0/Q
1.828 0.142 tNET RR 1 R11C35[2][A] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_8_cal_2_s0/I1
2.354 0.526 tINS RR 2 R11C35[2][A] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_8_cal_2_s0/F
3.453 1.099 tNET RR 1 R9C36[1][B] u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_tmp_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 pclk_tx
6.667 0.000 tCL RR 26 TOPSIDE[1] u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT
7.975 1.308 tNET RR 1 R9C36[1][B] u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_tmp_2_s0/CLK
7.911 -0.064 tSu 1 R9C36[1][B] u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_tmp_2_s0

Path Statistics:

Clock Skew 0.005
Setup Relationship 6.667
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.303, 100.000%
Arrival Data Path Delay cell: 0.526, 24.477%; route: 1.241, 57.733%; tC2Q: 0.382, 17.791%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.308, 100.000%

Path8

Path Summary:

Slack 4.470
Data Arrival Time 3.366
Data Required Time 7.836
From u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_0_s1
To u_motivation_response/u_tx_module_top/u_OSER8
Launch Clk pclk_tx:[R]
Latch Clk pclk_tx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_tx
0.000 0.000 tCL RR 26 TOPSIDE[1] u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT
1.317 1.317 tNET RR 1 R9C37[0][B] u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_0_s1/CLK
1.700 0.382 tC2Q RR 1 R9C37[0][B] u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_0_s1/Q
3.366 1.666 tNET RR 1 IOT56[A] u_motivation_response/u_tx_module_top/u_OSER8/D0

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 pclk_tx
6.667 0.000 tCL RR 26 TOPSIDE[1] u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT
8.004 1.337 tNET RR 1 IOT56[A] u_motivation_response/u_tx_module_top/u_OSER8/PCLK
7.836 -0.168 tSu 1 IOT56[A] u_motivation_response/u_tx_module_top/u_OSER8

Path Statistics:

Clock Skew 0.020
Setup Relationship 6.667
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.317, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.666, 81.330%; tC2Q: 0.382, 18.670%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.337, 100.000%

Path9

Path Summary:

Slack 4.497
Data Arrival Time 3.339
Data Required Time 7.836
From u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_6_s1
To u_motivation_response/u_tx_module_top/u_OSER8
Launch Clk pclk_tx:[R]
Latch Clk pclk_tx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_tx
0.000 0.000 tCL RR 26 TOPSIDE[1] u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT
1.317 1.317 tNET RR 1 R9C35[1][A] u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_6_s1/CLK
1.700 0.382 tC2Q RR 1 R9C35[1][A] u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_6_s1/Q
3.339 1.639 tNET RR 1 IOT56[A] u_motivation_response/u_tx_module_top/u_OSER8/D6

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 pclk_tx
6.667 0.000 tCL RR 26 TOPSIDE[1] u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT
8.004 1.337 tNET RR 1 IOT56[A] u_motivation_response/u_tx_module_top/u_OSER8/PCLK
7.836 -0.168 tSu 1 IOT56[A] u_motivation_response/u_tx_module_top/u_OSER8

Path Statistics:

Clock Skew 0.020
Setup Relationship 6.667
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.317, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.639, 81.076%; tC2Q: 0.382, 18.924%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.337, 100.000%

Path10

Path Summary:

Slack 4.526
Data Arrival Time 3.311
Data Required Time 7.836
From u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_4_s1
To u_motivation_response/u_tx_module_top/u_OSER8
Launch Clk pclk_tx:[R]
Latch Clk pclk_tx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_tx
0.000 0.000 tCL RR 26 TOPSIDE[1] u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT
1.308 1.308 tNET RR 1 R9C36[3][A] u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_4_s1/CLK
1.691 0.382 tC2Q RR 1 R9C36[3][A] u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_4_s1/Q
3.311 1.620 tNET RR 1 IOT56[A] u_motivation_response/u_tx_module_top/u_OSER8/D4

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 pclk_tx
6.667 0.000 tCL RR 26 TOPSIDE[1] u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT
8.004 1.337 tNET RR 1 IOT56[A] u_motivation_response/u_tx_module_top/u_OSER8/PCLK
7.836 -0.168 tSu 1 IOT56[A] u_motivation_response/u_tx_module_top/u_OSER8

Path Statistics:

Clock Skew 0.029
Setup Relationship 6.667
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.308, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.620, 80.899%; tC2Q: 0.382, 19.101%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.337, 100.000%

Path11

Path Summary:

Slack 4.551
Data Arrival Time 3.355
Data Required Time 7.906
From u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_8_s0
To u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_2_s0
Launch Clk pclk_tx:[R]
Latch Clk pclk_tx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_tx
0.000 0.000 tCL RR 26 TOPSIDE[1] u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT
1.317 1.317 tNET RR 1 R9C35[3][A] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_8_s0/CLK
1.700 0.382 tC2Q RR 2 R9C35[3][A] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_8_s0/Q
2.436 0.736 tNET RR 1 R11C36[1][A] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_8_cal_5_s0/I0
2.897 0.461 tINS RR 2 R11C36[1][A] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_8_cal_5_s0/F
3.355 0.457 tNET RR 1 R11C35[1][B] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 pclk_tx
6.667 0.000 tCL RR 26 TOPSIDE[1] u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT
7.970 1.303 tNET RR 1 R11C35[1][B] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_2_s0/CLK
7.906 -0.064 tSu 1 R11C35[1][B] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_2_s0

Path Statistics:

Clock Skew -0.014
Setup Relationship 6.667
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.317, 100.000%
Arrival Data Path Delay cell: 0.461, 22.638%; route: 1.194, 58.589%; tC2Q: 0.382, 18.773%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.303, 100.000%

Path12

Path Summary:

Slack 4.611
Data Arrival Time 3.226
Data Required Time 7.836
From u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_2_s1
To u_motivation_response/u_tx_module_top/u_OSER8
Launch Clk pclk_tx:[R]
Latch Clk pclk_tx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_tx
0.000 0.000 tCL RR 26 TOPSIDE[1] u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT
1.308 1.308 tNET RR 1 R9C36[1][A] u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_2_s1/CLK
1.691 0.382 tC2Q RR 1 R9C36[1][A] u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_2_s1/Q
3.226 1.535 tNET RR 1 IOT56[A] u_motivation_response/u_tx_module_top/u_OSER8/D2

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 pclk_tx
6.667 0.000 tCL RR 26 TOPSIDE[1] u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT
8.004 1.337 tNET RR 1 IOT56[A] u_motivation_response/u_tx_module_top/u_OSER8/PCLK
7.836 -0.168 tSu 1 IOT56[A] u_motivation_response/u_tx_module_top/u_OSER8

Path Statistics:

Clock Skew 0.029
Setup Relationship 6.667
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.308, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.535, 80.052%; tC2Q: 0.382, 19.948%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.337, 100.000%

Path13

Path Summary:

Slack 4.614
Data Arrival Time 3.226
Data Required Time 7.839
From u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_3_s1
To u_motivation_response/u_tx_module_top/u_OSER8
Launch Clk pclk_tx:[R]
Latch Clk pclk_tx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_tx
0.000 0.000 tCL RR 26 TOPSIDE[1] u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT
1.308 1.308 tNET RR 1 R9C36[2][A] u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_3_s1/CLK
1.691 0.382 tC2Q RR 1 R9C36[2][A] u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_3_s1/Q
3.226 1.535 tNET RR 1 IOT56[A] u_motivation_response/u_tx_module_top/u_OSER8/D3

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 pclk_tx
6.667 0.000 tCL RR 26 TOPSIDE[1] u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT
8.004 1.337 tNET RR 1 IOT56[A] u_motivation_response/u_tx_module_top/u_OSER8/PCLK
7.839 -0.165 tSu 1 IOT56[A] u_motivation_response/u_tx_module_top/u_OSER8

Path Statistics:

Clock Skew 0.029
Setup Relationship 6.667
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.308, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.535, 80.052%; tC2Q: 0.382, 19.948%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.337, 100.000%

Path14

Path Summary:

Slack 4.619
Data Arrival Time 3.301
Data Required Time 7.920
From u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_7_s0
To u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_tmp_6_s0
Launch Clk pclk_tx:[R]
Latch Clk pclk_tx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_tx
0.000 0.000 tCL RR 26 TOPSIDE[1] u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT
1.294 1.294 tNET RR 1 R11C36[2][B] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_7_s0/CLK
1.676 0.382 tC2Q RR 2 R11C36[2][B] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_7_s0/Q
1.836 0.160 tNET RR 1 R11C35[3][B] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_8_cal_6_s0/I0
2.358 0.521 tINS RR 2 R11C35[3][B] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_8_cal_6_s0/F
3.301 0.944 tNET RR 1 R9C35[1][B] u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_tmp_6_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 pclk_tx
6.667 0.000 tCL RR 26 TOPSIDE[1] u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT
7.984 1.317 tNET RR 1 R9C35[1][B] u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_tmp_6_s0/CLK
7.920 -0.064 tSu 1 R9C35[1][B] u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_tmp_6_s0

Path Statistics:

Clock Skew 0.024
Setup Relationship 6.667
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.294, 100.000%
Arrival Data Path Delay cell: 0.521, 25.965%; route: 1.104, 54.981%; tC2Q: 0.382, 19.054%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.317, 100.000%

Path15

Path Summary:

Slack 4.622
Data Arrival Time 3.298
Data Required Time 7.920
From u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_6_s0
To u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_0_s0
Launch Clk pclk_tx:[R]
Latch Clk pclk_tx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_tx
0.000 0.000 tCL RR 26 TOPSIDE[1] u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT
1.303 1.303 tNET RR 1 R11C35[0][A] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_6_s0/CLK
1.686 0.382 tC2Q RR 2 R11C35[0][A] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_6_s0/Q
1.826 0.140 tNET RR 1 R11C35[0][B] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_8_cal_7_s0/I0
2.352 0.526 tINS RR 2 R11C35[0][B] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_8_cal_7_s0/F
3.298 0.946 tNET RR 1 R9C35[3][B] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 pclk_tx
6.667 0.000 tCL RR 26 TOPSIDE[1] u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT
7.984 1.317 tNET RR 1 R9C35[3][B] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_0_s0/CLK
7.920 -0.064 tSu 1 R9C35[3][B] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_0_s0

Path Statistics:

Clock Skew 0.014
Setup Relationship 6.667
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.303, 100.000%
Arrival Data Path Delay cell: 0.526, 26.378%; route: 1.086, 54.449%; tC2Q: 0.382, 19.173%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.317, 100.000%

Path16

Path Summary:

Slack 4.625
Data Arrival Time 3.296
Data Required Time 7.920
From u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_6_s0
To u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_tmp_7_s0
Launch Clk pclk_tx:[R]
Latch Clk pclk_tx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_tx
0.000 0.000 tCL RR 26 TOPSIDE[1] u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT
1.303 1.303 tNET RR 1 R11C35[0][A] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_6_s0/CLK
1.686 0.382 tC2Q RR 2 R11C35[0][A] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_6_s0/Q
1.826 0.140 tNET RR 1 R11C35[0][B] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_8_cal_7_s0/I0
2.352 0.526 tINS RR 2 R11C35[0][B] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_8_cal_7_s0/F
3.296 0.944 tNET RR 1 R9C35[2][B] u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_tmp_7_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 pclk_tx
6.667 0.000 tCL RR 26 TOPSIDE[1] u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT
7.984 1.317 tNET RR 1 R9C35[2][B] u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_tmp_7_s0/CLK
7.920 -0.064 tSu 1 R9C35[2][B] u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_tmp_7_s0

Path Statistics:

Clock Skew 0.014
Setup Relationship 6.667
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.303, 100.000%
Arrival Data Path Delay cell: 0.526, 26.412%; route: 1.084, 54.391%; tC2Q: 0.382, 19.197%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.317, 100.000%

Path17

Path Summary:

Slack 4.660
Data Arrival Time 3.251
Data Required Time 7.911
From u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_1_s0
To u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_tmp_3_s0
Launch Clk pclk_tx:[R]
Latch Clk pclk_tx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_tx
0.000 0.000 tCL RR 26 TOPSIDE[1] u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT
1.303 1.303 tNET RR 1 R11C35[1][A] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_1_s0/CLK
1.686 0.382 tC2Q RR 2 R11C35[1][A] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_1_s0/Q
1.846 0.160 tNET RR 1 R11C36[1][B] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_8_cal_3_s0/I1
2.307 0.461 tINS RR 2 R11C36[1][B] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_8_cal_3_s0/F
3.251 0.944 tNET RR 1 R9C36[2][B] u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_tmp_3_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 pclk_tx
6.667 0.000 tCL RR 26 TOPSIDE[1] u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT
7.975 1.308 tNET RR 1 R9C36[2][B] u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_tmp_3_s0/CLK
7.911 -0.064 tSu 1 R9C36[2][B] u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_tmp_3_s0

Path Statistics:

Clock Skew 0.005
Setup Relationship 6.667
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.303, 100.000%
Arrival Data Path Delay cell: 0.461, 23.684%; route: 1.104, 56.675%; tC2Q: 0.382, 19.641%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.308, 100.000%

Path18

Path Summary:

Slack 4.732
Data Arrival Time 3.165
Data Required Time 7.897
From u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_8_s0
To u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_7_s0
Launch Clk pclk_tx:[R]
Latch Clk pclk_tx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_tx
0.000 0.000 tCL RR 26 TOPSIDE[1] u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT
1.317 1.317 tNET RR 1 R9C35[3][A] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_8_s0/CLK
1.700 0.382 tC2Q RR 2 R9C35[3][A] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_8_s0/Q
2.436 0.736 tNET RR 1 R11C36[0][A] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_8_cal_0_s0/I0
2.897 0.461 tINS RR 2 R11C36[0][A] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_8_cal_0_s0/F
3.165 0.267 tNET RR 1 R11C36[2][B] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_7_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 pclk_tx
6.667 0.000 tCL RR 26 TOPSIDE[1] u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT
7.960 1.294 tNET RR 1 R11C36[2][B] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_7_s0/CLK
7.897 -0.064 tSu 1 R11C36[2][B] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_7_s0

Path Statistics:

Clock Skew -0.024
Setup Relationship 6.667
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.317, 100.000%
Arrival Data Path Delay cell: 0.461, 24.966%; route: 1.004, 54.330%; tC2Q: 0.382, 20.704%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.294, 100.000%

Path19

Path Summary:

Slack 4.779
Data Arrival Time 3.127
Data Required Time 7.906
From u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_2_s0
To u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_5_s0
Launch Clk pclk_tx:[R]
Latch Clk pclk_tx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_tx
0.000 0.000 tCL RR 26 TOPSIDE[1] u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT
1.303 1.303 tNET RR 1 R11C35[1][B] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_2_s0/CLK
1.686 0.382 tC2Q RR 3 R11C35[1][B] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_2_s0/Q
1.828 0.142 tNET RR 1 R11C35[2][A] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_8_cal_2_s0/I1
2.354 0.526 tINS RR 2 R11C35[2][A] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_8_cal_2_s0/F
3.127 0.772 tNET RR 1 R11C37[0][A] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_5_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 pclk_tx
6.667 0.000 tCL RR 26 TOPSIDE[1] u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT
7.970 1.303 tNET RR 1 R11C37[0][A] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_5_s0/CLK
7.906 -0.064 tSu 1 R11C37[0][A] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_5_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 6.667
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.303, 100.000%
Arrival Data Path Delay cell: 0.526, 28.855%; route: 0.915, 50.171%; tC2Q: 0.382, 20.973%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.303, 100.000%

Path20

Path Summary:

Slack 4.957
Data Arrival Time 2.954
Data Required Time 7.911
From u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_4_s0
To u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_tmp_4_s0
Launch Clk pclk_tx:[R]
Latch Clk pclk_tx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_tx
0.000 0.000 tCL RR 26 TOPSIDE[1] u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT
1.294 1.294 tNET RR 1 R11C36[2][A] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_4_s0/CLK
1.676 0.382 tC2Q RR 3 R11C36[2][A] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_4_s0/Q
2.222 0.546 tNET RR 1 R9C36[0][A] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_8_cal_4_s0/I0
2.684 0.461 tINS RR 2 R9C36[0][A] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_8_cal_4_s0/F
2.954 0.270 tNET RR 1 R9C36[3][B] u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_tmp_4_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 pclk_tx
6.667 0.000 tCL RR 26 TOPSIDE[1] u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT
7.975 1.308 tNET RR 1 R9C36[3][B] u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_tmp_4_s0/CLK
7.911 -0.064 tSu 1 R9C36[3][B] u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_tmp_4_s0

Path Statistics:

Clock Skew 0.014
Setup Relationship 6.667
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.294, 100.000%
Arrival Data Path Delay cell: 0.461, 27.786%; route: 0.816, 49.172%; tC2Q: 0.382, 23.042%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.308, 100.000%

Path21

Path Summary:

Slack 5.144
Data Arrival Time 2.762
Data Required Time 7.906
From u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_7_s0
To u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_tmp_1_s0
Launch Clk pclk_tx:[R]
Latch Clk pclk_tx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_tx
0.000 0.000 tCL RR 26 TOPSIDE[1] u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT
1.294 1.294 tNET RR 1 R11C36[2][B] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_7_s0/CLK
1.676 0.382 tC2Q RR 2 R11C36[2][B] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_7_s0/Q
1.816 0.140 tNET RR 1 R11C36[3][A] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_8_cal_1_s0/I0
2.338 0.521 tINS RR 2 R11C36[3][A] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_8_cal_1_s0/F
2.763 0.425 tNET RR 1 R11C35[3][A] u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_tmp_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 pclk_tx
6.667 0.000 tCL RR 26 TOPSIDE[1] u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT
7.970 1.303 tNET RR 1 R11C35[3][A] u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_tmp_1_s0/CLK
7.906 -0.064 tSu 1 R11C35[3][A] u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_tmp_1_s0

Path Statistics:

Clock Skew 0.009
Setup Relationship 6.667
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.294, 100.000%
Arrival Data Path Delay cell: 0.521, 35.489%; route: 0.565, 38.468%; tC2Q: 0.382, 26.043%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.303, 100.000%

Path22

Path Summary:

Slack 5.146
Data Arrival Time 2.760
Data Required Time 7.906
From u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_7_s0
To u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_1_s0
Launch Clk pclk_tx:[R]
Latch Clk pclk_tx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_tx
0.000 0.000 tCL RR 26 TOPSIDE[1] u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT
1.294 1.294 tNET RR 1 R11C36[2][B] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_7_s0/CLK
1.676 0.382 tC2Q RR 2 R11C36[2][B] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_7_s0/Q
1.836 0.160 tNET RR 1 R11C35[3][B] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_8_cal_6_s0/I0
2.358 0.521 tINS RR 2 R11C35[3][B] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_8_cal_6_s0/F
2.760 0.402 tNET RR 1 R11C35[1][A] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 pclk_tx
6.667 0.000 tCL RR 26 TOPSIDE[1] u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT
7.970 1.303 tNET RR 1 R11C35[1][A] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_1_s0/CLK
7.906 -0.064 tSu 1 R11C35[1][A] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_1_s0

Path Statistics:

Clock Skew 0.009
Setup Relationship 6.667
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.294, 100.000%
Arrival Data Path Delay cell: 0.521, 35.550%; route: 0.562, 38.363%; tC2Q: 0.382, 26.087%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.303, 100.000%

Path23

Path Summary:

Slack 5.146
Data Arrival Time 2.760
Data Required Time 7.906
From u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_7_s0
To u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_6_s0
Launch Clk pclk_tx:[R]
Latch Clk pclk_tx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_tx
0.000 0.000 tCL RR 26 TOPSIDE[1] u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT
1.294 1.294 tNET RR 1 R11C36[2][B] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_7_s0/CLK
1.676 0.382 tC2Q RR 2 R11C36[2][B] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_7_s0/Q
1.816 0.140 tNET RR 1 R11C36[3][A] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_8_cal_1_s0/I0
2.338 0.521 tINS RR 2 R11C36[3][A] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_8_cal_1_s0/F
2.760 0.422 tNET RR 1 R11C35[0][A] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_6_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 pclk_tx
6.667 0.000 tCL RR 26 TOPSIDE[1] u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT
7.970 1.303 tNET RR 1 R11C35[0][A] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_6_s0/CLK
7.906 -0.064 tSu 1 R11C35[0][A] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_6_s0

Path Statistics:

Clock Skew 0.009
Setup Relationship 6.667
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.294, 100.000%
Arrival Data Path Delay cell: 0.521, 35.550%; route: 0.562, 38.363%; tC2Q: 0.382, 26.087%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.303, 100.000%

Path24

Path Summary:

Slack 5.187
Data Arrival Time 2.709
Data Required Time 7.897
From u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_1_s0
To u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_4_s0
Launch Clk pclk_tx:[R]
Latch Clk pclk_tx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_tx
0.000 0.000 tCL RR 26 TOPSIDE[1] u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT
1.303 1.303 tNET RR 1 R11C35[1][A] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_1_s0/CLK
1.686 0.382 tC2Q RR 2 R11C35[1][A] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_1_s0/Q
1.846 0.160 tNET RR 1 R11C36[1][B] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_8_cal_3_s0/I1
2.307 0.461 tINS RR 2 R11C36[1][B] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_8_cal_3_s0/F
2.709 0.402 tNET RR 1 R11C36[2][A] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_4_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 pclk_tx
6.667 0.000 tCL RR 26 TOPSIDE[1] u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT
7.960 1.294 tNET RR 1 R11C36[2][A] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_4_s0/CLK
7.897 -0.064 tSu 1 R11C36[2][A] u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_4_s0

Path Statistics:

Clock Skew -0.009
Setup Relationship 6.667
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.303, 100.000%
Arrival Data Path Delay cell: 0.461, 32.800%; route: 0.562, 40.000%; tC2Q: 0.382, 27.200%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.294, 100.000%

Path25

Path Summary:

Slack 5.658
Data Arrival Time 8.931
Data Required Time 14.589
From u_EasyCDR_Top/u_easycdr/u_easycdr_64/u_gearbox_15_16_17_to_20/remained_cnt_1_s1
To u_EasyCDR_Top/u_easycdr/u_easycdr_64/u_gearbox_15_16_17_to_20/o_dout_6_s0
Launch Clk pclk_rx:[R]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
1.334 1.334 tNET RR 1 R24C20[2][A] u_EasyCDR_Top/u_easycdr/u_easycdr_64/u_gearbox_15_16_17_to_20/remained_cnt_1_s1/CLK
1.702 0.368 tC2Q RF 105 R24C20[2][A] u_EasyCDR_Top/u_easycdr/u_easycdr_64/u_gearbox_15_16_17_to_20/remained_cnt_1_s1/Q
4.008 2.307 tNET FF 1 R18C27[1][A] u_EasyCDR_Top/u_easycdr/u_easycdr_64/u_gearbox_15_16_17_to_20/n351_s11/I2
4.525 0.516 tINS FR 4 R18C27[1][A] u_EasyCDR_Top/u_easycdr/u_easycdr_64/u_gearbox_15_16_17_to_20/n351_s11/F
5.067 0.542 tNET RR 1 R18C22[1][B] u_EasyCDR_Top/u_easycdr/u_easycdr_64/u_gearbox_15_16_17_to_20/n349_s18/I1
5.593 0.526 tINS RR 1 R18C22[1][B] u_EasyCDR_Top/u_easycdr/u_easycdr_64/u_gearbox_15_16_17_to_20/n349_s18/F
6.326 0.733 tNET RR 1 R21C22[3][A] u_EasyCDR_Top/u_easycdr/u_easycdr_64/u_gearbox_15_16_17_to_20/n349_s10/I3
6.591 0.265 tINS RR 2 R21C22[3][A] u_EasyCDR_Top/u_easycdr/u_easycdr_64/u_gearbox_15_16_17_to_20/n349_s10/F
7.156 0.565 tNET RR 1 R20C19[0][A] u_EasyCDR_Top/u_easycdr/u_easycdr_64/u_gearbox_15_16_17_to_20/n350_s1/I1
7.682 0.526 tINS RR 1 R20C19[0][A] u_EasyCDR_Top/u_easycdr/u_easycdr_64/u_gearbox_15_16_17_to_20/n350_s1/F
8.415 0.733 tNET RR 1 R18C19[0][A] u_EasyCDR_Top/u_easycdr/u_easycdr_64/u_gearbox_15_16_17_to_20/n350_s0/I0
8.931 0.516 tINS RR 1 R18C19[0][A] u_EasyCDR_Top/u_easycdr/u_easycdr_64/u_gearbox_15_16_17_to_20/n350_s0/F
8.931 0.000 tNET RR 1 R18C19[0][A] u_EasyCDR_Top/u_easycdr/u_easycdr_64/u_gearbox_15_16_17_to_20/o_dout_6_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.333 13.333 active clock edge time
13.333 0.000 pclk_rx
13.333 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
14.653 1.319 tNET RR 1 R18C19[0][A] u_EasyCDR_Top/u_easycdr/u_easycdr_64/u_gearbox_15_16_17_to_20/o_dout_6_s0/CLK
14.589 -0.064 tSu 1 R18C19[0][A] u_EasyCDR_Top/u_easycdr/u_easycdr_64/u_gearbox_15_16_17_to_20/o_dout_6_s0

Path Statistics:

Clock Skew -0.015
Setup Relationship 13.333
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.334, 100.000%
Arrival Data Path Delay cell: 2.350, 30.935%; route: 4.879, 64.227%; tC2Q: 0.368, 4.838%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.319, 100.000%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 0.100
Data Arrival Time 0.835
Data Required Time 0.735
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_23_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk pclk_rx:[R]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.500 0.500 tNET RR 1 R23C34[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_23_s0/CLK
0.644 0.144 tC2Q RR 1 R23C34[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_23_s0/Q
0.835 0.191 tNET RR 1 BSRAM_R28[10] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[7]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.486 0.486 tNET RR 1 BSRAM_R28[10] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
0.735 0.249 tHld 1 BSRAM_R28[10] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew -0.014
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.500, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.191, 57.015%; tC2Q: 0.144, 42.985%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.486, 100.000%

Path2

Path Summary:

Slack 0.104
Data Arrival Time 0.835
Data Required Time 0.731
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_0_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk pclk_rx:[R]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.500 0.500 tNET RR 1 R23C34[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_0_s0/CLK
0.644 0.144 tC2Q RR 1 R23C34[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_0_s0/Q
0.835 0.191 tNET RR 1 BSRAM_R28[9] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[0]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.482 0.482 tNET RR 1 BSRAM_R28[9] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
0.731 0.249 tHld 1 BSRAM_R28[9] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew -0.018
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.500, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.191, 57.015%; tC2Q: 0.144, 42.985%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.482, 100.000%

Path3

Path Summary:

Slack 0.108
Data Arrival Time 0.839
Data Required Time 0.731
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_4_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk pclk_rx:[R]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.498 0.498 tNET RR 1 R22C33[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_4_s0/CLK
0.642 0.144 tC2Q RR 1 R22C33[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_4_s0/Q
0.839 0.197 tNET RR 1 BSRAM_R28[9] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[4]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.482 0.482 tNET RR 1 BSRAM_R28[9] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
0.731 0.249 tHld 1 BSRAM_R28[9] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew -0.016
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.498, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.197, 57.771%; tC2Q: 0.144, 42.229%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.482, 100.000%

Path4

Path Summary:

Slack 0.108
Data Arrival Time 0.839
Data Required Time 0.731
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_3_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk pclk_rx:[R]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.498 0.498 tNET RR 1 R22C33[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_3_s0/CLK
0.642 0.144 tC2Q RR 1 R22C33[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_3_s0/Q
0.839 0.197 tNET RR 1 BSRAM_R28[9] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[3]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.482 0.482 tNET RR 1 BSRAM_R28[9] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
0.731 0.249 tHld 1 BSRAM_R28[9] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew -0.016
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.498, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.197, 57.771%; tC2Q: 0.144, 42.229%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.482, 100.000%

Path5

Path Summary:

Slack 0.150
Data Arrival Time 0.881
Data Required Time 0.731
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_2_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk pclk_rx:[R]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.500 0.500 tNET RR 1 R23C34[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_2_s0/CLK
0.644 0.144 tC2Q RR 1 R23C34[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_2_s0/Q
0.881 0.237 tNET RR 1 BSRAM_R28[9] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[2]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.482 0.482 tNET RR 1 BSRAM_R28[9] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
0.731 0.249 tHld 1 BSRAM_R28[9] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew -0.018
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.500, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.237, 62.205%; tC2Q: 0.144, 37.795%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.482, 100.000%

Path6

Path Summary:

Slack 0.155
Data Arrival Time 0.890
Data Required Time 0.735
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_18_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk pclk_rx:[R]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.502 0.502 tNET RR 1 R20C33[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_18_s0/CLK
0.646 0.144 tC2Q RR 1 R20C33[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_18_s0/Q
0.890 0.244 tNET RR 1 BSRAM_R28[10] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[2]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.486 0.486 tNET RR 1 BSRAM_R28[10] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
0.735 0.249 tHld 1 BSRAM_R28[10] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew -0.016
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.502, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.244, 62.887%; tC2Q: 0.144, 37.113%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.486, 100.000%

Path7

Path Summary:

Slack 0.155
Data Arrival Time 0.890
Data Required Time 0.735
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_17_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk pclk_rx:[R]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.502 0.502 tNET RR 1 R20C33[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_17_s0/CLK
0.646 0.144 tC2Q RR 1 R20C33[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_17_s0/Q
0.890 0.244 tNET RR 1 BSRAM_R28[10] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[1]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.486 0.486 tNET RR 1 BSRAM_R28[10] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
0.735 0.249 tHld 1 BSRAM_R28[10] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew -0.016
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.502, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.244, 62.887%; tC2Q: 0.144, 37.113%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.486, 100.000%

Path8

Path Summary:

Slack 0.159
Data Arrival Time 0.894
Data Required Time 0.735
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_20_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk pclk_rx:[R]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.506 0.506 tNET RR 1 R20C34[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_20_s0/CLK
0.650 0.144 tC2Q RR 1 R20C34[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_20_s0/Q
0.894 0.244 tNET RR 1 BSRAM_R28[10] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[4]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.486 0.486 tNET RR 1 BSRAM_R28[10] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
0.735 0.249 tHld 1 BSRAM_R28[10] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew -0.020
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.506, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.244, 62.887%; tC2Q: 0.144, 37.113%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.486, 100.000%

Path9

Path Summary:

Slack 0.209
Data Arrival Time 0.940
Data Required Time 0.731
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_8_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk pclk_rx:[R]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.502 0.502 tNET RR 1 R22C34[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_8_s0/CLK
0.646 0.144 tC2Q RR 1 R22C34[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_8_s0/Q
0.940 0.294 tNET RR 1 BSRAM_R28[9] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[8]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.482 0.482 tNET RR 1 BSRAM_R28[9] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
0.731 0.249 tHld 1 BSRAM_R28[9] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew -0.020
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.502, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.294, 67.123%; tC2Q: 0.144, 32.877%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.482, 100.000%

Path10

Path Summary:

Slack 0.230
Data Arrival Time 0.965
Data Required Time 0.735
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_19_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk pclk_rx:[R]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.502 0.502 tNET RR 1 R20C33[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_19_s0/CLK
0.646 0.144 tC2Q RR 1 R20C33[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_19_s0/Q
0.965 0.319 tNET RR 1 BSRAM_R28[10] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[3]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.486 0.486 tNET RR 1 BSRAM_R28[10] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
0.735 0.249 tHld 1 BSRAM_R28[10] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew -0.016
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.502, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.319, 68.898%; tC2Q: 0.144, 31.102%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.486, 100.000%

Path11

Path Summary:

Slack 0.234
Data Arrival Time 0.969
Data Required Time 0.735
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_22_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk pclk_rx:[R]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.506 0.506 tNET RR 1 R20C34[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_22_s0/CLK
0.650 0.144 tC2Q RR 1 R20C34[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_22_s0/Q
0.969 0.319 tNET RR 1 BSRAM_R28[10] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[6]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.486 0.486 tNET RR 1 BSRAM_R28[10] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
0.735 0.249 tHld 1 BSRAM_R28[10] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew -0.020
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.506, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.319, 68.898%; tC2Q: 0.144, 31.102%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.486, 100.000%

Path12

Path Summary:

Slack 0.251
Data Arrival Time 0.982
Data Required Time 0.731
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_14_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk pclk_rx:[R]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.504 0.504 tNET RR 1 R21C34[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_14_s0/CLK
0.648 0.144 tC2Q RR 1 R21C34[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_14_s0/Q
0.982 0.334 tNET RR 1 BSRAM_R28[9] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[14]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.482 0.482 tNET RR 1 BSRAM_R28[9] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
0.731 0.249 tHld 1 BSRAM_R28[9] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew -0.022
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.504, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.334, 69.874%; tC2Q: 0.144, 30.126%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.482, 100.000%

Path13

Path Summary:

Slack 0.275
Data Arrival Time 0.777
Data Required Time 0.502
From u_motivation_response/u_prbs_inspector/dat_corr_cnt_3_s1
To u_motivation_response/u_prbs_inspector/dat_corr_cnt_3_s1
Launch Clk pclk_rx:[R]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.477 0.477 tNET RR 1 R11C34[0][A] u_motivation_response/u_prbs_inspector/dat_corr_cnt_3_s1/CLK
0.618 0.141 tC2Q RF 4 R11C34[0][A] u_motivation_response/u_prbs_inspector/dat_corr_cnt_3_s1/Q
0.624 0.006 tNET FF 1 R11C34[0][A] u_motivation_response/u_prbs_inspector/n167_s1/I2
0.777 0.153 tINS FF 1 R11C34[0][A] u_motivation_response/u_prbs_inspector/n167_s1/F
0.777 0.000 tNET FF 1 R11C34[0][A] u_motivation_response/u_prbs_inspector/dat_corr_cnt_3_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.477 0.477 tNET RR 1 R11C34[0][A] u_motivation_response/u_prbs_inspector/dat_corr_cnt_3_s1/CLK
0.502 0.025 tHld 1 R11C34[0][A] u_motivation_response/u_prbs_inspector/dat_corr_cnt_3_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.477, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.477, 100.000%

Path14

Path Summary:

Slack 0.275
Data Arrival Time 0.805
Data Required Time 0.530
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1
Launch Clk pclk_rx:[R]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.505 0.505 tNET RR 1 R23C31[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLK
0.646 0.141 tC2Q RF 3 R23C31[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/Q
0.652 0.006 tNET FF 1 R23C31[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n233_s0/I1
0.805 0.153 tINS FF 1 R23C31[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n233_s0/F
0.805 0.000 tNET FF 1 R23C31[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.505 0.505 tNET RR 1 R23C31[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLK
0.530 0.025 tHld 1 R23C31[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.505, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.505, 100.000%

Path15

Path Summary:

Slack 0.275
Data Arrival Time 1.465
Data Required Time 1.190
From u_EasyCDR_Top/u_easycdr/u_share_logic/delay_cnt_1_s0
To u_EasyCDR_Top/u_easycdr/u_share_logic/delay_cnt_1_s0
Launch Clk board_clk:[R]
Latch Clk board_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 board_clk
0.000 0.000 tCL RR 1 IOB29[A] gowin_ibuf_board_clk/I
0.675 0.675 tINS RR 12 IOB29[A] gowin_ibuf_board_clk/O
1.165 0.490 tNET RR 1 R9C28[1][A] u_EasyCDR_Top/u_easycdr/u_share_logic/delay_cnt_1_s0/CLK
1.306 0.141 tC2Q RF 4 R9C28[1][A] u_EasyCDR_Top/u_easycdr/u_share_logic/delay_cnt_1_s0/Q
1.312 0.006 tNET FF 1 R9C28[1][A] u_EasyCDR_Top/u_easycdr/u_share_logic/n24_s1/I1
1.465 0.153 tINS FF 1 R9C28[1][A] u_EasyCDR_Top/u_easycdr/u_share_logic/n24_s1/F
1.465 0.000 tNET FF 1 R9C28[1][A] u_EasyCDR_Top/u_easycdr/u_share_logic/delay_cnt_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 board_clk
0.000 0.000 tCL RR 1 IOB29[A] gowin_ibuf_board_clk/I
0.675 0.675 tINS RR 12 IOB29[A] gowin_ibuf_board_clk/O
1.165 0.490 tNET RR 1 R9C28[1][A] u_EasyCDR_Top/u_easycdr/u_share_logic/delay_cnt_1_s0/CLK
1.190 0.025 tHld 1 R9C28[1][A] u_EasyCDR_Top/u_easycdr/u_share_logic/delay_cnt_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.675, 57.958%; route: 0.490, 42.042%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.675, 57.958%; route: 0.490, 42.042%

Path16

Path Summary:

Slack 0.275
Data Arrival Time 2.591
Data Required Time 2.316
From gw_gao_inst_0/u_la0_top/word_count_7_s0
To gw_gao_inst_0/u_la0_top/word_count_7_s0
Launch Clk tck_pad:[R]
Latch Clk tck_pad:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 234 - gw_gao_inst_0/u_gw_jtag/tck_o
2.291 0.940 tNET RR 1 R13C37[0][A] gw_gao_inst_0/u_la0_top/word_count_7_s0/CLK
2.432 0.141 tC2Q RF 4 R13C37[0][A] gw_gao_inst_0/u_la0_top/word_count_7_s0/Q
2.438 0.006 tNET FF 1 R13C37[0][A] gw_gao_inst_0/u_la0_top/data_to_word_counter_7_s0/I1
2.591 0.153 tINS FF 1 R13C37[0][A] gw_gao_inst_0/u_la0_top/data_to_word_counter_7_s0/F
2.591 0.000 tNET FF 1 R13C37[0][A] gw_gao_inst_0/u_la0_top/word_count_7_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 234 - gw_gao_inst_0/u_gw_jtag/tck_o
2.291 0.940 tNET RR 1 R13C37[0][A] gw_gao_inst_0/u_la0_top/word_count_7_s0/CLK
2.316 0.025 tHld 1 R13C37[0][A] gw_gao_inst_0/u_la0_top/word_count_7_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.351, 58.970%; route: 0.940, 41.030%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 1.351, 58.970%; route: 0.940, 41.030%

Path17

Path Summary:

Slack 0.278
Data Arrival Time 2.598
Data Required Time 2.320
From gw_gao_inst_0/u_la0_top/word_count_0_s0
To gw_gao_inst_0/u_la0_top/word_count_0_s0
Launch Clk tck_pad:[R]
Latch Clk tck_pad:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 234 - gw_gao_inst_0/u_gw_jtag/tck_o
2.295 0.944 tNET RR 1 R15C38[0][A] gw_gao_inst_0/u_la0_top/word_count_0_s0/CLK
2.436 0.141 tC2Q RF 5 R15C38[0][A] gw_gao_inst_0/u_la0_top/word_count_0_s0/Q
2.445 0.009 tNET FF 1 R15C38[0][A] gw_gao_inst_0/u_la0_top/data_to_word_counter_0_s1/I1
2.598 0.153 tINS FF 1 R15C38[0][A] gw_gao_inst_0/u_la0_top/data_to_word_counter_0_s1/F
2.598 0.000 tNET FF 1 R15C38[0][A] gw_gao_inst_0/u_la0_top/word_count_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 234 - gw_gao_inst_0/u_gw_jtag/tck_o
2.295 0.944 tNET RR 1 R15C38[0][A] gw_gao_inst_0/u_la0_top/word_count_0_s0/CLK
2.320 0.025 tHld 1 R15C38[0][A] gw_gao_inst_0/u_la0_top/word_count_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.351, 58.867%; route: 0.944, 41.133%
Arrival Data Path Delay cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay cell: 1.351, 58.867%; route: 0.944, 41.133%

Path18

Path Summary:

Slack 0.278
Data Arrival Time 2.598
Data Required Time 2.320
From gw_gao_inst_0/u_la0_top/word_count_4_s0
To gw_gao_inst_0/u_la0_top/word_count_4_s0
Launch Clk tck_pad:[R]
Latch Clk tck_pad:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 234 - gw_gao_inst_0/u_gw_jtag/tck_o
2.295 0.944 tNET RR 1 R14C35[1][A] gw_gao_inst_0/u_la0_top/word_count_4_s0/CLK
2.436 0.141 tC2Q RF 6 R14C35[1][A] gw_gao_inst_0/u_la0_top/word_count_4_s0/Q
2.445 0.009 tNET FF 1 R14C35[1][A] gw_gao_inst_0/u_la0_top/data_to_word_counter_4_s0/I1
2.598 0.153 tINS FF 1 R14C35[1][A] gw_gao_inst_0/u_la0_top/data_to_word_counter_4_s0/F
2.598 0.000 tNET FF 1 R14C35[1][A] gw_gao_inst_0/u_la0_top/word_count_4_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 234 - gw_gao_inst_0/u_gw_jtag/tck_o
2.295 0.944 tNET RR 1 R14C35[1][A] gw_gao_inst_0/u_la0_top/word_count_4_s0/CLK
2.320 0.025 tHld 1 R14C35[1][A] gw_gao_inst_0/u_la0_top/word_count_4_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.351, 58.867%; route: 0.944, 41.133%
Arrival Data Path Delay cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay cell: 1.351, 58.867%; route: 0.944, 41.133%

Path19

Path Summary:

Slack 0.278
Data Arrival Time 2.594
Data Required Time 2.316
From gw_gao_inst_0/u_la0_top/word_count_10_s0
To gw_gao_inst_0/u_la0_top/word_count_10_s0
Launch Clk tck_pad:[R]
Latch Clk tck_pad:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 234 - gw_gao_inst_0/u_gw_jtag/tck_o
2.291 0.940 tNET RR 1 R14C38[1][A] gw_gao_inst_0/u_la0_top/word_count_10_s0/CLK
2.432 0.141 tC2Q RF 3 R14C38[1][A] gw_gao_inst_0/u_la0_top/word_count_10_s0/Q
2.441 0.009 tNET FF 1 R14C38[1][A] gw_gao_inst_0/u_la0_top/data_to_word_counter_10_s0/I1
2.594 0.153 tINS FF 1 R14C38[1][A] gw_gao_inst_0/u_la0_top/data_to_word_counter_10_s0/F
2.594 0.000 tNET FF 1 R14C38[1][A] gw_gao_inst_0/u_la0_top/word_count_10_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 234 - gw_gao_inst_0/u_gw_jtag/tck_o
2.291 0.940 tNET RR 1 R14C38[1][A] gw_gao_inst_0/u_la0_top/word_count_10_s0/CLK
2.316 0.025 tHld 1 R14C38[1][A] gw_gao_inst_0/u_la0_top/word_count_10_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.351, 58.970%; route: 0.940, 41.030%
Arrival Data Path Delay cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay cell: 1.351, 58.970%; route: 0.940, 41.030%

Path20

Path Summary:

Slack 0.278
Data Arrival Time 0.799
Data Required Time 0.521
From gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1
To gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1
Launch Clk pclk_rx:[R]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.496 0.496 tNET RR 1 R26C31[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLK
0.637 0.141 tC2Q RF 12 R26C31[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/Q
0.646 0.009 tNET FF 1 R26C31[1][A] gw_gao_inst_0/u_la0_top/n2044_s1/I0
0.799 0.153 tINS FF 1 R26C31[1][A] gw_gao_inst_0/u_la0_top/n2044_s1/F
0.799 0.000 tNET FF 1 R26C31[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.496 0.496 tNET RR 1 R26C31[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLK
0.521 0.025 tHld 1 R26C31[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.496, 100.000%
Arrival Data Path Delay cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.496, 100.000%

Path21

Path Summary:

Slack 0.278
Data Arrival Time 0.800
Data Required Time 0.522
From gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1
To gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1
Launch Clk pclk_rx:[R]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.497 0.497 tNET RR 1 R25C32[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLK
0.638 0.141 tC2Q RF 6 R25C32[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/Q
0.647 0.009 tNET FF 1 R25C32[1][A] gw_gao_inst_0/u_la0_top/n2039_s1/I0
0.800 0.153 tINS FF 1 R25C32[1][A] gw_gao_inst_0/u_la0_top/n2039_s1/F
0.800 0.000 tNET FF 1 R25C32[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.497 0.497 tNET RR 1 R25C32[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLK
0.522 0.025 tHld 1 R25C32[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.497, 100.000%
Arrival Data Path Delay cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.497, 100.000%

Path22

Path Summary:

Slack 0.278
Data Arrival Time 0.796
Data Required Time 0.518
From gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1
To gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1
Launch Clk pclk_rx:[R]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.493 0.493 tNET RR 1 R25C33[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLK
0.634 0.141 tC2Q RF 3 R25C33[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/Q
0.643 0.009 tNET FF 1 R25C33[0][A] gw_gao_inst_0/u_la0_top/n2037_s1/I0
0.796 0.153 tINS FF 1 R25C33[0][A] gw_gao_inst_0/u_la0_top/n2037_s1/F
0.796 0.000 tNET FF 1 R25C33[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.493 0.493 tNET RR 1 R25C33[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLK
0.518 0.025 tHld 1 R25C33[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.493, 100.000%
Arrival Data Path Delay cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.493, 100.000%

Path23

Path Summary:

Slack 0.278
Data Arrival Time 0.809
Data Required Time 0.531
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
Launch Clk pclk_rx:[R]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.506 0.506 tNET RR 1 R22C31[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK
0.647 0.141 tC2Q RF 6 R22C31[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/Q
0.656 0.009 tNET FF 1 R22C31[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n329_s1/I1
0.809 0.153 tINS FF 1 R22C31[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n329_s1/F
0.809 0.000 tNET FF 1 R22C31[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.506 0.506 tNET RR 1 R22C31[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK
0.531 0.025 tHld 1 R22C31[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.506, 100.000%
Arrival Data Path Delay cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.506, 100.000%

Path24

Path Summary:

Slack 0.278
Data Arrival Time 0.805
Data Required Time 0.527
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
Launch Clk pclk_rx:[R]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.502 0.502 tNET RR 1 R22C30[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK
0.643 0.141 tC2Q RF 6 R22C30[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/Q
0.652 0.009 tNET FF 1 R22C30[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n328_s1/I1
0.805 0.153 tINS FF 1 R22C30[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n328_s1/F
0.805 0.000 tNET FF 1 R22C30[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.502 0.502 tNET RR 1 R22C30[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK
0.527 0.025 tHld 1 R22C30[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.502, 100.000%
Arrival Data Path Delay cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.502, 100.000%

Path25

Path Summary:

Slack 0.278
Data Arrival Time 0.803
Data Required Time 0.525
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1
Launch Clk pclk_rx:[R]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.500 0.500 tNET RR 1 R23C30[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLK
0.641 0.141 tC2Q RF 4 R23C30[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/Q
0.650 0.009 tNET FF 1 R23C30[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s0/I1
0.803 0.153 tINS FF 1 R23C30[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s0/F
0.803 0.000 tNET FF 1 R23C30[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.500 0.500 tNET RR 1 R23C30[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLK
0.525 0.025 tHld 1 R23C30[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.500, 100.000%
Arrival Data Path Delay cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.500, 100.000%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 3.595
Data Arrival Time 10.689
Data Required Time 14.285
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 pclk_rx
6.667 0.000 tCL FF 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
7.978 1.312 tNET FF 1 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.421 0.442 tC2Q FF 58 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
10.689 2.269 tNET FF 1 R17C29[0][A] gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.333 13.333 active clock edge time
13.333 0.000 pclk_rx
13.333 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
14.632 1.299 tNET RR 1 R17C29[0][A] gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLK
14.285 -0.347 tSu 1 R17C29[0][A] gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0

Path Statistics:

Clock Skew -0.013
Setup Relationship 6.667
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.312, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.269, 83.679%; tC2Q: 0.442, 16.321%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.299, 100.000%

Path2

Path Summary:

Slack 3.732
Data Arrival Time 10.562
Data Required Time 14.294
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 pclk_rx
6.667 0.000 tCL FF 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
7.978 1.312 tNET FF 1 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.421 0.442 tC2Q FF 58 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
10.562 2.141 tNET FF 1 R17C30[2][A] gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.333 13.333 active clock edge time
13.333 0.000 pclk_rx
13.333 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
14.641 1.308 tNET RR 1 R17C30[2][A] gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLK
14.294 -0.347 tSu 1 R17C30[2][A] gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0

Path Statistics:

Clock Skew -0.003
Setup Relationship 6.667
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.312, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.141, 82.874%; tC2Q: 0.442, 17.126%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.308, 100.000%

Path3

Path Summary:

Slack 3.781
Data Arrival Time 10.506
Data Required Time 14.286
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s1
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 pclk_rx
6.667 0.000 tCL FF 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
7.978 1.312 tNET FF 1 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.421 0.442 tC2Q FF 58 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
10.506 2.085 tNET FF 1 R18C29[1][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.333 13.333 active clock edge time
13.333 0.000 pclk_rx
13.333 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
14.634 1.301 tNET RR 1 R18C29[1][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s1/CLK
14.286 -0.347 tSu 1 R18C29[1][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s1

Path Statistics:

Clock Skew -0.011
Setup Relationship 6.667
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.312, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.085, 82.493%; tC2Q: 0.442, 17.507%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.301, 100.000%

Path4

Path Summary:

Slack 4.025
Data Arrival Time 10.271
Data Required Time 14.296
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 pclk_rx
6.667 0.000 tCL FF 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
7.978 1.312 tNET FF 1 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.421 0.442 tC2Q FF 58 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
10.271 1.850 tNET FF 1 R18C30[1][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.333 13.333 active clock edge time
13.333 0.000 pclk_rx
13.333 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
14.643 1.310 tNET RR 1 R18C30[1][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLK
14.296 -0.347 tSu 1 R18C30[1][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1

Path Statistics:

Clock Skew -0.002
Setup Relationship 6.667
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.312, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.850, 80.698%; tC2Q: 0.442, 19.302%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.310, 100.000%

Path5

Path Summary:

Slack 4.025
Data Arrival Time 10.271
Data Required Time 14.296
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 pclk_rx
6.667 0.000 tCL FF 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
7.978 1.312 tNET FF 1 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.421 0.442 tC2Q FF 58 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
10.271 1.850 tNET FF 1 R18C30[0][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.333 13.333 active clock edge time
13.333 0.000 pclk_rx
13.333 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
14.643 1.310 tNET RR 1 R18C30[0][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLK
14.296 -0.347 tSu 1 R18C30[0][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1

Path Statistics:

Clock Skew -0.002
Setup Relationship 6.667
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.312, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.850, 80.698%; tC2Q: 0.442, 19.302%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.310, 100.000%

Path6

Path Summary:

Slack 4.025
Data Arrival Time 10.271
Data Required Time 14.296
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 pclk_rx
6.667 0.000 tCL FF 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
7.978 1.312 tNET FF 1 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.421 0.442 tC2Q FF 58 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
10.271 1.850 tNET FF 1 R18C30[0][A] gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.333 13.333 active clock edge time
13.333 0.000 pclk_rx
13.333 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
14.643 1.310 tNET RR 1 R18C30[0][A] gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLK
14.296 -0.347 tSu 1 R18C30[0][A] gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1

Path Statistics:

Clock Skew -0.002
Setup Relationship 6.667
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.312, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.850, 80.698%; tC2Q: 0.442, 19.302%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.310, 100.000%

Path7

Path Summary:

Slack 4.163
Data Arrival Time 10.158
Data Required Time 14.321
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 pclk_rx
6.667 0.000 tCL FF 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
7.978 1.312 tNET FF 1 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.421 0.442 tC2Q FF 58 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
10.158 1.738 tNET FF 1 R20C29[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.333 13.333 active clock edge time
13.333 0.000 pclk_rx
13.333 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
14.668 1.335 tNET RR 1 R20C29[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK
14.321 -0.347 tSu 1 R20C29[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1

Path Statistics:

Clock Skew 0.023
Setup Relationship 6.667
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.312, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.738, 79.702%; tC2Q: 0.442, 20.298%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.335, 100.000%

Path8

Path Summary:

Slack 4.376
Data Arrival Time 9.908
Data Required Time 14.285
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_0_s0
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 pclk_rx
6.667 0.000 tCL FF 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
7.978 1.312 tNET FF 1 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.421 0.442 tC2Q FF 58 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.908 1.488 tNET FF 1 R17C37[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.333 13.333 active clock edge time
13.333 0.000 pclk_rx
13.333 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
14.632 1.299 tNET RR 1 R17C37[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_0_s0/CLK
14.285 -0.347 tSu 1 R17C37[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_0_s0

Path Statistics:

Clock Skew -0.013
Setup Relationship 6.667
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.312, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.488, 77.073%; tC2Q: 0.442, 22.927%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.299, 100.000%

Path9

Path Summary:

Slack 4.376
Data Arrival Time 9.908
Data Required Time 14.285
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_1/trig_dly_in_0_s0
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 pclk_rx
6.667 0.000 tCL FF 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
7.978 1.312 tNET FF 1 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.421 0.442 tC2Q FF 58 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.908 1.488 tNET FF 1 R17C37[0][B] gw_gao_inst_0/u_la0_top/u_ao_match_1/trig_dly_in_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.333 13.333 active clock edge time
13.333 0.000 pclk_rx
13.333 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
14.632 1.299 tNET RR 1 R17C37[0][B] gw_gao_inst_0/u_la0_top/u_ao_match_1/trig_dly_in_0_s0/CLK
14.285 -0.347 tSu 1 R17C37[0][B] gw_gao_inst_0/u_la0_top/u_ao_match_1/trig_dly_in_0_s0

Path Statistics:

Clock Skew -0.013
Setup Relationship 6.667
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.312, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.488, 77.073%; tC2Q: 0.442, 22.927%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.299, 100.000%

Path10

Path Summary:

Slack 4.496
Data Arrival Time 9.798
Data Required Time 14.294
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 pclk_rx
6.667 0.000 tCL FF 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
7.978 1.312 tNET FF 1 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.421 0.442 tC2Q FF 58 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.798 1.378 tNET FF 1 R17C32[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.333 13.333 active clock edge time
13.333 0.000 pclk_rx
13.333 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
14.641 1.308 tNET RR 1 R17C32[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLK
14.294 -0.347 tSu 1 R17C32[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0

Path Statistics:

Clock Skew -0.003
Setup Relationship 6.667
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.312, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.378, 75.687%; tC2Q: 0.442, 24.313%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.308, 100.000%

Path11

Path Summary:

Slack 4.496
Data Arrival Time 9.798
Data Required Time 14.294
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 pclk_rx
6.667 0.000 tCL FF 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
7.978 1.312 tNET FF 1 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.421 0.442 tC2Q FF 58 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.798 1.378 tNET FF 1 R17C32[0][B] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.333 13.333 active clock edge time
13.333 0.000 pclk_rx
13.333 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
14.641 1.308 tNET RR 1 R17C32[0][B] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLK
14.294 -0.347 tSu 1 R17C32[0][B] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0

Path Statistics:

Clock Skew -0.003
Setup Relationship 6.667
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.312, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.378, 75.687%; tC2Q: 0.442, 24.313%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.308, 100.000%

Path12

Path Summary:

Slack 4.496
Data Arrival Time 9.798
Data Required Time 14.294
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 pclk_rx
6.667 0.000 tCL FF 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
7.978 1.312 tNET FF 1 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.421 0.442 tC2Q FF 58 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.798 1.378 tNET FF 1 R17C32[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.333 13.333 active clock edge time
13.333 0.000 pclk_rx
13.333 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
14.641 1.308 tNET RR 1 R17C32[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0/CLK
14.294 -0.347 tSu 1 R17C32[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0

Path Statistics:

Clock Skew -0.003
Setup Relationship 6.667
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.312, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.378, 75.687%; tC2Q: 0.442, 24.313%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.308, 100.000%

Path13

Path Summary:

Slack 4.496
Data Arrival Time 9.798
Data Required Time 14.294
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_1_s0
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 pclk_rx
6.667 0.000 tCL FF 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
7.978 1.312 tNET FF 1 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.421 0.442 tC2Q FF 58 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.798 1.378 tNET FF 1 R17C32[1][B] gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.333 13.333 active clock edge time
13.333 0.000 pclk_rx
13.333 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
14.641 1.308 tNET RR 1 R17C32[1][B] gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_1_s0/CLK
14.294 -0.347 tSu 1 R17C32[1][B] gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_1_s0

Path Statistics:

Clock Skew -0.003
Setup Relationship 6.667
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.312, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.378, 75.687%; tC2Q: 0.442, 24.313%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.308, 100.000%

Path14

Path Summary:

Slack 4.502
Data Arrival Time 9.821
Data Required Time 14.323
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 pclk_rx
6.667 0.000 tCL FF 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
7.978 1.312 tNET FF 1 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.421 0.442 tC2Q FF 58 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.821 1.400 tNET FF 1 R23C30[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.333 13.333 active clock edge time
13.333 0.000 pclk_rx
13.333 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
14.670 1.337 tNET RR 1 R23C30[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/CLK
14.323 -0.347 tSu 1 R23C30[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1

Path Statistics:

Clock Skew 0.025
Setup Relationship 6.667
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.312, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.400, 75.984%; tC2Q: 0.442, 24.016%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.337, 100.000%

Path15

Path Summary:

Slack 4.502
Data Arrival Time 9.821
Data Required Time 14.323
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 pclk_rx
6.667 0.000 tCL FF 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
7.978 1.312 tNET FF 1 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.421 0.442 tC2Q FF 58 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.821 1.400 tNET FF 1 R23C30[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.333 13.333 active clock edge time
13.333 0.000 pclk_rx
13.333 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
14.670 1.337 tNET RR 1 R23C30[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLK
14.323 -0.347 tSu 1 R23C30[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1

Path Statistics:

Clock Skew 0.025
Setup Relationship 6.667
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.312, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.400, 75.984%; tC2Q: 0.442, 24.016%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.337, 100.000%

Path16

Path Summary:

Slack 4.502
Data Arrival Time 9.821
Data Required Time 14.323
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 pclk_rx
6.667 0.000 tCL FF 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
7.978 1.312 tNET FF 1 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.421 0.442 tC2Q FF 58 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.821 1.400 tNET FF 1 R23C30[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.333 13.333 active clock edge time
13.333 0.000 pclk_rx
13.333 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
14.670 1.337 tNET RR 1 R23C30[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLK
14.323 -0.347 tSu 1 R23C30[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1

Path Statistics:

Clock Skew 0.025
Setup Relationship 6.667
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.312, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.400, 75.984%; tC2Q: 0.442, 24.016%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.337, 100.000%

Path17

Path Summary:

Slack 4.502
Data Arrival Time 9.821
Data Required Time 14.323
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 pclk_rx
6.667 0.000 tCL FF 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
7.978 1.312 tNET FF 1 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.421 0.442 tC2Q FF 58 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.821 1.400 tNET FF 1 R23C30[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.333 13.333 active clock edge time
13.333 0.000 pclk_rx
13.333 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
14.670 1.337 tNET RR 1 R23C30[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLK
14.323 -0.347 tSu 1 R23C30[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1

Path Statistics:

Clock Skew 0.025
Setup Relationship 6.667
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.312, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.400, 75.984%; tC2Q: 0.442, 24.016%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.337, 100.000%

Path18

Path Summary:

Slack 4.505
Data Arrival Time 9.798
Data Required Time 14.303
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_1/match_sep_s0
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 pclk_rx
6.667 0.000 tCL FF 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
7.978 1.312 tNET FF 1 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.421 0.442 tC2Q FF 58 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.798 1.378 tNET FF 1 R17C35[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_sep_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.333 13.333 active clock edge time
13.333 0.000 pclk_rx
13.333 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
14.651 1.317 tNET RR 1 R17C35[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_sep_s0/CLK
14.303 -0.347 tSu 1 R17C35[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_sep_s0

Path Statistics:

Clock Skew 0.006
Setup Relationship 6.667
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.312, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.378, 75.687%; tC2Q: 0.442, 24.313%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.317, 100.000%

Path19

Path Summary:

Slack 4.509
Data Arrival Time 9.821
Data Required Time 14.330
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 pclk_rx
6.667 0.000 tCL FF 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
7.978 1.312 tNET FF 1 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.421 0.442 tC2Q FF 58 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.821 1.400 tNET FF 1 R20C30[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.333 13.333 active clock edge time
13.333 0.000 pclk_rx
13.333 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
14.678 1.344 tNET RR 1 R20C30[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK
14.330 -0.347 tSu 1 R20C30[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1

Path Statistics:

Clock Skew 0.033
Setup Relationship 6.667
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.312, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.400, 75.984%; tC2Q: 0.442, 24.016%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.344, 100.000%

Path20

Path Summary:

Slack 4.509
Data Arrival Time 9.821
Data Required Time 14.330
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 pclk_rx
6.667 0.000 tCL FF 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
7.978 1.312 tNET FF 1 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.421 0.442 tC2Q FF 58 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.821 1.400 tNET FF 1 R20C30[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.333 13.333 active clock edge time
13.333 0.000 pclk_rx
13.333 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
14.678 1.344 tNET RR 1 R20C30[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK
14.330 -0.347 tSu 1 R20C30[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1

Path Statistics:

Clock Skew 0.033
Setup Relationship 6.667
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.312, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.400, 75.984%; tC2Q: 0.442, 24.016%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.344, 100.000%

Path21

Path Summary:

Slack 4.510
Data Arrival Time 9.803
Data Required Time 14.313
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_end_dly_s0
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 pclk_rx
6.667 0.000 tCL FF 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
7.978 1.312 tNET FF 1 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.421 0.442 tC2Q FF 58 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.803 1.383 tNET FF 1 R23C29[0][A] gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.333 13.333 active clock edge time
13.333 0.000 pclk_rx
13.333 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
14.661 1.327 tNET RR 1 R23C29[0][A] gw_gao_inst_0/u_la0_top/capture_end_dly_s0/CLK
14.313 -0.347 tSu 1 R23C29[0][A] gw_gao_inst_0/u_la0_top/capture_end_dly_s0

Path Statistics:

Clock Skew 0.016
Setup Relationship 6.667
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.312, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.383, 75.753%; tC2Q: 0.442, 24.247%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.327, 100.000%

Path22

Path Summary:

Slack 4.593
Data Arrival Time 9.732
Data Required Time 14.325
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 pclk_rx
6.667 0.000 tCL FF 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
7.978 1.312 tNET FF 1 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.421 0.442 tC2Q FF 58 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.732 1.311 tNET FF 1 R22C30[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.333 13.333 active clock edge time
13.333 0.000 pclk_rx
13.333 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
14.673 1.339 tNET RR 1 R22C30[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLK
14.325 -0.347 tSu 1 R22C30[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1

Path Statistics:

Clock Skew 0.028
Setup Relationship 6.667
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.312, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.311, 74.768%; tC2Q: 0.442, 25.232%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.339, 100.000%

Path23

Path Summary:

Slack 4.593
Data Arrival Time 9.732
Data Required Time 14.325
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 pclk_rx
6.667 0.000 tCL FF 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
7.978 1.312 tNET FF 1 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.421 0.442 tC2Q FF 58 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.732 1.311 tNET FF 1 R22C30[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.333 13.333 active clock edge time
13.333 0.000 pclk_rx
13.333 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
14.673 1.339 tNET RR 1 R22C30[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK
14.325 -0.347 tSu 1 R22C30[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1

Path Statistics:

Clock Skew 0.028
Setup Relationship 6.667
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.312, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.311, 74.768%; tC2Q: 0.442, 25.232%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.339, 100.000%

Path24

Path Summary:

Slack 4.593
Data Arrival Time 9.732
Data Required Time 14.325
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 pclk_rx
6.667 0.000 tCL FF 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
7.978 1.312 tNET FF 1 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.421 0.442 tC2Q FF 58 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.732 1.311 tNET FF 1 R22C30[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.333 13.333 active clock edge time
13.333 0.000 pclk_rx
13.333 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
14.673 1.339 tNET RR 1 R22C30[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK
14.325 -0.347 tSu 1 R22C30[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1

Path Statistics:

Clock Skew 0.028
Setup Relationship 6.667
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.312, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.311, 74.768%; tC2Q: 0.442, 25.232%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.339, 100.000%

Path25

Path Summary:

Slack 4.670
Data Arrival Time 9.614
Data Required Time 14.285
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 pclk_rx
6.667 0.000 tCL FF 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
7.978 1.312 tNET FF 1 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.421 0.442 tC2Q FF 58 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.614 1.194 tNET FF 1 R17C33[2][B] gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.333 13.333 active clock edge time
13.333 0.000 pclk_rx
13.333 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
14.632 1.299 tNET RR 1 R17C33[2][B] gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLK
14.285 -0.347 tSu 1 R17C33[2][B] gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0

Path Statistics:

Clock Skew -0.013
Setup Relationship 6.667
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.312, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.194, 72.956%; tC2Q: 0.442, 27.044%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.299, 100.000%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 0.303
Data Arrival Time 1.415
Data Required Time 1.112
From u_EasyCDR_Top/u_easycdr/u_share_logic/rst_n_s0
To u_EasyCDR_Top/u_easycdr/u_share_logic/delay_cnt_0_s0
Launch Clk board_clk:[R]
Latch Clk board_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 board_clk
0.000 0.000 tCL RR 1 IOB29[A] gowin_ibuf_board_clk/I
0.675 0.675 tINS RR 12 IOB29[A] gowin_ibuf_board_clk/O
1.165 0.490 tNET RR 1 R9C26[0][B] u_EasyCDR_Top/u_easycdr/u_share_logic/rst_n_s0/CLK
1.309 0.144 tC2Q RR 7 R9C26[0][B] u_EasyCDR_Top/u_easycdr/u_share_logic/rst_n_s0/Q
1.415 0.106 tNET RR 1 R9C28[1][B] u_EasyCDR_Top/u_easycdr/u_share_logic/delay_cnt_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 board_clk
0.000 0.000 tCL RR 1 IOB29[A] gowin_ibuf_board_clk/I
0.675 0.675 tINS RR 12 IOB29[A] gowin_ibuf_board_clk/O
1.165 0.490 tNET RR 1 R9C28[1][B] u_EasyCDR_Top/u_easycdr/u_share_logic/delay_cnt_0_s0/CLK
1.112 -0.053 tHld 1 R9C28[1][B] u_EasyCDR_Top/u_easycdr/u_share_logic/delay_cnt_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 57.958%; route: 0.490, 42.042%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.106, 42.400%; tC2Q: 0.144, 57.600%
Required Clock Path Delay cell: 0.675, 57.958%; route: 0.490, 42.042%

Path2

Path Summary:

Slack 0.303
Data Arrival Time 1.415
Data Required Time 1.112
From u_EasyCDR_Top/u_easycdr/u_share_logic/rst_n_s0
To u_EasyCDR_Top/u_easycdr/u_share_logic/delay_cnt_1_s0
Launch Clk board_clk:[R]
Latch Clk board_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 board_clk
0.000 0.000 tCL RR 1 IOB29[A] gowin_ibuf_board_clk/I
0.675 0.675 tINS RR 12 IOB29[A] gowin_ibuf_board_clk/O
1.165 0.490 tNET RR 1 R9C26[0][B] u_EasyCDR_Top/u_easycdr/u_share_logic/rst_n_s0/CLK
1.309 0.144 tC2Q RR 7 R9C26[0][B] u_EasyCDR_Top/u_easycdr/u_share_logic/rst_n_s0/Q
1.415 0.106 tNET RR 1 R9C28[1][A] u_EasyCDR_Top/u_easycdr/u_share_logic/delay_cnt_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 board_clk
0.000 0.000 tCL RR 1 IOB29[A] gowin_ibuf_board_clk/I
0.675 0.675 tINS RR 12 IOB29[A] gowin_ibuf_board_clk/O
1.165 0.490 tNET RR 1 R9C28[1][A] u_EasyCDR_Top/u_easycdr/u_share_logic/delay_cnt_1_s0/CLK
1.112 -0.053 tHld 1 R9C28[1][A] u_EasyCDR_Top/u_easycdr/u_share_logic/delay_cnt_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 57.958%; route: 0.490, 42.042%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.106, 42.400%; tC2Q: 0.144, 57.600%
Required Clock Path Delay cell: 0.675, 57.958%; route: 0.490, 42.042%

Path3

Path Summary:

Slack 0.303
Data Arrival Time 1.415
Data Required Time 1.112
From u_EasyCDR_Top/u_easycdr/u_share_logic/rst_n_s0
To u_EasyCDR_Top/u_easycdr/u_share_logic/delay_cnt_2_s0
Launch Clk board_clk:[R]
Latch Clk board_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 board_clk
0.000 0.000 tCL RR 1 IOB29[A] gowin_ibuf_board_clk/I
0.675 0.675 tINS RR 12 IOB29[A] gowin_ibuf_board_clk/O
1.165 0.490 tNET RR 1 R9C26[0][B] u_EasyCDR_Top/u_easycdr/u_share_logic/rst_n_s0/CLK
1.309 0.144 tC2Q RR 7 R9C26[0][B] u_EasyCDR_Top/u_easycdr/u_share_logic/rst_n_s0/Q
1.415 0.106 tNET RR 1 R9C28[0][B] u_EasyCDR_Top/u_easycdr/u_share_logic/delay_cnt_2_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 board_clk
0.000 0.000 tCL RR 1 IOB29[A] gowin_ibuf_board_clk/I
0.675 0.675 tINS RR 12 IOB29[A] gowin_ibuf_board_clk/O
1.165 0.490 tNET RR 1 R9C28[0][B] u_EasyCDR_Top/u_easycdr/u_share_logic/delay_cnt_2_s0/CLK
1.112 -0.053 tHld 1 R9C28[0][B] u_EasyCDR_Top/u_easycdr/u_share_logic/delay_cnt_2_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 57.958%; route: 0.490, 42.042%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.106, 42.400%; tC2Q: 0.144, 57.600%
Required Clock Path Delay cell: 0.675, 57.958%; route: 0.490, 42.042%

Path4

Path Summary:

Slack 0.303
Data Arrival Time 1.415
Data Required Time 1.112
From u_EasyCDR_Top/u_easycdr/u_share_logic/rst_n_s0
To u_EasyCDR_Top/u_easycdr/u_share_logic/delay_cnt_3_s0
Launch Clk board_clk:[R]
Latch Clk board_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 board_clk
0.000 0.000 tCL RR 1 IOB29[A] gowin_ibuf_board_clk/I
0.675 0.675 tINS RR 12 IOB29[A] gowin_ibuf_board_clk/O
1.165 0.490 tNET RR 1 R9C26[0][B] u_EasyCDR_Top/u_easycdr/u_share_logic/rst_n_s0/CLK
1.309 0.144 tC2Q RR 7 R9C26[0][B] u_EasyCDR_Top/u_easycdr/u_share_logic/rst_n_s0/Q
1.415 0.106 tNET RR 1 R9C28[0][A] u_EasyCDR_Top/u_easycdr/u_share_logic/delay_cnt_3_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 board_clk
0.000 0.000 tCL RR 1 IOB29[A] gowin_ibuf_board_clk/I
0.675 0.675 tINS RR 12 IOB29[A] gowin_ibuf_board_clk/O
1.165 0.490 tNET RR 1 R9C28[0][A] u_EasyCDR_Top/u_easycdr/u_share_logic/delay_cnt_3_s0/CLK
1.112 -0.053 tHld 1 R9C28[0][A] u_EasyCDR_Top/u_easycdr/u_share_logic/delay_cnt_3_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 57.958%; route: 0.490, 42.042%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.106, 42.400%; tC2Q: 0.144, 57.600%
Required Clock Path Delay cell: 0.675, 57.958%; route: 0.490, 42.042%

Path5

Path Summary:

Slack 0.307
Data Arrival Time 1.415
Data Required Time 1.109
From u_EasyCDR_Top/u_easycdr/u_share_logic/rst_n_s0
To u_EasyCDR_Top/u_easycdr/u_share_logic/cen_s0
Launch Clk board_clk:[R]
Latch Clk board_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 board_clk
0.000 0.000 tCL RR 1 IOB29[A] gowin_ibuf_board_clk/I
0.675 0.675 tINS RR 12 IOB29[A] gowin_ibuf_board_clk/O
1.165 0.490 tNET RR 1 R9C26[0][B] u_EasyCDR_Top/u_easycdr/u_share_logic/rst_n_s0/CLK
1.309 0.144 tC2Q RR 7 R9C26[0][B] u_EasyCDR_Top/u_easycdr/u_share_logic/rst_n_s0/Q
1.415 0.106 tNET RR 1 R9C27[0][A] u_EasyCDR_Top/u_easycdr/u_share_logic/cen_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 board_clk
0.000 0.000 tCL RR 1 IOB29[A] gowin_ibuf_board_clk/I
0.675 0.675 tINS RR 12 IOB29[A] gowin_ibuf_board_clk/O
1.161 0.486 tNET RR 1 R9C27[0][A] u_EasyCDR_Top/u_easycdr/u_share_logic/cen_s0/CLK
1.109 -0.053 tHld 1 R9C27[0][A] u_EasyCDR_Top/u_easycdr/u_share_logic/cen_s0

Path Statistics:

Clock Skew -0.004
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 57.958%; route: 0.490, 42.042%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.106, 42.400%; tC2Q: 0.144, 57.600%
Required Clock Path Delay cell: 0.675, 58.158%; route: 0.486, 41.842%

Path6

Path Summary:

Slack 0.307
Data Arrival Time 1.415
Data Required Time 1.109
From u_EasyCDR_Top/u_easycdr/u_share_logic/rst_n_s0
To u_EasyCDR_Top/u_easycdr/u_share_logic/reset_o_s0
Launch Clk board_clk:[R]
Latch Clk board_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 board_clk
0.000 0.000 tCL RR 1 IOB29[A] gowin_ibuf_board_clk/I
0.675 0.675 tINS RR 12 IOB29[A] gowin_ibuf_board_clk/O
1.165 0.490 tNET RR 1 R9C26[0][B] u_EasyCDR_Top/u_easycdr/u_share_logic/rst_n_s0/CLK
1.309 0.144 tC2Q RR 7 R9C26[0][B] u_EasyCDR_Top/u_easycdr/u_share_logic/rst_n_s0/Q
1.415 0.106 tNET RR 1 R9C27[0][B] u_EasyCDR_Top/u_easycdr/u_share_logic/reset_o_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 board_clk
0.000 0.000 tCL RR 1 IOB29[A] gowin_ibuf_board_clk/I
0.675 0.675 tINS RR 12 IOB29[A] gowin_ibuf_board_clk/O
1.161 0.486 tNET RR 1 R9C27[0][B] u_EasyCDR_Top/u_easycdr/u_share_logic/reset_o_s0/CLK
1.109 -0.053 tHld 1 R9C27[0][B] u_EasyCDR_Top/u_easycdr/u_share_logic/reset_o_s0

Path Statistics:

Clock Skew -0.004
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 57.958%; route: 0.490, 42.042%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.106, 42.400%; tC2Q: 0.144, 57.600%
Required Clock Path Delay cell: 0.675, 58.158%; route: 0.486, 41.842%

Path7

Path Summary:

Slack 0.515
Data Arrival Time 1.646
Data Required Time 1.131
From u_EasyCDR_Top/u_easycdr/u_share_logic/rst_n_s0
To u_EasyCDR_Top/u_easycdr/u_share_logic/resetn_s0
Launch Clk board_clk:[R]
Latch Clk board_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 board_clk
0.000 0.000 tCL RR 1 IOB29[A] gowin_ibuf_board_clk/I
0.675 0.675 tINS RR 12 IOB29[A] gowin_ibuf_board_clk/O
1.165 0.490 tNET RR 1 R9C26[0][B] u_EasyCDR_Top/u_easycdr/u_share_logic/rst_n_s0/CLK
1.309 0.144 tC2Q RR 7 R9C26[0][B] u_EasyCDR_Top/u_easycdr/u_share_logic/rst_n_s0/Q
1.646 0.337 tNET RR 1 R2C28[0][A] u_EasyCDR_Top/u_easycdr/u_share_logic/resetn_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 board_clk
0.000 0.000 tCL RR 1 IOB29[A] gowin_ibuf_board_clk/I
0.675 0.675 tINS RR 12 IOB29[A] gowin_ibuf_board_clk/O
1.184 0.509 tNET RR 1 R2C28[0][A] u_EasyCDR_Top/u_easycdr/u_share_logic/resetn_s0/CLK
1.131 -0.053 tHld 1 R2C28[0][A] u_EasyCDR_Top/u_easycdr/u_share_logic/resetn_s0

Path Statistics:

Clock Skew 0.019
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 57.958%; route: 0.490, 42.042%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.337, 70.062%; tC2Q: 0.144, 29.938%
Required Clock Path Delay cell: 0.675, 57.040%; route: 0.509, 42.960%

Path8

Path Summary:

Slack 6.969
Data Arrival Time 7.404
Data Required Time 0.435
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 pclk_rx
6.667 0.000 tCL FF 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
7.159 0.492 tNET FF 1 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
7.317 0.158 tC2Q FR 58 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.404 0.087 tNET RR 1 R26C33[2][A] gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.488 0.488 tNET RR 1 R26C33[2][A] gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLK
0.435 -0.053 tHld 1 R26C33[2][A] gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3

Path Statistics:

Clock Skew -0.004
Hold Relationship -6.667
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.492, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.087, 35.510%; tC2Q: 0.158, 64.490%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.488, 100.000%

Path9

Path Summary:

Slack 6.969
Data Arrival Time 7.404
Data Required Time 0.435
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 pclk_rx
6.667 0.000 tCL FF 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
7.159 0.492 tNET FF 1 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
7.317 0.158 tC2Q FR 58 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.404 0.087 tNET RR 1 R26C33[1][A] gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.488 0.488 tNET RR 1 R26C33[1][A] gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLK
0.435 -0.053 tHld 1 R26C33[1][A] gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0

Path Statistics:

Clock Skew -0.004
Hold Relationship -6.667
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.492, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.087, 35.510%; tC2Q: 0.158, 64.490%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.488, 100.000%

Path10

Path Summary:

Slack 7.079
Data Arrival Time 7.518
Data Required Time 0.439
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 pclk_rx
6.667 0.000 tCL FF 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
7.159 0.492 tNET FF 1 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
7.317 0.158 tC2Q FR 58 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.518 0.201 tNET RR 1 R26C34[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.492 0.492 tNET RR 1 R26C34[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLK
0.439 -0.053 tHld 1 R26C34[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1

Path Statistics:

Clock Skew -0.000
Hold Relationship -6.667
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.492, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.201, 55.989%; tC2Q: 0.158, 44.011%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.492, 100.000%

Path11

Path Summary:

Slack 7.079
Data Arrival Time 7.518
Data Required Time 0.439
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 pclk_rx
6.667 0.000 tCL FF 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
7.159 0.492 tNET FF 1 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
7.317 0.158 tC2Q FR 58 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.518 0.201 tNET RR 1 R26C34[2][A] gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.492 0.492 tNET RR 1 R26C34[2][A] gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLK
0.439 -0.053 tHld 1 R26C34[2][A] gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0

Path Statistics:

Clock Skew -0.000
Hold Relationship -6.667
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.492, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.201, 55.989%; tC2Q: 0.158, 44.011%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.492, 100.000%

Path12

Path Summary:

Slack 7.079
Data Arrival Time 7.518
Data Required Time 0.439
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 pclk_rx
6.667 0.000 tCL FF 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
7.159 0.492 tNET FF 1 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
7.317 0.158 tC2Q FR 58 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.518 0.201 tNET RR 1 R26C34[2][B] gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.492 0.492 tNET RR 1 R26C34[2][B] gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLK
0.439 -0.053 tHld 1 R26C34[2][B] gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0

Path Statistics:

Clock Skew -0.000
Hold Relationship -6.667
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.492, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.201, 55.989%; tC2Q: 0.158, 44.011%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.492, 100.000%

Path13

Path Summary:

Slack 7.084
Data Arrival Time 7.524
Data Required Time 0.440
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 pclk_rx
6.667 0.000 tCL FF 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
7.159 0.492 tNET FF 1 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
7.317 0.158 tC2Q FR 58 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.524 0.207 tNET RR 1 R25C33[2][A] gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.493 0.493 tNET RR 1 R25C33[2][A] gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLK
0.440 -0.053 tHld 1 R25C33[2][A] gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1

Path Statistics:

Clock Skew 0.001
Hold Relationship -6.667
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.492, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.207, 56.712%; tC2Q: 0.158, 43.288%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.493, 100.000%

Path14

Path Summary:

Slack 7.084
Data Arrival Time 7.524
Data Required Time 0.440
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 pclk_rx
6.667 0.000 tCL FF 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
7.159 0.492 tNET FF 1 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
7.317 0.158 tC2Q FR 58 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.524 0.207 tNET RR 1 R25C33[3][A] gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.493 0.493 tNET RR 1 R25C33[3][A] gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLK
0.440 -0.053 tHld 1 R25C33[3][A] gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1

Path Statistics:

Clock Skew 0.001
Hold Relationship -6.667
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.492, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.207, 56.712%; tC2Q: 0.158, 43.288%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.493, 100.000%

Path15

Path Summary:

Slack 7.084
Data Arrival Time 7.524
Data Required Time 0.440
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 pclk_rx
6.667 0.000 tCL FF 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
7.159 0.492 tNET FF 1 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
7.317 0.158 tC2Q FR 58 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.524 0.207 tNET RR 1 R25C33[1][B] gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.493 0.493 tNET RR 1 R25C33[1][B] gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLK
0.440 -0.053 tHld 1 R25C33[1][B] gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1

Path Statistics:

Clock Skew 0.001
Hold Relationship -6.667
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.492, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.207, 56.712%; tC2Q: 0.158, 43.288%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.493, 100.000%

Path16

Path Summary:

Slack 7.084
Data Arrival Time 7.524
Data Required Time 0.440
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 pclk_rx
6.667 0.000 tCL FF 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
7.159 0.492 tNET FF 1 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
7.317 0.158 tC2Q FR 58 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.524 0.207 tNET RR 1 R25C33[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.493 0.493 tNET RR 1 R25C33[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLK
0.440 -0.053 tHld 1 R25C33[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1

Path Statistics:

Clock Skew 0.001
Hold Relationship -6.667
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.492, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.207, 56.712%; tC2Q: 0.158, 43.288%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.493, 100.000%

Path17

Path Summary:

Slack 7.084
Data Arrival Time 7.524
Data Required Time 0.440
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 pclk_rx
6.667 0.000 tCL FF 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
7.159 0.492 tNET FF 1 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
7.317 0.158 tC2Q FR 58 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.524 0.207 tNET RR 1 R25C33[0][B] gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.493 0.493 tNET RR 1 R25C33[0][B] gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLK
0.440 -0.053 tHld 1 R25C33[0][B] gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1

Path Statistics:

Clock Skew 0.001
Hold Relationship -6.667
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.492, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.207, 56.712%; tC2Q: 0.158, 43.288%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.493, 100.000%

Path18

Path Summary:

Slack 7.146
Data Arrival Time 7.592
Data Required Time 0.446
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 pclk_rx
6.667 0.000 tCL FF 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
7.159 0.492 tNET FF 1 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
7.317 0.158 tC2Q FR 58 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.592 0.275 tNET RR 1 R24C32[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.499 0.499 tNET RR 1 R24C32[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLK
0.446 -0.053 tHld 1 R24C32[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1

Path Statistics:

Clock Skew 0.007
Hold Relationship -6.667
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.492, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.275, 63.510%; tC2Q: 0.158, 36.490%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.499, 100.000%

Path19

Path Summary:

Slack 7.146
Data Arrival Time 7.592
Data Required Time 0.446
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 pclk_rx
6.667 0.000 tCL FF 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
7.159 0.492 tNET FF 1 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
7.317 0.158 tC2Q FR 58 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.592 0.275 tNET RR 1 R24C32[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.499 0.499 tNET RR 1 R24C32[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
0.446 -0.053 tHld 1 R24C32[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1

Path Statistics:

Clock Skew 0.007
Hold Relationship -6.667
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.492, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.275, 63.510%; tC2Q: 0.158, 36.490%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.499, 100.000%

Path20

Path Summary:

Slack 7.152
Data Arrival Time 7.596
Data Required Time 0.444
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 pclk_rx
6.667 0.000 tCL FF 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
7.159 0.492 tNET FF 1 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
7.317 0.158 tC2Q FR 58 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.596 0.279 tNET RR 1 R25C32[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.497 0.497 tNET RR 1 R25C32[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLK
0.444 -0.053 tHld 1 R25C32[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1

Path Statistics:

Clock Skew 0.005
Hold Relationship -6.667
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.492, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.279, 63.844%; tC2Q: 0.158, 36.156%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.497, 100.000%

Path21

Path Summary:

Slack 7.154
Data Arrival Time 7.593
Data Required Time 0.439
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/triger_s0
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 pclk_rx
6.667 0.000 tCL FF 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
7.159 0.492 tNET FF 1 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
7.317 0.158 tC2Q FR 58 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.593 0.276 tNET RR 1 R26C30[0][A] gw_gao_inst_0/u_la0_top/triger_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.492 0.492 tNET RR 1 R26C30[0][A] gw_gao_inst_0/u_la0_top/triger_s0/CLK
0.439 -0.053 tHld 1 R26C30[0][A] gw_gao_inst_0/u_la0_top/triger_s0

Path Statistics:

Clock Skew -0.000
Hold Relationship -6.667
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.492, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.276, 63.594%; tC2Q: 0.158, 36.406%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.492, 100.000%

Path22

Path Summary:

Slack 7.156
Data Arrival Time 7.599
Data Required Time 0.443
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 pclk_rx
6.667 0.000 tCL FF 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
7.159 0.492 tNET FF 1 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
7.317 0.158 tC2Q FR 58 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.599 0.282 tNET RR 1 R26C31[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.496 0.496 tNET RR 1 R26C31[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLK
0.443 -0.053 tHld 1 R26C31[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1

Path Statistics:

Clock Skew 0.004
Hold Relationship -6.667
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.492, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.282, 64.091%; tC2Q: 0.158, 35.909%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.496, 100.000%

Path23

Path Summary:

Slack 7.156
Data Arrival Time 7.599
Data Required Time 0.443
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 pclk_rx
6.667 0.000 tCL FF 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
7.159 0.492 tNET FF 1 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
7.317 0.158 tC2Q FR 58 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.599 0.282 tNET RR 1 R26C31[1][B] gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.496 0.496 tNET RR 1 R26C31[1][B] gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLK
0.443 -0.053 tHld 1 R26C31[1][B] gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1

Path Statistics:

Clock Skew 0.004
Hold Relationship -6.667
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.492, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.282, 64.091%; tC2Q: 0.158, 35.909%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.496, 100.000%

Path24

Path Summary:

Slack 7.156
Data Arrival Time 7.599
Data Required Time 0.443
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/trigger_seq_start_s1
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 pclk_rx
6.667 0.000 tCL FF 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
7.159 0.492 tNET FF 1 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
7.317 0.158 tC2Q FR 58 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.599 0.282 tNET RR 1 R26C31[2][A] gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.496 0.496 tNET RR 1 R26C31[2][A] gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLK
0.443 -0.053 tHld 1 R26C31[2][A] gw_gao_inst_0/u_la0_top/trigger_seq_start_s1

Path Statistics:

Clock Skew 0.004
Hold Relationship -6.667
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.492, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.282, 64.091%; tC2Q: 0.158, 35.909%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.496, 100.000%

Path25

Path Summary:

Slack 7.156
Data Arrival Time 7.599
Data Required Time 0.443
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/start_reg_s0
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 pclk_rx
6.667 0.000 tCL FF 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
7.159 0.492 tNET FF 1 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
7.317 0.158 tC2Q FR 58 R26C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.599 0.282 tNET RR 1 R26C31[0][B] gw_gao_inst_0/u_la0_top/start_reg_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 527 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.496 0.496 tNET RR 1 R26C31[0][B] gw_gao_inst_0/u_la0_top/start_reg_s0/CLK
0.443 -0.053 tHld 1 R26C31[0][B] gw_gao_inst_0/u_la0_top/start_reg_s0

Path Statistics:

Clock Skew 0.004
Hold Relationship -6.667
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.492, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.282, 64.091%; tC2Q: 0.158, 35.909%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.496, 100.000%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack: 2.257
Actual Width: 2.507
Required Width: 0.250
Type: Low Pulse Width
Clock: pclk_tx
Objects: u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_0_s0

Late clock Path:

AT DELAY TYPE RF NODE
3.333 0.000 active clock edge time
3.333 0.000 pclk_tx
3.333 0.000 tCL FF u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT
4.647 1.314 tNET FF u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_0_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
6.667 0.000 active clock edge time
6.667 0.000 pclk_tx
6.667 0.000 tCL RR u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT
7.154 0.487 tNET RR u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_0_s0/CLK

MPW2

MPW Summary:

Slack: 2.257
Actual Width: 2.507
Required Width: 0.250
Type: Low Pulse Width
Clock: pclk_tx
Objects: u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_tmp_7_s0

Late clock Path:

AT DELAY TYPE RF NODE
3.333 0.000 active clock edge time
3.333 0.000 pclk_tx
3.333 0.000 tCL FF u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT
4.647 1.314 tNET FF u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_tmp_7_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
6.667 0.000 active clock edge time
6.667 0.000 pclk_tx
6.667 0.000 tCL RR u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT
7.154 0.487 tNET RR u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_tmp_7_s0/CLK

MPW3

MPW Summary:

Slack: 2.257
Actual Width: 2.507
Required Width: 0.250
Type: Low Pulse Width
Clock: pclk_tx
Objects: u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_tmp_6_s0

Late clock Path:

AT DELAY TYPE RF NODE
3.333 0.000 active clock edge time
3.333 0.000 pclk_tx
3.333 0.000 tCL FF u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT
4.647 1.314 tNET FF u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_tmp_6_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
6.667 0.000 active clock edge time
6.667 0.000 pclk_tx
6.667 0.000 tCL RR u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT
7.154 0.487 tNET RR u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_tmp_6_s0/CLK

MPW4

MPW Summary:

Slack: 2.257
Actual Width: 2.507
Required Width: 0.250
Type: Low Pulse Width
Clock: pclk_tx
Objects: u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_tmp_5_s0

Late clock Path:

AT DELAY TYPE RF NODE
3.333 0.000 active clock edge time
3.333 0.000 pclk_tx
3.333 0.000 tCL FF u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT
4.647 1.314 tNET FF u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_tmp_5_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
6.667 0.000 active clock edge time
6.667 0.000 pclk_tx
6.667 0.000 tCL RR u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT
7.154 0.487 tNET RR u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_tmp_5_s0/CLK

MPW5

MPW Summary:

Slack: 2.257
Actual Width: 2.507
Required Width: 0.250
Type: Low Pulse Width
Clock: pclk_tx
Objects: u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_7_s2

Late clock Path:

AT DELAY TYPE RF NODE
3.333 0.000 active clock edge time
3.333 0.000 pclk_tx
3.333 0.000 tCL FF u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT
4.647 1.314 tNET FF u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_7_s2/CLK

Early clock Path:

AT DELAY TYPE RF NODE
6.667 0.000 active clock edge time
6.667 0.000 pclk_tx
6.667 0.000 tCL RR u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT
7.154 0.487 tNET RR u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_7_s2/CLK

MPW6

MPW Summary:

Slack: 2.257
Actual Width: 2.507
Required Width: 0.250
Type: Low Pulse Width
Clock: pclk_tx
Objects: u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_6_s1

Late clock Path:

AT DELAY TYPE RF NODE
3.333 0.000 active clock edge time
3.333 0.000 pclk_tx
3.333 0.000 tCL FF u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT
4.647 1.314 tNET FF u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_6_s1/CLK

Early clock Path:

AT DELAY TYPE RF NODE
6.667 0.000 active clock edge time
6.667 0.000 pclk_tx
6.667 0.000 tCL RR u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT
7.154 0.487 tNET RR u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_6_s1/CLK

MPW7

MPW Summary:

Slack: 2.257
Actual Width: 2.507
Required Width: 0.250
Type: Low Pulse Width
Clock: pclk_tx
Objects: u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_0_s1

Late clock Path:

AT DELAY TYPE RF NODE
3.333 0.000 active clock edge time
3.333 0.000 pclk_tx
3.333 0.000 tCL FF u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT
4.647 1.314 tNET FF u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_0_s1/CLK

Early clock Path:

AT DELAY TYPE RF NODE
6.667 0.000 active clock edge time
6.667 0.000 pclk_tx
6.667 0.000 tCL RR u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT
7.154 0.487 tNET RR u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_0_s1/CLK

MPW8

MPW Summary:

Slack: 2.257
Actual Width: 2.507
Required Width: 0.250
Type: Low Pulse Width
Clock: pclk_tx
Objects: u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_8_s0

Late clock Path:

AT DELAY TYPE RF NODE
3.333 0.000 active clock edge time
3.333 0.000 pclk_tx
3.333 0.000 tCL FF u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT
4.647 1.314 tNET FF u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_8_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
6.667 0.000 active clock edge time
6.667 0.000 pclk_tx
6.667 0.000 tCL RR u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT
7.154 0.487 tNET RR u_motivation_response/u_tx_module_top/u_prbs_generator/shift_reg_8_s0/CLK

MPW9

MPW Summary:

Slack: 2.257
Actual Width: 2.507
Required Width: 0.250
Type: Low Pulse Width
Clock: pclk_tx
Objects: u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_5_s1

Late clock Path:

AT DELAY TYPE RF NODE
3.333 0.000 active clock edge time
3.333 0.000 pclk_tx
3.333 0.000 tCL FF u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT
4.647 1.314 tNET FF u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_5_s1/CLK

Early clock Path:

AT DELAY TYPE RF NODE
6.667 0.000 active clock edge time
6.667 0.000 pclk_tx
6.667 0.000 tCL RR u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT
7.154 0.487 tNET RR u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_5_s1/CLK

MPW10

MPW Summary:

Slack: 2.257
Actual Width: 2.507
Required Width: 0.250
Type: High Pulse Width
Clock: pclk_tx
Objects: u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_0_s1

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_tx
0.000 0.000 tCL RR u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT
1.317 1.317 tNET RR u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_0_s1/CLK

Early clock Path:

AT DELAY TYPE RF NODE
3.333 0.000 active clock edge time
3.333 0.000 pclk_tx
3.333 0.000 tCL FF u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT
3.825 0.491 tNET FF u_motivation_response/u_tx_module_top/u_prbs_generator/o_dout_0_s1/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT NET NAME WORST SLACK MAX DELAY
527 u_motivation_response_0 5.658 1.356
234 control0[0] 41.444 2.385
127 remained_cnt[0] 6.077 3.333
105 remained_cnt[1] 5.658 2.528
91 remained_cnt[2] 6.302 1.796
58 rst_ao 3.595 2.308
55 remained_cnt[3] 5.776 2.655
53 cdr_dat_sel[1] 7.880 2.328
49 remained_cnt[4] 6.203 2.400
46 n20_3 45.769 1.208

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC ROUTE CONGESTIONS
R21C32 51.39%
R22C23 50.00%
R16C33 47.22%
R21C23 47.22%
R23C23 45.83%
R22C25 44.44%
R21C35 43.06%
R23C36 41.67%
R22C34 41.67%
R21C22 41.67%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type State Detail Command
TC_CLOCK Actived create_clock -name tck_pad -period 50 -waveform {0 25} [get_ports {tck_pad_i}]
TC_CLOCK Actived create_clock -name board_clk -period 20 -waveform {0 10} [get_pins {gowin_ibuf_board_clk/I}]
TC_GENERATED_CLOCK Actived create_generated_clock -name hclk_0_rx -source [get_pins {gowin_ibuf_board_clk/I}] -master_clock board_clk -divide_by 3 -multiply_by 18 [get_pins {u_motivation_response/u_pll_hclk/PLLA_inst/CLKOUT0}]
TC_GENERATED_CLOCK Actived create_generated_clock -name hclk_180_rx -source [get_pins {gowin_ibuf_board_clk/I}] -master_clock board_clk -divide_by 3 -multiply_by 18 -phase 180 [get_pins {u_motivation_response/u_pll_hclk/PLLA_inst/CLKOUT2}]
TC_GENERATED_CLOCK Actived create_generated_clock -name hclk_90_rx -source [get_pins {gowin_ibuf_board_clk/I}] -master_clock board_clk -divide_by 3 -multiply_by 18 -phase 90 [get_pins {u_motivation_response/u_pll_hclk/PLLA_inst/CLKOUT1}]
TC_GENERATED_CLOCK Actived create_generated_clock -name hclk_0_tx -source [get_pins {gowin_ibuf_board_clk/I}] -master_clock board_clk -divide_by 2 -multiply_by 24 [get_pins {u_motivation_response/u_pll_hclk_tx/PLLA_inst/CLKOUT0}]
TC_GENERATED_CLOCK Actived create_generated_clock -name pclk_rx -source [get_pins {u_motivation_response/u_pll_hclk/PLLA_inst/CLKOUT0}] -master_clock hclk_0_rx -divide_by 4 -multiply_by 1 [get_pins {u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT}]
TC_GENERATED_CLOCK Actived create_generated_clock -name hclk_270_rx -source [get_pins {gowin_ibuf_board_clk/I}] -master_clock board_clk -divide_by 3 -multiply_by 18 -phase 270 [get_pins {u_motivation_response/u_pll_hclk/PLLA_inst/CLKOUT3}]
TC_GENERATED_CLOCK Actived create_generated_clock -name pclk_tx -source [get_pins {u_motivation_response/u_pll_hclk_tx/PLLA_inst/CLKOUT0}] -master_clock hclk_0_tx -divide_by 4 -multiply_by 1 [get_pins {u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT}]
TC_FALSE_PATH Actived set_false_path -from [get_clocks {board_clk}] -to [get_clocks {hclk_0_rx hclk_90_rx hclk_180_rx hclk_270_rx hclk_0_tx pclk_rx pclk_tx}]
TC_FALSE_PATH Actived set_false_path -from [get_clocks {pclk_tx pclk_rx}] -to [get_clocks {tck_pad}]
TC_FALSE_PATH Actived set_false_path -from [get_clocks {tck_pad}] -to [get_clocks {pclk_tx pclk_rx}]