Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\EASYCDR\data\EasyCDR_Top.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\EASYCDR\data\EasyCDR.v |
GowinSynthesis Constraints File | --- |
Tool Version | V1.9.9.03 (64-bit) |
Part Number | GW5A-LV25UG324ES |
Device | GW5A-25 |
Device Version | A |
Created Time | Wed Apr 24 16:20:30 2024 |
Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | EasyCDR_Top |
Synthesis Process | Running parser: CPU time = 0h 0m 0.234s, Elapsed time = 0h 0m 0.262s, Peak memory usage = 79.656MB Running netlist conversion: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 79.656MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.025s, Peak memory usage = 79.656MB Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.014s, Peak memory usage = 79.656MB Optimizing Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.027s, Peak memory usage = 79.656MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 79.656MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 79.656MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 79.656MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 79.656MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.032s, Peak memory usage = 79.656MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 79.656MB Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 79.656MB Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 103.605MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.047s, Peak memory usage = 103.605MB Generate output files: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.035s, Peak memory usage = 103.605MB |
Total Time and Memory Usage | CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 103.605MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 28 |
I/O Buf | 27 |
    IBUF | 7 |
    OBUF | 19 |
    TLVDS_IBUF | 1 |
Register | 294 |
    DFFRE | 9 |
    DFFPE | 4 |
    DFFCE | 281 |
LUT | 452 |
    LUT2 | 37 |
    LUT3 | 133 |
    LUT4 | 282 |
INV | 6 |
    INV | 6 |
IOLOGIC | 1 |
    OSIDES32 | 1 |
CLOCK | 5 |
    CLKDIV | 1 |
    DHCE | 4 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 458(458 LUT, 0 ALU) / 23040 | 2% |
Register | 294 / 23685 | 2% |
  --Register as Latch | 0 / 23685 | 0% |
  --Register as FF | 294 / 23685 | 2% |
BSRAM | 0 / 56 | 0% |
Timing
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|
pll_clkout0_i | Base | 10.000 | 100.0 | 0.000 | 5.000 | pll_clkout0_i_ibuf/I | ||
pll_clkout1_i | Base | 10.000 | 100.0 | 0.000 | 5.000 | pll_clkout1_i_ibuf/I | ||
pll_clkout2_i | Base | 10.000 | 100.0 | 0.000 | 5.000 | pll_clkout2_i_ibuf/I | ||
pll_clkout3_i | Base | 10.000 | 100.0 | 0.000 | 5.000 | pll_clkout3_i_ibuf/I | ||
pll_clkin_i | Base | 10.000 | 100.0 | 0.000 | 5.000 | pll_clkin_i_ibuf/I | ||
u_easycdr/u_share_logic/clkdiv_inst/CLKOUT.default_gen_clk | Generated | 40.000 | 25.0 | 0.000 | 20.000 | pll_clkout0_i_ibuf/I | pll_clkout0_i | u_easycdr/u_share_logic/clkdiv_inst/CLKOUT |
Max Frequency Summary:
No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | pll_clkin_i | 100.000(MHz) | 382.592(MHz) | 3 | TOP |
2 | u_easycdr/u_share_logic/clkdiv_inst/CLKOUT.default_gen_clk | 25.000(MHz) | 190.024(MHz) | 6 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | 4.000 |
Data Arrival Time | 1.133 |
Data Required Time | 5.133 |
From | u_easycdr/u_share_logic/cen_s0 |
To | u_easycdr/u_share_logic/dhcen_625m_0 |
Launch Clk | pll_clkin_i[F] |
Latch Clk | pll_clkout0_i[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | pll_clkin_i | |||
0.000 | 0.000 | tCL | RR | 1 | pll_clkin_i_ibuf/I |
0.000 | 0.000 | tINS | RR | 9 | pll_clkin_i_ibuf/O |
0.375 | 0.375 | tNET | RR | 1 | u_easycdr/u_share_logic/cen_s0/CLK |
0.757 | 0.382 | tC2Q | RR | 4 | u_easycdr/u_share_logic/cen_s0/Q |
1.132 | 0.375 | tNET | RR | 1 | u_easycdr/u_share_logic/dhcen_625m_0/CEN |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
5.000 | 0.000 | pll_clkout0_i | |||
5.000 | 0.000 | tCL | FF | 1 | pll_clkout0_i_ibuf/I |
5.000 | 0.000 | tINS | FF | 1 | pll_clkout0_i_ibuf/O |
5.350 | 0.350 | tNET | FF | 3 | u_easycdr/u_share_logic/dhcen_625m_0/CLKIN |
5.315 | -0.035 | tUnc | u_easycdr/u_share_logic/dhcen_625m_0 | ||
5.133 | -0.182 | tSu | 1 | u_easycdr/u_share_logic/dhcen_625m_0 |
Clock Skew: | -0.025 |
Setup Relationship: | 5.000 |
Logic Level: | 1 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.375, 49.505%; tC2Q: 0.382, 50.495% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 2
Path Summary:Slack | 7.386 |
Data Arrival Time | 2.925 |
Data Required Time | 10.311 |
From | u_easycdr/u_share_logic/delay_cnt_0_s0 |
To | u_easycdr/u_share_logic/delay_cnt_0_s0 |
Launch Clk | pll_clkin_i[R] |
Latch Clk | pll_clkin_i[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | pll_clkin_i | |||
0.000 | 0.000 | tCL | RR | 1 | pll_clkin_i_ibuf/I |
0.000 | 0.000 | tINS | RR | 9 | pll_clkin_i_ibuf/O |
0.375 | 0.375 | tNET | RR | 1 | u_easycdr/u_share_logic/delay_cnt_0_s0/CLK |
0.757 | 0.382 | tC2Q | RR | 5 | u_easycdr/u_share_logic/delay_cnt_0_s0/Q |
1.132 | 0.375 | tNET | RR | 1 | u_easycdr/u_share_logic/n38_s1/I0 |
1.659 | 0.526 | tINS | RR | 3 | u_easycdr/u_share_logic/n38_s1/F |
2.034 | 0.375 | tNET | RR | 1 | u_easycdr/u_share_logic/n25_s2/I1 |
2.550 | 0.516 | tINS | RR | 1 | u_easycdr/u_share_logic/n25_s2/F |
2.925 | 0.375 | tNET | RR | 1 | u_easycdr/u_share_logic/delay_cnt_0_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | pll_clkin_i | |||
10.000 | 0.000 | tCL | RR | 1 | pll_clkin_i_ibuf/I |
10.000 | 0.000 | tINS | RR | 9 | pll_clkin_i_ibuf/O |
10.375 | 0.375 | tNET | RR | 1 | u_easycdr/u_share_logic/delay_cnt_0_s0/CLK |
10.311 | -0.064 | tSu | 1 | u_easycdr/u_share_logic/delay_cnt_0_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 3 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Arrival Data Path Delay: | cell: 1.043, 40.882%; route: 1.125, 44.118%; tC2Q: 0.382, 15.000% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 3
Path Summary:Slack | 7.441 |
Data Arrival Time | 2.870 |
Data Required Time | 10.311 |
From | u_easycdr/u_share_logic/delay_cnt_0_s0 |
To | u_easycdr/u_share_logic/delay_cnt_1_s0 |
Launch Clk | pll_clkin_i[R] |
Latch Clk | pll_clkin_i[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | pll_clkin_i | |||
0.000 | 0.000 | tCL | RR | 1 | pll_clkin_i_ibuf/I |
0.000 | 0.000 | tINS | RR | 9 | pll_clkin_i_ibuf/O |
0.375 | 0.375 | tNET | RR | 1 | u_easycdr/u_share_logic/delay_cnt_0_s0/CLK |
0.757 | 0.382 | tC2Q | RR | 5 | u_easycdr/u_share_logic/delay_cnt_0_s0/Q |
1.132 | 0.375 | tNET | RR | 1 | u_easycdr/u_share_logic/n38_s1/I0 |
1.659 | 0.526 | tINS | RR | 3 | u_easycdr/u_share_logic/n38_s1/F |
2.034 | 0.375 | tNET | RR | 1 | u_easycdr/u_share_logic/n24_s1/I2 |
2.495 | 0.461 | tINS | RR | 1 | u_easycdr/u_share_logic/n24_s1/F |
2.870 | 0.375 | tNET | RR | 1 | u_easycdr/u_share_logic/delay_cnt_1_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | pll_clkin_i | |||
10.000 | 0.000 | tCL | RR | 1 | pll_clkin_i_ibuf/I |
10.000 | 0.000 | tINS | RR | 9 | pll_clkin_i_ibuf/O |
10.375 | 0.375 | tNET | RR | 1 | u_easycdr/u_share_logic/delay_cnt_1_s0/CLK |
10.311 | -0.064 | tSu | 1 | u_easycdr/u_share_logic/delay_cnt_1_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 3 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Arrival Data Path Delay: | cell: 0.987, 39.579%; route: 1.125, 45.090%; tC2Q: 0.382, 15.331% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 4
Path Summary:Slack | 8.278 |
Data Arrival Time | 2.034 |
Data Required Time | 10.311 |
From | u_easycdr/u_share_logic/delay_cnt_0_s0 |
To | u_easycdr/u_share_logic/cen_s0 |
Launch Clk | pll_clkin_i[R] |
Latch Clk | pll_clkin_i[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | pll_clkin_i | |||
0.000 | 0.000 | tCL | RR | 1 | pll_clkin_i_ibuf/I |
0.000 | 0.000 | tINS | RR | 9 | pll_clkin_i_ibuf/O |
0.375 | 0.375 | tNET | RR | 1 | u_easycdr/u_share_logic/delay_cnt_0_s0/CLK |
0.757 | 0.382 | tC2Q | RR | 5 | u_easycdr/u_share_logic/delay_cnt_0_s0/Q |
1.132 | 0.375 | tNET | RR | 1 | u_easycdr/u_share_logic/n38_s1/I0 |
1.659 | 0.526 | tINS | RR | 3 | u_easycdr/u_share_logic/n38_s1/F |
2.034 | 0.375 | tNET | RR | 1 | u_easycdr/u_share_logic/cen_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | pll_clkin_i | |||
10.000 | 0.000 | tCL | RR | 1 | pll_clkin_i_ibuf/I |
10.000 | 0.000 | tINS | RR | 9 | pll_clkin_i_ibuf/O |
10.375 | 0.375 | tNET | RR | 1 | u_easycdr/u_share_logic/cen_s0/CLK |
10.311 | -0.064 | tSu | 1 | u_easycdr/u_share_logic/cen_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 2 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Arrival Data Path Delay: | cell: 0.526, 31.726%; route: 0.750, 45.214%; tC2Q: 0.382, 23.060% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 5
Path Summary:Slack | 8.278 |
Data Arrival Time | 2.034 |
Data Required Time | 10.311 |
From | u_easycdr/u_share_logic/delay_cnt_3_s0 |
To | u_easycdr/u_share_logic/delay_cnt_2_s0 |
Launch Clk | pll_clkin_i[R] |
Latch Clk | pll_clkin_i[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | pll_clkin_i | |||
0.000 | 0.000 | tCL | RR | 1 | pll_clkin_i_ibuf/I |
0.000 | 0.000 | tINS | RR | 9 | pll_clkin_i_ibuf/O |
0.375 | 0.375 | tNET | RR | 1 | u_easycdr/u_share_logic/delay_cnt_3_s0/CLK |
0.757 | 0.382 | tC2Q | RR | 3 | u_easycdr/u_share_logic/delay_cnt_3_s0/Q |
1.132 | 0.375 | tNET | RR | 1 | u_easycdr/u_share_logic/n23_s1/I0 |
1.659 | 0.526 | tINS | RR | 1 | u_easycdr/u_share_logic/n23_s1/F |
2.034 | 0.375 | tNET | RR | 1 | u_easycdr/u_share_logic/delay_cnt_2_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | pll_clkin_i | |||
10.000 | 0.000 | tCL | RR | 1 | pll_clkin_i_ibuf/I |
10.000 | 0.000 | tINS | RR | 9 | pll_clkin_i_ibuf/O |
10.375 | 0.375 | tNET | RR | 1 | u_easycdr/u_share_logic/delay_cnt_2_s0/CLK |
10.311 | -0.064 | tSu | 1 | u_easycdr/u_share_logic/delay_cnt_2_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 2 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Arrival Data Path Delay: | cell: 0.526, 31.726%; route: 0.750, 45.214%; tC2Q: 0.382, 23.060% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |