Timing Messages

Report Title Timing Analysis Report
Design File E:\IP_Release\EasyCDR\1.2\ref_design\Gowin_EasyCDR_RefDesign\project\impl\gwsynthesis\fpga_project.vg
Physical Constraints File E:\IP_Release\EasyCDR\1.2\ref_design\Gowin_EasyCDR_RefDesign\project\src\fpga_project.cst
Timing Constraint File E:\IP_Release\EasyCDR\1.2\ref_design\Gowin_EasyCDR_RefDesign\project\src\fpga_project.sdc
Tool Version V1.9.9.03 (64-bit)
Part Number GW5A-LV25UG324ES
Device GW5A-25
Device Version A
Created Time Wed Apr 24 16:24:04 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model Slow 0.855V 0C ES
Hold Delay Model Fast 0.945V 85C ES
Numbers of Paths Analyzed 3116
Numbers of Endpoints Analyzed 2254
Numbers of Falling Endpoints 3
Numbers of Setup Violated Endpoints 0
Numbers of Hold Violated Endpoints 0

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Objects
tck_pad Base 50.000 20.000 0.000 25.000 tck_pad_i
board_clk Base 20.000 50.000 0.000 10.000 board_clk_ibuf/I
hclk_0_rx Generated 2.000 500.000 0.000 1.000 board_clk_ibuf/I board_clk u_motivation_response/u_pll_hclk/PLLA_inst/CLKOUT0
hclk_180_rx Generated 2.000 500.000 1.000 0.000 board_clk_ibuf/I board_clk u_motivation_response/u_pll_hclk/PLLA_inst/CLKOUT2
hclk_90_rx Generated 2.000 500.000 0.500 1.500 board_clk_ibuf/I board_clk u_motivation_response/u_pll_hclk/PLLA_inst/CLKOUT1
hclk_0_tx Generated 2.000 500.000 0.000 1.000 board_clk_ibuf/I board_clk u_motivation_response/u_pll_hclk_tx/PLLA_inst/CLKOUT0
pclk_rx Generated 8.000 125.000 0.000 4.000 u_motivation_response/u_pll_hclk/PLLA_inst/CLKOUT0 hclk_0_rx u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
hclk_270_rx Generated 2.000 500.000 1.500 0.500 board_clk_ibuf/I board_clk u_motivation_response/u_pll_hclk/PLLA_inst/CLKOUT3
pclk_tx Generated 10.000 100.000 0.000 5.000 u_motivation_response/u_pll_hclk_tx/PLLA_inst/CLKOUT0 hclk_0_tx u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 tck_pad 20.000(MHz) 135.204(MHz) 6 TOP
2 board_clk 50.000(MHz) 271.163(MHz) 6 TOP
3 pclk_rx 125.000(MHz) 145.680(MHz) 5 TOP
4 pclk_tx 100.000(MHz) 217.465(MHz) 6 TOP

No timing paths to get frequency of hclk_0_rx!

No timing paths to get frequency of hclk_180_rx!

No timing paths to get frequency of hclk_90_rx!

No timing paths to get frequency of hclk_0_tx!

No timing paths to get frequency of hclk_270_rx!

Total Negative Slack Summary:

Clock Name Analysis Type Endpoints TNS Number of Endpoints
tck_pad Setup 0.000 0
tck_pad Hold 0.000 0
board_clk Setup 0.000 0
board_clk Hold 0.000 0
hclk_0_rx Setup 0.000 0
hclk_0_rx Hold 0.000 0
hclk_180_rx Setup 0.000 0
hclk_180_rx Hold 0.000 0
hclk_90_rx Setup 0.000 0
hclk_90_rx Hold 0.000 0
hclk_0_tx Setup 0.000 0
hclk_0_tx Hold 0.000 0
pclk_rx Setup 0.000 0
pclk_rx Hold 0.000 0
hclk_270_rx Setup 0.000 0
hclk_270_rx Hold 0.000 0
pclk_tx Setup 0.000 0
pclk_tx Hold 0.000 0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 1.136 u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/remained_cnt_1_s1/Q u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/o_dout_6_s0/D pclk_rx:[R] pclk_rx:[R] 8.000 -0.034 6.835
2 2.105 u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/remained_cnt_1_s1/Q u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/o_dout_7_s0/D pclk_rx:[R] pclk_rx:[R] 8.000 0.000 5.831
3 2.358 u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/remained_cnt_3_s0/Q u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/o_dout_2_s0/D pclk_rx:[R] pclk_rx:[R] 8.000 -0.016 5.594
4 2.621 u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/remained_cnt_1_s1/Q u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/o_dout_0_s0/D pclk_rx:[R] pclk_rx:[R] 8.000 -0.006 5.321
5 2.640 u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/remained_cnt_3_s0/Q u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/o_dout_1_s0/D pclk_rx:[R] pclk_rx:[R] 8.000 0.011 5.285
6 2.664 u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_cdr/o_dout_8_s2/Q u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/o_dout_4_s0/D pclk_rx:[R] pclk_rx:[R] 8.000 -0.019 5.291
7 2.769 u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/remained_cnt_0_s0/Q u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/o_dout_5_s0/D pclk_rx:[R] pclk_rx:[R] 8.000 0.034 5.133
8 2.969 u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/remained_cnt_0_s0/Q u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/o_dout_3_s0/D pclk_rx:[R] pclk_rx:[R] 8.000 0.025 4.943
9 3.081 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CE pclk_rx:[R] pclk_rx:[R] 8.000 -0.049 4.658
10 3.146 u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/remained_cnt_1_s1/Q u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/o_dout_9_s0/D pclk_rx:[R] pclk_rx:[R] 8.000 0.000 4.790
11 3.233 gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s/DO[0] gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CE pclk_rx:[R] pclk_rx:[R] 8.000 -0.034 4.490
12 3.350 u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/remained_cnt_1_s1/Q u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/o_dout_8_s0/D pclk_rx:[R] pclk_rx:[R] 8.000 0.000 4.586
13 3.417 u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_word_align/o_align_dat_1_s0/Q u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_decoder_8b10b/dout_kerr_s0/D pclk_rx:[R] pclk_rx:[R] 8.000 -0.014 4.534
14 3.632 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/D pclk_rx:[R] pclk_rx:[R] 8.000 0.000 4.304
15 3.771 gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_8_s0/D pclk_rx:[R] pclk_rx:[R] 8.000 0.038 4.128
16 3.771 gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s/DO[0] gw_gao_inst_0/u_la0_top/triger_s0/D pclk_rx:[R] pclk_rx:[R] 8.000 -0.043 4.209
17 3.777 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/D pclk_rx:[R] pclk_rx:[R] 8.000 0.000 4.159
18 3.777 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/D pclk_rx:[R] pclk_rx:[R] 8.000 0.000 4.159
19 3.873 u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_word_align/k_compare_d0_5_s1/Q u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_word_align/cur_state.PRE_ALIGN_s1/CE pclk_rx:[R] pclk_rx:[R] 8.000 0.022 3.794
20 3.906 gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_9_s0/D pclk_rx:[R] pclk_rx:[R] 8.000 0.046 3.985
21 3.968 gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s/DO[0] gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s1/CE pclk_rx:[R] pclk_rx:[R] 8.000 -0.027 3.747
22 3.968 gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s/DO[0] gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CE pclk_rx:[R] pclk_rx:[R] 8.000 -0.027 3.747
23 3.968 gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s/DO[0] gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CE pclk_rx:[R] pclk_rx:[R] 8.000 -0.027 3.747
24 3.968 gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s/DO[0] gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CE pclk_rx:[R] pclk_rx:[R] 8.000 -0.027 3.747
25 4.010 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/D pclk_rx:[R] pclk_rx:[R] 8.000 0.000 3.926

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.245 gw_gao_inst_0/u_la0_top/expression0_data_s0/Q gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s/DI[0] tck_pad:[R] tck_pad:[R] 0.000 0.019 0.475
2 0.247 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_3_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[3] pclk_rx:[R] pclk_rx:[R] 0.000 -0.010 0.506
3 0.275 gw_gao_inst_0/u_la0_top/word_count_4_s0/Q gw_gao_inst_0/u_la0_top/word_count_4_s0/D tck_pad:[R] tck_pad:[R] 0.000 0.000 0.300
4 0.275 gw_gao_inst_0/u_la0_top/word_count_13_s0/Q gw_gao_inst_0/u_la0_top/word_count_13_s0/D tck_pad:[R] tck_pad:[R] 0.000 0.000 0.300
5 0.275 gw_gao_inst_0/u_la0_top/word_count_14_s0/Q gw_gao_inst_0/u_la0_top/word_count_14_s0/D tck_pad:[R] tck_pad:[R] 0.000 0.000 0.300
6 0.275 gw_gao_inst_0/u_la0_top/address_counter_9_s0/Q gw_gao_inst_0/u_la0_top/address_counter_9_s0/D tck_pad:[R] tck_pad:[R] 0.000 0.000 0.300
7 0.275 u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_word_align/align_cnt_full_s6/Q u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_word_align/align_cnt_full_s6/D pclk_rx:[R] pclk_rx:[R] 0.000 0.000 0.300
8 0.275 u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_word_align/align_cnt_1_s1/Q u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_word_align/align_cnt_1_s1/D pclk_rx:[R] pclk_rx:[R] 0.000 0.000 0.300
9 0.275 u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_word_align/align_cnt_3_s1/Q u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_word_align/align_cnt_3_s1/D pclk_rx:[R] pclk_rx:[R] 0.000 0.000 0.300
10 0.275 u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_word_align/wait_state_cnt_0_s0/Q u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_word_align/wait_state_cnt_0_s0/D pclk_rx:[R] pclk_rx:[R] 0.000 0.000 0.300
11 0.275 u_motivation_response/u_prbs_inspector/dat_corr_cnt_3_s1/Q u_motivation_response/u_prbs_inspector/dat_corr_cnt_3_s1/D pclk_rx:[R] pclk_rx:[R] 0.000 0.000 0.300
12 0.275 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/D pclk_rx:[R] pclk_rx:[R] 0.000 0.000 0.300
13 0.275 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/D pclk_rx:[R] pclk_rx:[R] 0.000 0.000 0.300
14 0.275 gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/Q gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/D pclk_rx:[R] pclk_rx:[R] 0.000 0.000 0.300
15 0.275 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/D pclk_rx:[R] pclk_rx:[R] 0.000 0.000 0.300
16 0.275 u_EasyCDR_Top/u_easycdr/u_share_logic/delay_cnt_1_s0/Q u_EasyCDR_Top/u_easycdr/u_share_logic/delay_cnt_1_s0/D board_clk:[R] board_clk:[R] 0.000 0.000 0.300
17 0.275 u_motivation_response/rstn_fabric_cnt_9_s0/Q u_motivation_response/rstn_fabric_cnt_9_s0/D board_clk:[R] board_clk:[R] 0.000 0.000 0.300
18 0.275 u_motivation_response/rstn_fabric_cnt_10_s0/Q u_motivation_response/rstn_fabric_cnt_10_s0/D board_clk:[R] board_clk:[R] 0.000 0.000 0.300
19 0.275 u_motivation_response/rstn_fabric_cnt_11_s0/Q u_motivation_response/rstn_fabric_cnt_11_s0/D board_clk:[R] board_clk:[R] 0.000 0.000 0.300
20 0.275 gw_gao_inst_0/u_la0_top/word_count_5_s0/Q gw_gao_inst_0/u_la0_top/word_count_5_s0/D tck_pad:[R] tck_pad:[R] 0.000 0.000 0.300
21 0.275 gw_gao_inst_0/u_la0_top/address_counter_1_s0/Q gw_gao_inst_0/u_la0_top/address_counter_1_s0/D tck_pad:[R] tck_pad:[R] 0.000 0.000 0.300
22 0.278 gw_gao_inst_0/u_la0_top/word_count_10_s0/Q gw_gao_inst_0/u_la0_top/word_count_10_s0/D tck_pad:[R] tck_pad:[R] 0.000 0.000 0.303
23 0.278 gw_gao_inst_0/u_la0_top/address_counter_7_s0/Q gw_gao_inst_0/u_la0_top/address_counter_7_s0/D tck_pad:[R] tck_pad:[R] 0.000 0.000 0.303
24 0.278 u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_word_align/decode_err_cnt_full_s6/Q u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_word_align/decode_err_cnt_full_s6/D pclk_rx:[R] pclk_rx:[R] 0.000 0.000 0.303
25 0.278 u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_cdr/status_0_s0/Q u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_cdr/status_0_s0/D pclk_rx:[R] pclk_rx:[R] 0.000 0.000 0.303

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 1.572 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_0_s0/CLEAR pclk_rx:[F] pclk_rx:[R] 4.000 -0.047 2.128
2 1.710 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR pclk_rx:[F] pclk_rx:[R] 4.000 -0.045 1.988
3 1.710 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLEAR pclk_rx:[F] pclk_rx:[R] 4.000 -0.045 1.988
4 1.710 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLEAR pclk_rx:[F] pclk_rx:[R] 4.000 -0.045 1.988
5 1.710 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLEAR pclk_rx:[F] pclk_rx:[R] 4.000 -0.045 1.988
6 1.710 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLEAR pclk_rx:[F] pclk_rx:[R] 4.000 -0.045 1.988
7 1.719 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_1/trig_dly_in_0_s0/CLEAR pclk_rx:[F] pclk_rx:[R] 4.000 -0.054 1.988
8 1.719 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR pclk_rx:[F] pclk_rx:[R] 4.000 -0.054 1.988
9 1.719 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR pclk_rx:[F] pclk_rx:[R] 4.000 -0.054 1.988
10 1.719 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLEAR pclk_rx:[F] pclk_rx:[R] 4.000 -0.054 1.988
11 1.719 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/start_reg_s0/CLEAR pclk_rx:[F] pclk_rx:[R] 4.000 -0.054 1.988
12 1.747 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET pclk_rx:[F] pclk_rx:[R] 4.000 -0.049 1.955
13 1.756 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s1/CLEAR pclk_rx:[F] pclk_rx:[R] 4.000 -0.047 1.944
14 1.756 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR pclk_rx:[F] pclk_rx:[R] 4.000 -0.047 1.944
15 1.756 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLEAR pclk_rx:[F] pclk_rx:[R] 4.000 -0.047 1.944
16 1.756 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR pclk_rx:[F] pclk_rx:[R] 4.000 -0.047 1.944
17 1.765 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_1/match_sep_s0/CLEAR pclk_rx:[F] pclk_rx:[R] 4.000 -0.056 1.944
18 1.769 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLEAR pclk_rx:[F] pclk_rx:[R] 4.000 -0.052 1.935
19 1.769 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLEAR pclk_rx:[F] pclk_rx:[R] 4.000 -0.052 1.935
20 1.769 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLEAR pclk_rx:[F] pclk_rx:[R] 4.000 -0.052 1.935
21 1.769 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLEAR pclk_rx:[F] pclk_rx:[R] 4.000 -0.052 1.935
22 1.776 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR pclk_rx:[F] pclk_rx:[R] 4.000 -0.049 1.926
23 1.776 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR pclk_rx:[F] pclk_rx:[R] 4.000 -0.049 1.926
24 1.776 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0/CLEAR pclk_rx:[F] pclk_rx:[R] 4.000 -0.049 1.926
25 1.964 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR pclk_rx:[F] pclk_rx:[R] 4.000 -0.054 1.743

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.281 u_EasyCDR_Top/u_easycdr/u_share_logic/rst_n_s0/Q u_EasyCDR_Top/u_easycdr/u_share_logic/delay_cnt_0_s0/CLEAR board_clk:[R] board_clk:[R] 0.000 0.000 0.228
2 0.281 u_EasyCDR_Top/u_easycdr/u_share_logic/rst_n_s0/Q u_EasyCDR_Top/u_easycdr/u_share_logic/delay_cnt_1_s0/CLEAR board_clk:[R] board_clk:[R] 0.000 0.000 0.228
3 0.281 u_EasyCDR_Top/u_easycdr/u_share_logic/rst_n_s0/Q u_EasyCDR_Top/u_easycdr/u_share_logic/delay_cnt_2_s0/CLEAR board_clk:[R] board_clk:[R] 0.000 0.000 0.228
4 0.281 u_EasyCDR_Top/u_easycdr/u_share_logic/rst_n_s0/Q u_EasyCDR_Top/u_easycdr/u_share_logic/delay_cnt_3_s0/CLEAR board_clk:[R] board_clk:[R] 0.000 0.000 0.228
5 0.387 u_EasyCDR_Top/u_easycdr/u_share_logic/rst_n_s0/Q u_EasyCDR_Top/u_easycdr/u_share_logic/cen_s0/PRESET board_clk:[R] board_clk:[R] 0.000 -0.004 0.338
6 0.387 u_EasyCDR_Top/u_easycdr/u_share_logic/rst_n_s0/Q u_EasyCDR_Top/u_easycdr/u_share_logic/reset_o_s0/PRESET board_clk:[R] board_clk:[R] 0.000 -0.004 0.338
7 0.546 u_EasyCDR_Top/u_easycdr/u_share_logic/rst_n_s0/Q u_EasyCDR_Top/u_easycdr/u_share_logic/resetn_s0/CLEAR board_clk:[R] board_clk:[R] 0.000 -0.029 0.522
8 4.411 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLEAR pclk_rx:[F] pclk_rx:[R] -4.000 -0.005 0.363
9 4.411 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR pclk_rx:[F] pclk_rx:[R] -4.000 -0.005 0.363
10 4.411 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR pclk_rx:[F] pclk_rx:[R] -4.000 -0.005 0.363
11 4.415 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR pclk_rx:[F] pclk_rx:[R] -4.000 -0.001 0.363
12 4.415 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR pclk_rx:[F] pclk_rx:[R] -4.000 -0.001 0.363
13 4.415 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR pclk_rx:[F] pclk_rx:[R] -4.000 -0.001 0.363
14 4.417 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR pclk_rx:[F] pclk_rx:[R] -4.000 0.007 0.357
15 4.421 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR pclk_rx:[F] pclk_rx:[R] -4.000 0.000 0.367
16 4.422 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR pclk_rx:[F] pclk_rx:[R] -4.000 0.002 0.367
17 4.422 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR pclk_rx:[F] pclk_rx:[R] -4.000 0.002 0.367
18 4.422 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR pclk_rx:[F] pclk_rx:[R] -4.000 0.002 0.367
19 4.422 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR pclk_rx:[F] pclk_rx:[R] -4.000 0.002 0.367
20 4.515 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR pclk_rx:[F] pclk_rx:[R] -4.000 -0.001 0.463
21 4.515 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR pclk_rx:[F] pclk_rx:[R] -4.000 -0.001 0.463
22 4.519 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET pclk_rx:[F] pclk_rx:[R] -4.000 -0.001 0.467
23 4.519 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR pclk_rx:[F] pclk_rx:[R] -4.000 -0.001 0.467
24 4.519 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR pclk_rx:[F] pclk_rx:[R] -4.000 -0.001 0.467
25 4.519 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR pclk_rx:[F] pclk_rx:[R] -4.000 -0.001 0.467

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number Slack Actual Width Required Width Type Clock Objects
1 2.175 3.175 1.000 Low Pulse Width pclk_rx gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s
2 2.176 3.176 1.000 High Pulse Width pclk_rx gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s
3 2.181 3.181 1.000 Low Pulse Width pclk_rx gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
4 2.182 3.182 1.000 High Pulse Width pclk_rx gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
5 2.908 3.158 0.250 Low Pulse Width pclk_rx gw_gao_inst_0/u_la0_top/triger_s0
6 2.908 3.158 0.250 Low Pulse Width pclk_rx gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3
7 2.908 3.158 0.250 Low Pulse Width pclk_rx gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1
8 2.909 3.159 0.250 Low Pulse Width pclk_rx u_EasyCDR_Top/u_easycdr/u_easycdr_32/dout_en_s0
9 2.909 3.159 0.250 Low Pulse Width pclk_rx u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_word_align/data_location_3_s2
10 2.909 3.159 0.250 Low Pulse Width pclk_rx u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_decoder_8b10b/dout_dat_6_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 1.136
Data Arrival Time 8.145
Data Required Time 9.281
From u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/remained_cnt_1_s1
To u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/o_dout_6_s0
Launch Clk pclk_rx:[R]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
1.310 1.310 tNET RR 1 R18C24[1][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/remained_cnt_1_s1/CLK
1.692 0.382 tC2Q RR 38 R18C24[1][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/remained_cnt_1_s1/Q
2.949 1.256 tNET RR 1 R20C27[2][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n195_s1/I0
3.465 0.516 tINS RR 13 R20C27[2][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n195_s1/F
5.441 1.976 tNET RR 1 R18C21[2][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n192_s12/I0
5.968 0.526 tINS RR 1 R18C21[2][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n192_s12/F
7.010 1.043 tNET RR 1 R20C27[1][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n192_s2/I1
7.471 0.461 tINS RR 1 R20C27[1][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n192_s2/F
7.629 0.157 tNET RR 1 R20C26[1][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n192_s0/I2
8.145 0.516 tINS RR 1 R20C26[1][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n192_s0/F
8.145 0.000 tNET RR 1 R20C26[1][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/o_dout_6_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk_rx
8.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
9.344 1.344 tNET RR 1 R20C26[1][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/o_dout_6_s0/CLK
9.281 -0.064 tSu 1 R20C26[1][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/o_dout_6_s0

Path Statistics:

Clock Skew 0.034
Setup Relationship 8.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.310, 100.000%
Arrival Data Path Delay cell: 2.020, 29.554%; route: 4.432, 64.850%; tC2Q: 0.382, 5.596%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.344, 100.000%

Path2

Path Summary:

Slack 2.105
Data Arrival Time 7.141
Data Required Time 9.246
From u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/remained_cnt_1_s1
To u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/o_dout_7_s0
Launch Clk pclk_rx:[R]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
1.310 1.310 tNET RR 1 R18C24[1][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/remained_cnt_1_s1/CLK
1.692 0.382 tC2Q RR 38 R18C24[1][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/remained_cnt_1_s1/Q
2.949 1.256 tNET RR 1 R20C27[2][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n195_s1/I0
3.465 0.516 tINS RR 13 R20C27[2][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n195_s1/F
5.576 2.111 tNET RR 1 R17C21[0][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n191_s4/I0
6.102 0.526 tINS RR 1 R17C21[0][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n191_s4/F
6.260 0.157 tNET RR 1 R17C22[0][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n191_s10/I3
6.721 0.461 tINS RR 1 R17C22[0][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n191_s10/F
6.879 0.157 tNET RR 1 R18C22[0][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n191_s0/I0
7.141 0.262 tINS RR 1 R18C22[0][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n191_s0/F
7.141 0.000 tNET RR 1 R18C22[0][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/o_dout_7_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk_rx
8.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
9.310 1.310 tNET RR 1 R18C22[0][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/o_dout_7_s0/CLK
9.246 -0.064 tSu 1 R18C22[0][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/o_dout_7_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 8.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.310, 100.000%
Arrival Data Path Delay cell: 1.766, 30.289%; route: 3.683, 63.151%; tC2Q: 0.382, 6.559%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.310, 100.000%

Path3

Path Summary:

Slack 2.358
Data Arrival Time 6.913
Data Required Time 9.271
From u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/remained_cnt_3_s0
To u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/o_dout_2_s0
Launch Clk pclk_rx:[R]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
1.319 1.319 tNET RR 1 R18C27[1][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/remained_cnt_3_s0/CLK
1.687 0.368 tC2Q RF 25 R18C27[1][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/remained_cnt_3_s0/Q
2.748 1.061 tNET FF 1 R17C21[3][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n194_s6/I0
3.163 0.415 tINS FR 6 R17C21[3][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n194_s6/F
4.453 1.290 tNET RR 1 R16C25[0][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n196_s9/I0
4.716 0.262 tINS RR 1 R16C25[0][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n196_s9/F
4.718 0.003 tNET RR 1 R16C25[3][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n196_s6/I2
5.239 0.521 tINS RR 2 R16C25[3][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n196_s6/F
5.589 0.350 tNET RR 1 R18C25[3][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n196_s2/I0
5.854 0.265 tINS RR 1 R18C25[3][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n196_s2/F
6.397 0.543 tNET RR 1 R20C25[2][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n196_s0/I1
6.913 0.516 tINS RR 1 R20C25[2][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n196_s0/F
6.913 0.000 tNET RR 1 R20C25[2][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/o_dout_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk_rx
8.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
9.335 1.335 tNET RR 1 R20C25[2][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/o_dout_2_s0/CLK
9.271 -0.064 tSu 1 R20C25[2][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/o_dout_2_s0

Path Statistics:

Clock Skew 0.016
Setup Relationship 8.000
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.319, 100.000%
Arrival Data Path Delay cell: 1.980, 35.397%; route: 3.246, 58.034%; tC2Q: 0.368, 6.570%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.335, 100.000%

Path4

Path Summary:

Slack 2.621
Data Arrival Time 6.631
Data Required Time 9.252
From u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/remained_cnt_1_s1
To u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/o_dout_0_s0
Launch Clk pclk_rx:[R]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
1.310 1.310 tNET RR 1 R18C24[1][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/remained_cnt_1_s1/CLK
1.692 0.382 tC2Q RR 38 R18C24[1][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/remained_cnt_1_s1/Q
2.949 1.256 tNET RR 1 R20C27[2][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n195_s1/I0
3.465 0.516 tINS RR 13 R20C27[2][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n195_s1/F
4.727 1.263 tNET RR 1 R16C26[3][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n198_s9/I0
5.017 0.290 tINS RF 1 R16C26[3][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n198_s9/F
5.023 0.005 tNET FF 1 R16C26[2][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n198_s5/I2
5.484 0.461 tINS FR 1 R16C26[2][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n198_s5/F
5.486 0.003 tNET RR 1 R16C26[0][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n198_s2/I1
6.012 0.526 tINS RR 1 R16C26[0][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n198_s2/F
6.170 0.157 tNET RR 1 R16C27[0][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n198_s0/I3
6.631 0.461 tINS RR 1 R16C27[0][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n198_s0/F
6.631 0.000 tNET RR 1 R16C27[0][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/o_dout_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk_rx
8.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
9.316 1.316 tNET RR 1 R16C27[0][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/o_dout_0_s0/CLK
9.252 -0.064 tSu 1 R16C27[0][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/o_dout_0_s0

Path Statistics:

Clock Skew 0.006
Setup Relationship 8.000
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.310, 100.000%
Arrival Data Path Delay cell: 2.255, 42.377%; route: 2.684, 50.435%; tC2Q: 0.382, 7.188%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.316, 100.000%

Path5

Path Summary:

Slack 2.640
Data Arrival Time 6.604
Data Required Time 9.244
From u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/remained_cnt_3_s0
To u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/o_dout_1_s0
Launch Clk pclk_rx:[R]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
1.319 1.319 tNET RR 1 R18C27[1][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/remained_cnt_3_s0/CLK
1.687 0.368 tC2Q RF 25 R18C27[1][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/remained_cnt_3_s0/Q
2.748 1.061 tNET FF 1 R17C21[3][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n194_s6/I0
3.163 0.415 tINS FR 6 R17C21[3][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n194_s6/F
4.453 1.290 tNET RR 1 R16C25[0][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n196_s9/I0
4.716 0.262 tINS RR 1 R16C25[0][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n196_s9/F
4.718 0.003 tNET RR 1 R16C25[3][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n196_s6/I2
5.239 0.521 tINS RR 2 R16C25[3][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n196_s6/F
5.399 0.160 tNET RR 1 R17C25[2][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n197_s4/I3
5.926 0.526 tINS RR 1 R17C25[2][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n197_s4/F
6.083 0.157 tNET RR 1 R17C26[3][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n197_s0/I3
6.604 0.521 tINS RR 1 R17C26[3][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n197_s0/F
6.604 0.000 tNET RR 1 R17C26[3][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/o_dout_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk_rx
8.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
9.308 1.308 tNET RR 1 R17C26[3][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/o_dout_1_s0/CLK
9.244 -0.064 tSu 1 R17C26[3][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/o_dout_1_s0

Path Statistics:

Clock Skew -0.011
Setup Relationship 8.000
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.319, 100.000%
Arrival Data Path Delay cell: 2.246, 42.502%; route: 2.671, 50.544%; tC2Q: 0.368, 6.954%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.308, 100.000%

Path6

Path Summary:

Slack 2.664
Data Arrival Time 6.580
Data Required Time 9.244
From u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_cdr/o_dout_8_s2
To u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/o_dout_4_s0
Launch Clk pclk_rx:[R]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
1.289 1.289 tNET RR 1 R14C25[0][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_cdr/o_dout_8_s2/CLK
1.672 0.382 tC2Q RR 4 R14C25[0][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_cdr/o_dout_8_s2/Q
2.980 1.309 tNET RR 1 R20C25[0][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n198_s3/I1
3.442 0.461 tINS RR 4 R20C25[0][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n198_s3/F
4.528 1.086 tNET RR 1 R17C27[3][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n194_s13/I0
4.943 0.415 tINS RR 1 R17C27[3][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n194_s13/F
4.945 0.003 tNET RR 1 R17C27[3][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n194_s9/I3
5.443 0.498 tINS RR 1 R17C27[3][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n194_s9/F
5.445 0.003 tNET RR 1 R17C27[0][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n194_s3/I0
5.907 0.461 tINS RR 1 R17C27[0][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n194_s3/F
6.064 0.157 tNET RR 1 R17C26[0][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n194_s0/I3
6.580 0.516 tINS RR 1 R17C26[0][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n194_s0/F
6.580 0.000 tNET RR 1 R17C26[0][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/o_dout_4_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk_rx
8.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
9.308 1.308 tNET RR 1 R17C26[0][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/o_dout_4_s0/CLK
9.244 -0.064 tSu 1 R17C26[0][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/o_dout_4_s0

Path Statistics:

Clock Skew 0.019
Setup Relationship 8.000
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.289, 100.000%
Arrival Data Path Delay cell: 2.351, 44.437%; route: 2.558, 48.335%; tC2Q: 0.382, 7.229%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.308, 100.000%

Path7

Path Summary:

Slack 2.769
Data Arrival Time 6.467
Data Required Time 9.237
From u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/remained_cnt_0_s0
To u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/o_dout_5_s0
Launch Clk pclk_rx:[R]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
1.335 1.335 tNET RR 1 R20C25[3][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/remained_cnt_0_s0/CLK
1.717 0.382 tC2Q RR 45 R20C25[3][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/remained_cnt_0_s0/Q
2.824 1.106 tNET RR 1 R17C23[2][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n189_s6/I2
3.285 0.461 tINS RR 10 R17C23[2][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n189_s6/F
4.062 0.777 tNET RR 1 R18C27[2][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n193_s9/I1
4.589 0.526 tINS RR 1 R18C27[2][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n193_s9/F
4.746 0.157 tNET RR 1 R18C26[2][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n193_s5/I3
5.262 0.516 tINS RR 2 R18C26[2][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n193_s5/F
5.267 0.005 tNET RR 1 R18C26[1][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n193_s1/I2
5.794 0.526 tINS RR 1 R18C26[1][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n193_s1/F
5.951 0.157 tNET RR 1 R18C25[1][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n193_s0/I0
6.467 0.516 tINS RR 1 R18C25[1][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n193_s0/F
6.467 0.000 tNET RR 1 R18C25[1][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/o_dout_5_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk_rx
8.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
9.301 1.301 tNET RR 1 R18C25[1][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/o_dout_5_s0/CLK
9.237 -0.064 tSu 1 R18C25[1][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/o_dout_5_s0

Path Statistics:

Clock Skew -0.034
Setup Relationship 8.000
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.335, 100.000%
Arrival Data Path Delay cell: 2.546, 49.610%; route: 2.204, 42.937%; tC2Q: 0.382, 7.453%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.301, 100.000%

Path8

Path Summary:

Slack 2.969
Data Arrival Time 6.277
Data Required Time 9.246
From u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/remained_cnt_0_s0
To u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/o_dout_3_s0
Launch Clk pclk_rx:[R]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
1.335 1.335 tNET RR 1 R20C25[3][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/remained_cnt_0_s0/CLK
1.717 0.382 tC2Q RR 45 R20C25[3][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/remained_cnt_0_s0/Q
2.824 1.106 tNET RR 1 R17C23[2][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n189_s6/I2
3.285 0.461 tINS RR 10 R17C23[2][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n189_s6/F
3.808 0.522 tNET RR 1 R16C25[3][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n195_s9/I3
4.223 0.415 tINS RR 2 R16C25[3][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n195_s9/F
4.383 0.160 tNET RR 1 R17C25[3][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n195_s5/I3
4.904 0.521 tINS RR 1 R17C25[3][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n195_s5/F
4.906 0.003 tNET RR 1 R17C25[3][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n195_s3/I2
5.404 0.498 tINS RR 1 R17C25[3][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n195_s3/F
5.751 0.347 tNET RR 1 R18C24[0][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n195_s0/I2
6.278 0.526 tINS RR 1 R18C24[0][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n195_s0/F
6.278 0.000 tNET RR 1 R18C24[0][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/o_dout_3_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk_rx
8.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
9.310 1.310 tNET RR 1 R18C24[0][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/o_dout_3_s0/CLK
9.246 -0.064 tSu 1 R18C24[0][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/o_dout_3_s0

Path Statistics:

Clock Skew -0.025
Setup Relationship 8.000
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.335, 100.000%
Arrival Data Path Delay cell: 2.421, 48.988%; route: 2.139, 43.273%; tC2Q: 0.382, 7.739%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.310, 100.000%

Path9

Path Summary:

Slack 3.081
Data Arrival Time 5.962
Data Required Time 9.043
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1
Launch Clk pclk_rx:[R]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
1.304 1.304 tNET RR 1 R15C32[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK
1.687 0.382 tC2Q RR 5 R15C32[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/Q
2.182 0.495 tNET RR 1 R16C36[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n285_s9/I0
2.698 0.516 tINS RR 1 R16C36[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n285_s9/F
3.201 0.502 tNET RR 1 R15C32[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n285_s5/I2
3.662 0.461 tINS RR 2 R15C32[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n285_s5/F
3.822 0.160 tNET RR 1 R15C31[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n285_s4/I0
4.343 0.521 tINS RR 10 R15C31[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n285_s4/F
4.712 0.369 tNET RR 1 R17C31[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s4/I0
5.228 0.516 tINS RR 1 R17C31[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s4/F
5.962 0.734 tNET RR 1 R20C31[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk_rx
8.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
9.354 1.354 tNET RR 1 R20C31[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK
9.043 -0.311 tSu 1 R20C31[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1

Path Statistics:

Clock Skew 0.049
Setup Relationship 8.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.304, 100.000%
Arrival Data Path Delay cell: 2.015, 43.264%; route: 2.260, 48.524%; tC2Q: 0.382, 8.213%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.354, 100.000%

Path10

Path Summary:

Slack 3.146
Data Arrival Time 6.100
Data Required Time 9.246
From u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/remained_cnt_1_s1
To u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/o_dout_9_s0
Launch Clk pclk_rx:[R]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
1.310 1.310 tNET RR 1 R18C24[1][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/remained_cnt_1_s1/CLK
1.692 0.382 tC2Q RR 38 R18C24[1][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/remained_cnt_1_s1/Q
2.949 1.256 tNET RR 1 R20C27[2][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n195_s1/I0
3.465 0.516 tINS RR 13 R20C27[2][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n195_s1/F
5.115 1.650 tNET RR 1 R18C22[3][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n189_s1/I3
5.636 0.521 tINS RR 1 R18C22[3][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n189_s1/F
5.639 0.003 tNET RR 1 R18C22[2][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n189_s0/I0
6.100 0.461 tINS RR 1 R18C22[2][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n189_s0/F
6.100 0.000 tNET RR 1 R18C22[2][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/o_dout_9_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk_rx
8.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
9.310 1.310 tNET RR 1 R18C22[2][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/o_dout_9_s0/CLK
9.246 -0.064 tSu 1 R18C22[2][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/o_dout_9_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 8.000
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.310, 100.000%
Arrival Data Path Delay cell: 1.499, 31.289%; route: 2.909, 60.725%; tC2Q: 0.382, 7.985%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.310, 100.000%

Path11

Path Summary:

Slack 3.233
Data Arrival Time 5.800
Data Required Time 9.033
From gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s
To gw_gao_inst_0/u_la0_top/trigger_seq_start_s1
Launch Clk pclk_rx:[R]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
1.310 1.310 tNET RR 1 BSRAM_R28[8] gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s/CLKB
3.570 2.260 tC2Q RR 2 BSRAM_R28[8] gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s/DO[0]
4.247 0.676 tNET RR 1 R23C31[0][B] gw_gao_inst_0/u_la0_top/n1784_s1/I1
4.708 0.461 tINS RR 2 R23C31[0][B] gw_gao_inst_0/u_la0_top/n1784_s1/F
5.248 0.540 tNET RR 1 R20C32[3][A] gw_gao_inst_0/u_la0_top/trigger_seq_start_s3/I3
5.663 0.415 tINS RR 1 R20C32[3][A] gw_gao_inst_0/u_la0_top/trigger_seq_start_s3/F
5.800 0.137 tNET RR 1 R20C32[2][A] gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk_rx
8.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
9.344 1.344 tNET RR 1 R20C32[2][A] gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLK
9.033 -0.311 tSu 1 R20C32[2][A] gw_gao_inst_0/u_la0_top/trigger_seq_start_s1

Path Statistics:

Clock Skew 0.034
Setup Relationship 8.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.310, 100.000%
Arrival Data Path Delay cell: 0.876, 19.516%; route: 1.354, 30.150%; tC2Q: 2.260, 50.334%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.344, 100.000%

Path12

Path Summary:

Slack 3.350
Data Arrival Time 5.896
Data Required Time 9.246
From u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/remained_cnt_1_s1
To u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/o_dout_8_s0
Launch Clk pclk_rx:[R]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
1.310 1.310 tNET RR 1 R18C24[1][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/remained_cnt_1_s1/CLK
1.692 0.382 tC2Q RR 38 R18C24[1][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/remained_cnt_1_s1/Q
2.949 1.256 tNET RR 1 R20C27[2][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n195_s1/I0
3.465 0.516 tINS RR 13 R20C27[2][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n195_s1/F
5.115 1.650 tNET RR 1 R18C22[1][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n190_s1/I3
5.378 0.262 tINS RR 1 R18C22[1][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n190_s1/F
5.380 0.003 tNET RR 1 R18C22[0][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n190_s0/I0
5.896 0.516 tINS RR 1 R18C22[0][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/n190_s0/F
5.896 0.000 tNET RR 1 R18C22[0][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/o_dout_8_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk_rx
8.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
9.310 1.310 tNET RR 1 R18C22[0][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/o_dout_8_s0/CLK
9.246 -0.064 tSu 1 R18C22[0][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_gearbox_7_8_9_to_10/o_dout_8_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 8.000
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.310, 100.000%
Arrival Data Path Delay cell: 1.295, 28.237%; route: 2.909, 63.423%; tC2Q: 0.382, 8.340%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.310, 100.000%

Path13

Path Summary:

Slack 3.417
Data Arrival Time 5.859
Data Required Time 9.276
From u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_word_align/o_align_dat_1_s0
To u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_decoder_8b10b/dout_kerr_s0
Launch Clk pclk_rx:[R]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
1.325 1.325 tNET RR 1 R24C25[2][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_word_align/o_align_dat_1_s0/CLK
1.692 0.368 tC2Q RF 13 R24C25[2][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_word_align/o_align_dat_1_s0/Q
2.495 0.802 tNET FF 1 R22C27[3][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_decoder_8b10b/E_s3/I1
3.016 0.521 tINS FR 5 R22C27[3][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_decoder_8b10b/E_s3/F
3.374 0.357 tNET RR 1 R23C26[1][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_decoder_8b10b/n909_s3/I1
3.890 0.516 tINS RR 2 R23C26[1][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_decoder_8b10b/n909_s3/F
4.050 0.160 tNET RR 1 R22C26[0][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_decoder_8b10b/n910_s8/I3
4.511 0.461 tINS RR 1 R22C26[0][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_decoder_8b10b/n910_s8/F
4.669 0.157 tNET RR 1 R23C26[0][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_decoder_8b10b/n910_s4/I2
5.185 0.516 tINS RR 1 R23C26[0][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_decoder_8b10b/n910_s4/F
5.342 0.157 tNET RR 1 R22C26[1][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_decoder_8b10b/n910_s1/I2
5.859 0.516 tINS RR 1 R22C26[1][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_decoder_8b10b/n910_s1/F
5.859 0.000 tNET RR 1 R22C26[1][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_decoder_8b10b/dout_kerr_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk_rx
8.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
9.339 1.339 tNET RR 1 R22C26[1][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_decoder_8b10b/dout_kerr_s0/CLK
9.276 -0.064 tSu 1 R22C26[1][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_decoder_8b10b/dout_kerr_s0

Path Statistics:

Clock Skew 0.014
Setup Relationship 8.000
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.325, 100.000%
Arrival Data Path Delay cell: 2.531, 55.831%; route: 1.635, 36.063%; tC2Q: 0.368, 8.106%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.339, 100.000%

Path14

Path Summary:

Slack 3.632
Data Arrival Time 5.608
Data Required Time 9.241
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
Launch Clk pclk_rx:[R]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
1.304 1.304 tNET RR 1 R15C32[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK
1.687 0.382 tC2Q RR 5 R15C32[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/Q
2.182 0.495 tNET RR 1 R16C36[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n285_s9/I0
2.698 0.516 tINS RR 1 R16C36[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n285_s9/F
3.201 0.502 tNET RR 1 R15C32[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n285_s5/I2
3.662 0.461 tINS RR 2 R15C32[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n285_s5/F
3.822 0.160 tNET RR 1 R15C31[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n285_s4/I0
4.343 0.521 tINS RR 10 R15C31[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n285_s4/F
5.082 0.739 tNET RR 1 R15C28[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n286_s1/I3
5.608 0.526 tINS RR 1 R15C28[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n286_s1/F
5.608 0.000 tNET RR 1 R15C28[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk_rx
8.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
9.304 1.304 tNET RR 1 R15C28[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK
9.241 -0.064 tSu 1 R15C28[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 8.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.304, 100.000%
Arrival Data Path Delay cell: 2.025, 47.052%; route: 1.896, 44.060%; tC2Q: 0.382, 8.888%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.304, 100.000%

Path15

Path Summary:

Slack 3.771
Data Arrival Time 5.472
Data Required Time 9.242
From gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_8_s0
Launch Clk pclk_rx:[R]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
1.344 1.344 tNET RR 1 R20C32[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLK
1.727 0.382 tC2Q RR 12 R20C32[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/Q
3.223 1.496 tNET RR 1 R18C28[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_8_s14/I2
3.513 0.290 tINS RF 1 R18C28[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_8_s14/F
3.518 0.005 tNET FF 1 R18C28[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_8_s13/I1
3.979 0.461 tINS FR 1 R18C28[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_8_s13/F
3.982 0.003 tNET RR 1 R18C28[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_8_s12/I0
4.244 0.262 tINS RR 1 R18C28[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_8_s12/F
4.437 0.192 tNET RR 1 R16C28[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_8_s11/I1
4.953 0.516 tINS RR 1 R16C28[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_8_s11/F
4.956 0.003 tNET RR 1 R16C28[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_8_s9/I3
5.472 0.516 tINS RR 1 R16C28[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_8_s9/F
5.472 0.000 tNET RR 1 R16C28[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_8_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk_rx
8.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
9.306 1.306 tNET RR 1 R16C28[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_8_s0/CLK
9.242 -0.064 tSu 1 R16C28[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_8_s0

Path Statistics:

Clock Skew -0.038
Setup Relationship 8.000
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.344, 100.000%
Arrival Data Path Delay cell: 2.046, 49.576%; route: 1.699, 41.157%; tC2Q: 0.382, 9.267%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.306, 100.000%

Path16

Path Summary:

Slack 3.771
Data Arrival Time 5.519
Data Required Time 9.290
From gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s
To gw_gao_inst_0/u_la0_top/triger_s0
Launch Clk pclk_rx:[R]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
1.310 1.310 tNET RR 1 BSRAM_R28[8] gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s/CLKB
3.570 2.260 tC2Q RR 2 BSRAM_R28[8] gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s/DO[0]
4.247 0.676 tNET RR 1 R23C31[0][B] gw_gao_inst_0/u_la0_top/n1784_s1/I1
4.708 0.461 tINS RR 2 R23C31[0][B] gw_gao_inst_0/u_la0_top/n1784_s1/F
5.058 0.350 tNET RR 1 R20C31[0][B] gw_gao_inst_0/u_la0_top/n1784_s0/I1
5.519 0.461 tINS RR 1 R20C31[0][B] gw_gao_inst_0/u_la0_top/n1784_s0/F
5.519 0.000 tNET RR 1 R20C31[0][B] gw_gao_inst_0/u_la0_top/triger_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk_rx
8.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
9.354 1.354 tNET RR 1 R20C31[0][B] gw_gao_inst_0/u_la0_top/triger_s0/CLK
9.290 -0.064 tSu 1 R20C31[0][B] gw_gao_inst_0/u_la0_top/triger_s0

Path Statistics:

Clock Skew 0.043
Setup Relationship 8.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.310, 100.000%
Arrival Data Path Delay cell: 0.922, 21.919%; route: 1.026, 24.384%; tC2Q: 2.260, 53.698%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.354, 100.000%

Path17

Path Summary:

Slack 3.777
Data Arrival Time 5.463
Data Required Time 9.241
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
Launch Clk pclk_rx:[R]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
1.304 1.304 tNET RR 1 R15C32[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK
1.687 0.382 tC2Q RR 5 R15C32[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/Q
2.182 0.495 tNET RR 1 R16C36[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n285_s9/I0
2.698 0.516 tINS RR 1 R16C36[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n285_s9/F
3.201 0.502 tNET RR 1 R15C32[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n285_s5/I2
3.662 0.461 tINS RR 2 R15C32[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n285_s5/F
3.822 0.160 tNET RR 1 R15C31[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n285_s4/I0
4.343 0.521 tINS RR 10 R15C31[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n285_s4/F
4.947 0.604 tNET RR 1 R15C28[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n287_s1/I3
5.463 0.516 tINS RR 1 R15C28[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n287_s1/F
5.463 0.000 tNET RR 1 R15C28[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk_rx
8.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
9.304 1.304 tNET RR 1 R15C28[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK
9.241 -0.064 tSu 1 R15C28[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 8.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.304, 100.000%
Arrival Data Path Delay cell: 2.015, 48.452%; route: 1.761, 42.350%; tC2Q: 0.382, 9.197%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.304, 100.000%

Path18

Path Summary:

Slack 3.777
Data Arrival Time 5.463
Data Required Time 9.241
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
Launch Clk pclk_rx:[R]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
1.304 1.304 tNET RR 1 R15C32[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK
1.687 0.382 tC2Q RR 5 R15C32[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/Q
2.182 0.495 tNET RR 1 R16C36[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n285_s9/I0
2.698 0.516 tINS RR 1 R16C36[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n285_s9/F
3.201 0.502 tNET RR 1 R15C32[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n285_s5/I2
3.662 0.461 tINS RR 2 R15C32[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n285_s5/F
3.822 0.160 tNET RR 1 R15C31[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n285_s4/I0
4.343 0.521 tINS RR 10 R15C31[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n285_s4/F
4.947 0.604 tNET RR 1 R15C28[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n285_s2/I3
5.463 0.516 tINS RR 1 R15C28[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n285_s2/F
5.463 0.000 tNET RR 1 R15C28[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk_rx
8.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
9.304 1.304 tNET RR 1 R15C28[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK
9.241 -0.064 tSu 1 R15C28[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 8.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.304, 100.000%
Arrival Data Path Delay cell: 2.015, 48.452%; route: 1.761, 42.350%; tC2Q: 0.382, 9.197%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.304, 100.000%

Path19

Path Summary:

Slack 3.873
Data Arrival Time 5.133
Data Required Time 9.006
From u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_word_align/k_compare_d0_5_s1
To u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_word_align/cur_state.PRE_ALIGN_s1
Launch Clk pclk_rx:[R]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
1.339 1.339 tNET RR 1 R22C20[0][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_word_align/k_compare_d0_5_s1/CLK
1.722 0.382 tC2Q RR 4 R22C20[0][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_word_align/k_compare_d0_5_s1/Q
2.299 0.577 tNET RR 1 R24C23[3][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_word_align/n410_s2/I1
2.821 0.521 tINS RR 2 R24C23[3][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_word_align/n410_s2/F
2.981 0.160 tNET RR 1 R23C23[2][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_word_align/next_state.PRE_ALIGN_s11/I3
3.507 0.526 tINS RR 2 R23C23[2][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_word_align/next_state.PRE_ALIGN_s11/F
3.667 0.160 tNET RR 1 R24C23[1][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_word_align/next_state.PRE_ALIGN_s13/I2
3.929 0.262 tINS RR 2 R24C23[1][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_word_align/next_state.PRE_ALIGN_s13/F
4.469 0.540 tNET RR 1 R27C24[0][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_word_align/cur_state.PRE_ALIGN_s3/I3
4.996 0.526 tINS RR 1 R27C24[0][B] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_word_align/cur_state.PRE_ALIGN_s3/F
5.133 0.137 tNET RR 1 R27C24[2][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_word_align/cur_state.PRE_ALIGN_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk_rx
8.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
9.318 1.317 tNET RR 1 R27C24[2][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_word_align/cur_state.PRE_ALIGN_s1/CLK
9.006 -0.311 tSu 1 R27C24[2][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_word_align/cur_state.PRE_ALIGN_s1

Path Statistics:

Clock Skew -0.022
Setup Relationship 8.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.339, 100.000%
Arrival Data Path Delay cell: 1.836, 48.402%; route: 1.575, 41.516%; tC2Q: 0.382, 10.082%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.317, 100.000%

Path20

Path Summary:

Slack 3.906
Data Arrival Time 5.339
Data Required Time 9.244
From gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_9_s0
Launch Clk pclk_rx:[R]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
1.354 1.354 tNET RR 1 R20C31[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLK
1.736 0.382 tC2Q RR 14 R20C31[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/Q
3.264 1.527 tNET RR 1 R17C28[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s17/I1
3.790 0.526 tINS RR 1 R17C28[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s17/F
3.793 0.003 tNET RR 1 R17C28[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s16/I1
4.055 0.262 tINS RR 1 R17C28[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s16/F
4.057 0.003 tNET RR 1 R17C28[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s15/I0
4.574 0.516 tINS RR 1 R17C28[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s15/F
4.576 0.003 tNET RR 1 R17C28[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s12/I1
4.839 0.262 tINS RR 1 R17C28[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s12/F
4.841 0.003 tNET RR 1 R17C28[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s10/I1
5.339 0.498 tINS RR 1 R17C28[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s10/F
5.339 0.000 tNET RR 1 R17C28[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_9_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk_rx
8.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
9.308 1.308 tNET RR 1 R17C28[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_9_s0/CLK
9.244 -0.064 tSu 1 R17C28[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_9_s0

Path Statistics:

Clock Skew -0.046
Setup Relationship 8.000
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.354, 100.000%
Arrival Data Path Delay cell: 2.065, 51.819%; route: 1.538, 38.582%; tC2Q: 0.382, 9.598%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.308, 100.000%

Path21

Path Summary:

Slack 3.968
Data Arrival Time 5.058
Data Required Time 9.026
From gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s
To gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s1
Launch Clk pclk_rx:[R]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
1.310 1.310 tNET RR 1 BSRAM_R28[8] gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s/CLKB
3.570 2.260 tC2Q RR 2 BSRAM_R28[8] gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s/DO[0]
4.247 0.676 tNET RR 1 R23C31[1][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s3/I1
4.708 0.461 tINS RR 4 R23C31[1][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s3/F
5.058 0.350 tNET RR 1 R23C30[0][A] gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk_rx
8.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
9.337 1.337 tNET RR 1 R23C30[0][A] gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s1/CLK
9.026 -0.311 tSu 1 R23C30[0][A] gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s1

Path Statistics:

Clock Skew 0.027
Setup Relationship 8.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.310, 100.000%
Arrival Data Path Delay cell: 0.461, 12.308%; route: 1.026, 27.385%; tC2Q: 2.260, 60.307%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.337, 100.000%

Path22

Path Summary:

Slack 3.968
Data Arrival Time 5.058
Data Required Time 9.026
From gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s
To gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1
Launch Clk pclk_rx:[R]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
1.310 1.310 tNET RR 1 BSRAM_R28[8] gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s/CLKB
3.570 2.260 tC2Q RR 2 BSRAM_R28[8] gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s/DO[0]
4.247 0.676 tNET RR 1 R23C31[1][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s3/I1
4.708 0.461 tINS RR 4 R23C31[1][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s3/F
5.058 0.350 tNET RR 1 R23C30[0][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk_rx
8.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
9.337 1.337 tNET RR 1 R23C30[0][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLK
9.026 -0.311 tSu 1 R23C30[0][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1

Path Statistics:

Clock Skew 0.027
Setup Relationship 8.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.310, 100.000%
Arrival Data Path Delay cell: 0.461, 12.308%; route: 1.026, 27.385%; tC2Q: 2.260, 60.307%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.337, 100.000%

Path23

Path Summary:

Slack 3.968
Data Arrival Time 5.058
Data Required Time 9.026
From gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s
To gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1
Launch Clk pclk_rx:[R]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
1.310 1.310 tNET RR 1 BSRAM_R28[8] gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s/CLKB
3.570 2.260 tC2Q RR 2 BSRAM_R28[8] gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s/DO[0]
4.247 0.676 tNET RR 1 R23C31[1][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s3/I1
4.708 0.461 tINS RR 4 R23C31[1][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s3/F
5.058 0.350 tNET RR 1 R23C30[1][A] gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk_rx
8.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
9.337 1.337 tNET RR 1 R23C30[1][A] gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLK
9.026 -0.311 tSu 1 R23C30[1][A] gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1

Path Statistics:

Clock Skew 0.027
Setup Relationship 8.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.310, 100.000%
Arrival Data Path Delay cell: 0.461, 12.308%; route: 1.026, 27.385%; tC2Q: 2.260, 60.307%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.337, 100.000%

Path24

Path Summary:

Slack 3.968
Data Arrival Time 5.058
Data Required Time 9.026
From gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s
To gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1
Launch Clk pclk_rx:[R]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
1.310 1.310 tNET RR 1 BSRAM_R28[8] gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s/CLKB
3.570 2.260 tC2Q RR 2 BSRAM_R28[8] gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s/DO[0]
4.247 0.676 tNET RR 1 R23C31[1][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s3/I1
4.708 0.461 tINS RR 4 R23C31[1][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s3/F
5.058 0.350 tNET RR 1 R23C30[1][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk_rx
8.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
9.337 1.337 tNET RR 1 R23C30[1][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLK
9.026 -0.311 tSu 1 R23C30[1][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1

Path Statistics:

Clock Skew 0.027
Setup Relationship 8.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.310, 100.000%
Arrival Data Path Delay cell: 0.461, 12.308%; route: 1.026, 27.385%; tC2Q: 2.260, 60.307%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.337, 100.000%

Path25

Path Summary:

Slack 4.010
Data Arrival Time 5.231
Data Required Time 9.241
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
Launch Clk pclk_rx:[R]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
1.304 1.304 tNET RR 1 R15C32[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK
1.687 0.382 tC2Q RR 5 R15C32[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/Q
2.182 0.495 tNET RR 1 R16C36[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n285_s9/I0
2.698 0.516 tINS RR 1 R16C36[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n285_s9/F
3.201 0.502 tNET RR 1 R15C32[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n285_s5/I2
3.662 0.461 tINS RR 2 R15C32[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n285_s5/F
3.822 0.160 tNET RR 1 R15C31[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n285_s4/I0
4.343 0.521 tINS RR 10 R15C31[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n285_s4/F
4.714 0.371 tNET RR 1 R15C30[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n291_s1/I3
5.231 0.516 tINS RR 1 R15C30[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n291_s1/F
5.231 0.000 tNET RR 1 R15C30[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk_rx
8.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
9.304 1.304 tNET RR 1 R15C30[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK
9.241 -0.064 tSu 1 R15C30[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 8.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.304, 100.000%
Arrival Data Path Delay cell: 2.015, 51.321%; route: 1.529, 38.937%; tC2Q: 0.382, 9.742%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.304, 100.000%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 0.245
Data Arrival Time 2.795
Data Required Time 2.550
From gw_gao_inst_0/u_la0_top/expression0_data_s0
To gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s
Launch Clk tck_pad:[R]
Latch Clk tck_pad:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 217 - gw_gao_inst_0/u_gw_jtag/tck_o
2.319 0.968 tNET RR 1 R23C29[2][A] gw_gao_inst_0/u_la0_top/expression0_data_s0/CLK
2.464 0.144 tC2Q RR 1 R23C29[2][A] gw_gao_inst_0/u_la0_top/expression0_data_s0/Q
2.794 0.331 tNET RR 1 BSRAM_R28[8] gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s/DI[0]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 217 - gw_gao_inst_0/u_gw_jtag/tck_o
2.301 0.950 tNET RR 1 BSRAM_R28[8] gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s/CLKA
2.550 0.249 tHld 1 BSRAM_R28[8] gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s

Path Statistics:

Clock Skew -0.019
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 1.351, 58.245%; route: 0.968, 41.755%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.331, 69.684%; tC2Q: 0.144, 30.316%
Required Clock Path Delay cell: 1.351, 58.714%; route: 0.950, 41.286%

Path2

Path Summary:

Slack 0.247
Data Arrival Time 0.974
Data Required Time 0.727
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_3_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk pclk_rx:[R]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.468 0.468 tNET RR 1 R13C29[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_3_s0/CLK
0.612 0.144 tC2Q RR 1 R13C29[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_3_s0/Q
0.974 0.362 tNET RR 1 BSRAM_R10[8] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[3]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.478 0.478 tNET RR 1 BSRAM_R10[8] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
0.727 0.249 tHld 1 BSRAM_R10[8] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew 0.010
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.468, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.362, 71.542%; tC2Q: 0.144, 28.458%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.478, 100.000%

Path3

Path Summary:

Slack 0.275
Data Arrival Time 2.614
Data Required Time 2.339
From gw_gao_inst_0/u_la0_top/word_count_4_s0
To gw_gao_inst_0/u_la0_top/word_count_4_s0
Launch Clk tck_pad:[R]
Latch Clk tck_pad:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 217 - gw_gao_inst_0/u_gw_jtag/tck_o
2.314 0.963 tNET RR 1 R24C34[0][A] gw_gao_inst_0/u_la0_top/word_count_4_s0/CLK
2.455 0.141 tC2Q RF 5 R24C34[0][A] gw_gao_inst_0/u_la0_top/word_count_4_s0/Q
2.461 0.006 tNET FF 1 R24C34[0][A] gw_gao_inst_0/u_la0_top/data_to_word_counter_4_s0/I1
2.614 0.153 tINS FF 1 R24C34[0][A] gw_gao_inst_0/u_la0_top/data_to_word_counter_4_s0/F
2.614 0.000 tNET FF 1 R24C34[0][A] gw_gao_inst_0/u_la0_top/word_count_4_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 217 - gw_gao_inst_0/u_gw_jtag/tck_o
2.314 0.963 tNET RR 1 R24C34[0][A] gw_gao_inst_0/u_la0_top/word_count_4_s0/CLK
2.339 0.025 tHld 1 R24C34[0][A] gw_gao_inst_0/u_la0_top/word_count_4_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.351, 58.390%; route: 0.963, 41.610%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 1.351, 58.390%; route: 0.963, 41.610%

Path4

Path Summary:

Slack 0.275
Data Arrival Time 2.607
Data Required Time 2.332
From gw_gao_inst_0/u_la0_top/word_count_13_s0
To gw_gao_inst_0/u_la0_top/word_count_13_s0
Launch Clk tck_pad:[R]
Latch Clk tck_pad:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 217 - gw_gao_inst_0/u_gw_jtag/tck_o
2.307 0.956 tNET RR 1 R26C34[0][A] gw_gao_inst_0/u_la0_top/word_count_13_s0/CLK
2.448 0.141 tC2Q RF 4 R26C34[0][A] gw_gao_inst_0/u_la0_top/word_count_13_s0/Q
2.454 0.006 tNET FF 1 R26C34[0][A] gw_gao_inst_0/u_la0_top/data_to_word_counter_13_s0/I1
2.607 0.153 tINS FF 1 R26C34[0][A] gw_gao_inst_0/u_la0_top/data_to_word_counter_13_s0/F
2.607 0.000 tNET FF 1 R26C34[0][A] gw_gao_inst_0/u_la0_top/word_count_13_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 217 - gw_gao_inst_0/u_gw_jtag/tck_o
2.307 0.956 tNET RR 1 R26C34[0][A] gw_gao_inst_0/u_la0_top/word_count_13_s0/CLK
2.332 0.025 tHld 1 R26C34[0][A] gw_gao_inst_0/u_la0_top/word_count_13_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.351, 58.561%; route: 0.956, 41.439%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 1.351, 58.561%; route: 0.956, 41.439%

Path5

Path Summary:

Slack 0.275
Data Arrival Time 2.607
Data Required Time 2.332
From gw_gao_inst_0/u_la0_top/word_count_14_s0
To gw_gao_inst_0/u_la0_top/word_count_14_s0
Launch Clk tck_pad:[R]
Latch Clk tck_pad:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 217 - gw_gao_inst_0/u_gw_jtag/tck_o
2.307 0.956 tNET RR 1 R26C34[1][A] gw_gao_inst_0/u_la0_top/word_count_14_s0/CLK
2.448 0.141 tC2Q RF 3 R26C34[1][A] gw_gao_inst_0/u_la0_top/word_count_14_s0/Q
2.454 0.006 tNET FF 1 R26C34[1][A] gw_gao_inst_0/u_la0_top/data_to_word_counter_14_s0/I2
2.607 0.153 tINS FF 1 R26C34[1][A] gw_gao_inst_0/u_la0_top/data_to_word_counter_14_s0/F
2.607 0.000 tNET FF 1 R26C34[1][A] gw_gao_inst_0/u_la0_top/word_count_14_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 217 - gw_gao_inst_0/u_gw_jtag/tck_o
2.307 0.956 tNET RR 1 R26C34[1][A] gw_gao_inst_0/u_la0_top/word_count_14_s0/CLK
2.332 0.025 tHld 1 R26C34[1][A] gw_gao_inst_0/u_la0_top/word_count_14_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.351, 58.561%; route: 0.956, 41.439%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 1.351, 58.561%; route: 0.956, 41.439%

Path6

Path Summary:

Slack 0.275
Data Arrival Time 2.612
Data Required Time 2.337
From gw_gao_inst_0/u_la0_top/address_counter_9_s0
To gw_gao_inst_0/u_la0_top/address_counter_9_s0
Launch Clk tck_pad:[R]
Latch Clk tck_pad:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 217 - gw_gao_inst_0/u_gw_jtag/tck_o
2.312 0.961 tNET RR 1 R25C30[0][A] gw_gao_inst_0/u_la0_top/address_counter_9_s0/CLK
2.453 0.141 tC2Q RF 2 R25C30[0][A] gw_gao_inst_0/u_la0_top/address_counter_9_s0/Q
2.459 0.006 tNET FF 1 R25C30[0][A] gw_gao_inst_0/u_la0_top/data_to_addr_counter_9_s0/I2
2.612 0.153 tINS FF 1 R25C30[0][A] gw_gao_inst_0/u_la0_top/data_to_addr_counter_9_s0/F
2.612 0.000 tNET FF 1 R25C30[0][A] gw_gao_inst_0/u_la0_top/address_counter_9_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 217 - gw_gao_inst_0/u_gw_jtag/tck_o
2.312 0.961 tNET RR 1 R25C30[0][A] gw_gao_inst_0/u_la0_top/address_counter_9_s0/CLK
2.337 0.025 tHld 1 R25C30[0][A] gw_gao_inst_0/u_la0_top/address_counter_9_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.351, 58.434%; route: 0.961, 41.566%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 1.351, 58.434%; route: 0.961, 41.566%

Path7

Path Summary:

Slack 0.275
Data Arrival Time 0.783
Data Required Time 0.508
From u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_word_align/align_cnt_full_s6
To u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_word_align/align_cnt_full_s6
Launch Clk pclk_rx:[R]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.483 0.483 tNET RR 1 R27C25[0][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_word_align/align_cnt_full_s6/CLK
0.624 0.141 tC2Q RF 3 R27C25[0][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_word_align/align_cnt_full_s6/Q
0.630 0.006 tNET FF 1 R27C25[0][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_word_align/n543_s4/I0
0.783 0.153 tINS FF 1 R27C25[0][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_word_align/n543_s4/F
0.783 0.000 tNET FF 1 R27C25[0][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_word_align/align_cnt_full_s6/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.483 0.483 tNET RR 1 R27C25[0][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_word_align/align_cnt_full_s6/CLK
0.508 0.025 tHld 1 R27C25[0][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_word_align/align_cnt_full_s6

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.483, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.483, 100.000%

Path8

Path Summary:

Slack 0.275
Data Arrival Time 0.783
Data Required Time 0.508
From u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_word_align/align_cnt_1_s1
To u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_word_align/align_cnt_1_s1
Launch Clk pclk_rx:[R]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.483 0.483 tNET RR 1 R27C25[1][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_word_align/align_cnt_1_s1/CLK
0.624 0.141 tC2Q RF 4 R27C25[1][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_word_align/align_cnt_1_s1/Q
0.630 0.006 tNET FF 1 R27C25[1][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_word_align/n525_s3/I1
0.783 0.153 tINS FF 1 R27C25[1][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_word_align/n525_s3/F
0.783 0.000 tNET FF 1 R27C25[1][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_word_align/align_cnt_1_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.483 0.483 tNET RR 1 R27C25[1][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_word_align/align_cnt_1_s1/CLK
0.508 0.025 tHld 1 R27C25[1][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_word_align/align_cnt_1_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.483, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.483, 100.000%

Path9

Path Summary:

Slack 0.275
Data Arrival Time 0.787
Data Required Time 0.512
From u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_word_align/align_cnt_3_s1
To u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_word_align/align_cnt_3_s1
Launch Clk pclk_rx:[R]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.487 0.487 tNET RR 1 R27C24[1][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_word_align/align_cnt_3_s1/CLK
0.628 0.141 tC2Q RF 2 R27C24[1][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_word_align/align_cnt_3_s1/Q
0.634 0.006 tNET FF 1 R27C24[1][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_word_align/n523_s3/I1
0.787 0.153 tINS FF 1 R27C24[1][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_word_align/n523_s3/F
0.787 0.000 tNET FF 1 R27C24[1][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_word_align/align_cnt_3_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.487 0.487 tNET RR 1 R27C24[1][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_word_align/align_cnt_3_s1/CLK
0.512 0.025 tHld 1 R27C24[1][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_word_align/align_cnt_3_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.487, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.487, 100.000%

Path10

Path Summary:

Slack 0.275
Data Arrival Time 0.797
Data Required Time 0.522
From u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_word_align/wait_state_cnt_0_s0
To u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_word_align/wait_state_cnt_0_s0
Launch Clk pclk_rx:[R]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.497 0.497 tNET RR 1 R25C22[0][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_word_align/wait_state_cnt_0_s0/CLK
0.638 0.141 tC2Q RF 3 R25C22[0][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_word_align/wait_state_cnt_0_s0/Q
0.644 0.006 tNET FF 1 R25C22[0][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_word_align/n45_s2/I0
0.797 0.153 tINS FF 1 R25C22[0][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_word_align/n45_s2/F
0.797 0.000 tNET FF 1 R25C22[0][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_word_align/wait_state_cnt_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.497 0.497 tNET RR 1 R25C22[0][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_word_align/wait_state_cnt_0_s0/CLK
0.522 0.025 tHld 1 R25C22[0][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_word_align/wait_state_cnt_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.497, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.497, 100.000%

Path11

Path Summary:

Slack 0.275
Data Arrival Time 0.768
Data Required Time 0.493
From u_motivation_response/u_prbs_inspector/dat_corr_cnt_3_s1
To u_motivation_response/u_prbs_inspector/dat_corr_cnt_3_s1
Launch Clk pclk_rx:[R]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.468 0.468 tNET RR 1 R12C30[1][A] u_motivation_response/u_prbs_inspector/dat_corr_cnt_3_s1/CLK
0.609 0.141 tC2Q RF 3 R12C30[1][A] u_motivation_response/u_prbs_inspector/dat_corr_cnt_3_s1/Q
0.615 0.006 tNET FF 1 R12C30[1][A] u_motivation_response/u_prbs_inspector/n107_s1/I2
0.768 0.153 tINS FF 1 R12C30[1][A] u_motivation_response/u_prbs_inspector/n107_s1/F
0.768 0.000 tNET FF 1 R12C30[1][A] u_motivation_response/u_prbs_inspector/dat_corr_cnt_3_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.468 0.468 tNET RR 1 R12C30[1][A] u_motivation_response/u_prbs_inspector/dat_corr_cnt_3_s1/CLK
0.493 0.025 tHld 1 R12C30[1][A] u_motivation_response/u_prbs_inspector/dat_corr_cnt_3_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.468, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.468, 100.000%

Path12

Path Summary:

Slack 0.275
Data Arrival Time 0.780
Data Required Time 0.505
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1
Launch Clk pclk_rx:[R]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.480 0.480 tNET RR 1 R18C33[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLK
0.621 0.141 tC2Q RF 3 R18C33[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/Q
0.627 0.006 tNET FF 1 R18C33[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n193_s0/I2
0.780 0.153 tINS FF 1 R18C33[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n193_s0/F
0.780 0.000 tNET FF 1 R18C33[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.480 0.480 tNET RR 1 R18C33[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLK
0.505 0.025 tHld 1 R18C33[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.480, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.480, 100.000%

Path13

Path Summary:

Slack 0.275
Data Arrival Time 0.777
Data Required Time 0.502
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1
Launch Clk pclk_rx:[R]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.477 0.477 tNET RR 1 R16C33[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLK
0.618 0.141 tC2Q RF 2 R16C33[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/Q
0.624 0.006 tNET FF 1 R16C33[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n190_s0/I2
0.777 0.153 tINS FF 1 R16C33[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n190_s0/F
0.777 0.000 tNET FF 1 R16C33[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.477 0.477 tNET RR 1 R16C33[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLK
0.502 0.025 tHld 1 R16C33[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.477, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.477, 100.000%

Path14

Path Summary:

Slack 0.275
Data Arrival Time 0.804
Data Required Time 0.529
From gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1
To gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1
Launch Clk pclk_rx:[R]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.504 0.504 tNET RR 1 R21C32[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLK
0.645 0.141 tC2Q RF 3 R21C32[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/Q
0.651 0.006 tNET FF 1 R21C32[1][A] gw_gao_inst_0/u_la0_top/n1803_s1/I1
0.804 0.153 tINS FF 1 R21C32[1][A] gw_gao_inst_0/u_la0_top/n1803_s1/F
0.804 0.000 tNET FF 1 R21C32[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.504 0.504 tNET RR 1 R21C32[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLK
0.529 0.025 tHld 1 R21C32[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.504, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.504, 100.000%

Path15

Path Summary:

Slack 0.275
Data Arrival Time 0.779
Data Required Time 0.503
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1
Launch Clk pclk_rx:[R]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.479 0.479 tNET RR 1 R17C33[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLK
0.620 0.141 tC2Q RF 2 R17C33[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/Q
0.626 0.006 tNET FF 1 R17C33[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n192_s0/I2
0.779 0.153 tINS FF 1 R17C33[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n192_s0/F
0.779 0.000 tNET FF 1 R17C33[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.479 0.479 tNET RR 1 R17C33[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLK
0.503 0.025 tHld 1 R17C33[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.479, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.479, 100.000%

Path16

Path Summary:

Slack 0.275
Data Arrival Time 1.452
Data Required Time 1.176
From u_EasyCDR_Top/u_easycdr/u_share_logic/delay_cnt_1_s0
To u_EasyCDR_Top/u_easycdr/u_share_logic/delay_cnt_1_s0
Launch Clk board_clk:[R]
Latch Clk board_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 board_clk
0.000 0.000 tCL RR 1 IOB29[A] board_clk_ibuf/I
0.675 0.675 tINS RR 28 IOB29[A] board_clk_ibuf/O
1.151 0.476 tNET RR 1 R11C27[1][A] u_EasyCDR_Top/u_easycdr/u_share_logic/delay_cnt_1_s0/CLK
1.293 0.141 tC2Q RF 4 R11C27[1][A] u_EasyCDR_Top/u_easycdr/u_share_logic/delay_cnt_1_s0/Q
1.299 0.006 tNET FF 1 R11C27[1][A] u_EasyCDR_Top/u_easycdr/u_share_logic/n24_s1/I1
1.452 0.153 tINS FF 1 R11C27[1][A] u_EasyCDR_Top/u_easycdr/u_share_logic/n24_s1/F
1.452 0.000 tNET FF 1 R11C27[1][A] u_EasyCDR_Top/u_easycdr/u_share_logic/delay_cnt_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 board_clk
0.000 0.000 tCL RR 1 IOB29[A] board_clk_ibuf/I
0.675 0.675 tINS RR 28 IOB29[A] board_clk_ibuf/O
1.151 0.476 tNET RR 1 R11C27[1][A] u_EasyCDR_Top/u_easycdr/u_share_logic/delay_cnt_1_s0/CLK
1.176 0.025 tHld 1 R11C27[1][A] u_EasyCDR_Top/u_easycdr/u_share_logic/delay_cnt_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.675, 58.663%; route: 0.476, 41.337%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.675, 58.663%; route: 0.476, 41.337%

Path17

Path Summary:

Slack 0.275
Data Arrival Time 1.456
Data Required Time 1.180
From u_motivation_response/rstn_fabric_cnt_9_s0
To u_motivation_response/rstn_fabric_cnt_9_s0
Launch Clk board_clk:[R]
Latch Clk board_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 board_clk
0.000 0.000 tCL RR 1 IOB29[A] board_clk_ibuf/I
0.675 0.675 tINS RR 28 IOB29[A] board_clk_ibuf/O
1.155 0.480 tNET RR 1 R11C32[0][A] u_motivation_response/rstn_fabric_cnt_9_s0/CLK
1.296 0.141 tC2Q RF 4 R11C32[0][A] u_motivation_response/rstn_fabric_cnt_9_s0/Q
1.303 0.006 tNET FF 1 R11C32[0][A] u_motivation_response/n40_s3/I0
1.456 0.153 tINS FF 1 R11C32[0][A] u_motivation_response/n40_s3/F
1.456 0.000 tNET FF 1 R11C32[0][A] u_motivation_response/rstn_fabric_cnt_9_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 board_clk
0.000 0.000 tCL RR 1 IOB29[A] board_clk_ibuf/I
0.675 0.675 tINS RR 28 IOB29[A] board_clk_ibuf/O
1.155 0.480 tNET RR 1 R11C32[0][A] u_motivation_response/rstn_fabric_cnt_9_s0/CLK
1.180 0.025 tHld 1 R11C32[0][A] u_motivation_response/rstn_fabric_cnt_9_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.675, 58.460%; route: 0.480, 41.540%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.675, 58.460%; route: 0.480, 41.540%

Path18

Path Summary:

Slack 0.275
Data Arrival Time 1.451
Data Required Time 1.176
From u_motivation_response/rstn_fabric_cnt_10_s0
To u_motivation_response/rstn_fabric_cnt_10_s0
Launch Clk board_clk:[R]
Latch Clk board_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 board_clk
0.000 0.000 tCL RR 1 IOB29[A] board_clk_ibuf/I
0.675 0.675 tINS RR 28 IOB29[A] board_clk_ibuf/O
1.151 0.475 tNET RR 1 R13C32[0][A] u_motivation_response/rstn_fabric_cnt_10_s0/CLK
1.292 0.141 tC2Q RF 3 R13C32[0][A] u_motivation_response/rstn_fabric_cnt_10_s0/Q
1.298 0.006 tNET FF 1 R13C32[0][A] u_motivation_response/n39_s1/I2
1.451 0.153 tINS FF 1 R13C32[0][A] u_motivation_response/n39_s1/F
1.451 0.000 tNET FF 1 R13C32[0][A] u_motivation_response/rstn_fabric_cnt_10_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 board_clk
0.000 0.000 tCL RR 1 IOB29[A] board_clk_ibuf/I
0.675 0.675 tINS RR 28 IOB29[A] board_clk_ibuf/O
1.151 0.475 tNET RR 1 R13C32[0][A] u_motivation_response/rstn_fabric_cnt_10_s0/CLK
1.176 0.025 tHld 1 R13C32[0][A] u_motivation_response/rstn_fabric_cnt_10_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.675, 58.714%; route: 0.475, 41.286%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.675, 58.714%; route: 0.475, 41.286%

Path19

Path Summary:

Slack 0.275
Data Arrival Time 1.452
Data Required Time 1.176
From u_motivation_response/rstn_fabric_cnt_11_s0
To u_motivation_response/rstn_fabric_cnt_11_s0
Launch Clk board_clk:[R]
Latch Clk board_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 board_clk
0.000 0.000 tCL RR 1 IOB29[A] board_clk_ibuf/I
0.675 0.675 tINS RR 28 IOB29[A] board_clk_ibuf/O
1.151 0.476 tNET RR 1 R11C31[0][A] u_motivation_response/rstn_fabric_cnt_11_s0/CLK
1.293 0.141 tC2Q RF 4 R11C31[0][A] u_motivation_response/rstn_fabric_cnt_11_s0/Q
1.299 0.006 tNET FF 1 R11C31[0][A] u_motivation_response/n38_s4/I0
1.452 0.153 tINS FF 1 R11C31[0][A] u_motivation_response/n38_s4/F
1.452 0.000 tNET FF 1 R11C31[0][A] u_motivation_response/rstn_fabric_cnt_11_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 board_clk
0.000 0.000 tCL RR 1 IOB29[A] board_clk_ibuf/I
0.675 0.675 tINS RR 28 IOB29[A] board_clk_ibuf/O
1.151 0.476 tNET RR 1 R11C31[0][A] u_motivation_response/rstn_fabric_cnt_11_s0/CLK
1.176 0.025 tHld 1 R11C31[0][A] u_motivation_response/rstn_fabric_cnt_11_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.675, 58.663%; route: 0.476, 41.337%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.675, 58.663%; route: 0.476, 41.337%

Path20

Path Summary:

Slack 0.275
Data Arrival Time 2.616
Data Required Time 2.341
From gw_gao_inst_0/u_la0_top/word_count_5_s0
To gw_gao_inst_0/u_la0_top/word_count_5_s0
Launch Clk tck_pad:[R]
Latch Clk tck_pad:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 217 - gw_gao_inst_0/u_gw_jtag/tck_o
2.316 0.965 tNET RR 1 R25C33[0][A] gw_gao_inst_0/u_la0_top/word_count_5_s0/CLK
2.457 0.141 tC2Q RF 4 R25C33[0][A] gw_gao_inst_0/u_la0_top/word_count_5_s0/Q
2.463 0.006 tNET FF 1 R25C33[0][A] gw_gao_inst_0/u_la0_top/data_to_word_counter_5_s0/I2
2.616 0.153 tINS FF 1 R25C33[0][A] gw_gao_inst_0/u_la0_top/data_to_word_counter_5_s0/F
2.616 0.000 tNET FF 1 R25C33[0][A] gw_gao_inst_0/u_la0_top/word_count_5_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 217 - gw_gao_inst_0/u_gw_jtag/tck_o
2.316 0.965 tNET RR 1 R25C33[0][A] gw_gao_inst_0/u_la0_top/word_count_5_s0/CLK
2.341 0.025 tHld 1 R25C33[0][A] gw_gao_inst_0/u_la0_top/word_count_5_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.351, 58.333%; route: 0.965, 41.667%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 1.351, 58.333%; route: 0.965, 41.667%

Path21

Path Summary:

Slack 0.275
Data Arrival Time 2.611
Data Required Time 2.336
From gw_gao_inst_0/u_la0_top/address_counter_1_s0
To gw_gao_inst_0/u_la0_top/address_counter_1_s0
Launch Clk tck_pad:[R]
Latch Clk tck_pad:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 217 - gw_gao_inst_0/u_gw_jtag/tck_o
2.311 0.960 tNET RR 1 R26C31[1][A] gw_gao_inst_0/u_la0_top/address_counter_1_s0/CLK
2.452 0.141 tC2Q RF 5 R26C31[1][A] gw_gao_inst_0/u_la0_top/address_counter_1_s0/Q
2.458 0.006 tNET FF 1 R26C31[1][A] gw_gao_inst_0/u_la0_top/data_to_addr_counter_1_s0/I2
2.611 0.153 tINS FF 1 R26C31[1][A] gw_gao_inst_0/u_la0_top/data_to_addr_counter_1_s0/F
2.611 0.000 tNET FF 1 R26C31[1][A] gw_gao_inst_0/u_la0_top/address_counter_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 217 - gw_gao_inst_0/u_gw_jtag/tck_o
2.311 0.960 tNET RR 1 R26C31[1][A] gw_gao_inst_0/u_la0_top/address_counter_1_s0/CLK
2.336 0.025 tHld 1 R26C31[1][A] gw_gao_inst_0/u_la0_top/address_counter_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.351, 58.460%; route: 0.960, 41.540%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 1.351, 58.460%; route: 0.960, 41.540%

Path22

Path Summary:

Slack 0.278
Data Arrival Time 2.624
Data Required Time 2.346
From gw_gao_inst_0/u_la0_top/word_count_10_s0
To gw_gao_inst_0/u_la0_top/word_count_10_s0
Launch Clk tck_pad:[R]
Latch Clk tck_pad:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 217 - gw_gao_inst_0/u_gw_jtag/tck_o
2.321 0.970 tNET RR 1 R22C37[0][A] gw_gao_inst_0/u_la0_top/word_count_10_s0/CLK
2.462 0.141 tC2Q RF 4 R22C37[0][A] gw_gao_inst_0/u_la0_top/word_count_10_s0/Q
2.471 0.009 tNET FF 1 R22C37[0][A] gw_gao_inst_0/u_la0_top/data_to_word_counter_10_s0/I2
2.624 0.153 tINS FF 1 R22C37[0][A] gw_gao_inst_0/u_la0_top/data_to_word_counter_10_s0/F
2.624 0.000 tNET FF 1 R22C37[0][A] gw_gao_inst_0/u_la0_top/word_count_10_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 217 - gw_gao_inst_0/u_gw_jtag/tck_o
2.321 0.970 tNET RR 1 R22C37[0][A] gw_gao_inst_0/u_la0_top/word_count_10_s0/CLK
2.346 0.025 tHld 1 R22C37[0][A] gw_gao_inst_0/u_la0_top/word_count_10_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.351, 58.201%; route: 0.970, 41.799%
Arrival Data Path Delay cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay cell: 1.351, 58.201%; route: 0.970, 41.799%

Path23

Path Summary:

Slack 0.278
Data Arrival Time 2.618
Data Required Time 2.340
From gw_gao_inst_0/u_la0_top/address_counter_7_s0
To gw_gao_inst_0/u_la0_top/address_counter_7_s0
Launch Clk tck_pad:[R]
Latch Clk tck_pad:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 217 - gw_gao_inst_0/u_gw_jtag/tck_o
2.315 0.964 tNET RR 1 R26C32[0][A] gw_gao_inst_0/u_la0_top/address_counter_7_s0/CLK
2.456 0.141 tC2Q RF 4 R26C32[0][A] gw_gao_inst_0/u_la0_top/address_counter_7_s0/Q
2.465 0.009 tNET FF 1 R26C32[0][A] gw_gao_inst_0/u_la0_top/data_to_addr_counter_7_s0/I1
2.618 0.153 tINS FF 1 R26C32[0][A] gw_gao_inst_0/u_la0_top/data_to_addr_counter_7_s0/F
2.618 0.000 tNET FF 1 R26C32[0][A] gw_gao_inst_0/u_la0_top/address_counter_7_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 217 - gw_gao_inst_0/u_gw_jtag/tck_o
2.315 0.964 tNET RR 1 R26C32[0][A] gw_gao_inst_0/u_la0_top/address_counter_7_s0/CLK
2.340 0.025 tHld 1 R26C32[0][A] gw_gao_inst_0/u_la0_top/address_counter_7_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.351, 58.359%; route: 0.964, 41.641%
Arrival Data Path Delay cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay cell: 1.351, 58.359%; route: 0.964, 41.641%

Path24

Path Summary:

Slack 0.278
Data Arrival Time 0.796
Data Required Time 0.518
From u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_word_align/decode_err_cnt_full_s6
To u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_word_align/decode_err_cnt_full_s6
Launch Clk pclk_rx:[R]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.493 0.493 tNET RR 1 R25C21[1][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_word_align/decode_err_cnt_full_s6/CLK
0.634 0.141 tC2Q RF 4 R25C21[1][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_word_align/decode_err_cnt_full_s6/Q
0.643 0.009 tNET FF 1 R25C21[1][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_word_align/n591_s4/I0
0.796 0.153 tINS FF 1 R25C21[1][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_word_align/n591_s4/F
0.796 0.000 tNET FF 1 R25C21[1][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_word_align/decode_err_cnt_full_s6/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.493 0.493 tNET RR 1 R25C21[1][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_word_align/decode_err_cnt_full_s6/CLK
0.518 0.025 tHld 1 R25C21[1][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_word_align/decode_err_cnt_full_s6

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.493, 100.000%
Arrival Data Path Delay cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.493, 100.000%

Path25

Path Summary:

Slack 0.278
Data Arrival Time 0.771
Data Required Time 0.493
From u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_cdr/status_0_s0
To u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_cdr/status_0_s0
Launch Clk pclk_rx:[R]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.468 0.468 tNET RR 1 R12C26[1][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_cdr/status_0_s0/CLK
0.609 0.141 tC2Q RF 21 R12C26[1][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_cdr/status_0_s0/Q
0.618 0.009 tNET FF 1 R12C26[1][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_cdr/n220_s3/I3
0.771 0.153 tINS FF 1 R12C26[1][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_cdr/n220_s3/F
0.771 0.000 tNET FF 1 R12C26[1][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_cdr/status_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.468 0.468 tNET RR 1 R12C26[1][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_cdr/status_0_s0/CLK
0.493 0.025 tHld 1 R12C26[1][A] u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_cdr/status_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.468, 100.000%
Arrival Data Path Delay cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.468, 100.000%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 1.572
Data Arrival Time 7.418
Data Required Time 8.989
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_0_s0
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.000 4.000 active clock edge time
4.000 0.000 pclk_rx
4.000 0.000 tCL FF 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
5.290 1.290 tNET FF 1 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
5.733 0.442 tC2Q FF 58 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.418 1.685 tNET FF 1 R23C32[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk_rx
8.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
9.337 1.337 tNET RR 1 R23C32[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_0_s0/CLK
8.989 -0.347 tSu 1 R23C32[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_0_s0

Path Statistics:

Clock Skew 0.047
Setup Relationship 4.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.290, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.685, 79.201%; tC2Q: 0.442, 20.799%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.337, 100.000%

Path2

Path Summary:

Slack 1.710
Data Arrival Time 7.278
Data Required Time 8.988
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.000 4.000 active clock edge time
4.000 0.000 pclk_rx
4.000 0.000 tCL FF 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
5.290 1.290 tNET FF 1 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
5.733 0.442 tC2Q FF 58 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.278 1.545 tNET FF 1 R20C33[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk_rx
8.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
9.335 1.335 tNET RR 1 R20C33[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLK
8.988 -0.347 tSu 1 R20C33[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1

Path Statistics:

Clock Skew 0.045
Setup Relationship 4.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.290, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.545, 77.736%; tC2Q: 0.442, 22.264%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.335, 100.000%

Path3

Path Summary:

Slack 1.710
Data Arrival Time 7.278
Data Required Time 8.988
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.000 4.000 active clock edge time
4.000 0.000 pclk_rx
4.000 0.000 tCL FF 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
5.290 1.290 tNET FF 1 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
5.733 0.442 tC2Q FF 58 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.278 1.545 tNET FF 1 R20C33[1][B] gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk_rx
8.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
9.335 1.335 tNET RR 1 R20C33[1][B] gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLK
8.988 -0.347 tSu 1 R20C33[1][B] gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0

Path Statistics:

Clock Skew 0.045
Setup Relationship 4.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.290, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.545, 77.736%; tC2Q: 0.442, 22.264%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.335, 100.000%

Path4

Path Summary:

Slack 1.710
Data Arrival Time 7.278
Data Required Time 8.988
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.000 4.000 active clock edge time
4.000 0.000 pclk_rx
4.000 0.000 tCL FF 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
5.290 1.290 tNET FF 1 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
5.733 0.442 tC2Q FF 58 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.278 1.545 tNET FF 1 R20C33[2][A] gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk_rx
8.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
9.335 1.335 tNET RR 1 R20C33[2][A] gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLK
8.988 -0.347 tSu 1 R20C33[2][A] gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0

Path Statistics:

Clock Skew 0.045
Setup Relationship 4.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.290, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.545, 77.736%; tC2Q: 0.442, 22.264%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.335, 100.000%

Path5

Path Summary:

Slack 1.710
Data Arrival Time 7.278
Data Required Time 8.988
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.000 4.000 active clock edge time
4.000 0.000 pclk_rx
4.000 0.000 tCL FF 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
5.290 1.290 tNET FF 1 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
5.733 0.442 tC2Q FF 58 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.278 1.545 tNET FF 1 R20C33[3][A] gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk_rx
8.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
9.335 1.335 tNET RR 1 R20C33[3][A] gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLK
8.988 -0.347 tSu 1 R20C33[3][A] gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0

Path Statistics:

Clock Skew 0.045
Setup Relationship 4.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.290, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.545, 77.736%; tC2Q: 0.442, 22.264%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.335, 100.000%

Path6

Path Summary:

Slack 1.710
Data Arrival Time 7.278
Data Required Time 8.988
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.000 4.000 active clock edge time
4.000 0.000 pclk_rx
4.000 0.000 tCL FF 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
5.290 1.290 tNET FF 1 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
5.733 0.442 tC2Q FF 58 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.278 1.545 tNET FF 1 R20C33[2][B] gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk_rx
8.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
9.335 1.335 tNET RR 1 R20C33[2][B] gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLK
8.988 -0.347 tSu 1 R20C33[2][B] gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0

Path Statistics:

Clock Skew 0.045
Setup Relationship 4.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.290, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.545, 77.736%; tC2Q: 0.442, 22.264%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.335, 100.000%

Path7

Path Summary:

Slack 1.719
Data Arrival Time 7.278
Data Required Time 8.997
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_1/trig_dly_in_0_s0
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.000 4.000 active clock edge time
4.000 0.000 pclk_rx
4.000 0.000 tCL FF 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
5.290 1.290 tNET FF 1 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
5.733 0.442 tC2Q FF 58 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.278 1.545 tNET FF 1 R20C32[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/trig_dly_in_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk_rx
8.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
9.344 1.344 tNET RR 1 R20C32[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/trig_dly_in_0_s0/CLK
8.997 -0.347 tSu 1 R20C32[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/trig_dly_in_0_s0

Path Statistics:

Clock Skew 0.054
Setup Relationship 4.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.290, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.545, 77.736%; tC2Q: 0.442, 22.264%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.344, 100.000%

Path8

Path Summary:

Slack 1.719
Data Arrival Time 7.278
Data Required Time 8.997
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.000 4.000 active clock edge time
4.000 0.000 pclk_rx
4.000 0.000 tCL FF 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
5.290 1.290 tNET FF 1 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
5.733 0.442 tC2Q FF 58 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.278 1.545 tNET FF 1 R20C32[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk_rx
8.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
9.344 1.344 tNET RR 1 R20C32[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLK
8.997 -0.347 tSu 1 R20C32[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1

Path Statistics:

Clock Skew 0.054
Setup Relationship 4.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.290, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.545, 77.736%; tC2Q: 0.442, 22.264%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.344, 100.000%

Path9

Path Summary:

Slack 1.719
Data Arrival Time 7.278
Data Required Time 8.997
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.000 4.000 active clock edge time
4.000 0.000 pclk_rx
4.000 0.000 tCL FF 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
5.290 1.290 tNET FF 1 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
5.733 0.442 tC2Q FF 58 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.278 1.545 tNET FF 1 R20C32[1][B] gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk_rx
8.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
9.344 1.344 tNET RR 1 R20C32[1][B] gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLK
8.997 -0.347 tSu 1 R20C32[1][B] gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1

Path Statistics:

Clock Skew 0.054
Setup Relationship 4.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.290, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.545, 77.736%; tC2Q: 0.442, 22.264%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.344, 100.000%

Path10

Path Summary:

Slack 1.719
Data Arrival Time 7.278
Data Required Time 8.997
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/trigger_seq_start_s1
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.000 4.000 active clock edge time
4.000 0.000 pclk_rx
4.000 0.000 tCL FF 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
5.290 1.290 tNET FF 1 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
5.733 0.442 tC2Q FF 58 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.278 1.545 tNET FF 1 R20C32[2][A] gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk_rx
8.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
9.344 1.344 tNET RR 1 R20C32[2][A] gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLK
8.997 -0.347 tSu 1 R20C32[2][A] gw_gao_inst_0/u_la0_top/trigger_seq_start_s1

Path Statistics:

Clock Skew 0.054
Setup Relationship 4.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.290, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.545, 77.736%; tC2Q: 0.442, 22.264%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.344, 100.000%

Path11

Path Summary:

Slack 1.719
Data Arrival Time 7.278
Data Required Time 8.997
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/start_reg_s0
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.000 4.000 active clock edge time
4.000 0.000 pclk_rx
4.000 0.000 tCL FF 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
5.290 1.290 tNET FF 1 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
5.733 0.442 tC2Q FF 58 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.278 1.545 tNET FF 1 R20C32[0][B] gw_gao_inst_0/u_la0_top/start_reg_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk_rx
8.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
9.344 1.344 tNET RR 1 R20C32[0][B] gw_gao_inst_0/u_la0_top/start_reg_s0/CLK
8.997 -0.347 tSu 1 R20C32[0][B] gw_gao_inst_0/u_la0_top/start_reg_s0

Path Statistics:

Clock Skew 0.054
Setup Relationship 4.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.290, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.545, 77.736%; tC2Q: 0.442, 22.264%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.344, 100.000%

Path12

Path Summary:

Slack 1.747
Data Arrival Time 7.245
Data Required Time 8.992
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_end_dly_s0
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.000 4.000 active clock edge time
4.000 0.000 pclk_rx
4.000 0.000 tCL FF 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
5.290 1.290 tNET FF 1 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
5.733 0.442 tC2Q FF 58 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.245 1.513 tNET FF 1 R22C28[0][A] gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk_rx
8.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
9.339 1.339 tNET RR 1 R22C28[0][A] gw_gao_inst_0/u_la0_top/capture_end_dly_s0/CLK
8.992 -0.347 tSu 1 R22C28[0][A] gw_gao_inst_0/u_la0_top/capture_end_dly_s0

Path Statistics:

Clock Skew 0.049
Setup Relationship 4.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.290, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.513, 77.366%; tC2Q: 0.442, 22.634%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.339, 100.000%

Path13

Path Summary:

Slack 1.756
Data Arrival Time 7.234
Data Required Time 8.989
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s1
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.000 4.000 active clock edge time
4.000 0.000 pclk_rx
4.000 0.000 tCL FF 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
5.290 1.290 tNET FF 1 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
5.733 0.442 tC2Q FF 58 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.234 1.501 tNET FF 1 R23C30[0][A] gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk_rx
8.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
9.337 1.337 tNET RR 1 R23C30[0][A] gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s1/CLK
8.989 -0.347 tSu 1 R23C30[0][A] gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s1

Path Statistics:

Clock Skew 0.047
Setup Relationship 4.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.290, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.501, 77.235%; tC2Q: 0.442, 22.765%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.337, 100.000%

Path14

Path Summary:

Slack 1.756
Data Arrival Time 7.234
Data Required Time 8.989
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.000 4.000 active clock edge time
4.000 0.000 pclk_rx
4.000 0.000 tCL FF 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
5.290 1.290 tNET FF 1 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
5.733 0.442 tC2Q FF 58 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.234 1.501 tNET FF 1 R23C30[0][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk_rx
8.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
9.337 1.337 tNET RR 1 R23C30[0][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLK
8.989 -0.347 tSu 1 R23C30[0][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1

Path Statistics:

Clock Skew 0.047
Setup Relationship 4.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.290, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.501, 77.235%; tC2Q: 0.442, 22.765%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.337, 100.000%

Path15

Path Summary:

Slack 1.756
Data Arrival Time 7.234
Data Required Time 8.989
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.000 4.000 active clock edge time
4.000 0.000 pclk_rx
4.000 0.000 tCL FF 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
5.290 1.290 tNET FF 1 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
5.733 0.442 tC2Q FF 58 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.234 1.501 tNET FF 1 R23C30[1][A] gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk_rx
8.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
9.337 1.337 tNET RR 1 R23C30[1][A] gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLK
8.989 -0.347 tSu 1 R23C30[1][A] gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1

Path Statistics:

Clock Skew 0.047
Setup Relationship 4.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.290, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.501, 77.235%; tC2Q: 0.442, 22.765%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.337, 100.000%

Path16

Path Summary:

Slack 1.756
Data Arrival Time 7.234
Data Required Time 8.989
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.000 4.000 active clock edge time
4.000 0.000 pclk_rx
4.000 0.000 tCL FF 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
5.290 1.290 tNET FF 1 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
5.733 0.442 tC2Q FF 58 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.234 1.501 tNET FF 1 R23C30[1][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk_rx
8.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
9.337 1.337 tNET RR 1 R23C30[1][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLK
8.989 -0.347 tSu 1 R23C30[1][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1

Path Statistics:

Clock Skew 0.047
Setup Relationship 4.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.290, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.501, 77.235%; tC2Q: 0.442, 22.765%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.337, 100.000%

Path17

Path Summary:

Slack 1.765
Data Arrival Time 7.234
Data Required Time 8.999
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_1/match_sep_s0
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.000 4.000 active clock edge time
4.000 0.000 pclk_rx
4.000 0.000 tCL FF 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
5.290 1.290 tNET FF 1 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
5.733 0.442 tC2Q FF 58 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.234 1.501 tNET FF 1 R23C31[2][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_sep_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk_rx
8.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
9.346 1.346 tNET RR 1 R23C31[2][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_sep_s0/CLK
8.999 -0.347 tSu 1 R23C31[2][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_sep_s0

Path Statistics:

Clock Skew 0.056
Setup Relationship 4.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.290, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.501, 77.235%; tC2Q: 0.442, 22.765%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.346, 100.000%

Path18

Path Summary:

Slack 1.769
Data Arrival Time 7.225
Data Required Time 8.994
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.000 4.000 active clock edge time
4.000 0.000 pclk_rx
4.000 0.000 tCL FF 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
5.290 1.290 tNET FF 1 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
5.733 0.442 tC2Q FF 58 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.225 1.493 tNET FF 1 R21C32[2][A] gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk_rx
8.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
9.342 1.342 tNET RR 1 R21C32[2][A] gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLK
8.994 -0.347 tSu 1 R21C32[2][A] gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1

Path Statistics:

Clock Skew 0.052
Setup Relationship 4.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.290, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.493, 77.132%; tC2Q: 0.442, 22.868%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.342, 100.000%

Path19

Path Summary:

Slack 1.769
Data Arrival Time 7.225
Data Required Time 8.994
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.000 4.000 active clock edge time
4.000 0.000 pclk_rx
4.000 0.000 tCL FF 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
5.290 1.290 tNET FF 1 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
5.733 0.442 tC2Q FF 58 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.225 1.493 tNET FF 1 R21C32[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk_rx
8.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
9.342 1.342 tNET RR 1 R21C32[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLK
8.994 -0.347 tSu 1 R21C32[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1

Path Statistics:

Clock Skew 0.052
Setup Relationship 4.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.290, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.493, 77.132%; tC2Q: 0.442, 22.868%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.342, 100.000%

Path20

Path Summary:

Slack 1.769
Data Arrival Time 7.225
Data Required Time 8.994
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.000 4.000 active clock edge time
4.000 0.000 pclk_rx
4.000 0.000 tCL FF 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
5.290 1.290 tNET FF 1 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
5.733 0.442 tC2Q FF 58 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.225 1.493 tNET FF 1 R21C32[0][B] gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk_rx
8.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
9.342 1.342 tNET RR 1 R21C32[0][B] gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLK
8.994 -0.347 tSu 1 R21C32[0][B] gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1

Path Statistics:

Clock Skew 0.052
Setup Relationship 4.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.290, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.493, 77.132%; tC2Q: 0.442, 22.868%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.342, 100.000%

Path21

Path Summary:

Slack 1.769
Data Arrival Time 7.225
Data Required Time 8.994
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.000 4.000 active clock edge time
4.000 0.000 pclk_rx
4.000 0.000 tCL FF 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
5.290 1.290 tNET FF 1 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
5.733 0.442 tC2Q FF 58 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.225 1.493 tNET FF 1 R21C32[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk_rx
8.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
9.342 1.342 tNET RR 1 R21C32[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLK
8.994 -0.347 tSu 1 R21C32[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1

Path Statistics:

Clock Skew 0.052
Setup Relationship 4.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.290, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.493, 77.132%; tC2Q: 0.442, 22.868%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.342, 100.000%

Path22

Path Summary:

Slack 1.776
Data Arrival Time 7.216
Data Required Time 8.992
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.000 4.000 active clock edge time
4.000 0.000 pclk_rx
4.000 0.000 tCL FF 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
5.290 1.290 tNET FF 1 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
5.733 0.442 tC2Q FF 58 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.216 1.484 tNET FF 1 R22C30[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk_rx
8.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
9.339 1.339 tNET RR 1 R22C30[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLK
8.992 -0.347 tSu 1 R22C30[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0

Path Statistics:

Clock Skew 0.049
Setup Relationship 4.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.290, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.484, 77.028%; tC2Q: 0.442, 22.972%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.339, 100.000%

Path23

Path Summary:

Slack 1.776
Data Arrival Time 7.216
Data Required Time 8.992
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.000 4.000 active clock edge time
4.000 0.000 pclk_rx
4.000 0.000 tCL FF 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
5.290 1.290 tNET FF 1 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
5.733 0.442 tC2Q FF 58 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.216 1.484 tNET FF 1 R22C30[0][B] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk_rx
8.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
9.339 1.339 tNET RR 1 R22C30[0][B] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLK
8.992 -0.347 tSu 1 R22C30[0][B] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0

Path Statistics:

Clock Skew 0.049
Setup Relationship 4.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.290, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.484, 77.028%; tC2Q: 0.442, 22.972%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.339, 100.000%

Path24

Path Summary:

Slack 1.776
Data Arrival Time 7.216
Data Required Time 8.992
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.000 4.000 active clock edge time
4.000 0.000 pclk_rx
4.000 0.000 tCL FF 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
5.290 1.290 tNET FF 1 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
5.733 0.442 tC2Q FF 58 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.216 1.484 tNET FF 1 R22C30[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk_rx
8.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
9.339 1.339 tNET RR 1 R22C30[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0/CLK
8.992 -0.347 tSu 1 R22C30[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0

Path Statistics:

Clock Skew 0.049
Setup Relationship 4.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.290, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.484, 77.028%; tC2Q: 0.442, 22.972%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.339, 100.000%

Path25

Path Summary:

Slack 1.964
Data Arrival Time 7.033
Data Required Time 8.997
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.000 4.000 active clock edge time
4.000 0.000 pclk_rx
4.000 0.000 tCL FF 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
5.290 1.290 tNET FF 1 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
5.733 0.442 tC2Q FF 58 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.033 1.300 tNET FF 1 R20C30[0][B] gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk_rx
8.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
9.344 1.344 tNET RR 1 R20C30[0][B] gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLK
8.997 -0.347 tSu 1 R20C30[0][B] gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0

Path Statistics:

Clock Skew 0.054
Setup Relationship 4.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.290, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.300, 74.605%; tC2Q: 0.442, 25.395%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.344, 100.000%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 0.281
Data Arrival Time 1.380
Data Required Time 1.099
From u_EasyCDR_Top/u_easycdr/u_share_logic/rst_n_s0
To u_EasyCDR_Top/u_easycdr/u_share_logic/delay_cnt_0_s0
Launch Clk board_clk:[R]
Latch Clk board_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 board_clk
0.000 0.000 tCL RR 1 IOB29[A] board_clk_ibuf/I
0.675 0.675 tINS RR 28 IOB29[A] board_clk_ibuf/O
1.151 0.476 tNET RR 1 R11C27[2][A] u_EasyCDR_Top/u_easycdr/u_share_logic/rst_n_s0/CLK
1.296 0.144 tC2Q RR 7 R11C27[2][A] u_EasyCDR_Top/u_easycdr/u_share_logic/rst_n_s0/Q
1.380 0.084 tNET RR 1 R11C27[1][B] u_EasyCDR_Top/u_easycdr/u_share_logic/delay_cnt_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 board_clk
0.000 0.000 tCL RR 1 IOB29[A] board_clk_ibuf/I
0.675 0.675 tINS RR 28 IOB29[A] board_clk_ibuf/O
1.151 0.476 tNET RR 1 R11C27[1][B] u_EasyCDR_Top/u_easycdr/u_share_logic/delay_cnt_0_s0/CLK
1.099 -0.053 tHld 1 R11C27[1][B] u_EasyCDR_Top/u_easycdr/u_share_logic/delay_cnt_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 58.663%; route: 0.476, 41.337%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.084, 36.842%; tC2Q: 0.144, 63.158%
Required Clock Path Delay cell: 0.675, 58.663%; route: 0.476, 41.337%

Path2

Path Summary:

Slack 0.281
Data Arrival Time 1.380
Data Required Time 1.099
From u_EasyCDR_Top/u_easycdr/u_share_logic/rst_n_s0
To u_EasyCDR_Top/u_easycdr/u_share_logic/delay_cnt_1_s0
Launch Clk board_clk:[R]
Latch Clk board_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 board_clk
0.000 0.000 tCL RR 1 IOB29[A] board_clk_ibuf/I
0.675 0.675 tINS RR 28 IOB29[A] board_clk_ibuf/O
1.151 0.476 tNET RR 1 R11C27[2][A] u_EasyCDR_Top/u_easycdr/u_share_logic/rst_n_s0/CLK
1.296 0.144 tC2Q RR 7 R11C27[2][A] u_EasyCDR_Top/u_easycdr/u_share_logic/rst_n_s0/Q
1.380 0.084 tNET RR 1 R11C27[1][A] u_EasyCDR_Top/u_easycdr/u_share_logic/delay_cnt_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 board_clk
0.000 0.000 tCL RR 1 IOB29[A] board_clk_ibuf/I
0.675 0.675 tINS RR 28 IOB29[A] board_clk_ibuf/O
1.151 0.476 tNET RR 1 R11C27[1][A] u_EasyCDR_Top/u_easycdr/u_share_logic/delay_cnt_1_s0/CLK
1.099 -0.053 tHld 1 R11C27[1][A] u_EasyCDR_Top/u_easycdr/u_share_logic/delay_cnt_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 58.663%; route: 0.476, 41.337%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.084, 36.842%; tC2Q: 0.144, 63.158%
Required Clock Path Delay cell: 0.675, 58.663%; route: 0.476, 41.337%

Path3

Path Summary:

Slack 0.281
Data Arrival Time 1.380
Data Required Time 1.099
From u_EasyCDR_Top/u_easycdr/u_share_logic/rst_n_s0
To u_EasyCDR_Top/u_easycdr/u_share_logic/delay_cnt_2_s0
Launch Clk board_clk:[R]
Latch Clk board_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 board_clk
0.000 0.000 tCL RR 1 IOB29[A] board_clk_ibuf/I
0.675 0.675 tINS RR 28 IOB29[A] board_clk_ibuf/O
1.151 0.476 tNET RR 1 R11C27[2][A] u_EasyCDR_Top/u_easycdr/u_share_logic/rst_n_s0/CLK
1.296 0.144 tC2Q RR 7 R11C27[2][A] u_EasyCDR_Top/u_easycdr/u_share_logic/rst_n_s0/Q
1.380 0.084 tNET RR 1 R11C27[0][B] u_EasyCDR_Top/u_easycdr/u_share_logic/delay_cnt_2_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 board_clk
0.000 0.000 tCL RR 1 IOB29[A] board_clk_ibuf/I
0.675 0.675 tINS RR 28 IOB29[A] board_clk_ibuf/O
1.151 0.476 tNET RR 1 R11C27[0][B] u_EasyCDR_Top/u_easycdr/u_share_logic/delay_cnt_2_s0/CLK
1.099 -0.053 tHld 1 R11C27[0][B] u_EasyCDR_Top/u_easycdr/u_share_logic/delay_cnt_2_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 58.663%; route: 0.476, 41.337%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.084, 36.842%; tC2Q: 0.144, 63.158%
Required Clock Path Delay cell: 0.675, 58.663%; route: 0.476, 41.337%

Path4

Path Summary:

Slack 0.281
Data Arrival Time 1.380
Data Required Time 1.099
From u_EasyCDR_Top/u_easycdr/u_share_logic/rst_n_s0
To u_EasyCDR_Top/u_easycdr/u_share_logic/delay_cnt_3_s0
Launch Clk board_clk:[R]
Latch Clk board_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 board_clk
0.000 0.000 tCL RR 1 IOB29[A] board_clk_ibuf/I
0.675 0.675 tINS RR 28 IOB29[A] board_clk_ibuf/O
1.151 0.476 tNET RR 1 R11C27[2][A] u_EasyCDR_Top/u_easycdr/u_share_logic/rst_n_s0/CLK
1.296 0.144 tC2Q RR 7 R11C27[2][A] u_EasyCDR_Top/u_easycdr/u_share_logic/rst_n_s0/Q
1.380 0.084 tNET RR 1 R11C27[0][A] u_EasyCDR_Top/u_easycdr/u_share_logic/delay_cnt_3_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 board_clk
0.000 0.000 tCL RR 1 IOB29[A] board_clk_ibuf/I
0.675 0.675 tINS RR 28 IOB29[A] board_clk_ibuf/O
1.151 0.476 tNET RR 1 R11C27[0][A] u_EasyCDR_Top/u_easycdr/u_share_logic/delay_cnt_3_s0/CLK
1.099 -0.053 tHld 1 R11C27[0][A] u_EasyCDR_Top/u_easycdr/u_share_logic/delay_cnt_3_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 58.663%; route: 0.476, 41.337%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.084, 36.842%; tC2Q: 0.144, 63.158%
Required Clock Path Delay cell: 0.675, 58.663%; route: 0.476, 41.337%

Path5

Path Summary:

Slack 0.387
Data Arrival Time 1.490
Data Required Time 1.102
From u_EasyCDR_Top/u_easycdr/u_share_logic/rst_n_s0
To u_EasyCDR_Top/u_easycdr/u_share_logic/cen_s0
Launch Clk board_clk:[R]
Latch Clk board_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 board_clk
0.000 0.000 tCL RR 1 IOB29[A] board_clk_ibuf/I
0.675 0.675 tINS RR 28 IOB29[A] board_clk_ibuf/O
1.151 0.476 tNET RR 1 R11C27[2][A] u_EasyCDR_Top/u_easycdr/u_share_logic/rst_n_s0/CLK
1.296 0.144 tC2Q RR 7 R11C27[2][A] u_EasyCDR_Top/u_easycdr/u_share_logic/rst_n_s0/Q
1.490 0.194 tNET RR 1 R11C26[3][A] u_EasyCDR_Top/u_easycdr/u_share_logic/cen_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 board_clk
0.000 0.000 tCL RR 1 IOB29[A] board_clk_ibuf/I
0.675 0.675 tINS RR 28 IOB29[A] board_clk_ibuf/O
1.155 0.480 tNET RR 1 R11C26[3][A] u_EasyCDR_Top/u_easycdr/u_share_logic/cen_s0/CLK
1.102 -0.053 tHld 1 R11C26[3][A] u_EasyCDR_Top/u_easycdr/u_share_logic/cen_s0

Path Statistics:

Clock Skew 0.004
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 58.663%; route: 0.476, 41.337%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.194, 57.396%; tC2Q: 0.144, 42.604%
Required Clock Path Delay cell: 0.675, 58.460%; route: 0.480, 41.540%

Path6

Path Summary:

Slack 0.387
Data Arrival Time 1.490
Data Required Time 1.102
From u_EasyCDR_Top/u_easycdr/u_share_logic/rst_n_s0
To u_EasyCDR_Top/u_easycdr/u_share_logic/reset_o_s0
Launch Clk board_clk:[R]
Latch Clk board_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 board_clk
0.000 0.000 tCL RR 1 IOB29[A] board_clk_ibuf/I
0.675 0.675 tINS RR 28 IOB29[A] board_clk_ibuf/O
1.151 0.476 tNET RR 1 R11C27[2][A] u_EasyCDR_Top/u_easycdr/u_share_logic/rst_n_s0/CLK
1.296 0.144 tC2Q RR 7 R11C27[2][A] u_EasyCDR_Top/u_easycdr/u_share_logic/rst_n_s0/Q
1.490 0.194 tNET RR 1 R11C26[2][A] u_EasyCDR_Top/u_easycdr/u_share_logic/reset_o_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 board_clk
0.000 0.000 tCL RR 1 IOB29[A] board_clk_ibuf/I
0.675 0.675 tINS RR 28 IOB29[A] board_clk_ibuf/O
1.155 0.480 tNET RR 1 R11C26[2][A] u_EasyCDR_Top/u_easycdr/u_share_logic/reset_o_s0/CLK
1.102 -0.053 tHld 1 R11C26[2][A] u_EasyCDR_Top/u_easycdr/u_share_logic/reset_o_s0

Path Statistics:

Clock Skew 0.004
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 58.663%; route: 0.476, 41.337%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.194, 57.396%; tC2Q: 0.144, 42.604%
Required Clock Path Delay cell: 0.675, 58.460%; route: 0.480, 41.540%

Path7

Path Summary:

Slack 0.546
Data Arrival Time 1.674
Data Required Time 1.127
From u_EasyCDR_Top/u_easycdr/u_share_logic/rst_n_s0
To u_EasyCDR_Top/u_easycdr/u_share_logic/resetn_s0
Launch Clk board_clk:[R]
Latch Clk board_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 board_clk
0.000 0.000 tCL RR 1 IOB29[A] board_clk_ibuf/I
0.675 0.675 tINS RR 28 IOB29[A] board_clk_ibuf/O
1.151 0.476 tNET RR 1 R11C27[2][A] u_EasyCDR_Top/u_easycdr/u_share_logic/rst_n_s0/CLK
1.296 0.144 tC2Q RR 7 R11C27[2][A] u_EasyCDR_Top/u_easycdr/u_share_logic/rst_n_s0/Q
1.674 0.378 tNET RR 1 R2C27[0][A] u_EasyCDR_Top/u_easycdr/u_share_logic/resetn_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 board_clk
0.000 0.000 tCL RR 1 IOB29[A] board_clk_ibuf/I
0.675 0.675 tINS RR 28 IOB29[A] board_clk_ibuf/O
1.180 0.505 tNET RR 1 R2C27[0][A] u_EasyCDR_Top/u_easycdr/u_share_logic/resetn_s0/CLK
1.127 -0.053 tHld 1 R2C27[0][A] u_EasyCDR_Top/u_easycdr/u_share_logic/resetn_s0

Path Statistics:

Clock Skew 0.029
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 58.663%; route: 0.476, 41.337%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.378, 72.414%; tC2Q: 0.144, 27.586%
Required Clock Path Delay cell: 0.675, 57.234%; route: 0.505, 42.766%

Path8

Path Summary:

Slack 4.411
Data Arrival Time 4.842
Data Required Time 0.431
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.000 4.000 active clock edge time
4.000 0.000 pclk_rx
4.000 0.000 tCL FF 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
4.479 0.479 tNET FF 1 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
4.637 0.158 tC2Q FR 58 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
4.842 0.205 tNET RR 1 R15C31[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.484 0.484 tNET RR 1 R15C31[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLK
0.431 -0.053 tHld 1 R15C31[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1

Path Statistics:

Clock Skew 0.005
Hold Relationship -4.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.479, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.205, 56.474%; tC2Q: 0.158, 43.526%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.484, 100.000%

Path9

Path Summary:

Slack 4.411
Data Arrival Time 4.842
Data Required Time 0.431
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.000 4.000 active clock edge time
4.000 0.000 pclk_rx
4.000 0.000 tCL FF 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
4.479 0.479 tNET FF 1 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
4.637 0.158 tC2Q FR 58 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
4.842 0.205 tNET RR 1 R15C31[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.484 0.484 tNET RR 1 R15C31[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK
0.431 -0.053 tHld 1 R15C31[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1

Path Statistics:

Clock Skew 0.005
Hold Relationship -4.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.479, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.205, 56.474%; tC2Q: 0.158, 43.526%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.484, 100.000%

Path10

Path Summary:

Slack 4.411
Data Arrival Time 4.842
Data Required Time 0.431
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.000 4.000 active clock edge time
4.000 0.000 pclk_rx
4.000 0.000 tCL FF 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
4.479 0.479 tNET FF 1 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
4.637 0.158 tC2Q FR 58 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
4.842 0.205 tNET RR 1 R15C31[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.484 0.484 tNET RR 1 R15C31[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK
0.431 -0.053 tHld 1 R15C31[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1

Path Statistics:

Clock Skew 0.005
Hold Relationship -4.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.479, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.205, 56.474%; tC2Q: 0.158, 43.526%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.484, 100.000%

Path11

Path Summary:

Slack 4.415
Data Arrival Time 4.842
Data Required Time 0.427
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.000 4.000 active clock edge time
4.000 0.000 pclk_rx
4.000 0.000 tCL FF 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
4.479 0.479 tNET FF 1 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
4.637 0.158 tC2Q FR 58 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
4.842 0.205 tNET RR 1 R15C32[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.480 0.480 tNET RR 1 R15C32[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
0.427 -0.053 tHld 1 R15C32[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1

Path Statistics:

Clock Skew 0.001
Hold Relationship -4.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.479, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.205, 56.474%; tC2Q: 0.158, 43.526%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.480, 100.000%

Path12

Path Summary:

Slack 4.415
Data Arrival Time 4.842
Data Required Time 0.427
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.000 4.000 active clock edge time
4.000 0.000 pclk_rx
4.000 0.000 tCL FF 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
4.479 0.479 tNET FF 1 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
4.637 0.158 tC2Q FR 58 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
4.842 0.205 tNET RR 1 R15C32[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.480 0.480 tNET RR 1 R15C32[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK
0.427 -0.053 tHld 1 R15C32[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1

Path Statistics:

Clock Skew 0.001
Hold Relationship -4.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.479, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.205, 56.474%; tC2Q: 0.158, 43.526%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.480, 100.000%

Path13

Path Summary:

Slack 4.415
Data Arrival Time 4.842
Data Required Time 0.427
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.000 4.000 active clock edge time
4.000 0.000 pclk_rx
4.000 0.000 tCL FF 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
4.479 0.479 tNET FF 1 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
4.637 0.158 tC2Q FR 58 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
4.842 0.205 tNET RR 1 R15C32[1][A] gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.480 0.480 tNET RR 1 R15C32[1][A] gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLK
0.427 -0.053 tHld 1 R15C32[1][A] gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0

Path Statistics:

Clock Skew 0.001
Hold Relationship -4.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.479, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.205, 56.474%; tC2Q: 0.158, 43.526%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.480, 100.000%

Path14

Path Summary:

Slack 4.417
Data Arrival Time 4.836
Data Required Time 0.419
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.000 4.000 active clock edge time
4.000 0.000 pclk_rx
4.000 0.000 tCL FF 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
4.479 0.479 tNET FF 1 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
4.637 0.158 tC2Q FR 58 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
4.836 0.199 tNET RR 1 R14C33[0][A] gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.472 0.472 tNET RR 1 R14C33[0][A] gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLK
0.419 -0.053 tHld 1 R14C33[0][A] gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0

Path Statistics:

Clock Skew -0.007
Hold Relationship -4.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.479, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.199, 55.742%; tC2Q: 0.158, 44.258%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.472, 100.000%

Path15

Path Summary:

Slack 4.421
Data Arrival Time 4.846
Data Required Time 0.425
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.000 4.000 active clock edge time
4.000 0.000 pclk_rx
4.000 0.000 tCL FF 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
4.479 0.479 tNET FF 1 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
4.637 0.158 tC2Q FR 58 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
4.846 0.209 tNET RR 1 R17C33[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.479 0.479 tNET RR 1 R17C33[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLK
0.426 -0.053 tHld 1 R17C33[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1

Path Statistics:

Clock Skew -0.000
Hold Relationship -4.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.479, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.209, 56.948%; tC2Q: 0.158, 43.052%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.479, 100.000%

Path16

Path Summary:

Slack 4.422
Data Arrival Time 4.846
Data Required Time 0.424
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.000 4.000 active clock edge time
4.000 0.000 pclk_rx
4.000 0.000 tCL FF 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
4.479 0.479 tNET FF 1 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
4.637 0.158 tC2Q FR 58 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
4.846 0.209 tNET RR 1 R16C33[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.477 0.477 tNET RR 1 R16C33[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLK
0.424 -0.053 tHld 1 R16C33[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1

Path Statistics:

Clock Skew -0.002
Hold Relationship -4.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.479, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.209, 56.948%; tC2Q: 0.158, 43.052%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.477, 100.000%

Path17

Path Summary:

Slack 4.422
Data Arrival Time 4.846
Data Required Time 0.424
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.000 4.000 active clock edge time
4.000 0.000 pclk_rx
4.000 0.000 tCL FF 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
4.479 0.479 tNET FF 1 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
4.637 0.158 tC2Q FR 58 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
4.846 0.209 tNET RR 1 R16C33[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.477 0.477 tNET RR 1 R16C33[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLK
0.424 -0.053 tHld 1 R16C33[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1

Path Statistics:

Clock Skew -0.002
Hold Relationship -4.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.479, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.209, 56.948%; tC2Q: 0.158, 43.052%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.477, 100.000%

Path18

Path Summary:

Slack 4.422
Data Arrival Time 4.846
Data Required Time 0.424
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.000 4.000 active clock edge time
4.000 0.000 pclk_rx
4.000 0.000 tCL FF 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
4.479 0.479 tNET FF 1 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
4.637 0.158 tC2Q FR 58 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
4.846 0.209 tNET RR 1 R16C33[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.477 0.477 tNET RR 1 R16C33[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLK
0.424 -0.053 tHld 1 R16C33[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1

Path Statistics:

Clock Skew -0.002
Hold Relationship -4.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.479, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.209, 56.948%; tC2Q: 0.158, 43.052%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.477, 100.000%

Path19

Path Summary:

Slack 4.422
Data Arrival Time 4.846
Data Required Time 0.424
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.000 4.000 active clock edge time
4.000 0.000 pclk_rx
4.000 0.000 tCL FF 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
4.479 0.479 tNET FF 1 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
4.637 0.158 tC2Q FR 58 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
4.846 0.209 tNET RR 1 R16C33[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.477 0.477 tNET RR 1 R16C33[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLK
0.424 -0.053 tHld 1 R16C33[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1

Path Statistics:

Clock Skew -0.002
Hold Relationship -4.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.479, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.209, 56.948%; tC2Q: 0.158, 43.052%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.477, 100.000%

Path20

Path Summary:

Slack 4.515
Data Arrival Time 4.942
Data Required Time 0.427
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.000 4.000 active clock edge time
4.000 0.000 pclk_rx
4.000 0.000 tCL FF 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
4.479 0.479 tNET FF 1 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
4.637 0.158 tC2Q FR 58 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
4.942 0.305 tNET RR 1 R15C30[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.480 0.480 tNET RR 1 R15C30[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
0.427 -0.053 tHld 1 R15C30[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1

Path Statistics:

Clock Skew 0.001
Hold Relationship -4.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.479, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.305, 65.875%; tC2Q: 0.158, 34.125%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.480, 100.000%

Path21

Path Summary:

Slack 4.515
Data Arrival Time 4.942
Data Required Time 0.427
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.000 4.000 active clock edge time
4.000 0.000 pclk_rx
4.000 0.000 tCL FF 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
4.479 0.479 tNET FF 1 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
4.637 0.158 tC2Q FR 58 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
4.942 0.305 tNET RR 1 R15C30[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.480 0.480 tNET RR 1 R15C30[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK
0.427 -0.053 tHld 1 R15C30[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1

Path Statistics:

Clock Skew 0.001
Hold Relationship -4.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.479, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.305, 65.875%; tC2Q: 0.158, 34.125%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.480, 100.000%

Path22

Path Summary:

Slack 4.519
Data Arrival Time 4.946
Data Required Time 0.427
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.000 4.000 active clock edge time
4.000 0.000 pclk_rx
4.000 0.000 tCL FF 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
4.479 0.479 tNET FF 1 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
4.637 0.158 tC2Q FR 58 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
4.946 0.309 tNET RR 1 R18C33[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.480 0.480 tNET RR 1 R18C33[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/CLK
0.427 -0.053 tHld 1 R18C33[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1

Path Statistics:

Clock Skew 0.001
Hold Relationship -4.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.479, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.309, 66.167%; tC2Q: 0.158, 33.833%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.480, 100.000%

Path23

Path Summary:

Slack 4.519
Data Arrival Time 4.946
Data Required Time 0.427
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.000 4.000 active clock edge time
4.000 0.000 pclk_rx
4.000 0.000 tCL FF 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
4.479 0.479 tNET FF 1 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
4.637 0.158 tC2Q FR 58 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
4.946 0.309 tNET RR 1 R18C33[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.480 0.480 tNET RR 1 R18C33[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLK
0.427 -0.053 tHld 1 R18C33[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1

Path Statistics:

Clock Skew 0.001
Hold Relationship -4.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.479, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.309, 66.167%; tC2Q: 0.158, 33.833%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.480, 100.000%

Path24

Path Summary:

Slack 4.519
Data Arrival Time 4.946
Data Required Time 0.427
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.000 4.000 active clock edge time
4.000 0.000 pclk_rx
4.000 0.000 tCL FF 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
4.479 0.479 tNET FF 1 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
4.637 0.158 tC2Q FR 58 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
4.946 0.309 tNET RR 1 R18C33[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.480 0.480 tNET RR 1 R18C33[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLK
0.427 -0.053 tHld 1 R18C33[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1

Path Statistics:

Clock Skew 0.001
Hold Relationship -4.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.479, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.309, 66.167%; tC2Q: 0.158, 33.833%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.480, 100.000%

Path25

Path Summary:

Slack 4.519
Data Arrival Time 4.946
Data Required Time 0.427
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1
Launch Clk pclk_rx:[F]
Latch Clk pclk_rx:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.000 4.000 active clock edge time
4.000 0.000 pclk_rx
4.000 0.000 tCL FF 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
4.479 0.479 tNET FF 1 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
4.637 0.158 tC2Q FR 58 R15C33[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
4.946 0.309 tNET RR 1 R18C33[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR 422 TOPSIDE[0] u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
0.480 0.480 tNET RR 1 R18C33[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLK
0.427 -0.053 tHld 1 R18C33[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1

Path Statistics:

Clock Skew 0.001
Hold Relationship -4.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.479, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.309, 66.167%; tC2Q: 0.158, 33.833%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.480, 100.000%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack: 2.175
Actual Width: 3.175
Required Width: 1.000
Type: Low Pulse Width
Clock: pclk_rx
Objects: gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s

Late clock Path:

AT DELAY TYPE RF NODE
4.000 0.000 active clock edge time
4.000 0.000 pclk_rx
4.000 0.000 tCL FF u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
5.307 1.307 tNET FF gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s/CLKB

Early clock Path:

AT DELAY TYPE RF NODE
8.000 0.000 active clock edge time
8.000 0.000 pclk_rx
8.000 0.000 tCL RR u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
8.482 0.482 tNET RR gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s/CLKB

MPW2

MPW Summary:

Slack: 2.176
Actual Width: 3.176
Required Width: 1.000
Type: High Pulse Width
Clock: pclk_rx
Objects: gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
1.310 1.310 tNET RR gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s/CLKB

Early clock Path:

AT DELAY TYPE RF NODE
4.000 0.000 active clock edge time
4.000 0.000 pclk_rx
4.000 0.000 tCL FF u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
4.487 0.487 tNET FF gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s/CLKB

MPW3

MPW Summary:

Slack: 2.181
Actual Width: 3.181
Required Width: 1.000
Type: Low Pulse Width
Clock: pclk_rx
Objects: gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Late clock Path:

AT DELAY TYPE RF NODE
4.000 0.000 active clock edge time
4.000 0.000 pclk_rx
4.000 0.000 tCL FF u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
5.297 1.297 tNET FF gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA

Early clock Path:

AT DELAY TYPE RF NODE
8.000 0.000 active clock edge time
8.000 0.000 pclk_rx
8.000 0.000 tCL RR u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
8.478 0.478 tNET RR gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA

MPW4

MPW Summary:

Slack: 2.182
Actual Width: 3.182
Required Width: 1.000
Type: High Pulse Width
Clock: pclk_rx
Objects: gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk_rx
0.000 0.000 tCL RR u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
1.301 1.301 tNET RR gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA

Early clock Path:

AT DELAY TYPE RF NODE
4.000 0.000 active clock edge time
4.000 0.000 pclk_rx
4.000 0.000 tCL FF u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
4.483 0.483 tNET FF gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA

MPW5

MPW Summary:

Slack: 2.908
Actual Width: 3.158
Required Width: 0.250
Type: Low Pulse Width
Clock: pclk_rx
Objects: gw_gao_inst_0/u_la0_top/triger_s0

Late clock Path:

AT DELAY TYPE RF NODE
4.000 0.000 active clock edge time
4.000 0.000 pclk_rx
4.000 0.000 tCL FF u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
5.352 1.352 tNET FF gw_gao_inst_0/u_la0_top/triger_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
8.000 0.000 active clock edge time
8.000 0.000 pclk_rx
8.000 0.000 tCL RR u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
8.510 0.510 tNET RR gw_gao_inst_0/u_la0_top/triger_s0/CLK

MPW6

MPW Summary:

Slack: 2.908
Actual Width: 3.158
Required Width: 0.250
Type: Low Pulse Width
Clock: pclk_rx
Objects: gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3

Late clock Path:

AT DELAY TYPE RF NODE
4.000 0.000 active clock edge time
4.000 0.000 pclk_rx
4.000 0.000 tCL FF u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
5.352 1.352 tNET FF gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLK

Early clock Path:

AT DELAY TYPE RF NODE
8.000 0.000 active clock edge time
8.000 0.000 pclk_rx
8.000 0.000 tCL RR u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
8.510 0.510 tNET RR gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLK

MPW7

MPW Summary:

Slack: 2.908
Actual Width: 3.158
Required Width: 0.250
Type: Low Pulse Width
Clock: pclk_rx
Objects: gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1

Late clock Path:

AT DELAY TYPE RF NODE
4.000 0.000 active clock edge time
4.000 0.000 pclk_rx
4.000 0.000 tCL FF u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
5.352 1.352 tNET FF gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK

Early clock Path:

AT DELAY TYPE RF NODE
8.000 0.000 active clock edge time
8.000 0.000 pclk_rx
8.000 0.000 tCL RR u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
8.510 0.510 tNET RR gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK

MPW8

MPW Summary:

Slack: 2.909
Actual Width: 3.159
Required Width: 0.250
Type: Low Pulse Width
Clock: pclk_rx
Objects: u_EasyCDR_Top/u_easycdr/u_easycdr_32/dout_en_s0

Late clock Path:

AT DELAY TYPE RF NODE
4.000 0.000 active clock edge time
4.000 0.000 pclk_rx
4.000 0.000 tCL FF u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
5.349 1.349 tNET FF u_EasyCDR_Top/u_easycdr/u_easycdr_32/dout_en_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
8.000 0.000 active clock edge time
8.000 0.000 pclk_rx
8.000 0.000 tCL RR u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
8.508 0.508 tNET RR u_EasyCDR_Top/u_easycdr/u_easycdr_32/dout_en_s0/CLK

MPW9

MPW Summary:

Slack: 2.909
Actual Width: 3.159
Required Width: 0.250
Type: Low Pulse Width
Clock: pclk_rx
Objects: u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_word_align/data_location_3_s2

Late clock Path:

AT DELAY TYPE RF NODE
4.000 0.000 active clock edge time
4.000 0.000 pclk_rx
4.000 0.000 tCL FF u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
5.349 1.349 tNET FF u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_word_align/data_location_3_s2/CLK

Early clock Path:

AT DELAY TYPE RF NODE
8.000 0.000 active clock edge time
8.000 0.000 pclk_rx
8.000 0.000 tCL RR u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
8.508 0.508 tNET RR u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_word_align/data_location_3_s2/CLK

MPW10

MPW Summary:

Slack: 2.909
Actual Width: 3.159
Required Width: 0.250
Type: Low Pulse Width
Clock: pclk_rx
Objects: u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_decoder_8b10b/dout_dat_6_s0

Late clock Path:

AT DELAY TYPE RF NODE
4.000 0.000 active clock edge time
4.000 0.000 pclk_rx
4.000 0.000 tCL FF u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
5.349 1.349 tNET FF u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_decoder_8b10b/dout_dat_6_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
8.000 0.000 active clock edge time
8.000 0.000 pclk_rx
8.000 0.000 tCL RR u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT
8.508 0.508 tNET RR u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_decoder_8b10b/dout_dat_6_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT NET NAME WORST SLACK MAX DELAY
422 u_motivation_response_0 1.136 1.354
217 control0[0] 42.604 2.380
58 rst_ao 1.572 1.775
54 pll_clkout0_div_tx 5.402 1.347
53 data_to_word_counter_15_5 42.604 1.145
45 remained_cnt[0] 2.758 1.529
41 gearbox_err 4.714 1.419
39 stor_18_11 4.562 1.613
38 remained_cnt[1] 1.136 1.256
38 n20_3 47.006 0.770

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC ROUTE CONGESTIONS
R17C34 50.00%
R18C31 50.00%
R22C31 48.61%
R24C34 45.83%
R24C22 43.06%
R24C32 43.06%
R24C35 40.28%
R21C32 40.28%
R22C35 40.28%
R17C23 40.28%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type State Detail Command
TC_CLOCK Actived create_clock -name tck_pad -period 50 -waveform {0 25} [get_ports {tck_pad_i}]
TC_CLOCK Actived create_clock -name board_clk -period 20 -waveform {0 10} [get_pins {board_clk_ibuf/I}]
TC_GENERATED_CLOCK Actived create_generated_clock -name hclk_0_rx -source [get_pins {board_clk_ibuf/I}] -master_clock board_clk -divide_by 2 -multiply_by 20 [get_pins {u_motivation_response/u_pll_hclk/PLLA_inst/CLKOUT0}]
TC_GENERATED_CLOCK Actived create_generated_clock -name hclk_180_rx -source [get_pins {board_clk_ibuf/I}] -master_clock board_clk -divide_by 2 -multiply_by 20 -phase 180 [get_pins {u_motivation_response/u_pll_hclk/PLLA_inst/CLKOUT2}]
TC_GENERATED_CLOCK Actived create_generated_clock -name hclk_90_rx -source [get_pins {board_clk_ibuf/I}] -master_clock board_clk -divide_by 2 -multiply_by 20 -phase 90 [get_pins {u_motivation_response/u_pll_hclk/PLLA_inst/CLKOUT1}]
TC_GENERATED_CLOCK Actived create_generated_clock -name hclk_0_tx -source [get_pins {board_clk_ibuf/I}] -master_clock board_clk -divide_by 2 -multiply_by 20 [get_pins {u_motivation_response/u_pll_hclk_tx/PLLA_inst/CLKOUT0}]
TC_GENERATED_CLOCK Actived create_generated_clock -name pclk_rx -source [get_pins {u_motivation_response/u_pll_hclk/PLLA_inst/CLKOUT0}] -master_clock hclk_0_rx -divide_by 4 -multiply_by 1 [get_pins {u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT}]
TC_GENERATED_CLOCK Actived create_generated_clock -name hclk_270_rx -source [get_pins {board_clk_ibuf/I}] -master_clock board_clk -divide_by 2 -multiply_by 20 -phase 270 [get_pins {u_motivation_response/u_pll_hclk/PLLA_inst/CLKOUT3}]
TC_GENERATED_CLOCK Actived create_generated_clock -name pclk_tx -source [get_pins {u_motivation_response/u_pll_hclk_tx/PLLA_inst/CLKOUT0}] -master_clock hclk_0_tx -divide_by 5 -multiply_by 1 [get_pins {u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT}]
TC_FALSE_PATH Actived set_false_path -from [get_clocks {board_clk}] -to [get_clocks {hclk_0_rx hclk_90_rx hclk_180_rx hclk_270_rx hclk_0_tx pclk_rx pclk_tx}]
TC_FALSE_PATH Actived set_false_path -from [get_clocks {pclk_tx pclk_rx}] -to [get_clocks {tck_pad}]
TC_FALSE_PATH Actived set_false_path -from [get_clocks {tck_pad}] -to [get_clocks {pclk_tx pclk_rx}]