Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | C:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\EQUALIZER\data\Equalizer_wrap.v C:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\EQUALIZER\data\Equalizer.v |
GowinSynthesis Constraints File | --- |
Version | V1.9.9 Beta-3 |
Part Number | GW2A-LV55PG484C8/I7 |
Device | GW2A-55 |
Device Version | C |
Created Time | Mon Aug 21 10:14:34 2023 |
Legal Announcement | Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | Equalizer_Top |
Synthesis Process | Running parser: CPU time = 0h 0m 0.484s, Elapsed time = 0h 0m 0.527s, Peak memory usage = 48.281MB Running netlist conversion: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.03s, Peak memory usage = 48.281MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.159s, Peak memory usage = 48.281MB Optimizing Phase 1: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.127s, Peak memory usage = 48.281MB Optimizing Phase 2: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.153s, Peak memory usage = 48.281MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.049s, Peak memory usage = 48.281MB Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.021s, Peak memory usage = 48.281MB Inferring Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.027s, Peak memory usage = 48.281MB Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 48.281MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.265s, Elapsed time = 0h 0m 0.269s, Peak memory usage = 48.281MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.07s, Peak memory usage = 48.281MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.103s, Peak memory usage = 48.281MB Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 60.309MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.224s, Peak memory usage = 60.309MB Generate output files: CPU time = 0h 0m 0.296s, Elapsed time = 0h 0m 0.328s, Peak memory usage = 65.676MB |
Total Time and Memory Usage | CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s, Peak memory usage = 65.676MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 52 |
I/O Buf | 52 |
    IBUF | 28 |
    OBUF | 24 |
Register | 3307 |
    DFFPE | 30 |
    DFFC | 5 |
    DFFCE | 3272 |
LUT | 2323 |
    LUT2 | 299 |
    LUT3 | 1441 |
    LUT4 | 583 |
ALU | 186 |
    ALU | 186 |
INV | 3 |
    INV | 3 |
DSP | |
    MULT36X36 | 5 |
BSRAM | 5 |
    pROM | 5 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 2512(2326 LUT, 186 ALU) / 54720 | 5% |
Register | 3307 / 41997 | 8% |
  --Register as Latch | 0 / 41997 | 0% |
  --Register as FF | 3307 / 41997 | 8% |
BSRAM | 5 / 140 | 4% |
Timing
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|
clk | Base | 10.000 | 100.0 | 0.000 | 5.000 | clk_ibuf/I |
Max Frequency Summary:
No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | clk | 100.0(MHz) | 109.6(MHz) | 7 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | 0.877 |
Data Arrival Time | 9.951 |
Data Required Time | 10.828 |
From | Equalizer_inst/cnt_band_1_s0 |
To | Equalizer_inst/prod_1_0_s0 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 3312 | clk_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | Equalizer_inst/cnt_band_1_s0/CLK |
1.095 | 0.232 | tC2Q | RF | 855 | Equalizer_inst/cnt_band_1_s0/Q |
1.332 | 0.237 | tNET | FF | 1 | Equalizer_inst/n6886_s5/I1 |
1.887 | 0.555 | tINS | FF | 90 | Equalizer_inst/n6886_s5/F |
2.124 | 0.237 | tNET | FF | 1 | Equalizer_inst/n6918_s19/I1 |
2.679 | 0.555 | tINS | FF | 1 | Equalizer_inst/n6918_s19/F |
2.916 | 0.237 | tNET | FF | 1 | Equalizer_inst/n6918_s30/I0 |
3.433 | 0.517 | tINS | FF | 1 | Equalizer_inst/n6918_s30/F |
3.670 | 0.237 | tNET | FF | 1 | Equalizer_inst/n6918_s27/I0 |
3.773 | 0.103 | tINS | FF | 1 | Equalizer_inst/n6918_s27/O |
4.010 | 0.237 | tNET | FF | 1 | Equalizer_inst/n6918_s25/I1 |
4.113 | 0.103 | tINS | FF | 2 | Equalizer_inst/n6918_s25/O |
4.350 | 0.237 | tNET | FF | 1 | Equalizer_inst/n6940_s0/I1 |
4.905 | 0.555 | tINS | FF | 1 | Equalizer_inst/n6940_s0/F |
5.141 | 0.237 | tNET | FF | 39 | Equalizer_inst/mult_12140_s2/B[6] |
8.922 | 3.780 | tINS | FF | 1 | Equalizer_inst/mult_12140_s2/DOUT[0] |
9.159 | 0.237 | tNET | FF | 1 | Equalizer_inst/n13191_s2/I1 |
9.714 | 0.555 | tINS | FF | 1 | Equalizer_inst/n13191_s2/F |
9.951 | 0.237 | tNET | FF | 1 | Equalizer_inst/prod_1_0_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk | |||
10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 3312 | clk_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | Equalizer_inst/prod_1_0_s0/CLK |
10.828 | -0.035 | tSu | 1 | Equalizer_inst/prod_1_0_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 7 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 6.723, 73.976%; route: 2.133, 23.471%; tC2Q: 0.232, 2.553% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 2
Path Summary:Slack | 0.877 |
Data Arrival Time | 9.951 |
Data Required Time | 10.828 |
From | Equalizer_inst/cnt_band_1_s0 |
To | Equalizer_inst/prod_1_1_s0 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 3312 | clk_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | Equalizer_inst/cnt_band_1_s0/CLK |
1.095 | 0.232 | tC2Q | RF | 855 | Equalizer_inst/cnt_band_1_s0/Q |
1.332 | 0.237 | tNET | FF | 1 | Equalizer_inst/n6886_s5/I1 |
1.887 | 0.555 | tINS | FF | 90 | Equalizer_inst/n6886_s5/F |
2.124 | 0.237 | tNET | FF | 1 | Equalizer_inst/n6918_s19/I1 |
2.679 | 0.555 | tINS | FF | 1 | Equalizer_inst/n6918_s19/F |
2.916 | 0.237 | tNET | FF | 1 | Equalizer_inst/n6918_s30/I0 |
3.433 | 0.517 | tINS | FF | 1 | Equalizer_inst/n6918_s30/F |
3.670 | 0.237 | tNET | FF | 1 | Equalizer_inst/n6918_s27/I0 |
3.773 | 0.103 | tINS | FF | 1 | Equalizer_inst/n6918_s27/O |
4.010 | 0.237 | tNET | FF | 1 | Equalizer_inst/n6918_s25/I1 |
4.113 | 0.103 | tINS | FF | 2 | Equalizer_inst/n6918_s25/O |
4.350 | 0.237 | tNET | FF | 1 | Equalizer_inst/n6940_s0/I1 |
4.905 | 0.555 | tINS | FF | 1 | Equalizer_inst/n6940_s0/F |
5.141 | 0.237 | tNET | FF | 39 | Equalizer_inst/mult_12140_s2/B[6] |
8.922 | 3.780 | tINS | FF | 1 | Equalizer_inst/mult_12140_s2/DOUT[1] |
9.159 | 0.237 | tNET | FF | 1 | Equalizer_inst/n13190_s2/I1 |
9.714 | 0.555 | tINS | FF | 1 | Equalizer_inst/n13190_s2/F |
9.951 | 0.237 | tNET | FF | 1 | Equalizer_inst/prod_1_1_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk | |||
10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 3312 | clk_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | Equalizer_inst/prod_1_1_s0/CLK |
10.828 | -0.035 | tSu | 1 | Equalizer_inst/prod_1_1_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 7 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 6.723, 73.976%; route: 2.133, 23.471%; tC2Q: 0.232, 2.553% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 3
Path Summary:Slack | 0.877 |
Data Arrival Time | 9.951 |
Data Required Time | 10.828 |
From | Equalizer_inst/cnt_band_1_s0 |
To | Equalizer_inst/prod_1_2_s0 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 3312 | clk_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | Equalizer_inst/cnt_band_1_s0/CLK |
1.095 | 0.232 | tC2Q | RF | 855 | Equalizer_inst/cnt_band_1_s0/Q |
1.332 | 0.237 | tNET | FF | 1 | Equalizer_inst/n6886_s5/I1 |
1.887 | 0.555 | tINS | FF | 90 | Equalizer_inst/n6886_s5/F |
2.124 | 0.237 | tNET | FF | 1 | Equalizer_inst/n6918_s19/I1 |
2.679 | 0.555 | tINS | FF | 1 | Equalizer_inst/n6918_s19/F |
2.916 | 0.237 | tNET | FF | 1 | Equalizer_inst/n6918_s30/I0 |
3.433 | 0.517 | tINS | FF | 1 | Equalizer_inst/n6918_s30/F |
3.670 | 0.237 | tNET | FF | 1 | Equalizer_inst/n6918_s27/I0 |
3.773 | 0.103 | tINS | FF | 1 | Equalizer_inst/n6918_s27/O |
4.010 | 0.237 | tNET | FF | 1 | Equalizer_inst/n6918_s25/I1 |
4.113 | 0.103 | tINS | FF | 2 | Equalizer_inst/n6918_s25/O |
4.350 | 0.237 | tNET | FF | 1 | Equalizer_inst/n6940_s0/I1 |
4.905 | 0.555 | tINS | FF | 1 | Equalizer_inst/n6940_s0/F |
5.141 | 0.237 | tNET | FF | 39 | Equalizer_inst/mult_12140_s2/B[6] |
8.922 | 3.780 | tINS | FF | 1 | Equalizer_inst/mult_12140_s2/DOUT[2] |
9.159 | 0.237 | tNET | FF | 1 | Equalizer_inst/n13189_s2/I1 |
9.714 | 0.555 | tINS | FF | 1 | Equalizer_inst/n13189_s2/F |
9.951 | 0.237 | tNET | FF | 1 | Equalizer_inst/prod_1_2_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk | |||
10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 3312 | clk_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | Equalizer_inst/prod_1_2_s0/CLK |
10.828 | -0.035 | tSu | 1 | Equalizer_inst/prod_1_2_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 7 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 6.723, 73.976%; route: 2.133, 23.471%; tC2Q: 0.232, 2.553% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 4
Path Summary:Slack | 0.877 |
Data Arrival Time | 9.951 |
Data Required Time | 10.828 |
From | Equalizer_inst/cnt_band_1_s0 |
To | Equalizer_inst/prod_1_3_s0 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 3312 | clk_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | Equalizer_inst/cnt_band_1_s0/CLK |
1.095 | 0.232 | tC2Q | RF | 855 | Equalizer_inst/cnt_band_1_s0/Q |
1.332 | 0.237 | tNET | FF | 1 | Equalizer_inst/n6886_s5/I1 |
1.887 | 0.555 | tINS | FF | 90 | Equalizer_inst/n6886_s5/F |
2.124 | 0.237 | tNET | FF | 1 | Equalizer_inst/n6918_s19/I1 |
2.679 | 0.555 | tINS | FF | 1 | Equalizer_inst/n6918_s19/F |
2.916 | 0.237 | tNET | FF | 1 | Equalizer_inst/n6918_s30/I0 |
3.433 | 0.517 | tINS | FF | 1 | Equalizer_inst/n6918_s30/F |
3.670 | 0.237 | tNET | FF | 1 | Equalizer_inst/n6918_s27/I0 |
3.773 | 0.103 | tINS | FF | 1 | Equalizer_inst/n6918_s27/O |
4.010 | 0.237 | tNET | FF | 1 | Equalizer_inst/n6918_s25/I1 |
4.113 | 0.103 | tINS | FF | 2 | Equalizer_inst/n6918_s25/O |
4.350 | 0.237 | tNET | FF | 1 | Equalizer_inst/n6940_s0/I1 |
4.905 | 0.555 | tINS | FF | 1 | Equalizer_inst/n6940_s0/F |
5.141 | 0.237 | tNET | FF | 39 | Equalizer_inst/mult_12140_s2/B[6] |
8.922 | 3.780 | tINS | FF | 1 | Equalizer_inst/mult_12140_s2/DOUT[3] |
9.159 | 0.237 | tNET | FF | 1 | Equalizer_inst/n13188_s2/I1 |
9.714 | 0.555 | tINS | FF | 1 | Equalizer_inst/n13188_s2/F |
9.951 | 0.237 | tNET | FF | 1 | Equalizer_inst/prod_1_3_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk | |||
10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 3312 | clk_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | Equalizer_inst/prod_1_3_s0/CLK |
10.828 | -0.035 | tSu | 1 | Equalizer_inst/prod_1_3_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 7 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 6.723, 73.976%; route: 2.133, 23.471%; tC2Q: 0.232, 2.553% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 5
Path Summary:Slack | 0.877 |
Data Arrival Time | 9.951 |
Data Required Time | 10.828 |
From | Equalizer_inst/cnt_band_1_s0 |
To | Equalizer_inst/prod_1_4_s0 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 3312 | clk_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | Equalizer_inst/cnt_band_1_s0/CLK |
1.095 | 0.232 | tC2Q | RF | 855 | Equalizer_inst/cnt_band_1_s0/Q |
1.332 | 0.237 | tNET | FF | 1 | Equalizer_inst/n6886_s5/I1 |
1.887 | 0.555 | tINS | FF | 90 | Equalizer_inst/n6886_s5/F |
2.124 | 0.237 | tNET | FF | 1 | Equalizer_inst/n6918_s19/I1 |
2.679 | 0.555 | tINS | FF | 1 | Equalizer_inst/n6918_s19/F |
2.916 | 0.237 | tNET | FF | 1 | Equalizer_inst/n6918_s30/I0 |
3.433 | 0.517 | tINS | FF | 1 | Equalizer_inst/n6918_s30/F |
3.670 | 0.237 | tNET | FF | 1 | Equalizer_inst/n6918_s27/I0 |
3.773 | 0.103 | tINS | FF | 1 | Equalizer_inst/n6918_s27/O |
4.010 | 0.237 | tNET | FF | 1 | Equalizer_inst/n6918_s25/I1 |
4.113 | 0.103 | tINS | FF | 2 | Equalizer_inst/n6918_s25/O |
4.350 | 0.237 | tNET | FF | 1 | Equalizer_inst/n6940_s0/I1 |
4.905 | 0.555 | tINS | FF | 1 | Equalizer_inst/n6940_s0/F |
5.141 | 0.237 | tNET | FF | 39 | Equalizer_inst/mult_12140_s2/B[6] |
8.922 | 3.780 | tINS | FF | 1 | Equalizer_inst/mult_12140_s2/DOUT[4] |
9.159 | 0.237 | tNET | FF | 1 | Equalizer_inst/n13187_s2/I1 |
9.714 | 0.555 | tINS | FF | 1 | Equalizer_inst/n13187_s2/F |
9.951 | 0.237 | tNET | FF | 1 | Equalizer_inst/prod_1_4_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk | |||
10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 3312 | clk_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | Equalizer_inst/prod_1_4_s0/CLK |
10.828 | -0.035 | tSu | 1 | Equalizer_inst/prod_1_4_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 7 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 6.723, 73.976%; route: 2.133, 23.471%; tC2Q: 0.232, 2.553% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |