Timing Messages
Report Title | Timing Analysis Report |
Design File | E:\myWork\IP\releaseVerify\RefDesign\DSP_Math\zipFile\1994\FP_Div_RefDesign\proj\impl\gwsynthesis\FP_Div.vg |
Physical Constraints File | E:\myWork\IP\releaseVerify\RefDesign\DSP_Math\zipFile\1994\FP_Div_RefDesign\proj\src\FP_Div.cst |
Timing Constraint File | E:\myWork\IP\releaseVerify\RefDesign\DSP_Math\zipFile\1994\FP_Div_RefDesign\proj\src\FP_Div.sdc |
Version | V1.9.9 Beta-4 |
Part Number | GW2A-LV55PG484C8/I7 |
Device | GW2A-55 |
Created Time | Thu Sep 07 17:01:15 2023 |
Legal Announcement | Copyright (C)2014-2023 Gowin Semiconductor Corporation. All rights reserved. |
Timing Summaries
STA Tool Run Summary:
Setup Delay Model | Slow 0.95V 85C C8/I7 |
Hold Delay Model | Fast 1.05V 0C C8/I7 |
Numbers of Paths Analyzed | 8935 |
Numbers of Endpoints Analyzed | 9287 |
Numbers of Falling Endpoints | 3 |
Numbers of Setup Violated Endpoints | 0 |
Numbers of Hold Violated Endpoints | 0 |
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Objects |
---|---|---|---|---|---|---|---|---|
clk | Base | 20.000 | 50.000 | 0.000 | 10.000 | clk | ||
tck_pad_i | Base | 50.000 | 20.000 | 0.000 | 25.000 | tck_pad_i |
Max Frequency Summary:
NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | clk | 50.000(MHz) | 79.419(MHz) | 14 | TOP |
2 | tck_pad_i | 20.000(MHz) | 132.489(MHz) | 5 | TOP |
Total Negative Slack Summary:
Clock Name | Analysis Type | Endpoints TNS | Number of Endpoints |
---|---|---|---|
clk | Setup | 0.000 | 0 |
clk | Hold | 0.000 | 0 |
tck_pad_i | Setup | 0.000 | 0 |
tck_pad_i | Hold | 0.000 | 0 |
Timing Details
Path Slacks Table:
Setup Paths Table
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 4.425 | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/D | tck_pad_i:[R] | clk:[R] | 10.000 | 1.221 | 4.284 |
2 | 4.433 | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CE | tck_pad_i:[R] | clk:[R] | 10.000 | 1.221 | 4.276 |
3 | 4.621 | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/D | tck_pad_i:[R] | clk:[R] | 10.000 | 1.221 | 4.088 |
4 | 4.649 | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/D | tck_pad_i:[R] | clk:[R] | 10.000 | 1.221 | 4.060 |
5 | 4.682 | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/D | tck_pad_i:[R] | clk:[R] | 10.000 | 1.221 | 4.027 |
6 | 4.717 | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/D | tck_pad_i:[R] | clk:[R] | 10.000 | 1.221 | 3.992 |
7 | 4.898 | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/D | tck_pad_i:[R] | clk:[R] | 10.000 | 1.221 | 3.812 |
8 | 4.916 | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/D | tck_pad_i:[R] | clk:[R] | 10.000 | 1.221 | 3.793 |
9 | 5.112 | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/D | tck_pad_i:[R] | clk:[R] | 10.000 | 1.221 | 3.597 |
10 | 5.112 | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/D | tck_pad_i:[R] | clk:[R] | 10.000 | 1.221 | 3.597 |
11 | 5.142 | gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_10_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CE | tck_pad_i:[R] | clk:[R] | 10.000 | 1.221 | 3.567 |
12 | 5.678 | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/D | tck_pad_i:[R] | clk:[R] | 10.000 | 1.221 | 3.031 |
13 | 5.699 | gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_1_s0/Q | gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CE | tck_pad_i:[R] | clk:[R] | 10.000 | 1.221 | 3.010 |
14 | 5.722 | gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_10_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CE | tck_pad_i:[R] | clk:[R] | 10.000 | 1.221 | 2.988 |
15 | 5.866 | gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_10_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/D | tck_pad_i:[R] | clk:[R] | 10.000 | 1.221 | 2.843 |
16 | 6.063 | gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_1_s0/Q | gw_gao_inst_0/u_la0_top/triger_s0/D | tck_pad_i:[R] | clk:[R] | 10.000 | 1.221 | 2.646 |
17 | 6.110 | gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_1_s0/Q | gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/D | tck_pad_i:[R] | clk:[R] | 10.000 | 1.221 | 2.599 |
18 | 6.131 | gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_1_s0/Q | gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/D | tck_pad_i:[R] | clk:[R] | 10.000 | 1.221 | 2.578 |
19 | 6.131 | gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_1_s0/Q | gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/D | tck_pad_i:[R] | clk:[R] | 10.000 | 1.221 | 2.578 |
20 | 6.154 | gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_1_s0/Q | gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/D | tck_pad_i:[R] | clk:[R] | 10.000 | 1.221 | 2.555 |
21 | 6.486 | gw_gao_inst_0/u_la0_top/capture_windows_num_0_s0/Q | gw_gao_inst_0/u_la0_top/start_reg_s0/D | tck_pad_i:[R] | clk:[R] | 10.000 | 1.221 | 2.223 |
22 | 7.052 | gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_2_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/D | tck_pad_i:[R] | clk:[R] | 10.000 | 1.221 | 1.658 |
23 | 7.109 | gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_0_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/D | tck_pad_i:[R] | clk:[R] | 10.000 | 1.221 | 1.601 |
24 | 7.226 | gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_1_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/D | tck_pad_i:[R] | clk:[R] | 10.000 | 1.221 | 1.483 |
25 | 7.237 | gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_3_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/D | tck_pad_i:[R] | clk:[R] | 10.000 | 1.221 | 1.472 |
Hold Paths Table
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 0.190 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/CEA | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.202 |
2 | 0.190 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/CEA | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.202 |
3 | 0.190 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CEA | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.202 |
4 | 0.190 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CEA | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.202 |
5 | 0.190 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CEA | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.202 |
6 | 0.190 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CEA | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.202 |
7 | 0.190 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CEA | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.202 |
8 | 0.213 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_91_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/DI[11] | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.462 |
9 | 0.213 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_90_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/DI[10] | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.462 |
10 | 0.213 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_88_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/DI[8] | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.462 |
11 | 0.213 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_57_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[9] | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.462 |
12 | 0.213 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_15_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[15] | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.462 |
13 | 0.213 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_3_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[3] | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.462 |
14 | 0.225 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_95_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/DI[15] | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.474 |
15 | 0.225 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_81_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/DI[1] | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.474 |
16 | 0.225 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_28_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[12] | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.474 |
17 | 0.225 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_2_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[2] | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.474 |
18 | 0.335 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_89_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/DI[9] | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.584 |
19 | 0.335 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_20_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[4] | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.584 |
20 | 0.335 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_16_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[0] | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.584 |
21 | 0.347 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_30_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[14] | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.596 |
22 | 0.351 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_100_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/DI[4] | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.600 |
23 | 0.351 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_93_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/DI[13] | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.600 |
24 | 0.351 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_24_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[8] | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.600 |
25 | 0.351 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_23_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[7] | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.600 |
Recovery Paths Table
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 7.980 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR | clk:[F] | clk:[R] | 10.000 | 0.023 | 1.962 |
2 | 7.980 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR | clk:[F] | clk:[R] | 10.000 | 0.023 | 1.962 |
3 | 8.092 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR | clk:[F] | clk:[R] | 10.000 | 0.023 | 1.850 |
4 | 8.234 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR | clk:[F] | clk:[R] | 10.000 | 0.023 | 1.708 |
5 | 8.234 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR | clk:[F] | clk:[R] | 10.000 | 0.023 | 1.708 |
6 | 8.258 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR | clk:[F] | clk:[R] | 10.000 | 0.023 | 1.684 |
7 | 8.417 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR | clk:[F] | clk:[R] | 10.000 | 0.023 | 1.525 |
8 | 8.417 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR | clk:[F] | clk:[R] | 10.000 | 0.023 | 1.525 |
9 | 8.417 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_s0/CLEAR | clk:[F] | clk:[R] | 10.000 | 0.023 | 1.525 |
10 | 8.417 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET | clk:[F] | clk:[R] | 10.000 | 0.023 | 1.525 |
11 | 8.471 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR | clk:[F] | clk:[R] | 10.000 | 0.023 | 1.471 |
12 | 8.471 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_flag_s0/CLEAR | clk:[F] | clk:[R] | 10.000 | 0.023 | 1.471 |
13 | 8.477 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLEAR | clk:[F] | clk:[R] | 10.000 | 0.023 | 1.465 |
14 | 8.477 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR | clk:[F] | clk:[R] | 10.000 | 0.023 | 1.465 |
15 | 8.477 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR | clk:[F] | clk:[R] | 10.000 | 0.023 | 1.465 |
16 | 8.477 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR | clk:[F] | clk:[R] | 10.000 | 0.023 | 1.465 |
17 | 8.477 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR | clk:[F] | clk:[R] | 10.000 | 0.023 | 1.465 |
18 | 8.477 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR | clk:[F] | clk:[R] | 10.000 | 0.023 | 1.465 |
19 | 8.482 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR | clk:[F] | clk:[R] | 10.000 | 0.023 | 1.460 |
20 | 8.482 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR | clk:[F] | clk:[R] | 10.000 | 0.023 | 1.460 |
21 | 8.725 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET | clk:[F] | clk:[R] | 10.000 | 0.023 | 1.217 |
22 | 8.725 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR | clk:[F] | clk:[R] | 10.000 | 0.023 | 1.217 |
23 | 8.725 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR | clk:[F] | clk:[R] | 10.000 | 0.023 | 1.217 |
24 | 8.725 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR | clk:[F] | clk:[R] | 10.000 | 0.023 | 1.217 |
25 | 8.725 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR | clk:[F] | clk:[R] | 10.000 | 0.023 | 1.217 |
Removal Paths Table
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 10.471 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLEAR | clk:[F] | clk:[R] | -10.000 | 0.012 | 0.470 |
2 | 10.471 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR | clk:[F] | clk:[R] | -10.000 | 0.012 | 0.470 |
3 | 10.471 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLEAR | clk:[F] | clk:[R] | -10.000 | 0.012 | 0.470 |
4 | 10.471 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR | clk:[F] | clk:[R] | -10.000 | 0.012 | 0.470 |
5 | 10.471 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/start_reg_s0/CLEAR | clk:[F] | clk:[R] | -10.000 | 0.012 | 0.470 |
6 | 10.472 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLEAR | clk:[F] | clk:[R] | -10.000 | 0.012 | 0.471 |
7 | 10.472 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR | clk:[F] | clk:[R] | -10.000 | 0.012 | 0.471 |
8 | 10.478 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLEAR | clk:[F] | clk:[R] | -10.000 | 0.012 | 0.477 |
9 | 10.478 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR | clk:[F] | clk:[R] | -10.000 | 0.012 | 0.477 |
10 | 10.478 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR | clk:[F] | clk:[R] | -10.000 | 0.012 | 0.477 |
11 | 10.478 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR | clk:[F] | clk:[R] | -10.000 | 0.012 | 0.477 |
12 | 10.478 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR | clk:[F] | clk:[R] | -10.000 | 0.012 | 0.477 |
13 | 10.594 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR | clk:[F] | clk:[R] | -10.000 | 0.012 | 0.593 |
14 | 10.594 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR | clk:[F] | clk:[R] | -10.000 | 0.012 | 0.593 |
15 | 10.600 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLEAR | clk:[F] | clk:[R] | -10.000 | 0.012 | 0.599 |
16 | 10.603 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/triger_s0/CLEAR | clk:[F] | clk:[R] | -10.000 | 0.012 | 0.602 |
17 | 10.725 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLEAR | clk:[F] | clk:[R] | -10.000 | 0.012 | 0.724 |
18 | 10.725 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLEAR | clk:[F] | clk:[R] | -10.000 | 0.012 | 0.724 |
19 | 10.728 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLEAR | clk:[F] | clk:[R] | -10.000 | 0.012 | 0.727 |
20 | 10.778 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET | clk:[F] | clk:[R] | -10.000 | 0.012 | 0.776 |
21 | 10.778 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR | clk:[F] | clk:[R] | -10.000 | 0.012 | 0.776 |
22 | 10.778 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR | clk:[F] | clk:[R] | -10.000 | 0.012 | 0.776 |
23 | 10.778 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR | clk:[F] | clk:[R] | -10.000 | 0.012 | 0.776 |
24 | 10.778 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR | clk:[F] | clk:[R] | -10.000 | 0.012 | 0.776 |
25 | 10.778 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR | clk:[F] | clk:[R] | -10.000 | 0.012 | 0.776 |
Minimum Pulse Width Table:
Number | Slack | Actual Width | Required Width | Type | Clock | Objects |
---|---|---|---|---|---|---|
1 | 8.911 | 9.911 | 1.000 | Low Pulse Width | clk | i_data_9_s0 |
2 | 8.911 | 9.911 | 1.000 | Low Pulse Width | clk | i_data_7_s0 |
3 | 8.911 | 9.911 | 1.000 | Low Pulse Width | clk | i_data_3_s0 |
4 | 8.911 | 9.911 | 1.000 | Low Pulse Width | clk | mem_data_1_mem_data_1_0_1_s |
5 | 8.911 | 9.911 | 1.000 | Low Pulse Width | clk | FP_Div/FP_Div_inst/mant_a_wire_16_s0 |
6 | 8.911 | 9.911 | 1.000 | Low Pulse Width | clk | FP_Div/FP_Div_inst/mant_b_wire_8_s0 |
7 | 8.911 | 9.911 | 1.000 | Low Pulse Width | clk | FP_Div/FP_Div_inst/mant_bdelay[0]_8_s0 |
8 | 8.911 | 9.911 | 1.000 | Low Pulse Width | clk | FP_Div/FP_Div_inst/div0/integer_division_frac_inst/reg_divisor_20_s0 |
9 | 8.911 | 9.911 | 1.000 | Low Pulse Width | clk | FP_Div/FP_Div_inst/div0/integer_division_frac_inst/gen_non_restoring[2].non_restoring_division_latency_inst/reg_b_o_12_s0 |
10 | 8.911 | 9.911 | 1.000 | Low Pulse Width | clk | FP_Div/FP_Div_inst/div0/integer_division_frac_inst/gen_non_restoring[10].non_restoring_division_latency_inst/reg_sub_add_o_1_s0 |
Timing Report By Analysis Type:
Setup Analysis Report
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 4.425 |
Data Arrival Time | 56.431 |
Data Required Time | 60.856 |
From | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | tck_pad_i | ||||
50.000 | 0.000 | tCL | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/I |
50.682 | 0.683 | tINS | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/O |
50.682 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
51.365 | 0.683 | tINS | RR | 393 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
52.147 | 0.782 | tNET | RR | 1 | R26C74[0][B] | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0/CLK |
52.379 | 0.232 | tC2Q | RF | 2 | R26C74[0][B] | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0/Q |
53.356 | 0.977 | tNET | FF | 1 | R22C74[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n684_s10/I2 |
53.818 | 0.462 | tINS | FR | 1 | R22C74[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n684_s10/F |
53.991 | 0.172 | tNET | RR | 1 | R21C74[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n684_s7/I1 |
54.540 | 0.549 | tINS | RR | 2 | R21C74[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n684_s7/F |
54.715 | 0.176 | tNET | RR | 1 | R21C75[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n684_s5/I0 |
55.168 | 0.453 | tINS | RF | 10 | R21C75[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n684_s5/F |
55.861 | 0.693 | tNET | FF | 1 | R22C75[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n684_s2/I3 |
56.431 | 0.570 | tINS | FR | 1 | R22C75[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n684_s2/F |
56.431 | 0.000 | tNET | RR | 1 | R22C75[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
60.000 | 60.000 | active clock edge time | ||||
60.000 | 0.000 | clk | ||||
60.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
60.682 | 0.683 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
60.926 | 0.243 | tNET | RR | 1 | R22C75[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK |
60.891 | -0.035 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1 | |||
60.856 | -0.035 | tSu | 1 | R22C75[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1 |
Path Statistics:
Clock Skew | -1.221 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 1.365, 63.584%; route: 0.782, 36.416% |
Arrival Data Path Delay | cell: 2.034, 47.476%; route: 2.018, 47.109%; tC2Q: 0.232, 5.415% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path2
Path Summary:
Slack | 4.433 |
Data Arrival Time | 56.423 |
Data Required Time | 60.856 |
From | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | tck_pad_i | ||||
50.000 | 0.000 | tCL | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/I |
50.682 | 0.683 | tINS | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/O |
50.682 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
51.365 | 0.683 | tINS | RR | 393 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
52.147 | 0.782 | tNET | RR | 1 | R26C74[0][B] | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0/CLK |
52.379 | 0.232 | tC2Q | RF | 2 | R26C74[0][B] | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0/Q |
53.356 | 0.977 | tNET | FF | 1 | R22C74[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n684_s10/I2 |
53.818 | 0.462 | tINS | FR | 1 | R22C74[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n684_s10/F |
53.991 | 0.172 | tNET | RR | 1 | R21C74[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n684_s7/I1 |
54.540 | 0.549 | tINS | RR | 2 | R21C74[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n684_s7/F |
54.715 | 0.176 | tNET | RR | 1 | R21C75[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n684_s5/I0 |
55.168 | 0.453 | tINS | RF | 10 | R21C75[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n684_s5/F |
55.708 | 0.540 | tNET | FF | 1 | R22C71[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s4/I0 |
56.278 | 0.570 | tINS | FR | 1 | R22C71[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s4/F |
56.423 | 0.144 | tNET | RR | 1 | R22C71[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
60.000 | 60.000 | active clock edge time | ||||
60.000 | 0.000 | clk | ||||
60.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
60.682 | 0.683 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
60.926 | 0.243 | tNET | RR | 1 | R22C71[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK |
60.891 | -0.035 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1 | |||
60.856 | -0.035 | tSu | 1 | R22C71[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1 |
Path Statistics:
Clock Skew | -1.221 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 1.365, 63.584%; route: 0.782, 36.416% |
Arrival Data Path Delay | cell: 2.034, 47.570%; route: 2.010, 47.004%; tC2Q: 0.232, 5.426% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path3
Path Summary:
Slack | 4.621 |
Data Arrival Time | 56.235 |
Data Required Time | 60.856 |
From | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | tck_pad_i | ||||
50.000 | 0.000 | tCL | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/I |
50.682 | 0.683 | tINS | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/O |
50.682 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
51.365 | 0.683 | tINS | RR | 393 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
52.147 | 0.782 | tNET | RR | 1 | R26C74[0][B] | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0/CLK |
52.379 | 0.232 | tC2Q | RF | 2 | R26C74[0][B] | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0/Q |
53.356 | 0.977 | tNET | FF | 1 | R22C74[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n684_s10/I2 |
53.818 | 0.462 | tINS | FR | 1 | R22C74[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n684_s10/F |
53.991 | 0.172 | tNET | RR | 1 | R21C74[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n684_s7/I1 |
54.540 | 0.549 | tINS | RR | 2 | R21C74[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n684_s7/F |
54.715 | 0.176 | tNET | RR | 1 | R21C75[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n684_s5/I0 |
55.168 | 0.453 | tINS | RF | 10 | R21C75[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n684_s5/F |
55.686 | 0.518 | tNET | FF | 1 | R20C77[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n687_s1/I2 |
56.235 | 0.549 | tINS | FR | 1 | R20C77[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n687_s1/F |
56.235 | 0.000 | tNET | RR | 1 | R20C77[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
60.000 | 60.000 | active clock edge time | ||||
60.000 | 0.000 | clk | ||||
60.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
60.682 | 0.683 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
60.926 | 0.243 | tNET | RR | 1 | R20C77[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK |
60.891 | -0.035 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1 | |||
60.856 | -0.035 | tSu | 1 | R20C77[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1 |
Path Statistics:
Clock Skew | -1.221 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 1.365, 63.584%; route: 0.782, 36.416% |
Arrival Data Path Delay | cell: 2.013, 49.240%; route: 1.843, 45.085%; tC2Q: 0.232, 5.675% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path4
Path Summary:
Slack | 4.649 |
Data Arrival Time | 56.207 |
Data Required Time | 60.856 |
From | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | tck_pad_i | ||||
50.000 | 0.000 | tCL | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/I |
50.682 | 0.683 | tINS | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/O |
50.682 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
51.365 | 0.683 | tINS | RR | 393 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
52.147 | 0.782 | tNET | RR | 1 | R26C74[0][B] | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0/CLK |
52.379 | 0.232 | tC2Q | RF | 2 | R26C74[0][B] | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0/Q |
53.356 | 0.977 | tNET | FF | 1 | R22C74[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n684_s10/I2 |
53.818 | 0.462 | tINS | FR | 1 | R22C74[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n684_s10/F |
53.991 | 0.172 | tNET | RR | 1 | R21C74[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n684_s7/I1 |
54.540 | 0.549 | tINS | RR | 2 | R21C74[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n684_s7/F |
54.715 | 0.176 | tNET | RR | 1 | R21C75[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n684_s5/I0 |
55.168 | 0.453 | tINS | RF | 10 | R21C75[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n684_s5/F |
55.836 | 0.667 | tNET | FF | 1 | R20C77[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n691_s1/I3 |
56.207 | 0.371 | tINS | FF | 1 | R20C77[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n691_s1/F |
56.207 | 0.000 | tNET | FF | 1 | R20C77[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
60.000 | 60.000 | active clock edge time | ||||
60.000 | 0.000 | clk | ||||
60.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
60.682 | 0.683 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
60.926 | 0.243 | tNET | RR | 1 | R20C77[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK |
60.891 | -0.035 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1 | |||
60.856 | -0.035 | tSu | 1 | R20C77[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1 |
Path Statistics:
Clock Skew | -1.221 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 1.365, 63.584%; route: 0.782, 36.416% |
Arrival Data Path Delay | cell: 1.835, 45.197%; route: 1.993, 49.089%; tC2Q: 0.232, 5.714% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path5
Path Summary:
Slack | 4.682 |
Data Arrival Time | 56.173 |
Data Required Time | 60.856 |
From | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | tck_pad_i | ||||
50.000 | 0.000 | tCL | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/I |
50.682 | 0.683 | tINS | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/O |
50.682 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
51.365 | 0.683 | tINS | RR | 393 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
52.147 | 0.782 | tNET | RR | 1 | R26C74[0][B] | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0/CLK |
52.379 | 0.232 | tC2Q | RF | 2 | R26C74[0][B] | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0/Q |
53.356 | 0.977 | tNET | FF | 1 | R22C74[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n684_s10/I2 |
53.818 | 0.462 | tINS | FR | 1 | R22C74[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n684_s10/F |
53.991 | 0.172 | tNET | RR | 1 | R21C74[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n684_s7/I1 |
54.540 | 0.549 | tINS | RR | 2 | R21C74[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n684_s7/F |
54.715 | 0.176 | tNET | RR | 1 | R21C75[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n684_s5/I0 |
55.168 | 0.453 | tINS | RF | 10 | R21C75[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n684_s5/F |
55.603 | 0.435 | tNET | FF | 1 | R22C76[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n686_s1/I3 |
56.173 | 0.570 | tINS | FR | 1 | R22C76[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n686_s1/F |
56.173 | 0.000 | tNET | RR | 1 | R22C76[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
60.000 | 60.000 | active clock edge time | ||||
60.000 | 0.000 | clk | ||||
60.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
60.682 | 0.683 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
60.926 | 0.243 | tNET | RR | 1 | R22C76[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK |
60.891 | -0.035 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1 | |||
60.856 | -0.035 | tSu | 1 | R22C76[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1 |
Path Statistics:
Clock Skew | -1.221 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 1.365, 63.584%; route: 0.782, 36.416% |
Arrival Data Path Delay | cell: 2.034, 50.512%; route: 1.761, 43.726%; tC2Q: 0.232, 5.761% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path6
Path Summary:
Slack | 4.717 |
Data Arrival Time | 56.139 |
Data Required Time | 60.856 |
From | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | tck_pad_i | ||||
50.000 | 0.000 | tCL | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/I |
50.682 | 0.683 | tINS | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/O |
50.682 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
51.365 | 0.683 | tINS | RR | 393 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
52.147 | 0.782 | tNET | RR | 1 | R26C74[0][B] | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0/CLK |
52.379 | 0.232 | tC2Q | RF | 2 | R26C74[0][B] | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0/Q |
53.356 | 0.977 | tNET | FF | 1 | R22C74[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n684_s10/I2 |
53.818 | 0.462 | tINS | FR | 1 | R22C74[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n684_s10/F |
53.991 | 0.172 | tNET | RR | 1 | R21C74[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n684_s7/I1 |
54.540 | 0.549 | tINS | RR | 2 | R21C74[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n684_s7/F |
54.715 | 0.176 | tNET | RR | 1 | R21C75[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n684_s5/I0 |
55.168 | 0.453 | tINS | RF | 10 | R21C75[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n684_s5/F |
55.768 | 0.600 | tNET | FF | 1 | R22C76[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n685_s1/I3 |
56.139 | 0.371 | tINS | FF | 1 | R22C76[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n685_s1/F |
56.139 | 0.000 | tNET | FF | 1 | R22C76[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
60.000 | 60.000 | active clock edge time | ||||
60.000 | 0.000 | clk | ||||
60.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
60.682 | 0.683 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
60.926 | 0.243 | tNET | RR | 1 | R22C76[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK |
60.891 | -0.035 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1 | |||
60.856 | -0.035 | tSu | 1 | R22C76[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1 |
Path Statistics:
Clock Skew | -1.221 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 1.365, 63.584%; route: 0.782, 36.416% |
Arrival Data Path Delay | cell: 1.835, 45.963%; route: 1.925, 48.226%; tC2Q: 0.232, 5.811% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path7
Path Summary:
Slack | 4.898 |
Data Arrival Time | 55.958 |
Data Required Time | 60.856 |
From | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | tck_pad_i | ||||
50.000 | 0.000 | tCL | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/I |
50.682 | 0.683 | tINS | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/O |
50.682 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
51.365 | 0.683 | tINS | RR | 393 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
52.147 | 0.782 | tNET | RR | 1 | R26C74[0][B] | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0/CLK |
52.379 | 0.232 | tC2Q | RF | 2 | R26C74[0][B] | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0/Q |
53.356 | 0.977 | tNET | FF | 1 | R22C74[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n684_s10/I2 |
53.818 | 0.462 | tINS | FR | 1 | R22C74[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n684_s10/F |
53.991 | 0.172 | tNET | RR | 1 | R21C74[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n684_s7/I1 |
54.540 | 0.549 | tINS | RR | 2 | R21C74[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n684_s7/F |
54.715 | 0.176 | tNET | RR | 1 | R21C75[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n684_s5/I0 |
55.168 | 0.453 | tINS | RF | 10 | R21C75[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n684_s5/F |
55.587 | 0.419 | tNET | FF | 1 | R21C76[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n688_s1/I3 |
55.958 | 0.371 | tINS | FF | 1 | R21C76[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n688_s1/F |
55.958 | 0.000 | tNET | FF | 1 | R21C76[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
60.000 | 60.000 | active clock edge time | ||||
60.000 | 0.000 | clk | ||||
60.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
60.682 | 0.683 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
60.926 | 0.243 | tNET | RR | 1 | R21C76[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK |
60.891 | -0.035 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1 | |||
60.856 | -0.035 | tSu | 1 | R21C76[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1 |
Path Statistics:
Clock Skew | -1.221 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 1.365, 63.584%; route: 0.782, 36.416% |
Arrival Data Path Delay | cell: 1.835, 48.143%; route: 1.745, 45.770%; tC2Q: 0.232, 6.087% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path8
Path Summary:
Slack | 4.916 |
Data Arrival Time | 55.940 |
Data Required Time | 60.856 |
From | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | tck_pad_i | ||||
50.000 | 0.000 | tCL | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/I |
50.682 | 0.683 | tINS | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/O |
50.682 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
51.365 | 0.683 | tINS | RR | 393 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
52.147 | 0.782 | tNET | RR | 1 | R26C74[0][B] | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0/CLK |
52.379 | 0.232 | tC2Q | RF | 2 | R26C74[0][B] | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0/Q |
53.356 | 0.977 | tNET | FF | 1 | R22C74[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n684_s10/I2 |
53.818 | 0.462 | tINS | FR | 1 | R22C74[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n684_s10/F |
53.991 | 0.172 | tNET | RR | 1 | R21C74[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n684_s7/I1 |
54.540 | 0.549 | tINS | RR | 2 | R21C74[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n684_s7/F |
54.715 | 0.176 | tNET | RR | 1 | R21C75[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n684_s5/I0 |
55.168 | 0.453 | tINS | RF | 10 | R21C75[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n684_s5/F |
55.370 | 0.201 | tNET | FF | 1 | R21C76[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n689_s1/I2 |
55.940 | 0.570 | tINS | FR | 1 | R21C76[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n689_s1/F |
55.940 | 0.000 | tNET | RR | 1 | R21C76[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
60.000 | 60.000 | active clock edge time | ||||
60.000 | 0.000 | clk | ||||
60.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
60.682 | 0.683 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
60.926 | 0.243 | tNET | RR | 1 | R21C76[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK |
60.891 | -0.035 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1 | |||
60.856 | -0.035 | tSu | 1 | R21C76[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1 |
Path Statistics:
Clock Skew | -1.221 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 1.365, 63.584%; route: 0.782, 36.416% |
Arrival Data Path Delay | cell: 2.034, 53.624%; route: 1.527, 40.259%; tC2Q: 0.232, 6.116% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path9
Path Summary:
Slack | 5.112 |
Data Arrival Time | 55.744 |
Data Required Time | 60.856 |
From | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | tck_pad_i | ||||
50.000 | 0.000 | tCL | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/I |
50.682 | 0.683 | tINS | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/O |
50.682 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
51.365 | 0.683 | tINS | RR | 393 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
52.147 | 0.782 | tNET | RR | 1 | R26C74[0][B] | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0/CLK |
52.379 | 0.232 | tC2Q | RF | 2 | R26C74[0][B] | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0/Q |
53.356 | 0.977 | tNET | FF | 1 | R22C74[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n684_s10/I2 |
53.818 | 0.462 | tINS | FR | 1 | R22C74[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n684_s10/F |
53.991 | 0.172 | tNET | RR | 1 | R21C74[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n684_s7/I1 |
54.540 | 0.549 | tINS | RR | 2 | R21C74[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n684_s7/F |
54.715 | 0.176 | tNET | RR | 1 | R21C75[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n684_s5/I0 |
55.168 | 0.453 | tINS | RF | 10 | R21C75[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n684_s5/F |
55.195 | 0.026 | tNET | FF | 1 | R21C75[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n692_s1/I2 |
55.744 | 0.549 | tINS | FR | 1 | R21C75[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n692_s1/F |
55.744 | 0.000 | tNET | RR | 1 | R21C75[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
60.000 | 60.000 | active clock edge time | ||||
60.000 | 0.000 | clk | ||||
60.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
60.682 | 0.683 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
60.926 | 0.243 | tNET | RR | 1 | R21C75[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK |
60.891 | -0.035 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1 | |||
60.856 | -0.035 | tSu | 1 | R21C75[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1 |
Path Statistics:
Clock Skew | -1.221 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 1.365, 63.584%; route: 0.782, 36.416% |
Arrival Data Path Delay | cell: 2.013, 55.964%; route: 1.352, 37.586%; tC2Q: 0.232, 6.450% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path10
Path Summary:
Slack | 5.112 |
Data Arrival Time | 55.744 |
Data Required Time | 60.856 |
From | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | tck_pad_i | ||||
50.000 | 0.000 | tCL | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/I |
50.682 | 0.683 | tINS | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/O |
50.682 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
51.365 | 0.683 | tINS | RR | 393 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
52.147 | 0.782 | tNET | RR | 1 | R26C74[0][B] | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0/CLK |
52.379 | 0.232 | tC2Q | RF | 2 | R26C74[0][B] | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0/Q |
53.356 | 0.977 | tNET | FF | 1 | R22C74[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n684_s10/I2 |
53.818 | 0.462 | tINS | FR | 1 | R22C74[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n684_s10/F |
53.991 | 0.172 | tNET | RR | 1 | R21C74[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n684_s7/I1 |
54.540 | 0.549 | tINS | RR | 2 | R21C74[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n684_s7/F |
54.715 | 0.176 | tNET | RR | 1 | R21C75[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n684_s5/I0 |
55.168 | 0.453 | tINS | RF | 10 | R21C75[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n684_s5/F |
55.195 | 0.026 | tNET | FF | 1 | R21C75[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n690_s1/I2 |
55.744 | 0.549 | tINS | FR | 1 | R21C75[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n690_s1/F |
55.744 | 0.000 | tNET | RR | 1 | R21C75[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
60.000 | 60.000 | active clock edge time | ||||
60.000 | 0.000 | clk | ||||
60.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
60.682 | 0.683 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
60.926 | 0.243 | tNET | RR | 1 | R21C75[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK |
60.891 | -0.035 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1 | |||
60.856 | -0.035 | tSu | 1 | R21C75[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1 |
Path Statistics:
Clock Skew | -1.221 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 1.365, 63.584%; route: 0.782, 36.416% |
Arrival Data Path Delay | cell: 2.013, 55.964%; route: 1.352, 37.586%; tC2Q: 0.232, 6.450% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path11
Path Summary:
Slack | 5.142 |
Data Arrival Time | 55.714 |
Data Required Time | 60.856 |
From | gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_10_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | tck_pad_i | ||||
50.000 | 0.000 | tCL | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/I |
50.682 | 0.683 | tINS | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/O |
50.682 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
51.365 | 0.683 | tINS | RR | 393 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
52.147 | 0.782 | tNET | RR | 1 | R27C73[0][A] | gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_10_s0/CLK |
52.379 | 0.232 | tC2Q | RF | 2 | R27C73[0][A] | gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_10_s0/Q |
52.899 | 0.520 | tNET | FF | 1 | R21C73[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s8/I2 |
53.454 | 0.555 | tINS | FF | 1 | R21C73[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s8/F |
53.867 | 0.413 | tNET | FF | 1 | R20C74[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s4/I2 |
54.437 | 0.570 | tINS | FR | 3 | R20C74[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s4/F |
54.441 | 0.004 | tNET | RR | 1 | R20C74[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s3/I0 |
54.990 | 0.549 | tINS | RR | 1 | R20C74[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s3/F |
55.714 | 0.724 | tNET | RR | 1 | R20C74[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
60.000 | 60.000 | active clock edge time | ||||
60.000 | 0.000 | clk | ||||
60.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
60.682 | 0.683 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
60.926 | 0.243 | tNET | RR | 1 | R20C74[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK |
60.891 | -0.035 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1 | |||
60.856 | -0.035 | tSu | 1 | R20C74[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1 |
Path Statistics:
Clock Skew | -1.221 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 1.365, 63.584%; route: 0.782, 36.416% |
Arrival Data Path Delay | cell: 1.674, 46.932%; route: 1.661, 46.563%; tC2Q: 0.232, 6.504% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path12
Path Summary:
Slack | 5.678 |
Data Arrival Time | 55.177 |
Data Required Time | 60.856 |
From | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | tck_pad_i | ||||
50.000 | 0.000 | tCL | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/I |
50.682 | 0.683 | tINS | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/O |
50.682 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
51.365 | 0.683 | tINS | RR | 393 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
52.147 | 0.782 | tNET | RR | 1 | R26C74[0][B] | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0/CLK |
52.379 | 0.232 | tC2Q | RF | 2 | R26C74[0][B] | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0/Q |
53.356 | 0.977 | tNET | FF | 1 | R22C74[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n684_s10/I2 |
53.818 | 0.462 | tINS | FR | 1 | R22C74[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n684_s10/F |
53.991 | 0.172 | tNET | RR | 1 | R21C74[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n684_s7/I1 |
54.540 | 0.549 | tINS | RR | 2 | R21C74[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n684_s7/F |
54.715 | 0.176 | tNET | RR | 1 | R21C75[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n693_s2/I1 |
55.177 | 0.462 | tINS | RR | 1 | R21C75[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n693_s2/F |
55.177 | 0.000 | tNET | RR | 1 | R21C75[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
60.000 | 60.000 | active clock edge time | ||||
60.000 | 0.000 | clk | ||||
60.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
60.682 | 0.683 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
60.926 | 0.243 | tNET | RR | 1 | R21C75[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLK |
60.891 | -0.035 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1 | |||
60.856 | -0.035 | tSu | 1 | R21C75[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1 |
Path Statistics:
Clock Skew | -1.221 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 1.365, 63.584%; route: 0.782, 36.416% |
Arrival Data Path Delay | cell: 1.473, 48.604%; route: 1.326, 43.741%; tC2Q: 0.232, 7.655% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path13
Path Summary:
Slack | 5.699 |
Data Arrival Time | 55.157 |
Data Required Time | 60.856 |
From | gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_1_s0 |
To | gw_gao_inst_0/u_la0_top/trigger_seq_start_s1 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | tck_pad_i | ||||
50.000 | 0.000 | tCL | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/I |
50.682 | 0.683 | tINS | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/O |
50.682 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
51.365 | 0.683 | tINS | RR | 393 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
52.147 | 0.782 | tNET | RR | 1 | R28C72[1][B] | gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_1_s0/CLK |
52.379 | 0.232 | tC2Q | RF | 2 | R28C72[1][B] | gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_1_s0/Q |
52.794 | 0.415 | tNET | FF | 1 | R29C71[1][A] | gw_gao_inst_0/u_la0_top/n3837_s0/I1 |
53.364 | 0.570 | tINS | FR | 1 | R29C71[1][A] | gw_gao_inst_0/u_la0_top/n3837_s0/COUT |
53.364 | 0.000 | tNET | RR | 1 | R29C71[1][B] | gw_gao_inst_0/u_la0_top/n3838_s0/CIN |
53.399 | 0.035 | tINS | RF | 1 | R29C71[1][B] | gw_gao_inst_0/u_la0_top/n3838_s0/COUT |
53.399 | 0.000 | tNET | FF | 1 | R29C71[2][A] | gw_gao_inst_0/u_la0_top/n3839_s0/CIN |
53.434 | 0.035 | tINS | FF | 6 | R29C71[2][A] | gw_gao_inst_0/u_la0_top/n3839_s0/COUT |
54.088 | 0.654 | tNET | FF | 1 | R28C71[3][B] | gw_gao_inst_0/u_la0_top/n3880_s1/I0 |
54.459 | 0.371 | tINS | FF | 1 | R28C71[3][B] | gw_gao_inst_0/u_la0_top/n3880_s1/F |
54.463 | 0.004 | tNET | FF | 1 | R28C71[2][B] | gw_gao_inst_0/u_la0_top/trigger_seq_start_s3/I3 |
55.012 | 0.549 | tINS | FR | 1 | R28C71[2][B] | gw_gao_inst_0/u_la0_top/trigger_seq_start_s3/F |
55.157 | 0.144 | tNET | RR | 1 | R28C71[2][A] | gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
60.000 | 60.000 | active clock edge time | ||||
60.000 | 0.000 | clk | ||||
60.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
60.682 | 0.683 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
60.926 | 0.243 | tNET | RR | 1 | R28C71[2][A] | gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLK |
60.891 | -0.035 | tUnc | gw_gao_inst_0/u_la0_top/trigger_seq_start_s1 | |||
60.856 | -0.035 | tSu | 1 | R28C71[2][A] | gw_gao_inst_0/u_la0_top/trigger_seq_start_s1 |
Path Statistics:
Clock Skew | -1.221 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 1.365, 63.584%; route: 0.782, 36.416% |
Arrival Data Path Delay | cell: 1.560, 51.842%; route: 1.218, 40.450%; tC2Q: 0.232, 7.708% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path14
Path Summary:
Slack | 5.722 |
Data Arrival Time | 55.134 |
Data Required Time | 60.856 |
From | gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_10_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | tck_pad_i | ||||
50.000 | 0.000 | tCL | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/I |
50.682 | 0.683 | tINS | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/O |
50.682 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
51.365 | 0.683 | tINS | RR | 393 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
52.147 | 0.782 | tNET | RR | 1 | R27C73[0][A] | gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_10_s0/CLK |
52.379 | 0.232 | tC2Q | RF | 2 | R27C73[0][A] | gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_10_s0/Q |
52.899 | 0.520 | tNET | FF | 1 | R21C73[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s8/I2 |
53.454 | 0.555 | tINS | FF | 1 | R21C73[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s8/F |
53.867 | 0.413 | tNET | FF | 1 | R20C74[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s4/I2 |
54.437 | 0.570 | tINS | FR | 3 | R20C74[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s4/F |
54.441 | 0.004 | tNET | RR | 1 | R20C74[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s5/I1 |
54.990 | 0.549 | tINS | RR | 1 | R20C74[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s5/F |
55.134 | 0.144 | tNET | RR | 1 | R20C74[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
60.000 | 60.000 | active clock edge time | ||||
60.000 | 0.000 | clk | ||||
60.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
60.682 | 0.683 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
60.926 | 0.243 | tNET | RR | 1 | R20C74[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLK |
60.891 | -0.035 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1 | |||
60.856 | -0.035 | tSu | 1 | R20C74[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1 |
Path Statistics:
Clock Skew | -1.221 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 1.365, 63.584%; route: 0.782, 36.416% |
Arrival Data Path Delay | cell: 1.674, 56.033%; route: 1.082, 36.202%; tC2Q: 0.232, 7.766% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path15
Path Summary:
Slack | 5.866 |
Data Arrival Time | 54.990 |
Data Required Time | 60.856 |
From | gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_10_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | tck_pad_i | ||||
50.000 | 0.000 | tCL | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/I |
50.682 | 0.683 | tINS | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/O |
50.682 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
51.365 | 0.683 | tINS | RR | 393 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
52.147 | 0.782 | tNET | RR | 1 | R27C73[0][A] | gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_10_s0/CLK |
52.379 | 0.232 | tC2Q | RF | 2 | R27C73[0][A] | gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_10_s0/Q |
52.899 | 0.520 | tNET | FF | 1 | R21C73[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s8/I2 |
53.454 | 0.555 | tINS | FF | 1 | R21C73[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s8/F |
53.867 | 0.413 | tNET | FF | 1 | R20C74[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s4/I2 |
54.437 | 0.570 | tINS | FR | 3 | R20C74[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s4/F |
54.441 | 0.004 | tNET | RR | 1 | R20C74[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n584_s3/I1 |
54.990 | 0.549 | tINS | RR | 1 | R20C74[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n584_s3/F |
54.990 | 0.000 | tNET | RR | 1 | R20C74[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
60.000 | 60.000 | active clock edge time | ||||
60.000 | 0.000 | clk | ||||
60.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
60.682 | 0.683 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
60.926 | 0.243 | tNET | RR | 1 | R20C74[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLK |
60.891 | -0.035 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1 | |||
60.856 | -0.035 | tSu | 1 | R20C74[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1 |
Path Statistics:
Clock Skew | -1.221 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 1.365, 63.584%; route: 0.782, 36.416% |
Arrival Data Path Delay | cell: 1.674, 58.874%; route: 0.937, 32.966%; tC2Q: 0.232, 8.159% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path16
Path Summary:
Slack | 6.063 |
Data Arrival Time | 54.793 |
Data Required Time | 60.856 |
From | gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_1_s0 |
To | gw_gao_inst_0/u_la0_top/triger_s0 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | tck_pad_i | ||||
50.000 | 0.000 | tCL | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/I |
50.682 | 0.683 | tINS | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/O |
50.682 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
51.365 | 0.683 | tINS | RR | 393 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
52.147 | 0.782 | tNET | RR | 1 | R28C72[1][B] | gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_1_s0/CLK |
52.379 | 0.232 | tC2Q | RF | 2 | R28C72[1][B] | gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_1_s0/Q |
52.794 | 0.415 | tNET | FF | 1 | R29C71[1][A] | gw_gao_inst_0/u_la0_top/n3837_s0/I1 |
53.364 | 0.570 | tINS | FR | 1 | R29C71[1][A] | gw_gao_inst_0/u_la0_top/n3837_s0/COUT |
53.364 | 0.000 | tNET | RR | 1 | R29C71[1][B] | gw_gao_inst_0/u_la0_top/n3838_s0/CIN |
53.399 | 0.035 | tINS | RF | 1 | R29C71[1][B] | gw_gao_inst_0/u_la0_top/n3838_s0/COUT |
53.399 | 0.000 | tNET | FF | 1 | R29C71[2][A] | gw_gao_inst_0/u_la0_top/n3839_s0/CIN |
53.434 | 0.035 | tINS | FF | 6 | R29C71[2][A] | gw_gao_inst_0/u_la0_top/n3839_s0/COUT |
54.331 | 0.896 | tNET | FF | 1 | R28C70[0][A] | gw_gao_inst_0/u_la0_top/n3880_s2/I1 |
54.793 | 0.462 | tINS | FR | 1 | R28C70[0][A] | gw_gao_inst_0/u_la0_top/n3880_s2/F |
54.793 | 0.000 | tNET | RR | 1 | R28C70[0][A] | gw_gao_inst_0/u_la0_top/triger_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
60.000 | 60.000 | active clock edge time | ||||
60.000 | 0.000 | clk | ||||
60.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
60.682 | 0.683 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
60.926 | 0.243 | tNET | RR | 1 | R28C70[0][A] | gw_gao_inst_0/u_la0_top/triger_s0/CLK |
60.891 | -0.035 | tUnc | gw_gao_inst_0/u_la0_top/triger_s0 | |||
60.856 | -0.035 | tSu | 1 | R28C70[0][A] | gw_gao_inst_0/u_la0_top/triger_s0 |
Path Statistics:
Clock Skew | -1.221 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 1.365, 63.584%; route: 0.782, 36.416% |
Arrival Data Path Delay | cell: 1.102, 41.662%; route: 1.312, 49.570%; tC2Q: 0.232, 8.768% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path17
Path Summary:
Slack | 6.110 |
Data Arrival Time | 54.746 |
Data Required Time | 60.856 |
From | gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_1_s0 |
To | gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | tck_pad_i | ||||
50.000 | 0.000 | tCL | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/I |
50.682 | 0.683 | tINS | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/O |
50.682 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
51.365 | 0.683 | tINS | RR | 393 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
52.147 | 0.782 | tNET | RR | 1 | R28C72[1][B] | gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_1_s0/CLK |
52.379 | 0.232 | tC2Q | RF | 2 | R28C72[1][B] | gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_1_s0/Q |
52.794 | 0.415 | tNET | FF | 1 | R29C71[1][A] | gw_gao_inst_0/u_la0_top/n3837_s0/I1 |
53.364 | 0.570 | tINS | FR | 1 | R29C71[1][A] | gw_gao_inst_0/u_la0_top/n3837_s0/COUT |
53.364 | 0.000 | tNET | RR | 1 | R29C71[1][B] | gw_gao_inst_0/u_la0_top/n3838_s0/CIN |
53.399 | 0.035 | tINS | RF | 1 | R29C71[1][B] | gw_gao_inst_0/u_la0_top/n3838_s0/COUT |
53.399 | 0.000 | tNET | FF | 1 | R29C71[2][A] | gw_gao_inst_0/u_la0_top/n3839_s0/CIN |
53.434 | 0.035 | tINS | FF | 6 | R29C71[2][A] | gw_gao_inst_0/u_la0_top/n3839_s0/COUT |
54.176 | 0.742 | tNET | FF | 1 | R27C71[2][A] | gw_gao_inst_0/u_la0_top/n3858_s1/I3 |
54.746 | 0.570 | tINS | FR | 1 | R27C71[2][A] | gw_gao_inst_0/u_la0_top/n3858_s1/F |
54.746 | 0.000 | tNET | RR | 1 | R27C71[2][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
60.000 | 60.000 | active clock edge time | ||||
60.000 | 0.000 | clk | ||||
60.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
60.682 | 0.683 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
60.926 | 0.243 | tNET | RR | 1 | R27C71[2][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLK |
60.891 | -0.035 | tUnc | gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1 | |||
60.856 | -0.035 | tSu | 1 | R27C71[2][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1 |
Path Statistics:
Clock Skew | -1.221 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 1.365, 63.584%; route: 0.782, 36.416% |
Arrival Data Path Delay | cell: 1.210, 46.563%; route: 1.157, 44.512%; tC2Q: 0.232, 8.925% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path18
Path Summary:
Slack | 6.131 |
Data Arrival Time | 54.725 |
Data Required Time | 60.856 |
From | gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_1_s0 |
To | gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | tck_pad_i | ||||
50.000 | 0.000 | tCL | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/I |
50.682 | 0.683 | tINS | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/O |
50.682 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
51.365 | 0.683 | tINS | RR | 393 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
52.147 | 0.782 | tNET | RR | 1 | R28C72[1][B] | gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_1_s0/CLK |
52.379 | 0.232 | tC2Q | RF | 2 | R28C72[1][B] | gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_1_s0/Q |
52.794 | 0.415 | tNET | FF | 1 | R29C71[1][A] | gw_gao_inst_0/u_la0_top/n3837_s0/I1 |
53.364 | 0.570 | tINS | FR | 1 | R29C71[1][A] | gw_gao_inst_0/u_la0_top/n3837_s0/COUT |
53.364 | 0.000 | tNET | RR | 1 | R29C71[1][B] | gw_gao_inst_0/u_la0_top/n3838_s0/CIN |
53.399 | 0.035 | tINS | RF | 1 | R29C71[1][B] | gw_gao_inst_0/u_la0_top/n3838_s0/COUT |
53.399 | 0.000 | tNET | FF | 1 | R29C71[2][A] | gw_gao_inst_0/u_la0_top/n3839_s0/CIN |
53.434 | 0.035 | tINS | FF | 6 | R29C71[2][A] | gw_gao_inst_0/u_la0_top/n3839_s0/COUT |
54.176 | 0.742 | tNET | FF | 1 | R27C71[1][A] | gw_gao_inst_0/u_la0_top/n3860_s1/I3 |
54.725 | 0.549 | tINS | FR | 1 | R27C71[1][A] | gw_gao_inst_0/u_la0_top/n3860_s1/F |
54.725 | 0.000 | tNET | RR | 1 | R27C71[1][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
60.000 | 60.000 | active clock edge time | ||||
60.000 | 0.000 | clk | ||||
60.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
60.682 | 0.683 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
60.926 | 0.243 | tNET | RR | 1 | R27C71[1][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLK |
60.891 | -0.035 | tUnc | gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1 | |||
60.856 | -0.035 | tSu | 1 | R27C71[1][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1 |
Path Statistics:
Clock Skew | -1.221 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 1.365, 63.584%; route: 0.782, 36.416% |
Arrival Data Path Delay | cell: 1.189, 46.128%; route: 1.157, 44.874%; tC2Q: 0.232, 8.998% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path19
Path Summary:
Slack | 6.131 |
Data Arrival Time | 54.725 |
Data Required Time | 60.856 |
From | gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_1_s0 |
To | gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | tck_pad_i | ||||
50.000 | 0.000 | tCL | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/I |
50.682 | 0.683 | tINS | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/O |
50.682 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
51.365 | 0.683 | tINS | RR | 393 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
52.147 | 0.782 | tNET | RR | 1 | R28C72[1][B] | gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_1_s0/CLK |
52.379 | 0.232 | tC2Q | RF | 2 | R28C72[1][B] | gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_1_s0/Q |
52.794 | 0.415 | tNET | FF | 1 | R29C71[1][A] | gw_gao_inst_0/u_la0_top/n3837_s0/I1 |
53.364 | 0.570 | tINS | FR | 1 | R29C71[1][A] | gw_gao_inst_0/u_la0_top/n3837_s0/COUT |
53.364 | 0.000 | tNET | RR | 1 | R29C71[1][B] | gw_gao_inst_0/u_la0_top/n3838_s0/CIN |
53.399 | 0.035 | tINS | RF | 1 | R29C71[1][B] | gw_gao_inst_0/u_la0_top/n3838_s0/COUT |
53.399 | 0.000 | tNET | FF | 1 | R29C71[2][A] | gw_gao_inst_0/u_la0_top/n3839_s0/CIN |
53.434 | 0.035 | tINS | FF | 6 | R29C71[2][A] | gw_gao_inst_0/u_la0_top/n3839_s0/COUT |
54.176 | 0.742 | tNET | FF | 1 | R27C71[1][B] | gw_gao_inst_0/u_la0_top/n3859_s1/I3 |
54.725 | 0.549 | tINS | FR | 1 | R27C71[1][B] | gw_gao_inst_0/u_la0_top/n3859_s1/F |
54.725 | 0.000 | tNET | RR | 1 | R27C71[1][B] | gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
60.000 | 60.000 | active clock edge time | ||||
60.000 | 0.000 | clk | ||||
60.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
60.682 | 0.683 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
60.926 | 0.243 | tNET | RR | 1 | R27C71[1][B] | gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLK |
60.891 | -0.035 | tUnc | gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1 | |||
60.856 | -0.035 | tSu | 1 | R27C71[1][B] | gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1 |
Path Statistics:
Clock Skew | -1.221 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 1.365, 63.584%; route: 0.782, 36.416% |
Arrival Data Path Delay | cell: 1.189, 46.128%; route: 1.157, 44.874%; tC2Q: 0.232, 8.998% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path20
Path Summary:
Slack | 6.154 |
Data Arrival Time | 54.702 |
Data Required Time | 60.856 |
From | gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_1_s0 |
To | gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | tck_pad_i | ||||
50.000 | 0.000 | tCL | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/I |
50.682 | 0.683 | tINS | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/O |
50.682 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
51.365 | 0.683 | tINS | RR | 393 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
52.147 | 0.782 | tNET | RR | 1 | R28C72[1][B] | gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_1_s0/CLK |
52.379 | 0.232 | tC2Q | RF | 2 | R28C72[1][B] | gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_1_s0/Q |
52.794 | 0.415 | tNET | FF | 1 | R29C71[1][A] | gw_gao_inst_0/u_la0_top/n3837_s0/I1 |
53.364 | 0.570 | tINS | FR | 1 | R29C71[1][A] | gw_gao_inst_0/u_la0_top/n3837_s0/COUT |
53.364 | 0.000 | tNET | RR | 1 | R29C71[1][B] | gw_gao_inst_0/u_la0_top/n3838_s0/CIN |
53.399 | 0.035 | tINS | RF | 1 | R29C71[1][B] | gw_gao_inst_0/u_la0_top/n3838_s0/COUT |
53.399 | 0.000 | tNET | FF | 1 | R29C71[2][A] | gw_gao_inst_0/u_la0_top/n3839_s0/CIN |
53.434 | 0.035 | tINS | FF | 6 | R29C71[2][A] | gw_gao_inst_0/u_la0_top/n3839_s0/COUT |
54.331 | 0.896 | tNET | FF | 1 | R27C71[0][B] | gw_gao_inst_0/u_la0_top/n3861_s3/I2 |
54.702 | 0.371 | tINS | FF | 1 | R27C71[0][B] | gw_gao_inst_0/u_la0_top/n3861_s3/F |
54.702 | 0.000 | tNET | FF | 1 | R27C71[0][B] | gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
60.000 | 60.000 | active clock edge time | ||||
60.000 | 0.000 | clk | ||||
60.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
60.682 | 0.683 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
60.926 | 0.243 | tNET | RR | 1 | R27C71[0][B] | gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLK |
60.891 | -0.035 | tUnc | gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3 | |||
60.856 | -0.035 | tSu | 1 | R27C71[0][B] | gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3 |
Path Statistics:
Clock Skew | -1.221 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 1.365, 63.584%; route: 0.782, 36.416% |
Arrival Data Path Delay | cell: 1.011, 39.584%; route: 1.312, 51.336%; tC2Q: 0.232, 9.080% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path21
Path Summary:
Slack | 6.486 |
Data Arrival Time | 54.370 |
Data Required Time | 60.856 |
From | gw_gao_inst_0/u_la0_top/capture_windows_num_0_s0 |
To | gw_gao_inst_0/u_la0_top/start_reg_s0 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | tck_pad_i | ||||
50.000 | 0.000 | tCL | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/I |
50.682 | 0.683 | tINS | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/O |
50.682 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
51.365 | 0.683 | tINS | RR | 393 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
52.147 | 0.782 | tNET | RR | 1 | R28C70[1][A] | gw_gao_inst_0/u_la0_top/capture_windows_num_0_s0/CLK |
52.378 | 0.231 | tC2Q | RR | 4 | R28C70[1][A] | gw_gao_inst_0/u_la0_top/capture_windows_num_0_s0/Q |
53.075 | 0.697 | tNET | RR | 1 | R28C71[0][A] | gw_gao_inst_0/u_la0_top/n3810_s8/CIN |
53.110 | 0.035 | tINS | RF | 1 | R28C71[0][A] | gw_gao_inst_0/u_la0_top/n3810_s8/COUT |
53.110 | 0.000 | tNET | FF | 1 | R28C71[0][B] | gw_gao_inst_0/u_la0_top/n3810_s9/CIN |
53.145 | 0.035 | tINS | FF | 1 | R28C71[0][B] | gw_gao_inst_0/u_la0_top/n3810_s9/COUT |
53.145 | 0.000 | tNET | FF | 1 | R28C71[1][A] | gw_gao_inst_0/u_la0_top/n3810_s10/CIN |
53.180 | 0.035 | tINS | FF | 1 | R28C71[1][A] | gw_gao_inst_0/u_la0_top/n3810_s10/COUT |
53.821 | 0.640 | tNET | FF | 1 | R27C71[0][A] | gw_gao_inst_0/u_la0_top/start_reg1_s0/I3 |
54.370 | 0.549 | tINS | FR | 1 | R27C71[0][A] | gw_gao_inst_0/u_la0_top/start_reg1_s0/F |
54.370 | 0.000 | tNET | RR | 1 | R27C71[0][A] | gw_gao_inst_0/u_la0_top/start_reg_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
60.000 | 60.000 | active clock edge time | ||||
60.000 | 0.000 | clk | ||||
60.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
60.682 | 0.683 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
60.926 | 0.243 | tNET | RR | 1 | R27C71[0][A] | gw_gao_inst_0/u_la0_top/start_reg_s0/CLK |
60.891 | -0.035 | tUnc | gw_gao_inst_0/u_la0_top/start_reg_s0 | |||
60.856 | -0.035 | tSu | 1 | R27C71[0][A] | gw_gao_inst_0/u_la0_top/start_reg_s0 |
Path Statistics:
Clock Skew | -1.221 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 1.365, 63.584%; route: 0.782, 36.416% |
Arrival Data Path Delay | cell: 0.655, 29.448%; route: 1.337, 60.160%; tC2Q: 0.231, 10.392% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path22
Path Summary:
Slack | 7.052 |
Data Arrival Time | 53.804 |
Data Required Time | 60.856 |
From | gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_2_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | tck_pad_i | ||||
50.000 | 0.000 | tCL | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/I |
50.682 | 0.683 | tINS | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/O |
50.682 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
51.365 | 0.683 | tINS | RR | 393 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
52.147 | 0.782 | tNET | RR | 1 | R27C72[1][B] | gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_2_s0/CLK |
52.379 | 0.232 | tC2Q | RF | 3 | R27C72[1][B] | gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_2_s0/Q |
53.234 | 0.856 | tNET | FF | 1 | R20C75[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n607_s0/I0 |
53.804 | 0.570 | tINS | FR | 1 | R20C75[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n607_s0/F |
53.804 | 0.000 | tNET | RR | 1 | R20C75[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
60.000 | 60.000 | active clock edge time | ||||
60.000 | 0.000 | clk | ||||
60.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
60.682 | 0.683 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
60.926 | 0.243 | tNET | RR | 1 | R20C75[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLK |
60.891 | -0.035 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1 | |||
60.856 | -0.035 | tSu | 1 | R20C75[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1 |
Path Statistics:
Clock Skew | -1.221 |
Setup Relationship | 10.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.365, 63.584%; route: 0.782, 36.416% |
Arrival Data Path Delay | cell: 0.570, 34.388%; route: 0.856, 51.615%; tC2Q: 0.232, 13.997% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path23
Path Summary:
Slack | 7.109 |
Data Arrival Time | 53.747 |
Data Required Time | 60.856 |
From | gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_0_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | tck_pad_i | ||||
50.000 | 0.000 | tCL | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/I |
50.682 | 0.683 | tINS | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/O |
50.682 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
51.365 | 0.683 | tINS | RR | 393 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
52.147 | 0.782 | tNET | RR | 1 | R23C72[2][A] | gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_0_s0/CLK |
52.379 | 0.232 | tC2Q | RF | 3 | R23C72[2][A] | gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_0_s0/Q |
53.285 | 0.907 | tNET | FF | 1 | R20C75[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n609_s2/I0 |
53.747 | 0.462 | tINS | FR | 1 | R20C75[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n609_s2/F |
53.747 | 0.000 | tNET | RR | 1 | R20C75[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
60.000 | 60.000 | active clock edge time | ||||
60.000 | 0.000 | clk | ||||
60.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
60.682 | 0.683 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
60.926 | 0.243 | tNET | RR | 1 | R20C75[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLK |
60.891 | -0.035 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1 | |||
60.856 | -0.035 | tSu | 1 | R20C75[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1 |
Path Statistics:
Clock Skew | -1.221 |
Setup Relationship | 10.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.365, 63.584%; route: 0.782, 36.416% |
Arrival Data Path Delay | cell: 0.462, 28.866%; route: 0.907, 56.639%; tC2Q: 0.232, 14.495% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path24
Path Summary:
Slack | 7.226 |
Data Arrival Time | 53.630 |
Data Required Time | 60.856 |
From | gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_1_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | tck_pad_i | ||||
50.000 | 0.000 | tCL | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/I |
50.682 | 0.683 | tINS | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/O |
50.682 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
51.365 | 0.683 | tINS | RR | 393 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
52.147 | 0.782 | tNET | RR | 1 | R28C73[1][B] | gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_1_s0/CLK |
52.379 | 0.232 | tC2Q | RF | 3 | R28C73[1][B] | gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_1_s0/Q |
53.259 | 0.880 | tNET | FF | 1 | R20C76[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n608_s0/I0 |
53.630 | 0.371 | tINS | FF | 1 | R20C76[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n608_s0/F |
53.630 | 0.000 | tNET | FF | 1 | R20C76[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
60.000 | 60.000 | active clock edge time | ||||
60.000 | 0.000 | clk | ||||
60.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
60.682 | 0.683 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
60.926 | 0.243 | tNET | RR | 1 | R20C76[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLK |
60.891 | -0.035 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1 | |||
60.856 | -0.035 | tSu | 1 | R20C76[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1 |
Path Statistics:
Clock Skew | -1.221 |
Setup Relationship | 10.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.365, 63.584%; route: 0.782, 36.416% |
Arrival Data Path Delay | cell: 0.371, 25.010%; route: 0.880, 59.351%; tC2Q: 0.232, 15.639% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path25
Path Summary:
Slack | 7.237 |
Data Arrival Time | 53.619 |
Data Required Time | 60.856 |
From | gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_3_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | tck_pad_i | ||||
50.000 | 0.000 | tCL | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/I |
50.682 | 0.683 | tINS | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/O |
50.682 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
51.365 | 0.683 | tINS | RR | 393 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
52.147 | 0.782 | tNET | RR | 1 | R27C73[0][B] | gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_3_s0/CLK |
52.379 | 0.232 | tC2Q | RF | 3 | R27C73[0][B] | gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_3_s0/Q |
53.070 | 0.691 | tNET | FF | 1 | R20C75[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n606_s0/I0 |
53.619 | 0.549 | tINS | FR | 1 | R20C75[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n606_s0/F |
53.619 | 0.000 | tNET | RR | 1 | R20C75[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
60.000 | 60.000 | active clock edge time | ||||
60.000 | 0.000 | clk | ||||
60.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
60.682 | 0.683 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
60.926 | 0.243 | tNET | RR | 1 | R20C75[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/CLK |
60.891 | -0.035 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1 | |||
60.856 | -0.035 | tSu | 1 | R20C75[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1 |
Path Statistics:
Clock Skew | -1.221 |
Setup Relationship | 10.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.365, 63.584%; route: 0.782, 36.416% |
Arrival Data Path Delay | cell: 0.549, 37.293%; route: 0.691, 46.947%; tC2Q: 0.232, 15.760% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Hold Analysis Report
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 0.190 |
Data Arrival Time | 1.062 |
Data Required Time | 0.872 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R20C74[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK |
1.062 | 0.202 | tC2Q | RR | 14 | R20C74[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q |
1.062 | 0.000 | tNET | RR | 1 | BSRAM_R10[26] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/CEA |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | BSRAM_R10[26] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/CLKA |
0.872 | 0.012 | tHld | 1 | BSRAM_R10[26] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.202, 100.000% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path2
Path Summary:
Slack | 0.190 |
Data Arrival Time | 1.062 |
Data Required Time | 0.872 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R20C74[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK |
1.062 | 0.202 | tC2Q | RR | 14 | R20C74[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q |
1.062 | 0.000 | tNET | RR | 1 | BSRAM_R10[25] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/CEA |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | BSRAM_R10[25] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/CLKA |
0.872 | 0.012 | tHld | 1 | BSRAM_R10[25] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.202, 100.000% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path3
Path Summary:
Slack | 0.190 |
Data Arrival Time | 1.062 |
Data Required Time | 0.872 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R20C74[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK |
1.062 | 0.202 | tC2Q | RR | 14 | R20C74[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q |
1.062 | 0.000 | tNET | RR | 1 | BSRAM_R36[24] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CEA |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | BSRAM_R36[24] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CLKA |
0.872 | 0.012 | tHld | 1 | BSRAM_R36[24] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.202, 100.000% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path4
Path Summary:
Slack | 0.190 |
Data Arrival Time | 1.062 |
Data Required Time | 0.872 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R20C74[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK |
1.062 | 0.202 | tC2Q | RR | 14 | R20C74[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q |
1.062 | 0.000 | tNET | RR | 1 | BSRAM_R10[24] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CEA |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | BSRAM_R10[24] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA |
0.872 | 0.012 | tHld | 1 | BSRAM_R10[24] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.202, 100.000% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path5
Path Summary:
Slack | 0.190 |
Data Arrival Time | 1.062 |
Data Required Time | 0.872 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R20C74[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK |
1.062 | 0.202 | tC2Q | RR | 14 | R20C74[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q |
1.062 | 0.000 | tNET | RR | 1 | BSRAM_R36[23] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CEA |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | BSRAM_R36[23] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA |
0.872 | 0.012 | tHld | 1 | BSRAM_R36[23] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.202, 100.000% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path6
Path Summary:
Slack | 0.190 |
Data Arrival Time | 1.062 |
Data Required Time | 0.872 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R20C74[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK |
1.062 | 0.202 | tC2Q | RR | 14 | R20C74[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q |
1.062 | 0.000 | tNET | RR | 1 | BSRAM_R10[23] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CEA |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | BSRAM_R10[23] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA |
0.872 | 0.012 | tHld | 1 | BSRAM_R10[23] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.202, 100.000% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path7
Path Summary:
Slack | 0.190 |
Data Arrival Time | 1.062 |
Data Required Time | 0.872 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R20C74[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK |
1.062 | 0.202 | tC2Q | RR | 14 | R20C74[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q |
1.062 | 0.000 | tNET | RR | 1 | BSRAM_R10[22] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CEA |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | BSRAM_R10[22] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA |
0.872 | 0.012 | tHld | 1 | BSRAM_R10[22] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.202, 100.000% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path8
Path Summary:
Slack | 0.213 |
Data Arrival Time | 1.322 |
Data Required Time | 1.109 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_91_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R11C79[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_91_s0/CLK |
1.062 | 0.202 | tC2Q | RR | 1 | R11C79[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_91_s0/Q |
1.322 | 0.260 | tNET | RR | 1 | BSRAM_R10[25] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/DI[11] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | BSRAM_R10[25] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/CLKA |
1.109 | 0.249 | tHld | 1 | BSRAM_R10[25] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path9
Path Summary:
Slack | 0.213 |
Data Arrival Time | 1.322 |
Data Required Time | 1.109 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_90_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R11C79[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_90_s0/CLK |
1.062 | 0.202 | tC2Q | RR | 1 | R11C79[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_90_s0/Q |
1.322 | 0.260 | tNET | RR | 1 | BSRAM_R10[25] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/DI[10] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | BSRAM_R10[25] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/CLKA |
1.109 | 0.249 | tHld | 1 | BSRAM_R10[25] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path10
Path Summary:
Slack | 0.213 |
Data Arrival Time | 1.322 |
Data Required Time | 1.109 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_88_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R11C78[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_88_s0/CLK |
1.062 | 0.202 | tC2Q | RR | 1 | R11C78[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_88_s0/Q |
1.322 | 0.260 | tNET | RR | 1 | BSRAM_R10[25] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/DI[8] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | BSRAM_R10[25] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/CLKA |
1.109 | 0.249 | tHld | 1 | BSRAM_R10[25] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path11
Path Summary:
Slack | 0.213 |
Data Arrival Time | 1.322 |
Data Required Time | 1.109 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_57_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R11C76[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_57_s0/CLK |
1.062 | 0.202 | tC2Q | RR | 1 | R11C76[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_57_s0/Q |
1.322 | 0.260 | tNET | RR | 1 | BSRAM_R10[24] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[9] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | BSRAM_R10[24] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA |
1.109 | 0.249 | tHld | 1 | BSRAM_R10[24] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path12
Path Summary:
Slack | 0.213 |
Data Arrival Time | 1.322 |
Data Required Time | 1.109 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_15_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R12C71[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_15_s0/CLK |
1.062 | 0.202 | tC2Q | RR | 1 | R12C71[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_15_s0/Q |
1.322 | 0.260 | tNET | RR | 1 | BSRAM_R10[22] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[15] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | BSRAM_R10[22] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA |
1.109 | 0.249 | tHld | 1 | BSRAM_R10[22] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path13
Path Summary:
Slack | 0.213 |
Data Arrival Time | 1.322 |
Data Required Time | 1.109 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_3_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R12C71[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_3_s0/CLK |
1.062 | 0.202 | tC2Q | RR | 1 | R12C71[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_3_s0/Q |
1.322 | 0.260 | tNET | RR | 1 | BSRAM_R10[22] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[3] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | BSRAM_R10[22] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA |
1.109 | 0.249 | tHld | 1 | BSRAM_R10[22] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path14
Path Summary:
Slack | 0.225 |
Data Arrival Time | 1.334 |
Data Required Time | 1.109 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_95_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R11C73[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_95_s0/CLK |
1.062 | 0.202 | tC2Q | RR | 1 | R11C73[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_95_s0/Q |
1.334 | 0.272 | tNET | RR | 1 | BSRAM_R10[25] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/DI[15] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | BSRAM_R10[25] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/CLKA |
1.109 | 0.249 | tHld | 1 | BSRAM_R10[25] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.272, 57.427%; tC2Q: 0.202, 42.573% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path15
Path Summary:
Slack | 0.225 |
Data Arrival Time | 1.334 |
Data Required Time | 1.109 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_81_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R11C76[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_81_s0/CLK |
1.062 | 0.202 | tC2Q | RR | 1 | R11C76[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_81_s0/Q |
1.334 | 0.272 | tNET | RR | 1 | BSRAM_R10[25] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/DI[1] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | BSRAM_R10[25] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/CLKA |
1.109 | 0.249 | tHld | 1 | BSRAM_R10[25] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.272, 57.427%; tC2Q: 0.202, 42.573% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path16
Path Summary:
Slack | 0.225 |
Data Arrival Time | 1.334 |
Data Required Time | 1.109 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_28_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R16C75[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_28_s0/CLK |
1.062 | 0.202 | tC2Q | RR | 1 | R16C75[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_28_s0/Q |
1.334 | 0.272 | tNET | RR | 1 | BSRAM_R10[23] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[12] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | BSRAM_R10[23] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA |
1.109 | 0.249 | tHld | 1 | BSRAM_R10[23] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.272, 57.427%; tC2Q: 0.202, 42.573% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path17
Path Summary:
Slack | 0.225 |
Data Arrival Time | 1.334 |
Data Required Time | 1.109 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_2_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R12C63[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_2_s0/CLK |
1.062 | 0.202 | tC2Q | RR | 1 | R12C63[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_2_s0/Q |
1.334 | 0.272 | tNET | RR | 1 | BSRAM_R10[22] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[2] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | BSRAM_R10[22] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA |
1.109 | 0.249 | tHld | 1 | BSRAM_R10[22] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.272, 57.427%; tC2Q: 0.202, 42.573% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path18
Path Summary:
Slack | 0.335 |
Data Arrival Time | 1.444 |
Data Required Time | 1.109 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_89_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R11C78[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_89_s0/CLK |
1.062 | 0.202 | tC2Q | RR | 1 | R11C78[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_89_s0/Q |
1.444 | 0.382 | tNET | RR | 1 | BSRAM_R10[25] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/DI[9] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | BSRAM_R10[25] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/CLKA |
1.109 | 0.249 | tHld | 1 | BSRAM_R10[25] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.382, 65.434%; tC2Q: 0.202, 34.566% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path19
Path Summary:
Slack | 0.335 |
Data Arrival Time | 1.444 |
Data Required Time | 1.109 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_20_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R12C71[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_20_s0/CLK |
1.062 | 0.202 | tC2Q | RR | 1 | R12C71[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_20_s0/Q |
1.444 | 0.382 | tNET | RR | 1 | BSRAM_R10[23] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[4] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | BSRAM_R10[23] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA |
1.109 | 0.249 | tHld | 1 | BSRAM_R10[23] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.382, 65.434%; tC2Q: 0.202, 34.566% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path20
Path Summary:
Slack | 0.335 |
Data Arrival Time | 1.444 |
Data Required Time | 1.109 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_16_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R12C74[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_16_s0/CLK |
1.062 | 0.202 | tC2Q | RR | 1 | R12C74[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_16_s0/Q |
1.444 | 0.382 | tNET | RR | 1 | BSRAM_R10[23] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[0] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | BSRAM_R10[23] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA |
1.109 | 0.249 | tHld | 1 | BSRAM_R10[23] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.382, 65.434%; tC2Q: 0.202, 34.566% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path21
Path Summary:
Slack | 0.347 |
Data Arrival Time | 1.456 |
Data Required Time | 1.109 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_30_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R16C74[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_30_s0/CLK |
1.062 | 0.202 | tC2Q | RR | 1 | R16C74[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_30_s0/Q |
1.456 | 0.394 | tNET | RR | 1 | BSRAM_R10[23] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[14] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | BSRAM_R10[23] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA |
1.109 | 0.249 | tHld | 1 | BSRAM_R10[23] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.394, 66.134%; tC2Q: 0.202, 33.866% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path22
Path Summary:
Slack | 0.351 |
Data Arrival Time | 1.460 |
Data Required Time | 1.109 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_100_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R11C79[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_100_s0/CLK |
1.062 | 0.202 | tC2Q | RR | 1 | R11C79[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_100_s0/Q |
1.460 | 0.398 | tNET | RR | 1 | BSRAM_R10[26] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/DI[4] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | BSRAM_R10[26] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/CLKA |
1.109 | 0.249 | tHld | 1 | BSRAM_R10[26] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.398, 66.358%; tC2Q: 0.202, 33.642% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path23
Path Summary:
Slack | 0.351 |
Data Arrival Time | 1.460 |
Data Required Time | 1.109 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_93_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R11C73[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_93_s0/CLK |
1.062 | 0.202 | tC2Q | RR | 1 | R11C73[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_93_s0/Q |
1.460 | 0.398 | tNET | RR | 1 | BSRAM_R10[25] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/DI[13] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | BSRAM_R10[25] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/CLKA |
1.109 | 0.249 | tHld | 1 | BSRAM_R10[25] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.398, 66.358%; tC2Q: 0.202, 33.642% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path24
Path Summary:
Slack | 0.351 |
Data Arrival Time | 1.460 |
Data Required Time | 1.109 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_24_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R12C70[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_24_s0/CLK |
1.062 | 0.202 | tC2Q | RR | 1 | R12C70[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_24_s0/Q |
1.460 | 0.398 | tNET | RR | 1 | BSRAM_R10[23] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[8] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | BSRAM_R10[23] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA |
1.109 | 0.249 | tHld | 1 | BSRAM_R10[23] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.398, 66.358%; tC2Q: 0.202, 33.642% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path25
Path Summary:
Slack | 0.351 |
Data Arrival Time | 1.460 |
Data Required Time | 1.109 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_23_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R12C70[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_23_s0/CLK |
1.062 | 0.202 | tC2Q | RR | 1 | R12C70[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_23_s0/Q |
1.460 | 0.398 | tNET | RR | 1 | BSRAM_R10[23] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[7] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | BSRAM_R10[23] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA |
1.109 | 0.249 | tHld | 1 | BSRAM_R10[23] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.398, 66.358%; tC2Q: 0.202, 33.642% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Recovery Analysis Report
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 7.980 |
Data Arrival Time | 12.911 |
Data Required Time | 20.891 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | 3878 | IOR44[A] | clk_ibuf/O |
10.949 | 0.261 | tNET | FF | 1 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.181 | 0.232 | tC2Q | FF | 49 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
12.911 | 1.730 | tNET | FF | 1 | R20C74[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
20.000 | 20.000 | active clock edge time | ||||
20.000 | 0.000 | clk | ||||
20.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
20.683 | 0.683 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
20.926 | 0.243 | tNET | RR | 1 | R20C74[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLK |
20.891 | -0.035 | tSu | 1 | R20C74[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1 |
Path Statistics:
Clock Skew | -0.023 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 72.453%; route: 0.261, 27.547% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.730, 88.177%; tC2Q: 0.232, 11.823% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path2
Path Summary:
Slack | 7.980 |
Data Arrival Time | 12.911 |
Data Required Time | 20.891 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | 3878 | IOR44[A] | clk_ibuf/O |
10.949 | 0.261 | tNET | FF | 1 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.181 | 0.232 | tC2Q | FF | 49 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
12.911 | 1.730 | tNET | FF | 1 | R20C74[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
20.000 | 20.000 | active clock edge time | ||||
20.000 | 0.000 | clk | ||||
20.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
20.683 | 0.683 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
20.926 | 0.243 | tNET | RR | 1 | R20C74[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK |
20.891 | -0.035 | tSu | 1 | R20C74[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1 |
Path Statistics:
Clock Skew | -0.023 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 72.453%; route: 0.261, 27.547% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.730, 88.177%; tC2Q: 0.232, 11.823% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path3
Path Summary:
Slack | 8.092 |
Data Arrival Time | 12.799 |
Data Required Time | 20.891 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | 3878 | IOR44[A] | clk_ibuf/O |
10.949 | 0.261 | tNET | FF | 1 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.181 | 0.232 | tC2Q | FF | 49 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
12.799 | 1.618 | tNET | FF | 1 | R18C69[1][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
20.000 | 20.000 | active clock edge time | ||||
20.000 | 0.000 | clk | ||||
20.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
20.683 | 0.683 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
20.926 | 0.243 | tNET | RR | 1 | R18C69[1][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLK |
20.891 | -0.035 | tSu | 1 | R18C69[1][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0 |
Path Statistics:
Clock Skew | -0.023 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 72.453%; route: 0.261, 27.547% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.618, 87.460%; tC2Q: 0.232, 12.540% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path4
Path Summary:
Slack | 8.234 |
Data Arrival Time | 12.657 |
Data Required Time | 20.891 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | 3878 | IOR44[A] | clk_ibuf/O |
10.949 | 0.261 | tNET | FF | 1 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.181 | 0.232 | tC2Q | FF | 49 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
12.657 | 1.476 | tNET | FF | 1 | R22C76[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
20.000 | 20.000 | active clock edge time | ||||
20.000 | 0.000 | clk | ||||
20.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
20.683 | 0.683 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
20.926 | 0.243 | tNET | RR | 1 | R22C76[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK |
20.891 | -0.035 | tSu | 1 | R22C76[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1 |
Path Statistics:
Clock Skew | -0.023 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 72.453%; route: 0.261, 27.547% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.476, 86.418%; tC2Q: 0.232, 13.582% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path5
Path Summary:
Slack | 8.234 |
Data Arrival Time | 12.657 |
Data Required Time | 20.891 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | 3878 | IOR44[A] | clk_ibuf/O |
10.949 | 0.261 | tNET | FF | 1 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.181 | 0.232 | tC2Q | FF | 49 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
12.657 | 1.476 | tNET | FF | 1 | R22C76[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
20.000 | 20.000 | active clock edge time | ||||
20.000 | 0.000 | clk | ||||
20.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
20.683 | 0.683 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
20.926 | 0.243 | tNET | RR | 1 | R22C76[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK |
20.891 | -0.035 | tSu | 1 | R22C76[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1 |
Path Statistics:
Clock Skew | -0.023 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 72.453%; route: 0.261, 27.547% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.476, 86.418%; tC2Q: 0.232, 13.582% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path6
Path Summary:
Slack | 8.258 |
Data Arrival Time | 12.633 |
Data Required Time | 20.891 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | 3878 | IOR44[A] | clk_ibuf/O |
10.949 | 0.261 | tNET | FF | 1 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.181 | 0.232 | tC2Q | FF | 49 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
12.633 | 1.452 | tNET | FF | 1 | R22C71[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
20.000 | 20.000 | active clock edge time | ||||
20.000 | 0.000 | clk | ||||
20.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
20.683 | 0.683 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
20.926 | 0.243 | tNET | RR | 1 | R22C71[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK |
20.891 | -0.035 | tSu | 1 | R22C71[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1 |
Path Statistics:
Clock Skew | -0.023 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 72.453%; route: 0.261, 27.547% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.452, 86.224%; tC2Q: 0.232, 13.776% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path7
Path Summary:
Slack | 8.417 |
Data Arrival Time | 12.474 |
Data Required Time | 20.891 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | 3878 | IOR44[A] | clk_ibuf/O |
10.949 | 0.261 | tNET | FF | 1 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.181 | 0.232 | tC2Q | FF | 49 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
12.474 | 1.293 | tNET | FF | 1 | R18C74[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
20.000 | 20.000 | active clock edge time | ||||
20.000 | 0.000 | clk | ||||
20.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
20.683 | 0.683 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
20.926 | 0.243 | tNET | RR | 1 | R18C74[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLK |
20.891 | -0.035 | tSu | 1 | R18C74[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1 |
Path Statistics:
Clock Skew | -0.023 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 72.453%; route: 0.261, 27.547% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.293, 84.786%; tC2Q: 0.232, 15.214% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path8
Path Summary:
Slack | 8.417 |
Data Arrival Time | 12.474 |
Data Required Time | 20.891 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | 3878 | IOR44[A] | clk_ibuf/O |
10.949 | 0.261 | tNET | FF | 1 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.181 | 0.232 | tC2Q | FF | 49 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
12.474 | 1.293 | tNET | FF | 1 | R18C74[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
20.000 | 20.000 | active clock edge time | ||||
20.000 | 0.000 | clk | ||||
20.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
20.683 | 0.683 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
20.926 | 0.243 | tNET | RR | 1 | R18C74[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLK |
20.891 | -0.035 | tSu | 1 | R18C74[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1 |
Path Statistics:
Clock Skew | -0.023 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 72.453%; route: 0.261, 27.547% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.293, 84.786%; tC2Q: 0.232, 15.214% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path9
Path Summary:
Slack | 8.417 |
Data Arrival Time | 12.474 |
Data Required Time | 20.891 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_s0 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | 3878 | IOR44[A] | clk_ibuf/O |
10.949 | 0.261 | tNET | FF | 1 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.181 | 0.232 | tC2Q | FF | 49 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
12.474 | 1.293 | tNET | FF | 1 | R18C74[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
20.000 | 20.000 | active clock edge time | ||||
20.000 | 0.000 | clk | ||||
20.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
20.683 | 0.683 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
20.926 | 0.243 | tNET | RR | 1 | R18C74[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_s0/CLK |
20.891 | -0.035 | tSu | 1 | R18C74[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_s0 |
Path Statistics:
Clock Skew | -0.023 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 72.453%; route: 0.261, 27.547% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.293, 84.786%; tC2Q: 0.232, 15.214% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path10
Path Summary:
Slack | 8.417 |
Data Arrival Time | 12.474 |
Data Required Time | 20.891 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_end_dly_s0 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | 3878 | IOR44[A] | clk_ibuf/O |
10.949 | 0.261 | tNET | FF | 1 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.181 | 0.232 | tC2Q | FF | 49 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
12.474 | 1.293 | tNET | FF | 1 | R18C74[0][A] | gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
20.000 | 20.000 | active clock edge time | ||||
20.000 | 0.000 | clk | ||||
20.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
20.683 | 0.683 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
20.926 | 0.243 | tNET | RR | 1 | R18C74[0][A] | gw_gao_inst_0/u_la0_top/capture_end_dly_s0/CLK |
20.891 | -0.035 | tSu | 1 | R18C74[0][A] | gw_gao_inst_0/u_la0_top/capture_end_dly_s0 |
Path Statistics:
Clock Skew | -0.023 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 72.453%; route: 0.261, 27.547% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.293, 84.786%; tC2Q: 0.232, 15.214% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path11
Path Summary:
Slack | 8.471 |
Data Arrival Time | 12.420 |
Data Required Time | 20.891 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | 3878 | IOR44[A] | clk_ibuf/O |
10.949 | 0.261 | tNET | FF | 1 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.181 | 0.232 | tC2Q | FF | 49 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
12.420 | 1.239 | tNET | FF | 1 | R18C75[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
20.000 | 20.000 | active clock edge time | ||||
20.000 | 0.000 | clk | ||||
20.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
20.683 | 0.683 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
20.926 | 0.243 | tNET | RR | 1 | R18C75[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLK |
20.891 | -0.035 | tSu | 1 | R18C75[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1 |
Path Statistics:
Clock Skew | -0.023 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 72.453%; route: 0.261, 27.547% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.239, 84.230%; tC2Q: 0.232, 15.770% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path12
Path Summary:
Slack | 8.471 |
Data Arrival Time | 12.420 |
Data Required Time | 20.891 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_flag_s0 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | 3878 | IOR44[A] | clk_ibuf/O |
10.949 | 0.261 | tNET | FF | 1 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.181 | 0.232 | tC2Q | FF | 49 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
12.420 | 1.239 | tNET | FF | 1 | R18C75[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_flag_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
20.000 | 20.000 | active clock edge time | ||||
20.000 | 0.000 | clk | ||||
20.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
20.683 | 0.683 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
20.926 | 0.243 | tNET | RR | 1 | R18C75[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_flag_s0/CLK |
20.891 | -0.035 | tSu | 1 | R18C75[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_flag_s0 |
Path Statistics:
Clock Skew | -0.023 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 72.453%; route: 0.261, 27.547% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.239, 84.230%; tC2Q: 0.232, 15.770% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path13
Path Summary:
Slack | 8.477 |
Data Arrival Time | 12.414 |
Data Required Time | 20.891 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | 3878 | IOR44[A] | clk_ibuf/O |
10.949 | 0.261 | tNET | FF | 1 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.181 | 0.232 | tC2Q | FF | 49 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
12.414 | 1.233 | tNET | FF | 1 | R21C75[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
20.000 | 20.000 | active clock edge time | ||||
20.000 | 0.000 | clk | ||||
20.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
20.683 | 0.683 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
20.926 | 0.243 | tNET | RR | 1 | R21C75[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLK |
20.891 | -0.035 | tSu | 1 | R21C75[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1 |
Path Statistics:
Clock Skew | -0.023 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 72.453%; route: 0.261, 27.547% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.233, 84.168%; tC2Q: 0.232, 15.832% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path14
Path Summary:
Slack | 8.477 |
Data Arrival Time | 12.414 |
Data Required Time | 20.891 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | 3878 | IOR44[A] | clk_ibuf/O |
10.949 | 0.261 | tNET | FF | 1 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.181 | 0.232 | tC2Q | FF | 49 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
12.414 | 1.233 | tNET | FF | 1 | R21C75[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
20.000 | 20.000 | active clock edge time | ||||
20.000 | 0.000 | clk | ||||
20.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
20.683 | 0.683 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
20.926 | 0.243 | tNET | RR | 1 | R21C75[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK |
20.891 | -0.035 | tSu | 1 | R21C75[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1 |
Path Statistics:
Clock Skew | -0.023 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 72.453%; route: 0.261, 27.547% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.233, 84.168%; tC2Q: 0.232, 15.832% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path15
Path Summary:
Slack | 8.477 |
Data Arrival Time | 12.414 |
Data Required Time | 20.891 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | 3878 | IOR44[A] | clk_ibuf/O |
10.949 | 0.261 | tNET | FF | 1 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.181 | 0.232 | tC2Q | FF | 49 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
12.414 | 1.233 | tNET | FF | 1 | R20C77[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
20.000 | 20.000 | active clock edge time | ||||
20.000 | 0.000 | clk | ||||
20.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
20.683 | 0.683 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
20.926 | 0.243 | tNET | RR | 1 | R20C77[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK |
20.891 | -0.035 | tSu | 1 | R20C77[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1 |
Path Statistics:
Clock Skew | -0.023 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 72.453%; route: 0.261, 27.547% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.233, 84.168%; tC2Q: 0.232, 15.832% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path16
Path Summary:
Slack | 8.477 |
Data Arrival Time | 12.414 |
Data Required Time | 20.891 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | 3878 | IOR44[A] | clk_ibuf/O |
10.949 | 0.261 | tNET | FF | 1 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.181 | 0.232 | tC2Q | FF | 49 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
12.414 | 1.233 | tNET | FF | 1 | R21C75[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
20.000 | 20.000 | active clock edge time | ||||
20.000 | 0.000 | clk | ||||
20.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
20.683 | 0.683 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
20.926 | 0.243 | tNET | RR | 1 | R21C75[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK |
20.891 | -0.035 | tSu | 1 | R21C75[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1 |
Path Statistics:
Clock Skew | -0.023 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 72.453%; route: 0.261, 27.547% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.233, 84.168%; tC2Q: 0.232, 15.832% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path17
Path Summary:
Slack | 8.477 |
Data Arrival Time | 12.414 |
Data Required Time | 20.891 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | 3878 | IOR44[A] | clk_ibuf/O |
10.949 | 0.261 | tNET | FF | 1 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.181 | 0.232 | tC2Q | FF | 49 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
12.414 | 1.233 | tNET | FF | 1 | R20C77[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
20.000 | 20.000 | active clock edge time | ||||
20.000 | 0.000 | clk | ||||
20.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
20.683 | 0.683 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
20.926 | 0.243 | tNET | RR | 1 | R20C77[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK |
20.891 | -0.035 | tSu | 1 | R20C77[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1 |
Path Statistics:
Clock Skew | -0.023 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 72.453%; route: 0.261, 27.547% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.233, 84.168%; tC2Q: 0.232, 15.832% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path18
Path Summary:
Slack | 8.477 |
Data Arrival Time | 12.414 |
Data Required Time | 20.891 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | 3878 | IOR44[A] | clk_ibuf/O |
10.949 | 0.261 | tNET | FF | 1 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.181 | 0.232 | tC2Q | FF | 49 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
12.414 | 1.233 | tNET | FF | 1 | R22C75[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
20.000 | 20.000 | active clock edge time | ||||
20.000 | 0.000 | clk | ||||
20.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
20.683 | 0.683 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
20.926 | 0.243 | tNET | RR | 1 | R22C75[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK |
20.891 | -0.035 | tSu | 1 | R22C75[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1 |
Path Statistics:
Clock Skew | -0.023 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 72.453%; route: 0.261, 27.547% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.233, 84.168%; tC2Q: 0.232, 15.832% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path19
Path Summary:
Slack | 8.482 |
Data Arrival Time | 12.409 |
Data Required Time | 20.891 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | 3878 | IOR44[A] | clk_ibuf/O |
10.949 | 0.261 | tNET | FF | 1 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.181 | 0.232 | tC2Q | FF | 49 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
12.409 | 1.228 | tNET | FF | 1 | R21C76[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
20.000 | 20.000 | active clock edge time | ||||
20.000 | 0.000 | clk | ||||
20.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
20.683 | 0.683 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
20.926 | 0.243 | tNET | RR | 1 | R21C76[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK |
20.891 | -0.035 | tSu | 1 | R21C76[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1 |
Path Statistics:
Clock Skew | -0.023 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 72.453%; route: 0.261, 27.547% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.228, 84.106%; tC2Q: 0.232, 15.894% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path20
Path Summary:
Slack | 8.482 |
Data Arrival Time | 12.409 |
Data Required Time | 20.891 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | 3878 | IOR44[A] | clk_ibuf/O |
10.949 | 0.261 | tNET | FF | 1 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.181 | 0.232 | tC2Q | FF | 49 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
12.409 | 1.228 | tNET | FF | 1 | R21C76[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
20.000 | 20.000 | active clock edge time | ||||
20.000 | 0.000 | clk | ||||
20.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
20.683 | 0.683 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
20.926 | 0.243 | tNET | RR | 1 | R21C76[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK |
20.891 | -0.035 | tSu | 1 | R21C76[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1 |
Path Statistics:
Clock Skew | -0.023 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 72.453%; route: 0.261, 27.547% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.228, 84.106%; tC2Q: 0.232, 15.894% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path21
Path Summary:
Slack | 8.725 |
Data Arrival Time | 12.166 |
Data Required Time | 20.891 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | 3878 | IOR44[A] | clk_ibuf/O |
10.949 | 0.261 | tNET | FF | 1 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.181 | 0.232 | tC2Q | FF | 49 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
12.166 | 0.985 | tNET | FF | 1 | R20C75[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
20.000 | 20.000 | active clock edge time | ||||
20.000 | 0.000 | clk | ||||
20.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
20.683 | 0.683 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
20.926 | 0.243 | tNET | RR | 1 | R20C75[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/CLK |
20.891 | -0.035 | tSu | 1 | R20C75[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1 |
Path Statistics:
Clock Skew | -0.023 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 72.453%; route: 0.261, 27.547% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.985, 80.935%; tC2Q: 0.232, 19.065% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path22
Path Summary:
Slack | 8.725 |
Data Arrival Time | 12.166 |
Data Required Time | 20.891 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | 3878 | IOR44[A] | clk_ibuf/O |
10.949 | 0.261 | tNET | FF | 1 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.181 | 0.232 | tC2Q | FF | 49 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
12.166 | 0.985 | tNET | FF | 1 | R20C75[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
20.000 | 20.000 | active clock edge time | ||||
20.000 | 0.000 | clk | ||||
20.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
20.683 | 0.683 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
20.926 | 0.243 | tNET | RR | 1 | R20C75[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLK |
20.891 | -0.035 | tSu | 1 | R20C75[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1 |
Path Statistics:
Clock Skew | -0.023 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 72.453%; route: 0.261, 27.547% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.985, 80.935%; tC2Q: 0.232, 19.065% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path23
Path Summary:
Slack | 8.725 |
Data Arrival Time | 12.166 |
Data Required Time | 20.891 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | 3878 | IOR44[A] | clk_ibuf/O |
10.949 | 0.261 | tNET | FF | 1 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.181 | 0.232 | tC2Q | FF | 49 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
12.166 | 0.985 | tNET | FF | 1 | R20C76[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
20.000 | 20.000 | active clock edge time | ||||
20.000 | 0.000 | clk | ||||
20.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
20.683 | 0.683 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
20.926 | 0.243 | tNET | RR | 1 | R20C76[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLK |
20.891 | -0.035 | tSu | 1 | R20C76[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1 |
Path Statistics:
Clock Skew | -0.023 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 72.453%; route: 0.261, 27.547% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.985, 80.935%; tC2Q: 0.232, 19.065% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path24
Path Summary:
Slack | 8.725 |
Data Arrival Time | 12.166 |
Data Required Time | 20.891 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | 3878 | IOR44[A] | clk_ibuf/O |
10.949 | 0.261 | tNET | FF | 1 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.181 | 0.232 | tC2Q | FF | 49 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
12.166 | 0.985 | tNET | FF | 1 | R20C75[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
20.000 | 20.000 | active clock edge time | ||||
20.000 | 0.000 | clk | ||||
20.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
20.683 | 0.683 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
20.926 | 0.243 | tNET | RR | 1 | R20C75[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLK |
20.891 | -0.035 | tSu | 1 | R20C75[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1 |
Path Statistics:
Clock Skew | -0.023 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 72.453%; route: 0.261, 27.547% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.985, 80.935%; tC2Q: 0.232, 19.065% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path25
Path Summary:
Slack | 8.725 |
Data Arrival Time | 12.166 |
Data Required Time | 20.891 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | 3878 | IOR44[A] | clk_ibuf/O |
10.949 | 0.261 | tNET | FF | 1 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.181 | 0.232 | tC2Q | FF | 49 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
12.166 | 0.985 | tNET | FF | 1 | R20C76[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
20.000 | 20.000 | active clock edge time | ||||
20.000 | 0.000 | clk | ||||
20.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
20.683 | 0.683 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
20.926 | 0.243 | tNET | RR | 1 | R20C76[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLK |
20.891 | -0.035 | tSu | 1 | R20C76[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1 |
Path Statistics:
Clock Skew | -0.023 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 72.453%; route: 0.261, 27.547% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.985, 80.935%; tC2Q: 0.232, 19.065% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Removal Analysis Report
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 10.471 |
Data Arrival Time | 11.342 |
Data Required Time | 0.871 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | 3878 | IOR44[A] | clk_ibuf/O |
10.872 | 0.195 | tNET | FF | 1 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.074 | 0.202 | tC2Q | FR | 49 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
11.342 | 0.268 | tNET | RR | 1 | R27C71[0][B] | gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R27C71[0][B] | gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLK |
0.871 | 0.011 | tHld | 1 | R27C71[0][B] | gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3 |
Path Statistics:
Clock Skew | -0.012 |
Hold Relationship | -10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 77.694%; route: 0.195, 22.306% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.268, 56.986%; tC2Q: 0.202, 43.014% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path2
Path Summary:
Slack | 10.471 |
Data Arrival Time | 11.342 |
Data Required Time | 0.871 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | 3878 | IOR44[A] | clk_ibuf/O |
10.872 | 0.195 | tNET | FF | 1 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.074 | 0.202 | tC2Q | FR | 49 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
11.342 | 0.268 | tNET | RR | 1 | R27C71[1][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R27C71[1][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLK |
0.871 | 0.011 | tHld | 1 | R27C71[1][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1 |
Path Statistics:
Clock Skew | -0.012 |
Hold Relationship | -10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 77.694%; route: 0.195, 22.306% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.268, 56.986%; tC2Q: 0.202, 43.014% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path3
Path Summary:
Slack | 10.471 |
Data Arrival Time | 11.342 |
Data Required Time | 0.871 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | 3878 | IOR44[A] | clk_ibuf/O |
10.872 | 0.195 | tNET | FF | 1 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.074 | 0.202 | tC2Q | FR | 49 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
11.342 | 0.268 | tNET | RR | 1 | R27C71[1][B] | gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R27C71[1][B] | gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLK |
0.871 | 0.011 | tHld | 1 | R27C71[1][B] | gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1 |
Path Statistics:
Clock Skew | -0.012 |
Hold Relationship | -10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 77.694%; route: 0.195, 22.306% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.268, 56.986%; tC2Q: 0.202, 43.014% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path4
Path Summary:
Slack | 10.471 |
Data Arrival Time | 11.342 |
Data Required Time | 0.871 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | 3878 | IOR44[A] | clk_ibuf/O |
10.872 | 0.195 | tNET | FF | 1 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.074 | 0.202 | tC2Q | FR | 49 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
11.342 | 0.268 | tNET | RR | 1 | R27C71[2][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R27C71[2][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLK |
0.871 | 0.011 | tHld | 1 | R27C71[2][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1 |
Path Statistics:
Clock Skew | -0.012 |
Hold Relationship | -10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 77.694%; route: 0.195, 22.306% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.268, 56.986%; tC2Q: 0.202, 43.014% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path5
Path Summary:
Slack | 10.471 |
Data Arrival Time | 11.342 |
Data Required Time | 0.871 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/start_reg_s0 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | 3878 | IOR44[A] | clk_ibuf/O |
10.872 | 0.195 | tNET | FF | 1 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.074 | 0.202 | tC2Q | FR | 49 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
11.342 | 0.268 | tNET | RR | 1 | R27C71[0][A] | gw_gao_inst_0/u_la0_top/start_reg_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R27C71[0][A] | gw_gao_inst_0/u_la0_top/start_reg_s0/CLK |
0.871 | 0.011 | tHld | 1 | R27C71[0][A] | gw_gao_inst_0/u_la0_top/start_reg_s0 |
Path Statistics:
Clock Skew | -0.012 |
Hold Relationship | -10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 77.694%; route: 0.195, 22.306% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.268, 56.986%; tC2Q: 0.202, 43.014% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path6
Path Summary:
Slack | 10.472 |
Data Arrival Time | 11.343 |
Data Required Time | 0.871 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | 3878 | IOR44[A] | clk_ibuf/O |
10.872 | 0.195 | tNET | FF | 1 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.074 | 0.202 | tC2Q | FR | 49 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
11.343 | 0.269 | tNET | RR | 1 | R29C69[0][A] | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R29C69[0][A] | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLK |
0.871 | 0.011 | tHld | 1 | R29C69[0][A] | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0 |
Path Statistics:
Clock Skew | -0.012 |
Hold Relationship | -10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 77.694%; route: 0.195, 22.306% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.269, 57.092%; tC2Q: 0.202, 42.908% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path7
Path Summary:
Slack | 10.472 |
Data Arrival Time | 11.343 |
Data Required Time | 0.871 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | 3878 | IOR44[A] | clk_ibuf/O |
10.872 | 0.195 | tNET | FF | 1 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.074 | 0.202 | tC2Q | FR | 49 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
11.343 | 0.269 | tNET | RR | 1 | R29C69[0][B] | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R29C69[0][B] | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLK |
0.871 | 0.011 | tHld | 1 | R29C69[0][B] | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0 |
Path Statistics:
Clock Skew | -0.012 |
Hold Relationship | -10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 77.694%; route: 0.195, 22.306% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.269, 57.092%; tC2Q: 0.202, 42.908% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path8
Path Summary:
Slack | 10.478 |
Data Arrival Time | 11.349 |
Data Required Time | 0.871 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | 3878 | IOR44[A] | clk_ibuf/O |
10.872 | 0.195 | tNET | FF | 1 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.074 | 0.202 | tC2Q | FR | 49 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
11.349 | 0.275 | tNET | RR | 1 | R28C69[0][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R28C69[0][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLK |
0.871 | 0.011 | tHld | 1 | R28C69[0][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3 |
Path Statistics:
Clock Skew | -0.012 |
Hold Relationship | -10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 77.694%; route: 0.195, 22.306% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.275, 57.632%; tC2Q: 0.202, 42.368% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path9
Path Summary:
Slack | 10.478 |
Data Arrival Time | 11.349 |
Data Required Time | 0.871 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | 3878 | IOR44[A] | clk_ibuf/O |
10.872 | 0.195 | tNET | FF | 1 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.074 | 0.202 | tC2Q | FR | 49 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
11.349 | 0.275 | tNET | RR | 1 | R28C69[1][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R28C69[1][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLK |
0.871 | 0.011 | tHld | 1 | R28C69[1][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1 |
Path Statistics:
Clock Skew | -0.012 |
Hold Relationship | -10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 77.694%; route: 0.195, 22.306% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.275, 57.632%; tC2Q: 0.202, 42.368% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path10
Path Summary:
Slack | 10.478 |
Data Arrival Time | 11.349 |
Data Required Time | 0.871 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | 3878 | IOR44[A] | clk_ibuf/O |
10.872 | 0.195 | tNET | FF | 1 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.074 | 0.202 | tC2Q | FR | 49 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
11.349 | 0.275 | tNET | RR | 1 | R28C69[1][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R28C69[1][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLK |
0.871 | 0.011 | tHld | 1 | R28C69[1][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1 |
Path Statistics:
Clock Skew | -0.012 |
Hold Relationship | -10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 77.694%; route: 0.195, 22.306% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.275, 57.632%; tC2Q: 0.202, 42.368% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path11
Path Summary:
Slack | 10.478 |
Data Arrival Time | 11.349 |
Data Required Time | 0.871 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | 3878 | IOR44[A] | clk_ibuf/O |
10.872 | 0.195 | tNET | FF | 1 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.074 | 0.202 | tC2Q | FR | 49 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
11.349 | 0.275 | tNET | RR | 1 | R28C69[2][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R28C69[2][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLK |
0.871 | 0.011 | tHld | 1 | R28C69[2][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1 |
Path Statistics:
Clock Skew | -0.012 |
Hold Relationship | -10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 77.694%; route: 0.195, 22.306% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.275, 57.632%; tC2Q: 0.202, 42.368% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path12
Path Summary:
Slack | 10.478 |
Data Arrival Time | 11.349 |
Data Required Time | 0.871 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | 3878 | IOR44[A] | clk_ibuf/O |
10.872 | 0.195 | tNET | FF | 1 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.074 | 0.202 | tC2Q | FR | 49 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
11.349 | 0.275 | tNET | RR | 1 | R28C69[0][B] | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R28C69[0][B] | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLK |
0.871 | 0.011 | tHld | 1 | R28C69[0][B] | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0 |
Path Statistics:
Clock Skew | -0.012 |
Hold Relationship | -10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 77.694%; route: 0.195, 22.306% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.275, 57.632%; tC2Q: 0.202, 42.368% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path13
Path Summary:
Slack | 10.594 |
Data Arrival Time | 11.465 |
Data Required Time | 0.871 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | 3878 | IOR44[A] | clk_ibuf/O |
10.872 | 0.195 | tNET | FF | 1 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.074 | 0.202 | tC2Q | FR | 49 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
11.465 | 0.391 | tNET | RR | 1 | R30C69[1][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R30C69[1][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLK |
0.871 | 0.011 | tHld | 1 | R30C69[1][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0 |
Path Statistics:
Clock Skew | -0.012 |
Hold Relationship | -10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 77.694%; route: 0.195, 22.306% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.391, 65.923%; tC2Q: 0.202, 34.077% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path14
Path Summary:
Slack | 10.594 |
Data Arrival Time | 11.465 |
Data Required Time | 0.871 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | 3878 | IOR44[A] | clk_ibuf/O |
10.872 | 0.195 | tNET | FF | 1 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.074 | 0.202 | tC2Q | FR | 49 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
11.465 | 0.391 | tNET | RR | 1 | R30C69[1][B] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R30C69[1][B] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLK |
0.871 | 0.011 | tHld | 1 | R30C69[1][B] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0 |
Path Statistics:
Clock Skew | -0.012 |
Hold Relationship | -10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 77.694%; route: 0.195, 22.306% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.391, 65.923%; tC2Q: 0.202, 34.077% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path15
Path Summary:
Slack | 10.600 |
Data Arrival Time | 11.471 |
Data Required Time | 0.871 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/trigger_seq_start_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | 3878 | IOR44[A] | clk_ibuf/O |
10.872 | 0.195 | tNET | FF | 1 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.074 | 0.202 | tC2Q | FR | 49 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
11.471 | 0.397 | tNET | RR | 1 | R28C71[2][A] | gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R28C71[2][A] | gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLK |
0.871 | 0.011 | tHld | 1 | R28C71[2][A] | gw_gao_inst_0/u_la0_top/trigger_seq_start_s1 |
Path Statistics:
Clock Skew | -0.012 |
Hold Relationship | -10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 77.694%; route: 0.195, 22.306% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.397, 66.265%; tC2Q: 0.202, 33.735% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path16
Path Summary:
Slack | 10.603 |
Data Arrival Time | 11.474 |
Data Required Time | 0.871 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/triger_s0 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | 3878 | IOR44[A] | clk_ibuf/O |
10.872 | 0.195 | tNET | FF | 1 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.074 | 0.202 | tC2Q | FR | 49 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
11.474 | 0.400 | tNET | RR | 1 | R28C70[0][A] | gw_gao_inst_0/u_la0_top/triger_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R28C70[0][A] | gw_gao_inst_0/u_la0_top/triger_s0/CLK |
0.871 | 0.011 | tHld | 1 | R28C70[0][A] | gw_gao_inst_0/u_la0_top/triger_s0 |
Path Statistics:
Clock Skew | -0.012 |
Hold Relationship | -10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 77.694%; route: 0.195, 22.306% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.400, 66.433%; tC2Q: 0.202, 33.567% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path17
Path Summary:
Slack | 10.725 |
Data Arrival Time | 11.596 |
Data Required Time | 0.871 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | 3878 | IOR44[A] | clk_ibuf/O |
10.872 | 0.195 | tNET | FF | 1 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.074 | 0.202 | tC2Q | FR | 49 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
11.596 | 0.522 | tNET | RR | 1 | R29C68[2][A] | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R29C68[2][A] | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLK |
0.871 | 0.011 | tHld | 1 | R29C68[2][A] | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0 |
Path Statistics:
Clock Skew | -0.012 |
Hold Relationship | -10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 77.694%; route: 0.195, 22.306% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.522, 72.091%; tC2Q: 0.202, 27.909% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path18
Path Summary:
Slack | 10.725 |
Data Arrival Time | 11.596 |
Data Required Time | 0.871 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | 3878 | IOR44[A] | clk_ibuf/O |
10.872 | 0.195 | tNET | FF | 1 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.074 | 0.202 | tC2Q | FR | 49 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
11.596 | 0.522 | tNET | RR | 1 | R29C68[1][A] | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R29C68[1][A] | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLK |
0.871 | 0.011 | tHld | 1 | R29C68[1][A] | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0 |
Path Statistics:
Clock Skew | -0.012 |
Hold Relationship | -10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 77.694%; route: 0.195, 22.306% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.522, 72.091%; tC2Q: 0.202, 27.909% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path19
Path Summary:
Slack | 10.728 |
Data Arrival Time | 11.599 |
Data Required Time | 0.871 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | 3878 | IOR44[A] | clk_ibuf/O |
10.872 | 0.195 | tNET | FF | 1 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.074 | 0.202 | tC2Q | FR | 49 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
11.599 | 0.525 | tNET | RR | 1 | R27C70[2][A] | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R27C70[2][A] | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLK |
0.871 | 0.011 | tHld | 1 | R27C70[2][A] | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0 |
Path Statistics:
Clock Skew | -0.012 |
Hold Relationship | -10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 77.694%; route: 0.195, 22.306% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.525, 72.206%; tC2Q: 0.202, 27.794% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path20
Path Summary:
Slack | 10.778 |
Data Arrival Time | 11.648 |
Data Required Time | 0.871 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | 3878 | IOR44[A] | clk_ibuf/O |
10.872 | 0.195 | tNET | FF | 1 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.074 | 0.202 | tC2Q | FR | 49 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
11.648 | 0.574 | tNET | RR | 1 | R20C75[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R20C75[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/CLK |
0.871 | 0.011 | tHld | 1 | R20C75[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1 |
Path Statistics:
Clock Skew | -0.012 |
Hold Relationship | -10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 77.694%; route: 0.195, 22.306% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.574, 73.982%; tC2Q: 0.202, 26.018% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path21
Path Summary:
Slack | 10.778 |
Data Arrival Time | 11.648 |
Data Required Time | 0.871 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | 3878 | IOR44[A] | clk_ibuf/O |
10.872 | 0.195 | tNET | FF | 1 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.074 | 0.202 | tC2Q | FR | 49 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
11.648 | 0.574 | tNET | RR | 1 | R20C75[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R20C75[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLK |
0.871 | 0.011 | tHld | 1 | R20C75[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1 |
Path Statistics:
Clock Skew | -0.012 |
Hold Relationship | -10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 77.694%; route: 0.195, 22.306% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.574, 73.982%; tC2Q: 0.202, 26.018% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path22
Path Summary:
Slack | 10.778 |
Data Arrival Time | 11.648 |
Data Required Time | 0.871 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | 3878 | IOR44[A] | clk_ibuf/O |
10.872 | 0.195 | tNET | FF | 1 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.074 | 0.202 | tC2Q | FR | 49 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
11.648 | 0.574 | tNET | RR | 1 | R20C76[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R20C76[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLK |
0.871 | 0.011 | tHld | 1 | R20C76[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1 |
Path Statistics:
Clock Skew | -0.012 |
Hold Relationship | -10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 77.694%; route: 0.195, 22.306% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.574, 73.982%; tC2Q: 0.202, 26.018% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path23
Path Summary:
Slack | 10.778 |
Data Arrival Time | 11.648 |
Data Required Time | 0.871 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | 3878 | IOR44[A] | clk_ibuf/O |
10.872 | 0.195 | tNET | FF | 1 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.074 | 0.202 | tC2Q | FR | 49 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
11.648 | 0.574 | tNET | RR | 1 | R20C75[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R20C75[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLK |
0.871 | 0.011 | tHld | 1 | R20C75[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1 |
Path Statistics:
Clock Skew | -0.012 |
Hold Relationship | -10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 77.694%; route: 0.195, 22.306% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.574, 73.982%; tC2Q: 0.202, 26.018% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path24
Path Summary:
Slack | 10.778 |
Data Arrival Time | 11.648 |
Data Required Time | 0.871 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | 3878 | IOR44[A] | clk_ibuf/O |
10.872 | 0.195 | tNET | FF | 1 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.074 | 0.202 | tC2Q | FR | 49 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
11.648 | 0.574 | tNET | RR | 1 | R20C76[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R20C76[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLK |
0.871 | 0.011 | tHld | 1 | R20C76[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1 |
Path Statistics:
Clock Skew | -0.012 |
Hold Relationship | -10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 77.694%; route: 0.195, 22.306% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.574, 73.982%; tC2Q: 0.202, 26.018% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path25
Path Summary:
Slack | 10.778 |
Data Arrival Time | 11.648 |
Data Required Time | 0.871 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | 3878 | IOR44[A] | clk_ibuf/O |
10.872 | 0.195 | tNET | FF | 1 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.074 | 0.202 | tC2Q | FR | 49 | R27C70[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
11.648 | 0.574 | tNET | RR | 1 | R20C76[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 3878 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R20C76[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLK |
0.871 | 0.011 | tHld | 1 | R20C76[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1 |
Path Statistics:
Clock Skew | -0.012 |
Hold Relationship | -10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 77.694%; route: 0.195, 22.306% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.574, 73.982%; tC2Q: 0.202, 26.018% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Minimum Pulse Width Report:
Report Command:report_min_pulse_width -nworst 10 -detail
MPW1
MPW Summary:
Slack: | 8.911 |
Actual Width: | 9.911 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | clk |
Objects: | i_data_9_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk | ||
10.000 | 0.000 | tCL | FF | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | clk_ibuf/O |
10.949 | 0.261 | tNET | FF | i_data_9_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
20.000 | 0.000 | active clock edge time | ||
20.000 | 0.000 | clk | ||
20.000 | 0.000 | tCL | RR | clk_ibuf/I |
20.676 | 0.675 | tINS | RR | clk_ibuf/O |
20.860 | 0.184 | tNET | RR | i_data_9_s0/CLK |
MPW2
MPW Summary:
Slack: | 8.911 |
Actual Width: | 9.911 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | clk |
Objects: | i_data_7_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk | ||
10.000 | 0.000 | tCL | FF | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | clk_ibuf/O |
10.949 | 0.261 | tNET | FF | i_data_7_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
20.000 | 0.000 | active clock edge time | ||
20.000 | 0.000 | clk | ||
20.000 | 0.000 | tCL | RR | clk_ibuf/I |
20.676 | 0.675 | tINS | RR | clk_ibuf/O |
20.860 | 0.184 | tNET | RR | i_data_7_s0/CLK |
MPW3
MPW Summary:
Slack: | 8.911 |
Actual Width: | 9.911 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | clk |
Objects: | i_data_3_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk | ||
10.000 | 0.000 | tCL | FF | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | clk_ibuf/O |
10.949 | 0.261 | tNET | FF | i_data_3_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
20.000 | 0.000 | active clock edge time | ||
20.000 | 0.000 | clk | ||
20.000 | 0.000 | tCL | RR | clk_ibuf/I |
20.676 | 0.675 | tINS | RR | clk_ibuf/O |
20.860 | 0.184 | tNET | RR | i_data_3_s0/CLK |
MPW4
MPW Summary:
Slack: | 8.911 |
Actual Width: | 9.911 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | clk |
Objects: | mem_data_1_mem_data_1_0_1_s |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk | ||
10.000 | 0.000 | tCL | FF | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | clk_ibuf/O |
10.949 | 0.261 | tNET | FF | mem_data_1_mem_data_1_0_1_s/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
20.000 | 0.000 | active clock edge time | ||
20.000 | 0.000 | clk | ||
20.000 | 0.000 | tCL | RR | clk_ibuf/I |
20.676 | 0.675 | tINS | RR | clk_ibuf/O |
20.860 | 0.184 | tNET | RR | mem_data_1_mem_data_1_0_1_s/CLK |
MPW5
MPW Summary:
Slack: | 8.911 |
Actual Width: | 9.911 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | clk |
Objects: | FP_Div/FP_Div_inst/mant_a_wire_16_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk | ||
10.000 | 0.000 | tCL | FF | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | clk_ibuf/O |
10.949 | 0.261 | tNET | FF | FP_Div/FP_Div_inst/mant_a_wire_16_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
20.000 | 0.000 | active clock edge time | ||
20.000 | 0.000 | clk | ||
20.000 | 0.000 | tCL | RR | clk_ibuf/I |
20.676 | 0.675 | tINS | RR | clk_ibuf/O |
20.860 | 0.184 | tNET | RR | FP_Div/FP_Div_inst/mant_a_wire_16_s0/CLK |
MPW6
MPW Summary:
Slack: | 8.911 |
Actual Width: | 9.911 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | clk |
Objects: | FP_Div/FP_Div_inst/mant_b_wire_8_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk | ||
10.000 | 0.000 | tCL | FF | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | clk_ibuf/O |
10.949 | 0.261 | tNET | FF | FP_Div/FP_Div_inst/mant_b_wire_8_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
20.000 | 0.000 | active clock edge time | ||
20.000 | 0.000 | clk | ||
20.000 | 0.000 | tCL | RR | clk_ibuf/I |
20.676 | 0.675 | tINS | RR | clk_ibuf/O |
20.860 | 0.184 | tNET | RR | FP_Div/FP_Div_inst/mant_b_wire_8_s0/CLK |
MPW7
MPW Summary:
Slack: | 8.911 |
Actual Width: | 9.911 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | clk |
Objects: | FP_Div/FP_Div_inst/mant_bdelay[0]_8_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk | ||
10.000 | 0.000 | tCL | FF | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | clk_ibuf/O |
10.949 | 0.261 | tNET | FF | FP_Div/FP_Div_inst/mant_bdelay[0]_8_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
20.000 | 0.000 | active clock edge time | ||
20.000 | 0.000 | clk | ||
20.000 | 0.000 | tCL | RR | clk_ibuf/I |
20.676 | 0.675 | tINS | RR | clk_ibuf/O |
20.860 | 0.184 | tNET | RR | FP_Div/FP_Div_inst/mant_bdelay[0]_8_s0/CLK |
MPW8
MPW Summary:
Slack: | 8.911 |
Actual Width: | 9.911 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | clk |
Objects: | FP_Div/FP_Div_inst/div0/integer_division_frac_inst/reg_divisor_20_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk | ||
10.000 | 0.000 | tCL | FF | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | clk_ibuf/O |
10.949 | 0.261 | tNET | FF | FP_Div/FP_Div_inst/div0/integer_division_frac_inst/reg_divisor_20_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
20.000 | 0.000 | active clock edge time | ||
20.000 | 0.000 | clk | ||
20.000 | 0.000 | tCL | RR | clk_ibuf/I |
20.676 | 0.675 | tINS | RR | clk_ibuf/O |
20.860 | 0.184 | tNET | RR | FP_Div/FP_Div_inst/div0/integer_division_frac_inst/reg_divisor_20_s0/CLK |
MPW9
MPW Summary:
Slack: | 8.911 |
Actual Width: | 9.911 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | clk |
Objects: | FP_Div/FP_Div_inst/div0/integer_division_frac_inst/gen_non_restoring[2].non_restoring_division_latency_inst/reg_b_o_12_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk | ||
10.000 | 0.000 | tCL | FF | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | clk_ibuf/O |
10.949 | 0.261 | tNET | FF | FP_Div/FP_Div_inst/div0/integer_division_frac_inst/gen_non_restoring[2].non_restoring_division_latency_inst/reg_b_o_12_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
20.000 | 0.000 | active clock edge time | ||
20.000 | 0.000 | clk | ||
20.000 | 0.000 | tCL | RR | clk_ibuf/I |
20.676 | 0.675 | tINS | RR | clk_ibuf/O |
20.860 | 0.184 | tNET | RR | FP_Div/FP_Div_inst/div0/integer_division_frac_inst/gen_non_restoring[2].non_restoring_division_latency_inst/reg_b_o_12_s0/CLK |
MPW10
MPW Summary:
Slack: | 8.911 |
Actual Width: | 9.911 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | clk |
Objects: | FP_Div/FP_Div_inst/div0/integer_division_frac_inst/gen_non_restoring[10].non_restoring_division_latency_inst/reg_sub_add_o_1_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk | ||
10.000 | 0.000 | tCL | FF | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | clk_ibuf/O |
10.949 | 0.261 | tNET | FF | FP_Div/FP_Div_inst/div0/integer_division_frac_inst/gen_non_restoring[10].non_restoring_division_latency_inst/reg_sub_add_o_1_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
20.000 | 0.000 | active clock edge time | ||
20.000 | 0.000 | clk | ||
20.000 | 0.000 | tCL | RR | clk_ibuf/I |
20.676 | 0.675 | tINS | RR | clk_ibuf/O |
20.860 | 0.184 | tNET | RR | FP_Div/FP_Div_inst/div0/integer_division_frac_inst/gen_non_restoring[10].non_restoring_division_latency_inst/reg_sub_add_o_1_s0/CLK |
High Fanout Nets Report:
Report Command:report_high_fanout_nets -max_nets 10
FANOUT | NET NAME | WORST SLACK | MAX DELAY |
---|---|---|---|
3878 | clk_d | 7.409 | 0.261 |
393 | control0[0] | 4.425 | 0.912 |
131 | n20_3 | 42.452 | 2.849 |
109 | data_out_shift_reg_107_9 | 42.452 | 2.274 |
109 | n1049_5 | 43.215 | 2.356 |
95 | n1049_4 | 43.215 | 1.089 |
70 | exponent_normalize[1] | 7.409 | 1.040 |
49 | rst_ao | 7.980 | 1.730 |
42 | n15238_3 | 15.118 | 2.908 |
37 | n15962_3 | 16.548 | 0.787 |
Route Congestions Report:
Report Command:report_route_congestion -max_grids 10
GRID LOC | ROUTE CONGESTIONS |
---|---|
R9C66 | 88.89% |
R29C34 | 88.89% |
R11C66 | 87.50% |
R11C67 | 87.50% |
R9C65 | 87.50% |
R17C42 | 87.50% |
R27C42 | 87.50% |
R26C44 | 87.50% |
R11C62 | 86.11% |
R11C65 | 86.11% |
Timing Exceptions Report:
Setup Analysis Report
Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Hold Analysis Report
Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Recovery Analysis Report
Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Removal Analysis Report
Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Timing Constraints Report:
SDC Command Type | State | Detail Command |
---|---|---|
TC_CLOCK | Actived | create_clock -name clk -period 20 -waveform {0 10} [get_ports {clk}] |
TC_CLOCK | Actived | create_clock -name tck_pad_i -period 50 -waveform {0 25} [get_ports {tck_pad_i}] |
TC_FALSE_PATH | Actived | set_false_path -from [get_clocks {clk}] -to [get_clocks {tck_pad_i}] |