Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | C:\Gowin\Gowin_V1.9.9Beta-4\IDE\ipcore\FPDIV\data\FP_Div.v C:\Gowin\Gowin_V1.9.9Beta-4\IDE\ipcore\FPDIV\data\FP_Div_wrap.v |
GowinSynthesis Constraints File | --- |
Version | V1.9.9 Beta-4 |
Part Number | GW2A-LV55PG484C8/I7 |
Device | GW2A-55 |
Created Time | Tue Sep 05 17:50:39 2023 |
Legal Announcement | Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | FP_Div_Top |
Synthesis Process | Running parser: CPU time = 0h 0m 0.328s, Elapsed time = 0h 0m 0.574s, Peak memory usage = 63.805MB Running netlist conversion: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.074s, Peak memory usage = 63.805MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.263s, Peak memory usage = 63.805MB Optimizing Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.072s, Peak memory usage = 63.805MB Optimizing Phase 2: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.181s, Peak memory usage = 63.805MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.038s, Peak memory usage = 63.805MB Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.035s, Peak memory usage = 63.805MB Inferring Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.025s, Peak memory usage = 63.805MB Inferring Phase 3: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.06s, Peak memory usage = 63.805MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.105s, Peak memory usage = 63.805MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.024s, Peak memory usage = 63.805MB Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.017s, Peak memory usage = 63.805MB Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 4s, Peak memory usage = 74.352MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.126s, Peak memory usage = 74.352MB Generate output files: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.186s, Peak memory usage = 74.352MB |
Total Time and Memory Usage | CPU time = 0h 0m 3s, Elapsed time = 0h 0m 5s, Peak memory usage = 74.352MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 104 |
I/O Buf | 104 |
    IBUF | 67 |
    OBUF | 37 |
Register | 3588 |
    DFF | 1 |
    DFFE | 5 |
    DFFC | 3381 |
    DFFCE | 201 |
LUT | 496 |
    LUT2 | 123 |
    LUT3 | 98 |
    LUT4 | 275 |
ALU | 1394 |
    ALU | 1394 |
INV | 109 |
    INV | 109 |
BSRAM | 2 |
    SDPB | 2 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 1999(605 LUT, 1394 ALU) / 54720 | 4% |
Register | 3588 / 41997 | 9% |
  --Register as Latch | 0 / 41997 | 0% |
  --Register as FF | 3588 / 41997 | 9% |
BSRAM | 2 / 140 | 2% |
Timing
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|
clk | Base | 10.000 | 100.0 | 0.000 | 5.000 | clk_ibuf/I |
Max Frequency Summary:
No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | clk | 100.0(MHz) | 99.6(MHz) | 14 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | -0.041 |
Data Arrival Time | 10.868 |
Data Required Time | 10.828 |
From | FP_Div_inst/div0/integer_division_frac_inst/remainder_6_s0 |
To | FP_Div_inst/overflow_reg_s0 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 3592 | clk_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | FP_Div_inst/div0/integer_division_frac_inst/remainder_6_s0/CLK |
1.095 | 0.232 | tC2Q | RF | 7 | FP_Div_inst/div0/integer_division_frac_inst/remainder_6_s0/Q |
1.332 | 0.237 | tNET | FF | 1 | FP_Div_inst/exponent_normalize_9_s12/I1 |
1.887 | 0.555 | tINS | FF | 9 | FP_Div_inst/exponent_normalize_9_s12/F |
2.124 | 0.237 | tNET | FF | 1 | FP_Div_inst/exponent_normalize_2_s8/I1 |
2.679 | 0.555 | tINS | FF | 1 | FP_Div_inst/exponent_normalize_2_s8/F |
2.916 | 0.237 | tNET | FF | 1 | FP_Div_inst/exponent_normalize_2_s6/I1 |
3.471 | 0.555 | tINS | FF | 1 | FP_Div_inst/exponent_normalize_2_s6/F |
3.708 | 0.237 | tNET | FF | 1 | FP_Div_inst/exponent_normalize_2_s4/I0 |
4.225 | 0.517 | tINS | FF | 1 | FP_Div_inst/exponent_normalize_2_s4/F |
4.462 | 0.237 | tNET | FF | 1 | FP_Div_inst/exponent_normalize_2_s3/I0 |
4.979 | 0.517 | tINS | FF | 12 | FP_Div_inst/exponent_normalize_2_s3/F |
5.216 | 0.237 | tNET | FF | 1 | FP_Div_inst/exponent_normalize_0_s8/I0 |
5.733 | 0.517 | tINS | FF | 2 | FP_Div_inst/exponent_normalize_0_s8/F |
5.970 | 0.237 | tNET | FF | 1 | FP_Div_inst/exponent_normalize_0_s7/I3 |
6.341 | 0.371 | tINS | FF | 4 | FP_Div_inst/exponent_normalize_0_s7/F |
6.578 | 0.237 | tNET | FF | 1 | FP_Div_inst/exponent_normalize_0_s9/I0 |
7.095 | 0.517 | tINS | FF | 2 | FP_Div_inst/exponent_normalize_0_s9/F |
7.332 | 0.237 | tNET | FF | 2 | FP_Div_inst/n15567_s/I1 |
7.902 | 0.570 | tINS | FR | 1 | FP_Div_inst/n15567_s/COUT |
7.902 | 0.000 | tNET | RR | 2 | FP_Div_inst/n15566_s/CIN |
7.937 | 0.035 | tINS | RF | 1 | FP_Div_inst/n15566_s/COUT |
7.937 | 0.000 | tNET | FF | 2 | FP_Div_inst/n15565_s/CIN |
7.972 | 0.035 | tINS | FF | 1 | FP_Div_inst/n15565_s/COUT |
7.972 | 0.000 | tNET | FF | 2 | FP_Div_inst/n15564_s/CIN |
8.007 | 0.035 | tINS | FF | 1 | FP_Div_inst/n15564_s/COUT |
8.007 | 0.000 | tNET | FF | 2 | FP_Div_inst/n15563_s/CIN |
8.477 | 0.470 | tINS | FF | 1 | FP_Div_inst/n15563_s/SUM |
8.714 | 0.237 | tNET | FF | 1 | FP_Div_inst/n15570_s4/I1 |
9.269 | 0.555 | tINS | FF | 1 | FP_Div_inst/n15570_s4/F |
9.506 | 0.237 | tNET | FF | 1 | FP_Div_inst/n15570_s2/I3 |
9.877 | 0.371 | tINS | FF | 1 | FP_Div_inst/n15570_s2/F |
10.114 | 0.237 | tNET | FF | 1 | FP_Div_inst/n15570_s1/I0 |
10.631 | 0.517 | tINS | FF | 1 | FP_Div_inst/n15570_s1/F |
10.868 | 0.237 | tNET | FF | 1 | FP_Div_inst/overflow_reg_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk | |||
10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 3592 | clk_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | FP_Div_inst/overflow_reg_s0/CLK |
10.828 | -0.035 | tSu | 1 | FP_Div_inst/overflow_reg_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 14 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 6.693, 66.888%; route: 3.081, 30.793%; tC2Q: 0.232, 2.319% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 2
Path Summary:Slack | 1.216 |
Data Arrival Time | 9.612 |
Data Required Time | 10.828 |
From | FP_Div_inst/div0/integer_division_frac_inst/remainder_6_s0 |
To | FP_Div_inst/underflow_reg_s0 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 3592 | clk_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | FP_Div_inst/div0/integer_division_frac_inst/remainder_6_s0/CLK |
1.095 | 0.232 | tC2Q | RF | 7 | FP_Div_inst/div0/integer_division_frac_inst/remainder_6_s0/Q |
1.332 | 0.237 | tNET | FF | 1 | FP_Div_inst/exponent_normalize_9_s12/I1 |
1.887 | 0.555 | tINS | FF | 9 | FP_Div_inst/exponent_normalize_9_s12/F |
2.124 | 0.237 | tNET | FF | 1 | FP_Div_inst/exponent_normalize_2_s8/I1 |
2.679 | 0.555 | tINS | FF | 1 | FP_Div_inst/exponent_normalize_2_s8/F |
2.916 | 0.237 | tNET | FF | 1 | FP_Div_inst/exponent_normalize_2_s6/I1 |
3.471 | 0.555 | tINS | FF | 1 | FP_Div_inst/exponent_normalize_2_s6/F |
3.708 | 0.237 | tNET | FF | 1 | FP_Div_inst/exponent_normalize_2_s4/I0 |
4.225 | 0.517 | tINS | FF | 1 | FP_Div_inst/exponent_normalize_2_s4/F |
4.462 | 0.237 | tNET | FF | 1 | FP_Div_inst/exponent_normalize_2_s3/I0 |
4.979 | 0.517 | tINS | FF | 12 | FP_Div_inst/exponent_normalize_2_s3/F |
5.216 | 0.237 | tNET | FF | 1 | FP_Div_inst/exponent_normalize_0_s8/I0 |
5.733 | 0.517 | tINS | FF | 2 | FP_Div_inst/exponent_normalize_0_s8/F |
5.970 | 0.237 | tNET | FF | 1 | FP_Div_inst/exponent_normalize_0_s7/I3 |
6.341 | 0.371 | tINS | FF | 4 | FP_Div_inst/exponent_normalize_0_s7/F |
6.578 | 0.237 | tNET | FF | 1 | FP_Div_inst/exponent_normalize_0_s9/I0 |
7.095 | 0.517 | tINS | FF | 2 | FP_Div_inst/exponent_normalize_0_s9/F |
7.332 | 0.237 | tNET | FF | 1 | FP_Div_inst/n15613_s/I1 |
7.902 | 0.570 | tINS | FR | 1 | FP_Div_inst/n15613_s/COUT |
7.902 | 0.000 | tNET | RR | 1 | FP_Div_inst/n15612_s/CIN |
7.937 | 0.035 | tINS | RF | 1 | FP_Div_inst/n15612_s/COUT |
7.937 | 0.000 | tNET | FF | 1 | FP_Div_inst/n15611_s/CIN |
7.972 | 0.035 | tINS | FF | 1 | FP_Div_inst/n15611_s/COUT |
7.972 | 0.000 | tNET | FF | 1 | FP_Div_inst/n15610_s/CIN |
8.007 | 0.035 | tINS | FF | 1 | FP_Div_inst/n15610_s/COUT |
8.007 | 0.000 | tNET | FF | 1 | FP_Div_inst/n15609_s/CIN |
8.042 | 0.035 | tINS | FF | 1 | FP_Div_inst/n15609_s/COUT |
8.042 | 0.000 | tNET | FF | 1 | FP_Div_inst/n15608_s/CIN |
8.078 | 0.035 | tINS | FF | 1 | FP_Div_inst/n15608_s/COUT |
8.078 | 0.000 | tNET | FF | 1 | FP_Div_inst/n15607_s/CIN |
8.113 | 0.035 | tINS | FF | 1 | FP_Div_inst/n15607_s/COUT |
8.113 | 0.000 | tNET | FF | 2 | FP_Div_inst/n15606_s/CIN |
8.583 | 0.470 | tINS | FF | 1 | FP_Div_inst/n15606_s/SUM |
8.820 | 0.237 | tNET | FF | 1 | FP_Div_inst/n15616_s1/I1 |
9.375 | 0.555 | tINS | FF | 1 | FP_Div_inst/n15616_s1/F |
9.612 | 0.237 | tNET | FF | 1 | FP_Div_inst/underflow_reg_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk | |||
10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 3592 | clk_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | FP_Div_inst/underflow_reg_s0/CLK |
10.828 | -0.035 | tSu | 1 | FP_Div_inst/underflow_reg_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 13 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 5.910, 67.551%; route: 2.607, 29.797%; tC2Q: 0.232, 2.652% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 3
Path Summary:Slack | 1.614 |
Data Arrival Time | 9.214 |
Data Required Time | 10.828 |
From | FP_Div_inst/div0/integer_division_frac_inst/remainder_6_s0 |
To | FP_Div_inst/mant_prod_r_7_s0 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 3592 | clk_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | FP_Div_inst/div0/integer_division_frac_inst/remainder_6_s0/CLK |
1.095 | 0.232 | tC2Q | RF | 7 | FP_Div_inst/div0/integer_division_frac_inst/remainder_6_s0/Q |
1.332 | 0.237 | tNET | FF | 1 | FP_Div_inst/exponent_normalize_9_s12/I1 |
1.887 | 0.555 | tINS | FF | 9 | FP_Div_inst/exponent_normalize_9_s12/F |
2.124 | 0.237 | tNET | FF | 1 | FP_Div_inst/exponent_normalize_1_s17/I1 |
2.679 | 0.555 | tINS | FF | 3 | FP_Div_inst/exponent_normalize_1_s17/F |
2.916 | 0.237 | tNET | FF | 1 | FP_Div_inst/exponent_normalize_1_s9/I1 |
3.471 | 0.555 | tINS | FF | 3 | FP_Div_inst/exponent_normalize_1_s9/F |
3.708 | 0.237 | tNET | FF | 1 | FP_Div_inst/exponent_normalize_1_s4/I1 |
4.263 | 0.555 | tINS | FF | 1 | FP_Div_inst/exponent_normalize_1_s4/F |
4.500 | 0.237 | tNET | FF | 1 | FP_Div_inst/exponent_normalize_1_s2/I1 |
5.055 | 0.555 | tINS | FF | 70 | FP_Div_inst/exponent_normalize_1_s2/F |
5.292 | 0.237 | tNET | FF | 1 | FP_Div_inst/n15825_s23/I0 |
5.809 | 0.517 | tINS | FF | 1 | FP_Div_inst/n15825_s23/F |
6.046 | 0.237 | tNET | FF | 1 | FP_Div_inst/n15825_s18/I1 |
6.601 | 0.555 | tINS | FF | 1 | FP_Div_inst/n15825_s18/F |
6.838 | 0.237 | tNET | FF | 1 | FP_Div_inst/n15825_s13/I1 |
7.392 | 0.555 | tINS | FF | 5 | FP_Div_inst/n15825_s13/F |
7.629 | 0.237 | tNET | FF | 1 | FP_Div_inst/n15837_s3/I1 |
8.184 | 0.555 | tINS | FF | 1 | FP_Div_inst/n15837_s3/F |
8.422 | 0.237 | tNET | FF | 1 | FP_Div_inst/n15837_s1/I1 |
8.977 | 0.555 | tINS | FF | 1 | FP_Div_inst/n15837_s1/F |
9.214 | 0.237 | tNET | FF | 1 | FP_Div_inst/mant_prod_r_7_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk | |||
10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 3592 | clk_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | FP_Div_inst/mant_prod_r_7_s0/CLK |
10.828 | -0.035 | tSu | 1 | FP_Div_inst/mant_prod_r_7_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 11 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 5.512, 66.004%; route: 2.607, 31.218%; tC2Q: 0.232, 2.778% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 4
Path Summary:Slack | 1.652 |
Data Arrival Time | 9.176 |
Data Required Time | 10.828 |
From | FP_Div_inst/div0/integer_division_frac_inst/remainder_6_s0 |
To | FP_Div_inst/mant_prod_r_11_s0 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 3592 | clk_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | FP_Div_inst/div0/integer_division_frac_inst/remainder_6_s0/CLK |
1.095 | 0.232 | tC2Q | RF | 7 | FP_Div_inst/div0/integer_division_frac_inst/remainder_6_s0/Q |
1.332 | 0.237 | tNET | FF | 1 | FP_Div_inst/exponent_normalize_9_s12/I1 |
1.887 | 0.555 | tINS | FF | 9 | FP_Div_inst/exponent_normalize_9_s12/F |
2.124 | 0.237 | tNET | FF | 1 | FP_Div_inst/exponent_normalize_1_s17/I1 |
2.679 | 0.555 | tINS | FF | 3 | FP_Div_inst/exponent_normalize_1_s17/F |
2.916 | 0.237 | tNET | FF | 1 | FP_Div_inst/exponent_normalize_1_s9/I1 |
3.471 | 0.555 | tINS | FF | 3 | FP_Div_inst/exponent_normalize_1_s9/F |
3.708 | 0.237 | tNET | FF | 1 | FP_Div_inst/exponent_normalize_1_s4/I1 |
4.263 | 0.555 | tINS | FF | 1 | FP_Div_inst/exponent_normalize_1_s4/F |
4.500 | 0.237 | tNET | FF | 1 | FP_Div_inst/exponent_normalize_1_s2/I1 |
5.055 | 0.555 | tINS | FF | 70 | FP_Div_inst/exponent_normalize_1_s2/F |
5.292 | 0.237 | tNET | FF | 1 | FP_Div_inst/n15825_s23/I0 |
5.809 | 0.517 | tINS | FF | 1 | FP_Div_inst/n15825_s23/F |
6.046 | 0.237 | tNET | FF | 1 | FP_Div_inst/n15825_s18/I1 |
6.601 | 0.555 | tINS | FF | 1 | FP_Div_inst/n15825_s18/F |
6.838 | 0.237 | tNET | FF | 1 | FP_Div_inst/n15825_s13/I1 |
7.392 | 0.555 | tINS | FF | 5 | FP_Div_inst/n15825_s13/F |
7.629 | 0.237 | tNET | FF | 1 | FP_Div_inst/n15833_s2/I1 |
8.184 | 0.555 | tINS | FF | 1 | FP_Div_inst/n15833_s2/F |
8.422 | 0.237 | tNET | FF | 1 | FP_Div_inst/n15833_s1/I0 |
8.939 | 0.517 | tINS | FF | 1 | FP_Div_inst/n15833_s1/F |
9.176 | 0.237 | tNET | FF | 1 | FP_Div_inst/mant_prod_r_11_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk | |||
10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 3592 | clk_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | FP_Div_inst/mant_prod_r_11_s0/CLK |
10.828 | -0.035 | tSu | 1 | FP_Div_inst/mant_prod_r_11_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 11 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 5.474, 65.848%; route: 2.607, 31.361%; tC2Q: 0.232, 2.791% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 5
Path Summary:Slack | 1.652 |
Data Arrival Time | 9.176 |
Data Required Time | 10.828 |
From | FP_Div_inst/div0/integer_division_frac_inst/remainder_6_s0 |
To | FP_Div_inst/mant_prod_r_15_s0 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 3592 | clk_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | FP_Div_inst/div0/integer_division_frac_inst/remainder_6_s0/CLK |
1.095 | 0.232 | tC2Q | RF | 7 | FP_Div_inst/div0/integer_division_frac_inst/remainder_6_s0/Q |
1.332 | 0.237 | tNET | FF | 1 | FP_Div_inst/exponent_normalize_9_s12/I1 |
1.887 | 0.555 | tINS | FF | 9 | FP_Div_inst/exponent_normalize_9_s12/F |
2.124 | 0.237 | tNET | FF | 1 | FP_Div_inst/exponent_normalize_1_s17/I1 |
2.679 | 0.555 | tINS | FF | 3 | FP_Div_inst/exponent_normalize_1_s17/F |
2.916 | 0.237 | tNET | FF | 1 | FP_Div_inst/exponent_normalize_1_s9/I1 |
3.471 | 0.555 | tINS | FF | 3 | FP_Div_inst/exponent_normalize_1_s9/F |
3.708 | 0.237 | tNET | FF | 1 | FP_Div_inst/exponent_normalize_1_s4/I1 |
4.263 | 0.555 | tINS | FF | 1 | FP_Div_inst/exponent_normalize_1_s4/F |
4.500 | 0.237 | tNET | FF | 1 | FP_Div_inst/exponent_normalize_1_s2/I1 |
5.055 | 0.555 | tINS | FF | 70 | FP_Div_inst/exponent_normalize_1_s2/F |
5.292 | 0.237 | tNET | FF | 1 | FP_Div_inst/n15825_s23/I0 |
5.809 | 0.517 | tINS | FF | 1 | FP_Div_inst/n15825_s23/F |
6.046 | 0.237 | tNET | FF | 1 | FP_Div_inst/n15825_s18/I1 |
6.601 | 0.555 | tINS | FF | 1 | FP_Div_inst/n15825_s18/F |
6.838 | 0.237 | tNET | FF | 1 | FP_Div_inst/n15825_s13/I1 |
7.392 | 0.555 | tINS | FF | 5 | FP_Div_inst/n15825_s13/F |
7.629 | 0.237 | tNET | FF | 1 | FP_Div_inst/n15829_s2/I1 |
8.184 | 0.555 | tINS | FF | 1 | FP_Div_inst/n15829_s2/F |
8.422 | 0.237 | tNET | FF | 1 | FP_Div_inst/n15829_s1/I0 |
8.939 | 0.517 | tINS | FF | 1 | FP_Div_inst/n15829_s1/F |
9.176 | 0.237 | tNET | FF | 1 | FP_Div_inst/mant_prod_r_15_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk | |||
10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 3592 | clk_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | FP_Div_inst/mant_prod_r_15_s0/CLK |
10.828 | -0.035 | tSu | 1 | FP_Div_inst/mant_prod_r_15_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 11 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 5.474, 65.848%; route: 2.607, 31.361%; tC2Q: 0.232, 2.791% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |