Synthesis Messages

Report Title GowinSynthesis Report
Design File E:\myWork\IP\releaseVerify\RefDesign\DSP_Math\zipFile\1994\FP_Div_RefDesign\proj\src\fp_div\fp_div.v
E:\myWork\IP\releaseVerify\RefDesign\DSP_Math\zipFile\1994\FP_Div_RefDesign\proj\src\top.v
C:\Gowin\Gowin_V1.9.9Beta-4\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v
C:\Gowin\Gowin_V1.9.9Beta-4\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v
C:\Gowin\Gowin_V1.9.9Beta-4\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v
C:\Gowin\Gowin_V1.9.9Beta-4\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v
C:\Gowin\Gowin_V1.9.9Beta-4\IDE\data\ipcores\GAO\GW_CON\gw_con_top.v
C:\Gowin\Gowin_V1.9.9Beta-4\IDE\data\ipcores\gw_jtag.v
E:\myWork\IP\releaseVerify\RefDesign\DSP_Math\zipFile\1994\FP_Div_RefDesign\proj\impl\gwsynthesis\RTL_GAO\gw_gao_top.v
GowinSynthesis Constraints File ---
Version V1.9.9 Beta-4
Part Number GW2A-LV55PG484C8/I7
Device GW2A-55
Created Time Wed Sep 06 16:33:33 2023
Legal Announcement Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module top
Synthesis Process Running parser:
    CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 296.078MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.18s, Peak memory usage = 296.078MB
    Optimizing Phase 1: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.13s, Peak memory usage = 296.078MB
    Optimizing Phase 2: CPU time = 0h 0m 0.25s, Elapsed time = 0h 0m 0.248s, Peak memory usage = 296.078MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.116s, Peak memory usage = 296.078MB
    Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 296.078MB
    Inferring Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.033s, Peak memory usage = 296.078MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 296.078MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.15s, Peak memory usage = 296.078MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.056s, Peak memory usage = 296.078MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.03s, Peak memory usage = 296.078MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 296.078MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.16s, Peak memory usage = 296.078MB
Generate output files:
    CPU time = 0h 0m 0.375s, Elapsed time = 0h 0m 0.362s, Peak memory usage = 296.078MB
Total Time and Memory Usage CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s, Peak memory usage = 296.078MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 107
I/O Buf 107
    IBUF 5
    OBUF 102
Register 4249
    DFF 218
    DFFE 5
    DFFP 3
    DFFPE 33
    DFFC 3408
    DFFCE 582
LUT 936
    LUT2 174
    LUT3 189
    LUT4 573
MUX 1
    MUX16 1
ALU 1413
    ALU 1413
INV 114
    INV 114
BSRAM 13
    SDPB 9
    pROM 4
Black Box 1
    GW_JTAG 1

Resource Utilization Summary

Resource Usage Utilization
Logic 2471(1058 LUT, 1413 ALU) / 54720 5%
Register 4249 / 41997 11%
  --Register as Latch 0 / 41997 0%
  --Register as FF 4249 / 41997 11%
BSRAM 13 / 140 10%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
clk Base 10.000 100.0 0.000 5.000 clk_ibuf/I
gw_gao_inst_0/u_icon_top/n19_6 Base 10.000 100.0 0.000 5.000 gw_gao_inst_0/u_icon_top/n19_s2/O
gw_gao_inst_0/u_la0_top/n15_6 Base 10.000 100.0 0.000 5.000 gw_gao_inst_0/u_la0_top/n15_s2/O

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 100.0(MHz) 99.6(MHz) 14 TOP
2 gw_gao_inst_0/u_icon_top/n19_6 100.0(MHz) 1984.1(MHz) 1 TOP
3 gw_gao_inst_0/u_la0_top/n15_6 100.0(MHz) 1984.1(MHz) 1 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack -0.041
Data Arrival Time 10.868
Data Required Time 10.828
From FP_Div/FP_Div_inst/div0/integer_division_frac_inst/remainder_6_s0
To FP_Div/FP_Div_inst/overflow_reg_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.683 0.683 tINS RR 3877 clk_ibuf/O
0.863 0.180 tNET RR 1 FP_Div/FP_Div_inst/div0/integer_division_frac_inst/remainder_6_s0/CLK
1.095 0.232 tC2Q RF 7 FP_Div/FP_Div_inst/div0/integer_division_frac_inst/remainder_6_s0/Q
1.332 0.237 tNET FF 1 FP_Div/FP_Div_inst/exponent_normalize_9_s12/I1
1.887 0.555 tINS FF 9 FP_Div/FP_Div_inst/exponent_normalize_9_s12/F
2.124 0.237 tNET FF 1 FP_Div/FP_Div_inst/exponent_normalize_2_s8/I1
2.679 0.555 tINS FF 1 FP_Div/FP_Div_inst/exponent_normalize_2_s8/F
2.916 0.237 tNET FF 1 FP_Div/FP_Div_inst/exponent_normalize_2_s6/I1
3.471 0.555 tINS FF 1 FP_Div/FP_Div_inst/exponent_normalize_2_s6/F
3.708 0.237 tNET FF 1 FP_Div/FP_Div_inst/exponent_normalize_2_s4/I0
4.225 0.517 tINS FF 1 FP_Div/FP_Div_inst/exponent_normalize_2_s4/F
4.462 0.237 tNET FF 1 FP_Div/FP_Div_inst/exponent_normalize_2_s3/I0
4.979 0.517 tINS FF 12 FP_Div/FP_Div_inst/exponent_normalize_2_s3/F
5.216 0.237 tNET FF 1 FP_Div/FP_Div_inst/exponent_normalize_0_s8/I0
5.733 0.517 tINS FF 2 FP_Div/FP_Div_inst/exponent_normalize_0_s8/F
5.970 0.237 tNET FF 1 FP_Div/FP_Div_inst/exponent_normalize_0_s7/I3
6.341 0.371 tINS FF 4 FP_Div/FP_Div_inst/exponent_normalize_0_s7/F
6.578 0.237 tNET FF 1 FP_Div/FP_Div_inst/exponent_normalize_0_s9/I0
7.095 0.517 tINS FF 2 FP_Div/FP_Div_inst/exponent_normalize_0_s9/F
7.332 0.237 tNET FF 2 FP_Div/FP_Div_inst/n15567_s/I1
7.902 0.570 tINS FR 1 FP_Div/FP_Div_inst/n15567_s/COUT
7.902 0.000 tNET RR 2 FP_Div/FP_Div_inst/n15566_s/CIN
7.937 0.035 tINS RF 1 FP_Div/FP_Div_inst/n15566_s/COUT
7.937 0.000 tNET FF 2 FP_Div/FP_Div_inst/n15565_s/CIN
7.972 0.035 tINS FF 1 FP_Div/FP_Div_inst/n15565_s/COUT
7.972 0.000 tNET FF 2 FP_Div/FP_Div_inst/n15564_s/CIN
8.007 0.035 tINS FF 1 FP_Div/FP_Div_inst/n15564_s/COUT
8.007 0.000 tNET FF 2 FP_Div/FP_Div_inst/n15563_s/CIN
8.477 0.470 tINS FF 1 FP_Div/FP_Div_inst/n15563_s/SUM
8.714 0.237 tNET FF 1 FP_Div/FP_Div_inst/n15570_s4/I1
9.269 0.555 tINS FF 1 FP_Div/FP_Div_inst/n15570_s4/F
9.506 0.237 tNET FF 1 FP_Div/FP_Div_inst/n15570_s2/I3
9.877 0.371 tINS FF 1 FP_Div/FP_Div_inst/n15570_s2/F
10.114 0.237 tNET FF 1 FP_Div/FP_Div_inst/n15570_s1/I0
10.631 0.517 tINS FF 1 FP_Div/FP_Div_inst/n15570_s1/F
10.868 0.237 tNET FF 1 FP_Div/FP_Div_inst/overflow_reg_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.682 0.683 tINS RR 3877 clk_ibuf/O
10.863 0.180 tNET RR 1 FP_Div/FP_Div_inst/overflow_reg_s0/CLK
10.828 -0.035 tSu 1 FP_Div/FP_Div_inst/overflow_reg_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 14
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 6.693, 66.888%; route: 3.081, 30.793%; tC2Q: 0.232, 2.319%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 2

Path Summary:
Slack 1.216
Data Arrival Time 9.612
Data Required Time 10.828
From FP_Div/FP_Div_inst/div0/integer_division_frac_inst/remainder_6_s0
To FP_Div/FP_Div_inst/underflow_reg_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.683 0.683 tINS RR 3877 clk_ibuf/O
0.863 0.180 tNET RR 1 FP_Div/FP_Div_inst/div0/integer_division_frac_inst/remainder_6_s0/CLK
1.095 0.232 tC2Q RF 7 FP_Div/FP_Div_inst/div0/integer_division_frac_inst/remainder_6_s0/Q
1.332 0.237 tNET FF 1 FP_Div/FP_Div_inst/exponent_normalize_9_s12/I1
1.887 0.555 tINS FF 9 FP_Div/FP_Div_inst/exponent_normalize_9_s12/F
2.124 0.237 tNET FF 1 FP_Div/FP_Div_inst/exponent_normalize_2_s8/I1
2.679 0.555 tINS FF 1 FP_Div/FP_Div_inst/exponent_normalize_2_s8/F
2.916 0.237 tNET FF 1 FP_Div/FP_Div_inst/exponent_normalize_2_s6/I1
3.471 0.555 tINS FF 1 FP_Div/FP_Div_inst/exponent_normalize_2_s6/F
3.708 0.237 tNET FF 1 FP_Div/FP_Div_inst/exponent_normalize_2_s4/I0
4.225 0.517 tINS FF 1 FP_Div/FP_Div_inst/exponent_normalize_2_s4/F
4.462 0.237 tNET FF 1 FP_Div/FP_Div_inst/exponent_normalize_2_s3/I0
4.979 0.517 tINS FF 12 FP_Div/FP_Div_inst/exponent_normalize_2_s3/F
5.216 0.237 tNET FF 1 FP_Div/FP_Div_inst/exponent_normalize_0_s8/I0
5.733 0.517 tINS FF 2 FP_Div/FP_Div_inst/exponent_normalize_0_s8/F
5.970 0.237 tNET FF 1 FP_Div/FP_Div_inst/exponent_normalize_0_s7/I3
6.341 0.371 tINS FF 4 FP_Div/FP_Div_inst/exponent_normalize_0_s7/F
6.578 0.237 tNET FF 1 FP_Div/FP_Div_inst/exponent_normalize_0_s9/I0
7.095 0.517 tINS FF 2 FP_Div/FP_Div_inst/exponent_normalize_0_s9/F
7.332 0.237 tNET FF 1 FP_Div/FP_Div_inst/n15613_s/I1
7.902 0.570 tINS FR 1 FP_Div/FP_Div_inst/n15613_s/COUT
7.902 0.000 tNET RR 1 FP_Div/FP_Div_inst/n15612_s/CIN
7.937 0.035 tINS RF 1 FP_Div/FP_Div_inst/n15612_s/COUT
7.937 0.000 tNET FF 1 FP_Div/FP_Div_inst/n15611_s/CIN
7.972 0.035 tINS FF 1 FP_Div/FP_Div_inst/n15611_s/COUT
7.972 0.000 tNET FF 1 FP_Div/FP_Div_inst/n15610_s/CIN
8.007 0.035 tINS FF 1 FP_Div/FP_Div_inst/n15610_s/COUT
8.007 0.000 tNET FF 1 FP_Div/FP_Div_inst/n15609_s/CIN
8.042 0.035 tINS FF 1 FP_Div/FP_Div_inst/n15609_s/COUT
8.042 0.000 tNET FF 1 FP_Div/FP_Div_inst/n15608_s/CIN
8.078 0.035 tINS FF 1 FP_Div/FP_Div_inst/n15608_s/COUT
8.078 0.000 tNET FF 1 FP_Div/FP_Div_inst/n15607_s/CIN
8.113 0.035 tINS FF 1 FP_Div/FP_Div_inst/n15607_s/COUT
8.113 0.000 tNET FF 2 FP_Div/FP_Div_inst/n15606_s/CIN
8.583 0.470 tINS FF 1 FP_Div/FP_Div_inst/n15606_s/SUM
8.820 0.237 tNET FF 1 FP_Div/FP_Div_inst/n15616_s1/I1
9.375 0.555 tINS FF 1 FP_Div/FP_Div_inst/n15616_s1/F
9.612 0.237 tNET FF 1 FP_Div/FP_Div_inst/underflow_reg_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.682 0.683 tINS RR 3877 clk_ibuf/O
10.863 0.180 tNET RR 1 FP_Div/FP_Div_inst/underflow_reg_s0/CLK
10.828 -0.035 tSu 1 FP_Div/FP_Div_inst/underflow_reg_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 13
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 5.910, 67.551%; route: 2.607, 29.797%; tC2Q: 0.232, 2.652%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 3

Path Summary:
Slack 1.614
Data Arrival Time 9.214
Data Required Time 10.828
From FP_Div/FP_Div_inst/div0/integer_division_frac_inst/remainder_6_s0
To FP_Div/FP_Div_inst/mant_prod_r_7_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.683 0.683 tINS RR 3877 clk_ibuf/O
0.863 0.180 tNET RR 1 FP_Div/FP_Div_inst/div0/integer_division_frac_inst/remainder_6_s0/CLK
1.095 0.232 tC2Q RF 7 FP_Div/FP_Div_inst/div0/integer_division_frac_inst/remainder_6_s0/Q
1.332 0.237 tNET FF 1 FP_Div/FP_Div_inst/exponent_normalize_9_s12/I1
1.887 0.555 tINS FF 9 FP_Div/FP_Div_inst/exponent_normalize_9_s12/F
2.124 0.237 tNET FF 1 FP_Div/FP_Div_inst/exponent_normalize_1_s17/I1
2.679 0.555 tINS FF 3 FP_Div/FP_Div_inst/exponent_normalize_1_s17/F
2.916 0.237 tNET FF 1 FP_Div/FP_Div_inst/exponent_normalize_1_s9/I1
3.471 0.555 tINS FF 3 FP_Div/FP_Div_inst/exponent_normalize_1_s9/F
3.708 0.237 tNET FF 1 FP_Div/FP_Div_inst/exponent_normalize_1_s4/I1
4.263 0.555 tINS FF 1 FP_Div/FP_Div_inst/exponent_normalize_1_s4/F
4.500 0.237 tNET FF 1 FP_Div/FP_Div_inst/exponent_normalize_1_s2/I1
5.055 0.555 tINS FF 70 FP_Div/FP_Div_inst/exponent_normalize_1_s2/F
5.292 0.237 tNET FF 1 FP_Div/FP_Div_inst/n15825_s23/I0
5.809 0.517 tINS FF 1 FP_Div/FP_Div_inst/n15825_s23/F
6.046 0.237 tNET FF 1 FP_Div/FP_Div_inst/n15825_s18/I1
6.601 0.555 tINS FF 1 FP_Div/FP_Div_inst/n15825_s18/F
6.838 0.237 tNET FF 1 FP_Div/FP_Div_inst/n15825_s13/I1
7.392 0.555 tINS FF 5 FP_Div/FP_Div_inst/n15825_s13/F
7.629 0.237 tNET FF 1 FP_Div/FP_Div_inst/n15837_s3/I1
8.184 0.555 tINS FF 1 FP_Div/FP_Div_inst/n15837_s3/F
8.422 0.237 tNET FF 1 FP_Div/FP_Div_inst/n15837_s1/I1
8.977 0.555 tINS FF 1 FP_Div/FP_Div_inst/n15837_s1/F
9.214 0.237 tNET FF 1 FP_Div/FP_Div_inst/mant_prod_r_7_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.682 0.683 tINS RR 3877 clk_ibuf/O
10.863 0.180 tNET RR 1 FP_Div/FP_Div_inst/mant_prod_r_7_s0/CLK
10.828 -0.035 tSu 1 FP_Div/FP_Div_inst/mant_prod_r_7_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 11
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 5.512, 66.004%; route: 2.607, 31.218%; tC2Q: 0.232, 2.778%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 4

Path Summary:
Slack 1.652
Data Arrival Time 9.176
Data Required Time 10.828
From FP_Div/FP_Div_inst/div0/integer_division_frac_inst/remainder_6_s0
To FP_Div/FP_Div_inst/mant_prod_r_11_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.683 0.683 tINS RR 3877 clk_ibuf/O
0.863 0.180 tNET RR 1 FP_Div/FP_Div_inst/div0/integer_division_frac_inst/remainder_6_s0/CLK
1.095 0.232 tC2Q RF 7 FP_Div/FP_Div_inst/div0/integer_division_frac_inst/remainder_6_s0/Q
1.332 0.237 tNET FF 1 FP_Div/FP_Div_inst/exponent_normalize_9_s12/I1
1.887 0.555 tINS FF 9 FP_Div/FP_Div_inst/exponent_normalize_9_s12/F
2.124 0.237 tNET FF 1 FP_Div/FP_Div_inst/exponent_normalize_1_s17/I1
2.679 0.555 tINS FF 3 FP_Div/FP_Div_inst/exponent_normalize_1_s17/F
2.916 0.237 tNET FF 1 FP_Div/FP_Div_inst/exponent_normalize_1_s9/I1
3.471 0.555 tINS FF 3 FP_Div/FP_Div_inst/exponent_normalize_1_s9/F
3.708 0.237 tNET FF 1 FP_Div/FP_Div_inst/exponent_normalize_1_s4/I1
4.263 0.555 tINS FF 1 FP_Div/FP_Div_inst/exponent_normalize_1_s4/F
4.500 0.237 tNET FF 1 FP_Div/FP_Div_inst/exponent_normalize_1_s2/I1
5.055 0.555 tINS FF 70 FP_Div/FP_Div_inst/exponent_normalize_1_s2/F
5.292 0.237 tNET FF 1 FP_Div/FP_Div_inst/n15825_s23/I0
5.809 0.517 tINS FF 1 FP_Div/FP_Div_inst/n15825_s23/F
6.046 0.237 tNET FF 1 FP_Div/FP_Div_inst/n15825_s18/I1
6.601 0.555 tINS FF 1 FP_Div/FP_Div_inst/n15825_s18/F
6.838 0.237 tNET FF 1 FP_Div/FP_Div_inst/n15825_s13/I1
7.392 0.555 tINS FF 5 FP_Div/FP_Div_inst/n15825_s13/F
7.629 0.237 tNET FF 1 FP_Div/FP_Div_inst/n15833_s2/I1
8.184 0.555 tINS FF 1 FP_Div/FP_Div_inst/n15833_s2/F
8.422 0.237 tNET FF 1 FP_Div/FP_Div_inst/n15833_s1/I0
8.939 0.517 tINS FF 1 FP_Div/FP_Div_inst/n15833_s1/F
9.176 0.237 tNET FF 1 FP_Div/FP_Div_inst/mant_prod_r_11_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.682 0.683 tINS RR 3877 clk_ibuf/O
10.863 0.180 tNET RR 1 FP_Div/FP_Div_inst/mant_prod_r_11_s0/CLK
10.828 -0.035 tSu 1 FP_Div/FP_Div_inst/mant_prod_r_11_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 11
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 5.474, 65.848%; route: 2.607, 31.361%; tC2Q: 0.232, 2.791%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 5

Path Summary:
Slack 1.652
Data Arrival Time 9.176
Data Required Time 10.828
From FP_Div/FP_Div_inst/div0/integer_division_frac_inst/remainder_6_s0
To FP_Div/FP_Div_inst/mant_prod_r_15_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.683 0.683 tINS RR 3877 clk_ibuf/O
0.863 0.180 tNET RR 1 FP_Div/FP_Div_inst/div0/integer_division_frac_inst/remainder_6_s0/CLK
1.095 0.232 tC2Q RF 7 FP_Div/FP_Div_inst/div0/integer_division_frac_inst/remainder_6_s0/Q
1.332 0.237 tNET FF 1 FP_Div/FP_Div_inst/exponent_normalize_9_s12/I1
1.887 0.555 tINS FF 9 FP_Div/FP_Div_inst/exponent_normalize_9_s12/F
2.124 0.237 tNET FF 1 FP_Div/FP_Div_inst/exponent_normalize_1_s17/I1
2.679 0.555 tINS FF 3 FP_Div/FP_Div_inst/exponent_normalize_1_s17/F
2.916 0.237 tNET FF 1 FP_Div/FP_Div_inst/exponent_normalize_1_s9/I1
3.471 0.555 tINS FF 3 FP_Div/FP_Div_inst/exponent_normalize_1_s9/F
3.708 0.237 tNET FF 1 FP_Div/FP_Div_inst/exponent_normalize_1_s4/I1
4.263 0.555 tINS FF 1 FP_Div/FP_Div_inst/exponent_normalize_1_s4/F
4.500 0.237 tNET FF 1 FP_Div/FP_Div_inst/exponent_normalize_1_s2/I1
5.055 0.555 tINS FF 70 FP_Div/FP_Div_inst/exponent_normalize_1_s2/F
5.292 0.237 tNET FF 1 FP_Div/FP_Div_inst/n15825_s23/I0
5.809 0.517 tINS FF 1 FP_Div/FP_Div_inst/n15825_s23/F
6.046 0.237 tNET FF 1 FP_Div/FP_Div_inst/n15825_s18/I1
6.601 0.555 tINS FF 1 FP_Div/FP_Div_inst/n15825_s18/F
6.838 0.237 tNET FF 1 FP_Div/FP_Div_inst/n15825_s13/I1
7.392 0.555 tINS FF 5 FP_Div/FP_Div_inst/n15825_s13/F
7.629 0.237 tNET FF 1 FP_Div/FP_Div_inst/n15829_s2/I1
8.184 0.555 tINS FF 1 FP_Div/FP_Div_inst/n15829_s2/F
8.422 0.237 tNET FF 1 FP_Div/FP_Div_inst/n15829_s1/I0
8.939 0.517 tINS FF 1 FP_Div/FP_Div_inst/n15829_s1/F
9.176 0.237 tNET FF 1 FP_Div/FP_Div_inst/mant_prod_r_15_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.682 0.683 tINS RR 3877 clk_ibuf/O
10.863 0.180 tNET RR 1 FP_Div/FP_Div_inst/mant_prod_r_15_s0/CLK
10.828 -0.035 tSu 1 FP_Div/FP_Div_inst/mant_prod_r_15_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 11
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 5.474, 65.848%; route: 2.607, 31.361%; tC2Q: 0.232, 2.791%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%