Timing Messages
Report Title | Timing Analysis Report |
Design File | E:\myWork\IP\releaseVerify\RefDesign\DSP_Math\zipFile\1994\FP_Sqrt_RefDesign\proj\impl\gwsynthesis\FP_Sqrt_Refdesign.vg |
Physical Constraints File | E:\myWork\IP\releaseVerify\RefDesign\DSP_Math\zipFile\1994\FP_Sqrt_RefDesign\proj\src\FP_Sqrt.cst |
Timing Constraint File | E:\myWork\IP\releaseVerify\RefDesign\DSP_Math\zipFile\1994\FP_Sqrt_RefDesign\proj\src\FP_Sqrt.sdc |
Version | V1.9.9 Beta-4 |
Part Number | GW2A-LV55PG484C8/I7 |
Device | GW2A-55 |
Created Time | Mon Sep 11 15:01:54 2023 |
Legal Announcement | Copyright (C)2014-2023 Gowin Semiconductor Corporation. All rights reserved. |
Timing Summaries
STA Tool Run Summary:
Setup Delay Model | Slow 0.95V 85C C8/I7 |
Hold Delay Model | Fast 1.05V 0C C8/I7 |
Numbers of Paths Analyzed | 4847 |
Numbers of Endpoints Analyzed | 5131 |
Numbers of Falling Endpoints | 3 |
Numbers of Setup Violated Endpoints | 0 |
Numbers of Hold Violated Endpoints | 0 |
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Objects |
---|---|---|---|---|---|---|---|---|
clk | Base | 20.000 | 50.000 | 0.000 | 10.000 | clk | ||
tck_pad_i | Base | 50.000 | 20.000 | 0.000 | 25.000 | tck_pad_i |
Max Frequency Summary:
NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | clk | 50.000(MHz) | 94.854(MHz) | 13 | TOP |
2 | tck_pad_i | 20.000(MHz) | 141.393(MHz) | 6 | TOP |
Total Negative Slack Summary:
Clock Name | Analysis Type | Endpoints TNS | Number of Endpoints |
---|---|---|---|
clk | Setup | 0.000 | 0 |
clk | Hold | 0.000 | 0 |
tck_pad_i | Setup | 0.000 | 0 |
tck_pad_i | Hold | 0.000 | 0 |
Timing Details
Path Slacks Table:
Setup Paths Table
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 4.423 | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_15_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/D | tck_pad_i:[R] | clk:[R] | 10.000 | 1.221 | 4.286 |
2 | 4.469 | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_15_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/D | tck_pad_i:[R] | clk:[R] | 10.000 | 1.221 | 4.240 |
3 | 4.619 | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_15_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/D | tck_pad_i:[R] | clk:[R] | 10.000 | 1.221 | 4.090 |
4 | 4.650 | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_15_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CE | tck_pad_i:[R] | clk:[R] | 10.000 | 1.221 | 4.059 |
5 | 4.687 | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_15_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/D | tck_pad_i:[R] | clk:[R] | 10.000 | 1.221 | 4.022 |
6 | 4.698 | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_15_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/D | tck_pad_i:[R] | clk:[R] | 10.000 | 1.221 | 4.011 |
7 | 4.896 | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_15_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/D | tck_pad_i:[R] | clk:[R] | 10.000 | 1.221 | 3.813 |
8 | 4.941 | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_15_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/D | tck_pad_i:[R] | clk:[R] | 10.000 | 1.221 | 3.768 |
9 | 5.026 | gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_15_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CE | tck_pad_i:[R] | clk:[R] | 10.000 | 1.221 | 3.683 |
10 | 5.095 | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_15_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/D | tck_pad_i:[R] | clk:[R] | 10.000 | 1.221 | 3.614 |
11 | 5.095 | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_15_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/D | tck_pad_i:[R] | clk:[R] | 10.000 | 1.221 | 3.614 |
12 | 5.258 | gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_2_s0/Q | gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/D | tck_pad_i:[R] | clk:[R] | 10.000 | 1.221 | 3.451 |
13 | 5.264 | gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_15_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CE | tck_pad_i:[R] | clk:[R] | 10.000 | 1.221 | 3.445 |
14 | 5.311 | gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_2_s0/Q | gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CE | tck_pad_i:[R] | clk:[R] | 10.000 | 1.221 | 3.398 |
15 | 5.537 | gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_2_s0/Q | gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/D | tck_pad_i:[R] | clk:[R] | 10.000 | 1.221 | 3.172 |
16 | 5.678 | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_15_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/D | tck_pad_i:[R] | clk:[R] | 10.000 | 1.221 | 3.031 |
17 | 5.706 | gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_15_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/D | tck_pad_i:[R] | clk:[R] | 10.000 | 1.221 | 3.003 |
18 | 5.776 | gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_2_s0/Q | gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/D | tck_pad_i:[R] | clk:[R] | 10.000 | 1.221 | 2.934 |
19 | 5.925 | gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_2_s0/Q | gw_gao_inst_0/u_la0_top/triger_s0/D | tck_pad_i:[R] | clk:[R] | 10.000 | 1.221 | 2.784 |
20 | 5.936 | gw_gao_inst_0/u_la0_top/capture_windows_num_0_s0/Q | gw_gao_inst_0/u_la0_top/start_reg_s0/D | tck_pad_i:[R] | clk:[R] | 10.000 | 1.221 | 2.773 |
21 | 6.023 | gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_2_s0/Q | gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/D | tck_pad_i:[R] | clk:[R] | 10.000 | 1.221 | 2.686 |
22 | 6.846 | gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_9_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/D | tck_pad_i:[R] | clk:[R] | 10.000 | 1.221 | 1.863 |
23 | 6.941 | gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_5_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/D | tck_pad_i:[R] | clk:[R] | 10.000 | 1.221 | 1.768 |
24 | 6.978 | gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_6_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/D | tck_pad_i:[R] | clk:[R] | 10.000 | 1.221 | 1.731 |
25 | 7.046 | gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_3_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/D | tck_pad_i:[R] | clk:[R] | 10.000 | 1.221 | 1.663 |
Hold Paths Table
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 0.190 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CEA | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.202 |
2 | 0.190 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CEA | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.202 |
3 | 0.190 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CEA | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.202 |
4 | 0.190 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CEA | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.202 |
5 | 0.190 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CEA | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.202 |
6 | 0.213 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_44_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[12] | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.462 |
7 | 0.213 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_28_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[12] | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.462 |
8 | 0.213 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_27_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[11] | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.462 |
9 | 0.225 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_57_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[9] | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.474 |
10 | 0.225 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_26_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[10] | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.474 |
11 | 0.225 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_23_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[7] | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.474 |
12 | 0.225 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_19_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[3] | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.474 |
13 | 0.225 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_17_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[1] | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.474 |
14 | 0.335 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_53_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[5] | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.584 |
15 | 0.335 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_24_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[8] | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.584 |
16 | 0.347 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_50_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[2] | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.596 |
17 | 0.347 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_20_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[4] | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.596 |
18 | 0.347 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_18_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[2] | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.596 |
19 | 0.347 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_0_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[0] | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.596 |
20 | 0.351 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_49_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[1] | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.600 |
21 | 0.351 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_41_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[9] | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.600 |
22 | 0.351 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_29_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[13] | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.600 |
23 | 0.351 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_25_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[9] | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.600 |
24 | 0.351 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_21_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[5] | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.600 |
25 | 0.351 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_16_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[0] | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.600 |
Recovery Paths Table
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 8.325 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR | clk:[F] | clk:[R] | 10.000 | 0.023 | 1.617 |
2 | 8.538 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLEAR | clk:[F] | clk:[R] | 10.000 | 0.023 | 1.404 |
3 | 8.544 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR | clk:[F] | clk:[R] | 10.000 | 0.023 | 1.398 |
4 | 8.544 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR | clk:[F] | clk:[R] | 10.000 | 0.023 | 1.398 |
5 | 8.567 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR | clk:[F] | clk:[R] | 10.000 | 0.023 | 1.374 |
6 | 8.567 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR | clk:[F] | clk:[R] | 10.000 | 0.023 | 1.374 |
7 | 8.567 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR | clk:[F] | clk:[R] | 10.000 | 0.023 | 1.374 |
8 | 8.573 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR | clk:[F] | clk:[R] | 10.000 | 0.023 | 1.369 |
9 | 8.573 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLEAR | clk:[F] | clk:[R] | 10.000 | 0.023 | 1.369 |
10 | 8.573 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR | clk:[F] | clk:[R] | 10.000 | 0.023 | 1.369 |
11 | 8.573 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR | clk:[F] | clk:[R] | 10.000 | 0.023 | 1.369 |
12 | 8.573 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR | clk:[F] | clk:[R] | 10.000 | 0.023 | 1.369 |
13 | 8.756 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET | clk:[F] | clk:[R] | 10.000 | 0.023 | 1.186 |
14 | 8.756 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR | clk:[F] | clk:[R] | 10.000 | 0.023 | 1.186 |
15 | 8.756 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR | clk:[F] | clk:[R] | 10.000 | 0.023 | 1.186 |
16 | 8.756 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR | clk:[F] | clk:[R] | 10.000 | 0.023 | 1.186 |
17 | 8.762 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR | clk:[F] | clk:[R] | 10.000 | 0.023 | 1.180 |
18 | 8.762 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR | clk:[F] | clk:[R] | 10.000 | 0.023 | 1.180 |
19 | 8.781 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR | clk:[F] | clk:[R] | 10.000 | 0.023 | 1.161 |
20 | 8.822 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR | clk:[F] | clk:[R] | 10.000 | 0.023 | 1.120 |
21 | 8.822 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR | clk:[F] | clk:[R] | 10.000 | 0.023 | 1.120 |
22 | 8.822 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR | clk:[F] | clk:[R] | 10.000 | 0.023 | 1.120 |
23 | 8.822 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR | clk:[F] | clk:[R] | 10.000 | 0.023 | 1.120 |
24 | 8.822 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR | clk:[F] | clk:[R] | 10.000 | 0.023 | 1.120 |
25 | 8.822 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR | clk:[F] | clk:[R] | 10.000 | 0.023 | 1.120 |
Removal Paths Table
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 10.477 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLEAR | clk:[F] | clk:[R] | -10.000 | 0.012 | 0.476 |
2 | 10.477 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLEAR | clk:[F] | clk:[R] | -10.000 | 0.012 | 0.476 |
3 | 10.477 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLEAR | clk:[F] | clk:[R] | -10.000 | 0.012 | 0.476 |
4 | 10.477 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLEAR | clk:[F] | clk:[R] | -10.000 | 0.012 | 0.476 |
5 | 10.590 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR | clk:[F] | clk:[R] | -10.000 | 0.012 | 0.589 |
6 | 10.590 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/triger_s0/CLEAR | clk:[F] | clk:[R] | -10.000 | 0.012 | 0.589 |
7 | 10.590 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/start_reg_s0/CLEAR | clk:[F] | clk:[R] | -10.000 | 0.012 | 0.589 |
8 | 10.599 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLEAR | clk:[F] | clk:[R] | -10.000 | 0.012 | 0.598 |
9 | 10.602 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLEAR | clk:[F] | clk:[R] | -10.000 | 0.012 | 0.601 |
10 | 10.602 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR | clk:[F] | clk:[R] | -10.000 | 0.012 | 0.601 |
11 | 10.602 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR | clk:[F] | clk:[R] | -10.000 | 0.012 | 0.601 |
12 | 10.602 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR | clk:[F] | clk:[R] | -10.000 | 0.012 | 0.601 |
13 | 10.602 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLEAR | clk:[F] | clk:[R] | -10.000 | 0.012 | 0.601 |
14 | 10.618 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR | clk:[F] | clk:[R] | -10.000 | 0.012 | 0.616 |
15 | 10.618 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR | clk:[F] | clk:[R] | -10.000 | 0.012 | 0.616 |
16 | 10.618 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR | clk:[F] | clk:[R] | -10.000 | 0.012 | 0.616 |
17 | 10.620 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR | clk:[F] | clk:[R] | -10.000 | 0.012 | 0.619 |
18 | 10.620 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_flag_s0/CLEAR | clk:[F] | clk:[R] | -10.000 | 0.012 | 0.619 |
19 | 10.620 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET | clk:[F] | clk:[R] | -10.000 | 0.012 | 0.619 |
20 | 10.724 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR | clk:[F] | clk:[R] | -10.000 | 0.012 | 0.723 |
21 | 10.742 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR | clk:[F] | clk:[R] | -10.000 | 0.012 | 0.741 |
22 | 10.742 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR | clk:[F] | clk:[R] | -10.000 | 0.012 | 0.741 |
23 | 10.745 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET | clk:[F] | clk:[R] | -10.000 | 0.012 | 0.744 |
24 | 10.745 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR | clk:[F] | clk:[R] | -10.000 | 0.012 | 0.744 |
25 | 10.745 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR | clk:[F] | clk:[R] | -10.000 | 0.012 | 0.744 |
Minimum Pulse Width Table:
Number | Slack | Actual Width | Required Width | Type | Clock | Objects |
---|---|---|---|---|---|---|
1 | 8.911 | 9.911 | 1.000 | Low Pulse Width | clk | i_data_5_s0 |
2 | 8.911 | 9.911 | 1.000 | Low Pulse Width | clk | i_data_3_s0 |
3 | 8.911 | 9.911 | 1.000 | Low Pulse Width | clk | start_s0 |
4 | 8.911 | 9.911 | 1.000 | Low Pulse Width | clk | FP_Sqrt/FP_Sqrt_inst/count_3_s0 |
5 | 8.911 | 9.911 | 1.000 | Low Pulse Width | clk | FP_Sqrt/FP_Sqrt_inst/s_reg_14_s0 |
6 | 8.911 | 9.911 | 1.000 | Low Pulse Width | clk | FP_Sqrt/FP_Sqrt_inst/mant_adelay[0]_13_s0 |
7 | 8.911 | 9.911 | 1.000 | Low Pulse Width | clk | FP_Sqrt/FP_Sqrt_inst/gen[0].uut/s_out_17_s0 |
8 | 8.911 | 9.911 | 1.000 | Low Pulse Width | clk | FP_Sqrt/FP_Sqrt_inst/gen[4].uut/q_out1_23_s0 |
9 | 8.911 | 9.911 | 1.000 | Low Pulse Width | clk | FP_Sqrt/FP_Sqrt_inst/gen[10].uut/q_out1_1_s0 |
10 | 8.911 | 9.911 | 1.000 | Low Pulse Width | clk | FP_Sqrt/FP_Sqrt_inst/gen[24].uut/q_out_9_s0 |
Timing Report By Analysis Type:
Setup Analysis Report
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 4.423 |
Data Arrival Time | 56.433 |
Data Required Time | 60.856 |
From | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_15_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | tck_pad_i | ||||
50.000 | 0.000 | tCL | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/I |
50.682 | 0.683 | tINS | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/O |
50.682 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
51.365 | 0.683 | tINS | RR | 323 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
52.147 | 0.782 | tNET | RR | 1 | R22C75[1][A] | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_15_s0/CLK |
52.379 | 0.232 | tC2Q | RF | 2 | R22C75[1][A] | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_15_s0/Q |
53.021 | 0.642 | tNET | FF | 1 | R18C75[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n514_s9/I3 |
53.570 | 0.549 | tINS | FR | 1 | R18C75[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n514_s9/F |
53.742 | 0.172 | tNET | RR | 1 | R18C76[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n514_s7/I0 |
54.297 | 0.555 | tINS | RF | 2 | R18C76[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n514_s7/F |
54.716 | 0.419 | tNET | FF | 1 | R17C77[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n514_s5/I0 |
55.169 | 0.453 | tINS | FF | 10 | R17C77[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n514_s5/F |
55.863 | 0.694 | tNET | FF | 1 | R14C78[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n522_s1/I2 |
56.433 | 0.570 | tINS | FR | 1 | R14C78[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n522_s1/F |
56.433 | 0.000 | tNET | RR | 1 | R14C78[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
60.000 | 60.000 | active clock edge time | ||||
60.000 | 0.000 | clk | ||||
60.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
60.682 | 0.683 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
60.926 | 0.243 | tNET | RR | 1 | R14C78[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK |
60.891 | -0.035 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1 | |||
60.856 | -0.035 | tSu | 1 | R14C78[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1 |
Path Statistics:
Clock Skew | -1.221 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 1.365, 63.584%; route: 0.782, 36.416% |
Arrival Data Path Delay | cell: 2.127, 49.624%; route: 1.927, 44.963%; tC2Q: 0.232, 5.413% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path2
Path Summary:
Slack | 4.469 |
Data Arrival Time | 56.387 |
Data Required Time | 60.856 |
From | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_15_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | tck_pad_i | ||||
50.000 | 0.000 | tCL | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/I |
50.682 | 0.683 | tINS | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/O |
50.682 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
51.365 | 0.683 | tINS | RR | 323 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
52.147 | 0.782 | tNET | RR | 1 | R22C75[1][A] | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_15_s0/CLK |
52.379 | 0.232 | tC2Q | RF | 2 | R22C75[1][A] | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_15_s0/Q |
53.021 | 0.642 | tNET | FF | 1 | R18C75[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n514_s9/I3 |
53.570 | 0.549 | tINS | FR | 1 | R18C75[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n514_s9/F |
53.742 | 0.172 | tNET | RR | 1 | R18C76[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n514_s7/I0 |
54.297 | 0.555 | tINS | RF | 2 | R18C76[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n514_s7/F |
54.716 | 0.419 | tNET | FF | 1 | R17C77[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n514_s5/I0 |
55.169 | 0.453 | tINS | FF | 10 | R17C77[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n514_s5/F |
55.838 | 0.669 | tNET | FF | 1 | R13C77[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n516_s1/I3 |
56.387 | 0.549 | tINS | FR | 1 | R13C77[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n516_s1/F |
56.387 | 0.000 | tNET | RR | 1 | R13C77[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
60.000 | 60.000 | active clock edge time | ||||
60.000 | 0.000 | clk | ||||
60.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
60.682 | 0.683 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
60.926 | 0.243 | tNET | RR | 1 | R13C77[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK |
60.891 | -0.035 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1 | |||
60.856 | -0.035 | tSu | 1 | R13C77[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1 |
Path Statistics:
Clock Skew | -1.221 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 1.365, 63.584%; route: 0.782, 36.416% |
Arrival Data Path Delay | cell: 2.106, 49.670%; route: 1.902, 44.858%; tC2Q: 0.232, 5.472% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path3
Path Summary:
Slack | 4.619 |
Data Arrival Time | 56.237 |
Data Required Time | 60.856 |
From | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_15_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | tck_pad_i | ||||
50.000 | 0.000 | tCL | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/I |
50.682 | 0.683 | tINS | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/O |
50.682 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
51.365 | 0.683 | tINS | RR | 323 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
52.147 | 0.782 | tNET | RR | 1 | R22C75[1][A] | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_15_s0/CLK |
52.379 | 0.232 | tC2Q | RF | 2 | R22C75[1][A] | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_15_s0/Q |
53.021 | 0.642 | tNET | FF | 1 | R18C75[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n514_s9/I3 |
53.570 | 0.549 | tINS | FR | 1 | R18C75[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n514_s9/F |
53.742 | 0.172 | tNET | RR | 1 | R18C76[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n514_s7/I0 |
54.297 | 0.555 | tINS | RF | 2 | R18C76[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n514_s7/F |
54.716 | 0.419 | tNET | FF | 1 | R17C77[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n514_s5/I0 |
55.169 | 0.453 | tINS | FF | 10 | R17C77[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n514_s5/F |
55.688 | 0.519 | tNET | FF | 1 | R13C77[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n521_s1/I3 |
56.237 | 0.549 | tINS | FR | 1 | R13C77[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n521_s1/F |
56.237 | 0.000 | tNET | RR | 1 | R13C77[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
60.000 | 60.000 | active clock edge time | ||||
60.000 | 0.000 | clk | ||||
60.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
60.682 | 0.683 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
60.926 | 0.243 | tNET | RR | 1 | R13C77[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK |
60.891 | -0.035 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1 | |||
60.856 | -0.035 | tSu | 1 | R13C77[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1 |
Path Statistics:
Clock Skew | -1.221 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 1.365, 63.584%; route: 0.782, 36.416% |
Arrival Data Path Delay | cell: 2.106, 51.490%; route: 1.752, 42.838%; tC2Q: 0.232, 5.672% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path4
Path Summary:
Slack | 4.650 |
Data Arrival Time | 56.206 |
Data Required Time | 60.856 |
From | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_15_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | tck_pad_i | ||||
50.000 | 0.000 | tCL | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/I |
50.682 | 0.683 | tINS | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/O |
50.682 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
51.365 | 0.683 | tINS | RR | 323 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
52.147 | 0.782 | tNET | RR | 1 | R22C75[1][A] | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_15_s0/CLK |
52.379 | 0.232 | tC2Q | RF | 2 | R22C75[1][A] | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_15_s0/Q |
53.021 | 0.642 | tNET | FF | 1 | R18C75[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n514_s9/I3 |
53.570 | 0.549 | tINS | FR | 1 | R18C75[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n514_s9/F |
53.742 | 0.172 | tNET | RR | 1 | R18C76[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n514_s7/I0 |
54.297 | 0.555 | tINS | RF | 2 | R18C76[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n514_s7/F |
54.716 | 0.419 | tNET | FF | 1 | R17C77[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n514_s5/I0 |
55.169 | 0.453 | tINS | FF | 10 | R17C77[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n514_s5/F |
55.600 | 0.431 | tNET | FF | 1 | R18C78[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s4/I0 |
56.062 | 0.462 | tINS | FR | 1 | R18C78[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s4/F |
56.206 | 0.144 | tNET | RR | 1 | R18C78[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
60.000 | 60.000 | active clock edge time | ||||
60.000 | 0.000 | clk | ||||
60.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
60.682 | 0.683 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
60.926 | 0.243 | tNET | RR | 1 | R18C78[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK |
60.891 | -0.035 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1 | |||
60.856 | -0.035 | tSu | 1 | R18C78[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1 |
Path Statistics:
Clock Skew | -1.221 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 1.365, 63.584%; route: 0.782, 36.416% |
Arrival Data Path Delay | cell: 2.019, 49.739%; route: 1.808, 44.545%; tC2Q: 0.232, 5.715% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path5
Path Summary:
Slack | 4.687 |
Data Arrival Time | 56.169 |
Data Required Time | 60.856 |
From | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_15_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | tck_pad_i | ||||
50.000 | 0.000 | tCL | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/I |
50.682 | 0.683 | tINS | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/O |
50.682 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
51.365 | 0.683 | tINS | RR | 323 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
52.147 | 0.782 | tNET | RR | 1 | R22C75[1][A] | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_15_s0/CLK |
52.379 | 0.232 | tC2Q | RF | 2 | R22C75[1][A] | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_15_s0/Q |
53.021 | 0.642 | tNET | FF | 1 | R18C75[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n514_s9/I3 |
53.570 | 0.549 | tINS | FR | 1 | R18C75[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n514_s9/F |
53.742 | 0.172 | tNET | RR | 1 | R18C76[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n514_s7/I0 |
54.297 | 0.555 | tINS | RF | 2 | R18C76[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n514_s7/F |
54.716 | 0.419 | tNET | FF | 1 | R17C77[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n514_s5/I0 |
55.169 | 0.453 | tINS | FF | 10 | R17C77[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n514_s5/F |
55.620 | 0.451 | tNET | FF | 1 | R14C77[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n514_s2/I2 |
56.169 | 0.549 | tINS | FR | 1 | R14C77[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n514_s2/F |
56.169 | 0.000 | tNET | RR | 1 | R14C77[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
60.000 | 60.000 | active clock edge time | ||||
60.000 | 0.000 | clk | ||||
60.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
60.682 | 0.683 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
60.926 | 0.243 | tNET | RR | 1 | R14C77[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK |
60.891 | -0.035 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1 | |||
60.856 | -0.035 | tSu | 1 | R14C77[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1 |
Path Statistics:
Clock Skew | -1.221 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 1.365, 63.584%; route: 0.782, 36.416% |
Arrival Data Path Delay | cell: 2.106, 52.356%; route: 1.684, 41.877%; tC2Q: 0.232, 5.768% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path6
Path Summary:
Slack | 4.698 |
Data Arrival Time | 56.158 |
Data Required Time | 60.856 |
From | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_15_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | tck_pad_i | ||||
50.000 | 0.000 | tCL | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/I |
50.682 | 0.683 | tINS | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/O |
50.682 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
51.365 | 0.683 | tINS | RR | 323 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
52.147 | 0.782 | tNET | RR | 1 | R22C75[1][A] | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_15_s0/CLK |
52.379 | 0.232 | tC2Q | RF | 2 | R22C75[1][A] | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_15_s0/Q |
53.021 | 0.642 | tNET | FF | 1 | R18C75[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n514_s9/I3 |
53.570 | 0.549 | tINS | FR | 1 | R18C75[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n514_s9/F |
53.742 | 0.172 | tNET | RR | 1 | R18C76[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n514_s7/I0 |
54.297 | 0.555 | tINS | RF | 2 | R18C76[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n514_s7/F |
54.716 | 0.419 | tNET | FF | 1 | R17C77[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n514_s5/I0 |
55.169 | 0.453 | tINS | FF | 10 | R17C77[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n514_s5/F |
55.609 | 0.440 | tNET | FF | 1 | R16C77[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n520_s1/I2 |
56.158 | 0.549 | tINS | FR | 1 | R16C77[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n520_s1/F |
56.158 | 0.000 | tNET | RR | 1 | R16C77[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
60.000 | 60.000 | active clock edge time | ||||
60.000 | 0.000 | clk | ||||
60.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
60.682 | 0.683 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
60.926 | 0.243 | tNET | RR | 1 | R16C77[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK |
60.891 | -0.035 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1 | |||
60.856 | -0.035 | tSu | 1 | R16C77[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1 |
Path Statistics:
Clock Skew | -1.221 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 1.365, 63.584%; route: 0.782, 36.416% |
Arrival Data Path Delay | cell: 2.106, 52.505%; route: 1.673, 41.711%; tC2Q: 0.232, 5.784% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path7
Path Summary:
Slack | 4.896 |
Data Arrival Time | 55.960 |
Data Required Time | 60.856 |
From | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_15_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | tck_pad_i | ||||
50.000 | 0.000 | tCL | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/I |
50.682 | 0.683 | tINS | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/O |
50.682 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
51.365 | 0.683 | tINS | RR | 323 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
52.147 | 0.782 | tNET | RR | 1 | R22C75[1][A] | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_15_s0/CLK |
52.379 | 0.232 | tC2Q | RF | 2 | R22C75[1][A] | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_15_s0/Q |
53.021 | 0.642 | tNET | FF | 1 | R18C75[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n514_s9/I3 |
53.570 | 0.549 | tINS | FR | 1 | R18C75[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n514_s9/F |
53.742 | 0.172 | tNET | RR | 1 | R18C76[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n514_s7/I0 |
54.297 | 0.555 | tINS | RF | 2 | R18C76[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n514_s7/F |
54.716 | 0.419 | tNET | FF | 1 | R17C77[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n514_s5/I0 |
55.169 | 0.453 | tINS | FF | 10 | R17C77[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n514_s5/F |
55.589 | 0.420 | tNET | FF | 1 | R15C77[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n515_s1/I3 |
55.960 | 0.371 | tINS | FF | 1 | R15C77[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n515_s1/F |
55.960 | 0.000 | tNET | FF | 1 | R15C77[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
60.000 | 60.000 | active clock edge time | ||||
60.000 | 0.000 | clk | ||||
60.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
60.682 | 0.683 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
60.926 | 0.243 | tNET | RR | 1 | R15C77[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK |
60.891 | -0.035 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1 | |||
60.856 | -0.035 | tSu | 1 | R15C77[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1 |
Path Statistics:
Clock Skew | -1.221 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 1.365, 63.584%; route: 0.782, 36.416% |
Arrival Data Path Delay | cell: 1.928, 50.557%; route: 1.653, 43.359%; tC2Q: 0.232, 6.084% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path8
Path Summary:
Slack | 4.941 |
Data Arrival Time | 55.915 |
Data Required Time | 60.856 |
From | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_15_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | tck_pad_i | ||||
50.000 | 0.000 | tCL | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/I |
50.682 | 0.683 | tINS | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/O |
50.682 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
51.365 | 0.683 | tINS | RR | 323 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
52.147 | 0.782 | tNET | RR | 1 | R22C75[1][A] | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_15_s0/CLK |
52.379 | 0.232 | tC2Q | RF | 2 | R22C75[1][A] | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_15_s0/Q |
53.021 | 0.642 | tNET | FF | 1 | R18C75[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n514_s9/I3 |
53.570 | 0.549 | tINS | FR | 1 | R18C75[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n514_s9/F |
53.742 | 0.172 | tNET | RR | 1 | R18C76[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n514_s7/I0 |
54.297 | 0.555 | tINS | RF | 2 | R18C76[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n514_s7/F |
54.716 | 0.419 | tNET | FF | 1 | R17C77[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n514_s5/I0 |
55.169 | 0.453 | tINS | FF | 10 | R17C77[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n514_s5/F |
55.366 | 0.197 | tNET | FF | 1 | R16C77[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n518_s1/I3 |
55.915 | 0.549 | tINS | FR | 1 | R16C77[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n518_s1/F |
55.915 | 0.000 | tNET | RR | 1 | R16C77[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
60.000 | 60.000 | active clock edge time | ||||
60.000 | 0.000 | clk | ||||
60.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
60.682 | 0.683 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
60.926 | 0.243 | tNET | RR | 1 | R16C77[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK |
60.891 | -0.035 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1 | |||
60.856 | -0.035 | tSu | 1 | R16C77[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1 |
Path Statistics:
Clock Skew | -1.221 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 1.365, 63.584%; route: 0.782, 36.416% |
Arrival Data Path Delay | cell: 2.106, 55.887%; route: 1.430, 37.956%; tC2Q: 0.232, 6.157% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path9
Path Summary:
Slack | 5.026 |
Data Arrival Time | 55.830 |
Data Required Time | 60.856 |
From | gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_15_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | tck_pad_i | ||||
50.000 | 0.000 | tCL | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/I |
50.682 | 0.683 | tINS | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/O |
50.682 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
51.365 | 0.683 | tINS | RR | 323 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
52.147 | 0.782 | tNET | RR | 1 | R22C73[2][B] | gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_15_s0/CLK |
52.379 | 0.232 | tC2Q | RF | 2 | R22C73[2][B] | gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_15_s0/Q |
52.794 | 0.415 | tNET | FF | 1 | R21C74[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s6/I3 |
53.349 | 0.555 | tINS | FF | 1 | R21C74[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s6/F |
53.762 | 0.413 | tNET | FF | 1 | R18C74[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s4/I0 |
54.279 | 0.517 | tINS | FF | 3 | R18C74[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s4/F |
54.779 | 0.500 | tNET | FF | 1 | R18C78[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s5/I1 |
55.106 | 0.327 | tINS | FR | 1 | R18C78[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s5/F |
55.830 | 0.724 | tNET | RR | 1 | R18C78[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
60.000 | 60.000 | active clock edge time | ||||
60.000 | 0.000 | clk | ||||
60.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
60.682 | 0.683 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
60.926 | 0.243 | tNET | RR | 1 | R18C78[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLK |
60.891 | -0.035 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1 | |||
60.856 | -0.035 | tSu | 1 | R18C78[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1 |
Path Statistics:
Clock Skew | -1.221 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 1.365, 63.584%; route: 0.782, 36.416% |
Arrival Data Path Delay | cell: 1.399, 37.986%; route: 2.052, 55.715%; tC2Q: 0.232, 6.299% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path10
Path Summary:
Slack | 5.095 |
Data Arrival Time | 55.761 |
Data Required Time | 60.856 |
From | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_15_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | tck_pad_i | ||||
50.000 | 0.000 | tCL | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/I |
50.682 | 0.683 | tINS | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/O |
50.682 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
51.365 | 0.683 | tINS | RR | 323 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
52.147 | 0.782 | tNET | RR | 1 | R22C75[1][A] | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_15_s0/CLK |
52.379 | 0.232 | tC2Q | RF | 2 | R22C75[1][A] | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_15_s0/Q |
53.021 | 0.642 | tNET | FF | 1 | R18C75[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n514_s9/I3 |
53.570 | 0.549 | tINS | FR | 1 | R18C75[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n514_s9/F |
53.742 | 0.172 | tNET | RR | 1 | R18C76[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n514_s7/I0 |
54.297 | 0.555 | tINS | RF | 2 | R18C76[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n514_s7/F |
54.716 | 0.419 | tNET | FF | 1 | R17C77[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n514_s5/I0 |
55.169 | 0.453 | tINS | FF | 10 | R17C77[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n514_s5/F |
55.191 | 0.022 | tNET | FF | 1 | R17C77[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n519_s1/I2 |
55.761 | 0.570 | tINS | FR | 1 | R17C77[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n519_s1/F |
55.761 | 0.000 | tNET | RR | 1 | R17C77[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
60.000 | 60.000 | active clock edge time | ||||
60.000 | 0.000 | clk | ||||
60.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
60.682 | 0.683 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
60.926 | 0.243 | tNET | RR | 1 | R17C77[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK |
60.891 | -0.035 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1 | |||
60.856 | -0.035 | tSu | 1 | R17C77[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1 |
Path Statistics:
Clock Skew | -1.221 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 1.365, 63.584%; route: 0.782, 36.416% |
Arrival Data Path Delay | cell: 2.127, 58.851%; route: 1.255, 34.730%; tC2Q: 0.232, 6.419% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path11
Path Summary:
Slack | 5.095 |
Data Arrival Time | 55.761 |
Data Required Time | 60.856 |
From | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_15_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | tck_pad_i | ||||
50.000 | 0.000 | tCL | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/I |
50.682 | 0.683 | tINS | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/O |
50.682 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
51.365 | 0.683 | tINS | RR | 323 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
52.147 | 0.782 | tNET | RR | 1 | R22C75[1][A] | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_15_s0/CLK |
52.379 | 0.232 | tC2Q | RF | 2 | R22C75[1][A] | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_15_s0/Q |
53.021 | 0.642 | tNET | FF | 1 | R18C75[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n514_s9/I3 |
53.570 | 0.549 | tINS | FR | 1 | R18C75[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n514_s9/F |
53.742 | 0.172 | tNET | RR | 1 | R18C76[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n514_s7/I0 |
54.297 | 0.555 | tINS | RF | 2 | R18C76[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n514_s7/F |
54.716 | 0.419 | tNET | FF | 1 | R17C77[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n514_s5/I0 |
55.169 | 0.453 | tINS | FF | 10 | R17C77[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n514_s5/F |
55.191 | 0.022 | tNET | FF | 1 | R17C77[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n517_s1/I2 |
55.761 | 0.570 | tINS | FR | 1 | R17C77[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n517_s1/F |
55.761 | 0.000 | tNET | RR | 1 | R17C77[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
60.000 | 60.000 | active clock edge time | ||||
60.000 | 0.000 | clk | ||||
60.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
60.682 | 0.683 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
60.926 | 0.243 | tNET | RR | 1 | R17C77[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK |
60.891 | -0.035 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1 | |||
60.856 | -0.035 | tSu | 1 | R17C77[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1 |
Path Statistics:
Clock Skew | -1.221 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 1.365, 63.584%; route: 0.782, 36.416% |
Arrival Data Path Delay | cell: 2.127, 58.851%; route: 1.255, 34.730%; tC2Q: 0.232, 6.419% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path12
Path Summary:
Slack | 5.258 |
Data Arrival Time | 55.598 |
Data Required Time | 60.856 |
From | gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_2_s0 |
To | gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | tck_pad_i | ||||
50.000 | 0.000 | tCL | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/I |
50.682 | 0.683 | tINS | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/O |
50.682 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
51.365 | 0.683 | tINS | RR | 323 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
52.147 | 0.782 | tNET | RR | 1 | R22C78[2][A] | gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_2_s0/CLK |
52.379 | 0.232 | tC2Q | RF | 2 | R22C78[2][A] | gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_2_s0/Q |
53.021 | 0.642 | tNET | FF | 1 | R26C78[1][B] | gw_gao_inst_0/u_la0_top/n2919_s0/I1 |
53.591 | 0.570 | tINS | FR | 1 | R26C78[1][B] | gw_gao_inst_0/u_la0_top/n2919_s0/COUT |
53.591 | 0.000 | tNET | RR | 1 | R26C78[2][A] | gw_gao_inst_0/u_la0_top/n2920_s0/CIN |
53.626 | 0.035 | tINS | RF | 5 | R26C78[2][A] | gw_gao_inst_0/u_la0_top/n2920_s0/COUT |
54.284 | 0.658 | tNET | FF | 1 | R25C78[3][A] | gw_gao_inst_0/u_la0_top/n2942_s2/I1 |
54.854 | 0.570 | tINS | FR | 2 | R25C78[3][A] | gw_gao_inst_0/u_la0_top/n2942_s2/F |
55.028 | 0.174 | tNET | RR | 1 | R25C77[1][A] | gw_gao_inst_0/u_la0_top/n2939_s1/I3 |
55.598 | 0.570 | tINS | RR | 1 | R25C77[1][A] | gw_gao_inst_0/u_la0_top/n2939_s1/F |
55.598 | 0.000 | tNET | RR | 1 | R25C77[1][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
60.000 | 60.000 | active clock edge time | ||||
60.000 | 0.000 | clk | ||||
60.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
60.682 | 0.683 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
60.926 | 0.243 | tNET | RR | 1 | R25C77[1][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLK |
60.891 | -0.035 | tUnc | gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1 | |||
60.856 | -0.035 | tSu | 1 | R25C77[1][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1 |
Path Statistics:
Clock Skew | -1.221 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 1.365, 63.584%; route: 0.782, 36.416% |
Arrival Data Path Delay | cell: 1.745, 50.573%; route: 1.474, 42.704%; tC2Q: 0.232, 6.723% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path13
Path Summary:
Slack | 5.264 |
Data Arrival Time | 55.592 |
Data Required Time | 60.856 |
From | gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_15_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | tck_pad_i | ||||
50.000 | 0.000 | tCL | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/I |
50.682 | 0.683 | tINS | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/O |
50.682 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
51.365 | 0.683 | tINS | RR | 323 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
52.147 | 0.782 | tNET | RR | 1 | R22C73[2][B] | gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_15_s0/CLK |
52.379 | 0.232 | tC2Q | RF | 2 | R22C73[2][B] | gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_15_s0/Q |
52.794 | 0.415 | tNET | FF | 1 | R21C74[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s6/I3 |
53.349 | 0.555 | tINS | FF | 1 | R21C74[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s6/F |
53.762 | 0.413 | tNET | FF | 1 | R18C74[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s4/I0 |
54.279 | 0.517 | tINS | FF | 3 | R18C74[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s4/F |
54.802 | 0.522 | tNET | FF | 1 | R17C78[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s3/I0 |
55.264 | 0.462 | tINS | FR | 1 | R17C78[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s3/F |
55.592 | 0.328 | tNET | RR | 1 | R17C79[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
60.000 | 60.000 | active clock edge time | ||||
60.000 | 0.000 | clk | ||||
60.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
60.682 | 0.683 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
60.926 | 0.243 | tNET | RR | 1 | R17C79[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK |
60.891 | -0.035 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1 | |||
60.856 | -0.035 | tSu | 1 | R17C79[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1 |
Path Statistics:
Clock Skew | -1.221 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 1.365, 63.584%; route: 0.782, 36.416% |
Arrival Data Path Delay | cell: 1.534, 44.531%; route: 1.679, 48.734%; tC2Q: 0.232, 6.735% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path14
Path Summary:
Slack | 5.311 |
Data Arrival Time | 55.545 |
Data Required Time | 60.856 |
From | gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_2_s0 |
To | gw_gao_inst_0/u_la0_top/trigger_seq_start_s1 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | tck_pad_i | ||||
50.000 | 0.000 | tCL | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/I |
50.682 | 0.683 | tINS | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/O |
50.682 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
51.365 | 0.683 | tINS | RR | 323 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
52.147 | 0.782 | tNET | RR | 1 | R22C78[2][A] | gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_2_s0/CLK |
52.379 | 0.232 | tC2Q | RF | 2 | R22C78[2][A] | gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_2_s0/Q |
53.021 | 0.642 | tNET | FF | 1 | R26C78[1][B] | gw_gao_inst_0/u_la0_top/n2919_s0/I1 |
53.591 | 0.570 | tINS | FR | 1 | R26C78[1][B] | gw_gao_inst_0/u_la0_top/n2919_s0/COUT |
53.591 | 0.000 | tNET | RR | 1 | R26C78[2][A] | gw_gao_inst_0/u_la0_top/n2920_s0/CIN |
53.626 | 0.035 | tINS | RF | 5 | R26C78[2][A] | gw_gao_inst_0/u_la0_top/n2920_s0/COUT |
54.118 | 0.492 | tNET | FF | 1 | R26C78[3][B] | gw_gao_inst_0/u_la0_top/n2961_s1/I0 |
54.667 | 0.549 | tINS | FR | 1 | R26C78[3][B] | gw_gao_inst_0/u_la0_top/n2961_s1/F |
54.668 | 0.001 | tNET | RR | 1 | R26C78[3][A] | gw_gao_inst_0/u_la0_top/trigger_seq_start_s3/I3 |
55.217 | 0.549 | tINS | RR | 1 | R26C78[3][A] | gw_gao_inst_0/u_la0_top/trigger_seq_start_s3/F |
55.545 | 0.328 | tNET | RR | 1 | R26C79[2][A] | gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
60.000 | 60.000 | active clock edge time | ||||
60.000 | 0.000 | clk | ||||
60.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
60.682 | 0.683 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
60.926 | 0.243 | tNET | RR | 1 | R26C79[2][A] | gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLK |
60.891 | -0.035 | tUnc | gw_gao_inst_0/u_la0_top/trigger_seq_start_s1 | |||
60.856 | -0.035 | tSu | 1 | R26C79[2][A] | gw_gao_inst_0/u_la0_top/trigger_seq_start_s1 |
Path Statistics:
Clock Skew | -1.221 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 1.365, 63.584%; route: 0.782, 36.416% |
Arrival Data Path Delay | cell: 1.703, 50.121%; route: 1.463, 43.052%; tC2Q: 0.232, 6.827% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path15
Path Summary:
Slack | 5.537 |
Data Arrival Time | 55.318 |
Data Required Time | 60.856 |
From | gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_2_s0 |
To | gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | tck_pad_i | ||||
50.000 | 0.000 | tCL | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/I |
50.682 | 0.683 | tINS | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/O |
50.682 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
51.365 | 0.683 | tINS | RR | 323 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
52.147 | 0.782 | tNET | RR | 1 | R22C78[2][A] | gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_2_s0/CLK |
52.379 | 0.232 | tC2Q | RF | 2 | R22C78[2][A] | gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_2_s0/Q |
53.021 | 0.642 | tNET | FF | 1 | R26C78[1][B] | gw_gao_inst_0/u_la0_top/n2919_s0/I1 |
53.591 | 0.570 | tINS | FR | 1 | R26C78[1][B] | gw_gao_inst_0/u_la0_top/n2919_s0/COUT |
53.591 | 0.000 | tNET | RR | 1 | R26C78[2][A] | gw_gao_inst_0/u_la0_top/n2920_s0/CIN |
53.626 | 0.035 | tINS | RF | 5 | R26C78[2][A] | gw_gao_inst_0/u_la0_top/n2920_s0/COUT |
54.284 | 0.658 | tNET | FF | 1 | R25C78[3][A] | gw_gao_inst_0/u_la0_top/n2942_s2/I1 |
54.854 | 0.570 | tINS | FR | 2 | R25C78[3][A] | gw_gao_inst_0/u_la0_top/n2942_s2/F |
54.856 | 0.003 | tNET | RR | 1 | R25C78[2][A] | gw_gao_inst_0/u_la0_top/n2940_s3/I3 |
55.318 | 0.462 | tINS | RR | 1 | R25C78[2][A] | gw_gao_inst_0/u_la0_top/n2940_s3/F |
55.318 | 0.000 | tNET | RR | 1 | R25C78[2][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
60.000 | 60.000 | active clock edge time | ||||
60.000 | 0.000 | clk | ||||
60.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
60.682 | 0.683 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
60.926 | 0.243 | tNET | RR | 1 | R25C78[2][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLK |
60.891 | -0.035 | tUnc | gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1 | |||
60.856 | -0.035 | tSu | 1 | R25C78[2][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1 |
Path Statistics:
Clock Skew | -1.221 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 1.365, 63.584%; route: 0.782, 36.416% |
Arrival Data Path Delay | cell: 1.637, 51.619%; route: 1.303, 41.067%; tC2Q: 0.232, 7.315% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path16
Path Summary:
Slack | 5.678 |
Data Arrival Time | 55.178 |
Data Required Time | 60.856 |
From | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_15_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | tck_pad_i | ||||
50.000 | 0.000 | tCL | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/I |
50.682 | 0.683 | tINS | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/O |
50.682 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
51.365 | 0.683 | tINS | RR | 323 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
52.147 | 0.782 | tNET | RR | 1 | R22C75[1][A] | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_15_s0/CLK |
52.379 | 0.232 | tC2Q | RF | 2 | R22C75[1][A] | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_15_s0/Q |
53.021 | 0.642 | tNET | FF | 1 | R18C75[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n514_s9/I3 |
53.570 | 0.549 | tINS | FR | 1 | R18C75[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n514_s9/F |
53.742 | 0.172 | tNET | RR | 1 | R18C76[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n514_s7/I0 |
54.297 | 0.555 | tINS | RF | 2 | R18C76[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n514_s7/F |
54.716 | 0.419 | tNET | FF | 1 | R17C77[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n523_s2/I1 |
55.178 | 0.462 | tINS | FR | 1 | R17C77[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n523_s2/F |
55.178 | 0.000 | tNET | RR | 1 | R17C77[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
60.000 | 60.000 | active clock edge time | ||||
60.000 | 0.000 | clk | ||||
60.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
60.682 | 0.683 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
60.926 | 0.243 | tNET | RR | 1 | R17C77[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLK |
60.891 | -0.035 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1 | |||
60.856 | -0.035 | tSu | 1 | R17C77[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1 |
Path Statistics:
Clock Skew | -1.221 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 1.365, 63.584%; route: 0.782, 36.416% |
Arrival Data Path Delay | cell: 1.566, 51.662%; route: 1.233, 40.685%; tC2Q: 0.232, 7.654% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path17
Path Summary:
Slack | 5.706 |
Data Arrival Time | 55.150 |
Data Required Time | 60.856 |
From | gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_15_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | tck_pad_i | ||||
50.000 | 0.000 | tCL | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/I |
50.682 | 0.683 | tINS | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/O |
50.682 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
51.365 | 0.683 | tINS | RR | 323 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
52.147 | 0.782 | tNET | RR | 1 | R22C73[2][B] | gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_15_s0/CLK |
52.379 | 0.232 | tC2Q | RF | 2 | R22C73[2][B] | gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_15_s0/Q |
52.794 | 0.415 | tNET | FF | 1 | R21C74[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s6/I3 |
53.349 | 0.555 | tINS | FF | 1 | R21C74[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s6/F |
53.762 | 0.413 | tNET | FF | 1 | R18C74[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s4/I0 |
54.279 | 0.517 | tINS | FF | 3 | R18C74[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s4/F |
54.779 | 0.500 | tNET | FF | 1 | R18C78[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n414_s3/I1 |
55.150 | 0.371 | tINS | FF | 1 | R18C78[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n414_s3/F |
55.150 | 0.000 | tNET | FF | 1 | R18C78[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
60.000 | 60.000 | active clock edge time | ||||
60.000 | 0.000 | clk | ||||
60.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
60.682 | 0.683 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
60.926 | 0.243 | tNET | RR | 1 | R18C78[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLK |
60.891 | -0.035 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1 | |||
60.856 | -0.035 | tSu | 1 | R18C78[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1 |
Path Statistics:
Clock Skew | -1.221 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 1.365, 63.584%; route: 0.782, 36.416% |
Arrival Data Path Delay | cell: 1.443, 48.045%; route: 1.328, 44.231%; tC2Q: 0.232, 7.724% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path18
Path Summary:
Slack | 5.776 |
Data Arrival Time | 55.080 |
Data Required Time | 60.856 |
From | gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_2_s0 |
To | gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | tck_pad_i | ||||
50.000 | 0.000 | tCL | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/I |
50.682 | 0.683 | tINS | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/O |
50.682 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
51.365 | 0.683 | tINS | RR | 323 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
52.147 | 0.782 | tNET | RR | 1 | R22C78[2][A] | gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_2_s0/CLK |
52.379 | 0.232 | tC2Q | RF | 2 | R22C78[2][A] | gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_2_s0/Q |
53.021 | 0.642 | tNET | FF | 1 | R26C78[1][B] | gw_gao_inst_0/u_la0_top/n2919_s0/I1 |
53.591 | 0.570 | tINS | FR | 1 | R26C78[1][B] | gw_gao_inst_0/u_la0_top/n2919_s0/COUT |
53.591 | 0.000 | tNET | RR | 1 | R26C78[2][A] | gw_gao_inst_0/u_la0_top/n2920_s0/CIN |
53.626 | 0.035 | tINS | RF | 5 | R26C78[2][A] | gw_gao_inst_0/u_la0_top/n2920_s0/COUT |
54.510 | 0.885 | tNET | FF | 1 | R26C76[1][A] | gw_gao_inst_0/u_la0_top/n2942_s5/I2 |
55.080 | 0.570 | tINS | FR | 1 | R26C76[1][A] | gw_gao_inst_0/u_la0_top/n2942_s5/F |
55.080 | 0.000 | tNET | RR | 1 | R26C76[1][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
60.000 | 60.000 | active clock edge time | ||||
60.000 | 0.000 | clk | ||||
60.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
60.682 | 0.683 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
60.926 | 0.243 | tNET | RR | 1 | R26C76[1][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLK |
60.891 | -0.035 | tUnc | gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3 | |||
60.856 | -0.035 | tSu | 1 | R26C76[1][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3 |
Path Statistics:
Clock Skew | -1.221 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 1.365, 63.584%; route: 0.782, 36.416% |
Arrival Data Path Delay | cell: 1.175, 40.060%; route: 1.526, 52.031%; tC2Q: 0.232, 7.908% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path19
Path Summary:
Slack | 5.925 |
Data Arrival Time | 54.930 |
Data Required Time | 60.856 |
From | gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_2_s0 |
To | gw_gao_inst_0/u_la0_top/triger_s0 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | tck_pad_i | ||||
50.000 | 0.000 | tCL | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/I |
50.682 | 0.683 | tINS | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/O |
50.682 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
51.365 | 0.683 | tINS | RR | 323 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
52.147 | 0.782 | tNET | RR | 1 | R22C78[2][A] | gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_2_s0/CLK |
52.379 | 0.232 | tC2Q | RF | 2 | R22C78[2][A] | gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_2_s0/Q |
53.021 | 0.642 | tNET | FF | 1 | R26C78[1][B] | gw_gao_inst_0/u_la0_top/n2919_s0/I1 |
53.591 | 0.570 | tINS | FR | 1 | R26C78[1][B] | gw_gao_inst_0/u_la0_top/n2919_s0/COUT |
53.591 | 0.000 | tNET | RR | 1 | R26C78[2][A] | gw_gao_inst_0/u_la0_top/n2920_s0/CIN |
53.626 | 0.035 | tINS | RF | 5 | R26C78[2][A] | gw_gao_inst_0/u_la0_top/n2920_s0/COUT |
54.360 | 0.735 | tNET | FF | 1 | R24C78[2][A] | gw_gao_inst_0/u_la0_top/n2961_s2/I1 |
54.930 | 0.570 | tINS | FR | 1 | R24C78[2][A] | gw_gao_inst_0/u_la0_top/n2961_s2/F |
54.930 | 0.000 | tNET | RR | 1 | R24C78[2][A] | gw_gao_inst_0/u_la0_top/triger_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
60.000 | 60.000 | active clock edge time | ||||
60.000 | 0.000 | clk | ||||
60.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
60.682 | 0.683 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
60.926 | 0.243 | tNET | RR | 1 | R24C78[2][A] | gw_gao_inst_0/u_la0_top/triger_s0/CLK |
60.891 | -0.035 | tUnc | gw_gao_inst_0/u_la0_top/triger_s0 | |||
60.856 | -0.035 | tSu | 1 | R24C78[2][A] | gw_gao_inst_0/u_la0_top/triger_s0 |
Path Statistics:
Clock Skew | -1.221 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 1.365, 63.584%; route: 0.782, 36.416% |
Arrival Data Path Delay | cell: 1.175, 42.217%; route: 1.377, 49.449%; tC2Q: 0.232, 8.334% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path20
Path Summary:
Slack | 5.936 |
Data Arrival Time | 54.920 |
Data Required Time | 60.856 |
From | gw_gao_inst_0/u_la0_top/capture_windows_num_0_s0 |
To | gw_gao_inst_0/u_la0_top/start_reg_s0 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | tck_pad_i | ||||
50.000 | 0.000 | tCL | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/I |
50.682 | 0.683 | tINS | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/O |
50.682 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
51.365 | 0.683 | tINS | RR | 323 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
52.147 | 0.782 | tNET | RR | 1 | R22C74[2][A] | gw_gao_inst_0/u_la0_top/capture_windows_num_0_s0/CLK |
52.379 | 0.232 | tC2Q | RF | 4 | R22C74[2][A] | gw_gao_inst_0/u_la0_top/capture_windows_num_0_s0/Q |
53.803 | 1.424 | tNET | FF | 1 | R25C78[0][A] | gw_gao_inst_0/u_la0_top/n2891_s8/CIN |
53.838 | 0.035 | tINS | FF | 1 | R25C78[0][A] | gw_gao_inst_0/u_la0_top/n2891_s8/COUT |
53.838 | 0.000 | tNET | FF | 1 | R25C78[0][B] | gw_gao_inst_0/u_la0_top/n2891_s9/CIN |
53.873 | 0.035 | tINS | FF | 1 | R25C78[0][B] | gw_gao_inst_0/u_la0_top/n2891_s9/COUT |
53.873 | 0.000 | tNET | FF | 1 | R25C78[1][A] | gw_gao_inst_0/u_la0_top/n2891_s10/CIN |
53.909 | 0.035 | tINS | FF | 1 | R25C78[1][A] | gw_gao_inst_0/u_la0_top/n2891_s10/COUT |
54.549 | 0.640 | tNET | FF | 1 | R24C78[2][B] | gw_gao_inst_0/u_la0_top/start_reg1_s0/I3 |
54.920 | 0.371 | tINS | FF | 1 | R24C78[2][B] | gw_gao_inst_0/u_la0_top/start_reg1_s0/F |
54.920 | 0.000 | tNET | FF | 1 | R24C78[2][B] | gw_gao_inst_0/u_la0_top/start_reg_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
60.000 | 60.000 | active clock edge time | ||||
60.000 | 0.000 | clk | ||||
60.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
60.682 | 0.683 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
60.926 | 0.243 | tNET | RR | 1 | R24C78[2][B] | gw_gao_inst_0/u_la0_top/start_reg_s0/CLK |
60.891 | -0.035 | tUnc | gw_gao_inst_0/u_la0_top/start_reg_s0 | |||
60.856 | -0.035 | tSu | 1 | R24C78[2][B] | gw_gao_inst_0/u_la0_top/start_reg_s0 |
Path Statistics:
Clock Skew | -1.221 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 1.365, 63.584%; route: 0.782, 36.416% |
Arrival Data Path Delay | cell: 0.477, 17.185%; route: 2.065, 74.450%; tC2Q: 0.232, 8.365% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path21
Path Summary:
Slack | 6.023 |
Data Arrival Time | 54.833 |
Data Required Time | 60.856 |
From | gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_2_s0 |
To | gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | tck_pad_i | ||||
50.000 | 0.000 | tCL | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/I |
50.682 | 0.683 | tINS | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/O |
50.682 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
51.365 | 0.683 | tINS | RR | 323 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
52.147 | 0.782 | tNET | RR | 1 | R22C78[2][A] | gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_2_s0/CLK |
52.379 | 0.232 | tC2Q | RF | 2 | R22C78[2][A] | gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_2_s0/Q |
53.021 | 0.642 | tNET | FF | 1 | R26C78[1][B] | gw_gao_inst_0/u_la0_top/n2919_s0/I1 |
53.591 | 0.570 | tINS | FR | 1 | R26C78[1][B] | gw_gao_inst_0/u_la0_top/n2919_s0/COUT |
53.591 | 0.000 | tNET | RR | 1 | R26C78[2][A] | gw_gao_inst_0/u_la0_top/n2920_s0/CIN |
53.626 | 0.035 | tINS | RF | 5 | R26C78[2][A] | gw_gao_inst_0/u_la0_top/n2920_s0/COUT |
54.284 | 0.658 | tNET | FF | 1 | R26C77[2][A] | gw_gao_inst_0/u_la0_top/n2941_s2/I3 |
54.833 | 0.549 | tINS | FR | 1 | R26C77[2][A] | gw_gao_inst_0/u_la0_top/n2941_s2/F |
54.833 | 0.000 | tNET | RR | 1 | R26C77[2][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
60.000 | 60.000 | active clock edge time | ||||
60.000 | 0.000 | clk | ||||
60.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
60.682 | 0.683 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
60.926 | 0.243 | tNET | RR | 1 | R26C77[2][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLK |
60.891 | -0.035 | tUnc | gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1 | |||
60.856 | -0.035 | tSu | 1 | R26C77[2][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1 |
Path Statistics:
Clock Skew | -1.221 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 1.365, 63.584%; route: 0.782, 36.416% |
Arrival Data Path Delay | cell: 1.154, 42.970%; route: 1.300, 48.393%; tC2Q: 0.232, 8.637% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path22
Path Summary:
Slack | 6.846 |
Data Arrival Time | 54.010 |
Data Required Time | 60.856 |
From | gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_9_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | tck_pad_i | ||||
50.000 | 0.000 | tCL | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/I |
50.682 | 0.683 | tINS | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/O |
50.682 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
51.365 | 0.683 | tINS | RR | 323 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
52.147 | 0.782 | tNET | RR | 1 | R20C73[2][A] | gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_9_s0/CLK |
52.379 | 0.232 | tC2Q | RF | 3 | R20C73[2][A] | gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_9_s0/Q |
53.461 | 1.082 | tNET | FF | 1 | R17C78[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n430_s3/I1 |
54.010 | 0.549 | tINS | FR | 1 | R17C78[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n430_s3/F |
54.010 | 0.000 | tNET | RR | 1 | R17C78[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
60.000 | 60.000 | active clock edge time | ||||
60.000 | 0.000 | clk | ||||
60.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
60.682 | 0.683 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
60.926 | 0.243 | tNET | RR | 1 | R17C78[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLK |
60.891 | -0.035 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1 | |||
60.856 | -0.035 | tSu | 1 | R17C78[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1 |
Path Statistics:
Clock Skew | -1.221 |
Setup Relationship | 10.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.365, 63.584%; route: 0.782, 36.416% |
Arrival Data Path Delay | cell: 0.549, 29.467%; route: 1.082, 58.080%; tC2Q: 0.232, 12.453% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path23
Path Summary:
Slack | 6.941 |
Data Arrival Time | 53.915 |
Data Required Time | 60.856 |
From | gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_5_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | tck_pad_i | ||||
50.000 | 0.000 | tCL | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/I |
50.682 | 0.683 | tINS | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/O |
50.682 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
51.365 | 0.683 | tINS | RR | 323 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
52.147 | 0.782 | tNET | RR | 1 | R22C73[1][A] | gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_5_s0/CLK |
52.379 | 0.232 | tC2Q | RF | 3 | R22C73[1][A] | gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_5_s0/Q |
53.345 | 0.966 | tNET | FF | 1 | R13C78[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n434_s0/I0 |
53.915 | 0.570 | tINS | FR | 1 | R13C78[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n434_s0/F |
53.915 | 0.000 | tNET | RR | 1 | R13C78[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
60.000 | 60.000 | active clock edge time | ||||
60.000 | 0.000 | clk | ||||
60.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
60.682 | 0.683 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
60.926 | 0.243 | tNET | RR | 1 | R13C78[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLK |
60.891 | -0.035 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1 | |||
60.856 | -0.035 | tSu | 1 | R13C78[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1 |
Path Statistics:
Clock Skew | -1.221 |
Setup Relationship | 10.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.365, 63.584%; route: 0.782, 36.416% |
Arrival Data Path Delay | cell: 0.570, 32.237%; route: 0.966, 54.642%; tC2Q: 0.232, 13.121% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path24
Path Summary:
Slack | 6.978 |
Data Arrival Time | 53.878 |
Data Required Time | 60.856 |
From | gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_6_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | tck_pad_i | ||||
50.000 | 0.000 | tCL | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/I |
50.682 | 0.683 | tINS | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/O |
50.682 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
51.365 | 0.683 | tINS | RR | 323 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
52.147 | 0.782 | tNET | RR | 1 | R22C73[1][B] | gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_6_s0/CLK |
52.379 | 0.232 | tC2Q | RF | 3 | R22C73[1][B] | gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_6_s0/Q |
53.416 | 1.037 | tNET | FF | 1 | R17C78[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n433_s2/I1 |
53.878 | 0.462 | tINS | FR | 1 | R17C78[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n433_s2/F |
53.878 | 0.000 | tNET | RR | 1 | R17C78[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
60.000 | 60.000 | active clock edge time | ||||
60.000 | 0.000 | clk | ||||
60.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
60.682 | 0.683 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
60.926 | 0.243 | tNET | RR | 1 | R17C78[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLK |
60.891 | -0.035 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1 | |||
60.856 | -0.035 | tSu | 1 | R17C78[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1 |
Path Statistics:
Clock Skew | -1.221 |
Setup Relationship | 10.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.365, 63.584%; route: 0.782, 36.416% |
Arrival Data Path Delay | cell: 0.462, 26.689%; route: 1.037, 59.909%; tC2Q: 0.232, 13.402% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path25
Path Summary:
Slack | 7.046 |
Data Arrival Time | 53.810 |
Data Required Time | 60.856 |
From | gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_3_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | tck_pad_i | ||||
50.000 | 0.000 | tCL | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/I |
50.682 | 0.683 | tINS | RR | 1 | IOR43[A] | gw_gao_inst_0/tck_ibuf/O |
50.682 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
51.365 | 0.683 | tINS | RR | 323 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
52.147 | 0.782 | tNET | RR | 1 | R22C75[0][B] | gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_3_s0/CLK |
52.379 | 0.232 | tC2Q | RF | 3 | R22C75[0][B] | gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_3_s0/Q |
53.240 | 0.861 | tNET | FF | 1 | R13C78[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n436_s0/I0 |
53.810 | 0.570 | tINS | FR | 1 | R13C78[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n436_s0/F |
53.810 | 0.000 | tNET | RR | 1 | R13C78[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
60.000 | 60.000 | active clock edge time | ||||
60.000 | 0.000 | clk | ||||
60.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
60.682 | 0.683 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
60.926 | 0.243 | tNET | RR | 1 | R13C78[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/CLK |
60.891 | -0.035 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1 | |||
60.856 | -0.035 | tSu | 1 | R13C78[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1 |
Path Statistics:
Clock Skew | -1.221 |
Setup Relationship | 10.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.365, 63.584%; route: 0.782, 36.416% |
Arrival Data Path Delay | cell: 0.570, 34.269%; route: 0.861, 51.783%; tC2Q: 0.232, 13.948% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Hold Analysis Report
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 0.190 |
Data Arrival Time | 1.062 |
Data Required Time | 0.872 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R17C79[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK |
1.062 | 0.202 | tC2Q | RR | 12 | R17C79[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q |
1.062 | 0.000 | tNET | RR | 1 | BSRAM_R10[26] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CEA |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | BSRAM_R10[26] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CLKA |
0.872 | 0.012 | tHld | 1 | BSRAM_R10[26] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.202, 100.000% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path2
Path Summary:
Slack | 0.190 |
Data Arrival Time | 1.062 |
Data Required Time | 0.872 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R17C79[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK |
1.062 | 0.202 | tC2Q | RR | 12 | R17C79[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q |
1.062 | 0.000 | tNET | RR | 1 | BSRAM_R10[25] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CEA |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | BSRAM_R10[25] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA |
0.872 | 0.012 | tHld | 1 | BSRAM_R10[25] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.202, 100.000% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path3
Path Summary:
Slack | 0.190 |
Data Arrival Time | 1.062 |
Data Required Time | 0.872 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R17C79[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK |
1.062 | 0.202 | tC2Q | RR | 12 | R17C79[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q |
1.062 | 0.000 | tNET | RR | 1 | BSRAM_R10[24] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CEA |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | BSRAM_R10[24] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA |
0.872 | 0.012 | tHld | 1 | BSRAM_R10[24] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.202, 100.000% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path4
Path Summary:
Slack | 0.190 |
Data Arrival Time | 1.062 |
Data Required Time | 0.872 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R17C79[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK |
1.062 | 0.202 | tC2Q | RR | 12 | R17C79[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q |
1.062 | 0.000 | tNET | RR | 1 | BSRAM_R10[23] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CEA |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | BSRAM_R10[23] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA |
0.872 | 0.012 | tHld | 1 | BSRAM_R10[23] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.202, 100.000% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path5
Path Summary:
Slack | 0.190 |
Data Arrival Time | 1.062 |
Data Required Time | 0.872 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R17C79[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK |
1.062 | 0.202 | tC2Q | RR | 12 | R17C79[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q |
1.062 | 0.000 | tNET | RR | 1 | BSRAM_R10[22] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CEA |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | BSRAM_R10[22] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA |
0.872 | 0.012 | tHld | 1 | BSRAM_R10[22] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.202, 100.000% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path6
Path Summary:
Slack | 0.213 |
Data Arrival Time | 1.322 |
Data Required Time | 1.109 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_44_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R11C76[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_44_s0/CLK |
1.062 | 0.202 | tC2Q | RR | 1 | R11C76[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_44_s0/Q |
1.322 | 0.260 | tNET | RR | 1 | BSRAM_R10[24] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[12] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | BSRAM_R10[24] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA |
1.109 | 0.249 | tHld | 1 | BSRAM_R10[24] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path7
Path Summary:
Slack | 0.213 |
Data Arrival Time | 1.322 |
Data Required Time | 1.109 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_28_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R12C74[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_28_s0/CLK |
1.062 | 0.202 | tC2Q | RR | 1 | R12C74[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_28_s0/Q |
1.322 | 0.260 | tNET | RR | 1 | BSRAM_R10[23] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[12] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | BSRAM_R10[23] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA |
1.109 | 0.249 | tHld | 1 | BSRAM_R10[23] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path8
Path Summary:
Slack | 0.213 |
Data Arrival Time | 1.322 |
Data Required Time | 1.109 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_27_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R12C74[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_27_s0/CLK |
1.062 | 0.202 | tC2Q | RR | 1 | R12C74[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_27_s0/Q |
1.322 | 0.260 | tNET | RR | 1 | BSRAM_R10[23] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[11] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | BSRAM_R10[23] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA |
1.109 | 0.249 | tHld | 1 | BSRAM_R10[23] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path9
Path Summary:
Slack | 0.225 |
Data Arrival Time | 1.334 |
Data Required Time | 1.109 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_57_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R11C73[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_57_s0/CLK |
1.062 | 0.202 | tC2Q | RR | 1 | R11C73[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_57_s0/Q |
1.334 | 0.272 | tNET | RR | 1 | BSRAM_R10[25] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[9] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | BSRAM_R10[25] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA |
1.109 | 0.249 | tHld | 1 | BSRAM_R10[25] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.272, 57.427%; tC2Q: 0.202, 42.573% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path10
Path Summary:
Slack | 0.225 |
Data Arrival Time | 1.334 |
Data Required Time | 1.109 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_26_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R18C73[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_26_s0/CLK |
1.062 | 0.202 | tC2Q | RR | 1 | R18C73[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_26_s0/Q |
1.334 | 0.272 | tNET | RR | 1 | BSRAM_R10[23] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[10] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | BSRAM_R10[23] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA |
1.109 | 0.249 | tHld | 1 | BSRAM_R10[23] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.272, 57.427%; tC2Q: 0.202, 42.573% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path11
Path Summary:
Slack | 0.225 |
Data Arrival Time | 1.334 |
Data Required Time | 1.109 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_23_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R17C74[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_23_s0/CLK |
1.062 | 0.202 | tC2Q | RR | 1 | R17C74[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_23_s0/Q |
1.334 | 0.272 | tNET | RR | 1 | BSRAM_R10[23] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[7] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | BSRAM_R10[23] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA |
1.109 | 0.249 | tHld | 1 | BSRAM_R10[23] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.272, 57.427%; tC2Q: 0.202, 42.573% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path12
Path Summary:
Slack | 0.225 |
Data Arrival Time | 1.334 |
Data Required Time | 1.109 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_19_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R16C74[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_19_s0/CLK |
1.062 | 0.202 | tC2Q | RR | 1 | R16C74[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_19_s0/Q |
1.334 | 0.272 | tNET | RR | 1 | BSRAM_R10[23] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[3] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | BSRAM_R10[23] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA |
1.109 | 0.249 | tHld | 1 | BSRAM_R10[23] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.272, 57.427%; tC2Q: 0.202, 42.573% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path13
Path Summary:
Slack | 0.225 |
Data Arrival Time | 1.334 |
Data Required Time | 1.109 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_17_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R17C74[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_17_s0/CLK |
1.062 | 0.202 | tC2Q | RR | 1 | R17C74[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_17_s0/Q |
1.334 | 0.272 | tNET | RR | 1 | BSRAM_R10[23] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[1] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | BSRAM_R10[23] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA |
1.109 | 0.249 | tHld | 1 | BSRAM_R10[23] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.272, 57.427%; tC2Q: 0.202, 42.573% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path14
Path Summary:
Slack | 0.335 |
Data Arrival Time | 1.444 |
Data Required Time | 1.109 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_53_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R11C76[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_53_s0/CLK |
1.062 | 0.202 | tC2Q | RR | 1 | R11C76[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_53_s0/Q |
1.444 | 0.382 | tNET | RR | 1 | BSRAM_R10[25] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[5] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | BSRAM_R10[25] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA |
1.109 | 0.249 | tHld | 1 | BSRAM_R10[25] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.382, 65.434%; tC2Q: 0.202, 34.566% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path15
Path Summary:
Slack | 0.335 |
Data Arrival Time | 1.444 |
Data Required Time | 1.109 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_24_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R12C71[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_24_s0/CLK |
1.062 | 0.202 | tC2Q | RR | 1 | R12C71[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_24_s0/Q |
1.444 | 0.382 | tNET | RR | 1 | BSRAM_R10[23] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[8] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | BSRAM_R10[23] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA |
1.109 | 0.249 | tHld | 1 | BSRAM_R10[23] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.382, 65.434%; tC2Q: 0.202, 34.566% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path16
Path Summary:
Slack | 0.347 |
Data Arrival Time | 1.456 |
Data Required Time | 1.109 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_50_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R14C76[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_50_s0/CLK |
1.062 | 0.202 | tC2Q | RR | 1 | R14C76[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_50_s0/Q |
1.456 | 0.394 | tNET | RR | 1 | BSRAM_R10[25] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[2] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | BSRAM_R10[25] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA |
1.109 | 0.249 | tHld | 1 | BSRAM_R10[25] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.394, 66.134%; tC2Q: 0.202, 33.866% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path17
Path Summary:
Slack | 0.347 |
Data Arrival Time | 1.456 |
Data Required Time | 1.109 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_20_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R16C72[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_20_s0/CLK |
1.062 | 0.202 | tC2Q | RR | 1 | R16C72[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_20_s0/Q |
1.456 | 0.394 | tNET | RR | 1 | BSRAM_R10[23] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[4] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | BSRAM_R10[23] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA |
1.109 | 0.249 | tHld | 1 | BSRAM_R10[23] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.394, 66.134%; tC2Q: 0.202, 33.866% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path18
Path Summary:
Slack | 0.347 |
Data Arrival Time | 1.456 |
Data Required Time | 1.109 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_18_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R18C78[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_18_s0/CLK |
1.062 | 0.202 | tC2Q | RR | 1 | R18C78[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_18_s0/Q |
1.456 | 0.394 | tNET | RR | 1 | BSRAM_R10[23] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[2] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | BSRAM_R10[23] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA |
1.109 | 0.249 | tHld | 1 | BSRAM_R10[23] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.394, 66.134%; tC2Q: 0.202, 33.866% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path19
Path Summary:
Slack | 0.347 |
Data Arrival Time | 1.456 |
Data Required Time | 1.109 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_0_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R14C75[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_0_s0/CLK |
1.062 | 0.202 | tC2Q | RR | 1 | R14C75[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_0_s0/Q |
1.456 | 0.394 | tNET | RR | 1 | BSRAM_R10[22] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[0] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | BSRAM_R10[22] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA |
1.109 | 0.249 | tHld | 1 | BSRAM_R10[22] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.394, 66.134%; tC2Q: 0.202, 33.866% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path20
Path Summary:
Slack | 0.351 |
Data Arrival Time | 1.460 |
Data Required Time | 1.109 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_49_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R11C72[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_49_s0/CLK |
1.062 | 0.202 | tC2Q | RR | 1 | R11C72[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_49_s0/Q |
1.460 | 0.398 | tNET | RR | 1 | BSRAM_R10[25] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[1] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | BSRAM_R10[25] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA |
1.109 | 0.249 | tHld | 1 | BSRAM_R10[25] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.398, 66.358%; tC2Q: 0.202, 33.642% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path21
Path Summary:
Slack | 0.351 |
Data Arrival Time | 1.460 |
Data Required Time | 1.109 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_41_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R12C74[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_41_s0/CLK |
1.062 | 0.202 | tC2Q | RR | 1 | R12C74[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_41_s0/Q |
1.460 | 0.398 | tNET | RR | 1 | BSRAM_R10[24] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[9] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | BSRAM_R10[24] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA |
1.109 | 0.249 | tHld | 1 | BSRAM_R10[24] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.398, 66.358%; tC2Q: 0.202, 33.642% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path22
Path Summary:
Slack | 0.351 |
Data Arrival Time | 1.460 |
Data Required Time | 1.109 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_29_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R16C75[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_29_s0/CLK |
1.062 | 0.202 | tC2Q | RR | 1 | R16C75[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_29_s0/Q |
1.460 | 0.398 | tNET | RR | 1 | BSRAM_R10[23] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[13] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | BSRAM_R10[23] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA |
1.109 | 0.249 | tHld | 1 | BSRAM_R10[23] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.398, 66.358%; tC2Q: 0.202, 33.642% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path23
Path Summary:
Slack | 0.351 |
Data Arrival Time | 1.460 |
Data Required Time | 1.109 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_25_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R12C71[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_25_s0/CLK |
1.062 | 0.202 | tC2Q | RR | 1 | R12C71[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_25_s0/Q |
1.460 | 0.398 | tNET | RR | 1 | BSRAM_R10[23] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[9] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | BSRAM_R10[23] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA |
1.109 | 0.249 | tHld | 1 | BSRAM_R10[23] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.398, 66.358%; tC2Q: 0.202, 33.642% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path24
Path Summary:
Slack | 0.351 |
Data Arrival Time | 1.460 |
Data Required Time | 1.109 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_21_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R16C74[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_21_s0/CLK |
1.062 | 0.202 | tC2Q | RR | 1 | R16C74[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_21_s0/Q |
1.460 | 0.398 | tNET | RR | 1 | BSRAM_R10[23] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[5] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | BSRAM_R10[23] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA |
1.109 | 0.249 | tHld | 1 | BSRAM_R10[23] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.398, 66.358%; tC2Q: 0.202, 33.642% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path25
Path Summary:
Slack | 0.351 |
Data Arrival Time | 1.460 |
Data Required Time | 1.109 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_16_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R18C72[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_16_s0/CLK |
1.062 | 0.202 | tC2Q | RR | 1 | R18C72[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_16_s0/Q |
1.460 | 0.398 | tNET | RR | 1 | BSRAM_R10[23] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[0] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | BSRAM_R10[23] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA |
1.109 | 0.249 | tHld | 1 | BSRAM_R10[23] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.398, 66.358%; tC2Q: 0.202, 33.642% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Recovery Analysis Report
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 8.325 |
Data Arrival Time | 12.566 |
Data Required Time | 20.891 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | 1986 | IOR44[A] | clk_ibuf/O |
10.949 | 0.261 | tNET | FF | 1 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.181 | 0.232 | tC2Q | FF | 49 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
12.566 | 1.385 | tNET | FF | 1 | R17C79[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
20.000 | 20.000 | active clock edge time | ||||
20.000 | 0.000 | clk | ||||
20.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
20.683 | 0.683 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
20.926 | 0.243 | tNET | RR | 1 | R17C79[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK |
20.891 | -0.035 | tSu | 1 | R17C79[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1 |
Path Statistics:
Clock Skew | -0.023 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 72.453%; route: 0.261, 27.547% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.385, 85.654%; tC2Q: 0.232, 14.346% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path2
Path Summary:
Slack | 8.538 |
Data Arrival Time | 12.353 |
Data Required Time | 20.891 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/trigger_seq_start_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | 1986 | IOR44[A] | clk_ibuf/O |
10.949 | 0.261 | tNET | FF | 1 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.181 | 0.232 | tC2Q | FF | 49 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
12.353 | 1.172 | tNET | FF | 1 | R26C79[2][A] | gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
20.000 | 20.000 | active clock edge time | ||||
20.000 | 0.000 | clk | ||||
20.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
20.683 | 0.683 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
20.926 | 0.243 | tNET | RR | 1 | R26C79[2][A] | gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLK |
20.891 | -0.035 | tSu | 1 | R26C79[2][A] | gw_gao_inst_0/u_la0_top/trigger_seq_start_s1 |
Path Statistics:
Clock Skew | -0.023 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 72.453%; route: 0.261, 27.547% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.172, 83.478%; tC2Q: 0.232, 16.522% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path3
Path Summary:
Slack | 8.544 |
Data Arrival Time | 12.347 |
Data Required Time | 20.891 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | 1986 | IOR44[A] | clk_ibuf/O |
10.949 | 0.261 | tNET | FF | 1 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.181 | 0.232 | tC2Q | FF | 49 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
12.347 | 1.166 | tNET | FF | 1 | R26C75[0][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
20.000 | 20.000 | active clock edge time | ||||
20.000 | 0.000 | clk | ||||
20.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
20.683 | 0.683 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
20.926 | 0.243 | tNET | RR | 1 | R26C75[0][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLK |
20.891 | -0.035 | tSu | 1 | R26C75[0][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0 |
Path Statistics:
Clock Skew | -0.023 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 72.453%; route: 0.261, 27.547% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.166, 83.410%; tC2Q: 0.232, 16.590% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path4
Path Summary:
Slack | 8.544 |
Data Arrival Time | 12.347 |
Data Required Time | 20.891 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | 1986 | IOR44[A] | clk_ibuf/O |
10.949 | 0.261 | tNET | FF | 1 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.181 | 0.232 | tC2Q | FF | 49 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
12.347 | 1.166 | tNET | FF | 1 | R26C75[0][B] | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
20.000 | 20.000 | active clock edge time | ||||
20.000 | 0.000 | clk | ||||
20.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
20.683 | 0.683 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
20.926 | 0.243 | tNET | RR | 1 | R26C75[0][B] | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLK |
20.891 | -0.035 | tSu | 1 | R26C75[0][B] | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0 |
Path Statistics:
Clock Skew | -0.023 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 72.453%; route: 0.261, 27.547% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.166, 83.410%; tC2Q: 0.232, 16.590% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path5
Path Summary:
Slack | 8.567 |
Data Arrival Time | 12.323 |
Data Required Time | 20.891 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | 1986 | IOR44[A] | clk_ibuf/O |
10.949 | 0.261 | tNET | FF | 1 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.181 | 0.232 | tC2Q | FF | 49 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
12.323 | 1.142 | tNET | FF | 1 | R17C78[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
20.000 | 20.000 | active clock edge time | ||||
20.000 | 0.000 | clk | ||||
20.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
20.683 | 0.683 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
20.926 | 0.243 | tNET | RR | 1 | R17C78[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLK |
20.891 | -0.035 | tSu | 1 | R17C78[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1 |
Path Statistics:
Clock Skew | -0.023 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 72.453%; route: 0.261, 27.547% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.142, 83.121%; tC2Q: 0.232, 16.879% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path6
Path Summary:
Slack | 8.567 |
Data Arrival Time | 12.323 |
Data Required Time | 20.891 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | 1986 | IOR44[A] | clk_ibuf/O |
10.949 | 0.261 | tNET | FF | 1 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.181 | 0.232 | tC2Q | FF | 49 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
12.323 | 1.142 | tNET | FF | 1 | R17C78[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
20.000 | 20.000 | active clock edge time | ||||
20.000 | 0.000 | clk | ||||
20.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
20.683 | 0.683 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
20.926 | 0.243 | tNET | RR | 1 | R17C78[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLK |
20.891 | -0.035 | tSu | 1 | R17C78[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1 |
Path Statistics:
Clock Skew | -0.023 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 72.453%; route: 0.261, 27.547% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.142, 83.121%; tC2Q: 0.232, 16.879% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path7
Path Summary:
Slack | 8.567 |
Data Arrival Time | 12.323 |
Data Required Time | 20.891 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | 1986 | IOR44[A] | clk_ibuf/O |
10.949 | 0.261 | tNET | FF | 1 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.181 | 0.232 | tC2Q | FF | 49 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
12.323 | 1.142 | tNET | FF | 1 | R17C78[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
20.000 | 20.000 | active clock edge time | ||||
20.000 | 0.000 | clk | ||||
20.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
20.683 | 0.683 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
20.926 | 0.243 | tNET | RR | 1 | R17C78[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLK |
20.891 | -0.035 | tSu | 1 | R17C78[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1 |
Path Statistics:
Clock Skew | -0.023 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 72.453%; route: 0.261, 27.547% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.142, 83.121%; tC2Q: 0.232, 16.879% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path8
Path Summary:
Slack | 8.573 |
Data Arrival Time | 12.318 |
Data Required Time | 20.891 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | 1986 | IOR44[A] | clk_ibuf/O |
10.949 | 0.261 | tNET | FF | 1 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.181 | 0.232 | tC2Q | FF | 49 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
12.318 | 1.137 | tNET | FF | 1 | R18C78[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
20.000 | 20.000 | active clock edge time | ||||
20.000 | 0.000 | clk | ||||
20.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
20.683 | 0.683 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
20.926 | 0.243 | tNET | RR | 1 | R18C78[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK |
20.891 | -0.035 | tSu | 1 | R18C78[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1 |
Path Statistics:
Clock Skew | -0.023 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 72.453%; route: 0.261, 27.547% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.137, 83.050%; tC2Q: 0.232, 16.950% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path9
Path Summary:
Slack | 8.573 |
Data Arrival Time | 12.318 |
Data Required Time | 20.891 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | 1986 | IOR44[A] | clk_ibuf/O |
10.949 | 0.261 | tNET | FF | 1 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.181 | 0.232 | tC2Q | FF | 49 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
12.318 | 1.137 | tNET | FF | 1 | R17C77[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
20.000 | 20.000 | active clock edge time | ||||
20.000 | 0.000 | clk | ||||
20.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
20.683 | 0.683 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
20.926 | 0.243 | tNET | RR | 1 | R17C77[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLK |
20.891 | -0.035 | tSu | 1 | R17C77[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1 |
Path Statistics:
Clock Skew | -0.023 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 72.453%; route: 0.261, 27.547% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.137, 83.050%; tC2Q: 0.232, 16.950% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path10
Path Summary:
Slack | 8.573 |
Data Arrival Time | 12.318 |
Data Required Time | 20.891 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | 1986 | IOR44[A] | clk_ibuf/O |
10.949 | 0.261 | tNET | FF | 1 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.181 | 0.232 | tC2Q | FF | 49 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
12.318 | 1.137 | tNET | FF | 1 | R17C77[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
20.000 | 20.000 | active clock edge time | ||||
20.000 | 0.000 | clk | ||||
20.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
20.683 | 0.683 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
20.926 | 0.243 | tNET | RR | 1 | R17C77[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK |
20.891 | -0.035 | tSu | 1 | R17C77[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1 |
Path Statistics:
Clock Skew | -0.023 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 72.453%; route: 0.261, 27.547% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.137, 83.050%; tC2Q: 0.232, 16.950% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path11
Path Summary:
Slack | 8.573 |
Data Arrival Time | 12.318 |
Data Required Time | 20.891 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | 1986 | IOR44[A] | clk_ibuf/O |
10.949 | 0.261 | tNET | FF | 1 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.181 | 0.232 | tC2Q | FF | 49 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
12.318 | 1.137 | tNET | FF | 1 | R17C77[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
20.000 | 20.000 | active clock edge time | ||||
20.000 | 0.000 | clk | ||||
20.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
20.683 | 0.683 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
20.926 | 0.243 | tNET | RR | 1 | R17C77[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK |
20.891 | -0.035 | tSu | 1 | R17C77[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1 |
Path Statistics:
Clock Skew | -0.023 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 72.453%; route: 0.261, 27.547% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.137, 83.050%; tC2Q: 0.232, 16.950% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path12
Path Summary:
Slack | 8.573 |
Data Arrival Time | 12.318 |
Data Required Time | 20.891 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | 1986 | IOR44[A] | clk_ibuf/O |
10.949 | 0.261 | tNET | FF | 1 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.181 | 0.232 | tC2Q | FF | 49 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
12.318 | 1.137 | tNET | FF | 1 | R18C78[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
20.000 | 20.000 | active clock edge time | ||||
20.000 | 0.000 | clk | ||||
20.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
20.683 | 0.683 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
20.926 | 0.243 | tNET | RR | 1 | R18C78[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLK |
20.891 | -0.035 | tSu | 1 | R18C78[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1 |
Path Statistics:
Clock Skew | -0.023 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 72.453%; route: 0.261, 27.547% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.137, 83.050%; tC2Q: 0.232, 16.950% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path13
Path Summary:
Slack | 8.756 |
Data Arrival Time | 12.134 |
Data Required Time | 20.891 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | 1986 | IOR44[A] | clk_ibuf/O |
10.949 | 0.261 | tNET | FF | 1 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.181 | 0.232 | tC2Q | FF | 49 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
12.134 | 0.954 | tNET | FF | 1 | R13C78[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
20.000 | 20.000 | active clock edge time | ||||
20.000 | 0.000 | clk | ||||
20.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
20.683 | 0.683 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
20.926 | 0.243 | tNET | RR | 1 | R13C78[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/CLK |
20.891 | -0.035 | tSu | 1 | R13C78[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1 |
Path Statistics:
Clock Skew | -0.023 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 72.453%; route: 0.261, 27.547% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.954, 80.430%; tC2Q: 0.232, 19.570% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path14
Path Summary:
Slack | 8.756 |
Data Arrival Time | 12.134 |
Data Required Time | 20.891 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | 1986 | IOR44[A] | clk_ibuf/O |
10.949 | 0.261 | tNET | FF | 1 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.181 | 0.232 | tC2Q | FF | 49 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
12.134 | 0.954 | tNET | FF | 1 | R13C77[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
20.000 | 20.000 | active clock edge time | ||||
20.000 | 0.000 | clk | ||||
20.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
20.683 | 0.683 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
20.926 | 0.243 | tNET | RR | 1 | R13C77[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK |
20.891 | -0.035 | tSu | 1 | R13C77[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1 |
Path Statistics:
Clock Skew | -0.023 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 72.453%; route: 0.261, 27.547% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.954, 80.430%; tC2Q: 0.232, 19.570% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path15
Path Summary:
Slack | 8.756 |
Data Arrival Time | 12.134 |
Data Required Time | 20.891 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | 1986 | IOR44[A] | clk_ibuf/O |
10.949 | 0.261 | tNET | FF | 1 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.181 | 0.232 | tC2Q | FF | 49 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
12.134 | 0.954 | tNET | FF | 1 | R13C77[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
20.000 | 20.000 | active clock edge time | ||||
20.000 | 0.000 | clk | ||||
20.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
20.683 | 0.683 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
20.926 | 0.243 | tNET | RR | 1 | R13C77[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK |
20.891 | -0.035 | tSu | 1 | R13C77[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1 |
Path Statistics:
Clock Skew | -0.023 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 72.453%; route: 0.261, 27.547% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.954, 80.430%; tC2Q: 0.232, 19.570% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path16
Path Summary:
Slack | 8.756 |
Data Arrival Time | 12.134 |
Data Required Time | 20.891 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | 1986 | IOR44[A] | clk_ibuf/O |
10.949 | 0.261 | tNET | FF | 1 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.181 | 0.232 | tC2Q | FF | 49 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
12.134 | 0.954 | tNET | FF | 1 | R13C78[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
20.000 | 20.000 | active clock edge time | ||||
20.000 | 0.000 | clk | ||||
20.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
20.683 | 0.683 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
20.926 | 0.243 | tNET | RR | 1 | R13C78[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLK |
20.891 | -0.035 | tSu | 1 | R13C78[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1 |
Path Statistics:
Clock Skew | -0.023 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 72.453%; route: 0.261, 27.547% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.954, 80.430%; tC2Q: 0.232, 19.570% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path17
Path Summary:
Slack | 8.762 |
Data Arrival Time | 12.129 |
Data Required Time | 20.891 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | 1986 | IOR44[A] | clk_ibuf/O |
10.949 | 0.261 | tNET | FF | 1 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.181 | 0.232 | tC2Q | FF | 49 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
12.129 | 0.948 | tNET | FF | 1 | R14C78[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
20.000 | 20.000 | active clock edge time | ||||
20.000 | 0.000 | clk | ||||
20.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
20.683 | 0.683 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
20.926 | 0.243 | tNET | RR | 1 | R14C78[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK |
20.891 | -0.035 | tSu | 1 | R14C78[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1 |
Path Statistics:
Clock Skew | -0.023 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 72.453%; route: 0.261, 27.547% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.948, 80.335%; tC2Q: 0.232, 19.665% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path18
Path Summary:
Slack | 8.762 |
Data Arrival Time | 12.129 |
Data Required Time | 20.891 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | 1986 | IOR44[A] | clk_ibuf/O |
10.949 | 0.261 | tNET | FF | 1 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.181 | 0.232 | tC2Q | FF | 49 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
12.129 | 0.948 | tNET | FF | 1 | R14C77[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
20.000 | 20.000 | active clock edge time | ||||
20.000 | 0.000 | clk | ||||
20.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
20.683 | 0.683 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
20.926 | 0.243 | tNET | RR | 1 | R14C77[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK |
20.891 | -0.035 | tSu | 1 | R14C77[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1 |
Path Statistics:
Clock Skew | -0.023 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 72.453%; route: 0.261, 27.547% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.948, 80.335%; tC2Q: 0.232, 19.665% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path19
Path Summary:
Slack | 8.781 |
Data Arrival Time | 12.110 |
Data Required Time | 20.891 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | 1986 | IOR44[A] | clk_ibuf/O |
10.949 | 0.261 | tNET | FF | 1 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.181 | 0.232 | tC2Q | FF | 49 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
12.110 | 0.929 | tNET | FF | 1 | R26C77[2][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
20.000 | 20.000 | active clock edge time | ||||
20.000 | 0.000 | clk | ||||
20.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
20.683 | 0.683 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
20.926 | 0.243 | tNET | RR | 1 | R26C77[2][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLK |
20.891 | -0.035 | tSu | 1 | R26C77[2][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1 |
Path Statistics:
Clock Skew | -0.023 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 72.453%; route: 0.261, 27.547% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.929, 80.025%; tC2Q: 0.232, 19.975% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path20
Path Summary:
Slack | 8.822 |
Data Arrival Time | 12.069 |
Data Required Time | 20.891 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | 1986 | IOR44[A] | clk_ibuf/O |
10.949 | 0.261 | tNET | FF | 1 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.181 | 0.232 | tC2Q | FF | 49 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
12.069 | 0.888 | tNET | FF | 1 | R16C77[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
20.000 | 20.000 | active clock edge time | ||||
20.000 | 0.000 | clk | ||||
20.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
20.683 | 0.683 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
20.926 | 0.243 | tNET | RR | 1 | R16C77[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK |
20.891 | -0.035 | tSu | 1 | R16C77[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1 |
Path Statistics:
Clock Skew | -0.023 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 72.453%; route: 0.261, 27.547% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.888, 79.291%; tC2Q: 0.232, 20.709% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path21
Path Summary:
Slack | 8.822 |
Data Arrival Time | 12.069 |
Data Required Time | 20.891 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | 1986 | IOR44[A] | clk_ibuf/O |
10.949 | 0.261 | tNET | FF | 1 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.181 | 0.232 | tC2Q | FF | 49 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
12.069 | 0.888 | tNET | FF | 1 | R16C77[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
20.000 | 20.000 | active clock edge time | ||||
20.000 | 0.000 | clk | ||||
20.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
20.683 | 0.683 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
20.926 | 0.243 | tNET | RR | 1 | R16C77[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK |
20.891 | -0.035 | tSu | 1 | R16C77[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1 |
Path Statistics:
Clock Skew | -0.023 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 72.453%; route: 0.261, 27.547% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.888, 79.291%; tC2Q: 0.232, 20.709% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path22
Path Summary:
Slack | 8.822 |
Data Arrival Time | 12.069 |
Data Required Time | 20.891 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | 1986 | IOR44[A] | clk_ibuf/O |
10.949 | 0.261 | tNET | FF | 1 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.181 | 0.232 | tC2Q | FF | 49 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
12.069 | 0.888 | tNET | FF | 1 | R16C78[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
20.000 | 20.000 | active clock edge time | ||||
20.000 | 0.000 | clk | ||||
20.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
20.683 | 0.683 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
20.926 | 0.243 | tNET | RR | 1 | R16C78[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLK |
20.891 | -0.035 | tSu | 1 | R16C78[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1 |
Path Statistics:
Clock Skew | -0.023 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 72.453%; route: 0.261, 27.547% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.888, 79.291%; tC2Q: 0.232, 20.709% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path23
Path Summary:
Slack | 8.822 |
Data Arrival Time | 12.069 |
Data Required Time | 20.891 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | 1986 | IOR44[A] | clk_ibuf/O |
10.949 | 0.261 | tNET | FF | 1 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.181 | 0.232 | tC2Q | FF | 49 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
12.069 | 0.888 | tNET | FF | 1 | R16C78[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
20.000 | 20.000 | active clock edge time | ||||
20.000 | 0.000 | clk | ||||
20.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
20.683 | 0.683 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
20.926 | 0.243 | tNET | RR | 1 | R16C78[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLK |
20.891 | -0.035 | tSu | 1 | R16C78[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1 |
Path Statistics:
Clock Skew | -0.023 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 72.453%; route: 0.261, 27.547% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.888, 79.291%; tC2Q: 0.232, 20.709% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path24
Path Summary:
Slack | 8.822 |
Data Arrival Time | 12.069 |
Data Required Time | 20.891 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | 1986 | IOR44[A] | clk_ibuf/O |
10.949 | 0.261 | tNET | FF | 1 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.181 | 0.232 | tC2Q | FF | 49 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
12.069 | 0.888 | tNET | FF | 1 | R16C78[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
20.000 | 20.000 | active clock edge time | ||||
20.000 | 0.000 | clk | ||||
20.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
20.683 | 0.683 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
20.926 | 0.243 | tNET | RR | 1 | R16C78[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLK |
20.891 | -0.035 | tSu | 1 | R16C78[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1 |
Path Statistics:
Clock Skew | -0.023 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 72.453%; route: 0.261, 27.547% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.888, 79.291%; tC2Q: 0.232, 20.709% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path25
Path Summary:
Slack | 8.822 |
Data Arrival Time | 12.069 |
Data Required Time | 20.891 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | 1986 | IOR44[A] | clk_ibuf/O |
10.949 | 0.261 | tNET | FF | 1 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.181 | 0.232 | tC2Q | FF | 49 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
12.069 | 0.888 | tNET | FF | 1 | R16C77[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
20.000 | 20.000 | active clock edge time | ||||
20.000 | 0.000 | clk | ||||
20.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
20.683 | 0.683 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
20.926 | 0.243 | tNET | RR | 1 | R16C77[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLK |
20.891 | -0.035 | tSu | 1 | R16C77[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1 |
Path Statistics:
Clock Skew | -0.023 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 72.453%; route: 0.261, 27.547% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.888, 79.291%; tC2Q: 0.232, 20.709% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Removal Analysis Report
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 10.477 |
Data Arrival Time | 11.348 |
Data Required Time | 0.871 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | 1986 | IOR44[A] | clk_ibuf/O |
10.872 | 0.195 | tNET | FF | 1 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.074 | 0.202 | tC2Q | FR | 49 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
11.348 | 0.274 | tNET | RR | 1 | R25C76[0][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R25C76[0][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLK |
0.871 | 0.011 | tHld | 1 | R25C76[0][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3 |
Path Statistics:
Clock Skew | -0.012 |
Hold Relationship | -10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 77.694%; route: 0.195, 22.306% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.274, 57.528%; tC2Q: 0.202, 42.472% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path2
Path Summary:
Slack | 10.477 |
Data Arrival Time | 11.348 |
Data Required Time | 0.871 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | 1986 | IOR44[A] | clk_ibuf/O |
10.872 | 0.195 | tNET | FF | 1 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.074 | 0.202 | tC2Q | FR | 49 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
11.348 | 0.274 | tNET | RR | 1 | R25C76[0][B] | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R25C76[0][B] | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLK |
0.871 | 0.011 | tHld | 1 | R25C76[0][B] | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0 |
Path Statistics:
Clock Skew | -0.012 |
Hold Relationship | -10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 77.694%; route: 0.195, 22.306% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.274, 57.528%; tC2Q: 0.202, 42.472% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path3
Path Summary:
Slack | 10.477 |
Data Arrival Time | 11.348 |
Data Required Time | 0.871 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | 1986 | IOR44[A] | clk_ibuf/O |
10.872 | 0.195 | tNET | FF | 1 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.074 | 0.202 | tC2Q | FR | 49 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
11.348 | 0.274 | tNET | RR | 1 | R25C76[1][A] | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R25C76[1][A] | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLK |
0.871 | 0.011 | tHld | 1 | R25C76[1][A] | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0 |
Path Statistics:
Clock Skew | -0.012 |
Hold Relationship | -10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 77.694%; route: 0.195, 22.306% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.274, 57.528%; tC2Q: 0.202, 42.472% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path4
Path Summary:
Slack | 10.477 |
Data Arrival Time | 11.348 |
Data Required Time | 0.871 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | 1986 | IOR44[A] | clk_ibuf/O |
10.872 | 0.195 | tNET | FF | 1 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.074 | 0.202 | tC2Q | FR | 49 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
11.348 | 0.274 | tNET | RR | 1 | R25C76[1][B] | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R25C76[1][B] | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLK |
0.871 | 0.011 | tHld | 1 | R25C76[1][B] | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0 |
Path Statistics:
Clock Skew | -0.012 |
Hold Relationship | -10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 77.694%; route: 0.195, 22.306% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.274, 57.528%; tC2Q: 0.202, 42.472% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path5
Path Summary:
Slack | 10.590 |
Data Arrival Time | 11.461 |
Data Required Time | 0.871 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | 1986 | IOR44[A] | clk_ibuf/O |
10.872 | 0.195 | tNET | FF | 1 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.074 | 0.202 | tC2Q | FR | 49 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
11.461 | 0.387 | tNET | RR | 1 | R24C77[2][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R24C77[2][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLK |
0.871 | 0.011 | tHld | 1 | R24C77[2][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1 |
Path Statistics:
Clock Skew | -0.012 |
Hold Relationship | -10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 77.694%; route: 0.195, 22.306% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.387, 65.682%; tC2Q: 0.202, 34.318% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path6
Path Summary:
Slack | 10.590 |
Data Arrival Time | 11.461 |
Data Required Time | 0.871 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/triger_s0 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | 1986 | IOR44[A] | clk_ibuf/O |
10.872 | 0.195 | tNET | FF | 1 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.074 | 0.202 | tC2Q | FR | 49 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
11.461 | 0.387 | tNET | RR | 1 | R24C78[2][A] | gw_gao_inst_0/u_la0_top/triger_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R24C78[2][A] | gw_gao_inst_0/u_la0_top/triger_s0/CLK |
0.871 | 0.011 | tHld | 1 | R24C78[2][A] | gw_gao_inst_0/u_la0_top/triger_s0 |
Path Statistics:
Clock Skew | -0.012 |
Hold Relationship | -10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 77.694%; route: 0.195, 22.306% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.387, 65.682%; tC2Q: 0.202, 34.318% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path7
Path Summary:
Slack | 10.590 |
Data Arrival Time | 11.461 |
Data Required Time | 0.871 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/start_reg_s0 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | 1986 | IOR44[A] | clk_ibuf/O |
10.872 | 0.195 | tNET | FF | 1 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.074 | 0.202 | tC2Q | FR | 49 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
11.461 | 0.387 | tNET | RR | 1 | R24C78[2][B] | gw_gao_inst_0/u_la0_top/start_reg_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R24C78[2][B] | gw_gao_inst_0/u_la0_top/start_reg_s0/CLK |
0.871 | 0.011 | tHld | 1 | R24C78[2][B] | gw_gao_inst_0/u_la0_top/start_reg_s0 |
Path Statistics:
Clock Skew | -0.012 |
Hold Relationship | -10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 77.694%; route: 0.195, 22.306% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.387, 65.682%; tC2Q: 0.202, 34.318% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path8
Path Summary:
Slack | 10.599 |
Data Arrival Time | 11.470 |
Data Required Time | 0.871 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | 1986 | IOR44[A] | clk_ibuf/O |
10.872 | 0.195 | tNET | FF | 1 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.074 | 0.202 | tC2Q | FR | 49 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
11.470 | 0.396 | tNET | RR | 1 | R25C78[2][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R25C78[2][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLK |
0.871 | 0.011 | tHld | 1 | R25C78[2][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1 |
Path Statistics:
Clock Skew | -0.012 |
Hold Relationship | -10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 77.694%; route: 0.195, 22.306% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.396, 66.199%; tC2Q: 0.202, 33.801% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path9
Path Summary:
Slack | 10.602 |
Data Arrival Time | 11.473 |
Data Required Time | 0.871 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | 1986 | IOR44[A] | clk_ibuf/O |
10.872 | 0.195 | tNET | FF | 1 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.074 | 0.202 | tC2Q | FR | 49 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
11.473 | 0.399 | tNET | RR | 1 | R26C76[1][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R26C76[1][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLK |
0.871 | 0.011 | tHld | 1 | R26C76[1][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3 |
Path Statistics:
Clock Skew | -0.012 |
Hold Relationship | -10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 77.694%; route: 0.195, 22.306% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.399, 66.368%; tC2Q: 0.202, 33.632% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path10
Path Summary:
Slack | 10.602 |
Data Arrival Time | 11.473 |
Data Required Time | 0.871 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | 1986 | IOR44[A] | clk_ibuf/O |
10.872 | 0.195 | tNET | FF | 1 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.074 | 0.202 | tC2Q | FR | 49 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
11.473 | 0.399 | tNET | RR | 1 | R25C77[0][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R25C77[0][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLK |
0.871 | 0.011 | tHld | 1 | R25C77[0][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1 |
Path Statistics:
Clock Skew | -0.012 |
Hold Relationship | -10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 77.694%; route: 0.195, 22.306% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.399, 66.368%; tC2Q: 0.202, 33.632% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path11
Path Summary:
Slack | 10.602 |
Data Arrival Time | 11.473 |
Data Required Time | 0.871 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | 1986 | IOR44[A] | clk_ibuf/O |
10.872 | 0.195 | tNET | FF | 1 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.074 | 0.202 | tC2Q | FR | 49 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
11.473 | 0.399 | tNET | RR | 1 | R25C77[0][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R25C77[0][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLK |
0.871 | 0.011 | tHld | 1 | R25C77[0][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1 |
Path Statistics:
Clock Skew | -0.012 |
Hold Relationship | -10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 77.694%; route: 0.195, 22.306% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.399, 66.368%; tC2Q: 0.202, 33.632% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path12
Path Summary:
Slack | 10.602 |
Data Arrival Time | 11.473 |
Data Required Time | 0.871 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | 1986 | IOR44[A] | clk_ibuf/O |
10.872 | 0.195 | tNET | FF | 1 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.074 | 0.202 | tC2Q | FR | 49 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
11.473 | 0.399 | tNET | RR | 1 | R25C77[1][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R25C77[1][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLK |
0.871 | 0.011 | tHld | 1 | R25C77[1][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1 |
Path Statistics:
Clock Skew | -0.012 |
Hold Relationship | -10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 77.694%; route: 0.195, 22.306% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.399, 66.368%; tC2Q: 0.202, 33.632% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path13
Path Summary:
Slack | 10.602 |
Data Arrival Time | 11.473 |
Data Required Time | 0.871 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | 1986 | IOR44[A] | clk_ibuf/O |
10.872 | 0.195 | tNET | FF | 1 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.074 | 0.202 | tC2Q | FR | 49 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
11.473 | 0.399 | tNET | RR | 1 | R26C76[1][B] | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R26C76[1][B] | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLK |
0.871 | 0.011 | tHld | 1 | R26C76[1][B] | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0 |
Path Statistics:
Clock Skew | -0.012 |
Hold Relationship | -10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 77.694%; route: 0.195, 22.306% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.399, 66.368%; tC2Q: 0.202, 33.632% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path14
Path Summary:
Slack | 10.618 |
Data Arrival Time | 11.488 |
Data Required Time | 0.871 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | 1986 | IOR44[A] | clk_ibuf/O |
10.872 | 0.195 | tNET | FF | 1 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.074 | 0.202 | tC2Q | FR | 49 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
11.488 | 0.414 | tNET | RR | 1 | R27C75[1][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R27C75[1][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLK |
0.871 | 0.011 | tHld | 1 | R27C75[1][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0 |
Path Statistics:
Clock Skew | -0.012 |
Hold Relationship | -10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 77.694%; route: 0.195, 22.306% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.414, 67.223%; tC2Q: 0.202, 32.777% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path15
Path Summary:
Slack | 10.618 |
Data Arrival Time | 11.488 |
Data Required Time | 0.871 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | 1986 | IOR44[A] | clk_ibuf/O |
10.872 | 0.195 | tNET | FF | 1 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.074 | 0.202 | tC2Q | FR | 49 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
11.488 | 0.414 | tNET | RR | 1 | R27C77[2][A] | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R27C77[2][A] | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLK |
0.871 | 0.011 | tHld | 1 | R27C77[2][A] | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0 |
Path Statistics:
Clock Skew | -0.012 |
Hold Relationship | -10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 77.694%; route: 0.195, 22.306% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.414, 67.223%; tC2Q: 0.202, 32.777% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path16
Path Summary:
Slack | 10.618 |
Data Arrival Time | 11.488 |
Data Required Time | 0.871 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | 1986 | IOR44[A] | clk_ibuf/O |
10.872 | 0.195 | tNET | FF | 1 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.074 | 0.202 | tC2Q | FR | 49 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
11.488 | 0.414 | tNET | RR | 1 | R27C77[2][B] | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R27C77[2][B] | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLK |
0.871 | 0.011 | tHld | 1 | R27C77[2][B] | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0 |
Path Statistics:
Clock Skew | -0.012 |
Hold Relationship | -10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 77.694%; route: 0.195, 22.306% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.414, 67.223%; tC2Q: 0.202, 32.777% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path17
Path Summary:
Slack | 10.620 |
Data Arrival Time | 11.491 |
Data Required Time | 0.871 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | 1986 | IOR44[A] | clk_ibuf/O |
10.872 | 0.195 | tNET | FF | 1 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.074 | 0.202 | tC2Q | FR | 49 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
11.491 | 0.417 | tNET | RR | 1 | R15C77[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R15C77[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK |
0.871 | 0.011 | tHld | 1 | R15C77[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1 |
Path Statistics:
Clock Skew | -0.012 |
Hold Relationship | -10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 77.694%; route: 0.195, 22.306% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.417, 67.342%; tC2Q: 0.202, 32.658% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path18
Path Summary:
Slack | 10.620 |
Data Arrival Time | 11.491 |
Data Required Time | 0.871 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_flag_s0 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | 1986 | IOR44[A] | clk_ibuf/O |
10.872 | 0.195 | tNET | FF | 1 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.074 | 0.202 | tC2Q | FR | 49 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
11.491 | 0.417 | tNET | RR | 1 | R15C78[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_flag_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R15C78[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_flag_s0/CLK |
0.871 | 0.011 | tHld | 1 | R15C78[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_flag_s0 |
Path Statistics:
Clock Skew | -0.012 |
Hold Relationship | -10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 77.694%; route: 0.195, 22.306% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.417, 67.342%; tC2Q: 0.202, 32.658% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path19
Path Summary:
Slack | 10.620 |
Data Arrival Time | 11.491 |
Data Required Time | 0.871 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_end_dly_s0 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | 1986 | IOR44[A] | clk_ibuf/O |
10.872 | 0.195 | tNET | FF | 1 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.074 | 0.202 | tC2Q | FR | 49 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
11.491 | 0.417 | tNET | RR | 1 | R15C78[2][A] | gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R15C78[2][A] | gw_gao_inst_0/u_la0_top/capture_end_dly_s0/CLK |
0.871 | 0.011 | tHld | 1 | R15C78[2][A] | gw_gao_inst_0/u_la0_top/capture_end_dly_s0 |
Path Statistics:
Clock Skew | -0.012 |
Hold Relationship | -10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 77.694%; route: 0.195, 22.306% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.417, 67.342%; tC2Q: 0.202, 32.658% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path20
Path Summary:
Slack | 10.724 |
Data Arrival Time | 11.595 |
Data Required Time | 0.871 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | 1986 | IOR44[A] | clk_ibuf/O |
10.872 | 0.195 | tNET | FF | 1 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.074 | 0.202 | tC2Q | FR | 49 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
11.595 | 0.521 | tNET | RR | 1 | R26C77[2][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R26C77[2][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLK |
0.871 | 0.011 | tHld | 1 | R26C77[2][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1 |
Path Statistics:
Clock Skew | -0.012 |
Hold Relationship | -10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 77.694%; route: 0.195, 22.306% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.521, 72.046%; tC2Q: 0.202, 27.954% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path21
Path Summary:
Slack | 10.742 |
Data Arrival Time | 11.613 |
Data Required Time | 0.871 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | 1986 | IOR44[A] | clk_ibuf/O |
10.872 | 0.195 | tNET | FF | 1 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.074 | 0.202 | tC2Q | FR | 49 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
11.613 | 0.539 | tNET | RR | 1 | R14C78[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R14C78[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK |
0.871 | 0.011 | tHld | 1 | R14C78[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1 |
Path Statistics:
Clock Skew | -0.012 |
Hold Relationship | -10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 77.694%; route: 0.195, 22.306% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.539, 72.723%; tC2Q: 0.202, 27.277% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path22
Path Summary:
Slack | 10.742 |
Data Arrival Time | 11.613 |
Data Required Time | 0.871 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | 1986 | IOR44[A] | clk_ibuf/O |
10.872 | 0.195 | tNET | FF | 1 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.074 | 0.202 | tC2Q | FR | 49 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
11.613 | 0.539 | tNET | RR | 1 | R14C77[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R14C77[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK |
0.871 | 0.011 | tHld | 1 | R14C77[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1 |
Path Statistics:
Clock Skew | -0.012 |
Hold Relationship | -10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 77.694%; route: 0.195, 22.306% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.539, 72.723%; tC2Q: 0.202, 27.277% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path23
Path Summary:
Slack | 10.745 |
Data Arrival Time | 11.616 |
Data Required Time | 0.871 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | 1986 | IOR44[A] | clk_ibuf/O |
10.872 | 0.195 | tNET | FF | 1 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.074 | 0.202 | tC2Q | FR | 49 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
11.616 | 0.542 | tNET | RR | 1 | R13C78[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R13C78[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/CLK |
0.871 | 0.011 | tHld | 1 | R13C78[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1 |
Path Statistics:
Clock Skew | -0.012 |
Hold Relationship | -10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 77.694%; route: 0.195, 22.306% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.542, 72.833%; tC2Q: 0.202, 27.167% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path24
Path Summary:
Slack | 10.745 |
Data Arrival Time | 11.616 |
Data Required Time | 0.871 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | 1986 | IOR44[A] | clk_ibuf/O |
10.872 | 0.195 | tNET | FF | 1 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.074 | 0.202 | tC2Q | FR | 49 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
11.616 | 0.542 | tNET | RR | 1 | R13C77[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R13C77[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK |
0.871 | 0.011 | tHld | 1 | R13C77[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1 |
Path Statistics:
Clock Skew | -0.012 |
Hold Relationship | -10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 77.694%; route: 0.195, 22.306% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.542, 72.833%; tC2Q: 0.202, 27.167% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path25
Path Summary:
Slack | 10.745 |
Data Arrival Time | 11.616 |
Data Required Time | 0.871 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | FF | 1 | IOR44[A] | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | 1986 | IOR44[A] | clk_ibuf/O |
10.872 | 0.195 | tNET | FF | 1 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.074 | 0.202 | tC2Q | FR | 49 | R23C77[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
11.616 | 0.542 | tNET | RR | 1 | R13C77[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1986 | IOR44[A] | clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R13C77[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK |
0.871 | 0.011 | tHld | 1 | R13C77[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1 |
Path Statistics:
Clock Skew | -0.012 |
Hold Relationship | -10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 77.694%; route: 0.195, 22.306% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.542, 72.833%; tC2Q: 0.202, 27.167% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Minimum Pulse Width Report:
Report Command:report_min_pulse_width -nworst 10 -detail
MPW1
MPW Summary:
Slack: | 8.911 |
Actual Width: | 9.911 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | clk |
Objects: | i_data_5_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk | ||
10.000 | 0.000 | tCL | FF | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | clk_ibuf/O |
10.949 | 0.261 | tNET | FF | i_data_5_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
20.000 | 0.000 | active clock edge time | ||
20.000 | 0.000 | clk | ||
20.000 | 0.000 | tCL | RR | clk_ibuf/I |
20.676 | 0.675 | tINS | RR | clk_ibuf/O |
20.860 | 0.184 | tNET | RR | i_data_5_s0/CLK |
MPW2
MPW Summary:
Slack: | 8.911 |
Actual Width: | 9.911 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | clk |
Objects: | i_data_3_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk | ||
10.000 | 0.000 | tCL | FF | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | clk_ibuf/O |
10.949 | 0.261 | tNET | FF | i_data_3_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
20.000 | 0.000 | active clock edge time | ||
20.000 | 0.000 | clk | ||
20.000 | 0.000 | tCL | RR | clk_ibuf/I |
20.676 | 0.675 | tINS | RR | clk_ibuf/O |
20.860 | 0.184 | tNET | RR | i_data_3_s0/CLK |
MPW3
MPW Summary:
Slack: | 8.911 |
Actual Width: | 9.911 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | clk |
Objects: | start_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk | ||
10.000 | 0.000 | tCL | FF | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | clk_ibuf/O |
10.949 | 0.261 | tNET | FF | start_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
20.000 | 0.000 | active clock edge time | ||
20.000 | 0.000 | clk | ||
20.000 | 0.000 | tCL | RR | clk_ibuf/I |
20.676 | 0.675 | tINS | RR | clk_ibuf/O |
20.860 | 0.184 | tNET | RR | start_s0/CLK |
MPW4
MPW Summary:
Slack: | 8.911 |
Actual Width: | 9.911 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | clk |
Objects: | FP_Sqrt/FP_Sqrt_inst/count_3_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk | ||
10.000 | 0.000 | tCL | FF | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | clk_ibuf/O |
10.949 | 0.261 | tNET | FF | FP_Sqrt/FP_Sqrt_inst/count_3_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
20.000 | 0.000 | active clock edge time | ||
20.000 | 0.000 | clk | ||
20.000 | 0.000 | tCL | RR | clk_ibuf/I |
20.676 | 0.675 | tINS | RR | clk_ibuf/O |
20.860 | 0.184 | tNET | RR | FP_Sqrt/FP_Sqrt_inst/count_3_s0/CLK |
MPW5
MPW Summary:
Slack: | 8.911 |
Actual Width: | 9.911 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | clk |
Objects: | FP_Sqrt/FP_Sqrt_inst/s_reg_14_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk | ||
10.000 | 0.000 | tCL | FF | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | clk_ibuf/O |
10.949 | 0.261 | tNET | FF | FP_Sqrt/FP_Sqrt_inst/s_reg_14_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
20.000 | 0.000 | active clock edge time | ||
20.000 | 0.000 | clk | ||
20.000 | 0.000 | tCL | RR | clk_ibuf/I |
20.676 | 0.675 | tINS | RR | clk_ibuf/O |
20.860 | 0.184 | tNET | RR | FP_Sqrt/FP_Sqrt_inst/s_reg_14_s0/CLK |
MPW6
MPW Summary:
Slack: | 8.911 |
Actual Width: | 9.911 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | clk |
Objects: | FP_Sqrt/FP_Sqrt_inst/mant_adelay[0]_13_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk | ||
10.000 | 0.000 | tCL | FF | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | clk_ibuf/O |
10.949 | 0.261 | tNET | FF | FP_Sqrt/FP_Sqrt_inst/mant_adelay[0]_13_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
20.000 | 0.000 | active clock edge time | ||
20.000 | 0.000 | clk | ||
20.000 | 0.000 | tCL | RR | clk_ibuf/I |
20.676 | 0.675 | tINS | RR | clk_ibuf/O |
20.860 | 0.184 | tNET | RR | FP_Sqrt/FP_Sqrt_inst/mant_adelay[0]_13_s0/CLK |
MPW7
MPW Summary:
Slack: | 8.911 |
Actual Width: | 9.911 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | clk |
Objects: | FP_Sqrt/FP_Sqrt_inst/gen[0].uut/s_out_17_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk | ||
10.000 | 0.000 | tCL | FF | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | clk_ibuf/O |
10.949 | 0.261 | tNET | FF | FP_Sqrt/FP_Sqrt_inst/gen[0].uut/s_out_17_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
20.000 | 0.000 | active clock edge time | ||
20.000 | 0.000 | clk | ||
20.000 | 0.000 | tCL | RR | clk_ibuf/I |
20.676 | 0.675 | tINS | RR | clk_ibuf/O |
20.860 | 0.184 | tNET | RR | FP_Sqrt/FP_Sqrt_inst/gen[0].uut/s_out_17_s0/CLK |
MPW8
MPW Summary:
Slack: | 8.911 |
Actual Width: | 9.911 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | clk |
Objects: | FP_Sqrt/FP_Sqrt_inst/gen[4].uut/q_out1_23_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk | ||
10.000 | 0.000 | tCL | FF | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | clk_ibuf/O |
10.949 | 0.261 | tNET | FF | FP_Sqrt/FP_Sqrt_inst/gen[4].uut/q_out1_23_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
20.000 | 0.000 | active clock edge time | ||
20.000 | 0.000 | clk | ||
20.000 | 0.000 | tCL | RR | clk_ibuf/I |
20.676 | 0.675 | tINS | RR | clk_ibuf/O |
20.860 | 0.184 | tNET | RR | FP_Sqrt/FP_Sqrt_inst/gen[4].uut/q_out1_23_s0/CLK |
MPW9
MPW Summary:
Slack: | 8.911 |
Actual Width: | 9.911 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | clk |
Objects: | FP_Sqrt/FP_Sqrt_inst/gen[10].uut/q_out1_1_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk | ||
10.000 | 0.000 | tCL | FF | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | clk_ibuf/O |
10.949 | 0.261 | tNET | FF | FP_Sqrt/FP_Sqrt_inst/gen[10].uut/q_out1_1_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
20.000 | 0.000 | active clock edge time | ||
20.000 | 0.000 | clk | ||
20.000 | 0.000 | tCL | RR | clk_ibuf/I |
20.676 | 0.675 | tINS | RR | clk_ibuf/O |
20.860 | 0.184 | tNET | RR | FP_Sqrt/FP_Sqrt_inst/gen[10].uut/q_out1_1_s0/CLK |
MPW10
MPW Summary:
Slack: | 8.911 |
Actual Width: | 9.911 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | clk |
Objects: | FP_Sqrt/FP_Sqrt_inst/gen[24].uut/q_out_9_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk | ||
10.000 | 0.000 | tCL | FF | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | clk_ibuf/O |
10.949 | 0.261 | tNET | FF | FP_Sqrt/FP_Sqrt_inst/gen[24].uut/q_out_9_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
20.000 | 0.000 | active clock edge time | ||
20.000 | 0.000 | clk | ||
20.000 | 0.000 | tCL | RR | clk_ibuf/I |
20.676 | 0.675 | tINS | RR | clk_ibuf/O |
20.860 | 0.184 | tNET | RR | FP_Sqrt/FP_Sqrt_inst/gen[24].uut/q_out_9_s0/CLK |
High Fanout Nets Report:
Report Command:report_high_fanout_nets -max_nets 10
FANOUT | NET NAME | WORST SLACK | MAX DELAY |
---|---|---|---|
1986 | clk_d | 9.458 | 0.261 |
323 | control0[0] | 4.423 | 0.912 |
97 | n20_3 | 42.928 | 2.517 |
76 | data_out_shift_reg_73_7 | 42.928 | 1.320 |
75 | n878_5 | 43.917 | 1.215 |
59 | n878_4 | 43.533 | 0.967 |
50 | data_to_word_counter_15_8 | 45.269 | 1.292 |
49 | rst_ao | 8.325 | 1.385 |
35 | op_reg_en_9 | 44.581 | 0.731 |
34 | n5595_3 | 17.750 | 0.703 |
Route Congestions Report:
Report Command:report_route_congestion -max_grids 10
GRID LOC | ROUTE CONGESTIONS |
---|---|
R27C16 | 90.28% |
R22C19 | 88.89% |
R30C42 | 88.89% |
R20C39 | 88.89% |
R26C64 | 88.89% |
R27C17 | 88.89% |
R27C53 | 88.89% |
R9C68 | 87.50% |
R20C26 | 87.50% |
R11C68 | 87.50% |
Timing Exceptions Report:
Setup Analysis Report
Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Hold Analysis Report
Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Recovery Analysis Report
Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Removal Analysis Report
Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Timing Constraints Report:
SDC Command Type | State | Detail Command |
---|---|---|
TC_CLOCK | Actived | create_clock -name clk -period 20 -waveform {0 10} [get_ports {clk}] |
TC_CLOCK | Actived | create_clock -name tck_pad_i -period 50 -waveform {0 25} [get_ports {tck_pad_i}] |
TC_FALSE_PATH | Actived | set_false_path -from [get_clocks {clk}] -to [get_clocks {tck_pad_i}] |