Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\default\gorv32_plus_const.vh D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\ahb_bridge.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\apb_bridge.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\apb_gpio.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\apb_iic.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\apb_pit.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\apb_sd.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\apb_spi.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\apb_uart.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\apb_wdt.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\axi_bridge.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\bus_matrix.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\gorv32_plus.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\gorv32_plus_top.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\misc.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\onchip_ram.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\riscv_plus_core.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.12.02 (64-bit) |
| Part Number | GW5AT-LV60UG225C2/I1 |
| Device | GW5AT-60 |
| Device Version | B |
| Created Time | Fri Mar 6 10:45:05 2026 |
| Legal Announcement | Copyright (C)2014-2026 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | Gowin_GoRV32_Plus_Top |
| Synthesis Process | Running parser: CPU time = 0h 0m 6s, Elapsed time = 0h 0m 7s, Peak memory usage = 466.512MB Running netlist conversion: CPU time = 0h 0m 0.921s, Elapsed time = 0h 0m 0.929s, Peak memory usage = 466.512MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 9s, Elapsed time = 0h 0m 9s, Peak memory usage = 466.512MB Optimizing Phase 1: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 466.512MB Optimizing Phase 2: CPU time = 0h 0m 14s, Elapsed time = 0h 0m 14s, Peak memory usage = 466.512MB Running inference: Inferring Phase 0: CPU time = 0h 0m 16s, Elapsed time = 0h 0m 16s, Peak memory usage = 466.512MB Inferring Phase 1: CPU time = 0h 0m 6s, Elapsed time = 0h 0m 6s, Peak memory usage = 466.512MB Inferring Phase 2: CPU time = 0h 0m 0.484s, Elapsed time = 0h 0m 0.521s, Peak memory usage = 466.512MB Inferring Phase 3: CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.241s, Peak memory usage = 466.512MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 10s, Elapsed time = 0h 0m 10s, Peak memory usage = 466.512MB Tech-Mapping Phase 1: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 466.512MB Tech-Mapping Phase 2: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 466.512MB Tech-Mapping Phase 3: CPU time = 0h 1m 13s, Elapsed time = 0h 1m 13s, Peak memory usage = 466.512MB Tech-Mapping Phase 4: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 466.512MB Generate output files: CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s, Peak memory usage = 509.414MB |
| Total Time and Memory Usage | CPU time = 0h 2m 28s, Elapsed time = 0h 2m 29s, Peak memory usage = 509.414MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 123 |
| I/O Buf | 123 |
| IBUF | 47 |
| OBUF | 70 |
| IOBUF | 6 |
| Register | 16244 |
| DFFSE | 130 |
| DFFRE | 11022 |
| DFFPE | 109 |
| DFFCE | 4982 |
| DLCE | 1 |
| LUT | 19257 |
| LUT2 | 1424 |
| LUT3 | 8822 |
| LUT4 | 9011 |
| ALU | 2457 |
| ALU | 2457 |
| INV | 65 |
| INV | 65 |
| DSP | |
| MULTALU27X18 | 9 |
| MULT27X36 | 4 |
| BSRAM | 67 |
| SP | 32 |
| SDPB | 29 |
| SDPX9B | 6 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 21779(19322 LUT, 2457 ALU) / 59904 | 37% |
| Register | 16244 / 60228 | 27% |
| --Register as Latch | 1 / 60228 | <1% |
| --Register as FF | 16243 / 60228 | 27% |
| BSRAM | 67 / 118 | 57% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | axi_clk | Base | 10.000 | 100.000 | 0.000 | 5.000 | axi_clk_ibuf/I | ||
| 2 | JTAG_TCK | Base | 10.000 | 100.000 | 0.000 | 5.000 | JTAG_TCK_ibuf/I | ||
| 3 | ahb_clk | Base | 10.000 | 100.000 | 0.000 | 5.000 | ahb_clk_ibuf/I | ||
| 4 | apb_clk | Base | 10.000 | 100.000 | 0.000 | 5.000 | apb_clk_ibuf/I | ||
| 5 | FLASH_QSPI_CLK | Base | 10.000 | 100.000 | 0.000 | 5.000 | FLASH_QSPI_CLK_iobuf/IO |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | axi_clk | 100.000(MHz) | 84.035(MHz) | 22 | TOP |
| 2 | JTAG_TCK | 100.000(MHz) | 160.705(MHz) | 5 | TOP |
| 3 | ahb_clk | 100.000(MHz) | 116.848(MHz) | 14 | TOP |
| 4 | apb_clk | 100.000(MHz) | 102.709(MHz) | 8 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | -1.900 |
| Data Arrival Time | 12.124 |
| Data Required Time | 10.224 |
| From | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_input_payload_exactMask_1_s0 |
| To | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_exponent_2_s0 |
| Launch Clk | axi_clk[R] |
| Latch Clk | axi_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | axi_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | axi_clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 12646 | axi_clk_ibuf/O |
| 0.270 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_input_payload_exactMask_1_s0/CLK |
| 0.545 | 0.275 | tC2Q | RR | 3 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_input_payload_exactMask_1_s0/Q |
| 0.815 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adderRightOp_0_s1/I0 |
| 1.194 | 0.379 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adderRightOp_0_s1/F |
| 1.464 | 0.270 | tNET | RR | 2 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_0_s/I1 |
| 1.869 | 0.405 | tINS | RF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_0_s/COUT |
| 1.869 | 0.000 | tNET | FF | 2 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_1_s/CIN |
| 2.045 | 0.175 | tINS | FR | 3 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_1_s/SUM |
| 2.315 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_3_s5/I2 |
| 2.647 | 0.332 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_3_s5/F |
| 2.917 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_6_s5/I3 |
| 3.106 | 0.189 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_6_s5/F |
| 3.376 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_9_s5/I3 |
| 3.565 | 0.189 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_9_s5/F |
| 3.835 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_12_s5/I3 |
| 4.024 | 0.189 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_12_s5/F |
| 4.294 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_15_s5/I3 |
| 4.483 | 0.189 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_15_s5/F |
| 4.753 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_18_s5/I3 |
| 4.942 | 0.189 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_18_s5/F |
| 5.212 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_21_s5/I3 |
| 5.401 | 0.189 | tINS | RR | 5 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_21_s5/F |
| 5.671 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_29_s5/I3 |
| 5.860 | 0.189 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_29_s5/F |
| 6.130 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_31_s5/I2 |
| 6.462 | 0.332 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_31_s5/F |
| 6.732 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_45_s5/I3 |
| 6.921 | 0.189 | tINS | RR | 19 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_45_s5/F |
| 7.191 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_52_s4/I0 |
| 7.570 | 0.379 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_52_s4/F |
| 7.840 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s9/I0 |
| 8.219 | 0.379 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s9/F |
| 8.489 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s8/I1 |
| 8.861 | 0.372 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s8/F |
| 9.131 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s6/I1 |
| 9.502 | 0.372 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s6/F |
| 9.772 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s4/I0 |
| 10.151 | 0.379 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s4/F |
| 10.421 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s3/I2 |
| 10.753 | 0.332 | tINS | RR | 6 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s3/F |
| 11.023 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_mantissa_51_s1/I1 |
| 11.395 | 0.372 | tINS | RR | 62 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_mantissa_51_s1/F |
| 11.665 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_2_s1/I3 |
| 11.854 | 0.189 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_2_s1/F |
| 12.124 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_exponent_2_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | |||
| 10.000 | 0.000 | axi_clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | axi_clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 12646 | axi_clk_ibuf/O |
| 10.270 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_exponent_2_s0/CLK |
| 10.224 | -0.046 | tSu | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_exponent_2_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 22 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.270, 100.000% |
| Arrival Data Path Delay: | cell: 5.908, 49.845%; route: 5.670, 47.832%; tC2Q: 0.275, 2.323% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.270, 100.000% |
Path 2
Path Summary:| Slack | -1.900 |
| Data Arrival Time | 12.124 |
| Data Required Time | 10.224 |
| From | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_input_payload_exactMask_1_s0 |
| To | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_exponent_5_s0 |
| Launch Clk | axi_clk[R] |
| Latch Clk | axi_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | axi_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | axi_clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 12646 | axi_clk_ibuf/O |
| 0.270 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_input_payload_exactMask_1_s0/CLK |
| 0.545 | 0.275 | tC2Q | RR | 3 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_input_payload_exactMask_1_s0/Q |
| 0.815 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adderRightOp_0_s1/I0 |
| 1.194 | 0.379 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adderRightOp_0_s1/F |
| 1.464 | 0.270 | tNET | RR | 2 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_0_s/I1 |
| 1.869 | 0.405 | tINS | RF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_0_s/COUT |
| 1.869 | 0.000 | tNET | FF | 2 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_1_s/CIN |
| 2.045 | 0.175 | tINS | FR | 3 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_1_s/SUM |
| 2.315 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_3_s5/I2 |
| 2.647 | 0.332 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_3_s5/F |
| 2.917 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_6_s5/I3 |
| 3.106 | 0.189 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_6_s5/F |
| 3.376 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_9_s5/I3 |
| 3.565 | 0.189 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_9_s5/F |
| 3.835 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_12_s5/I3 |
| 4.024 | 0.189 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_12_s5/F |
| 4.294 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_15_s5/I3 |
| 4.483 | 0.189 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_15_s5/F |
| 4.753 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_18_s5/I3 |
| 4.942 | 0.189 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_18_s5/F |
| 5.212 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_21_s5/I3 |
| 5.401 | 0.189 | tINS | RR | 5 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_21_s5/F |
| 5.671 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_29_s5/I3 |
| 5.860 | 0.189 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_29_s5/F |
| 6.130 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_31_s5/I2 |
| 6.462 | 0.332 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_31_s5/F |
| 6.732 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_45_s5/I3 |
| 6.921 | 0.189 | tINS | RR | 19 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_45_s5/F |
| 7.191 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_52_s4/I0 |
| 7.570 | 0.379 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_52_s4/F |
| 7.840 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s9/I0 |
| 8.219 | 0.379 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s9/F |
| 8.489 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s8/I1 |
| 8.861 | 0.372 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s8/F |
| 9.131 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s6/I1 |
| 9.502 | 0.372 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s6/F |
| 9.772 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s4/I0 |
| 10.151 | 0.379 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s4/F |
| 10.421 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s3/I2 |
| 10.753 | 0.332 | tINS | RR | 6 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s3/F |
| 11.023 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_mantissa_51_s1/I1 |
| 11.395 | 0.372 | tINS | RR | 62 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_mantissa_51_s1/F |
| 11.665 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_5_s2/I3 |
| 11.854 | 0.189 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_5_s2/F |
| 12.124 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_exponent_5_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | |||
| 10.000 | 0.000 | axi_clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | axi_clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 12646 | axi_clk_ibuf/O |
| 10.270 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_exponent_5_s0/CLK |
| 10.224 | -0.046 | tSu | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_exponent_5_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 22 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.270, 100.000% |
| Arrival Data Path Delay: | cell: 5.908, 49.845%; route: 5.670, 47.832%; tC2Q: 0.275, 2.323% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.270, 100.000% |
Path 3
Path Summary:| Slack | -1.900 |
| Data Arrival Time | 12.124 |
| Data Required Time | 10.224 |
| From | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_input_payload_exactMask_1_s0 |
| To | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_exponent_7_s0 |
| Launch Clk | axi_clk[R] |
| Latch Clk | axi_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | axi_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | axi_clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 12646 | axi_clk_ibuf/O |
| 0.270 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_input_payload_exactMask_1_s0/CLK |
| 0.545 | 0.275 | tC2Q | RR | 3 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_input_payload_exactMask_1_s0/Q |
| 0.815 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adderRightOp_0_s1/I0 |
| 1.194 | 0.379 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adderRightOp_0_s1/F |
| 1.464 | 0.270 | tNET | RR | 2 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_0_s/I1 |
| 1.869 | 0.405 | tINS | RF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_0_s/COUT |
| 1.869 | 0.000 | tNET | FF | 2 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_1_s/CIN |
| 2.045 | 0.175 | tINS | FR | 3 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_1_s/SUM |
| 2.315 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_3_s5/I2 |
| 2.647 | 0.332 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_3_s5/F |
| 2.917 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_6_s5/I3 |
| 3.106 | 0.189 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_6_s5/F |
| 3.376 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_9_s5/I3 |
| 3.565 | 0.189 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_9_s5/F |
| 3.835 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_12_s5/I3 |
| 4.024 | 0.189 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_12_s5/F |
| 4.294 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_15_s5/I3 |
| 4.483 | 0.189 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_15_s5/F |
| 4.753 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_18_s5/I3 |
| 4.942 | 0.189 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_18_s5/F |
| 5.212 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_21_s5/I3 |
| 5.401 | 0.189 | tINS | RR | 5 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_21_s5/F |
| 5.671 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_29_s5/I3 |
| 5.860 | 0.189 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_29_s5/F |
| 6.130 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_31_s5/I2 |
| 6.462 | 0.332 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_31_s5/F |
| 6.732 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_45_s5/I3 |
| 6.921 | 0.189 | tINS | RR | 19 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_45_s5/F |
| 7.191 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_52_s4/I0 |
| 7.570 | 0.379 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_52_s4/F |
| 7.840 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s9/I0 |
| 8.219 | 0.379 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s9/F |
| 8.489 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s8/I1 |
| 8.861 | 0.372 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s8/F |
| 9.131 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s6/I1 |
| 9.502 | 0.372 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s6/F |
| 9.772 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s4/I0 |
| 10.151 | 0.379 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s4/F |
| 10.421 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s3/I2 |
| 10.753 | 0.332 | tINS | RR | 6 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s3/F |
| 11.023 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_mantissa_51_s1/I1 |
| 11.395 | 0.372 | tINS | RR | 62 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_mantissa_51_s1/F |
| 11.665 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_7_s2/I3 |
| 11.854 | 0.189 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_7_s2/F |
| 12.124 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_exponent_7_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | |||
| 10.000 | 0.000 | axi_clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | axi_clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 12646 | axi_clk_ibuf/O |
| 10.270 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_exponent_7_s0/CLK |
| 10.224 | -0.046 | tSu | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_exponent_7_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 22 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.270, 100.000% |
| Arrival Data Path Delay: | cell: 5.908, 49.845%; route: 5.670, 47.832%; tC2Q: 0.275, 2.323% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.270, 100.000% |
Path 4
Path Summary:| Slack | -1.900 |
| Data Arrival Time | 12.124 |
| Data Required Time | 10.224 |
| From | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_input_payload_exactMask_1_s0 |
| To | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_exponent_10_s0 |
| Launch Clk | axi_clk[R] |
| Latch Clk | axi_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | axi_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | axi_clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 12646 | axi_clk_ibuf/O |
| 0.270 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_input_payload_exactMask_1_s0/CLK |
| 0.545 | 0.275 | tC2Q | RR | 3 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_input_payload_exactMask_1_s0/Q |
| 0.815 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adderRightOp_0_s1/I0 |
| 1.194 | 0.379 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adderRightOp_0_s1/F |
| 1.464 | 0.270 | tNET | RR | 2 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_0_s/I1 |
| 1.869 | 0.405 | tINS | RF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_0_s/COUT |
| 1.869 | 0.000 | tNET | FF | 2 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_1_s/CIN |
| 2.045 | 0.175 | tINS | FR | 3 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_1_s/SUM |
| 2.315 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_3_s5/I2 |
| 2.647 | 0.332 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_3_s5/F |
| 2.917 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_6_s5/I3 |
| 3.106 | 0.189 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_6_s5/F |
| 3.376 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_9_s5/I3 |
| 3.565 | 0.189 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_9_s5/F |
| 3.835 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_12_s5/I3 |
| 4.024 | 0.189 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_12_s5/F |
| 4.294 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_15_s5/I3 |
| 4.483 | 0.189 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_15_s5/F |
| 4.753 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_18_s5/I3 |
| 4.942 | 0.189 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_18_s5/F |
| 5.212 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_21_s5/I3 |
| 5.401 | 0.189 | tINS | RR | 5 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_21_s5/F |
| 5.671 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_29_s5/I3 |
| 5.860 | 0.189 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_29_s5/F |
| 6.130 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_31_s5/I2 |
| 6.462 | 0.332 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_31_s5/F |
| 6.732 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_45_s5/I3 |
| 6.921 | 0.189 | tINS | RR | 19 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_45_s5/F |
| 7.191 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_52_s4/I0 |
| 7.570 | 0.379 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_52_s4/F |
| 7.840 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s9/I0 |
| 8.219 | 0.379 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s9/F |
| 8.489 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s8/I1 |
| 8.861 | 0.372 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s8/F |
| 9.131 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s6/I1 |
| 9.502 | 0.372 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s6/F |
| 9.772 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s4/I0 |
| 10.151 | 0.379 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s4/F |
| 10.421 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s3/I2 |
| 10.753 | 0.332 | tINS | RR | 6 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s3/F |
| 11.023 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_mantissa_51_s1/I1 |
| 11.395 | 0.372 | tINS | RR | 62 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_mantissa_51_s1/F |
| 11.665 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_10_s2/I3 |
| 11.854 | 0.189 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_10_s2/F |
| 12.124 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_exponent_10_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | |||
| 10.000 | 0.000 | axi_clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | axi_clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 12646 | axi_clk_ibuf/O |
| 10.270 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_exponent_10_s0/CLK |
| 10.224 | -0.046 | tSu | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_exponent_10_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 22 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.270, 100.000% |
| Arrival Data Path Delay: | cell: 5.908, 49.845%; route: 5.670, 47.832%; tC2Q: 0.275, 2.323% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.270, 100.000% |
Path 5
Path Summary:| Slack | -1.663 |
| Data Arrival Time | 11.665 |
| Data Required Time | 10.002 |
| From | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_input_payload_exactMask_1_s0 |
| To | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_special_s0 |
| Launch Clk | axi_clk[R] |
| Latch Clk | axi_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | axi_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | axi_clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 12646 | axi_clk_ibuf/O |
| 0.270 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_input_payload_exactMask_1_s0/CLK |
| 0.545 | 0.275 | tC2Q | RR | 3 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_input_payload_exactMask_1_s0/Q |
| 0.815 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adderRightOp_0_s1/I0 |
| 1.194 | 0.379 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adderRightOp_0_s1/F |
| 1.464 | 0.270 | tNET | RR | 2 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_0_s/I1 |
| 1.869 | 0.405 | tINS | RF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_0_s/COUT |
| 1.869 | 0.000 | tNET | FF | 2 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_1_s/CIN |
| 2.045 | 0.175 | tINS | FR | 3 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_1_s/SUM |
| 2.315 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_3_s5/I2 |
| 2.647 | 0.332 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_3_s5/F |
| 2.917 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_6_s5/I3 |
| 3.106 | 0.189 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_6_s5/F |
| 3.376 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_9_s5/I3 |
| 3.565 | 0.189 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_9_s5/F |
| 3.835 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_12_s5/I3 |
| 4.024 | 0.189 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_12_s5/F |
| 4.294 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_15_s5/I3 |
| 4.483 | 0.189 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_15_s5/F |
| 4.753 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_18_s5/I3 |
| 4.942 | 0.189 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_18_s5/F |
| 5.212 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_21_s5/I3 |
| 5.401 | 0.189 | tINS | RR | 5 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_21_s5/F |
| 5.671 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_29_s5/I3 |
| 5.860 | 0.189 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_29_s5/F |
| 6.130 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_31_s5/I2 |
| 6.462 | 0.332 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_31_s5/F |
| 6.732 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_45_s5/I3 |
| 6.921 | 0.189 | tINS | RR | 19 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_45_s5/F |
| 7.191 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_52_s4/I0 |
| 7.570 | 0.379 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_52_s4/F |
| 7.840 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s9/I0 |
| 8.219 | 0.379 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s9/F |
| 8.489 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s8/I1 |
| 8.861 | 0.372 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s8/F |
| 9.131 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s6/I1 |
| 9.502 | 0.372 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s6/F |
| 9.772 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s4/I0 |
| 10.151 | 0.379 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s4/F |
| 10.421 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s3/I2 |
| 10.753 | 0.332 | tINS | RR | 6 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s3/F |
| 11.023 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_special_s1/I1 |
| 11.395 | 0.372 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_special_s1/F |
| 11.665 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_special_s0/SET |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | |||
| 10.000 | 0.000 | axi_clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | axi_clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 12646 | axi_clk_ibuf/O |
| 10.270 | 0.270 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_special_s0/CLK |
| 10.002 | -0.268 | tSu | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_special_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 21 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.270, 100.000% |
| Arrival Data Path Delay: | cell: 5.719, 50.193%; route: 5.400, 47.390%; tC2Q: 0.275, 2.417% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.270, 100.000% |