Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\default\gorv32_plus_const.vh D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\ahb_bridge.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\apb_bridge.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\apb_gpio.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\apb_iic.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\apb_pit.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\apb_sd.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\apb_spi.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\apb_uart.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\apb_wdt.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\axi_bridge.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\bus_matrix.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\gorv32_plus.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\gorv32_plus_top.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\misc.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\onchip_ram.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\riscv_plus_core.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.12.02 (64-bit) |
| Part Number | GW2A-LV55PG484C8/I7 |
| Device | GW2A-55 |
| Device Version | C |
| Created Time | Fri Mar 6 11:30:16 2026 |
| Legal Announcement | Copyright (C)2014-2026 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | Gowin_GoRV32_Plus_Top |
| Synthesis Process | Running parser: CPU time = 0h 0m 7s, Elapsed time = 0h 0m 8s, Peak memory usage = 475.059MB Running netlist conversion: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 475.059MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 10s, Elapsed time = 0h 0m 10s, Peak memory usage = 475.059MB Optimizing Phase 1: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 475.059MB Optimizing Phase 2: CPU time = 0h 0m 17s, Elapsed time = 0h 0m 17s, Peak memory usage = 475.059MB Running inference: Inferring Phase 0: CPU time = 0h 0m 22s, Elapsed time = 0h 0m 22s, Peak memory usage = 475.059MB Inferring Phase 1: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 475.059MB Inferring Phase 2: CPU time = 0h 0m 0.375s, Elapsed time = 0h 0m 0.387s, Peak memory usage = 475.059MB Inferring Phase 3: CPU time = 0h 0m 0.25s, Elapsed time = 0h 0m 0.384s, Peak memory usage = 475.059MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 11s, Elapsed time = 0h 0m 12s, Peak memory usage = 475.059MB Tech-Mapping Phase 1: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 475.059MB Tech-Mapping Phase 2: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 475.059MB Tech-Mapping Phase 3: CPU time = 0h 1m 27s, Elapsed time = 0h 1m 33s, Peak memory usage = 475.059MB Tech-Mapping Phase 4: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 475.059MB Generate output files: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 4s, Peak memory usage = 475.059MB |
| Total Time and Memory Usage | CPU time = 0h 2m 47s, Elapsed time = 0h 2m 56s, Peak memory usage = 475.059MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 129 |
| I/O Buf | 129 |
| IBUF | 47 |
| OBUF | 71 |
| IOBUF | 11 |
| Register | 13481 |
| DFF | 662 |
| DFFE | 6064 |
| DFFS | 70 |
| DFFSE | 69 |
| DFFR | 160 |
| DFFRE | 411 |
| DFFP | 74 |
| DFFPE | 53 |
| DFFC | 1744 |
| DFFCE | 4173 |
| DL | 1 |
| LUT | 18600 |
| LUT2 | 1875 |
| LUT3 | 7223 |
| LUT4 | 9502 |
| ALU | 2590 |
| ALU | 2590 |
| SSRAM | 270 |
| RAM16SDP1 | 21 |
| RAM16SDP2 | 4 |
| RAM16SDP4 | 245 |
| INV | 79 |
| INV | 79 |
| DSP | |
| MULT18X18 | 13 |
| ALU54D | 3 |
| BSRAM | 67 |
| SP | 32 |
| SDPB | 29 |
| SDPX9B | 6 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 22889(18679 LUT, 2590 ALU, 270 RAM16) / 54720 | 42% |
| Register | 13481 / 42000 | 33% |
| --Register as Latch | 1 / 42000 | <1% |
| --Register as FF | 13480 / 42000 | 33% |
| BSRAM | 67 / 140 | 48% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | axi_clk | Base | 10.000 | 100.000 | 0.000 | 5.000 | axi_clk_ibuf/I | ||
| 2 | JTAG_TCK | Base | 10.000 | 100.000 | 0.000 | 5.000 | JTAG_TCK_ibuf/I | ||
| 3 | ahb_clk | Base | 10.000 | 100.000 | 0.000 | 5.000 | ahb_clk_ibuf/I | ||
| 4 | apb_clk | Base | 10.000 | 100.000 | 0.000 | 5.000 | apb_clk_ibuf/I | ||
| 5 | FLASH_QSPI_CLK | Base | 10.000 | 100.000 | 0.000 | 5.000 | FLASH_QSPI_CLK_iobuf/IO | ||
| 6 | u_gorv32_plus/u_gw_sdhc/clock_divider0/SD_CLK_d | Base | 10.000 | 100.000 | 0.000 | 5.000 | u_gorv32_plus/u_gw_sdhc/clock_divider0/SD_CLK_O_s2/Q |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | axi_clk | 100.000(MHz) | 48.740(MHz) | 23 | TOP |
| 2 | JTAG_TCK | 100.000(MHz) | 108.625(MHz) | 5 | TOP |
| 3 | ahb_clk | 100.000(MHz) | 70.003(MHz) | 15 | TOP |
| 4 | apb_clk | 100.000(MHz) | 59.559(MHz) | 9 | TOP |
| 5 | u_gorv32_plus/u_gw_sdhc/clock_divider0/SD_CLK_d | 100.000(MHz) | 74.121(MHz) | 15 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | -10.517 |
| Data Arrival Time | 20.842 |
| Data Required Time | 10.325 |
| From | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_input_payload_mantissaIncrement_s0 |
| To | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_UF_s0 |
| Launch Clk | axi_clk[R] |
| Latch Clk | axi_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | axi_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | axi_clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 10242 | axi_clk_ibuf/O |
| 0.360 | 0.360 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_input_payload_mantissaIncrement_s0/CLK |
| 0.592 | 0.232 | tC2Q | RF | 108 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_input_payload_mantissaIncrement_s0/Q |
| 1.066 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adderRightOp_0_s1/I1 |
| 1.621 | 0.555 | tINS | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adderRightOp_0_s1/F |
| 2.095 | 0.474 | tNET | FF | 2 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_0_s/I1 |
| 2.665 | 0.570 | tINS | FR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_0_s/COUT |
| 2.665 | 0.000 | tNET | RR | 2 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_1_s/CIN |
| 3.135 | 0.470 | tINS | RF | 3 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_1_s/SUM |
| 3.609 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_3_s5/I2 |
| 4.062 | 0.453 | tINS | FF | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_3_s5/F |
| 4.536 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_6_s5/I3 |
| 4.907 | 0.371 | tINS | FF | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_6_s5/F |
| 5.381 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_9_s5/I3 |
| 5.752 | 0.371 | tINS | FF | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_9_s5/F |
| 6.226 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_12_s5/I3 |
| 6.597 | 0.371 | tINS | FF | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_12_s5/F |
| 7.071 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_15_s5/I3 |
| 7.442 | 0.371 | tINS | FF | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_15_s5/F |
| 7.916 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_18_s5/I3 |
| 8.287 | 0.371 | tINS | FF | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_18_s5/F |
| 8.761 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_21_s5/I3 |
| 9.132 | 0.371 | tINS | FF | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_21_s5/F |
| 9.606 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_24_s5/I3 |
| 9.977 | 0.371 | tINS | FF | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_24_s5/F |
| 10.451 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_26_s5/I2 |
| 10.904 | 0.453 | tINS | FF | 3 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_26_s5/F |
| 11.378 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_29_s5/I3 |
| 11.749 | 0.371 | tINS | FF | 16 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_29_s5/F |
| 12.223 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_45_s5/I2 |
| 12.676 | 0.453 | tINS | FF | 19 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_45_s5/F |
| 13.150 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_52_s4/I0 |
| 13.667 | 0.517 | tINS | FF | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_52_s4/F |
| 14.141 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s9/I0 |
| 14.658 | 0.517 | tINS | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s9/F |
| 15.132 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s7/I1 |
| 15.687 | 0.555 | tINS | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s7/F |
| 16.161 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s6/I0 |
| 16.678 | 0.517 | tINS | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s6/F |
| 17.152 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s5/I2 |
| 17.605 | 0.453 | tINS | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s5/F |
| 18.079 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s4/I0 |
| 18.596 | 0.517 | tINS | FF | 3 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s4/F |
| 19.070 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s3/I2 |
| 19.523 | 0.453 | tINS | FF | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s3/F |
| 19.997 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_uf_s1/I3 |
| 20.368 | 0.371 | tINS | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_uf_s1/F |
| 20.842 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_UF_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | |||
| 10.000 | 0.000 | axi_clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | axi_clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 10242 | axi_clk_ibuf/O |
| 10.360 | 0.360 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_UF_s0/CLK |
| 10.325 | -0.035 | tSu | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_UF_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 23 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
| Arrival Data Path Delay: | cell: 9.822, 47.954%; route: 10.428, 50.913%; tC2Q: 0.232, 1.133% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Path 2
Path Summary:| Slack | -10.517 |
| Data Arrival Time | 20.842 |
| Data Required Time | 10.325 |
| From | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_input_payload_mantissaIncrement_s0 |
| To | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_NX_s0 |
| Launch Clk | axi_clk[R] |
| Latch Clk | axi_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | axi_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | axi_clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 10242 | axi_clk_ibuf/O |
| 0.360 | 0.360 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_input_payload_mantissaIncrement_s0/CLK |
| 0.592 | 0.232 | tC2Q | RF | 108 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_input_payload_mantissaIncrement_s0/Q |
| 1.066 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adderRightOp_0_s1/I1 |
| 1.621 | 0.555 | tINS | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adderRightOp_0_s1/F |
| 2.095 | 0.474 | tNET | FF | 2 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_0_s/I1 |
| 2.665 | 0.570 | tINS | FR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_0_s/COUT |
| 2.665 | 0.000 | tNET | RR | 2 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_1_s/CIN |
| 3.135 | 0.470 | tINS | RF | 3 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_1_s/SUM |
| 3.609 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_3_s5/I2 |
| 4.062 | 0.453 | tINS | FF | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_3_s5/F |
| 4.536 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_6_s5/I3 |
| 4.907 | 0.371 | tINS | FF | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_6_s5/F |
| 5.381 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_9_s5/I3 |
| 5.752 | 0.371 | tINS | FF | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_9_s5/F |
| 6.226 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_12_s5/I3 |
| 6.597 | 0.371 | tINS | FF | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_12_s5/F |
| 7.071 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_15_s5/I3 |
| 7.442 | 0.371 | tINS | FF | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_15_s5/F |
| 7.916 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_18_s5/I3 |
| 8.287 | 0.371 | tINS | FF | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_18_s5/F |
| 8.761 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_21_s5/I3 |
| 9.132 | 0.371 | tINS | FF | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_21_s5/F |
| 9.606 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_24_s5/I3 |
| 9.977 | 0.371 | tINS | FF | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_24_s5/F |
| 10.451 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_26_s5/I2 |
| 10.904 | 0.453 | tINS | FF | 3 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_26_s5/F |
| 11.378 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_29_s5/I3 |
| 11.749 | 0.371 | tINS | FF | 16 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_29_s5/F |
| 12.223 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_45_s5/I2 |
| 12.676 | 0.453 | tINS | FF | 19 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_45_s5/F |
| 13.150 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_52_s4/I0 |
| 13.667 | 0.517 | tINS | FF | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_52_s4/F |
| 14.141 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s9/I0 |
| 14.658 | 0.517 | tINS | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s9/F |
| 15.132 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s7/I1 |
| 15.687 | 0.555 | tINS | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s7/F |
| 16.161 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s6/I0 |
| 16.678 | 0.517 | tINS | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s6/F |
| 17.152 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s5/I2 |
| 17.605 | 0.453 | tINS | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s5/F |
| 18.079 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s4/I0 |
| 18.596 | 0.517 | tINS | FF | 3 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s4/F |
| 19.070 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s3/I2 |
| 19.523 | 0.453 | tINS | FF | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s3/F |
| 19.997 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_nx_s1/I3 |
| 20.368 | 0.371 | tINS | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_nx_s1/F |
| 20.842 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_NX_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | |||
| 10.000 | 0.000 | axi_clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | axi_clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 10242 | axi_clk_ibuf/O |
| 10.360 | 0.360 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_NX_s0/CLK |
| 10.325 | -0.035 | tSu | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_NX_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 23 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
| Arrival Data Path Delay: | cell: 9.822, 47.954%; route: 10.428, 50.913%; tC2Q: 0.232, 1.133% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Path 3
Path Summary:| Slack | -10.517 |
| Data Arrival Time | 20.842 |
| Data Required Time | 10.325 |
| From | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_input_payload_mantissaIncrement_s0 |
| To | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_exponent_0_s0 |
| Launch Clk | axi_clk[R] |
| Latch Clk | axi_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | axi_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | axi_clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 10242 | axi_clk_ibuf/O |
| 0.360 | 0.360 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_input_payload_mantissaIncrement_s0/CLK |
| 0.592 | 0.232 | tC2Q | RF | 108 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_input_payload_mantissaIncrement_s0/Q |
| 1.066 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adderRightOp_0_s1/I1 |
| 1.621 | 0.555 | tINS | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adderRightOp_0_s1/F |
| 2.095 | 0.474 | tNET | FF | 2 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_0_s/I1 |
| 2.665 | 0.570 | tINS | FR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_0_s/COUT |
| 2.665 | 0.000 | tNET | RR | 2 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_1_s/CIN |
| 3.135 | 0.470 | tINS | RF | 3 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_1_s/SUM |
| 3.609 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_3_s5/I2 |
| 4.062 | 0.453 | tINS | FF | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_3_s5/F |
| 4.536 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_6_s5/I3 |
| 4.907 | 0.371 | tINS | FF | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_6_s5/F |
| 5.381 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_9_s5/I3 |
| 5.752 | 0.371 | tINS | FF | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_9_s5/F |
| 6.226 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_12_s5/I3 |
| 6.597 | 0.371 | tINS | FF | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_12_s5/F |
| 7.071 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_15_s5/I3 |
| 7.442 | 0.371 | tINS | FF | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_15_s5/F |
| 7.916 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_18_s5/I3 |
| 8.287 | 0.371 | tINS | FF | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_18_s5/F |
| 8.761 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_21_s5/I3 |
| 9.132 | 0.371 | tINS | FF | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_21_s5/F |
| 9.606 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_24_s5/I3 |
| 9.977 | 0.371 | tINS | FF | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_24_s5/F |
| 10.451 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_26_s5/I2 |
| 10.904 | 0.453 | tINS | FF | 3 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_26_s5/F |
| 11.378 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_29_s5/I3 |
| 11.749 | 0.371 | tINS | FF | 16 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_29_s5/F |
| 12.223 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_45_s5/I2 |
| 12.676 | 0.453 | tINS | FF | 19 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_45_s5/F |
| 13.150 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_52_s4/I0 |
| 13.667 | 0.517 | tINS | FF | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_52_s4/F |
| 14.141 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s9/I0 |
| 14.658 | 0.517 | tINS | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s9/F |
| 15.132 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s7/I1 |
| 15.687 | 0.555 | tINS | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s7/F |
| 16.161 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s6/I0 |
| 16.678 | 0.517 | tINS | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s6/F |
| 17.152 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s5/I2 |
| 17.605 | 0.453 | tINS | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s5/F |
| 18.079 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s4/I0 |
| 18.596 | 0.517 | tINS | FF | 3 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s4/F |
| 19.070 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s3/I2 |
| 19.523 | 0.453 | tINS | FF | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s3/F |
| 19.997 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_0_s0/I3 |
| 20.368 | 0.371 | tINS | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_0_s0/F |
| 20.842 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_exponent_0_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | |||
| 10.000 | 0.000 | axi_clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | axi_clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 10242 | axi_clk_ibuf/O |
| 10.360 | 0.360 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_exponent_0_s0/CLK |
| 10.325 | -0.035 | tSu | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_exponent_0_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 23 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
| Arrival Data Path Delay: | cell: 9.822, 47.954%; route: 10.428, 50.913%; tC2Q: 0.232, 1.133% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Path 4
Path Summary:| Slack | -10.517 |
| Data Arrival Time | 20.842 |
| Data Required Time | 10.325 |
| From | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_input_payload_mantissaIncrement_s0 |
| To | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_exponent_1_s0 |
| Launch Clk | axi_clk[R] |
| Latch Clk | axi_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | axi_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | axi_clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 10242 | axi_clk_ibuf/O |
| 0.360 | 0.360 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_input_payload_mantissaIncrement_s0/CLK |
| 0.592 | 0.232 | tC2Q | RF | 108 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_input_payload_mantissaIncrement_s0/Q |
| 1.066 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adderRightOp_0_s1/I1 |
| 1.621 | 0.555 | tINS | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adderRightOp_0_s1/F |
| 2.095 | 0.474 | tNET | FF | 2 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_0_s/I1 |
| 2.665 | 0.570 | tINS | FR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_0_s/COUT |
| 2.665 | 0.000 | tNET | RR | 2 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_1_s/CIN |
| 3.135 | 0.470 | tINS | RF | 3 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_1_s/SUM |
| 3.609 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_3_s5/I2 |
| 4.062 | 0.453 | tINS | FF | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_3_s5/F |
| 4.536 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_6_s5/I3 |
| 4.907 | 0.371 | tINS | FF | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_6_s5/F |
| 5.381 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_9_s5/I3 |
| 5.752 | 0.371 | tINS | FF | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_9_s5/F |
| 6.226 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_12_s5/I3 |
| 6.597 | 0.371 | tINS | FF | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_12_s5/F |
| 7.071 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_15_s5/I3 |
| 7.442 | 0.371 | tINS | FF | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_15_s5/F |
| 7.916 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_18_s5/I3 |
| 8.287 | 0.371 | tINS | FF | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_18_s5/F |
| 8.761 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_21_s5/I3 |
| 9.132 | 0.371 | tINS | FF | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_21_s5/F |
| 9.606 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_24_s5/I3 |
| 9.977 | 0.371 | tINS | FF | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_24_s5/F |
| 10.451 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_26_s5/I2 |
| 10.904 | 0.453 | tINS | FF | 3 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_26_s5/F |
| 11.378 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_29_s5/I3 |
| 11.749 | 0.371 | tINS | FF | 16 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_29_s5/F |
| 12.223 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_45_s5/I2 |
| 12.676 | 0.453 | tINS | FF | 19 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_45_s5/F |
| 13.150 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_52_s4/I0 |
| 13.667 | 0.517 | tINS | FF | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_52_s4/F |
| 14.141 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s9/I0 |
| 14.658 | 0.517 | tINS | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s9/F |
| 15.132 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s7/I1 |
| 15.687 | 0.555 | tINS | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s7/F |
| 16.161 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s6/I0 |
| 16.678 | 0.517 | tINS | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s6/F |
| 17.152 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s5/I2 |
| 17.605 | 0.453 | tINS | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s5/F |
| 18.079 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s4/I0 |
| 18.596 | 0.517 | tINS | FF | 3 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s4/F |
| 19.070 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s3/I2 |
| 19.523 | 0.453 | tINS | FF | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s3/F |
| 19.997 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s0/I3 |
| 20.368 | 0.371 | tINS | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s0/F |
| 20.842 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_exponent_1_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | |||
| 10.000 | 0.000 | axi_clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | axi_clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 10242 | axi_clk_ibuf/O |
| 10.360 | 0.360 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_exponent_1_s0/CLK |
| 10.325 | -0.035 | tSu | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_exponent_1_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 23 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
| Arrival Data Path Delay: | cell: 9.822, 47.954%; route: 10.428, 50.913%; tC2Q: 0.232, 1.133% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Path 5
Path Summary:| Slack | -10.435 |
| Data Arrival Time | 20.760 |
| Data Required Time | 10.325 |
| From | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_input_payload_mantissaIncrement_s0 |
| To | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_exponent_2_s0 |
| Launch Clk | axi_clk[R] |
| Latch Clk | axi_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | axi_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | axi_clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 10242 | axi_clk_ibuf/O |
| 0.360 | 0.360 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_input_payload_mantissaIncrement_s0/CLK |
| 0.592 | 0.232 | tC2Q | RF | 108 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_input_payload_mantissaIncrement_s0/Q |
| 1.066 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adderRightOp_0_s1/I1 |
| 1.621 | 0.555 | tINS | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adderRightOp_0_s1/F |
| 2.095 | 0.474 | tNET | FF | 2 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_0_s/I1 |
| 2.665 | 0.570 | tINS | FR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_0_s/COUT |
| 2.665 | 0.000 | tNET | RR | 2 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_1_s/CIN |
| 3.135 | 0.470 | tINS | RF | 3 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_1_s/SUM |
| 3.609 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_3_s5/I2 |
| 4.062 | 0.453 | tINS | FF | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_3_s5/F |
| 4.536 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_6_s5/I3 |
| 4.907 | 0.371 | tINS | FF | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_6_s5/F |
| 5.381 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_9_s5/I3 |
| 5.752 | 0.371 | tINS | FF | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_9_s5/F |
| 6.226 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_12_s5/I3 |
| 6.597 | 0.371 | tINS | FF | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_12_s5/F |
| 7.071 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_15_s5/I3 |
| 7.442 | 0.371 | tINS | FF | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_15_s5/F |
| 7.916 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_18_s5/I3 |
| 8.287 | 0.371 | tINS | FF | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_18_s5/F |
| 8.761 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_21_s5/I3 |
| 9.132 | 0.371 | tINS | FF | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_21_s5/F |
| 9.606 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_24_s5/I3 |
| 9.977 | 0.371 | tINS | FF | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_24_s5/F |
| 10.451 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_26_s5/I2 |
| 10.904 | 0.453 | tINS | FF | 3 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_26_s5/F |
| 11.378 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_29_s5/I3 |
| 11.749 | 0.371 | tINS | FF | 16 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_29_s5/F |
| 12.223 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_45_s5/I2 |
| 12.676 | 0.453 | tINS | FF | 19 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_45_s5/F |
| 13.150 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_52_s4/I0 |
| 13.667 | 0.517 | tINS | FF | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_52_s4/F |
| 14.141 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s9/I0 |
| 14.658 | 0.517 | tINS | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s9/F |
| 15.132 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s7/I1 |
| 15.687 | 0.555 | tINS | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s7/F |
| 16.161 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s6/I0 |
| 16.678 | 0.517 | tINS | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s6/F |
| 17.152 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s5/I2 |
| 17.605 | 0.453 | tINS | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s5/F |
| 18.079 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s4/I0 |
| 18.596 | 0.517 | tINS | FF | 3 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s4/F |
| 19.070 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_mantissa_51_s2/I3 |
| 19.441 | 0.371 | tINS | FF | 62 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_mantissa_51_s2/F |
| 19.915 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_2_s1/I3 |
| 20.286 | 0.371 | tINS | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_2_s1/F |
| 20.760 | 0.474 | tNET | FF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_exponent_2_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | |||
| 10.000 | 0.000 | axi_clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | axi_clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 10242 | axi_clk_ibuf/O |
| 10.360 | 0.360 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_exponent_2_s0/CLK |
| 10.325 | -0.035 | tSu | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_exponent_2_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 23 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
| Arrival Data Path Delay: | cell: 9.740, 47.745%; route: 10.428, 51.118%; tC2Q: 0.232, 1.137% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |