Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\default\gorv32_plus_const.vh D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\ahb_bridge.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\apb_bridge.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\apb_gpio.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\apb_iic.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\apb_pit.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\apb_sd.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\apb_spi.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\apb_uart.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\apb_wdt.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\axi_bridge.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\bus_matrix.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\gorv32_plus.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\gorv32_plus_top.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\misc.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\onchip_ram.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\riscv_plus_core.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.12.02 (64-bit) |
| Part Number | GW5AST-LV138FPG676AC1/I0 |
| Device | GW5AST-138 |
| Device Version | B |
| Created Time | Thu Mar 5 21:34:49 2026 |
| Legal Announcement | Copyright (C)2014-2026 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | Gowin_GoRV32_Plus_Top |
| Synthesis Process | Running parser: CPU time = 0h 0m 6s, Elapsed time = 0h 0m 7s, Peak memory usage = 478.270MB Running netlist conversion: CPU time = 0h 0m 0.906s, Elapsed time = 0h 0m 0.904s, Peak memory usage = 478.270MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 9s, Elapsed time = 0h 0m 9s, Peak memory usage = 478.270MB Optimizing Phase 1: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 478.270MB Optimizing Phase 2: CPU time = 0h 0m 15s, Elapsed time = 0h 0m 15s, Peak memory usage = 478.270MB Running inference: Inferring Phase 0: CPU time = 0h 0m 18s, Elapsed time = 0h 0m 18s, Peak memory usage = 478.270MB Inferring Phase 1: CPU time = 0h 0m 9s, Elapsed time = 0h 0m 9s, Peak memory usage = 478.270MB Inferring Phase 2: CPU time = 0h 0m 0.5s, Elapsed time = 0h 0m 0.505s, Peak memory usage = 478.270MB Inferring Phase 3: CPU time = 0h 0m 0.265s, Elapsed time = 0h 0m 0.263s, Peak memory usage = 478.270MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 11s, Elapsed time = 0h 0m 11s, Peak memory usage = 478.270MB Tech-Mapping Phase 1: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 478.270MB Tech-Mapping Phase 2: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 478.270MB Tech-Mapping Phase 3: CPU time = 0h 1m 24s, Elapsed time = 0h 1m 24s, Peak memory usage = 478.270MB Tech-Mapping Phase 4: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 478.270MB Generate output files: CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s, Peak memory usage = 567.164MB |
| Total Time and Memory Usage | CPU time = 0h 2m 47s, Elapsed time = 0h 2m 48s, Peak memory usage = 567.164MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 57 |
| I/O Buf | 57 |
| IBUF | 23 |
| OBUF | 28 |
| IOBUF | 6 |
| Register | 18856 |
| DFFSE | 130 |
| DFFRE | 13109 |
| DFFPE | 164 |
| DFFCE | 5450 |
| DLCE | 3 |
| LUT | 22436 |
| LUT2 | 1721 |
| LUT3 | 9389 |
| LUT4 | 11326 |
| ALU | 2590 |
| ALU | 2590 |
| INV | 71 |
| INV | 71 |
| DSP | |
| MULTALU27X18 | 9 |
| MULT27X36 | 4 |
| BSRAM | 67 |
| SP | 32 |
| SDPB | 29 |
| SDPX9B | 6 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 25097(22507 LUT, 2590 ALU) / 138240 | 19% |
| Register | 18856 / 139140 | 14% |
| --Register as Latch | 3 / 139140 | <1% |
| --Register as FF | 18853 / 139140 | 14% |
| BSRAM | 67 / 340 | 20% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | axi_clk | Base | 10.000 | 100.000 | 0.000 | 5.000 | axi_clk_ibuf/I | ||
| 2 | JTAG_TCK | Base | 10.000 | 100.000 | 0.000 | 5.000 | JTAG_TCK_ibuf/I | ||
| 3 | ahb_clk | Base | 10.000 | 100.000 | 0.000 | 5.000 | ahb_clk_ibuf/I | ||
| 4 | apb_clk | Base | 10.000 | 100.000 | 0.000 | 5.000 | apb_clk_ibuf/I | ||
| 5 | FLASH_QSPI_CLK | Base | 10.000 | 100.000 | 0.000 | 5.000 | FLASH_QSPI_CLK_iobuf/IO | ||
| 6 | u_gorv32_plus/u_gw_spi_2/u_spi_spiif/spi_w_clk_slv_20 | Base | 10.000 | 100.000 | 0.000 | 5.000 | u_gorv32_plus/u_gw_spi_2/u_spi_spiif/spi_w_clk_slv_s9/F |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | axi_clk | 100.000(MHz) | 56.488(MHz) | 23 | TOP |
| 2 | JTAG_TCK | 100.000(MHz) | 117.578(MHz) | 5 | TOP |
| 3 | ahb_clk | 100.000(MHz) | 80.970(MHz) | 14 | TOP |
| 4 | apb_clk | 100.000(MHz) | 62.819(MHz) | 21 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | -7.703 |
| Data Arrival Time | 18.017 |
| Data Required Time | 10.314 |
| From | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_input_payload_exactMask_1_s0 |
| To | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_exponent_2_s0 |
| Launch Clk | axi_clk[R] |
| Latch Clk | axi_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | axi_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | axi_clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 12654 | axi_clk_ibuf/O |
| 0.371 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_input_payload_exactMask_1_s0/CLK |
| 0.715 | 0.344 | tC2Q | RR | 3 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_input_payload_exactMask_1_s0/Q |
| 1.087 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adderRightOp_0_s1/I0 |
| 1.608 | 0.521 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adderRightOp_0_s1/F |
| 1.979 | 0.371 | tNET | RR | 2 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_0_s/I1 |
| 2.519 | 0.540 | tINS | RF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_0_s/COUT |
| 2.519 | 0.000 | tNET | FF | 2 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_1_s/CIN |
| 2.564 | 0.045 | tINS | FR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_1_s/COUT |
| 2.564 | 0.000 | tNET | RR | 2 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_2_s/CIN |
| 2.609 | 0.045 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_2_s/COUT |
| 2.609 | 0.000 | tNET | RR | 2 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_3_s/CIN |
| 2.654 | 0.045 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_3_s/COUT |
| 2.654 | 0.000 | tNET | RR | 2 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_4_s/CIN |
| 2.873 | 0.219 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_4_s/SUM |
| 3.245 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_5_s5/I1 |
| 3.755 | 0.511 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_5_s5/F |
| 4.127 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_9_s5/I2 |
| 4.583 | 0.457 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_9_s5/F |
| 4.955 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_12_s5/I3 |
| 5.214 | 0.260 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_12_s5/F |
| 5.586 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_15_s5/I3 |
| 5.845 | 0.260 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_15_s5/F |
| 6.217 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_18_s5/I3 |
| 6.477 | 0.260 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_18_s5/F |
| 6.848 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_21_s5/I3 |
| 7.108 | 0.260 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_21_s5/F |
| 7.479 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_24_s5/I3 |
| 7.739 | 0.260 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_24_s5/F |
| 8.110 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_26_s5/I2 |
| 8.567 | 0.457 | tINS | RR | 3 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_26_s5/F |
| 8.938 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_29_s5/I3 |
| 9.198 | 0.260 | tINS | RR | 5 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_29_s5/F |
| 9.569 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_45_s5/I2 |
| 10.026 | 0.457 | tINS | RR | 13 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_45_s5/F |
| 10.397 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_52_s4/I0 |
| 10.918 | 0.521 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_52_s4/F |
| 11.289 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s11/I0 |
| 11.810 | 0.521 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s11/F |
| 12.182 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s10/I0 |
| 12.702 | 0.521 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s10/F |
| 13.074 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s9/I2 |
| 13.530 | 0.457 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s9/F |
| 13.902 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s8/I1 |
| 14.412 | 0.511 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s8/F |
| 14.784 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s6/I0 |
| 15.305 | 0.521 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s6/F |
| 15.676 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s3/I2 |
| 16.133 | 0.457 | tINS | RR | 6 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s3/F |
| 16.504 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_mantissa_51_s1/I1 |
| 17.015 | 0.511 | tINS | RR | 62 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_mantissa_51_s1/F |
| 17.386 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_2_s1/I3 |
| 17.646 | 0.260 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_2_s1/F |
| 18.017 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_exponent_2_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | |||
| 10.000 | 0.000 | axi_clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | axi_clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 12654 | axi_clk_ibuf/O |
| 10.371 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_exponent_2_s0/CLK |
| 10.314 | -0.057 | tSu | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_exponent_2_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 23 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.371, 100.000% |
| Arrival Data Path Delay: | cell: 9.134, 51.763%; route: 8.168, 46.286%; tC2Q: 0.344, 1.951% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.371, 100.000% |
Path 2
Path Summary:| Slack | -7.703 |
| Data Arrival Time | 18.017 |
| Data Required Time | 10.314 |
| From | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_input_payload_exactMask_1_s0 |
| To | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_exponent_5_s0 |
| Launch Clk | axi_clk[R] |
| Latch Clk | axi_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | axi_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | axi_clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 12654 | axi_clk_ibuf/O |
| 0.371 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_input_payload_exactMask_1_s0/CLK |
| 0.715 | 0.344 | tC2Q | RR | 3 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_input_payload_exactMask_1_s0/Q |
| 1.087 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adderRightOp_0_s1/I0 |
| 1.608 | 0.521 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adderRightOp_0_s1/F |
| 1.979 | 0.371 | tNET | RR | 2 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_0_s/I1 |
| 2.519 | 0.540 | tINS | RF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_0_s/COUT |
| 2.519 | 0.000 | tNET | FF | 2 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_1_s/CIN |
| 2.564 | 0.045 | tINS | FR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_1_s/COUT |
| 2.564 | 0.000 | tNET | RR | 2 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_2_s/CIN |
| 2.609 | 0.045 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_2_s/COUT |
| 2.609 | 0.000 | tNET | RR | 2 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_3_s/CIN |
| 2.654 | 0.045 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_3_s/COUT |
| 2.654 | 0.000 | tNET | RR | 2 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_4_s/CIN |
| 2.873 | 0.219 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_4_s/SUM |
| 3.245 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_5_s5/I1 |
| 3.755 | 0.511 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_5_s5/F |
| 4.127 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_9_s5/I2 |
| 4.583 | 0.457 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_9_s5/F |
| 4.955 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_12_s5/I3 |
| 5.214 | 0.260 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_12_s5/F |
| 5.586 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_15_s5/I3 |
| 5.845 | 0.260 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_15_s5/F |
| 6.217 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_18_s5/I3 |
| 6.477 | 0.260 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_18_s5/F |
| 6.848 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_21_s5/I3 |
| 7.108 | 0.260 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_21_s5/F |
| 7.479 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_24_s5/I3 |
| 7.739 | 0.260 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_24_s5/F |
| 8.110 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_26_s5/I2 |
| 8.567 | 0.457 | tINS | RR | 3 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_26_s5/F |
| 8.938 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_29_s5/I3 |
| 9.198 | 0.260 | tINS | RR | 5 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_29_s5/F |
| 9.569 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_45_s5/I2 |
| 10.026 | 0.457 | tINS | RR | 13 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_45_s5/F |
| 10.397 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_52_s4/I0 |
| 10.918 | 0.521 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_52_s4/F |
| 11.289 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s11/I0 |
| 11.810 | 0.521 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s11/F |
| 12.182 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s10/I0 |
| 12.702 | 0.521 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s10/F |
| 13.074 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s9/I2 |
| 13.530 | 0.457 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s9/F |
| 13.902 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s8/I1 |
| 14.412 | 0.511 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s8/F |
| 14.784 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s6/I0 |
| 15.305 | 0.521 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s6/F |
| 15.676 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s3/I2 |
| 16.133 | 0.457 | tINS | RR | 6 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s3/F |
| 16.504 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_mantissa_51_s1/I1 |
| 17.015 | 0.511 | tINS | RR | 62 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_mantissa_51_s1/F |
| 17.386 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_5_s2/I3 |
| 17.646 | 0.260 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_5_s2/F |
| 18.017 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_exponent_5_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | |||
| 10.000 | 0.000 | axi_clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | axi_clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 12654 | axi_clk_ibuf/O |
| 10.371 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_exponent_5_s0/CLK |
| 10.314 | -0.057 | tSu | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_exponent_5_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 23 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.371, 100.000% |
| Arrival Data Path Delay: | cell: 9.134, 51.763%; route: 8.168, 46.286%; tC2Q: 0.344, 1.951% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.371, 100.000% |
Path 3
Path Summary:| Slack | -7.703 |
| Data Arrival Time | 18.017 |
| Data Required Time | 10.314 |
| From | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_input_payload_exactMask_1_s0 |
| To | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_exponent_7_s0 |
| Launch Clk | axi_clk[R] |
| Latch Clk | axi_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | axi_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | axi_clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 12654 | axi_clk_ibuf/O |
| 0.371 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_input_payload_exactMask_1_s0/CLK |
| 0.715 | 0.344 | tC2Q | RR | 3 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_input_payload_exactMask_1_s0/Q |
| 1.087 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adderRightOp_0_s1/I0 |
| 1.608 | 0.521 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adderRightOp_0_s1/F |
| 1.979 | 0.371 | tNET | RR | 2 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_0_s/I1 |
| 2.519 | 0.540 | tINS | RF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_0_s/COUT |
| 2.519 | 0.000 | tNET | FF | 2 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_1_s/CIN |
| 2.564 | 0.045 | tINS | FR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_1_s/COUT |
| 2.564 | 0.000 | tNET | RR | 2 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_2_s/CIN |
| 2.609 | 0.045 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_2_s/COUT |
| 2.609 | 0.000 | tNET | RR | 2 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_3_s/CIN |
| 2.654 | 0.045 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_3_s/COUT |
| 2.654 | 0.000 | tNET | RR | 2 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_4_s/CIN |
| 2.873 | 0.219 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_4_s/SUM |
| 3.245 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_5_s5/I1 |
| 3.755 | 0.511 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_5_s5/F |
| 4.127 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_9_s5/I2 |
| 4.583 | 0.457 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_9_s5/F |
| 4.955 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_12_s5/I3 |
| 5.214 | 0.260 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_12_s5/F |
| 5.586 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_15_s5/I3 |
| 5.845 | 0.260 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_15_s5/F |
| 6.217 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_18_s5/I3 |
| 6.477 | 0.260 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_18_s5/F |
| 6.848 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_21_s5/I3 |
| 7.108 | 0.260 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_21_s5/F |
| 7.479 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_24_s5/I3 |
| 7.739 | 0.260 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_24_s5/F |
| 8.110 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_26_s5/I2 |
| 8.567 | 0.457 | tINS | RR | 3 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_26_s5/F |
| 8.938 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_29_s5/I3 |
| 9.198 | 0.260 | tINS | RR | 5 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_29_s5/F |
| 9.569 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_45_s5/I2 |
| 10.026 | 0.457 | tINS | RR | 13 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_45_s5/F |
| 10.397 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_52_s4/I0 |
| 10.918 | 0.521 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_52_s4/F |
| 11.289 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s11/I0 |
| 11.810 | 0.521 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s11/F |
| 12.182 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s10/I0 |
| 12.702 | 0.521 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s10/F |
| 13.074 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s9/I2 |
| 13.530 | 0.457 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s9/F |
| 13.902 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s8/I1 |
| 14.412 | 0.511 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s8/F |
| 14.784 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s6/I0 |
| 15.305 | 0.521 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s6/F |
| 15.676 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s3/I2 |
| 16.133 | 0.457 | tINS | RR | 6 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s3/F |
| 16.504 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_mantissa_51_s1/I1 |
| 17.015 | 0.511 | tINS | RR | 62 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_mantissa_51_s1/F |
| 17.386 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_7_s2/I3 |
| 17.646 | 0.260 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_7_s2/F |
| 18.017 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_exponent_7_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | |||
| 10.000 | 0.000 | axi_clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | axi_clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 12654 | axi_clk_ibuf/O |
| 10.371 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_exponent_7_s0/CLK |
| 10.314 | -0.057 | tSu | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_exponent_7_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 23 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.371, 100.000% |
| Arrival Data Path Delay: | cell: 9.134, 51.763%; route: 8.168, 46.286%; tC2Q: 0.344, 1.951% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.371, 100.000% |
Path 4
Path Summary:| Slack | -7.703 |
| Data Arrival Time | 18.017 |
| Data Required Time | 10.314 |
| From | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_input_payload_exactMask_1_s0 |
| To | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_exponent_10_s0 |
| Launch Clk | axi_clk[R] |
| Latch Clk | axi_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | axi_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | axi_clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 12654 | axi_clk_ibuf/O |
| 0.371 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_input_payload_exactMask_1_s0/CLK |
| 0.715 | 0.344 | tC2Q | RR | 3 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_input_payload_exactMask_1_s0/Q |
| 1.087 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adderRightOp_0_s1/I0 |
| 1.608 | 0.521 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adderRightOp_0_s1/F |
| 1.979 | 0.371 | tNET | RR | 2 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_0_s/I1 |
| 2.519 | 0.540 | tINS | RF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_0_s/COUT |
| 2.519 | 0.000 | tNET | FF | 2 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_1_s/CIN |
| 2.564 | 0.045 | tINS | FR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_1_s/COUT |
| 2.564 | 0.000 | tNET | RR | 2 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_2_s/CIN |
| 2.609 | 0.045 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_2_s/COUT |
| 2.609 | 0.000 | tNET | RR | 2 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_3_s/CIN |
| 2.654 | 0.045 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_3_s/COUT |
| 2.654 | 0.000 | tNET | RR | 2 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_4_s/CIN |
| 2.873 | 0.219 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_4_s/SUM |
| 3.245 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_5_s5/I1 |
| 3.755 | 0.511 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_5_s5/F |
| 4.127 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_9_s5/I2 |
| 4.583 | 0.457 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_9_s5/F |
| 4.955 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_12_s5/I3 |
| 5.214 | 0.260 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_12_s5/F |
| 5.586 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_15_s5/I3 |
| 5.845 | 0.260 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_15_s5/F |
| 6.217 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_18_s5/I3 |
| 6.477 | 0.260 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_18_s5/F |
| 6.848 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_21_s5/I3 |
| 7.108 | 0.260 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_21_s5/F |
| 7.479 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_24_s5/I3 |
| 7.739 | 0.260 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_24_s5/F |
| 8.110 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_26_s5/I2 |
| 8.567 | 0.457 | tINS | RR | 3 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_26_s5/F |
| 8.938 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_29_s5/I3 |
| 9.198 | 0.260 | tINS | RR | 5 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_29_s5/F |
| 9.569 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_45_s5/I2 |
| 10.026 | 0.457 | tINS | RR | 13 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_45_s5/F |
| 10.397 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_52_s4/I0 |
| 10.918 | 0.521 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_52_s4/F |
| 11.289 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s11/I0 |
| 11.810 | 0.521 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s11/F |
| 12.182 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s10/I0 |
| 12.702 | 0.521 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s10/F |
| 13.074 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s9/I2 |
| 13.530 | 0.457 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s9/F |
| 13.902 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s8/I1 |
| 14.412 | 0.511 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s8/F |
| 14.784 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s6/I0 |
| 15.305 | 0.521 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s6/F |
| 15.676 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s3/I2 |
| 16.133 | 0.457 | tINS | RR | 6 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s3/F |
| 16.504 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_mantissa_51_s1/I1 |
| 17.015 | 0.511 | tINS | RR | 62 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_mantissa_51_s1/F |
| 17.386 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_10_s2/I3 |
| 17.646 | 0.260 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_10_s2/F |
| 18.017 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_exponent_10_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | |||
| 10.000 | 0.000 | axi_clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | axi_clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 12654 | axi_clk_ibuf/O |
| 10.371 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_exponent_10_s0/CLK |
| 10.314 | -0.057 | tSu | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_exponent_10_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 23 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.371, 100.000% |
| Arrival Data Path Delay: | cell: 9.134, 51.763%; route: 8.168, 46.286%; tC2Q: 0.344, 1.951% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.371, 100.000% |
Path 5
Path Summary:| Slack | -7.350 |
| Data Arrival Time | 17.386 |
| Data Required Time | 10.036 |
| From | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_input_payload_exactMask_1_s0 |
| To | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_special_s0 |
| Launch Clk | axi_clk[R] |
| Latch Clk | axi_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | axi_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | axi_clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 12654 | axi_clk_ibuf/O |
| 0.371 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_input_payload_exactMask_1_s0/CLK |
| 0.715 | 0.344 | tC2Q | RR | 3 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_input_payload_exactMask_1_s0/Q |
| 1.087 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adderRightOp_0_s1/I0 |
| 1.608 | 0.521 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adderRightOp_0_s1/F |
| 1.979 | 0.371 | tNET | RR | 2 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_0_s/I1 |
| 2.519 | 0.540 | tINS | RF | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_0_s/COUT |
| 2.519 | 0.000 | tNET | FF | 2 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_1_s/CIN |
| 2.564 | 0.045 | tINS | FR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_1_s/COUT |
| 2.564 | 0.000 | tNET | RR | 2 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_2_s/CIN |
| 2.609 | 0.045 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_2_s/COUT |
| 2.609 | 0.000 | tNET | RR | 2 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_3_s/CIN |
| 2.654 | 0.045 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_3_s/COUT |
| 2.654 | 0.000 | tNET | RR | 2 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_4_s/CIN |
| 2.873 | 0.219 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_4_s/SUM |
| 3.245 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_5_s5/I1 |
| 3.755 | 0.511 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_5_s5/F |
| 4.127 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_9_s5/I2 |
| 4.583 | 0.457 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_9_s5/F |
| 4.955 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_12_s5/I3 |
| 5.214 | 0.260 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_12_s5/F |
| 5.586 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_15_s5/I3 |
| 5.845 | 0.260 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_15_s5/F |
| 6.217 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_18_s5/I3 |
| 6.477 | 0.260 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_18_s5/F |
| 6.848 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_21_s5/I3 |
| 7.108 | 0.260 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_21_s5/F |
| 7.479 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_24_s5/I3 |
| 7.739 | 0.260 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_24_s5/F |
| 8.110 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_26_s5/I2 |
| 8.567 | 0.457 | tINS | RR | 3 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_26_s5/F |
| 8.938 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_29_s5/I3 |
| 9.198 | 0.260 | tINS | RR | 5 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_29_s5/F |
| 9.569 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_45_s5/I2 |
| 10.026 | 0.457 | tINS | RR | 13 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_45_s5/F |
| 10.397 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_52_s4/I0 |
| 10.918 | 0.521 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_52_s4/F |
| 11.289 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s11/I0 |
| 11.810 | 0.521 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s11/F |
| 12.182 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s10/I0 |
| 12.702 | 0.521 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s10/F |
| 13.074 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s9/I2 |
| 13.530 | 0.457 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s9/F |
| 13.902 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s8/I1 |
| 14.412 | 0.511 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s8/F |
| 14.784 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s6/I0 |
| 15.305 | 0.521 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s6/F |
| 15.676 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s3/I2 |
| 16.133 | 0.457 | tINS | RR | 6 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s3/F |
| 16.504 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_special_s1/I1 |
| 17.015 | 0.511 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_special_s1/F |
| 17.386 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_special_s0/SET |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | |||
| 10.000 | 0.000 | axi_clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | axi_clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 12654 | axi_clk_ibuf/O |
| 10.371 | 0.371 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_special_s0/CLK |
| 10.036 | -0.335 | tSu | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_special_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 22 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.371, 100.000% |
| Arrival Data Path Delay: | cell: 8.874, 52.156%; route: 7.796, 45.821%; tC2Q: 0.344, 2.023% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.371, 100.000% |