Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\AXI2AHB_Async\data\axi_to_ahb_async_top.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\AXI2AHB_Async\data\axi_to_ahb_async.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.12.02 (64-bit) |
| Part Number | GW5AST-LV138FPG676AC2/I1 |
| Device | GW5AST-138 |
| Device Version | C |
| Created Time | Thu Mar 5 21:19:08 2026 |
| Legal Announcement | Copyright (C)2014-2026 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | AXI_to_AHB_Async_Top |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.234s, Elapsed time = 0h 0m 0.327s, Peak memory usage = 71.930MB Running netlist conversion: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 71.930MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.053s, Peak memory usage = 71.930MB Optimizing Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.024s, Peak memory usage = 71.930MB Optimizing Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.069s, Peak memory usage = 71.930MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.101s, Peak memory usage = 71.930MB Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 71.930MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 71.930MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 71.930MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.056s, Peak memory usage = 71.930MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 71.930MB Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 71.930MB Tech-Mapping Phase 3: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 99.141MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.311s, Peak memory usage = 99.141MB Generate output files: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.127s, Peak memory usage = 99.141MB |
| Total Time and Memory Usage | CPU time = 0h 0m 3s, Elapsed time = 0h 0m 4s, Peak memory usage = 99.141MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 337 |
| I/O Buf | 328 |
| IBUF | 193 |
| OBUF | 135 |
| Register | 274 |
| DFFPE | 6 |
| DFFCE | 268 |
| LUT | 525 |
| LUT2 | 61 |
| LUT3 | 151 |
| LUT4 | 313 |
| ALU | 41 |
| ALU | 41 |
| SSRAM | 53 |
| RAM16SDP4 | 53 |
| INV | 7 |
| INV | 7 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 891(532 LUT, 41 ALU, 53 RAM16) / 138240 | <1% |
| Register | 274 / 139140 | <1% |
| --Register as Latch | 0 / 139140 | 0% |
| --Register as FF | 274 / 139140 | <1% |
| BSRAM | 0 / 340 | 0% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | hclk | Base | 10.000 | 100.000 | 0.000 | 5.000 | hclk_ibuf/I | ||
| 2 | aclk | Base | 10.000 | 100.000 | 0.000 | 5.000 | aclk_ibuf/I |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | hclk | 100.000(MHz) | 123.897(MHz) | 11 | TOP |
| 2 | aclk | 100.000(MHz) | 242.760(MHz) | 6 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 1.929 |
| Data Arrival Time | 8.144 |
| Data Required Time | 10.073 |
| From | u_axi_to_ahb_async/fifo2ahb/hsize_0_s1 |
| To | u_axi_to_ahb_async/fifo2ahb/error_wstrb_ap_s1 |
| Launch Clk | hclk[R] |
| Latch Clk | hclk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | hclk | |||
| 0.000 | 0.000 | tCL | RR | 1 | hclk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 228 | hclk_ibuf/O |
| 0.297 | 0.297 | tNET | RR | 1 | u_axi_to_ahb_async/fifo2ahb/hsize_0_s1/CLK |
| 0.572 | 0.275 | tC2Q | RR | 28 | u_axi_to_ahb_async/fifo2ahb/hsize_0_s1/Q |
| 0.869 | 0.297 | tNET | RR | 1 | u_axi_to_ahb_async/fifo2ahb/haddr_adder_0_s/I0 |
| 1.286 | 0.417 | tINS | RR | 2 | u_axi_to_ahb_async/fifo2ahb/haddr_adder_0_s/F |
| 1.583 | 0.297 | tNET | RR | 2 | u_axi_to_ahb_async/fifo2ahb/haddr_inc_0_s/I1 |
| 2.146 | 0.563 | tINS | RR | 2 | u_axi_to_ahb_async/fifo2ahb/haddr_inc_0_s/SUM |
| 2.443 | 0.297 | tNET | RR | 1 | u_axi_to_ahb_async/fifo2ahb/wstrb_ap_part_wr_nxt_4_s7/I0 |
| 2.859 | 0.417 | tINS | RR | 8 | u_axi_to_ahb_async/fifo2ahb/wstrb_ap_part_wr_nxt_4_s7/F |
| 3.156 | 0.297 | tNET | RR | 1 | u_axi_to_ahb_async/fifo2ahb/n1343_s17/I0 |
| 3.573 | 0.417 | tINS | RR | 1 | u_axi_to_ahb_async/fifo2ahb/n1343_s17/F |
| 3.870 | 0.297 | tNET | RR | 1 | u_axi_to_ahb_async/fifo2ahb/n1343_s12/I0 |
| 4.287 | 0.417 | tINS | RR | 3 | u_axi_to_ahb_async/fifo2ahb/n1343_s12/F |
| 4.584 | 0.297 | tNET | RR | 1 | u_axi_to_ahb_async/fifo2ahb/n2192_s19/I0 |
| 5.000 | 0.417 | tINS | RR | 4 | u_axi_to_ahb_async/fifo2ahb/n2192_s19/F |
| 5.297 | 0.297 | tNET | RR | 1 | u_axi_to_ahb_async/fifo2ahb/n2192_s9/I0 |
| 5.714 | 0.417 | tINS | RR | 1 | u_axi_to_ahb_async/fifo2ahb/n2192_s9/F |
| 6.011 | 0.297 | tNET | RR | 1 | u_axi_to_ahb_async/fifo2ahb/n2192_s3/I0 |
| 6.428 | 0.417 | tINS | RR | 2 | u_axi_to_ahb_async/fifo2ahb/n2192_s3/F |
| 6.725 | 0.297 | tNET | RR | 1 | u_axi_to_ahb_async/fifo2ahb/n519_s1/I1 |
| 7.133 | 0.409 | tINS | RR | 3 | u_axi_to_ahb_async/fifo2ahb/n519_s1/F |
| 7.430 | 0.297 | tNET | RR | 1 | u_axi_to_ahb_async/fifo2ahb/error_wstrb_ap_s3/I0 |
| 7.847 | 0.417 | tINS | RR | 1 | u_axi_to_ahb_async/fifo2ahb/error_wstrb_ap_s3/F |
| 8.144 | 0.297 | tNET | RR | 1 | u_axi_to_ahb_async/fifo2ahb/error_wstrb_ap_s1/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | |||
| 10.000 | 0.000 | hclk | |||
| 10.000 | 0.000 | tCL | RR | 1 | hclk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 228 | hclk_ibuf/O |
| 10.297 | 0.297 | tNET | RR | 1 | u_axi_to_ahb_async/fifo2ahb/error_wstrb_ap_s1/CLK |
| 10.073 | -0.224 | tSu | 1 | u_axi_to_ahb_async/fifo2ahb/error_wstrb_ap_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 11 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.297, 100.000% |
| Arrival Data Path Delay: | cell: 4.305, 54.857%; route: 3.267, 41.633%; tC2Q: 0.275, 3.510% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.297, 100.000% |
Path 2
Path Summary:| Slack | 2.099 |
| Data Arrival Time | 8.152 |
| Data Required Time | 10.251 |
| From | u_axi_to_ahb_async/fifo2ahb/hsize_0_s1 |
| To | u_axi_to_ahb_async/fifo2ahb/multi_partial_write_valid_s1 |
| Launch Clk | hclk[R] |
| Latch Clk | hclk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | hclk | |||
| 0.000 | 0.000 | tCL | RR | 1 | hclk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 228 | hclk_ibuf/O |
| 0.297 | 0.297 | tNET | RR | 1 | u_axi_to_ahb_async/fifo2ahb/hsize_0_s1/CLK |
| 0.572 | 0.275 | tC2Q | RR | 28 | u_axi_to_ahb_async/fifo2ahb/hsize_0_s1/Q |
| 0.869 | 0.297 | tNET | RR | 1 | u_axi_to_ahb_async/fifo2ahb/haddr_adder_0_s/I0 |
| 1.286 | 0.417 | tINS | RR | 2 | u_axi_to_ahb_async/fifo2ahb/haddr_adder_0_s/F |
| 1.583 | 0.297 | tNET | RR | 2 | u_axi_to_ahb_async/fifo2ahb/haddr_inc_0_s/I1 |
| 2.146 | 0.563 | tINS | RR | 2 | u_axi_to_ahb_async/fifo2ahb/haddr_inc_0_s/SUM |
| 2.443 | 0.297 | tNET | RR | 1 | u_axi_to_ahb_async/fifo2ahb/wstrb_ap_part_wr_nxt_4_s7/I0 |
| 2.859 | 0.417 | tINS | RR | 8 | u_axi_to_ahb_async/fifo2ahb/wstrb_ap_part_wr_nxt_4_s7/F |
| 3.156 | 0.297 | tNET | RR | 1 | u_axi_to_ahb_async/fifo2ahb/n1343_s15/I0 |
| 3.573 | 0.417 | tINS | RR | 1 | u_axi_to_ahb_async/fifo2ahb/n1343_s15/F |
| 3.870 | 0.297 | tNET | RR | 1 | u_axi_to_ahb_async/fifo2ahb/n1343_s10/I0 |
| 4.287 | 0.417 | tINS | RR | 2 | u_axi_to_ahb_async/fifo2ahb/n1343_s10/F |
| 4.584 | 0.297 | tNET | RR | 1 | u_axi_to_ahb_async/fifo2ahb/n2192_s28/I0 |
| 5.000 | 0.417 | tINS | RR | 5 | u_axi_to_ahb_async/fifo2ahb/n2192_s28/F |
| 5.297 | 0.297 | tNET | RR | 1 | u_axi_to_ahb_async/fifo2ahb/n519_s13/I0 |
| 5.714 | 0.417 | tINS | RR | 2 | u_axi_to_ahb_async/fifo2ahb/n519_s13/F |
| 6.011 | 0.297 | tNET | RR | 1 | u_axi_to_ahb_async/fifo2ahb/n2192_s29/I0 |
| 6.428 | 0.417 | tINS | RR | 1 | u_axi_to_ahb_async/fifo2ahb/n2192_s29/F |
| 6.725 | 0.297 | tNET | RR | 1 | u_axi_to_ahb_async/fifo2ahb/n2192_s1/I0 |
| 7.141 | 0.417 | tINS | RR | 1 | u_axi_to_ahb_async/fifo2ahb/n2192_s1/F |
| 7.438 | 0.297 | tNET | RR | 1 | u_axi_to_ahb_async/fifo2ahb/n2192_s0/I0 |
| 7.855 | 0.417 | tINS | RR | 1 | u_axi_to_ahb_async/fifo2ahb/n2192_s0/F |
| 8.152 | 0.297 | tNET | RR | 1 | u_axi_to_ahb_async/fifo2ahb/multi_partial_write_valid_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | |||
| 10.000 | 0.000 | hclk | |||
| 10.000 | 0.000 | tCL | RR | 1 | hclk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 228 | hclk_ibuf/O |
| 10.297 | 0.297 | tNET | RR | 1 | u_axi_to_ahb_async/fifo2ahb/multi_partial_write_valid_s1/CLK |
| 10.251 | -0.046 | tSu | 1 | u_axi_to_ahb_async/fifo2ahb/multi_partial_write_valid_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 11 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.297, 100.000% |
| Arrival Data Path Delay: | cell: 4.313, 54.904%; route: 3.267, 41.590%; tC2Q: 0.275, 3.506% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.297, 100.000% |
Path 3
Path Summary:| Slack | 2.107 |
| Data Arrival Time | 8.144 |
| Data Required Time | 10.251 |
| From | u_axi_to_ahb_async/fifo2ahb/hsize_0_s1 |
| To | u_axi_to_ahb_async/fifo2ahb/error_wstrb_ap_s1 |
| Launch Clk | hclk[R] |
| Latch Clk | hclk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | hclk | |||
| 0.000 | 0.000 | tCL | RR | 1 | hclk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 228 | hclk_ibuf/O |
| 0.297 | 0.297 | tNET | RR | 1 | u_axi_to_ahb_async/fifo2ahb/hsize_0_s1/CLK |
| 0.572 | 0.275 | tC2Q | RR | 28 | u_axi_to_ahb_async/fifo2ahb/hsize_0_s1/Q |
| 0.869 | 0.297 | tNET | RR | 1 | u_axi_to_ahb_async/fifo2ahb/haddr_adder_0_s/I0 |
| 1.286 | 0.417 | tINS | RR | 2 | u_axi_to_ahb_async/fifo2ahb/haddr_adder_0_s/F |
| 1.583 | 0.297 | tNET | RR | 2 | u_axi_to_ahb_async/fifo2ahb/haddr_inc_0_s/I1 |
| 2.146 | 0.563 | tINS | RR | 2 | u_axi_to_ahb_async/fifo2ahb/haddr_inc_0_s/SUM |
| 2.443 | 0.297 | tNET | RR | 1 | u_axi_to_ahb_async/fifo2ahb/wstrb_ap_part_wr_nxt_4_s7/I0 |
| 2.859 | 0.417 | tINS | RR | 8 | u_axi_to_ahb_async/fifo2ahb/wstrb_ap_part_wr_nxt_4_s7/F |
| 3.156 | 0.297 | tNET | RR | 1 | u_axi_to_ahb_async/fifo2ahb/n1343_s17/I0 |
| 3.573 | 0.417 | tINS | RR | 1 | u_axi_to_ahb_async/fifo2ahb/n1343_s17/F |
| 3.870 | 0.297 | tNET | RR | 1 | u_axi_to_ahb_async/fifo2ahb/n1343_s12/I0 |
| 4.287 | 0.417 | tINS | RR | 3 | u_axi_to_ahb_async/fifo2ahb/n1343_s12/F |
| 4.584 | 0.297 | tNET | RR | 1 | u_axi_to_ahb_async/fifo2ahb/n2192_s19/I0 |
| 5.000 | 0.417 | tINS | RR | 4 | u_axi_to_ahb_async/fifo2ahb/n2192_s19/F |
| 5.297 | 0.297 | tNET | RR | 1 | u_axi_to_ahb_async/fifo2ahb/n2192_s9/I0 |
| 5.714 | 0.417 | tINS | RR | 1 | u_axi_to_ahb_async/fifo2ahb/n2192_s9/F |
| 6.011 | 0.297 | tNET | RR | 1 | u_axi_to_ahb_async/fifo2ahb/n2192_s3/I0 |
| 6.428 | 0.417 | tINS | RR | 2 | u_axi_to_ahb_async/fifo2ahb/n2192_s3/F |
| 6.725 | 0.297 | tNET | RR | 1 | u_axi_to_ahb_async/fifo2ahb/n519_s1/I1 |
| 7.133 | 0.409 | tINS | RR | 3 | u_axi_to_ahb_async/fifo2ahb/n519_s1/F |
| 7.430 | 0.297 | tNET | RR | 1 | u_axi_to_ahb_async/fifo2ahb/n2201_s2/I0 |
| 7.847 | 0.417 | tINS | RR | 1 | u_axi_to_ahb_async/fifo2ahb/n2201_s2/F |
| 8.144 | 0.297 | tNET | RR | 1 | u_axi_to_ahb_async/fifo2ahb/error_wstrb_ap_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | |||
| 10.000 | 0.000 | hclk | |||
| 10.000 | 0.000 | tCL | RR | 1 | hclk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 228 | hclk_ibuf/O |
| 10.297 | 0.297 | tNET | RR | 1 | u_axi_to_ahb_async/fifo2ahb/error_wstrb_ap_s1/CLK |
| 10.251 | -0.046 | tSu | 1 | u_axi_to_ahb_async/fifo2ahb/error_wstrb_ap_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 11 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.297, 100.000% |
| Arrival Data Path Delay: | cell: 4.305, 54.857%; route: 3.267, 41.633%; tC2Q: 0.275, 3.510% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.297, 100.000% |
Path 4
Path Summary:| Slack | 2.107 |
| Data Arrival Time | 8.144 |
| Data Required Time | 10.251 |
| From | u_axi_to_ahb_async/fifo2ahb/hsize_0_s1 |
| To | u_axi_to_ahb_async/fifo2ahb/hsize_1_s1 |
| Launch Clk | hclk[R] |
| Latch Clk | hclk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | hclk | |||
| 0.000 | 0.000 | tCL | RR | 1 | hclk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 228 | hclk_ibuf/O |
| 0.297 | 0.297 | tNET | RR | 1 | u_axi_to_ahb_async/fifo2ahb/hsize_0_s1/CLK |
| 0.572 | 0.275 | tC2Q | RR | 28 | u_axi_to_ahb_async/fifo2ahb/hsize_0_s1/Q |
| 0.869 | 0.297 | tNET | RR | 1 | u_axi_to_ahb_async/fifo2ahb/haddr_adder_0_s/I0 |
| 1.286 | 0.417 | tINS | RR | 2 | u_axi_to_ahb_async/fifo2ahb/haddr_adder_0_s/F |
| 1.583 | 0.297 | tNET | RR | 2 | u_axi_to_ahb_async/fifo2ahb/haddr_inc_0_s/I1 |
| 2.146 | 0.563 | tINS | RR | 2 | u_axi_to_ahb_async/fifo2ahb/haddr_inc_0_s/SUM |
| 2.443 | 0.297 | tNET | RR | 1 | u_axi_to_ahb_async/fifo2ahb/wstrb_ap_part_wr_nxt_4_s7/I0 |
| 2.859 | 0.417 | tINS | RR | 8 | u_axi_to_ahb_async/fifo2ahb/wstrb_ap_part_wr_nxt_4_s7/F |
| 3.156 | 0.297 | tNET | RR | 1 | u_axi_to_ahb_async/fifo2ahb/n1343_s15/I0 |
| 3.573 | 0.417 | tINS | RR | 1 | u_axi_to_ahb_async/fifo2ahb/n1343_s15/F |
| 3.870 | 0.297 | tNET | RR | 1 | u_axi_to_ahb_async/fifo2ahb/n1343_s10/I0 |
| 4.287 | 0.417 | tINS | RR | 2 | u_axi_to_ahb_async/fifo2ahb/n1343_s10/F |
| 4.584 | 0.297 | tNET | RR | 1 | u_axi_to_ahb_async/fifo2ahb/n1343_s24/I0 |
| 5.000 | 0.417 | tINS | RR | 7 | u_axi_to_ahb_async/fifo2ahb/n1343_s24/F |
| 5.297 | 0.297 | tNET | RR | 1 | u_axi_to_ahb_async/fifo2ahb/n1343_s4/I0 |
| 5.714 | 0.417 | tINS | RR | 6 | u_axi_to_ahb_async/fifo2ahb/n1343_s4/F |
| 6.011 | 0.297 | tNET | RR | 1 | u_axi_to_ahb_async/fifo2ahb/n1345_s4/I1 |
| 6.420 | 0.409 | tINS | RR | 9 | u_axi_to_ahb_async/fifo2ahb/n1345_s4/F |
| 6.717 | 0.297 | tNET | RR | 1 | u_axi_to_ahb_async/fifo2ahb/n1423_s2/I0 |
| 7.133 | 0.417 | tINS | RR | 1 | u_axi_to_ahb_async/fifo2ahb/n1423_s2/F |
| 7.430 | 0.297 | tNET | RR | 1 | u_axi_to_ahb_async/fifo2ahb/n1423_s3/I0 |
| 7.847 | 0.417 | tINS | RR | 1 | u_axi_to_ahb_async/fifo2ahb/n1423_s3/F |
| 8.144 | 0.297 | tNET | RR | 1 | u_axi_to_ahb_async/fifo2ahb/hsize_1_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | |||
| 10.000 | 0.000 | hclk | |||
| 10.000 | 0.000 | tCL | RR | 1 | hclk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 228 | hclk_ibuf/O |
| 10.297 | 0.297 | tNET | RR | 1 | u_axi_to_ahb_async/fifo2ahb/hsize_1_s1/CLK |
| 10.251 | -0.046 | tSu | 1 | u_axi_to_ahb_async/fifo2ahb/hsize_1_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 11 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.297, 100.000% |
| Arrival Data Path Delay: | cell: 4.305, 54.857%; route: 3.267, 41.633%; tC2Q: 0.275, 3.510% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.297, 100.000% |
Path 5
Path Summary:| Slack | 2.107 |
| Data Arrival Time | 8.144 |
| Data Required Time | 10.251 |
| From | u_axi_to_ahb_async/fifo2ahb/hsize_0_s1 |
| To | u_axi_to_ahb_async/fifo2ahb/haddr_1_s1 |
| Launch Clk | hclk[R] |
| Latch Clk | hclk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | hclk | |||
| 0.000 | 0.000 | tCL | RR | 1 | hclk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 228 | hclk_ibuf/O |
| 0.297 | 0.297 | tNET | RR | 1 | u_axi_to_ahb_async/fifo2ahb/hsize_0_s1/CLK |
| 0.572 | 0.275 | tC2Q | RR | 28 | u_axi_to_ahb_async/fifo2ahb/hsize_0_s1/Q |
| 0.869 | 0.297 | tNET | RR | 1 | u_axi_to_ahb_async/fifo2ahb/haddr_adder_0_s/I0 |
| 1.286 | 0.417 | tINS | RR | 2 | u_axi_to_ahb_async/fifo2ahb/haddr_adder_0_s/F |
| 1.583 | 0.297 | tNET | RR | 2 | u_axi_to_ahb_async/fifo2ahb/haddr_inc_0_s/I1 |
| 2.146 | 0.563 | tINS | RR | 2 | u_axi_to_ahb_async/fifo2ahb/haddr_inc_0_s/SUM |
| 2.443 | 0.297 | tNET | RR | 1 | u_axi_to_ahb_async/fifo2ahb/wstrb_ap_part_wr_nxt_4_s7/I0 |
| 2.859 | 0.417 | tINS | RR | 8 | u_axi_to_ahb_async/fifo2ahb/wstrb_ap_part_wr_nxt_4_s7/F |
| 3.156 | 0.297 | tNET | RR | 1 | u_axi_to_ahb_async/fifo2ahb/n1343_s15/I0 |
| 3.573 | 0.417 | tINS | RR | 1 | u_axi_to_ahb_async/fifo2ahb/n1343_s15/F |
| 3.870 | 0.297 | tNET | RR | 1 | u_axi_to_ahb_async/fifo2ahb/n1343_s10/I0 |
| 4.287 | 0.417 | tINS | RR | 2 | u_axi_to_ahb_async/fifo2ahb/n1343_s10/F |
| 4.584 | 0.297 | tNET | RR | 1 | u_axi_to_ahb_async/fifo2ahb/n1343_s24/I0 |
| 5.000 | 0.417 | tINS | RR | 7 | u_axi_to_ahb_async/fifo2ahb/n1343_s24/F |
| 5.297 | 0.297 | tNET | RR | 1 | u_axi_to_ahb_async/fifo2ahb/n1343_s4/I0 |
| 5.714 | 0.417 | tINS | RR | 6 | u_axi_to_ahb_async/fifo2ahb/n1343_s4/F |
| 6.011 | 0.297 | tNET | RR | 1 | u_axi_to_ahb_async/fifo2ahb/n1345_s4/I1 |
| 6.420 | 0.409 | tINS | RR | 9 | u_axi_to_ahb_async/fifo2ahb/n1345_s4/F |
| 6.717 | 0.297 | tNET | RR | 1 | u_axi_to_ahb_async/fifo2ahb/n1344_s3/I0 |
| 7.133 | 0.417 | tINS | RR | 1 | u_axi_to_ahb_async/fifo2ahb/n1344_s3/F |
| 7.430 | 0.297 | tNET | RR | 1 | u_axi_to_ahb_async/fifo2ahb/n1344_s2/I0 |
| 7.847 | 0.417 | tINS | RR | 1 | u_axi_to_ahb_async/fifo2ahb/n1344_s2/F |
| 8.144 | 0.297 | tNET | RR | 1 | u_axi_to_ahb_async/fifo2ahb/haddr_1_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | |||
| 10.000 | 0.000 | hclk | |||
| 10.000 | 0.000 | tCL | RR | 1 | hclk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 228 | hclk_ibuf/O |
| 10.297 | 0.297 | tNET | RR | 1 | u_axi_to_ahb_async/fifo2ahb/haddr_1_s1/CLK |
| 10.251 | -0.046 | tSu | 1 | u_axi_to_ahb_async/fifo2ahb/haddr_1_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 11 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.297, 100.000% |
| Arrival Data Path Delay: | cell: 4.305, 54.857%; route: 3.267, 41.633%; tC2Q: 0.275, 3.510% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.297, 100.000% |