Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\DDR3\data\ddr3_1_4code_hs\ddr3_1_4code_hs.v
D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\DDR3\data\ddr3_1_4code_hs\DDR3_TOP.v
GowinSynthesis Constraints File ---
Tool Version V1.9.12.02 (64-bit)
Part Number GW5AST-LV138FPG676AC2/I1
Device GW5AST-138
Device Version C
Created Time Thu Mar 5 21:19:29 2026
Legal Announcement Copyright (C)2014-2026 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module DDR3_Memory_Interface_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 119.055MB
Running netlist conversion:
    CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.118s, Peak memory usage = 119.055MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.593s, Elapsed time = 0h 0m 0.615s, Peak memory usage = 119.055MB
    Optimizing Phase 1: CPU time = 0h 0m 0.328s, Elapsed time = 0h 0m 0.323s, Peak memory usage = 119.055MB
    Optimizing Phase 2: CPU time = 0h 0m 0.937s, Elapsed time = 0h 0m 0.939s, Peak memory usage = 119.055MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.593s, Elapsed time = 0h 0m 0.618s, Peak memory usage = 119.055MB
    Inferring Phase 1: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.124s, Peak memory usage = 119.055MB
    Inferring Phase 2: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.063s, Peak memory usage = 119.055MB
    Inferring Phase 3: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.032s, Peak memory usage = 119.055MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.625s, Elapsed time = 0h 0m 0.626s, Peak memory usage = 119.055MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.206s, Peak memory usage = 119.055MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.155s, Peak memory usage = 119.055MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 132.750MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.562s, Elapsed time = 0h 0m 0.654s, Peak memory usage = 132.750MB
Generate output files:
    CPU time = 0h 0m 0.562s, Elapsed time = 0h 0m 0.963s, Peak memory usage = 134.734MB
Total Time and Memory Usage CPU time = 0h 0m 8s, Elapsed time = 0h 0m 9s, Peak memory usage = 134.734MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 371
I/O Buf 365
    IBUF 182
    OBUF 162
    TBUF 2
    IOBUF 16
    ELVDS_OBUF 1
    ELVDS_IOBUF 2
Register 3561
    DFFSE 1
    DFFRE 249
    DFFPE 66
    DFFCE 3245
LUT 2000
    LUT2 276
    LUT3 908
    LUT4 816
ALU 125
    ALU 125
INV 22
    INV 22
IOLOGIC 76
    IDES8_MEM 16
    OSER8 24
    OSER8_MEM 20
    IODELAY 16
BSRAM 8
    SDPB 4
    SDPX9B 4
CLOCK 4
    CLKDIV 1
    DQS 2
    DDRDLL 1

Resource Utilization Summary

Resource Usage Utilization
Logic 2147(2022 LUT, 125 ALU) / 138240 2%
Register 3561 / 139140 3%
  --Register as Latch 0 / 139140 0%
  --Register as FF 3561 / 139140 3%
BSRAM 8 / 340 3%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 memory_clk Base 10.000 100.000 0.000 5.000 memory_clk_ibuf/I
2 clk Base 10.000 100.000 0.000 5.000 clk_ibuf/I
3 gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk Generated 40.000 25.000 0.000 20.000 memory_clk_ibuf/I memory_clk gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 memory_clk 100.000(MHz) 1487.017(MHz) 1 TOP
2 clk 100.000(MHz) 289.277(MHz) 5 TOP
3 gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk 25.000(MHz) 223.924(MHz) 3 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 3.010
Data Arrival Time 1.857
Data Required Time 4.867
From gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_1_s0
To gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Launch Clk gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R]
Latch Clk memory_clk[F]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.274 0.274 tCL RR 3600 gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.571 0.297 tNET RR 1 gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_1_s0/CLK
0.846 0.275 tC2Q RR 14 gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_1_s0/Q
1.143 0.297 tNET RR 1 gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_1_s/I0
1.560 0.417 tINS RR 1 gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_1_s/F
1.857 0.297 tNET RR 1 gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
5.000 5.000 active clock edge time
5.000 0.000 memory_clk
5.000 0.000 tCL FF 1 memory_clk_ibuf/I
5.000 0.000 tINS FF 64 memory_clk_ibuf/O
5.277 0.277 tNET FF 1 gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
5.242 -0.035 tUnc gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
4.867 -0.375 tSu 1 gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Path Statistics:
Clock Skew: -0.294
Setup Relationship: 5.000
Logic Level: 2
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.297, 100.000%
Arrival Data Path Delay: cell: 0.417, 32.400%; route: 0.594, 46.186%; tC2Q: 0.275, 21.414%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.297, 100.000%

Path 2

Path Summary:
Slack 3.010
Data Arrival Time 1.857
Data Required Time 4.867
From gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_0_s0
To gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Launch Clk gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R]
Latch Clk memory_clk[F]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.274 0.274 tCL RR 3600 gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.571 0.297 tNET RR 1 gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_0_s0/CLK
0.846 0.275 tC2Q RR 11 gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_0_s0/Q
1.143 0.297 tNET RR 1 gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_0_s/I0
1.560 0.417 tINS RR 1 gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_0_s/F
1.857 0.297 tNET RR 1 gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
5.000 5.000 active clock edge time
5.000 0.000 memory_clk
5.000 0.000 tCL FF 1 memory_clk_ibuf/I
5.000 0.000 tINS FF 64 memory_clk_ibuf/O
5.277 0.277 tNET FF 1 gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
5.242 -0.035 tUnc gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
4.867 -0.375 tSu 1 gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Path Statistics:
Clock Skew: -0.294
Setup Relationship: 5.000
Logic Level: 2
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.297, 100.000%
Arrival Data Path Delay: cell: 0.417, 32.400%; route: 0.594, 46.186%; tC2Q: 0.275, 21.414%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.297, 100.000%

Path 3

Path Summary:
Slack 6.543
Data Arrival Time 3.708
Data Required Time 10.251
From gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_0_s3
To gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_9_s1
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 40 clk_ibuf/O
0.297 0.297 tNET RR 1 gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_0_s3/CLK
0.572 0.275 tC2Q RR 6 gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_0_s3/Q
0.869 0.297 tNET RR 1 gw3_top/u_ddr_phy_top/ddr_sync/n53_s2/I0
1.286 0.417 tINS RR 4 gw3_top/u_ddr_phy_top/ddr_sync/n53_s2/F
1.583 0.297 tNET RR 1 gw3_top/u_ddr_phy_top/ddr_sync/n50_s3/I1
1.992 0.409 tINS RR 4 gw3_top/u_ddr_phy_top/ddr_sync/n50_s3/F
2.289 0.297 tNET RR 1 gw3_top/u_ddr_phy_top/ddr_sync/n48_s4/I0
2.705 0.417 tINS RR 2 gw3_top/u_ddr_phy_top/ddr_sync/n48_s4/F
3.002 0.297 tNET RR 1 gw3_top/u_ddr_phy_top/ddr_sync/n48_s5/I1
3.411 0.409 tINS RR 1 gw3_top/u_ddr_phy_top/ddr_sync/n48_s5/F
3.708 0.297 tNET RR 1 gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_9_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 40 clk_ibuf/O
10.297 0.297 tNET RR 1 gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_9_s1/CLK
10.251 -0.046 tSu 1 gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_9_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.297, 100.000%
Arrival Data Path Delay: cell: 1.651, 48.390%; route: 1.485, 43.536%; tC2Q: 0.275, 8.074%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.297, 100.000%

Path 4

Path Summary:
Slack 6.543
Data Arrival Time 3.708
Data Required Time 10.251
From gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_0_s3
To gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_10_s1
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 40 clk_ibuf/O
0.297 0.297 tNET RR 1 gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_0_s3/CLK
0.572 0.275 tC2Q RR 6 gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_0_s3/Q
0.869 0.297 tNET RR 1 gw3_top/u_ddr_phy_top/ddr_sync/n53_s2/I0
1.286 0.417 tINS RR 4 gw3_top/u_ddr_phy_top/ddr_sync/n53_s2/F
1.583 0.297 tNET RR 1 gw3_top/u_ddr_phy_top/ddr_sync/n50_s3/I1
1.992 0.409 tINS RR 4 gw3_top/u_ddr_phy_top/ddr_sync/n50_s3/F
2.289 0.297 tNET RR 1 gw3_top/u_ddr_phy_top/ddr_sync/n48_s4/I0
2.705 0.417 tINS RR 2 gw3_top/u_ddr_phy_top/ddr_sync/n48_s4/F
3.002 0.297 tNET RR 1 gw3_top/u_ddr_phy_top/ddr_sync/n47_s1/I1
3.411 0.409 tINS RR 1 gw3_top/u_ddr_phy_top/ddr_sync/n47_s1/F
3.708 0.297 tNET RR 1 gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_10_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 40 clk_ibuf/O
10.297 0.297 tNET RR 1 gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_10_s1/CLK
10.251 -0.046 tSu 1 gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_10_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.297, 100.000%
Arrival Data Path Delay: cell: 1.651, 48.390%; route: 1.485, 43.536%; tC2Q: 0.275, 8.074%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.297, 100.000%

Path 5

Path Summary:
Slack 6.543
Data Arrival Time 3.708
Data Required Time 10.251
From gw3_top/u_ddr_phy_top/ddr_sync/cs_memsync_5_s0
To gw3_top/u_ddr_phy_top/ddr_sync/cs_memsync_0_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 40 clk_ibuf/O
0.297 0.297 tNET RR 1 gw3_top/u_ddr_phy_top/ddr_sync/cs_memsync_5_s0/CLK
0.572 0.275 tC2Q RR 5 gw3_top/u_ddr_phy_top/ddr_sync/cs_memsync_5_s0/Q
0.869 0.297 tNET RR 1 gw3_top/u_ddr_phy_top/ddr_sync/ns_memsync_2_s16/I0
1.286 0.417 tINS RR 3 gw3_top/u_ddr_phy_top/ddr_sync/ns_memsync_2_s16/F
1.583 0.297 tNET RR 1 gw3_top/u_ddr_phy_top/ddr_sync/ns_memsync_0_s15/I1
1.992 0.409 tINS RR 1 gw3_top/u_ddr_phy_top/ddr_sync/ns_memsync_0_s15/F
2.289 0.297 tNET RR 1 gw3_top/u_ddr_phy_top/ddr_sync/ns_memsync_0_s13/I1
2.697 0.409 tINS RR 1 gw3_top/u_ddr_phy_top/ddr_sync/ns_memsync_0_s13/F
2.994 0.297 tNET RR 1 gw3_top/u_ddr_phy_top/ddr_sync/ns_memsync_0_s12/I0
3.411 0.417 tINS RR 1 gw3_top/u_ddr_phy_top/ddr_sync/ns_memsync_0_s12/F
3.708 0.297 tNET RR 1 gw3_top/u_ddr_phy_top/ddr_sync/cs_memsync_0_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 40 clk_ibuf/O
10.297 0.297 tNET RR 1 gw3_top/u_ddr_phy_top/ddr_sync/cs_memsync_0_s0/CLK
10.251 -0.046 tSu 1 gw3_top/u_ddr_phy_top/ddr_sync/cs_memsync_0_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.297, 100.000%
Arrival Data Path Delay: cell: 1.651, 48.390%; route: 1.485, 43.536%; tC2Q: 0.275, 8.074%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.297, 100.000%