Synthesis Messages

Report Title GowinSynthesis Report
Design File F:\EMB_pub\embedded\risc_v\gorv32_plus\ref_design\1.0\FPGA_RefDesign\DK_START_GW5AST138_V2.1\axi_ddr\src\fifo_top_128to32\temp\FIFO\fifo_define.v
F:\EMB_pub\embedded\risc_v\gorv32_plus\ref_design\1.0\FPGA_RefDesign\DK_START_GW5AST138_V2.1\axi_ddr\src\fifo_top_128to32\temp\FIFO\fifo_parameter.v
D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\FIFO\data\edc.v
D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\FIFO\data\fifo.v
D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\FIFO\data\fifo_top.v
GowinSynthesis Constraints File ---
Tool Version V1.9.12.02 (64-bit)
Part Number GW5AST-LV138FPG676AC2/I1
Device GW5AST-138
Device Version C
Created Time Thu Mar 5 21:19:54 2026
Legal Announcement Copyright (C)2014-2026 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module fifo_top_128to32
Synthesis Process Running parser:
    CPU time = 0h 0m 0.468s, Elapsed time = 0h 0m 0.476s, Peak memory usage = 69.672MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 69.672MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 69.672MB
    Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 69.672MB
    Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 69.672MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 69.672MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 69.672MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 69.672MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 69.672MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 69.672MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 69.672MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 69.672MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.406s, Elapsed time = 0h 0m 0.478s, Peak memory usage = 86.520MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.098s, Peak memory usage = 86.520MB
Generate output files:
    CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.023s, Peak memory usage = 86.520MB
Total Time and Memory Usage CPU time = 0h 0m 0.98s, Elapsed time = 0h 0m 1s, Peak memory usage = 86.520MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 168
I/O Buf 168
    IBUF 133
    OBUF 35
Register 63
    DFFPE 5
    DFFCE 58
LUT 118
    LUT2 10
    LUT3 18
    LUT4 90
ALU 12
    ALU 12
INV 2
    INV 2
BSRAM 4
    SDPB 4

Resource Utilization Summary

Resource Usage Utilization
Logic 132(120 LUT, 12 ALU) / 138240 <1%
Register 63 / 139140 <1%
  --Register as Latch 0 / 139140 0%
  --Register as FF 63 / 139140 <1%
BSRAM 4 / 340 2%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 RdClk Base 10.000 100.000 0.000 5.000 RdClk_ibuf/I
2 WrClk Base 10.000 100.000 0.000 5.000 WrClk_ibuf/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 RdClk 100.000(MHz) 208.581(MHz) 8 TOP
2 WrClk 100.000(MHz) 180.874(MHz) 9 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 4.471
Data Arrival Time 5.780
Data Required Time 10.251
From fifo_inst/Small.wq2_rptr_6_s0
To fifo_inst/Almost_Full_s0
Launch Clk WrClk[R]
Latch Clk WrClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 WrClk
0.000 0.000 tCL RR 1 WrClk_ibuf/I
0.000 0.000 tINS RR 35 WrClk_ibuf/O
0.297 0.297 tNET RR 1 fifo_inst/Small.wq2_rptr_6_s0/CLK
0.572 0.275 tC2Q RR 4 fifo_inst/Small.wq2_rptr_6_s0/Q
0.869 0.297 tNET RR 1 fifo_inst/Small.rcount_w_5_s0/I0
1.286 0.417 tINS RR 4 fifo_inst/Small.rcount_w_5_s0/F
1.583 0.297 tNET RR 1 fifo_inst/Small.rcount_w_2_s0/I3
1.791 0.208 tINS RR 3 fifo_inst/Small.rcount_w_2_s0/F
2.088 0.297 tNET RR 1 fifo_inst/Small.rcount_w_1_s0/I1
2.497 0.409 tINS RR 1 fifo_inst/Small.rcount_w_1_s0/F
2.794 0.297 tNET RR 2 fifo_inst/wcnt_sub_1_s/I1
3.226 0.432 tINS RF 1 fifo_inst/wcnt_sub_1_s/COUT
3.226 0.000 tNET FF 2 fifo_inst/wcnt_sub_2_s/CIN
3.401 0.175 tINS FR 1 fifo_inst/wcnt_sub_2_s/SUM
3.698 0.297 tNET RR 1 fifo_inst/awfull_val_s2/I2
4.063 0.365 tINS RR 1 fifo_inst/awfull_val_s2/F
4.360 0.297 tNET RR 1 fifo_inst/awfull_val_s1/I1
4.769 0.409 tINS RR 1 fifo_inst/awfull_val_s1/F
5.066 0.297 tNET RR 1 fifo_inst/awfull_val_s3/I0
5.483 0.417 tINS RR 1 fifo_inst/awfull_val_s3/F
5.780 0.297 tNET RR 1 fifo_inst/Almost_Full_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 WrClk
10.000 0.000 tCL RR 1 WrClk_ibuf/I
10.000 0.000 tINS RR 35 WrClk_ibuf/O
10.297 0.297 tNET RR 1 fifo_inst/Almost_Full_s0/CLK
10.251 -0.046 tSu 1 fifo_inst/Almost_Full_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.297, 100.000%
Arrival Data Path Delay: cell: 2.831, 51.641%; route: 2.376, 43.336%; tC2Q: 0.275, 5.023%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.297, 100.000%

Path 2

Path Summary:
Slack 5.206
Data Arrival Time 5.045
Data Required Time 10.251
From fifo_inst/Empty_s0
To fifo_inst/Empty_s0
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.000 0.000 tINS RR 36 RdClk_ibuf/O
0.297 0.297 tNET RR 1 fifo_inst/Empty_s0/CLK
0.572 0.275 tC2Q RR 5 fifo_inst/Empty_s0/Q
0.869 0.297 tNET RR 1 fifo_inst/Small.rgraynext_0_s1/I0
1.286 0.417 tINS RR 6 fifo_inst/Small.rgraynext_0_s1/F
1.583 0.297 tNET RR 1 fifo_inst/Small.rgraynext_2_s1/I2
1.948 0.365 tINS RR 5 fifo_inst/Small.rgraynext_2_s1/F
2.245 0.297 tNET RR 1 fifo_inst/rbin_num_next_6_s3/I2
2.611 0.365 tINS RR 2 fifo_inst/rbin_num_next_6_s3/F
2.908 0.297 tNET RR 1 fifo_inst/Small.rgraynext_4_s0/I2
3.273 0.365 tINS RR 2 fifo_inst/Small.rgraynext_4_s0/F
3.570 0.297 tNET RR 2 fifo_inst/n598_s0/I0
3.999 0.428 tINS RF 1 fifo_inst/n598_s0/COUT
3.999 0.000 tNET FF 2 fifo_inst/n599_s0/CIN
4.035 0.036 tINS FR 1 fifo_inst/n599_s0/COUT
4.332 0.297 tNET RR 1 fifo_inst/rempty_val_s1/I0
4.748 0.417 tINS RR 1 fifo_inst/rempty_val_s1/F
5.045 0.297 tNET RR 1 fifo_inst/Empty_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.000 0.000 tINS RR 36 RdClk_ibuf/O
10.297 0.297 tNET RR 1 fifo_inst/Empty_s0/CLK
10.251 -0.046 tSu 1 fifo_inst/Empty_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 8
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.297, 100.000%
Arrival Data Path Delay: cell: 2.394, 50.417%; route: 2.079, 43.783%; tC2Q: 0.275, 5.800%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.297, 100.000%

Path 3

Path Summary:
Slack 6.551
Data Arrival Time 3.700
Data Required Time 10.251
From fifo_inst/Full_s0
To fifo_inst/Full_s0
Launch Clk WrClk[R]
Latch Clk WrClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 WrClk
0.000 0.000 tCL RR 1 WrClk_ibuf/I
0.000 0.000 tINS RR 35 WrClk_ibuf/O
0.297 0.297 tNET RR 1 fifo_inst/Full_s0/CLK
0.572 0.275 tC2Q RR 6 fifo_inst/Full_s0/Q
0.869 0.297 tNET RR 1 fifo_inst/Small.wgraynext_2_s1/I0
1.286 0.417 tINS RR 8 fifo_inst/Small.wgraynext_2_s1/F
1.583 0.297 tNET RR 1 fifo_inst/Small.wgraynext_2_s0/I1
1.992 0.409 tINS RR 2 fifo_inst/Small.wgraynext_2_s0/F
2.289 0.297 tNET RR 1 fifo_inst/wfull_val_s2/I1
2.697 0.409 tINS RR 1 fifo_inst/wfull_val_s2/F
2.994 0.297 tNET RR 1 fifo_inst/wfull_val_s0/I1
3.403 0.409 tINS RR 1 fifo_inst/wfull_val_s0/F
3.700 0.297 tNET RR 1 fifo_inst/Full_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 WrClk
10.000 0.000 tCL RR 1 WrClk_ibuf/I
10.000 0.000 tINS RR 35 WrClk_ibuf/O
10.297 0.297 tNET RR 1 fifo_inst/Full_s0/CLK
10.251 -0.046 tSu 1 fifo_inst/Full_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.297, 100.000%
Arrival Data Path Delay: cell: 1.642, 48.268%; route: 1.485, 43.639%; tC2Q: 0.275, 8.093%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.297, 100.000%

Path 4

Path Summary:
Slack 6.681
Data Arrival Time 3.570
Data Required Time 10.251
From fifo_inst/Empty_s0
To fifo_inst/Small.rptr_4_s0
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.000 0.000 tINS RR 36 RdClk_ibuf/O
0.297 0.297 tNET RR 1 fifo_inst/Empty_s0/CLK
0.572 0.275 tC2Q RR 5 fifo_inst/Empty_s0/Q
0.869 0.297 tNET RR 1 fifo_inst/Small.rgraynext_0_s1/I0
1.286 0.417 tINS RR 6 fifo_inst/Small.rgraynext_0_s1/F
1.583 0.297 tNET RR 1 fifo_inst/Small.rgraynext_2_s1/I2
1.948 0.365 tINS RR 5 fifo_inst/Small.rgraynext_2_s1/F
2.245 0.297 tNET RR 1 fifo_inst/rbin_num_next_6_s3/I2
2.611 0.365 tINS RR 2 fifo_inst/rbin_num_next_6_s3/F
2.908 0.297 tNET RR 1 fifo_inst/Small.rgraynext_4_s0/I2
3.273 0.365 tINS RR 2 fifo_inst/Small.rgraynext_4_s0/F
3.570 0.297 tNET RR 1 fifo_inst/Small.rptr_4_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.000 0.000 tINS RR 36 RdClk_ibuf/O
10.297 0.297 tNET RR 1 fifo_inst/Small.rptr_4_s0/CLK
10.251 -0.046 tSu 1 fifo_inst/Small.rptr_4_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.297, 100.000%
Arrival Data Path Delay: cell: 1.513, 46.219%; route: 1.485, 45.367%; tC2Q: 0.275, 8.414%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.297, 100.000%

Path 5

Path Summary:
Slack 6.795
Data Arrival Time 3.456
Data Required Time 10.251
From fifo_inst/Empty_s0
To fifo_inst/Small.rptr_5_s0
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.000 0.000 tINS RR 36 RdClk_ibuf/O
0.297 0.297 tNET RR 1 fifo_inst/Empty_s0/CLK
0.572 0.275 tC2Q RR 5 fifo_inst/Empty_s0/Q
0.869 0.297 tNET RR 1 fifo_inst/Small.rgraynext_0_s1/I0
1.286 0.417 tINS RR 6 fifo_inst/Small.rgraynext_0_s1/F
1.583 0.297 tNET RR 1 fifo_inst/Small.rgraynext_2_s1/I2
1.948 0.365 tINS RR 5 fifo_inst/Small.rgraynext_2_s1/F
2.245 0.297 tNET RR 1 fifo_inst/Small.rgraynext_5_s1/I3
2.453 0.208 tINS RR 3 fifo_inst/Small.rgraynext_5_s1/F
2.750 0.297 tNET RR 1 fifo_inst/Small.rgraynext_5_s0/I1
3.159 0.409 tINS RR 2 fifo_inst/Small.rgraynext_5_s0/F
3.456 0.297 tNET RR 1 fifo_inst/Small.rptr_5_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.000 0.000 tINS RR 36 RdClk_ibuf/O
10.297 0.297 tNET RR 1 fifo_inst/Small.rptr_5_s0/CLK
10.251 -0.046 tSu 1 fifo_inst/Small.rptr_5_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.297, 100.000%
Arrival Data Path Delay: cell: 1.399, 44.274%; route: 1.485, 47.008%; tC2Q: 0.275, 8.718%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.297, 100.000%