Synthesis Messages

Report Title GowinSynthesis Report
Design File F:\EMB_pub\embedded\risc_v\gorv32_plus\ref_design\1.0\FPGA_RefDesign\DK_START_GW5AST138_V2.1\axi_ddr\src\fifo_top_32to128\temp\FIFO\fifo_define.v
F:\EMB_pub\embedded\risc_v\gorv32_plus\ref_design\1.0\FPGA_RefDesign\DK_START_GW5AST138_V2.1\axi_ddr\src\fifo_top_32to128\temp\FIFO\fifo_parameter.v
D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\FIFO\data\edc.v
D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\FIFO\data\fifo.v
D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\FIFO\data\fifo_top.v
GowinSynthesis Constraints File ---
Tool Version V1.9.12.02 (64-bit)
Part Number GW5AST-LV138FPG676AC2/I1
Device GW5AST-138
Device Version C
Created Time Thu Mar 5 21:19:42 2026
Legal Announcement Copyright (C)2014-2026 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module fifo_top_32to128
Synthesis Process Running parser:
    CPU time = 0h 0m 0.484s, Elapsed time = 0h 0m 0.581s, Peak memory usage = 76.688MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 76.688MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 76.688MB
    Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 76.688MB
    Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 76.688MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.022s, Peak memory usage = 76.688MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 76.688MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 76.688MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 76.688MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 76.688MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 76.688MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 76.688MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.312s, Elapsed time = 0h 0m 0.38s, Peak memory usage = 91.781MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.102s, Peak memory usage = 91.781MB
Generate output files:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.022s, Peak memory usage = 91.781MB
Total Time and Memory Usage CPU time = 0h 0m 0.949s, Elapsed time = 0h 0m 1s, Peak memory usage = 91.781MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 198
I/O Buf 198
    IBUF 41
    OBUF 157
Register 73
    DFFPE 6
    DFFCE 67
LUT 69
    LUT2 13
    LUT3 21
    LUT4 35
ALU 20
    ALU 20
INV 3
    INV 3
BSRAM 4
    SDPX9B 4

Resource Utilization Summary

Resource Usage Utilization
Logic 92(72 LUT, 20 ALU) / 138240 <1%
Register 73 / 139140 <1%
  --Register as Latch 0 / 139140 0%
  --Register as FF 73 / 139140 <1%
BSRAM 4 / 340 2%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 RdClk Base 10.000 100.000 0.000 5.000 RdClk_ibuf/I
2 WrClk Base 10.000 100.000 0.000 5.000 WrClk_ibuf/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 RdClk 100.000(MHz) 199.517(MHz) 8 TOP
2 WrClk 100.000(MHz) 216.043(MHz) 7 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 4.988
Data Arrival Time 5.263
Data Required Time 10.251
From fifo_inst/Empty_s0
To fifo_inst/Empty_s0
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.000 0.000 tINS RR 35 RdClk_ibuf/O
0.297 0.297 tNET RR 1 fifo_inst/Empty_s0/CLK
0.572 0.275 tC2Q RR 3 fifo_inst/Empty_s0/Q
0.869 0.297 tNET RR 1 fifo_inst/rbin_num_next_0_s4/I0
1.286 0.417 tINS RR 11 fifo_inst/rbin_num_next_0_s4/F
1.583 0.297 tNET RR 1 fifo_inst/rbin_num_next_2_s5/I0
2.000 0.417 tINS RR 4 fifo_inst/rbin_num_next_2_s5/F
2.297 0.297 tNET RR 1 fifo_inst/rbin_num_next_3_s4/I1
2.705 0.409 tINS RR 6 fifo_inst/rbin_num_next_3_s4/F
3.002 0.297 tNET RR 1 fifo_inst/Big.rgraynext_3_s0/I0
3.419 0.417 tINS RR 2 fifo_inst/Big.rgraynext_3_s0/F
3.716 0.297 tNET RR 2 fifo_inst/n730_s0/I0
4.144 0.428 tINS RF 1 fifo_inst/n730_s0/COUT
4.144 0.000 tNET FF 2 fifo_inst/n731_s0/CIN
4.180 0.036 tINS FR 1 fifo_inst/n731_s0/COUT
4.180 0.000 tNET RR 2 fifo_inst/n732_s0/CIN
4.216 0.036 tINS RR 1 fifo_inst/n732_s0/COUT
4.216 0.000 tNET RR 2 fifo_inst/n733_s0/CIN
4.252 0.036 tINS RR 2 fifo_inst/n733_s0/COUT
4.549 0.297 tNET RR 1 fifo_inst/rempty_val_s1/I0
4.966 0.417 tINS RR 1 fifo_inst/rempty_val_s1/F
5.263 0.297 tNET RR 1 fifo_inst/Empty_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.000 0.000 tINS RR 35 RdClk_ibuf/O
10.297 0.297 tNET RR 1 fifo_inst/Empty_s0/CLK
10.251 -0.046 tSu 1 fifo_inst/Empty_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 8
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.297, 100.000%
Arrival Data Path Delay: cell: 2.612, 52.592%; route: 2.079, 41.863%; tC2Q: 0.275, 5.545%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.297, 100.000%

Path 2

Path Summary:
Slack 5.019
Data Arrival Time 5.212
Data Required Time 10.231
From fifo_inst/Empty_s0
To fifo_inst/Big.mem_Big.mem_0_3_s
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.000 0.000 tINS RR 35 RdClk_ibuf/O
0.297 0.297 tNET RR 1 fifo_inst/Empty_s0/CLK
0.572 0.275 tC2Q RR 3 fifo_inst/Empty_s0/Q
0.869 0.297 tNET RR 1 fifo_inst/rbin_num_next_0_s4/I0
1.286 0.417 tINS RR 11 fifo_inst/rbin_num_next_0_s4/F
1.583 0.297 tNET RR 1 fifo_inst/rbin_num_next_2_s5/I0
2.000 0.417 tINS RR 4 fifo_inst/rbin_num_next_2_s5/F
2.297 0.297 tNET RR 1 fifo_inst/rbin_num_next_3_s4/I1
2.705 0.409 tINS RR 6 fifo_inst/rbin_num_next_3_s4/F
3.002 0.297 tNET RR 1 fifo_inst/Big.rgraynext_3_s0/I0
3.419 0.417 tINS RR 2 fifo_inst/Big.rgraynext_3_s0/F
3.716 0.297 tNET RR 2 fifo_inst/n730_s0/I0
4.144 0.428 tINS RF 1 fifo_inst/n730_s0/COUT
4.144 0.000 tNET FF 2 fifo_inst/n731_s0/CIN
4.180 0.036 tINS FR 1 fifo_inst/n731_s0/COUT
4.180 0.000 tNET RR 2 fifo_inst/n732_s0/CIN
4.216 0.036 tINS RR 1 fifo_inst/n732_s0/COUT
4.216 0.000 tNET RR 2 fifo_inst/n733_s0/CIN
4.252 0.036 tINS RR 2 fifo_inst/n733_s0/COUT
4.549 0.297 tNET RR 1 fifo_inst/n31_s1/I2
4.915 0.365 tINS RR 4 fifo_inst/n31_s1/F
5.212 0.297 tNET RR 1 fifo_inst/Big.mem_Big.mem_0_3_s/CEB
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.000 0.000 tINS RR 35 RdClk_ibuf/O
10.297 0.297 tNET RR 1 fifo_inst/Big.mem_Big.mem_0_3_s/CLKB
10.231 -0.066 tSu 1 fifo_inst/Big.mem_Big.mem_0_3_s
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 8
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.297, 100.000%
Arrival Data Path Delay: cell: 2.560, 52.097%; route: 2.079, 42.300%; tC2Q: 0.275, 5.603%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.297, 100.000%

Path 3

Path Summary:
Slack 5.019
Data Arrival Time 5.212
Data Required Time 10.231
From fifo_inst/Empty_s0
To fifo_inst/Big.mem_Big.mem_0_2_s
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.000 0.000 tINS RR 35 RdClk_ibuf/O
0.297 0.297 tNET RR 1 fifo_inst/Empty_s0/CLK
0.572 0.275 tC2Q RR 3 fifo_inst/Empty_s0/Q
0.869 0.297 tNET RR 1 fifo_inst/rbin_num_next_0_s4/I0
1.286 0.417 tINS RR 11 fifo_inst/rbin_num_next_0_s4/F
1.583 0.297 tNET RR 1 fifo_inst/rbin_num_next_2_s5/I0
2.000 0.417 tINS RR 4 fifo_inst/rbin_num_next_2_s5/F
2.297 0.297 tNET RR 1 fifo_inst/rbin_num_next_3_s4/I1
2.705 0.409 tINS RR 6 fifo_inst/rbin_num_next_3_s4/F
3.002 0.297 tNET RR 1 fifo_inst/Big.rgraynext_3_s0/I0
3.419 0.417 tINS RR 2 fifo_inst/Big.rgraynext_3_s0/F
3.716 0.297 tNET RR 2 fifo_inst/n730_s0/I0
4.144 0.428 tINS RF 1 fifo_inst/n730_s0/COUT
4.144 0.000 tNET FF 2 fifo_inst/n731_s0/CIN
4.180 0.036 tINS FR 1 fifo_inst/n731_s0/COUT
4.180 0.000 tNET RR 2 fifo_inst/n732_s0/CIN
4.216 0.036 tINS RR 1 fifo_inst/n732_s0/COUT
4.216 0.000 tNET RR 2 fifo_inst/n733_s0/CIN
4.252 0.036 tINS RR 2 fifo_inst/n733_s0/COUT
4.549 0.297 tNET RR 1 fifo_inst/n31_s1/I2
4.915 0.365 tINS RR 4 fifo_inst/n31_s1/F
5.212 0.297 tNET RR 1 fifo_inst/Big.mem_Big.mem_0_2_s/CEB
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.000 0.000 tINS RR 35 RdClk_ibuf/O
10.297 0.297 tNET RR 1 fifo_inst/Big.mem_Big.mem_0_2_s/CLKB
10.231 -0.066 tSu 1 fifo_inst/Big.mem_Big.mem_0_2_s
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 8
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.297, 100.000%
Arrival Data Path Delay: cell: 2.560, 52.097%; route: 2.079, 42.300%; tC2Q: 0.275, 5.603%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.297, 100.000%

Path 4

Path Summary:
Slack 5.019
Data Arrival Time 5.212
Data Required Time 10.231
From fifo_inst/Empty_s0
To fifo_inst/Big.mem_Big.mem_0_1_s
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.000 0.000 tINS RR 35 RdClk_ibuf/O
0.297 0.297 tNET RR 1 fifo_inst/Empty_s0/CLK
0.572 0.275 tC2Q RR 3 fifo_inst/Empty_s0/Q
0.869 0.297 tNET RR 1 fifo_inst/rbin_num_next_0_s4/I0
1.286 0.417 tINS RR 11 fifo_inst/rbin_num_next_0_s4/F
1.583 0.297 tNET RR 1 fifo_inst/rbin_num_next_2_s5/I0
2.000 0.417 tINS RR 4 fifo_inst/rbin_num_next_2_s5/F
2.297 0.297 tNET RR 1 fifo_inst/rbin_num_next_3_s4/I1
2.705 0.409 tINS RR 6 fifo_inst/rbin_num_next_3_s4/F
3.002 0.297 tNET RR 1 fifo_inst/Big.rgraynext_3_s0/I0
3.419 0.417 tINS RR 2 fifo_inst/Big.rgraynext_3_s0/F
3.716 0.297 tNET RR 2 fifo_inst/n730_s0/I0
4.144 0.428 tINS RF 1 fifo_inst/n730_s0/COUT
4.144 0.000 tNET FF 2 fifo_inst/n731_s0/CIN
4.180 0.036 tINS FR 1 fifo_inst/n731_s0/COUT
4.180 0.000 tNET RR 2 fifo_inst/n732_s0/CIN
4.216 0.036 tINS RR 1 fifo_inst/n732_s0/COUT
4.216 0.000 tNET RR 2 fifo_inst/n733_s0/CIN
4.252 0.036 tINS RR 2 fifo_inst/n733_s0/COUT
4.549 0.297 tNET RR 1 fifo_inst/n31_s1/I2
4.915 0.365 tINS RR 4 fifo_inst/n31_s1/F
5.212 0.297 tNET RR 1 fifo_inst/Big.mem_Big.mem_0_1_s/CEB
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.000 0.000 tINS RR 35 RdClk_ibuf/O
10.297 0.297 tNET RR 1 fifo_inst/Big.mem_Big.mem_0_1_s/CLKB
10.231 -0.066 tSu 1 fifo_inst/Big.mem_Big.mem_0_1_s
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 8
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.297, 100.000%
Arrival Data Path Delay: cell: 2.560, 52.097%; route: 2.079, 42.300%; tC2Q: 0.275, 5.603%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.297, 100.000%

Path 5

Path Summary:
Slack 5.019
Data Arrival Time 5.212
Data Required Time 10.231
From fifo_inst/Empty_s0
To fifo_inst/Big.mem_Big.mem_0_0_s
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.000 0.000 tINS RR 35 RdClk_ibuf/O
0.297 0.297 tNET RR 1 fifo_inst/Empty_s0/CLK
0.572 0.275 tC2Q RR 3 fifo_inst/Empty_s0/Q
0.869 0.297 tNET RR 1 fifo_inst/rbin_num_next_0_s4/I0
1.286 0.417 tINS RR 11 fifo_inst/rbin_num_next_0_s4/F
1.583 0.297 tNET RR 1 fifo_inst/rbin_num_next_2_s5/I0
2.000 0.417 tINS RR 4 fifo_inst/rbin_num_next_2_s5/F
2.297 0.297 tNET RR 1 fifo_inst/rbin_num_next_3_s4/I1
2.705 0.409 tINS RR 6 fifo_inst/rbin_num_next_3_s4/F
3.002 0.297 tNET RR 1 fifo_inst/Big.rgraynext_3_s0/I0
3.419 0.417 tINS RR 2 fifo_inst/Big.rgraynext_3_s0/F
3.716 0.297 tNET RR 2 fifo_inst/n730_s0/I0
4.144 0.428 tINS RF 1 fifo_inst/n730_s0/COUT
4.144 0.000 tNET FF 2 fifo_inst/n731_s0/CIN
4.180 0.036 tINS FR 1 fifo_inst/n731_s0/COUT
4.180 0.000 tNET RR 2 fifo_inst/n732_s0/CIN
4.216 0.036 tINS RR 1 fifo_inst/n732_s0/COUT
4.216 0.000 tNET RR 2 fifo_inst/n733_s0/CIN
4.252 0.036 tINS RR 2 fifo_inst/n733_s0/COUT
4.549 0.297 tNET RR 1 fifo_inst/n31_s1/I2
4.915 0.365 tINS RR 4 fifo_inst/n31_s1/F
5.212 0.297 tNET RR 1 fifo_inst/Big.mem_Big.mem_0_0_s/CEB
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.000 0.000 tINS RR 35 RdClk_ibuf/O
10.297 0.297 tNET RR 1 fifo_inst/Big.mem_Big.mem_0_0_s/CLKB
10.231 -0.066 tSu 1 fifo_inst/Big.mem_Big.mem_0_0_s
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 8
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.297, 100.000%
Arrival Data Path Delay: cell: 2.560, 52.097%; route: 2.079, 42.300%; tC2Q: 0.275, 5.603%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.297, 100.000%