Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\custom\gorv32_plus_const.vh D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\ahb_bridge.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\apb_bridge.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\apb_gpio.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\apb_iic.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\apb_pit.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\apb_sd.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\apb_spi.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\apb_uart.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\apb_wdt.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\axi_bridge.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\bus_matrix.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\gorv32_plus.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\gorv32_plus_top.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\misc.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\onchip_ram.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\riscv_plus_core.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.12.02 (64-bit) |
| Part Number | GW5AST-LV138FPG676AC2/I1 |
| Device | GW5AST-138 |
| Device Version | C |
| Created Time | Thu Mar 5 21:22:29 2026 |
| Legal Announcement | Copyright (C)2014-2026 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | Gowin_GoRV32_Plus_Top |
| Synthesis Process | Running parser: CPU time = 0h 0m 6s, Elapsed time = 0h 0m 6s, Peak memory usage = 464.934MB Running netlist conversion: CPU time = 0h 0m 0.906s, Elapsed time = 0h 0m 0.905s, Peak memory usage = 464.934MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 9s, Elapsed time = 0h 0m 9s, Peak memory usage = 464.934MB Optimizing Phase 1: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 464.934MB Optimizing Phase 2: CPU time = 0h 0m 14s, Elapsed time = 0h 0m 14s, Peak memory usage = 464.934MB Running inference: Inferring Phase 0: CPU time = 0h 0m 16s, Elapsed time = 0h 0m 16s, Peak memory usage = 464.934MB Inferring Phase 1: CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s, Peak memory usage = 464.934MB Inferring Phase 2: CPU time = 0h 0m 0.343s, Elapsed time = 0h 0m 0.364s, Peak memory usage = 464.934MB Inferring Phase 3: CPU time = 0h 0m 0.187s, Elapsed time = 0h 0m 0.19s, Peak memory usage = 464.934MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 7s, Elapsed time = 0h 0m 7s, Peak memory usage = 464.934MB Tech-Mapping Phase 1: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 464.934MB Tech-Mapping Phase 2: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 464.934MB Tech-Mapping Phase 3: CPU time = 0h 1m 10s, Elapsed time = 0h 1m 11s, Peak memory usage = 464.934MB Tech-Mapping Phase 4: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 464.934MB Generate output files: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 3s, Peak memory usage = 464.934MB |
| Total Time and Memory Usage | CPU time = 0h 2m 15s, Elapsed time = 0h 2m 17s, Peak memory usage = 464.934MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 345 |
| I/O Buf | 337 |
| IBUF | 97 |
| OBUF | 234 |
| IOBUF | 6 |
| Register | 11623 |
| DFFSE | 130 |
| DFFRE | 6335 |
| DFFPE | 109 |
| DFFCE | 5048 |
| DLCE | 1 |
| LUT | 16729 |
| LUT2 | 1470 |
| LUT3 | 6792 |
| LUT4 | 8467 |
| ALU | 2462 |
| ALU | 2462 |
| SSRAM | 253 |
| RAM16SDP1 | 21 |
| RAM16SDP2 | 4 |
| RAM16SDP4 | 228 |
| INV | 71 |
| INV | 71 |
| DSP | |
| MULTALU27X18 | 9 |
| MULT27X36 | 4 |
| BSRAM | 67 |
| SP | 32 |
| SDPB | 29 |
| SDPX9B | 6 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 20780(16800 LUT, 2462 ALU, 253 RAM16) / 138240 | 16% |
| Register | 11623 / 139140 | 9% |
| --Register as Latch | 1 / 139140 | <1% |
| --Register as FF | 11622 / 139140 | 9% |
| BSRAM | 67 / 340 | 20% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | axi_clk | Base | 10.000 | 100.000 | 0.000 | 5.000 | axi_clk_ibuf/I | ||
| 2 | JTAG_TCK | Base | 10.000 | 100.000 | 0.000 | 5.000 | JTAG_TCK_ibuf/I | ||
| 3 | ahb_clk | Base | 10.000 | 100.000 | 0.000 | 5.000 | ahb_clk_ibuf/I | ||
| 4 | apb_clk | Base | 10.000 | 100.000 | 0.000 | 5.000 | apb_clk_ibuf/I | ||
| 5 | FLASH_QSPI_CLK | Base | 10.000 | 100.000 | 0.000 | 5.000 | FLASH_QSPI_CLK_iobuf/IO |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | axi_clk | 100.000(MHz) | 75.222(MHz) | 21 | TOP |
| 2 | JTAG_TCK | 100.000(MHz) | 147.323(MHz) | 5 | TOP |
| 3 | ahb_clk | 100.000(MHz) | 107.385(MHz) | 13 | TOP |
| 4 | apb_clk | 100.000(MHz) | 89.751(MHz) | 9 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | -3.294 |
| Data Arrival Time | 13.545 |
| Data Required Time | 10.251 |
| From | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_input_payload_exactMask_1_s0 |
| To | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_UF_s0 |
| Launch Clk | axi_clk[R] |
| Latch Clk | axi_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | axi_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | axi_clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 10117 | axi_clk_ibuf/O |
| 0.297 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_input_payload_exactMask_1_s0/CLK |
| 0.572 | 0.275 | tC2Q | RR | 3 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_input_payload_exactMask_1_s0/Q |
| 0.869 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adderMantissa_0_s1/I0 |
| 1.286 | 0.417 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adderMantissa_0_s1/F |
| 1.583 | 0.297 | tNET | RR | 2 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_0_s/I0 |
| 2.147 | 0.564 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_0_s/SUM |
| 2.444 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_3_s5/I0 |
| 2.861 | 0.417 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_3_s5/F |
| 3.158 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_6_s5/I3 |
| 3.366 | 0.208 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_6_s5/F |
| 3.663 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_9_s5/I3 |
| 3.871 | 0.208 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_9_s5/F |
| 4.168 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_12_s5/I3 |
| 4.376 | 0.208 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_12_s5/F |
| 4.673 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_15_s5/I3 |
| 4.881 | 0.208 | tINS | RR | 7 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_15_s5/F |
| 5.178 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_21_s5/I3 |
| 5.386 | 0.208 | tINS | RR | 7 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_21_s5/F |
| 5.683 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_30_s5/I1 |
| 6.091 | 0.409 | tINS | RR | 3 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_30_s5/F |
| 6.388 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_33_s5/I3 |
| 6.596 | 0.208 | tINS | RR | 15 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_33_s5/F |
| 6.893 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_51_s5/I0 |
| 7.310 | 0.417 | tINS | RR | 5 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_51_s5/F |
| 7.607 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_54_s5/I3 |
| 7.815 | 0.208 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_54_s5/F |
| 8.112 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_54_s4/I0 |
| 8.528 | 0.417 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_54_s4/F |
| 8.825 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s9/I1 |
| 9.234 | 0.409 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s9/F |
| 9.531 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s7/I1 |
| 9.940 | 0.409 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s7/F |
| 10.237 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s6/I0 |
| 10.653 | 0.417 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s6/F |
| 10.950 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s5/I0 |
| 11.367 | 0.417 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s5/F |
| 11.664 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s4/I0 |
| 12.081 | 0.417 | tINS | RR | 3 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s4/F |
| 12.378 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s3/I2 |
| 12.743 | 0.365 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s3/F |
| 13.040 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_uf_s1/I3 |
| 13.248 | 0.208 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_uf_s1/F |
| 13.545 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_UF_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | |||
| 10.000 | 0.000 | axi_clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | axi_clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 10117 | axi_clk_ibuf/O |
| 10.297 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_UF_s0/CLK |
| 10.251 | -0.046 | tSu | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_UF_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 21 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.297, 100.000% |
| Arrival Data Path Delay: | cell: 6.736, 50.842%; route: 6.237, 47.079%; tC2Q: 0.275, 2.079% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.297, 100.000% |
Path 2
Path Summary:| Slack | -3.294 |
| Data Arrival Time | 13.545 |
| Data Required Time | 10.251 |
| From | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_input_payload_exactMask_1_s0 |
| To | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_NX_s0 |
| Launch Clk | axi_clk[R] |
| Latch Clk | axi_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | axi_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | axi_clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 10117 | axi_clk_ibuf/O |
| 0.297 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_input_payload_exactMask_1_s0/CLK |
| 0.572 | 0.275 | tC2Q | RR | 3 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_input_payload_exactMask_1_s0/Q |
| 0.869 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adderMantissa_0_s1/I0 |
| 1.286 | 0.417 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adderMantissa_0_s1/F |
| 1.583 | 0.297 | tNET | RR | 2 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_0_s/I0 |
| 2.147 | 0.564 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_0_s/SUM |
| 2.444 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_3_s5/I0 |
| 2.861 | 0.417 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_3_s5/F |
| 3.158 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_6_s5/I3 |
| 3.366 | 0.208 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_6_s5/F |
| 3.663 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_9_s5/I3 |
| 3.871 | 0.208 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_9_s5/F |
| 4.168 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_12_s5/I3 |
| 4.376 | 0.208 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_12_s5/F |
| 4.673 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_15_s5/I3 |
| 4.881 | 0.208 | tINS | RR | 7 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_15_s5/F |
| 5.178 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_21_s5/I3 |
| 5.386 | 0.208 | tINS | RR | 7 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_21_s5/F |
| 5.683 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_30_s5/I1 |
| 6.091 | 0.409 | tINS | RR | 3 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_30_s5/F |
| 6.388 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_33_s5/I3 |
| 6.596 | 0.208 | tINS | RR | 15 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_33_s5/F |
| 6.893 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_51_s5/I0 |
| 7.310 | 0.417 | tINS | RR | 5 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_51_s5/F |
| 7.607 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_54_s5/I3 |
| 7.815 | 0.208 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_54_s5/F |
| 8.112 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_54_s4/I0 |
| 8.528 | 0.417 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_54_s4/F |
| 8.825 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s9/I1 |
| 9.234 | 0.409 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s9/F |
| 9.531 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s7/I1 |
| 9.940 | 0.409 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s7/F |
| 10.237 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s6/I0 |
| 10.653 | 0.417 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s6/F |
| 10.950 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s5/I0 |
| 11.367 | 0.417 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s5/F |
| 11.664 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s4/I0 |
| 12.081 | 0.417 | tINS | RR | 3 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s4/F |
| 12.378 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s3/I2 |
| 12.743 | 0.365 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s3/F |
| 13.040 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_nx_s1/I3 |
| 13.248 | 0.208 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_nx_s1/F |
| 13.545 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_NX_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | |||
| 10.000 | 0.000 | axi_clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | axi_clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 10117 | axi_clk_ibuf/O |
| 10.297 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_NX_s0/CLK |
| 10.251 | -0.046 | tSu | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_NX_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 21 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.297, 100.000% |
| Arrival Data Path Delay: | cell: 6.736, 50.842%; route: 6.237, 47.079%; tC2Q: 0.275, 2.079% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.297, 100.000% |
Path 3
Path Summary:| Slack | -3.294 |
| Data Arrival Time | 13.545 |
| Data Required Time | 10.251 |
| From | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_input_payload_exactMask_1_s0 |
| To | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_exponent_0_s0 |
| Launch Clk | axi_clk[R] |
| Latch Clk | axi_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | axi_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | axi_clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 10117 | axi_clk_ibuf/O |
| 0.297 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_input_payload_exactMask_1_s0/CLK |
| 0.572 | 0.275 | tC2Q | RR | 3 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_input_payload_exactMask_1_s0/Q |
| 0.869 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adderMantissa_0_s1/I0 |
| 1.286 | 0.417 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adderMantissa_0_s1/F |
| 1.583 | 0.297 | tNET | RR | 2 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_0_s/I0 |
| 2.147 | 0.564 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_0_s/SUM |
| 2.444 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_3_s5/I0 |
| 2.861 | 0.417 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_3_s5/F |
| 3.158 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_6_s5/I3 |
| 3.366 | 0.208 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_6_s5/F |
| 3.663 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_9_s5/I3 |
| 3.871 | 0.208 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_9_s5/F |
| 4.168 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_12_s5/I3 |
| 4.376 | 0.208 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_12_s5/F |
| 4.673 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_15_s5/I3 |
| 4.881 | 0.208 | tINS | RR | 7 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_15_s5/F |
| 5.178 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_21_s5/I3 |
| 5.386 | 0.208 | tINS | RR | 7 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_21_s5/F |
| 5.683 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_30_s5/I1 |
| 6.091 | 0.409 | tINS | RR | 3 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_30_s5/F |
| 6.388 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_33_s5/I3 |
| 6.596 | 0.208 | tINS | RR | 15 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_33_s5/F |
| 6.893 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_51_s5/I0 |
| 7.310 | 0.417 | tINS | RR | 5 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_51_s5/F |
| 7.607 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_54_s5/I3 |
| 7.815 | 0.208 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_54_s5/F |
| 8.112 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_54_s4/I0 |
| 8.528 | 0.417 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_54_s4/F |
| 8.825 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s9/I1 |
| 9.234 | 0.409 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s9/F |
| 9.531 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s7/I1 |
| 9.940 | 0.409 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s7/F |
| 10.237 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s6/I0 |
| 10.653 | 0.417 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s6/F |
| 10.950 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s5/I0 |
| 11.367 | 0.417 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s5/F |
| 11.664 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s4/I0 |
| 12.081 | 0.417 | tINS | RR | 3 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s4/F |
| 12.378 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s3/I2 |
| 12.743 | 0.365 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s3/F |
| 13.040 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_0_s0/I3 |
| 13.248 | 0.208 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_0_s0/F |
| 13.545 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_exponent_0_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | |||
| 10.000 | 0.000 | axi_clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | axi_clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 10117 | axi_clk_ibuf/O |
| 10.297 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_exponent_0_s0/CLK |
| 10.251 | -0.046 | tSu | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_exponent_0_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 21 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.297, 100.000% |
| Arrival Data Path Delay: | cell: 6.736, 50.842%; route: 6.237, 47.079%; tC2Q: 0.275, 2.079% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.297, 100.000% |
Path 4
Path Summary:| Slack | -3.294 |
| Data Arrival Time | 13.545 |
| Data Required Time | 10.251 |
| From | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_input_payload_exactMask_1_s0 |
| To | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_exponent_1_s0 |
| Launch Clk | axi_clk[R] |
| Latch Clk | axi_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | axi_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | axi_clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 10117 | axi_clk_ibuf/O |
| 0.297 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_input_payload_exactMask_1_s0/CLK |
| 0.572 | 0.275 | tC2Q | RR | 3 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_input_payload_exactMask_1_s0/Q |
| 0.869 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adderMantissa_0_s1/I0 |
| 1.286 | 0.417 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adderMantissa_0_s1/F |
| 1.583 | 0.297 | tNET | RR | 2 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_0_s/I0 |
| 2.147 | 0.564 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_0_s/SUM |
| 2.444 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_3_s5/I0 |
| 2.861 | 0.417 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_3_s5/F |
| 3.158 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_6_s5/I3 |
| 3.366 | 0.208 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_6_s5/F |
| 3.663 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_9_s5/I3 |
| 3.871 | 0.208 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_9_s5/F |
| 4.168 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_12_s5/I3 |
| 4.376 | 0.208 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_12_s5/F |
| 4.673 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_15_s5/I3 |
| 4.881 | 0.208 | tINS | RR | 7 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_15_s5/F |
| 5.178 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_21_s5/I3 |
| 5.386 | 0.208 | tINS | RR | 7 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_21_s5/F |
| 5.683 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_30_s5/I1 |
| 6.091 | 0.409 | tINS | RR | 3 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_30_s5/F |
| 6.388 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_33_s5/I3 |
| 6.596 | 0.208 | tINS | RR | 15 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_33_s5/F |
| 6.893 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_51_s5/I0 |
| 7.310 | 0.417 | tINS | RR | 5 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_51_s5/F |
| 7.607 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_54_s5/I3 |
| 7.815 | 0.208 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_54_s5/F |
| 8.112 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_54_s4/I0 |
| 8.528 | 0.417 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_54_s4/F |
| 8.825 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s9/I1 |
| 9.234 | 0.409 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s9/F |
| 9.531 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s7/I1 |
| 9.940 | 0.409 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s7/F |
| 10.237 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s6/I0 |
| 10.653 | 0.417 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s6/F |
| 10.950 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s5/I0 |
| 11.367 | 0.417 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s5/F |
| 11.664 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s4/I0 |
| 12.081 | 0.417 | tINS | RR | 3 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s4/F |
| 12.378 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s3/I2 |
| 12.743 | 0.365 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s3/F |
| 13.040 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s0/I3 |
| 13.248 | 0.208 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s0/F |
| 13.545 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_exponent_1_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | |||
| 10.000 | 0.000 | axi_clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | axi_clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 10117 | axi_clk_ibuf/O |
| 10.297 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_exponent_1_s0/CLK |
| 10.251 | -0.046 | tSu | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_exponent_1_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 21 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.297, 100.000% |
| Arrival Data Path Delay: | cell: 6.736, 50.842%; route: 6.237, 47.079%; tC2Q: 0.275, 2.079% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.297, 100.000% |
Path 5
Path Summary:| Slack | -3.136 |
| Data Arrival Time | 13.387 |
| Data Required Time | 10.251 |
| From | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_input_payload_exactMask_1_s0 |
| To | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_exponent_2_s0 |
| Launch Clk | axi_clk[R] |
| Latch Clk | axi_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | axi_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | axi_clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 10117 | axi_clk_ibuf/O |
| 0.297 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_input_payload_exactMask_1_s0/CLK |
| 0.572 | 0.275 | tC2Q | RR | 3 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_input_payload_exactMask_1_s0/Q |
| 0.869 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adderMantissa_0_s1/I0 |
| 1.286 | 0.417 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adderMantissa_0_s1/F |
| 1.583 | 0.297 | tNET | RR | 2 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_0_s/I0 |
| 2.147 | 0.564 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_0_s/SUM |
| 2.444 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_3_s5/I0 |
| 2.861 | 0.417 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_3_s5/F |
| 3.158 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_6_s5/I3 |
| 3.366 | 0.208 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_6_s5/F |
| 3.663 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_9_s5/I3 |
| 3.871 | 0.208 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_9_s5/F |
| 4.168 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_12_s5/I3 |
| 4.376 | 0.208 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_12_s5/F |
| 4.673 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_15_s5/I3 |
| 4.881 | 0.208 | tINS | RR | 7 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_15_s5/F |
| 5.178 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_21_s5/I3 |
| 5.386 | 0.208 | tINS | RR | 7 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_21_s5/F |
| 5.683 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_30_s5/I1 |
| 6.091 | 0.409 | tINS | RR | 3 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_30_s5/F |
| 6.388 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_33_s5/I3 |
| 6.596 | 0.208 | tINS | RR | 15 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_33_s5/F |
| 6.893 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_51_s5/I0 |
| 7.310 | 0.417 | tINS | RR | 5 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_51_s5/F |
| 7.607 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_54_s5/I3 |
| 7.815 | 0.208 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_54_s5/F |
| 8.112 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_54_s4/I0 |
| 8.528 | 0.417 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_54_s4/F |
| 8.825 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s9/I1 |
| 9.234 | 0.409 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s9/F |
| 9.531 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s7/I1 |
| 9.940 | 0.409 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s7/F |
| 10.237 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s6/I0 |
| 10.653 | 0.417 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s6/F |
| 10.950 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s5/I0 |
| 11.367 | 0.417 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s5/F |
| 11.664 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s4/I0 |
| 12.081 | 0.417 | tINS | RR | 3 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_1_s4/F |
| 12.378 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_mantissa_51_s2/I3 |
| 12.586 | 0.208 | tINS | RR | 62 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_mantissa_51_s2/F |
| 12.883 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_2_s1/I3 |
| 13.090 | 0.208 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_2_s1/F |
| 13.387 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_exponent_2_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | |||
| 10.000 | 0.000 | axi_clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | axi_clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 10117 | axi_clk_ibuf/O |
| 10.297 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_exponent_2_s0/CLK |
| 10.251 | -0.046 | tSu | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_exponent_2_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 21 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.297, 100.000% |
| Arrival Data Path Delay: | cell: 6.578, 50.251%; route: 6.237, 47.645%; tC2Q: 0.275, 2.104% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.297, 100.000% |