Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\custom\gorv32_plus_const.vh D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\ahb_bridge.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\apb_bridge.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\apb_gpio.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\apb_iic.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\apb_pit.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\apb_sd.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\apb_spi.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\apb_uart.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\apb_wdt.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\axi_bridge.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\bus_matrix.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\gorv32_plus.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\gorv32_plus_top.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\misc.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\onchip_ram.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\riscv_plus_core.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.12.02 (64-bit) |
| Part Number | GW5AST-LV138FPG676AC2/I1 |
| Device | GW5AST-138 |
| Device Version | C |
| Created Time | Thu Mar 5 20:29:17 2026 |
| Legal Announcement | Copyright (C)2014-2026 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | Gowin_GoRV32_Plus_Top |
| Synthesis Process | Running parser: CPU time = 0h 0m 7s, Elapsed time = 0h 0m 7s, Peak memory usage = 457.379MB Running netlist conversion: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 457.379MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 10s, Elapsed time = 0h 0m 10s, Peak memory usage = 457.379MB Optimizing Phase 1: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 457.379MB Optimizing Phase 2: CPU time = 0h 0m 14s, Elapsed time = 0h 0m 14s, Peak memory usage = 457.379MB Running inference: Inferring Phase 0: CPU time = 0h 0m 19s, Elapsed time = 0h 0m 19s, Peak memory usage = 457.379MB Inferring Phase 1: CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s, Peak memory usage = 457.379MB Inferring Phase 2: CPU time = 0h 0m 0.375s, Elapsed time = 0h 0m 0.367s, Peak memory usage = 457.379MB Inferring Phase 3: CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.217s, Peak memory usage = 457.379MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 8s, Elapsed time = 0h 0m 8s, Peak memory usage = 457.379MB Tech-Mapping Phase 1: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 457.379MB Tech-Mapping Phase 2: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 457.379MB Tech-Mapping Phase 3: CPU time = 0h 1m 24s, Elapsed time = 0h 1m 25s, Peak memory usage = 457.379MB Tech-Mapping Phase 4: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 3s, Peak memory usage = 457.379MB Generate output files: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 457.379MB |
| Total Time and Memory Usage | CPU time = 0h 2m 37s, Elapsed time = 0h 2m 39s, Peak memory usage = 457.379MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 454 |
| I/O Buf | 454 |
| IBUF | 228 |
| OBUF | 220 |
| IOBUF | 6 |
| Register | 11610 |
| DFFSE | 130 |
| DFFRE | 6345 |
| DFFPE | 111 |
| DFFCE | 5023 |
| DLCE | 1 |
| LUT | 17573 |
| LUT2 | 1487 |
| LUT3 | 7517 |
| LUT4 | 8569 |
| ALU | 2495 |
| ALU | 2495 |
| SSRAM | 255 |
| RAM16SDP1 | 21 |
| RAM16SDP2 | 4 |
| RAM16SDP4 | 230 |
| INV | 75 |
| INV | 75 |
| DSP | |
| MULTALU27X18 | 9 |
| MULT27X36 | 4 |
| BSRAM | 67 |
| SP | 32 |
| SDPB | 29 |
| SDPX9B | 6 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 21673(17648 LUT, 2495 ALU, 255 RAM16) / 138240 | 16% |
| Register | 11610 / 139140 | 9% |
| --Register as Latch | 1 / 139140 | <1% |
| --Register as FF | 11609 / 139140 | 9% |
| BSRAM | 67 / 340 | 20% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | axi_clk | Base | 10.000 | 100.000 | 0.000 | 5.000 | axi_clk_ibuf/I | ||
| 2 | JTAG_TCK | Base | 10.000 | 100.000 | 0.000 | 5.000 | JTAG_TCK_ibuf/I | ||
| 3 | ahb_clk | Base | 10.000 | 100.000 | 0.000 | 5.000 | ahb_clk_ibuf/I | ||
| 4 | apb_clk | Base | 10.000 | 100.000 | 0.000 | 5.000 | apb_clk_ibuf/I | ||
| 5 | FLASH_QSPI_CLK | Base | 10.000 | 100.000 | 0.000 | 5.000 | FLASH_QSPI_CLK_iobuf/IO |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | axi_clk | 100.000(MHz) | 76.681(MHz) | 20 | TOP |
| 2 | JTAG_TCK | 100.000(MHz) | 147.323(MHz) | 5 | TOP |
| 3 | ahb_clk | 100.000(MHz) | 102.482(MHz) | 14 | TOP |
| 4 | apb_clk | 100.000(MHz) | 91.314(MHz) | 8 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | -3.041 |
| Data Arrival Time | 13.292 |
| Data Required Time | 10.251 |
| From | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_input_payload_exactMask_1_s0 |
| To | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_exponent_10_s0 |
| Launch Clk | axi_clk[R] |
| Latch Clk | axi_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | axi_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | axi_clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 10628 | axi_clk_ibuf/O |
| 0.297 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_input_payload_exactMask_1_s0/CLK |
| 0.572 | 0.275 | tC2Q | RR | 3 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_input_payload_exactMask_1_s0/Q |
| 0.869 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adderMantissa_0_s1/I0 |
| 1.286 | 0.417 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adderMantissa_0_s1/F |
| 1.583 | 0.297 | tNET | RR | 2 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_0_s/I0 |
| 2.147 | 0.564 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_0_s/SUM |
| 2.444 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_3_s5/I0 |
| 2.861 | 0.417 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_3_s5/F |
| 3.158 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_6_s5/I3 |
| 3.366 | 0.208 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_6_s5/F |
| 3.663 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_9_s5/I3 |
| 3.871 | 0.208 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_9_s5/F |
| 4.168 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_12_s5/I3 |
| 4.376 | 0.208 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_12_s5/F |
| 4.673 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_15_s5/I3 |
| 4.881 | 0.208 | tINS | RR | 6 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_15_s5/F |
| 5.178 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_20_s5/I3 |
| 5.386 | 0.208 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_20_s5/F |
| 5.683 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_21_s5/I1 |
| 6.091 | 0.409 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_21_s5/F |
| 6.388 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_26_s5/I3 |
| 6.596 | 0.208 | tINS | RR | 5 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_26_s5/F |
| 6.893 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_27_s5/I1 |
| 7.302 | 0.409 | tINS | RR | 28 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_27_s5/F |
| 7.599 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_55_s5/I0 |
| 8.015 | 0.417 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_55_s5/F |
| 8.312 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_55_s4/I0 |
| 8.729 | 0.417 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_55_s4/F |
| 9.026 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/when_FpuCore_l1619_s5/I0 |
| 9.443 | 0.417 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/when_FpuCore_l1619_s5/F |
| 9.740 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/when_FpuCore_l1619_s3/I0 |
| 10.156 | 0.417 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/when_FpuCore_l1619_s3/F |
| 10.453 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/when_FpuCore_l1619_s2/I1 |
| 10.862 | 0.409 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/when_FpuCore_l1619_s2/F |
| 11.159 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/when_FpuCore_l1619_s1/I0 |
| 11.576 | 0.417 | tINS | RR | 63 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/when_FpuCore_l1619_s1/F |
| 11.873 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/n25162_s1/I1 |
| 12.281 | 0.409 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/n25162_s1/F |
| 12.578 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_10_s2/I0 |
| 12.995 | 0.417 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_10_s2/F |
| 13.292 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_exponent_10_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | |||
| 10.000 | 0.000 | axi_clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | axi_clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 10628 | axi_clk_ibuf/O |
| 10.297 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_exponent_10_s0/CLK |
| 10.251 | -0.046 | tSu | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_exponent_10_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 20 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.297, 100.000% |
| Arrival Data Path Delay: | cell: 6.780, 52.171%; route: 5.940, 45.710%; tC2Q: 0.275, 2.119% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.297, 100.000% |
Path 2
Path Summary:| Slack | -3.033 |
| Data Arrival Time | 13.284 |
| Data Required Time | 10.251 |
| From | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_input_payload_exactMask_1_s0 |
| To | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_exponent_2_s0 |
| Launch Clk | axi_clk[R] |
| Latch Clk | axi_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | axi_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | axi_clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 10628 | axi_clk_ibuf/O |
| 0.297 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_input_payload_exactMask_1_s0/CLK |
| 0.572 | 0.275 | tC2Q | RR | 3 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_input_payload_exactMask_1_s0/Q |
| 0.869 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adderMantissa_0_s1/I0 |
| 1.286 | 0.417 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adderMantissa_0_s1/F |
| 1.583 | 0.297 | tNET | RR | 2 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_0_s/I0 |
| 2.147 | 0.564 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_0_s/SUM |
| 2.444 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_3_s5/I0 |
| 2.861 | 0.417 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_3_s5/F |
| 3.158 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_6_s5/I3 |
| 3.366 | 0.208 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_6_s5/F |
| 3.663 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_9_s5/I3 |
| 3.871 | 0.208 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_9_s5/F |
| 4.168 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_12_s5/I3 |
| 4.376 | 0.208 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_12_s5/F |
| 4.673 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_15_s5/I3 |
| 4.881 | 0.208 | tINS | RR | 6 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_15_s5/F |
| 5.178 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_20_s5/I3 |
| 5.386 | 0.208 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_20_s5/F |
| 5.683 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_21_s5/I1 |
| 6.091 | 0.409 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_21_s5/F |
| 6.388 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_26_s5/I3 |
| 6.596 | 0.208 | tINS | RR | 5 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_26_s5/F |
| 6.893 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_27_s5/I1 |
| 7.302 | 0.409 | tINS | RR | 28 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_27_s5/F |
| 7.599 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_55_s5/I0 |
| 8.015 | 0.417 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_55_s5/F |
| 8.312 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_55_s4/I0 |
| 8.729 | 0.417 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_55_s4/F |
| 9.026 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/when_FpuCore_l1619_s5/I0 |
| 9.443 | 0.417 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/when_FpuCore_l1619_s5/F |
| 9.740 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/when_FpuCore_l1619_s3/I0 |
| 10.156 | 0.417 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/when_FpuCore_l1619_s3/F |
| 10.453 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/when_FpuCore_l1619_s2/I1 |
| 10.862 | 0.409 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/when_FpuCore_l1619_s2/F |
| 11.159 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/when_FpuCore_l1619_s1/I0 |
| 11.576 | 0.417 | tINS | RR | 63 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/when_FpuCore_l1619_s1/F |
| 11.873 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/n25162_s1/I1 |
| 12.281 | 0.409 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/n25162_s1/F |
| 12.578 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_2_s1/I1 |
| 12.987 | 0.409 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_2_s1/F |
| 13.284 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_exponent_2_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | |||
| 10.000 | 0.000 | axi_clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | axi_clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 10628 | axi_clk_ibuf/O |
| 10.297 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_exponent_2_s0/CLK |
| 10.251 | -0.046 | tSu | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_exponent_2_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 20 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.297, 100.000% |
| Arrival Data Path Delay: | cell: 6.772, 52.141%; route: 5.940, 45.738%; tC2Q: 0.275, 2.121% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.297, 100.000% |
Path 3
Path Summary:| Slack | -3.033 |
| Data Arrival Time | 13.284 |
| Data Required Time | 10.251 |
| From | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_input_payload_exactMask_1_s0 |
| To | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_exponent_5_s0 |
| Launch Clk | axi_clk[R] |
| Latch Clk | axi_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | axi_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | axi_clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 10628 | axi_clk_ibuf/O |
| 0.297 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_input_payload_exactMask_1_s0/CLK |
| 0.572 | 0.275 | tC2Q | RR | 3 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_input_payload_exactMask_1_s0/Q |
| 0.869 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adderMantissa_0_s1/I0 |
| 1.286 | 0.417 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adderMantissa_0_s1/F |
| 1.583 | 0.297 | tNET | RR | 2 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_0_s/I0 |
| 2.147 | 0.564 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_0_s/SUM |
| 2.444 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_3_s5/I0 |
| 2.861 | 0.417 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_3_s5/F |
| 3.158 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_6_s5/I3 |
| 3.366 | 0.208 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_6_s5/F |
| 3.663 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_9_s5/I3 |
| 3.871 | 0.208 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_9_s5/F |
| 4.168 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_12_s5/I3 |
| 4.376 | 0.208 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_12_s5/F |
| 4.673 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_15_s5/I3 |
| 4.881 | 0.208 | tINS | RR | 6 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_15_s5/F |
| 5.178 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_20_s5/I3 |
| 5.386 | 0.208 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_20_s5/F |
| 5.683 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_21_s5/I1 |
| 6.091 | 0.409 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_21_s5/F |
| 6.388 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_26_s5/I3 |
| 6.596 | 0.208 | tINS | RR | 5 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_26_s5/F |
| 6.893 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_27_s5/I1 |
| 7.302 | 0.409 | tINS | RR | 28 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_27_s5/F |
| 7.599 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_55_s5/I0 |
| 8.015 | 0.417 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_55_s5/F |
| 8.312 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_55_s4/I0 |
| 8.729 | 0.417 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_55_s4/F |
| 9.026 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/when_FpuCore_l1619_s5/I0 |
| 9.443 | 0.417 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/when_FpuCore_l1619_s5/F |
| 9.740 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/when_FpuCore_l1619_s3/I0 |
| 10.156 | 0.417 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/when_FpuCore_l1619_s3/F |
| 10.453 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/when_FpuCore_l1619_s2/I1 |
| 10.862 | 0.409 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/when_FpuCore_l1619_s2/F |
| 11.159 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/when_FpuCore_l1619_s1/I0 |
| 11.576 | 0.417 | tINS | RR | 63 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/when_FpuCore_l1619_s1/F |
| 11.873 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/n25162_s1/I1 |
| 12.281 | 0.409 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/n25162_s1/F |
| 12.578 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_5_s2/I1 |
| 12.987 | 0.409 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_5_s2/F |
| 13.284 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_exponent_5_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | |||
| 10.000 | 0.000 | axi_clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | axi_clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 10628 | axi_clk_ibuf/O |
| 10.297 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_exponent_5_s0/CLK |
| 10.251 | -0.046 | tSu | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_exponent_5_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 20 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.297, 100.000% |
| Arrival Data Path Delay: | cell: 6.772, 52.141%; route: 5.940, 45.738%; tC2Q: 0.275, 2.121% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.297, 100.000% |
Path 4
Path Summary:| Slack | -2.990 |
| Data Arrival Time | 13.241 |
| Data Required Time | 10.251 |
| From | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_input_payload_exactMask_1_s0 |
| To | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_exponent_7_s0 |
| Launch Clk | axi_clk[R] |
| Latch Clk | axi_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | axi_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | axi_clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 10628 | axi_clk_ibuf/O |
| 0.297 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_input_payload_exactMask_1_s0/CLK |
| 0.572 | 0.275 | tC2Q | RR | 3 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_input_payload_exactMask_1_s0/Q |
| 0.869 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adderMantissa_0_s1/I0 |
| 1.286 | 0.417 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adderMantissa_0_s1/F |
| 1.583 | 0.297 | tNET | RR | 2 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_0_s/I0 |
| 2.147 | 0.564 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_0_s/SUM |
| 2.444 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_3_s5/I0 |
| 2.861 | 0.417 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_3_s5/F |
| 3.158 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_6_s5/I3 |
| 3.366 | 0.208 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_6_s5/F |
| 3.663 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_9_s5/I3 |
| 3.871 | 0.208 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_9_s5/F |
| 4.168 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_12_s5/I3 |
| 4.376 | 0.208 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_12_s5/F |
| 4.673 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_15_s5/I3 |
| 4.881 | 0.208 | tINS | RR | 6 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_15_s5/F |
| 5.178 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_20_s5/I3 |
| 5.386 | 0.208 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_20_s5/F |
| 5.683 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_21_s5/I1 |
| 6.091 | 0.409 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_21_s5/F |
| 6.388 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_26_s5/I3 |
| 6.596 | 0.208 | tINS | RR | 5 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_26_s5/F |
| 6.893 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_27_s5/I1 |
| 7.302 | 0.409 | tINS | RR | 28 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_27_s5/F |
| 7.599 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_55_s5/I0 |
| 8.015 | 0.417 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_55_s5/F |
| 8.312 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_55_s4/I0 |
| 8.729 | 0.417 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_55_s4/F |
| 9.026 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/when_FpuCore_l1619_s5/I0 |
| 9.443 | 0.417 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/when_FpuCore_l1619_s5/F |
| 9.740 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/when_FpuCore_l1619_s3/I0 |
| 10.156 | 0.417 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/when_FpuCore_l1619_s3/F |
| 10.453 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/when_FpuCore_l1619_s2/I1 |
| 10.862 | 0.409 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/when_FpuCore_l1619_s2/F |
| 11.159 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/when_FpuCore_l1619_s1/I0 |
| 11.576 | 0.417 | tINS | RR | 63 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/when_FpuCore_l1619_s1/F |
| 11.873 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/n25162_s1/I1 |
| 12.281 | 0.409 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/n25162_s1/F |
| 12.578 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_7_s2/I2 |
| 12.944 | 0.365 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_7_s2/F |
| 13.241 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_exponent_7_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | |||
| 10.000 | 0.000 | axi_clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | axi_clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 10628 | axi_clk_ibuf/O |
| 10.297 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_exponent_7_s0/CLK |
| 10.251 | -0.046 | tSu | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_exponent_7_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 20 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.297, 100.000% |
| Arrival Data Path Delay: | cell: 6.728, 51.981%; route: 5.940, 45.891%; tC2Q: 0.275, 2.128% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.297, 100.000% |
Path 5
Path Summary:| Slack | -2.946 |
| Data Arrival Time | 13.198 |
| Data Required Time | 10.251 |
| From | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_input_payload_exactMask_1_s0 |
| To | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_exponent_0_s0 |
| Launch Clk | axi_clk[R] |
| Latch Clk | axi_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | axi_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | axi_clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 10628 | axi_clk_ibuf/O |
| 0.297 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_input_payload_exactMask_1_s0/CLK |
| 0.572 | 0.275 | tC2Q | RR | 3 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_input_payload_exactMask_1_s0/Q |
| 0.869 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adderMantissa_0_s1/I0 |
| 1.286 | 0.417 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adderMantissa_0_s1/F |
| 1.583 | 0.297 | tNET | RR | 2 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_0_s/I0 |
| 2.147 | 0.564 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/_zz_roundBack_adder_2_0_s/SUM |
| 2.444 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_3_s5/I0 |
| 2.861 | 0.417 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_3_s5/F |
| 3.158 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_6_s5/I3 |
| 3.366 | 0.208 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_6_s5/F |
| 3.663 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_9_s5/I3 |
| 3.871 | 0.208 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_9_s5/F |
| 4.168 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_12_s5/I3 |
| 4.376 | 0.208 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_12_s5/F |
| 4.673 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_15_s5/I3 |
| 4.881 | 0.208 | tINS | RR | 6 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_15_s5/F |
| 5.178 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_20_s5/I3 |
| 5.386 | 0.208 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_20_s5/F |
| 5.683 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_21_s5/I1 |
| 6.091 | 0.409 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_21_s5/F |
| 6.388 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_26_s5/I3 |
| 6.596 | 0.208 | tINS | RR | 5 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_26_s5/F |
| 6.893 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_27_s5/I1 |
| 7.302 | 0.409 | tINS | RR | 28 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_27_s5/F |
| 7.599 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_55_s5/I0 |
| 8.015 | 0.417 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_55_s5/F |
| 8.312 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_55_s4/I0 |
| 8.729 | 0.417 | tINS | RR | 4 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_adder_55_s4/F |
| 9.026 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/when_FpuCore_l1619_s5/I0 |
| 9.443 | 0.417 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/when_FpuCore_l1619_s5/F |
| 9.740 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/when_FpuCore_l1619_s3/I0 |
| 10.156 | 0.417 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/when_FpuCore_l1619_s3/F |
| 10.453 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/when_FpuCore_l1619_s2/I1 |
| 10.862 | 0.409 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/when_FpuCore_l1619_s2/F |
| 11.159 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/when_FpuCore_l1619_s1/I0 |
| 11.576 | 0.417 | tINS | RR | 63 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/when_FpuCore_l1619_s1/F |
| 11.873 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_0_s1/I2 |
| 12.238 | 0.365 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_0_s1/F |
| 12.535 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_0_s0/I2 |
| 12.901 | 0.365 | tINS | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/roundBack_patched_exponent_0_s0/F |
| 13.198 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_exponent_0_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | |||
| 10.000 | 0.000 | axi_clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | axi_clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 10628 | axi_clk_ibuf/O |
| 10.297 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_exponent_0_s0/CLK |
| 10.251 | -0.046 | tSu | 1 | u_gorv32_plus/u_VexRiscvLitexSmpCluster/fpu_0_logic/writeback_input_payload_value_exponent_0_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 20 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.297, 100.000% |
| Arrival Data Path Delay: | cell: 6.685, 51.821%; route: 5.940, 46.044%; tC2Q: 0.275, 2.135% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.297, 100.000% |