Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\custom\gorv32_plus_const.vh D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\ahb_bridge.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\apb_bridge.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\apb_gpio.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\apb_iic.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\apb_pit.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\apb_sd.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\apb_spi.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\apb_uart.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\apb_wdt.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\axi_bridge.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\bus_matrix.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\gorv32_plus.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\gorv32_plus_top.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\misc.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\onchip_ram.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\GowinGoRV32Plus\data\riscv_plus_core.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.12.02 (64-bit) |
| Part Number | GW5AST-LV138FPG676AC2/I1 |
| Device | GW5AST-138 |
| Device Version | C |
| Created Time | Thu Mar 5 17:20:31 2026 |
| Legal Announcement | Copyright (C)2014-2026 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | Gowin_GoRV32_Plus_Top |
| Synthesis Process | Running parser: CPU time = 0h 0m 6s, Elapsed time = 0h 0m 6s, Peak memory usage = 466.863MB Running netlist conversion: CPU time = 0h 0m 0.89s, Elapsed time = 0h 0m 0.892s, Peak memory usage = 466.863MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 8s, Elapsed time = 0h 0m 8s, Peak memory usage = 466.863MB Optimizing Phase 1: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 466.863MB Optimizing Phase 2: CPU time = 0h 0m 14s, Elapsed time = 0h 0m 14s, Peak memory usage = 466.863MB Running inference: Inferring Phase 0: CPU time = 0h 0m 17s, Elapsed time = 0h 0m 17s, Peak memory usage = 466.863MB Inferring Phase 1: CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s, Peak memory usage = 466.863MB Inferring Phase 2: CPU time = 0h 0m 0.375s, Elapsed time = 0h 0m 0.373s, Peak memory usage = 466.863MB Inferring Phase 3: CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.212s, Peak memory usage = 466.863MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 8s, Elapsed time = 0h 0m 8s, Peak memory usage = 466.863MB Tech-Mapping Phase 1: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 466.863MB Tech-Mapping Phase 2: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 466.863MB Tech-Mapping Phase 3: CPU time = 0h 1m 16s, Elapsed time = 0h 1m 16s, Peak memory usage = 466.863MB Tech-Mapping Phase 4: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 466.863MB Generate output files: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 466.863MB |
| Total Time and Memory Usage | CPU time = 0h 2m 22s, Elapsed time = 0h 2m 22s, Peak memory usage = 466.863MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 124 |
| I/O Buf | 124 |
| IBUF | 48 |
| OBUF | 70 |
| IOBUF | 6 |
| Register | 11847 |
| DFFSE | 130 |
| DFFRE | 6340 |
| DFFPE | 135 |
| DFFCE | 5240 |
| DLCE | 2 |
| LUT | 17573 |
| LUT2 | 1476 |
| LUT3 | 7391 |
| LUT4 | 8706 |
| ALU | 2517 |
| ALU | 2517 |
| SSRAM | 269 |
| RAM16SDP1 | 21 |
| RAM16SDP2 | 4 |
| RAM16SDP4 | 244 |
| INV | 64 |
| INV | 64 |
| DSP | |
| MULTALU27X18 | 9 |
| MULT27X36 | 4 |
| BSRAM | 67 |
| SP | 32 |
| SDPB | 29 |
| SDPX9B | 6 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 21768(17637 LUT, 2517 ALU, 269 RAM16) / 138240 | 16% |
| Register | 11847 / 139140 | 9% |
| --Register as Latch | 2 / 139140 | <1% |
| --Register as FF | 11845 / 139140 | 9% |
| BSRAM | 67 / 340 | 20% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | axi_clk | Base | 10.000 | 100.000 | 0.000 | 5.000 | axi_clk_ibuf/I | ||
| 2 | JTAG_TCK | Base | 10.000 | 100.000 | 0.000 | 5.000 | JTAG_TCK_ibuf/I | ||
| 3 | ahb_clk | Base | 10.000 | 100.000 | 0.000 | 5.000 | ahb_clk_ibuf/I | ||
| 4 | apb_clk | Base | 10.000 | 100.000 | 0.000 | 5.000 | apb_clk_ibuf/I | ||
| 5 | u_gorv32_plus/u_gw_spi_1/u_spi_spiif/spi_w_clk_slv_20 | Base | 10.000 | 100.000 | 0.000 | 5.000 | u_gorv32_plus/u_gw_spi_1/u_spi_spiif/spi_w_clk_slv_s9/F |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | axi_clk | 100.000(MHz) | 79.764(MHz) | 20 | TOP |
| 2 | JTAG_TCK | 100.000(MHz) | 147.323(MHz) | 5 | TOP |
| 3 | ahb_clk | 100.000(MHz) | 103.736(MHz) | 14 | TOP |
| 4 | apb_clk | 100.000(MHz) | 72.922(MHz) | 23 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | -4.364 |
| Data Arrival Time | 9.600 |
| Data Required Time | 5.236 |
| From | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/slave_cmd_1_s3 |
| To | u_gorv32_plus/u_gw_spi_1/u_spi_spiif/spi_out_slv_r_1_s2 |
| Launch Clk | apb_clk[R] |
| Latch Clk | u_gorv32_plus/u_gw_spi_1/u_spi_spiif/spi_w_clk_slv_20[F] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | apb_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | apb_clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 1202 | apb_clk_ibuf/O |
| 0.297 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/slave_cmd_1_s3/CLK |
| 0.572 | 0.275 | tC2Q | RR | 8 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/slave_cmd_1_s3/Q |
| 0.869 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/arb_trans_end_sclk_Z_s3/I0 |
| 1.286 | 0.417 | tINS | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/arb_trans_end_sclk_Z_s3/F |
| 1.583 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/arb_trans_end_sclk_Z_s0/I2 |
| 1.948 | 0.365 | tINS | RR | 14 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/arb_trans_end_sclk_Z_s0/F |
| 2.245 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/ctrl_word_len_2_s6/I3 |
| 2.453 | 0.208 | tINS | RR | 5 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/ctrl_word_len_2_s6/F |
| 2.750 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/ctrl_word_len_0_s4/I1 |
| 3.159 | 0.409 | tINS | RR | 4 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/ctrl_word_len_0_s4/F |
| 3.456 | 0.297 | tNET | RR | 2 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n1258_s/I0 |
| 3.884 | 0.428 | tINS | RF | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n1258_s/COUT |
| 3.884 | 0.000 | tNET | FF | 2 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n1257_s/CIN |
| 4.060 | 0.175 | tINS | FR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n1257_s/SUM |
| 4.357 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/tx_ptr_1_s0/I0 |
| 4.774 | 0.417 | tINS | RR | 24 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/tx_ptr_1_s0/F |
| 5.071 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n1277_s118/I2 |
| 5.436 | 0.365 | tINS | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n1277_s118/F |
| 5.733 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n1277_s110/I1 |
| 5.841 | 0.108 | tINS | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n1277_s110/O |
| 6.138 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n1277_s100/I1 |
| 6.200 | 0.062 | tINS | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n1277_s100/O |
| 6.497 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n1277_s97/I1 |
| 6.559 | 0.062 | tINS | RR | 2 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n1277_s97/O |
| 6.856 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_spiif/n395_s3/I0 |
| 7.273 | 0.417 | tINS | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_spiif/n395_s3/F |
| 7.570 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_spiif/n395_s2/I2 |
| 7.935 | 0.365 | tINS | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_spiif/n395_s2/F |
| 8.232 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_spiif/n395_s0/I1 |
| 8.641 | 0.409 | tINS | RR | 2 | u_gorv32_plus/u_gw_spi_1/u_spi_spiif/n395_s0/F |
| 8.938 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_spiif/n363_s0/I2 |
| 9.303 | 0.365 | tINS | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_spiif/n363_s0/F |
| 9.600 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_spiif/spi_out_slv_r_1_s2/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 5.000 | 5.000 | active clock edge time | |||
| 5.000 | 0.000 | u_gorv32_plus/u_gw_spi_1/u_spi_spiif/spi_w_clk_slv_20 | |||
| 5.000 | 0.000 | tCL | FF | 11 | u_gorv32_plus/u_gw_spi_1/u_spi_spiif/spi_w_clk_slv_s9/F |
| 5.277 | 0.277 | tNET | FF | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_spiif/spi_out_slv_r_1_s2/CLK |
| 5.242 | -0.035 | tUnc | u_gorv32_plus/u_gw_spi_1/u_spi_spiif/spi_out_slv_r_1_s2 | ||
| 5.236 | -0.006 | tSu | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_spiif/spi_out_slv_r_1_s2 |
| Clock Skew: | -0.020 |
| Setup Relationship: | 5.000 |
| Logic Level: | 14 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.297, 100.000% |
| Arrival Data Path Delay: | cell: 4.573, 49.154%; route: 4.455, 47.886%; tC2Q: 0.275, 2.960% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.297, 100.000% |
Path 2
Path Summary:| Slack | -3.745 |
| Data Arrival Time | 8.981 |
| Data Required Time | 5.236 |
| From | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/slave_cmd_1_s3 |
| To | u_gorv32_plus/u_gw_spi_1/u_spi_spiif/spi_out_slv_r_0_s2 |
| Launch Clk | apb_clk[R] |
| Latch Clk | u_gorv32_plus/u_gw_spi_1/u_spi_spiif/spi_w_clk_slv_20[F] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | apb_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | apb_clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 1202 | apb_clk_ibuf/O |
| 0.297 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/slave_cmd_1_s3/CLK |
| 0.572 | 0.275 | tC2Q | RR | 8 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/slave_cmd_1_s3/Q |
| 0.869 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/arb_trans_end_sclk_Z_s3/I0 |
| 1.286 | 0.417 | tINS | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/arb_trans_end_sclk_Z_s3/F |
| 1.583 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/arb_trans_end_sclk_Z_s0/I2 |
| 1.948 | 0.365 | tINS | RR | 14 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/arb_trans_end_sclk_Z_s0/F |
| 2.245 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/ctrl_word_len_2_s6/I3 |
| 2.453 | 0.208 | tINS | RR | 5 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/ctrl_word_len_2_s6/F |
| 2.750 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/ctrl_word_len_0_s4/I1 |
| 3.159 | 0.409 | tINS | RR | 4 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/ctrl_word_len_0_s4/F |
| 3.456 | 0.297 | tNET | RR | 2 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n1258_s/I0 |
| 3.884 | 0.428 | tINS | RF | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n1258_s/COUT |
| 3.884 | 0.000 | tNET | FF | 2 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n1257_s/CIN |
| 4.060 | 0.175 | tINS | FR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n1257_s/SUM |
| 4.357 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/tx_ptr_1_s0/I0 |
| 4.774 | 0.417 | tINS | RR | 24 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/tx_ptr_1_s0/F |
| 5.071 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n1277_s126/I2 |
| 5.436 | 0.365 | tINS | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n1277_s126/F |
| 5.733 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n1277_s106/I1 |
| 5.841 | 0.108 | tINS | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n1277_s106/O |
| 6.138 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n1277_s102/I1 |
| 6.200 | 0.062 | tINS | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n1277_s102/O |
| 6.497 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n1277_s98/I1 |
| 6.559 | 0.062 | tINS | RR | 2 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n1277_s98/O |
| 6.856 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_spiif/n399_s5/I0 |
| 7.273 | 0.417 | tINS | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_spiif/n399_s5/F |
| 7.570 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_spiif/n399_s3/I1 |
| 7.978 | 0.409 | tINS | RR | 2 | u_gorv32_plus/u_gw_spi_1/u_spi_spiif/n399_s3/F |
| 8.275 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_spiif/n366_s3/I1 |
| 8.684 | 0.409 | tINS | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_spiif/n366_s3/F |
| 8.981 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_spiif/spi_out_slv_r_0_s2/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 5.000 | 5.000 | active clock edge time | |||
| 5.000 | 0.000 | u_gorv32_plus/u_gw_spi_1/u_spi_spiif/spi_w_clk_slv_20 | |||
| 5.000 | 0.000 | tCL | FF | 11 | u_gorv32_plus/u_gw_spi_1/u_spi_spiif/spi_w_clk_slv_s9/F |
| 5.277 | 0.277 | tNET | FF | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_spiif/spi_out_slv_r_0_s2/CLK |
| 5.242 | -0.035 | tUnc | u_gorv32_plus/u_gw_spi_1/u_spi_spiif/spi_out_slv_r_0_s2 | ||
| 5.236 | -0.006 | tSu | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_spiif/spi_out_slv_r_0_s2 |
| Clock Skew: | -0.020 |
| Setup Relationship: | 5.000 |
| Logic Level: | 13 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.297, 100.000% |
| Arrival Data Path Delay: | cell: 4.251, 48.948%; route: 4.158, 47.881%; tC2Q: 0.275, 3.171% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.297, 100.000% |
Path 3
Path Summary:| Slack | -3.713 |
| Data Arrival Time | 13.964 |
| Data Required Time | 10.251 |
| From | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/slave_cmd_2_s3 |
| To | u_gorv32_plus/u_gw_spi_1/u_spi_fifo/u_spi_txfifo/empty_s0 |
| Launch Clk | apb_clk[R] |
| Latch Clk | apb_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | apb_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | apb_clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 1202 | apb_clk_ibuf/O |
| 0.297 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/slave_cmd_2_s3/CLK |
| 0.572 | 0.275 | tC2Q | RR | 6 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/slave_cmd_2_s3/Q |
| 0.869 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/spi_quad_Z_s15/I0 |
| 1.286 | 0.417 | tINS | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/spi_quad_Z_s15/F |
| 1.583 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/spi_quad_Z_s10/I0 |
| 2.000 | 0.417 | tINS | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/spi_quad_Z_s10/F |
| 2.297 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/spi_quad_Z_s4/I2 |
| 2.662 | 0.365 | tINS | RR | 7 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/spi_quad_Z_s4/F |
| 2.959 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/arb_wr_num_0_s3/I2 |
| 3.325 | 0.365 | tINS | RR | 9 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/arb_wr_num_0_s3/F |
| 3.622 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/arb_wr_num_0_s1/I2 |
| 3.987 | 0.365 | tINS | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/arb_wr_num_0_s1/F |
| 4.284 | 0.297 | tNET | RR | 2 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n394_s0/I1 |
| 4.716 | 0.432 | tINS | RF | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n394_s0/COUT |
| 4.716 | 0.000 | tNET | FF | 2 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n395_s0/CIN |
| 4.752 | 0.036 | tINS | FR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n395_s0/COUT |
| 4.752 | 0.000 | tNET | RR | 2 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n396_s0/CIN |
| 4.788 | 0.036 | tINS | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n396_s0/COUT |
| 4.788 | 0.000 | tNET | RR | 2 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n397_s0/CIN |
| 4.824 | 0.036 | tINS | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n397_s0/COUT |
| 4.824 | 0.000 | tNET | RR | 2 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n398_s0/CIN |
| 4.860 | 0.036 | tINS | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n398_s0/COUT |
| 4.860 | 0.000 | tNET | RR | 2 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n399_s0/CIN |
| 4.896 | 0.036 | tINS | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n399_s0/COUT |
| 4.896 | 0.000 | tNET | RR | 2 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n400_s0/CIN |
| 4.932 | 0.036 | tINS | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n400_s0/COUT |
| 4.932 | 0.000 | tNET | RR | 2 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n401_s0/CIN |
| 4.968 | 0.036 | tINS | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n401_s0/COUT |
| 4.968 | 0.000 | tNET | RR | 2 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n402_s0/CIN |
| 5.004 | 0.036 | tINS | RR | 5 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n402_s0/COUT |
| 5.301 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n609_s16/I0 |
| 5.718 | 0.417 | tINS | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n609_s16/F |
| 6.015 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n609_s14/I2 |
| 6.380 | 0.365 | tINS | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n609_s14/F |
| 6.677 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n609_s11/I2 |
| 7.042 | 0.365 | tINS | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n609_s11/F |
| 7.339 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n609_s6/I2 |
| 7.705 | 0.365 | tINS | RR | 5 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n609_s6/F |
| 8.002 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/ctrl_ns_1_s25/I1 |
| 8.410 | 0.409 | tINS | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/ctrl_ns_1_s25/F |
| 8.707 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/ctrl_ns_1_s14/I3 |
| 8.915 | 0.208 | tINS | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/ctrl_ns_1_s14/F |
| 9.212 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/ctrl_ns_1_s6/I0 |
| 9.629 | 0.417 | tINS | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/ctrl_ns_1_s6/F |
| 9.926 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/ctrl_ns_1_s2/I3 |
| 10.134 | 0.208 | tINS | RR | 32 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/ctrl_ns_1_s2/F |
| 10.431 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_fifo/u_spi_txfifo/next_gray_rd_ptr_0_s4/I2 |
| 10.796 | 0.365 | tINS | RR | 32 | u_gorv32_plus/u_gw_spi_1/u_spi_fifo/u_spi_txfifo/next_gray_rd_ptr_0_s4/F |
| 11.093 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_fifo/u_spi_txfifo/next_gray_rd_ptr_0_s2/I1 |
| 11.502 | 0.409 | tINS | RR | 13 | u_gorv32_plus/u_gw_spi_1/u_spi_fifo/u_spi_txfifo/next_gray_rd_ptr_0_s2/F |
| 11.799 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_fifo/u_spi_txfifo/next_gray_rd_ptr_2_s0/I2 |
| 12.164 | 0.365 | tINS | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_fifo/u_spi_txfifo/next_gray_rd_ptr_2_s0/F |
| 12.461 | 0.297 | tNET | RR | 2 | u_gorv32_plus/u_gw_spi_1/u_spi_fifo/u_spi_txfifo/n407_s0/I0 |
| 12.890 | 0.428 | tINS | RF | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_fifo/u_spi_txfifo/n407_s0/COUT |
| 12.890 | 0.000 | tNET | FF | 2 | u_gorv32_plus/u_gw_spi_1/u_spi_fifo/u_spi_txfifo/n408_s0/CIN |
| 12.926 | 0.036 | tINS | FR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_fifo/u_spi_txfifo/n408_s0/COUT |
| 12.926 | 0.000 | tNET | RR | 2 | u_gorv32_plus/u_gw_spi_1/u_spi_fifo/u_spi_txfifo/n409_s0/CIN |
| 12.962 | 0.036 | tINS | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_fifo/u_spi_txfifo/n409_s0/COUT |
| 13.259 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_fifo/u_spi_txfifo/n412_s2/I1 |
| 13.667 | 0.409 | tINS | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_fifo/u_spi_txfifo/n412_s2/F |
| 13.964 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_fifo/u_spi_txfifo/empty_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | |||
| 10.000 | 0.000 | apb_clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | apb_clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 1202 | apb_clk_ibuf/O |
| 10.297 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_fifo/u_spi_txfifo/empty_s0/CLK |
| 10.251 | -0.046 | tSu | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_fifo/u_spi_txfifo/empty_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 23 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.297, 100.000% |
| Arrival Data Path Delay: | cell: 7.452, 54.524%; route: 5.940, 43.461%; tC2Q: 0.275, 2.015% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.297, 100.000% |
Path 4
Path Summary:| Slack | -3.291 |
| Data Arrival Time | 13.542 |
| Data Required Time | 10.251 |
| From | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/slave_cmd_2_s3 |
| To | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/data_cnt_r_0_s1 |
| Launch Clk | apb_clk[R] |
| Latch Clk | apb_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | apb_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | apb_clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 1202 | apb_clk_ibuf/O |
| 0.297 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/slave_cmd_2_s3/CLK |
| 0.572 | 0.275 | tC2Q | RR | 6 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/slave_cmd_2_s3/Q |
| 0.869 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/spi_quad_Z_s15/I0 |
| 1.286 | 0.417 | tINS | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/spi_quad_Z_s15/F |
| 1.583 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/spi_quad_Z_s10/I0 |
| 2.000 | 0.417 | tINS | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/spi_quad_Z_s10/F |
| 2.297 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/spi_quad_Z_s4/I2 |
| 2.662 | 0.365 | tINS | RR | 7 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/spi_quad_Z_s4/F |
| 2.959 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/arb_wr_num_0_s3/I2 |
| 3.325 | 0.365 | tINS | RR | 9 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/arb_wr_num_0_s3/F |
| 3.622 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/arb_wr_num_0_s1/I2 |
| 3.987 | 0.365 | tINS | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/arb_wr_num_0_s1/F |
| 4.284 | 0.297 | tNET | RR | 2 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n394_s0/I1 |
| 4.716 | 0.432 | tINS | RF | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n394_s0/COUT |
| 4.716 | 0.000 | tNET | FF | 2 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n395_s0/CIN |
| 4.752 | 0.036 | tINS | FR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n395_s0/COUT |
| 4.752 | 0.000 | tNET | RR | 2 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n396_s0/CIN |
| 4.788 | 0.036 | tINS | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n396_s0/COUT |
| 4.788 | 0.000 | tNET | RR | 2 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n397_s0/CIN |
| 4.824 | 0.036 | tINS | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n397_s0/COUT |
| 4.824 | 0.000 | tNET | RR | 2 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n398_s0/CIN |
| 4.860 | 0.036 | tINS | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n398_s0/COUT |
| 4.860 | 0.000 | tNET | RR | 2 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n399_s0/CIN |
| 4.896 | 0.036 | tINS | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n399_s0/COUT |
| 4.896 | 0.000 | tNET | RR | 2 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n400_s0/CIN |
| 4.932 | 0.036 | tINS | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n400_s0/COUT |
| 4.932 | 0.000 | tNET | RR | 2 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n401_s0/CIN |
| 4.968 | 0.036 | tINS | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n401_s0/COUT |
| 4.968 | 0.000 | tNET | RR | 2 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n402_s0/CIN |
| 5.004 | 0.036 | tINS | RR | 5 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n402_s0/COUT |
| 5.301 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n609_s16/I0 |
| 5.718 | 0.417 | tINS | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n609_s16/F |
| 6.015 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n609_s14/I2 |
| 6.380 | 0.365 | tINS | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n609_s14/F |
| 6.677 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n609_s11/I2 |
| 7.042 | 0.365 | tINS | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n609_s11/F |
| 7.339 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n609_s6/I2 |
| 7.705 | 0.365 | tINS | RR | 5 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n609_s6/F |
| 8.002 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/ctrl_ns_0_s14/I1 |
| 8.410 | 0.409 | tINS | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/ctrl_ns_0_s14/F |
| 8.707 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/ctrl_ns_0_s7/I2 |
| 9.073 | 0.365 | tINS | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/ctrl_ns_0_s7/F |
| 9.370 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/ctrl_ns_0_s3/I1 |
| 9.778 | 0.409 | tINS | RR | 4 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/ctrl_ns_0_s3/F |
| 10.075 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/ctrl_ns_0_s2/I0 |
| 10.492 | 0.417 | tINS | RR | 9 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/ctrl_ns_0_s2/F |
| 10.789 | 0.297 | tNET | RR | 2 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n9_s0/I1 |
| 11.221 | 0.432 | tINS | RF | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n9_s0/COUT |
| 11.221 | 0.000 | tNET | FF | 2 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n10_s0/CIN |
| 11.257 | 0.036 | tINS | FR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n10_s0/COUT |
| 11.257 | 0.000 | tNET | RR | 2 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n11_s0/CIN |
| 11.293 | 0.036 | tINS | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n11_s0/COUT |
| 11.293 | 0.000 | tNET | RR | 2 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n12_s0/CIN |
| 11.329 | 0.036 | tINS | RR | 11 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n12_s0/COUT |
| 11.626 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/data_cnt_r_8_s9/I1 |
| 12.035 | 0.409 | tINS | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/data_cnt_r_8_s9/F |
| 12.332 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/data_cnt_r_8_s6/I3 |
| 12.540 | 0.208 | tINS | RR | 10 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/data_cnt_r_8_s6/F |
| 12.837 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n503_s2/I1 |
| 13.245 | 0.409 | tINS | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n503_s2/F |
| 13.542 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/data_cnt_r_0_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | |||
| 10.000 | 0.000 | apb_clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | apb_clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 1202 | apb_clk_ibuf/O |
| 10.297 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/data_cnt_r_0_s1/CLK |
| 10.251 | -0.046 | tSu | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/data_cnt_r_0_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 22 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.297, 100.000% |
| Arrival Data Path Delay: | cell: 7.327, 55.317%; route: 5.643, 42.604%; tC2Q: 0.275, 2.079% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.297, 100.000% |
Path 5
Path Summary:| Slack | -3.269 |
| Data Arrival Time | 13.342 |
| Data Required Time | 10.073 |
| From | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/slave_cmd_2_s3 |
| To | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/data_cnt_r_0_s1 |
| Launch Clk | apb_clk[R] |
| Latch Clk | apb_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | apb_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | apb_clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 1202 | apb_clk_ibuf/O |
| 0.297 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/slave_cmd_2_s3/CLK |
| 0.572 | 0.275 | tC2Q | RR | 6 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/slave_cmd_2_s3/Q |
| 0.869 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/spi_quad_Z_s15/I0 |
| 1.286 | 0.417 | tINS | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/spi_quad_Z_s15/F |
| 1.583 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/spi_quad_Z_s10/I0 |
| 2.000 | 0.417 | tINS | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/spi_quad_Z_s10/F |
| 2.297 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/spi_quad_Z_s4/I2 |
| 2.662 | 0.365 | tINS | RR | 7 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/spi_quad_Z_s4/F |
| 2.959 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/arb_wr_num_0_s3/I2 |
| 3.325 | 0.365 | tINS | RR | 9 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/arb_wr_num_0_s3/F |
| 3.622 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/arb_wr_num_0_s1/I2 |
| 3.987 | 0.365 | tINS | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/arb_wr_num_0_s1/F |
| 4.284 | 0.297 | tNET | RR | 2 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n394_s0/I1 |
| 4.716 | 0.432 | tINS | RF | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n394_s0/COUT |
| 4.716 | 0.000 | tNET | FF | 2 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n395_s0/CIN |
| 4.752 | 0.036 | tINS | FR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n395_s0/COUT |
| 4.752 | 0.000 | tNET | RR | 2 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n396_s0/CIN |
| 4.788 | 0.036 | tINS | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n396_s0/COUT |
| 4.788 | 0.000 | tNET | RR | 2 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n397_s0/CIN |
| 4.824 | 0.036 | tINS | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n397_s0/COUT |
| 4.824 | 0.000 | tNET | RR | 2 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n398_s0/CIN |
| 4.860 | 0.036 | tINS | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n398_s0/COUT |
| 4.860 | 0.000 | tNET | RR | 2 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n399_s0/CIN |
| 4.896 | 0.036 | tINS | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n399_s0/COUT |
| 4.896 | 0.000 | tNET | RR | 2 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n400_s0/CIN |
| 4.932 | 0.036 | tINS | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n400_s0/COUT |
| 4.932 | 0.000 | tNET | RR | 2 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n401_s0/CIN |
| 4.968 | 0.036 | tINS | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n401_s0/COUT |
| 4.968 | 0.000 | tNET | RR | 2 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n402_s0/CIN |
| 5.004 | 0.036 | tINS | RR | 5 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n402_s0/COUT |
| 5.301 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n609_s16/I0 |
| 5.718 | 0.417 | tINS | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n609_s16/F |
| 6.015 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n609_s14/I2 |
| 6.380 | 0.365 | tINS | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n609_s14/F |
| 6.677 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n609_s11/I2 |
| 7.042 | 0.365 | tINS | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n609_s11/F |
| 7.339 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n609_s6/I2 |
| 7.705 | 0.365 | tINS | RR | 5 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n609_s6/F |
| 8.002 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/ctrl_ns_0_s14/I1 |
| 8.410 | 0.409 | tINS | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/ctrl_ns_0_s14/F |
| 8.707 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/ctrl_ns_0_s7/I2 |
| 9.073 | 0.365 | tINS | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/ctrl_ns_0_s7/F |
| 9.370 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/ctrl_ns_0_s3/I1 |
| 9.778 | 0.409 | tINS | RR | 4 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/ctrl_ns_0_s3/F |
| 10.075 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/ctrl_ns_0_s2/I0 |
| 10.492 | 0.417 | tINS | RR | 9 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/ctrl_ns_0_s2/F |
| 10.789 | 0.297 | tNET | RR | 2 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n9_s0/I1 |
| 11.221 | 0.432 | tINS | RF | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n9_s0/COUT |
| 11.221 | 0.000 | tNET | FF | 2 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n10_s0/CIN |
| 11.257 | 0.036 | tINS | FR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n10_s0/COUT |
| 11.257 | 0.000 | tNET | RR | 2 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n11_s0/CIN |
| 11.293 | 0.036 | tINS | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n11_s0/COUT |
| 11.293 | 0.000 | tNET | RR | 2 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n12_s0/CIN |
| 11.329 | 0.036 | tINS | RR | 11 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/n12_s0/COUT |
| 11.626 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/data_cnt_r_8_s9/I1 |
| 12.035 | 0.409 | tINS | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/data_cnt_r_8_s9/F |
| 12.332 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/data_cnt_r_8_s6/I3 |
| 12.540 | 0.208 | tINS | RR | 10 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/data_cnt_r_8_s6/F |
| 12.837 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/data_cnt_r_8_s3/I3 |
| 13.045 | 0.208 | tINS | RR | 9 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/data_cnt_r_8_s3/F |
| 13.342 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/data_cnt_r_0_s1/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | |||
| 10.000 | 0.000 | apb_clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | apb_clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 1202 | apb_clk_ibuf/O |
| 10.297 | 0.297 | tNET | RR | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/data_cnt_r_0_s1/CLK |
| 10.073 | -0.224 | tSu | 1 | u_gorv32_plus/u_gw_spi_1/u_spi_ctrl/data_cnt_r_0_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 22 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.297, 100.000% |
| Arrival Data Path Delay: | cell: 7.126, 54.630%; route: 5.643, 43.259%; tC2Q: 0.275, 2.111% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.297, 100.000% |