Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\I3C_DUAL_CLK\data\i3c_dual_clock.v
C:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\I3C_DUAL_CLK\data\i3c_dual_clock_top.v
GowinSynthesis Constraints File ---
Version GowinSynthesis V1.9.8.01
Part Number GW1NS-LV4CQN48C7/I6
Device GW1NS-4C
Created Time Mon Nov 01 11:12:36 2021
Legal Announcement Copyright (C)2014-2021 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module I3C_Dual_Clock_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.406s, Elapsed time = 0h 0m 0.428s, Peak memory usage = 52.730MB
Running netlist conversion:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.022s, Peak memory usage = 52.730MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.126s, Peak memory usage = 52.730MB
    Optimizing Phase 1: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.152s, Peak memory usage = 52.730MB
    Optimizing Phase 2: CPU time = 0h 0m 0.187s, Elapsed time = 0h 0m 0.192s, Peak memory usage = 52.730MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.037s, Peak memory usage = 52.730MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 52.730MB
    Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.021s, Peak memory usage = 52.730MB
    Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 52.730MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.145s, Peak memory usage = 52.730MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.06s, Peak memory usage = 52.730MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.04s, Peak memory usage = 52.730MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 7s, Elapsed time = 0h 0m 7s, Peak memory usage = 65.082MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.39s, Elapsed time = 0h 0m 0.384s, Peak memory usage = 65.082MB
Generate output files:
    CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.162s, Peak memory usage = 65.082MB
Total Time and Memory Usage CPU time = 0h 0m 8s, Elapsed time = 0h 0m 8s, Peak memory usage = 65.082MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 82
I/O Buf 82
    IBUF 46
    OBUF 33
    TBUF 2
    IOBUF 1
Register 1466
    DFFE 256
    DFFP 24
    DFFPE 31
    DFFC 628
    DFFCE 527
LUT 1908
    LUT2 263
    LUT3 608
    LUT4 1037
ALU 119
    ALU 119
INV 4
    INV 4

Resource Utilization Summary

Resource Usage Utilization
Logic 2031(1912 LUTs, 119 ALUs) / 4608 44%
Register 1466 / 3570 41%
  --Register as Latch 0 / 3570 0%
  --Register as FF 1466 / 3570 41%
BSRAM 0 / 10 0%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
i3c_clk Base 20.000 50.0 0.000 10.000 i3c_clk_ibuf/I
fclk Base 20.000 50.0 0.000 10.000 fclk_ibuf/I

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 i3c_clk 50.0(MHz) 186.3(MHz) 5 TOP
2 fclk 50.0(MHz) 84.6(MHz) 13 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 8.183
Data Arrival Time 12.517
Data Required Time 20.700
From u_i3c_dual_clock_top/u_i3c_controller/m_c_state_9_s0
To u_i3c_dual_clock_top/u_i3c_controller/m_start_cnt_d2_1_s3
Launch Clk fclk[R]
Latch Clk fclk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 fclk
0.000 0.000 tCL RR 1 fclk_ibuf/I
0.728 0.728 tINS RR 1174 fclk_ibuf/O
0.997 0.269 tNET RR 1 u_i3c_dual_clock_top/u_i3c_controller/m_c_state_9_s0/CLK
1.336 0.340 tC2Q RF 8 u_i3c_dual_clock_top/u_i3c_controller/m_c_state_9_s0/Q
1.692 0.356 tNET FF 1 u_i3c_dual_clock_top/u_i3c_controller/n3357_s4/I1
2.506 0.814 tINS FF 10 u_i3c_dual_clock_top/u_i3c_controller/n3357_s4/F
2.862 0.356 tNET FF 1 u_i3c_dual_clock_top/u_i3c_controller/flag_m_rd_bus_Z_s5/I1
3.676 0.814 tINS FF 2 u_i3c_dual_clock_top/u_i3c_controller/flag_m_rd_bus_Z_s5/F
4.032 0.356 tNET FF 1 u_i3c_dual_clock_top/u_i3c_controller/n5214_s3/I0
4.797 0.765 tINS FF 23 u_i3c_dual_clock_top/u_i3c_controller/n5214_s3/F
5.152 0.356 tNET FF 1 u_i3c_dual_clock_top/u_i3c_controller/m_n_state_1_s4/I1
5.967 0.814 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/m_n_state_1_s4/F
6.322 0.356 tNET FF 1 u_i3c_dual_clock_top/u_i3c_controller/m_n_state_1_s2/I2
6.931 0.609 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/m_n_state_1_s2/F
7.287 0.356 tNET FF 1 u_i3c_dual_clock_top/u_i3c_controller/m_n_state_1_s1/I0
8.052 0.765 tINS FF 3 u_i3c_dual_clock_top/u_i3c_controller/m_n_state_1_s1/F
8.408 0.356 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2962_s0/I1
9.182 0.774 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2962_s0/COUT
9.182 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2963_s0/CIN
9.224 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2963_s0/COUT
9.224 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2964_s0/CIN
9.266 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2964_s0/COUT
9.266 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2965_s0/CIN
9.309 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2965_s0/COUT
9.309 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2966_s0/CIN
9.351 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2966_s0/COUT
9.351 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2967_s0/CIN
9.393 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2967_s0/COUT
9.393 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2968_s0/CIN
9.435 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2968_s0/COUT
9.435 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2969_s0/CIN
9.478 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2969_s0/COUT
9.478 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2970_s0/CIN
9.520 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2970_s0/COUT
9.520 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2971_s0/CIN
9.562 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2971_s0/COUT
9.562 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2972_s0/CIN
9.604 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2972_s0/COUT
9.604 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2973_s0/CIN
9.646 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2973_s0/COUT
9.646 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2974_s0/CIN
9.689 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2974_s0/COUT
9.689 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2975_s0/CIN
9.731 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2975_s0/COUT
9.731 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2976_s0/CIN
9.773 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2976_s0/COUT
9.773 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2977_s0/CIN
9.815 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2977_s0/COUT
9.815 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2978_s0/CIN
9.858 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2978_s0/COUT
9.858 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2979_s0/CIN
9.900 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2979_s0/COUT
9.900 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2980_s0/CIN
9.942 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2980_s0/COUT
9.942 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2981_s0/CIN
9.984 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2981_s0/COUT
9.984 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2982_s0/CIN
10.027 0.042 tINS FF 16 u_i3c_dual_clock_top/u_i3c_controller/n2982_s0/COUT
10.382 0.356 tNET FF 1 u_i3c_dual_clock_top/u_i3c_controller/n3041_s4/I1
11.197 0.814 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n3041_s4/F
11.552 0.356 tNET FF 1 u_i3c_dual_clock_top/u_i3c_controller/n3041_s5/I2
12.161 0.609 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n3041_s5/F
12.517 0.356 tNET FF 1 u_i3c_dual_clock_top/u_i3c_controller/m_start_cnt_d2_1_s3/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 fclk
20.000 0.000 tCL RR 1 fclk_ibuf/I
20.728 0.728 tINS RR 1174 fclk_ibuf/O
20.997 0.269 tNET RR 1 u_i3c_dual_clock_top/u_i3c_controller/m_start_cnt_d2_1_s3/CLK
20.700 -0.296 tSu 1 u_i3c_dual_clock_top/u_i3c_controller/m_start_cnt_d2_1_s3
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 13
Arrival Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%
Arrival Data Path Delay: cell: 7.624, 66.179%; route: 3.557, 30.873%; tC2Q: 0.340, 2.948%
Required Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%

Path 2

Path Summary:
Slack 8.233
Data Arrival Time 12.467
Data Required Time 20.700
From u_i3c_dual_clock_top/u_i3c_controller/m_c_state_9_s0
To u_i3c_dual_clock_top/u_i3c_controller/m_start_cnt_d3_1_s3
Launch Clk fclk[R]
Latch Clk fclk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 fclk
0.000 0.000 tCL RR 1 fclk_ibuf/I
0.728 0.728 tINS RR 1174 fclk_ibuf/O
0.997 0.269 tNET RR 1 u_i3c_dual_clock_top/u_i3c_controller/m_c_state_9_s0/CLK
1.336 0.340 tC2Q RF 8 u_i3c_dual_clock_top/u_i3c_controller/m_c_state_9_s0/Q
1.692 0.356 tNET FF 1 u_i3c_dual_clock_top/u_i3c_controller/n3357_s4/I1
2.506 0.814 tINS FF 10 u_i3c_dual_clock_top/u_i3c_controller/n3357_s4/F
2.862 0.356 tNET FF 1 u_i3c_dual_clock_top/u_i3c_controller/flag_m_rd_bus_Z_s5/I1
3.676 0.814 tINS FF 2 u_i3c_dual_clock_top/u_i3c_controller/flag_m_rd_bus_Z_s5/F
4.032 0.356 tNET FF 1 u_i3c_dual_clock_top/u_i3c_controller/n5214_s3/I0
4.797 0.765 tINS FF 23 u_i3c_dual_clock_top/u_i3c_controller/n5214_s3/F
5.152 0.356 tNET FF 1 u_i3c_dual_clock_top/u_i3c_controller/m_n_state_1_s4/I1
5.967 0.814 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/m_n_state_1_s4/F
6.322 0.356 tNET FF 1 u_i3c_dual_clock_top/u_i3c_controller/m_n_state_1_s2/I2
6.931 0.609 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/m_n_state_1_s2/F
7.287 0.356 tNET FF 1 u_i3c_dual_clock_top/u_i3c_controller/m_n_state_1_s1/I0
8.052 0.765 tINS FF 3 u_i3c_dual_clock_top/u_i3c_controller/m_n_state_1_s1/F
8.408 0.356 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2962_s0/I1
9.182 0.774 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2962_s0/COUT
9.182 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2963_s0/CIN
9.224 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2963_s0/COUT
9.224 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2964_s0/CIN
9.266 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2964_s0/COUT
9.266 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2965_s0/CIN
9.309 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2965_s0/COUT
9.309 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2966_s0/CIN
9.351 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2966_s0/COUT
9.351 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2967_s0/CIN
9.393 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2967_s0/COUT
9.393 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2968_s0/CIN
9.435 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2968_s0/COUT
9.435 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2969_s0/CIN
9.478 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2969_s0/COUT
9.478 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2970_s0/CIN
9.520 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2970_s0/COUT
9.520 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2971_s0/CIN
9.562 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2971_s0/COUT
9.562 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2972_s0/CIN
9.604 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2972_s0/COUT
9.604 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2973_s0/CIN
9.646 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2973_s0/COUT
9.646 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2974_s0/CIN
9.689 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2974_s0/COUT
9.689 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2975_s0/CIN
9.731 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2975_s0/COUT
9.731 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2976_s0/CIN
9.773 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2976_s0/COUT
9.773 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2977_s0/CIN
9.815 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2977_s0/COUT
9.815 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2978_s0/CIN
9.858 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2978_s0/COUT
9.858 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2979_s0/CIN
9.900 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2979_s0/COUT
9.900 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2980_s0/CIN
9.942 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2980_s0/COUT
9.942 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2981_s0/CIN
9.984 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2981_s0/COUT
9.984 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2982_s0/CIN
10.027 0.042 tINS FF 16 u_i3c_dual_clock_top/u_i3c_controller/n2982_s0/COUT
10.382 0.356 tNET FF 1 u_i3c_dual_clock_top/u_i3c_controller/n3090_s4/I0
11.147 0.765 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n3090_s4/F
11.503 0.356 tNET FF 1 u_i3c_dual_clock_top/u_i3c_controller/n3090_s5/I2
12.112 0.609 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n3090_s5/F
12.467 0.356 tNET FF 1 u_i3c_dual_clock_top/u_i3c_controller/m_start_cnt_d3_1_s3/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 fclk
20.000 0.000 tCL RR 1 fclk_ibuf/I
20.728 0.728 tINS RR 1174 fclk_ibuf/O
20.997 0.269 tNET RR 1 u_i3c_dual_clock_top/u_i3c_controller/m_start_cnt_d3_1_s3/CLK
20.700 -0.296 tSu 1 u_i3c_dual_clock_top/u_i3c_controller/m_start_cnt_d3_1_s3
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 13
Arrival Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%
Arrival Data Path Delay: cell: 7.574, 66.032%; route: 3.557, 31.007%; tC2Q: 0.340, 2.961%
Required Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%

Path 3

Path Summary:
Slack 9.148
Data Arrival Time 11.552
Data Required Time 20.700
From u_i3c_dual_clock_top/u_i3c_controller/m_c_state_9_s0
To u_i3c_dual_clock_top/u_i3c_controller/flag_m_data_keep_s0
Launch Clk fclk[R]
Latch Clk fclk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 fclk
0.000 0.000 tCL RR 1 fclk_ibuf/I
0.728 0.728 tINS RR 1174 fclk_ibuf/O
0.997 0.269 tNET RR 1 u_i3c_dual_clock_top/u_i3c_controller/m_c_state_9_s0/CLK
1.336 0.340 tC2Q RF 8 u_i3c_dual_clock_top/u_i3c_controller/m_c_state_9_s0/Q
1.692 0.356 tNET FF 1 u_i3c_dual_clock_top/u_i3c_controller/n3357_s4/I1
2.506 0.814 tINS FF 10 u_i3c_dual_clock_top/u_i3c_controller/n3357_s4/F
2.862 0.356 tNET FF 1 u_i3c_dual_clock_top/u_i3c_controller/flag_m_rd_bus_Z_s5/I1
3.676 0.814 tINS FF 2 u_i3c_dual_clock_top/u_i3c_controller/flag_m_rd_bus_Z_s5/F
4.032 0.356 tNET FF 1 u_i3c_dual_clock_top/u_i3c_controller/n5214_s3/I0
4.797 0.765 tINS FF 23 u_i3c_dual_clock_top/u_i3c_controller/n5214_s3/F
5.152 0.356 tNET FF 1 u_i3c_dual_clock_top/u_i3c_controller/m_n_state_1_s4/I1
5.967 0.814 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/m_n_state_1_s4/F
6.322 0.356 tNET FF 1 u_i3c_dual_clock_top/u_i3c_controller/m_n_state_1_s2/I2
6.931 0.609 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/m_n_state_1_s2/F
7.287 0.356 tNET FF 1 u_i3c_dual_clock_top/u_i3c_controller/m_n_state_1_s1/I0
8.052 0.765 tINS FF 3 u_i3c_dual_clock_top/u_i3c_controller/m_n_state_1_s1/F
8.408 0.356 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2962_s1/I1
9.182 0.774 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2962_s1/COUT
9.182 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2963_s1/CIN
9.224 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2963_s1/COUT
9.224 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2964_s1/CIN
9.266 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2964_s1/COUT
9.266 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2965_s1/CIN
9.309 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2965_s1/COUT
9.309 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2966_s1/CIN
9.351 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2966_s1/COUT
9.351 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2967_s1/CIN
9.393 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2967_s1/COUT
9.393 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2968_s1/CIN
9.435 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2968_s1/COUT
9.435 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2969_s1/CIN
9.478 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2969_s1/COUT
9.478 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2970_s1/CIN
9.520 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2970_s1/COUT
9.520 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2971_s1/CIN
9.562 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2971_s1/COUT
9.562 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2972_s1/CIN
9.604 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2972_s1/COUT
9.604 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2973_s1/CIN
9.646 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2973_s1/COUT
9.646 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2974_s1/CIN
9.689 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2974_s1/COUT
9.689 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2975_s1/CIN
9.731 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2975_s1/COUT
9.731 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2976_s1/CIN
9.773 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2976_s1/COUT
9.773 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2977_s1/CIN
9.815 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2977_s1/COUT
9.815 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2978_s1/CIN
9.858 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2978_s1/COUT
9.858 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2979_s1/CIN
9.900 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2979_s1/COUT
9.900 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2980_s1/CIN
9.942 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2980_s1/COUT
9.942 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2981_s1/CIN
9.984 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2981_s1/COUT
9.984 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2982_s1/CIN
10.027 0.042 tINS FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2982_s1/COUT
10.382 0.356 tNET FF 1 u_i3c_dual_clock_top/u_i3c_controller/n3762_s0/I1
11.197 0.814 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n3762_s0/F
11.552 0.356 tNET FF 1 u_i3c_dual_clock_top/u_i3c_controller/flag_m_data_keep_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 fclk
20.000 0.000 tCL RR 1 fclk_ibuf/I
20.728 0.728 tINS RR 1174 fclk_ibuf/O
20.997 0.269 tNET RR 1 u_i3c_dual_clock_top/u_i3c_controller/flag_m_data_keep_s0/CLK
20.700 -0.296 tSu 1 u_i3c_dual_clock_top/u_i3c_controller/flag_m_data_keep_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 12
Arrival Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%
Arrival Data Path Delay: cell: 7.015, 66.457%; route: 3.201, 30.326%; tC2Q: 0.340, 3.217%
Required Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%

Path 4

Path Summary:
Slack 9.148
Data Arrival Time 11.552
Data Required Time 20.700
From u_i3c_dual_clock_top/u_i3c_controller/m_c_state_9_s0
To u_i3c_dual_clock_top/u_i3c_controller/m_start_cnt_d1_0_s0
Launch Clk fclk[R]
Latch Clk fclk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 fclk
0.000 0.000 tCL RR 1 fclk_ibuf/I
0.728 0.728 tINS RR 1174 fclk_ibuf/O
0.997 0.269 tNET RR 1 u_i3c_dual_clock_top/u_i3c_controller/m_c_state_9_s0/CLK
1.336 0.340 tC2Q RF 8 u_i3c_dual_clock_top/u_i3c_controller/m_c_state_9_s0/Q
1.692 0.356 tNET FF 1 u_i3c_dual_clock_top/u_i3c_controller/n3357_s4/I1
2.506 0.814 tINS FF 10 u_i3c_dual_clock_top/u_i3c_controller/n3357_s4/F
2.862 0.356 tNET FF 1 u_i3c_dual_clock_top/u_i3c_controller/flag_m_rd_bus_Z_s5/I1
3.676 0.814 tINS FF 2 u_i3c_dual_clock_top/u_i3c_controller/flag_m_rd_bus_Z_s5/F
4.032 0.356 tNET FF 1 u_i3c_dual_clock_top/u_i3c_controller/n5214_s3/I0
4.797 0.765 tINS FF 23 u_i3c_dual_clock_top/u_i3c_controller/n5214_s3/F
5.152 0.356 tNET FF 1 u_i3c_dual_clock_top/u_i3c_controller/m_n_state_1_s4/I1
5.967 0.814 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/m_n_state_1_s4/F
6.322 0.356 tNET FF 1 u_i3c_dual_clock_top/u_i3c_controller/m_n_state_1_s2/I2
6.931 0.609 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/m_n_state_1_s2/F
7.287 0.356 tNET FF 1 u_i3c_dual_clock_top/u_i3c_controller/m_n_state_1_s1/I0
8.052 0.765 tINS FF 3 u_i3c_dual_clock_top/u_i3c_controller/m_n_state_1_s1/F
8.408 0.356 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2962_s0/I1
9.182 0.774 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2962_s0/COUT
9.182 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2963_s0/CIN
9.224 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2963_s0/COUT
9.224 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2964_s0/CIN
9.266 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2964_s0/COUT
9.266 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2965_s0/CIN
9.309 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2965_s0/COUT
9.309 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2966_s0/CIN
9.351 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2966_s0/COUT
9.351 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2967_s0/CIN
9.393 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2967_s0/COUT
9.393 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2968_s0/CIN
9.435 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2968_s0/COUT
9.435 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2969_s0/CIN
9.478 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2969_s0/COUT
9.478 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2970_s0/CIN
9.520 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2970_s0/COUT
9.520 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2971_s0/CIN
9.562 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2971_s0/COUT
9.562 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2972_s0/CIN
9.604 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2972_s0/COUT
9.604 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2973_s0/CIN
9.646 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2973_s0/COUT
9.646 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2974_s0/CIN
9.689 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2974_s0/COUT
9.689 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2975_s0/CIN
9.731 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2975_s0/COUT
9.731 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2976_s0/CIN
9.773 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2976_s0/COUT
9.773 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2977_s0/CIN
9.815 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2977_s0/COUT
9.815 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2978_s0/CIN
9.858 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2978_s0/COUT
9.858 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2979_s0/CIN
9.900 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2979_s0/COUT
9.900 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2980_s0/CIN
9.942 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2980_s0/COUT
9.942 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2981_s0/CIN
9.984 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2981_s0/COUT
9.984 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2982_s0/CIN
10.027 0.042 tINS FF 16 u_i3c_dual_clock_top/u_i3c_controller/n2982_s0/COUT
10.382 0.356 tNET FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2990_s1/I1
11.197 0.814 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2990_s1/F
11.552 0.356 tNET FF 1 u_i3c_dual_clock_top/u_i3c_controller/m_start_cnt_d1_0_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 fclk
20.000 0.000 tCL RR 1 fclk_ibuf/I
20.728 0.728 tINS RR 1174 fclk_ibuf/O
20.997 0.269 tNET RR 1 u_i3c_dual_clock_top/u_i3c_controller/m_start_cnt_d1_0_s0/CLK
20.700 -0.296 tSu 1 u_i3c_dual_clock_top/u_i3c_controller/m_start_cnt_d1_0_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 12
Arrival Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%
Arrival Data Path Delay: cell: 7.015, 66.457%; route: 3.201, 30.326%; tC2Q: 0.340, 3.217%
Required Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%

Path 5

Path Summary:
Slack 9.197
Data Arrival Time 11.503
Data Required Time 20.700
From u_i3c_dual_clock_top/u_i3c_controller/m_c_state_9_s0
To u_i3c_dual_clock_top/u_i3c_controller/m_start_cnt_d3_0_s3
Launch Clk fclk[R]
Latch Clk fclk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 fclk
0.000 0.000 tCL RR 1 fclk_ibuf/I
0.728 0.728 tINS RR 1174 fclk_ibuf/O
0.997 0.269 tNET RR 1 u_i3c_dual_clock_top/u_i3c_controller/m_c_state_9_s0/CLK
1.336 0.340 tC2Q RF 8 u_i3c_dual_clock_top/u_i3c_controller/m_c_state_9_s0/Q
1.692 0.356 tNET FF 1 u_i3c_dual_clock_top/u_i3c_controller/n3357_s4/I1
2.506 0.814 tINS FF 10 u_i3c_dual_clock_top/u_i3c_controller/n3357_s4/F
2.862 0.356 tNET FF 1 u_i3c_dual_clock_top/u_i3c_controller/flag_m_rd_bus_Z_s5/I1
3.676 0.814 tINS FF 2 u_i3c_dual_clock_top/u_i3c_controller/flag_m_rd_bus_Z_s5/F
4.032 0.356 tNET FF 1 u_i3c_dual_clock_top/u_i3c_controller/n5214_s3/I0
4.797 0.765 tINS FF 23 u_i3c_dual_clock_top/u_i3c_controller/n5214_s3/F
5.152 0.356 tNET FF 1 u_i3c_dual_clock_top/u_i3c_controller/m_n_state_1_s4/I1
5.967 0.814 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/m_n_state_1_s4/F
6.322 0.356 tNET FF 1 u_i3c_dual_clock_top/u_i3c_controller/m_n_state_1_s2/I2
6.931 0.609 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/m_n_state_1_s2/F
7.287 0.356 tNET FF 1 u_i3c_dual_clock_top/u_i3c_controller/m_n_state_1_s1/I0
8.052 0.765 tINS FF 3 u_i3c_dual_clock_top/u_i3c_controller/m_n_state_1_s1/F
8.408 0.356 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2962_s0/I1
9.182 0.774 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2962_s0/COUT
9.182 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2963_s0/CIN
9.224 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2963_s0/COUT
9.224 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2964_s0/CIN
9.266 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2964_s0/COUT
9.266 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2965_s0/CIN
9.309 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2965_s0/COUT
9.309 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2966_s0/CIN
9.351 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2966_s0/COUT
9.351 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2967_s0/CIN
9.393 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2967_s0/COUT
9.393 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2968_s0/CIN
9.435 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2968_s0/COUT
9.435 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2969_s0/CIN
9.478 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2969_s0/COUT
9.478 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2970_s0/CIN
9.520 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2970_s0/COUT
9.520 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2971_s0/CIN
9.562 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2971_s0/COUT
9.562 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2972_s0/CIN
9.604 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2972_s0/COUT
9.604 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2973_s0/CIN
9.646 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2973_s0/COUT
9.646 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2974_s0/CIN
9.689 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2974_s0/COUT
9.689 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2975_s0/CIN
9.731 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2975_s0/COUT
9.731 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2976_s0/CIN
9.773 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2976_s0/COUT
9.773 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2977_s0/CIN
9.815 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2977_s0/COUT
9.815 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2978_s0/CIN
9.858 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2978_s0/COUT
9.858 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2979_s0/CIN
9.900 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2979_s0/COUT
9.900 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2980_s0/CIN
9.942 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2980_s0/COUT
9.942 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2981_s0/CIN
9.984 0.042 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n2981_s0/COUT
9.984 0.000 tNET FF 2 u_i3c_dual_clock_top/u_i3c_controller/n2982_s0/CIN
10.027 0.042 tINS FF 16 u_i3c_dual_clock_top/u_i3c_controller/n2982_s0/COUT
10.382 0.356 tNET FF 1 u_i3c_dual_clock_top/u_i3c_controller/n3091_s3/I0
11.147 0.765 tINS FF 1 u_i3c_dual_clock_top/u_i3c_controller/n3091_s3/F
11.503 0.356 tNET FF 1 u_i3c_dual_clock_top/u_i3c_controller/m_start_cnt_d3_0_s3/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 fclk
20.000 0.000 tCL RR 1 fclk_ibuf/I
20.728 0.728 tINS RR 1174 fclk_ibuf/O
20.997 0.269 tNET RR 1 u_i3c_dual_clock_top/u_i3c_controller/m_start_cnt_d3_0_s3/CLK
20.700 -0.296 tSu 1 u_i3c_dual_clock_top/u_i3c_controller/m_start_cnt_d3_0_s3
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 12
Arrival Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%
Arrival Data Path Delay: cell: 6.965, 66.298%; route: 3.201, 30.469%; tC2Q: 0.340, 3.233%
Required Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%