Timing Messages
Report Title | Timing Analysis Report |
Design File | E:\myWork\IP\releaseVerify\RefDesign\Interface\19811\Gowin_IES_RefDesign\GW_IES\impl\gwsynthesis\GW_IES.vg |
Physical Constraints File | E:\myWork\IP\releaseVerify\RefDesign\Interface\19811\Gowin_IES_RefDesign\GW_IES\src\gowin_empu_m1.cst |
Timing Constraint File | E:\myWork\IP\releaseVerify\RefDesign\Interface\19811\Gowin_IES_RefDesign\GW_IES\src\m1_esc.sdc |
Version | V1.9.8.11 |
Part Number | GW2A-LV55PG484C8/I7 |
Device | GW2A-55 |
Device Version | C |
Created Time | Fri Mar 31 16:09:38 2023 |
Legal Announcement | Copyright (C)2014-2023 Gowin Semiconductor Corporation. All rights reserved. |
Timing Summaries
STA Tool Run Summary:
Setup Delay Model | Slow 0.95V 85C C8/I7 |
Hold Delay Model | Fast 1.05V 0C C8/I7 |
Numbers of Paths Analyzed | 51494 |
Numbers of Endpoints Analyzed | 38342 |
Numbers of Falling Endpoints | 0 |
Numbers of Setup Violated Endpoints | 0 |
Numbers of Hold Violated Endpoints | 0 |
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Objects |
---|---|---|---|---|---|---|---|---|
mii_rx1 | Base | 40.000 | 25.000 | 0.000 | 12.500 | mii_rx_clk_1 | ||
mii_rx0 | Base | 40.000 | 25.000 | 0.000 | 12.500 | mii_rx_clk_0 | ||
esc_sysclk | Base | 10.000 | 100.000 | 0.000 | 5.000 | clk100 | ||
clkin | Base | 40.000 | 25.000 | 0.000 | 20.000 | clk25 | ||
mcu_sysclk | Base | 12.500 | 80.000 | 0.000 | 6.250 | MCU_CLK | ||
u_Gowin_rPLL/rpll_inst/CLKOUTP.default_gen_clk | Generated | 10.000 | 100.000 | 0.000 | 5.000 | clk25_ibuf/I | clkin | u_Gowin_rPLL/rpll_inst/CLKOUTP |
u_Gowin_rPLL/rpll_inst/CLKOUTD.default_gen_clk | Generated | 40.000 | 25.000 | 0.000 | 20.000 | clk25_ibuf/I | clkin | u_Gowin_rPLL/rpll_inst/CLKOUTD |
u_Gowin_rPLL/rpll_inst/CLKOUTD3.default_gen_clk | Generated | 30.000 | 33.333 | 0.000 | 15.000 | clk25_ibuf/I | clkin | u_Gowin_rPLL/rpll_inst/CLKOUTD3 |
u_Gowin_rPLL_MCU/rpll_inst/CLKOUTP.default_gen_clk | Generated | 12.500 | 80.000 | 0.000 | 6.250 | clk25_ibuf/I | clkin | u_Gowin_rPLL_MCU/rpll_inst/CLKOUTP |
u_Gowin_rPLL_MCU/rpll_inst/CLKOUTD.default_gen_clk | Generated | 25.000 | 40.000 | 0.000 | 12.500 | clk25_ibuf/I | clkin | u_Gowin_rPLL_MCU/rpll_inst/CLKOUTD |
u_Gowin_rPLL_MCU/rpll_inst/CLKOUTD3.default_gen_clk | Generated | 37.500 | 26.667 | 0.000 | 18.750 | clk25_ibuf/I | clkin | u_Gowin_rPLL_MCU/rpll_inst/CLKOUTD3 |
Max Frequency Summary:
NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | mii_rx1 | 25.000(MHz) | 149.084(MHz) | 9 | TOP |
2 | mii_rx0 | 25.000(MHz) | 137.992(MHz) | 8 | TOP |
3 | esc_sysclk | 100.000(MHz) | 111.719(MHz) | 6 | TOP |
4 | clkin | 25.000(MHz) | 328.426(MHz) | 4 | TOP |
5 | mcu_sysclk | 80.000(MHz) | 83.403(MHz) | 13 | TOP |
No timing paths to get frequency of u_Gowin_rPLL/rpll_inst/CLKOUTP.default_gen_clk!
No timing paths to get frequency of u_Gowin_rPLL/rpll_inst/CLKOUTD.default_gen_clk!
No timing paths to get frequency of u_Gowin_rPLL/rpll_inst/CLKOUTD3.default_gen_clk!
No timing paths to get frequency of u_Gowin_rPLL_MCU/rpll_inst/CLKOUTP.default_gen_clk!
No timing paths to get frequency of u_Gowin_rPLL_MCU/rpll_inst/CLKOUTD.default_gen_clk!
No timing paths to get frequency of u_Gowin_rPLL_MCU/rpll_inst/CLKOUTD3.default_gen_clk!
Total Negative Slack Summary:
Clock Name | Analysis Type | Endpoints TNS | Number of Endpoints |
---|---|---|---|
mii_rx1 | Setup | 0.000 | 0 |
mii_rx1 | Hold | 0.000 | 0 |
mii_rx0 | Setup | 0.000 | 0 |
mii_rx0 | Hold | 0.000 | 0 |
esc_sysclk | Setup | 0.000 | 0 |
esc_sysclk | Hold | 0.000 | 0 |
clkin | Setup | 0.000 | 0 |
clkin | Hold | 0.000 | 0 |
mcu_sysclk | Setup | 0.000 | 0 |
mcu_sysclk | Hold | 0.000 | 0 |
u_Gowin_rPLL/rpll_inst/CLKOUTP.default_gen_clk | Setup | 0.000 | 0 |
u_Gowin_rPLL/rpll_inst/CLKOUTP.default_gen_clk | Hold | 0.000 | 0 |
u_Gowin_rPLL/rpll_inst/CLKOUTD.default_gen_clk | Setup | 0.000 | 0 |
u_Gowin_rPLL/rpll_inst/CLKOUTD.default_gen_clk | Hold | 0.000 | 0 |
u_Gowin_rPLL/rpll_inst/CLKOUTD3.default_gen_clk | Setup | 0.000 | 0 |
u_Gowin_rPLL/rpll_inst/CLKOUTD3.default_gen_clk | Hold | 0.000 | 0 |
u_Gowin_rPLL_MCU/rpll_inst/CLKOUTP.default_gen_clk | Setup | 0.000 | 0 |
u_Gowin_rPLL_MCU/rpll_inst/CLKOUTP.default_gen_clk | Hold | 0.000 | 0 |
u_Gowin_rPLL_MCU/rpll_inst/CLKOUTD.default_gen_clk | Setup | 0.000 | 0 |
u_Gowin_rPLL_MCU/rpll_inst/CLKOUTD.default_gen_clk | Hold | 0.000 | 0 |
u_Gowin_rPLL_MCU/rpll_inst/CLKOUTD3.default_gen_clk | Setup | 0.000 | 0 |
u_Gowin_rPLL_MCU/rpll_inst/CLKOUTD3.default_gen_clk | Hold | 0.000 | 0 |
Timing Details
Path Slacks Table:
Setup Paths Table
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 0.510 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_1_s0/Q | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/dtcm_sel_s0/D | mcu_sysclk:[R] | mcu_sysclk:[R] | 12.500 | 0.000 | 11.955 |
2 | 1.018 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_1_s0/Q | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/itcm_sel_s0/D | mcu_sysclk:[R] | mcu_sysclk:[R] | 12.500 | 0.000 | 11.447 |
3 | 1.049 | U_IES_Top/IES_inst/u_fmmu_mem/ecat_addr_1d_1_s0/Q | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[3].u_fmmu_reg/ecat_rdata_5_s0/D | esc_sysclk:[R] | esc_sysclk:[R] | 10.000 | 0.000 | 8.916 |
4 | 1.129 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/u_excpt/micro_code_de_s0/Q | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_nvic/u_ahb/en_itcm_core_0_s0/CE | mcu_sysclk:[R] | mcu_sysclk:[R] | 12.500 | 0.000 | 11.336 |
5 | 1.129 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/u_excpt/micro_code_de_s0/Q | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_nvic/u_ahb/en_itcm_core_1_s0/CE | mcu_sysclk:[R] | mcu_sysclk:[R] | 12.500 | 0.000 | 11.336 |
6 | 1.154 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_1_s0/Q | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/z_flag_mux_s0/D | mcu_sysclk:[R] | mcu_sysclk:[R] | 12.500 | 0.000 | 11.311 |
7 | 1.238 | U_IES_Top/IES_inst/u_fmmu_mem/ecat_addr_1d_1_s0/Q | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[3].u_fmmu_reg/pdi_rdata_2_s0/D | esc_sysclk:[R] | esc_sysclk:[R] | 10.000 | 0.000 | 8.727 |
8 | 1.238 | U_IES_Top/IES_inst/u_fmmu_mem/ecat_addr_1d_1_s0/Q | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[3].u_fmmu_reg/ecat_rdata_2_s0/D | esc_sysclk:[R] | esc_sysclk:[R] | 10.000 | 0.000 | 8.727 |
9 | 1.241 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/u_excpt/micro_code_de_s0/Q | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/sel_wf_v_s0/CE | mcu_sysclk:[R] | mcu_sysclk:[R] | 12.500 | 0.000 | 11.224 |
10 | 1.241 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/u_excpt/micro_code_de_s0/Q | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/v_flag_wf_s0/CE | mcu_sysclk:[R] | mcu_sysclk:[R] | 12.500 | 0.000 | 11.224 |
11 | 1.355 | U_IES_Top/IES_inst/u_fmmu_mem/ecat_addr_1d_3_s0/Q | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[1].u_fmmu_reg/ecat_rdata_0_s0/D | esc_sysclk:[R] | esc_sysclk:[R] | 10.000 | 0.000 | 8.610 |
12 | 1.371 | U_IES_Top/IES_inst/u_fmmu_mem/ecat_addr_1d_3_s0/Q | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[1].u_fmmu_reg/pdi_rdata_0_s0/D | esc_sysclk:[R] | esc_sysclk:[R] | 10.000 | 0.000 | 8.594 |
13 | 1.465 | u_button/out_s0/Q | U_IES_Top/IES_inst/u_i2c/rx_shift_buf_4_s0/CE | clkin:[R] | esc_sysclk:[R] | 10.000 | 0.683 | 7.783 |
14 | 1.469 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem3_mem3_0_1_s/DO[0] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/DI[1] | mcu_sysclk:[R] | mcu_sysclk:[R] | 12.500 | 0.000 | 10.997 |
15 | 1.474 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_1_s0/Q | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/biu_commit_reg_s0/D | mcu_sysclk:[R] | mcu_sysclk:[R] | 12.500 | 0.000 | 10.991 |
16 | 1.474 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_1_s0/Q | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_5_s/DI[0] | mcu_sysclk:[R] | mcu_sysclk:[R] | 12.500 | 0.000 | 10.991 |
17 | 1.479 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_1_s0/Q | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem3_mem3_0_1_s/AD[6] | mcu_sysclk:[R] | mcu_sysclk:[R] | 12.500 | 0.000 | 10.987 |
18 | 1.518 | U_IES_Top/IES_inst/u_fmmu_mem/ecat_addr_1d_1_s0/Q | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[3].u_fmmu_reg/pdi_rdata_5_s0/D | esc_sysclk:[R] | esc_sysclk:[R] | 10.000 | 0.000 | 8.447 |
19 | 1.522 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_1_s0/Q | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/n_flag_s0/D | mcu_sysclk:[R] | mcu_sysclk:[R] | 12.500 | 0.000 | 10.943 |
20 | 1.524 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/u_excpt/micro_code_de_s0/Q | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/v_flag_au_s0/CE | mcu_sysclk:[R] | mcu_sysclk:[R] | 12.500 | 0.000 | 10.941 |
21 | 1.534 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_1_s0/Q | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/u_excpt/dp_ipsr_7to2_6_s0/D | mcu_sysclk:[R] | mcu_sysclk:[R] | 12.500 | 0.000 | 10.931 |
22 | 1.540 | U_IES_Top/IES_inst/u_fmmu_mem/ecat_addr_1d_1_s0/Q | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[3].u_fmmu_reg/pdi_rdata_6_s0/D | esc_sysclk:[R] | esc_sysclk:[R] | 10.000 | 0.000 | 8.425 |
23 | 1.540 | U_IES_Top/IES_inst/u_fmmu_mem/ecat_addr_1d_1_s0/Q | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[3].u_fmmu_reg/ecat_rdata_6_s0/D | esc_sysclk:[R] | esc_sysclk:[R] | 10.000 | 0.000 | 8.425 |
24 | 1.544 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_1_s0/Q | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/u_excpt/dp_ipsr_7to2_5_s0/D | mcu_sysclk:[R] | mcu_sysclk:[R] | 12.500 | 0.000 | 10.921 |
25 | 1.549 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_1_s0/Q | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem3_mem3_0_2_s/AD[6] | mcu_sysclk:[R] | mcu_sysclk:[R] | 12.500 | 0.000 | 10.916 |
Hold Paths Table
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 0.311 | U_IES_Top/IES_inst/u_phy_manager/rx_shift_buf_15_s0/Q | U_IES_Top/IES_inst/u_phy_manager/phy_rdata_0_s8/DI[3] | esc_sysclk:[R] | esc_sysclk:[R] | 0.000 | 0.000 | 0.323 |
2 | 0.311 | U_IES_Top/IES_inst/u_phy_manager/rx_shift_buf_10_s0/Q | U_IES_Top/IES_inst/u_phy_manager/phy_rdata_0_s6/DI[2] | esc_sysclk:[R] | esc_sysclk:[R] | 0.000 | 0.000 | 0.323 |
3 | 0.313 | U_IES_Top/IES_inst/u_pdi_sm/status_reg_6_s0/Q | U_IES_Top/IES_inst/u_pdi_sm/sm_status_reg_pdi_0_s4/DI[2] | esc_sysclk:[R] | esc_sysclk:[R] | 0.000 | 0.000 | 0.325 |
4 | 0.314 | U_IES_Top/IES_inst/u_phy_manager/rx_shift_buf_14_s0/Q | U_IES_Top/IES_inst/u_phy_manager/phy_rdata_0_s8/DI[2] | esc_sysclk:[R] | esc_sysclk:[R] | 0.000 | 0.000 | 0.326 |
5 | 0.314 | U_IES_Top/IES_inst/u_phy_manager/rx_shift_buf_13_s0/Q | U_IES_Top/IES_inst/u_phy_manager/phy_rdata_0_s8/DI[1] | esc_sysclk:[R] | esc_sysclk:[R] | 0.000 | 0.000 | 0.326 |
6 | 0.314 | U_IES_Top/IES_inst/u_phy_manager/rx_shift_buf_9_s0/Q | U_IES_Top/IES_inst/u_phy_manager/phy_rdata_0_s6/DI[1] | esc_sysclk:[R] | esc_sysclk:[R] | 0.000 | 0.000 | 0.326 |
7 | 0.314 | U_IES_Top/IES_inst/u_phy_manager/rx_shift_buf_8_s0/Q | U_IES_Top/IES_inst/u_phy_manager/phy_rdata_0_s6/DI[0] | esc_sysclk:[R] | esc_sysclk:[R] | 0.000 | 0.000 | 0.326 |
8 | 0.314 | U_IES_Top/IES_inst/u_phy_manager/rx_shift_buf_3_s0/Q | U_IES_Top/IES_inst/u_phy_manager/phy_rdata_0_s2/DI[3] | esc_sysclk:[R] | esc_sysclk:[R] | 0.000 | 0.000 | 0.326 |
9 | 0.314 | U_IES_Top/IES_inst/u_phy_manager/rx_shift_buf_2_s0/Q | U_IES_Top/IES_inst/u_phy_manager/phy_rdata_0_s2/DI[2] | esc_sysclk:[R] | esc_sysclk:[R] | 0.000 | 0.000 | 0.326 |
10 | 0.314 | U_IES_Top/IES_inst/u_phy_manager/rx_shift_buf_1_s0/Q | U_IES_Top/IES_inst/u_phy_manager/phy_rdata_0_s2/DI[1] | esc_sysclk:[R] | esc_sysclk:[R] | 0.000 | 0.000 | 0.326 |
11 | 0.321 | U_IES_Top/IES_inst/u_pdi_sm/req_valid_s0/Q | U_IES_Top/IES_inst/u_pdi_search_m_top/pdi_search_m_gen[0].u_pdi_search_m/first_addr_tmp_0_s0/CE | esc_sysclk:[R] | esc_sysclk:[R] | 0.000 | 0.000 | 0.332 |
12 | 0.321 | U_IES_Top/IES_inst/u_pdi_sm/req_valid_s0/Q | U_IES_Top/IES_inst/u_pdi_search_m_top/pdi_search_m_gen[0].u_pdi_search_m/first_addr_tmp_1_s0/CE | esc_sysclk:[R] | esc_sysclk:[R] | 0.000 | 0.000 | 0.332 |
13 | 0.321 | U_IES_Top/IES_inst/u_pdi_sm/req_valid_s0/Q | U_IES_Top/IES_inst/u_pdi_search_m_top/pdi_search_m_gen[0].u_pdi_search_m/first_addr_tmp_2_s0/CE | esc_sysclk:[R] | esc_sysclk:[R] | 0.000 | 0.000 | 0.332 |
14 | 0.321 | U_IES_Top/IES_inst/u_pdi_sm/req_valid_s0/Q | U_IES_Top/IES_inst/u_pdi_search_m_top/pdi_search_m_gen[0].u_pdi_search_m/first_addr_tmp_3_s0/CE | esc_sysclk:[R] | esc_sysclk:[R] | 0.000 | 0.000 | 0.332 |
15 | 0.321 | U_IES_Top/IES_inst/u_pdi_sm/req_valid_s0/Q | U_IES_Top/IES_inst/u_pdi_search_m_top/pdi_search_m_gen[0].u_pdi_search_m/first_addr_tmp_7_s0/CE | esc_sysclk:[R] | esc_sysclk:[R] | 0.000 | 0.000 | 0.332 |
16 | 0.321 | U_IES_Top/IES_inst/u_pdi_sm/req_valid_s0/Q | U_IES_Top/IES_inst/u_pdi_search_m_top/pdi_search_m_gen[0].u_pdi_search_m/first_addr_tmp_15_s0/CE | esc_sysclk:[R] | esc_sysclk:[R] | 0.000 | 0.000 | 0.332 |
17 | 0.322 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb12/HREADYOUT_s0/Q | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb12/HRESP_0_s0/CE | mcu_sysclk:[R] | mcu_sysclk:[R] | 0.000 | 0.000 | 0.333 |
18 | 0.322 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb4/HREADYOUT_s0/Q | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb4/HRESP_0_s0/CE | mcu_sysclk:[R] | mcu_sysclk:[R] | 0.000 | 0.000 | 0.333 |
19 | 0.322 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb_spi_flash/HREADYOUT_s0/Q | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb_spi_flash/HRESP_0_s0/CE | mcu_sysclk:[R] | mcu_sysclk:[R] | 0.000 | 0.000 | 0.333 |
20 | 0.322 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb_can/HREADYOUT_s0/Q | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb_can/HRESP_0_s0/CE | mcu_sysclk:[R] | mcu_sysclk:[R] | 0.000 | 0.000 | 0.333 |
21 | 0.323 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb11/HREADYOUT_s0/Q | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb11/HRESP_0_s0/CE | mcu_sysclk:[R] | mcu_sysclk:[R] | 0.000 | 0.000 | 0.334 |
22 | 0.323 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_ahb/haddr_en_reg_s0/Q | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_ahb/asel_ppb_reg_s0/CE | mcu_sysclk:[R] | mcu_sysclk:[R] | 0.000 | 0.000 | 0.334 |
23 | 0.324 | U_IES_Top/IES_inst/u_pdi_sm/req_valid_s0/Q | U_IES_Top/IES_inst/u_pdi_search_m_top/pdi_search_m_gen[0].u_pdi_search_m/first_addr_tmp_8_s0/CE | esc_sysclk:[R] | esc_sysclk:[R] | 0.000 | 0.000 | 0.335 |
24 | 0.324 | U_IES_Top/IES_inst/u_pdi_sm/req_valid_s0/Q | U_IES_Top/IES_inst/u_pdi_search_m_top/pdi_search_m_gen[0].u_pdi_search_m/first_addr_tmp_9_s0/CE | esc_sysclk:[R] | esc_sysclk:[R] | 0.000 | 0.000 | 0.335 |
25 | 0.324 | U_IES_Top/IES_inst/u_pdi_sm/req_valid_s0/Q | U_IES_Top/IES_inst/u_pdi_search_m_top/pdi_search_m_gen[0].u_pdi_search_m/first_addr_tmp_13_s0/CE | esc_sysclk:[R] | esc_sysclk:[R] | 0.000 | 0.000 | 0.335 |
Recovery Paths Table
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 4.942 | u_button/out_s0/Q | U_IES_Top/IES_inst/fifo_top_inst1/fifo_inst/Equal.mem_Equal.mem_0_0_s/RESETB | clkin:[R] | esc_sysclk:[R] | 10.000 | 0.683 | 3.902 |
2 | 4.942 | u_button/out_s0/Q | U_IES_Top/IES_inst/fifo_top_inst0/fifo_inst/Equal.mem_Equal.mem_0_0_s/RESETB | clkin:[R] | esc_sysclk:[R] | 10.000 | 0.683 | 3.902 |
3 | 4.942 | u_button/out_s0/Q | U_IES_Top/IES_inst/u_dp_mem/mem_u_mem_u_0_0_s/RESETB | clkin:[R] | esc_sysclk:[R] | 10.000 | 0.683 | 3.902 |
4 | 4.942 | u_button/out_s0/Q | U_IES_Top/IES_inst/u_dp_mem/mem_u_mem_u_0_0_s/RESETA | clkin:[R] | esc_sysclk:[R] | 10.000 | 0.683 | 3.902 |
5 | 4.942 | u_button/out_s0/Q | U_IES_Top/IES_inst/u_dp_mem/mem_mem_0_3_s/RESETB | clkin:[R] | esc_sysclk:[R] | 10.000 | 0.683 | 3.902 |
6 | 4.942 | u_button/out_s0/Q | U_IES_Top/IES_inst/u_dp_mem/mem_mem_0_3_s/RESETA | clkin:[R] | esc_sysclk:[R] | 10.000 | 0.683 | 3.902 |
7 | 4.942 | u_button/out_s0/Q | U_IES_Top/IES_inst/u_dp_mem/mem_mem_0_2_s/RESETB | clkin:[R] | esc_sysclk:[R] | 10.000 | 0.683 | 3.902 |
8 | 4.942 | u_button/out_s0/Q | U_IES_Top/IES_inst/u_dp_mem/mem_mem_0_2_s/RESETA | clkin:[R] | esc_sysclk:[R] | 10.000 | 0.683 | 3.902 |
9 | 4.942 | u_button/out_s0/Q | U_IES_Top/IES_inst/u_dp_mem/mem_mem_0_1_s/RESETB | clkin:[R] | esc_sysclk:[R] | 10.000 | 0.683 | 3.902 |
10 | 4.942 | u_button/out_s0/Q | U_IES_Top/IES_inst/u_dp_mem/mem_mem_0_1_s/RESETA | clkin:[R] | esc_sysclk:[R] | 10.000 | 0.683 | 3.902 |
11 | 4.942 | u_button/out_s0/Q | U_IES_Top/IES_inst/u_dp_mem/mem_mem_0_0_s/RESETB | clkin:[R] | esc_sysclk:[R] | 10.000 | 0.683 | 3.902 |
12 | 4.942 | u_button/out_s0/Q | U_IES_Top/IES_inst/u_dp_mem/mem_mem_0_0_s/RESETA | clkin:[R] | esc_sysclk:[R] | 10.000 | 0.683 | 3.902 |
13 | 5.330 | u_button/out_s0/Q | U_IES_Top/IES_inst/u_mii_enh/phy_er_cnt[1]_0_s3/CLEAR | clkin:[R] | esc_sysclk:[R] | 10.000 | 0.683 | 3.918 |
14 | 5.330 | u_button/out_s0/Q | U_IES_Top/IES_inst/u_mii_enh/phy_er_cnt[1]_1_s3/CLEAR | clkin:[R] | esc_sysclk:[R] | 10.000 | 0.683 | 3.918 |
15 | 5.330 | u_button/out_s0/Q | U_IES_Top/IES_inst/u_mii_enh/phy_er_cnt[1]_4_s3/CLEAR | clkin:[R] | esc_sysclk:[R] | 10.000 | 0.683 | 3.918 |
16 | 5.330 | u_button/out_s0/Q | U_IES_Top/IES_inst/u_mii_enh/phy_er_cnt[1]_2_s1/CLEAR | clkin:[R] | esc_sysclk:[R] | 10.000 | 0.683 | 3.918 |
17 | 5.330 | u_button/out_s0/Q | U_IES_Top/IES_inst/u_mii_enh/phy_er_cnt[1]_3_s1/CLEAR | clkin:[R] | esc_sysclk:[R] | 10.000 | 0.683 | 3.918 |
18 | 5.330 | u_button/out_s0/Q | U_IES_Top/IES_inst/u_mii_enh/phy_er_cnt[1]_5_s1/CLEAR | clkin:[R] | esc_sysclk:[R] | 10.000 | 0.683 | 3.918 |
19 | 5.330 | u_button/out_s0/Q | U_IES_Top/IES_inst/u_mii_enh/phy_er_cnt[0]_2_s1/CLEAR | clkin:[R] | esc_sysclk:[R] | 10.000 | 0.683 | 3.918 |
20 | 5.330 | u_button/out_s0/Q | U_IES_Top/IES_inst/u_mii_enh/enh_cnt_9_s0/CLEAR | clkin:[R] | esc_sysclk:[R] | 10.000 | 0.683 | 3.918 |
21 | 5.330 | u_button/out_s0/Q | U_IES_Top/IES_inst/u_mii_enh/enh_link_err_int_1_s0/CLEAR | clkin:[R] | esc_sysclk:[R] | 10.000 | 0.683 | 3.918 |
22 | 5.330 | u_button/out_s0/Q | U_IES_Top/IES_inst/u_mii_enh/enh_link_err_int_0_s0/CLEAR | clkin:[R] | esc_sysclk:[R] | 10.000 | 0.683 | 3.918 |
23 | 5.330 | u_button/out_s0/Q | U_IES_Top/IES_inst/u_mii_enh/mii_link_rr_0_s0/CLEAR | clkin:[R] | esc_sysclk:[R] | 10.000 | 0.683 | 3.918 |
24 | 5.330 | u_button/out_s0/Q | U_IES_Top/IES_inst/u_mii_enh/mii_link_rr_1_s0/CLEAR | clkin:[R] | esc_sysclk:[R] | 10.000 | 0.683 | 3.918 |
25 | 5.330 | u_button/out_s0/Q | U_IES_Top/IES_inst/u_mii_enh/p_10us_s0/CLEAR | clkin:[R] | esc_sysclk:[R] | 10.000 | 0.683 | 3.918 |
Removal Paths Table
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 1.199 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q | U_IES_Top/IES_inst/u_AHB/rstn_reg1_s0/CLEAR | mcu_sysclk:[R] | mcu_sysclk:[R] | 0.000 | 0.000 | 1.210 |
2 | 1.199 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0/CLEAR | mcu_sysclk:[R] | mcu_sysclk:[R] | 0.000 | 0.000 | 1.210 |
3 | 1.659 | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0/Q | U_IES_Top/IES_inst/u_AHB/c_state.TRANS_TYPE_s4/CLEAR | mcu_sysclk:[R] | mcu_sysclk:[R] | 0.000 | 0.000 | 1.670 |
4 | 1.659 | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0/Q | U_IES_Top/IES_inst/u_AHB/rd_finished_tmp_s5/CLEAR | mcu_sysclk:[R] | mcu_sysclk:[R] | 0.000 | 0.000 | 1.670 |
5 | 1.659 | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0/Q | U_IES_Top/IES_inst/u_AHB/wr_finished_tmp_s6/CLEAR | mcu_sysclk:[R] | mcu_sysclk:[R] | 0.000 | 0.000 | 1.670 |
6 | 1.659 | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0/Q | U_IES_Top/IES_inst/u_AHB/beat_cnt_0_s3/CLEAR | mcu_sysclk:[R] | mcu_sysclk:[R] | 0.000 | 0.000 | 1.670 |
7 | 1.659 | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0/Q | U_IES_Top/IES_inst/u_AHB/axi_rready_reg1_s5/CLEAR | mcu_sysclk:[R] | mcu_sysclk:[R] | 0.000 | 0.000 | 1.670 |
8 | 1.659 | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0/Q | U_IES_Top/IES_inst/u_AHB/axi_wstrb_1_s3/CLEAR | mcu_sysclk:[R] | mcu_sysclk:[R] | 0.000 | 0.000 | 1.670 |
9 | 1.659 | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0/Q | U_IES_Top/IES_inst/u_AHB/axi_wstrb_3_s3/CLEAR | mcu_sysclk:[R] | mcu_sysclk:[R] | 0.000 | 0.000 | 1.670 |
10 | 1.659 | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0/Q | U_IES_Top/IES_inst/u_AHB/axi_wvalid_reg1_s5/CLEAR | mcu_sysclk:[R] | mcu_sysclk:[R] | 0.000 | 0.000 | 1.670 |
11 | 1.659 | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0/Q | U_IES_Top/IES_inst/u_AHB/axi_arvalid_reg1_s5/CLEAR | mcu_sysclk:[R] | mcu_sysclk:[R] | 0.000 | 0.000 | 1.670 |
12 | 1.659 | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0/Q | U_IES_Top/IES_inst/u_AHB/axi_awvalid_reg1_s7/CLEAR | mcu_sysclk:[R] | mcu_sysclk:[R] | 0.000 | 0.000 | 1.670 |
13 | 1.659 | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0/Q | U_IES_Top/IES_inst/u_AHB/c_state.IDLE_s1/PRESET | mcu_sysclk:[R] | mcu_sysclk:[R] | 0.000 | 0.000 | 1.670 |
14 | 1.659 | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0/Q | U_IES_Top/IES_inst/u_AHB/c_state.SAVE_CTRL_s1/CLEAR | mcu_sysclk:[R] | mcu_sysclk:[R] | 0.000 | 0.000 | 1.670 |
15 | 1.659 | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0/Q | U_IES_Top/IES_inst/u_AHB/c_state.SR_SM_s1/CLEAR | mcu_sysclk:[R] | mcu_sysclk:[R] | 0.000 | 0.000 | 1.670 |
16 | 1.659 | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0/Q | U_IES_Top/IES_inst/u_AHB/rd_finished_pulse_reg1_s1/CLEAR | mcu_sysclk:[R] | mcu_sysclk:[R] | 0.000 | 0.000 | 1.670 |
17 | 1.659 | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0/Q | U_IES_Top/IES_inst/u_AHB/wr_finished_pulse_reg1_s1/CLEAR | mcu_sysclk:[R] | mcu_sysclk:[R] | 0.000 | 0.000 | 1.670 |
18 | 1.659 | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0/Q | U_IES_Top/IES_inst/u_AHB/beat_cnt_1_s1/CLEAR | mcu_sysclk:[R] | mcu_sysclk:[R] | 0.000 | 0.000 | 1.670 |
19 | 1.659 | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0/Q | U_IES_Top/IES_inst/u_AHB/beat_cnt_2_s1/CLEAR | mcu_sysclk:[R] | mcu_sysclk:[R] | 0.000 | 0.000 | 1.670 |
20 | 1.659 | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0/Q | U_IES_Top/IES_inst/u_AHB/beat_cnt_3_s1/CLEAR | mcu_sysclk:[R] | mcu_sysclk:[R] | 0.000 | 0.000 | 1.670 |
21 | 1.659 | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0/Q | U_IES_Top/IES_inst/u_AHB/beat_cnt_4_s1/CLEAR | mcu_sysclk:[R] | mcu_sysclk:[R] | 0.000 | 0.000 | 1.670 |
22 | 1.659 | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0/Q | U_IES_Top/IES_inst/u_AHB/sr_finished_tmp_s1/CLEAR | mcu_sysclk:[R] | mcu_sysclk:[R] | 0.000 | 0.000 | 1.670 |
23 | 1.659 | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0/Q | U_IES_Top/IES_inst/u_AHB/release_busy_s1/CLEAR | mcu_sysclk:[R] | mcu_sysclk:[R] | 0.000 | 0.000 | 1.670 |
24 | 1.659 | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0/Q | U_IES_Top/IES_inst/u_AHB/access_end_reg2_s0/CLEAR | mcu_sysclk:[R] | mcu_sysclk:[R] | 0.000 | 0.000 | 1.670 |
25 | 1.659 | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0/Q | U_IES_Top/IES_inst/u_AHB/rd_finished_pulse_reg2_s0/CLEAR | mcu_sysclk:[R] | mcu_sysclk:[R] | 0.000 | 0.000 | 1.670 |
Minimum Pulse Width Table:
Number | Slack | Actual Width | Required Width | Type | Clock | Objects |
---|---|---|---|---|---|---|
1 | 3.923 | 4.923 | 1.000 | Low Pulse Width | esc_sysclk | U_IES_Top/IES_inst/mii_link_0_s0 |
2 | 3.923 | 4.923 | 1.000 | Low Pulse Width | esc_sysclk | U_IES_Top/IES_inst/u_rx_top/u_mii_rx_0/offset_tmp_7_s0 |
3 | 3.923 | 4.923 | 1.000 | Low Pulse Width | esc_sysclk | U_IES_Top/IES_inst/u_rx_top/u_mii_rx_0/system_time_10_s0 |
4 | 3.923 | 4.923 | 1.000 | Low Pulse Width | esc_sysclk | U_IES_Top/IES_inst/u_rx_top/u_mii_rx_0/rcv_time_tmp_10_s0 |
5 | 3.923 | 4.923 | 1.000 | Low Pulse Width | esc_sysclk | U_IES_Top/IES_inst/u_rx_top/u_mii_rx_1/rcv_time_tmp_10_s0 |
6 | 3.923 | 4.923 | 1.000 | Low Pulse Width | esc_sysclk | U_IES_Top/IES_inst/u_tx_top/u0_mii_tx/frame_type_14_s0 |
7 | 3.923 | 4.923 | 1.000 | Low Pulse Width | esc_sysclk | U_IES_Top/IES_inst/u_tx_top/u0_mii_tx/frame_type_6_s0 |
8 | 3.923 | 4.923 | 1.000 | Low Pulse Width | esc_sysclk | U_IES_Top/IES_inst/u_tx_top/u0_mii_tx/frame_type_2_s0 |
9 | 3.923 | 4.923 | 1.000 | Low Pulse Width | esc_sysclk | U_IES_Top/IES_inst/u_tx_top/u0_mii_tx/frame_type_0_s0 |
10 | 3.923 | 4.923 | 1.000 | Low Pulse Width | esc_sysclk | U_IES_Top/IES_inst/u_tx_top/u0_mii_tx/tx_info_data_valid_1d_s0 |
Timing Report By Analysis Type:
Setup Analysis Report
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 0.510 |
Data Arrival Time | 12.198 |
Data Required Time | 12.708 |
From | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_1_s0 |
To | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/dtcm_sel_s0 |
Launch Clk | mcu_sysclk:[R] |
Latch Clk | mcu_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | mcu_sysclk | ||||
0.000 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R66C9[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_1_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 8 | R66C9[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_1_s0/Q |
1.327 | 0.852 | tNET | FF | 4 | R58C10 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_1_s0/RAD[1] |
1.844 | 0.517 | tINS | FF | 8 | R58C10 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_1_s0/DO[0] |
3.278 | 1.433 | tNET | FF | 1 | R48C10[3][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_4_s2/I0 |
3.827 | 0.549 | tINS | FR | 1 | R48C10[3][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_4_s2/F |
3.828 | 0.001 | tNET | RR | 1 | R48C10[3][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_4_s1/I1 |
4.345 | 0.517 | tINS | RF | 1 | R48C10[3][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_4_s1/F |
4.758 | 0.413 | tNET | FF | 1 | R48C8[3][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_4_s0/I1 |
5.275 | 0.517 | tINS | FF | 2 | R48C8[3][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_4_s0/F |
6.040 | 0.765 | tNET | FF | 2 | R42C6[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/I1 |
6.411 | 0.371 | tINS | FF | 1 | R42C6[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/COUT |
6.411 | 0.000 | tNET | FF | 2 | R42C7[0][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/CIN |
6.446 | 0.035 | tINS | FF | 1 | R42C7[0][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/COUT |
6.446 | 0.000 | tNET | FF | 2 | R42C7[0][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/CIN |
6.482 | 0.035 | tINS | FF | 1 | R42C7[0][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/COUT |
6.482 | 0.000 | tNET | FF | 2 | R42C7[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/CIN |
6.517 | 0.035 | tINS | FF | 1 | R42C7[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/COUT |
6.517 | 0.000 | tNET | FF | 2 | R42C7[1][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/CIN |
6.552 | 0.035 | tINS | FF | 1 | R42C7[1][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/COUT |
6.552 | 0.000 | tNET | FF | 2 | R42C7[2][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/CIN |
6.587 | 0.035 | tINS | FF | 1 | R42C7[2][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/COUT |
6.587 | 0.000 | tNET | FF | 2 | R42C7[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/CIN |
6.622 | 0.035 | tINS | FF | 1 | R42C7[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/COUT |
6.622 | 0.000 | tNET | FF | 2 | R42C8[0][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/CIN |
6.658 | 0.035 | tINS | FF | 1 | R42C8[0][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/COUT |
6.658 | 0.000 | tNET | FF | 2 | R42C8[0][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/CIN |
6.693 | 0.035 | tINS | FF | 1 | R42C8[0][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/COUT |
6.693 | 0.000 | tNET | FF | 2 | R42C8[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/CIN |
6.728 | 0.035 | tINS | FF | 1 | R42C8[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/COUT |
6.728 | 0.000 | tNET | FF | 2 | R42C8[1][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/CIN |
6.763 | 0.035 | tINS | FF | 1 | R42C8[1][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/COUT |
6.763 | 0.000 | tNET | FF | 2 | R42C8[2][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/CIN |
6.798 | 0.035 | tINS | FF | 1 | R42C8[2][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/COUT |
6.798 | 0.000 | tNET | FF | 2 | R42C8[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/CIN |
6.834 | 0.035 | tINS | FF | 1 | R42C8[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/COUT |
6.834 | 0.000 | tNET | FF | 2 | R42C9[0][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/CIN |
6.869 | 0.035 | tINS | FF | 1 | R42C9[0][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/COUT |
6.869 | 0.000 | tNET | FF | 2 | R42C9[0][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/CIN |
6.904 | 0.035 | tINS | FF | 1 | R42C9[0][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/COUT |
6.904 | 0.000 | tNET | FF | 2 | R42C9[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_19_s/CIN |
7.374 | 0.470 | tINS | FF | 4 | R42C9[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_19_s/SUM |
8.585 | 1.211 | tNET | FF | 1 | R43C10[0][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s8/I0 |
9.047 | 0.462 | tINS | FR | 1 | R43C10[0][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s8/F |
9.049 | 0.001 | tNET | RR | 1 | R43C10[0][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s6/I2 |
9.619 | 0.570 | tINS | RR | 1 | R43C10[0][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s6/F |
9.620 | 0.001 | tNET | RR | 1 | R43C10[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s1/I2 |
9.991 | 0.371 | tINS | RF | 3 | R43C10[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s1/F |
10.656 | 0.665 | tNET | FF | 1 | R46C10[2][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_itcm_sel_s2/I3 |
11.211 | 0.555 | tINS | FF | 2 | R46C10[2][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_itcm_sel_s2/F |
11.628 | 0.418 | tNET | FF | 1 | R47C12[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_dtcm_sel_s0/I2 |
12.198 | 0.570 | tINS | FR | 1 | R47C12[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_dtcm_sel_s0/F |
12.198 | 0.000 | tNET | RR | 1 | R47C12[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/dtcm_sel_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
12.500 | 12.500 | active clock edge time | ||||
12.500 | 0.000 | mcu_sysclk | ||||
12.500 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
12.743 | 0.243 | tNET | RR | 1 | R47C12[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/dtcm_sel_s0/CLK |
12.708 | -0.035 | tSu | 1 | R47C12[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/dtcm_sel_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 12.500 |
Logic Level | 13 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 5.962, 49.869%; route: 5.761, 48.190%; tC2Q: 0.232, 1.941% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path2
Path Summary:
Slack | 1.018 |
Data Arrival Time | 11.690 |
Data Required Time | 12.708 |
From | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_1_s0 |
To | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/itcm_sel_s0 |
Launch Clk | mcu_sysclk:[R] |
Latch Clk | mcu_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | mcu_sysclk | ||||
0.000 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R66C9[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_1_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 8 | R66C9[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_1_s0/Q |
1.327 | 0.852 | tNET | FF | 4 | R58C10 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_1_s0/RAD[1] |
1.844 | 0.517 | tINS | FF | 8 | R58C10 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_1_s0/DO[0] |
3.278 | 1.433 | tNET | FF | 1 | R48C10[3][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_4_s2/I0 |
3.827 | 0.549 | tINS | FR | 1 | R48C10[3][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_4_s2/F |
3.828 | 0.001 | tNET | RR | 1 | R48C10[3][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_4_s1/I1 |
4.345 | 0.517 | tINS | RF | 1 | R48C10[3][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_4_s1/F |
4.758 | 0.413 | tNET | FF | 1 | R48C8[3][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_4_s0/I1 |
5.275 | 0.517 | tINS | FF | 2 | R48C8[3][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_4_s0/F |
6.040 | 0.765 | tNET | FF | 2 | R42C6[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/I1 |
6.411 | 0.371 | tINS | FF | 1 | R42C6[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/COUT |
6.411 | 0.000 | tNET | FF | 2 | R42C7[0][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/CIN |
6.446 | 0.035 | tINS | FF | 1 | R42C7[0][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/COUT |
6.446 | 0.000 | tNET | FF | 2 | R42C7[0][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/CIN |
6.482 | 0.035 | tINS | FF | 1 | R42C7[0][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/COUT |
6.482 | 0.000 | tNET | FF | 2 | R42C7[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/CIN |
6.517 | 0.035 | tINS | FF | 1 | R42C7[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/COUT |
6.517 | 0.000 | tNET | FF | 2 | R42C7[1][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/CIN |
6.552 | 0.035 | tINS | FF | 1 | R42C7[1][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/COUT |
6.552 | 0.000 | tNET | FF | 2 | R42C7[2][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/CIN |
6.587 | 0.035 | tINS | FF | 1 | R42C7[2][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/COUT |
6.587 | 0.000 | tNET | FF | 2 | R42C7[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/CIN |
6.622 | 0.035 | tINS | FF | 1 | R42C7[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/COUT |
6.622 | 0.000 | tNET | FF | 2 | R42C8[0][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/CIN |
6.658 | 0.035 | tINS | FF | 1 | R42C8[0][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/COUT |
6.658 | 0.000 | tNET | FF | 2 | R42C8[0][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/CIN |
6.693 | 0.035 | tINS | FF | 1 | R42C8[0][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/COUT |
6.693 | 0.000 | tNET | FF | 2 | R42C8[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/CIN |
6.728 | 0.035 | tINS | FF | 1 | R42C8[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/COUT |
6.728 | 0.000 | tNET | FF | 2 | R42C8[1][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/CIN |
6.763 | 0.035 | tINS | FF | 1 | R42C8[1][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/COUT |
6.763 | 0.000 | tNET | FF | 2 | R42C8[2][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/CIN |
6.798 | 0.035 | tINS | FF | 1 | R42C8[2][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/COUT |
6.798 | 0.000 | tNET | FF | 2 | R42C8[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/CIN |
6.834 | 0.035 | tINS | FF | 1 | R42C8[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/COUT |
6.834 | 0.000 | tNET | FF | 2 | R42C9[0][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/CIN |
6.869 | 0.035 | tINS | FF | 1 | R42C9[0][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/COUT |
6.869 | 0.000 | tNET | FF | 2 | R42C9[0][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/CIN |
6.904 | 0.035 | tINS | FF | 1 | R42C9[0][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/COUT |
6.904 | 0.000 | tNET | FF | 2 | R42C9[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_19_s/CIN |
7.374 | 0.470 | tINS | FF | 4 | R42C9[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_19_s/SUM |
8.585 | 1.211 | tNET | FF | 1 | R43C10[0][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s8/I0 |
9.047 | 0.462 | tINS | FR | 1 | R43C10[0][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s8/F |
9.049 | 0.001 | tNET | RR | 1 | R43C10[0][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s6/I2 |
9.619 | 0.570 | tINS | RR | 1 | R43C10[0][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s6/F |
9.620 | 0.001 | tNET | RR | 1 | R43C10[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s1/I2 |
9.991 | 0.371 | tINS | RF | 3 | R43C10[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s1/F |
10.656 | 0.665 | tNET | FF | 1 | R46C10[2][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_itcm_sel_s2/I3 |
11.226 | 0.570 | tINS | FR | 2 | R46C10[2][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_itcm_sel_s2/F |
11.228 | 0.003 | tNET | RR | 1 | R46C10[0][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_itcm_sel_s0/I2 |
11.690 | 0.462 | tINS | RR | 1 | R46C10[0][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_itcm_sel_s0/F |
11.690 | 0.000 | tNET | RR | 1 | R46C10[0][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/itcm_sel_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
12.500 | 12.500 | active clock edge time | ||||
12.500 | 0.000 | mcu_sysclk | ||||
12.500 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
12.743 | 0.243 | tNET | RR | 1 | R46C10[0][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/itcm_sel_s0/CLK |
12.708 | -0.035 | tSu | 1 | R46C10[0][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/itcm_sel_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 12.500 |
Logic Level | 13 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 5.869, 51.269%; route: 5.346, 46.704%; tC2Q: 0.232, 2.027% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path3
Path Summary:
Slack | 1.049 |
Data Arrival Time | 9.159 |
Data Required Time | 10.208 |
From | U_IES_Top/IES_inst/u_fmmu_mem/ecat_addr_1d_1_s0 |
To | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[3].u_fmmu_reg/ecat_rdata_5_s0 |
Launch Clk | esc_sysclk:[R] |
Latch Clk | esc_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | esc_sysclk | ||||
0.000 | 0.000 | tCL | RR | 12119 | PLL_R[0] | u_Gowin_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R32C53[1][A] | U_IES_Top/IES_inst/u_fmmu_mem/ecat_addr_1d_1_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 31 | R32C53[1][A] | U_IES_Top/IES_inst/u_fmmu_mem/ecat_addr_1d_1_s0/Q |
2.366 | 1.891 | tNET | FF | 1 | R49C75[2][B] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[0].u_fmmu_reg/n149_s10/I0 |
2.921 | 0.555 | tINS | FF | 49 | R49C75[2][B] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[0].u_fmmu_reg/n149_s10/F |
5.785 | 2.864 | tNET | FF | 1 | R43C68[3][B] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[3].u_fmmu_reg/n896_s5/I0 |
6.156 | 0.371 | tINS | FF | 1 | R43C68[3][B] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[3].u_fmmu_reg/n896_s5/F |
6.570 | 0.413 | tNET | FF | 1 | R43C65[2][B] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[3].u_fmmu_reg/n896_s3/I0 |
7.140 | 0.570 | tINS | FR | 1 | R43C65[2][B] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[3].u_fmmu_reg/n896_s3/F |
7.141 | 0.001 | tNET | RR | 1 | R43C65[3][A] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[3].u_fmmu_reg/n896_s1/I1 |
7.690 | 0.549 | tINS | RR | 1 | R43C65[3][A] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[3].u_fmmu_reg/n896_s1/F |
7.691 | 0.001 | tNET | RR | 1 | R43C65[1][B] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[3].u_fmmu_reg/n896_s0/I0 |
8.144 | 0.453 | tINS | RF | 2 | R43C65[1][B] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[3].u_fmmu_reg/n896_s0/F |
9.159 | 1.015 | tNET | FF | 1 | R43C69[1][B] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[3].u_fmmu_reg/ecat_rdata_5_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | esc_sysclk | ||||
10.000 | 0.000 | tCL | RR | 12119 | PLL_R[0] | u_Gowin_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R43C69[1][B] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[3].u_fmmu_reg/ecat_rdata_5_s0/CLK |
10.208 | -0.035 | tSu | 1 | R43C69[1][B] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[3].u_fmmu_reg/ecat_rdata_5_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 2.498, 28.017%; route: 6.186, 69.381%; tC2Q: 0.232, 2.602% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path4
Path Summary:
Slack | 1.129 |
Data Arrival Time | 11.579 |
Data Required Time | 12.708 |
From | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/u_excpt/micro_code_de_s0 |
To | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_nvic/u_ahb/en_itcm_core_0_s0 |
Launch Clk | mcu_sysclk:[R] |
Latch Clk | mcu_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | mcu_sysclk | ||||
0.000 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R74C10[2][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/u_excpt/micro_code_de_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 15 | R74C10[2][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/u_excpt/micro_code_de_s0/Q |
1.596 | 1.120 | tNET | FF | 1 | R63C7[0][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_fetch/n108_s3/I3 |
1.967 | 0.371 | tINS | FF | 6 | R63C7[0][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_fetch/n108_s3/F |
4.027 | 2.061 | tNET | FF | 1 | R26C13[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_ahb/biu_rdy_s3/I0 |
4.576 | 0.549 | tINS | FR | 1 | R26C13[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_ahb/biu_rdy_s3/F |
4.749 | 0.172 | tNET | RR | 1 | R26C14[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_ahb/biu_rdy_s1/I3 |
5.298 | 0.549 | tINS | RR | 1 | R26C14[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_ahb/biu_rdy_s1/F |
5.470 | 0.172 | tNET | RR | 1 | R25C14[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_ahb/biu_rdy_s0/I0 |
6.025 | 0.555 | tINS | RF | 195 | R25C14[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_ahb/biu_rdy_s0/F |
7.881 | 1.855 | tNET | FF | 1 | R66C6[3][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/adv_de_to_ex_s1/I0 |
8.398 | 0.517 | tINS | FF | 42 | R66C6[3][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/adv_de_to_ex_s1/F |
9.412 | 1.014 | tNET | FF | 1 | R73C11[0][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/en_itcm_core_sync_Z_s/I3 |
9.961 | 0.549 | tINS | FR | 2 | R73C11[0][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/en_itcm_core_sync_Z_s/F |
11.579 | 1.618 | tNET | RR | 1 | R30C9[2][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_nvic/u_ahb/en_itcm_core_0_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
12.500 | 12.500 | active clock edge time | ||||
12.500 | 0.000 | mcu_sysclk | ||||
12.500 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
12.743 | 0.243 | tNET | RR | 1 | R30C9[2][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_nvic/u_ahb/en_itcm_core_0_s0/CLK |
12.708 | -0.035 | tSu | 1 | R30C9[2][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_nvic/u_ahb/en_itcm_core_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 12.500 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 3.090, 27.258%; route: 8.014, 70.695%; tC2Q: 0.232, 2.047% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path5
Path Summary:
Slack | 1.129 |
Data Arrival Time | 11.579 |
Data Required Time | 12.708 |
From | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/u_excpt/micro_code_de_s0 |
To | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_nvic/u_ahb/en_itcm_core_1_s0 |
Launch Clk | mcu_sysclk:[R] |
Latch Clk | mcu_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | mcu_sysclk | ||||
0.000 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R74C10[2][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/u_excpt/micro_code_de_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 15 | R74C10[2][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/u_excpt/micro_code_de_s0/Q |
1.596 | 1.120 | tNET | FF | 1 | R63C7[0][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_fetch/n108_s3/I3 |
1.967 | 0.371 | tINS | FF | 6 | R63C7[0][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_fetch/n108_s3/F |
4.027 | 2.061 | tNET | FF | 1 | R26C13[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_ahb/biu_rdy_s3/I0 |
4.576 | 0.549 | tINS | FR | 1 | R26C13[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_ahb/biu_rdy_s3/F |
4.749 | 0.172 | tNET | RR | 1 | R26C14[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_ahb/biu_rdy_s1/I3 |
5.298 | 0.549 | tINS | RR | 1 | R26C14[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_ahb/biu_rdy_s1/F |
5.470 | 0.172 | tNET | RR | 1 | R25C14[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_ahb/biu_rdy_s0/I0 |
6.025 | 0.555 | tINS | RF | 195 | R25C14[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_ahb/biu_rdy_s0/F |
7.881 | 1.855 | tNET | FF | 1 | R66C6[3][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/adv_de_to_ex_s1/I0 |
8.398 | 0.517 | tINS | FF | 42 | R66C6[3][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/adv_de_to_ex_s1/F |
9.412 | 1.014 | tNET | FF | 1 | R73C11[0][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/en_itcm_core_sync_Z_s/I3 |
9.961 | 0.549 | tINS | FR | 2 | R73C11[0][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/en_itcm_core_sync_Z_s/F |
11.579 | 1.618 | tNET | RR | 1 | R30C9[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_nvic/u_ahb/en_itcm_core_1_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
12.500 | 12.500 | active clock edge time | ||||
12.500 | 0.000 | mcu_sysclk | ||||
12.500 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
12.743 | 0.243 | tNET | RR | 1 | R30C9[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_nvic/u_ahb/en_itcm_core_1_s0/CLK |
12.708 | -0.035 | tSu | 1 | R30C9[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_nvic/u_ahb/en_itcm_core_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 12.500 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 3.090, 27.258%; route: 8.014, 70.695%; tC2Q: 0.232, 2.047% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path6
Path Summary:
Slack | 1.154 |
Data Arrival Time | 11.554 |
Data Required Time | 12.708 |
From | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_1_s0 |
To | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/z_flag_mux_s0 |
Launch Clk | mcu_sysclk:[R] |
Latch Clk | mcu_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | mcu_sysclk | ||||
0.000 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R66C9[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_1_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 8 | R66C9[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_1_s0/Q |
1.327 | 0.852 | tNET | FF | 4 | R58C10 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_1_s0/RAD[1] |
1.844 | 0.517 | tINS | FF | 8 | R58C10 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_1_s0/DO[0] |
3.278 | 1.433 | tNET | FF | 1 | R48C10[3][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_4_s2/I0 |
3.827 | 0.549 | tINS | FR | 1 | R48C10[3][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_4_s2/F |
3.828 | 0.001 | tNET | RR | 1 | R48C10[3][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_4_s1/I1 |
4.345 | 0.517 | tINS | RF | 1 | R48C10[3][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_4_s1/F |
4.758 | 0.413 | tNET | FF | 1 | R48C8[3][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_4_s0/I1 |
5.275 | 0.517 | tINS | FF | 2 | R48C8[3][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_4_s0/F |
6.040 | 0.765 | tNET | FF | 2 | R42C6[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/I1 |
6.411 | 0.371 | tINS | FF | 1 | R42C6[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/COUT |
6.411 | 0.000 | tNET | FF | 2 | R42C7[0][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/CIN |
6.446 | 0.035 | tINS | FF | 1 | R42C7[0][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/COUT |
6.446 | 0.000 | tNET | FF | 2 | R42C7[0][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/CIN |
6.482 | 0.035 | tINS | FF | 1 | R42C7[0][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/COUT |
6.482 | 0.000 | tNET | FF | 2 | R42C7[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/CIN |
6.517 | 0.035 | tINS | FF | 1 | R42C7[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/COUT |
6.517 | 0.000 | tNET | FF | 2 | R42C7[1][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/CIN |
6.552 | 0.035 | tINS | FF | 1 | R42C7[1][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/COUT |
6.552 | 0.000 | tNET | FF | 2 | R42C7[2][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/CIN |
6.587 | 0.035 | tINS | FF | 1 | R42C7[2][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/COUT |
6.587 | 0.000 | tNET | FF | 2 | R42C7[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/CIN |
6.622 | 0.035 | tINS | FF | 1 | R42C7[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/COUT |
6.622 | 0.000 | tNET | FF | 2 | R42C8[0][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/CIN |
6.658 | 0.035 | tINS | FF | 1 | R42C8[0][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/COUT |
6.658 | 0.000 | tNET | FF | 2 | R42C8[0][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/CIN |
6.693 | 0.035 | tINS | FF | 1 | R42C8[0][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/COUT |
6.693 | 0.000 | tNET | FF | 2 | R42C8[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/CIN |
6.728 | 0.035 | tINS | FF | 1 | R42C8[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/COUT |
6.728 | 0.000 | tNET | FF | 2 | R42C8[1][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/CIN |
6.763 | 0.035 | tINS | FF | 1 | R42C8[1][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/COUT |
6.763 | 0.000 | tNET | FF | 2 | R42C8[2][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/CIN |
7.233 | 0.470 | tINS | FF | 4 | R42C8[2][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/SUM |
8.538 | 1.305 | tNET | FF | 1 | R43C11[2][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s3/I1 |
9.108 | 0.570 | tINS | FR | 1 | R43C11[2][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s3/F |
9.109 | 0.001 | tNET | RR | 1 | R43C11[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s0/I1 |
9.562 | 0.453 | tINS | RF | 1 | R43C11[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s0/F |
10.788 | 1.226 | tNET | FF | 1 | R52C10[3][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/nxt_z_flag_mux_s8/I2 |
11.337 | 0.549 | tINS | FR | 1 | R52C10[3][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/nxt_z_flag_mux_s8/F |
11.337 | 0.000 | tNET | RR | 1 | R52C10[3][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/nxt_z_flag_mux_s6/I0 |
11.442 | 0.105 | tINS | RR | 1 | R52C10[3][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/nxt_z_flag_mux_s6/O |
11.442 | 0.000 | tNET | RR | 1 | R52C10[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/nxt_z_flag_mux_s3/I0 |
11.547 | 0.105 | tINS | RR | 1 | R52C10[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/nxt_z_flag_mux_s3/O |
11.554 | 0.007 | tNET | RR | 1 | R52C10[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/z_flag_mux_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
12.500 | 12.500 | active clock edge time | ||||
12.500 | 0.000 | mcu_sysclk | ||||
12.500 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
12.743 | 0.243 | tNET | RR | 1 | R52C10[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/z_flag_mux_s0/CLK |
12.708 | -0.035 | tSu | 1 | R52C10[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/z_flag_mux_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 12.500 |
Logic Level | 11 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 5.075, 44.869%; route: 6.004, 53.080%; tC2Q: 0.232, 2.051% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path7
Path Summary:
Slack | 1.238 |
Data Arrival Time | 8.970 |
Data Required Time | 10.208 |
From | U_IES_Top/IES_inst/u_fmmu_mem/ecat_addr_1d_1_s0 |
To | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[3].u_fmmu_reg/pdi_rdata_2_s0 |
Launch Clk | esc_sysclk:[R] |
Latch Clk | esc_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | esc_sysclk | ||||
0.000 | 0.000 | tCL | RR | 12119 | PLL_R[0] | u_Gowin_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R32C53[1][A] | U_IES_Top/IES_inst/u_fmmu_mem/ecat_addr_1d_1_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 31 | R32C53[1][A] | U_IES_Top/IES_inst/u_fmmu_mem/ecat_addr_1d_1_s0/Q |
2.366 | 1.891 | tNET | FF | 1 | R49C75[2][B] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[0].u_fmmu_reg/n149_s10/I0 |
2.921 | 0.555 | tINS | FF | 49 | R49C75[2][B] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[0].u_fmmu_reg/n149_s10/F |
6.022 | 3.101 | tNET | FF | 1 | R44C69[1][B] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[3].u_fmmu_reg/n899_s6/I1 |
6.393 | 0.371 | tINS | FF | 1 | R44C69[1][B] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[3].u_fmmu_reg/n899_s6/F |
6.398 | 0.004 | tNET | FF | 1 | R44C69[3][A] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[3].u_fmmu_reg/n899_s4/I3 |
6.953 | 0.555 | tINS | FF | 1 | R44C69[3][A] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[3].u_fmmu_reg/n899_s4/F |
7.200 | 0.247 | tNET | FF | 1 | R44C67[3][B] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[3].u_fmmu_reg/n899_s2/I3 |
7.653 | 0.453 | tINS | FF | 1 | R44C67[3][B] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[3].u_fmmu_reg/n899_s2/F |
8.066 | 0.413 | tNET | FF | 1 | R43C69[3][A] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[3].u_fmmu_reg/n899_s0/I1 |
8.437 | 0.371 | tINS | FF | 2 | R43C69[3][A] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[3].u_fmmu_reg/n899_s0/F |
8.970 | 0.533 | tNET | FF | 1 | R43C69[0][A] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[3].u_fmmu_reg/pdi_rdata_2_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | esc_sysclk | ||||
10.000 | 0.000 | tCL | RR | 12119 | PLL_R[0] | u_Gowin_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R43C69[0][A] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[3].u_fmmu_reg/pdi_rdata_2_s0/CLK |
10.208 | -0.035 | tSu | 1 | R43C69[0][A] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[3].u_fmmu_reg/pdi_rdata_2_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 2.305, 26.413%; route: 6.190, 70.929%; tC2Q: 0.232, 2.658% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path8
Path Summary:
Slack | 1.238 |
Data Arrival Time | 8.970 |
Data Required Time | 10.208 |
From | U_IES_Top/IES_inst/u_fmmu_mem/ecat_addr_1d_1_s0 |
To | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[3].u_fmmu_reg/ecat_rdata_2_s0 |
Launch Clk | esc_sysclk:[R] |
Latch Clk | esc_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | esc_sysclk | ||||
0.000 | 0.000 | tCL | RR | 12119 | PLL_R[0] | u_Gowin_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R32C53[1][A] | U_IES_Top/IES_inst/u_fmmu_mem/ecat_addr_1d_1_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 31 | R32C53[1][A] | U_IES_Top/IES_inst/u_fmmu_mem/ecat_addr_1d_1_s0/Q |
2.366 | 1.891 | tNET | FF | 1 | R49C75[2][B] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[0].u_fmmu_reg/n149_s10/I0 |
2.921 | 0.555 | tINS | FF | 49 | R49C75[2][B] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[0].u_fmmu_reg/n149_s10/F |
6.022 | 3.101 | tNET | FF | 1 | R44C69[1][B] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[3].u_fmmu_reg/n899_s6/I1 |
6.393 | 0.371 | tINS | FF | 1 | R44C69[1][B] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[3].u_fmmu_reg/n899_s6/F |
6.398 | 0.004 | tNET | FF | 1 | R44C69[3][A] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[3].u_fmmu_reg/n899_s4/I3 |
6.953 | 0.555 | tINS | FF | 1 | R44C69[3][A] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[3].u_fmmu_reg/n899_s4/F |
7.200 | 0.247 | tNET | FF | 1 | R44C67[3][B] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[3].u_fmmu_reg/n899_s2/I3 |
7.653 | 0.453 | tINS | FF | 1 | R44C67[3][B] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[3].u_fmmu_reg/n899_s2/F |
8.066 | 0.413 | tNET | FF | 1 | R43C69[3][A] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[3].u_fmmu_reg/n899_s0/I1 |
8.437 | 0.371 | tINS | FF | 2 | R43C69[3][A] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[3].u_fmmu_reg/n899_s0/F |
8.970 | 0.533 | tNET | FF | 1 | R43C69[1][A] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[3].u_fmmu_reg/ecat_rdata_2_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | esc_sysclk | ||||
10.000 | 0.000 | tCL | RR | 12119 | PLL_R[0] | u_Gowin_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R43C69[1][A] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[3].u_fmmu_reg/ecat_rdata_2_s0/CLK |
10.208 | -0.035 | tSu | 1 | R43C69[1][A] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[3].u_fmmu_reg/ecat_rdata_2_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 2.305, 26.413%; route: 6.190, 70.929%; tC2Q: 0.232, 2.658% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path9
Path Summary:
Slack | 1.241 |
Data Arrival Time | 11.468 |
Data Required Time | 12.708 |
From | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/u_excpt/micro_code_de_s0 |
To | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/sel_wf_v_s0 |
Launch Clk | mcu_sysclk:[R] |
Latch Clk | mcu_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | mcu_sysclk | ||||
0.000 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R74C10[2][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/u_excpt/micro_code_de_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 15 | R74C10[2][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/u_excpt/micro_code_de_s0/Q |
1.596 | 1.120 | tNET | FF | 1 | R63C7[0][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_fetch/n108_s3/I3 |
1.967 | 0.371 | tINS | FF | 6 | R63C7[0][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_fetch/n108_s3/F |
4.027 | 2.061 | tNET | FF | 1 | R26C13[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_ahb/biu_rdy_s3/I0 |
4.576 | 0.549 | tINS | FR | 1 | R26C13[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_ahb/biu_rdy_s3/F |
4.749 | 0.172 | tNET | RR | 1 | R26C14[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_ahb/biu_rdy_s1/I3 |
5.298 | 0.549 | tINS | RR | 1 | R26C14[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_ahb/biu_rdy_s1/F |
5.470 | 0.172 | tNET | RR | 1 | R25C14[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_ahb/biu_rdy_s0/I0 |
6.025 | 0.555 | tINS | RF | 195 | R25C14[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_ahb/biu_rdy_s0/F |
8.308 | 2.282 | tNET | FF | 1 | R72C9[2][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/write_flags_ex_Z_s/I0 |
8.863 | 0.555 | tINS | FF | 6 | R72C9[2][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/write_flags_ex_Z_s/F |
9.566 | 0.703 | tNET | FF | 1 | R65C11[0][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/update_v_ex_Z_s0/I3 |
10.028 | 0.462 | tINS | FR | 3 | R65C11[0][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/update_v_ex_Z_s0/F |
11.468 | 1.440 | tNET | RR | 1 | R42C15[0][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/sel_wf_v_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
12.500 | 12.500 | active clock edge time | ||||
12.500 | 0.000 | mcu_sysclk | ||||
12.500 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
12.743 | 0.243 | tNET | RR | 1 | R42C15[0][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/sel_wf_v_s0/CLK |
12.708 | -0.035 | tSu | 1 | R42C15[0][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/sel_wf_v_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 12.500 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 3.041, 27.093%; route: 7.951, 70.840%; tC2Q: 0.232, 2.067% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path10
Path Summary:
Slack | 1.241 |
Data Arrival Time | 11.468 |
Data Required Time | 12.708 |
From | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/u_excpt/micro_code_de_s0 |
To | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/v_flag_wf_s0 |
Launch Clk | mcu_sysclk:[R] |
Latch Clk | mcu_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | mcu_sysclk | ||||
0.000 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R74C10[2][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/u_excpt/micro_code_de_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 15 | R74C10[2][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/u_excpt/micro_code_de_s0/Q |
1.596 | 1.120 | tNET | FF | 1 | R63C7[0][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_fetch/n108_s3/I3 |
1.967 | 0.371 | tINS | FF | 6 | R63C7[0][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_fetch/n108_s3/F |
4.027 | 2.061 | tNET | FF | 1 | R26C13[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_ahb/biu_rdy_s3/I0 |
4.576 | 0.549 | tINS | FR | 1 | R26C13[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_ahb/biu_rdy_s3/F |
4.749 | 0.172 | tNET | RR | 1 | R26C14[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_ahb/biu_rdy_s1/I3 |
5.298 | 0.549 | tINS | RR | 1 | R26C14[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_ahb/biu_rdy_s1/F |
5.470 | 0.172 | tNET | RR | 1 | R25C14[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_ahb/biu_rdy_s0/I0 |
6.025 | 0.555 | tINS | RF | 195 | R25C14[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_ahb/biu_rdy_s0/F |
8.308 | 2.282 | tNET | FF | 1 | R72C9[2][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/write_flags_ex_Z_s/I0 |
8.863 | 0.555 | tINS | FF | 6 | R72C9[2][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/write_flags_ex_Z_s/F |
9.566 | 0.703 | tNET | FF | 1 | R65C11[0][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/update_v_ex_Z_s0/I3 |
10.028 | 0.462 | tINS | FR | 3 | R65C11[0][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/update_v_ex_Z_s0/F |
11.468 | 1.440 | tNET | RR | 1 | R42C15[1][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/v_flag_wf_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
12.500 | 12.500 | active clock edge time | ||||
12.500 | 0.000 | mcu_sysclk | ||||
12.500 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
12.743 | 0.243 | tNET | RR | 1 | R42C15[1][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/v_flag_wf_s0/CLK |
12.708 | -0.035 | tSu | 1 | R42C15[1][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/v_flag_wf_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 12.500 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 3.041, 27.093%; route: 7.951, 70.840%; tC2Q: 0.232, 2.067% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path11
Path Summary:
Slack | 1.355 |
Data Arrival Time | 8.854 |
Data Required Time | 10.208 |
From | U_IES_Top/IES_inst/u_fmmu_mem/ecat_addr_1d_3_s0 |
To | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[1].u_fmmu_reg/ecat_rdata_0_s0 |
Launch Clk | esc_sysclk:[R] |
Latch Clk | esc_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | esc_sysclk | ||||
0.000 | 0.000 | tCL | RR | 12119 | PLL_R[0] | u_Gowin_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R32C53[0][A] | U_IES_Top/IES_inst/u_fmmu_mem/ecat_addr_1d_3_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 32 | R32C53[0][A] | U_IES_Top/IES_inst/u_fmmu_mem/ecat_addr_1d_3_s0/Q |
2.592 | 2.116 | tNET | FF | 1 | R49C80[3][A] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[0].u_fmmu_reg/n398_s2/I3 |
3.147 | 0.555 | tINS | FF | 16 | R49C80[3][A] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[0].u_fmmu_reg/n398_s2/F |
3.867 | 0.721 | tNET | FF | 1 | R47C75[3][B] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[1].u_fmmu_reg/n901_s5/I1 |
4.422 | 0.555 | tINS | FF | 1 | R47C75[3][B] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[1].u_fmmu_reg/n901_s5/F |
5.471 | 1.048 | tNET | FF | 1 | R50C75[3][A] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[1].u_fmmu_reg/n901_s3/I0 |
5.924 | 0.453 | tINS | FF | 1 | R50C75[3][A] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[1].u_fmmu_reg/n901_s3/F |
6.337 | 0.413 | tNET | FF | 1 | R47C75[3][A] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[1].u_fmmu_reg/n901_s1/I0 |
6.854 | 0.517 | tINS | FF | 1 | R47C75[3][A] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[1].u_fmmu_reg/n901_s1/F |
7.510 | 0.656 | tNET | FF | 1 | R44C74[3][B] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[1].u_fmmu_reg/n901_s0/I0 |
8.065 | 0.555 | tINS | FF | 2 | R44C74[3][B] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[1].u_fmmu_reg/n901_s0/F |
8.854 | 0.789 | tNET | FF | 1 | R44C71[1][A] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[1].u_fmmu_reg/ecat_rdata_0_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | esc_sysclk | ||||
10.000 | 0.000 | tCL | RR | 12119 | PLL_R[0] | u_Gowin_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R44C71[1][A] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[1].u_fmmu_reg/ecat_rdata_0_s0/CLK |
10.208 | -0.035 | tSu | 1 | R44C71[1][A] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[1].u_fmmu_reg/ecat_rdata_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 2.635, 30.603%; route: 5.743, 66.702%; tC2Q: 0.232, 2.694% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path12
Path Summary:
Slack | 1.371 |
Data Arrival Time | 8.837 |
Data Required Time | 10.208 |
From | U_IES_Top/IES_inst/u_fmmu_mem/ecat_addr_1d_3_s0 |
To | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[1].u_fmmu_reg/pdi_rdata_0_s0 |
Launch Clk | esc_sysclk:[R] |
Latch Clk | esc_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | esc_sysclk | ||||
0.000 | 0.000 | tCL | RR | 12119 | PLL_R[0] | u_Gowin_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R32C53[0][A] | U_IES_Top/IES_inst/u_fmmu_mem/ecat_addr_1d_3_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 32 | R32C53[0][A] | U_IES_Top/IES_inst/u_fmmu_mem/ecat_addr_1d_3_s0/Q |
2.592 | 2.116 | tNET | FF | 1 | R49C80[3][A] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[0].u_fmmu_reg/n398_s2/I3 |
3.147 | 0.555 | tINS | FF | 16 | R49C80[3][A] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[0].u_fmmu_reg/n398_s2/F |
3.867 | 0.721 | tNET | FF | 1 | R47C75[3][B] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[1].u_fmmu_reg/n901_s5/I1 |
4.422 | 0.555 | tINS | FF | 1 | R47C75[3][B] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[1].u_fmmu_reg/n901_s5/F |
5.471 | 1.048 | tNET | FF | 1 | R50C75[3][A] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[1].u_fmmu_reg/n901_s3/I0 |
5.924 | 0.453 | tINS | FF | 1 | R50C75[3][A] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[1].u_fmmu_reg/n901_s3/F |
6.337 | 0.413 | tNET | FF | 1 | R47C75[3][A] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[1].u_fmmu_reg/n901_s1/I0 |
6.854 | 0.517 | tINS | FF | 1 | R47C75[3][A] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[1].u_fmmu_reg/n901_s1/F |
7.510 | 0.656 | tNET | FF | 1 | R44C74[3][B] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[1].u_fmmu_reg/n901_s0/I0 |
8.065 | 0.555 | tINS | FF | 2 | R44C74[3][B] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[1].u_fmmu_reg/n901_s0/F |
8.837 | 0.772 | tNET | FF | 1 | R44C72[1][A] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[1].u_fmmu_reg/pdi_rdata_0_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | esc_sysclk | ||||
10.000 | 0.000 | tCL | RR | 12119 | PLL_R[0] | u_Gowin_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R44C72[1][A] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[1].u_fmmu_reg/pdi_rdata_0_s0/CLK |
10.208 | -0.035 | tSu | 1 | R44C72[1][A] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[1].u_fmmu_reg/pdi_rdata_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 2.635, 30.661%; route: 5.727, 66.640%; tC2Q: 0.232, 2.700% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path13
Path Summary:
Slack | 1.465 |
Data Arrival Time | 8.709 |
Data Required Time | 10.173 |
From | u_button/out_s0 |
To | U_IES_Top/IES_inst/u_i2c/rx_shift_buf_4_s0 |
Launch Clk | clkin:[R] |
Latch Clk | esc_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clkin | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk25_ibuf/I |
0.683 | 0.683 | tINS | RR | 42 | IOT48[A] | clk25_ibuf/O |
0.926 | 0.243 | tNET | RR | 1 | R35C18[0][A] | u_button/out_s0/CLK |
1.158 | 0.232 | tC2Q | RF | 27 | R35C18[0][A] | u_button/out_s0/Q |
5.051 | 3.894 | tNET | FF | 1 | R8C32[0][B] | U_IES_Top/IES_inst/sys_rst_n_s0/I0 |
5.422 | 0.371 | tINS | FF | 9 | R8C32[0][B] | U_IES_Top/IES_inst/sys_rst_n_s0/F |
5.962 | 0.540 | tNET | FF | 1 | R9C36[0][B] | U_IES_Top/IES_inst/u_i2c/n1854_s1/I2 |
6.517 | 0.555 | tINS | FF | 8 | R9C36[0][B] | U_IES_Top/IES_inst/u_i2c/n1854_s1/F |
7.436 | 0.919 | tNET | FF | 1 | R12C33[1][A] | U_IES_Top/IES_inst/u_i2c/n1846_s2/I3 |
7.985 | 0.549 | tINS | FR | 1 | R12C33[1][A] | U_IES_Top/IES_inst/u_i2c/n1846_s2/F |
8.709 | 0.724 | tNET | RR | 1 | R12C33[1][B] | U_IES_Top/IES_inst/u_i2c/rx_shift_buf_4_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | esc_sysclk | ||||
10.000 | 0.000 | tCL | RR | 12119 | PLL_R[0] | u_Gowin_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R12C33[1][B] | U_IES_Top/IES_inst/u_i2c/rx_shift_buf_4_s0/CLK |
10.208 | -0.035 | tUnc | U_IES_Top/IES_inst/u_i2c/rx_shift_buf_4_s0 | |||
10.173 | -0.035 | tSu | 1 | R12C33[1][B] | U_IES_Top/IES_inst/u_i2c/rx_shift_buf_4_s0 |
Path Statistics:
Clock Skew | -0.683 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Arrival Data Path Delay | cell: 1.475, 18.952%; route: 6.076, 78.067%; tC2Q: 0.232, 2.981% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path14
Path Summary:
Slack | 1.469 |
Data Arrival Time | 11.240 |
Data Required Time | 12.709 |
From | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem3_mem3_0_1_s |
To | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0 |
Launch Clk | mcu_sysclk:[R] |
Latch Clk | mcu_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | mcu_sysclk | ||||
0.000 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | BSRAM_R10[1] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem3_mem3_0_1_s/CLK |
2.503 | 2.260 | tC2Q | RF | 2 | BSRAM_R10[1] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem3_mem3_0_1_s/DO[0] |
4.400 | 1.897 | tNET | FF | 1 | R46C9[3][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/mem_r_data_25_s9/I1 |
4.771 | 0.371 | tINS | FF | 1 | R46C9[3][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/mem_r_data_25_s9/F |
4.771 | 0.000 | tNET | FF | 1 | R46C9[3][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/mem_r_data_25_s5/I1 |
4.874 | 0.103 | tINS | FF | 4 | R46C9[3][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/mem_r_data_25_s5/O |
5.633 | 0.759 | tNET | FF | 1 | R46C15[3][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/mem_r_data_rot_1_s4/I0 |
6.095 | 0.462 | tINS | FR | 1 | R46C15[3][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/mem_r_data_rot_1_s4/F |
6.097 | 0.001 | tNET | RR | 1 | R46C15[3][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/mem_r_data_rot_1_s3/I3 |
6.550 | 0.453 | tINS | RF | 2 | R46C15[3][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/mem_r_data_rot_1_s3/F |
7.680 | 1.131 | tNET | FF | 1 | R51C13[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_rf1_mux/dp_ipsr_1_s1/I1 |
8.051 | 0.371 | tINS | FF | 1 | R51C13[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_rf1_mux/dp_ipsr_1_s1/F |
8.569 | 0.518 | tNET | FF | 1 | R57C13[2][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_rf1_mux/dp_ipsr_1_s/I3 |
8.940 | 0.371 | tINS | FF | 2 | R57C13[2][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_rf1_mux/dp_ipsr_1_s/F |
9.706 | 0.766 | tNET | FF | 1 | R58C7[3][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/rf_wdata_1_s0/I1 |
10.159 | 0.453 | tINS | FF | 2 | R58C7[3][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/rf_wdata_1_s0/F |
11.240 | 1.081 | tNET | FF | 1 | R59C9 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/DI[1] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
12.500 | 12.500 | active clock edge time | ||||
12.500 | 0.000 | mcu_sysclk | ||||
12.500 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
12.743 | 0.243 | tNET | RR | 1 | R59C9 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/CLK |
12.709 | -0.035 | tSu | 1 | R59C9 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 12.500 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 2.584, 23.498%; route: 6.153, 55.951%; tC2Q: 2.260, 20.551% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path15
Path Summary:
Slack | 1.474 |
Data Arrival Time | 11.234 |
Data Required Time | 12.708 |
From | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_1_s0 |
To | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/biu_commit_reg_s0 |
Launch Clk | mcu_sysclk:[R] |
Latch Clk | mcu_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | mcu_sysclk | ||||
0.000 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R66C9[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_1_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 8 | R66C9[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_1_s0/Q |
1.327 | 0.852 | tNET | FF | 4 | R58C10 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_1_s0/RAD[1] |
1.844 | 0.517 | tINS | FF | 8 | R58C10 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_1_s0/DO[0] |
3.278 | 1.433 | tNET | FF | 1 | R48C10[3][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_4_s2/I0 |
3.827 | 0.549 | tINS | FR | 1 | R48C10[3][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_4_s2/F |
3.828 | 0.001 | tNET | RR | 1 | R48C10[3][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_4_s1/I1 |
4.345 | 0.517 | tINS | RF | 1 | R48C10[3][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_4_s1/F |
4.758 | 0.413 | tNET | FF | 1 | R48C8[3][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_4_s0/I1 |
5.275 | 0.517 | tINS | FF | 2 | R48C8[3][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_4_s0/F |
6.040 | 0.765 | tNET | FF | 2 | R42C6[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/I1 |
6.411 | 0.371 | tINS | FF | 1 | R42C6[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/COUT |
6.411 | 0.000 | tNET | FF | 2 | R42C7[0][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/CIN |
6.446 | 0.035 | tINS | FF | 1 | R42C7[0][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/COUT |
6.446 | 0.000 | tNET | FF | 2 | R42C7[0][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/CIN |
6.482 | 0.035 | tINS | FF | 1 | R42C7[0][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/COUT |
6.482 | 0.000 | tNET | FF | 2 | R42C7[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/CIN |
6.517 | 0.035 | tINS | FF | 1 | R42C7[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/COUT |
6.517 | 0.000 | tNET | FF | 2 | R42C7[1][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/CIN |
6.552 | 0.035 | tINS | FF | 1 | R42C7[1][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/COUT |
6.552 | 0.000 | tNET | FF | 2 | R42C7[2][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/CIN |
6.587 | 0.035 | tINS | FF | 1 | R42C7[2][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/COUT |
6.587 | 0.000 | tNET | FF | 2 | R42C7[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/CIN |
6.622 | 0.035 | tINS | FF | 1 | R42C7[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/COUT |
6.622 | 0.000 | tNET | FF | 2 | R42C8[0][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/CIN |
6.658 | 0.035 | tINS | FF | 1 | R42C8[0][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/COUT |
6.658 | 0.000 | tNET | FF | 2 | R42C8[0][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/CIN |
6.693 | 0.035 | tINS | FF | 1 | R42C8[0][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/COUT |
6.693 | 0.000 | tNET | FF | 2 | R42C8[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/CIN |
6.728 | 0.035 | tINS | FF | 1 | R42C8[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/COUT |
6.728 | 0.000 | tNET | FF | 2 | R42C8[1][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/CIN |
6.763 | 0.035 | tINS | FF | 1 | R42C8[1][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/COUT |
6.763 | 0.000 | tNET | FF | 2 | R42C8[2][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/CIN |
6.798 | 0.035 | tINS | FF | 1 | R42C8[2][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/COUT |
6.798 | 0.000 | tNET | FF | 2 | R42C8[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/CIN |
6.834 | 0.035 | tINS | FF | 1 | R42C8[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/COUT |
6.834 | 0.000 | tNET | FF | 2 | R42C9[0][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/CIN |
6.869 | 0.035 | tINS | FF | 1 | R42C9[0][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/COUT |
6.869 | 0.000 | tNET | FF | 2 | R42C9[0][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/CIN |
6.904 | 0.035 | tINS | FF | 1 | R42C9[0][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/COUT |
6.904 | 0.000 | tNET | FF | 2 | R42C9[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_19_s/CIN |
7.374 | 0.470 | tINS | FF | 4 | R42C9[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_19_s/SUM |
8.585 | 1.211 | tNET | FF | 1 | R43C10[0][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s8/I0 |
9.047 | 0.462 | tINS | FR | 1 | R43C10[0][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s8/F |
9.049 | 0.001 | tNET | RR | 1 | R43C10[0][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s6/I2 |
9.619 | 0.570 | tINS | RR | 1 | R43C10[0][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s6/F |
9.620 | 0.001 | tNET | RR | 1 | R43C10[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s1/I2 |
9.991 | 0.371 | tINS | RF | 3 | R43C10[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s1/F |
10.397 | 0.406 | tNET | FF | 1 | R43C8[2][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/biu_commit_Z_s3/I1 |
10.768 | 0.371 | tINS | FF | 1 | R43C8[2][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/biu_commit_Z_s3/F |
10.772 | 0.004 | tNET | FF | 1 | R43C8[1][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/biu_commit_Z_s/I3 |
11.234 | 0.462 | tINS | FR | 1 | R43C8[1][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/biu_commit_Z_s/F |
11.234 | 0.000 | tNET | RR | 1 | R43C8[1][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/biu_commit_reg_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
12.500 | 12.500 | active clock edge time | ||||
12.500 | 0.000 | mcu_sysclk | ||||
12.500 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
12.743 | 0.243 | tNET | RR | 1 | R43C8[1][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/biu_commit_reg_s0/CLK |
12.708 | -0.035 | tSu | 1 | R43C8[1][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/biu_commit_reg_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 12.500 |
Logic Level | 13 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 5.670, 51.587%; route: 5.089, 46.302%; tC2Q: 0.232, 2.111% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path16
Path Summary:
Slack | 1.474 |
Data Arrival Time | 11.234 |
Data Required Time | 12.709 |
From | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_1_s0 |
To | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_5_s |
Launch Clk | mcu_sysclk:[R] |
Latch Clk | mcu_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | mcu_sysclk | ||||
0.000 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R66C9[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_1_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 8 | R66C9[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_1_s0/Q |
1.327 | 0.852 | tNET | FF | 4 | R58C10 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_1_s0/RAD[1] |
1.844 | 0.517 | tINS | FF | 8 | R58C10 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_1_s0/DO[0] |
3.278 | 1.433 | tNET | FF | 1 | R48C10[3][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_4_s2/I0 |
3.827 | 0.549 | tINS | FR | 1 | R48C10[3][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_4_s2/F |
3.828 | 0.001 | tNET | RR | 1 | R48C10[3][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_4_s1/I1 |
4.345 | 0.517 | tINS | RF | 1 | R48C10[3][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_4_s1/F |
4.758 | 0.413 | tNET | FF | 1 | R48C8[3][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_4_s0/I1 |
5.275 | 0.517 | tINS | FF | 2 | R48C8[3][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_4_s0/F |
6.040 | 0.765 | tNET | FF | 2 | R42C6[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/I1 |
6.411 | 0.371 | tINS | FF | 1 | R42C6[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/COUT |
6.411 | 0.000 | tNET | FF | 2 | R42C7[0][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/CIN |
6.446 | 0.035 | tINS | FF | 1 | R42C7[0][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/COUT |
6.446 | 0.000 | tNET | FF | 2 | R42C7[0][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/CIN |
6.482 | 0.035 | tINS | FF | 1 | R42C7[0][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/COUT |
6.482 | 0.000 | tNET | FF | 2 | R42C7[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/CIN |
6.517 | 0.035 | tINS | FF | 1 | R42C7[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/COUT |
6.517 | 0.000 | tNET | FF | 2 | R42C7[1][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/CIN |
6.552 | 0.035 | tINS | FF | 1 | R42C7[1][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/COUT |
6.552 | 0.000 | tNET | FF | 2 | R42C7[2][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/CIN |
6.587 | 0.035 | tINS | FF | 1 | R42C7[2][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/COUT |
6.587 | 0.000 | tNET | FF | 2 | R42C7[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/CIN |
6.622 | 0.035 | tINS | FF | 1 | R42C7[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/COUT |
6.622 | 0.000 | tNET | FF | 2 | R42C8[0][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/CIN |
6.658 | 0.035 | tINS | FF | 1 | R42C8[0][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/COUT |
6.658 | 0.000 | tNET | FF | 2 | R42C8[0][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/CIN |
6.693 | 0.035 | tINS | FF | 1 | R42C8[0][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/COUT |
6.693 | 0.000 | tNET | FF | 2 | R42C8[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/CIN |
6.728 | 0.035 | tINS | FF | 1 | R42C8[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/COUT |
6.728 | 0.000 | tNET | FF | 2 | R42C8[1][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/CIN |
6.763 | 0.035 | tINS | FF | 1 | R42C8[1][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/COUT |
6.763 | 0.000 | tNET | FF | 2 | R42C8[2][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/CIN |
6.798 | 0.035 | tINS | FF | 1 | R42C8[2][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/COUT |
6.798 | 0.000 | tNET | FF | 2 | R42C8[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/CIN |
6.834 | 0.035 | tINS | FF | 1 | R42C8[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/COUT |
6.834 | 0.000 | tNET | FF | 2 | R42C9[0][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/CIN |
6.869 | 0.035 | tINS | FF | 1 | R42C9[0][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/COUT |
6.869 | 0.000 | tNET | FF | 2 | R42C9[0][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/CIN |
6.904 | 0.035 | tINS | FF | 1 | R42C9[0][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/COUT |
6.904 | 0.000 | tNET | FF | 2 | R42C9[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_19_s/CIN |
6.939 | 0.035 | tINS | FF | 1 | R42C9[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_19_s/COUT |
6.939 | 0.000 | tNET | FF | 2 | R42C9[1][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_20_s/CIN |
7.409 | 0.470 | tINS | FF | 4 | R42C9[1][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_20_s/SUM |
9.207 | 1.798 | tNET | FF | 1 | R53C12[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_rf1_mux/rf1_mux_out_20_s1/I1 |
9.660 | 0.453 | tINS | FF | 1 | R53C12[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_rf1_mux/rf1_mux_out_20_s1/F |
10.057 | 0.397 | tNET | FF | 1 | R55C12[3][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_rf1_mux/rf1_mux_out_20_s/I2 |
10.574 | 0.517 | tINS | FF | 2 | R55C12[3][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_rf1_mux/rf1_mux_out_20_s/F |
11.234 | 0.660 | tNET | FF | 1 | R58C13 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_5_s/DI[0] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
12.500 | 12.500 | active clock edge time | ||||
12.500 | 0.000 | mcu_sysclk | ||||
12.500 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
12.743 | 0.243 | tNET | RR | 1 | R58C13 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_5_s/CLK |
12.709 | -0.035 | tSu | 1 | R58C13 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_5_s |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 12.500 |
Logic Level | 10 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 4.439, 40.388%; route: 6.320, 57.502%; tC2Q: 0.232, 2.111% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path17
Path Summary:
Slack | 1.479 |
Data Arrival Time | 11.230 |
Data Required Time | 12.709 |
From | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_1_s0 |
To | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem3_mem3_0_1_s |
Launch Clk | mcu_sysclk:[R] |
Latch Clk | mcu_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | mcu_sysclk | ||||
0.000 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R66C9[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_1_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 8 | R66C9[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_1_s0/Q |
1.327 | 0.852 | tNET | FF | 4 | R58C10 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_1_s0/RAD[1] |
1.844 | 0.517 | tINS | FF | 8 | R58C10 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_1_s0/DO[0] |
3.278 | 1.433 | tNET | FF | 1 | R48C10[3][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_4_s2/I0 |
3.827 | 0.549 | tINS | FR | 1 | R48C10[3][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_4_s2/F |
3.828 | 0.001 | tNET | RR | 1 | R48C10[3][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_4_s1/I1 |
4.345 | 0.517 | tINS | RF | 1 | R48C10[3][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_4_s1/F |
4.758 | 0.413 | tNET | FF | 1 | R48C8[3][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_4_s0/I1 |
5.275 | 0.517 | tINS | FF | 2 | R48C8[3][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_4_s0/F |
6.040 | 0.765 | tNET | FF | 2 | R42C6[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/I1 |
6.411 | 0.371 | tINS | FF | 1 | R42C6[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/COUT |
6.411 | 0.000 | tNET | FF | 2 | R42C7[0][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/CIN |
6.446 | 0.035 | tINS | FF | 1 | R42C7[0][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/COUT |
6.446 | 0.000 | tNET | FF | 2 | R42C7[0][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/CIN |
6.482 | 0.035 | tINS | FF | 1 | R42C7[0][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/COUT |
6.482 | 0.000 | tNET | FF | 2 | R42C7[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/CIN |
6.517 | 0.035 | tINS | FF | 1 | R42C7[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/COUT |
6.517 | 0.000 | tNET | FF | 2 | R42C7[1][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/CIN |
6.987 | 0.470 | tINS | FF | 4 | R42C7[1][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/SUM |
8.166 | 1.179 | tNET | FF | 1 | R51C13[3][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/DTCMADDR_Z_8_s/I1 |
8.721 | 0.555 | tINS | FF | 66 | R51C13[3][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/DTCMADDR_Z_8_s/F |
11.230 | 2.509 | tNET | FF | 1 | BSRAM_R10[1] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem3_mem3_0_1_s/AD[6] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
12.500 | 12.500 | active clock edge time | ||||
12.500 | 0.000 | mcu_sysclk | ||||
12.500 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
12.743 | 0.243 | tNET | RR | 1 | BSRAM_R10[1] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem3_mem3_0_1_s/CLK |
12.709 | -0.035 | tSu | 1 | BSRAM_R10[1] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem3_mem3_0_1_s |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 12.500 |
Logic Level | 8 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 3.602, 32.782%; route: 7.153, 65.106%; tC2Q: 0.232, 2.112% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path18
Path Summary:
Slack | 1.518 |
Data Arrival Time | 8.690 |
Data Required Time | 10.208 |
From | U_IES_Top/IES_inst/u_fmmu_mem/ecat_addr_1d_1_s0 |
To | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[3].u_fmmu_reg/pdi_rdata_5_s0 |
Launch Clk | esc_sysclk:[R] |
Latch Clk | esc_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | esc_sysclk | ||||
0.000 | 0.000 | tCL | RR | 12119 | PLL_R[0] | u_Gowin_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R32C53[1][A] | U_IES_Top/IES_inst/u_fmmu_mem/ecat_addr_1d_1_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 31 | R32C53[1][A] | U_IES_Top/IES_inst/u_fmmu_mem/ecat_addr_1d_1_s0/Q |
2.366 | 1.891 | tNET | FF | 1 | R49C75[2][B] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[0].u_fmmu_reg/n149_s10/I0 |
2.921 | 0.555 | tINS | FF | 49 | R49C75[2][B] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[0].u_fmmu_reg/n149_s10/F |
5.785 | 2.864 | tNET | FF | 1 | R43C68[3][B] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[3].u_fmmu_reg/n896_s5/I0 |
6.156 | 0.371 | tINS | FF | 1 | R43C68[3][B] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[3].u_fmmu_reg/n896_s5/F |
6.570 | 0.413 | tNET | FF | 1 | R43C65[2][B] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[3].u_fmmu_reg/n896_s3/I0 |
7.140 | 0.570 | tINS | FR | 1 | R43C65[2][B] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[3].u_fmmu_reg/n896_s3/F |
7.141 | 0.001 | tNET | RR | 1 | R43C65[3][A] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[3].u_fmmu_reg/n896_s1/I1 |
7.690 | 0.549 | tINS | RR | 1 | R43C65[3][A] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[3].u_fmmu_reg/n896_s1/F |
7.691 | 0.001 | tNET | RR | 1 | R43C65[1][B] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[3].u_fmmu_reg/n896_s0/I0 |
8.144 | 0.453 | tINS | RF | 2 | R43C65[1][B] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[3].u_fmmu_reg/n896_s0/F |
8.690 | 0.546 | tNET | FF | 1 | R43C64[0][A] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[3].u_fmmu_reg/pdi_rdata_5_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | esc_sysclk | ||||
10.000 | 0.000 | tCL | RR | 12119 | PLL_R[0] | u_Gowin_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R43C64[0][A] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[3].u_fmmu_reg/pdi_rdata_5_s0/CLK |
10.208 | -0.035 | tSu | 1 | R43C64[0][A] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[3].u_fmmu_reg/pdi_rdata_5_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 2.498, 29.574%; route: 5.717, 67.680%; tC2Q: 0.232, 2.747% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path19
Path Summary:
Slack | 1.522 |
Data Arrival Time | 11.187 |
Data Required Time | 12.708 |
From | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_1_s0 |
To | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/n_flag_s0 |
Launch Clk | mcu_sysclk:[R] |
Latch Clk | mcu_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | mcu_sysclk | ||||
0.000 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R66C9[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_1_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 8 | R66C9[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_1_s0/Q |
1.327 | 0.852 | tNET | FF | 4 | R58C10 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_1_s0/RAD[1] |
1.844 | 0.517 | tINS | FF | 8 | R58C10 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_1_s0/DO[0] |
3.278 | 1.433 | tNET | FF | 1 | R48C10[3][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_4_s2/I0 |
3.827 | 0.549 | tINS | FR | 1 | R48C10[3][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_4_s2/F |
3.828 | 0.001 | tNET | RR | 1 | R48C10[3][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_4_s1/I1 |
4.345 | 0.517 | tINS | RF | 1 | R48C10[3][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_4_s1/F |
4.758 | 0.413 | tNET | FF | 1 | R48C8[3][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_4_s0/I1 |
5.275 | 0.517 | tINS | FF | 2 | R48C8[3][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_4_s0/F |
6.040 | 0.765 | tNET | FF | 2 | R42C6[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/I1 |
6.411 | 0.371 | tINS | FF | 1 | R42C6[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/COUT |
6.411 | 0.000 | tNET | FF | 2 | R42C7[0][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/CIN |
6.446 | 0.035 | tINS | FF | 1 | R42C7[0][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/COUT |
6.446 | 0.000 | tNET | FF | 2 | R42C7[0][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/CIN |
6.482 | 0.035 | tINS | FF | 1 | R42C7[0][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/COUT |
6.482 | 0.000 | tNET | FF | 2 | R42C7[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/CIN |
6.517 | 0.035 | tINS | FF | 1 | R42C7[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/COUT |
6.517 | 0.000 | tNET | FF | 2 | R42C7[1][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/CIN |
6.552 | 0.035 | tINS | FF | 1 | R42C7[1][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/COUT |
6.552 | 0.000 | tNET | FF | 2 | R42C7[2][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/CIN |
6.587 | 0.035 | tINS | FF | 1 | R42C7[2][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/COUT |
6.587 | 0.000 | tNET | FF | 2 | R42C7[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/CIN |
6.622 | 0.035 | tINS | FF | 1 | R42C7[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/COUT |
6.622 | 0.000 | tNET | FF | 2 | R42C8[0][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/CIN |
6.658 | 0.035 | tINS | FF | 1 | R42C8[0][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/COUT |
6.658 | 0.000 | tNET | FF | 2 | R42C8[0][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/CIN |
6.693 | 0.035 | tINS | FF | 1 | R42C8[0][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/COUT |
6.693 | 0.000 | tNET | FF | 2 | R42C8[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/CIN |
6.728 | 0.035 | tINS | FF | 1 | R42C8[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/COUT |
6.728 | 0.000 | tNET | FF | 2 | R42C8[1][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/CIN |
6.763 | 0.035 | tINS | FF | 1 | R42C8[1][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/COUT |
6.763 | 0.000 | tNET | FF | 2 | R42C8[2][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/CIN |
6.798 | 0.035 | tINS | FF | 1 | R42C8[2][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/COUT |
6.798 | 0.000 | tNET | FF | 2 | R42C8[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/CIN |
6.834 | 0.035 | tINS | FF | 1 | R42C8[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/COUT |
6.834 | 0.000 | tNET | FF | 2 | R42C9[0][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/CIN |
6.869 | 0.035 | tINS | FF | 1 | R42C9[0][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/COUT |
6.869 | 0.000 | tNET | FF | 2 | R42C9[0][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/CIN |
6.904 | 0.035 | tINS | FF | 1 | R42C9[0][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/COUT |
6.904 | 0.000 | tNET | FF | 2 | R42C9[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_19_s/CIN |
6.939 | 0.035 | tINS | FF | 1 | R42C9[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_19_s/COUT |
6.939 | 0.000 | tNET | FF | 2 | R42C9[1][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_20_s/CIN |
6.974 | 0.035 | tINS | FF | 1 | R42C9[1][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_20_s/COUT |
6.974 | 0.000 | tNET | FF | 2 | R42C9[2][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_21_s/CIN |
7.010 | 0.035 | tINS | FF | 1 | R42C9[2][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_21_s/COUT |
7.010 | 0.000 | tNET | FF | 2 | R42C9[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_22_s/CIN |
7.045 | 0.035 | tINS | FF | 1 | R42C9[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_22_s/COUT |
7.045 | 0.000 | tNET | FF | 2 | R42C10[0][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_23_s/CIN |
7.080 | 0.035 | tINS | FF | 1 | R42C10[0][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_23_s/COUT |
7.080 | 0.000 | tNET | FF | 2 | R42C10[0][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_24_s/CIN |
7.115 | 0.035 | tINS | FF | 1 | R42C10[0][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_24_s/COUT |
7.115 | 0.000 | tNET | FF | 2 | R42C10[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_25_s/CIN |
7.150 | 0.035 | tINS | FF | 1 | R42C10[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_25_s/COUT |
7.150 | 0.000 | tNET | FF | 2 | R42C10[1][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_26_s/CIN |
7.186 | 0.035 | tINS | FF | 1 | R42C10[1][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_26_s/COUT |
7.186 | 0.000 | tNET | FF | 2 | R42C10[2][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_27_s/CIN |
7.221 | 0.035 | tINS | FF | 1 | R42C10[2][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_27_s/COUT |
7.221 | 0.000 | tNET | FF | 2 | R42C10[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_28_s/CIN |
7.256 | 0.035 | tINS | FF | 1 | R42C10[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_28_s/COUT |
7.256 | 0.000 | tNET | FF | 2 | R42C11[0][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_29_s/CIN |
7.291 | 0.035 | tINS | FF | 1 | R42C11[0][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_29_s/COUT |
7.291 | 0.000 | tNET | FF | 2 | R42C11[0][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_30_s/CIN |
7.326 | 0.035 | tINS | FF | 1 | R42C11[0][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_30_s/COUT |
7.326 | 0.000 | tNET | FF | 2 | R42C11[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_31_s/CIN |
7.796 | 0.470 | tINS | FF | 6 | R42C11[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_31_s/SUM |
9.255 | 1.458 | tNET | FF | 1 | R55C13[0][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_rf1_mux/rf1_mux_out_31_s1/I1 |
9.626 | 0.371 | tINS | FF | 1 | R55C13[0][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_rf1_mux/rf1_mux_out_31_s1/F |
9.796 | 0.170 | tNET | FF | 1 | R56C13[0][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_rf1_mux/rf1_mux_out_31_s/I3 |
10.167 | 0.371 | tINS | FF | 3 | R56C13[0][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_rf1_mux/rf1_mux_out_31_s/F |
11.187 | 1.019 | tNET | FF | 1 | R56C9[2][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/n_flag_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
12.500 | 12.500 | active clock edge time | ||||
12.500 | 0.000 | mcu_sysclk | ||||
12.500 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
12.743 | 0.243 | tNET | RR | 1 | R56C9[2][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/n_flag_s0/CLK |
12.708 | -0.035 | tSu | 1 | R56C9[2][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/n_flag_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 12.500 |
Logic Level | 12 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 4.598, 42.019%; route: 6.113, 55.861%; tC2Q: 0.232, 2.120% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path20
Path Summary:
Slack | 1.524 |
Data Arrival Time | 11.184 |
Data Required Time | 12.708 |
From | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/u_excpt/micro_code_de_s0 |
To | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/v_flag_au_s0 |
Launch Clk | mcu_sysclk:[R] |
Latch Clk | mcu_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | mcu_sysclk | ||||
0.000 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R74C10[2][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/u_excpt/micro_code_de_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 15 | R74C10[2][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/u_excpt/micro_code_de_s0/Q |
1.596 | 1.120 | tNET | FF | 1 | R63C7[0][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_fetch/n108_s3/I3 |
1.967 | 0.371 | tINS | FF | 6 | R63C7[0][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_fetch/n108_s3/F |
4.027 | 2.061 | tNET | FF | 1 | R26C13[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_ahb/biu_rdy_s3/I0 |
4.576 | 0.549 | tINS | FR | 1 | R26C13[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_ahb/biu_rdy_s3/F |
4.749 | 0.172 | tNET | RR | 1 | R26C14[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_ahb/biu_rdy_s1/I3 |
5.298 | 0.549 | tINS | RR | 1 | R26C14[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_ahb/biu_rdy_s1/F |
5.470 | 0.172 | tNET | RR | 1 | R25C14[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_ahb/biu_rdy_s0/I0 |
6.025 | 0.555 | tINS | RF | 195 | R25C14[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_ahb/biu_rdy_s0/F |
8.308 | 2.282 | tNET | FF | 1 | R72C9[2][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/write_flags_ex_Z_s/I0 |
8.863 | 0.555 | tINS | FF | 6 | R72C9[2][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/write_flags_ex_Z_s/F |
9.566 | 0.703 | tNET | FF | 1 | R65C11[0][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/update_v_ex_Z_s0/I3 |
10.028 | 0.462 | tINS | FR | 3 | R65C11[0][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/update_v_ex_Z_s0/F |
11.184 | 1.156 | tNET | RR | 1 | R43C12[2][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/v_flag_au_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
12.500 | 12.500 | active clock edge time | ||||
12.500 | 0.000 | mcu_sysclk | ||||
12.500 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
12.743 | 0.243 | tNET | RR | 1 | R43C12[2][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/v_flag_au_s0/CLK |
12.708 | -0.035 | tSu | 1 | R43C12[2][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/v_flag_au_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 12.500 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 3.041, 27.795%; route: 7.668, 70.085%; tC2Q: 0.232, 2.120% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path21
Path Summary:
Slack | 1.534 |
Data Arrival Time | 11.174 |
Data Required Time | 12.708 |
From | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_1_s0 |
To | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/u_excpt/dp_ipsr_7to2_6_s0 |
Launch Clk | mcu_sysclk:[R] |
Latch Clk | mcu_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | mcu_sysclk | ||||
0.000 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R66C9[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_1_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 8 | R66C9[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_1_s0/Q |
1.327 | 0.852 | tNET | FF | 4 | R58C10 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_1_s0/RAD[1] |
1.844 | 0.517 | tINS | FF | 8 | R58C10 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_1_s0/DO[0] |
3.278 | 1.433 | tNET | FF | 1 | R48C10[3][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_4_s2/I0 |
3.827 | 0.549 | tINS | FR | 1 | R48C10[3][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_4_s2/F |
3.828 | 0.001 | tNET | RR | 1 | R48C10[3][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_4_s1/I1 |
4.345 | 0.517 | tINS | RF | 1 | R48C10[3][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_4_s1/F |
4.758 | 0.413 | tNET | FF | 1 | R48C8[3][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_4_s0/I1 |
5.275 | 0.517 | tINS | FF | 2 | R48C8[3][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_4_s0/F |
6.040 | 0.765 | tNET | FF | 2 | R42C6[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/I1 |
6.411 | 0.371 | tINS | FF | 1 | R42C6[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/COUT |
6.411 | 0.000 | tNET | FF | 2 | R42C7[0][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/CIN |
6.446 | 0.035 | tINS | FF | 1 | R42C7[0][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/COUT |
6.446 | 0.000 | tNET | FF | 2 | R42C7[0][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/CIN |
6.916 | 0.470 | tINS | FF | 4 | R42C7[0][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/SUM |
8.233 | 1.316 | tNET | FF | 1 | R52C10[1][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_rf1_mux/dp_ipsr_6_s1/I1 |
8.803 | 0.570 | tINS | FR | 1 | R52C10[1][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_rf1_mux/dp_ipsr_6_s1/F |
8.975 | 0.172 | tNET | RR | 1 | R53C10[3][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_rf1_mux/dp_ipsr_6_s/I3 |
9.346 | 0.371 | tINS | RF | 3 | R53C10[3][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_rf1_mux/dp_ipsr_6_s/F |
11.174 | 1.828 | tNET | FF | 1 | R73C6[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/u_excpt/dp_ipsr_7to2_6_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
12.500 | 12.500 | active clock edge time | ||||
12.500 | 0.000 | mcu_sysclk | ||||
12.500 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
12.743 | 0.243 | tNET | RR | 1 | R73C6[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/u_excpt/dp_ipsr_7to2_6_s0/CLK |
12.708 | -0.035 | tSu | 1 | R73C6[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/u_excpt/dp_ipsr_7to2_6_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 12.500 |
Logic Level | 9 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 3.917, 35.837%; route: 6.781, 62.040%; tC2Q: 0.232, 2.122% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path22
Path Summary:
Slack | 1.540 |
Data Arrival Time | 8.668 |
Data Required Time | 10.208 |
From | U_IES_Top/IES_inst/u_fmmu_mem/ecat_addr_1d_1_s0 |
To | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[3].u_fmmu_reg/pdi_rdata_6_s0 |
Launch Clk | esc_sysclk:[R] |
Latch Clk | esc_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | esc_sysclk | ||||
0.000 | 0.000 | tCL | RR | 12119 | PLL_R[0] | u_Gowin_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R32C53[1][A] | U_IES_Top/IES_inst/u_fmmu_mem/ecat_addr_1d_1_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 31 | R32C53[1][A] | U_IES_Top/IES_inst/u_fmmu_mem/ecat_addr_1d_1_s0/Q |
2.366 | 1.891 | tNET | FF | 1 | R49C75[2][B] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[0].u_fmmu_reg/n149_s10/I0 |
2.921 | 0.555 | tINS | FF | 49 | R49C75[2][B] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[0].u_fmmu_reg/n149_s10/F |
5.780 | 2.858 | tNET | FF | 1 | R44C67[0][A] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[3].u_fmmu_reg/n895_s5/I0 |
6.151 | 0.371 | tINS | FF | 1 | R44C67[0][A] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[3].u_fmmu_reg/n895_s5/F |
6.321 | 0.170 | tNET | FF | 1 | R44C66[3][B] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[3].u_fmmu_reg/n895_s2/I0 |
6.870 | 0.549 | tINS | FR | 1 | R44C66[3][B] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[3].u_fmmu_reg/n895_s2/F |
7.043 | 0.172 | tNET | RR | 1 | R44C65[1][B] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[3].u_fmmu_reg/n895_s1/I0 |
7.592 | 0.549 | tINS | RR | 1 | R44C65[1][B] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[3].u_fmmu_reg/n895_s1/F |
7.764 | 0.172 | tNET | RR | 1 | R44C64[3][B] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[3].u_fmmu_reg/n895_s0/I0 |
8.135 | 0.371 | tINS | RF | 2 | R44C64[3][B] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[3].u_fmmu_reg/n895_s0/F |
8.668 | 0.533 | tNET | FF | 1 | R44C64[0][A] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[3].u_fmmu_reg/pdi_rdata_6_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | esc_sysclk | ||||
10.000 | 0.000 | tCL | RR | 12119 | PLL_R[0] | u_Gowin_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R44C64[0][A] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[3].u_fmmu_reg/pdi_rdata_6_s0/CLK |
10.208 | -0.035 | tSu | 1 | R44C64[0][A] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[3].u_fmmu_reg/pdi_rdata_6_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 2.395, 28.428%; route: 5.798, 68.819%; tC2Q: 0.232, 2.754% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path23
Path Summary:
Slack | 1.540 |
Data Arrival Time | 8.668 |
Data Required Time | 10.208 |
From | U_IES_Top/IES_inst/u_fmmu_mem/ecat_addr_1d_1_s0 |
To | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[3].u_fmmu_reg/ecat_rdata_6_s0 |
Launch Clk | esc_sysclk:[R] |
Latch Clk | esc_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | esc_sysclk | ||||
0.000 | 0.000 | tCL | RR | 12119 | PLL_R[0] | u_Gowin_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R32C53[1][A] | U_IES_Top/IES_inst/u_fmmu_mem/ecat_addr_1d_1_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 31 | R32C53[1][A] | U_IES_Top/IES_inst/u_fmmu_mem/ecat_addr_1d_1_s0/Q |
2.366 | 1.891 | tNET | FF | 1 | R49C75[2][B] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[0].u_fmmu_reg/n149_s10/I0 |
2.921 | 0.555 | tINS | FF | 49 | R49C75[2][B] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[0].u_fmmu_reg/n149_s10/F |
5.780 | 2.858 | tNET | FF | 1 | R44C67[0][A] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[3].u_fmmu_reg/n895_s5/I0 |
6.151 | 0.371 | tINS | FF | 1 | R44C67[0][A] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[3].u_fmmu_reg/n895_s5/F |
6.321 | 0.170 | tNET | FF | 1 | R44C66[3][B] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[3].u_fmmu_reg/n895_s2/I0 |
6.870 | 0.549 | tINS | FR | 1 | R44C66[3][B] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[3].u_fmmu_reg/n895_s2/F |
7.043 | 0.172 | tNET | RR | 1 | R44C65[1][B] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[3].u_fmmu_reg/n895_s1/I0 |
7.592 | 0.549 | tINS | RR | 1 | R44C65[1][B] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[3].u_fmmu_reg/n895_s1/F |
7.764 | 0.172 | tNET | RR | 1 | R44C64[3][B] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[3].u_fmmu_reg/n895_s0/I0 |
8.135 | 0.371 | tINS | RF | 2 | R44C64[3][B] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[3].u_fmmu_reg/n895_s0/F |
8.668 | 0.533 | tNET | FF | 1 | R44C64[1][A] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[3].u_fmmu_reg/ecat_rdata_6_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | esc_sysclk | ||||
10.000 | 0.000 | tCL | RR | 12119 | PLL_R[0] | u_Gowin_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R44C64[1][A] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[3].u_fmmu_reg/ecat_rdata_6_s0/CLK |
10.208 | -0.035 | tSu | 1 | R44C64[1][A] | U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[3].u_fmmu_reg/ecat_rdata_6_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 2.395, 28.428%; route: 5.798, 68.819%; tC2Q: 0.232, 2.754% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path24
Path Summary:
Slack | 1.544 |
Data Arrival Time | 11.164 |
Data Required Time | 12.708 |
From | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_1_s0 |
To | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/u_excpt/dp_ipsr_7to2_5_s0 |
Launch Clk | mcu_sysclk:[R] |
Latch Clk | mcu_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | mcu_sysclk | ||||
0.000 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R66C9[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_1_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 8 | R66C9[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_1_s0/Q |
1.327 | 0.852 | tNET | FF | 4 | R58C10 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_1_s0/RAD[1] |
1.844 | 0.517 | tINS | FF | 8 | R58C10 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_1_s0/DO[0] |
3.278 | 1.433 | tNET | FF | 1 | R48C10[3][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_4_s2/I0 |
3.827 | 0.549 | tINS | FR | 1 | R48C10[3][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_4_s2/F |
3.828 | 0.001 | tNET | RR | 1 | R48C10[3][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_4_s1/I1 |
4.345 | 0.517 | tINS | RF | 1 | R48C10[3][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_4_s1/F |
4.758 | 0.413 | tNET | FF | 1 | R48C8[3][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_4_s0/I1 |
5.275 | 0.517 | tINS | FF | 2 | R48C8[3][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_4_s0/F |
6.040 | 0.765 | tNET | FF | 2 | R42C6[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/I1 |
6.411 | 0.371 | tINS | FF | 1 | R42C6[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/COUT |
6.411 | 0.000 | tNET | FF | 2 | R42C7[0][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/CIN |
6.881 | 0.470 | tINS | FF | 4 | R42C7[0][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/SUM |
7.845 | 0.964 | tNET | FF | 1 | R51C11[3][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_rf1_mux/dp_ipsr_5_s1/I0 |
8.415 | 0.570 | tINS | FR | 1 | R51C11[3][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_rf1_mux/dp_ipsr_5_s1/F |
8.587 | 0.172 | tNET | RR | 1 | R52C11[0][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_rf1_mux/dp_ipsr_5_s/I3 |
9.142 | 0.555 | tINS | RF | 3 | R52C11[0][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_rf1_mux/dp_ipsr_5_s/F |
11.164 | 2.022 | tNET | FF | 1 | R73C8[0][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/u_excpt/dp_ipsr_7to2_5_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
12.500 | 12.500 | active clock edge time | ||||
12.500 | 0.000 | mcu_sysclk | ||||
12.500 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
12.743 | 0.243 | tNET | RR | 1 | R73C8[0][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/u_excpt/dp_ipsr_7to2_5_s0/CLK |
12.708 | -0.035 | tSu | 1 | R73C8[0][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/u_excpt/dp_ipsr_7to2_5_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 12.500 |
Logic Level | 9 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 4.066, 37.231%; route: 6.623, 60.645%; tC2Q: 0.232, 2.124% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path25
Path Summary:
Slack | 1.549 |
Data Arrival Time | 11.160 |
Data Required Time | 12.709 |
From | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_1_s0 |
To | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem3_mem3_0_2_s |
Launch Clk | mcu_sysclk:[R] |
Latch Clk | mcu_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | mcu_sysclk | ||||
0.000 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R66C9[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_1_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 8 | R66C9[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_1_s0/Q |
1.327 | 0.852 | tNET | FF | 4 | R58C10 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_1_s0/RAD[1] |
1.844 | 0.517 | tINS | FF | 8 | R58C10 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_1_s0/DO[0] |
3.278 | 1.433 | tNET | FF | 1 | R48C10[3][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_4_s2/I0 |
3.827 | 0.549 | tINS | FR | 1 | R48C10[3][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_4_s2/F |
3.828 | 0.001 | tNET | RR | 1 | R48C10[3][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_4_s1/I1 |
4.345 | 0.517 | tINS | RF | 1 | R48C10[3][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_4_s1/F |
4.758 | 0.413 | tNET | FF | 1 | R48C8[3][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_4_s0/I1 |
5.275 | 0.517 | tINS | FF | 2 | R48C8[3][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_4_s0/F |
6.040 | 0.765 | tNET | FF | 2 | R42C6[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/I1 |
6.411 | 0.371 | tINS | FF | 1 | R42C6[2][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/COUT |
6.411 | 0.000 | tNET | FF | 2 | R42C7[0][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/CIN |
6.446 | 0.035 | tINS | FF | 1 | R42C7[0][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/COUT |
6.446 | 0.000 | tNET | FF | 2 | R42C7[0][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/CIN |
6.482 | 0.035 | tINS | FF | 1 | R42C7[0][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/COUT |
6.482 | 0.000 | tNET | FF | 2 | R42C7[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/CIN |
6.517 | 0.035 | tINS | FF | 1 | R42C7[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/COUT |
6.517 | 0.000 | tNET | FF | 2 | R42C7[1][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/CIN |
6.987 | 0.470 | tINS | FF | 4 | R42C7[1][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/SUM |
8.166 | 1.179 | tNET | FF | 1 | R51C13[3][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/DTCMADDR_Z_8_s/I1 |
8.721 | 0.555 | tINS | FF | 66 | R51C13[3][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/DTCMADDR_Z_8_s/F |
11.160 | 2.439 | tNET | FF | 1 | BSRAM_R10[2] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem3_mem3_0_2_s/AD[6] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
12.500 | 12.500 | active clock edge time | ||||
12.500 | 0.000 | mcu_sysclk | ||||
12.500 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
12.743 | 0.243 | tNET | RR | 1 | BSRAM_R10[2] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem3_mem3_0_2_s/CLK |
12.709 | -0.035 | tSu | 1 | BSRAM_R10[2] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem3_mem3_0_2_s |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 12.500 |
Logic Level | 8 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 3.602, 32.993%; route: 7.083, 64.882%; tC2Q: 0.232, 2.125% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Hold Analysis Report
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 0.311 |
Data Arrival Time | 0.507 |
Data Required Time | 0.196 |
From | U_IES_Top/IES_inst/u_phy_manager/rx_shift_buf_15_s0 |
To | U_IES_Top/IES_inst/u_phy_manager/phy_rdata_0_s8 |
Launch Clk | esc_sysclk:[R] |
Latch Clk | esc_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | esc_sysclk | ||||
0.000 | 0.000 | tCL | RR | 12119 | PLL_R[0] | u_Gowin_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R25C33[0][A] | U_IES_Top/IES_inst/u_phy_manager/rx_shift_buf_15_s0/CLK |
0.385 | 0.201 | tC2Q | RF | 1 | R25C33[0][A] | U_IES_Top/IES_inst/u_phy_manager/rx_shift_buf_15_s0/Q |
0.507 | 0.122 | tNET | FF | 1 | R24C33 | U_IES_Top/IES_inst/u_phy_manager/phy_rdata_0_s8/DI[3] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | esc_sysclk | ||||
0.000 | 0.000 | tCL | RR | 12119 | PLL_R[0] | u_Gowin_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R24C33 | U_IES_Top/IES_inst/u_phy_manager/phy_rdata_0_s8/CLK |
0.196 | 0.012 | tHld | 1 | R24C33 | U_IES_Top/IES_inst/u_phy_manager/phy_rdata_0_s8 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.122, 37.751%; tC2Q: 0.201, 62.249% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path2
Path Summary:
Slack | 0.311 |
Data Arrival Time | 0.507 |
Data Required Time | 0.196 |
From | U_IES_Top/IES_inst/u_phy_manager/rx_shift_buf_10_s0 |
To | U_IES_Top/IES_inst/u_phy_manager/phy_rdata_0_s6 |
Launch Clk | esc_sysclk:[R] |
Latch Clk | esc_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | esc_sysclk | ||||
0.000 | 0.000 | tCL | RR | 12119 | PLL_R[0] | u_Gowin_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R25C32[1][B] | U_IES_Top/IES_inst/u_phy_manager/rx_shift_buf_10_s0/CLK |
0.385 | 0.201 | tC2Q | RF | 2 | R25C32[1][B] | U_IES_Top/IES_inst/u_phy_manager/rx_shift_buf_10_s0/Q |
0.507 | 0.122 | tNET | FF | 1 | R24C32 | U_IES_Top/IES_inst/u_phy_manager/phy_rdata_0_s6/DI[2] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | esc_sysclk | ||||
0.000 | 0.000 | tCL | RR | 12119 | PLL_R[0] | u_Gowin_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R24C32 | U_IES_Top/IES_inst/u_phy_manager/phy_rdata_0_s6/CLK |
0.196 | 0.012 | tHld | 1 | R24C32 | U_IES_Top/IES_inst/u_phy_manager/phy_rdata_0_s6 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.122, 37.751%; tC2Q: 0.201, 62.249% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path3
Path Summary:
Slack | 0.313 |
Data Arrival Time | 0.509 |
Data Required Time | 0.196 |
From | U_IES_Top/IES_inst/u_pdi_sm/status_reg_6_s0 |
To | U_IES_Top/IES_inst/u_pdi_sm/sm_status_reg_pdi_0_s4 |
Launch Clk | esc_sysclk:[R] |
Latch Clk | esc_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | esc_sysclk | ||||
0.000 | 0.000 | tCL | RR | 12119 | PLL_R[0] | u_Gowin_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R38C29[1][A] | U_IES_Top/IES_inst/u_pdi_sm/status_reg_6_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 1 | R38C29[1][A] | U_IES_Top/IES_inst/u_pdi_sm/status_reg_6_s0/Q |
0.509 | 0.123 | tNET | RR | 1 | R40C29 | U_IES_Top/IES_inst/u_pdi_sm/sm_status_reg_pdi_0_s4/DI[2] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | esc_sysclk | ||||
0.000 | 0.000 | tCL | RR | 12119 | PLL_R[0] | u_Gowin_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R40C29 | U_IES_Top/IES_inst/u_pdi_sm/sm_status_reg_pdi_0_s4/CLK |
0.196 | 0.012 | tHld | 1 | R40C29 | U_IES_Top/IES_inst/u_pdi_sm/sm_status_reg_pdi_0_s4 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.123, 37.889%; tC2Q: 0.202, 62.111% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path4
Path Summary:
Slack | 0.314 |
Data Arrival Time | 0.510 |
Data Required Time | 0.196 |
From | U_IES_Top/IES_inst/u_phy_manager/rx_shift_buf_14_s0 |
To | U_IES_Top/IES_inst/u_phy_manager/phy_rdata_0_s8 |
Launch Clk | esc_sysclk:[R] |
Latch Clk | esc_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | esc_sysclk | ||||
0.000 | 0.000 | tCL | RR | 12119 | PLL_R[0] | u_Gowin_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R25C33[0][B] | U_IES_Top/IES_inst/u_phy_manager/rx_shift_buf_14_s0/CLK |
0.385 | 0.201 | tC2Q | RF | 2 | R25C33[0][B] | U_IES_Top/IES_inst/u_phy_manager/rx_shift_buf_14_s0/Q |
0.510 | 0.125 | tNET | FF | 1 | R24C33 | U_IES_Top/IES_inst/u_phy_manager/phy_rdata_0_s8/DI[2] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | esc_sysclk | ||||
0.000 | 0.000 | tCL | RR | 12119 | PLL_R[0] | u_Gowin_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R24C33 | U_IES_Top/IES_inst/u_phy_manager/phy_rdata_0_s8/CLK |
0.196 | 0.012 | tHld | 1 | R24C33 | U_IES_Top/IES_inst/u_phy_manager/phy_rdata_0_s8 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.125, 38.377%; tC2Q: 0.201, 61.623% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path5
Path Summary:
Slack | 0.314 |
Data Arrival Time | 0.510 |
Data Required Time | 0.196 |
From | U_IES_Top/IES_inst/u_phy_manager/rx_shift_buf_13_s0 |
To | U_IES_Top/IES_inst/u_phy_manager/phy_rdata_0_s8 |
Launch Clk | esc_sysclk:[R] |
Latch Clk | esc_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | esc_sysclk | ||||
0.000 | 0.000 | tCL | RR | 12119 | PLL_R[0] | u_Gowin_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R25C33[1][A] | U_IES_Top/IES_inst/u_phy_manager/rx_shift_buf_13_s0/CLK |
0.385 | 0.201 | tC2Q | RF | 2 | R25C33[1][A] | U_IES_Top/IES_inst/u_phy_manager/rx_shift_buf_13_s0/Q |
0.510 | 0.125 | tNET | FF | 1 | R24C33 | U_IES_Top/IES_inst/u_phy_manager/phy_rdata_0_s8/DI[1] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | esc_sysclk | ||||
0.000 | 0.000 | tCL | RR | 12119 | PLL_R[0] | u_Gowin_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R24C33 | U_IES_Top/IES_inst/u_phy_manager/phy_rdata_0_s8/CLK |
0.196 | 0.012 | tHld | 1 | R24C33 | U_IES_Top/IES_inst/u_phy_manager/phy_rdata_0_s8 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.125, 38.377%; tC2Q: 0.201, 61.623% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path6
Path Summary:
Slack | 0.314 |
Data Arrival Time | 0.510 |
Data Required Time | 0.196 |
From | U_IES_Top/IES_inst/u_phy_manager/rx_shift_buf_9_s0 |
To | U_IES_Top/IES_inst/u_phy_manager/phy_rdata_0_s6 |
Launch Clk | esc_sysclk:[R] |
Latch Clk | esc_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | esc_sysclk | ||||
0.000 | 0.000 | tCL | RR | 12119 | PLL_R[0] | u_Gowin_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R25C32[1][A] | U_IES_Top/IES_inst/u_phy_manager/rx_shift_buf_9_s0/CLK |
0.385 | 0.201 | tC2Q | RF | 2 | R25C32[1][A] | U_IES_Top/IES_inst/u_phy_manager/rx_shift_buf_9_s0/Q |
0.510 | 0.125 | tNET | FF | 1 | R24C32 | U_IES_Top/IES_inst/u_phy_manager/phy_rdata_0_s6/DI[1] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | esc_sysclk | ||||
0.000 | 0.000 | tCL | RR | 12119 | PLL_R[0] | u_Gowin_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R24C32 | U_IES_Top/IES_inst/u_phy_manager/phy_rdata_0_s6/CLK |
0.196 | 0.012 | tHld | 1 | R24C32 | U_IES_Top/IES_inst/u_phy_manager/phy_rdata_0_s6 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.125, 38.377%; tC2Q: 0.201, 61.623% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path7
Path Summary:
Slack | 0.314 |
Data Arrival Time | 0.510 |
Data Required Time | 0.196 |
From | U_IES_Top/IES_inst/u_phy_manager/rx_shift_buf_8_s0 |
To | U_IES_Top/IES_inst/u_phy_manager/phy_rdata_0_s6 |
Launch Clk | esc_sysclk:[R] |
Latch Clk | esc_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | esc_sysclk | ||||
0.000 | 0.000 | tCL | RR | 12119 | PLL_R[0] | u_Gowin_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R25C32[2][A] | U_IES_Top/IES_inst/u_phy_manager/rx_shift_buf_8_s0/CLK |
0.385 | 0.201 | tC2Q | RF | 2 | R25C32[2][A] | U_IES_Top/IES_inst/u_phy_manager/rx_shift_buf_8_s0/Q |
0.510 | 0.125 | tNET | FF | 1 | R24C32 | U_IES_Top/IES_inst/u_phy_manager/phy_rdata_0_s6/DI[0] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | esc_sysclk | ||||
0.000 | 0.000 | tCL | RR | 12119 | PLL_R[0] | u_Gowin_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R24C32 | U_IES_Top/IES_inst/u_phy_manager/phy_rdata_0_s6/CLK |
0.196 | 0.012 | tHld | 1 | R24C32 | U_IES_Top/IES_inst/u_phy_manager/phy_rdata_0_s6 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.125, 38.377%; tC2Q: 0.201, 61.623% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path8
Path Summary:
Slack | 0.314 |
Data Arrival Time | 0.510 |
Data Required Time | 0.196 |
From | U_IES_Top/IES_inst/u_phy_manager/rx_shift_buf_3_s0 |
To | U_IES_Top/IES_inst/u_phy_manager/phy_rdata_0_s2 |
Launch Clk | esc_sysclk:[R] |
Latch Clk | esc_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | esc_sysclk | ||||
0.000 | 0.000 | tCL | RR | 12119 | PLL_R[0] | u_Gowin_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R25C31[1][A] | U_IES_Top/IES_inst/u_phy_manager/rx_shift_buf_3_s0/CLK |
0.385 | 0.201 | tC2Q | RF | 2 | R25C31[1][A] | U_IES_Top/IES_inst/u_phy_manager/rx_shift_buf_3_s0/Q |
0.510 | 0.125 | tNET | FF | 1 | R24C31 | U_IES_Top/IES_inst/u_phy_manager/phy_rdata_0_s2/DI[3] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | esc_sysclk | ||||
0.000 | 0.000 | tCL | RR | 12119 | PLL_R[0] | u_Gowin_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R24C31 | U_IES_Top/IES_inst/u_phy_manager/phy_rdata_0_s2/CLK |
0.196 | 0.012 | tHld | 1 | R24C31 | U_IES_Top/IES_inst/u_phy_manager/phy_rdata_0_s2 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.125, 38.377%; tC2Q: 0.201, 61.623% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path9
Path Summary:
Slack | 0.314 |
Data Arrival Time | 0.510 |
Data Required Time | 0.196 |
From | U_IES_Top/IES_inst/u_phy_manager/rx_shift_buf_2_s0 |
To | U_IES_Top/IES_inst/u_phy_manager/phy_rdata_0_s2 |
Launch Clk | esc_sysclk:[R] |
Latch Clk | esc_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | esc_sysclk | ||||
0.000 | 0.000 | tCL | RR | 12119 | PLL_R[0] | u_Gowin_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R24C30[2][B] | U_IES_Top/IES_inst/u_phy_manager/rx_shift_buf_2_s0/CLK |
0.385 | 0.201 | tC2Q | RF | 2 | R24C30[2][B] | U_IES_Top/IES_inst/u_phy_manager/rx_shift_buf_2_s0/Q |
0.510 | 0.125 | tNET | FF | 1 | R24C31 | U_IES_Top/IES_inst/u_phy_manager/phy_rdata_0_s2/DI[2] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | esc_sysclk | ||||
0.000 | 0.000 | tCL | RR | 12119 | PLL_R[0] | u_Gowin_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R24C31 | U_IES_Top/IES_inst/u_phy_manager/phy_rdata_0_s2/CLK |
0.196 | 0.012 | tHld | 1 | R24C31 | U_IES_Top/IES_inst/u_phy_manager/phy_rdata_0_s2 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.125, 38.377%; tC2Q: 0.201, 61.623% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path10
Path Summary:
Slack | 0.314 |
Data Arrival Time | 0.510 |
Data Required Time | 0.196 |
From | U_IES_Top/IES_inst/u_phy_manager/rx_shift_buf_1_s0 |
To | U_IES_Top/IES_inst/u_phy_manager/phy_rdata_0_s2 |
Launch Clk | esc_sysclk:[R] |
Latch Clk | esc_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | esc_sysclk | ||||
0.000 | 0.000 | tCL | RR | 12119 | PLL_R[0] | u_Gowin_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R24C30[2][A] | U_IES_Top/IES_inst/u_phy_manager/rx_shift_buf_1_s0/CLK |
0.385 | 0.201 | tC2Q | RF | 2 | R24C30[2][A] | U_IES_Top/IES_inst/u_phy_manager/rx_shift_buf_1_s0/Q |
0.510 | 0.125 | tNET | FF | 1 | R24C31 | U_IES_Top/IES_inst/u_phy_manager/phy_rdata_0_s2/DI[1] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | esc_sysclk | ||||
0.000 | 0.000 | tCL | RR | 12119 | PLL_R[0] | u_Gowin_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R24C31 | U_IES_Top/IES_inst/u_phy_manager/phy_rdata_0_s2/CLK |
0.196 | 0.012 | tHld | 1 | R24C31 | U_IES_Top/IES_inst/u_phy_manager/phy_rdata_0_s2 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.125, 38.377%; tC2Q: 0.201, 61.623% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path11
Path Summary:
Slack | 0.321 |
Data Arrival Time | 0.517 |
Data Required Time | 0.195 |
From | U_IES_Top/IES_inst/u_pdi_sm/req_valid_s0 |
To | U_IES_Top/IES_inst/u_pdi_search_m_top/pdi_search_m_gen[0].u_pdi_search_m/first_addr_tmp_0_s0 |
Launch Clk | esc_sysclk:[R] |
Latch Clk | esc_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | esc_sysclk | ||||
0.000 | 0.000 | tCL | RR | 12119 | PLL_R[0] | u_Gowin_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R70C22[0][B] | U_IES_Top/IES_inst/u_pdi_sm/req_valid_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 18 | R70C22[0][B] | U_IES_Top/IES_inst/u_pdi_sm/req_valid_s0/Q |
0.517 | 0.130 | tNET | RR | 1 | R70C23[1][B] | U_IES_Top/IES_inst/u_pdi_search_m_top/pdi_search_m_gen[0].u_pdi_search_m/first_addr_tmp_0_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | esc_sysclk | ||||
0.000 | 0.000 | tCL | RR | 12119 | PLL_R[0] | u_Gowin_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R70C23[1][B] | U_IES_Top/IES_inst/u_pdi_search_m_top/pdi_search_m_gen[0].u_pdi_search_m/first_addr_tmp_0_s0/CLK |
0.195 | 0.011 | tHld | 1 | R70C23[1][B] | U_IES_Top/IES_inst/u_pdi_search_m_top/pdi_search_m_gen[0].u_pdi_search_m/first_addr_tmp_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.130, 39.238%; tC2Q: 0.202, 60.762% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path12
Path Summary:
Slack | 0.321 |
Data Arrival Time | 0.517 |
Data Required Time | 0.195 |
From | U_IES_Top/IES_inst/u_pdi_sm/req_valid_s0 |
To | U_IES_Top/IES_inst/u_pdi_search_m_top/pdi_search_m_gen[0].u_pdi_search_m/first_addr_tmp_1_s0 |
Launch Clk | esc_sysclk:[R] |
Latch Clk | esc_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | esc_sysclk | ||||
0.000 | 0.000 | tCL | RR | 12119 | PLL_R[0] | u_Gowin_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R70C22[0][B] | U_IES_Top/IES_inst/u_pdi_sm/req_valid_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 18 | R70C22[0][B] | U_IES_Top/IES_inst/u_pdi_sm/req_valid_s0/Q |
0.517 | 0.130 | tNET | RR | 1 | R70C23[0][B] | U_IES_Top/IES_inst/u_pdi_search_m_top/pdi_search_m_gen[0].u_pdi_search_m/first_addr_tmp_1_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | esc_sysclk | ||||
0.000 | 0.000 | tCL | RR | 12119 | PLL_R[0] | u_Gowin_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R70C23[0][B] | U_IES_Top/IES_inst/u_pdi_search_m_top/pdi_search_m_gen[0].u_pdi_search_m/first_addr_tmp_1_s0/CLK |
0.195 | 0.011 | tHld | 1 | R70C23[0][B] | U_IES_Top/IES_inst/u_pdi_search_m_top/pdi_search_m_gen[0].u_pdi_search_m/first_addr_tmp_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.130, 39.238%; tC2Q: 0.202, 60.762% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path13
Path Summary:
Slack | 0.321 |
Data Arrival Time | 0.517 |
Data Required Time | 0.195 |
From | U_IES_Top/IES_inst/u_pdi_sm/req_valid_s0 |
To | U_IES_Top/IES_inst/u_pdi_search_m_top/pdi_search_m_gen[0].u_pdi_search_m/first_addr_tmp_2_s0 |
Launch Clk | esc_sysclk:[R] |
Latch Clk | esc_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | esc_sysclk | ||||
0.000 | 0.000 | tCL | RR | 12119 | PLL_R[0] | u_Gowin_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R70C22[0][B] | U_IES_Top/IES_inst/u_pdi_sm/req_valid_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 18 | R70C22[0][B] | U_IES_Top/IES_inst/u_pdi_sm/req_valid_s0/Q |
0.517 | 0.130 | tNET | RR | 1 | R70C23[2][B] | U_IES_Top/IES_inst/u_pdi_search_m_top/pdi_search_m_gen[0].u_pdi_search_m/first_addr_tmp_2_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | esc_sysclk | ||||
0.000 | 0.000 | tCL | RR | 12119 | PLL_R[0] | u_Gowin_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R70C23[2][B] | U_IES_Top/IES_inst/u_pdi_search_m_top/pdi_search_m_gen[0].u_pdi_search_m/first_addr_tmp_2_s0/CLK |
0.195 | 0.011 | tHld | 1 | R70C23[2][B] | U_IES_Top/IES_inst/u_pdi_search_m_top/pdi_search_m_gen[0].u_pdi_search_m/first_addr_tmp_2_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.130, 39.238%; tC2Q: 0.202, 60.762% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path14
Path Summary:
Slack | 0.321 |
Data Arrival Time | 0.517 |
Data Required Time | 0.195 |
From | U_IES_Top/IES_inst/u_pdi_sm/req_valid_s0 |
To | U_IES_Top/IES_inst/u_pdi_search_m_top/pdi_search_m_gen[0].u_pdi_search_m/first_addr_tmp_3_s0 |
Launch Clk | esc_sysclk:[R] |
Latch Clk | esc_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | esc_sysclk | ||||
0.000 | 0.000 | tCL | RR | 12119 | PLL_R[0] | u_Gowin_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R70C22[0][B] | U_IES_Top/IES_inst/u_pdi_sm/req_valid_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 18 | R70C22[0][B] | U_IES_Top/IES_inst/u_pdi_sm/req_valid_s0/Q |
0.517 | 0.130 | tNET | RR | 1 | R70C23[2][A] | U_IES_Top/IES_inst/u_pdi_search_m_top/pdi_search_m_gen[0].u_pdi_search_m/first_addr_tmp_3_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | esc_sysclk | ||||
0.000 | 0.000 | tCL | RR | 12119 | PLL_R[0] | u_Gowin_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R70C23[2][A] | U_IES_Top/IES_inst/u_pdi_search_m_top/pdi_search_m_gen[0].u_pdi_search_m/first_addr_tmp_3_s0/CLK |
0.195 | 0.011 | tHld | 1 | R70C23[2][A] | U_IES_Top/IES_inst/u_pdi_search_m_top/pdi_search_m_gen[0].u_pdi_search_m/first_addr_tmp_3_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.130, 39.238%; tC2Q: 0.202, 60.762% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path15
Path Summary:
Slack | 0.321 |
Data Arrival Time | 0.517 |
Data Required Time | 0.195 |
From | U_IES_Top/IES_inst/u_pdi_sm/req_valid_s0 |
To | U_IES_Top/IES_inst/u_pdi_search_m_top/pdi_search_m_gen[0].u_pdi_search_m/first_addr_tmp_7_s0 |
Launch Clk | esc_sysclk:[R] |
Latch Clk | esc_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | esc_sysclk | ||||
0.000 | 0.000 | tCL | RR | 12119 | PLL_R[0] | u_Gowin_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R70C22[0][B] | U_IES_Top/IES_inst/u_pdi_sm/req_valid_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 18 | R70C22[0][B] | U_IES_Top/IES_inst/u_pdi_sm/req_valid_s0/Q |
0.517 | 0.130 | tNET | RR | 1 | R70C23[1][A] | U_IES_Top/IES_inst/u_pdi_search_m_top/pdi_search_m_gen[0].u_pdi_search_m/first_addr_tmp_7_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | esc_sysclk | ||||
0.000 | 0.000 | tCL | RR | 12119 | PLL_R[0] | u_Gowin_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R70C23[1][A] | U_IES_Top/IES_inst/u_pdi_search_m_top/pdi_search_m_gen[0].u_pdi_search_m/first_addr_tmp_7_s0/CLK |
0.195 | 0.011 | tHld | 1 | R70C23[1][A] | U_IES_Top/IES_inst/u_pdi_search_m_top/pdi_search_m_gen[0].u_pdi_search_m/first_addr_tmp_7_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.130, 39.238%; tC2Q: 0.202, 60.762% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path16
Path Summary:
Slack | 0.321 |
Data Arrival Time | 0.517 |
Data Required Time | 0.195 |
From | U_IES_Top/IES_inst/u_pdi_sm/req_valid_s0 |
To | U_IES_Top/IES_inst/u_pdi_search_m_top/pdi_search_m_gen[0].u_pdi_search_m/first_addr_tmp_15_s0 |
Launch Clk | esc_sysclk:[R] |
Latch Clk | esc_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | esc_sysclk | ||||
0.000 | 0.000 | tCL | RR | 12119 | PLL_R[0] | u_Gowin_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R70C22[0][B] | U_IES_Top/IES_inst/u_pdi_sm/req_valid_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 18 | R70C22[0][B] | U_IES_Top/IES_inst/u_pdi_sm/req_valid_s0/Q |
0.517 | 0.130 | tNET | RR | 1 | R70C23[0][A] | U_IES_Top/IES_inst/u_pdi_search_m_top/pdi_search_m_gen[0].u_pdi_search_m/first_addr_tmp_15_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | esc_sysclk | ||||
0.000 | 0.000 | tCL | RR | 12119 | PLL_R[0] | u_Gowin_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R70C23[0][A] | U_IES_Top/IES_inst/u_pdi_search_m_top/pdi_search_m_gen[0].u_pdi_search_m/first_addr_tmp_15_s0/CLK |
0.195 | 0.011 | tHld | 1 | R70C23[0][A] | U_IES_Top/IES_inst/u_pdi_search_m_top/pdi_search_m_gen[0].u_pdi_search_m/first_addr_tmp_15_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.130, 39.238%; tC2Q: 0.202, 60.762% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path17
Path Summary:
Slack | 0.322 |
Data Arrival Time | 0.517 |
Data Required Time | 0.195 |
From | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb12/HREADYOUT_s0 |
To | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb12/HRESP_0_s0 |
Launch Clk | mcu_sysclk:[R] |
Latch Clk | mcu_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | mcu_sysclk | ||||
0.000 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R15C16[0][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb12/HREADYOUT_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 4 | R15C16[0][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb12/HREADYOUT_s0/Q |
0.517 | 0.131 | tNET | RR | 1 | R15C16[2][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb12/HRESP_0_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | mcu_sysclk | ||||
0.000 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R15C16[2][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb12/HRESP_0_s0/CLK |
0.195 | 0.011 | tHld | 1 | R15C16[2][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb12/HRESP_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.131, 39.314%; tC2Q: 0.202, 60.686% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path18
Path Summary:
Slack | 0.322 |
Data Arrival Time | 0.517 |
Data Required Time | 0.195 |
From | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb4/HREADYOUT_s0 |
To | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb4/HRESP_0_s0 |
Launch Clk | mcu_sysclk:[R] |
Latch Clk | mcu_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | mcu_sysclk | ||||
0.000 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R13C17[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb4/HREADYOUT_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 5 | R13C17[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb4/HREADYOUT_s0/Q |
0.517 | 0.131 | tNET | RR | 1 | R13C17[0][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb4/HRESP_0_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | mcu_sysclk | ||||
0.000 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R13C17[0][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb4/HRESP_0_s0/CLK |
0.195 | 0.011 | tHld | 1 | R13C17[0][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb4/HRESP_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.131, 39.314%; tC2Q: 0.202, 60.686% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path19
Path Summary:
Slack | 0.322 |
Data Arrival Time | 0.517 |
Data Required Time | 0.195 |
From | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb_spi_flash/HREADYOUT_s0 |
To | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb_spi_flash/HRESP_0_s0 |
Launch Clk | mcu_sysclk:[R] |
Latch Clk | mcu_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | mcu_sysclk | ||||
0.000 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R15C16[0][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb_spi_flash/HREADYOUT_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 5 | R15C16[0][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb_spi_flash/HREADYOUT_s0/Q |
0.517 | 0.131 | tNET | RR | 1 | R15C16[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb_spi_flash/HRESP_0_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | mcu_sysclk | ||||
0.000 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R15C16[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb_spi_flash/HRESP_0_s0/CLK |
0.195 | 0.011 | tHld | 1 | R15C16[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb_spi_flash/HRESP_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.131, 39.314%; tC2Q: 0.202, 60.686% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path20
Path Summary:
Slack | 0.322 |
Data Arrival Time | 0.517 |
Data Required Time | 0.195 |
From | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb_can/HREADYOUT_s0 |
To | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb_can/HRESP_0_s0 |
Launch Clk | mcu_sysclk:[R] |
Latch Clk | mcu_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | mcu_sysclk | ||||
0.000 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R9C17[0][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb_can/HREADYOUT_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 6 | R9C17[0][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb_can/HREADYOUT_s0/Q |
0.517 | 0.131 | tNET | RR | 1 | R11C17[0][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb_can/HRESP_0_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | mcu_sysclk | ||||
0.000 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R11C17[0][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb_can/HRESP_0_s0/CLK |
0.195 | 0.011 | tHld | 1 | R11C17[0][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb_can/HRESP_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.131, 39.360%; tC2Q: 0.202, 60.640% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path21
Path Summary:
Slack | 0.323 |
Data Arrival Time | 0.518 |
Data Required Time | 0.195 |
From | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb11/HREADYOUT_s0 |
To | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb11/HRESP_0_s0 |
Launch Clk | mcu_sysclk:[R] |
Latch Clk | mcu_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | mcu_sysclk | ||||
0.000 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R12C16[0][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb11/HREADYOUT_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 5 | R12C16[0][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb11/HREADYOUT_s0/Q |
0.518 | 0.132 | tNET | RR | 1 | R12C16[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb11/HRESP_0_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | mcu_sysclk | ||||
0.000 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R12C16[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb11/HRESP_0_s0/CLK |
0.195 | 0.011 | tHld | 1 | R12C16[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb11/HRESP_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.132, 39.536%; tC2Q: 0.202, 60.464% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path22
Path Summary:
Slack | 0.323 |
Data Arrival Time | 0.518 |
Data Required Time | 0.195 |
From | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_ahb/haddr_en_reg_s0 |
To | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_ahb/asel_ppb_reg_s0 |
Launch Clk | mcu_sysclk:[R] |
Latch Clk | mcu_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | mcu_sysclk | ||||
0.000 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R26C11[1][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_ahb/haddr_en_reg_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 2 | R26C11[1][B] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_ahb/haddr_en_reg_s0/Q |
0.518 | 0.132 | tNET | RR | 1 | R26C11[2][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_ahb/asel_ppb_reg_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | mcu_sysclk | ||||
0.000 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R26C11[2][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_ahb/asel_ppb_reg_s0/CLK |
0.195 | 0.011 | tHld | 1 | R26C11[2][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_ahb/asel_ppb_reg_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.132, 39.550%; tC2Q: 0.202, 60.450% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path23
Path Summary:
Slack | 0.324 |
Data Arrival Time | 0.520 |
Data Required Time | 0.195 |
From | U_IES_Top/IES_inst/u_pdi_sm/req_valid_s0 |
To | U_IES_Top/IES_inst/u_pdi_search_m_top/pdi_search_m_gen[0].u_pdi_search_m/first_addr_tmp_8_s0 |
Launch Clk | esc_sysclk:[R] |
Latch Clk | esc_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | esc_sysclk | ||||
0.000 | 0.000 | tCL | RR | 12119 | PLL_R[0] | u_Gowin_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R70C22[0][B] | U_IES_Top/IES_inst/u_pdi_sm/req_valid_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 18 | R70C22[0][B] | U_IES_Top/IES_inst/u_pdi_sm/req_valid_s0/Q |
0.520 | 0.133 | tNET | RR | 1 | R70C22[1][A] | U_IES_Top/IES_inst/u_pdi_search_m_top/pdi_search_m_gen[0].u_pdi_search_m/first_addr_tmp_8_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | esc_sysclk | ||||
0.000 | 0.000 | tCL | RR | 12119 | PLL_R[0] | u_Gowin_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R70C22[1][A] | U_IES_Top/IES_inst/u_pdi_search_m_top/pdi_search_m_gen[0].u_pdi_search_m/first_addr_tmp_8_s0/CLK |
0.195 | 0.011 | tHld | 1 | R70C22[1][A] | U_IES_Top/IES_inst/u_pdi_search_m_top/pdi_search_m_gen[0].u_pdi_search_m/first_addr_tmp_8_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.133, 39.771%; tC2Q: 0.202, 60.229% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path24
Path Summary:
Slack | 0.324 |
Data Arrival Time | 0.520 |
Data Required Time | 0.195 |
From | U_IES_Top/IES_inst/u_pdi_sm/req_valid_s0 |
To | U_IES_Top/IES_inst/u_pdi_search_m_top/pdi_search_m_gen[0].u_pdi_search_m/first_addr_tmp_9_s0 |
Launch Clk | esc_sysclk:[R] |
Latch Clk | esc_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | esc_sysclk | ||||
0.000 | 0.000 | tCL | RR | 12119 | PLL_R[0] | u_Gowin_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R70C22[0][B] | U_IES_Top/IES_inst/u_pdi_sm/req_valid_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 18 | R70C22[0][B] | U_IES_Top/IES_inst/u_pdi_sm/req_valid_s0/Q |
0.520 | 0.133 | tNET | RR | 1 | R70C22[2][B] | U_IES_Top/IES_inst/u_pdi_search_m_top/pdi_search_m_gen[0].u_pdi_search_m/first_addr_tmp_9_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | esc_sysclk | ||||
0.000 | 0.000 | tCL | RR | 12119 | PLL_R[0] | u_Gowin_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R70C22[2][B] | U_IES_Top/IES_inst/u_pdi_search_m_top/pdi_search_m_gen[0].u_pdi_search_m/first_addr_tmp_9_s0/CLK |
0.195 | 0.011 | tHld | 1 | R70C22[2][B] | U_IES_Top/IES_inst/u_pdi_search_m_top/pdi_search_m_gen[0].u_pdi_search_m/first_addr_tmp_9_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.133, 39.771%; tC2Q: 0.202, 60.229% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path25
Path Summary:
Slack | 0.324 |
Data Arrival Time | 0.520 |
Data Required Time | 0.195 |
From | U_IES_Top/IES_inst/u_pdi_sm/req_valid_s0 |
To | U_IES_Top/IES_inst/u_pdi_search_m_top/pdi_search_m_gen[0].u_pdi_search_m/first_addr_tmp_13_s0 |
Launch Clk | esc_sysclk:[R] |
Latch Clk | esc_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | esc_sysclk | ||||
0.000 | 0.000 | tCL | RR | 12119 | PLL_R[0] | u_Gowin_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R70C22[0][B] | U_IES_Top/IES_inst/u_pdi_sm/req_valid_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 18 | R70C22[0][B] | U_IES_Top/IES_inst/u_pdi_sm/req_valid_s0/Q |
0.520 | 0.133 | tNET | RR | 1 | R70C22[2][A] | U_IES_Top/IES_inst/u_pdi_search_m_top/pdi_search_m_gen[0].u_pdi_search_m/first_addr_tmp_13_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | esc_sysclk | ||||
0.000 | 0.000 | tCL | RR | 12119 | PLL_R[0] | u_Gowin_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R70C22[2][A] | U_IES_Top/IES_inst/u_pdi_search_m_top/pdi_search_m_gen[0].u_pdi_search_m/first_addr_tmp_13_s0/CLK |
0.195 | 0.011 | tHld | 1 | R70C22[2][A] | U_IES_Top/IES_inst/u_pdi_search_m_top/pdi_search_m_gen[0].u_pdi_search_m/first_addr_tmp_13_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.133, 39.771%; tC2Q: 0.202, 60.229% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Recovery Analysis Report
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 4.942 |
Data Arrival Time | 4.828 |
Data Required Time | 9.770 |
From | u_button/out_s0 |
To | U_IES_Top/IES_inst/fifo_top_inst1/fifo_inst/Equal.mem_Equal.mem_0_0_s |
Launch Clk | clkin:[R] |
Latch Clk | esc_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clkin | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk25_ibuf/I |
0.683 | 0.683 | tINS | RR | 42 | IOT48[A] | clk25_ibuf/O |
0.926 | 0.243 | tNET | RR | 1 | R35C18[0][A] | u_button/out_s0/CLK |
1.158 | 0.232 | tC2Q | RF | 27 | R35C18[0][A] | u_button/out_s0/Q |
2.225 | 1.067 | tNET | FF | 1 | R34C42[0][A] | U_IES_Top/IES_inst/n364_s2/I0 |
2.780 | 0.555 | tINS | FF | 12187 | R34C42[0][A] | U_IES_Top/IES_inst/n364_s2/F |
4.828 | 2.048 | tNET | FF | 16 | BSRAM_R10[25] | U_IES_Top/IES_inst/fifo_top_inst1/fifo_inst/Equal.mem_Equal.mem_0_0_s/RESETB |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | esc_sysclk | ||||
10.000 | 0.000 | tCL | RR | 12119 | PLL_R[0] | u_Gowin_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | BSRAM_R10[25] | U_IES_Top/IES_inst/fifo_top_inst1/fifo_inst/Equal.mem_Equal.mem_0_0_s/CLKB |
10.208 | -0.035 | tUnc | U_IES_Top/IES_inst/fifo_top_inst1/fifo_inst/Equal.mem_Equal.mem_0_0_s | |||
9.770 | -0.438 | tSu | 1 | BSRAM_R10[25] | U_IES_Top/IES_inst/fifo_top_inst1/fifo_inst/Equal.mem_Equal.mem_0_0_s |
Path Statistics:
Clock Skew | -0.683 |
Setup Relationship | 10.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Arrival Data Path Delay | cell: 0.555, 14.223%; route: 3.115, 79.832%; tC2Q: 0.232, 5.945% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path2
Path Summary:
Slack | 4.942 |
Data Arrival Time | 4.828 |
Data Required Time | 9.770 |
From | u_button/out_s0 |
To | U_IES_Top/IES_inst/fifo_top_inst0/fifo_inst/Equal.mem_Equal.mem_0_0_s |
Launch Clk | clkin:[R] |
Latch Clk | esc_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clkin | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk25_ibuf/I |
0.683 | 0.683 | tINS | RR | 42 | IOT48[A] | clk25_ibuf/O |
0.926 | 0.243 | tNET | RR | 1 | R35C18[0][A] | u_button/out_s0/CLK |
1.158 | 0.232 | tC2Q | RF | 27 | R35C18[0][A] | u_button/out_s0/Q |
2.225 | 1.067 | tNET | FF | 1 | R34C42[0][A] | U_IES_Top/IES_inst/n364_s2/I0 |
2.780 | 0.555 | tINS | FF | 12187 | R34C42[0][A] | U_IES_Top/IES_inst/n364_s2/F |
4.828 | 2.048 | tNET | FF | 16 | BSRAM_R36[17] | U_IES_Top/IES_inst/fifo_top_inst0/fifo_inst/Equal.mem_Equal.mem_0_0_s/RESETB |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | esc_sysclk | ||||
10.000 | 0.000 | tCL | RR | 12119 | PLL_R[0] | u_Gowin_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | BSRAM_R36[17] | U_IES_Top/IES_inst/fifo_top_inst0/fifo_inst/Equal.mem_Equal.mem_0_0_s/CLKB |
10.208 | -0.035 | tUnc | U_IES_Top/IES_inst/fifo_top_inst0/fifo_inst/Equal.mem_Equal.mem_0_0_s | |||
9.770 | -0.438 | tSu | 1 | BSRAM_R36[17] | U_IES_Top/IES_inst/fifo_top_inst0/fifo_inst/Equal.mem_Equal.mem_0_0_s |
Path Statistics:
Clock Skew | -0.683 |
Setup Relationship | 10.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Arrival Data Path Delay | cell: 0.555, 14.223%; route: 3.115, 79.832%; tC2Q: 0.232, 5.945% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path3
Path Summary:
Slack | 4.942 |
Data Arrival Time | 4.828 |
Data Required Time | 9.770 |
From | u_button/out_s0 |
To | U_IES_Top/IES_inst/u_dp_mem/mem_u_mem_u_0_0_s |
Launch Clk | clkin:[R] |
Latch Clk | esc_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clkin | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk25_ibuf/I |
0.683 | 0.683 | tINS | RR | 42 | IOT48[A] | clk25_ibuf/O |
0.926 | 0.243 | tNET | RR | 1 | R35C18[0][A] | u_button/out_s0/CLK |
1.158 | 0.232 | tC2Q | RF | 27 | R35C18[0][A] | u_button/out_s0/Q |
2.225 | 1.067 | tNET | FF | 1 | R34C42[0][A] | U_IES_Top/IES_inst/n364_s2/I0 |
2.780 | 0.555 | tINS | FF | 12187 | R34C42[0][A] | U_IES_Top/IES_inst/n364_s2/F |
4.828 | 2.048 | tNET | FF | 8 | BSRAM_R36[14] | U_IES_Top/IES_inst/u_dp_mem/mem_u_mem_u_0_0_s/RESETB |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | esc_sysclk | ||||
10.000 | 0.000 | tCL | RR | 12119 | PLL_R[0] | u_Gowin_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | BSRAM_R36[14] | U_IES_Top/IES_inst/u_dp_mem/mem_u_mem_u_0_0_s/CLKB |
10.208 | -0.035 | tUnc | U_IES_Top/IES_inst/u_dp_mem/mem_u_mem_u_0_0_s | |||
9.770 | -0.438 | tSu | 1 | BSRAM_R36[14] | U_IES_Top/IES_inst/u_dp_mem/mem_u_mem_u_0_0_s |
Path Statistics:
Clock Skew | -0.683 |
Setup Relationship | 10.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Arrival Data Path Delay | cell: 0.555, 14.223%; route: 3.115, 79.832%; tC2Q: 0.232, 5.945% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path4
Path Summary:
Slack | 4.942 |
Data Arrival Time | 4.828 |
Data Required Time | 9.770 |
From | u_button/out_s0 |
To | U_IES_Top/IES_inst/u_dp_mem/mem_u_mem_u_0_0_s |
Launch Clk | clkin:[R] |
Latch Clk | esc_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clkin | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk25_ibuf/I |
0.683 | 0.683 | tINS | RR | 42 | IOT48[A] | clk25_ibuf/O |
0.926 | 0.243 | tNET | RR | 1 | R35C18[0][A] | u_button/out_s0/CLK |
1.158 | 0.232 | tC2Q | RF | 27 | R35C18[0][A] | u_button/out_s0/Q |
2.225 | 1.067 | tNET | FF | 1 | R34C42[0][A] | U_IES_Top/IES_inst/n364_s2/I0 |
2.780 | 0.555 | tINS | FF | 12187 | R34C42[0][A] | U_IES_Top/IES_inst/n364_s2/F |
4.828 | 2.048 | tNET | FF | 8 | BSRAM_R36[14] | U_IES_Top/IES_inst/u_dp_mem/mem_u_mem_u_0_0_s/RESETA |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | esc_sysclk | ||||
10.000 | 0.000 | tCL | RR | 12119 | PLL_R[0] | u_Gowin_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | BSRAM_R36[14] | U_IES_Top/IES_inst/u_dp_mem/mem_u_mem_u_0_0_s/CLKA |
10.208 | -0.035 | tUnc | U_IES_Top/IES_inst/u_dp_mem/mem_u_mem_u_0_0_s | |||
9.770 | -0.438 | tSu | 1 | BSRAM_R36[14] | U_IES_Top/IES_inst/u_dp_mem/mem_u_mem_u_0_0_s |
Path Statistics:
Clock Skew | -0.683 |
Setup Relationship | 10.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Arrival Data Path Delay | cell: 0.555, 14.223%; route: 3.115, 79.832%; tC2Q: 0.232, 5.945% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path5
Path Summary:
Slack | 4.942 |
Data Arrival Time | 4.828 |
Data Required Time | 9.770 |
From | u_button/out_s0 |
To | U_IES_Top/IES_inst/u_dp_mem/mem_mem_0_3_s |
Launch Clk | clkin:[R] |
Latch Clk | esc_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clkin | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk25_ibuf/I |
0.683 | 0.683 | tINS | RR | 42 | IOT48[A] | clk25_ibuf/O |
0.926 | 0.243 | tNET | RR | 1 | R35C18[0][A] | u_button/out_s0/CLK |
1.158 | 0.232 | tC2Q | RF | 27 | R35C18[0][A] | u_button/out_s0/Q |
2.225 | 1.067 | tNET | FF | 1 | R34C42[0][A] | U_IES_Top/IES_inst/n364_s2/I0 |
2.780 | 0.555 | tINS | FF | 12187 | R34C42[0][A] | U_IES_Top/IES_inst/n364_s2/F |
4.828 | 2.048 | tNET | FF | 2 | BSRAM_R45[16] | U_IES_Top/IES_inst/u_dp_mem/mem_mem_0_3_s/RESETB |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | esc_sysclk | ||||
10.000 | 0.000 | tCL | RR | 12119 | PLL_R[0] | u_Gowin_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | BSRAM_R45[16] | U_IES_Top/IES_inst/u_dp_mem/mem_mem_0_3_s/CLKB |
10.208 | -0.035 | tUnc | U_IES_Top/IES_inst/u_dp_mem/mem_mem_0_3_s | |||
9.770 | -0.438 | tSu | 1 | BSRAM_R45[16] | U_IES_Top/IES_inst/u_dp_mem/mem_mem_0_3_s |
Path Statistics:
Clock Skew | -0.683 |
Setup Relationship | 10.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Arrival Data Path Delay | cell: 0.555, 14.223%; route: 3.115, 79.832%; tC2Q: 0.232, 5.945% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path6
Path Summary:
Slack | 4.942 |
Data Arrival Time | 4.828 |
Data Required Time | 9.770 |
From | u_button/out_s0 |
To | U_IES_Top/IES_inst/u_dp_mem/mem_mem_0_3_s |
Launch Clk | clkin:[R] |
Latch Clk | esc_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clkin | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk25_ibuf/I |
0.683 | 0.683 | tINS | RR | 42 | IOT48[A] | clk25_ibuf/O |
0.926 | 0.243 | tNET | RR | 1 | R35C18[0][A] | u_button/out_s0/CLK |
1.158 | 0.232 | tC2Q | RF | 27 | R35C18[0][A] | u_button/out_s0/Q |
2.225 | 1.067 | tNET | FF | 1 | R34C42[0][A] | U_IES_Top/IES_inst/n364_s2/I0 |
2.780 | 0.555 | tINS | FF | 12187 | R34C42[0][A] | U_IES_Top/IES_inst/n364_s2/F |
4.828 | 2.048 | tNET | FF | 2 | BSRAM_R45[16] | U_IES_Top/IES_inst/u_dp_mem/mem_mem_0_3_s/RESETA |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | esc_sysclk | ||||
10.000 | 0.000 | tCL | RR | 12119 | PLL_R[0] | u_Gowin_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | BSRAM_R45[16] | U_IES_Top/IES_inst/u_dp_mem/mem_mem_0_3_s/CLKA |
10.208 | -0.035 | tUnc | U_IES_Top/IES_inst/u_dp_mem/mem_mem_0_3_s | |||
9.770 | -0.438 | tSu | 1 | BSRAM_R45[16] | U_IES_Top/IES_inst/u_dp_mem/mem_mem_0_3_s |
Path Statistics:
Clock Skew | -0.683 |
Setup Relationship | 10.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Arrival Data Path Delay | cell: 0.555, 14.223%; route: 3.115, 79.832%; tC2Q: 0.232, 5.945% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path7
Path Summary:
Slack | 4.942 |
Data Arrival Time | 4.828 |
Data Required Time | 9.770 |
From | u_button/out_s0 |
To | U_IES_Top/IES_inst/u_dp_mem/mem_mem_0_2_s |
Launch Clk | clkin:[R] |
Latch Clk | esc_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clkin | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk25_ibuf/I |
0.683 | 0.683 | tINS | RR | 42 | IOT48[A] | clk25_ibuf/O |
0.926 | 0.243 | tNET | RR | 1 | R35C18[0][A] | u_button/out_s0/CLK |
1.158 | 0.232 | tC2Q | RF | 27 | R35C18[0][A] | u_button/out_s0/Q |
2.225 | 1.067 | tNET | FF | 1 | R34C42[0][A] | U_IES_Top/IES_inst/n364_s2/I0 |
2.780 | 0.555 | tINS | FF | 12187 | R34C42[0][A] | U_IES_Top/IES_inst/n364_s2/F |
4.828 | 2.048 | tNET | FF | 2 | BSRAM_R36[16] | U_IES_Top/IES_inst/u_dp_mem/mem_mem_0_2_s/RESETB |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | esc_sysclk | ||||
10.000 | 0.000 | tCL | RR | 12119 | PLL_R[0] | u_Gowin_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | BSRAM_R36[16] | U_IES_Top/IES_inst/u_dp_mem/mem_mem_0_2_s/CLKB |
10.208 | -0.035 | tUnc | U_IES_Top/IES_inst/u_dp_mem/mem_mem_0_2_s | |||
9.770 | -0.438 | tSu | 1 | BSRAM_R36[16] | U_IES_Top/IES_inst/u_dp_mem/mem_mem_0_2_s |
Path Statistics:
Clock Skew | -0.683 |
Setup Relationship | 10.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Arrival Data Path Delay | cell: 0.555, 14.223%; route: 3.115, 79.832%; tC2Q: 0.232, 5.945% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path8
Path Summary:
Slack | 4.942 |
Data Arrival Time | 4.828 |
Data Required Time | 9.770 |
From | u_button/out_s0 |
To | U_IES_Top/IES_inst/u_dp_mem/mem_mem_0_2_s |
Launch Clk | clkin:[R] |
Latch Clk | esc_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clkin | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk25_ibuf/I |
0.683 | 0.683 | tINS | RR | 42 | IOT48[A] | clk25_ibuf/O |
0.926 | 0.243 | tNET | RR | 1 | R35C18[0][A] | u_button/out_s0/CLK |
1.158 | 0.232 | tC2Q | RF | 27 | R35C18[0][A] | u_button/out_s0/Q |
2.225 | 1.067 | tNET | FF | 1 | R34C42[0][A] | U_IES_Top/IES_inst/n364_s2/I0 |
2.780 | 0.555 | tINS | FF | 12187 | R34C42[0][A] | U_IES_Top/IES_inst/n364_s2/F |
4.828 | 2.048 | tNET | FF | 2 | BSRAM_R36[16] | U_IES_Top/IES_inst/u_dp_mem/mem_mem_0_2_s/RESETA |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | esc_sysclk | ||||
10.000 | 0.000 | tCL | RR | 12119 | PLL_R[0] | u_Gowin_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | BSRAM_R36[16] | U_IES_Top/IES_inst/u_dp_mem/mem_mem_0_2_s/CLKA |
10.208 | -0.035 | tUnc | U_IES_Top/IES_inst/u_dp_mem/mem_mem_0_2_s | |||
9.770 | -0.438 | tSu | 1 | BSRAM_R36[16] | U_IES_Top/IES_inst/u_dp_mem/mem_mem_0_2_s |
Path Statistics:
Clock Skew | -0.683 |
Setup Relationship | 10.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Arrival Data Path Delay | cell: 0.555, 14.223%; route: 3.115, 79.832%; tC2Q: 0.232, 5.945% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path9
Path Summary:
Slack | 4.942 |
Data Arrival Time | 4.828 |
Data Required Time | 9.770 |
From | u_button/out_s0 |
To | U_IES_Top/IES_inst/u_dp_mem/mem_mem_0_1_s |
Launch Clk | clkin:[R] |
Latch Clk | esc_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clkin | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk25_ibuf/I |
0.683 | 0.683 | tINS | RR | 42 | IOT48[A] | clk25_ibuf/O |
0.926 | 0.243 | tNET | RR | 1 | R35C18[0][A] | u_button/out_s0/CLK |
1.158 | 0.232 | tC2Q | RF | 27 | R35C18[0][A] | u_button/out_s0/Q |
2.225 | 1.067 | tNET | FF | 1 | R34C42[0][A] | U_IES_Top/IES_inst/n364_s2/I0 |
2.780 | 0.555 | tINS | FF | 12187 | R34C42[0][A] | U_IES_Top/IES_inst/n364_s2/F |
4.828 | 2.048 | tNET | FF | 2 | BSRAM_R36[15] | U_IES_Top/IES_inst/u_dp_mem/mem_mem_0_1_s/RESETB |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | esc_sysclk | ||||
10.000 | 0.000 | tCL | RR | 12119 | PLL_R[0] | u_Gowin_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | BSRAM_R36[15] | U_IES_Top/IES_inst/u_dp_mem/mem_mem_0_1_s/CLKB |
10.208 | -0.035 | tUnc | U_IES_Top/IES_inst/u_dp_mem/mem_mem_0_1_s | |||
9.770 | -0.438 | tSu | 1 | BSRAM_R36[15] | U_IES_Top/IES_inst/u_dp_mem/mem_mem_0_1_s |
Path Statistics:
Clock Skew | -0.683 |
Setup Relationship | 10.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Arrival Data Path Delay | cell: 0.555, 14.223%; route: 3.115, 79.832%; tC2Q: 0.232, 5.945% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path10
Path Summary:
Slack | 4.942 |
Data Arrival Time | 4.828 |
Data Required Time | 9.770 |
From | u_button/out_s0 |
To | U_IES_Top/IES_inst/u_dp_mem/mem_mem_0_1_s |
Launch Clk | clkin:[R] |
Latch Clk | esc_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clkin | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk25_ibuf/I |
0.683 | 0.683 | tINS | RR | 42 | IOT48[A] | clk25_ibuf/O |
0.926 | 0.243 | tNET | RR | 1 | R35C18[0][A] | u_button/out_s0/CLK |
1.158 | 0.232 | tC2Q | RF | 27 | R35C18[0][A] | u_button/out_s0/Q |
2.225 | 1.067 | tNET | FF | 1 | R34C42[0][A] | U_IES_Top/IES_inst/n364_s2/I0 |
2.780 | 0.555 | tINS | FF | 12187 | R34C42[0][A] | U_IES_Top/IES_inst/n364_s2/F |
4.828 | 2.048 | tNET | FF | 2 | BSRAM_R36[15] | U_IES_Top/IES_inst/u_dp_mem/mem_mem_0_1_s/RESETA |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | esc_sysclk | ||||
10.000 | 0.000 | tCL | RR | 12119 | PLL_R[0] | u_Gowin_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | BSRAM_R36[15] | U_IES_Top/IES_inst/u_dp_mem/mem_mem_0_1_s/CLKA |
10.208 | -0.035 | tUnc | U_IES_Top/IES_inst/u_dp_mem/mem_mem_0_1_s | |||
9.770 | -0.438 | tSu | 1 | BSRAM_R36[15] | U_IES_Top/IES_inst/u_dp_mem/mem_mem_0_1_s |
Path Statistics:
Clock Skew | -0.683 |
Setup Relationship | 10.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Arrival Data Path Delay | cell: 0.555, 14.223%; route: 3.115, 79.832%; tC2Q: 0.232, 5.945% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path11
Path Summary:
Slack | 4.942 |
Data Arrival Time | 4.828 |
Data Required Time | 9.770 |
From | u_button/out_s0 |
To | U_IES_Top/IES_inst/u_dp_mem/mem_mem_0_0_s |
Launch Clk | clkin:[R] |
Latch Clk | esc_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clkin | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk25_ibuf/I |
0.683 | 0.683 | tINS | RR | 42 | IOT48[A] | clk25_ibuf/O |
0.926 | 0.243 | tNET | RR | 1 | R35C18[0][A] | u_button/out_s0/CLK |
1.158 | 0.232 | tC2Q | RF | 27 | R35C18[0][A] | u_button/out_s0/Q |
2.225 | 1.067 | tNET | FF | 1 | R34C42[0][A] | U_IES_Top/IES_inst/n364_s2/I0 |
2.780 | 0.555 | tINS | FF | 12187 | R34C42[0][A] | U_IES_Top/IES_inst/n364_s2/F |
4.828 | 2.048 | tNET | FF | 2 | BSRAM_R10[8] | U_IES_Top/IES_inst/u_dp_mem/mem_mem_0_0_s/RESETB |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | esc_sysclk | ||||
10.000 | 0.000 | tCL | RR | 12119 | PLL_R[0] | u_Gowin_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | BSRAM_R10[8] | U_IES_Top/IES_inst/u_dp_mem/mem_mem_0_0_s/CLKB |
10.208 | -0.035 | tUnc | U_IES_Top/IES_inst/u_dp_mem/mem_mem_0_0_s | |||
9.770 | -0.438 | tSu | 1 | BSRAM_R10[8] | U_IES_Top/IES_inst/u_dp_mem/mem_mem_0_0_s |
Path Statistics:
Clock Skew | -0.683 |
Setup Relationship | 10.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Arrival Data Path Delay | cell: 0.555, 14.223%; route: 3.115, 79.832%; tC2Q: 0.232, 5.945% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path12
Path Summary:
Slack | 4.942 |
Data Arrival Time | 4.828 |
Data Required Time | 9.770 |
From | u_button/out_s0 |
To | U_IES_Top/IES_inst/u_dp_mem/mem_mem_0_0_s |
Launch Clk | clkin:[R] |
Latch Clk | esc_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clkin | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk25_ibuf/I |
0.683 | 0.683 | tINS | RR | 42 | IOT48[A] | clk25_ibuf/O |
0.926 | 0.243 | tNET | RR | 1 | R35C18[0][A] | u_button/out_s0/CLK |
1.158 | 0.232 | tC2Q | RF | 27 | R35C18[0][A] | u_button/out_s0/Q |
2.225 | 1.067 | tNET | FF | 1 | R34C42[0][A] | U_IES_Top/IES_inst/n364_s2/I0 |
2.780 | 0.555 | tINS | FF | 12187 | R34C42[0][A] | U_IES_Top/IES_inst/n364_s2/F |
4.828 | 2.048 | tNET | FF | 2 | BSRAM_R10[8] | U_IES_Top/IES_inst/u_dp_mem/mem_mem_0_0_s/RESETA |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | esc_sysclk | ||||
10.000 | 0.000 | tCL | RR | 12119 | PLL_R[0] | u_Gowin_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | BSRAM_R10[8] | U_IES_Top/IES_inst/u_dp_mem/mem_mem_0_0_s/CLKA |
10.208 | -0.035 | tUnc | U_IES_Top/IES_inst/u_dp_mem/mem_mem_0_0_s | |||
9.770 | -0.438 | tSu | 1 | BSRAM_R10[8] | U_IES_Top/IES_inst/u_dp_mem/mem_mem_0_0_s |
Path Statistics:
Clock Skew | -0.683 |
Setup Relationship | 10.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Arrival Data Path Delay | cell: 0.555, 14.223%; route: 3.115, 79.832%; tC2Q: 0.232, 5.945% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path13
Path Summary:
Slack | 5.330 |
Data Arrival Time | 4.844 |
Data Required Time | 10.173 |
From | u_button/out_s0 |
To | U_IES_Top/IES_inst/u_mii_enh/phy_er_cnt[1]_0_s3 |
Launch Clk | clkin:[R] |
Latch Clk | esc_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clkin | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk25_ibuf/I |
0.683 | 0.683 | tINS | RR | 42 | IOT48[A] | clk25_ibuf/O |
0.926 | 0.243 | tNET | RR | 1 | R35C18[0][A] | u_button/out_s0/CLK |
1.158 | 0.232 | tC2Q | RF | 27 | R35C18[0][A] | u_button/out_s0/Q |
2.225 | 1.067 | tNET | FF | 1 | R34C42[0][A] | U_IES_Top/IES_inst/n364_s2/I0 |
2.780 | 0.555 | tINS | FF | 12187 | R34C42[0][A] | U_IES_Top/IES_inst/n364_s2/F |
4.844 | 2.064 | tNET | FF | 1 | R16C44[1][B] | U_IES_Top/IES_inst/u_mii_enh/phy_er_cnt[1]_0_s3/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | esc_sysclk | ||||
10.000 | 0.000 | tCL | RR | 12119 | PLL_R[0] | u_Gowin_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R16C44[1][B] | U_IES_Top/IES_inst/u_mii_enh/phy_er_cnt[1]_0_s3/CLK |
10.208 | -0.035 | tUnc | U_IES_Top/IES_inst/u_mii_enh/phy_er_cnt[1]_0_s3 | |||
10.173 | -0.035 | tSu | 1 | R16C44[1][B] | U_IES_Top/IES_inst/u_mii_enh/phy_er_cnt[1]_0_s3 |
Path Statistics:
Clock Skew | -0.683 |
Setup Relationship | 10.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Arrival Data Path Delay | cell: 0.555, 14.166%; route: 3.131, 79.913%; tC2Q: 0.232, 5.922% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path14
Path Summary:
Slack | 5.330 |
Data Arrival Time | 4.844 |
Data Required Time | 10.173 |
From | u_button/out_s0 |
To | U_IES_Top/IES_inst/u_mii_enh/phy_er_cnt[1]_1_s3 |
Launch Clk | clkin:[R] |
Latch Clk | esc_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clkin | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk25_ibuf/I |
0.683 | 0.683 | tINS | RR | 42 | IOT48[A] | clk25_ibuf/O |
0.926 | 0.243 | tNET | RR | 1 | R35C18[0][A] | u_button/out_s0/CLK |
1.158 | 0.232 | tC2Q | RF | 27 | R35C18[0][A] | u_button/out_s0/Q |
2.225 | 1.067 | tNET | FF | 1 | R34C42[0][A] | U_IES_Top/IES_inst/n364_s2/I0 |
2.780 | 0.555 | tINS | FF | 12187 | R34C42[0][A] | U_IES_Top/IES_inst/n364_s2/F |
4.844 | 2.064 | tNET | FF | 1 | R16C44[2][A] | U_IES_Top/IES_inst/u_mii_enh/phy_er_cnt[1]_1_s3/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | esc_sysclk | ||||
10.000 | 0.000 | tCL | RR | 12119 | PLL_R[0] | u_Gowin_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R16C44[2][A] | U_IES_Top/IES_inst/u_mii_enh/phy_er_cnt[1]_1_s3/CLK |
10.208 | -0.035 | tUnc | U_IES_Top/IES_inst/u_mii_enh/phy_er_cnt[1]_1_s3 | |||
10.173 | -0.035 | tSu | 1 | R16C44[2][A] | U_IES_Top/IES_inst/u_mii_enh/phy_er_cnt[1]_1_s3 |
Path Statistics:
Clock Skew | -0.683 |
Setup Relationship | 10.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Arrival Data Path Delay | cell: 0.555, 14.166%; route: 3.131, 79.913%; tC2Q: 0.232, 5.922% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path15
Path Summary:
Slack | 5.330 |
Data Arrival Time | 4.844 |
Data Required Time | 10.173 |
From | u_button/out_s0 |
To | U_IES_Top/IES_inst/u_mii_enh/phy_er_cnt[1]_4_s3 |
Launch Clk | clkin:[R] |
Latch Clk | esc_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clkin | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk25_ibuf/I |
0.683 | 0.683 | tINS | RR | 42 | IOT48[A] | clk25_ibuf/O |
0.926 | 0.243 | tNET | RR | 1 | R35C18[0][A] | u_button/out_s0/CLK |
1.158 | 0.232 | tC2Q | RF | 27 | R35C18[0][A] | u_button/out_s0/Q |
2.225 | 1.067 | tNET | FF | 1 | R34C42[0][A] | U_IES_Top/IES_inst/n364_s2/I0 |
2.780 | 0.555 | tINS | FF | 12187 | R34C42[0][A] | U_IES_Top/IES_inst/n364_s2/F |
4.844 | 2.064 | tNET | FF | 1 | R15C44[2][A] | U_IES_Top/IES_inst/u_mii_enh/phy_er_cnt[1]_4_s3/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | esc_sysclk | ||||
10.000 | 0.000 | tCL | RR | 12119 | PLL_R[0] | u_Gowin_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R15C44[2][A] | U_IES_Top/IES_inst/u_mii_enh/phy_er_cnt[1]_4_s3/CLK |
10.208 | -0.035 | tUnc | U_IES_Top/IES_inst/u_mii_enh/phy_er_cnt[1]_4_s3 | |||
10.173 | -0.035 | tSu | 1 | R15C44[2][A] | U_IES_Top/IES_inst/u_mii_enh/phy_er_cnt[1]_4_s3 |
Path Statistics:
Clock Skew | -0.683 |
Setup Relationship | 10.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Arrival Data Path Delay | cell: 0.555, 14.166%; route: 3.131, 79.913%; tC2Q: 0.232, 5.922% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path16
Path Summary:
Slack | 5.330 |
Data Arrival Time | 4.844 |
Data Required Time | 10.173 |
From | u_button/out_s0 |
To | U_IES_Top/IES_inst/u_mii_enh/phy_er_cnt[1]_2_s1 |
Launch Clk | clkin:[R] |
Latch Clk | esc_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clkin | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk25_ibuf/I |
0.683 | 0.683 | tINS | RR | 42 | IOT48[A] | clk25_ibuf/O |
0.926 | 0.243 | tNET | RR | 1 | R35C18[0][A] | u_button/out_s0/CLK |
1.158 | 0.232 | tC2Q | RF | 27 | R35C18[0][A] | u_button/out_s0/Q |
2.225 | 1.067 | tNET | FF | 1 | R34C42[0][A] | U_IES_Top/IES_inst/n364_s2/I0 |
2.780 | 0.555 | tINS | FF | 12187 | R34C42[0][A] | U_IES_Top/IES_inst/n364_s2/F |
4.844 | 2.064 | tNET | FF | 1 | R16C44[0][B] | U_IES_Top/IES_inst/u_mii_enh/phy_er_cnt[1]_2_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | esc_sysclk | ||||
10.000 | 0.000 | tCL | RR | 12119 | PLL_R[0] | u_Gowin_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R16C44[0][B] | U_IES_Top/IES_inst/u_mii_enh/phy_er_cnt[1]_2_s1/CLK |
10.208 | -0.035 | tUnc | U_IES_Top/IES_inst/u_mii_enh/phy_er_cnt[1]_2_s1 | |||
10.173 | -0.035 | tSu | 1 | R16C44[0][B] | U_IES_Top/IES_inst/u_mii_enh/phy_er_cnt[1]_2_s1 |
Path Statistics:
Clock Skew | -0.683 |
Setup Relationship | 10.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Arrival Data Path Delay | cell: 0.555, 14.166%; route: 3.131, 79.913%; tC2Q: 0.232, 5.922% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path17
Path Summary:
Slack | 5.330 |
Data Arrival Time | 4.844 |
Data Required Time | 10.173 |
From | u_button/out_s0 |
To | U_IES_Top/IES_inst/u_mii_enh/phy_er_cnt[1]_3_s1 |
Launch Clk | clkin:[R] |
Latch Clk | esc_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clkin | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk25_ibuf/I |
0.683 | 0.683 | tINS | RR | 42 | IOT48[A] | clk25_ibuf/O |
0.926 | 0.243 | tNET | RR | 1 | R35C18[0][A] | u_button/out_s0/CLK |
1.158 | 0.232 | tC2Q | RF | 27 | R35C18[0][A] | u_button/out_s0/Q |
2.225 | 1.067 | tNET | FF | 1 | R34C42[0][A] | U_IES_Top/IES_inst/n364_s2/I0 |
2.780 | 0.555 | tINS | FF | 12187 | R34C42[0][A] | U_IES_Top/IES_inst/n364_s2/F |
4.844 | 2.064 | tNET | FF | 1 | R16C43[2][A] | U_IES_Top/IES_inst/u_mii_enh/phy_er_cnt[1]_3_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | esc_sysclk | ||||
10.000 | 0.000 | tCL | RR | 12119 | PLL_R[0] | u_Gowin_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R16C43[2][A] | U_IES_Top/IES_inst/u_mii_enh/phy_er_cnt[1]_3_s1/CLK |
10.208 | -0.035 | tUnc | U_IES_Top/IES_inst/u_mii_enh/phy_er_cnt[1]_3_s1 | |||
10.173 | -0.035 | tSu | 1 | R16C43[2][A] | U_IES_Top/IES_inst/u_mii_enh/phy_er_cnt[1]_3_s1 |
Path Statistics:
Clock Skew | -0.683 |
Setup Relationship | 10.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Arrival Data Path Delay | cell: 0.555, 14.166%; route: 3.131, 79.913%; tC2Q: 0.232, 5.922% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path18
Path Summary:
Slack | 5.330 |
Data Arrival Time | 4.844 |
Data Required Time | 10.173 |
From | u_button/out_s0 |
To | U_IES_Top/IES_inst/u_mii_enh/phy_er_cnt[1]_5_s1 |
Launch Clk | clkin:[R] |
Latch Clk | esc_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clkin | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk25_ibuf/I |
0.683 | 0.683 | tINS | RR | 42 | IOT48[A] | clk25_ibuf/O |
0.926 | 0.243 | tNET | RR | 1 | R35C18[0][A] | u_button/out_s0/CLK |
1.158 | 0.232 | tC2Q | RF | 27 | R35C18[0][A] | u_button/out_s0/Q |
2.225 | 1.067 | tNET | FF | 1 | R34C42[0][A] | U_IES_Top/IES_inst/n364_s2/I0 |
2.780 | 0.555 | tINS | FF | 12187 | R34C42[0][A] | U_IES_Top/IES_inst/n364_s2/F |
4.844 | 2.064 | tNET | FF | 1 | R15C43[2][B] | U_IES_Top/IES_inst/u_mii_enh/phy_er_cnt[1]_5_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | esc_sysclk | ||||
10.000 | 0.000 | tCL | RR | 12119 | PLL_R[0] | u_Gowin_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R15C43[2][B] | U_IES_Top/IES_inst/u_mii_enh/phy_er_cnt[1]_5_s1/CLK |
10.208 | -0.035 | tUnc | U_IES_Top/IES_inst/u_mii_enh/phy_er_cnt[1]_5_s1 | |||
10.173 | -0.035 | tSu | 1 | R15C43[2][B] | U_IES_Top/IES_inst/u_mii_enh/phy_er_cnt[1]_5_s1 |
Path Statistics:
Clock Skew | -0.683 |
Setup Relationship | 10.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Arrival Data Path Delay | cell: 0.555, 14.166%; route: 3.131, 79.913%; tC2Q: 0.232, 5.922% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path19
Path Summary:
Slack | 5.330 |
Data Arrival Time | 4.844 |
Data Required Time | 10.173 |
From | u_button/out_s0 |
To | U_IES_Top/IES_inst/u_mii_enh/phy_er_cnt[0]_2_s1 |
Launch Clk | clkin:[R] |
Latch Clk | esc_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clkin | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk25_ibuf/I |
0.683 | 0.683 | tINS | RR | 42 | IOT48[A] | clk25_ibuf/O |
0.926 | 0.243 | tNET | RR | 1 | R35C18[0][A] | u_button/out_s0/CLK |
1.158 | 0.232 | tC2Q | RF | 27 | R35C18[0][A] | u_button/out_s0/Q |
2.225 | 1.067 | tNET | FF | 1 | R34C42[0][A] | U_IES_Top/IES_inst/n364_s2/I0 |
2.780 | 0.555 | tINS | FF | 12187 | R34C42[0][A] | U_IES_Top/IES_inst/n364_s2/F |
4.844 | 2.064 | tNET | FF | 1 | R15C44[1][A] | U_IES_Top/IES_inst/u_mii_enh/phy_er_cnt[0]_2_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | esc_sysclk | ||||
10.000 | 0.000 | tCL | RR | 12119 | PLL_R[0] | u_Gowin_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R15C44[1][A] | U_IES_Top/IES_inst/u_mii_enh/phy_er_cnt[0]_2_s1/CLK |
10.208 | -0.035 | tUnc | U_IES_Top/IES_inst/u_mii_enh/phy_er_cnt[0]_2_s1 | |||
10.173 | -0.035 | tSu | 1 | R15C44[1][A] | U_IES_Top/IES_inst/u_mii_enh/phy_er_cnt[0]_2_s1 |
Path Statistics:
Clock Skew | -0.683 |
Setup Relationship | 10.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Arrival Data Path Delay | cell: 0.555, 14.166%; route: 3.131, 79.913%; tC2Q: 0.232, 5.922% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path20
Path Summary:
Slack | 5.330 |
Data Arrival Time | 4.844 |
Data Required Time | 10.173 |
From | u_button/out_s0 |
To | U_IES_Top/IES_inst/u_mii_enh/enh_cnt_9_s0 |
Launch Clk | clkin:[R] |
Latch Clk | esc_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clkin | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk25_ibuf/I |
0.683 | 0.683 | tINS | RR | 42 | IOT48[A] | clk25_ibuf/O |
0.926 | 0.243 | tNET | RR | 1 | R35C18[0][A] | u_button/out_s0/CLK |
1.158 | 0.232 | tC2Q | RF | 27 | R35C18[0][A] | u_button/out_s0/Q |
2.225 | 1.067 | tNET | FF | 1 | R34C42[0][A] | U_IES_Top/IES_inst/n364_s2/I0 |
2.780 | 0.555 | tINS | FF | 12187 | R34C42[0][A] | U_IES_Top/IES_inst/n364_s2/F |
4.844 | 2.064 | tNET | FF | 1 | R16C43[1][B] | U_IES_Top/IES_inst/u_mii_enh/enh_cnt_9_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | esc_sysclk | ||||
10.000 | 0.000 | tCL | RR | 12119 | PLL_R[0] | u_Gowin_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R16C43[1][B] | U_IES_Top/IES_inst/u_mii_enh/enh_cnt_9_s0/CLK |
10.208 | -0.035 | tUnc | U_IES_Top/IES_inst/u_mii_enh/enh_cnt_9_s0 | |||
10.173 | -0.035 | tSu | 1 | R16C43[1][B] | U_IES_Top/IES_inst/u_mii_enh/enh_cnt_9_s0 |
Path Statistics:
Clock Skew | -0.683 |
Setup Relationship | 10.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Arrival Data Path Delay | cell: 0.555, 14.166%; route: 3.131, 79.913%; tC2Q: 0.232, 5.922% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path21
Path Summary:
Slack | 5.330 |
Data Arrival Time | 4.844 |
Data Required Time | 10.173 |
From | u_button/out_s0 |
To | U_IES_Top/IES_inst/u_mii_enh/enh_link_err_int_1_s0 |
Launch Clk | clkin:[R] |
Latch Clk | esc_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clkin | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk25_ibuf/I |
0.683 | 0.683 | tINS | RR | 42 | IOT48[A] | clk25_ibuf/O |
0.926 | 0.243 | tNET | RR | 1 | R35C18[0][A] | u_button/out_s0/CLK |
1.158 | 0.232 | tC2Q | RF | 27 | R35C18[0][A] | u_button/out_s0/Q |
2.225 | 1.067 | tNET | FF | 1 | R34C42[0][A] | U_IES_Top/IES_inst/n364_s2/I0 |
2.780 | 0.555 | tINS | FF | 12187 | R34C42[0][A] | U_IES_Top/IES_inst/n364_s2/F |
4.844 | 2.064 | tNET | FF | 1 | R16C43[0][A] | U_IES_Top/IES_inst/u_mii_enh/enh_link_err_int_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | esc_sysclk | ||||
10.000 | 0.000 | tCL | RR | 12119 | PLL_R[0] | u_Gowin_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R16C43[0][A] | U_IES_Top/IES_inst/u_mii_enh/enh_link_err_int_1_s0/CLK |
10.208 | -0.035 | tUnc | U_IES_Top/IES_inst/u_mii_enh/enh_link_err_int_1_s0 | |||
10.173 | -0.035 | tSu | 1 | R16C43[0][A] | U_IES_Top/IES_inst/u_mii_enh/enh_link_err_int_1_s0 |
Path Statistics:
Clock Skew | -0.683 |
Setup Relationship | 10.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Arrival Data Path Delay | cell: 0.555, 14.166%; route: 3.131, 79.913%; tC2Q: 0.232, 5.922% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path22
Path Summary:
Slack | 5.330 |
Data Arrival Time | 4.844 |
Data Required Time | 10.173 |
From | u_button/out_s0 |
To | U_IES_Top/IES_inst/u_mii_enh/enh_link_err_int_0_s0 |
Launch Clk | clkin:[R] |
Latch Clk | esc_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clkin | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk25_ibuf/I |
0.683 | 0.683 | tINS | RR | 42 | IOT48[A] | clk25_ibuf/O |
0.926 | 0.243 | tNET | RR | 1 | R35C18[0][A] | u_button/out_s0/CLK |
1.158 | 0.232 | tC2Q | RF | 27 | R35C18[0][A] | u_button/out_s0/Q |
2.225 | 1.067 | tNET | FF | 1 | R34C42[0][A] | U_IES_Top/IES_inst/n364_s2/I0 |
2.780 | 0.555 | tINS | FF | 12187 | R34C42[0][A] | U_IES_Top/IES_inst/n364_s2/F |
4.844 | 2.064 | tNET | FF | 1 | R15C44[2][B] | U_IES_Top/IES_inst/u_mii_enh/enh_link_err_int_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | esc_sysclk | ||||
10.000 | 0.000 | tCL | RR | 12119 | PLL_R[0] | u_Gowin_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R15C44[2][B] | U_IES_Top/IES_inst/u_mii_enh/enh_link_err_int_0_s0/CLK |
10.208 | -0.035 | tUnc | U_IES_Top/IES_inst/u_mii_enh/enh_link_err_int_0_s0 | |||
10.173 | -0.035 | tSu | 1 | R15C44[2][B] | U_IES_Top/IES_inst/u_mii_enh/enh_link_err_int_0_s0 |
Path Statistics:
Clock Skew | -0.683 |
Setup Relationship | 10.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Arrival Data Path Delay | cell: 0.555, 14.166%; route: 3.131, 79.913%; tC2Q: 0.232, 5.922% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path23
Path Summary:
Slack | 5.330 |
Data Arrival Time | 4.844 |
Data Required Time | 10.173 |
From | u_button/out_s0 |
To | U_IES_Top/IES_inst/u_mii_enh/mii_link_rr_0_s0 |
Launch Clk | clkin:[R] |
Latch Clk | esc_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clkin | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk25_ibuf/I |
0.683 | 0.683 | tINS | RR | 42 | IOT48[A] | clk25_ibuf/O |
0.926 | 0.243 | tNET | RR | 1 | R35C18[0][A] | u_button/out_s0/CLK |
1.158 | 0.232 | tC2Q | RF | 27 | R35C18[0][A] | u_button/out_s0/Q |
2.225 | 1.067 | tNET | FF | 1 | R34C42[0][A] | U_IES_Top/IES_inst/n364_s2/I0 |
2.780 | 0.555 | tINS | FF | 12187 | R34C42[0][A] | U_IES_Top/IES_inst/n364_s2/F |
4.844 | 2.064 | tNET | FF | 1 | R13C44[2][A] | U_IES_Top/IES_inst/u_mii_enh/mii_link_rr_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | esc_sysclk | ||||
10.000 | 0.000 | tCL | RR | 12119 | PLL_R[0] | u_Gowin_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R13C44[2][A] | U_IES_Top/IES_inst/u_mii_enh/mii_link_rr_0_s0/CLK |
10.208 | -0.035 | tUnc | U_IES_Top/IES_inst/u_mii_enh/mii_link_rr_0_s0 | |||
10.173 | -0.035 | tSu | 1 | R13C44[2][A] | U_IES_Top/IES_inst/u_mii_enh/mii_link_rr_0_s0 |
Path Statistics:
Clock Skew | -0.683 |
Setup Relationship | 10.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Arrival Data Path Delay | cell: 0.555, 14.166%; route: 3.131, 79.913%; tC2Q: 0.232, 5.922% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path24
Path Summary:
Slack | 5.330 |
Data Arrival Time | 4.844 |
Data Required Time | 10.173 |
From | u_button/out_s0 |
To | U_IES_Top/IES_inst/u_mii_enh/mii_link_rr_1_s0 |
Launch Clk | clkin:[R] |
Latch Clk | esc_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clkin | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk25_ibuf/I |
0.683 | 0.683 | tINS | RR | 42 | IOT48[A] | clk25_ibuf/O |
0.926 | 0.243 | tNET | RR | 1 | R35C18[0][A] | u_button/out_s0/CLK |
1.158 | 0.232 | tC2Q | RF | 27 | R35C18[0][A] | u_button/out_s0/Q |
2.225 | 1.067 | tNET | FF | 1 | R34C42[0][A] | U_IES_Top/IES_inst/n364_s2/I0 |
2.780 | 0.555 | tINS | FF | 12187 | R34C42[0][A] | U_IES_Top/IES_inst/n364_s2/F |
4.844 | 2.064 | tNET | FF | 1 | R9C42[1][B] | U_IES_Top/IES_inst/u_mii_enh/mii_link_rr_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | esc_sysclk | ||||
10.000 | 0.000 | tCL | RR | 12119 | PLL_R[0] | u_Gowin_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R9C42[1][B] | U_IES_Top/IES_inst/u_mii_enh/mii_link_rr_1_s0/CLK |
10.208 | -0.035 | tUnc | U_IES_Top/IES_inst/u_mii_enh/mii_link_rr_1_s0 | |||
10.173 | -0.035 | tSu | 1 | R9C42[1][B] | U_IES_Top/IES_inst/u_mii_enh/mii_link_rr_1_s0 |
Path Statistics:
Clock Skew | -0.683 |
Setup Relationship | 10.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Arrival Data Path Delay | cell: 0.555, 14.166%; route: 3.131, 79.913%; tC2Q: 0.232, 5.922% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path25
Path Summary:
Slack | 5.330 |
Data Arrival Time | 4.844 |
Data Required Time | 10.173 |
From | u_button/out_s0 |
To | U_IES_Top/IES_inst/u_mii_enh/p_10us_s0 |
Launch Clk | clkin:[R] |
Latch Clk | esc_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clkin | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk25_ibuf/I |
0.683 | 0.683 | tINS | RR | 42 | IOT48[A] | clk25_ibuf/O |
0.926 | 0.243 | tNET | RR | 1 | R35C18[0][A] | u_button/out_s0/CLK |
1.158 | 0.232 | tC2Q | RF | 27 | R35C18[0][A] | u_button/out_s0/Q |
2.225 | 1.067 | tNET | FF | 1 | R34C42[0][A] | U_IES_Top/IES_inst/n364_s2/I0 |
2.780 | 0.555 | tINS | FF | 12187 | R34C42[0][A] | U_IES_Top/IES_inst/n364_s2/F |
4.844 | 2.064 | tNET | FF | 1 | R15C44[0][A] | U_IES_Top/IES_inst/u_mii_enh/p_10us_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | esc_sysclk | ||||
10.000 | 0.000 | tCL | RR | 12119 | PLL_R[0] | u_Gowin_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R15C44[0][A] | U_IES_Top/IES_inst/u_mii_enh/p_10us_s0/CLK |
10.208 | -0.035 | tUnc | U_IES_Top/IES_inst/u_mii_enh/p_10us_s0 | |||
10.173 | -0.035 | tSu | 1 | R15C44[0][A] | U_IES_Top/IES_inst/u_mii_enh/p_10us_s0 |
Path Statistics:
Clock Skew | -0.683 |
Setup Relationship | 10.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Arrival Data Path Delay | cell: 0.555, 14.166%; route: 3.131, 79.913%; tC2Q: 0.232, 5.922% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Removal Analysis Report
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 1.199 |
Data Arrival Time | 1.394 |
Data Required Time | 0.195 |
From | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/sysRstGen_3_s0 |
To | U_IES_Top/IES_inst/u_AHB/rstn_reg1_s0 |
Launch Clk | mcu_sysclk:[R] |
Latch Clk | mcu_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | mcu_sysclk | ||||
0.000 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R50C5[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 3 | R50C5[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q |
1.394 | 1.008 | tNET | RR | 1 | R26C18[1][B] | U_IES_Top/IES_inst/u_AHB/rstn_reg1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | mcu_sysclk | ||||
0.000 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R26C18[1][B] | U_IES_Top/IES_inst/u_AHB/rstn_reg1_s0/CLK |
0.195 | 0.011 | tHld | 1 | R26C18[1][B] | U_IES_Top/IES_inst/u_AHB/rstn_reg1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.008, 83.304%; tC2Q: 0.202, 16.696% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path2
Path Summary:
Slack | 1.199 |
Data Arrival Time | 1.394 |
Data Required Time | 0.195 |
From | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/sysRstGen_3_s0 |
To | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0 |
Launch Clk | mcu_sysclk:[R] |
Latch Clk | mcu_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | mcu_sysclk | ||||
0.000 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R50C5[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 3 | R50C5[1][A] | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q |
1.394 | 1.008 | tNET | RR | 1 | R26C18[1][A] | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | mcu_sysclk | ||||
0.000 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R26C18[1][A] | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0/CLK |
0.195 | 0.011 | tHld | 1 | R26C18[1][A] | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.008, 83.304%; tC2Q: 0.202, 16.696% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path3
Path Summary:
Slack | 1.659 |
Data Arrival Time | 1.854 |
Data Required Time | 0.195 |
From | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0 |
To | U_IES_Top/IES_inst/u_AHB/c_state.TRANS_TYPE_s4 |
Launch Clk | mcu_sysclk:[R] |
Latch Clk | mcu_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | mcu_sysclk | ||||
0.000 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R26C18[1][A] | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 310 | R26C18[1][A] | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0/Q |
1.854 | 1.468 | tNET | RR | 1 | R25C18[1][A] | U_IES_Top/IES_inst/u_AHB/c_state.TRANS_TYPE_s4/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | mcu_sysclk | ||||
0.000 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R25C18[1][A] | U_IES_Top/IES_inst/u_AHB/c_state.TRANS_TYPE_s4/CLK |
0.195 | 0.011 | tHld | 1 | R25C18[1][A] | U_IES_Top/IES_inst/u_AHB/c_state.TRANS_TYPE_s4 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.468, 87.904%; tC2Q: 0.202, 12.096% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path4
Path Summary:
Slack | 1.659 |
Data Arrival Time | 1.854 |
Data Required Time | 0.195 |
From | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0 |
To | U_IES_Top/IES_inst/u_AHB/rd_finished_tmp_s5 |
Launch Clk | mcu_sysclk:[R] |
Latch Clk | mcu_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | mcu_sysclk | ||||
0.000 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R26C18[1][A] | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 310 | R26C18[1][A] | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0/Q |
1.854 | 1.468 | tNET | RR | 1 | R26C18[2][A] | U_IES_Top/IES_inst/u_AHB/rd_finished_tmp_s5/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | mcu_sysclk | ||||
0.000 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R26C18[2][A] | U_IES_Top/IES_inst/u_AHB/rd_finished_tmp_s5/CLK |
0.195 | 0.011 | tHld | 1 | R26C18[2][A] | U_IES_Top/IES_inst/u_AHB/rd_finished_tmp_s5 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.468, 87.904%; tC2Q: 0.202, 12.096% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path5
Path Summary:
Slack | 1.659 |
Data Arrival Time | 1.854 |
Data Required Time | 0.195 |
From | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0 |
To | U_IES_Top/IES_inst/u_AHB/wr_finished_tmp_s6 |
Launch Clk | mcu_sysclk:[R] |
Latch Clk | mcu_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | mcu_sysclk | ||||
0.000 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R26C18[1][A] | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 310 | R26C18[1][A] | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0/Q |
1.854 | 1.468 | tNET | RR | 1 | R25C18[1][B] | U_IES_Top/IES_inst/u_AHB/wr_finished_tmp_s6/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | mcu_sysclk | ||||
0.000 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R25C18[1][B] | U_IES_Top/IES_inst/u_AHB/wr_finished_tmp_s6/CLK |
0.195 | 0.011 | tHld | 1 | R25C18[1][B] | U_IES_Top/IES_inst/u_AHB/wr_finished_tmp_s6 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.468, 87.904%; tC2Q: 0.202, 12.096% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path6
Path Summary:
Slack | 1.659 |
Data Arrival Time | 1.854 |
Data Required Time | 0.195 |
From | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0 |
To | U_IES_Top/IES_inst/u_AHB/beat_cnt_0_s3 |
Launch Clk | mcu_sysclk:[R] |
Latch Clk | mcu_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | mcu_sysclk | ||||
0.000 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R26C18[1][A] | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 310 | R26C18[1][A] | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0/Q |
1.854 | 1.468 | tNET | RR | 1 | R17C18[0][A] | U_IES_Top/IES_inst/u_AHB/beat_cnt_0_s3/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | mcu_sysclk | ||||
0.000 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R17C18[0][A] | U_IES_Top/IES_inst/u_AHB/beat_cnt_0_s3/CLK |
0.195 | 0.011 | tHld | 1 | R17C18[0][A] | U_IES_Top/IES_inst/u_AHB/beat_cnt_0_s3 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.468, 87.904%; tC2Q: 0.202, 12.096% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path7
Path Summary:
Slack | 1.659 |
Data Arrival Time | 1.854 |
Data Required Time | 0.195 |
From | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0 |
To | U_IES_Top/IES_inst/u_AHB/axi_rready_reg1_s5 |
Launch Clk | mcu_sysclk:[R] |
Latch Clk | mcu_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | mcu_sysclk | ||||
0.000 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R26C18[1][A] | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 310 | R26C18[1][A] | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0/Q |
1.854 | 1.468 | tNET | RR | 1 | R32C21[1][A] | U_IES_Top/IES_inst/u_AHB/axi_rready_reg1_s5/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | mcu_sysclk | ||||
0.000 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R32C21[1][A] | U_IES_Top/IES_inst/u_AHB/axi_rready_reg1_s5/CLK |
0.195 | 0.011 | tHld | 1 | R32C21[1][A] | U_IES_Top/IES_inst/u_AHB/axi_rready_reg1_s5 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.468, 87.904%; tC2Q: 0.202, 12.096% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path8
Path Summary:
Slack | 1.659 |
Data Arrival Time | 1.854 |
Data Required Time | 0.195 |
From | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0 |
To | U_IES_Top/IES_inst/u_AHB/axi_wstrb_1_s3 |
Launch Clk | mcu_sysclk:[R] |
Latch Clk | mcu_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | mcu_sysclk | ||||
0.000 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R26C18[1][A] | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 310 | R26C18[1][A] | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0/Q |
1.854 | 1.468 | tNET | RR | 1 | R23C19[0][A] | U_IES_Top/IES_inst/u_AHB/axi_wstrb_1_s3/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | mcu_sysclk | ||||
0.000 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R23C19[0][A] | U_IES_Top/IES_inst/u_AHB/axi_wstrb_1_s3/CLK |
0.195 | 0.011 | tHld | 1 | R23C19[0][A] | U_IES_Top/IES_inst/u_AHB/axi_wstrb_1_s3 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.468, 87.904%; tC2Q: 0.202, 12.096% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path9
Path Summary:
Slack | 1.659 |
Data Arrival Time | 1.854 |
Data Required Time | 0.195 |
From | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0 |
To | U_IES_Top/IES_inst/u_AHB/axi_wstrb_3_s3 |
Launch Clk | mcu_sysclk:[R] |
Latch Clk | mcu_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | mcu_sysclk | ||||
0.000 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R26C18[1][A] | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 310 | R26C18[1][A] | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0/Q |
1.854 | 1.468 | tNET | RR | 1 | R23C19[0][B] | U_IES_Top/IES_inst/u_AHB/axi_wstrb_3_s3/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | mcu_sysclk | ||||
0.000 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R23C19[0][B] | U_IES_Top/IES_inst/u_AHB/axi_wstrb_3_s3/CLK |
0.195 | 0.011 | tHld | 1 | R23C19[0][B] | U_IES_Top/IES_inst/u_AHB/axi_wstrb_3_s3 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.468, 87.904%; tC2Q: 0.202, 12.096% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path10
Path Summary:
Slack | 1.659 |
Data Arrival Time | 1.854 |
Data Required Time | 0.195 |
From | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0 |
To | U_IES_Top/IES_inst/u_AHB/axi_wvalid_reg1_s5 |
Launch Clk | mcu_sysclk:[R] |
Latch Clk | mcu_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | mcu_sysclk | ||||
0.000 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R26C18[1][A] | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 310 | R26C18[1][A] | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0/Q |
1.854 | 1.468 | tNET | RR | 1 | R37C21[1][B] | U_IES_Top/IES_inst/u_AHB/axi_wvalid_reg1_s5/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | mcu_sysclk | ||||
0.000 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R37C21[1][B] | U_IES_Top/IES_inst/u_AHB/axi_wvalid_reg1_s5/CLK |
0.195 | 0.011 | tHld | 1 | R37C21[1][B] | U_IES_Top/IES_inst/u_AHB/axi_wvalid_reg1_s5 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.468, 87.904%; tC2Q: 0.202, 12.096% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path11
Path Summary:
Slack | 1.659 |
Data Arrival Time | 1.854 |
Data Required Time | 0.195 |
From | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0 |
To | U_IES_Top/IES_inst/u_AHB/axi_arvalid_reg1_s5 |
Launch Clk | mcu_sysclk:[R] |
Latch Clk | mcu_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | mcu_sysclk | ||||
0.000 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R26C18[1][A] | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 310 | R26C18[1][A] | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0/Q |
1.854 | 1.468 | tNET | RR | 1 | R25C21[1][A] | U_IES_Top/IES_inst/u_AHB/axi_arvalid_reg1_s5/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | mcu_sysclk | ||||
0.000 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R25C21[1][A] | U_IES_Top/IES_inst/u_AHB/axi_arvalid_reg1_s5/CLK |
0.195 | 0.011 | tHld | 1 | R25C21[1][A] | U_IES_Top/IES_inst/u_AHB/axi_arvalid_reg1_s5 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.468, 87.904%; tC2Q: 0.202, 12.096% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path12
Path Summary:
Slack | 1.659 |
Data Arrival Time | 1.854 |
Data Required Time | 0.195 |
From | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0 |
To | U_IES_Top/IES_inst/u_AHB/axi_awvalid_reg1_s7 |
Launch Clk | mcu_sysclk:[R] |
Latch Clk | mcu_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | mcu_sysclk | ||||
0.000 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R26C18[1][A] | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 310 | R26C18[1][A] | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0/Q |
1.854 | 1.468 | tNET | RR | 1 | R26C21[1][A] | U_IES_Top/IES_inst/u_AHB/axi_awvalid_reg1_s7/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | mcu_sysclk | ||||
0.000 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R26C21[1][A] | U_IES_Top/IES_inst/u_AHB/axi_awvalid_reg1_s7/CLK |
0.195 | 0.011 | tHld | 1 | R26C21[1][A] | U_IES_Top/IES_inst/u_AHB/axi_awvalid_reg1_s7 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.468, 87.904%; tC2Q: 0.202, 12.096% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path13
Path Summary:
Slack | 1.659 |
Data Arrival Time | 1.854 |
Data Required Time | 0.195 |
From | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0 |
To | U_IES_Top/IES_inst/u_AHB/c_state.IDLE_s1 |
Launch Clk | mcu_sysclk:[R] |
Latch Clk | mcu_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | mcu_sysclk | ||||
0.000 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R26C18[1][A] | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 310 | R26C18[1][A] | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0/Q |
1.854 | 1.468 | tNET | RR | 1 | R25C18[0][A] | U_IES_Top/IES_inst/u_AHB/c_state.IDLE_s1/PRESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | mcu_sysclk | ||||
0.000 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R25C18[0][A] | U_IES_Top/IES_inst/u_AHB/c_state.IDLE_s1/CLK |
0.195 | 0.011 | tHld | 1 | R25C18[0][A] | U_IES_Top/IES_inst/u_AHB/c_state.IDLE_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.468, 87.904%; tC2Q: 0.202, 12.096% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path14
Path Summary:
Slack | 1.659 |
Data Arrival Time | 1.854 |
Data Required Time | 0.195 |
From | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0 |
To | U_IES_Top/IES_inst/u_AHB/c_state.SAVE_CTRL_s1 |
Launch Clk | mcu_sysclk:[R] |
Latch Clk | mcu_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | mcu_sysclk | ||||
0.000 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R26C18[1][A] | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 310 | R26C18[1][A] | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0/Q |
1.854 | 1.468 | tNET | RR | 1 | R24C18[1][A] | U_IES_Top/IES_inst/u_AHB/c_state.SAVE_CTRL_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | mcu_sysclk | ||||
0.000 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R24C18[1][A] | U_IES_Top/IES_inst/u_AHB/c_state.SAVE_CTRL_s1/CLK |
0.195 | 0.011 | tHld | 1 | R24C18[1][A] | U_IES_Top/IES_inst/u_AHB/c_state.SAVE_CTRL_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.468, 87.904%; tC2Q: 0.202, 12.096% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path15
Path Summary:
Slack | 1.659 |
Data Arrival Time | 1.854 |
Data Required Time | 0.195 |
From | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0 |
To | U_IES_Top/IES_inst/u_AHB/c_state.SR_SM_s1 |
Launch Clk | mcu_sysclk:[R] |
Latch Clk | mcu_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | mcu_sysclk | ||||
0.000 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R26C18[1][A] | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 310 | R26C18[1][A] | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0/Q |
1.854 | 1.468 | tNET | RR | 1 | R23C18[1][A] | U_IES_Top/IES_inst/u_AHB/c_state.SR_SM_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | mcu_sysclk | ||||
0.000 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R23C18[1][A] | U_IES_Top/IES_inst/u_AHB/c_state.SR_SM_s1/CLK |
0.195 | 0.011 | tHld | 1 | R23C18[1][A] | U_IES_Top/IES_inst/u_AHB/c_state.SR_SM_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.468, 87.904%; tC2Q: 0.202, 12.096% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path16
Path Summary:
Slack | 1.659 |
Data Arrival Time | 1.854 |
Data Required Time | 0.195 |
From | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0 |
To | U_IES_Top/IES_inst/u_AHB/rd_finished_pulse_reg1_s1 |
Launch Clk | mcu_sysclk:[R] |
Latch Clk | mcu_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | mcu_sysclk | ||||
0.000 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R26C18[1][A] | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 310 | R26C18[1][A] | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0/Q |
1.854 | 1.468 | tNET | RR | 1 | R25C21[2][A] | U_IES_Top/IES_inst/u_AHB/rd_finished_pulse_reg1_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | mcu_sysclk | ||||
0.000 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R25C21[2][A] | U_IES_Top/IES_inst/u_AHB/rd_finished_pulse_reg1_s1/CLK |
0.195 | 0.011 | tHld | 1 | R25C21[2][A] | U_IES_Top/IES_inst/u_AHB/rd_finished_pulse_reg1_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.468, 87.904%; tC2Q: 0.202, 12.096% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path17
Path Summary:
Slack | 1.659 |
Data Arrival Time | 1.854 |
Data Required Time | 0.195 |
From | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0 |
To | U_IES_Top/IES_inst/u_AHB/wr_finished_pulse_reg1_s1 |
Launch Clk | mcu_sysclk:[R] |
Latch Clk | mcu_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | mcu_sysclk | ||||
0.000 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R26C18[1][A] | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 310 | R26C18[1][A] | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0/Q |
1.854 | 1.468 | tNET | RR | 1 | R26C21[2][A] | U_IES_Top/IES_inst/u_AHB/wr_finished_pulse_reg1_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | mcu_sysclk | ||||
0.000 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R26C21[2][A] | U_IES_Top/IES_inst/u_AHB/wr_finished_pulse_reg1_s1/CLK |
0.195 | 0.011 | tHld | 1 | R26C21[2][A] | U_IES_Top/IES_inst/u_AHB/wr_finished_pulse_reg1_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.468, 87.904%; tC2Q: 0.202, 12.096% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path18
Path Summary:
Slack | 1.659 |
Data Arrival Time | 1.854 |
Data Required Time | 0.195 |
From | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0 |
To | U_IES_Top/IES_inst/u_AHB/beat_cnt_1_s1 |
Launch Clk | mcu_sysclk:[R] |
Latch Clk | mcu_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | mcu_sysclk | ||||
0.000 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R26C18[1][A] | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 310 | R26C18[1][A] | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0/Q |
1.854 | 1.468 | tNET | RR | 1 | R22C19[1][A] | U_IES_Top/IES_inst/u_AHB/beat_cnt_1_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | mcu_sysclk | ||||
0.000 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R22C19[1][A] | U_IES_Top/IES_inst/u_AHB/beat_cnt_1_s1/CLK |
0.195 | 0.011 | tHld | 1 | R22C19[1][A] | U_IES_Top/IES_inst/u_AHB/beat_cnt_1_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.468, 87.904%; tC2Q: 0.202, 12.096% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path19
Path Summary:
Slack | 1.659 |
Data Arrival Time | 1.854 |
Data Required Time | 0.195 |
From | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0 |
To | U_IES_Top/IES_inst/u_AHB/beat_cnt_2_s1 |
Launch Clk | mcu_sysclk:[R] |
Latch Clk | mcu_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | mcu_sysclk | ||||
0.000 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R26C18[1][A] | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 310 | R26C18[1][A] | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0/Q |
1.854 | 1.468 | tNET | RR | 1 | R22C19[1][B] | U_IES_Top/IES_inst/u_AHB/beat_cnt_2_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | mcu_sysclk | ||||
0.000 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R22C19[1][B] | U_IES_Top/IES_inst/u_AHB/beat_cnt_2_s1/CLK |
0.195 | 0.011 | tHld | 1 | R22C19[1][B] | U_IES_Top/IES_inst/u_AHB/beat_cnt_2_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.468, 87.904%; tC2Q: 0.202, 12.096% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path20
Path Summary:
Slack | 1.659 |
Data Arrival Time | 1.854 |
Data Required Time | 0.195 |
From | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0 |
To | U_IES_Top/IES_inst/u_AHB/beat_cnt_3_s1 |
Launch Clk | mcu_sysclk:[R] |
Latch Clk | mcu_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | mcu_sysclk | ||||
0.000 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R26C18[1][A] | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 310 | R26C18[1][A] | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0/Q |
1.854 | 1.468 | tNET | RR | 1 | R20C19[1][A] | U_IES_Top/IES_inst/u_AHB/beat_cnt_3_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | mcu_sysclk | ||||
0.000 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R20C19[1][A] | U_IES_Top/IES_inst/u_AHB/beat_cnt_3_s1/CLK |
0.195 | 0.011 | tHld | 1 | R20C19[1][A] | U_IES_Top/IES_inst/u_AHB/beat_cnt_3_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.468, 87.904%; tC2Q: 0.202, 12.096% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path21
Path Summary:
Slack | 1.659 |
Data Arrival Time | 1.854 |
Data Required Time | 0.195 |
From | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0 |
To | U_IES_Top/IES_inst/u_AHB/beat_cnt_4_s1 |
Launch Clk | mcu_sysclk:[R] |
Latch Clk | mcu_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | mcu_sysclk | ||||
0.000 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R26C18[1][A] | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 310 | R26C18[1][A] | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0/Q |
1.854 | 1.468 | tNET | RR | 1 | R20C20[0][A] | U_IES_Top/IES_inst/u_AHB/beat_cnt_4_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | mcu_sysclk | ||||
0.000 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R20C20[0][A] | U_IES_Top/IES_inst/u_AHB/beat_cnt_4_s1/CLK |
0.195 | 0.011 | tHld | 1 | R20C20[0][A] | U_IES_Top/IES_inst/u_AHB/beat_cnt_4_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.468, 87.904%; tC2Q: 0.202, 12.096% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path22
Path Summary:
Slack | 1.659 |
Data Arrival Time | 1.854 |
Data Required Time | 0.195 |
From | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0 |
To | U_IES_Top/IES_inst/u_AHB/sr_finished_tmp_s1 |
Launch Clk | mcu_sysclk:[R] |
Latch Clk | mcu_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | mcu_sysclk | ||||
0.000 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R26C18[1][A] | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 310 | R26C18[1][A] | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0/Q |
1.854 | 1.468 | tNET | RR | 1 | R23C19[1][A] | U_IES_Top/IES_inst/u_AHB/sr_finished_tmp_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | mcu_sysclk | ||||
0.000 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R23C19[1][A] | U_IES_Top/IES_inst/u_AHB/sr_finished_tmp_s1/CLK |
0.195 | 0.011 | tHld | 1 | R23C19[1][A] | U_IES_Top/IES_inst/u_AHB/sr_finished_tmp_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.468, 87.904%; tC2Q: 0.202, 12.096% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path23
Path Summary:
Slack | 1.659 |
Data Arrival Time | 1.854 |
Data Required Time | 0.195 |
From | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0 |
To | U_IES_Top/IES_inst/u_AHB/release_busy_s1 |
Launch Clk | mcu_sysclk:[R] |
Latch Clk | mcu_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | mcu_sysclk | ||||
0.000 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R26C18[1][A] | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 310 | R26C18[1][A] | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0/Q |
1.854 | 1.468 | tNET | RR | 1 | R23C19[2][A] | U_IES_Top/IES_inst/u_AHB/release_busy_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | mcu_sysclk | ||||
0.000 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R23C19[2][A] | U_IES_Top/IES_inst/u_AHB/release_busy_s1/CLK |
0.195 | 0.011 | tHld | 1 | R23C19[2][A] | U_IES_Top/IES_inst/u_AHB/release_busy_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.468, 87.904%; tC2Q: 0.202, 12.096% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path24
Path Summary:
Slack | 1.659 |
Data Arrival Time | 1.854 |
Data Required Time | 0.195 |
From | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0 |
To | U_IES_Top/IES_inst/u_AHB/access_end_reg2_s0 |
Launch Clk | mcu_sysclk:[R] |
Latch Clk | mcu_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | mcu_sysclk | ||||
0.000 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R26C18[1][A] | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 310 | R26C18[1][A] | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0/Q |
1.854 | 1.468 | tNET | RR | 1 | R21C18[1][B] | U_IES_Top/IES_inst/u_AHB/access_end_reg2_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | mcu_sysclk | ||||
0.000 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R21C18[1][B] | U_IES_Top/IES_inst/u_AHB/access_end_reg2_s0/CLK |
0.195 | 0.011 | tHld | 1 | R21C18[1][B] | U_IES_Top/IES_inst/u_AHB/access_end_reg2_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.468, 87.904%; tC2Q: 0.202, 12.096% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path25
Path Summary:
Slack | 1.659 |
Data Arrival Time | 1.854 |
Data Required Time | 0.195 |
From | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0 |
To | U_IES_Top/IES_inst/u_AHB/rd_finished_pulse_reg2_s0 |
Launch Clk | mcu_sysclk:[R] |
Latch Clk | mcu_sysclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | mcu_sysclk | ||||
0.000 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R26C18[1][A] | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 310 | R26C18[1][A] | U_IES_Top/IES_inst/u_AHB/rstn_reg2_s0/Q |
1.854 | 1.468 | tNET | RR | 1 | R25C23[0][A] | U_IES_Top/IES_inst/u_AHB/rd_finished_pulse_reg2_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | mcu_sysclk | ||||
0.000 | 0.000 | tCL | RR | 1747 | PLL_L[0] | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R25C23[0][A] | U_IES_Top/IES_inst/u_AHB/rd_finished_pulse_reg2_s0/CLK |
0.195 | 0.011 | tHld | 1 | R25C23[0][A] | U_IES_Top/IES_inst/u_AHB/rd_finished_pulse_reg2_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.468, 87.904%; tC2Q: 0.202, 12.096% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Minimum Pulse Width Report:
Report Command:report_min_pulse_width -nworst 10 -detail
MPW1
MPW Summary:
Slack: | 3.923 |
Actual Width: | 4.923 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | esc_sysclk |
Objects: | U_IES_Top/IES_inst/mii_link_0_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | esc_sysclk | ||
5.000 | 0.000 | tCL | FF | u_Gowin_rPLL/rpll_inst/CLKOUT |
5.261 | 0.261 | tNET | FF | U_IES_Top/IES_inst/mii_link_0_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | esc_sysclk | ||
10.000 | 0.000 | tCL | RR | u_Gowin_rPLL/rpll_inst/CLKOUT |
10.184 | 0.184 | tNET | RR | U_IES_Top/IES_inst/mii_link_0_s0/CLK |
MPW2
MPW Summary:
Slack: | 3.923 |
Actual Width: | 4.923 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | esc_sysclk |
Objects: | U_IES_Top/IES_inst/u_rx_top/u_mii_rx_0/offset_tmp_7_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | esc_sysclk | ||
5.000 | 0.000 | tCL | FF | u_Gowin_rPLL/rpll_inst/CLKOUT |
5.261 | 0.261 | tNET | FF | U_IES_Top/IES_inst/u_rx_top/u_mii_rx_0/offset_tmp_7_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | esc_sysclk | ||
10.000 | 0.000 | tCL | RR | u_Gowin_rPLL/rpll_inst/CLKOUT |
10.184 | 0.184 | tNET | RR | U_IES_Top/IES_inst/u_rx_top/u_mii_rx_0/offset_tmp_7_s0/CLK |
MPW3
MPW Summary:
Slack: | 3.923 |
Actual Width: | 4.923 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | esc_sysclk |
Objects: | U_IES_Top/IES_inst/u_rx_top/u_mii_rx_0/system_time_10_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | esc_sysclk | ||
5.000 | 0.000 | tCL | FF | u_Gowin_rPLL/rpll_inst/CLKOUT |
5.261 | 0.261 | tNET | FF | U_IES_Top/IES_inst/u_rx_top/u_mii_rx_0/system_time_10_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | esc_sysclk | ||
10.000 | 0.000 | tCL | RR | u_Gowin_rPLL/rpll_inst/CLKOUT |
10.184 | 0.184 | tNET | RR | U_IES_Top/IES_inst/u_rx_top/u_mii_rx_0/system_time_10_s0/CLK |
MPW4
MPW Summary:
Slack: | 3.923 |
Actual Width: | 4.923 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | esc_sysclk |
Objects: | U_IES_Top/IES_inst/u_rx_top/u_mii_rx_0/rcv_time_tmp_10_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | esc_sysclk | ||
5.000 | 0.000 | tCL | FF | u_Gowin_rPLL/rpll_inst/CLKOUT |
5.261 | 0.261 | tNET | FF | U_IES_Top/IES_inst/u_rx_top/u_mii_rx_0/rcv_time_tmp_10_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | esc_sysclk | ||
10.000 | 0.000 | tCL | RR | u_Gowin_rPLL/rpll_inst/CLKOUT |
10.184 | 0.184 | tNET | RR | U_IES_Top/IES_inst/u_rx_top/u_mii_rx_0/rcv_time_tmp_10_s0/CLK |
MPW5
MPW Summary:
Slack: | 3.923 |
Actual Width: | 4.923 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | esc_sysclk |
Objects: | U_IES_Top/IES_inst/u_rx_top/u_mii_rx_1/rcv_time_tmp_10_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | esc_sysclk | ||
5.000 | 0.000 | tCL | FF | u_Gowin_rPLL/rpll_inst/CLKOUT |
5.261 | 0.261 | tNET | FF | U_IES_Top/IES_inst/u_rx_top/u_mii_rx_1/rcv_time_tmp_10_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | esc_sysclk | ||
10.000 | 0.000 | tCL | RR | u_Gowin_rPLL/rpll_inst/CLKOUT |
10.184 | 0.184 | tNET | RR | U_IES_Top/IES_inst/u_rx_top/u_mii_rx_1/rcv_time_tmp_10_s0/CLK |
MPW6
MPW Summary:
Slack: | 3.923 |
Actual Width: | 4.923 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | esc_sysclk |
Objects: | U_IES_Top/IES_inst/u_tx_top/u0_mii_tx/frame_type_14_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | esc_sysclk | ||
5.000 | 0.000 | tCL | FF | u_Gowin_rPLL/rpll_inst/CLKOUT |
5.261 | 0.261 | tNET | FF | U_IES_Top/IES_inst/u_tx_top/u0_mii_tx/frame_type_14_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | esc_sysclk | ||
10.000 | 0.000 | tCL | RR | u_Gowin_rPLL/rpll_inst/CLKOUT |
10.184 | 0.184 | tNET | RR | U_IES_Top/IES_inst/u_tx_top/u0_mii_tx/frame_type_14_s0/CLK |
MPW7
MPW Summary:
Slack: | 3.923 |
Actual Width: | 4.923 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | esc_sysclk |
Objects: | U_IES_Top/IES_inst/u_tx_top/u0_mii_tx/frame_type_6_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | esc_sysclk | ||
5.000 | 0.000 | tCL | FF | u_Gowin_rPLL/rpll_inst/CLKOUT |
5.261 | 0.261 | tNET | FF | U_IES_Top/IES_inst/u_tx_top/u0_mii_tx/frame_type_6_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | esc_sysclk | ||
10.000 | 0.000 | tCL | RR | u_Gowin_rPLL/rpll_inst/CLKOUT |
10.184 | 0.184 | tNET | RR | U_IES_Top/IES_inst/u_tx_top/u0_mii_tx/frame_type_6_s0/CLK |
MPW8
MPW Summary:
Slack: | 3.923 |
Actual Width: | 4.923 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | esc_sysclk |
Objects: | U_IES_Top/IES_inst/u_tx_top/u0_mii_tx/frame_type_2_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | esc_sysclk | ||
5.000 | 0.000 | tCL | FF | u_Gowin_rPLL/rpll_inst/CLKOUT |
5.261 | 0.261 | tNET | FF | U_IES_Top/IES_inst/u_tx_top/u0_mii_tx/frame_type_2_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | esc_sysclk | ||
10.000 | 0.000 | tCL | RR | u_Gowin_rPLL/rpll_inst/CLKOUT |
10.184 | 0.184 | tNET | RR | U_IES_Top/IES_inst/u_tx_top/u0_mii_tx/frame_type_2_s0/CLK |
MPW9
MPW Summary:
Slack: | 3.923 |
Actual Width: | 4.923 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | esc_sysclk |
Objects: | U_IES_Top/IES_inst/u_tx_top/u0_mii_tx/frame_type_0_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | esc_sysclk | ||
5.000 | 0.000 | tCL | FF | u_Gowin_rPLL/rpll_inst/CLKOUT |
5.261 | 0.261 | tNET | FF | U_IES_Top/IES_inst/u_tx_top/u0_mii_tx/frame_type_0_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | esc_sysclk | ||
10.000 | 0.000 | tCL | RR | u_Gowin_rPLL/rpll_inst/CLKOUT |
10.184 | 0.184 | tNET | RR | U_IES_Top/IES_inst/u_tx_top/u0_mii_tx/frame_type_0_s0/CLK |
MPW10
MPW Summary:
Slack: | 3.923 |
Actual Width: | 4.923 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | esc_sysclk |
Objects: | U_IES_Top/IES_inst/u_tx_top/u0_mii_tx/tx_info_data_valid_1d_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | esc_sysclk | ||
5.000 | 0.000 | tCL | FF | u_Gowin_rPLL/rpll_inst/CLKOUT |
5.261 | 0.261 | tNET | FF | U_IES_Top/IES_inst/u_tx_top/u0_mii_tx/tx_info_data_valid_1d_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | esc_sysclk | ||
10.000 | 0.000 | tCL | RR | u_Gowin_rPLL/rpll_inst/CLKOUT |
10.184 | 0.184 | tNET | RR | U_IES_Top/IES_inst/u_tx_top/u0_mii_tx/tx_info_data_valid_1d_s0/CLK |
High Fanout Nets Report:
Report Command:report_high_fanout_nets -max_nets 10
FANOUT | NET NAME | WORST SLACK | MAX DELAY |
---|---|---|---|
12187 | n364_7 | 4.942 | 2.064 |
12119 | clk100 | 1.049 | 0.261 |
1747 | MCU_CLK | 0.510 | 0.261 |
1349 | n74_6 | 8.542 | 1.870 |
349 | map_valid | 4.554 | 4.609 |
344 | mii_rx_clk_0_d | 32.753 | 0.925 |
310 | rstn_reg2 | 8.663 | 2.738 |
303 | mii_rx_clk_1_d | 33.292 | 1.466 |
203 | eof_1d | 2.878 | 5.391 |
195 | biu_rdy | 1.129 | 2.727 |
Route Congestions Report:
Report Command:report_route_congestion -max_grids 10
GRID LOC | ROUTE CONGESTIONS |
---|---|
R34C76 | 93.06% |
R34C80 | 93.06% |
R34C81 | 93.06% |
R30C83 | 91.67% |
R34C79 | 91.67% |
R34C85 | 91.67% |
R66C11 | 91.67% |
R13C81 | 90.28% |
R15C75 | 90.28% |
R15C76 | 90.28% |
Timing Exceptions Report:
Setup Analysis Report
Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Hold Analysis Report
Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Recovery Analysis Report
Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Removal Analysis Report
Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Timing Constraints Report:
SDC Command Type | State | Detail Command |
---|---|---|
TC_CLOCK | Actived | create_clock -name mii_rx1 -period 40 -waveform {0 12.5} [get_ports {mii_rx_clk_1}] |
TC_CLOCK | Actived | create_clock -name mii_rx0 -period 40 -waveform {0 12.5} [get_ports {mii_rx_clk_0}] |
TC_CLOCK | Actived | create_clock -name esc_sysclk -period 10 -waveform {0 5} [get_nets {clk100}] |
TC_CLOCK | Actived | create_clock -name clkin -period 40 -waveform {0 20} [get_ports {clk25}] |
TC_CLOCK | Actived | create_clock -name mcu_sysclk -period 12.5 -waveform {0 6.25} [get_nets {MCU_CLK}] |
TC_CLOCK_GROUP | Actived | set_clock_groups -asynchronous -group [get_clocks {esc_sysclk}] -group [get_clocks {mii_rx0}] -group [get_clocks {mii_rx1}] |
TC_CLOCK_GROUP | Actived | set_clock_groups -asynchronous -group [get_clocks {esc_sysclk}] -group [get_clocks {mcu_sysclk}] |
TC_CLOCK_GROUP | Actived | set_clock_groups -asynchronous -group [get_clocks {clkin}] -group [get_clocks {mcu_sysclk}] |