Hierarchy Entity |
Total Power(mW) |
Block Dynamic Power(mW) |
m1_esc |
168.595 |
168.595(168.561) |
m1_esc/U_IES_Top/ |
85.731 |
85.731(85.731) |
m1_esc/U_IES_Top/IES_inst/ |
85.731 |
85.731(85.697) |
m1_esc/U_IES_Top/IES_inst/fifo_top_inst0/ |
9.405 |
9.405(9.405) |
m1_esc/U_IES_Top/IES_inst/fifo_top_inst0/fifo_inst/ |
9.405 |
9.405(0.000) |
m1_esc/U_IES_Top/IES_inst/fifo_top_inst1/ |
9.405 |
9.405(9.405) |
m1_esc/U_IES_Top/IES_inst/fifo_top_inst1/fifo_inst/ |
9.405 |
9.405(0.000) |
m1_esc/U_IES_Top/IES_inst/u0_port_forward/ |
0.066 |
0.066(0.051) |
m1_esc/U_IES_Top/IES_inst/u0_port_forward/u_down_forward/ |
0.020 |
0.020(0.000) |
m1_esc/U_IES_Top/IES_inst/u0_port_forward/u_up_forward/ |
0.032 |
0.032(0.000) |
m1_esc/U_IES_Top/IES_inst/u1_port_forward/ |
0.066 |
0.066(0.051) |
m1_esc/U_IES_Top/IES_inst/u1_port_forward/u_down_forward/ |
0.020 |
0.020(0.000) |
m1_esc/U_IES_Top/IES_inst/u1_port_forward/u_up_forward/ |
0.032 |
0.032(0.000) |
m1_esc/U_IES_Top/IES_inst/u_AHB/ |
0.296 |
0.296(0.000) |
m1_esc/U_IES_Top/IES_inst/u_dc/ |
5.263 |
5.263(0.000) |
m1_esc/U_IES_Top/IES_inst/u_dc_mem0/ |
0.772 |
0.772(0.000) |
m1_esc/U_IES_Top/IES_inst/u_dc_mem1/ |
0.566 |
0.566(0.000) |
m1_esc/U_IES_Top/IES_inst/u_dc_mem2/ |
0.534 |
0.534(0.000) |
m1_esc/U_IES_Top/IES_inst/u_dig_io_mem/ |
0.057 |
0.057(0.000) |
m1_esc/U_IES_Top/IES_inst/u_dp_mem/ |
35.120 |
35.120(0.000) |
m1_esc/U_IES_Top/IES_inst/u_ecat_mem_space/ |
0.243 |
0.243(0.000) |
m1_esc/U_IES_Top/IES_inst/u_eprom_mem/ |
0.457 |
0.457(0.000) |
m1_esc/U_IES_Top/IES_inst/u_err_counter_mem/ |
0.220 |
0.220(0.000) |
m1_esc/U_IES_Top/IES_inst/u_esc_support_mem/ |
0.353 |
0.353(0.000) |
m1_esc/U_IES_Top/IES_inst/u_event_int_mem/ |
0.213 |
0.213(0.000) |
m1_esc/U_IES_Top/IES_inst/u_f_sel/ |
0.512 |
0.512(0.000) |
m1_esc/U_IES_Top/IES_inst/u_fmmu/ |
0.751 |
0.751(0.000) |
m1_esc/U_IES_Top/IES_inst/u_fmmu_mem/ |
0.803 |
0.803(0.748) |
m1_esc/U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[0].u_fmmu_reg/ |
0.199 |
0.199(0.000) |
m1_esc/U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[1].u_fmmu_reg/ |
0.183 |
0.183(0.000) |
m1_esc/U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[2].u_fmmu_reg/ |
0.184 |
0.184(0.000) |
m1_esc/U_IES_Top/IES_inst/u_fmmu_mem/fmmu_reg_gen[3].u_fmmu_reg/ |
0.181 |
0.181(0.000) |
m1_esc/U_IES_Top/IES_inst/u_frm_process/ |
4.096 |
4.096(0.000) |
m1_esc/U_IES_Top/IES_inst/u_i2c/ |
0.269 |
0.269(0.000) |
m1_esc/U_IES_Top/IES_inst/u_led/ |
0.381 |
0.381(0.000) |
m1_esc/U_IES_Top/IES_inst/u_link_detect/ |
0.007 |
0.007(0.000) |
m1_esc/U_IES_Top/IES_inst/u_m_sel/ |
0.593 |
0.593(0.000) |
m1_esc/U_IES_Top/IES_inst/u_mi_mem/ |
0.285 |
0.285(0.000) |
m1_esc/U_IES_Top/IES_inst/u_mii_enh/ |
0.060 |
0.060(0.000) |
m1_esc/U_IES_Top/IES_inst/u_pdi_m_sel/ |
0.081 |
0.081(0.000) |
m1_esc/U_IES_Top/IES_inst/u_pdi_mem_space/ |
0.234 |
0.234(0.000) |
m1_esc/U_IES_Top/IES_inst/u_pdi_search_m_top/ |
2.007 |
2.007(2.007) |
m1_esc/U_IES_Top/IES_inst/u_pdi_search_m_top/pdi_search_m_gen[0].u_pdi_search_m/ |
0.518 |
0.518(0.000) |
m1_esc/U_IES_Top/IES_inst/u_pdi_search_m_top/pdi_search_m_gen[1].u_pdi_search_m/ |
0.495 |
0.495(0.000) |
m1_esc/U_IES_Top/IES_inst/u_pdi_search_m_top/pdi_search_m_gen[2].u_pdi_search_m/ |
0.495 |
0.495(0.000) |
m1_esc/U_IES_Top/IES_inst/u_pdi_search_m_top/pdi_search_m_gen[3].u_pdi_search_m/ |
0.499 |
0.499(0.000) |
m1_esc/U_IES_Top/IES_inst/u_pdi_sm/ |
1.180 |
1.180(0.000) |
m1_esc/U_IES_Top/IES_inst/u_phy_manager/ |
0.150 |
0.150(0.000) |
m1_esc/U_IES_Top/IES_inst/u_rx_top/ |
1.222 |
1.222(1.222) |
m1_esc/U_IES_Top/IES_inst/u_rx_top/u_mii_rx_0/ |
0.810 |
0.810(0.017) |
m1_esc/U_IES_Top/IES_inst/u_rx_top/u_mii_rx_0/u_crc_chk/ |
0.017 |
0.017(0.000) |
m1_esc/U_IES_Top/IES_inst/u_rx_top/u_mii_rx_1/ |
0.411 |
0.411(0.018) |
m1_esc/U_IES_Top/IES_inst/u_rx_top/u_mii_rx_1/u_crc_chk/ |
0.018 |
0.018(0.000) |
m1_esc/U_IES_Top/IES_inst/u_search_f_top/ |
3.057 |
3.057(3.057) |
m1_esc/U_IES_Top/IES_inst/u_search_f_top/search_f_top_gen[0].u_search_f/ |
0.976 |
0.976(0.000) |
m1_esc/U_IES_Top/IES_inst/u_search_f_top/search_f_top_gen[1].u_search_f/ |
0.694 |
0.694(0.000) |
m1_esc/U_IES_Top/IES_inst/u_search_f_top/search_f_top_gen[2].u_search_f/ |
0.694 |
0.694(0.000) |
m1_esc/U_IES_Top/IES_inst/u_search_f_top/search_f_top_gen[3].u_search_f/ |
0.694 |
0.694(0.000) |
m1_esc/U_IES_Top/IES_inst/u_search_m_top/ |
4.718 |
4.718(4.718) |
m1_esc/U_IES_Top/IES_inst/u_search_m_top/search_m_gen[0].u_search_m/ |
1.439 |
1.439(0.000) |
m1_esc/U_IES_Top/IES_inst/u_search_m_top/search_m_gen[1].u_search_m/ |
1.093 |
1.093(0.000) |
m1_esc/U_IES_Top/IES_inst/u_search_m_top/search_m_gen[2].u_search_m/ |
1.093 |
1.093(0.000) |
m1_esc/U_IES_Top/IES_inst/u_search_m_top/search_m_gen[3].u_search_m/ |
1.094 |
1.094(0.000) |
m1_esc/U_IES_Top/IES_inst/u_sm_mem/ |
0.911 |
0.911(0.863) |
m1_esc/U_IES_Top/IES_inst/u_sm_mem/sm_reg_gen[0].u_sm_reg/ |
0.237 |
0.237(0.000) |
m1_esc/U_IES_Top/IES_inst/u_sm_mem/sm_reg_gen[1].u_sm_reg/ |
0.208 |
0.208(0.000) |
m1_esc/U_IES_Top/IES_inst/u_sm_mem/sm_reg_gen[2].u_sm_reg/ |
0.210 |
0.210(0.000) |
m1_esc/U_IES_Top/IES_inst/u_sm_mem/sm_reg_gen[3].u_sm_reg/ |
0.210 |
0.210(0.000) |
m1_esc/U_IES_Top/IES_inst/u_spec_reg_mem/ |
0.023 |
0.023(0.000) |
m1_esc/U_IES_Top/IES_inst/u_status_ctrl_mem/ |
0.368 |
0.368(0.000) |
m1_esc/U_IES_Top/IES_inst/u_tx_top/ |
0.479 |
0.479(0.479) |
m1_esc/U_IES_Top/IES_inst/u_tx_top/u0_mii_tx/ |
0.238 |
0.238(0.084) |
m1_esc/U_IES_Top/IES_inst/u_tx_top/u0_mii_tx/u_crc_gen/ |
0.084 |
0.084(0.000) |
m1_esc/U_IES_Top/IES_inst/u_tx_top/u1_mii_tx/ |
0.241 |
0.241(0.088) |
m1_esc/U_IES_Top/IES_inst/u_tx_top/u1_mii_tx/u_crc_gen/ |
0.088 |
0.088(0.000) |
m1_esc/U_IES_Top/IES_inst/u_watchdog/ |
0.265 |
0.265(0.000) |
m1_esc/U_IES_Top/IES_inst/u_wd_mem/ |
0.207 |
0.207(0.000) |
m1_esc/u_Gowin_EMPU_M1_template/ |
65.700 |
65.700(65.700) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/ |
65.700 |
65.700(65.697) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/ |
64.943 |
64.943(64.943) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/ |
64.943 |
64.943(64.943) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/ |
8.726 |
8.726(8.726) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_ahb/ |
0.286 |
0.286(0.000) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/ |
7.849 |
7.849(7.849) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/ |
0.749 |
0.749(0.212) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/u_decode/ |
0.094 |
0.094(0.000) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/u_excpt/ |
0.099 |
0.099(0.000) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/u_r_list_add/ |
0.019 |
0.019(0.000) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/ |
7.031 |
7.031(6.448) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/ |
0.247 |
0.247(0.202) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/ |
0.202 |
0.202(0.000) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/ |
0.026 |
0.026(0.000) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mul_shft/ |
5.904 |
5.904(5.904) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mul_shft/u_mul/ |
5.768 |
5.768(0.000) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mul_shft/u_shft/ |
0.136 |
0.136(0.000) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/ |
0.056 |
0.056(0.000) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_rf1_mux/ |
0.215 |
0.215(0.000) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_fetch/ |
0.068 |
0.068(0.000) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_nvic/ |
0.591 |
0.591(0.591) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_nvic/u_ahb/ |
0.372 |
0.372(0.000) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_nvic/u_main/ |
0.015 |
0.015(0.000) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_nvic/u_tree/ |
0.203 |
0.203(0.181) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_nvic/u_tree/u_pri_lvl0/ |
0.144 |
0.144(0.000) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_nvic/u_tree/u_pri_lvl2/ |
0.002 |
0.002(0.000) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_nvic/u_tree/u_pri_num1/ |
0.036 |
0.036(0.000) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_dtcm/ |
28.109 |
28.109(0.000) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/ |
28.109 |
28.109(0.000) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/ |
0.753 |
0.753(0.753) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/ |
0.753 |
0.753(0.753) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb10/ |
0.002 |
0.002(0.000) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb11/ |
0.002 |
0.002(0.000) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb12/ |
0.003 |
0.003(0.000) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb4/ |
0.002 |
0.002(0.000) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb5/ |
0.003 |
0.003(0.000) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb6/ |
0.002 |
0.002(0.000) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb9/ |
0.002 |
0.002(0.000) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb_apb2/ |
0.002 |
0.002(0.000) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb_can/ |
0.003 |
0.003(0.000) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb_internet/ |
0.002 |
0.002(0.000) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb_spi_flash/ |
0.002 |
0.002(0.000) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_cmsdk_ahb_gpio_0/ |
0.302 |
0.302(0.302) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_cmsdk_ahb_gpio_0/u_ahb_to_gpio/ |
0.007 |
0.007(0.000) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_cmsdk_ahb_gpio_0/u_iop_gpio/ |
0.294 |
0.294(0.000) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/ |
0.185 |
0.185(0.185) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/ |
0.185 |
0.185(0.185) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uInputStage0/ |
0.022 |
0.022(0.000) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uMatrixDecodeS0/ |
0.025 |
0.025(0.000) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage0/ |
0.015 |
0.015(0.002) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage0/uOutputArb/ |
0.002 |
0.002(0.000) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage1/ |
0.007 |
0.007(0.003) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage1/uOutputArb/ |
0.003 |
0.003(0.000) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage10/ |
0.001 |
0.001(0.001) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage10/uOutputArb/ |
0.001 |
0.001(0.000) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage11/ |
0.028 |
0.028(0.002) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage11/uOutputArb/ |
0.002 |
0.002(0.000) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage12/ |
0.006 |
0.006(0.003) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage12/uOutputArb/ |
0.003 |
0.003(0.000) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage13/ |
0.005 |
0.005(0.003) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage13/uOutputArb/ |
0.003 |
0.003(0.000) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage14/ |
0.005 |
0.005(0.003) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage14/uOutputArb/ |
0.003 |
0.003(0.000) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage15/ |
0.004 |
0.004(0.002) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage15/uOutputArb/ |
0.002 |
0.002(0.000) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage2/ |
0.008 |
0.008(0.003) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage2/uOutputArb/ |
0.003 |
0.003(0.000) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage3/ |
0.008 |
0.008(0.003) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage3/uOutputArb/ |
0.003 |
0.003(0.000) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage4/ |
0.020 |
0.020(0.005) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage4/uOutputArb/ |
0.005 |
0.005(0.000) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage5/ |
0.008 |
0.008(0.003) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage5/uOutputArb/ |
0.003 |
0.003(0.000) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage6/ |
0.007 |
0.007(0.007) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage6/uOutputArb/ |
0.007 |
0.007(0.000) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage7/ |
0.004 |
0.004(0.002) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage7/uOutputArb/ |
0.002 |
0.002(0.000) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage8/ |
0.010 |
0.010(0.001) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage8/uOutputArb/ |
0.001 |
0.001(0.000) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage9/ |
0.004 |
0.004(0.002) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage9/uOutputArb/ |
0.002 |
0.002(0.000) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gw_apb_int_wrapper/ |
0.237 |
0.237(0.237) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gw_apb_int_wrapper/u_integration_peripherals/ |
0.154 |
0.154(0.154) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gw_apb_int_wrapper/u_integration_peripherals/u_cmsdk_apb_timer0/ |
0.154 |
0.154(0.000) |
m1_esc/u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gw_apb_int_wrapper/u_p_sse050_interconnect_f0_ahb_to_apb/ |
0.084 |
0.084(0.000) |
m1_esc/u_Gowin_rPLL/ |
8.720 |
8.720(0.000) |
m1_esc/u_Gowin_rPLL_MCU/ |
8.368 |
8.368(0.000) |
m1_esc/u_button/ |
0.042 |
0.042(0.000) |