Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\ahb_def_slave.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\BusMatrix.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\can.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\can_define.vh D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\can_static_macro_define.vh D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\can_top.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_adder.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_ahb.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_alu_dec.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_core.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_ctl.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_ctl_add3.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_decoder.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_defs.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_dp.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_excpt.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_fetch.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_fns.vh D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_mem_ctl.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_multiplier.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_multiply_shift.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_mux4.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_nvic.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_nvic_ahb.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_nvic_ahb_os.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_nvic_defs.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_nvic_main.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_nvic_pri_lvl.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_nvic_pri_num.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_nvic_tree.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_nvic_undefs.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_reg_bank.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_shifter.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_undef_check.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_undefs.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_ethmac.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_ethmac_miim_wrapper.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_ethmac_rx_buffer_to_ahb.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_ethmac_rx_to_buffer.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_ethmac_rx_wrapper.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_ethmac_sdp_wrapper_32bit.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_ethmac_top.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_ethmac_tx_wrapper.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_ethmac_wrapper.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_gpio.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_ahbif_ctrl.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_arbiter.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_async_fifo_clr.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_config.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_const.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_ctrl.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_eilmif_ctrl.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_fifo.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_gck.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_pad_lib.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_reg.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_regif.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_regif_ctrl.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_spiif.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_sync.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_sync_l2l.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_sync_p2p.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_to_iop.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_dualtimers.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_dualtimers_defs.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_dualtimers_frc.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_spi.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_timer.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_autocorrelation.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_balancefilter.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_collector.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_crngt_to_trng.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_dx_inv_chain.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_dx_trng_top.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_dxm_ff.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_dxm_interrupt_low.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_dxm_mux.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_dxm_mux_clk.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_dxm_sync.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_ehr.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_entropy_gen.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_gtech_models.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_lfsr_new.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_line.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_noise_gen.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_pmf_table.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_prng_top_wrap.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_reg_file.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_rng_engine.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_rng_misc.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_rng_top.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_rng_top_wrap_unconnected.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_rosc.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_rst_logic.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_sample_cntr.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_slave_bus_ifc.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_sync.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_tests_misc.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_top.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_uart.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_watchdog.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_watchdog_defs.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_watchdog_frc.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_iop_gpio.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\CortexM1.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\CortexM1Integration.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\CortexM1IntegrationWrapper.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\ddr3_1_4code.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\DDR3_define.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\ddr3_name.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\ddr3_to_ahb_top.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\DDR3_TOP.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\dtcm.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\Gowin_EMPU_M1_top.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\GowinAhbExt.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\GowinCM1AhbExt.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\GowinCM1AhbExtWrapper.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\gw_ahb_psram.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\gw_apb_i2c.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\gw_apb_int_wrapper.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\gw_apb_sd.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\gw_gpio.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\InputStage.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\itcm.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\MatrixDecodeS0.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\MatrixDecodeS1.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\MatrixDecodeS2.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\OutputArb1.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\OutputArb2.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\OutputArb3.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\OutputStage1.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\OutputStage2.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\OutputStage3.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\p_sse050_interconnect_f0_ahb_to_apb.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\p_sse050_interconnect_f0_apb_slave_mux.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\psram_code.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\psram_top.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\rng_addr_params.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\rng_cc_params.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\rng_params.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\Rtc.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\RtcApbif.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\RtcControl.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\RtcCounter.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\RtcInterrupt.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\RtcParams.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\RtcRevAnd.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\RtcSynctoPCLK.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\RtcUpdate.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\sse050_int_apb_decoder.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\sse050_integration_peripherals.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\sync_p2p.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\triple_speed_mac_name.v D:\PRJ\ethercat\GW-IES\Ref_Design\gw_ies_ref.design-v1.0-ahb\GW_IES\src\gowin_empu_m1\temp\gw_empu_m1\cm1_option_defs.v D:\PRJ\ethercat\GW-IES\Ref_Design\gw_ies_ref.design-v1.0-ahb\GW_IES\src\gowin_empu_m1\temp\gw_empu_m1\ahb_option_defs.v D:\PRJ\ethercat\GW-IES\Ref_Design\gw_ies_ref.design-v1.0-ahb\GW_IES\src\gowin_empu_m1\temp\gw_empu_m1\can_parameter.vh D:\PRJ\ethercat\GW-IES\Ref_Design\gw_ies_ref.design-v1.0-ahb\GW_IES\src\gowin_empu_m1\temp\gw_empu_m1\triple_speed_mac_param.v D:\PRJ\ethercat\GW-IES\Ref_Design\gw_ies_ref.design-v1.0-ahb\GW_IES\src\gowin_empu_m1\temp\gw_empu_m1\triple_speed_mac_define.v |
GowinSynthesis Constraints File | --- |
Version | GowinSynthesis V1.9.8.01 |
Part Number | GW2A-LV55PG484C8/I7 |
Device | GW2A-55C |
Created Time | Thu Dec 23 17:24:56 2021 |
Legal Announcement | Copyright (C)2014-2021 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | Gowin_EMPU_M1_Top |
Synthesis Process | Running parser: CPU time = 0h 0m 7s, Elapsed time = 0h 0m 8s, Peak memory usage = 89.801MB Running netlist conversion: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.145s, Peak memory usage = 89.801MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 89.801MB Optimizing Phase 1: CPU time = 0h 0m 0.265s, Elapsed time = 0h 0m 0.269s, Peak memory usage = 89.801MB Optimizing Phase 2: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 89.801MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.176s, Peak memory usage = 89.801MB Inferring Phase 1: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.058s, Peak memory usage = 89.801MB Inferring Phase 2: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.065s, Peak memory usage = 89.801MB Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.015s, Peak memory usage = 89.801MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.75s, Elapsed time = 0h 0m 0.793s, Peak memory usage = 89.801MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.21s, Peak memory usage = 89.801MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.39s, Elapsed time = 0h 0m 0.389s, Peak memory usage = 89.801MB Tech-Mapping Phase 3: CPU time = 0h 0m 28s, Elapsed time = 0h 0m 28s, Peak memory usage = 89.801MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.937s, Elapsed time = 0h 0m 0.974s, Peak memory usage = 89.801MB Generate output files: CPU time = 0h 0m 0.515s, Elapsed time = 0h 0m 0.527s, Peak memory usage = 89.801MB |
Total Time and Memory Usage | CPU time = 0h 0m 40s, Elapsed time = 0h 0m 41s, Peak memory usage = 89.801MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 173 |
I/O Buf | 172 |
    IBUF | 53 |
    OBUF | 119 |
Register | 1368 |
    DFF | 10 |
    DFFSE | 1 |
    DFFR | 3 |
    DFFRE | 1 |
    DFFP | 21 |
    DFFPE | 63 |
    DFFC | 276 |
    DFFCE | 993 |
LUT | 3620 |
    LUT2 | 310 |
    LUT3 | 970 |
    LUT4 | 2340 |
ALU | 39 |
    ALU | 39 |
SSRAM | 20 |
    RAM16S4 | 4 |
    RAM16SDP4 | 16 |
INV | 2 |
    INV | 2 |
DSP | 1 |
    MULT36X36 | 1 |
BSRAM | 64 |
    SP | 64 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 3781(3622 LUTs, 39 ALUs, 20 SSRAMs) / 54720 | 7% |
Register | 1368 / 41997 | 3% |
  --Register as Latch | 0 / 41997 | 0% |
  --Register as FF | 1368 / 41997 | 3% |
BSRAM | 64 / 140 | 46% |
Timing
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|
HCLK | Base | 10.000 | 100.0 | 0.000 | 5.000 | HCLK_ibuf/I |
Max Frequency Summary:
No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | HCLK | 100.0(MHz) | 110.4(MHz) | 14 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | 0.945 |
Data Arrival Time | 9.883 |
Data Required Time | 10.828 |
From | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0 |
To | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/biu_commit_reg_s0 |
Launch Clk | HCLK[R] |
Latch Clk | HCLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | HCLK | |||
0.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 1454 | HCLK_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/CLK |
1.095 | 0.232 | tC2Q | RF | 8 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/Q |
1.332 | 0.237 | tNET | FF | 4 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/RAD[0] |
1.849 | 0.517 | tINS | FF | 8 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/DO[2] |
2.086 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/I0 |
2.602 | 0.517 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/F |
2.839 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/I1 |
3.395 | 0.555 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/F |
3.632 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/I1 |
4.187 | 0.555 | tINS | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/F |
4.424 | 0.237 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/I1 |
4.994 | 0.570 | tINS | FR | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/COUT |
4.994 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/CIN |
5.029 | 0.035 | tINS | RF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/COUT |
5.029 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/CIN |
5.064 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/COUT |
5.064 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/CIN |
5.099 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/COUT |
5.099 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/CIN |
5.134 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/COUT |
5.134 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/CIN |
5.170 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/COUT |
5.170 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/CIN |
5.205 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/COUT |
5.205 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/CIN |
5.240 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/COUT |
5.240 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/CIN |
5.275 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/COUT |
5.275 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/CIN |
5.310 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/COUT |
5.310 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/CIN |
5.346 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/COUT |
5.346 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/CIN |
5.381 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/COUT |
5.381 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/CIN |
5.416 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/COUT |
5.416 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/CIN |
5.451 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/COUT |
5.451 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/CIN |
5.486 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/COUT |
5.486 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/CIN |
5.522 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/COUT |
5.522 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/CIN |
5.557 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/COUT |
5.557 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_19_s/CIN |
5.592 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_19_s/COUT |
5.592 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_20_s/CIN |
5.627 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_20_s/COUT |
5.627 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_21_s/CIN |
5.662 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_21_s/COUT |
5.662 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_22_s/CIN |
5.698 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_22_s/COUT |
5.698 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_23_s/CIN |
5.733 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_23_s/COUT |
5.733 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_24_s/CIN |
5.768 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_24_s/COUT |
5.768 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_25_s/CIN |
6.238 | 0.470 | tINS | FF | 4 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_25_s/SUM |
6.475 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s9/I1 |
7.030 | 0.555 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s9/F |
7.267 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s7/I3 |
7.638 | 0.371 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s7/F |
7.875 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s1/I3 |
8.246 | 0.371 | tINS | FF | 3 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s1/F |
8.483 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/biu_commit_Z_s3/I1 |
9.038 | 0.555 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/biu_commit_Z_s3/F |
9.275 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/biu_commit_Z_s/I3 |
9.646 | 0.371 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/biu_commit_Z_s/F |
9.883 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/biu_commit_reg_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | HCLK | |||
10.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 1454 | HCLK_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/biu_commit_reg_s0/CLK |
10.828 | -0.035 | tSu | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/biu_commit_reg_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 14 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 6.181, 68.527%; route: 2.607, 28.901%; tC2Q: 0.232, 2.572% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 2
Path Summary:Slack | 1.047 |
Data Arrival Time | 9.781 |
Data Required Time | 10.828 |
From | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0 |
To | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/dtcm_sel_s0 |
Launch Clk | HCLK[R] |
Latch Clk | HCLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | HCLK | |||
0.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 1454 | HCLK_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/CLK |
1.095 | 0.232 | tC2Q | RF | 8 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/Q |
1.332 | 0.237 | tNET | FF | 4 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/RAD[0] |
1.849 | 0.517 | tINS | FF | 8 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/DO[2] |
2.086 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/I0 |
2.602 | 0.517 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/F |
2.839 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/I1 |
3.395 | 0.555 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/F |
3.632 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/I1 |
4.187 | 0.555 | tINS | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/F |
4.424 | 0.237 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/I1 |
4.994 | 0.570 | tINS | FR | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/COUT |
4.994 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/CIN |
5.029 | 0.035 | tINS | RF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/COUT |
5.029 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/CIN |
5.064 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/COUT |
5.064 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/CIN |
5.099 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/COUT |
5.099 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/CIN |
5.134 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/COUT |
5.134 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/CIN |
5.170 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/COUT |
5.170 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/CIN |
5.205 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/COUT |
5.205 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/CIN |
5.240 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/COUT |
5.240 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/CIN |
5.275 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/COUT |
5.275 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/CIN |
5.310 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/COUT |
5.310 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/CIN |
5.346 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/COUT |
5.346 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/CIN |
5.381 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/COUT |
5.381 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/CIN |
5.416 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/COUT |
5.416 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/CIN |
5.451 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/COUT |
5.451 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/CIN |
5.486 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/COUT |
5.486 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/CIN |
5.522 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/COUT |
5.522 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/CIN |
5.557 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/COUT |
5.557 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_19_s/CIN |
5.592 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_19_s/COUT |
5.592 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_20_s/CIN |
5.627 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_20_s/COUT |
5.627 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_21_s/CIN |
5.662 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_21_s/COUT |
5.662 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_22_s/CIN |
5.698 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_22_s/COUT |
5.698 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_23_s/CIN |
5.733 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_23_s/COUT |
5.733 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_24_s/CIN |
5.768 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_24_s/COUT |
5.768 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_25_s/CIN |
6.238 | 0.470 | tINS | FF | 4 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_25_s/SUM |
6.475 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s9/I1 |
7.030 | 0.555 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s9/F |
7.267 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s7/I3 |
7.638 | 0.371 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s7/F |
7.875 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s1/I3 |
8.246 | 0.371 | tINS | FF | 3 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s1/F |
8.483 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_itcm_sel_s2/I3 |
8.854 | 0.371 | tINS | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_itcm_sel_s2/F |
9.091 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_dtcm_sel_s0/I2 |
9.544 | 0.453 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_dtcm_sel_s0/F |
9.781 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/dtcm_sel_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | HCLK | |||
10.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 1454 | HCLK_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/dtcm_sel_s0/CLK |
10.828 | -0.035 | tSu | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/dtcm_sel_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 14 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 6.079, 68.167%; route: 2.607, 29.232%; tC2Q: 0.232, 2.601% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 3
Path Summary:Slack | 1.047 |
Data Arrival Time | 9.781 |
Data Required Time | 10.828 |
From | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0 |
To | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/itcm_sel_s0 |
Launch Clk | HCLK[R] |
Latch Clk | HCLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | HCLK | |||
0.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 1454 | HCLK_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/CLK |
1.095 | 0.232 | tC2Q | RF | 8 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/Q |
1.332 | 0.237 | tNET | FF | 4 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/RAD[0] |
1.849 | 0.517 | tINS | FF | 8 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/DO[2] |
2.086 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/I0 |
2.602 | 0.517 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/F |
2.839 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/I1 |
3.395 | 0.555 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/F |
3.632 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/I1 |
4.187 | 0.555 | tINS | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/F |
4.424 | 0.237 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/I1 |
4.994 | 0.570 | tINS | FR | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/COUT |
4.994 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/CIN |
5.029 | 0.035 | tINS | RF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/COUT |
5.029 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/CIN |
5.064 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/COUT |
5.064 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/CIN |
5.099 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/COUT |
5.099 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/CIN |
5.134 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/COUT |
5.134 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/CIN |
5.170 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/COUT |
5.170 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/CIN |
5.205 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/COUT |
5.205 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/CIN |
5.240 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/COUT |
5.240 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/CIN |
5.275 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/COUT |
5.275 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/CIN |
5.310 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/COUT |
5.310 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/CIN |
5.346 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/COUT |
5.346 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/CIN |
5.381 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/COUT |
5.381 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/CIN |
5.416 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/COUT |
5.416 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/CIN |
5.451 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/COUT |
5.451 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/CIN |
5.486 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/COUT |
5.486 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/CIN |
5.522 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/COUT |
5.522 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/CIN |
5.557 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/COUT |
5.557 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_19_s/CIN |
5.592 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_19_s/COUT |
5.592 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_20_s/CIN |
5.627 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_20_s/COUT |
5.627 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_21_s/CIN |
5.662 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_21_s/COUT |
5.662 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_22_s/CIN |
5.698 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_22_s/COUT |
5.698 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_23_s/CIN |
5.733 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_23_s/COUT |
5.733 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_24_s/CIN |
5.768 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_24_s/COUT |
5.768 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_25_s/CIN |
6.238 | 0.470 | tINS | FF | 4 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_25_s/SUM |
6.475 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s9/I1 |
7.030 | 0.555 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s9/F |
7.267 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s7/I3 |
7.638 | 0.371 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s7/F |
7.875 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s1/I3 |
8.246 | 0.371 | tINS | FF | 3 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s1/F |
8.483 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_itcm_sel_s2/I3 |
8.854 | 0.371 | tINS | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_itcm_sel_s2/F |
9.091 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_itcm_sel_s0/I2 |
9.544 | 0.453 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_itcm_sel_s0/F |
9.781 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/itcm_sel_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | HCLK | |||
10.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 1454 | HCLK_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/itcm_sel_s0/CLK |
10.828 | -0.035 | tSu | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/itcm_sel_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 14 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 6.079, 68.167%; route: 2.607, 29.232%; tC2Q: 0.232, 2.601% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 4
Path Summary:Slack | 1.057 |
Data Arrival Time | 9.771 |
Data Required Time | 10.828 |
From | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0 |
To | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/z_flag_mux_s0 |
Launch Clk | HCLK[R] |
Latch Clk | HCLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | HCLK | |||
0.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 1454 | HCLK_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/CLK |
1.095 | 0.232 | tC2Q | RF | 8 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/Q |
1.332 | 0.237 | tNET | FF | 4 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/RAD[0] |
1.849 | 0.517 | tINS | FF | 8 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/DO[2] |
2.086 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/I0 |
2.602 | 0.517 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/F |
2.839 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/I1 |
3.395 | 0.555 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/F |
3.632 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/I1 |
4.187 | 0.555 | tINS | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/F |
4.424 | 0.237 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/I1 |
4.994 | 0.570 | tINS | FR | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/COUT |
4.994 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/CIN |
5.029 | 0.035 | tINS | RF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/COUT |
5.029 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/CIN |
5.064 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/COUT |
5.064 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/CIN |
5.099 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/COUT |
5.099 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/CIN |
5.134 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/COUT |
5.134 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/CIN |
5.170 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/COUT |
5.170 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/CIN |
5.205 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/COUT |
5.205 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/CIN |
5.240 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/COUT |
5.240 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/CIN |
5.275 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/COUT |
5.275 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/CIN |
5.310 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/COUT |
5.310 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/CIN |
5.346 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/COUT |
5.346 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/CIN |
5.381 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/COUT |
5.381 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/CIN |
5.416 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/COUT |
5.416 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/CIN |
5.451 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/COUT |
5.451 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/CIN |
5.486 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/COUT |
5.486 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/CIN |
5.522 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/COUT |
5.522 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/CIN |
5.557 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/COUT |
5.557 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_19_s/CIN |
5.592 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_19_s/COUT |
5.592 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_20_s/CIN |
5.627 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_20_s/COUT |
5.627 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_21_s/CIN |
5.662 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_21_s/COUT |
5.662 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_22_s/CIN |
5.698 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_22_s/COUT |
5.698 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_23_s/CIN |
5.733 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_23_s/COUT |
5.733 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_24_s/CIN |
5.768 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_24_s/COUT |
5.768 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_25_s/CIN |
6.238 | 0.470 | tINS | FF | 4 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_25_s/SUM |
6.475 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s9/I1 |
7.030 | 0.555 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s9/F |
7.267 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s7/I3 |
7.638 | 0.371 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s7/F |
7.875 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s1/I3 |
8.246 | 0.371 | tINS | FF | 3 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s1/F |
8.483 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/nxt_z_flag_mux_s8/I3 |
8.854 | 0.371 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/nxt_z_flag_mux_s8/F |
9.091 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/nxt_z_flag_mux_s6/I0 |
9.194 | 0.103 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/nxt_z_flag_mux_s6/O |
9.431 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/nxt_z_flag_mux_s3/I0 |
9.534 | 0.103 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/nxt_z_flag_mux_s3/O |
9.771 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/z_flag_mux_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | HCLK | |||
10.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 1454 | HCLK_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/z_flag_mux_s0/CLK |
10.828 | -0.035 | tSu | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/z_flag_mux_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 14 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 5.832, 65.471%; route: 2.844, 31.925%; tC2Q: 0.232, 2.604% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 5
Path Summary:Slack | 2.274 |
Data Arrival Time | 8.554 |
Data Required Time | 10.828 |
From | M1_inst/u_CortexM1Integration/u_cortexm1/u_ahb/HADDR_31_s0 |
To | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uInputStage0/PendTranReg_s1 |
Launch Clk | HCLK[R] |
Latch Clk | HCLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | HCLK | |||
0.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 1454 | HCLK_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_ahb/HADDR_31_s0/CLK |
1.095 | 0.232 | tC2Q | RF | 5 | M1_inst/u_CortexM1Integration/u_cortexm1/u_ahb/HADDR_31_s0/Q |
1.332 | 0.237 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage6/uOutputArb/NoPortNext_s5/I1 |
1.887 | 0.555 | tINS | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage6/uOutputArb/NoPortNext_s5/F |
2.124 | 0.237 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage6/uOutputArb/NoPortNext_s3/I3 |
2.495 | 0.371 | tINS | FF | 4 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage6/uOutputArb/NoPortNext_s3/F |
2.732 | 0.237 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage2/AHB2HSEL_s2/I2 |
3.185 | 0.453 | tINS | FF | 7 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage2/AHB2HSEL_s2/F |
3.422 | 0.237 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage2/AHB2HSEL_s0/I2 |
3.875 | 0.453 | tINS | FF | 4 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage2/AHB2HSEL_s0/F |
4.112 | 0.237 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uMatrixDecodeS0/AddrOutPort_0_s3/I1 |
4.667 | 0.555 | tINS | FF | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uMatrixDecodeS0/AddrOutPort_0_s3/F |
4.904 | 0.237 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uMatrixDecodeS0/AddrOutPort_0_s4/I3 |
5.274 | 0.371 | tINS | FF | 13 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uMatrixDecodeS0/AddrOutPort_0_s4/F |
5.511 | 0.237 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage8/Active0to8_s6/I2 |
5.964 | 0.453 | tINS | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage8/Active0to8_s6/F |
6.201 | 0.237 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage8/Active0to8_s2/I0 |
6.305 | 0.103 | tINS | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage8/Active0to8_s2/O |
6.542 | 0.237 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage8/Active0to8_s0/I0 |
6.645 | 0.103 | tINS | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage8/Active0to8_s0/O |
6.882 | 0.237 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage8/Active0to8_s/I0 |
6.985 | 0.103 | tINS | FF | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage8/Active0to8_s/O |
7.222 | 0.237 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uInputStage0/n115_s1/I2 |
7.675 | 0.453 | tINS | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uInputStage0/n115_s1/F |
7.912 | 0.237 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uInputStage0/PendTranReg_s3/I2 |
8.374 | 0.462 | tINS | FR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uInputStage0/PendTranReg_s3/F |
8.554 | 0.180 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uInputStage0/PendTranReg_s1/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | HCLK | |||
10.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 1454 | HCLK_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uInputStage0/PendTranReg_s1/CLK |
10.828 | -0.035 | tSu | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uInputStage0/PendTranReg_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 11 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 4.435, 57.664%; route: 3.024, 39.319%; tC2Q: 0.232, 3.017% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |