Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | E:\myWork\IP\releaseVerify\RefDesign\Interface\19811\Gowin_IES_RefDesign\GW_IES\src\GW_IES_Top\GW_IES_Top.v E:\myWork\IP\releaseVerify\RefDesign\Interface\19811\Gowin_IES_RefDesign\GW_IES\src\M1_ESC.v E:\myWork\IP\releaseVerify\RefDesign\Interface\19811\Gowin_IES_RefDesign\GW_IES\src\button.v E:\myWork\IP\releaseVerify\RefDesign\Interface\19811\Gowin_IES_RefDesign\GW_IES\src\gowin_empu_m1\gowin_empu_m1.v E:\myWork\IP\releaseVerify\RefDesign\Interface\19811\Gowin_IES_RefDesign\GW_IES\src\gowin_empu_m1_template.v E:\myWork\IP\releaseVerify\RefDesign\Interface\19811\Gowin_IES_RefDesign\GW_IES\src\gowin_rpll\gowin_rpll.v E:\myWork\IP\releaseVerify\RefDesign\Interface\19811\Gowin_IES_RefDesign\GW_IES\src\gowin_rpll_mcu\gowin_rpll_mcu.v |
| GowinSynthesis Constraints File | --- |
| Version | V1.9.8.11 |
| Part Number | GW2A-LV55PG484C8/I7 |
| Device | GW2A-55 |
| Device Version | C |
| Created Time | Fri Mar 31 16:07:07 2023 |
| Legal Announcement | Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | m1_esc |
| Synthesis Process | Running parser: CPU time = 0h 0m 6s, Elapsed time = 0h 0m 8s, Peak memory usage = 266.242MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.609s, Elapsed time = 0h 0m 0.607s, Peak memory usage = 266.242MB Optimizing Phase 1: CPU time = 0h 0m 0.562s, Elapsed time = 0h 0m 0.561s, Peak memory usage = 266.242MB Optimizing Phase 2: CPU time = 0h 0m 0.859s, Elapsed time = 0h 0m 0.856s, Peak memory usage = 266.242MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.531s, Elapsed time = 0h 0m 0.529s, Peak memory usage = 266.242MB Inferring Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.037s, Peak memory usage = 266.242MB Inferring Phase 2: CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.184s, Peak memory usage = 266.242MB Inferring Phase 3: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.043s, Peak memory usage = 266.242MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.453s, Elapsed time = 0h 0m 0.458s, Peak memory usage = 266.242MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.312s, Elapsed time = 0h 0m 0.311s, Peak memory usage = 266.242MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.25s, Elapsed time = 0h 0m 0.246s, Peak memory usage = 266.242MB Tech-Mapping Phase 3: CPU time = 0h 0m 0.937s, Elapsed time = 0h 0m 0.959s, Peak memory usage = 266.242MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.515s, Elapsed time = 0h 0m 0.514s, Peak memory usage = 266.242MB Generate output files: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 328.797MB |
| Total Time and Memory Usage | CPU time = 0h 0m 13s, Elapsed time = 0h 0m 15s, Peak memory usage = 328.797MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 43 |
| I/O Buf | 156 |
| IBUF | 71 |
| OBUF | 82 |
| TBUF | 1 |
| IOBUF | 2 |
| Register | 14421 |
| DFF | 131 |
| DFFE | 188 |
| DFFSE | 7 |
| DFFR | 227 |
| DFFRE | 32 |
| DFFP | 50 |
| DFFPE | 266 |
| DFFC | 6418 |
| DFFCE | 7102 |
| LUT | 15281 |
| LUT2 | 1818 |
| LUT3 | 4909 |
| LUT4 | 8554 |
| ALU | 2596 |
| ALU | 2596 |
| SSRAM | 53 |
| RAM16S4 | 37 |
| RAM16SDP4 | 16 |
| INV | 55 |
| INV | 55 |
| DSP | 1 |
| MULT36X36 | 1 |
| BSRAM | 71 |
| SP | 64 |
| SDPB | 2 |
| DPB | 5 |
| CLOCK | 2 |
| rPLL | 2 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 18250(15336 LUTs, 2596 ALUs, 53 SSRAMs) / 54720 | 34% |
| Register | 14421 / 41997 | 35% |
| --Register as Latch | 0 / 41997 | 0% |
| --Register as FF | 14421 / 41997 | 35% |
| BSRAM | 71 / 140 | 51% |
Timing
Clock Summary:
| Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|
| clk25 | Base | 40.000 | 25.0 | 0.000 | 20.000 | clk25_ibuf/I | ||
| mii_rx_clk_0 | Base | 10.000 | 100.0 | 0.000 | 5.000 | mii_rx_clk_0_ibuf/I | ||
| mii_rx_clk_1 | Base | 10.000 | 100.0 | 0.000 | 5.000 | mii_rx_clk_1_ibuf/I | ||
| u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/HCLK_ibuf/I | Base | 10.000 | 100.0 | 0.000 | 5.000 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/HCLK_ibuf/I | ||
| u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk | Generated | 10.000 | 100.0 | 0.000 | 5.000 | clk25_ibuf/I | clk25 | u_Gowin_rPLL/rpll_inst/CLKOUT |
| u_Gowin_rPLL/rpll_inst/CLKOUTP.default_gen_clk | Generated | 10.000 | 100.0 | 0.000 | 5.000 | clk25_ibuf/I | clk25 | u_Gowin_rPLL/rpll_inst/CLKOUTP |
| u_Gowin_rPLL/rpll_inst/CLKOUTD.default_gen_clk | Generated | 40.000 | 25.0 | 0.000 | 20.000 | clk25_ibuf/I | clk25 | u_Gowin_rPLL/rpll_inst/CLKOUTD |
| u_Gowin_rPLL/rpll_inst/CLKOUTD3.default_gen_clk | Generated | 30.000 | 33.3 | 0.000 | 15.000 | clk25_ibuf/I | clk25 | u_Gowin_rPLL/rpll_inst/CLKOUTD3 |
| u_Gowin_rPLL_MCU/rpll_inst/CLKOUT.default_gen_clk | Generated | 12.500 | 80.0 | 0.000 | 6.250 | clk25_ibuf/I | clk25 | u_Gowin_rPLL_MCU/rpll_inst/CLKOUT |
| u_Gowin_rPLL_MCU/rpll_inst/CLKOUTP.default_gen_clk | Generated | 12.500 | 80.0 | 0.000 | 6.250 | clk25_ibuf/I | clk25 | u_Gowin_rPLL_MCU/rpll_inst/CLKOUTP |
| u_Gowin_rPLL_MCU/rpll_inst/CLKOUTD.default_gen_clk | Generated | 25.000 | 40.0 | 0.000 | 12.500 | clk25_ibuf/I | clk25 | u_Gowin_rPLL_MCU/rpll_inst/CLKOUTD |
| u_Gowin_rPLL_MCU/rpll_inst/CLKOUTD3.default_gen_clk | Generated | 37.500 | 26.7 | 0.000 | 18.750 | clk25_ibuf/I | clk25 | u_Gowin_rPLL_MCU/rpll_inst/CLKOUTD3 |
Max Frequency Summary:
| No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | clk25 | 25.0(MHz) | 355.0(MHz) | 4 | TOP |
| 2 | mii_rx_clk_0 | 100.0(MHz) | 162.7(MHz) | 9 | TOP |
| 3 | mii_rx_clk_1 | 100.0(MHz) | 141.5(MHz) | 10 | TOP |
| 4 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/HCLK_ibuf/I | 100.0(MHz) | 110.4(MHz) | 14 | TOP |
| 5 | u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk | 100.0(MHz) | 155.8(MHz) | 9 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 0.945 |
| Data Arrival Time | 9.883 |
| Data Required Time | 10.828 |
| From | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0 |
| To | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/biu_commit_reg_s0 |
| Launch Clk | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/HCLK_ibuf/I[R] |
| Latch Clk | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/HCLK_ibuf/I[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/HCLK_ibuf/I | |||
| 0.000 | 0.000 | tCL | RR | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/HCLK_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 1449 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/HCLK_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/CLK |
| 1.095 | 0.232 | tC2Q | RF | 8 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/Q |
| 1.332 | 0.237 | tNET | FF | 4 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/RAD[0] |
| 1.849 | 0.517 | tINS | FF | 8 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/DO[2] |
| 2.086 | 0.237 | tNET | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/I0 |
| 2.602 | 0.517 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/F |
| 2.839 | 0.237 | tNET | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/I1 |
| 3.395 | 0.555 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/F |
| 3.632 | 0.237 | tNET | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/I1 |
| 4.187 | 0.555 | tINS | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/F |
| 4.424 | 0.237 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/I1 |
| 4.994 | 0.570 | tINS | FR | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/COUT |
| 4.994 | 0.000 | tNET | RR | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/CIN |
| 5.029 | 0.035 | tINS | RF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/COUT |
| 5.029 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/CIN |
| 5.064 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/COUT |
| 5.064 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/CIN |
| 5.099 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/COUT |
| 5.099 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/CIN |
| 5.134 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/COUT |
| 5.134 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/CIN |
| 5.170 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/COUT |
| 5.170 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/CIN |
| 5.205 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/COUT |
| 5.205 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/CIN |
| 5.240 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/COUT |
| 5.240 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/CIN |
| 5.275 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/COUT |
| 5.275 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/CIN |
| 5.310 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/COUT |
| 5.310 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/CIN |
| 5.346 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/COUT |
| 5.346 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/CIN |
| 5.381 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/COUT |
| 5.381 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/CIN |
| 5.416 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/COUT |
| 5.416 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/CIN |
| 5.451 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/COUT |
| 5.451 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/CIN |
| 5.486 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/COUT |
| 5.486 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/CIN |
| 5.522 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/COUT |
| 5.522 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/CIN |
| 5.557 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/COUT |
| 5.557 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_19_s/CIN |
| 5.592 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_19_s/COUT |
| 5.592 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_20_s/CIN |
| 5.627 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_20_s/COUT |
| 5.627 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_21_s/CIN |
| 5.662 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_21_s/COUT |
| 5.662 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_22_s/CIN |
| 5.698 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_22_s/COUT |
| 5.698 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_23_s/CIN |
| 5.733 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_23_s/COUT |
| 5.733 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_24_s/CIN |
| 5.768 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_24_s/COUT |
| 5.768 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_25_s/CIN |
| 6.238 | 0.470 | tINS | FF | 4 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_25_s/SUM |
| 6.475 | 0.237 | tNET | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s9/I1 |
| 7.030 | 0.555 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s9/F |
| 7.267 | 0.237 | tNET | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s7/I3 |
| 7.638 | 0.371 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s7/F |
| 7.875 | 0.237 | tNET | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s1/I3 |
| 8.246 | 0.371 | tINS | FF | 3 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s1/F |
| 8.483 | 0.237 | tNET | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/biu_commit_Z_s3/I1 |
| 9.038 | 0.555 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/biu_commit_Z_s3/F |
| 9.275 | 0.237 | tNET | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/biu_commit_Z_s/I3 |
| 9.646 | 0.371 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/biu_commit_Z_s/F |
| 9.883 | 0.237 | tNET | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/biu_commit_reg_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/HCLK_ibuf/I | |||
| 10.000 | 0.000 | tCL | RR | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/HCLK_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 1449 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/HCLK_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/biu_commit_reg_s0/CLK |
| 10.828 | -0.035 | tSu | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/biu_commit_reg_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 14 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 6.181, 68.527%; route: 2.607, 28.901%; tC2Q: 0.232, 2.572% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 2
Path Summary:| Slack | 1.047 |
| Data Arrival Time | 9.781 |
| Data Required Time | 10.828 |
| From | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0 |
| To | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/dtcm_sel_s0 |
| Launch Clk | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/HCLK_ibuf/I[R] |
| Latch Clk | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/HCLK_ibuf/I[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/HCLK_ibuf/I | |||
| 0.000 | 0.000 | tCL | RR | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/HCLK_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 1449 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/HCLK_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/CLK |
| 1.095 | 0.232 | tC2Q | RF | 8 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/Q |
| 1.332 | 0.237 | tNET | FF | 4 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/RAD[0] |
| 1.849 | 0.517 | tINS | FF | 8 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/DO[2] |
| 2.086 | 0.237 | tNET | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/I0 |
| 2.602 | 0.517 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/F |
| 2.839 | 0.237 | tNET | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/I1 |
| 3.395 | 0.555 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/F |
| 3.632 | 0.237 | tNET | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/I1 |
| 4.187 | 0.555 | tINS | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/F |
| 4.424 | 0.237 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/I1 |
| 4.994 | 0.570 | tINS | FR | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/COUT |
| 4.994 | 0.000 | tNET | RR | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/CIN |
| 5.029 | 0.035 | tINS | RF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/COUT |
| 5.029 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/CIN |
| 5.064 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/COUT |
| 5.064 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/CIN |
| 5.099 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/COUT |
| 5.099 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/CIN |
| 5.134 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/COUT |
| 5.134 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/CIN |
| 5.170 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/COUT |
| 5.170 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/CIN |
| 5.205 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/COUT |
| 5.205 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/CIN |
| 5.240 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/COUT |
| 5.240 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/CIN |
| 5.275 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/COUT |
| 5.275 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/CIN |
| 5.310 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/COUT |
| 5.310 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/CIN |
| 5.346 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/COUT |
| 5.346 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/CIN |
| 5.381 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/COUT |
| 5.381 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/CIN |
| 5.416 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/COUT |
| 5.416 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/CIN |
| 5.451 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/COUT |
| 5.451 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/CIN |
| 5.486 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/COUT |
| 5.486 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/CIN |
| 5.522 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/COUT |
| 5.522 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/CIN |
| 5.557 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/COUT |
| 5.557 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_19_s/CIN |
| 5.592 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_19_s/COUT |
| 5.592 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_20_s/CIN |
| 5.627 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_20_s/COUT |
| 5.627 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_21_s/CIN |
| 5.662 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_21_s/COUT |
| 5.662 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_22_s/CIN |
| 5.698 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_22_s/COUT |
| 5.698 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_23_s/CIN |
| 5.733 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_23_s/COUT |
| 5.733 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_24_s/CIN |
| 5.768 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_24_s/COUT |
| 5.768 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_25_s/CIN |
| 6.238 | 0.470 | tINS | FF | 4 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_25_s/SUM |
| 6.475 | 0.237 | tNET | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s9/I1 |
| 7.030 | 0.555 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s9/F |
| 7.267 | 0.237 | tNET | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s7/I3 |
| 7.638 | 0.371 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s7/F |
| 7.875 | 0.237 | tNET | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s1/I3 |
| 8.246 | 0.371 | tINS | FF | 3 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s1/F |
| 8.483 | 0.237 | tNET | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_itcm_sel_s2/I3 |
| 8.854 | 0.371 | tINS | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_itcm_sel_s2/F |
| 9.091 | 0.237 | tNET | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_dtcm_sel_s0/I2 |
| 9.544 | 0.453 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_dtcm_sel_s0/F |
| 9.781 | 0.237 | tNET | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/dtcm_sel_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/HCLK_ibuf/I | |||
| 10.000 | 0.000 | tCL | RR | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/HCLK_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 1449 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/HCLK_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/dtcm_sel_s0/CLK |
| 10.828 | -0.035 | tSu | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/dtcm_sel_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 14 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 6.079, 68.167%; route: 2.607, 29.232%; tC2Q: 0.232, 2.601% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 3
Path Summary:| Slack | 1.047 |
| Data Arrival Time | 9.781 |
| Data Required Time | 10.828 |
| From | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0 |
| To | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/itcm_sel_s0 |
| Launch Clk | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/HCLK_ibuf/I[R] |
| Latch Clk | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/HCLK_ibuf/I[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/HCLK_ibuf/I | |||
| 0.000 | 0.000 | tCL | RR | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/HCLK_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 1449 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/HCLK_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/CLK |
| 1.095 | 0.232 | tC2Q | RF | 8 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/Q |
| 1.332 | 0.237 | tNET | FF | 4 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/RAD[0] |
| 1.849 | 0.517 | tINS | FF | 8 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/DO[2] |
| 2.086 | 0.237 | tNET | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/I0 |
| 2.602 | 0.517 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/F |
| 2.839 | 0.237 | tNET | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/I1 |
| 3.395 | 0.555 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/F |
| 3.632 | 0.237 | tNET | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/I1 |
| 4.187 | 0.555 | tINS | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/F |
| 4.424 | 0.237 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/I1 |
| 4.994 | 0.570 | tINS | FR | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/COUT |
| 4.994 | 0.000 | tNET | RR | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/CIN |
| 5.029 | 0.035 | tINS | RF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/COUT |
| 5.029 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/CIN |
| 5.064 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/COUT |
| 5.064 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/CIN |
| 5.099 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/COUT |
| 5.099 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/CIN |
| 5.134 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/COUT |
| 5.134 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/CIN |
| 5.170 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/COUT |
| 5.170 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/CIN |
| 5.205 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/COUT |
| 5.205 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/CIN |
| 5.240 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/COUT |
| 5.240 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/CIN |
| 5.275 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/COUT |
| 5.275 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/CIN |
| 5.310 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/COUT |
| 5.310 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/CIN |
| 5.346 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/COUT |
| 5.346 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/CIN |
| 5.381 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/COUT |
| 5.381 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/CIN |
| 5.416 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/COUT |
| 5.416 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/CIN |
| 5.451 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/COUT |
| 5.451 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/CIN |
| 5.486 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/COUT |
| 5.486 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/CIN |
| 5.522 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/COUT |
| 5.522 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/CIN |
| 5.557 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/COUT |
| 5.557 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_19_s/CIN |
| 5.592 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_19_s/COUT |
| 5.592 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_20_s/CIN |
| 5.627 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_20_s/COUT |
| 5.627 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_21_s/CIN |
| 5.662 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_21_s/COUT |
| 5.662 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_22_s/CIN |
| 5.698 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_22_s/COUT |
| 5.698 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_23_s/CIN |
| 5.733 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_23_s/COUT |
| 5.733 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_24_s/CIN |
| 5.768 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_24_s/COUT |
| 5.768 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_25_s/CIN |
| 6.238 | 0.470 | tINS | FF | 4 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_25_s/SUM |
| 6.475 | 0.237 | tNET | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s9/I1 |
| 7.030 | 0.555 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s9/F |
| 7.267 | 0.237 | tNET | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s7/I3 |
| 7.638 | 0.371 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s7/F |
| 7.875 | 0.237 | tNET | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s1/I3 |
| 8.246 | 0.371 | tINS | FF | 3 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s1/F |
| 8.483 | 0.237 | tNET | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_itcm_sel_s2/I3 |
| 8.854 | 0.371 | tINS | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_itcm_sel_s2/F |
| 9.091 | 0.237 | tNET | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_itcm_sel_s0/I2 |
| 9.544 | 0.453 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_itcm_sel_s0/F |
| 9.781 | 0.237 | tNET | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/itcm_sel_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/HCLK_ibuf/I | |||
| 10.000 | 0.000 | tCL | RR | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/HCLK_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 1449 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/HCLK_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/itcm_sel_s0/CLK |
| 10.828 | -0.035 | tSu | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/itcm_sel_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 14 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 6.079, 68.167%; route: 2.607, 29.232%; tC2Q: 0.232, 2.601% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 4
Path Summary:| Slack | 1.057 |
| Data Arrival Time | 9.771 |
| Data Required Time | 10.828 |
| From | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0 |
| To | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/z_flag_mux_s0 |
| Launch Clk | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/HCLK_ibuf/I[R] |
| Latch Clk | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/HCLK_ibuf/I[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/HCLK_ibuf/I | |||
| 0.000 | 0.000 | tCL | RR | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/HCLK_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 1449 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/HCLK_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/CLK |
| 1.095 | 0.232 | tC2Q | RF | 8 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/Q |
| 1.332 | 0.237 | tNET | FF | 4 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/RAD[0] |
| 1.849 | 0.517 | tINS | FF | 8 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/DO[2] |
| 2.086 | 0.237 | tNET | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/I0 |
| 2.602 | 0.517 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/F |
| 2.839 | 0.237 | tNET | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/I1 |
| 3.395 | 0.555 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/F |
| 3.632 | 0.237 | tNET | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/I1 |
| 4.187 | 0.555 | tINS | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/F |
| 4.424 | 0.237 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/I1 |
| 4.994 | 0.570 | tINS | FR | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/COUT |
| 4.994 | 0.000 | tNET | RR | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/CIN |
| 5.029 | 0.035 | tINS | RF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/COUT |
| 5.029 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/CIN |
| 5.064 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/COUT |
| 5.064 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/CIN |
| 5.099 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/COUT |
| 5.099 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/CIN |
| 5.134 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/COUT |
| 5.134 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/CIN |
| 5.170 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/COUT |
| 5.170 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/CIN |
| 5.205 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/COUT |
| 5.205 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/CIN |
| 5.240 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/COUT |
| 5.240 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/CIN |
| 5.275 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/COUT |
| 5.275 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/CIN |
| 5.310 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/COUT |
| 5.310 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/CIN |
| 5.346 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/COUT |
| 5.346 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/CIN |
| 5.381 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/COUT |
| 5.381 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/CIN |
| 5.416 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/COUT |
| 5.416 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/CIN |
| 5.451 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/COUT |
| 5.451 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/CIN |
| 5.486 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/COUT |
| 5.486 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/CIN |
| 5.522 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/COUT |
| 5.522 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/CIN |
| 5.557 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/COUT |
| 5.557 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_19_s/CIN |
| 5.592 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_19_s/COUT |
| 5.592 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_20_s/CIN |
| 5.627 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_20_s/COUT |
| 5.627 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_21_s/CIN |
| 5.662 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_21_s/COUT |
| 5.662 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_22_s/CIN |
| 5.698 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_22_s/COUT |
| 5.698 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_23_s/CIN |
| 5.733 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_23_s/COUT |
| 5.733 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_24_s/CIN |
| 5.768 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_24_s/COUT |
| 5.768 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_25_s/CIN |
| 6.238 | 0.470 | tINS | FF | 4 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_25_s/SUM |
| 6.475 | 0.237 | tNET | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s9/I1 |
| 7.030 | 0.555 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s9/F |
| 7.267 | 0.237 | tNET | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s7/I3 |
| 7.638 | 0.371 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s7/F |
| 7.875 | 0.237 | tNET | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s1/I3 |
| 8.246 | 0.371 | tINS | FF | 3 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s1/F |
| 8.483 | 0.237 | tNET | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/nxt_z_flag_mux_s8/I3 |
| 8.854 | 0.371 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/nxt_z_flag_mux_s8/F |
| 9.091 | 0.237 | tNET | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/nxt_z_flag_mux_s6/I0 |
| 9.194 | 0.103 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/nxt_z_flag_mux_s6/O |
| 9.431 | 0.237 | tNET | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/nxt_z_flag_mux_s3/I0 |
| 9.534 | 0.103 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/nxt_z_flag_mux_s3/O |
| 9.771 | 0.237 | tNET | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/z_flag_mux_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/HCLK_ibuf/I | |||
| 10.000 | 0.000 | tCL | RR | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/HCLK_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 1449 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/HCLK_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/z_flag_mux_s0/CLK |
| 10.828 | -0.035 | tSu | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/z_flag_mux_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 14 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 5.832, 65.471%; route: 2.844, 31.925%; tC2Q: 0.232, 2.604% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 5
Path Summary:| Slack | 2.274 |
| Data Arrival Time | 8.554 |
| Data Required Time | 10.828 |
| From | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_ahb/HADDR_31_s0 |
| To | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uInputStage0/PendTranReg_s1 |
| Launch Clk | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/HCLK_ibuf/I[R] |
| Latch Clk | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/HCLK_ibuf/I[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/HCLK_ibuf/I | |||
| 0.000 | 0.000 | tCL | RR | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/HCLK_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 1449 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/HCLK_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_ahb/HADDR_31_s0/CLK |
| 1.095 | 0.232 | tC2Q | RF | 4 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_ahb/HADDR_31_s0/Q |
| 1.332 | 0.237 | tNET | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage6/uOutputArb/NoPortNext_s5/I1 |
| 1.887 | 0.555 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage6/uOutputArb/NoPortNext_s5/F |
| 2.124 | 0.237 | tNET | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage6/uOutputArb/NoPortNext_s3/I3 |
| 2.495 | 0.371 | tINS | FF | 4 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage6/uOutputArb/NoPortNext_s3/F |
| 2.732 | 0.237 | tNET | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage2/AHB2HSEL_s2/I2 |
| 3.185 | 0.453 | tINS | FF | 7 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage2/AHB2HSEL_s2/F |
| 3.422 | 0.237 | tNET | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage2/AHB2HSEL_s0/I2 |
| 3.875 | 0.453 | tINS | FF | 4 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage2/AHB2HSEL_s0/F |
| 4.112 | 0.237 | tNET | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uMatrixDecodeS0/AddrOutPort_0_s3/I1 |
| 4.667 | 0.555 | tINS | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uMatrixDecodeS0/AddrOutPort_0_s3/F |
| 4.904 | 0.237 | tNET | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uMatrixDecodeS0/AddrOutPort_0_s4/I3 |
| 5.274 | 0.371 | tINS | FF | 13 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uMatrixDecodeS0/AddrOutPort_0_s4/F |
| 5.511 | 0.237 | tNET | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage8/Active0to8_s7/I2 |
| 5.964 | 0.453 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage8/Active0to8_s7/F |
| 6.201 | 0.237 | tNET | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage8/Active0to8_s2/I1 |
| 6.305 | 0.103 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage8/Active0to8_s2/O |
| 6.542 | 0.237 | tNET | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage8/Active0to8_s0/I0 |
| 6.645 | 0.103 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage8/Active0to8_s0/O |
| 6.882 | 0.237 | tNET | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage8/Active0to8_s/I0 |
| 6.985 | 0.103 | tINS | FF | 2 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage8/Active0to8_s/O |
| 7.222 | 0.237 | tNET | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uInputStage0/n115_s1/I2 |
| 7.675 | 0.453 | tINS | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uInputStage0/n115_s1/F |
| 7.912 | 0.237 | tNET | FF | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uInputStage0/PendTranReg_s3/I2 |
| 8.374 | 0.462 | tINS | FR | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uInputStage0/PendTranReg_s3/F |
| 8.554 | 0.180 | tNET | RR | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uInputStage0/PendTranReg_s1/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/HCLK_ibuf/I | |||
| 10.000 | 0.000 | tCL | RR | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/HCLK_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 1449 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/HCLK_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uInputStage0/PendTranReg_s1/CLK |
| 10.828 | -0.035 | tSu | 1 | u_Gowin_EMPU_M1_template/u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uInputStage0/PendTranReg_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 11 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 4.435, 57.664%; route: 3.024, 39.319%; tC2Q: 0.232, 3.017% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |