Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | C:\Gowin\pacth\Gowin\Gowin_V1.9.8.11\IDE\ipcore\IES\data\GW_IES.v C:\Gowin\pacth\Gowin\Gowin_V1.9.8.11\IDE\ipcore\IES\data\GW_IES_Top.v |
GowinSynthesis Constraints File | --- |
Version | V1.9.8.11 |
Part Number | GW2A-LV55PG484C8/I7 |
Device | GW2A-55 |
Device Version | C |
Created Time | Fri Mar 31 16:00:58 2023 |
Legal Announcement | Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | IES_Top |
Synthesis Process | Running parser: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 129.070MB Running netlist conversion: CPU time = 0h 0m 0.281s, Elapsed time = 0h 0m 0.285s, Peak memory usage = 129.070MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 129.070MB Optimizing Phase 1: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 129.070MB Optimizing Phase 2: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 129.070MB Running inference: Inferring Phase 0: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 129.070MB Inferring Phase 1: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.062s, Peak memory usage = 129.070MB Inferring Phase 2: CPU time = 0h 0m 0.312s, Elapsed time = 0h 0m 0.321s, Peak memory usage = 129.070MB Inferring Phase 3: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.074s, Peak memory usage = 129.070MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 129.070MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.562s, Elapsed time = 0h 0m 0.577s, Peak memory usage = 129.070MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.718s, Elapsed time = 0h 0m 0.727s, Peak memory usage = 129.070MB Tech-Mapping Phase 3: CPU time = 0h 0m 33s, Elapsed time = 0h 0m 34s, Peak memory usage = 138.414MB Tech-Mapping Phase 4: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 138.414MB Generate output files: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 199.430MB |
Total Time and Memory Usage | CPU time = 0h 0m 49s, Elapsed time = 0h 0m 50s, Peak memory usage = 199.430MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 151 |
I/O Buf | 151 |
    IBUF | 93 |
    OBUF | 57 |
    TBUF | 1 |
Register | 13018 |
    DFF | 118 |
    DFFE | 187 |
    DFFSE | 6 |
    DFFR | 204 |
    DFFRE | 31 |
    DFFP | 29 |
    DFFPE | 203 |
    DFFC | 6142 |
    DFFCE | 6098 |
LUT | 11662 |
    LUT2 | 1507 |
    LUT3 | 3935 |
    LUT4 | 6220 |
ALU | 2524 |
    ALU | 2524 |
SSRAM | 33 |
    RAM16S4 | 33 |
INV | 45 |
    INV | 45 |
BSRAM | 7 |
    SDPB | 2 |
    DPB | 5 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 14429(11707 LUTs, 2524 ALUs, 33 SSRAMs) / 54720 | 27% |
Register | 13018 / 41997 | 31% |
  --Register as Latch | 0 / 41997 | 0% |
  --Register as FF | 13018 / 41997 | 31% |
BSRAM | 7 / 140 | 5% |
Timing
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|
clk100 | Base | 10.000 | 100.0 | 0.000 | 5.000 | clk100_ibuf/I | ||
mii_rx_clk_0 | Base | 10.000 | 100.0 | 0.000 | 5.000 | mii_rx_clk_0_ibuf/I | ||
mii_rx_clk_1 | Base | 10.000 | 100.0 | 0.000 | 5.000 | mii_rx_clk_1_ibuf/I | ||
HCLK | Base | 10.000 | 100.0 | 0.000 | 5.000 | HCLK_ibuf/I |
Max Frequency Summary:
No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | clk100 | 100.0(MHz) | 155.8(MHz) | 9 | TOP |
2 | mii_rx_clk_0 | 100.0(MHz) | 162.7(MHz) | 9 | TOP |
3 | mii_rx_clk_1 | 100.0(MHz) | 141.5(MHz) | 10 | TOP |
4 | HCLK | 100.0(MHz) | 291.5(MHz) | 5 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | 2.934 |
Data Arrival Time | 7.894 |
Data Required Time | 10.828 |
From | IES_inst/u_rx_top/u_mii_rx_1/frmlen_cnt_8_s3 |
To | IES_inst/u_rx_top/u_mii_rx_1/c_state_6_s0 |
Launch Clk | mii_rx_clk_1[R] |
Latch Clk | mii_rx_clk_1[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | mii_rx_clk_1 | |||
0.000 | 0.000 | tCL | RR | 1 | mii_rx_clk_1_ibuf/I |
0.683 | 0.683 | tINS | RR | 303 | mii_rx_clk_1_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | IES_inst/u_rx_top/u_mii_rx_1/frmlen_cnt_8_s3/CLK |
1.095 | 0.232 | tC2Q | RF | 5 | IES_inst/u_rx_top/u_mii_rx_1/frmlen_cnt_8_s3/Q |
1.332 | 0.237 | tNET | FF | 1 | IES_inst/u_rx_top/u_mii_rx_1/n891_s2/I1 |
1.887 | 0.555 | tINS | FF | 9 | IES_inst/u_rx_top/u_mii_rx_1/n891_s2/F |
2.124 | 0.237 | tNET | FF | 1 | IES_inst/u_rx_top/u_mii_rx_1/n584_s1/I1 |
2.679 | 0.555 | tINS | FF | 7 | IES_inst/u_rx_top/u_mii_rx_1/n584_s1/F |
2.916 | 0.237 | tNET | FF | 1 | IES_inst/u_rx_top/u_mii_rx_1/n567_s3/I1 |
3.471 | 0.555 | tINS | FF | 2 | IES_inst/u_rx_top/u_mii_rx_1/n567_s3/F |
3.708 | 0.237 | tNET | FF | 1 | IES_inst/u_rx_top/u_mii_rx_1/n567_s0/I3 |
4.079 | 0.371 | tINS | FF | 1 | IES_inst/u_rx_top/u_mii_rx_1/n567_s0/F |
4.316 | 0.237 | tNET | FF | 1 | IES_inst/u_rx_top/u_mii_rx_1/n587_s4/I2 |
4.769 | 0.453 | tINS | FF | 2 | IES_inst/u_rx_top/u_mii_rx_1/n587_s4/F |
5.006 | 0.237 | tNET | FF | 1 | IES_inst/u_rx_top/u_mii_rx_1/n588_s4/I0 |
5.523 | 0.517 | tINS | FF | 1 | IES_inst/u_rx_top/u_mii_rx_1/n588_s4/F |
5.760 | 0.237 | tNET | FF | 1 | IES_inst/u_rx_top/u_mii_rx_1/n_state_6_s10/I0 |
6.277 | 0.517 | tINS | FF | 1 | IES_inst/u_rx_top/u_mii_rx_1/n_state_6_s10/F |
6.514 | 0.237 | tNET | FF | 1 | IES_inst/u_rx_top/u_mii_rx_1/n_state_6_s8/I2 |
6.967 | 0.453 | tINS | FF | 1 | IES_inst/u_rx_top/u_mii_rx_1/n_state_6_s8/F |
7.204 | 0.237 | tNET | FF | 1 | IES_inst/u_rx_top/u_mii_rx_1/n_state_6_s6/I2 |
7.657 | 0.453 | tINS | FF | 1 | IES_inst/u_rx_top/u_mii_rx_1/n_state_6_s6/F |
7.894 | 0.237 | tNET | FF | 1 | IES_inst/u_rx_top/u_mii_rx_1/c_state_6_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | mii_rx_clk_1 | |||
10.000 | 0.000 | tCL | RR | 1 | mii_rx_clk_1_ibuf/I |
10.682 | 0.683 | tINS | RR | 303 | mii_rx_clk_1_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | IES_inst/u_rx_top/u_mii_rx_1/c_state_6_s0/CLK |
10.828 | -0.035 | tSu | 1 | IES_inst/u_rx_top/u_mii_rx_1/c_state_6_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 10 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 4.429, 62.992%; route: 2.370, 33.708%; tC2Q: 0.232, 3.300% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 2
Path Summary:Slack | 3.580 |
Data Arrival Time | 7.247 |
Data Required Time | 10.828 |
From | IES_inst/u_frm_process/rdata_tmp0_1_s1 |
To | IES_inst/u_frm_process/map_result_data_7_s0 |
Launch Clk | clk100[R] |
Latch Clk | clk100[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk100 | |||
0.000 | 0.000 | tCL | RR | 1 | clk100_ibuf/I |
0.683 | 0.683 | tINS | RR | 12119 | clk100_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | IES_inst/u_frm_process/rdata_tmp0_1_s1/CLK |
1.095 | 0.232 | tC2Q | RF | 3 | IES_inst/u_frm_process/rdata_tmp0_1_s1/Q |
1.332 | 0.237 | tNET | FF | 1 | IES_inst/u_frm_process/n1558_s36/I1 |
1.887 | 0.555 | tINS | FF | 1 | IES_inst/u_frm_process/n1558_s36/F |
2.124 | 0.237 | tNET | FF | 1 | IES_inst/u_frm_process/n1558_s32/I0 |
2.227 | 0.103 | tINS | FF | 1 | IES_inst/u_frm_process/n1558_s32/O |
2.464 | 0.237 | tNET | FF | 1 | IES_inst/u_frm_process/n1558_s30/I0 |
2.566 | 0.103 | tINS | FF | 1 | IES_inst/u_frm_process/n1558_s30/O |
2.803 | 0.237 | tNET | FF | 1 | IES_inst/u_frm_process/n1558_s29/I0 |
2.906 | 0.103 | tINS | FF | 8 | IES_inst/u_frm_process/n1558_s29/O |
3.143 | 0.237 | tNET | FF | 1 | IES_inst/u_frm_process/n2039_s128/I0 |
3.660 | 0.517 | tINS | FF | 1 | IES_inst/u_frm_process/n2039_s128/F |
3.897 | 0.237 | tNET | FF | 1 | IES_inst/u_frm_process/n2039_s67/I0 |
4.414 | 0.517 | tINS | FF | 1 | IES_inst/u_frm_process/n2039_s67/F |
4.651 | 0.237 | tNET | FF | 1 | IES_inst/u_frm_process/n2039_s30/I3 |
5.022 | 0.371 | tINS | FF | 1 | IES_inst/u_frm_process/n2039_s30/F |
5.259 | 0.237 | tNET | FF | 1 | IES_inst/u_frm_process/n2039_s14/I3 |
5.630 | 0.371 | tINS | FF | 1 | IES_inst/u_frm_process/n2039_s14/F |
5.867 | 0.237 | tNET | FF | 1 | IES_inst/u_frm_process/n2039_s3/I2 |
6.320 | 0.453 | tINS | FF | 1 | IES_inst/u_frm_process/n2039_s3/F |
6.557 | 0.237 | tNET | FF | 1 | IES_inst/u_frm_process/n2039_s0/I2 |
7.010 | 0.453 | tINS | FF | 1 | IES_inst/u_frm_process/n2039_s0/F |
7.247 | 0.237 | tNET | FF | 1 | IES_inst/u_frm_process/map_result_data_7_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk100 | |||
10.000 | 0.000 | tCL | RR | 1 | clk100_ibuf/I |
10.682 | 0.683 | tINS | RR | 12119 | clk100_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | IES_inst/u_frm_process/map_result_data_7_s0/CLK |
10.828 | -0.035 | tSu | 1 | IES_inst/u_frm_process/map_result_data_7_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 9 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 3.546, 55.536%; route: 2.607, 40.830%; tC2Q: 0.232, 3.634% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 3
Path Summary:Slack | 3.624 |
Data Arrival Time | 7.204 |
Data Required Time | 10.828 |
From | IES_inst/u_rx_top/u_mii_rx_1/frmlen_cnt_8_s3 |
To | IES_inst/u_rx_top/u_mii_rx_1/c_state_7_s0 |
Launch Clk | mii_rx_clk_1[R] |
Latch Clk | mii_rx_clk_1[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | mii_rx_clk_1 | |||
0.000 | 0.000 | tCL | RR | 1 | mii_rx_clk_1_ibuf/I |
0.683 | 0.683 | tINS | RR | 303 | mii_rx_clk_1_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | IES_inst/u_rx_top/u_mii_rx_1/frmlen_cnt_8_s3/CLK |
1.095 | 0.232 | tC2Q | RF | 5 | IES_inst/u_rx_top/u_mii_rx_1/frmlen_cnt_8_s3/Q |
1.332 | 0.237 | tNET | FF | 1 | IES_inst/u_rx_top/u_mii_rx_1/n891_s2/I1 |
1.887 | 0.555 | tINS | FF | 9 | IES_inst/u_rx_top/u_mii_rx_1/n891_s2/F |
2.124 | 0.237 | tNET | FF | 1 | IES_inst/u_rx_top/u_mii_rx_1/n584_s1/I1 |
2.679 | 0.555 | tINS | FF | 7 | IES_inst/u_rx_top/u_mii_rx_1/n584_s1/F |
2.916 | 0.237 | tNET | FF | 1 | IES_inst/u_rx_top/u_mii_rx_1/n567_s3/I1 |
3.471 | 0.555 | tINS | FF | 2 | IES_inst/u_rx_top/u_mii_rx_1/n567_s3/F |
3.708 | 0.237 | tNET | FF | 1 | IES_inst/u_rx_top/u_mii_rx_1/n567_s0/I3 |
4.079 | 0.371 | tINS | FF | 1 | IES_inst/u_rx_top/u_mii_rx_1/n567_s0/F |
4.316 | 0.237 | tNET | FF | 1 | IES_inst/u_rx_top/u_mii_rx_1/n587_s4/I2 |
4.769 | 0.453 | tINS | FF | 2 | IES_inst/u_rx_top/u_mii_rx_1/n587_s4/F |
5.006 | 0.237 | tNET | FF | 1 | IES_inst/u_rx_top/u_mii_rx_1/n587_s3/I0 |
5.523 | 0.517 | tINS | FF | 1 | IES_inst/u_rx_top/u_mii_rx_1/n587_s3/F |
5.760 | 0.237 | tNET | FF | 1 | IES_inst/u_rx_top/u_mii_rx_1/n_state_7_s9/I0 |
6.277 | 0.517 | tINS | FF | 1 | IES_inst/u_rx_top/u_mii_rx_1/n_state_7_s9/F |
6.514 | 0.237 | tNET | FF | 1 | IES_inst/u_rx_top/u_mii_rx_1/n_state_7_s5/I2 |
6.967 | 0.453 | tINS | FF | 1 | IES_inst/u_rx_top/u_mii_rx_1/n_state_7_s5/F |
7.204 | 0.237 | tNET | FF | 1 | IES_inst/u_rx_top/u_mii_rx_1/c_state_7_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | mii_rx_clk_1 | |||
10.000 | 0.000 | tCL | RR | 1 | mii_rx_clk_1_ibuf/I |
10.682 | 0.683 | tINS | RR | 303 | mii_rx_clk_1_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | IES_inst/u_rx_top/u_mii_rx_1/c_state_7_s0/CLK |
10.828 | -0.035 | tSu | 1 | IES_inst/u_rx_top/u_mii_rx_1/c_state_7_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 9 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 3.976, 62.703%; route: 2.133, 33.638%; tC2Q: 0.232, 3.659% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 4
Path Summary:Slack | 3.654 |
Data Arrival Time | 7.174 |
Data Required Time | 10.828 |
From | IES_inst/u_frm_process/bit_wise_wdata_tmp_5_s0 |
To | IES_inst/u_frm_process/wbyte_digi_tmp_5_s0 |
Launch Clk | clk100[R] |
Latch Clk | clk100[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk100 | |||
0.000 | 0.000 | tCL | RR | 1 | clk100_ibuf/I |
0.683 | 0.683 | tINS | RR | 12119 | clk100_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | IES_inst/u_frm_process/bit_wise_wdata_tmp_5_s0/CLK |
1.095 | 0.232 | tC2Q | RF | 6 | IES_inst/u_frm_process/bit_wise_wdata_tmp_5_s0/Q |
1.332 | 0.237 | tNET | FF | 1 | IES_inst/u_frm_process/n2352_s18/I1 |
1.887 | 0.555 | tINS | FF | 1 | IES_inst/u_frm_process/n2352_s18/F |
2.124 | 0.237 | tNET | FF | 1 | IES_inst/u_frm_process/n2352_s15/I0 |
2.227 | 0.103 | tINS | FF | 1 | IES_inst/u_frm_process/n2352_s15/O |
2.464 | 0.237 | tNET | FF | 1 | IES_inst/u_frm_process/n2352_s13/I1 |
2.566 | 0.103 | tINS | FF | 13 | IES_inst/u_frm_process/n2352_s13/O |
2.803 | 0.237 | tNET | FF | 1 | IES_inst/u_frm_process/n3150_s17/I0 |
3.320 | 0.517 | tINS | FF | 3 | IES_inst/u_frm_process/n3150_s17/F |
3.557 | 0.237 | tNET | FF | 1 | IES_inst/u_frm_process/n3148_s22/I1 |
4.112 | 0.555 | tINS | FF | 1 | IES_inst/u_frm_process/n3148_s22/F |
4.349 | 0.237 | tNET | FF | 1 | IES_inst/u_frm_process/n3148_s17/I2 |
4.802 | 0.453 | tINS | FF | 1 | IES_inst/u_frm_process/n3148_s17/F |
5.039 | 0.237 | tNET | FF | 1 | IES_inst/u_frm_process/n3148_s7/I2 |
5.492 | 0.453 | tINS | FF | 1 | IES_inst/u_frm_process/n3148_s7/F |
5.729 | 0.237 | tNET | FF | 1 | IES_inst/u_frm_process/n3148_s3/I2 |
6.182 | 0.453 | tINS | FF | 1 | IES_inst/u_frm_process/n3148_s3/F |
6.419 | 0.237 | tNET | FF | 1 | IES_inst/u_frm_process/n3148_s2/I0 |
6.937 | 0.517 | tINS | FF | 1 | IES_inst/u_frm_process/n3148_s2/F |
7.174 | 0.237 | tNET | FF | 1 | IES_inst/u_frm_process/wbyte_digi_tmp_5_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk100 | |||
10.000 | 0.000 | tCL | RR | 1 | clk100_ibuf/I |
10.682 | 0.683 | tINS | RR | 12119 | clk100_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | IES_inst/u_frm_process/wbyte_digi_tmp_5_s0/CLK |
10.828 | -0.035 | tSu | 1 | IES_inst/u_frm_process/wbyte_digi_tmp_5_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 8 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 3.709, 58.771%; route: 2.370, 37.553%; tC2Q: 0.232, 3.676% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 5
Path Summary:Slack | 3.662 |
Data Arrival Time | 7.165 |
Data Required Time | 10.828 |
From | IES_inst/u_frm_process/rdata_tmp0_1_s1 |
To | IES_inst/u_frm_process/map_result_data_6_s0 |
Launch Clk | clk100[R] |
Latch Clk | clk100[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk100 | |||
0.000 | 0.000 | tCL | RR | 1 | clk100_ibuf/I |
0.683 | 0.683 | tINS | RR | 12119 | clk100_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | IES_inst/u_frm_process/rdata_tmp0_1_s1/CLK |
1.095 | 0.232 | tC2Q | RF | 3 | IES_inst/u_frm_process/rdata_tmp0_1_s1/Q |
1.332 | 0.237 | tNET | FF | 1 | IES_inst/u_frm_process/n1558_s36/I1 |
1.887 | 0.555 | tINS | FF | 1 | IES_inst/u_frm_process/n1558_s36/F |
2.124 | 0.237 | tNET | FF | 1 | IES_inst/u_frm_process/n1558_s32/I0 |
2.227 | 0.103 | tINS | FF | 1 | IES_inst/u_frm_process/n1558_s32/O |
2.464 | 0.237 | tNET | FF | 1 | IES_inst/u_frm_process/n1558_s30/I0 |
2.566 | 0.103 | tINS | FF | 1 | IES_inst/u_frm_process/n1558_s30/O |
2.803 | 0.237 | tNET | FF | 1 | IES_inst/u_frm_process/n1558_s29/I0 |
2.906 | 0.103 | tINS | FF | 8 | IES_inst/u_frm_process/n1558_s29/O |
3.143 | 0.237 | tNET | FF | 1 | IES_inst/u_frm_process/n2040_s28/I0 |
3.660 | 0.517 | tINS | FF | 1 | IES_inst/u_frm_process/n2040_s28/F |
3.897 | 0.237 | tNET | FF | 1 | IES_inst/u_frm_process/n2040_s27/I0 |
4.414 | 0.517 | tINS | FF | 1 | IES_inst/u_frm_process/n2040_s27/F |
4.651 | 0.237 | tNET | FF | 1 | IES_inst/u_frm_process/n2040_s22/I3 |
5.022 | 0.371 | tINS | FF | 1 | IES_inst/u_frm_process/n2040_s22/F |
5.259 | 0.237 | tNET | FF | 1 | IES_inst/u_frm_process/n2040_s14/I3 |
5.630 | 0.371 | tINS | FF | 1 | IES_inst/u_frm_process/n2040_s14/F |
5.867 | 0.237 | tNET | FF | 1 | IES_inst/u_frm_process/n2040_s3/I3 |
6.238 | 0.371 | tINS | FF | 1 | IES_inst/u_frm_process/n2040_s3/F |
6.475 | 0.237 | tNET | FF | 1 | IES_inst/u_frm_process/n2040_s0/I2 |
6.928 | 0.453 | tINS | FF | 1 | IES_inst/u_frm_process/n2040_s0/F |
7.165 | 0.237 | tNET | FF | 1 | IES_inst/u_frm_process/map_result_data_6_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk100 | |||
10.000 | 0.000 | tCL | RR | 1 | clk100_ibuf/I |
10.682 | 0.683 | tINS | RR | 12119 | clk100_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | IES_inst/u_frm_process/map_result_data_6_s0/CLK |
10.828 | -0.035 | tSu | 1 | IES_inst/u_frm_process/map_result_data_6_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 9 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 3.464, 54.958%; route: 2.607, 41.361%; tC2Q: 0.232, 3.681% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |