Timing Messages
Report Title | Timing Analysis Report |
Design File | E:\W_File\ISP_V2\Onboard_230320\Gowin_ISP_RefDesign_0423_keil_SRAM\Gowin_ISP_RefDesign\FPGA_Design\impl\gwsynthesis\isp_proj.vg |
Physical Constraints File | E:\W_File\ISP_V2\Onboard_230320\Gowin_ISP_RefDesign_0423_keil_SRAM\Gowin_ISP_RefDesign\FPGA_Design\src\isp_proj.cst |
Timing Constraint File | E:\W_File\ISP_V2\Onboard_230320\Gowin_ISP_RefDesign_0423_keil_SRAM\Gowin_ISP_RefDesign\FPGA_Design\src\isp_proj.sdc |
Version | V1.9.9 Beta3-1 |
Part Number | GW2A-LV55PG484C8/I7 |
Device | GW2A-55 |
Device Version | C |
Created Time | Tue Apr 25 14:35:05 2023 |
Legal Announcement | Copyright (C)2014-2023 Gowin Semiconductor Corporation. All rights reserved. |
Timing Summaries
STA Tool Run Summary:
Setup Delay Model | Slow 0.95V 85C C8/I7 |
Hold Delay Model | Fast 1.05V 0C C8/I7 |
Numbers of Paths Analyzed | 29052 |
Numbers of Endpoints Analyzed | 28090 |
Numbers of Falling Endpoints | 8 |
Numbers of Setup Violated Endpoints | 0 |
Numbers of Hold Violated Endpoints | 0 |
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Objects |
---|---|---|---|---|---|---|---|---|
LCD_DCLK_d | Base | 30.000 | 33.333 | 0.000 | 15.000 | LCD_DCLK_d | ||
I_clk | Base | 20.000 | 50.000 | 0.000 | 10.000 | I_clk | ||
csi_clk | Base | 6.250 | 160.000 | 0.000 | 3.125 | csi_clk | ||
I_CSI_CKP | Base | 3.125 | 320.000 | 0.000 | 1.562 | I_CSI_CKP | ||
dma_clk | Base | 13.333 | 75.002 | 0.000 | 6.667 | dma_clk | ||
ddr3_clk | Base | 3.333 | 300.030 | 0.000 | 1.667 | ddr3_clk | ||
byte_clk | Base | 12.500 | 80.000 | 0.000 | 6.250 | CSI2RAW8_inst/byte_clk | ||
ddr_rst | Base | 10.000 | 100.000 | 0.000 | 5.000 | DDR3_Memory_Interface_Top_inst/gw3_top/ddr_rst | ||
pixel_pll/rpll_inst/CLKOUTP.default_gen_clk | Generated | 30.000 | 33.333 | 0.000 | 15.000 | gowin_ibuf_I_clk/I | I_clk | pixel_pll/rpll_inst/CLKOUTP |
pixel_pll/rpll_inst/CLKOUTD.default_gen_clk | Generated | 60.000 | 16.667 | 0.000 | 30.000 | gowin_ibuf_I_clk/I | I_clk | pixel_pll/rpll_inst/CLKOUTD |
pixel_pll/rpll_inst/CLKOUTD3.default_gen_clk | Generated | 90.000 | 11.111 | 0.000 | 45.000 | gowin_ibuf_I_clk/I | I_clk | pixel_pll/rpll_inst/CLKOUTD3 |
ddr3_pll/rpll_inst/CLKOUTP.default_gen_clk | Generated | 3.333 | 300.000 | 0.000 | 1.667 | gowin_ibuf_I_clk/I | I_clk | ddr3_pll/rpll_inst/CLKOUTP |
ddr3_pll/rpll_inst/CLKOUTD.default_gen_clk | Generated | 6.667 | 150.000 | 0.000 | 3.333 | gowin_ibuf_I_clk/I | I_clk | ddr3_pll/rpll_inst/CLKOUTD |
ddr3_pll/rpll_inst/CLKOUTD3.default_gen_clk | Generated | 10.000 | 100.000 | 0.000 | 5.000 | gowin_ibuf_I_clk/I | I_clk | ddr3_pll/rpll_inst/CLKOUTD3 |
CSI2RAW8_inst/pll/pll_inst/CLKOUTP.default_gen_clk | Generated | 6.250 | 160.000 | 1.563 | 4.688 | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT | byte_clk | CSI2RAW8_inst/pll/pll_inst/CLKOUTP |
CSI2RAW8_inst/pll/pll_inst/CLKOUTD.default_gen_clk | Generated | 12.500 | 80.000 | 0.000 | 6.250 | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT | byte_clk | CSI2RAW8_inst/pll/pll_inst/CLKOUTD |
CSI2RAW8_inst/pll/pll_inst/CLKOUTD3.default_gen_clk | Generated | 18.750 | 53.333 | 0.000 | 9.375 | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT | byte_clk | CSI2RAW8_inst/pll/pll_inst/CLKOUTD3 |
Max Frequency Summary:
NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | LCD_DCLK_d | 33.333(MHz) | 133.047(MHz) | 8 | TOP |
2 | I_clk | 50.000(MHz) | 72.849(MHz) | 15 | TOP |
3 | dma_clk | 75.002(MHz) | 100.573(MHz) | 8 | TOP |
4 | ddr3_clk | 300.030(MHz) | 2016.129(MHz) | 1 | TOP |
5 | byte_clk | 80.000(MHz) | 138.491(MHz) | 7 | TOP |
6 | ddr_rst | 100.000(MHz) | 782.609(MHz) | 2 | TOP |
No timing paths to get frequency of csi_clk!
No timing paths to get frequency of I_CSI_CKP!
No timing paths to get frequency of pixel_pll/rpll_inst/CLKOUTP.default_gen_clk!
No timing paths to get frequency of pixel_pll/rpll_inst/CLKOUTD.default_gen_clk!
No timing paths to get frequency of pixel_pll/rpll_inst/CLKOUTD3.default_gen_clk!
No timing paths to get frequency of ddr3_pll/rpll_inst/CLKOUTP.default_gen_clk!
No timing paths to get frequency of ddr3_pll/rpll_inst/CLKOUTD.default_gen_clk!
No timing paths to get frequency of ddr3_pll/rpll_inst/CLKOUTD3.default_gen_clk!
No timing paths to get frequency of CSI2RAW8_inst/pll/pll_inst/CLKOUTP.default_gen_clk!
No timing paths to get frequency of CSI2RAW8_inst/pll/pll_inst/CLKOUTD.default_gen_clk!
No timing paths to get frequency of CSI2RAW8_inst/pll/pll_inst/CLKOUTD3.default_gen_clk!
Total Negative Slack Summary:
Clock Name | Analysis Type | Endpoints TNS | Number of Endpoints |
---|---|---|---|
LCD_DCLK_d | Setup | 0.000 | 0 |
LCD_DCLK_d | Hold | 0.000 | 0 |
I_clk | Setup | 0.000 | 0 |
I_clk | Hold | 0.000 | 0 |
csi_clk | Setup | 0.000 | 0 |
csi_clk | Hold | 0.000 | 0 |
I_CSI_CKP | Setup | 0.000 | 0 |
I_CSI_CKP | Hold | 0.000 | 0 |
dma_clk | Setup | 0.000 | 0 |
dma_clk | Hold | 0.000 | 0 |
ddr3_clk | Setup | 0.000 | 0 |
ddr3_clk | Hold | 0.000 | 0 |
byte_clk | Setup | 0.000 | 0 |
byte_clk | Hold | 0.000 | 0 |
ddr_rst | Setup | 0.000 | 0 |
ddr_rst | Hold | 0.000 | 0 |
pixel_pll/rpll_inst/CLKOUTP.default_gen_clk | Setup | 0.000 | 0 |
pixel_pll/rpll_inst/CLKOUTP.default_gen_clk | Hold | 0.000 | 0 |
pixel_pll/rpll_inst/CLKOUTD.default_gen_clk | Setup | 0.000 | 0 |
pixel_pll/rpll_inst/CLKOUTD.default_gen_clk | Hold | 0.000 | 0 |
pixel_pll/rpll_inst/CLKOUTD3.default_gen_clk | Setup | 0.000 | 0 |
pixel_pll/rpll_inst/CLKOUTD3.default_gen_clk | Hold | 0.000 | 0 |
ddr3_pll/rpll_inst/CLKOUTP.default_gen_clk | Setup | 0.000 | 0 |
ddr3_pll/rpll_inst/CLKOUTP.default_gen_clk | Hold | 0.000 | 0 |
ddr3_pll/rpll_inst/CLKOUTD.default_gen_clk | Setup | 0.000 | 0 |
ddr3_pll/rpll_inst/CLKOUTD.default_gen_clk | Hold | 0.000 | 0 |
ddr3_pll/rpll_inst/CLKOUTD3.default_gen_clk | Setup | 0.000 | 0 |
ddr3_pll/rpll_inst/CLKOUTD3.default_gen_clk | Hold | 0.000 | 0 |
CSI2RAW8_inst/pll/pll_inst/CLKOUTP.default_gen_clk | Setup | 0.000 | 0 |
CSI2RAW8_inst/pll/pll_inst/CLKOUTP.default_gen_clk | Hold | 0.000 | 0 |
CSI2RAW8_inst/pll/pll_inst/CLKOUTD.default_gen_clk | Setup | 0.000 | 0 |
CSI2RAW8_inst/pll/pll_inst/CLKOUTD.default_gen_clk | Hold | 0.000 | 0 |
CSI2RAW8_inst/pll/pll_inst/CLKOUTD3.default_gen_clk | Setup | 0.000 | 0 |
CSI2RAW8_inst/pll/pll_inst/CLKOUTD3.default_gen_clk | Hold | 0.000 | 0 |
Timing Details
Path Slacks Table:
Setup Paths Table
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 2.837 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/RPOINT[2] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[7].u_ides8_mem/RADDR[2] | ddr3_clk:[R] | ddr3_clk:[R] | 3.333 | 0.000 | 0.496 |
2 | 2.837 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/RPOINT[1] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[7].u_ides8_mem/RADDR[1] | ddr3_clk:[R] | ddr3_clk:[R] | 3.333 | 0.000 | 0.496 |
3 | 2.837 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/RPOINT[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[7].u_ides8_mem/RADDR[0] | ddr3_clk:[R] | ddr3_clk:[R] | 3.333 | 0.000 | 0.496 |
4 | 2.837 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/RPOINT[2] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[6].u_ides8_mem/RADDR[2] | ddr3_clk:[R] | ddr3_clk:[R] | 3.333 | 0.000 | 0.496 |
5 | 2.837 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/RPOINT[1] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[6].u_ides8_mem/RADDR[1] | ddr3_clk:[R] | ddr3_clk:[R] | 3.333 | 0.000 | 0.496 |
6 | 2.837 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/RPOINT[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[6].u_ides8_mem/RADDR[0] | ddr3_clk:[R] | ddr3_clk:[R] | 3.333 | 0.000 | 0.496 |
7 | 2.837 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/RPOINT[2] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[5].u_ides8_mem/RADDR[2] | ddr3_clk:[R] | ddr3_clk:[R] | 3.333 | 0.000 | 0.496 |
8 | 2.837 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/RPOINT[1] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[5].u_ides8_mem/RADDR[1] | ddr3_clk:[R] | ddr3_clk:[R] | 3.333 | 0.000 | 0.496 |
9 | 2.837 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/RPOINT[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[5].u_ides8_mem/RADDR[0] | ddr3_clk:[R] | ddr3_clk:[R] | 3.333 | 0.000 | 0.496 |
10 | 2.837 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/RPOINT[2] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[4].u_ides8_mem/RADDR[2] | ddr3_clk:[R] | ddr3_clk:[R] | 3.333 | 0.000 | 0.496 |
11 | 2.837 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/RPOINT[1] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[4].u_ides8_mem/RADDR[1] | ddr3_clk:[R] | ddr3_clk:[R] | 3.333 | 0.000 | 0.496 |
12 | 2.837 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/RPOINT[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[4].u_ides8_mem/RADDR[0] | ddr3_clk:[R] | ddr3_clk:[R] | 3.333 | 0.000 | 0.496 |
13 | 2.837 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/RPOINT[2] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[3].u_ides8_mem/RADDR[2] | ddr3_clk:[R] | ddr3_clk:[R] | 3.333 | 0.000 | 0.496 |
14 | 2.837 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/RPOINT[1] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[3].u_ides8_mem/RADDR[1] | ddr3_clk:[R] | ddr3_clk:[R] | 3.333 | 0.000 | 0.496 |
15 | 2.837 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/RPOINT[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[3].u_ides8_mem/RADDR[0] | ddr3_clk:[R] | ddr3_clk:[R] | 3.333 | 0.000 | 0.496 |
16 | 2.837 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/RPOINT[2] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[2].u_ides8_mem/RADDR[2] | ddr3_clk:[R] | ddr3_clk:[R] | 3.333 | 0.000 | 0.496 |
17 | 2.837 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/RPOINT[1] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[2].u_ides8_mem/RADDR[1] | ddr3_clk:[R] | ddr3_clk:[R] | 3.333 | 0.000 | 0.496 |
18 | 2.837 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/RPOINT[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[2].u_ides8_mem/RADDR[0] | ddr3_clk:[R] | ddr3_clk:[R] | 3.333 | 0.000 | 0.496 |
19 | 2.837 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/RPOINT[2] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[1].u_ides8_mem/RADDR[2] | ddr3_clk:[R] | ddr3_clk:[R] | 3.333 | 0.000 | 0.496 |
20 | 2.837 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/RPOINT[1] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[1].u_ides8_mem/RADDR[1] | ddr3_clk:[R] | ddr3_clk:[R] | 3.333 | 0.000 | 0.496 |
21 | 2.837 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/RPOINT[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[1].u_ides8_mem/RADDR[0] | ddr3_clk:[R] | ddr3_clk:[R] | 3.333 | 0.000 | 0.496 |
22 | 2.837 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/RPOINT[2] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[0].u_ides8_mem/RADDR[2] | ddr3_clk:[R] | ddr3_clk:[R] | 3.333 | 0.000 | 0.496 |
23 | 2.837 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/RPOINT[1] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[0].u_ides8_mem/RADDR[1] | ddr3_clk:[R] | ddr3_clk:[R] | 3.333 | 0.000 | 0.496 |
24 | 2.837 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/RPOINT[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[0].u_ides8_mem/RADDR[0] | ddr3_clk:[R] | ddr3_clk:[R] | 3.333 | 0.000 | 0.496 |
25 | 2.837 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[0].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/RPOINT[2] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[0].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[7].u_ides8_mem/RADDR[2] | ddr3_clk:[R] | ddr3_clk:[R] | 3.333 | 0.000 | 0.496 |
Hold Paths Table
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 0.213 | CSI2RAW8_inst/u_control_capture/q_din2_5_s1/Q | CSI2RAW8_inst/u_raw8_lane2/u_fifo16b_8b/fifo_inst/mem_mem_0_0/DI[5] | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.462 |
2 | 0.213 | CSI2RAW8_inst/u_control_capture/q_din2_4_s1/Q | CSI2RAW8_inst/u_raw8_lane2/u_fifo16b_8b/fifo_inst/mem_mem_0_0/DI[4] | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.462 |
3 | 0.213 | CSI2RAW8_inst/u_control_capture/q_din2_3_s1/Q | CSI2RAW8_inst/u_raw8_lane2/u_fifo16b_8b/fifo_inst/mem_mem_0_0/DI[3] | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.462 |
4 | 0.213 | CSI2RAW8_inst/u_control_capture/q_din2_2_s1/Q | CSI2RAW8_inst/u_raw8_lane2/u_fifo16b_8b/fifo_inst/mem_mem_0_0/DI[2] | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.462 |
5 | 0.213 | CSI2RAW8_inst/u_control_capture/q_din2_1_s1/Q | CSI2RAW8_inst/u_raw8_lane2/u_fifo16b_8b/fifo_inst/mem_mem_0_0/DI[1] | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.462 |
6 | 0.217 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_fifo_ctrl/of_wbin_2_s0/Q | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[0].u_ddr3_phy_data_lane/u_out_fifo/mem4_mem4_0_1_s/ADA[7] | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 0.335 |
7 | 0.219 | Gowin_EMPU_M1_Top_inst/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApMst/HWDATAM_17_s0/Q | Gowin_EMPU_M1_Top_inst/M1_inst/u_CortexM1DbgIntegration_inst/u_itcm/mem2_mem2_0_0_s/DIA[1] | I_clk:[R] | I_clk:[R] | 0.000 | 0.000 | 0.468 |
8 | 0.224 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_fifo_ctrl/of_rbin_4_s0/Q | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[0].u_ddr3_phy_data_lane/u_out_fifo/mem4_mem4_0_1_s/ADB[9] | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 0.342 |
9 | 0.225 | CSI2RAW8_inst/u_control_capture/q_din2_12_s1/Q | CSI2RAW8_inst/u_raw8_lane2/u_fifo16b_8b/fifo_inst/mem_mem_0_0/DI[12] | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.474 |
10 | 0.225 | CSI2RAW8_inst/u_control_capture/q_din2_11_s1/Q | CSI2RAW8_inst/u_raw8_lane2/u_fifo16b_8b/fifo_inst/mem_mem_0_0/DI[11] | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.474 |
11 | 0.234 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/oserdes_d_reg_91_s0/Q | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen/D6 | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 0.329 |
12 | 0.234 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/oserdes_d_reg_90_s0/Q | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen/D4 | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 0.329 |
13 | 0.234 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/oserdes_d_reg_89_s0/Q | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen/D2 | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 0.329 |
14 | 0.234 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/oserdes_d_reg_83_s0/Q | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen/D6 | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 0.329 |
15 | 0.234 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/oserdes_d_reg_82_s0/Q | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen/D4 | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 0.329 |
16 | 0.234 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/oserdes_d_reg_81_s0/Q | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen/D2 | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 0.329 |
17 | 0.234 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/oserdes_d_reg_45_s0/Q | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[11].u_cmd_gen/D2 | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 0.329 |
18 | 0.234 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/oserdes_d_reg_44_s0/Q | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[11].u_cmd_gen/D0 | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 0.329 |
19 | 0.234 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/oserdes_d_reg_39_s0/Q | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[9].u_cmd_gen/D6 | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 0.329 |
20 | 0.234 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/oserdes_d_reg_38_s0/Q | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[9].u_cmd_gen/D4 | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 0.329 |
21 | 0.234 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/oserdes_d_reg_37_s0/Q | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[9].u_cmd_gen/D2 | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 0.329 |
22 | 0.234 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/oserdes_d_reg_36_s0/Q | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[9].u_cmd_gen/D0 | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 0.329 |
23 | 0.234 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/oserdes_d_reg_35_s0/Q | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[8].u_cmd_gen/D6 | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 0.329 |
24 | 0.234 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/oserdes_d_reg_34_s0/Q | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[8].u_cmd_gen/D4 | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 0.329 |
25 | 0.234 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/oserdes_d_reg_33_s0/Q | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[8].u_cmd_gen/D2 | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 0.329 |
Recovery Paths Table
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 3.997 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/n2610_s0/I1 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/read_reg_3_s4/CLEAR | ddr_rst:[R] | ddr_rst:[F] | 5.000 | -2.406 | 3.374 |
2 | 8.619 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q | vfb_top_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/dma_wr_baseaddr_23_s0/CLEAR | dma_clk:[R] | dma_clk:[R] | 13.333 | 0.000 | 4.679 |
3 | 8.619 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q | vfb_top_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/dma_wr_baseaddr_24_s0/CLEAR | dma_clk:[R] | dma_clk:[R] | 13.333 | 0.000 | 4.679 |
4 | 8.862 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q | vfb_top_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/dma_rd_baseaddr_23_s0/CLEAR | dma_clk:[R] | dma_clk:[R] | 13.333 | 0.000 | 4.436 |
5 | 8.862 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q | vfb_top_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/dma_rd_baseaddr_24_s0/CLEAR | dma_clk:[R] | dma_clk:[R] | 13.333 | 0.000 | 4.436 |
6 | 8.862 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q | vfb_top_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/rd_ptr_0_s0/CLEAR | dma_clk:[R] | dma_clk:[R] | 13.333 | 0.000 | 4.436 |
7 | 8.862 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q | vfb_top_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/rd_ptr_1_s0/CLEAR | dma_clk:[R] | dma_clk:[R] | 13.333 | 0.000 | 4.436 |
8 | 8.862 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q | vfb_top_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/wr_ptr_0_s0/CLEAR | dma_clk:[R] | dma_clk:[R] | 13.333 | 0.000 | 4.436 |
9 | 8.862 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q | vfb_top_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/wr_ptr_1_s0/CLEAR | dma_clk:[R] | dma_clk:[R] | 13.333 | 0.000 | 4.436 |
10 | 4.489 | vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_16_128_inst/fifo_inst/reset_r_Z[1]/Q | vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_16_128_inst/fifo_inst/mem_3_0_mem_3_0_0_0/RESETB | dma_clk:[F] | dma_clk:[R] | 6.666 | 0.018 | 1.721 |
11 | 4.489 | vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_16_128_inst/fifo_inst/reset_r_Z[1]/Q | vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_16_128_inst/fifo_inst/mem_3_1_mem_3_1_0_0/RESETB | dma_clk:[F] | dma_clk:[R] | 6.666 | 0.018 | 1.721 |
12 | 4.489 | vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_16_128_inst/fifo_inst/reset_r_Z[1]/Q | vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_16_128_inst/fifo_inst/mem_3_2_mem_3_2_0_0/RESETB | dma_clk:[F] | dma_clk:[R] | 6.666 | 0.018 | 1.721 |
13 | 4.489 | vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_16_128_inst/fifo_inst/reset_r_Z[1]/Q | vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_16_128_inst/fifo_inst/mem_3_3_mem_3_3_0_0/RESETB | dma_clk:[F] | dma_clk:[R] | 6.666 | 0.018 | 1.721 |
14 | 9.199 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q | vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_1_s1/CLEAR | dma_clk:[R] | dma_clk:[R] | 13.333 | 0.000 | 4.099 |
15 | 9.199 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q | vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_2_s1/CLEAR | dma_clk:[R] | dma_clk:[R] | 13.333 | 0.000 | 4.099 |
16 | 9.205 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q | vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_0_s1/CLEAR | dma_clk:[R] | dma_clk:[R] | 13.333 | 0.000 | 4.093 |
17 | 9.525 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q | vfb_top_inst/u_dma_bus_arbiter/current_state.ST_IDLE_s0/PRESET | dma_clk:[R] | dma_clk:[R] | 13.333 | 0.000 | 3.773 |
18 | 9.538 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q | vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_0_s3/CLEAR | dma_clk:[R] | dma_clk:[R] | 13.333 | 0.000 | 3.760 |
19 | 9.619 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q | vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_1_s3/CLEAR | dma_clk:[R] | dma_clk:[R] | 13.333 | 0.000 | 3.679 |
20 | 9.619 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q | vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_3_s3/CLEAR | dma_clk:[R] | dma_clk:[R] | 13.333 | 0.000 | 3.679 |
21 | 9.619 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q | vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_4_s3/CLEAR | dma_clk:[R] | dma_clk:[R] | 13.333 | 0.000 | 3.679 |
22 | 9.619 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q | vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_5_s3/CLEAR | dma_clk:[R] | dma_clk:[R] | 13.333 | 0.000 | 3.679 |
23 | 9.619 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q | vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_3_s1/CLEAR | dma_clk:[R] | dma_clk:[R] | 13.333 | 0.000 | 3.679 |
24 | 9.619 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q | vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_4_s1/CLEAR | dma_clk:[R] | dma_clk:[R] | 13.333 | 0.000 | 3.679 |
25 | 9.619 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q | vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_5_s1/CLEAR | dma_clk:[R] | dma_clk:[R] | 13.333 | 0.000 | 3.679 |
Removal Paths Table
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 0.456 | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync1_s0/Q | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U1/wq1_rptr_0_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.467 |
2 | 0.456 | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync1_s0/Q | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U1/wq1_rptr_1_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.467 |
3 | 0.460 | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync0_s0/Q | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U0/Full_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.471 |
4 | 0.460 | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync0_s0/Q | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U0/wq2_rptr_1_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.471 |
5 | 0.460 | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync0_s0/Q | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U0/wq2_rptr_3_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.471 |
6 | 0.462 | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync0_s0/Q | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U0/wbin_0_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.473 |
7 | 0.462 | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync0_s0/Q | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U0/wbin_1_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.473 |
8 | 0.462 | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync0_s0/Q | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U0/wbin_4_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.473 |
9 | 0.462 | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync0_s0/Q | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U0/wq2_rptr_0_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.473 |
10 | 0.462 | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync1_s0/Q | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U1/Full_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.473 |
11 | 0.462 | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync1_s0/Q | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U1/wbin_0_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.473 |
12 | 0.462 | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync1_s0/Q | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U1/wbin_1_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.473 |
13 | 0.462 | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync1_s0/Q | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U1/wbin_2_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.473 |
14 | 0.462 | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync1_s0/Q | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U1/wbin_3_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.473 |
15 | 0.462 | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync1_s0/Q | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U1/wbin_4_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.473 |
16 | 0.462 | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync1_s0/Q | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U1/rbin_1_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.473 |
17 | 0.462 | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync1_s0/Q | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U1/rbin_2_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.473 |
18 | 0.462 | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync1_s0/Q | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U1/wq2_rptr_1_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.473 |
19 | 0.462 | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync1_s0/Q | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U1/wq2_rptr_3_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.473 |
20 | 0.463 | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync0_s0/Q | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U0/wbin_2_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.474 |
21 | 0.463 | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync0_s0/Q | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U0/wbin_3_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.474 |
22 | 0.463 | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync0_s0/Q | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U0/rbin_0_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.474 |
23 | 0.463 | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync0_s0/Q | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U0/rbin_1_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.474 |
24 | 0.463 | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync0_s0/Q | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U0/rbin_3_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.474 |
25 | 0.463 | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync0_s0/Q | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U0/rptr_0_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.474 |
Minimum Pulse Width Table:
Number | Slack | Actual Width | Required Width | Type | Clock | Objects |
---|---|---|---|---|---|---|
1 | 0.474 | 1.474 | 1.000 | Low Pulse Width | I_CSI_CKP | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/opensync_2_s0 |
2 | 0.474 | 1.474 | 1.000 | Low Pulse Width | I_CSI_CKP | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/opensync_1_s0 |
3 | 0.474 | 1.474 | 1.000 | Low Pulse Width | I_CSI_CKP | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/opensync_3_s0 |
4 | 0.474 | 1.474 | 1.000 | Low Pulse Width | I_CSI_CKP | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/opensync_0_s0 |
5 | 0.508 | 1.508 | 1.000 | High Pulse Width | I_CSI_CKP | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/opensync_2_s0 |
6 | 0.508 | 1.508 | 1.000 | High Pulse Width | I_CSI_CKP | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/opensync_1_s0 |
7 | 0.508 | 1.508 | 1.000 | High Pulse Width | I_CSI_CKP | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/opensync_3_s0 |
8 | 0.508 | 1.508 | 1.000 | High Pulse Width | I_CSI_CKP | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/opensync_0_s0 |
9 | 2.048 | 3.048 | 1.000 | Low Pulse Width | csi_clk | CSI2RAW8_inst/u_raw8_lane2/u_fifo16b_8b/fifo_inst/Empty_Z |
10 | 2.048 | 3.048 | 1.000 | Low Pulse Width | csi_clk | CSI2RAW8_inst/u_raw8_lane2/u_fifo16b_8b/fifo_inst/Small.rq1_wptr_Z[0] |
Timing Report By Analysis Type:
Setup Analysis Report
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 2.837 |
Data Arrival Time | 0.803 |
Data Required Time | 3.640 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs |
To | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[7].u_ides8_mem |
Launch Clk | ddr3_clk:[R] |
Latch Clk | ddr3_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | ddr3_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | PLL_R[2] | ddr3_pll/rpll_inst/CLKOUT |
0.000 | 0.000 | tNET | RR | 3 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKIN |
0.182 | 0.182 | tINS | RR | 64 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKOUT |
0.307 | 0.125 | tNET | RR | 5 | R35C0 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/FCLK |
0.803 | 0.496 | tC2Q | RF | 8 | R35C0 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/RPOINT[2] |
0.803 | 0.000 | tNET | FF | 1 | IOL29[B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[7].u_ides8_mem/RADDR[2] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.333 | 3.333 | active clock edge time | ||||
3.333 | 0.000 | ddr3_clk | ||||
3.333 | 0.000 | tCL | RR | 1 | PLL_R[2] | ddr3_pll/rpll_inst/CLKOUT |
3.333 | 0.000 | tNET | RR | 3 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKIN |
3.515 | 0.182 | tINS | RR | 64 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKOUT |
3.640 | 0.125 | tNET | RR | 1 | IOL29[B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[7].u_ides8_mem/FCLK |
3.640 | 0.000 | tSu | 1 | IOL29[B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[7].u_ides8_mem |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 3.333 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.182, 59.219%; route: 0.125, 40.781% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000% |
Required Clock Path Delay | cell: 0.182, 59.219%; route: 0.125, 40.781% |
Path2
Path Summary:
Slack | 2.837 |
Data Arrival Time | 0.803 |
Data Required Time | 3.640 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs |
To | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[7].u_ides8_mem |
Launch Clk | ddr3_clk:[R] |
Latch Clk | ddr3_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | ddr3_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | PLL_R[2] | ddr3_pll/rpll_inst/CLKOUT |
0.000 | 0.000 | tNET | RR | 3 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKIN |
0.182 | 0.182 | tINS | RR | 64 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKOUT |
0.307 | 0.125 | tNET | RR | 5 | R35C0 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/FCLK |
0.803 | 0.496 | tC2Q | RF | 8 | R35C0 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/RPOINT[1] |
0.803 | 0.000 | tNET | FF | 1 | IOL29[B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[7].u_ides8_mem/RADDR[1] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.333 | 3.333 | active clock edge time | ||||
3.333 | 0.000 | ddr3_clk | ||||
3.333 | 0.000 | tCL | RR | 1 | PLL_R[2] | ddr3_pll/rpll_inst/CLKOUT |
3.333 | 0.000 | tNET | RR | 3 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKIN |
3.515 | 0.182 | tINS | RR | 64 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKOUT |
3.640 | 0.125 | tNET | RR | 1 | IOL29[B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[7].u_ides8_mem/FCLK |
3.640 | 0.000 | tSu | 1 | IOL29[B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[7].u_ides8_mem |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 3.333 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.182, 59.219%; route: 0.125, 40.781% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000% |
Required Clock Path Delay | cell: 0.182, 59.219%; route: 0.125, 40.781% |
Path3
Path Summary:
Slack | 2.837 |
Data Arrival Time | 0.803 |
Data Required Time | 3.640 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs |
To | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[7].u_ides8_mem |
Launch Clk | ddr3_clk:[R] |
Latch Clk | ddr3_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | ddr3_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | PLL_R[2] | ddr3_pll/rpll_inst/CLKOUT |
0.000 | 0.000 | tNET | RR | 3 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKIN |
0.182 | 0.182 | tINS | RR | 64 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKOUT |
0.307 | 0.125 | tNET | RR | 5 | R35C0 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/FCLK |
0.803 | 0.496 | tC2Q | RF | 8 | R35C0 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/RPOINT[0] |
0.803 | 0.000 | tNET | FF | 1 | IOL29[B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[7].u_ides8_mem/RADDR[0] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.333 | 3.333 | active clock edge time | ||||
3.333 | 0.000 | ddr3_clk | ||||
3.333 | 0.000 | tCL | RR | 1 | PLL_R[2] | ddr3_pll/rpll_inst/CLKOUT |
3.333 | 0.000 | tNET | RR | 3 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKIN |
3.515 | 0.182 | tINS | RR | 64 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKOUT |
3.640 | 0.125 | tNET | RR | 1 | IOL29[B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[7].u_ides8_mem/FCLK |
3.640 | 0.000 | tSu | 1 | IOL29[B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[7].u_ides8_mem |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 3.333 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.182, 59.219%; route: 0.125, 40.781% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000% |
Required Clock Path Delay | cell: 0.182, 59.219%; route: 0.125, 40.781% |
Path4
Path Summary:
Slack | 2.837 |
Data Arrival Time | 0.803 |
Data Required Time | 3.640 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs |
To | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[6].u_ides8_mem |
Launch Clk | ddr3_clk:[R] |
Latch Clk | ddr3_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | ddr3_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | PLL_R[2] | ddr3_pll/rpll_inst/CLKOUT |
0.000 | 0.000 | tNET | RR | 3 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKIN |
0.182 | 0.182 | tINS | RR | 64 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKOUT |
0.307 | 0.125 | tNET | RR | 5 | R35C0 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/FCLK |
0.803 | 0.496 | tC2Q | RF | 8 | R35C0 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/RPOINT[2] |
0.803 | 0.000 | tNET | FF | 1 | IOL42[B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[6].u_ides8_mem/RADDR[2] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.333 | 3.333 | active clock edge time | ||||
3.333 | 0.000 | ddr3_clk | ||||
3.333 | 0.000 | tCL | RR | 1 | PLL_R[2] | ddr3_pll/rpll_inst/CLKOUT |
3.333 | 0.000 | tNET | RR | 3 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKIN |
3.515 | 0.182 | tINS | RR | 64 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKOUT |
3.640 | 0.125 | tNET | RR | 1 | IOL42[B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[6].u_ides8_mem/FCLK |
3.640 | 0.000 | tSu | 1 | IOL42[B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[6].u_ides8_mem |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 3.333 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.182, 59.219%; route: 0.125, 40.781% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000% |
Required Clock Path Delay | cell: 0.182, 59.219%; route: 0.125, 40.781% |
Path5
Path Summary:
Slack | 2.837 |
Data Arrival Time | 0.803 |
Data Required Time | 3.640 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs |
To | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[6].u_ides8_mem |
Launch Clk | ddr3_clk:[R] |
Latch Clk | ddr3_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | ddr3_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | PLL_R[2] | ddr3_pll/rpll_inst/CLKOUT |
0.000 | 0.000 | tNET | RR | 3 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKIN |
0.182 | 0.182 | tINS | RR | 64 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKOUT |
0.307 | 0.125 | tNET | RR | 5 | R35C0 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/FCLK |
0.803 | 0.496 | tC2Q | RF | 8 | R35C0 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/RPOINT[1] |
0.803 | 0.000 | tNET | FF | 1 | IOL42[B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[6].u_ides8_mem/RADDR[1] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.333 | 3.333 | active clock edge time | ||||
3.333 | 0.000 | ddr3_clk | ||||
3.333 | 0.000 | tCL | RR | 1 | PLL_R[2] | ddr3_pll/rpll_inst/CLKOUT |
3.333 | 0.000 | tNET | RR | 3 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKIN |
3.515 | 0.182 | tINS | RR | 64 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKOUT |
3.640 | 0.125 | tNET | RR | 1 | IOL42[B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[6].u_ides8_mem/FCLK |
3.640 | 0.000 | tSu | 1 | IOL42[B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[6].u_ides8_mem |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 3.333 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.182, 59.219%; route: 0.125, 40.781% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000% |
Required Clock Path Delay | cell: 0.182, 59.219%; route: 0.125, 40.781% |
Path6
Path Summary:
Slack | 2.837 |
Data Arrival Time | 0.803 |
Data Required Time | 3.640 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs |
To | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[6].u_ides8_mem |
Launch Clk | ddr3_clk:[R] |
Latch Clk | ddr3_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | ddr3_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | PLL_R[2] | ddr3_pll/rpll_inst/CLKOUT |
0.000 | 0.000 | tNET | RR | 3 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKIN |
0.182 | 0.182 | tINS | RR | 64 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKOUT |
0.307 | 0.125 | tNET | RR | 5 | R35C0 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/FCLK |
0.803 | 0.496 | tC2Q | RF | 8 | R35C0 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/RPOINT[0] |
0.803 | 0.000 | tNET | FF | 1 | IOL42[B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[6].u_ides8_mem/RADDR[0] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.333 | 3.333 | active clock edge time | ||||
3.333 | 0.000 | ddr3_clk | ||||
3.333 | 0.000 | tCL | RR | 1 | PLL_R[2] | ddr3_pll/rpll_inst/CLKOUT |
3.333 | 0.000 | tNET | RR | 3 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKIN |
3.515 | 0.182 | tINS | RR | 64 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKOUT |
3.640 | 0.125 | tNET | RR | 1 | IOL42[B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[6].u_ides8_mem/FCLK |
3.640 | 0.000 | tSu | 1 | IOL42[B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[6].u_ides8_mem |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 3.333 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.182, 59.219%; route: 0.125, 40.781% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000% |
Required Clock Path Delay | cell: 0.182, 59.219%; route: 0.125, 40.781% |
Path7
Path Summary:
Slack | 2.837 |
Data Arrival Time | 0.803 |
Data Required Time | 3.640 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs |
To | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[5].u_ides8_mem |
Launch Clk | ddr3_clk:[R] |
Latch Clk | ddr3_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | ddr3_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | PLL_R[2] | ddr3_pll/rpll_inst/CLKOUT |
0.000 | 0.000 | tNET | RR | 3 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKIN |
0.182 | 0.182 | tINS | RR | 64 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKOUT |
0.307 | 0.125 | tNET | RR | 5 | R35C0 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/FCLK |
0.803 | 0.496 | tC2Q | RF | 8 | R35C0 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/RPOINT[2] |
0.803 | 0.000 | tNET | FF | 1 | IOL28[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[5].u_ides8_mem/RADDR[2] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.333 | 3.333 | active clock edge time | ||||
3.333 | 0.000 | ddr3_clk | ||||
3.333 | 0.000 | tCL | RR | 1 | PLL_R[2] | ddr3_pll/rpll_inst/CLKOUT |
3.333 | 0.000 | tNET | RR | 3 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKIN |
3.515 | 0.182 | tINS | RR | 64 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKOUT |
3.640 | 0.125 | tNET | RR | 1 | IOL28[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[5].u_ides8_mem/FCLK |
3.640 | 0.000 | tSu | 1 | IOL28[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[5].u_ides8_mem |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 3.333 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.182, 59.219%; route: 0.125, 40.781% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000% |
Required Clock Path Delay | cell: 0.182, 59.219%; route: 0.125, 40.781% |
Path8
Path Summary:
Slack | 2.837 |
Data Arrival Time | 0.803 |
Data Required Time | 3.640 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs |
To | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[5].u_ides8_mem |
Launch Clk | ddr3_clk:[R] |
Latch Clk | ddr3_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | ddr3_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | PLL_R[2] | ddr3_pll/rpll_inst/CLKOUT |
0.000 | 0.000 | tNET | RR | 3 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKIN |
0.182 | 0.182 | tINS | RR | 64 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKOUT |
0.307 | 0.125 | tNET | RR | 5 | R35C0 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/FCLK |
0.803 | 0.496 | tC2Q | RF | 8 | R35C0 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/RPOINT[1] |
0.803 | 0.000 | tNET | FF | 1 | IOL28[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[5].u_ides8_mem/RADDR[1] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.333 | 3.333 | active clock edge time | ||||
3.333 | 0.000 | ddr3_clk | ||||
3.333 | 0.000 | tCL | RR | 1 | PLL_R[2] | ddr3_pll/rpll_inst/CLKOUT |
3.333 | 0.000 | tNET | RR | 3 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKIN |
3.515 | 0.182 | tINS | RR | 64 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKOUT |
3.640 | 0.125 | tNET | RR | 1 | IOL28[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[5].u_ides8_mem/FCLK |
3.640 | 0.000 | tSu | 1 | IOL28[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[5].u_ides8_mem |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 3.333 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.182, 59.219%; route: 0.125, 40.781% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000% |
Required Clock Path Delay | cell: 0.182, 59.219%; route: 0.125, 40.781% |
Path9
Path Summary:
Slack | 2.837 |
Data Arrival Time | 0.803 |
Data Required Time | 3.640 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs |
To | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[5].u_ides8_mem |
Launch Clk | ddr3_clk:[R] |
Latch Clk | ddr3_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | ddr3_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | PLL_R[2] | ddr3_pll/rpll_inst/CLKOUT |
0.000 | 0.000 | tNET | RR | 3 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKIN |
0.182 | 0.182 | tINS | RR | 64 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKOUT |
0.307 | 0.125 | tNET | RR | 5 | R35C0 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/FCLK |
0.803 | 0.496 | tC2Q | RF | 8 | R35C0 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/RPOINT[0] |
0.803 | 0.000 | tNET | FF | 1 | IOL28[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[5].u_ides8_mem/RADDR[0] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.333 | 3.333 | active clock edge time | ||||
3.333 | 0.000 | ddr3_clk | ||||
3.333 | 0.000 | tCL | RR | 1 | PLL_R[2] | ddr3_pll/rpll_inst/CLKOUT |
3.333 | 0.000 | tNET | RR | 3 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKIN |
3.515 | 0.182 | tINS | RR | 64 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKOUT |
3.640 | 0.125 | tNET | RR | 1 | IOL28[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[5].u_ides8_mem/FCLK |
3.640 | 0.000 | tSu | 1 | IOL28[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[5].u_ides8_mem |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 3.333 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.182, 59.219%; route: 0.125, 40.781% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000% |
Required Clock Path Delay | cell: 0.182, 59.219%; route: 0.125, 40.781% |
Path10
Path Summary:
Slack | 2.837 |
Data Arrival Time | 0.803 |
Data Required Time | 3.640 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs |
To | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[4].u_ides8_mem |
Launch Clk | ddr3_clk:[R] |
Latch Clk | ddr3_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | ddr3_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | PLL_R[2] | ddr3_pll/rpll_inst/CLKOUT |
0.000 | 0.000 | tNET | RR | 3 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKIN |
0.182 | 0.182 | tINS | RR | 64 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKOUT |
0.307 | 0.125 | tNET | RR | 5 | R35C0 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/FCLK |
0.803 | 0.496 | tC2Q | RF | 8 | R35C0 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/RPOINT[2] |
0.803 | 0.000 | tNET | FF | 1 | IOL33[B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[4].u_ides8_mem/RADDR[2] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.333 | 3.333 | active clock edge time | ||||
3.333 | 0.000 | ddr3_clk | ||||
3.333 | 0.000 | tCL | RR | 1 | PLL_R[2] | ddr3_pll/rpll_inst/CLKOUT |
3.333 | 0.000 | tNET | RR | 3 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKIN |
3.515 | 0.182 | tINS | RR | 64 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKOUT |
3.640 | 0.125 | tNET | RR | 1 | IOL33[B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[4].u_ides8_mem/FCLK |
3.640 | 0.000 | tSu | 1 | IOL33[B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[4].u_ides8_mem |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 3.333 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.182, 59.219%; route: 0.125, 40.781% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000% |
Required Clock Path Delay | cell: 0.182, 59.219%; route: 0.125, 40.781% |
Path11
Path Summary:
Slack | 2.837 |
Data Arrival Time | 0.803 |
Data Required Time | 3.640 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs |
To | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[4].u_ides8_mem |
Launch Clk | ddr3_clk:[R] |
Latch Clk | ddr3_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | ddr3_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | PLL_R[2] | ddr3_pll/rpll_inst/CLKOUT |
0.000 | 0.000 | tNET | RR | 3 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKIN |
0.182 | 0.182 | tINS | RR | 64 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKOUT |
0.307 | 0.125 | tNET | RR | 5 | R35C0 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/FCLK |
0.803 | 0.496 | tC2Q | RF | 8 | R35C0 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/RPOINT[1] |
0.803 | 0.000 | tNET | FF | 1 | IOL33[B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[4].u_ides8_mem/RADDR[1] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.333 | 3.333 | active clock edge time | ||||
3.333 | 0.000 | ddr3_clk | ||||
3.333 | 0.000 | tCL | RR | 1 | PLL_R[2] | ddr3_pll/rpll_inst/CLKOUT |
3.333 | 0.000 | tNET | RR | 3 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKIN |
3.515 | 0.182 | tINS | RR | 64 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKOUT |
3.640 | 0.125 | tNET | RR | 1 | IOL33[B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[4].u_ides8_mem/FCLK |
3.640 | 0.000 | tSu | 1 | IOL33[B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[4].u_ides8_mem |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 3.333 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.182, 59.219%; route: 0.125, 40.781% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000% |
Required Clock Path Delay | cell: 0.182, 59.219%; route: 0.125, 40.781% |
Path12
Path Summary:
Slack | 2.837 |
Data Arrival Time | 0.803 |
Data Required Time | 3.640 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs |
To | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[4].u_ides8_mem |
Launch Clk | ddr3_clk:[R] |
Latch Clk | ddr3_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | ddr3_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | PLL_R[2] | ddr3_pll/rpll_inst/CLKOUT |
0.000 | 0.000 | tNET | RR | 3 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKIN |
0.182 | 0.182 | tINS | RR | 64 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKOUT |
0.307 | 0.125 | tNET | RR | 5 | R35C0 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/FCLK |
0.803 | 0.496 | tC2Q | RF | 8 | R35C0 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/RPOINT[0] |
0.803 | 0.000 | tNET | FF | 1 | IOL33[B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[4].u_ides8_mem/RADDR[0] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.333 | 3.333 | active clock edge time | ||||
3.333 | 0.000 | ddr3_clk | ||||
3.333 | 0.000 | tCL | RR | 1 | PLL_R[2] | ddr3_pll/rpll_inst/CLKOUT |
3.333 | 0.000 | tNET | RR | 3 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKIN |
3.515 | 0.182 | tINS | RR | 64 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKOUT |
3.640 | 0.125 | tNET | RR | 1 | IOL33[B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[4].u_ides8_mem/FCLK |
3.640 | 0.000 | tSu | 1 | IOL33[B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[4].u_ides8_mem |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 3.333 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.182, 59.219%; route: 0.125, 40.781% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000% |
Required Clock Path Delay | cell: 0.182, 59.219%; route: 0.125, 40.781% |
Path13
Path Summary:
Slack | 2.837 |
Data Arrival Time | 0.803 |
Data Required Time | 3.640 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs |
To | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[3].u_ides8_mem |
Launch Clk | ddr3_clk:[R] |
Latch Clk | ddr3_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | ddr3_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | PLL_R[2] | ddr3_pll/rpll_inst/CLKOUT |
0.000 | 0.000 | tNET | RR | 3 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKIN |
0.182 | 0.182 | tINS | RR | 64 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKOUT |
0.307 | 0.125 | tNET | RR | 5 | R35C0 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/FCLK |
0.803 | 0.496 | tC2Q | RF | 8 | R35C0 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/RPOINT[2] |
0.803 | 0.000 | tNET | FF | 1 | IOL32[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[3].u_ides8_mem/RADDR[2] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.333 | 3.333 | active clock edge time | ||||
3.333 | 0.000 | ddr3_clk | ||||
3.333 | 0.000 | tCL | RR | 1 | PLL_R[2] | ddr3_pll/rpll_inst/CLKOUT |
3.333 | 0.000 | tNET | RR | 3 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKIN |
3.515 | 0.182 | tINS | RR | 64 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKOUT |
3.640 | 0.125 | tNET | RR | 1 | IOL32[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[3].u_ides8_mem/FCLK |
3.640 | 0.000 | tSu | 1 | IOL32[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[3].u_ides8_mem |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 3.333 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.182, 59.219%; route: 0.125, 40.781% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000% |
Required Clock Path Delay | cell: 0.182, 59.219%; route: 0.125, 40.781% |
Path14
Path Summary:
Slack | 2.837 |
Data Arrival Time | 0.803 |
Data Required Time | 3.640 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs |
To | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[3].u_ides8_mem |
Launch Clk | ddr3_clk:[R] |
Latch Clk | ddr3_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | ddr3_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | PLL_R[2] | ddr3_pll/rpll_inst/CLKOUT |
0.000 | 0.000 | tNET | RR | 3 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKIN |
0.182 | 0.182 | tINS | RR | 64 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKOUT |
0.307 | 0.125 | tNET | RR | 5 | R35C0 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/FCLK |
0.803 | 0.496 | tC2Q | RF | 8 | R35C0 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/RPOINT[1] |
0.803 | 0.000 | tNET | FF | 1 | IOL32[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[3].u_ides8_mem/RADDR[1] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.333 | 3.333 | active clock edge time | ||||
3.333 | 0.000 | ddr3_clk | ||||
3.333 | 0.000 | tCL | RR | 1 | PLL_R[2] | ddr3_pll/rpll_inst/CLKOUT |
3.333 | 0.000 | tNET | RR | 3 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKIN |
3.515 | 0.182 | tINS | RR | 64 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKOUT |
3.640 | 0.125 | tNET | RR | 1 | IOL32[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[3].u_ides8_mem/FCLK |
3.640 | 0.000 | tSu | 1 | IOL32[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[3].u_ides8_mem |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 3.333 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.182, 59.219%; route: 0.125, 40.781% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000% |
Required Clock Path Delay | cell: 0.182, 59.219%; route: 0.125, 40.781% |
Path15
Path Summary:
Slack | 2.837 |
Data Arrival Time | 0.803 |
Data Required Time | 3.640 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs |
To | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[3].u_ides8_mem |
Launch Clk | ddr3_clk:[R] |
Latch Clk | ddr3_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | ddr3_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | PLL_R[2] | ddr3_pll/rpll_inst/CLKOUT |
0.000 | 0.000 | tNET | RR | 3 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKIN |
0.182 | 0.182 | tINS | RR | 64 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKOUT |
0.307 | 0.125 | tNET | RR | 5 | R35C0 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/FCLK |
0.803 | 0.496 | tC2Q | RF | 8 | R35C0 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/RPOINT[0] |
0.803 | 0.000 | tNET | FF | 1 | IOL32[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[3].u_ides8_mem/RADDR[0] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.333 | 3.333 | active clock edge time | ||||
3.333 | 0.000 | ddr3_clk | ||||
3.333 | 0.000 | tCL | RR | 1 | PLL_R[2] | ddr3_pll/rpll_inst/CLKOUT |
3.333 | 0.000 | tNET | RR | 3 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKIN |
3.515 | 0.182 | tINS | RR | 64 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKOUT |
3.640 | 0.125 | tNET | RR | 1 | IOL32[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[3].u_ides8_mem/FCLK |
3.640 | 0.000 | tSu | 1 | IOL32[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[3].u_ides8_mem |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 3.333 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.182, 59.219%; route: 0.125, 40.781% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000% |
Required Clock Path Delay | cell: 0.182, 59.219%; route: 0.125, 40.781% |
Path16
Path Summary:
Slack | 2.837 |
Data Arrival Time | 0.803 |
Data Required Time | 3.640 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs |
To | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[2].u_ides8_mem |
Launch Clk | ddr3_clk:[R] |
Latch Clk | ddr3_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | ddr3_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | PLL_R[2] | ddr3_pll/rpll_inst/CLKOUT |
0.000 | 0.000 | tNET | RR | 3 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKIN |
0.182 | 0.182 | tINS | RR | 64 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKOUT |
0.307 | 0.125 | tNET | RR | 5 | R35C0 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/FCLK |
0.803 | 0.496 | tC2Q | RF | 8 | R35C0 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/RPOINT[2] |
0.803 | 0.000 | tNET | FF | 1 | IOL43[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[2].u_ides8_mem/RADDR[2] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.333 | 3.333 | active clock edge time | ||||
3.333 | 0.000 | ddr3_clk | ||||
3.333 | 0.000 | tCL | RR | 1 | PLL_R[2] | ddr3_pll/rpll_inst/CLKOUT |
3.333 | 0.000 | tNET | RR | 3 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKIN |
3.515 | 0.182 | tINS | RR | 64 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKOUT |
3.640 | 0.125 | tNET | RR | 1 | IOL43[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[2].u_ides8_mem/FCLK |
3.640 | 0.000 | tSu | 1 | IOL43[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[2].u_ides8_mem |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 3.333 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.182, 59.219%; route: 0.125, 40.781% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000% |
Required Clock Path Delay | cell: 0.182, 59.219%; route: 0.125, 40.781% |
Path17
Path Summary:
Slack | 2.837 |
Data Arrival Time | 0.803 |
Data Required Time | 3.640 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs |
To | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[2].u_ides8_mem |
Launch Clk | ddr3_clk:[R] |
Latch Clk | ddr3_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | ddr3_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | PLL_R[2] | ddr3_pll/rpll_inst/CLKOUT |
0.000 | 0.000 | tNET | RR | 3 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKIN |
0.182 | 0.182 | tINS | RR | 64 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKOUT |
0.307 | 0.125 | tNET | RR | 5 | R35C0 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/FCLK |
0.803 | 0.496 | tC2Q | RF | 8 | R35C0 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/RPOINT[1] |
0.803 | 0.000 | tNET | FF | 1 | IOL43[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[2].u_ides8_mem/RADDR[1] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.333 | 3.333 | active clock edge time | ||||
3.333 | 0.000 | ddr3_clk | ||||
3.333 | 0.000 | tCL | RR | 1 | PLL_R[2] | ddr3_pll/rpll_inst/CLKOUT |
3.333 | 0.000 | tNET | RR | 3 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKIN |
3.515 | 0.182 | tINS | RR | 64 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKOUT |
3.640 | 0.125 | tNET | RR | 1 | IOL43[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[2].u_ides8_mem/FCLK |
3.640 | 0.000 | tSu | 1 | IOL43[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[2].u_ides8_mem |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 3.333 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.182, 59.219%; route: 0.125, 40.781% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000% |
Required Clock Path Delay | cell: 0.182, 59.219%; route: 0.125, 40.781% |
Path18
Path Summary:
Slack | 2.837 |
Data Arrival Time | 0.803 |
Data Required Time | 3.640 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs |
To | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[2].u_ides8_mem |
Launch Clk | ddr3_clk:[R] |
Latch Clk | ddr3_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | ddr3_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | PLL_R[2] | ddr3_pll/rpll_inst/CLKOUT |
0.000 | 0.000 | tNET | RR | 3 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKIN |
0.182 | 0.182 | tINS | RR | 64 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKOUT |
0.307 | 0.125 | tNET | RR | 5 | R35C0 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/FCLK |
0.803 | 0.496 | tC2Q | RF | 8 | R35C0 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/RPOINT[0] |
0.803 | 0.000 | tNET | FF | 1 | IOL43[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[2].u_ides8_mem/RADDR[0] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.333 | 3.333 | active clock edge time | ||||
3.333 | 0.000 | ddr3_clk | ||||
3.333 | 0.000 | tCL | RR | 1 | PLL_R[2] | ddr3_pll/rpll_inst/CLKOUT |
3.333 | 0.000 | tNET | RR | 3 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKIN |
3.515 | 0.182 | tINS | RR | 64 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKOUT |
3.640 | 0.125 | tNET | RR | 1 | IOL43[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[2].u_ides8_mem/FCLK |
3.640 | 0.000 | tSu | 1 | IOL43[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[2].u_ides8_mem |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 3.333 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.182, 59.219%; route: 0.125, 40.781% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000% |
Required Clock Path Delay | cell: 0.182, 59.219%; route: 0.125, 40.781% |
Path19
Path Summary:
Slack | 2.837 |
Data Arrival Time | 0.803 |
Data Required Time | 3.640 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs |
To | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[1].u_ides8_mem |
Launch Clk | ddr3_clk:[R] |
Latch Clk | ddr3_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | ddr3_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | PLL_R[2] | ddr3_pll/rpll_inst/CLKOUT |
0.000 | 0.000 | tNET | RR | 3 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKIN |
0.182 | 0.182 | tINS | RR | 64 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKOUT |
0.307 | 0.125 | tNET | RR | 5 | R35C0 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/FCLK |
0.803 | 0.496 | tC2Q | RF | 8 | R35C0 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/RPOINT[2] |
0.803 | 0.000 | tNET | FF | 1 | IOL35[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[1].u_ides8_mem/RADDR[2] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.333 | 3.333 | active clock edge time | ||||
3.333 | 0.000 | ddr3_clk | ||||
3.333 | 0.000 | tCL | RR | 1 | PLL_R[2] | ddr3_pll/rpll_inst/CLKOUT |
3.333 | 0.000 | tNET | RR | 3 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKIN |
3.515 | 0.182 | tINS | RR | 64 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKOUT |
3.640 | 0.125 | tNET | RR | 1 | IOL35[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[1].u_ides8_mem/FCLK |
3.640 | 0.000 | tSu | 1 | IOL35[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[1].u_ides8_mem |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 3.333 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.182, 59.219%; route: 0.125, 40.781% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000% |
Required Clock Path Delay | cell: 0.182, 59.219%; route: 0.125, 40.781% |
Path20
Path Summary:
Slack | 2.837 |
Data Arrival Time | 0.803 |
Data Required Time | 3.640 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs |
To | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[1].u_ides8_mem |
Launch Clk | ddr3_clk:[R] |
Latch Clk | ddr3_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | ddr3_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | PLL_R[2] | ddr3_pll/rpll_inst/CLKOUT |
0.000 | 0.000 | tNET | RR | 3 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKIN |
0.182 | 0.182 | tINS | RR | 64 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKOUT |
0.307 | 0.125 | tNET | RR | 5 | R35C0 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/FCLK |
0.803 | 0.496 | tC2Q | RF | 8 | R35C0 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/RPOINT[1] |
0.803 | 0.000 | tNET | FF | 1 | IOL35[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[1].u_ides8_mem/RADDR[1] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.333 | 3.333 | active clock edge time | ||||
3.333 | 0.000 | ddr3_clk | ||||
3.333 | 0.000 | tCL | RR | 1 | PLL_R[2] | ddr3_pll/rpll_inst/CLKOUT |
3.333 | 0.000 | tNET | RR | 3 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKIN |
3.515 | 0.182 | tINS | RR | 64 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKOUT |
3.640 | 0.125 | tNET | RR | 1 | IOL35[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[1].u_ides8_mem/FCLK |
3.640 | 0.000 | tSu | 1 | IOL35[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[1].u_ides8_mem |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 3.333 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.182, 59.219%; route: 0.125, 40.781% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000% |
Required Clock Path Delay | cell: 0.182, 59.219%; route: 0.125, 40.781% |
Path21
Path Summary:
Slack | 2.837 |
Data Arrival Time | 0.803 |
Data Required Time | 3.640 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs |
To | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[1].u_ides8_mem |
Launch Clk | ddr3_clk:[R] |
Latch Clk | ddr3_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | ddr3_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | PLL_R[2] | ddr3_pll/rpll_inst/CLKOUT |
0.000 | 0.000 | tNET | RR | 3 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKIN |
0.182 | 0.182 | tINS | RR | 64 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKOUT |
0.307 | 0.125 | tNET | RR | 5 | R35C0 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/FCLK |
0.803 | 0.496 | tC2Q | RF | 8 | R35C0 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/RPOINT[0] |
0.803 | 0.000 | tNET | FF | 1 | IOL35[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[1].u_ides8_mem/RADDR[0] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.333 | 3.333 | active clock edge time | ||||
3.333 | 0.000 | ddr3_clk | ||||
3.333 | 0.000 | tCL | RR | 1 | PLL_R[2] | ddr3_pll/rpll_inst/CLKOUT |
3.333 | 0.000 | tNET | RR | 3 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKIN |
3.515 | 0.182 | tINS | RR | 64 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKOUT |
3.640 | 0.125 | tNET | RR | 1 | IOL35[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[1].u_ides8_mem/FCLK |
3.640 | 0.000 | tSu | 1 | IOL35[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[1].u_ides8_mem |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 3.333 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.182, 59.219%; route: 0.125, 40.781% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000% |
Required Clock Path Delay | cell: 0.182, 59.219%; route: 0.125, 40.781% |
Path22
Path Summary:
Slack | 2.837 |
Data Arrival Time | 0.803 |
Data Required Time | 3.640 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs |
To | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[0].u_ides8_mem |
Launch Clk | ddr3_clk:[R] |
Latch Clk | ddr3_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | ddr3_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | PLL_R[2] | ddr3_pll/rpll_inst/CLKOUT |
0.000 | 0.000 | tNET | RR | 3 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKIN |
0.182 | 0.182 | tINS | RR | 64 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKOUT |
0.307 | 0.125 | tNET | RR | 5 | R35C0 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/FCLK |
0.803 | 0.496 | tC2Q | RF | 8 | R35C0 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/RPOINT[2] |
0.803 | 0.000 | tNET | FF | 1 | IOL44[B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[0].u_ides8_mem/RADDR[2] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.333 | 3.333 | active clock edge time | ||||
3.333 | 0.000 | ddr3_clk | ||||
3.333 | 0.000 | tCL | RR | 1 | PLL_R[2] | ddr3_pll/rpll_inst/CLKOUT |
3.333 | 0.000 | tNET | RR | 3 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKIN |
3.515 | 0.182 | tINS | RR | 64 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKOUT |
3.640 | 0.125 | tNET | RR | 1 | IOL44[B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[0].u_ides8_mem/FCLK |
3.640 | 0.000 | tSu | 1 | IOL44[B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[0].u_ides8_mem |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 3.333 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.182, 59.219%; route: 0.125, 40.781% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000% |
Required Clock Path Delay | cell: 0.182, 59.219%; route: 0.125, 40.781% |
Path23
Path Summary:
Slack | 2.837 |
Data Arrival Time | 0.803 |
Data Required Time | 3.640 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs |
To | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[0].u_ides8_mem |
Launch Clk | ddr3_clk:[R] |
Latch Clk | ddr3_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | ddr3_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | PLL_R[2] | ddr3_pll/rpll_inst/CLKOUT |
0.000 | 0.000 | tNET | RR | 3 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKIN |
0.182 | 0.182 | tINS | RR | 64 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKOUT |
0.307 | 0.125 | tNET | RR | 5 | R35C0 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/FCLK |
0.803 | 0.496 | tC2Q | RF | 8 | R35C0 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/RPOINT[1] |
0.803 | 0.000 | tNET | FF | 1 | IOL44[B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[0].u_ides8_mem/RADDR[1] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.333 | 3.333 | active clock edge time | ||||
3.333 | 0.000 | ddr3_clk | ||||
3.333 | 0.000 | tCL | RR | 1 | PLL_R[2] | ddr3_pll/rpll_inst/CLKOUT |
3.333 | 0.000 | tNET | RR | 3 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKIN |
3.515 | 0.182 | tINS | RR | 64 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKOUT |
3.640 | 0.125 | tNET | RR | 1 | IOL44[B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[0].u_ides8_mem/FCLK |
3.640 | 0.000 | tSu | 1 | IOL44[B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[0].u_ides8_mem |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 3.333 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.182, 59.219%; route: 0.125, 40.781% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000% |
Required Clock Path Delay | cell: 0.182, 59.219%; route: 0.125, 40.781% |
Path24
Path Summary:
Slack | 2.837 |
Data Arrival Time | 0.803 |
Data Required Time | 3.640 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs |
To | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[0].u_ides8_mem |
Launch Clk | ddr3_clk:[R] |
Latch Clk | ddr3_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | ddr3_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | PLL_R[2] | ddr3_pll/rpll_inst/CLKOUT |
0.000 | 0.000 | tNET | RR | 3 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKIN |
0.182 | 0.182 | tINS | RR | 64 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKOUT |
0.307 | 0.125 | tNET | RR | 5 | R35C0 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/FCLK |
0.803 | 0.496 | tC2Q | RF | 8 | R35C0 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/RPOINT[0] |
0.803 | 0.000 | tNET | FF | 1 | IOL44[B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[0].u_ides8_mem/RADDR[0] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.333 | 3.333 | active clock edge time | ||||
3.333 | 0.000 | ddr3_clk | ||||
3.333 | 0.000 | tCL | RR | 1 | PLL_R[2] | ddr3_pll/rpll_inst/CLKOUT |
3.333 | 0.000 | tNET | RR | 3 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKIN |
3.515 | 0.182 | tINS | RR | 64 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKOUT |
3.640 | 0.125 | tNET | RR | 1 | IOL44[B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[0].u_ides8_mem/FCLK |
3.640 | 0.000 | tSu | 1 | IOL44[B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[0].u_ides8_mem |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 3.333 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.182, 59.219%; route: 0.125, 40.781% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000% |
Required Clock Path Delay | cell: 0.182, 59.219%; route: 0.125, 40.781% |
Path25
Path Summary:
Slack | 2.837 |
Data Arrival Time | 0.803 |
Data Required Time | 3.640 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[0].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs |
To | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[0].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[7].u_ides8_mem |
Launch Clk | ddr3_clk:[R] |
Latch Clk | ddr3_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | ddr3_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | PLL_R[2] | ddr3_pll/rpll_inst/CLKOUT |
0.000 | 0.000 | tNET | RR | 3 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKIN |
0.182 | 0.182 | tINS | RR | 64 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKOUT |
0.307 | 0.125 | tNET | RR | 5 | R53C0 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[0].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/FCLK |
0.803 | 0.496 | tC2Q | RF | 8 | R53C0 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[0].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/RPOINT[2] |
0.803 | 0.000 | tNET | FF | 1 | IOL51[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[0].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[7].u_ides8_mem/RADDR[2] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
3.333 | 3.333 | active clock edge time | ||||
3.333 | 0.000 | ddr3_clk | ||||
3.333 | 0.000 | tCL | RR | 1 | PLL_R[2] | ddr3_pll/rpll_inst/CLKOUT |
3.333 | 0.000 | tNET | RR | 3 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKIN |
3.515 | 0.182 | tINS | RR | 64 | - | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclk_dhcen/CLKOUT |
3.640 | 0.125 | tNET | RR | 1 | IOL51[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[0].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[7].u_ides8_mem/FCLK |
3.640 | 0.000 | tSu | 1 | IOL51[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[0].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[7].u_ides8_mem |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 3.333 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.182, 59.219%; route: 0.125, 40.781% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000% |
Required Clock Path Delay | cell: 0.182, 59.219%; route: 0.125, 40.781% |
Hold Analysis Report
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 0.213 |
Data Arrival Time | 0.647 |
Data Required Time | 0.433 |
From | CSI2RAW8_inst/u_control_capture/q_din2_5_s1 |
To | CSI2RAW8_inst/u_raw8_lane2/u_fifo16b_8b/fifo_inst/mem_mem_0_0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 398 | TOPSIDE[0] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R11C18[1][A] | CSI2RAW8_inst/u_control_capture/q_din2_5_s1/CLK |
0.386 | 0.202 | tC2Q | RR | 1 | R11C18[1][A] | CSI2RAW8_inst/u_control_capture/q_din2_5_s1/Q |
0.647 | 0.260 | tNET | RR | 1 | BSRAM_R10[5] | CSI2RAW8_inst/u_raw8_lane2/u_fifo16b_8b/fifo_inst/mem_mem_0_0/DI[5] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 398 | TOPSIDE[0] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | BSRAM_R10[5] | CSI2RAW8_inst/u_raw8_lane2/u_fifo16b_8b/fifo_inst/mem_mem_0_0/CLKA |
0.433 | 0.249 | tHld | 1 | BSRAM_R10[5] | CSI2RAW8_inst/u_raw8_lane2/u_fifo16b_8b/fifo_inst/mem_mem_0_0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path2
Path Summary:
Slack | 0.213 |
Data Arrival Time | 0.647 |
Data Required Time | 0.433 |
From | CSI2RAW8_inst/u_control_capture/q_din2_4_s1 |
To | CSI2RAW8_inst/u_raw8_lane2/u_fifo16b_8b/fifo_inst/mem_mem_0_0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 398 | TOPSIDE[0] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R11C18[1][B] | CSI2RAW8_inst/u_control_capture/q_din2_4_s1/CLK |
0.386 | 0.202 | tC2Q | RR | 1 | R11C18[1][B] | CSI2RAW8_inst/u_control_capture/q_din2_4_s1/Q |
0.647 | 0.260 | tNET | RR | 1 | BSRAM_R10[5] | CSI2RAW8_inst/u_raw8_lane2/u_fifo16b_8b/fifo_inst/mem_mem_0_0/DI[4] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 398 | TOPSIDE[0] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | BSRAM_R10[5] | CSI2RAW8_inst/u_raw8_lane2/u_fifo16b_8b/fifo_inst/mem_mem_0_0/CLKA |
0.433 | 0.249 | tHld | 1 | BSRAM_R10[5] | CSI2RAW8_inst/u_raw8_lane2/u_fifo16b_8b/fifo_inst/mem_mem_0_0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path3
Path Summary:
Slack | 0.213 |
Data Arrival Time | 0.647 |
Data Required Time | 0.433 |
From | CSI2RAW8_inst/u_control_capture/q_din2_3_s1 |
To | CSI2RAW8_inst/u_raw8_lane2/u_fifo16b_8b/fifo_inst/mem_mem_0_0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 398 | TOPSIDE[0] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R11C19[0][B] | CSI2RAW8_inst/u_control_capture/q_din2_3_s1/CLK |
0.386 | 0.202 | tC2Q | RR | 1 | R11C19[0][B] | CSI2RAW8_inst/u_control_capture/q_din2_3_s1/Q |
0.647 | 0.260 | tNET | RR | 1 | BSRAM_R10[5] | CSI2RAW8_inst/u_raw8_lane2/u_fifo16b_8b/fifo_inst/mem_mem_0_0/DI[3] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 398 | TOPSIDE[0] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | BSRAM_R10[5] | CSI2RAW8_inst/u_raw8_lane2/u_fifo16b_8b/fifo_inst/mem_mem_0_0/CLKA |
0.433 | 0.249 | tHld | 1 | BSRAM_R10[5] | CSI2RAW8_inst/u_raw8_lane2/u_fifo16b_8b/fifo_inst/mem_mem_0_0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path4
Path Summary:
Slack | 0.213 |
Data Arrival Time | 0.647 |
Data Required Time | 0.433 |
From | CSI2RAW8_inst/u_control_capture/q_din2_2_s1 |
To | CSI2RAW8_inst/u_raw8_lane2/u_fifo16b_8b/fifo_inst/mem_mem_0_0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 398 | TOPSIDE[0] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R11C19[0][A] | CSI2RAW8_inst/u_control_capture/q_din2_2_s1/CLK |
0.386 | 0.202 | tC2Q | RR | 1 | R11C19[0][A] | CSI2RAW8_inst/u_control_capture/q_din2_2_s1/Q |
0.647 | 0.260 | tNET | RR | 1 | BSRAM_R10[5] | CSI2RAW8_inst/u_raw8_lane2/u_fifo16b_8b/fifo_inst/mem_mem_0_0/DI[2] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 398 | TOPSIDE[0] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | BSRAM_R10[5] | CSI2RAW8_inst/u_raw8_lane2/u_fifo16b_8b/fifo_inst/mem_mem_0_0/CLKA |
0.433 | 0.249 | tHld | 1 | BSRAM_R10[5] | CSI2RAW8_inst/u_raw8_lane2/u_fifo16b_8b/fifo_inst/mem_mem_0_0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path5
Path Summary:
Slack | 0.213 |
Data Arrival Time | 0.647 |
Data Required Time | 0.433 |
From | CSI2RAW8_inst/u_control_capture/q_din2_1_s1 |
To | CSI2RAW8_inst/u_raw8_lane2/u_fifo16b_8b/fifo_inst/mem_mem_0_0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 398 | TOPSIDE[0] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R11C19[1][A] | CSI2RAW8_inst/u_control_capture/q_din2_1_s1/CLK |
0.386 | 0.202 | tC2Q | RR | 1 | R11C19[1][A] | CSI2RAW8_inst/u_control_capture/q_din2_1_s1/Q |
0.647 | 0.260 | tNET | RR | 1 | BSRAM_R10[5] | CSI2RAW8_inst/u_raw8_lane2/u_fifo16b_8b/fifo_inst/mem_mem_0_0/DI[1] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 398 | TOPSIDE[0] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | BSRAM_R10[5] | CSI2RAW8_inst/u_raw8_lane2/u_fifo16b_8b/fifo_inst/mem_mem_0_0/CLKA |
0.433 | 0.249 | tHld | 1 | BSRAM_R10[5] | CSI2RAW8_inst/u_raw8_lane2/u_fifo16b_8b/fifo_inst/mem_mem_0_0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path6
Path Summary:
Slack | 0.217 |
Data Arrival Time | 0.519 |
Data Required Time | 0.302 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_fifo_ctrl/of_wbin_2_s0 |
To | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[0].u_ddr3_phy_data_lane/u_out_fifo/mem4_mem4_0_1_s |
Launch Clk | dma_clk:[R] |
Latch Clk | dma_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | dma_clk | ||||
0.000 | 0.000 | tCL | RR | 1673 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R53C20[1][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_fifo_ctrl/of_wbin_2_s0/CLK |
0.385 | 0.201 | tC2Q | RF | 5 | R53C20[1][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_fifo_ctrl/of_wbin_2_s0/Q |
0.519 | 0.134 | tNET | FF | 1 | BSRAM_R54[6] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[0].u_ddr3_phy_data_lane/u_out_fifo/mem4_mem4_0_1_s/ADA[7] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | dma_clk | ||||
0.000 | 0.000 | tCL | RR | 1673 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | BSRAM_R54[6] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[0].u_ddr3_phy_data_lane/u_out_fifo/mem4_mem4_0_1_s/CLKA |
0.302 | 0.118 | tHld | 1 | BSRAM_R54[6] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[0].u_ddr3_phy_data_lane/u_out_fifo/mem4_mem4_0_1_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.134, 40.013%; tC2Q: 0.201, 59.987% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path7
Path Summary:
Slack | 0.219 |
Data Arrival Time | 1.328 |
Data Required Time | 1.109 |
From | Gowin_EMPU_M1_Top_inst/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApMst/HWDATAM_17_s0 |
To | Gowin_EMPU_M1_Top_inst/M1_inst/u_CortexM1DbgIntegration_inst/u_itcm/mem2_mem2_0_0_s |
Launch Clk | I_clk:[R] |
Latch Clk | I_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | I_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | gowin_ibuf_I_clk/I |
0.675 | 0.675 | tINS | RR | 2896 | IOR44[A] | gowin_ibuf_I_clk/O |
0.860 | 0.184 | tNET | RR | 1 | R43C69[0][A] | Gowin_EMPU_M1_Top_inst/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApMst/HWDATAM_17_s0/CLK |
1.062 | 0.202 | tC2Q | RR | 13 | R43C69[0][A] | Gowin_EMPU_M1_Top_inst/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApMst/HWDATAM_17_s0/Q |
1.328 | 0.266 | tNET | RR | 1 | BSRAM_R45[20] | Gowin_EMPU_M1_Top_inst/M1_inst/u_CortexM1DbgIntegration_inst/u_itcm/mem2_mem2_0_0_s/DIA[1] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | I_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | gowin_ibuf_I_clk/I |
0.675 | 0.675 | tINS | RR | 2896 | IOR44[A] | gowin_ibuf_I_clk/O |
0.860 | 0.184 | tNET | RR | 1 | BSRAM_R45[20] | Gowin_EMPU_M1_Top_inst/M1_inst/u_CortexM1DbgIntegration_inst/u_itcm/mem2_mem2_0_0_s/CLKA |
1.109 | 0.249 | tHld | 1 | BSRAM_R45[20] | Gowin_EMPU_M1_Top_inst/M1_inst/u_CortexM1DbgIntegration_inst/u_itcm/mem2_mem2_0_0_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.266, 56.879%; tC2Q: 0.202, 43.121% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path8
Path Summary:
Slack | 0.224 |
Data Arrival Time | 0.526 |
Data Required Time | 0.302 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_fifo_ctrl/of_rbin_4_s0 |
To | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[0].u_ddr3_phy_data_lane/u_out_fifo/mem4_mem4_0_1_s |
Launch Clk | dma_clk:[R] |
Latch Clk | dma_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | dma_clk | ||||
0.000 | 0.000 | tCL | RR | 1673 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R55C20[1][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_fifo_ctrl/of_rbin_4_s0/CLK |
0.385 | 0.201 | tC2Q | RF | 8 | R55C20[1][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_fifo_ctrl/of_rbin_4_s0/Q |
0.526 | 0.141 | tNET | FF | 1 | BSRAM_R54[6] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[0].u_ddr3_phy_data_lane/u_out_fifo/mem4_mem4_0_1_s/ADB[9] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | dma_clk | ||||
0.000 | 0.000 | tCL | RR | 1673 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | BSRAM_R54[6] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[0].u_ddr3_phy_data_lane/u_out_fifo/mem4_mem4_0_1_s/CLKB |
0.302 | 0.118 | tHld | 1 | BSRAM_R54[6] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[0].u_ddr3_phy_data_lane/u_out_fifo/mem4_mem4_0_1_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.141, 41.164%; tC2Q: 0.201, 58.836% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path9
Path Summary:
Slack | 0.225 |
Data Arrival Time | 0.659 |
Data Required Time | 0.433 |
From | CSI2RAW8_inst/u_control_capture/q_din2_12_s1 |
To | CSI2RAW8_inst/u_raw8_lane2/u_fifo16b_8b/fifo_inst/mem_mem_0_0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 398 | TOPSIDE[0] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R11C17[0][A] | CSI2RAW8_inst/u_control_capture/q_din2_12_s1/CLK |
0.386 | 0.202 | tC2Q | RR | 1 | R11C17[0][A] | CSI2RAW8_inst/u_control_capture/q_din2_12_s1/Q |
0.659 | 0.272 | tNET | RR | 1 | BSRAM_R10[5] | CSI2RAW8_inst/u_raw8_lane2/u_fifo16b_8b/fifo_inst/mem_mem_0_0/DI[12] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 398 | TOPSIDE[0] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | BSRAM_R10[5] | CSI2RAW8_inst/u_raw8_lane2/u_fifo16b_8b/fifo_inst/mem_mem_0_0/CLKA |
0.433 | 0.249 | tHld | 1 | BSRAM_R10[5] | CSI2RAW8_inst/u_raw8_lane2/u_fifo16b_8b/fifo_inst/mem_mem_0_0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.272, 57.427%; tC2Q: 0.202, 42.573% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path10
Path Summary:
Slack | 0.225 |
Data Arrival Time | 0.659 |
Data Required Time | 0.433 |
From | CSI2RAW8_inst/u_control_capture/q_din2_11_s1 |
To | CSI2RAW8_inst/u_raw8_lane2/u_fifo16b_8b/fifo_inst/mem_mem_0_0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 398 | TOPSIDE[0] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R11C17[0][B] | CSI2RAW8_inst/u_control_capture/q_din2_11_s1/CLK |
0.386 | 0.202 | tC2Q | RR | 1 | R11C17[0][B] | CSI2RAW8_inst/u_control_capture/q_din2_11_s1/Q |
0.659 | 0.272 | tNET | RR | 1 | BSRAM_R10[5] | CSI2RAW8_inst/u_raw8_lane2/u_fifo16b_8b/fifo_inst/mem_mem_0_0/DI[11] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 398 | TOPSIDE[0] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | BSRAM_R10[5] | CSI2RAW8_inst/u_raw8_lane2/u_fifo16b_8b/fifo_inst/mem_mem_0_0/CLKA |
0.433 | 0.249 | tHld | 1 | BSRAM_R10[5] | CSI2RAW8_inst/u_raw8_lane2/u_fifo16b_8b/fifo_inst/mem_mem_0_0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.272, 57.427%; tC2Q: 0.202, 42.573% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path11
Path Summary:
Slack | 0.234 |
Data Arrival Time | 0.513 |
Data Required Time | 0.279 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/oserdes_d_reg_91_s0 |
To | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen |
Launch Clk | dma_clk:[R] |
Latch Clk | dma_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | dma_clk | ||||
0.000 | 0.000 | tCL | RR | 1673 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R11C2[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/oserdes_d_reg_91_s0/CLK |
0.385 | 0.201 | tC2Q | RF | 2 | R11C2[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/oserdes_d_reg_91_s0/Q |
0.513 | 0.128 | tNET | FF | 1 | IOL11[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen/D6 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | dma_clk | ||||
0.000 | 0.000 | tCL | RR | 1673 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | IOL11[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen/PCLK |
0.279 | 0.095 | tHld | 1 | IOL11[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.128, 38.816%; tC2Q: 0.201, 61.184% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path12
Path Summary:
Slack | 0.234 |
Data Arrival Time | 0.513 |
Data Required Time | 0.279 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/oserdes_d_reg_90_s0 |
To | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen |
Launch Clk | dma_clk:[R] |
Latch Clk | dma_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | dma_clk | ||||
0.000 | 0.000 | tCL | RR | 1673 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R11C2[0][B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/oserdes_d_reg_90_s0/CLK |
0.385 | 0.201 | tC2Q | RF | 2 | R11C2[0][B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/oserdes_d_reg_90_s0/Q |
0.513 | 0.128 | tNET | FF | 1 | IOL11[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen/D4 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | dma_clk | ||||
0.000 | 0.000 | tCL | RR | 1673 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | IOL11[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen/PCLK |
0.279 | 0.095 | tHld | 1 | IOL11[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.128, 38.816%; tC2Q: 0.201, 61.184% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path13
Path Summary:
Slack | 0.234 |
Data Arrival Time | 0.513 |
Data Required Time | 0.279 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/oserdes_d_reg_89_s0 |
To | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen |
Launch Clk | dma_clk:[R] |
Latch Clk | dma_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | dma_clk | ||||
0.000 | 0.000 | tCL | RR | 1673 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R11C2[1][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/oserdes_d_reg_89_s0/CLK |
0.385 | 0.201 | tC2Q | RF | 2 | R11C2[1][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/oserdes_d_reg_89_s0/Q |
0.513 | 0.128 | tNET | FF | 1 | IOL11[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen/D2 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | dma_clk | ||||
0.000 | 0.000 | tCL | RR | 1673 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | IOL11[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen/PCLK |
0.279 | 0.095 | tHld | 1 | IOL11[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.128, 38.816%; tC2Q: 0.201, 61.184% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path14
Path Summary:
Slack | 0.234 |
Data Arrival Time | 0.513 |
Data Required Time | 0.279 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/oserdes_d_reg_83_s0 |
To | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen |
Launch Clk | dma_clk:[R] |
Latch Clk | dma_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | dma_clk | ||||
0.000 | 0.000 | tCL | RR | 1673 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R9C2[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/oserdes_d_reg_83_s0/CLK |
0.385 | 0.201 | tC2Q | RF | 2 | R9C2[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/oserdes_d_reg_83_s0/Q |
0.513 | 0.128 | tNET | FF | 1 | IOL9[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen/D6 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | dma_clk | ||||
0.000 | 0.000 | tCL | RR | 1673 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | IOL9[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen/PCLK |
0.279 | 0.095 | tHld | 1 | IOL9[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.128, 38.816%; tC2Q: 0.201, 61.184% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path15
Path Summary:
Slack | 0.234 |
Data Arrival Time | 0.513 |
Data Required Time | 0.279 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/oserdes_d_reg_82_s0 |
To | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen |
Launch Clk | dma_clk:[R] |
Latch Clk | dma_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | dma_clk | ||||
0.000 | 0.000 | tCL | RR | 1673 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R9C2[0][B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/oserdes_d_reg_82_s0/CLK |
0.385 | 0.201 | tC2Q | RF | 2 | R9C2[0][B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/oserdes_d_reg_82_s0/Q |
0.513 | 0.128 | tNET | FF | 1 | IOL9[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen/D4 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | dma_clk | ||||
0.000 | 0.000 | tCL | RR | 1673 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | IOL9[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen/PCLK |
0.279 | 0.095 | tHld | 1 | IOL9[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.128, 38.816%; tC2Q: 0.201, 61.184% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path16
Path Summary:
Slack | 0.234 |
Data Arrival Time | 0.513 |
Data Required Time | 0.279 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/oserdes_d_reg_81_s0 |
To | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen |
Launch Clk | dma_clk:[R] |
Latch Clk | dma_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | dma_clk | ||||
0.000 | 0.000 | tCL | RR | 1673 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R9C2[1][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/oserdes_d_reg_81_s0/CLK |
0.385 | 0.201 | tC2Q | RF | 2 | R9C2[1][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/oserdes_d_reg_81_s0/Q |
0.513 | 0.128 | tNET | FF | 1 | IOL9[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen/D2 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | dma_clk | ||||
0.000 | 0.000 | tCL | RR | 1673 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | IOL9[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen/PCLK |
0.279 | 0.095 | tHld | 1 | IOL9[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.128, 38.816%; tC2Q: 0.201, 61.184% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path17
Path Summary:
Slack | 0.234 |
Data Arrival Time | 0.513 |
Data Required Time | 0.279 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/oserdes_d_reg_45_s0 |
To | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[11].u_cmd_gen |
Launch Clk | dma_clk:[R] |
Latch Clk | dma_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | dma_clk | ||||
0.000 | 0.000 | tCL | RR | 1673 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R18C2[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/oserdes_d_reg_45_s0/CLK |
0.385 | 0.201 | tC2Q | RF | 2 | R18C2[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/oserdes_d_reg_45_s0/Q |
0.513 | 0.128 | tNET | FF | 1 | IOL18[B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[11].u_cmd_gen/D2 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | dma_clk | ||||
0.000 | 0.000 | tCL | RR | 1673 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | IOL18[B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[11].u_cmd_gen/PCLK |
0.279 | 0.095 | tHld | 1 | IOL18[B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[11].u_cmd_gen |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.128, 38.816%; tC2Q: 0.201, 61.184% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path18
Path Summary:
Slack | 0.234 |
Data Arrival Time | 0.513 |
Data Required Time | 0.279 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/oserdes_d_reg_44_s0 |
To | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[11].u_cmd_gen |
Launch Clk | dma_clk:[R] |
Latch Clk | dma_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | dma_clk | ||||
0.000 | 0.000 | tCL | RR | 1673 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R18C2[0][B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/oserdes_d_reg_44_s0/CLK |
0.385 | 0.201 | tC2Q | RF | 2 | R18C2[0][B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/oserdes_d_reg_44_s0/Q |
0.513 | 0.128 | tNET | FF | 1 | IOL18[B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[11].u_cmd_gen/D0 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | dma_clk | ||||
0.000 | 0.000 | tCL | RR | 1673 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | IOL18[B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[11].u_cmd_gen/PCLK |
0.279 | 0.095 | tHld | 1 | IOL18[B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[11].u_cmd_gen |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.128, 38.816%; tC2Q: 0.201, 61.184% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path19
Path Summary:
Slack | 0.234 |
Data Arrival Time | 0.513 |
Data Required Time | 0.279 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/oserdes_d_reg_39_s0 |
To | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[9].u_cmd_gen |
Launch Clk | dma_clk:[R] |
Latch Clk | dma_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | dma_clk | ||||
0.000 | 0.000 | tCL | RR | 1673 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R2C2[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/oserdes_d_reg_39_s0/CLK |
0.385 | 0.201 | tC2Q | RF | 2 | R2C2[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/oserdes_d_reg_39_s0/Q |
0.513 | 0.128 | tNET | FF | 1 | IOL2[B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[9].u_cmd_gen/D6 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | dma_clk | ||||
0.000 | 0.000 | tCL | RR | 1673 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | IOL2[B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[9].u_cmd_gen/PCLK |
0.279 | 0.095 | tHld | 1 | IOL2[B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[9].u_cmd_gen |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.128, 38.816%; tC2Q: 0.201, 61.184% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path20
Path Summary:
Slack | 0.234 |
Data Arrival Time | 0.513 |
Data Required Time | 0.279 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/oserdes_d_reg_38_s0 |
To | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[9].u_cmd_gen |
Launch Clk | dma_clk:[R] |
Latch Clk | dma_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | dma_clk | ||||
0.000 | 0.000 | tCL | RR | 1673 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R2C2[0][B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/oserdes_d_reg_38_s0/CLK |
0.385 | 0.201 | tC2Q | RF | 2 | R2C2[0][B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/oserdes_d_reg_38_s0/Q |
0.513 | 0.128 | tNET | FF | 1 | IOL2[B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[9].u_cmd_gen/D4 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | dma_clk | ||||
0.000 | 0.000 | tCL | RR | 1673 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | IOL2[B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[9].u_cmd_gen/PCLK |
0.279 | 0.095 | tHld | 1 | IOL2[B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[9].u_cmd_gen |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.128, 38.816%; tC2Q: 0.201, 61.184% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path21
Path Summary:
Slack | 0.234 |
Data Arrival Time | 0.513 |
Data Required Time | 0.279 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/oserdes_d_reg_37_s0 |
To | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[9].u_cmd_gen |
Launch Clk | dma_clk:[R] |
Latch Clk | dma_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | dma_clk | ||||
0.000 | 0.000 | tCL | RR | 1673 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R2C2[1][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/oserdes_d_reg_37_s0/CLK |
0.385 | 0.201 | tC2Q | RF | 2 | R2C2[1][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/oserdes_d_reg_37_s0/Q |
0.513 | 0.128 | tNET | FF | 1 | IOL2[B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[9].u_cmd_gen/D2 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | dma_clk | ||||
0.000 | 0.000 | tCL | RR | 1673 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | IOL2[B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[9].u_cmd_gen/PCLK |
0.279 | 0.095 | tHld | 1 | IOL2[B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[9].u_cmd_gen |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.128, 38.816%; tC2Q: 0.201, 61.184% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path22
Path Summary:
Slack | 0.234 |
Data Arrival Time | 0.513 |
Data Required Time | 0.279 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/oserdes_d_reg_36_s0 |
To | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[9].u_cmd_gen |
Launch Clk | dma_clk:[R] |
Latch Clk | dma_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | dma_clk | ||||
0.000 | 0.000 | tCL | RR | 1673 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R2C2[1][B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/oserdes_d_reg_36_s0/CLK |
0.385 | 0.201 | tC2Q | RF | 2 | R2C2[1][B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/oserdes_d_reg_36_s0/Q |
0.513 | 0.128 | tNET | FF | 1 | IOL2[B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[9].u_cmd_gen/D0 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | dma_clk | ||||
0.000 | 0.000 | tCL | RR | 1673 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | IOL2[B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[9].u_cmd_gen/PCLK |
0.279 | 0.095 | tHld | 1 | IOL2[B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[9].u_cmd_gen |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.128, 38.816%; tC2Q: 0.201, 61.184% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path23
Path Summary:
Slack | 0.234 |
Data Arrival Time | 0.513 |
Data Required Time | 0.279 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/oserdes_d_reg_35_s0 |
To | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[8].u_cmd_gen |
Launch Clk | dma_clk:[R] |
Latch Clk | dma_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | dma_clk | ||||
0.000 | 0.000 | tCL | RR | 1673 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R5C2[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/oserdes_d_reg_35_s0/CLK |
0.385 | 0.201 | tC2Q | RF | 2 | R5C2[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/oserdes_d_reg_35_s0/Q |
0.513 | 0.128 | tNET | FF | 1 | IOL5[B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[8].u_cmd_gen/D6 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | dma_clk | ||||
0.000 | 0.000 | tCL | RR | 1673 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | IOL5[B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[8].u_cmd_gen/PCLK |
0.279 | 0.095 | tHld | 1 | IOL5[B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[8].u_cmd_gen |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.128, 38.816%; tC2Q: 0.201, 61.184% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path24
Path Summary:
Slack | 0.234 |
Data Arrival Time | 0.513 |
Data Required Time | 0.279 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/oserdes_d_reg_34_s0 |
To | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[8].u_cmd_gen |
Launch Clk | dma_clk:[R] |
Latch Clk | dma_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | dma_clk | ||||
0.000 | 0.000 | tCL | RR | 1673 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R5C2[0][B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/oserdes_d_reg_34_s0/CLK |
0.385 | 0.201 | tC2Q | RF | 2 | R5C2[0][B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/oserdes_d_reg_34_s0/Q |
0.513 | 0.128 | tNET | FF | 1 | IOL5[B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[8].u_cmd_gen/D4 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | dma_clk | ||||
0.000 | 0.000 | tCL | RR | 1673 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | IOL5[B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[8].u_cmd_gen/PCLK |
0.279 | 0.095 | tHld | 1 | IOL5[B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[8].u_cmd_gen |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.128, 38.816%; tC2Q: 0.201, 61.184% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path25
Path Summary:
Slack | 0.234 |
Data Arrival Time | 0.513 |
Data Required Time | 0.279 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/oserdes_d_reg_33_s0 |
To | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[8].u_cmd_gen |
Launch Clk | dma_clk:[R] |
Latch Clk | dma_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | dma_clk | ||||
0.000 | 0.000 | tCL | RR | 1673 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R5C2[1][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/oserdes_d_reg_33_s0/CLK |
0.385 | 0.201 | tC2Q | RF | 2 | R5C2[1][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/oserdes_d_reg_33_s0/Q |
0.513 | 0.128 | tNET | FF | 1 | IOL5[B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[8].u_cmd_gen/D2 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | dma_clk | ||||
0.000 | 0.000 | tCL | RR | 1673 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | IOL5[B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[8].u_cmd_gen/PCLK |
0.279 | 0.095 | tHld | 1 | IOL5[B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[8].u_cmd_gen |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.128, 38.816%; tC2Q: 0.201, 61.184% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Recovery Analysis Report
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 3.997 |
Data Arrival Time | 3.374 |
Data Required Time | 7.371 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/n2610_s0 |
To | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/read_reg_3_s4 |
Launch Clk | ddr_rst:[R] |
Latch Clk | ddr_rst:[F] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | ddr_rst | ||||
0.000 | 0.000 | tCL | RR | 1178 | R73C13[2][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q |
1.896 | 1.896 | tNET | RR | 1 | R65C11[3][B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/n2610_s0/I1 |
2.451 | 0.555 | tINS | RF | 9 | R65C11[3][B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/n2610_s0/F |
3.374 | 0.923 | tNET | FF | 1 | R65C11[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/read_reg_3_s4/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | ddr_rst | ||||
5.000 | 0.000 | tCL | FF | 1178 | R73C13[2][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q |
7.406 | 2.406 | tNET | FF | 1 | R65C11[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/read_reg_3_s4/G |
7.371 | -0.035 | tSu | 1 | R65C11[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/read_reg_3_s4 |
Path Statistics:
Clock Skew | 2.406 |
Setup Relationship | 5.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.555, 16.447%; route: 0.923, 27.360%; tC2Q: 1.896, 56.193% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.406, 100.000% |
Path2
Path Summary:
Slack | 8.619 |
Data Arrival Time | 4.922 |
Data Required Time | 13.541 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0 |
To | vfb_top_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/dma_wr_baseaddr_23_s0 |
Launch Clk | dma_clk:[R] |
Latch Clk | dma_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | dma_clk | ||||
0.000 | 0.000 | tCL | RR | 1673 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R69C21[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 358 | R69C21[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q |
2.516 | 2.041 | tNET | FF | 1 | R68C43[1][A] | O_led_d_0_s0/I0 |
3.071 | 0.555 | tINS | FF | 130 | R68C43[1][A] | O_led_d_0_s0/F |
4.922 | 1.851 | tNET | FF | 1 | R53C46[0][B] | vfb_top_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/dma_wr_baseaddr_23_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
13.333 | 13.333 | active clock edge time | ||||
13.333 | 0.000 | dma_clk | ||||
13.333 | 0.000 | tCL | RR | 1673 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
13.576 | 0.243 | tNET | RR | 1 | R53C46[0][B] | vfb_top_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/dma_wr_baseaddr_23_s0/CLK |
13.541 | -0.035 | tSu | 1 | R53C46[0][B] | vfb_top_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/dma_wr_baseaddr_23_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 13.333 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 0.555, 11.861%; route: 3.892, 83.180%; tC2Q: 0.232, 4.958% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path3
Path Summary:
Slack | 8.619 |
Data Arrival Time | 4.922 |
Data Required Time | 13.541 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0 |
To | vfb_top_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/dma_wr_baseaddr_24_s0 |
Launch Clk | dma_clk:[R] |
Latch Clk | dma_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | dma_clk | ||||
0.000 | 0.000 | tCL | RR | 1673 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R69C21[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 358 | R69C21[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q |
2.516 | 2.041 | tNET | FF | 1 | R68C43[1][A] | O_led_d_0_s0/I0 |
3.071 | 0.555 | tINS | FF | 130 | R68C43[1][A] | O_led_d_0_s0/F |
4.922 | 1.851 | tNET | FF | 1 | R53C46[0][A] | vfb_top_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/dma_wr_baseaddr_24_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
13.333 | 13.333 | active clock edge time | ||||
13.333 | 0.000 | dma_clk | ||||
13.333 | 0.000 | tCL | RR | 1673 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
13.576 | 0.243 | tNET | RR | 1 | R53C46[0][A] | vfb_top_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/dma_wr_baseaddr_24_s0/CLK |
13.541 | -0.035 | tSu | 1 | R53C46[0][A] | vfb_top_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/dma_wr_baseaddr_24_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 13.333 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 0.555, 11.861%; route: 3.892, 83.180%; tC2Q: 0.232, 4.958% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path4
Path Summary:
Slack | 8.862 |
Data Arrival Time | 4.680 |
Data Required Time | 13.541 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0 |
To | vfb_top_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/dma_rd_baseaddr_23_s0 |
Launch Clk | dma_clk:[R] |
Latch Clk | dma_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | dma_clk | ||||
0.000 | 0.000 | tCL | RR | 1673 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R69C21[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 358 | R69C21[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q |
2.516 | 2.041 | tNET | FF | 1 | R68C43[1][A] | O_led_d_0_s0/I0 |
3.071 | 0.555 | tINS | FF | 130 | R68C43[1][A] | O_led_d_0_s0/F |
4.680 | 1.609 | tNET | FF | 1 | R53C45[0][B] | vfb_top_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/dma_rd_baseaddr_23_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
13.333 | 13.333 | active clock edge time | ||||
13.333 | 0.000 | dma_clk | ||||
13.333 | 0.000 | tCL | RR | 1673 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
13.576 | 0.243 | tNET | RR | 1 | R53C45[0][B] | vfb_top_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/dma_rd_baseaddr_23_s0/CLK |
13.541 | -0.035 | tSu | 1 | R53C45[0][B] | vfb_top_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/dma_rd_baseaddr_23_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 13.333 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 0.555, 12.510%; route: 3.649, 82.260%; tC2Q: 0.232, 5.230% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path5
Path Summary:
Slack | 8.862 |
Data Arrival Time | 4.680 |
Data Required Time | 13.541 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0 |
To | vfb_top_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/dma_rd_baseaddr_24_s0 |
Launch Clk | dma_clk:[R] |
Latch Clk | dma_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | dma_clk | ||||
0.000 | 0.000 | tCL | RR | 1673 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R69C21[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 358 | R69C21[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q |
2.516 | 2.041 | tNET | FF | 1 | R68C43[1][A] | O_led_d_0_s0/I0 |
3.071 | 0.555 | tINS | FF | 130 | R68C43[1][A] | O_led_d_0_s0/F |
4.680 | 1.609 | tNET | FF | 1 | R53C45[0][A] | vfb_top_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/dma_rd_baseaddr_24_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
13.333 | 13.333 | active clock edge time | ||||
13.333 | 0.000 | dma_clk | ||||
13.333 | 0.000 | tCL | RR | 1673 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
13.576 | 0.243 | tNET | RR | 1 | R53C45[0][A] | vfb_top_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/dma_rd_baseaddr_24_s0/CLK |
13.541 | -0.035 | tSu | 1 | R53C45[0][A] | vfb_top_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/dma_rd_baseaddr_24_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 13.333 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 0.555, 12.510%; route: 3.649, 82.260%; tC2Q: 0.232, 5.230% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path6
Path Summary:
Slack | 8.862 |
Data Arrival Time | 4.680 |
Data Required Time | 13.541 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0 |
To | vfb_top_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/rd_ptr_0_s0 |
Launch Clk | dma_clk:[R] |
Latch Clk | dma_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | dma_clk | ||||
0.000 | 0.000 | tCL | RR | 1673 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R69C21[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 358 | R69C21[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q |
2.516 | 2.041 | tNET | FF | 1 | R68C43[1][A] | O_led_d_0_s0/I0 |
3.071 | 0.555 | tINS | FF | 130 | R68C43[1][A] | O_led_d_0_s0/F |
4.680 | 1.609 | tNET | FF | 1 | R53C45[1][A] | vfb_top_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/rd_ptr_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
13.333 | 13.333 | active clock edge time | ||||
13.333 | 0.000 | dma_clk | ||||
13.333 | 0.000 | tCL | RR | 1673 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
13.576 | 0.243 | tNET | RR | 1 | R53C45[1][A] | vfb_top_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/rd_ptr_0_s0/CLK |
13.541 | -0.035 | tSu | 1 | R53C45[1][A] | vfb_top_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/rd_ptr_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 13.333 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 0.555, 12.510%; route: 3.649, 82.260%; tC2Q: 0.232, 5.230% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path7
Path Summary:
Slack | 8.862 |
Data Arrival Time | 4.680 |
Data Required Time | 13.541 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0 |
To | vfb_top_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/rd_ptr_1_s0 |
Launch Clk | dma_clk:[R] |
Latch Clk | dma_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | dma_clk | ||||
0.000 | 0.000 | tCL | RR | 1673 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R69C21[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 358 | R69C21[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q |
2.516 | 2.041 | tNET | FF | 1 | R68C43[1][A] | O_led_d_0_s0/I0 |
3.071 | 0.555 | tINS | FF | 130 | R68C43[1][A] | O_led_d_0_s0/F |
4.680 | 1.609 | tNET | FF | 1 | R53C45[1][B] | vfb_top_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/rd_ptr_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
13.333 | 13.333 | active clock edge time | ||||
13.333 | 0.000 | dma_clk | ||||
13.333 | 0.000 | tCL | RR | 1673 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
13.576 | 0.243 | tNET | RR | 1 | R53C45[1][B] | vfb_top_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/rd_ptr_1_s0/CLK |
13.541 | -0.035 | tSu | 1 | R53C45[1][B] | vfb_top_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/rd_ptr_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 13.333 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 0.555, 12.510%; route: 3.649, 82.260%; tC2Q: 0.232, 5.230% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path8
Path Summary:
Slack | 8.862 |
Data Arrival Time | 4.680 |
Data Required Time | 13.541 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0 |
To | vfb_top_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/wr_ptr_0_s0 |
Launch Clk | dma_clk:[R] |
Latch Clk | dma_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | dma_clk | ||||
0.000 | 0.000 | tCL | RR | 1673 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R69C21[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 358 | R69C21[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q |
2.516 | 2.041 | tNET | FF | 1 | R68C43[1][A] | O_led_d_0_s0/I0 |
3.071 | 0.555 | tINS | FF | 130 | R68C43[1][A] | O_led_d_0_s0/F |
4.680 | 1.609 | tNET | FF | 1 | R53C45[2][A] | vfb_top_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/wr_ptr_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
13.333 | 13.333 | active clock edge time | ||||
13.333 | 0.000 | dma_clk | ||||
13.333 | 0.000 | tCL | RR | 1673 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
13.576 | 0.243 | tNET | RR | 1 | R53C45[2][A] | vfb_top_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/wr_ptr_0_s0/CLK |
13.541 | -0.035 | tSu | 1 | R53C45[2][A] | vfb_top_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/wr_ptr_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 13.333 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 0.555, 12.510%; route: 3.649, 82.260%; tC2Q: 0.232, 5.230% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path9
Path Summary:
Slack | 8.862 |
Data Arrival Time | 4.680 |
Data Required Time | 13.541 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0 |
To | vfb_top_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/wr_ptr_1_s0 |
Launch Clk | dma_clk:[R] |
Latch Clk | dma_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | dma_clk | ||||
0.000 | 0.000 | tCL | RR | 1673 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R69C21[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 358 | R69C21[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q |
2.516 | 2.041 | tNET | FF | 1 | R68C43[1][A] | O_led_d_0_s0/I0 |
3.071 | 0.555 | tINS | FF | 130 | R68C43[1][A] | O_led_d_0_s0/F |
4.680 | 1.609 | tNET | FF | 1 | R53C45[2][B] | vfb_top_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/wr_ptr_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
13.333 | 13.333 | active clock edge time | ||||
13.333 | 0.000 | dma_clk | ||||
13.333 | 0.000 | tCL | RR | 1673 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
13.576 | 0.243 | tNET | RR | 1 | R53C45[2][B] | vfb_top_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/wr_ptr_1_s0/CLK |
13.541 | -0.035 | tSu | 1 | R53C45[2][B] | vfb_top_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/wr_ptr_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 13.333 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 0.555, 12.510%; route: 3.649, 82.260%; tC2Q: 0.232, 5.230% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path10
Path Summary:
Slack | 4.489 |
Data Arrival Time | 8.650 |
Data Required Time | 13.138 |
From | vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_16_128_inst/fifo_inst/reset_r_Z[1] |
To | vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_16_128_inst/fifo_inst/mem_3_0_mem_3_0_0_0 |
Launch Clk | dma_clk:[F] |
Latch Clk | dma_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.667 | 6.667 | active clock edge time | ||||
6.667 | 0.000 | dma_clk | ||||
6.667 | 0.000 | tCL | FF | 1673 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
6.928 | 0.261 | tNET | FF | 1 | R62C46[0][A] | vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_16_128_inst/fifo_inst/reset_r_Z[1]/CLK |
7.160 | 0.232 | tC2Q | FF | 63 | R62C46[0][A] | vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_16_128_inst/fifo_inst/reset_r_Z[1]/Q |
8.650 | 1.489 | tNET | FF | 32 | BSRAM_R54[16] | vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_16_128_inst/fifo_inst/mem_3_0_mem_3_0_0_0/RESETB |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
13.333 | 13.333 | active clock edge time | ||||
13.333 | 0.000 | dma_clk | ||||
13.333 | 0.000 | tCL | RR | 1673 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
13.576 | 0.243 | tNET | RR | 1 | BSRAM_R54[16] | vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_16_128_inst/fifo_inst/mem_3_0_mem_3_0_0_0/CLKB |
13.138 | -0.438 | tSu | 1 | BSRAM_R54[16] | vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_16_128_inst/fifo_inst/mem_3_0_mem_3_0_0_0 |
Path Statistics:
Clock Skew | -0.018 |
Setup Relationship | 6.666 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.261, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.489, 86.521%; tC2Q: 0.232, 13.479% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path11
Path Summary:
Slack | 4.489 |
Data Arrival Time | 8.650 |
Data Required Time | 13.138 |
From | vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_16_128_inst/fifo_inst/reset_r_Z[1] |
To | vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_16_128_inst/fifo_inst/mem_3_1_mem_3_1_0_0 |
Launch Clk | dma_clk:[F] |
Latch Clk | dma_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.667 | 6.667 | active clock edge time | ||||
6.667 | 0.000 | dma_clk | ||||
6.667 | 0.000 | tCL | FF | 1673 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
6.928 | 0.261 | tNET | FF | 1 | R62C46[0][A] | vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_16_128_inst/fifo_inst/reset_r_Z[1]/CLK |
7.160 | 0.232 | tC2Q | FF | 63 | R62C46[0][A] | vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_16_128_inst/fifo_inst/reset_r_Z[1]/Q |
8.650 | 1.489 | tNET | FF | 32 | BSRAM_R54[13] | vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_16_128_inst/fifo_inst/mem_3_1_mem_3_1_0_0/RESETB |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
13.333 | 13.333 | active clock edge time | ||||
13.333 | 0.000 | dma_clk | ||||
13.333 | 0.000 | tCL | RR | 1673 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
13.576 | 0.243 | tNET | RR | 1 | BSRAM_R54[13] | vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_16_128_inst/fifo_inst/mem_3_1_mem_3_1_0_0/CLKB |
13.138 | -0.438 | tSu | 1 | BSRAM_R54[13] | vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_16_128_inst/fifo_inst/mem_3_1_mem_3_1_0_0 |
Path Statistics:
Clock Skew | -0.018 |
Setup Relationship | 6.666 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.261, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.489, 86.521%; tC2Q: 0.232, 13.479% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path12
Path Summary:
Slack | 4.489 |
Data Arrival Time | 8.650 |
Data Required Time | 13.138 |
From | vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_16_128_inst/fifo_inst/reset_r_Z[1] |
To | vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_16_128_inst/fifo_inst/mem_3_2_mem_3_2_0_0 |
Launch Clk | dma_clk:[F] |
Latch Clk | dma_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.667 | 6.667 | active clock edge time | ||||
6.667 | 0.000 | dma_clk | ||||
6.667 | 0.000 | tCL | FF | 1673 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
6.928 | 0.261 | tNET | FF | 1 | R62C46[0][A] | vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_16_128_inst/fifo_inst/reset_r_Z[1]/CLK |
7.160 | 0.232 | tC2Q | FF | 63 | R62C46[0][A] | vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_16_128_inst/fifo_inst/reset_r_Z[1]/Q |
8.650 | 1.489 | tNET | FF | 32 | BSRAM_R54[12] | vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_16_128_inst/fifo_inst/mem_3_2_mem_3_2_0_0/RESETB |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
13.333 | 13.333 | active clock edge time | ||||
13.333 | 0.000 | dma_clk | ||||
13.333 | 0.000 | tCL | RR | 1673 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
13.576 | 0.243 | tNET | RR | 1 | BSRAM_R54[12] | vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_16_128_inst/fifo_inst/mem_3_2_mem_3_2_0_0/CLKB |
13.138 | -0.438 | tSu | 1 | BSRAM_R54[12] | vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_16_128_inst/fifo_inst/mem_3_2_mem_3_2_0_0 |
Path Statistics:
Clock Skew | -0.018 |
Setup Relationship | 6.666 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.261, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.489, 86.521%; tC2Q: 0.232, 13.479% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path13
Path Summary:
Slack | 4.489 |
Data Arrival Time | 8.650 |
Data Required Time | 13.138 |
From | vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_16_128_inst/fifo_inst/reset_r_Z[1] |
To | vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_16_128_inst/fifo_inst/mem_3_3_mem_3_3_0_0 |
Launch Clk | dma_clk:[F] |
Latch Clk | dma_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.667 | 6.667 | active clock edge time | ||||
6.667 | 0.000 | dma_clk | ||||
6.667 | 0.000 | tCL | FF | 1673 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
6.928 | 0.261 | tNET | FF | 1 | R62C46[0][A] | vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_16_128_inst/fifo_inst/reset_r_Z[1]/CLK |
7.160 | 0.232 | tC2Q | FF | 63 | R62C46[0][A] | vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_16_128_inst/fifo_inst/reset_r_Z[1]/Q |
8.650 | 1.489 | tNET | FF | 32 | BSRAM_R54[11] | vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_16_128_inst/fifo_inst/mem_3_3_mem_3_3_0_0/RESETB |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
13.333 | 13.333 | active clock edge time | ||||
13.333 | 0.000 | dma_clk | ||||
13.333 | 0.000 | tCL | RR | 1673 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
13.576 | 0.243 | tNET | RR | 1 | BSRAM_R54[11] | vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_16_128_inst/fifo_inst/mem_3_3_mem_3_3_0_0/CLKB |
13.138 | -0.438 | tSu | 1 | BSRAM_R54[11] | vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_16_128_inst/fifo_inst/mem_3_3_mem_3_3_0_0 |
Path Statistics:
Clock Skew | -0.018 |
Setup Relationship | 6.666 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.261, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.489, 86.521%; tC2Q: 0.232, 13.479% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path14
Path Summary:
Slack | 9.199 |
Data Arrival Time | 4.342 |
Data Required Time | 13.541 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0 |
To | vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_1_s1 |
Launch Clk | dma_clk:[R] |
Latch Clk | dma_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | dma_clk | ||||
0.000 | 0.000 | tCL | RR | 1673 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R69C21[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 358 | R69C21[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q |
2.516 | 2.041 | tNET | FF | 1 | R68C43[1][A] | O_led_d_0_s0/I0 |
3.071 | 0.555 | tINS | FF | 130 | R68C43[1][A] | O_led_d_0_s0/F |
4.342 | 1.271 | tNET | FF | 1 | R65C45[0][B] | vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_1_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
13.333 | 13.333 | active clock edge time | ||||
13.333 | 0.000 | dma_clk | ||||
13.333 | 0.000 | tCL | RR | 1673 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
13.576 | 0.243 | tNET | RR | 1 | R65C45[0][B] | vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_1_s1/CLK |
13.541 | -0.035 | tSu | 1 | R65C45[0][B] | vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_1_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 13.333 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 0.555, 13.542%; route: 3.312, 80.798%; tC2Q: 0.232, 5.661% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path15
Path Summary:
Slack | 9.199 |
Data Arrival Time | 4.342 |
Data Required Time | 13.541 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0 |
To | vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_2_s1 |
Launch Clk | dma_clk:[R] |
Latch Clk | dma_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | dma_clk | ||||
0.000 | 0.000 | tCL | RR | 1673 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R69C21[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 358 | R69C21[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q |
2.516 | 2.041 | tNET | FF | 1 | R68C43[1][A] | O_led_d_0_s0/I0 |
3.071 | 0.555 | tINS | FF | 130 | R68C43[1][A] | O_led_d_0_s0/F |
4.342 | 1.271 | tNET | FF | 1 | R65C45[1][A] | vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_2_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
13.333 | 13.333 | active clock edge time | ||||
13.333 | 0.000 | dma_clk | ||||
13.333 | 0.000 | tCL | RR | 1673 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
13.576 | 0.243 | tNET | RR | 1 | R65C45[1][A] | vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_2_s1/CLK |
13.541 | -0.035 | tSu | 1 | R65C45[1][A] | vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_2_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 13.333 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 0.555, 13.542%; route: 3.312, 80.798%; tC2Q: 0.232, 5.661% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path16
Path Summary:
Slack | 9.205 |
Data Arrival Time | 4.336 |
Data Required Time | 13.541 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0 |
To | vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_0_s1 |
Launch Clk | dma_clk:[R] |
Latch Clk | dma_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | dma_clk | ||||
0.000 | 0.000 | tCL | RR | 1673 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R69C21[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 358 | R69C21[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q |
2.516 | 2.041 | tNET | FF | 1 | R68C43[1][A] | O_led_d_0_s0/I0 |
3.071 | 0.555 | tINS | FF | 130 | R68C43[1][A] | O_led_d_0_s0/F |
4.336 | 1.265 | tNET | FF | 1 | R64C47[2][A] | vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_0_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
13.333 | 13.333 | active clock edge time | ||||
13.333 | 0.000 | dma_clk | ||||
13.333 | 0.000 | tCL | RR | 1673 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
13.576 | 0.243 | tNET | RR | 1 | R64C47[2][A] | vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_0_s1/CLK |
13.541 | -0.035 | tSu | 1 | R64C47[2][A] | vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_0_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 13.333 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 0.555, 13.560%; route: 3.306, 80.771%; tC2Q: 0.232, 5.669% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path17
Path Summary:
Slack | 9.525 |
Data Arrival Time | 4.017 |
Data Required Time | 13.541 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0 |
To | vfb_top_inst/u_dma_bus_arbiter/current_state.ST_IDLE_s0 |
Launch Clk | dma_clk:[R] |
Latch Clk | dma_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | dma_clk | ||||
0.000 | 0.000 | tCL | RR | 1673 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R69C21[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 358 | R69C21[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q |
2.516 | 2.041 | tNET | FF | 1 | R68C43[1][A] | O_led_d_0_s0/I0 |
3.071 | 0.555 | tINS | FF | 130 | R68C43[1][A] | O_led_d_0_s0/F |
4.017 | 0.946 | tNET | FF | 1 | R72C43[0][A] | vfb_top_inst/u_dma_bus_arbiter/current_state.ST_IDLE_s0/PRESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
13.333 | 13.333 | active clock edge time | ||||
13.333 | 0.000 | dma_clk | ||||
13.333 | 0.000 | tCL | RR | 1673 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
13.576 | 0.243 | tNET | RR | 1 | R72C43[0][A] | vfb_top_inst/u_dma_bus_arbiter/current_state.ST_IDLE_s0/CLK |
13.541 | -0.035 | tSu | 1 | R72C43[0][A] | vfb_top_inst/u_dma_bus_arbiter/current_state.ST_IDLE_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 13.333 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 0.555, 14.708%; route: 2.986, 79.143%; tC2Q: 0.232, 6.148% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path18
Path Summary:
Slack | 9.538 |
Data Arrival Time | 4.003 |
Data Required Time | 13.541 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0 |
To | vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_0_s3 |
Launch Clk | dma_clk:[R] |
Latch Clk | dma_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | dma_clk | ||||
0.000 | 0.000 | tCL | RR | 1673 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R69C21[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 358 | R69C21[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q |
2.516 | 2.041 | tNET | FF | 1 | R68C43[1][A] | O_led_d_0_s0/I0 |
3.071 | 0.555 | tINS | FF | 130 | R68C43[1][A] | O_led_d_0_s0/F |
4.003 | 0.932 | tNET | FF | 1 | R69C49[0][A] | vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_0_s3/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
13.333 | 13.333 | active clock edge time | ||||
13.333 | 0.000 | dma_clk | ||||
13.333 | 0.000 | tCL | RR | 1673 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
13.576 | 0.243 | tNET | RR | 1 | R69C49[0][A] | vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_0_s3/CLK |
13.541 | -0.035 | tSu | 1 | R69C49[0][A] | vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_0_s3 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 13.333 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 0.555, 14.761%; route: 2.973, 79.069%; tC2Q: 0.232, 6.170% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path19
Path Summary:
Slack | 9.619 |
Data Arrival Time | 3.922 |
Data Required Time | 13.541 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0 |
To | vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_1_s3 |
Launch Clk | dma_clk:[R] |
Latch Clk | dma_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | dma_clk | ||||
0.000 | 0.000 | tCL | RR | 1673 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R69C21[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 358 | R69C21[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q |
2.516 | 2.041 | tNET | FF | 1 | R68C43[1][A] | O_led_d_0_s0/I0 |
3.071 | 0.555 | tINS | FF | 130 | R68C43[1][A] | O_led_d_0_s0/F |
3.922 | 0.851 | tNET | FF | 1 | R69C50[2][B] | vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_1_s3/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
13.333 | 13.333 | active clock edge time | ||||
13.333 | 0.000 | dma_clk | ||||
13.333 | 0.000 | tCL | RR | 1673 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
13.576 | 0.243 | tNET | RR | 1 | R69C50[2][B] | vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_1_s3/CLK |
13.541 | -0.035 | tSu | 1 | R69C50[2][B] | vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_1_s3 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 13.333 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 0.555, 15.087%; route: 2.892, 78.606%; tC2Q: 0.232, 6.307% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path20
Path Summary:
Slack | 9.619 |
Data Arrival Time | 3.922 |
Data Required Time | 13.541 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0 |
To | vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_3_s3 |
Launch Clk | dma_clk:[R] |
Latch Clk | dma_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | dma_clk | ||||
0.000 | 0.000 | tCL | RR | 1673 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R69C21[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 358 | R69C21[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q |
2.516 | 2.041 | tNET | FF | 1 | R68C43[1][A] | O_led_d_0_s0/I0 |
3.071 | 0.555 | tINS | FF | 130 | R68C43[1][A] | O_led_d_0_s0/F |
3.922 | 0.851 | tNET | FF | 1 | R69C50[2][A] | vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_3_s3/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
13.333 | 13.333 | active clock edge time | ||||
13.333 | 0.000 | dma_clk | ||||
13.333 | 0.000 | tCL | RR | 1673 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
13.576 | 0.243 | tNET | RR | 1 | R69C50[2][A] | vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_3_s3/CLK |
13.541 | -0.035 | tSu | 1 | R69C50[2][A] | vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_3_s3 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 13.333 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 0.555, 15.087%; route: 2.892, 78.606%; tC2Q: 0.232, 6.307% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path21
Path Summary:
Slack | 9.619 |
Data Arrival Time | 3.922 |
Data Required Time | 13.541 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0 |
To | vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_4_s3 |
Launch Clk | dma_clk:[R] |
Latch Clk | dma_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | dma_clk | ||||
0.000 | 0.000 | tCL | RR | 1673 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R69C21[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 358 | R69C21[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q |
2.516 | 2.041 | tNET | FF | 1 | R68C43[1][A] | O_led_d_0_s0/I0 |
3.071 | 0.555 | tINS | FF | 130 | R68C43[1][A] | O_led_d_0_s0/F |
3.922 | 0.851 | tNET | FF | 1 | R69C50[1][B] | vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_4_s3/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
13.333 | 13.333 | active clock edge time | ||||
13.333 | 0.000 | dma_clk | ||||
13.333 | 0.000 | tCL | RR | 1673 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
13.576 | 0.243 | tNET | RR | 1 | R69C50[1][B] | vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_4_s3/CLK |
13.541 | -0.035 | tSu | 1 | R69C50[1][B] | vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_4_s3 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 13.333 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 0.555, 15.087%; route: 2.892, 78.606%; tC2Q: 0.232, 6.307% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path22
Path Summary:
Slack | 9.619 |
Data Arrival Time | 3.922 |
Data Required Time | 13.541 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0 |
To | vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_5_s3 |
Launch Clk | dma_clk:[R] |
Latch Clk | dma_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | dma_clk | ||||
0.000 | 0.000 | tCL | RR | 1673 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R69C21[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 358 | R69C21[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q |
2.516 | 2.041 | tNET | FF | 1 | R68C43[1][A] | O_led_d_0_s0/I0 |
3.071 | 0.555 | tINS | FF | 130 | R68C43[1][A] | O_led_d_0_s0/F |
3.922 | 0.851 | tNET | FF | 1 | R69C50[1][A] | vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_5_s3/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
13.333 | 13.333 | active clock edge time | ||||
13.333 | 0.000 | dma_clk | ||||
13.333 | 0.000 | tCL | RR | 1673 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
13.576 | 0.243 | tNET | RR | 1 | R69C50[1][A] | vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_5_s3/CLK |
13.541 | -0.035 | tSu | 1 | R69C50[1][A] | vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_5_s3 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 13.333 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 0.555, 15.087%; route: 2.892, 78.606%; tC2Q: 0.232, 6.307% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path23
Path Summary:
Slack | 9.619 |
Data Arrival Time | 3.922 |
Data Required Time | 13.541 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0 |
To | vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_3_s1 |
Launch Clk | dma_clk:[R] |
Latch Clk | dma_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | dma_clk | ||||
0.000 | 0.000 | tCL | RR | 1673 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R69C21[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 358 | R69C21[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q |
2.516 | 2.041 | tNET | FF | 1 | R68C43[1][A] | O_led_d_0_s0/I0 |
3.071 | 0.555 | tINS | FF | 130 | R68C43[1][A] | O_led_d_0_s0/F |
3.922 | 0.851 | tNET | FF | 1 | R64C50[0][A] | vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_3_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
13.333 | 13.333 | active clock edge time | ||||
13.333 | 0.000 | dma_clk | ||||
13.333 | 0.000 | tCL | RR | 1673 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
13.576 | 0.243 | tNET | RR | 1 | R64C50[0][A] | vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_3_s1/CLK |
13.541 | -0.035 | tSu | 1 | R64C50[0][A] | vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_3_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 13.333 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 0.555, 15.087%; route: 2.892, 78.606%; tC2Q: 0.232, 6.307% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path24
Path Summary:
Slack | 9.619 |
Data Arrival Time | 3.922 |
Data Required Time | 13.541 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0 |
To | vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_4_s1 |
Launch Clk | dma_clk:[R] |
Latch Clk | dma_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | dma_clk | ||||
0.000 | 0.000 | tCL | RR | 1673 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R69C21[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 358 | R69C21[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q |
2.516 | 2.041 | tNET | FF | 1 | R68C43[1][A] | O_led_d_0_s0/I0 |
3.071 | 0.555 | tINS | FF | 130 | R68C43[1][A] | O_led_d_0_s0/F |
3.922 | 0.851 | tNET | FF | 1 | R65C50[2][B] | vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_4_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
13.333 | 13.333 | active clock edge time | ||||
13.333 | 0.000 | dma_clk | ||||
13.333 | 0.000 | tCL | RR | 1673 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
13.576 | 0.243 | tNET | RR | 1 | R65C50[2][B] | vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_4_s1/CLK |
13.541 | -0.035 | tSu | 1 | R65C50[2][B] | vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_4_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 13.333 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 0.555, 15.087%; route: 2.892, 78.606%; tC2Q: 0.232, 6.307% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path25
Path Summary:
Slack | 9.619 |
Data Arrival Time | 3.922 |
Data Required Time | 13.541 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0 |
To | vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_5_s1 |
Launch Clk | dma_clk:[R] |
Latch Clk | dma_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | dma_clk | ||||
0.000 | 0.000 | tCL | RR | 1673 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R69C21[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 358 | R69C21[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q |
2.516 | 2.041 | tNET | FF | 1 | R68C43[1][A] | O_led_d_0_s0/I0 |
3.071 | 0.555 | tINS | FF | 130 | R68C43[1][A] | O_led_d_0_s0/F |
3.922 | 0.851 | tNET | FF | 1 | R65C50[1][B] | vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_5_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
13.333 | 13.333 | active clock edge time | ||||
13.333 | 0.000 | dma_clk | ||||
13.333 | 0.000 | tCL | RR | 1673 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
13.576 | 0.243 | tNET | RR | 1 | R65C50[1][B] | vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_5_s1/CLK |
13.541 | -0.035 | tSu | 1 | R65C50[1][B] | vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_5_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 13.333 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 0.555, 15.087%; route: 2.892, 78.606%; tC2Q: 0.232, 6.307% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Removal Analysis Report
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 0.456 |
Data Arrival Time | 0.651 |
Data Required Time | 0.195 |
From | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync1_s0 |
To | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U1/wq1_rptr_0_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 398 | TOPSIDE[0] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R17C14[2][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync1_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 29 | R17C14[2][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync1_s0/Q |
0.651 | 0.265 | tNET | RR | 1 | R20C14[0][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U1/wq1_rptr_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 398 | TOPSIDE[0] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R20C14[0][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U1/wq1_rptr_0_s0/CLK |
0.195 | 0.011 | tHld | 1 | R20C14[0][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U1/wq1_rptr_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.265, 56.766%; tC2Q: 0.202, 43.234% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path2
Path Summary:
Slack | 0.456 |
Data Arrival Time | 0.651 |
Data Required Time | 0.195 |
From | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync1_s0 |
To | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U1/wq1_rptr_1_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 398 | TOPSIDE[0] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R17C14[2][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync1_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 29 | R17C14[2][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync1_s0/Q |
0.651 | 0.265 | tNET | RR | 1 | R20C14[0][B] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U1/wq1_rptr_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 398 | TOPSIDE[0] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R20C14[0][B] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U1/wq1_rptr_1_s0/CLK |
0.195 | 0.011 | tHld | 1 | R20C14[0][B] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U1/wq1_rptr_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.265, 56.766%; tC2Q: 0.202, 43.234% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path3
Path Summary:
Slack | 0.460 |
Data Arrival Time | 0.656 |
Data Required Time | 0.195 |
From | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync0_s0 |
To | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U0/Full_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 398 | TOPSIDE[0] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R17C20[2][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync0_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 29 | R17C20[2][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync0_s0/Q |
0.656 | 0.269 | tNET | RR | 1 | R18C22[0][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U0/Full_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 398 | TOPSIDE[0] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R18C22[0][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U0/Full_s0/CLK |
0.195 | 0.011 | tHld | 1 | R18C22[0][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U0/Full_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.269, 57.153%; tC2Q: 0.202, 42.847% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path4
Path Summary:
Slack | 0.460 |
Data Arrival Time | 0.656 |
Data Required Time | 0.195 |
From | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync0_s0 |
To | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U0/wq2_rptr_1_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 398 | TOPSIDE[0] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R17C20[2][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync0_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 29 | R17C20[2][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync0_s0/Q |
0.656 | 0.269 | tNET | RR | 1 | R18C22[1][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U0/wq2_rptr_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 398 | TOPSIDE[0] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R18C22[1][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U0/wq2_rptr_1_s0/CLK |
0.195 | 0.011 | tHld | 1 | R18C22[1][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U0/wq2_rptr_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.269, 57.153%; tC2Q: 0.202, 42.847% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path5
Path Summary:
Slack | 0.460 |
Data Arrival Time | 0.656 |
Data Required Time | 0.195 |
From | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync0_s0 |
To | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U0/wq2_rptr_3_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 398 | TOPSIDE[0] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R17C20[2][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync0_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 29 | R17C20[2][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync0_s0/Q |
0.656 | 0.269 | tNET | RR | 1 | R18C22[0][B] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U0/wq2_rptr_3_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 398 | TOPSIDE[0] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R18C22[0][B] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U0/wq2_rptr_3_s0/CLK |
0.195 | 0.011 | tHld | 1 | R18C22[0][B] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U0/wq2_rptr_3_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.269, 57.153%; tC2Q: 0.202, 42.847% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path6
Path Summary:
Slack | 0.462 |
Data Arrival Time | 0.657 |
Data Required Time | 0.195 |
From | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync0_s0 |
To | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U0/wbin_0_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 398 | TOPSIDE[0] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R17C20[2][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync0_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 29 | R17C20[2][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync0_s0/Q |
0.657 | 0.271 | tNET | RR | 1 | R18C21[0][B] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U0/wbin_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 398 | TOPSIDE[0] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R18C21[0][B] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U0/wbin_0_s0/CLK |
0.195 | 0.011 | tHld | 1 | R18C21[0][B] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U0/wbin_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.271, 57.259%; tC2Q: 0.202, 42.741% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path7
Path Summary:
Slack | 0.462 |
Data Arrival Time | 0.657 |
Data Required Time | 0.195 |
From | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync0_s0 |
To | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U0/wbin_1_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 398 | TOPSIDE[0] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R17C20[2][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync0_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 29 | R17C20[2][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync0_s0/Q |
0.657 | 0.271 | tNET | RR | 1 | R18C21[0][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U0/wbin_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 398 | TOPSIDE[0] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R18C21[0][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U0/wbin_1_s0/CLK |
0.195 | 0.011 | tHld | 1 | R18C21[0][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U0/wbin_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.271, 57.259%; tC2Q: 0.202, 42.741% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path8
Path Summary:
Slack | 0.462 |
Data Arrival Time | 0.657 |
Data Required Time | 0.195 |
From | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync0_s0 |
To | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U0/wbin_4_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 398 | TOPSIDE[0] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R17C20[2][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync0_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 29 | R17C20[2][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync0_s0/Q |
0.657 | 0.271 | tNET | RR | 1 | R18C21[1][B] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U0/wbin_4_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 398 | TOPSIDE[0] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R18C21[1][B] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U0/wbin_4_s0/CLK |
0.195 | 0.011 | tHld | 1 | R18C21[1][B] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U0/wbin_4_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.271, 57.259%; tC2Q: 0.202, 42.741% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path9
Path Summary:
Slack | 0.462 |
Data Arrival Time | 0.657 |
Data Required Time | 0.195 |
From | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync0_s0 |
To | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U0/wq2_rptr_0_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 398 | TOPSIDE[0] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R17C20[2][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync0_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 29 | R17C20[2][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync0_s0/Q |
0.657 | 0.271 | tNET | RR | 1 | R18C21[1][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U0/wq2_rptr_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 398 | TOPSIDE[0] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R18C21[1][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U0/wq2_rptr_0_s0/CLK |
0.195 | 0.011 | tHld | 1 | R18C21[1][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U0/wq2_rptr_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.271, 57.259%; tC2Q: 0.202, 42.741% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path10
Path Summary:
Slack | 0.462 |
Data Arrival Time | 0.657 |
Data Required Time | 0.195 |
From | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync1_s0 |
To | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U1/Full_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 398 | TOPSIDE[0] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R17C14[2][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync1_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 29 | R17C14[2][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync1_s0/Q |
0.657 | 0.271 | tNET | RR | 1 | R18C15[0][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U1/Full_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 398 | TOPSIDE[0] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R18C15[0][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U1/Full_s0/CLK |
0.195 | 0.011 | tHld | 1 | R18C15[0][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U1/Full_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.271, 57.314%; tC2Q: 0.202, 42.686% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path11
Path Summary:
Slack | 0.462 |
Data Arrival Time | 0.657 |
Data Required Time | 0.195 |
From | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync1_s0 |
To | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U1/wbin_0_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 398 | TOPSIDE[0] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R17C14[2][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync1_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 29 | R17C14[2][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync1_s0/Q |
0.657 | 0.271 | tNET | RR | 1 | R18C13[2][B] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U1/wbin_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 398 | TOPSIDE[0] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R18C13[2][B] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U1/wbin_0_s0/CLK |
0.195 | 0.011 | tHld | 1 | R18C13[2][B] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U1/wbin_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.271, 57.314%; tC2Q: 0.202, 42.686% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path12
Path Summary:
Slack | 0.462 |
Data Arrival Time | 0.657 |
Data Required Time | 0.195 |
From | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync1_s0 |
To | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U1/wbin_1_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 398 | TOPSIDE[0] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R17C14[2][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync1_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 29 | R17C14[2][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync1_s0/Q |
0.657 | 0.271 | tNET | RR | 1 | R18C13[0][B] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U1/wbin_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 398 | TOPSIDE[0] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R18C13[0][B] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U1/wbin_1_s0/CLK |
0.195 | 0.011 | tHld | 1 | R18C13[0][B] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U1/wbin_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.271, 57.314%; tC2Q: 0.202, 42.686% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path13
Path Summary:
Slack | 0.462 |
Data Arrival Time | 0.657 |
Data Required Time | 0.195 |
From | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync1_s0 |
To | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U1/wbin_2_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 398 | TOPSIDE[0] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R17C14[2][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync1_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 29 | R17C14[2][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync1_s0/Q |
0.657 | 0.271 | tNET | RR | 1 | R18C13[0][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U1/wbin_2_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 398 | TOPSIDE[0] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R18C13[0][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U1/wbin_2_s0/CLK |
0.195 | 0.011 | tHld | 1 | R18C13[0][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U1/wbin_2_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.271, 57.314%; tC2Q: 0.202, 42.686% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path14
Path Summary:
Slack | 0.462 |
Data Arrival Time | 0.657 |
Data Required Time | 0.195 |
From | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync1_s0 |
To | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U1/wbin_3_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 398 | TOPSIDE[0] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R17C14[2][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync1_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 29 | R17C14[2][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync1_s0/Q |
0.657 | 0.271 | tNET | RR | 1 | R18C15[2][B] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U1/wbin_3_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 398 | TOPSIDE[0] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R18C15[2][B] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U1/wbin_3_s0/CLK |
0.195 | 0.011 | tHld | 1 | R18C15[2][B] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U1/wbin_3_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.271, 57.314%; tC2Q: 0.202, 42.686% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path15
Path Summary:
Slack | 0.462 |
Data Arrival Time | 0.657 |
Data Required Time | 0.195 |
From | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync1_s0 |
To | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U1/wbin_4_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 398 | TOPSIDE[0] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R17C14[2][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync1_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 29 | R17C14[2][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync1_s0/Q |
0.657 | 0.271 | tNET | RR | 1 | R18C15[1][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U1/wbin_4_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 398 | TOPSIDE[0] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R18C15[1][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U1/wbin_4_s0/CLK |
0.195 | 0.011 | tHld | 1 | R18C15[1][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U1/wbin_4_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.271, 57.314%; tC2Q: 0.202, 42.686% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path16
Path Summary:
Slack | 0.462 |
Data Arrival Time | 0.657 |
Data Required Time | 0.195 |
From | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync1_s0 |
To | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U1/rbin_1_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 398 | TOPSIDE[0] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R17C14[2][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync1_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 29 | R17C14[2][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync1_s0/Q |
0.657 | 0.271 | tNET | RR | 1 | R18C15[2][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U1/rbin_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 398 | TOPSIDE[0] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R18C15[2][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U1/rbin_1_s0/CLK |
0.195 | 0.011 | tHld | 1 | R18C15[2][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U1/rbin_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.271, 57.314%; tC2Q: 0.202, 42.686% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path17
Path Summary:
Slack | 0.462 |
Data Arrival Time | 0.657 |
Data Required Time | 0.195 |
From | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync1_s0 |
To | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U1/rbin_2_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 398 | TOPSIDE[0] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R17C14[2][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync1_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 29 | R17C14[2][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync1_s0/Q |
0.657 | 0.271 | tNET | RR | 1 | R18C15[1][B] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U1/rbin_2_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 398 | TOPSIDE[0] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R18C15[1][B] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U1/rbin_2_s0/CLK |
0.195 | 0.011 | tHld | 1 | R18C15[1][B] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U1/rbin_2_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.271, 57.314%; tC2Q: 0.202, 42.686% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path18
Path Summary:
Slack | 0.462 |
Data Arrival Time | 0.657 |
Data Required Time | 0.195 |
From | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync1_s0 |
To | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U1/wq2_rptr_1_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 398 | TOPSIDE[0] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R17C14[2][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync1_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 29 | R17C14[2][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync1_s0/Q |
0.657 | 0.271 | tNET | RR | 1 | R18C13[1][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U1/wq2_rptr_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 398 | TOPSIDE[0] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R18C13[1][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U1/wq2_rptr_1_s0/CLK |
0.195 | 0.011 | tHld | 1 | R18C13[1][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U1/wq2_rptr_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.271, 57.314%; tC2Q: 0.202, 42.686% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path19
Path Summary:
Slack | 0.462 |
Data Arrival Time | 0.657 |
Data Required Time | 0.195 |
From | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync1_s0 |
To | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U1/wq2_rptr_3_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 398 | TOPSIDE[0] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R17C14[2][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync1_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 29 | R17C14[2][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync1_s0/Q |
0.657 | 0.271 | tNET | RR | 1 | R18C15[0][B] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U1/wq2_rptr_3_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 398 | TOPSIDE[0] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R18C15[0][B] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U1/wq2_rptr_3_s0/CLK |
0.195 | 0.011 | tHld | 1 | R18C15[0][B] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U1/wq2_rptr_3_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.271, 57.314%; tC2Q: 0.202, 42.686% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path20
Path Summary:
Slack | 0.463 |
Data Arrival Time | 0.659 |
Data Required Time | 0.195 |
From | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync0_s0 |
To | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U0/wbin_2_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 398 | TOPSIDE[0] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R17C20[2][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync0_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 29 | R17C20[2][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync0_s0/Q |
0.659 | 0.272 | tNET | RR | 1 | R18C19[0][B] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U0/wbin_2_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 398 | TOPSIDE[0] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R18C19[0][B] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U0/wbin_2_s0/CLK |
0.195 | 0.011 | tHld | 1 | R18C19[0][B] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U0/wbin_2_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.272, 57.424%; tC2Q: 0.202, 42.576% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path21
Path Summary:
Slack | 0.463 |
Data Arrival Time | 0.659 |
Data Required Time | 0.195 |
From | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync0_s0 |
To | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U0/wbin_3_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 398 | TOPSIDE[0] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R17C20[2][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync0_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 29 | R17C20[2][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync0_s0/Q |
0.659 | 0.272 | tNET | RR | 1 | R18C19[1][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U0/wbin_3_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 398 | TOPSIDE[0] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R18C19[1][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U0/wbin_3_s0/CLK |
0.195 | 0.011 | tHld | 1 | R18C19[1][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U0/wbin_3_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.272, 57.424%; tC2Q: 0.202, 42.576% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path22
Path Summary:
Slack | 0.463 |
Data Arrival Time | 0.659 |
Data Required Time | 0.195 |
From | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync0_s0 |
To | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U0/rbin_0_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 398 | TOPSIDE[0] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R17C20[2][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync0_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 29 | R17C20[2][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync0_s0/Q |
0.659 | 0.272 | tNET | RR | 1 | R18C18[1][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U0/rbin_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 398 | TOPSIDE[0] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R18C18[1][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U0/rbin_0_s0/CLK |
0.195 | 0.011 | tHld | 1 | R18C18[1][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U0/rbin_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.272, 57.424%; tC2Q: 0.202, 42.576% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path23
Path Summary:
Slack | 0.463 |
Data Arrival Time | 0.659 |
Data Required Time | 0.195 |
From | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync0_s0 |
To | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U0/rbin_1_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 398 | TOPSIDE[0] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R17C20[2][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync0_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 29 | R17C20[2][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync0_s0/Q |
0.659 | 0.272 | tNET | RR | 1 | R18C18[2][B] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U0/rbin_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 398 | TOPSIDE[0] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R18C18[2][B] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U0/rbin_1_s0/CLK |
0.195 | 0.011 | tHld | 1 | R18C18[2][B] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U0/rbin_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.272, 57.424%; tC2Q: 0.202, 42.576% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path24
Path Summary:
Slack | 0.463 |
Data Arrival Time | 0.659 |
Data Required Time | 0.195 |
From | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync0_s0 |
To | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U0/rbin_3_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 398 | TOPSIDE[0] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R17C20[2][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync0_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 29 | R17C20[2][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync0_s0/Q |
0.659 | 0.272 | tNET | RR | 1 | R18C18[1][B] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U0/rbin_3_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 398 | TOPSIDE[0] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R18C18[1][B] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U0/rbin_3_s0/CLK |
0.195 | 0.011 | tHld | 1 | R18C18[1][B] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U0/rbin_3_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.272, 57.424%; tC2Q: 0.202, 42.576% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path25
Path Summary:
Slack | 0.463 |
Data Arrival Time | 0.659 |
Data Required Time | 0.195 |
From | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync0_s0 |
To | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U0/rptr_0_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 398 | TOPSIDE[0] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R17C20[2][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync0_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 29 | R17C20[2][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/sync0_s0/Q |
0.659 | 0.272 | tNET | RR | 1 | R18C19[2][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U0/rptr_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 398 | TOPSIDE[0] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R18C19[2][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U0/rptr_0_s0/CLK |
0.195 | 0.011 | tHld | 1 | R18C19[2][A] | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_Aligner/ln0/U0/rptr_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.272, 57.424%; tC2Q: 0.202, 42.576% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Minimum Pulse Width Report:
Report Command:report_min_pulse_width -nworst 10 -detail
MPW1
MPW Summary:
Slack: | 0.474 |
Actual Width: | 1.474 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | I_CSI_CKP |
Objects: | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/opensync_2_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
1.562 | 0.000 | active clock edge time | ||
1.562 | 0.000 | I_CSI_CKP | ||
1.562 | 0.000 | tCL | FF | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/U0_IB/I |
2.250 | 0.688 | tINS | FF | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/U0_IB/O |
2.511 | 0.261 | tNET | FF | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/opensync_2_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
3.125 | 0.000 | active clock edge time | ||
3.125 | 0.000 | I_CSI_CKP | ||
3.125 | 0.000 | tCL | RR | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/U0_IB/I |
3.800 | 0.675 | tINS | RR | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/U0_IB/O |
3.985 | 0.184 | tNET | RR | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/opensync_2_s0/CLK |
MPW2
MPW Summary:
Slack: | 0.474 |
Actual Width: | 1.474 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | I_CSI_CKP |
Objects: | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/opensync_1_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
1.562 | 0.000 | active clock edge time | ||
1.562 | 0.000 | I_CSI_CKP | ||
1.562 | 0.000 | tCL | FF | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/U0_IB/I |
2.250 | 0.688 | tINS | FF | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/U0_IB/O |
2.511 | 0.261 | tNET | FF | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/opensync_1_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
3.125 | 0.000 | active clock edge time | ||
3.125 | 0.000 | I_CSI_CKP | ||
3.125 | 0.000 | tCL | RR | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/U0_IB/I |
3.800 | 0.675 | tINS | RR | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/U0_IB/O |
3.985 | 0.184 | tNET | RR | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/opensync_1_s0/CLK |
MPW3
MPW Summary:
Slack: | 0.474 |
Actual Width: | 1.474 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | I_CSI_CKP |
Objects: | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/opensync_3_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
1.562 | 0.000 | active clock edge time | ||
1.562 | 0.000 | I_CSI_CKP | ||
1.562 | 0.000 | tCL | FF | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/U0_IB/I |
2.250 | 0.688 | tINS | FF | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/U0_IB/O |
2.511 | 0.261 | tNET | FF | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/opensync_3_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
3.125 | 0.000 | active clock edge time | ||
3.125 | 0.000 | I_CSI_CKP | ||
3.125 | 0.000 | tCL | RR | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/U0_IB/I |
3.800 | 0.675 | tINS | RR | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/U0_IB/O |
3.985 | 0.184 | tNET | RR | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/opensync_3_s0/CLK |
MPW4
MPW Summary:
Slack: | 0.474 |
Actual Width: | 1.474 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | I_CSI_CKP |
Objects: | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/opensync_0_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
1.562 | 0.000 | active clock edge time | ||
1.562 | 0.000 | I_CSI_CKP | ||
1.562 | 0.000 | tCL | FF | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/U0_IB/I |
2.250 | 0.688 | tINS | FF | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/U0_IB/O |
2.511 | 0.261 | tNET | FF | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/opensync_0_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
3.125 | 0.000 | active clock edge time | ||
3.125 | 0.000 | I_CSI_CKP | ||
3.125 | 0.000 | tCL | RR | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/U0_IB/I |
3.800 | 0.675 | tINS | RR | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/U0_IB/O |
3.985 | 0.184 | tNET | RR | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/opensync_0_s0/CLK |
MPW5
MPW Summary:
Slack: | 0.508 |
Actual Width: | 1.508 |
Required Width: | 1.000 |
Type: | High Pulse Width |
Clock: | I_CSI_CKP |
Objects: | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/opensync_2_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||
0.000 | 0.000 | I_CSI_CKP | ||
0.000 | 0.000 | tCL | RR | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/U0_IB/I |
0.683 | 0.683 | tINS | RR | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/U0_IB/O |
0.926 | 0.243 | tNET | RR | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/opensync_2_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
1.562 | 0.000 | active clock edge time | ||
1.562 | 0.000 | I_CSI_CKP | ||
1.562 | 0.000 | tCL | FF | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/U0_IB/I |
2.240 | 0.678 | tINS | FF | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/U0_IB/O |
2.434 | 0.195 | tNET | FF | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/opensync_2_s0/CLK |
MPW6
MPW Summary:
Slack: | 0.508 |
Actual Width: | 1.508 |
Required Width: | 1.000 |
Type: | High Pulse Width |
Clock: | I_CSI_CKP |
Objects: | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/opensync_1_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||
0.000 | 0.000 | I_CSI_CKP | ||
0.000 | 0.000 | tCL | RR | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/U0_IB/I |
0.683 | 0.683 | tINS | RR | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/U0_IB/O |
0.926 | 0.243 | tNET | RR | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/opensync_1_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
1.562 | 0.000 | active clock edge time | ||
1.562 | 0.000 | I_CSI_CKP | ||
1.562 | 0.000 | tCL | FF | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/U0_IB/I |
2.240 | 0.678 | tINS | FF | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/U0_IB/O |
2.434 | 0.195 | tNET | FF | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/opensync_1_s0/CLK |
MPW7
MPW Summary:
Slack: | 0.508 |
Actual Width: | 1.508 |
Required Width: | 1.000 |
Type: | High Pulse Width |
Clock: | I_CSI_CKP |
Objects: | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/opensync_3_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||
0.000 | 0.000 | I_CSI_CKP | ||
0.000 | 0.000 | tCL | RR | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/U0_IB/I |
0.683 | 0.683 | tINS | RR | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/U0_IB/O |
0.926 | 0.243 | tNET | RR | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/opensync_3_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
1.562 | 0.000 | active clock edge time | ||
1.562 | 0.000 | I_CSI_CKP | ||
1.562 | 0.000 | tCL | FF | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/U0_IB/I |
2.240 | 0.678 | tINS | FF | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/U0_IB/O |
2.434 | 0.195 | tNET | FF | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/opensync_3_s0/CLK |
MPW8
MPW Summary:
Slack: | 0.508 |
Actual Width: | 1.508 |
Required Width: | 1.000 |
Type: | High Pulse Width |
Clock: | I_CSI_CKP |
Objects: | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/opensync_0_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||
0.000 | 0.000 | I_CSI_CKP | ||
0.000 | 0.000 | tCL | RR | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/U0_IB/I |
0.683 | 0.683 | tINS | RR | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/U0_IB/O |
0.926 | 0.243 | tNET | RR | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/opensync_0_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
1.562 | 0.000 | active clock edge time | ||
1.562 | 0.000 | I_CSI_CKP | ||
1.562 | 0.000 | tCL | FF | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/U0_IB/I |
2.240 | 0.678 | tINS | FF | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/U0_IB/O |
2.434 | 0.195 | tNET | FF | CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/opensync_0_s0/CLK |
MPW9
MPW Summary:
Slack: | 2.048 |
Actual Width: | 3.048 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | csi_clk |
Objects: | CSI2RAW8_inst/u_raw8_lane2/u_fifo16b_8b/fifo_inst/Empty_Z |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
3.125 | 0.000 | active clock edge time | ||
3.125 | 0.000 | csi_clk | ||
3.125 | 0.000 | tCL | FF | CSI2RAW8_inst/pll/pll_inst/CLKOUT |
3.386 | 0.261 | tNET | FF | CSI2RAW8_inst/u_raw8_lane2/u_fifo16b_8b/fifo_inst/Empty_Z/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
6.250 | 0.000 | active clock edge time | ||
6.250 | 0.000 | csi_clk | ||
6.250 | 0.000 | tCL | RR | CSI2RAW8_inst/pll/pll_inst/CLKOUT |
6.434 | 0.184 | tNET | RR | CSI2RAW8_inst/u_raw8_lane2/u_fifo16b_8b/fifo_inst/Empty_Z/CLK |
MPW10
MPW Summary:
Slack: | 2.048 |
Actual Width: | 3.048 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | csi_clk |
Objects: | CSI2RAW8_inst/u_raw8_lane2/u_fifo16b_8b/fifo_inst/Small.rq1_wptr_Z[0] |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
3.125 | 0.000 | active clock edge time | ||
3.125 | 0.000 | csi_clk | ||
3.125 | 0.000 | tCL | FF | CSI2RAW8_inst/pll/pll_inst/CLKOUT |
3.386 | 0.261 | tNET | FF | CSI2RAW8_inst/u_raw8_lane2/u_fifo16b_8b/fifo_inst/Small.rq1_wptr_Z[0]/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
6.250 | 0.000 | active clock edge time | ||
6.250 | 0.000 | csi_clk | ||
6.250 | 0.000 | tCL | RR | CSI2RAW8_inst/pll/pll_inst/CLKOUT |
6.434 | 0.184 | tNET | RR | CSI2RAW8_inst/u_raw8_lane2/u_fifo16b_8b/fifo_inst/Small.rq1_wptr_Z[0]/CLK |
High Fanout Nets Report:
Report Command:report_high_fanout_nets -max_nets 10
FANOUT | NET NAME | WORST SLACK | MAX DELAY |
---|---|---|---|
1673 | dma_clk | 3.390 | 0.261 |
1505 | n929_6 | 8.798 | 8.854 |
1178 | ddr_rst | 3.997 | 2.406 |
849 | dbgRstGen | 14.711 | 3.746 |
398 | byte_clk | 5.013 | 0.261 |
358 | init_calib_complete | 3.390 | 2.498 |
207 | AHB1HRESET_d | 8.798 | 2.244 |
187 | biu_rdy | 7.788 | 3.916 |
160 | mc_wrdata_dly_0_9 | 10.432 | 1.285 |
160 | mc_wrdata_dly_0_10 | 9.584 | 2.080 |
Route Congestions Report:
Report Command:report_route_congestion -max_grids 10
GRID LOC | ROUTE CONGESTIONS |
---|---|
R20C34 | 93.06% |
R30C74 | 91.67% |
R33C74 | 91.67% |
R56C66 | 91.67% |
R30C73 | 90.28% |
R35C62 | 90.28% |
R59C75 | 90.28% |
R58C73 | 88.89% |
R32C75 | 88.89% |
R57C69 | 88.89% |
Timing Exceptions Report:
Setup Analysis Report
Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Hold Analysis Report
Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Recovery Analysis Report
Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Removal Analysis Report
Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Timing Constraints Report:
SDC Command Type | State | Detail Command |
---|---|---|
TC_CLOCK | Actived | create_clock -name LCD_DCLK_d -period 30 -waveform {0 15} [get_nets {LCD_DCLK_d}] |
TC_CLOCK | Actived | create_clock -name I_clk -period 20 -waveform {0 10} [get_ports {I_clk}] |
TC_CLOCK | Actived | create_clock -name csi_clk -period 6.25 -waveform {0 3.125} [get_nets {csi_clk}] |
TC_CLOCK | Actived | create_clock -name I_CSI_CKP -period 3.125 -waveform {0 1.562} [get_ports {I_CSI_CKP}] |
TC_CLOCK | Actived | create_clock -name dma_clk -period 13.333 -waveform {0 6.667} [get_nets {dma_clk}] |
TC_CLOCK | Actived | create_clock -name ddr3_clk -period 3.333 -waveform {0 1.667} [get_nets {ddr3_clk}] |
TC_CLOCK | Actived | create_clock -name byte_clk -period 12.5 -waveform {0 6.25} [get_nets {CSI2RAW8_inst/byte_clk}] |
TC_CLOCK | Actived | create_clock -name ddr_rst -period 10 -waveform {0 5} [get_nets {DDR3_Memory_Interface_Top_inst/gw3_top/ddr_rst}] -add |
TC_FALSE_PATH | Actived | set_false_path -from [get_clocks {csi_clk}] |
TC_FALSE_PATH | Actived | set_false_path -from [get_clocks {I_CSI_CKP}] |
TC_FALSE_PATH | Actived | set_false_path -from [get_clocks {ddr_rst}] -to [get_clocks {ddr3_clk}] |
TC_CLOCK_GROUP | Actived | set_clock_groups -exclusive -group [get_clocks {I_clk}] -group [get_clocks {I_CSI_CKP}] -group [get_clocks {LCD_DCLK_d}] -group [get_clocks {ddr3_clk}] -group [get_clocks {byte_clk}] -group [get_clocks {csi_clk}] -group [get_clocks {dma_clk}] |
TC_CLOCK_GROUP | Actived | set_clock_groups -exclusive -group [get_clocks {dma_clk}] -group [get_clocks {ddr_rst}] |