Synthesis Messages

Report Title GowinSynthesis Report
Design File E:\W_File\ISP_V2\Onboard_230320\Gowin_ISP_RefDesign_0423_keil_SRAM\Gowin_ISP_RefDesign\FPGA_Design\src\ISP\AEAWB\AEAWB_top.v
E:\W_File\ISP_V2\Onboard_230320\Gowin_ISP_RefDesign_0423_keil_SRAM\Gowin_ISP_RefDesign\FPGA_Design\src\ISP\CCM\CCM_top.v
E:\W_File\ISP_V2\Onboard_230320\Gowin_ISP_RefDesign_0423_keil_SRAM\Gowin_ISP_RefDesign\FPGA_Design\src\ISP\CFA\cfa_top.v
E:\W_File\ISP_V2\Onboard_230320\Gowin_ISP_RefDesign_0423_keil_SRAM\Gowin_ISP_RefDesign\FPGA_Design\src\ISP\GAMMA\gamma_top.v
E:\W_File\ISP_V2\Onboard_230320\Gowin_ISP_RefDesign_0423_keil_SRAM\Gowin_ISP_RefDesign\FPGA_Design\src\ISP\isp_top.v
E:\W_File\ISP_V2\Onboard_230320\Gowin_ISP_RefDesign_0423_keil_SRAM\Gowin_ISP_RefDesign\FPGA_Design\src\ahb_isp.v
E:\W_File\ISP_V2\Onboard_230320\Gowin_ISP_RefDesign_0423_keil_SRAM\Gowin_ISP_RefDesign\FPGA_Design\src\bayer_to_rgb\bayer_rgb.v
E:\W_File\ISP_V2\Onboard_230320\Gowin_ISP_RefDesign_0423_keil_SRAM\Gowin_ISP_RefDesign\FPGA_Design\src\ddr3_memory_interface\ddr3_memory_interface.v
E:\W_File\ISP_V2\Onboard_230320\Gowin_ISP_RefDesign_0423_keil_SRAM\Gowin_ISP_RefDesign\FPGA_Design\src\ddr3_rpll\ddr3_rpll.v
E:\W_File\ISP_V2\Onboard_230320\Gowin_ISP_RefDesign_0423_keil_SRAM\Gowin_ISP_RefDesign\FPGA_Design\src\frame_buffer\fifo\fifo_dma_read_128_16.v
E:\W_File\ISP_V2\Onboard_230320\Gowin_ISP_RefDesign_0423_keil_SRAM\Gowin_ISP_RefDesign\FPGA_Design\src\frame_buffer\fifo\fifo_dma_write_16_128.v
E:\W_File\ISP_V2\Onboard_230320\Gowin_ISP_RefDesign_0423_keil_SRAM\Gowin_ISP_RefDesign\FPGA_Design\src\frame_buffer\vfb_top.v
E:\W_File\ISP_V2\Onboard_230320\Gowin_ISP_RefDesign_0423_keil_SRAM\Gowin_ISP_RefDesign\FPGA_Design\src\gowin_empu_m1\gowin_empu_m1.v
E:\W_File\ISP_V2\Onboard_230320\Gowin_ISP_RefDesign_0423_keil_SRAM\Gowin_ISP_RefDesign\FPGA_Design\src\gowin_rpll\gowin_rpll.v
E:\W_File\ISP_V2\Onboard_230320\Gowin_ISP_RefDesign_0423_keil_SRAM\Gowin_ISP_RefDesign\FPGA_Design\src\mipi_csi\CSI2RAW8.v
E:\W_File\ISP_V2\Onboard_230320\Gowin_ISP_RefDesign_0423_keil_SRAM\Gowin_ISP_RefDesign\FPGA_Design\src\mipi_csi\fifo_top\fifo16b_8b.v
E:\W_File\ISP_V2\Onboard_230320\Gowin_ISP_RefDesign_0423_keil_SRAM\Gowin_ISP_RefDesign\FPGA_Design\src\mipi_csi\mipi_rx_advance\mipi_rx_advance.v
E:\W_File\ISP_V2\Onboard_230320\Gowin_ISP_RefDesign_0423_keil_SRAM\Gowin_ISP_RefDesign\FPGA_Design\src\ov5647_init\OV5647_Controller.v
E:\W_File\ISP_V2\Onboard_230320\Gowin_ISP_RefDesign_0423_keil_SRAM\Gowin_ISP_RefDesign\FPGA_Design\src\scaler\scaler.v
E:\W_File\ISP_V2\Onboard_230320\Gowin_ISP_RefDesign_0423_keil_SRAM\Gowin_ISP_RefDesign\FPGA_Design\src\syn_code\syn_gen.v
E:\W_File\ISP_V2\Onboard_230320\Gowin_ISP_RefDesign_0423_keil_SRAM\Gowin_ISP_RefDesign\FPGA_Design\src\testpattern.v
E:\W_File\ISP_V2\Onboard_230320\Gowin_ISP_RefDesign_0423_keil_SRAM\Gowin_ISP_RefDesign\FPGA_Design\src\video_clip_sl.v
E:\W_File\ISP_V2\Onboard_230320\Gowin_ISP_RefDesign_0423_keil_SRAM\Gowin_ISP_RefDesign\FPGA_Design\src\video_top.v
GowinSynthesis Constraints File ---
Version V1.9.9 Beta3-1
Part Number GW2A-LV55PG484C8/I7
Device GW2A-55
Device Version C
Created Time Tue Apr 25 14:33:53 2023
Legal Announcement Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module video_top
Synthesis Process Running parser:
    CPU time = 0h 0m 4s, Elapsed time = 0h 0m 5s, Peak memory usage = 710.160MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 710.160MB
    Optimizing Phase 1: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 710.160MB
    Optimizing Phase 2: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 710.160MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.953s, Elapsed time = 0h 0m 0.942s, Peak memory usage = 710.160MB
    Inferring Phase 1: CPU time = 0h 0m 0.375s, Elapsed time = 0h 0m 0.376s, Peak memory usage = 710.160MB
    Inferring Phase 2: CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.174s, Peak memory usage = 710.160MB
    Inferring Phase 3: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.057s, Peak memory usage = 710.160MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 710.160MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.359s, Elapsed time = 0h 0m 0.353s, Peak memory usage = 710.160MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.609s, Elapsed time = 0h 0m 0.613s, Peak memory usage = 710.160MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 12s, Elapsed time = 0h 0m 12s, Peak memory usage = 710.160MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 710.160MB
Generate output files:
    CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 710.160MB
Total Time and Memory Usage CPU time = 0h 0m 24s, Elapsed time = 0h 0m 25s, Peak memory usage = 710.160MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 101
I/O Buf 196
    IBUF 60
    OBUF 106
    TBUF 2
    IOBUF 22
    TLVDS_IBUF 3
    ELVDS_OBUF 1
    ELVDS_IOBUF 2
Register 8753
    DFF 253
    DFFE 268
    DFFS 16
    DFFSE 24
    DFFR 41
    DFFRE 674
    DFFP 204
    DFFPE 428
    DFFC 3378
    DFFCE 3454
    DFFNP 12
    DLCE 1
LUT 11450
    LUT2 1632
    LUT3 3276
    LUT4 6542
ALU 1938
    ALU 1938
SSRAM 180
    RAM16S4 87
    RAM16SDP1 2
    RAM16SDP4 91
INV 60
    INV 60
IOLOGIC 104
    IDES8 2
    IDES8_MEM 16
    OSER8 24
    OSER8_MEM 20
    IODELAY 42
DSP 13
    MULT36X36 1
    MULTALU36X18 3
    MULTADDALU18X18 6
    ALU54D 3
BSRAM 57
    SDP 5
    SDPX9 4
    SDPB 27
    SDPX9B 8
    DPB 12
    pROM 1
CLOCK 9
    PLL 1
    CLKDIV 2
    DQS 2
    DHCEN 2
    rPLL 2

Resource Utilization Summary

Resource Usage Utilization
Logic 14528(11510 LUTs, 1938 ALUs, 180 SSRAMs) / 54720 27%
Register 8753 / 41997 21%
  --Register as Latch 1 / 41997 <1%
  --Register as FF 8752 / 41997 21%
BSRAM 57 / 140 41%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
I_CSI_CKP Base 3.125 320.0 0.000 1.563 CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/U0_IB/I
I_clk Base 10.000 100.0 0.000 5.000 Gowin_EMPU_M1_Top_inst/HCLK_ibuf/I
Gowin_EMPU_M1_Top_inst/JTAG_9_ibuf/I Base 10.000 100.0 0.000 5.000 Gowin_EMPU_M1_Top_inst/JTAG_9_ibuf/I
ddr_rst Base 10.000 100.0 0.000 5.000 DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q
CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT.default_gen_clk Generated 12.500 80.0 0.000 6.250 CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/U0_IB/I I_CSI_CKP CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
CSI2RAW8_inst/pll/pll_inst/CLKOUT.default_gen_clk Generated 6.250 160.0 0.000 3.125 CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT.default_gen_clk CSI2RAW8_inst/pll/pll_inst/CLKOUT
CSI2RAW8_inst/pll/pll_inst/CLKOUTP.default_gen_clk Generated 6.250 160.0 1.563 4.688 CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT.default_gen_clk CSI2RAW8_inst/pll/pll_inst/CLKOUTP
CSI2RAW8_inst/pll/pll_inst/CLKOUTD.default_gen_clk Generated 12.500 80.0 0.000 6.250 CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT.default_gen_clk CSI2RAW8_inst/pll/pll_inst/CLKOUTD
CSI2RAW8_inst/pll/pll_inst/CLKOUTD3.default_gen_clk Generated 18.750 53.3 0.000 9.375 CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT.default_gen_clk CSI2RAW8_inst/pll/pll_inst/CLKOUTD3

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 I_CSI_CKP 320.0(MHz) 389.7(MHz) 2 TOP
2 I_clk 100.0(MHz) 99.3(MHz) 16 TOP
3 Gowin_EMPU_M1_Top_inst/JTAG_9_ibuf/I 100.0(MHz) 178.6(MHz) 8 TOP
4 ddr_rst 100.0(MHz) 683.1(MHz) 2 TOP
5 CSI2RAW8_inst/DPHY_RX_TOP_inst/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT.default_gen_clk 80.0(MHz) 193.1(MHz) 7 TOP
6 CSI2RAW8_inst/pll/pll_inst/CLKOUT.default_gen_clk 160.0(MHz) 109.7(MHz) 13 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack -2.865
Data Arrival Time 9.780
Data Required Time 6.916
From isp_inst/cfa_top_inst/interpolation/e_line_5_s0
To isp_inst/cfa_top_inst/interpolation/line_fifo[4].line_fifo/fifo_sc_inst/Full_s0
Launch Clk CSI2RAW8_inst/pll/pll_inst/CLKOUT.default_gen_clk[R]
Latch Clk CSI2RAW8_inst/pll/pll_inst/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 CSI2RAW8_inst/pll/pll_inst/CLKOUT.default_gen_clk
0.521 0.521 tCL RR 3916 CSI2RAW8_inst/pll/pll_inst/CLKOUT
0.701 0.180 tNET RR 1 isp_inst/cfa_top_inst/interpolation/e_line_5_s0/CLK
0.933 0.232 tC2Q RF 6 isp_inst/cfa_top_inst/interpolation/e_line_5_s0/Q
1.170 0.237 tNET FF 1 isp_inst/cfa_top_inst/interpolation/valid_plus_s14/I1
1.725 0.555 tINS FF 3 isp_inst/cfa_top_inst/interpolation/valid_plus_s14/F
1.962 0.237 tNET FF 1 isp_inst/cfa_top_inst/interpolation/valid_plus_s7/I1
2.517 0.555 tINS FF 1 isp_inst/cfa_top_inst/interpolation/valid_plus_s7/F
2.754 0.237 tNET FF 1 isp_inst/cfa_top_inst/interpolation/valid_plus_s3/I0
3.271 0.517 tINS FF 1 isp_inst/cfa_top_inst/interpolation/valid_plus_s3/F
3.508 0.237 tNET FF 1 isp_inst/cfa_top_inst/interpolation/valid_plus_s1/I1
4.063 0.555 tINS FF 14 isp_inst/cfa_top_inst/interpolation/valid_plus_s1/F
4.300 0.237 tNET FF 1 isp_inst/cfa_top_inst/interpolation/fifo_RdEn_4_s1/I1
4.855 0.555 tINS FF 1 isp_inst/cfa_top_inst/interpolation/fifo_RdEn_4_s1/F
5.092 0.237 tNET FF 1 isp_inst/cfa_top_inst/interpolation/line_fifo[4].line_fifo/fifo_sc_inst/n11_s0/I1
5.647 0.555 tINS FF 2 isp_inst/cfa_top_inst/interpolation/line_fifo[4].line_fifo/fifo_sc_inst/n11_s0/F
5.884 0.237 tNET FF 2 isp_inst/cfa_top_inst/interpolation/line_fifo[4].line_fifo/fifo_sc_inst/rbin_next_0_s/I1
6.454 0.570 tINS FR 1 isp_inst/cfa_top_inst/interpolation/line_fifo[4].line_fifo/fifo_sc_inst/rbin_next_0_s/COUT
6.454 0.000 tNET RR 2 isp_inst/cfa_top_inst/interpolation/line_fifo[4].line_fifo/fifo_sc_inst/rbin_next_1_s/CIN
6.489 0.035 tINS RF 1 isp_inst/cfa_top_inst/interpolation/line_fifo[4].line_fifo/fifo_sc_inst/rbin_next_1_s/COUT
6.489 0.000 tNET FF 2 isp_inst/cfa_top_inst/interpolation/line_fifo[4].line_fifo/fifo_sc_inst/rbin_next_2_s/CIN
6.524 0.035 tINS FF 1 isp_inst/cfa_top_inst/interpolation/line_fifo[4].line_fifo/fifo_sc_inst/rbin_next_2_s/COUT
6.524 0.000 tNET FF 2 isp_inst/cfa_top_inst/interpolation/line_fifo[4].line_fifo/fifo_sc_inst/rbin_next_3_s/CIN
6.559 0.035 tINS FF 1 isp_inst/cfa_top_inst/interpolation/line_fifo[4].line_fifo/fifo_sc_inst/rbin_next_3_s/COUT
6.559 0.000 tNET FF 2 isp_inst/cfa_top_inst/interpolation/line_fifo[4].line_fifo/fifo_sc_inst/rbin_next_4_s/CIN
6.595 0.035 tINS FF 1 isp_inst/cfa_top_inst/interpolation/line_fifo[4].line_fifo/fifo_sc_inst/rbin_next_4_s/COUT
6.595 0.000 tNET FF 2 isp_inst/cfa_top_inst/interpolation/line_fifo[4].line_fifo/fifo_sc_inst/rbin_next_5_s/CIN
6.630 0.035 tINS FF 1 isp_inst/cfa_top_inst/interpolation/line_fifo[4].line_fifo/fifo_sc_inst/rbin_next_5_s/COUT
6.630 0.000 tNET FF 2 isp_inst/cfa_top_inst/interpolation/line_fifo[4].line_fifo/fifo_sc_inst/rbin_next_6_s/CIN
6.665 0.035 tINS FF 1 isp_inst/cfa_top_inst/interpolation/line_fifo[4].line_fifo/fifo_sc_inst/rbin_next_6_s/COUT
6.665 0.000 tNET FF 2 isp_inst/cfa_top_inst/interpolation/line_fifo[4].line_fifo/fifo_sc_inst/rbin_next_7_s/CIN
6.700 0.035 tINS FF 1 isp_inst/cfa_top_inst/interpolation/line_fifo[4].line_fifo/fifo_sc_inst/rbin_next_7_s/COUT
6.700 0.000 tNET FF 2 isp_inst/cfa_top_inst/interpolation/line_fifo[4].line_fifo/fifo_sc_inst/rbin_next_8_s/CIN
6.735 0.035 tINS FF 1 isp_inst/cfa_top_inst/interpolation/line_fifo[4].line_fifo/fifo_sc_inst/rbin_next_8_s/COUT
6.735 0.000 tNET FF 2 isp_inst/cfa_top_inst/interpolation/line_fifo[4].line_fifo/fifo_sc_inst/rbin_next_9_s/CIN
7.205 0.470 tINS FF 3 isp_inst/cfa_top_inst/interpolation/line_fifo[4].line_fifo/fifo_sc_inst/rbin_next_9_s/SUM
7.442 0.237 tNET FF 1 isp_inst/cfa_top_inst/interpolation/line_fifo[4].line_fifo/fifo_sc_inst/wfull_val_s5/I1
7.997 0.555 tINS FF 1 isp_inst/cfa_top_inst/interpolation/line_fifo[4].line_fifo/fifo_sc_inst/wfull_val_s5/F
8.234 0.237 tNET FF 1 isp_inst/cfa_top_inst/interpolation/line_fifo[4].line_fifo/fifo_sc_inst/wfull_val_s1/I1
8.789 0.555 tINS FF 1 isp_inst/cfa_top_inst/interpolation/line_fifo[4].line_fifo/fifo_sc_inst/wfull_val_s1/F
9.026 0.237 tNET FF 1 isp_inst/cfa_top_inst/interpolation/line_fifo[4].line_fifo/fifo_sc_inst/wfull_val_s0/I0
9.543 0.517 tINS FF 1 isp_inst/cfa_top_inst/interpolation/line_fifo[4].line_fifo/fifo_sc_inst/wfull_val_s0/F
9.780 0.237 tNET FF 1 isp_inst/cfa_top_inst/interpolation/line_fifo[4].line_fifo/fifo_sc_inst/Full_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
6.250 0.000 CSI2RAW8_inst/pll/pll_inst/CLKOUT.default_gen_clk
6.771 0.521 tCL RR 3916 CSI2RAW8_inst/pll/pll_inst/CLKOUT
6.951 0.180 tNET RR 1 isp_inst/cfa_top_inst/interpolation/line_fifo[4].line_fifo/fifo_sc_inst/Full_s0/CLK
6.916 -0.035 tSu 1 isp_inst/cfa_top_inst/interpolation/line_fifo[4].line_fifo/fifo_sc_inst/Full_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 6.250
Logic Level: 13
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay: cell: 6.241, 68.732%; route: 2.607, 28.713%; tC2Q: 0.232, 2.555%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.180, 100.000%

Path 2

Path Summary:
Slack -2.865
Data Arrival Time 9.780
Data Required Time 6.916
From isp_inst/cfa_top_inst/interpolation/e_line_5_s0
To isp_inst/cfa_top_inst/interpolation/line_fifo[3].line_fifo/fifo_sc_inst/Full_s0
Launch Clk CSI2RAW8_inst/pll/pll_inst/CLKOUT.default_gen_clk[R]
Latch Clk CSI2RAW8_inst/pll/pll_inst/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 CSI2RAW8_inst/pll/pll_inst/CLKOUT.default_gen_clk
0.521 0.521 tCL RR 3916 CSI2RAW8_inst/pll/pll_inst/CLKOUT
0.701 0.180 tNET RR 1 isp_inst/cfa_top_inst/interpolation/e_line_5_s0/CLK
0.933 0.232 tC2Q RF 6 isp_inst/cfa_top_inst/interpolation/e_line_5_s0/Q
1.170 0.237 tNET FF 1 isp_inst/cfa_top_inst/interpolation/valid_plus_s14/I1
1.725 0.555 tINS FF 3 isp_inst/cfa_top_inst/interpolation/valid_plus_s14/F
1.962 0.237 tNET FF 1 isp_inst/cfa_top_inst/interpolation/valid_plus_s7/I1
2.517 0.555 tINS FF 1 isp_inst/cfa_top_inst/interpolation/valid_plus_s7/F
2.754 0.237 tNET FF 1 isp_inst/cfa_top_inst/interpolation/valid_plus_s3/I0
3.271 0.517 tINS FF 1 isp_inst/cfa_top_inst/interpolation/valid_plus_s3/F
3.508 0.237 tNET FF 1 isp_inst/cfa_top_inst/interpolation/valid_plus_s1/I1
4.063 0.555 tINS FF 14 isp_inst/cfa_top_inst/interpolation/valid_plus_s1/F
4.300 0.237 tNET FF 1 isp_inst/cfa_top_inst/interpolation/fifo_RdEn_3_s1/I1
4.855 0.555 tINS FF 1 isp_inst/cfa_top_inst/interpolation/fifo_RdEn_3_s1/F
5.092 0.237 tNET FF 1 isp_inst/cfa_top_inst/interpolation/line_fifo[3].line_fifo/fifo_sc_inst/n11_s0/I1
5.647 0.555 tINS FF 2 isp_inst/cfa_top_inst/interpolation/line_fifo[3].line_fifo/fifo_sc_inst/n11_s0/F
5.884 0.237 tNET FF 2 isp_inst/cfa_top_inst/interpolation/line_fifo[3].line_fifo/fifo_sc_inst/rbin_next_0_s/I1
6.454 0.570 tINS FR 1 isp_inst/cfa_top_inst/interpolation/line_fifo[3].line_fifo/fifo_sc_inst/rbin_next_0_s/COUT
6.454 0.000 tNET RR 2 isp_inst/cfa_top_inst/interpolation/line_fifo[3].line_fifo/fifo_sc_inst/rbin_next_1_s/CIN
6.489 0.035 tINS RF 1 isp_inst/cfa_top_inst/interpolation/line_fifo[3].line_fifo/fifo_sc_inst/rbin_next_1_s/COUT
6.489 0.000 tNET FF 2 isp_inst/cfa_top_inst/interpolation/line_fifo[3].line_fifo/fifo_sc_inst/rbin_next_2_s/CIN
6.524 0.035 tINS FF 1 isp_inst/cfa_top_inst/interpolation/line_fifo[3].line_fifo/fifo_sc_inst/rbin_next_2_s/COUT
6.524 0.000 tNET FF 2 isp_inst/cfa_top_inst/interpolation/line_fifo[3].line_fifo/fifo_sc_inst/rbin_next_3_s/CIN
6.559 0.035 tINS FF 1 isp_inst/cfa_top_inst/interpolation/line_fifo[3].line_fifo/fifo_sc_inst/rbin_next_3_s/COUT
6.559 0.000 tNET FF 2 isp_inst/cfa_top_inst/interpolation/line_fifo[3].line_fifo/fifo_sc_inst/rbin_next_4_s/CIN
6.595 0.035 tINS FF 1 isp_inst/cfa_top_inst/interpolation/line_fifo[3].line_fifo/fifo_sc_inst/rbin_next_4_s/COUT
6.595 0.000 tNET FF 2 isp_inst/cfa_top_inst/interpolation/line_fifo[3].line_fifo/fifo_sc_inst/rbin_next_5_s/CIN
6.630 0.035 tINS FF 1 isp_inst/cfa_top_inst/interpolation/line_fifo[3].line_fifo/fifo_sc_inst/rbin_next_5_s/COUT
6.630 0.000 tNET FF 2 isp_inst/cfa_top_inst/interpolation/line_fifo[3].line_fifo/fifo_sc_inst/rbin_next_6_s/CIN
6.665 0.035 tINS FF 1 isp_inst/cfa_top_inst/interpolation/line_fifo[3].line_fifo/fifo_sc_inst/rbin_next_6_s/COUT
6.665 0.000 tNET FF 2 isp_inst/cfa_top_inst/interpolation/line_fifo[3].line_fifo/fifo_sc_inst/rbin_next_7_s/CIN
6.700 0.035 tINS FF 1 isp_inst/cfa_top_inst/interpolation/line_fifo[3].line_fifo/fifo_sc_inst/rbin_next_7_s/COUT
6.700 0.000 tNET FF 2 isp_inst/cfa_top_inst/interpolation/line_fifo[3].line_fifo/fifo_sc_inst/rbin_next_8_s/CIN
6.735 0.035 tINS FF 1 isp_inst/cfa_top_inst/interpolation/line_fifo[3].line_fifo/fifo_sc_inst/rbin_next_8_s/COUT
6.735 0.000 tNET FF 2 isp_inst/cfa_top_inst/interpolation/line_fifo[3].line_fifo/fifo_sc_inst/rbin_next_9_s/CIN
7.205 0.470 tINS FF 3 isp_inst/cfa_top_inst/interpolation/line_fifo[3].line_fifo/fifo_sc_inst/rbin_next_9_s/SUM
7.442 0.237 tNET FF 1 isp_inst/cfa_top_inst/interpolation/line_fifo[3].line_fifo/fifo_sc_inst/wfull_val_s5/I1
7.997 0.555 tINS FF 1 isp_inst/cfa_top_inst/interpolation/line_fifo[3].line_fifo/fifo_sc_inst/wfull_val_s5/F
8.234 0.237 tNET FF 1 isp_inst/cfa_top_inst/interpolation/line_fifo[3].line_fifo/fifo_sc_inst/wfull_val_s1/I1
8.789 0.555 tINS FF 1 isp_inst/cfa_top_inst/interpolation/line_fifo[3].line_fifo/fifo_sc_inst/wfull_val_s1/F
9.026 0.237 tNET FF 1 isp_inst/cfa_top_inst/interpolation/line_fifo[3].line_fifo/fifo_sc_inst/wfull_val_s0/I0
9.543 0.517 tINS FF 1 isp_inst/cfa_top_inst/interpolation/line_fifo[3].line_fifo/fifo_sc_inst/wfull_val_s0/F
9.780 0.237 tNET FF 1 isp_inst/cfa_top_inst/interpolation/line_fifo[3].line_fifo/fifo_sc_inst/Full_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
6.250 0.000 CSI2RAW8_inst/pll/pll_inst/CLKOUT.default_gen_clk
6.771 0.521 tCL RR 3916 CSI2RAW8_inst/pll/pll_inst/CLKOUT
6.951 0.180 tNET RR 1 isp_inst/cfa_top_inst/interpolation/line_fifo[3].line_fifo/fifo_sc_inst/Full_s0/CLK
6.916 -0.035 tSu 1 isp_inst/cfa_top_inst/interpolation/line_fifo[3].line_fifo/fifo_sc_inst/Full_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 6.250
Logic Level: 13
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay: cell: 6.241, 68.732%; route: 2.607, 28.713%; tC2Q: 0.232, 2.555%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.180, 100.000%

Path 3

Path Summary:
Slack -2.865
Data Arrival Time 9.780
Data Required Time 6.916
From isp_inst/cfa_top_inst/interpolation/e_line_5_s0
To isp_inst/cfa_top_inst/interpolation/line_fifo[2].line_fifo/fifo_sc_inst/Full_s0
Launch Clk CSI2RAW8_inst/pll/pll_inst/CLKOUT.default_gen_clk[R]
Latch Clk CSI2RAW8_inst/pll/pll_inst/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 CSI2RAW8_inst/pll/pll_inst/CLKOUT.default_gen_clk
0.521 0.521 tCL RR 3916 CSI2RAW8_inst/pll/pll_inst/CLKOUT
0.701 0.180 tNET RR 1 isp_inst/cfa_top_inst/interpolation/e_line_5_s0/CLK
0.933 0.232 tC2Q RF 6 isp_inst/cfa_top_inst/interpolation/e_line_5_s0/Q
1.170 0.237 tNET FF 1 isp_inst/cfa_top_inst/interpolation/valid_plus_s14/I1
1.725 0.555 tINS FF 3 isp_inst/cfa_top_inst/interpolation/valid_plus_s14/F
1.962 0.237 tNET FF 1 isp_inst/cfa_top_inst/interpolation/valid_plus_s7/I1
2.517 0.555 tINS FF 1 isp_inst/cfa_top_inst/interpolation/valid_plus_s7/F
2.754 0.237 tNET FF 1 isp_inst/cfa_top_inst/interpolation/valid_plus_s3/I0
3.271 0.517 tINS FF 1 isp_inst/cfa_top_inst/interpolation/valid_plus_s3/F
3.508 0.237 tNET FF 1 isp_inst/cfa_top_inst/interpolation/valid_plus_s1/I1
4.063 0.555 tINS FF 14 isp_inst/cfa_top_inst/interpolation/valid_plus_s1/F
4.300 0.237 tNET FF 1 isp_inst/cfa_top_inst/interpolation/fifo_RdEn_2_s1/I1
4.855 0.555 tINS FF 2 isp_inst/cfa_top_inst/interpolation/fifo_RdEn_2_s1/F
5.092 0.237 tNET FF 1 isp_inst/cfa_top_inst/interpolation/line_fifo[2].line_fifo/fifo_sc_inst/n11_s0/I1
5.647 0.555 tINS FF 2 isp_inst/cfa_top_inst/interpolation/line_fifo[2].line_fifo/fifo_sc_inst/n11_s0/F
5.884 0.237 tNET FF 2 isp_inst/cfa_top_inst/interpolation/line_fifo[2].line_fifo/fifo_sc_inst/rbin_next_0_s/I1
6.454 0.570 tINS FR 1 isp_inst/cfa_top_inst/interpolation/line_fifo[2].line_fifo/fifo_sc_inst/rbin_next_0_s/COUT
6.454 0.000 tNET RR 2 isp_inst/cfa_top_inst/interpolation/line_fifo[2].line_fifo/fifo_sc_inst/rbin_next_1_s/CIN
6.489 0.035 tINS RF 1 isp_inst/cfa_top_inst/interpolation/line_fifo[2].line_fifo/fifo_sc_inst/rbin_next_1_s/COUT
6.489 0.000 tNET FF 2 isp_inst/cfa_top_inst/interpolation/line_fifo[2].line_fifo/fifo_sc_inst/rbin_next_2_s/CIN
6.524 0.035 tINS FF 1 isp_inst/cfa_top_inst/interpolation/line_fifo[2].line_fifo/fifo_sc_inst/rbin_next_2_s/COUT
6.524 0.000 tNET FF 2 isp_inst/cfa_top_inst/interpolation/line_fifo[2].line_fifo/fifo_sc_inst/rbin_next_3_s/CIN
6.559 0.035 tINS FF 1 isp_inst/cfa_top_inst/interpolation/line_fifo[2].line_fifo/fifo_sc_inst/rbin_next_3_s/COUT
6.559 0.000 tNET FF 2 isp_inst/cfa_top_inst/interpolation/line_fifo[2].line_fifo/fifo_sc_inst/rbin_next_4_s/CIN
6.595 0.035 tINS FF 1 isp_inst/cfa_top_inst/interpolation/line_fifo[2].line_fifo/fifo_sc_inst/rbin_next_4_s/COUT
6.595 0.000 tNET FF 2 isp_inst/cfa_top_inst/interpolation/line_fifo[2].line_fifo/fifo_sc_inst/rbin_next_5_s/CIN
6.630 0.035 tINS FF 1 isp_inst/cfa_top_inst/interpolation/line_fifo[2].line_fifo/fifo_sc_inst/rbin_next_5_s/COUT
6.630 0.000 tNET FF 2 isp_inst/cfa_top_inst/interpolation/line_fifo[2].line_fifo/fifo_sc_inst/rbin_next_6_s/CIN
6.665 0.035 tINS FF 1 isp_inst/cfa_top_inst/interpolation/line_fifo[2].line_fifo/fifo_sc_inst/rbin_next_6_s/COUT
6.665 0.000 tNET FF 2 isp_inst/cfa_top_inst/interpolation/line_fifo[2].line_fifo/fifo_sc_inst/rbin_next_7_s/CIN
6.700 0.035 tINS FF 1 isp_inst/cfa_top_inst/interpolation/line_fifo[2].line_fifo/fifo_sc_inst/rbin_next_7_s/COUT
6.700 0.000 tNET FF 2 isp_inst/cfa_top_inst/interpolation/line_fifo[2].line_fifo/fifo_sc_inst/rbin_next_8_s/CIN
6.735 0.035 tINS FF 1 isp_inst/cfa_top_inst/interpolation/line_fifo[2].line_fifo/fifo_sc_inst/rbin_next_8_s/COUT
6.735 0.000 tNET FF 2 isp_inst/cfa_top_inst/interpolation/line_fifo[2].line_fifo/fifo_sc_inst/rbin_next_9_s/CIN
7.205 0.470 tINS FF 3 isp_inst/cfa_top_inst/interpolation/line_fifo[2].line_fifo/fifo_sc_inst/rbin_next_9_s/SUM
7.442 0.237 tNET FF 1 isp_inst/cfa_top_inst/interpolation/line_fifo[2].line_fifo/fifo_sc_inst/wfull_val_s5/I1
7.997 0.555 tINS FF 1 isp_inst/cfa_top_inst/interpolation/line_fifo[2].line_fifo/fifo_sc_inst/wfull_val_s5/F
8.234 0.237 tNET FF 1 isp_inst/cfa_top_inst/interpolation/line_fifo[2].line_fifo/fifo_sc_inst/wfull_val_s1/I1
8.789 0.555 tINS FF 1 isp_inst/cfa_top_inst/interpolation/line_fifo[2].line_fifo/fifo_sc_inst/wfull_val_s1/F
9.026 0.237 tNET FF 1 isp_inst/cfa_top_inst/interpolation/line_fifo[2].line_fifo/fifo_sc_inst/wfull_val_s0/I0
9.543 0.517 tINS FF 1 isp_inst/cfa_top_inst/interpolation/line_fifo[2].line_fifo/fifo_sc_inst/wfull_val_s0/F
9.780 0.237 tNET FF 1 isp_inst/cfa_top_inst/interpolation/line_fifo[2].line_fifo/fifo_sc_inst/Full_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
6.250 0.000 CSI2RAW8_inst/pll/pll_inst/CLKOUT.default_gen_clk
6.771 0.521 tCL RR 3916 CSI2RAW8_inst/pll/pll_inst/CLKOUT
6.951 0.180 tNET RR 1 isp_inst/cfa_top_inst/interpolation/line_fifo[2].line_fifo/fifo_sc_inst/Full_s0/CLK
6.916 -0.035 tSu 1 isp_inst/cfa_top_inst/interpolation/line_fifo[2].line_fifo/fifo_sc_inst/Full_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 6.250
Logic Level: 13
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay: cell: 6.241, 68.732%; route: 2.607, 28.713%; tC2Q: 0.232, 2.555%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.180, 100.000%

Path 4

Path Summary:
Slack -2.865
Data Arrival Time 9.780
Data Required Time 6.916
From isp_inst/cfa_top_inst/interpolation/e_line_5_s0
To isp_inst/cfa_top_inst/interpolation/line_fifo[1].line_fifo/fifo_sc_inst/Full_s0
Launch Clk CSI2RAW8_inst/pll/pll_inst/CLKOUT.default_gen_clk[R]
Latch Clk CSI2RAW8_inst/pll/pll_inst/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 CSI2RAW8_inst/pll/pll_inst/CLKOUT.default_gen_clk
0.521 0.521 tCL RR 3916 CSI2RAW8_inst/pll/pll_inst/CLKOUT
0.701 0.180 tNET RR 1 isp_inst/cfa_top_inst/interpolation/e_line_5_s0/CLK
0.933 0.232 tC2Q RF 6 isp_inst/cfa_top_inst/interpolation/e_line_5_s0/Q
1.170 0.237 tNET FF 1 isp_inst/cfa_top_inst/interpolation/valid_plus_s14/I1
1.725 0.555 tINS FF 3 isp_inst/cfa_top_inst/interpolation/valid_plus_s14/F
1.962 0.237 tNET FF 1 isp_inst/cfa_top_inst/interpolation/valid_plus_s7/I1
2.517 0.555 tINS FF 1 isp_inst/cfa_top_inst/interpolation/valid_plus_s7/F
2.754 0.237 tNET FF 1 isp_inst/cfa_top_inst/interpolation/valid_plus_s3/I0
3.271 0.517 tINS FF 1 isp_inst/cfa_top_inst/interpolation/valid_plus_s3/F
3.508 0.237 tNET FF 1 isp_inst/cfa_top_inst/interpolation/valid_plus_s1/I1
4.063 0.555 tINS FF 14 isp_inst/cfa_top_inst/interpolation/valid_plus_s1/F
4.300 0.237 tNET FF 1 isp_inst/cfa_top_inst/interpolation/fifo_RdEn_1_s1/I1
4.855 0.555 tINS FF 1 isp_inst/cfa_top_inst/interpolation/fifo_RdEn_1_s1/F
5.092 0.237 tNET FF 1 isp_inst/cfa_top_inst/interpolation/line_fifo[1].line_fifo/fifo_sc_inst/n11_s0/I1
5.647 0.555 tINS FF 2 isp_inst/cfa_top_inst/interpolation/line_fifo[1].line_fifo/fifo_sc_inst/n11_s0/F
5.884 0.237 tNET FF 2 isp_inst/cfa_top_inst/interpolation/line_fifo[1].line_fifo/fifo_sc_inst/rbin_next_0_s/I1
6.454 0.570 tINS FR 1 isp_inst/cfa_top_inst/interpolation/line_fifo[1].line_fifo/fifo_sc_inst/rbin_next_0_s/COUT
6.454 0.000 tNET RR 2 isp_inst/cfa_top_inst/interpolation/line_fifo[1].line_fifo/fifo_sc_inst/rbin_next_1_s/CIN
6.489 0.035 tINS RF 1 isp_inst/cfa_top_inst/interpolation/line_fifo[1].line_fifo/fifo_sc_inst/rbin_next_1_s/COUT
6.489 0.000 tNET FF 2 isp_inst/cfa_top_inst/interpolation/line_fifo[1].line_fifo/fifo_sc_inst/rbin_next_2_s/CIN
6.524 0.035 tINS FF 1 isp_inst/cfa_top_inst/interpolation/line_fifo[1].line_fifo/fifo_sc_inst/rbin_next_2_s/COUT
6.524 0.000 tNET FF 2 isp_inst/cfa_top_inst/interpolation/line_fifo[1].line_fifo/fifo_sc_inst/rbin_next_3_s/CIN
6.559 0.035 tINS FF 1 isp_inst/cfa_top_inst/interpolation/line_fifo[1].line_fifo/fifo_sc_inst/rbin_next_3_s/COUT
6.559 0.000 tNET FF 2 isp_inst/cfa_top_inst/interpolation/line_fifo[1].line_fifo/fifo_sc_inst/rbin_next_4_s/CIN
6.595 0.035 tINS FF 1 isp_inst/cfa_top_inst/interpolation/line_fifo[1].line_fifo/fifo_sc_inst/rbin_next_4_s/COUT
6.595 0.000 tNET FF 2 isp_inst/cfa_top_inst/interpolation/line_fifo[1].line_fifo/fifo_sc_inst/rbin_next_5_s/CIN
6.630 0.035 tINS FF 1 isp_inst/cfa_top_inst/interpolation/line_fifo[1].line_fifo/fifo_sc_inst/rbin_next_5_s/COUT
6.630 0.000 tNET FF 2 isp_inst/cfa_top_inst/interpolation/line_fifo[1].line_fifo/fifo_sc_inst/rbin_next_6_s/CIN
6.665 0.035 tINS FF 1 isp_inst/cfa_top_inst/interpolation/line_fifo[1].line_fifo/fifo_sc_inst/rbin_next_6_s/COUT
6.665 0.000 tNET FF 2 isp_inst/cfa_top_inst/interpolation/line_fifo[1].line_fifo/fifo_sc_inst/rbin_next_7_s/CIN
6.700 0.035 tINS FF 1 isp_inst/cfa_top_inst/interpolation/line_fifo[1].line_fifo/fifo_sc_inst/rbin_next_7_s/COUT
6.700 0.000 tNET FF 2 isp_inst/cfa_top_inst/interpolation/line_fifo[1].line_fifo/fifo_sc_inst/rbin_next_8_s/CIN
6.735 0.035 tINS FF 1 isp_inst/cfa_top_inst/interpolation/line_fifo[1].line_fifo/fifo_sc_inst/rbin_next_8_s/COUT
6.735 0.000 tNET FF 2 isp_inst/cfa_top_inst/interpolation/line_fifo[1].line_fifo/fifo_sc_inst/rbin_next_9_s/CIN
7.205 0.470 tINS FF 3 isp_inst/cfa_top_inst/interpolation/line_fifo[1].line_fifo/fifo_sc_inst/rbin_next_9_s/SUM
7.442 0.237 tNET FF 1 isp_inst/cfa_top_inst/interpolation/line_fifo[1].line_fifo/fifo_sc_inst/wfull_val_s5/I1
7.997 0.555 tINS FF 1 isp_inst/cfa_top_inst/interpolation/line_fifo[1].line_fifo/fifo_sc_inst/wfull_val_s5/F
8.234 0.237 tNET FF 1 isp_inst/cfa_top_inst/interpolation/line_fifo[1].line_fifo/fifo_sc_inst/wfull_val_s1/I1
8.789 0.555 tINS FF 1 isp_inst/cfa_top_inst/interpolation/line_fifo[1].line_fifo/fifo_sc_inst/wfull_val_s1/F
9.026 0.237 tNET FF 1 isp_inst/cfa_top_inst/interpolation/line_fifo[1].line_fifo/fifo_sc_inst/wfull_val_s0/I0
9.543 0.517 tINS FF 1 isp_inst/cfa_top_inst/interpolation/line_fifo[1].line_fifo/fifo_sc_inst/wfull_val_s0/F
9.780 0.237 tNET FF 1 isp_inst/cfa_top_inst/interpolation/line_fifo[1].line_fifo/fifo_sc_inst/Full_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
6.250 0.000 CSI2RAW8_inst/pll/pll_inst/CLKOUT.default_gen_clk
6.771 0.521 tCL RR 3916 CSI2RAW8_inst/pll/pll_inst/CLKOUT
6.951 0.180 tNET RR 1 isp_inst/cfa_top_inst/interpolation/line_fifo[1].line_fifo/fifo_sc_inst/Full_s0/CLK
6.916 -0.035 tSu 1 isp_inst/cfa_top_inst/interpolation/line_fifo[1].line_fifo/fifo_sc_inst/Full_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 6.250
Logic Level: 13
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay: cell: 6.241, 68.732%; route: 2.607, 28.713%; tC2Q: 0.232, 2.555%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.180, 100.000%

Path 5

Path Summary:
Slack -2.865
Data Arrival Time 9.780
Data Required Time 6.916
From isp_inst/cfa_top_inst/interpolation/e_line_5_s0
To isp_inst/cfa_top_inst/interpolation/line_fifo[0].line_fifo/fifo_sc_inst/Full_s0
Launch Clk CSI2RAW8_inst/pll/pll_inst/CLKOUT.default_gen_clk[R]
Latch Clk CSI2RAW8_inst/pll/pll_inst/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 CSI2RAW8_inst/pll/pll_inst/CLKOUT.default_gen_clk
0.521 0.521 tCL RR 3916 CSI2RAW8_inst/pll/pll_inst/CLKOUT
0.701 0.180 tNET RR 1 isp_inst/cfa_top_inst/interpolation/e_line_5_s0/CLK
0.933 0.232 tC2Q RF 6 isp_inst/cfa_top_inst/interpolation/e_line_5_s0/Q
1.170 0.237 tNET FF 1 isp_inst/cfa_top_inst/interpolation/valid_plus_s14/I1
1.725 0.555 tINS FF 3 isp_inst/cfa_top_inst/interpolation/valid_plus_s14/F
1.962 0.237 tNET FF 1 isp_inst/cfa_top_inst/interpolation/valid_plus_s7/I1
2.517 0.555 tINS FF 1 isp_inst/cfa_top_inst/interpolation/valid_plus_s7/F
2.754 0.237 tNET FF 1 isp_inst/cfa_top_inst/interpolation/valid_plus_s3/I0
3.271 0.517 tINS FF 1 isp_inst/cfa_top_inst/interpolation/valid_plus_s3/F
3.508 0.237 tNET FF 1 isp_inst/cfa_top_inst/interpolation/valid_plus_s1/I1
4.063 0.555 tINS FF 14 isp_inst/cfa_top_inst/interpolation/valid_plus_s1/F
4.300 0.237 tNET FF 1 isp_inst/cfa_top_inst/interpolation/fifo_RdEn_0_s2/I1
4.855 0.555 tINS FF 1 isp_inst/cfa_top_inst/interpolation/fifo_RdEn_0_s2/F
5.092 0.237 tNET FF 1 isp_inst/cfa_top_inst/interpolation/line_fifo[0].line_fifo/fifo_sc_inst/n11_s0/I1
5.647 0.555 tINS FF 2 isp_inst/cfa_top_inst/interpolation/line_fifo[0].line_fifo/fifo_sc_inst/n11_s0/F
5.884 0.237 tNET FF 2 isp_inst/cfa_top_inst/interpolation/line_fifo[0].line_fifo/fifo_sc_inst/rbin_next_0_s/I1
6.454 0.570 tINS FR 1 isp_inst/cfa_top_inst/interpolation/line_fifo[0].line_fifo/fifo_sc_inst/rbin_next_0_s/COUT
6.454 0.000 tNET RR 2 isp_inst/cfa_top_inst/interpolation/line_fifo[0].line_fifo/fifo_sc_inst/rbin_next_1_s/CIN
6.489 0.035 tINS RF 1 isp_inst/cfa_top_inst/interpolation/line_fifo[0].line_fifo/fifo_sc_inst/rbin_next_1_s/COUT
6.489 0.000 tNET FF 2 isp_inst/cfa_top_inst/interpolation/line_fifo[0].line_fifo/fifo_sc_inst/rbin_next_2_s/CIN
6.524 0.035 tINS FF 1 isp_inst/cfa_top_inst/interpolation/line_fifo[0].line_fifo/fifo_sc_inst/rbin_next_2_s/COUT
6.524 0.000 tNET FF 2 isp_inst/cfa_top_inst/interpolation/line_fifo[0].line_fifo/fifo_sc_inst/rbin_next_3_s/CIN
6.559 0.035 tINS FF 1 isp_inst/cfa_top_inst/interpolation/line_fifo[0].line_fifo/fifo_sc_inst/rbin_next_3_s/COUT
6.559 0.000 tNET FF 2 isp_inst/cfa_top_inst/interpolation/line_fifo[0].line_fifo/fifo_sc_inst/rbin_next_4_s/CIN
6.595 0.035 tINS FF 1 isp_inst/cfa_top_inst/interpolation/line_fifo[0].line_fifo/fifo_sc_inst/rbin_next_4_s/COUT
6.595 0.000 tNET FF 2 isp_inst/cfa_top_inst/interpolation/line_fifo[0].line_fifo/fifo_sc_inst/rbin_next_5_s/CIN
6.630 0.035 tINS FF 1 isp_inst/cfa_top_inst/interpolation/line_fifo[0].line_fifo/fifo_sc_inst/rbin_next_5_s/COUT
6.630 0.000 tNET FF 2 isp_inst/cfa_top_inst/interpolation/line_fifo[0].line_fifo/fifo_sc_inst/rbin_next_6_s/CIN
6.665 0.035 tINS FF 1 isp_inst/cfa_top_inst/interpolation/line_fifo[0].line_fifo/fifo_sc_inst/rbin_next_6_s/COUT
6.665 0.000 tNET FF 2 isp_inst/cfa_top_inst/interpolation/line_fifo[0].line_fifo/fifo_sc_inst/rbin_next_7_s/CIN
6.700 0.035 tINS FF 1 isp_inst/cfa_top_inst/interpolation/line_fifo[0].line_fifo/fifo_sc_inst/rbin_next_7_s/COUT
6.700 0.000 tNET FF 2 isp_inst/cfa_top_inst/interpolation/line_fifo[0].line_fifo/fifo_sc_inst/rbin_next_8_s/CIN
6.735 0.035 tINS FF 1 isp_inst/cfa_top_inst/interpolation/line_fifo[0].line_fifo/fifo_sc_inst/rbin_next_8_s/COUT
6.735 0.000 tNET FF 2 isp_inst/cfa_top_inst/interpolation/line_fifo[0].line_fifo/fifo_sc_inst/rbin_next_9_s/CIN
7.205 0.470 tINS FF 3 isp_inst/cfa_top_inst/interpolation/line_fifo[0].line_fifo/fifo_sc_inst/rbin_next_9_s/SUM
7.442 0.237 tNET FF 1 isp_inst/cfa_top_inst/interpolation/line_fifo[0].line_fifo/fifo_sc_inst/wfull_val_s5/I1
7.997 0.555 tINS FF 1 isp_inst/cfa_top_inst/interpolation/line_fifo[0].line_fifo/fifo_sc_inst/wfull_val_s5/F
8.234 0.237 tNET FF 1 isp_inst/cfa_top_inst/interpolation/line_fifo[0].line_fifo/fifo_sc_inst/wfull_val_s1/I1
8.789 0.555 tINS FF 1 isp_inst/cfa_top_inst/interpolation/line_fifo[0].line_fifo/fifo_sc_inst/wfull_val_s1/F
9.026 0.237 tNET FF 1 isp_inst/cfa_top_inst/interpolation/line_fifo[0].line_fifo/fifo_sc_inst/wfull_val_s0/I0
9.543 0.517 tINS FF 1 isp_inst/cfa_top_inst/interpolation/line_fifo[0].line_fifo/fifo_sc_inst/wfull_val_s0/F
9.780 0.237 tNET FF 1 isp_inst/cfa_top_inst/interpolation/line_fifo[0].line_fifo/fifo_sc_inst/Full_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
6.250 0.000 CSI2RAW8_inst/pll/pll_inst/CLKOUT.default_gen_clk
6.771 0.521 tCL RR 3916 CSI2RAW8_inst/pll/pll_inst/CLKOUT
6.951 0.180 tNET RR 1 isp_inst/cfa_top_inst/interpolation/line_fifo[0].line_fifo/fifo_sc_inst/Full_s0/CLK
6.916 -0.035 tSu 1 isp_inst/cfa_top_inst/interpolation/line_fifo[0].line_fifo/fifo_sc_inst/Full_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 6.250
Logic Level: 13
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay: cell: 6.241, 68.732%; route: 2.607, 28.713%; tC2Q: 0.232, 2.555%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.180, 100.000%