Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Gowin\Gowin_V1.9.7.06Beta_GowinSynthesis-only\IDE\ipcore\SCALER\data\scaler_wrapper.vp
C:\Gowin\Gowin_V1.9.7.06Beta_GowinSynthesis-only\IDE\ipcore\SCALER\data\static_macro_define.v
C:\Gowin\Gowin_V1.9.7.06Beta_GowinSynthesis-only\IDE\ipcore\SCALER\data\scaler_top.v
GowinSynthesis Constraints File ---
GowinSynthesis Version GowinSynthesis V1.9.7.06Beta
Part Number GW2A-LV55PG484C8/I7
Device GW2A-55C
Created Time Wed Jul 07 10:18:51 2021
Legal Announcement Copyright (C)2014-2021 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module Scaler_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 35.176MB
Running netlist conversion:
    CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.021s, Peak memory usage = 35.176MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.115s, Peak memory usage = 35.176MB
    Optimizing Phase 1: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.059s, Peak memory usage = 35.176MB
    Optimizing Phase 2: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.114s, Peak memory usage = 35.176MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.014s, Peak memory usage = 35.176MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 35.176MB
    Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.014s, Peak memory usage = 35.176MB
    Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 35.176MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.104s, Peak memory usage = 35.176MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.021s, Peak memory usage = 35.176MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.017s, Peak memory usage = 35.176MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.968s, Elapsed time = 0h 0m 0.997s, Peak memory usage = 48.879MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.164s, Peak memory usage = 48.879MB
Generate output files:
    CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.297s, Peak memory usage = 48.879MB
Total Time and Memory Usage CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 48.879MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 56
I/O Buf 56
    IBUF 30
    OBUF 26
Register 916
    DFF 32
    DFFR 3
    DFFP 4
    DFFC 461
    DFFCE 416
LUT 627
    LUT2 144
    LUT3 249
    LUT4 234
ALU 68
    ALU 68
SSRAM 4
    RAM16S4 2
    RAM16SDP1 2
INV 4
    INV 4
BSRAM 18
    SDPB 18

Resource Utilization Summary

Resource Usage Utilization
Logic 723(631 LUTs, 68 ALUs, 4 SSRAMs) / 54720 1%
Register 916 / 41997 2%
  --Register as Latch 0 / 41997 0%
  --Register as FF 916 / 41997 2%
BSRAM 18 / 140 13%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
I_vin_clk Base 10.000 100.0 0.000 5.000 I_vin_clk_ibuf/I
I_sysclk Base 10.000 100.0 0.000 5.000 I_sysclk_ibuf/I
I_vout_clk Base 10.000 100.0 0.000 5.000 I_vout_clk_ibuf/I

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 I_vin_clk 100.0(MHz) 347.2(MHz) 4 TOP
2 I_sysclk 100.0(MHz) 325.5(MHz) 6 TOP
3 I_vout_clk 100.0(MHz) 347.2(MHz) 4 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 6.928
Data Arrival Time 3.899
Data Required Time 10.828
From scaler_wrapper_inst/scaler_core_inst/vin_hsize_sysclk_10_s0
To scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_coord_trans_inst/ver_kyacc_27_s1
Launch Clk I_sysclk[R]
Latch Clk I_sysclk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_sysclk
0.000 0.000 tCL RR 1 I_sysclk_ibuf/I
0.683 0.683 tINS RR 737 I_sysclk_ibuf/O
0.863 0.180 tNET RR 1 scaler_wrapper_inst/scaler_core_inst/vin_hsize_sysclk_10_s0/CLK
1.095 0.232 tC2Q RF 10 scaler_wrapper_inst/scaler_core_inst/vin_hsize_sysclk_10_s0/Q
1.332 0.237 tNET FF 2 scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_coord_trans_inst/n20_s/I1
1.901 0.570 tINS FR 1 scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_coord_trans_inst/n20_s/COUT
1.901 0.000 tNET RR 2 scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_coord_trans_inst/n19_s/CIN
1.937 0.035 tINS RF 1 scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_coord_trans_inst/n19_s/COUT
1.937 0.000 tNET FF 2 scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_coord_trans_inst/n18_s/CIN
1.972 0.035 tINS FF 1 scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_coord_trans_inst/n18_s/COUT
1.972 0.000 tNET FF 2 scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_coord_trans_inst/n17_s/CIN
2.007 0.035 tINS FF 1 scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_coord_trans_inst/n17_s/COUT
2.007 0.000 tNET FF 2 scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_coord_trans_inst/n16_s/CIN
2.042 0.035 tINS FF 1 scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_coord_trans_inst/n16_s/COUT
2.042 0.000 tNET FF 2 scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_coord_trans_inst/n15_s/CIN
2.078 0.035 tINS FF 1 scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_coord_trans_inst/n15_s/COUT
2.078 0.000 tNET FF 2 scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_coord_trans_inst/n14_s/CIN
2.113 0.035 tINS FF 1 scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_coord_trans_inst/n14_s/COUT
2.113 0.000 tNET FF 2 scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_coord_trans_inst/n13_s/CIN
2.148 0.035 tINS FF 1 scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_coord_trans_inst/n13_s/COUT
2.148 0.000 tNET FF 2 scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_coord_trans_inst/n12_s/CIN
2.183 0.035 tINS FF 1 scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_coord_trans_inst/n12_s/COUT
2.183 0.000 tNET FF 2 scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_coord_trans_inst/n11_s/CIN
2.218 0.035 tINS FF 1 scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_coord_trans_inst/n11_s/COUT
2.455 0.237 tNET FF 1 scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_coord_trans_inst/n38_s4/I2
2.908 0.453 tINS FF 1 scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_coord_trans_inst/n38_s4/F
3.145 0.237 tNET FF 1 scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_coord_trans_inst/n38_s3/I0
3.662 0.517 tINS FF 1 scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_coord_trans_inst/n38_s3/F
3.899 0.237 tNET FF 1 scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_coord_trans_inst/ver_kyacc_27_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_sysclk
10.000 0.000 tCL RR 1 I_sysclk_ibuf/I
10.682 0.683 tINS RR 737 I_sysclk_ibuf/O
10.863 0.180 tNET RR 1 scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_coord_trans_inst/ver_kyacc_27_s1/CLK
10.828 -0.035 tSu 1 scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_coord_trans_inst/ver_kyacc_27_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 1.857, 61.143%; route: 0.948, 31.217%; tC2Q: 0.232, 7.640%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 2

Path Summary:
Slack 7.120
Data Arrival Time 3.708
Data Required Time 10.828
From scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/oram_rdaddr_0_s3
To scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/oram_rdaddr_6_s1
Launch Clk I_vout_clk[R]
Latch Clk I_vout_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_vout_clk
0.000 0.000 tCL RR 1 I_vout_clk_ibuf/I
0.683 0.683 tINS RR 144 I_vout_clk_ibuf/O
0.863 0.180 tNET RR 1 scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/oram_rdaddr_0_s3/CLK
1.095 0.232 tC2Q RF 11 scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/oram_rdaddr_0_s3/Q
1.332 0.237 tNET FF 1 scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/n267_s2/I1
1.887 0.555 tINS FF 5 scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/n267_s2/F
2.124 0.237 tNET FF 1 scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/n266_s2/I1
2.679 0.555 tINS FF 2 scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/n266_s2/F
2.916 0.237 tNET FF 1 scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/n265_s1/I1
3.471 0.555 tINS FF 1 scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/n265_s1/F
3.708 0.237 tNET FF 1 scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/oram_rdaddr_6_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_vout_clk
10.000 0.000 tCL RR 1 I_vout_clk_ibuf/I
10.682 0.683 tINS RR 144 I_vout_clk_ibuf/O
10.863 0.180 tNET RR 1 scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/oram_rdaddr_6_s1/CLK
10.828 -0.035 tSu 1 scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/oram_rdaddr_6_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 4
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 1.665, 58.523%; route: 0.948, 33.322%; tC2Q: 0.232, 8.155%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 3

Path Summary:
Slack 7.120
Data Arrival Time 3.708
Data Required Time 10.828
From scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/oram_rdaddr_5_s1
To scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/oram_rdaddr_9_s1
Launch Clk I_vout_clk[R]
Latch Clk I_vout_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_vout_clk
0.000 0.000 tCL RR 1 I_vout_clk_ibuf/I
0.683 0.683 tINS RR 144 I_vout_clk_ibuf/O
0.863 0.180 tNET RR 1 scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/oram_rdaddr_5_s1/CLK
1.095 0.232 tC2Q RF 10 scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/oram_rdaddr_5_s1/Q
1.332 0.237 tNET FF 1 scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/n263_s3/I1
1.887 0.555 tINS FF 2 scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/n263_s3/F
2.124 0.237 tNET FF 1 scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/n263_s2/I1
2.679 0.555 tINS FF 2 scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/n263_s2/F
2.916 0.237 tNET FF 1 scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/n262_s1/I1
3.471 0.555 tINS FF 1 scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/n262_s1/F
3.708 0.237 tNET FF 1 scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/oram_rdaddr_9_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_vout_clk
10.000 0.000 tCL RR 1 I_vout_clk_ibuf/I
10.682 0.683 tINS RR 144 I_vout_clk_ibuf/O
10.863 0.180 tNET RR 1 scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/oram_rdaddr_9_s1/CLK
10.828 -0.035 tSu 1 scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/oram_rdaddr_9_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 4
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 1.665, 58.523%; route: 0.948, 33.322%; tC2Q: 0.232, 8.155%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 4

Path Summary:
Slack 7.120
Data Arrival Time 3.708
Data Required Time 10.828
From scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/oram_wraddr_0_s3
To scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/oram_wraddr_6_s1
Launch Clk I_sysclk[R]
Latch Clk I_sysclk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_sysclk
0.000 0.000 tCL RR 1 I_sysclk_ibuf/I
0.683 0.683 tINS RR 737 I_sysclk_ibuf/O
0.863 0.180 tNET RR 1 scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/oram_wraddr_0_s3/CLK
1.095 0.232 tC2Q RF 11 scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/oram_wraddr_0_s3/Q
1.332 0.237 tNET FF 1 scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/n114_s2/I1
1.887 0.555 tINS FF 5 scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/n114_s2/F
2.124 0.237 tNET FF 1 scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/n113_s2/I1
2.679 0.555 tINS FF 2 scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/n113_s2/F
2.916 0.237 tNET FF 1 scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/n112_s1/I1
3.471 0.555 tINS FF 1 scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/n112_s1/F
3.708 0.237 tNET FF 1 scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/oram_wraddr_6_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_sysclk
10.000 0.000 tCL RR 1 I_sysclk_ibuf/I
10.682 0.683 tINS RR 737 I_sysclk_ibuf/O
10.863 0.180 tNET RR 1 scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/oram_wraddr_6_s1/CLK
10.828 -0.035 tSu 1 scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/oram_wraddr_6_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 4
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 1.665, 58.523%; route: 0.948, 33.322%; tC2Q: 0.232, 8.155%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 5

Path Summary:
Slack 7.120
Data Arrival Time 3.708
Data Required Time 10.828
From scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/oram_wraddr_5_s1
To scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/oram_wraddr_9_s1
Launch Clk I_sysclk[R]
Latch Clk I_sysclk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_sysclk
0.000 0.000 tCL RR 1 I_sysclk_ibuf/I
0.683 0.683 tINS RR 737 I_sysclk_ibuf/O
0.863 0.180 tNET RR 1 scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/oram_wraddr_5_s1/CLK
1.095 0.232 tC2Q RF 10 scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/oram_wraddr_5_s1/Q
1.332 0.237 tNET FF 1 scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/n110_s3/I1
1.887 0.555 tINS FF 2 scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/n110_s3/F
2.124 0.237 tNET FF 1 scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/n110_s2/I1
2.679 0.555 tINS FF 2 scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/n110_s2/F
2.916 0.237 tNET FF 1 scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/n109_s1/I1
3.471 0.555 tINS FF 1 scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/n109_s1/F
3.708 0.237 tNET FF 1 scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/oram_wraddr_9_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_sysclk
10.000 0.000 tCL RR 1 I_sysclk_ibuf/I
10.682 0.683 tINS RR 737 I_sysclk_ibuf/O
10.863 0.180 tNET RR 1 scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/oram_wraddr_9_s1/CLK
10.828 -0.035 tSu 1 scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/oram_wraddr_9_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 4
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 1.665, 58.523%; route: 0.948, 33.322%; tC2Q: 0.232, 8.155%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%