Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\ahb_def_slave.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\BusMatrix.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\can.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\can_define.vh C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\can_static_macro_define.vh C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\can_top.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_adder.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_ahb.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_alu_dec.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_core.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_ctl.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_ctl_add3.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_ahb_dec.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_ahb_mux.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_bp.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_ctl.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_define.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_dw.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_mtx.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_mtx_dbg.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_mtx_sys.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_rom_tb.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_sys.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_tcm.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_undefs.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_decoder.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_defs.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dp.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_excpt.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_fetch.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_fns.vh C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_matrix_check_fns.vh C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_mem_ctl.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_multiplier.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_multiply_shift.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_mux4.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_nvic.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_nvic_ahb.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_nvic_ahb_os.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_nvic_defs.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_nvic_main.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_nvic_pri_lvl.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_nvic_pri_num.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_nvic_tree.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_nvic_undefs.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_reg_bank.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_shifter.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_undefs.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_ethmac.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_ethmac_miim_wrapper.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_ethmac_rx_buffer_to_ahb.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_ethmac_rx_to_buffer.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_ethmac_rx_wrapper.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_ethmac_sdp_wrapper_32bit.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_ethmac_top.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_ethmac_tx_wrapper.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_ethmac_wrapper.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_gpio.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_ahbif_ctrl.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_arbiter.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_async_fifo_clr.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_config.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_const.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_ctrl.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_eilmif_ctrl.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_fifo.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_gck.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_pad_lib.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_reg.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_regif.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_regif_ctrl.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_spiif.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_sync.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_sync_l2l.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_sync_p2p.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_to_iop.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_dualtimers.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_dualtimers_defs.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_dualtimers_frc.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_spi.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_timer.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_autocorrelation.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_balancefilter.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_collector.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_crngt_to_trng.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_dx_inv_chain.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_dx_trng_top.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_dxm_ff.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_dxm_interrupt_low.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_dxm_mux.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_dxm_mux_clk.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_dxm_sync.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_ehr.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_entropy_gen.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_gtech_models.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_lfsr_new.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_line.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_noise_gen.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_pmf_table.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_prng_top_wrap.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_reg_file.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_rng_engine.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_rng_misc.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_rng_top.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_rng_top_wrap_unconnected.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_rosc.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_rst_logic.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_sample_cntr.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_slave_bus_ifc.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_sync.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_tests_misc.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_top.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_uart.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_watchdog.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_watchdog_defs.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_watchdog_frc.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_iop_gpio.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\CortexM1Dbg.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\CortexM1DbgIntegration.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\CortexM1DbgIntegrationWrapper.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\dapahbap.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPAhbApAhbSync.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPAhbApDapSync.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPAhbApDefs.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPAhbApMst.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPAhbApSlv.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPAhbApSyn.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPDecMux.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPDpApbDefs.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPDpApbSync.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPDpEnSync.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPDpIMux.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPDpSync.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPJtagDpDefs.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPJtagDpProtocol.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPSwDpApbIf.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPSwDpDefs.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPSwDpProtocol.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPSwDpSync.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\dapswjdp.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPSwjDpDefs.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPSwjWatcher.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\ddr3_1_4code.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DDR3_define.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\ddr3_name.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\ddr3_to_ahb_top.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DDR3_TOP.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\dtcmdbg.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\Gowin_EMPU_M1_top.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\GowinAhbExt.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\GowinCM1AhbExt.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\GowinCM1AhbExtWrapper.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\gw_ahb_psram.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\gw_apb_i2c.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\gw_apb_int_wrapper.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\gw_apb_sd.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\gw_gpio.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\InputStage.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\itcmdbg_2ac.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\MatrixDecodeS0.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\MatrixDecodeS1.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\MatrixDecodeS2.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\OutputArb1.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\OutputArb2.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\OutputArb3.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\OutputStage1.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\OutputStage2.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\OutputStage3.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\p_sse050_interconnect_f0_ahb_to_apb.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\p_sse050_interconnect_f0_apb_slave_mux.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\psram_code.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\psram_top.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\rng_addr_params.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\rng_cc_params.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\rng_params.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\Rtc.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\RtcApbif.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\RtcControl.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\RtcCounter.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\RtcInterrupt.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\RtcParams.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\RtcRevAnd.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\RtcSynctoPCLK.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\RtcUpdate.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\sse050_int_apb_decoder.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\sse050_integration_peripherals.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\sync_p2p.v C:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\GOWIN_EMPU_M1\data\debug\triple_speed_mac_name.v E:\W_File\ISP_V2\Onboard_230320\Gowin_ISP_RefDesign_0423_keil_SRAM\Gowin_ISP_RefDesign\FPGA_Design\src\gowin_empu_m1\temp\gw_empu_m1\cm1_option_defs.v E:\W_File\ISP_V2\Onboard_230320\Gowin_ISP_RefDesign_0423_keil_SRAM\Gowin_ISP_RefDesign\FPGA_Design\src\gowin_empu_m1\temp\gw_empu_m1\ahb_option_defs.v E:\W_File\ISP_V2\Onboard_230320\Gowin_ISP_RefDesign_0423_keil_SRAM\Gowin_ISP_RefDesign\FPGA_Design\src\gowin_empu_m1\temp\gw_empu_m1\can_parameter.vh E:\W_File\ISP_V2\Onboard_230320\Gowin_ISP_RefDesign_0423_keil_SRAM\Gowin_ISP_RefDesign\FPGA_Design\src\gowin_empu_m1\temp\gw_empu_m1\triple_speed_mac_param.v E:\W_File\ISP_V2\Onboard_230320\Gowin_ISP_RefDesign_0423_keil_SRAM\Gowin_ISP_RefDesign\FPGA_Design\src\gowin_empu_m1\temp\gw_empu_m1\triple_speed_mac_define.v |
GowinSynthesis Constraints File | --- |
Version | V1.9.9 Beta3-1 |
Part Number | GW2A-LV55PG484C8/I7 |
Device | GW2A-55 |
Device Version | C |
Created Time | Tue Apr 25 14:32:38 2023 |
Legal Announcement | Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | Gowin_EMPU_M1_Top |
Synthesis Process | Running parser: CPU time = 0h 0m 10s, Elapsed time = 0h 0m 10s, Peak memory usage = 106.844MB Running netlist conversion: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.164s, Peak memory usage = 106.844MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.812s, Elapsed time = 0h 0m 0.804s, Peak memory usage = 106.844MB Optimizing Phase 1: CPU time = 0h 0m 0.281s, Elapsed time = 0h 0m 0.289s, Peak memory usage = 106.844MB Optimizing Phase 2: CPU time = 0h 0m 0.89s, Elapsed time = 0h 0m 0.89s, Peak memory usage = 106.844MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.265s, Elapsed time = 0h 0m 0.256s, Peak memory usage = 106.844MB Inferring Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.052s, Peak memory usage = 106.844MB Inferring Phase 2: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.076s, Peak memory usage = 106.844MB Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.014s, Peak memory usage = 106.844MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 106.844MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.193s, Peak memory usage = 106.844MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.343s, Elapsed time = 0h 0m 0.351s, Peak memory usage = 106.844MB Tech-Mapping Phase 3: CPU time = 0h 0m 30s, Elapsed time = 0h 0m 31s, Peak memory usage = 106.844MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.953s, Elapsed time = 0h 0m 0.96s, Peak memory usage = 106.844MB Generate output files: CPU time = 0h 0m 0.453s, Elapsed time = 0h 0m 0.494s, Peak memory usage = 106.844MB |
Total Time and Memory Usage | CPU time = 0h 0m 45s, Elapsed time = 0h 0m 46s, Peak memory usage = 106.844MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 191 |
I/O Buf | 190 |
    IBUF | 56 |
    OBUF | 133 |
    IOBUF | 1 |
Register | 2477 |
    DFF | 91 |
    DFFSE | 1 |
    DFFR | 3 |
    DFFRE | 1 |
    DFFP | 29 |
    DFFPE | 85 |
    DFFC | 459 |
    DFFCE | 1807 |
    DFFNC | 1 |
LUT | 5560 |
    LUT2 | 543 |
    LUT3 | 1578 |
    LUT4 | 3439 |
ALU | 149 |
    ALU | 149 |
SSRAM | 20 |
    RAM16S4 | 4 |
    RAM16SDP4 | 16 |
INV | 5 |
    INV | 5 |
DSP | 1 |
    MULT36X36 | 1 |
BSRAM | 12 |
    DPB | 12 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 5834(5565 LUTs, 149 ALUs, 20 SSRAMs) / 54720 | 11% |
Register | 2477 / 41997 | 6% |
  --Register as Latch | 0 / 41997 | 0% |
  --Register as FF | 2477 / 41997 | 6% |
BSRAM | 12 / 140 | 9% |
Timing
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|
HCLK | Base | 10.000 | 100.0 | 0.000 | 5.000 | HCLK_ibuf/I | ||
JTAG_9 | Base | 10.000 | 100.0 | 0.000 | 5.000 | JTAG_9_ibuf/I |
Max Frequency Summary:
No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | HCLK | 100.0(MHz) | 99.3(MHz) | 16 | TOP |
2 | JTAG_9 | 100.0(MHz) | 140.0(MHz) | 5 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | -0.188 |
Data Arrival Time | 10.981 |
Data Required Time | 10.793 |
From | M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/APbanksel_5_s0 |
To | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/PackCtr_0_s1 |
Launch Clk | JTAG_9[R] |
Latch Clk | HCLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | JTAG_9 | |||
0.000 | 0.000 | tCL | RR | 1 | JTAG_9_ibuf/I |
0.683 | 0.683 | tINS | RR | 137 | JTAG_9_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/APbanksel_5_s0/CLK |
1.095 | 0.232 | tC2Q | RF | 5 | M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/APbanksel_5_s0/Q |
1.332 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapSlvErr_s5/I1 |
1.887 | 0.555 | tINS | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapSlvErr_s5/F |
2.124 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapSlvErr_s3/I0 |
2.641 | 0.517 | tINS | FF | 3 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapSlvErr_s3/F |
2.878 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_0_s27/I2 |
3.331 | 0.453 | tINS | FF | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_0_s27/F |
3.568 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbTrReq_s4/I2 |
4.021 | 0.453 | tINS | FF | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbTrReq_s4/F |
4.258 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbTrReq_s3/I3 |
4.628 | 0.371 | tINS | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbTrReq_s3/F |
4.865 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbTrReq_s1/I1 |
5.420 | 0.555 | tINS | FF | 3 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbTrReq_s1/F |
5.657 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s26/I2 |
6.110 | 0.453 | tINS | FF | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s26/F |
6.347 | 0.237 | tNET | FF | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n364_s0/I1 |
6.918 | 0.570 | tINS | FR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n364_s0/COUT |
6.918 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n365_s0/CIN |
6.953 | 0.035 | tINS | RF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n365_s0/COUT |
6.953 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n366_s0/CIN |
6.988 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n366_s0/COUT |
7.225 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s2/I2 |
7.678 | 0.453 | tINS | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s2/F |
7.915 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s1/I1 |
8.470 | 0.555 | tINS | FF | 8 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s1/F |
8.707 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaWrEn_s4/I1 |
9.262 | 0.555 | tINS | FF | 3 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaWrEn_s4/F |
9.499 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextPackCtr_0_s8/I2 |
9.952 | 0.453 | tINS | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextPackCtr_0_s8/F |
10.189 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextPackCtr_0_s7/I1 |
10.744 | 0.555 | tINS | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextPackCtr_0_s7/F |
10.981 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/PackCtr_0_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | HCLK | |||
10.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 2386 | HCLK_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/PackCtr_0_s1/CLK |
10.828 | -0.035 | tUnc | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/PackCtr_0_s1 | ||
10.793 | -0.035 | tSu | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/PackCtr_0_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 15 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 6.568, 64.915%; route: 3.318, 32.792%; tC2Q: 0.232, 2.293% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 2
Path Summary:Slack | -0.150 |
Data Arrival Time | 10.943 |
Data Required Time | 10.793 |
From | M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/APbanksel_5_s0 |
To | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_12_s0 |
Launch Clk | JTAG_9[R] |
Latch Clk | HCLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | JTAG_9 | |||
0.000 | 0.000 | tCL | RR | 1 | JTAG_9_ibuf/I |
0.683 | 0.683 | tINS | RR | 137 | JTAG_9_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/APbanksel_5_s0/CLK |
1.095 | 0.232 | tC2Q | RF | 5 | M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/APbanksel_5_s0/Q |
1.332 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapSlvErr_s5/I1 |
1.887 | 0.555 | tINS | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapSlvErr_s5/F |
2.124 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapSlvErr_s3/I0 |
2.641 | 0.517 | tINS | FF | 3 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapSlvErr_s3/F |
2.878 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_0_s27/I2 |
3.331 | 0.453 | tINS | FF | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_0_s27/F |
3.568 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbTrReq_s4/I2 |
4.021 | 0.453 | tINS | FF | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbTrReq_s4/F |
4.258 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbTrReq_s3/I3 |
4.628 | 0.371 | tINS | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbTrReq_s3/F |
4.865 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbTrReq_s1/I1 |
5.420 | 0.555 | tINS | FF | 3 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbTrReq_s1/F |
5.657 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s26/I2 |
6.110 | 0.453 | tINS | FF | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s26/F |
6.347 | 0.237 | tNET | FF | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n364_s0/I1 |
6.918 | 0.570 | tINS | FR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n364_s0/COUT |
6.918 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n365_s0/CIN |
6.953 | 0.035 | tINS | RF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n365_s0/COUT |
6.953 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n366_s0/CIN |
6.988 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n366_s0/COUT |
7.225 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s2/I2 |
7.678 | 0.453 | tINS | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s2/F |
7.915 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s1/I1 |
8.470 | 0.555 | tINS | FF | 8 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s1/F |
8.707 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_1_s4/I0 |
9.224 | 0.517 | tINS | FF | 32 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_1_s4/F |
9.461 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_12_s1/I1 |
10.016 | 0.555 | tINS | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_12_s1/F |
10.253 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_12_s0/I2 |
10.706 | 0.453 | tINS | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_12_s0/F |
10.943 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_12_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | HCLK | |||
10.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 2386 | HCLK_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_12_s0/CLK |
10.828 | -0.035 | tUnc | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_12_s0 | ||
10.793 | -0.035 | tSu | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_12_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 15 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 6.530, 64.784%; route: 3.318, 32.915%; tC2Q: 0.232, 2.301% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 3
Path Summary:Slack | -0.150 |
Data Arrival Time | 10.943 |
Data Required Time | 10.793 |
From | M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/APbanksel_5_s0 |
To | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_13_s0 |
Launch Clk | JTAG_9[R] |
Latch Clk | HCLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | JTAG_9 | |||
0.000 | 0.000 | tCL | RR | 1 | JTAG_9_ibuf/I |
0.683 | 0.683 | tINS | RR | 137 | JTAG_9_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/APbanksel_5_s0/CLK |
1.095 | 0.232 | tC2Q | RF | 5 | M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/APbanksel_5_s0/Q |
1.332 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapSlvErr_s5/I1 |
1.887 | 0.555 | tINS | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapSlvErr_s5/F |
2.124 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapSlvErr_s3/I0 |
2.641 | 0.517 | tINS | FF | 3 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapSlvErr_s3/F |
2.878 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_0_s27/I2 |
3.331 | 0.453 | tINS | FF | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_0_s27/F |
3.568 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbTrReq_s4/I2 |
4.021 | 0.453 | tINS | FF | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbTrReq_s4/F |
4.258 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbTrReq_s3/I3 |
4.628 | 0.371 | tINS | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbTrReq_s3/F |
4.865 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbTrReq_s1/I1 |
5.420 | 0.555 | tINS | FF | 3 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbTrReq_s1/F |
5.657 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s26/I2 |
6.110 | 0.453 | tINS | FF | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s26/F |
6.347 | 0.237 | tNET | FF | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n364_s0/I1 |
6.918 | 0.570 | tINS | FR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n364_s0/COUT |
6.918 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n365_s0/CIN |
6.953 | 0.035 | tINS | RF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n365_s0/COUT |
6.953 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n366_s0/CIN |
6.988 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n366_s0/COUT |
7.225 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s2/I2 |
7.678 | 0.453 | tINS | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s2/F |
7.915 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s1/I1 |
8.470 | 0.555 | tINS | FF | 8 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s1/F |
8.707 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_1_s4/I0 |
9.224 | 0.517 | tINS | FF | 32 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_1_s4/F |
9.461 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_13_s1/I1 |
10.016 | 0.555 | tINS | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_13_s1/F |
10.253 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_13_s0/I2 |
10.706 | 0.453 | tINS | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_13_s0/F |
10.943 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_13_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | HCLK | |||
10.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 2386 | HCLK_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_13_s0/CLK |
10.828 | -0.035 | tUnc | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_13_s0 | ||
10.793 | -0.035 | tSu | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_13_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 15 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 6.530, 64.784%; route: 3.318, 32.915%; tC2Q: 0.232, 2.301% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 4
Path Summary:Slack | -0.150 |
Data Arrival Time | 10.943 |
Data Required Time | 10.793 |
From | M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/APbanksel_5_s0 |
To | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_14_s0 |
Launch Clk | JTAG_9[R] |
Latch Clk | HCLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | JTAG_9 | |||
0.000 | 0.000 | tCL | RR | 1 | JTAG_9_ibuf/I |
0.683 | 0.683 | tINS | RR | 137 | JTAG_9_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/APbanksel_5_s0/CLK |
1.095 | 0.232 | tC2Q | RF | 5 | M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/APbanksel_5_s0/Q |
1.332 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapSlvErr_s5/I1 |
1.887 | 0.555 | tINS | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapSlvErr_s5/F |
2.124 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapSlvErr_s3/I0 |
2.641 | 0.517 | tINS | FF | 3 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapSlvErr_s3/F |
2.878 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_0_s27/I2 |
3.331 | 0.453 | tINS | FF | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_0_s27/F |
3.568 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbTrReq_s4/I2 |
4.021 | 0.453 | tINS | FF | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbTrReq_s4/F |
4.258 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbTrReq_s3/I3 |
4.628 | 0.371 | tINS | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbTrReq_s3/F |
4.865 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbTrReq_s1/I1 |
5.420 | 0.555 | tINS | FF | 3 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbTrReq_s1/F |
5.657 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s26/I2 |
6.110 | 0.453 | tINS | FF | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s26/F |
6.347 | 0.237 | tNET | FF | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n364_s0/I1 |
6.918 | 0.570 | tINS | FR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n364_s0/COUT |
6.918 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n365_s0/CIN |
6.953 | 0.035 | tINS | RF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n365_s0/COUT |
6.953 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n366_s0/CIN |
6.988 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n366_s0/COUT |
7.225 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s2/I2 |
7.678 | 0.453 | tINS | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s2/F |
7.915 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s1/I1 |
8.470 | 0.555 | tINS | FF | 8 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s1/F |
8.707 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_1_s4/I0 |
9.224 | 0.517 | tINS | FF | 32 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_1_s4/F |
9.461 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_14_s1/I1 |
10.016 | 0.555 | tINS | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_14_s1/F |
10.253 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_14_s0/I2 |
10.706 | 0.453 | tINS | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_14_s0/F |
10.943 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_14_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | HCLK | |||
10.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 2386 | HCLK_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_14_s0/CLK |
10.828 | -0.035 | tUnc | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_14_s0 | ||
10.793 | -0.035 | tSu | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_14_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 15 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 6.530, 64.784%; route: 3.318, 32.915%; tC2Q: 0.232, 2.301% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 5
Path Summary:Slack | -0.150 |
Data Arrival Time | 10.943 |
Data Required Time | 10.793 |
From | M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/APbanksel_5_s0 |
To | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_15_s0 |
Launch Clk | JTAG_9[R] |
Latch Clk | HCLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | JTAG_9 | |||
0.000 | 0.000 | tCL | RR | 1 | JTAG_9_ibuf/I |
0.683 | 0.683 | tINS | RR | 137 | JTAG_9_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/APbanksel_5_s0/CLK |
1.095 | 0.232 | tC2Q | RF | 5 | M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/APbanksel_5_s0/Q |
1.332 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapSlvErr_s5/I1 |
1.887 | 0.555 | tINS | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapSlvErr_s5/F |
2.124 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapSlvErr_s3/I0 |
2.641 | 0.517 | tINS | FF | 3 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapSlvErr_s3/F |
2.878 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_0_s27/I2 |
3.331 | 0.453 | tINS | FF | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_0_s27/F |
3.568 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbTrReq_s4/I2 |
4.021 | 0.453 | tINS | FF | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbTrReq_s4/F |
4.258 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbTrReq_s3/I3 |
4.628 | 0.371 | tINS | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbTrReq_s3/F |
4.865 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbTrReq_s1/I1 |
5.420 | 0.555 | tINS | FF | 3 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbTrReq_s1/F |
5.657 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s26/I2 |
6.110 | 0.453 | tINS | FF | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s26/F |
6.347 | 0.237 | tNET | FF | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n364_s0/I1 |
6.918 | 0.570 | tINS | FR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n364_s0/COUT |
6.918 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n365_s0/CIN |
6.953 | 0.035 | tINS | RF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n365_s0/COUT |
6.953 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n366_s0/CIN |
6.988 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n366_s0/COUT |
7.225 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s2/I2 |
7.678 | 0.453 | tINS | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s2/F |
7.915 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s1/I1 |
8.470 | 0.555 | tINS | FF | 8 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s1/F |
8.707 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_1_s4/I0 |
9.224 | 0.517 | tINS | FF | 32 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_1_s4/F |
9.461 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_15_s1/I1 |
10.016 | 0.555 | tINS | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_15_s1/F |
10.253 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_15_s0/I2 |
10.706 | 0.453 | tINS | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_15_s0/F |
10.943 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_15_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | HCLK | |||
10.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 2386 | HCLK_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_15_s0/CLK |
10.828 | -0.035 | tUnc | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_15_s0 | ||
10.793 | -0.035 | tSu | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_15_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 15 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 6.530, 64.784%; route: 3.318, 32.915%; tC2Q: 0.232, 2.301% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |