Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | D:\Gowin\Gowin_V1.9.11_x64\IDE\ipcore\MII_to_RMII\data\mii_to_rmii_wrap.v D:\Gowin\Gowin_V1.9.11_x64\IDE\ipcore\MII_to_RMII\data\mii_to_rmii.v |
GowinSynthesis Constraints File | --- |
Tool Version | V1.9.11 (64-bit) |
Part Number | GW5A-LV25UG324ES |
Device | GW5A-25 |
Device Version | A |
Created Time | Mon Dec 9 10:37:38 2024 |
Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | MII_to_RMII_Top |
Synthesis Process | Running parser: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.599s, Peak memory usage = 77.055MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 77.055MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 77.055MB Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 77.055MB Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 77.055MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.017s, Peak memory usage = 77.055MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 77.055MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 77.055MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 77.055MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 77.055MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0s, Peak memory usage = 77.055MB Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 77.055MB Tech-Mapping Phase 3: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.186s, Peak memory usage = 97.438MB Tech-Mapping Phase 4: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 97.438MB Generate output files: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.335s, Peak memory usage = 97.438MB |
Total Time and Memory Usage | CPU time = 0h 0m 0.233s, Elapsed time = 0h 0m 1s, Peak memory usage = 97.438MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 26 |
I/O Buf | 25 |
    IBUF | 12 |
    OBUF | 13 |
Register | 37 |
    DFFPE | 1 |
    DFFCE | 36 |
LUT | 31 |
    LUT2 | 7 |
    LUT3 | 8 |
    LUT4 | 16 |
INV | 5 |
    INV | 5 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 36(36 LUT, 0 ALU) / 23040 | <1% |
Register | 37 / 23685 | <1% |
  --Register as Latch | 0 / 23685 | 0% |
  --Register as FF | 37 / 23685 | <1% |
BSRAM | 0 / 56 | 0% |
Timing
Clock Summary:
NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|---|
1 | refclk | Base | 10.000 | 100.0 | 0.000 | 5.000 | refclk_ibuf/I |
Max Frequency Summary:
NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | refclk | 100.000(MHz) | 348.280(MHz) | 3 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | 7.129 |
Data Arrival Time | 2.935 |
Data Required Time | 10.064 |
From | u_rmii_txrx/u_rmii_rx/rmii_rx_crs_dv_d1_s0 |
To | u_rmii_txrx/u_rmii_rx/di_bits_first_s0 |
Launch Clk | refclk[R] |
Latch Clk | refclk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | refclk | |||
0.000 | 0.000 | tCL | RR | 1 | refclk_ibuf/I |
0.000 | 0.000 | tINS | RR | 37 | refclk_ibuf/O |
0.375 | 0.375 | tNET | RR | 1 | u_rmii_txrx/u_rmii_rx/rmii_rx_crs_dv_d1_s0/CLK |
0.757 | 0.382 | tC2Q | RR | 3 | u_rmii_txrx/u_rmii_rx/rmii_rx_crs_dv_d1_s0/Q |
1.132 | 0.375 | tNET | RR | 1 | u_rmii_txrx/u_rmii_rx/di_bits_first_s3/I0 |
1.659 | 0.526 | tINS | RR | 1 | u_rmii_txrx/u_rmii_rx/di_bits_first_s3/F |
2.034 | 0.375 | tNET | RR | 1 | u_rmii_txrx/u_rmii_rx/di_bits_first_s4/I0 |
2.560 | 0.526 | tINS | RR | 1 | u_rmii_txrx/u_rmii_rx/di_bits_first_s4/F |
2.935 | 0.375 | tNET | RR | 1 | u_rmii_txrx/u_rmii_rx/di_bits_first_s0/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | refclk | |||
10.000 | 0.000 | tCL | RR | 1 | refclk_ibuf/I |
10.000 | 0.000 | tINS | RR | 37 | refclk_ibuf/O |
10.375 | 0.375 | tNET | RR | 1 | u_rmii_txrx/u_rmii_rx/di_bits_first_s0/CLK |
10.064 | -0.311 | tSu | 1 | u_rmii_txrx/u_rmii_rx/di_bits_first_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 3 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Arrival Data Path Delay: | cell: 1.053, 41.113%; route: 1.125, 43.946%; tC2Q: 0.382, 14.941% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 2
Path Summary:Slack | 7.139 |
Data Arrival Time | 2.925 |
Data Required Time | 10.064 |
From | u_rmii_txrx/u_rmii_rx/rmii_rxd_d1_1_s0 |
To | u_rmii_txrx/u_rmii_rx/di_bits_cnt_0_s0 |
Launch Clk | refclk[R] |
Latch Clk | refclk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | refclk | |||
0.000 | 0.000 | tCL | RR | 1 | refclk_ibuf/I |
0.000 | 0.000 | tINS | RR | 37 | refclk_ibuf/O |
0.375 | 0.375 | tNET | RR | 1 | u_rmii_txrx/u_rmii_rx/rmii_rxd_d1_1_s0/CLK |
0.757 | 0.382 | tC2Q | RR | 3 | u_rmii_txrx/u_rmii_rx/rmii_rxd_d1_1_s0/Q |
1.132 | 0.375 | tNET | RR | 1 | u_rmii_txrx/u_rmii_rx/di_bits_cnt_1_s3/I0 |
1.659 | 0.526 | tINS | RR | 4 | u_rmii_txrx/u_rmii_rx/di_bits_cnt_1_s3/F |
2.034 | 0.375 | tNET | RR | 1 | u_rmii_txrx/u_rmii_rx/di_bits_cnt_1_s4/I1 |
2.550 | 0.516 | tINS | RR | 2 | u_rmii_txrx/u_rmii_rx/di_bits_cnt_1_s4/F |
2.925 | 0.375 | tNET | RR | 1 | u_rmii_txrx/u_rmii_rx/di_bits_cnt_0_s0/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | refclk | |||
10.000 | 0.000 | tCL | RR | 1 | refclk_ibuf/I |
10.000 | 0.000 | tINS | RR | 37 | refclk_ibuf/O |
10.375 | 0.375 | tNET | RR | 1 | u_rmii_txrx/u_rmii_rx/di_bits_cnt_0_s0/CLK |
10.064 | -0.311 | tSu | 1 | u_rmii_txrx/u_rmii_rx/di_bits_cnt_0_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 3 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Arrival Data Path Delay: | cell: 1.043, 40.882%; route: 1.125, 44.118%; tC2Q: 0.382, 15.000% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 3
Path Summary:Slack | 7.139 |
Data Arrival Time | 2.925 |
Data Required Time | 10.064 |
From | u_rmii_txrx/u_rmii_rx/rmii_rxd_d1_1_s0 |
To | u_rmii_txrx/u_rmii_rx/di_bits_cnt_1_s0 |
Launch Clk | refclk[R] |
Latch Clk | refclk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | refclk | |||
0.000 | 0.000 | tCL | RR | 1 | refclk_ibuf/I |
0.000 | 0.000 | tINS | RR | 37 | refclk_ibuf/O |
0.375 | 0.375 | tNET | RR | 1 | u_rmii_txrx/u_rmii_rx/rmii_rxd_d1_1_s0/CLK |
0.757 | 0.382 | tC2Q | RR | 3 | u_rmii_txrx/u_rmii_rx/rmii_rxd_d1_1_s0/Q |
1.132 | 0.375 | tNET | RR | 1 | u_rmii_txrx/u_rmii_rx/di_bits_cnt_1_s3/I0 |
1.659 | 0.526 | tINS | RR | 4 | u_rmii_txrx/u_rmii_rx/di_bits_cnt_1_s3/F |
2.034 | 0.375 | tNET | RR | 1 | u_rmii_txrx/u_rmii_rx/di_bits_cnt_1_s4/I1 |
2.550 | 0.516 | tINS | RR | 2 | u_rmii_txrx/u_rmii_rx/di_bits_cnt_1_s4/F |
2.925 | 0.375 | tNET | RR | 1 | u_rmii_txrx/u_rmii_rx/di_bits_cnt_1_s0/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | refclk | |||
10.000 | 0.000 | tCL | RR | 1 | refclk_ibuf/I |
10.000 | 0.000 | tINS | RR | 37 | refclk_ibuf/O |
10.375 | 0.375 | tNET | RR | 1 | u_rmii_txrx/u_rmii_rx/di_bits_cnt_1_s0/CLK |
10.064 | -0.311 | tSu | 1 | u_rmii_txrx/u_rmii_rx/di_bits_cnt_1_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 3 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Arrival Data Path Delay: | cell: 1.043, 40.882%; route: 1.125, 44.118%; tC2Q: 0.382, 15.000% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 4
Path Summary:Slack | 7.139 |
Data Arrival Time | 2.925 |
Data Required Time | 10.064 |
From | u_rmii_txrx/u_clk_gen/clk_cnt_2_s0 |
To | u_rmii_txrx/u_clk_gen/clk_div_s3 |
Launch Clk | refclk[R] |
Latch Clk | refclk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | refclk | |||
0.000 | 0.000 | tCL | RR | 1 | refclk_ibuf/I |
0.000 | 0.000 | tINS | RR | 37 | refclk_ibuf/O |
0.375 | 0.375 | tNET | RR | 1 | u_rmii_txrx/u_clk_gen/clk_cnt_2_s0/CLK |
0.757 | 0.382 | tC2Q | RR | 6 | u_rmii_txrx/u_clk_gen/clk_cnt_2_s0/Q |
1.132 | 0.375 | tNET | RR | 1 | u_rmii_txrx/u_clk_gen/clk_div_s6/I0 |
1.659 | 0.526 | tINS | RR | 1 | u_rmii_txrx/u_clk_gen/clk_div_s6/F |
2.034 | 0.375 | tNET | RR | 1 | u_rmii_txrx/u_clk_gen/clk_div_s5/I1 |
2.550 | 0.516 | tINS | RR | 1 | u_rmii_txrx/u_clk_gen/clk_div_s5/F |
2.925 | 0.375 | tNET | RR | 1 | u_rmii_txrx/u_clk_gen/clk_div_s3/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | refclk | |||
10.000 | 0.000 | tCL | RR | 1 | refclk_ibuf/I |
10.000 | 0.000 | tINS | RR | 37 | refclk_ibuf/O |
10.375 | 0.375 | tNET | RR | 1 | u_rmii_txrx/u_clk_gen/clk_div_s3/CLK |
10.064 | -0.311 | tSu | 1 | u_rmii_txrx/u_clk_gen/clk_div_s3 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 3 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Arrival Data Path Delay: | cell: 1.043, 40.882%; route: 1.125, 44.118%; tC2Q: 0.382, 15.000% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 5
Path Summary:Slack | 7.376 |
Data Arrival Time | 2.935 |
Data Required Time | 10.311 |
From | u_rmii_txrx/u_rmii_rx/di_bits_er_0_s0 |
To | u_rmii_txrx/u_rmii_rx/mii_rx_er_s2 |
Launch Clk | refclk[R] |
Latch Clk | refclk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | refclk | |||
0.000 | 0.000 | tCL | RR | 1 | refclk_ibuf/I |
0.000 | 0.000 | tINS | RR | 37 | refclk_ibuf/O |
0.375 | 0.375 | tNET | RR | 1 | u_rmii_txrx/u_rmii_rx/di_bits_er_0_s0/CLK |
0.757 | 0.382 | tC2Q | RR | 1 | u_rmii_txrx/u_rmii_rx/di_bits_er_0_s0/Q |
1.132 | 0.375 | tNET | RR | 1 | u_rmii_txrx/u_rmii_rx/n100_s8/I0 |
1.659 | 0.526 | tINS | RR | 1 | u_rmii_txrx/u_rmii_rx/n100_s8/F |
2.034 | 0.375 | tNET | RR | 1 | u_rmii_txrx/u_rmii_rx/n100_s7/I0 |
2.560 | 0.526 | tINS | RR | 1 | u_rmii_txrx/u_rmii_rx/n100_s7/F |
2.935 | 0.375 | tNET | RR | 1 | u_rmii_txrx/u_rmii_rx/mii_rx_er_s2/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | refclk | |||
10.000 | 0.000 | tCL | RR | 1 | refclk_ibuf/I |
10.000 | 0.000 | tINS | RR | 37 | refclk_ibuf/O |
10.375 | 0.375 | tNET | RR | 1 | u_rmii_txrx/u_rmii_rx/mii_rx_er_s2/CLK |
10.311 | -0.064 | tSu | 1 | u_rmii_txrx/u_rmii_rx/mii_rx_er_s2 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 3 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Arrival Data Path Delay: | cell: 1.053, 41.113%; route: 1.125, 43.946%; tC2Q: 0.382, 14.941% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |