Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | E:\IP_Release\MII_TO_RMII\1.0\ref_design\Gowin_MII_to_RMII_RefDesign\project\src\mii_to_rmii\mii_to_rmii.v E:\IP_Release\MII_TO_RMII\1.0\ref_design\Gowin_MII_to_RMII_RefDesign\project\src\triple_speed_ethernet_mac\triple_speed_ethernet_mac.v E:\IP_Release\MII_TO_RMII\1.0\ref_design\Gowin_MII_to_RMII_RefDesign\project\src\top.v E:\IP_Release\MII_TO_RMII\1.0\ref_design\Gowin_MII_to_RMII_RefDesign\project\src\mac_rx_model.v E:\IP_Release\MII_TO_RMII\1.0\ref_design\Gowin_MII_to_RMII_RefDesign\project\src\mac_tx_model.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.11 (64-bit) |
| Part Number | GW5A-LV25UG324ES |
| Device | GW5A-25 |
| Device Version | A |
| Created Time | Mon Dec 9 15:14:04 2024 |
| Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | top |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.453s, Elapsed time = 0h 0m 0.482s, Peak memory usage = 246.168MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.042s, Peak memory usage = 246.168MB Optimizing Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.039s, Peak memory usage = 246.168MB Optimizing Phase 2: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.102s, Peak memory usage = 246.168MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.028s, Peak memory usage = 246.168MB Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 246.168MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 246.168MB Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 246.168MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.172s, Peak memory usage = 246.168MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.025s, Peak memory usage = 246.168MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 246.168MB Tech-Mapping Phase 3: CPU time = 0h 0m 0.843s, Elapsed time = 0h 0m 0.891s, Peak memory usage = 246.168MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.187s, Peak memory usage = 246.168MB Generate output files: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.124s, Peak memory usage = 246.168MB |
| Total Time and Memory Usage | CPU time = 0h 0m 1s, Elapsed time = 0h 0m 2s, Peak memory usage = 246.168MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 8 |
| I/O Buf | 8 |
| IBUF | 4 |
| OBUF | 4 |
| Register | 1340 |
| DFFPE | 91 |
| DFFCE | 1249 |
| LUT | 1184 |
| LUT2 | 192 |
| LUT3 | 239 |
| LUT4 | 753 |
| ALU | 146 |
| ALU | 146 |
| INV | 15 |
| INV | 15 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 1345(1199 LUT, 146 ALU) / 23040 | 6% |
| Register | 1340 / 23685 | 6% |
| --Register as Latch | 0 / 23685 | 0% |
| --Register as FF | 1340 / 23685 | 6% |
| BSRAM | 0 / 56 | 0% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | refclk | Base | 10.000 | 100.0 | 0.000 | 5.000 | refclk_ibuf/I | ||
| 2 | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/tx_mac_clk | Base | 10.000 | 100.0 | 0.000 | 5.000 | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | refclk | 100.000(MHz) | 225.925(MHz) | 5 | TOP |
| 2 | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/tx_mac_clk | 100.000(MHz) | 182.149(MHz) | 6 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 4.510 |
| Data Arrival Time | 5.554 |
| Data Required Time | 10.064 |
| From | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/frm_byte_cnt_3_s3 |
| To | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_fcs_s6 |
| Launch Clk | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/tx_mac_clk[R] |
| Latch Clk | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/tx_mac_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/tx_mac_clk | |||
| 0.000 | 0.000 | tCL | RR | 1284 | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 0.375 | 0.375 | tNET | RR | 1 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/frm_byte_cnt_3_s3/CLK |
| 0.757 | 0.382 | tC2Q | RR | 20 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/frm_byte_cnt_3_s3/Q |
| 1.132 | 0.375 | tNET | RR | 1 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/late_col_s8/I0 |
| 1.659 | 0.526 | tINS | RR | 3 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/late_col_s8/F |
| 2.034 | 0.375 | tNET | RR | 1 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s17/I1 |
| 2.550 | 0.516 | tINS | RR | 1 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s17/F |
| 2.925 | 0.375 | tNET | RR | 1 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s6/I1 |
| 3.441 | 0.516 | tINS | RR | 1 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s6/F |
| 3.816 | 0.375 | tNET | RR | 1 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s5/I0 |
| 4.343 | 0.526 | tINS | RR | 2 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s5/F |
| 4.718 | 0.375 | tNET | RR | 1 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s4/I2 |
| 5.179 | 0.461 | tINS | RR | 8 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s4/F |
| 5.554 | 0.375 | tNET | RR | 1 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_fcs_s6/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/tx_mac_clk | |||
| 10.000 | 0.000 | tCL | RR | 1284 | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 10.375 | 0.375 | tNET | RR | 1 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_fcs_s6/CLK |
| 10.064 | -0.311 | tSu | 1 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_fcs_s6 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
| Arrival Data Path Delay: | cell: 2.546, 49.167%; route: 2.250, 43.447%; tC2Q: 0.382, 7.386% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 2
Path Summary:| Slack | 4.510 |
| Data Arrival Time | 5.554 |
| Data Required Time | 10.064 |
| From | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/frm_byte_cnt_3_s3 |
| To | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_pad_s8 |
| Launch Clk | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/tx_mac_clk[R] |
| Latch Clk | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/tx_mac_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/tx_mac_clk | |||
| 0.000 | 0.000 | tCL | RR | 1284 | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 0.375 | 0.375 | tNET | RR | 1 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/frm_byte_cnt_3_s3/CLK |
| 0.757 | 0.382 | tC2Q | RR | 20 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/frm_byte_cnt_3_s3/Q |
| 1.132 | 0.375 | tNET | RR | 1 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/late_col_s8/I0 |
| 1.659 | 0.526 | tINS | RR | 3 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/late_col_s8/F |
| 2.034 | 0.375 | tNET | RR | 1 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s17/I1 |
| 2.550 | 0.516 | tINS | RR | 1 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s17/F |
| 2.925 | 0.375 | tNET | RR | 1 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s6/I1 |
| 3.441 | 0.516 | tINS | RR | 1 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s6/F |
| 3.816 | 0.375 | tNET | RR | 1 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s5/I0 |
| 4.343 | 0.526 | tINS | RR | 2 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s5/F |
| 4.718 | 0.375 | tNET | RR | 1 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s4/I2 |
| 5.179 | 0.461 | tINS | RR | 8 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s4/F |
| 5.554 | 0.375 | tNET | RR | 1 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_pad_s8/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/tx_mac_clk | |||
| 10.000 | 0.000 | tCL | RR | 1284 | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 10.375 | 0.375 | tNET | RR | 1 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_pad_s8/CLK |
| 10.064 | -0.311 | tSu | 1 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_pad_s8 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
| Arrival Data Path Delay: | cell: 2.546, 49.167%; route: 2.250, 43.447%; tC2Q: 0.382, 7.386% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 3
Path Summary:| Slack | 4.510 |
| Data Arrival Time | 5.554 |
| Data Required Time | 10.064 |
| From | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/frm_byte_cnt_3_s3 |
| To | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_jam_s4 |
| Launch Clk | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/tx_mac_clk[R] |
| Latch Clk | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/tx_mac_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/tx_mac_clk | |||
| 0.000 | 0.000 | tCL | RR | 1284 | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 0.375 | 0.375 | tNET | RR | 1 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/frm_byte_cnt_3_s3/CLK |
| 0.757 | 0.382 | tC2Q | RR | 20 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/frm_byte_cnt_3_s3/Q |
| 1.132 | 0.375 | tNET | RR | 1 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/late_col_s8/I0 |
| 1.659 | 0.526 | tINS | RR | 3 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/late_col_s8/F |
| 2.034 | 0.375 | tNET | RR | 1 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s17/I1 |
| 2.550 | 0.516 | tINS | RR | 1 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s17/F |
| 2.925 | 0.375 | tNET | RR | 1 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s6/I1 |
| 3.441 | 0.516 | tINS | RR | 1 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s6/F |
| 3.816 | 0.375 | tNET | RR | 1 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s5/I0 |
| 4.343 | 0.526 | tINS | RR | 2 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s5/F |
| 4.718 | 0.375 | tNET | RR | 1 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s4/I2 |
| 5.179 | 0.461 | tINS | RR | 8 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s4/F |
| 5.554 | 0.375 | tNET | RR | 1 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_jam_s4/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/tx_mac_clk | |||
| 10.000 | 0.000 | tCL | RR | 1284 | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 10.375 | 0.375 | tNET | RR | 1 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_jam_s4/CLK |
| 10.064 | -0.311 | tSu | 1 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_jam_s4 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
| Arrival Data Path Delay: | cell: 2.546, 49.167%; route: 2.250, 43.447%; tC2Q: 0.382, 7.386% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 4
Path Summary:| Slack | 4.510 |
| Data Arrival Time | 5.554 |
| Data Required Time | 10.064 |
| From | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/frm_byte_cnt_3_s3 |
| To | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_data_s12 |
| Launch Clk | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/tx_mac_clk[R] |
| Latch Clk | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/tx_mac_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/tx_mac_clk | |||
| 0.000 | 0.000 | tCL | RR | 1284 | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 0.375 | 0.375 | tNET | RR | 1 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/frm_byte_cnt_3_s3/CLK |
| 0.757 | 0.382 | tC2Q | RR | 20 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/frm_byte_cnt_3_s3/Q |
| 1.132 | 0.375 | tNET | RR | 1 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/late_col_s8/I0 |
| 1.659 | 0.526 | tINS | RR | 3 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/late_col_s8/F |
| 2.034 | 0.375 | tNET | RR | 1 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s17/I1 |
| 2.550 | 0.516 | tINS | RR | 1 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s17/F |
| 2.925 | 0.375 | tNET | RR | 1 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s6/I1 |
| 3.441 | 0.516 | tINS | RR | 1 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s6/F |
| 3.816 | 0.375 | tNET | RR | 1 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s5/I0 |
| 4.343 | 0.526 | tINS | RR | 2 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s5/F |
| 4.718 | 0.375 | tNET | RR | 1 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s4/I2 |
| 5.179 | 0.461 | tINS | RR | 8 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s4/F |
| 5.554 | 0.375 | tNET | RR | 1 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_data_s12/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/tx_mac_clk | |||
| 10.000 | 0.000 | tCL | RR | 1284 | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 10.375 | 0.375 | tNET | RR | 1 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_data_s12/CLK |
| 10.064 | -0.311 | tSu | 1 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_data_s12 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
| Arrival Data Path Delay: | cell: 2.546, 49.167%; route: 2.250, 43.447%; tC2Q: 0.382, 7.386% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 5
Path Summary:| Slack | 4.510 |
| Data Arrival Time | 5.554 |
| Data Required Time | 10.064 |
| From | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/frm_byte_cnt_3_s3 |
| To | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_preamble_s14 |
| Launch Clk | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/tx_mac_clk[R] |
| Latch Clk | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/tx_mac_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/tx_mac_clk | |||
| 0.000 | 0.000 | tCL | RR | 1284 | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 0.375 | 0.375 | tNET | RR | 1 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/frm_byte_cnt_3_s3/CLK |
| 0.757 | 0.382 | tC2Q | RR | 20 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/frm_byte_cnt_3_s3/Q |
| 1.132 | 0.375 | tNET | RR | 1 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/late_col_s8/I0 |
| 1.659 | 0.526 | tINS | RR | 3 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/late_col_s8/F |
| 2.034 | 0.375 | tNET | RR | 1 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s17/I1 |
| 2.550 | 0.516 | tINS | RR | 1 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s17/F |
| 2.925 | 0.375 | tNET | RR | 1 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s6/I1 |
| 3.441 | 0.516 | tINS | RR | 1 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s6/F |
| 3.816 | 0.375 | tNET | RR | 1 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s5/I0 |
| 4.343 | 0.526 | tINS | RR | 2 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s5/F |
| 4.718 | 0.375 | tNET | RR | 1 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s4/I2 |
| 5.179 | 0.461 | tINS | RR | 8 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_ifg_s4/F |
| 5.554 | 0.375 | tNET | RR | 1 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_preamble_s14/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/tx_mac_clk | |||
| 10.000 | 0.000 | tCL | RR | 1284 | u_mii_to_rmii_top/u_rmii_txrx/u_clk_gen/clk_div_s3/Q |
| 10.375 | 0.375 | tNET | RR | 1 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_preamble_s14/CLK |
| 10.064 | -0.311 | tSu | 1 | u_Triple_Speed_Ethernet_MAC_Top/u_triple_speed_mac/u_mac_tx_ctrl/c_state.s_preamble_s14 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
| Arrival Data Path Delay: | cell: 2.546, 49.167%; route: 2.250, 43.447%; tC2Q: 0.382, 7.386% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |