Synthesis Messages

Report Title GowinSynthesis Report
Design File E:\myWork\IP\releaseVerify\version\1.9.10.03\Gowin_MIPI_DPHY_Advance_RefDesign\MIPI_RefDesign_5a25_MIPI_IO\MIPI_RefDesign\src\DPHY_TOP.v
E:\myWork\IP\releaseVerify\version\1.9.10.03\Gowin_MIPI_DPHY_Advance_RefDesign\MIPI_RefDesign_5a25_MIPI_IO\MIPI_RefDesign\src\ROM549X17.v
E:\myWork\IP\releaseVerify\version\1.9.10.03\Gowin_MIPI_DPHY_Advance_RefDesign\MIPI_RefDesign_5a25_MIPI_IO\MIPI_RefDesign\src\mipi_rx_advance\mipi_rx_advance.v
E:\myWork\IP\releaseVerify\version\1.9.10.03\Gowin_MIPI_DPHY_Advance_RefDesign\MIPI_RefDesign_5a25_MIPI_IO\MIPI_RefDesign\src\mipi_tx_advance\mipi_tx_advance.v
C:\Gowin\Gowin_V1.9.10.03_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v
C:\Gowin\Gowin_V1.9.10.03_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v
C:\Gowin\Gowin_V1.9.10.03_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v
C:\Gowin\Gowin_V1.9.10.03_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v
C:\Gowin\Gowin_V1.9.10.03_x64\IDE\data\ipcores\GAO\GW_CON\gw_con_top.v
C:\Gowin\Gowin_V1.9.10.03_x64\IDE\data\ipcores\gw_jtag.v
E:\myWork\IP\releaseVerify\version\1.9.10.03\Gowin_MIPI_DPHY_Advance_RefDesign\MIPI_RefDesign_5a25_MIPI_IO\MIPI_RefDesign\impl\gwsynthesis\RTL_GAO\gw_gao_top.v
GowinSynthesis Constraints File ---
Tool Version V1.9.10.03 (64-bit)
Part Number GW5A-LV25UG324ES
Device GW5A-25
Device Version A
Created Time Thu Oct 24 15:37:49 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module DPHY_TOP
Synthesis Process Running parser:
    CPU time = 0h 0m 0.765s, Elapsed time = 0h 0m 0.704s, Peak memory usage = 1453.371MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.121s, Peak memory usage = 1453.371MB
    Optimizing Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.055s, Peak memory usage = 1453.371MB
    Optimizing Phase 2: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.154s, Peak memory usage = 1453.371MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.062s, Peak memory usage = 1453.371MB
    Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.014s, Peak memory usage = 1453.371MB
    Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 1453.371MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 1453.371MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.082s, Peak memory usage = 1453.371MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.023s, Peak memory usage = 1453.371MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.014s, Peak memory usage = 1453.371MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 1453.371MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.1s, Peak memory usage = 1453.371MB
Generate output files:
    CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.153s, Peak memory usage = 1453.371MB
Total Time and Memory Usage CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 1453.371MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 29
I/O Buf 19
    IBUF 4
    OBUF 5
    MIPI_IBUF 5
    MIPI_OBUF_A 5
Register 1255
    DFFRE 2
    DFFPE 40
    DFFCE 1213
LUT 1865
    LUT2 186
    LUT3 384
    LUT4 1295
MUX 1
    MUX16 1
ALU 25
    ALU 25
INV 12
    INV 12
IOLOGIC 13
    IDES16 4
    OSER16 5
    IODELAY 4
BSRAM 24
    SDPB 23
    pROM 1
CLOCK 4
    CLKDIV 2
    DHCE 1
    PLLA 1
Black Box 1
    GW_JTAG 1

Resource Utilization Summary

Resource Usage Utilization
Logic 1910(1885 LUT, 25 ALU) / 23040 9%
Register 1255 / 23685 6%
  --Register as Latch 0 / 23685 0%
  --Register as FF 1255 / 23685 6%
BSRAM 24 / 56 43%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 clkx2x4 Base 20.000 50.0 0.000 10.000 clkx2x4_ibuf/I
2 MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/IO Base 10.000 100.0 0.000 5.000 MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/IO
3 MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/IOB Base 10.000 100.0 0.000 5.000 MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/IOB
4 MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/IO_gowin Base 10.000 100.0 0.000 5.000 MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/IO
5 MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/IOB_gowin Base 10.000 100.0 0.000 5.000 MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/IOB
6 MIPI_RX_Advance_Top/DPHY_RX_INST/HS_CLK Base 10.000 100.0 0.000 5.000 MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/OH
7 PLLA_mipi_tx/CLKOUT0.default_gen_clk Generated 100.000 10.0 0.000 50.000 clkx2x4_ibuf/I clkx2x4 PLLA_mipi_tx/CLKOUT0
8 PLLA_mipi_tx/CLKOUT1.default_gen_clk Generated 100.000 10.0 0.000 50.000 clkx2x4_ibuf/I clkx2x4 PLLA_mipi_tx/CLKOUT1
9 U3_CLKDIV/CLKOUT.default_gen_clk Generated 800.000 1.3 0.000 400.000 PLLA_mipi_tx/CLKOUT0 PLLA_mipi_tx/CLKOUT0.default_gen_clk U3_CLKDIV/CLKOUT
10 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT.default_gen_clk Generated 80.000 12.5 0.000 40.000 MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/OH MIPI_RX_Advance_Top/DPHY_RX_INST/HS_CLK MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 MIPI_RX_Advance_Top/DPHY_RX_INST/HS_CLK 100.000(MHz) 277.662(MHz) 2 TOP
2 U3_CLKDIV/CLKOUT.default_gen_clk 1.250(MHz) 232.764(MHz) 5 TOP
3 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT.default_gen_clk 12.500(MHz) 181.818(MHz) 6 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 2.543
Data Arrival Time 3.287
Data Required Time 5.830
From u_ROM549x17/lp_dir_s0
To MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_0
Launch Clk U3_CLKDIV/CLKOUT.default_gen_clk[F]
Latch Clk MIPI_RX_Advance_Top/DPHY_RX_INST/HS_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 U3_CLKDIV/CLKOUT.default_gen_clk
0.362 0.362 tCL RR 30 U3_CLKDIV/CLKOUT
0.737 0.375 tNET RR 1 u_ROM549x17/lp_dir_s0/CLK
1.120 0.382 tC2Q RR 21 u_ROM549x17/lp_dir_s0/Q
1.495 0.375 tNET RR 4 MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_LANE0/OEN
2.177 0.683 tINS RR 1 MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_LANE0/OH
2.552 0.375 tNET RR 1 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/udel_dataini0/DI
2.912 0.360 tINS RR 1 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/udel_dataini0/DO
3.287 0.375 tNET RR 1 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
5.000 0.000 MIPI_RX_Advance_Top/DPHY_RX_INST/HS_CLK
5.000 0.000 tCL FF 5 MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/OH
5.350 0.350 tNET FF 3 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CLKIN
5.536 0.186 tINS FF 5 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CLKOUT
5.886 0.350 tNET FF 1 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_0/FCLK
5.851 -0.035 tUnc MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_0
5.830 -0.021 tSu 1 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_0
Path Statistics:
Clock Skew: 0.149
Setup Relationship: 5.000
Logic Level: 3
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 1.043, 40.882%; route: 1.125, 44.118%; tC2Q: 0.382, 15.000%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 2

Path Summary:
Slack 2.543
Data Arrival Time 3.287
Data Required Time 5.830
From u_ROM549x17/lp_dir_s0
To MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_1
Launch Clk U3_CLKDIV/CLKOUT.default_gen_clk[F]
Latch Clk MIPI_RX_Advance_Top/DPHY_RX_INST/HS_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 U3_CLKDIV/CLKOUT.default_gen_clk
0.362 0.362 tCL RR 30 U3_CLKDIV/CLKOUT
0.737 0.375 tNET RR 1 u_ROM549x17/lp_dir_s0/CLK
1.120 0.382 tC2Q RR 21 u_ROM549x17/lp_dir_s0/Q
1.495 0.375 tNET RR 4 MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_LANE1/OEN
2.177 0.683 tINS RR 1 MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_LANE1/OH
2.552 0.375 tNET RR 1 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/udel_dataini1/DI
2.912 0.360 tINS RR 1 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/udel_dataini1/DO
3.287 0.375 tNET RR 1 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
5.000 0.000 MIPI_RX_Advance_Top/DPHY_RX_INST/HS_CLK
5.000 0.000 tCL FF 5 MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/OH
5.350 0.350 tNET FF 3 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CLKIN
5.536 0.186 tINS FF 5 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CLKOUT
5.886 0.350 tNET FF 1 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_1/FCLK
5.851 -0.035 tUnc MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_1
5.830 -0.021 tSu 1 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_1
Path Statistics:
Clock Skew: 0.149
Setup Relationship: 5.000
Logic Level: 3
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 1.043, 40.882%; route: 1.125, 44.118%; tC2Q: 0.382, 15.000%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 3

Path Summary:
Slack 2.543
Data Arrival Time 3.287
Data Required Time 5.830
From u_ROM549x17/lp_dir_s0
To MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_2
Launch Clk U3_CLKDIV/CLKOUT.default_gen_clk[F]
Latch Clk MIPI_RX_Advance_Top/DPHY_RX_INST/HS_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 U3_CLKDIV/CLKOUT.default_gen_clk
0.362 0.362 tCL RR 30 U3_CLKDIV/CLKOUT
0.737 0.375 tNET RR 1 u_ROM549x17/lp_dir_s0/CLK
1.120 0.382 tC2Q RR 21 u_ROM549x17/lp_dir_s0/Q
1.495 0.375 tNET RR 4 MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_LANE2/OEN
2.177 0.683 tINS RR 1 MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_LANE2/OH
2.552 0.375 tNET RR 1 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/udel_dataini2/DI
2.912 0.360 tINS RR 1 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/udel_dataini2/DO
3.287 0.375 tNET RR 1 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_2/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
5.000 0.000 MIPI_RX_Advance_Top/DPHY_RX_INST/HS_CLK
5.000 0.000 tCL FF 5 MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/OH
5.350 0.350 tNET FF 3 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CLKIN
5.536 0.186 tINS FF 5 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CLKOUT
5.886 0.350 tNET FF 1 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_2/FCLK
5.851 -0.035 tUnc MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_2
5.830 -0.021 tSu 1 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_2
Path Statistics:
Clock Skew: 0.149
Setup Relationship: 5.000
Logic Level: 3
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 1.043, 40.882%; route: 1.125, 44.118%; tC2Q: 0.382, 15.000%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 4

Path Summary:
Slack 2.543
Data Arrival Time 3.287
Data Required Time 5.830
From u_ROM549x17/lp_dir_s0
To MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_3
Launch Clk U3_CLKDIV/CLKOUT.default_gen_clk[F]
Latch Clk MIPI_RX_Advance_Top/DPHY_RX_INST/HS_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 U3_CLKDIV/CLKOUT.default_gen_clk
0.362 0.362 tCL RR 30 U3_CLKDIV/CLKOUT
0.737 0.375 tNET RR 1 u_ROM549x17/lp_dir_s0/CLK
1.120 0.382 tC2Q RR 21 u_ROM549x17/lp_dir_s0/Q
1.495 0.375 tNET RR 4 MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_LANE3/OEN
2.177 0.683 tINS RR 1 MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_LANE3/OH
2.552 0.375 tNET RR 1 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/udel_dataini3/DI
2.912 0.360 tINS RR 1 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/udel_dataini3/DO
3.287 0.375 tNET RR 1 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_3/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
5.000 0.000 MIPI_RX_Advance_Top/DPHY_RX_INST/HS_CLK
5.000 0.000 tCL FF 5 MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/OH
5.350 0.350 tNET FF 3 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CLKIN
5.536 0.186 tINS FF 5 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CLKOUT
5.886 0.350 tNET FF 1 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_3/FCLK
5.851 -0.035 tUnc MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_3
5.830 -0.021 tSu 1 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_3
Path Statistics:
Clock Skew: 0.149
Setup Relationship: 5.000
Logic Level: 3
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 1.043, 40.882%; route: 1.125, 44.118%; tC2Q: 0.382, 15.000%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 5

Path Summary:
Slack 3.199
Data Arrival Time 1.969
Data Required Time 5.168
From MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0
To MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN
Launch Clk MIPI_RX_Advance_Top/DPHY_RX_INST/HS_CLK[F]
Latch Clk MIPI_RX_Advance_Top/DPHY_RX_INST/HS_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 MIPI_RX_Advance_Top/DPHY_RX_INST/HS_CLK
0.000 0.000 tCL RR 5 MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/OH
0.375 0.375 tNET RR 1 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0/CLK
0.757 0.382 tC2Q RR 2 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0/Q
1.132 0.375 tNET RR 1 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/LUT4_0/I2
1.594 0.461 tINS RR 1 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/LUT4_0/F
1.969 0.375 tNET RR 1 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CEN
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
5.000 0.000 MIPI_RX_Advance_Top/DPHY_RX_INST/HS_CLK
5.000 0.000 tCL FF 5 MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/OH
5.350 0.350 tNET FF 3 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CLKIN
5.168 -0.182 tSu 1 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN
Path Statistics:
Clock Skew: -0.025
Setup Relationship: 5.000
Logic Level: 2
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 0.461, 28.941%; route: 0.750, 47.059%; tC2Q: 0.382, 24.000%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%