Timing Messages

Report Title Timing Analysis Report
Design File E:\myWork\IP\releaseVerify\version\1.9.10.03\Gowin_MIPI_DPHY_Advance_RefDesign\MIPI_RefDesign_5a138_LVDS\MIPI_RefDesign\impl\gwsynthesis\MIPI_RefDesign.vg
Physical Constraints File E:\myWork\IP\releaseVerify\version\1.9.10.03\Gowin_MIPI_DPHY_Advance_RefDesign\MIPI_RefDesign_5a138_LVDS\MIPI_RefDesign\src\mipi.cst
Timing Constraint File E:\myWork\IP\releaseVerify\version\1.9.10.03\Gowin_MIPI_DPHY_Advance_RefDesign\MIPI_RefDesign_5a138_LVDS\MIPI_RefDesign\src\mipi.sdc
Tool Version V1.9.10.03 (64-bit)
Part Number GW5AST-LV138FPG676AES
Device GW5AST-138
Device Version B
Created Time Thu Oct 24 14:15:30 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model Slow 0.855V 0C ES
Hold Delay Model Fast 0.945V 85C ES
Numbers of Paths Analyzed 2046
Numbers of Endpoints Analyzed 3015
Numbers of Falling Endpoints 11
Numbers of Setup Violated Endpoints 0
Numbers of Hold Violated Endpoints 0

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Objects
1 U0_IB Base 10.000 100.000 0.000 5.000 MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/I
2 U3_CLKDIV Base 800.000 1.250 0.000 400.000 U3_CLKDIV/CLKOUT
3 PLL_0 Base 50.000 20.000 0.000 25.000 PLL_mipi_tx/CLKOUT0
4 PLL_1 Base 50.000 20.000 0.000 25.000 PLL_mipi_tx/CLKOUT1
5 HS_CLK Base 10.000 100.000 0.000 5.000 MIPI_RX_Advance_Top/DPHY_RX_INST/HS_CLK GND
6 tck_pad_i Base 50.000 20.000 0.000 25.000 tck_pad_i
7 sys_clk Base 20.000 50.000 0.000 10.000 clkx2x4
8 Inst3_CLKDIV_OUT Base 80.000 12.500 0.000 40.000 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 U3_CLKDIV 1.250(MHz) 325.570(MHz) 1 TOP
2 HS_CLK 100.000(MHz) 103.249(MHz) 2 TOP
3 tck_pad_i 20.000(MHz) 67.465(MHz) 5 TOP
4 Inst3_CLKDIV_OUT 12.500(MHz) 144.144(MHz) 4 TOP

No timing paths to get frequency of U0_IB!

No timing paths to get frequency of PLL_0!

No timing paths to get frequency of PLL_1!

No timing paths to get frequency of sys_clk!

Total Negative Slack Summary:

Clock Name Analysis Type Endpoints TNS Number of Endpoints
U0_IB Setup 0.000 0
U0_IB Hold 0.000 0
U3_CLKDIV Setup 0.000 0
U3_CLKDIV Hold 0.000 0
PLL_0 Setup 0.000 0
PLL_0 Hold 0.000 0
PLL_1 Setup 0.000 0
PLL_1 Hold 0.000 0
HS_CLK Setup 0.000 0
HS_CLK Hold 0.000 0
tck_pad_i Setup 0.000 0
tck_pad_i Hold 0.000 0
sys_clk Setup 0.000 0
sys_clk Hold 0.000 0
Inst3_CLKDIV_OUT Setup 0.000 0
Inst3_CLKDIV_OUT Hold 0.000 0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.157 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0/Q MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CEN HS_CLK:[R] HS_CLK:[F] 5.000 2.386 2.275
2 7.756 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0/Q MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0/CE HS_CLK:[R] HS_CLK:[R] 10.000 0.000 1.933
3 7.756 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0/Q MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/CE HS_CLK:[R] HS_CLK:[R] 10.000 0.000 1.933
4 7.756 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0/Q MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0/CE HS_CLK:[R] HS_CLK:[R] 10.000 0.000 1.933
5 7.756 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0/Q MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_2_s0/CE HS_CLK:[R] HS_CLK:[R] 10.000 0.000 1.933
6 9.068 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_2_s0/Q MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/D HS_CLK:[R] HS_CLK:[R] 10.000 0.000 0.869
7 9.109 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0/Q MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0/D HS_CLK:[R] HS_CLK:[R] 10.000 0.000 0.827
8 9.111 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/Q MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0/D HS_CLK:[R] HS_CLK:[R] 10.000 0.000 0.825
9 9.111 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0/Q MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_2_s0/D HS_CLK:[R] HS_CLK:[R] 10.000 0.000 0.825
10 4.832 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CALIB MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CALIB HS_CLK:[F] HS_CLK:[R] 5.000 -0.184 0.352
11 4.866 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES80/CALIB MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES80/CALIB HS_CLK:[F] HS_CLK:[R] 5.000 -0.184 0.319
12 4.866 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES81/CALIB MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES81/CALIB HS_CLK:[F] HS_CLK:[R] 5.000 -0.184 0.319
13 4.866 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES82/CALIB MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES82/CALIB HS_CLK:[F] HS_CLK:[R] 5.000 -0.184 0.319
14 4.866 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES83/CALIB MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES83/CALIB HS_CLK:[F] HS_CLK:[R] 5.000 -0.184 0.319
15 17.589 gw_gao_inst_0/u_icon_top/module_id_reg_3_s0/Q gw_gao_inst_0/u_la0_top/internal_reg_start_s1/CE tck_pad_i:[R] tck_pad_i:[F] 25.000 0.381 6.774
16 17.976 gw_gao_inst_0/u_icon_top/module_id_reg_3_s0/Q gw_gao_inst_0/u_la0_top/internal_reg_force_triger_s1/CE tck_pad_i:[R] tck_pad_i:[F] 25.000 0.373 6.395
17 18.857 gw_gao_inst_0/u_icon_top/module_id_reg_3_s0/Q gw_gao_inst_0/u_la0_top/internal_reg_force_triger_s1/D tck_pad_i:[R] tck_pad_i:[F] 25.000 0.373 5.761
18 18.979 gw_gao_inst_0/u_icon_top/module_id_reg_3_s0/Q gw_gao_inst_0/u_la0_top/internal_reg_start_s1/D tck_pad_i:[R] tck_pad_i:[F] 25.000 0.381 5.631
19 19.975 gw_gao_inst_0/u_la0_top/capture_windows_num_3_s0/Q gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0/D tck_pad_i:[R] tck_pad_i:[F] 25.000 0.370 4.646
20 20.408 gw_gao_inst_0/u_la0_top/internal_reg_start_s1/Q gw_gao_inst_0/u_la0_top/data_out_shift_reg_0_s1/D tck_pad_i:[F] tck_pad_i:[R] 25.000 -0.391 4.919
21 41.496 gw_gao_inst_0/u_la0_top/module_state_1_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CEB tck_pad_i:[R] tck_pad_i:[R] 50.000 0.027 8.386
22 42.339 gw_gao_inst_0/u_icon_top/module_id_reg_3_s0/Q gw_gao_inst_0/u_la0_top/address_counter_2_s0/CE tck_pad_i:[R] tck_pad_i:[R] 50.000 -0.005 7.355
23 42.339 gw_gao_inst_0/u_icon_top/module_id_reg_3_s0/Q gw_gao_inst_0/u_la0_top/address_counter_6_s0/CE tck_pad_i:[R] tck_pad_i:[R] 50.000 -0.005 7.355
24 42.339 gw_gao_inst_0/u_icon_top/module_id_reg_3_s0/Q gw_gao_inst_0/u_la0_top/address_counter_10_s0/CE tck_pad_i:[R] tck_pad_i:[R] 50.000 -0.005 7.355
25 42.769 gw_gao_inst_0/u_icon_top/module_id_reg_3_s0/Q gw_gao_inst_0/u_la0_top/address_counter_1_s0/CE tck_pad_i:[R] tck_pad_i:[R] 50.000 0.009 6.910

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.012 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES80/CALIB MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES80/CALIB HS_CLK:[R] HS_CLK:[R] 0.000 -0.159 0.171
2 0.012 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES81/CALIB MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES81/CALIB HS_CLK:[R] HS_CLK:[R] 0.000 -0.159 0.171
3 0.012 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES82/CALIB MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES82/CALIB HS_CLK:[R] HS_CLK:[R] 0.000 -0.159 0.171
4 0.012 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES83/CALIB MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES83/CALIB HS_CLK:[R] HS_CLK:[R] 0.000 -0.159 0.171
5 0.024 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CALIB MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CALIB HS_CLK:[R] HS_CLK:[R] 0.000 -0.159 0.183
6 0.275 gw_gao_inst_0/u_la0_top/word_count_3_s0/Q gw_gao_inst_0/u_la0_top/word_count_3_s0/D tck_pad_i:[R] tck_pad_i:[R] 0.000 0.000 0.300
7 0.275 gw_gao_inst_0/u_la0_top/word_count_4_s0/Q gw_gao_inst_0/u_la0_top/word_count_4_s0/D tck_pad_i:[R] tck_pad_i:[R] 0.000 0.000 0.300
8 0.275 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/D Inst3_CLKDIV_OUT:[R] Inst3_CLKDIV_OUT:[R] 0.000 0.000 0.300
9 0.275 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/D Inst3_CLKDIV_OUT:[R] Inst3_CLKDIV_OUT:[R] 0.000 0.000 0.300
10 0.275 gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/Q gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/D Inst3_CLKDIV_OUT:[R] Inst3_CLKDIV_OUT:[R] 0.000 0.000 0.300
11 0.275 gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/Q gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/D Inst3_CLKDIV_OUT:[R] Inst3_CLKDIV_OUT:[R] 0.000 0.000 0.300
12 0.275 gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/Q gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/D Inst3_CLKDIV_OUT:[R] Inst3_CLKDIV_OUT:[R] 0.000 0.000 0.300
13 0.275 gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/Q gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/D Inst3_CLKDIV_OUT:[R] Inst3_CLKDIV_OUT:[R] 0.000 0.000 0.300
14 0.275 gw_gao_inst_0/u_la0_top/capture_window_sel_10_s1/Q gw_gao_inst_0/u_la0_top/capture_window_sel_10_s1/D Inst3_CLKDIV_OUT:[R] Inst3_CLKDIV_OUT:[R] 0.000 0.000 0.300
15 0.278 gw_gao_inst_0/u_la0_top/bit_count_0_s1/Q gw_gao_inst_0/u_la0_top/bit_count_0_s1/D tck_pad_i:[R] tck_pad_i:[R] 0.000 0.000 0.303
16 0.278 gw_gao_inst_0/u_la0_top/word_count_13_s0/Q gw_gao_inst_0/u_la0_top/word_count_13_s0/D tck_pad_i:[R] tck_pad_i:[R] 0.000 0.000 0.303
17 0.278 gw_gao_inst_0/u_la0_top/address_counter_1_s0/Q gw_gao_inst_0/u_la0_top/address_counter_1_s0/D tck_pad_i:[R] tck_pad_i:[R] 0.000 0.000 0.303
18 0.278 gw_gao_inst_0/u_la0_top/address_counter_3_s0/Q gw_gao_inst_0/u_la0_top/address_counter_3_s0/D tck_pad_i:[R] tck_pad_i:[R] 0.000 0.000 0.303
19 0.278 gw_gao_inst_0/u_la0_top/address_counter_5_s0/Q gw_gao_inst_0/u_la0_top/address_counter_5_s0/D tck_pad_i:[R] tck_pad_i:[R] 0.000 0.000 0.303
20 0.278 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/D Inst3_CLKDIV_OUT:[R] Inst3_CLKDIV_OUT:[R] 0.000 0.000 0.303
21 0.278 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/D Inst3_CLKDIV_OUT:[R] Inst3_CLKDIV_OUT:[R] 0.000 0.000 0.303
22 0.278 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/D Inst3_CLKDIV_OUT:[R] Inst3_CLKDIV_OUT:[R] 0.000 0.000 0.303
23 0.278 gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/Q gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/D Inst3_CLKDIV_OUT:[R] Inst3_CLKDIV_OUT:[R] 0.000 0.000 0.303
24 0.278 MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/lane2_cnt_0_s1/Q MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/lane2_cnt_0_s1/D Inst3_CLKDIV_OUT:[R] Inst3_CLKDIV_OUT:[R] 0.000 0.000 0.303
25 0.281 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/D Inst3_CLKDIV_OUT:[R] Inst3_CLKDIV_OUT:[R] 0.000 0.000 0.306

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 38.419 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] 40.000 -0.320 1.554
2 38.419 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] 40.000 -0.320 1.554
3 38.428 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] 40.000 -0.330 1.554
4 38.451 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] 40.000 -0.321 1.522
5 38.483 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] 40.000 -0.320 1.490
6 38.483 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] 40.000 -0.320 1.490
7 38.483 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] 40.000 -0.320 1.490
8 38.573 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] 40.000 -0.323 1.402
9 38.573 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] 40.000 -0.323 1.402
10 38.623 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] 40.000 -0.335 1.364
11 38.623 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] 40.000 -0.335 1.364
12 38.623 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] 40.000 -0.335 1.364
13 38.628 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] 40.000 -0.311 1.335
14 38.628 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] 40.000 -0.311 1.335
15 38.656 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/triger_s0/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] 40.000 -0.316 1.313
16 38.656 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] 40.000 -0.316 1.313
17 38.658 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] 40.000 -0.318 1.313
18 38.658 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] 40.000 -0.318 1.313
19 38.658 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] 40.000 -0.318 1.313
20 38.658 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] 40.000 -0.318 1.313
21 38.683 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] 40.000 -0.311 1.280
22 38.683 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] 40.000 -0.311 1.280
23 38.683 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] 40.000 -0.311 1.280
24 38.708 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] 40.000 -0.318 1.262
25 38.778 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] 40.000 -0.313 1.188

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 40.572 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] -40.000 0.271 0.248
2 40.572 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] -40.000 0.271 0.248
3 40.596 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_10_s1/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] -40.000 0.271 0.272
4 40.596 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/start_reg_s0/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] -40.000 0.271 0.272
5 40.673 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] -40.000 0.274 0.346
6 40.673 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] -40.000 0.274 0.346
7 40.673 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] -40.000 0.274 0.346
8 40.678 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] -40.000 0.265 0.360
9 40.686 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] -40.000 0.269 0.364
10 40.687 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] -40.000 0.270 0.364
11 40.687 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_10_s1/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] -40.000 0.270 0.364
12 40.692 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] -40.000 0.273 0.366
13 40.692 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] -40.000 0.273 0.366
14 40.692 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] -40.000 0.273 0.366
15 40.692 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] -40.000 0.273 0.366
16 40.692 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] -40.000 0.273 0.366
17 40.699 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] -40.000 0.274 0.372
18 40.699 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] -40.000 0.274 0.372
19 40.703 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] -40.000 0.278 0.372
20 40.703 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] -40.000 0.278 0.372
21 40.703 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] -40.000 0.278 0.372
22 40.770 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] -40.000 0.271 0.446
23 40.770 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] -40.000 0.271 0.446
24 40.770 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_0_s0/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] -40.000 0.271 0.446
25 40.770 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] -40.000 0.271 0.446

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number Slack Actual Width Required Width Type Clock Objects
1 3.402 3.652 0.250 High Pulse Width HS_CLK MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_2_s0
2 3.402 3.652 0.250 High Pulse Width HS_CLK MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0
3 3.402 3.652 0.250 High Pulse Width HS_CLK MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0
4 3.402 3.652 0.250 High Pulse Width HS_CLK MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0
5 3.523 3.773 0.250 Low Pulse Width HS_CLK MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_2_s0
6 3.523 3.773 0.250 Low Pulse Width HS_CLK MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0
7 3.523 3.773 0.250 Low Pulse Width HS_CLK MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0
8 3.523 3.773 0.250 Low Pulse Width HS_CLK MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0
9 19.523 20.523 1.000 Low Pulse Width tck_pad_i gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
10 19.523 20.523 1.000 Low Pulse Width tck_pad_i gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 0.157
Data Arrival Time 4.661
Data Required Time 4.818
From MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0
To MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN
Launch Clk HS_CLK:[R]
Latch Clk HS_CLK:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 HS_CLK
0.000 0.000 tCL RR 5 IOB120 MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
2.386 2.386 tNET RR 1 R93C119[2][B] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0/CLK
2.768 0.382 tC2Q RR 2 R93C119[2][B] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0/Q
2.922 0.154 tNET RR 1 R93C119[3][A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/LUT4_0/I2
3.496 0.574 tINS RR 1 R93C119[3][A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/LUT4_0/F
4.661 1.165 tNET RR 1 - MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CEN

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 HS_CLK
5.000 0.000 tCL FF 5 IOB120 MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
5.000 0.000 tNET FF 3 - MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CLKIN
4.818 -0.182 tSu 1 - MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN

Path Statistics:

Clock Skew -2.386
Setup Relationship 5.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.386, 100.000%
Arrival Data Path Delay cell: 0.574, 25.220%; route: 1.319, 57.967%; tC2Q: 0.382, 16.813%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path2

Path Summary:

Slack 7.756
Data Arrival Time 4.318
Data Required Time 12.074
From MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0
To MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0
Launch Clk HS_CLK:[R]
Latch Clk HS_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 HS_CLK
0.000 0.000 tCL RR 5 IOB120 MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
2.386 2.386 tNET RR 1 R93C119[2][A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0/CLK
2.768 0.382 tC2Q RR 3 R93C119[2][A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0/Q
2.924 0.156 tNET RR 1 R93C119[0][B] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/LUT4_1/I3
3.492 0.567 tINS RR 4 R93C119[0][B] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/LUT4_1/F
4.318 0.826 tNET RR 1 R93C119[2][A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 HS_CLK
10.000 0.000 tCL RR 5 IOB120 MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
12.386 2.386 tNET RR 1 R93C119[2][A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0/CLK
12.074 -0.311 tSu 1 R93C119[2][A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.386, 100.000%
Arrival Data Path Delay cell: 0.567, 29.366%; route: 0.983, 50.841%; tC2Q: 0.382, 19.793%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.386, 100.000%

Path3

Path Summary:

Slack 7.756
Data Arrival Time 4.318
Data Required Time 12.074
From MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0
To MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0
Launch Clk HS_CLK:[R]
Latch Clk HS_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 HS_CLK
0.000 0.000 tCL RR 5 IOB120 MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
2.386 2.386 tNET RR 1 R93C119[2][A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0/CLK
2.768 0.382 tC2Q RR 3 R93C119[2][A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0/Q
2.924 0.156 tNET RR 1 R93C119[0][B] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/LUT4_1/I3
3.492 0.567 tINS RR 4 R93C119[0][B] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/LUT4_1/F
4.318 0.826 tNET RR 1 R93C119[1][B] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 HS_CLK
10.000 0.000 tCL RR 5 IOB120 MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
12.386 2.386 tNET RR 1 R93C119[1][B] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/CLK
12.074 -0.311 tSu 1 R93C119[1][B] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.386, 100.000%
Arrival Data Path Delay cell: 0.567, 29.366%; route: 0.983, 50.841%; tC2Q: 0.382, 19.793%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.386, 100.000%

Path4

Path Summary:

Slack 7.756
Data Arrival Time 4.318
Data Required Time 12.074
From MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0
To MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0
Launch Clk HS_CLK:[R]
Latch Clk HS_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 HS_CLK
0.000 0.000 tCL RR 5 IOB120 MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
2.386 2.386 tNET RR 1 R93C119[2][A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0/CLK
2.768 0.382 tC2Q RR 3 R93C119[2][A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0/Q
2.924 0.156 tNET RR 1 R93C119[0][B] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/LUT4_1/I3
3.492 0.567 tINS RR 4 R93C119[0][B] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/LUT4_1/F
4.318 0.826 tNET RR 1 R93C119[2][B] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 HS_CLK
10.000 0.000 tCL RR 5 IOB120 MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
12.386 2.386 tNET RR 1 R93C119[2][B] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0/CLK
12.074 -0.311 tSu 1 R93C119[2][B] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.386, 100.000%
Arrival Data Path Delay cell: 0.567, 29.366%; route: 0.983, 50.841%; tC2Q: 0.382, 19.793%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.386, 100.000%

Path5

Path Summary:

Slack 7.756
Data Arrival Time 4.318
Data Required Time 12.074
From MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0
To MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_2_s0
Launch Clk HS_CLK:[R]
Latch Clk HS_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 HS_CLK
0.000 0.000 tCL RR 5 IOB120 MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
2.386 2.386 tNET RR 1 R93C119[2][A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0/CLK
2.768 0.382 tC2Q RR 3 R93C119[2][A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0/Q
2.924 0.156 tNET RR 1 R93C119[0][B] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/LUT4_1/I3
3.492 0.567 tINS RR 4 R93C119[0][B] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/LUT4_1/F
4.318 0.826 tNET RR 1 R93C119[1][A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_2_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 HS_CLK
10.000 0.000 tCL RR 5 IOB120 MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
12.386 2.386 tNET RR 1 R93C119[1][A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_2_s0/CLK
12.074 -0.311 tSu 1 R93C119[1][A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_2_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.386, 100.000%
Arrival Data Path Delay cell: 0.567, 29.366%; route: 0.983, 50.841%; tC2Q: 0.382, 19.793%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.386, 100.000%

Path6

Path Summary:

Slack 9.068
Data Arrival Time 3.254
Data Required Time 12.322
From MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_2_s0
To MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0
Launch Clk HS_CLK:[R]
Latch Clk HS_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 HS_CLK
0.000 0.000 tCL RR 5 IOB120 MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
2.386 2.386 tNET RR 1 R93C119[1][A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_2_s0/CLK
2.768 0.382 tC2Q RR 1 R93C119[1][A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_2_s0/Q
3.254 0.486 tNET RR 1 R93C119[1][B] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 HS_CLK
10.000 0.000 tCL RR 5 IOB120 MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
12.386 2.386 tNET RR 1 R93C119[1][B] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/CLK
12.322 -0.064 tSu 1 R93C119[1][B] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.386, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.486, 55.971%; tC2Q: 0.382, 44.029%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.386, 100.000%

Path7

Path Summary:

Slack 9.109
Data Arrival Time 3.213
Data Required Time 12.322
From MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0
To MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0
Launch Clk HS_CLK:[R]
Latch Clk HS_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 HS_CLK
0.000 0.000 tCL RR 5 IOB120 MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
2.386 2.386 tNET RR 1 R93C119[2][A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0/CLK
2.768 0.382 tC2Q RR 3 R93C119[2][A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0/Q
3.213 0.445 tNET RR 1 R93C119[2][B] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 HS_CLK
10.000 0.000 tCL RR 5 IOB120 MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
12.386 2.386 tNET RR 1 R93C119[2][B] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0/CLK
12.322 -0.064 tSu 1 R93C119[2][B] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.386, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.445, 53.776%; tC2Q: 0.382, 46.224%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.386, 100.000%

Path8

Path Summary:

Slack 9.111
Data Arrival Time 3.211
Data Required Time 12.322
From MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0
To MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0
Launch Clk HS_CLK:[R]
Latch Clk HS_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 HS_CLK
0.000 0.000 tCL RR 5 IOB120 MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
2.386 2.386 tNET RR 1 R93C119[1][B] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/CLK
2.768 0.382 tC2Q RR 2 R93C119[1][B] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/Q
3.211 0.442 tNET RR 1 R93C119[2][A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 HS_CLK
10.000 0.000 tCL RR 5 IOB120 MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
12.386 2.386 tNET RR 1 R93C119[2][A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0/CLK
12.322 -0.064 tSu 1 R93C119[2][A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.386, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.442, 53.636%; tC2Q: 0.382, 46.364%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.386, 100.000%

Path9

Path Summary:

Slack 9.111
Data Arrival Time 3.211
Data Required Time 12.322
From MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0
To MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_2_s0
Launch Clk HS_CLK:[R]
Latch Clk HS_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 HS_CLK
0.000 0.000 tCL RR 5 IOB120 MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
2.386 2.386 tNET RR 1 R93C119[2][B] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0/CLK
2.768 0.382 tC2Q RR 2 R93C119[2][B] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0/Q
3.211 0.442 tNET RR 1 R93C119[1][A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 HS_CLK
10.000 0.000 tCL RR 5 IOB120 MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
12.386 2.386 tNET RR 1 R93C119[1][A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_2_s0/CLK
12.322 -0.064 tSu 1 R93C119[1][A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_2_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.386, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.442, 53.636%; tC2Q: 0.382, 46.364%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.386, 100.000%

Path10

Path Summary:

Slack 4.832
Data Arrival Time 5.352
Data Required Time 10.184
From MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV
To MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV
Launch Clk HS_CLK:[F]
Latch Clk HS_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 HS_CLK
5.000 0.000 tCL FF 548 - GND_cZ/G
5.352 0.352 tNET FF 1 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CALIB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 HS_CLK
10.000 0.000 tCL RR 5 IOB120 MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
10.000 0.000 tNET RR 3 - MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CLKIN
10.182 0.182 tINS RR 5 - MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CLKOUT
10.184 0.003 tNET RR 5 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/HCLKIN
10.184 0.000 tSu 1 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV

Path Statistics:

Clock Skew 0.184
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.352, 100.000%
Required Clock Path Delay cell: 0.182, 98.645%; route: 0.003, 1.355%

Path11

Path Summary:

Slack 4.866
Data Arrival Time 5.319
Data Required Time 10.184
From MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES80
To MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES80
Launch Clk HS_CLK:[F]
Latch Clk HS_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 HS_CLK
5.000 0.000 tCL FF 548 - GND_cZ/G
5.319 0.319 tNET FF 1 IOB112[A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES80/CALIB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 HS_CLK
10.000 0.000 tCL RR 5 IOB120 MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
10.000 0.000 tNET RR 3 - MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CLKIN
10.182 0.182 tINS RR 5 - MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CLKOUT
10.184 0.003 tNET RR 1 IOB112[A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES80/FCLK
10.184 0.000 tSu 1 IOB112[A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES80

Path Statistics:

Clock Skew 0.184
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.319, 100.000%
Required Clock Path Delay cell: 0.182, 98.645%; route: 0.003, 1.355%

Path12

Path Summary:

Slack 4.866
Data Arrival Time 5.319
Data Required Time 10.184
From MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES81
To MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES81
Launch Clk HS_CLK:[F]
Latch Clk HS_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 HS_CLK
5.000 0.000 tCL FF 548 - GND_cZ/G
5.319 0.319 tNET FF 1 IOB144[A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES81/CALIB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 HS_CLK
10.000 0.000 tCL RR 5 IOB120 MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
10.000 0.000 tNET RR 3 - MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CLKIN
10.182 0.182 tINS RR 5 - MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CLKOUT
10.184 0.003 tNET RR 1 IOB144[A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES81/FCLK
10.184 0.000 tSu 1 IOB144[A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES81

Path Statistics:

Clock Skew 0.184
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.319, 100.000%
Required Clock Path Delay cell: 0.182, 98.645%; route: 0.003, 1.355%

Path13

Path Summary:

Slack 4.866
Data Arrival Time 5.319
Data Required Time 10.184
From MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES82
To MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES82
Launch Clk HS_CLK:[F]
Latch Clk HS_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 HS_CLK
5.000 0.000 tCL FF 548 - GND_cZ/G
5.319 0.319 tNET FF 1 IOB133[A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES82/CALIB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 HS_CLK
10.000 0.000 tCL RR 5 IOB120 MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
10.000 0.000 tNET RR 3 - MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CLKIN
10.182 0.182 tINS RR 5 - MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CLKOUT
10.184 0.003 tNET RR 1 IOB133[A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES82/FCLK
10.184 0.000 tSu 1 IOB133[A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES82

Path Statistics:

Clock Skew 0.184
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.319, 100.000%
Required Clock Path Delay cell: 0.182, 98.645%; route: 0.003, 1.355%

Path14

Path Summary:

Slack 4.866
Data Arrival Time 5.319
Data Required Time 10.184
From MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES83
To MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES83
Launch Clk HS_CLK:[F]
Latch Clk HS_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 HS_CLK
5.000 0.000 tCL FF 548 - GND_cZ/G
5.319 0.319 tNET FF 1 IOB110[A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES83/CALIB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 HS_CLK
10.000 0.000 tCL RR 5 IOB120 MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
10.000 0.000 tNET RR 3 - MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CLKIN
10.182 0.182 tINS RR 5 - MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CLKOUT
10.184 0.003 tNET RR 1 IOB110[A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES83/FCLK
10.184 0.000 tSu 1 IOB110[A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES83

Path Statistics:

Clock Skew 0.184
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.319, 100.000%
Required Clock Path Delay cell: 0.182, 98.645%; route: 0.003, 1.355%

Path15

Path Summary:

Slack 17.589
Data Arrival Time 16.099
Data Required Time 33.688
From gw_gao_inst_0/u_icon_top/module_id_reg_3_s0
To gw_gao_inst_0/u_la0_top/internal_reg_start_s1
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOB173[A] gw_gao_inst_0/tck_ibuf/I
0.683 0.683 tINS RR 1 IOB173[A] gw_gao_inst_0/tck_ibuf/O
0.683 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365 0.683 tINS RR 252 - gw_gao_inst_0/u_gw_jtag/tck_o
9.326 7.961 tNET RR 1 R97C170[0][A] gw_gao_inst_0/u_icon_top/module_id_reg_3_s0/CLK
9.708 0.382 tC2Q RR 2 R97C170[0][A] gw_gao_inst_0/u_icon_top/module_id_reg_3_s0/Q
10.092 0.384 tNET RR 1 R96C169[0][B] gw_gao_inst_0/u_la0_top/n20_s1/I2
10.599 0.507 tINS RR 7 R96C169[0][B] gw_gao_inst_0/u_la0_top/n20_s1/F
11.408 0.809 tNET RR 1 R95C165[1][A] gw_gao_inst_0/u_la0_top/regsel_ld_en_s7/I2
11.916 0.507 tINS RR 26 R95C165[1][A] gw_gao_inst_0/u_la0_top/regsel_ld_en_s7/F
13.629 1.714 tNET RR 1 R97C143[3][B] gw_gao_inst_0/u_la0_top/internal_reg_start_s4/I3
14.203 0.574 tINS RR 3 R97C143[3][B] gw_gao_inst_0/u_la0_top/internal_reg_start_s4/F
15.216 1.013 tNET RR 1 R94C141[3][B] gw_gao_inst_0/u_la0_top/internal_reg_start_s3/I2
15.507 0.291 tINS RR 2 R94C141[3][B] gw_gao_inst_0/u_la0_top/internal_reg_start_s3/F
16.099 0.593 tNET RR 1 R97C142[0][B] gw_gao_inst_0/u_la0_top/internal_reg_start_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
25.000 25.000 active clock edge time
25.000 0.000 tck_pad_i
25.000 0.000 tCL FF 1 IOB173[A] gw_gao_inst_0/tck_ibuf/I
25.688 0.688 tINS FF 1 IOB173[A] gw_gao_inst_0/tck_ibuf/O
25.688 0.000 tNET FF 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
26.375 0.688 tINS FF 252 - gw_gao_inst_0/u_gw_jtag/tck_o
33.944 7.569 tNET FF 1 R97C142[0][B] gw_gao_inst_0/u_la0_top/internal_reg_start_s1/CLK
33.688 -0.256 tSu 1 R97C142[0][B] gw_gao_inst_0/u_la0_top/internal_reg_start_s1

Path Statistics:

Clock Skew -0.381
Setup Relationship 25.000
Logic Level 5
Arrival Clock Path Delay cell: 1.365, 14.637%; route: 7.961, 85.363%
Arrival Data Path Delay cell: 1.880, 27.754%; route: 4.511, 66.599%; tC2Q: 0.382, 5.647%
Required Clock Path Delay cell: 1.375, 15.373%; route: 7.569, 84.627%

Path16

Path Summary:

Slack 17.976
Data Arrival Time 15.721
Data Required Time 33.697
From gw_gao_inst_0/u_icon_top/module_id_reg_3_s0
To gw_gao_inst_0/u_la0_top/internal_reg_force_triger_s1
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOB173[A] gw_gao_inst_0/tck_ibuf/I
0.683 0.683 tINS RR 1 IOB173[A] gw_gao_inst_0/tck_ibuf/O
0.683 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365 0.683 tINS RR 252 - gw_gao_inst_0/u_gw_jtag/tck_o
9.326 7.961 tNET RR 1 R97C170[0][A] gw_gao_inst_0/u_icon_top/module_id_reg_3_s0/CLK
9.708 0.382 tC2Q RR 2 R97C170[0][A] gw_gao_inst_0/u_icon_top/module_id_reg_3_s0/Q
10.092 0.384 tNET RR 1 R96C169[0][B] gw_gao_inst_0/u_la0_top/n20_s1/I2
10.599 0.507 tINS RR 7 R96C169[0][B] gw_gao_inst_0/u_la0_top/n20_s1/F
11.408 0.809 tNET RR 1 R95C165[1][A] gw_gao_inst_0/u_la0_top/regsel_ld_en_s7/I2
11.916 0.507 tINS RR 26 R95C165[1][A] gw_gao_inst_0/u_la0_top/regsel_ld_en_s7/F
13.629 1.714 tNET RR 1 R97C143[3][B] gw_gao_inst_0/u_la0_top/internal_reg_start_s4/I3
14.203 0.574 tINS RR 3 R97C143[3][B] gw_gao_inst_0/u_la0_top/internal_reg_start_s4/F
15.216 1.013 tNET RR 1 R94C141[3][B] gw_gao_inst_0/u_la0_top/internal_reg_start_s3/I2
15.507 0.291 tINS RR 2 R94C141[3][B] gw_gao_inst_0/u_la0_top/internal_reg_start_s3/F
15.721 0.214 tNET RR 1 R94C142[2][B] gw_gao_inst_0/u_la0_top/internal_reg_force_triger_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
25.000 25.000 active clock edge time
25.000 0.000 tck_pad_i
25.000 0.000 tCL FF 1 IOB173[A] gw_gao_inst_0/tck_ibuf/I
25.688 0.688 tINS FF 1 IOB173[A] gw_gao_inst_0/tck_ibuf/O
25.688 0.000 tNET FF 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
26.375 0.688 tINS FF 252 - gw_gao_inst_0/u_gw_jtag/tck_o
33.953 7.578 tNET FF 1 R94C142[2][B] gw_gao_inst_0/u_la0_top/internal_reg_force_triger_s1/CLK
33.697 -0.256 tSu 1 R94C142[2][B] gw_gao_inst_0/u_la0_top/internal_reg_force_triger_s1

Path Statistics:

Clock Skew -0.373
Setup Relationship 25.000
Logic Level 5
Arrival Clock Path Delay cell: 1.365, 14.637%; route: 7.961, 85.363%
Arrival Data Path Delay cell: 1.880, 29.398%; route: 4.133, 64.621%; tC2Q: 0.382, 5.981%
Required Clock Path Delay cell: 1.375, 15.358%; route: 7.578, 84.642%

Path17

Path Summary:

Slack 18.857
Data Arrival Time 15.087
Data Required Time 33.944
From gw_gao_inst_0/u_icon_top/module_id_reg_3_s0
To gw_gao_inst_0/u_la0_top/internal_reg_force_triger_s1
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOB173[A] gw_gao_inst_0/tck_ibuf/I
0.683 0.683 tINS RR 1 IOB173[A] gw_gao_inst_0/tck_ibuf/O
0.683 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365 0.683 tINS RR 252 - gw_gao_inst_0/u_gw_jtag/tck_o
9.326 7.961 tNET RR 1 R97C170[0][A] gw_gao_inst_0/u_icon_top/module_id_reg_3_s0/CLK
9.708 0.382 tC2Q RR 2 R97C170[0][A] gw_gao_inst_0/u_icon_top/module_id_reg_3_s0/Q
10.092 0.384 tNET RR 1 R96C169[0][B] gw_gao_inst_0/u_la0_top/n20_s1/I2
10.599 0.507 tINS RR 7 R96C169[0][B] gw_gao_inst_0/u_la0_top/n20_s1/F
11.408 0.809 tNET RR 1 R95C165[1][A] gw_gao_inst_0/u_la0_top/regsel_ld_en_s7/I2
11.916 0.507 tINS RR 26 R95C165[1][A] gw_gao_inst_0/u_la0_top/regsel_ld_en_s7/F
13.629 1.714 tNET RR 1 R97C143[3][B] gw_gao_inst_0/u_la0_top/internal_reg_start_s4/I3
14.203 0.574 tINS RR 3 R97C143[3][B] gw_gao_inst_0/u_la0_top/internal_reg_start_s4/F
14.798 0.595 tNET RR 1 R94C142[2][B] gw_gao_inst_0/u_la0_top/n668_s1/I1
15.087 0.289 tINS RR 1 R94C142[2][B] gw_gao_inst_0/u_la0_top/n668_s1/F
15.087 0.000 tNET RR 1 R94C142[2][B] gw_gao_inst_0/u_la0_top/internal_reg_force_triger_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
25.000 25.000 active clock edge time
25.000 0.000 tck_pad_i
25.000 0.000 tCL FF 1 IOB173[A] gw_gao_inst_0/tck_ibuf/I
25.688 0.688 tINS FF 1 IOB173[A] gw_gao_inst_0/tck_ibuf/O
25.688 0.000 tNET FF 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
26.375 0.688 tINS FF 252 - gw_gao_inst_0/u_gw_jtag/tck_o
33.953 7.578 tNET FF 1 R94C142[2][B] gw_gao_inst_0/u_la0_top/internal_reg_force_triger_s1/CLK
33.944 -0.009 tSu 1 R94C142[2][B] gw_gao_inst_0/u_la0_top/internal_reg_force_triger_s1

Path Statistics:

Clock Skew -0.373
Setup Relationship 25.000
Logic Level 5
Arrival Clock Path Delay cell: 1.365, 14.637%; route: 7.961, 85.363%
Arrival Data Path Delay cell: 1.878, 32.588%; route: 3.501, 60.772%; tC2Q: 0.382, 6.639%
Required Clock Path Delay cell: 1.375, 15.358%; route: 7.578, 84.642%

Path18

Path Summary:

Slack 18.979
Data Arrival Time 14.957
Data Required Time 33.936
From gw_gao_inst_0/u_icon_top/module_id_reg_3_s0
To gw_gao_inst_0/u_la0_top/internal_reg_start_s1
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOB173[A] gw_gao_inst_0/tck_ibuf/I
0.683 0.683 tINS RR 1 IOB173[A] gw_gao_inst_0/tck_ibuf/O
0.683 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365 0.683 tINS RR 252 - gw_gao_inst_0/u_gw_jtag/tck_o
9.326 7.961 tNET RR 1 R97C170[0][A] gw_gao_inst_0/u_icon_top/module_id_reg_3_s0/CLK
9.708 0.382 tC2Q RR 2 R97C170[0][A] gw_gao_inst_0/u_icon_top/module_id_reg_3_s0/Q
10.092 0.384 tNET RR 1 R96C169[0][B] gw_gao_inst_0/u_la0_top/n20_s1/I2
10.599 0.507 tINS RR 7 R96C169[0][B] gw_gao_inst_0/u_la0_top/n20_s1/F
11.408 0.809 tNET RR 1 R95C165[1][A] gw_gao_inst_0/u_la0_top/regsel_ld_en_s7/I2
11.916 0.507 tINS RR 26 R95C165[1][A] gw_gao_inst_0/u_la0_top/regsel_ld_en_s7/F
13.629 1.714 tNET RR 1 R97C143[3][B] gw_gao_inst_0/u_la0_top/internal_reg_start_s4/I3
14.203 0.574 tINS RR 3 R97C143[3][B] gw_gao_inst_0/u_la0_top/internal_reg_start_s4/F
14.378 0.175 tNET RR 1 R97C142[0][B] gw_gao_inst_0/u_la0_top/n663_s1/I1
14.957 0.579 tINS RR 1 R97C142[0][B] gw_gao_inst_0/u_la0_top/n663_s1/F
14.957 0.000 tNET RR 1 R97C142[0][B] gw_gao_inst_0/u_la0_top/internal_reg_start_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
25.000 25.000 active clock edge time
25.000 0.000 tck_pad_i
25.000 0.000 tCL FF 1 IOB173[A] gw_gao_inst_0/tck_ibuf/I
25.688 0.688 tINS FF 1 IOB173[A] gw_gao_inst_0/tck_ibuf/O
25.688 0.000 tNET FF 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
26.375 0.688 tINS FF 252 - gw_gao_inst_0/u_gw_jtag/tck_o
33.944 7.569 tNET FF 1 R97C142[0][B] gw_gao_inst_0/u_la0_top/internal_reg_start_s1/CLK
33.936 -0.009 tSu 1 R97C142[0][B] gw_gao_inst_0/u_la0_top/internal_reg_start_s1

Path Statistics:

Clock Skew -0.381
Setup Relationship 25.000
Logic Level 5
Arrival Clock Path Delay cell: 1.365, 14.637%; route: 7.961, 85.363%
Arrival Data Path Delay cell: 2.168, 38.491%; route: 3.081, 54.717%; tC2Q: 0.382, 6.792%
Required Clock Path Delay cell: 1.375, 15.373%; route: 7.569, 84.627%

Path19

Path Summary:

Slack 19.975
Data Arrival Time 13.972
Data Required Time 33.947
From gw_gao_inst_0/u_la0_top/capture_windows_num_3_s0
To gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOB173[A] gw_gao_inst_0/tck_ibuf/I
0.683 0.683 tINS RR 1 IOB173[A] gw_gao_inst_0/tck_ibuf/O
0.683 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365 0.683 tINS RR 252 - gw_gao_inst_0/u_gw_jtag/tck_o
9.326 7.961 tNET RR 1 R97C148[2][A] gw_gao_inst_0/u_la0_top/capture_windows_num_3_s0/CLK
9.708 0.382 tC2Q RR 6 R97C148[2][A] gw_gao_inst_0/u_la0_top/capture_windows_num_3_s0/Q
10.726 1.018 tNET RR 2 R97C145[1][B] gw_gao_inst_0/u_la0_top/n2112_s25/I0
11.321 0.595 tINS RF 1 R97C145[1][B] gw_gao_inst_0/u_la0_top/n2112_s25/COUT
11.321 0.000 tNET FF 2 R97C145[2][A] gw_gao_inst_0/u_la0_top/n2112_s26/CIN
11.371 0.050 tINS FR 1 R97C145[2][A] gw_gao_inst_0/u_la0_top/n2112_s26/COUT
11.371 0.000 tNET RR 2 R97C145[2][B] gw_gao_inst_0/u_la0_top/n2112_s27/CIN
11.421 0.050 tINS RR 1 R97C145[2][B] gw_gao_inst_0/u_la0_top/n2112_s27/COUT
11.421 0.000 tNET RR 2 R97C146[0][A] gw_gao_inst_0/u_la0_top/n2112_s28/CIN
11.471 0.050 tINS RR 1 R97C146[0][A] gw_gao_inst_0/u_la0_top/n2112_s28/COUT
11.471 0.000 tNET RR 2 R97C146[0][B] gw_gao_inst_0/u_la0_top/n2112_s29/CIN
11.521 0.050 tINS RR 1 R97C146[0][B] gw_gao_inst_0/u_la0_top/n2112_s29/COUT
11.521 0.000 tNET RR 2 R97C146[1][A] gw_gao_inst_0/u_la0_top/n2112_s30/CIN
11.571 0.050 tINS RR 1 R97C146[1][A] gw_gao_inst_0/u_la0_top/n2112_s30/COUT
11.571 0.000 tNET RR 2 R97C146[1][B] gw_gao_inst_0/u_la0_top/n2112_s31/CIN
11.621 0.050 tINS RR 2 R97C146[1][B] gw_gao_inst_0/u_la0_top/n2112_s31/COUT
12.794 1.174 tNET RR 1 R94C141[1][A] gw_gao_inst_0/u_la0_top/n2176_s1/I1
13.302 0.507 tINS RR 1 R94C141[1][A] gw_gao_inst_0/u_la0_top/n2176_s1/F
13.972 0.670 tNET RR 1 R93C140[0][B] gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
25.000 25.000 active clock edge time
25.000 0.000 tck_pad_i
25.000 0.000 tCL FF 1 IOB173[A] gw_gao_inst_0/tck_ibuf/I
25.688 0.688 tINS FF 1 IOB173[A] gw_gao_inst_0/tck_ibuf/O
25.688 0.000 tNET FF 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
26.375 0.688 tINS FF 252 - gw_gao_inst_0/u_gw_jtag/tck_o
33.956 7.581 tNET FF 1 R93C140[0][B] gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0/CLK
33.947 -0.009 tSu 1 R93C140[0][B] gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0

Path Statistics:

Clock Skew -0.370
Setup Relationship 25.000
Logic Level 4
Arrival Clock Path Delay cell: 1.365, 14.637%; route: 7.961, 85.363%
Arrival Data Path Delay cell: 1.403, 30.186%; route: 2.861, 61.582%; tC2Q: 0.382, 8.232%
Required Clock Path Delay cell: 1.375, 15.353%; route: 7.581, 84.647%

Path20

Path Summary:

Slack 20.408
Data Arrival Time 38.863
Data Required Time 59.271
From gw_gao_inst_0/u_la0_top/internal_reg_start_s1
To gw_gao_inst_0/u_la0_top/data_out_shift_reg_0_s1
Launch Clk tck_pad_i:[F]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
25.000 25.000 active clock edge time
25.000 0.000 tck_pad_i
25.000 0.000 tCL FF 1 IOB173[A] gw_gao_inst_0/tck_ibuf/I
25.688 0.688 tINS FF 1 IOB173[A] gw_gao_inst_0/tck_ibuf/O
25.688 0.000 tNET FF 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
26.375 0.688 tINS FF 252 - gw_gao_inst_0/u_gw_jtag/tck_o
33.944 7.569 tNET FF 1 R97C142[0][B] gw_gao_inst_0/u_la0_top/internal_reg_start_s1/CLK
34.387 0.442 tC2Q FF 2 R97C142[0][B] gw_gao_inst_0/u_la0_top/internal_reg_start_s1/Q
35.268 0.881 tNET FF 1 R96C158[0][A] gw_gao_inst_0/u_la0_top/n1033_s13/I0
35.847 0.579 tINS FR 1 R96C158[0][A] gw_gao_inst_0/u_la0_top/n1033_s13/F
36.019 0.172 tNET RR 1 R96C159[3][A] gw_gao_inst_0/u_la0_top/n1033_s7/I0
36.567 0.548 tINS RR 1 R96C159[3][A] gw_gao_inst_0/u_la0_top/n1033_s7/F
36.739 0.172 tNET RR 1 R95C159[1][B] gw_gao_inst_0/u_la0_top/n1033_s3/I2
37.307 0.567 tINS RR 1 R95C159[1][B] gw_gao_inst_0/u_la0_top/n1033_s3/F
37.479 0.172 tNET RR 1 R95C160[2][A] gw_gao_inst_0/u_la0_top/n1033_s2/I0
37.987 0.507 tINS RR 1 R95C160[2][A] gw_gao_inst_0/u_la0_top/n1033_s2/F
38.407 0.420 tNET RR 1 R97C161[3][A] gw_gao_inst_0/u_la0_top/n1033_s0/I1
38.863 0.456 tINS RR 1 R97C161[3][A] gw_gao_inst_0/u_la0_top/n1033_s0/F
38.863 0.000 tNET RR 1 R97C161[3][A] gw_gao_inst_0/u_la0_top/data_out_shift_reg_0_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
50.000 50.000 active clock edge time
50.000 0.000 tck_pad_i
50.000 0.000 tCL RR 1 IOB173[A] gw_gao_inst_0/tck_ibuf/I
50.682 0.683 tINS RR 1 IOB173[A] gw_gao_inst_0/tck_ibuf/O
50.682 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365 0.683 tINS RR 252 - gw_gao_inst_0/u_gw_jtag/tck_o
59.335 7.970 tNET RR 1 R97C161[3][A] gw_gao_inst_0/u_la0_top/data_out_shift_reg_0_s1/CLK
59.271 -0.064 tSu 1 R97C161[3][A] gw_gao_inst_0/u_la0_top/data_out_shift_reg_0_s1

Path Statistics:

Clock Skew 0.391
Setup Relationship 25.000
Logic Level 6
Arrival Clock Path Delay cell: 1.375, 15.373%; route: 7.569, 84.627%
Arrival Data Path Delay cell: 2.658, 54.028%; route: 1.819, 36.976%; tC2Q: 0.442, 8.996%
Required Clock Path Delay cell: 1.365, 14.622%; route: 7.970, 85.378%

Path21

Path Summary:

Slack 41.496
Data Arrival Time 17.708
Data Required Time 59.203
From gw_gao_inst_0/u_la0_top/module_state_1_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOB173[A] gw_gao_inst_0/tck_ibuf/I
0.683 0.683 tINS RR 1 IOB173[A] gw_gao_inst_0/tck_ibuf/O
0.683 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365 0.683 tINS RR 252 - gw_gao_inst_0/u_gw_jtag/tck_o
9.321 7.956 tNET RR 1 R95C167[2][A] gw_gao_inst_0/u_la0_top/module_state_1_s0/CLK
9.689 0.368 tC2Q RF 28 R95C167[2][A] gw_gao_inst_0/u_la0_top/module_state_1_s0/Q
11.814 2.125 tNET FF 1 R94C162[1][B] gw_gao_inst_0/u_la0_top/data_out_shift_reg_33_s5/I1
12.321 0.507 tINS FR 3 R94C162[1][B] gw_gao_inst_0/u_la0_top/data_out_shift_reg_33_s5/F
12.329 0.008 tNET RR 1 R94C162[2][B] gw_gao_inst_0/u_la0_top/jtag_strobe_i_s3/I1
12.896 0.567 tINS RR 1 R94C162[2][B] gw_gao_inst_0/u_la0_top/jtag_strobe_i_s3/F
12.899 0.003 tNET RR 1 R94C162[3][A] gw_gao_inst_0/u_la0_top/jtag_strobe_i_s2/I2
13.446 0.548 tINS RR 1 R94C162[3][A] gw_gao_inst_0/u_la0_top/jtag_strobe_i_s2/F
13.449 0.003 tNET RR 1 R94C162[3][B] gw_gao_inst_0/u_la0_top/jtag_strobe_i_s0/I2
13.905 0.456 tINS RR 4 R94C162[3][B] gw_gao_inst_0/u_la0_top/jtag_strobe_i_s0/F
17.707 3.803 tNET RR 1 BSRAM_R82[29][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CEB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
50.000 50.000 active clock edge time
50.000 0.000 tck_pad_i
50.000 0.000 tCL RR 1 IOB173[A] gw_gao_inst_0/tck_ibuf/I
50.682 0.683 tINS RR 1 IOB173[A] gw_gao_inst_0/tck_ibuf/O
50.682 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365 0.683 tINS RR 252 - gw_gao_inst_0/u_gw_jtag/tck_o
59.295 7.930 tNET RR 1 BSRAM_R82[29][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKB
59.203 -0.091 tSu 1 BSRAM_R82[29][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew -0.027
Setup Relationship 50.000
Logic Level 5
Arrival Clock Path Delay cell: 1.365, 14.644%; route: 7.956, 85.356%
Arrival Data Path Delay cell: 2.079, 24.788%; route: 5.940, 70.830%; tC2Q: 0.368, 4.382%
Required Clock Path Delay cell: 1.365, 14.686%; route: 7.930, 85.314%

Path22

Path Summary:

Slack 42.339
Data Arrival Time 16.681
Data Required Time 59.019
From gw_gao_inst_0/u_icon_top/module_id_reg_3_s0
To gw_gao_inst_0/u_la0_top/address_counter_2_s0
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOB173[A] gw_gao_inst_0/tck_ibuf/I
0.683 0.683 tINS RR 1 IOB173[A] gw_gao_inst_0/tck_ibuf/O
0.683 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365 0.683 tINS RR 252 - gw_gao_inst_0/u_gw_jtag/tck_o
9.326 7.961 tNET RR 1 R97C170[0][A] gw_gao_inst_0/u_icon_top/module_id_reg_3_s0/CLK
9.708 0.382 tC2Q RR 2 R97C170[0][A] gw_gao_inst_0/u_icon_top/module_id_reg_3_s0/Q
10.092 0.384 tNET RR 1 R96C169[0][B] gw_gao_inst_0/u_la0_top/n20_s1/I2
10.599 0.507 tINS RR 7 R96C169[0][B] gw_gao_inst_0/u_la0_top/n20_s1/F
11.619 1.020 tNET RR 1 R95C165[3][A] gw_gao_inst_0/u_la0_top/op_reg_en_s3/I2
11.938 0.319 tINS RF 38 R95C165[3][A] gw_gao_inst_0/u_la0_top/op_reg_en_s3/F
13.186 1.247 tNET FF 1 R94C168[3][B] gw_gao_inst_0/u_la0_top/word_ct_en_s27/I3
13.759 0.574 tINS FR 4 R94C168[3][B] gw_gao_inst_0/u_la0_top/word_ct_en_s27/F
14.524 0.765 tNET RR 1 R95C162[0][B] gw_gao_inst_0/u_la0_top/addr_ct_en_s24/I3
15.032 0.507 tINS RR 11 R95C162[0][B] gw_gao_inst_0/u_la0_top/addr_ct_en_s24/F
16.681 1.649 tNET RR 1 R95C154[0][B] gw_gao_inst_0/u_la0_top/address_counter_2_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
50.000 50.000 active clock edge time
50.000 0.000 tck_pad_i
50.000 0.000 tCL RR 1 IOB173[A] gw_gao_inst_0/tck_ibuf/I
50.682 0.683 tINS RR 1 IOB173[A] gw_gao_inst_0/tck_ibuf/O
50.682 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365 0.683 tINS RR 252 - gw_gao_inst_0/u_gw_jtag/tck_o
59.331 7.966 tNET RR 1 R95C154[0][B] gw_gao_inst_0/u_la0_top/address_counter_2_s0/CLK
59.019 -0.311 tSu 1 R95C154[0][B] gw_gao_inst_0/u_la0_top/address_counter_2_s0

Path Statistics:

Clock Skew 0.005
Setup Relationship 50.000
Logic Level 5
Arrival Clock Path Delay cell: 1.365, 14.637%; route: 7.961, 85.363%
Arrival Data Path Delay cell: 1.908, 25.935%; route: 5.065, 68.865%; tC2Q: 0.382, 5.201%
Required Clock Path Delay cell: 1.365, 14.629%; route: 7.966, 85.371%

Path23

Path Summary:

Slack 42.339
Data Arrival Time 16.681
Data Required Time 59.019
From gw_gao_inst_0/u_icon_top/module_id_reg_3_s0
To gw_gao_inst_0/u_la0_top/address_counter_6_s0
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOB173[A] gw_gao_inst_0/tck_ibuf/I
0.683 0.683 tINS RR 1 IOB173[A] gw_gao_inst_0/tck_ibuf/O
0.683 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365 0.683 tINS RR 252 - gw_gao_inst_0/u_gw_jtag/tck_o
9.326 7.961 tNET RR 1 R97C170[0][A] gw_gao_inst_0/u_icon_top/module_id_reg_3_s0/CLK
9.708 0.382 tC2Q RR 2 R97C170[0][A] gw_gao_inst_0/u_icon_top/module_id_reg_3_s0/Q
10.092 0.384 tNET RR 1 R96C169[0][B] gw_gao_inst_0/u_la0_top/n20_s1/I2
10.599 0.507 tINS RR 7 R96C169[0][B] gw_gao_inst_0/u_la0_top/n20_s1/F
11.619 1.020 tNET RR 1 R95C165[3][A] gw_gao_inst_0/u_la0_top/op_reg_en_s3/I2
11.938 0.319 tINS RF 38 R95C165[3][A] gw_gao_inst_0/u_la0_top/op_reg_en_s3/F
13.186 1.247 tNET FF 1 R94C168[3][B] gw_gao_inst_0/u_la0_top/word_ct_en_s27/I3
13.759 0.574 tINS FR 4 R94C168[3][B] gw_gao_inst_0/u_la0_top/word_ct_en_s27/F
14.524 0.765 tNET RR 1 R95C162[0][B] gw_gao_inst_0/u_la0_top/addr_ct_en_s24/I3
15.032 0.507 tINS RR 11 R95C162[0][B] gw_gao_inst_0/u_la0_top/addr_ct_en_s24/F
16.681 1.649 tNET RR 1 R95C154[3][A] gw_gao_inst_0/u_la0_top/address_counter_6_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
50.000 50.000 active clock edge time
50.000 0.000 tck_pad_i
50.000 0.000 tCL RR 1 IOB173[A] gw_gao_inst_0/tck_ibuf/I
50.682 0.683 tINS RR 1 IOB173[A] gw_gao_inst_0/tck_ibuf/O
50.682 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365 0.683 tINS RR 252 - gw_gao_inst_0/u_gw_jtag/tck_o
59.331 7.966 tNET RR 1 R95C154[3][A] gw_gao_inst_0/u_la0_top/address_counter_6_s0/CLK
59.019 -0.311 tSu 1 R95C154[3][A] gw_gao_inst_0/u_la0_top/address_counter_6_s0

Path Statistics:

Clock Skew 0.005
Setup Relationship 50.000
Logic Level 5
Arrival Clock Path Delay cell: 1.365, 14.637%; route: 7.961, 85.363%
Arrival Data Path Delay cell: 1.908, 25.935%; route: 5.065, 68.865%; tC2Q: 0.382, 5.201%
Required Clock Path Delay cell: 1.365, 14.629%; route: 7.966, 85.371%

Path24

Path Summary:

Slack 42.339
Data Arrival Time 16.681
Data Required Time 59.019
From gw_gao_inst_0/u_icon_top/module_id_reg_3_s0
To gw_gao_inst_0/u_la0_top/address_counter_10_s0
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOB173[A] gw_gao_inst_0/tck_ibuf/I
0.683 0.683 tINS RR 1 IOB173[A] gw_gao_inst_0/tck_ibuf/O
0.683 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365 0.683 tINS RR 252 - gw_gao_inst_0/u_gw_jtag/tck_o
9.326 7.961 tNET RR 1 R97C170[0][A] gw_gao_inst_0/u_icon_top/module_id_reg_3_s0/CLK
9.708 0.382 tC2Q RR 2 R97C170[0][A] gw_gao_inst_0/u_icon_top/module_id_reg_3_s0/Q
10.092 0.384 tNET RR 1 R96C169[0][B] gw_gao_inst_0/u_la0_top/n20_s1/I2
10.599 0.507 tINS RR 7 R96C169[0][B] gw_gao_inst_0/u_la0_top/n20_s1/F
11.619 1.020 tNET RR 1 R95C165[3][A] gw_gao_inst_0/u_la0_top/op_reg_en_s3/I2
11.938 0.319 tINS RF 38 R95C165[3][A] gw_gao_inst_0/u_la0_top/op_reg_en_s3/F
13.186 1.247 tNET FF 1 R94C168[3][B] gw_gao_inst_0/u_la0_top/word_ct_en_s27/I3
13.759 0.574 tINS FR 4 R94C168[3][B] gw_gao_inst_0/u_la0_top/word_ct_en_s27/F
14.524 0.765 tNET RR 1 R95C162[0][B] gw_gao_inst_0/u_la0_top/addr_ct_en_s24/I3
15.032 0.507 tINS RR 11 R95C162[0][B] gw_gao_inst_0/u_la0_top/addr_ct_en_s24/F
16.681 1.649 tNET RR 1 R95C154[2][B] gw_gao_inst_0/u_la0_top/address_counter_10_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
50.000 50.000 active clock edge time
50.000 0.000 tck_pad_i
50.000 0.000 tCL RR 1 IOB173[A] gw_gao_inst_0/tck_ibuf/I
50.682 0.683 tINS RR 1 IOB173[A] gw_gao_inst_0/tck_ibuf/O
50.682 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365 0.683 tINS RR 252 - gw_gao_inst_0/u_gw_jtag/tck_o
59.331 7.966 tNET RR 1 R95C154[2][B] gw_gao_inst_0/u_la0_top/address_counter_10_s0/CLK
59.019 -0.311 tSu 1 R95C154[2][B] gw_gao_inst_0/u_la0_top/address_counter_10_s0

Path Statistics:

Clock Skew 0.005
Setup Relationship 50.000
Logic Level 5
Arrival Clock Path Delay cell: 1.365, 14.637%; route: 7.961, 85.363%
Arrival Data Path Delay cell: 1.908, 25.935%; route: 5.065, 68.865%; tC2Q: 0.382, 5.201%
Required Clock Path Delay cell: 1.365, 14.629%; route: 7.966, 85.371%

Path25

Path Summary:

Slack 42.769
Data Arrival Time 16.236
Data Required Time 59.005
From gw_gao_inst_0/u_icon_top/module_id_reg_3_s0
To gw_gao_inst_0/u_la0_top/address_counter_1_s0
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOB173[A] gw_gao_inst_0/tck_ibuf/I
0.683 0.683 tINS RR 1 IOB173[A] gw_gao_inst_0/tck_ibuf/O
0.683 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365 0.683 tINS RR 252 - gw_gao_inst_0/u_gw_jtag/tck_o
9.326 7.961 tNET RR 1 R97C170[0][A] gw_gao_inst_0/u_icon_top/module_id_reg_3_s0/CLK
9.708 0.382 tC2Q RR 2 R97C170[0][A] gw_gao_inst_0/u_icon_top/module_id_reg_3_s0/Q
10.092 0.384 tNET RR 1 R96C169[0][B] gw_gao_inst_0/u_la0_top/n20_s1/I2
10.599 0.507 tINS RR 7 R96C169[0][B] gw_gao_inst_0/u_la0_top/n20_s1/F
11.619 1.020 tNET RR 1 R95C165[3][A] gw_gao_inst_0/u_la0_top/op_reg_en_s3/I2
11.938 0.319 tINS RF 38 R95C165[3][A] gw_gao_inst_0/u_la0_top/op_reg_en_s3/F
13.186 1.247 tNET FF 1 R94C168[3][B] gw_gao_inst_0/u_la0_top/word_ct_en_s27/I3
13.759 0.574 tINS FR 4 R94C168[3][B] gw_gao_inst_0/u_la0_top/word_ct_en_s27/F
14.524 0.765 tNET RR 1 R95C162[0][B] gw_gao_inst_0/u_la0_top/addr_ct_en_s24/I3
15.032 0.507 tINS RR 11 R95C162[0][B] gw_gao_inst_0/u_la0_top/addr_ct_en_s24/F
16.236 1.204 tNET RR 1 R97C155[0][A] gw_gao_inst_0/u_la0_top/address_counter_1_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
50.000 50.000 active clock edge time
50.000 0.000 tck_pad_i
50.000 0.000 tCL RR 1 IOB173[A] gw_gao_inst_0/tck_ibuf/I
50.682 0.683 tINS RR 1 IOB173[A] gw_gao_inst_0/tck_ibuf/O
50.682 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365 0.683 tINS RR 252 - gw_gao_inst_0/u_gw_jtag/tck_o
59.316 7.951 tNET RR 1 R97C155[0][A] gw_gao_inst_0/u_la0_top/address_counter_1_s0/CLK
59.005 -0.311 tSu 1 R97C155[0][A] gw_gao_inst_0/u_la0_top/address_counter_1_s0

Path Statistics:

Clock Skew -0.009
Setup Relationship 50.000
Logic Level 5
Arrival Clock Path Delay cell: 1.365, 14.637%; route: 7.961, 85.363%
Arrival Data Path Delay cell: 1.908, 27.605%; route: 4.620, 66.860%; tC2Q: 0.382, 5.535%
Required Clock Path Delay cell: 1.365, 14.652%; route: 7.951, 85.348%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 0.012
Data Arrival Time 0.171
Data Required Time 0.159
From MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES80
To MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES80
Launch Clk HS_CLK:[R]
Latch Clk HS_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 HS_CLK
0.000 0.000 tCL RR 548 - GND_cZ/G
0.171 0.171 tNET RR 1 IOB112[A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES80/CALIB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 HS_CLK
0.000 0.000 tCL RR 5 IOB120 MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
0.000 0.000 tNET RR 3 - MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CLKIN
0.156 0.156 tINS RR 5 - MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CLKOUT
0.159 0.003 tNET RR 1 IOB112[A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES80/FCLK
0.159 0.000 tHld 1 IOB112[A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES80

Path Statistics:

Clock Skew 0.159
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.171, 100.000%
Required Clock Path Delay cell: 0.156, 98.113%; route: 0.003, 1.887%

Path2

Path Summary:

Slack 0.012
Data Arrival Time 0.171
Data Required Time 0.159
From MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES81
To MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES81
Launch Clk HS_CLK:[R]
Latch Clk HS_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 HS_CLK
0.000 0.000 tCL RR 548 - GND_cZ/G
0.171 0.171 tNET RR 1 IOB144[A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES81/CALIB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 HS_CLK
0.000 0.000 tCL RR 5 IOB120 MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
0.000 0.000 tNET RR 3 - MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CLKIN
0.156 0.156 tINS RR 5 - MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CLKOUT
0.159 0.003 tNET RR 1 IOB144[A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES81/FCLK
0.159 0.000 tHld 1 IOB144[A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES81

Path Statistics:

Clock Skew 0.159
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.171, 100.000%
Required Clock Path Delay cell: 0.156, 98.113%; route: 0.003, 1.887%

Path3

Path Summary:

Slack 0.012
Data Arrival Time 0.171
Data Required Time 0.159
From MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES82
To MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES82
Launch Clk HS_CLK:[R]
Latch Clk HS_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 HS_CLK
0.000 0.000 tCL RR 548 - GND_cZ/G
0.171 0.171 tNET RR 1 IOB133[A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES82/CALIB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 HS_CLK
0.000 0.000 tCL RR 5 IOB120 MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
0.000 0.000 tNET RR 3 - MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CLKIN
0.156 0.156 tINS RR 5 - MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CLKOUT
0.159 0.003 tNET RR 1 IOB133[A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES82/FCLK
0.159 0.000 tHld 1 IOB133[A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES82

Path Statistics:

Clock Skew 0.159
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.171, 100.000%
Required Clock Path Delay cell: 0.156, 98.113%; route: 0.003, 1.887%

Path4

Path Summary:

Slack 0.012
Data Arrival Time 0.171
Data Required Time 0.159
From MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES83
To MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES83
Launch Clk HS_CLK:[R]
Latch Clk HS_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 HS_CLK
0.000 0.000 tCL RR 548 - GND_cZ/G
0.171 0.171 tNET RR 1 IOB110[A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES83/CALIB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 HS_CLK
0.000 0.000 tCL RR 5 IOB120 MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
0.000 0.000 tNET RR 3 - MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CLKIN
0.156 0.156 tINS RR 5 - MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CLKOUT
0.159 0.003 tNET RR 1 IOB110[A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES83/FCLK
0.159 0.000 tHld 1 IOB110[A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES83

Path Statistics:

Clock Skew 0.159
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.171, 100.000%
Required Clock Path Delay cell: 0.156, 98.113%; route: 0.003, 1.887%

Path5

Path Summary:

Slack 0.024
Data Arrival Time 0.183
Data Required Time 0.159
From MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV
To MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV
Launch Clk HS_CLK:[R]
Latch Clk HS_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 HS_CLK
0.000 0.000 tCL RR 548 - GND_cZ/G
0.183 0.183 tNET RR 1 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CALIB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 HS_CLK
0.000 0.000 tCL RR 5 IOB120 MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
0.000 0.000 tNET RR 3 - MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CLKIN
0.156 0.156 tINS RR 5 - MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CLKOUT
0.159 0.003 tNET RR 5 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/HCLKIN
0.159 0.000 tHld 1 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV

Path Statistics:

Clock Skew 0.159
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.183, 100.000%
Required Clock Path Delay cell: 0.156, 98.113%; route: 0.003, 1.887%

Path6

Path Summary:

Slack 0.275
Data Arrival Time 4.758
Data Required Time 4.483
From gw_gao_inst_0/u_la0_top/word_count_3_s0
To gw_gao_inst_0/u_la0_top/word_count_3_s0
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOB173[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOB173[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 252 - gw_gao_inst_0/u_gw_jtag/tck_o
4.458 3.107 tNET RR 1 R93C164[1][A] gw_gao_inst_0/u_la0_top/word_count_3_s0/CLK
4.599 0.141 tC2Q RF 3 R93C164[1][A] gw_gao_inst_0/u_la0_top/word_count_3_s0/Q
4.605 0.006 tNET FF 1 R93C164[1][A] gw_gao_inst_0/u_la0_top/data_to_word_counter_3_s0/I2
4.758 0.153 tINS FF 1 R93C164[1][A] gw_gao_inst_0/u_la0_top/data_to_word_counter_3_s0/F
4.758 0.000 tNET FF 1 R93C164[1][A] gw_gao_inst_0/u_la0_top/word_count_3_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOB173[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOB173[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 252 - gw_gao_inst_0/u_gw_jtag/tck_o
4.458 3.107 tNET RR 1 R93C164[1][A] gw_gao_inst_0/u_la0_top/word_count_3_s0/CLK
4.483 0.025 tHld 1 R93C164[1][A] gw_gao_inst_0/u_la0_top/word_count_3_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.351, 30.305%; route: 3.107, 69.695%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 1.351, 30.305%; route: 3.107, 69.695%

Path7

Path Summary:

Slack 0.275
Data Arrival Time 4.755
Data Required Time 4.480
From gw_gao_inst_0/u_la0_top/word_count_4_s0
To gw_gao_inst_0/u_la0_top/word_count_4_s0
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOB173[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOB173[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 252 - gw_gao_inst_0/u_gw_jtag/tck_o
4.455 3.104 tNET RR 1 R97C165[0][A] gw_gao_inst_0/u_la0_top/word_count_4_s0/CLK
4.596 0.141 tC2Q RF 6 R97C165[0][A] gw_gao_inst_0/u_la0_top/word_count_4_s0/Q
4.602 0.006 tNET FF 1 R97C165[0][A] gw_gao_inst_0/u_la0_top/data_to_word_counter_4_s0/I1
4.755 0.153 tINS FF 1 R97C165[0][A] gw_gao_inst_0/u_la0_top/data_to_word_counter_4_s0/F
4.755 0.000 tNET FF 1 R97C165[0][A] gw_gao_inst_0/u_la0_top/word_count_4_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOB173[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOB173[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 252 - gw_gao_inst_0/u_gw_jtag/tck_o
4.455 3.104 tNET RR 1 R97C165[0][A] gw_gao_inst_0/u_la0_top/word_count_4_s0/CLK
4.480 0.025 tHld 1 R97C165[0][A] gw_gao_inst_0/u_la0_top/word_count_4_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.351, 30.325%; route: 3.104, 69.675%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 1.351, 30.325%; route: 3.104, 69.675%

Path8

Path Summary:

Slack 0.275
Data Arrival Time 1.735
Data Required Time 1.459
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
Launch Clk Inst3_CLKDIV_OUT:[R]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.434 1.434 tNET RR 1 R95C146[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK
1.576 0.141 tC2Q RF 7 R95C146[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/Q
1.582 0.006 tNET FF 1 R95C146[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n391_s1/I2
1.735 0.153 tINS FF 1 R95C146[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n391_s1/F
1.735 0.000 tNET FF 1 R95C146[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.434 1.434 tNET RR 1 R95C146[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK
1.459 0.025 tHld 1 R95C146[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.434, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.434, 100.000%

Path9

Path Summary:

Slack 0.275
Data Arrival Time 1.727
Data Required Time 1.452
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1
Launch Clk Inst3_CLKDIV_OUT:[R]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.427 1.427 tNET RR 1 R97C141[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLK
1.568 0.141 tC2Q RF 5 R97C141[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/Q
1.574 0.006 tNET FF 1 R97C141[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n289_s0/I2
1.727 0.153 tINS FF 1 R97C141[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n289_s0/F
1.727 0.000 tNET FF 1 R97C141[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.427 1.427 tNET RR 1 R97C141[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLK
1.452 0.025 tHld 1 R97C141[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.427, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.427, 100.000%

Path10

Path Summary:

Slack 0.275
Data Arrival Time 1.735
Data Required Time 1.459
From gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1
To gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1
Launch Clk Inst3_CLKDIV_OUT:[R]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.434 1.434 tNET RR 1 R95C142[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLK
1.576 0.141 tC2Q RF 13 R95C142[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/Q
1.582 0.006 tNET FF 1 R95C142[0][A] gw_gao_inst_0/u_la0_top/n2213_s1/I0
1.735 0.153 tINS FF 1 R95C142[0][A] gw_gao_inst_0/u_la0_top/n2213_s1/F
1.735 0.000 tNET FF 1 R95C142[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.434 1.434 tNET RR 1 R95C142[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLK
1.459 0.025 tHld 1 R95C142[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.434, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.434, 100.000%

Path11

Path Summary:

Slack 0.275
Data Arrival Time 1.728
Data Required Time 1.453
From gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1
To gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1
Launch Clk Inst3_CLKDIV_OUT:[R]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.428 1.428 tNET RR 1 R94C144[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLK
1.569 0.141 tC2Q RF 10 R94C144[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/Q
1.575 0.006 tNET FF 1 R94C144[0][A] gw_gao_inst_0/u_la0_top/n2210_s1/I0
1.728 0.153 tINS FF 1 R94C144[0][A] gw_gao_inst_0/u_la0_top/n2210_s1/F
1.728 0.000 tNET FF 1 R94C144[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.428 1.428 tNET RR 1 R94C144[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLK
1.453 0.025 tHld 1 R94C144[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.428, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.428, 100.000%

Path12

Path Summary:

Slack 0.275
Data Arrival Time 1.729
Data Required Time 1.454
From gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1
To gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1
Launch Clk Inst3_CLKDIV_OUT:[R]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.429 1.429 tNET RR 1 R96C143[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLK
1.570 0.141 tC2Q RF 6 R96C143[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/Q
1.576 0.006 tNET FF 1 R96C143[0][A] gw_gao_inst_0/u_la0_top/n2208_s1/I1
1.729 0.153 tINS FF 1 R96C143[0][A] gw_gao_inst_0/u_la0_top/n2208_s1/F
1.729 0.000 tNET FF 1 R96C143[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.429 1.429 tNET RR 1 R96C143[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLK
1.454 0.025 tHld 1 R96C143[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.429, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.429, 100.000%

Path13

Path Summary:

Slack 0.275
Data Arrival Time 1.728
Data Required Time 1.453
From gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1
To gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1
Launch Clk Inst3_CLKDIV_OUT:[R]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.428 1.428 tNET RR 1 R94C140[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLK
1.569 0.141 tC2Q RF 3 R94C140[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/Q
1.575 0.006 tNET FF 1 R94C140[0][A] gw_gao_inst_0/u_la0_top/n2205_s1/I1
1.728 0.153 tINS FF 1 R94C140[0][A] gw_gao_inst_0/u_la0_top/n2205_s1/F
1.728 0.000 tNET FF 1 R94C140[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.428 1.428 tNET RR 1 R94C140[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLK
1.453 0.025 tHld 1 R94C140[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.428, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.428, 100.000%

Path14

Path Summary:

Slack 0.275
Data Arrival Time 1.732
Data Required Time 1.457
From gw_gao_inst_0/u_la0_top/capture_window_sel_10_s1
To gw_gao_inst_0/u_la0_top/capture_window_sel_10_s1
Launch Clk Inst3_CLKDIV_OUT:[R]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.432 1.432 tNET RR 1 R94C141[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_10_s1/CLK
1.573 0.141 tC2Q RF 3 R94C141[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_10_s1/Q
1.579 0.006 tNET FF 1 R94C141[0][A] gw_gao_inst_0/u_la0_top/n2204_s1/I1
1.732 0.153 tINS FF 1 R94C141[0][A] gw_gao_inst_0/u_la0_top/n2204_s1/F
1.732 0.000 tNET FF 1 R94C141[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_10_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.432 1.432 tNET RR 1 R94C141[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_10_s1/CLK
1.457 0.025 tHld 1 R94C141[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_10_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.432, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.432, 100.000%

Path15

Path Summary:

Slack 0.278
Data Arrival Time 4.759
Data Required Time 4.481
From gw_gao_inst_0/u_la0_top/bit_count_0_s1
To gw_gao_inst_0/u_la0_top/bit_count_0_s1
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOB173[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOB173[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 252 - gw_gao_inst_0/u_gw_jtag/tck_o
4.456 3.105 tNET RR 1 R94C168[0][A] gw_gao_inst_0/u_la0_top/bit_count_0_s1/CLK
4.597 0.141 tC2Q RF 7 R94C168[0][A] gw_gao_inst_0/u_la0_top/bit_count_0_s1/Q
4.606 0.009 tNET FF 1 R94C168[0][A] gw_gao_inst_0/u_la0_top/n879_s3/I0
4.759 0.153 tINS FF 1 R94C168[0][A] gw_gao_inst_0/u_la0_top/n879_s3/F
4.759 0.000 tNET FF 1 R94C168[0][A] gw_gao_inst_0/u_la0_top/bit_count_0_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOB173[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOB173[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 252 - gw_gao_inst_0/u_gw_jtag/tck_o
4.456 3.105 tNET RR 1 R94C168[0][A] gw_gao_inst_0/u_la0_top/bit_count_0_s1/CLK
4.481 0.025 tHld 1 R94C168[0][A] gw_gao_inst_0/u_la0_top/bit_count_0_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.351, 30.317%; route: 3.105, 69.683%
Arrival Data Path Delay cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay cell: 1.351, 30.317%; route: 3.105, 69.683%

Path16

Path Summary:

Slack 0.278
Data Arrival Time 4.756
Data Required Time 4.478
From gw_gao_inst_0/u_la0_top/word_count_13_s0
To gw_gao_inst_0/u_la0_top/word_count_13_s0
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOB173[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOB173[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 252 - gw_gao_inst_0/u_gw_jtag/tck_o
4.453 3.102 tNET RR 1 R96C164[0][A] gw_gao_inst_0/u_la0_top/word_count_13_s0/CLK
4.594 0.141 tC2Q RF 4 R96C164[0][A] gw_gao_inst_0/u_la0_top/word_count_13_s0/Q
4.603 0.009 tNET FF 1 R96C164[0][A] gw_gao_inst_0/u_la0_top/data_to_word_counter_13_s0/I2
4.756 0.153 tINS FF 1 R96C164[0][A] gw_gao_inst_0/u_la0_top/data_to_word_counter_13_s0/F
4.756 0.000 tNET FF 1 R96C164[0][A] gw_gao_inst_0/u_la0_top/word_count_13_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOB173[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOB173[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 252 - gw_gao_inst_0/u_gw_jtag/tck_o
4.453 3.102 tNET RR 1 R96C164[0][A] gw_gao_inst_0/u_la0_top/word_count_13_s0/CLK
4.478 0.025 tHld 1 R96C164[0][A] gw_gao_inst_0/u_la0_top/word_count_13_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.351, 30.341%; route: 3.102, 69.659%
Arrival Data Path Delay cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay cell: 1.351, 30.341%; route: 3.102, 69.659%

Path17

Path Summary:

Slack 0.278
Data Arrival Time 4.750
Data Required Time 4.472
From gw_gao_inst_0/u_la0_top/address_counter_1_s0
To gw_gao_inst_0/u_la0_top/address_counter_1_s0
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOB173[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOB173[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 252 - gw_gao_inst_0/u_gw_jtag/tck_o
4.447 3.096 tNET RR 1 R97C155[0][A] gw_gao_inst_0/u_la0_top/address_counter_1_s0/CLK
4.588 0.141 tC2Q RF 8 R97C155[0][A] gw_gao_inst_0/u_la0_top/address_counter_1_s0/Q
4.597 0.009 tNET FF 1 R97C155[0][A] gw_gao_inst_0/u_la0_top/data_to_addr_counter_1_s0/I2
4.750 0.153 tINS FF 1 R97C155[0][A] gw_gao_inst_0/u_la0_top/data_to_addr_counter_1_s0/F
4.750 0.000 tNET FF 1 R97C155[0][A] gw_gao_inst_0/u_la0_top/address_counter_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOB173[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOB173[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 252 - gw_gao_inst_0/u_gw_jtag/tck_o
4.447 3.096 tNET RR 1 R97C155[0][A] gw_gao_inst_0/u_la0_top/address_counter_1_s0/CLK
4.472 0.025 tHld 1 R97C155[0][A] gw_gao_inst_0/u_la0_top/address_counter_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.351, 30.380%; route: 3.096, 69.620%
Arrival Data Path Delay cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay cell: 1.351, 30.380%; route: 3.096, 69.620%

Path18

Path Summary:

Slack 0.278
Data Arrival Time 4.756
Data Required Time 4.478
From gw_gao_inst_0/u_la0_top/address_counter_3_s0
To gw_gao_inst_0/u_la0_top/address_counter_3_s0
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOB173[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOB173[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 252 - gw_gao_inst_0/u_gw_jtag/tck_o
4.453 3.102 tNET RR 1 R96C154[1][A] gw_gao_inst_0/u_la0_top/address_counter_3_s0/CLK
4.594 0.141 tC2Q RF 6 R96C154[1][A] gw_gao_inst_0/u_la0_top/address_counter_3_s0/Q
4.603 0.009 tNET FF 1 R96C154[1][A] gw_gao_inst_0/u_la0_top/data_to_addr_counter_3_s0/I2
4.756 0.153 tINS FF 1 R96C154[1][A] gw_gao_inst_0/u_la0_top/data_to_addr_counter_3_s0/F
4.756 0.000 tNET FF 1 R96C154[1][A] gw_gao_inst_0/u_la0_top/address_counter_3_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOB173[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOB173[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 252 - gw_gao_inst_0/u_gw_jtag/tck_o
4.453 3.102 tNET RR 1 R96C154[1][A] gw_gao_inst_0/u_la0_top/address_counter_3_s0/CLK
4.478 0.025 tHld 1 R96C154[1][A] gw_gao_inst_0/u_la0_top/address_counter_3_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.351, 30.341%; route: 3.102, 69.659%
Arrival Data Path Delay cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay cell: 1.351, 30.341%; route: 3.102, 69.659%

Path19

Path Summary:

Slack 0.278
Data Arrival Time 4.754
Data Required Time 4.476
From gw_gao_inst_0/u_la0_top/address_counter_5_s0
To gw_gao_inst_0/u_la0_top/address_counter_5_s0
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOB173[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOB173[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 252 - gw_gao_inst_0/u_gw_jtag/tck_o
4.451 3.100 tNET RR 1 R97C154[1][A] gw_gao_inst_0/u_la0_top/address_counter_5_s0/CLK
4.592 0.141 tC2Q RF 7 R97C154[1][A] gw_gao_inst_0/u_la0_top/address_counter_5_s0/Q
4.601 0.009 tNET FF 1 R97C154[1][A] gw_gao_inst_0/u_la0_top/data_to_addr_counter_5_s0/I2
4.754 0.153 tINS FF 1 R97C154[1][A] gw_gao_inst_0/u_la0_top/data_to_addr_counter_5_s0/F
4.754 0.000 tNET FF 1 R97C154[1][A] gw_gao_inst_0/u_la0_top/address_counter_5_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOB173[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOB173[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 252 - gw_gao_inst_0/u_gw_jtag/tck_o
4.451 3.100 tNET RR 1 R97C154[1][A] gw_gao_inst_0/u_la0_top/address_counter_5_s0/CLK
4.476 0.025 tHld 1 R97C154[1][A] gw_gao_inst_0/u_la0_top/address_counter_5_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.351, 30.353%; route: 3.100, 69.647%
Arrival Data Path Delay cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay cell: 1.351, 30.353%; route: 3.100, 69.647%

Path20

Path Summary:

Slack 0.278
Data Arrival Time 1.734
Data Required Time 1.456
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
Launch Clk Inst3_CLKDIV_OUT:[R]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.431 1.431 tNET RR 1 R95C145[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK
1.572 0.141 tC2Q RF 7 R95C145[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/Q
1.581 0.009 tNET FF 1 R95C145[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n388_s1/I2
1.734 0.153 tINS FF 1 R95C145[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n388_s1/F
1.734 0.000 tNET FF 1 R95C145[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.431 1.431 tNET RR 1 R95C145[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK
1.456 0.025 tHld 1 R95C145[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.431, 100.000%
Arrival Data Path Delay cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.431, 100.000%

Path21

Path Summary:

Slack 0.278
Data Arrival Time 1.734
Data Required Time 1.456
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1
Launch Clk Inst3_CLKDIV_OUT:[R]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.431 1.431 tNET RR 1 R95C143[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/CLK
1.572 0.141 tC2Q RF 6 R95C143[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/Q
1.581 0.009 tNET FF 1 R95C143[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n384_s2/I2
1.734 0.153 tINS FF 1 R95C143[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n384_s2/F
1.734 0.000 tNET FF 1 R95C143[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.431 1.431 tNET RR 1 R95C143[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/CLK
1.456 0.025 tHld 1 R95C143[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.431, 100.000%
Arrival Data Path Delay cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.431, 100.000%

Path22

Path Summary:

Slack 0.278
Data Arrival Time 1.736
Data Required Time 1.458
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1
Launch Clk Inst3_CLKDIV_OUT:[R]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.433 1.433 tNET RR 1 R96C142[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLK
1.574 0.141 tC2Q RF 3 R96C142[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/Q
1.583 0.009 tNET FF 1 R96C142[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n281_s0/I2
1.736 0.153 tINS FF 1 R96C142[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n281_s0/F
1.736 0.000 tNET FF 1 R96C142[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.433 1.433 tNET RR 1 R96C142[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLK
1.458 0.025 tHld 1 R96C142[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.433, 100.000%
Arrival Data Path Delay cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.433, 100.000%

Path23

Path Summary:

Slack 0.278
Data Arrival Time 1.728
Data Required Time 1.450
From gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1
To gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1
Launch Clk Inst3_CLKDIV_OUT:[R]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.425 1.425 tNET RR 1 R96C144[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLK
1.566 0.141 tC2Q RF 5 R96C144[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/Q
1.575 0.009 tNET FF 1 R96C144[0][A] gw_gao_inst_0/u_la0_top/n2206_s1/I2
1.728 0.153 tINS FF 1 R96C144[0][A] gw_gao_inst_0/u_la0_top/n2206_s1/F
1.728 0.000 tNET FF 1 R96C144[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.425 1.425 tNET RR 1 R96C144[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLK
1.450 0.025 tHld 1 R96C144[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.425, 100.000%
Arrival Data Path Delay cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.425, 100.000%

Path24

Path Summary:

Slack 0.278
Data Arrival Time 1.734
Data Required Time 1.456
From MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/lane2_cnt_0_s1
To MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/lane2_cnt_0_s1
Launch Clk Inst3_CLKDIV_OUT:[R]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.431 1.431 tNET RR 1 R95C123[0][A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/lane2_cnt_0_s1/CLK
1.572 0.141 tC2Q RF 6 R95C123[0][A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/lane2_cnt_0_s1/Q
1.581 0.009 tNET FF 1 R95C123[0][A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/n171_s3/I1
1.734 0.153 tINS FF 1 R95C123[0][A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/n171_s3/F
1.734 0.000 tNET FF 1 R95C123[0][A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/lane2_cnt_0_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.431 1.431 tNET RR 1 R95C123[0][A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/lane2_cnt_0_s1/CLK
1.456 0.025 tHld 1 R95C123[0][A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/lane2_cnt_0_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.431, 100.000%
Arrival Data Path Delay cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.431, 100.000%

Path25

Path Summary:

Slack 0.281
Data Arrival Time 1.737
Data Required Time 1.456
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
Launch Clk Inst3_CLKDIV_OUT:[R]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.431 1.431 tNET RR 1 R95C143[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK
1.572 0.141 tC2Q RF 9 R95C143[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/Q
1.584 0.012 tNET FF 1 R95C143[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n387_s1/I1
1.737 0.153 tINS FF 1 R95C143[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n387_s1/F
1.737 0.000 tNET FF 1 R95C143[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.431 1.431 tNET RR 1 R95C143[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK
1.456 0.025 tHld 1 R95C143[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.431, 100.000%
Arrival Data Path Delay cell: 0.153, 50.000%; route: 0.012, 3.922%; tC2Q: 0.141, 46.078%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.431, 100.000%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 38.419
Data Arrival Time 44.909
Data Required Time 83.328
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
43.355 3.355 tNET FF 1 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
43.798 0.442 tC2Q FF 57 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
44.909 1.111 tNET FF 1 R97C141[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
80.000 80.000 active clock edge time
80.000 0.000 Inst3_CLKDIV_OUT
80.000 0.000 tCL RR 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
83.676 3.676 tNET RR 1 R97C141[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLK
83.328 -0.347 tSu 1 R97C141[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1

Path Statistics:

Clock Skew 0.320
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.355, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.111, 71.521%; tC2Q: 0.442, 28.479%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.676, 100.000%

Path2

Path Summary:

Slack 38.419
Data Arrival Time 44.909
Data Required Time 83.328
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
43.355 3.355 tNET FF 1 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
43.798 0.442 tC2Q FF 57 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
44.909 1.111 tNET FF 1 R97C141[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
80.000 80.000 active clock edge time
80.000 0.000 Inst3_CLKDIV_OUT
80.000 0.000 tCL RR 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
83.676 3.676 tNET RR 1 R97C141[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLK
83.328 -0.347 tSu 1 R97C141[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1

Path Statistics:

Clock Skew 0.320
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.355, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.111, 71.521%; tC2Q: 0.442, 28.479%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.676, 100.000%

Path3

Path Summary:

Slack 38.428
Data Arrival Time 44.909
Data Required Time 83.337
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
43.355 3.355 tNET FF 1 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
43.798 0.442 tC2Q FF 57 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
44.909 1.111 tNET FF 1 R97C142[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
80.000 80.000 active clock edge time
80.000 0.000 Inst3_CLKDIV_OUT
80.000 0.000 tCL RR 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
83.685 3.685 tNET RR 1 R97C142[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLK
83.337 -0.347 tSu 1 R97C142[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1

Path Statistics:

Clock Skew 0.330
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.355, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.111, 71.521%; tC2Q: 0.442, 28.479%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.685, 100.000%

Path4

Path Summary:

Slack 38.451
Data Arrival Time 44.878
Data Required Time 83.329
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
43.355 3.355 tNET FF 1 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
43.798 0.442 tC2Q FF 57 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
44.878 1.080 tNET FF 1 R93C140[1][A] gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
80.000 80.000 active clock edge time
80.000 0.000 Inst3_CLKDIV_OUT
80.000 0.000 tCL RR 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
83.676 3.676 tNET RR 1 R93C140[1][A] gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLK
83.329 -0.347 tSu 1 R93C140[1][A] gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0

Path Statistics:

Clock Skew 0.321
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.355, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.080, 70.936%; tC2Q: 0.442, 29.064%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.676, 100.000%

Path5

Path Summary:

Slack 38.483
Data Arrival Time 44.845
Data Required Time 83.328
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
43.355 3.355 tNET FF 1 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
43.798 0.442 tC2Q FF 57 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
44.845 1.047 tNET FF 1 R97C139[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
80.000 80.000 active clock edge time
80.000 0.000 Inst3_CLKDIV_OUT
80.000 0.000 tCL RR 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
83.676 3.676 tNET RR 1 R97C139[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLK
83.328 -0.347 tSu 1 R97C139[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1

Path Statistics:

Clock Skew 0.320
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.355, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.047, 70.302%; tC2Q: 0.442, 29.698%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.676, 100.000%

Path6

Path Summary:

Slack 38.483
Data Arrival Time 44.845
Data Required Time 83.328
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
43.355 3.355 tNET FF 1 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
43.798 0.442 tC2Q FF 57 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
44.845 1.047 tNET FF 1 R97C139[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
80.000 80.000 active clock edge time
80.000 0.000 Inst3_CLKDIV_OUT
80.000 0.000 tCL RR 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
83.676 3.676 tNET RR 1 R97C139[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLK
83.328 -0.347 tSu 1 R97C139[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1

Path Statistics:

Clock Skew 0.320
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.355, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.047, 70.302%; tC2Q: 0.442, 29.698%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.676, 100.000%

Path7

Path Summary:

Slack 38.483
Data Arrival Time 44.845
Data Required Time 83.328
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
43.355 3.355 tNET FF 1 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
43.798 0.442 tC2Q FF 57 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
44.845 1.047 tNET FF 1 R97C139[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
80.000 80.000 active clock edge time
80.000 0.000 Inst3_CLKDIV_OUT
80.000 0.000 tCL RR 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
83.676 3.676 tNET RR 1 R97C139[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLK
83.328 -0.347 tSu 1 R97C139[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1

Path Statistics:

Clock Skew 0.320
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.355, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.047, 70.302%; tC2Q: 0.442, 29.698%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.676, 100.000%

Path8

Path Summary:

Slack 38.573
Data Arrival Time 44.758
Data Required Time 83.331
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
43.355 3.355 tNET FF 1 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
43.798 0.442 tC2Q FF 57 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
44.758 0.960 tNET FF 1 R96C139[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
80.000 80.000 active clock edge time
80.000 0.000 Inst3_CLKDIV_OUT
80.000 0.000 tCL RR 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
83.678 3.678 tNET RR 1 R96C139[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/CLK
83.331 -0.347 tSu 1 R96C139[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1

Path Statistics:

Clock Skew 0.323
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.355, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.960, 68.449%; tC2Q: 0.442, 31.551%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.678, 100.000%

Path9

Path Summary:

Slack 38.573
Data Arrival Time 44.758
Data Required Time 83.331
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
43.355 3.355 tNET FF 1 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
43.798 0.442 tC2Q FF 57 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
44.758 0.960 tNET FF 1 R96C139[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
80.000 80.000 active clock edge time
80.000 0.000 Inst3_CLKDIV_OUT
80.000 0.000 tCL RR 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
83.678 3.678 tNET RR 1 R96C139[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLK
83.331 -0.347 tSu 1 R96C139[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1

Path Statistics:

Clock Skew 0.323
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.355, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.960, 68.449%; tC2Q: 0.442, 31.551%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.678, 100.000%

Path10

Path Summary:

Slack 38.623
Data Arrival Time 44.719
Data Required Time 83.342
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
43.355 3.355 tNET FF 1 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
43.798 0.442 tC2Q FF 57 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
44.719 0.921 tNET FF 1 R95C146[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
80.000 80.000 active clock edge time
80.000 0.000 Inst3_CLKDIV_OUT
80.000 0.000 tCL RR 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
83.690 3.690 tNET RR 1 R95C146[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
83.342 -0.347 tSu 1 R95C146[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1

Path Statistics:

Clock Skew 0.335
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.355, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.921, 67.553%; tC2Q: 0.442, 32.447%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.690, 100.000%

Path11

Path Summary:

Slack 38.623
Data Arrival Time 44.719
Data Required Time 83.342
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
43.355 3.355 tNET FF 1 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
43.798 0.442 tC2Q FF 57 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
44.719 0.921 tNET FF 1 R95C146[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
80.000 80.000 active clock edge time
80.000 0.000 Inst3_CLKDIV_OUT
80.000 0.000 tCL RR 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
83.690 3.690 tNET RR 1 R95C146[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK
83.342 -0.347 tSu 1 R95C146[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1

Path Statistics:

Clock Skew 0.335
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.355, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.921, 67.553%; tC2Q: 0.442, 32.447%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.690, 100.000%

Path12

Path Summary:

Slack 38.623
Data Arrival Time 44.719
Data Required Time 83.342
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
43.355 3.355 tNET FF 1 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
43.798 0.442 tC2Q FF 57 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
44.719 0.921 tNET FF 1 R95C146[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
80.000 80.000 active clock edge time
80.000 0.000 Inst3_CLKDIV_OUT
80.000 0.000 tCL RR 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
83.690 3.690 tNET RR 1 R95C146[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK
83.342 -0.347 tSu 1 R95C146[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1

Path Statistics:

Clock Skew 0.335
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.355, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.921, 67.553%; tC2Q: 0.442, 32.447%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.690, 100.000%

Path13

Path Summary:

Slack 38.628
Data Arrival Time 44.690
Data Required Time 83.319
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
43.355 3.355 tNET FF 1 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
43.798 0.442 tC2Q FF 57 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
44.690 0.892 tNET FF 1 R97C144[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
80.000 80.000 active clock edge time
80.000 0.000 Inst3_CLKDIV_OUT
80.000 0.000 tCL RR 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
83.666 3.666 tNET RR 1 R97C144[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
83.319 -0.347 tSu 1 R97C144[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1

Path Statistics:

Clock Skew 0.311
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.355, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.892, 66.854%; tC2Q: 0.442, 33.146%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.666, 100.000%

Path14

Path Summary:

Slack 38.628
Data Arrival Time 44.690
Data Required Time 83.319
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
43.355 3.355 tNET FF 1 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
43.798 0.442 tC2Q FF 57 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
44.690 0.892 tNET FF 1 R97C144[0][A] gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
80.000 80.000 active clock edge time
80.000 0.000 Inst3_CLKDIV_OUT
80.000 0.000 tCL RR 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
83.666 3.666 tNET RR 1 R97C144[0][A] gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLK
83.319 -0.347 tSu 1 R97C144[0][A] gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0

Path Statistics:

Clock Skew 0.311
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.355, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.892, 66.854%; tC2Q: 0.442, 33.146%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.666, 100.000%

Path15

Path Summary:

Slack 38.656
Data Arrival Time 44.668
Data Required Time 83.324
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/triger_s0
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
43.355 3.355 tNET FF 1 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
43.798 0.442 tC2Q FF 57 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
44.668 0.870 tNET FF 1 R95C140[0][A] gw_gao_inst_0/u_la0_top/triger_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
80.000 80.000 active clock edge time
80.000 0.000 Inst3_CLKDIV_OUT
80.000 0.000 tCL RR 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
83.671 3.671 tNET RR 1 R95C140[0][A] gw_gao_inst_0/u_la0_top/triger_s0/CLK
83.324 -0.347 tSu 1 R95C140[0][A] gw_gao_inst_0/u_la0_top/triger_s0

Path Statistics:

Clock Skew 0.316
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.355, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.870, 66.286%; tC2Q: 0.442, 33.714%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.671, 100.000%

Path16

Path Summary:

Slack 38.656
Data Arrival Time 44.668
Data Required Time 83.324
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
43.355 3.355 tNET FF 1 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
43.798 0.442 tC2Q FF 57 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
44.668 0.870 tNET FF 1 R95C140[0][B] gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
80.000 80.000 active clock edge time
80.000 0.000 Inst3_CLKDIV_OUT
80.000 0.000 tCL RR 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
83.671 3.671 tNET RR 1 R95C140[0][B] gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLK
83.324 -0.347 tSu 1 R95C140[0][B] gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0

Path Statistics:

Clock Skew 0.316
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.355, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.870, 66.286%; tC2Q: 0.442, 33.714%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.671, 100.000%

Path17

Path Summary:

Slack 38.658
Data Arrival Time 44.668
Data Required Time 83.326
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
43.355 3.355 tNET FF 1 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
43.798 0.442 tC2Q FF 57 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
44.668 0.870 tNET FF 1 R94C140[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
80.000 80.000 active clock edge time
80.000 0.000 Inst3_CLKDIV_OUT
80.000 0.000 tCL RR 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
83.674 3.674 tNET RR 1 R94C140[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLK
83.326 -0.347 tSu 1 R94C140[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1

Path Statistics:

Clock Skew 0.318
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.355, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.870, 66.286%; tC2Q: 0.442, 33.714%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.674, 100.000%

Path18

Path Summary:

Slack 38.658
Data Arrival Time 44.668
Data Required Time 83.326
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/trigger_seq_start_s1
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
43.355 3.355 tNET FF 1 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
43.798 0.442 tC2Q FF 57 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
44.668 0.870 tNET FF 1 R94C140[2][A] gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
80.000 80.000 active clock edge time
80.000 0.000 Inst3_CLKDIV_OUT
80.000 0.000 tCL RR 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
83.674 3.674 tNET RR 1 R94C140[2][A] gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLK
83.326 -0.347 tSu 1 R94C140[2][A] gw_gao_inst_0/u_la0_top/trigger_seq_start_s1

Path Statistics:

Clock Skew 0.318
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.355, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.870, 66.286%; tC2Q: 0.442, 33.714%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.674, 100.000%

Path19

Path Summary:

Slack 38.658
Data Arrival Time 44.668
Data Required Time 83.326
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
43.355 3.355 tNET FF 1 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
43.798 0.442 tC2Q FF 57 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
44.668 0.870 tNET FF 1 R94C140[1][B] gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
80.000 80.000 active clock edge time
80.000 0.000 Inst3_CLKDIV_OUT
80.000 0.000 tCL RR 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
83.674 3.674 tNET RR 1 R94C140[1][B] gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLK
83.326 -0.347 tSu 1 R94C140[1][B] gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0

Path Statistics:

Clock Skew 0.318
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.355, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.870, 66.286%; tC2Q: 0.442, 33.714%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.674, 100.000%

Path20

Path Summary:

Slack 38.658
Data Arrival Time 44.668
Data Required Time 83.326
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
43.355 3.355 tNET FF 1 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
43.798 0.442 tC2Q FF 57 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
44.668 0.870 tNET FF 1 R94C140[1][A] gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
80.000 80.000 active clock edge time
80.000 0.000 Inst3_CLKDIV_OUT
80.000 0.000 tCL RR 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
83.674 3.674 tNET RR 1 R94C140[1][A] gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLK
83.326 -0.347 tSu 1 R94C140[1][A] gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0

Path Statistics:

Clock Skew 0.318
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.355, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.870, 66.286%; tC2Q: 0.442, 33.714%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.674, 100.000%

Path21

Path Summary:

Slack 38.683
Data Arrival Time 44.635
Data Required Time 83.319
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
43.355 3.355 tNET FF 1 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
43.798 0.442 tC2Q FF 57 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
44.635 0.837 tNET FF 1 R97C140[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
80.000 80.000 active clock edge time
80.000 0.000 Inst3_CLKDIV_OUT
80.000 0.000 tCL RR 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
83.666 3.666 tNET RR 1 R97C140[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK
83.319 -0.347 tSu 1 R97C140[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1

Path Statistics:

Clock Skew 0.311
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.355, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.837, 65.430%; tC2Q: 0.442, 34.570%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.666, 100.000%

Path22

Path Summary:

Slack 38.683
Data Arrival Time 44.635
Data Required Time 83.319
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
43.355 3.355 tNET FF 1 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
43.798 0.442 tC2Q FF 57 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
44.635 0.837 tNET FF 1 R97C140[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
80.000 80.000 active clock edge time
80.000 0.000 Inst3_CLKDIV_OUT
80.000 0.000 tCL RR 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
83.666 3.666 tNET RR 1 R97C140[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLK
83.319 -0.347 tSu 1 R97C140[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1

Path Statistics:

Clock Skew 0.311
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.355, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.837, 65.430%; tC2Q: 0.442, 34.570%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.666, 100.000%

Path23

Path Summary:

Slack 38.683
Data Arrival Time 44.635
Data Required Time 83.319
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
43.355 3.355 tNET FF 1 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
43.798 0.442 tC2Q FF 57 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
44.635 0.837 tNET FF 1 R97C140[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
80.000 80.000 active clock edge time
80.000 0.000 Inst3_CLKDIV_OUT
80.000 0.000 tCL RR 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
83.666 3.666 tNET RR 1 R97C140[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLK
83.319 -0.347 tSu 1 R97C140[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1

Path Statistics:

Clock Skew 0.311
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.355, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.837, 65.430%; tC2Q: 0.442, 34.570%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.666, 100.000%

Path24

Path Summary:

Slack 38.708
Data Arrival Time 44.618
Data Required Time 83.326
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
43.355 3.355 tNET FF 1 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
43.798 0.442 tC2Q FF 57 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
44.618 0.820 tNET FF 1 R94C144[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
80.000 80.000 active clock edge time
80.000 0.000 Inst3_CLKDIV_OUT
80.000 0.000 tCL RR 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
83.674 3.674 tNET RR 1 R94C144[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLK
83.326 -0.347 tSu 1 R94C144[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1

Path Statistics:

Clock Skew 0.318
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.355, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.820, 64.950%; tC2Q: 0.442, 35.050%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.674, 100.000%

Path25

Path Summary:

Slack 38.778
Data Arrival Time 44.543
Data Required Time 83.321
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_end_dly_s0
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
43.355 3.355 tNET FF 1 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
43.798 0.442 tC2Q FF 57 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
44.543 0.745 tNET FF 1 R96C140[0][A] gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
80.000 80.000 active clock edge time
80.000 0.000 Inst3_CLKDIV_OUT
80.000 0.000 tCL RR 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
83.669 3.669 tNET RR 1 R96C140[0][A] gw_gao_inst_0/u_la0_top/capture_end_dly_s0/CLK
83.321 -0.347 tSu 1 R96C140[0][A] gw_gao_inst_0/u_la0_top/capture_end_dly_s0

Path Statistics:

Clock Skew 0.313
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.355, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.745, 62.737%; tC2Q: 0.442, 37.263%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.669, 100.000%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 40.572
Data Arrival Time 41.951
Data Required Time 1.379
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
41.703 1.703 tNET FF 1 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
41.861 0.158 tC2Q FR 57 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
41.951 0.090 tNET RR 1 R94C143[3][A] gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.432 1.432 tNET RR 1 R94C143[3][A] gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLK
1.379 -0.053 tHld 1 R94C143[3][A] gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3

Path Statistics:

Clock Skew -0.271
Hold Relationship -40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.703, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.090, 36.290%; tC2Q: 0.158, 63.710%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.432, 100.000%

Path2

Path Summary:

Slack 40.572
Data Arrival Time 41.951
Data Required Time 1.379
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
41.703 1.703 tNET FF 1 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
41.861 0.158 tC2Q FR 57 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
41.951 0.090 tNET RR 1 R94C143[1][B] gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.432 1.432 tNET RR 1 R94C143[1][B] gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLK
1.379 -0.053 tHld 1 R94C143[1][B] gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1

Path Statistics:

Clock Skew -0.271
Hold Relationship -40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.703, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.090, 36.290%; tC2Q: 0.158, 63.710%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.432, 100.000%

Path3

Path Summary:

Slack 40.596
Data Arrival Time 41.975
Data Required Time 1.379
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_10_s1
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
41.703 1.703 tNET FF 1 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
41.861 0.158 tC2Q FR 57 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
41.975 0.114 tNET RR 1 R94C141[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_10_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.432 1.432 tNET RR 1 R94C141[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_10_s1/CLK
1.379 -0.053 tHld 1 R94C141[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_10_s1

Path Statistics:

Clock Skew -0.271
Hold Relationship -40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.703, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.114, 41.912%; tC2Q: 0.158, 58.088%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.432, 100.000%

Path4

Path Summary:

Slack 40.596
Data Arrival Time 41.975
Data Required Time 1.379
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/start_reg_s0
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
41.703 1.703 tNET FF 1 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
41.861 0.158 tC2Q FR 57 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
41.975 0.114 tNET RR 1 R94C141[2][B] gw_gao_inst_0/u_la0_top/start_reg_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.432 1.432 tNET RR 1 R94C141[2][B] gw_gao_inst_0/u_la0_top/start_reg_s0/CLK
1.379 -0.053 tHld 1 R94C141[2][B] gw_gao_inst_0/u_la0_top/start_reg_s0

Path Statistics:

Clock Skew -0.271
Hold Relationship -40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.703, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.114, 41.912%; tC2Q: 0.158, 58.088%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.432, 100.000%

Path5

Path Summary:

Slack 40.673
Data Arrival Time 42.049
Data Required Time 1.376
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
41.703 1.703 tNET FF 1 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
41.861 0.158 tC2Q FR 57 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
42.049 0.188 tNET RR 1 R96C143[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.429 1.429 tNET RR 1 R96C143[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLK
1.376 -0.053 tHld 1 R96C143[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1

Path Statistics:

Clock Skew -0.274
Hold Relationship -40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.703, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.188, 54.335%; tC2Q: 0.158, 45.665%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.429, 100.000%

Path6

Path Summary:

Slack 40.673
Data Arrival Time 42.049
Data Required Time 1.376
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
41.703 1.703 tNET FF 1 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
41.861 0.158 tC2Q FR 57 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
42.049 0.188 tNET RR 1 R96C143[0][B] gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.429 1.429 tNET RR 1 R96C143[0][B] gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLK
1.376 -0.053 tHld 1 R96C143[0][B] gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1

Path Statistics:

Clock Skew -0.274
Hold Relationship -40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.703, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.188, 54.335%; tC2Q: 0.158, 45.665%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.429, 100.000%

Path7

Path Summary:

Slack 40.673
Data Arrival Time 42.049
Data Required Time 1.376
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
41.703 1.703 tNET FF 1 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
41.861 0.158 tC2Q FR 57 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
42.049 0.188 tNET RR 1 R96C143[1][A] gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.429 1.429 tNET RR 1 R96C143[1][A] gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLK
1.376 -0.053 tHld 1 R96C143[1][A] gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0

Path Statistics:

Clock Skew -0.274
Hold Relationship -40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.703, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.188, 54.335%; tC2Q: 0.158, 45.665%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.429, 100.000%

Path8

Path Summary:

Slack 40.678
Data Arrival Time 42.063
Data Required Time 1.385
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
41.703 1.703 tNET FF 1 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
41.861 0.158 tC2Q FR 57 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
42.063 0.202 tNET RR 1 R93C142[0][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.438 1.438 tNET RR 1 R93C142[0][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLK
1.385 -0.053 tHld 1 R93C142[0][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1

Path Statistics:

Clock Skew -0.265
Hold Relationship -40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.703, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.202, 56.111%; tC2Q: 0.158, 43.889%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.438, 100.000%

Path9

Path Summary:

Slack 40.686
Data Arrival Time 42.067
Data Required Time 1.382
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
41.703 1.703 tNET FF 1 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
41.861 0.158 tC2Q FR 57 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
42.067 0.206 tNET RR 1 R95C142[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.434 1.434 tNET RR 1 R95C142[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLK
1.382 -0.053 tHld 1 R95C142[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1

Path Statistics:

Clock Skew -0.269
Hold Relationship -40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.703, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.206, 56.593%; tC2Q: 0.158, 43.407%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.434, 100.000%

Path10

Path Summary:

Slack 40.687
Data Arrival Time 42.067
Data Required Time 1.380
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
41.703 1.703 tNET FF 1 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
41.861 0.158 tC2Q FR 57 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
42.067 0.206 tNET RR 1 R96C142[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.433 1.433 tNET RR 1 R96C142[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLK
1.380 -0.053 tHld 1 R96C142[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1

Path Statistics:

Clock Skew -0.270
Hold Relationship -40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.703, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.206, 56.593%; tC2Q: 0.158, 43.407%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.433, 100.000%

Path11

Path Summary:

Slack 40.687
Data Arrival Time 42.067
Data Required Time 1.380
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_10_s1
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
41.703 1.703 tNET FF 1 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
41.861 0.158 tC2Q FR 57 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
42.067 0.206 tNET RR 1 R96C142[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_10_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.433 1.433 tNET RR 1 R96C142[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_10_s1/CLK
1.380 -0.053 tHld 1 R96C142[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_10_s1

Path Statistics:

Clock Skew -0.270
Hold Relationship -40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.703, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.206, 56.593%; tC2Q: 0.158, 43.407%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.433, 100.000%

Path12

Path Summary:

Slack 40.692
Data Arrival Time 42.069
Data Required Time 1.378
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
41.703 1.703 tNET FF 1 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
41.861 0.158 tC2Q FR 57 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
42.069 0.208 tNET RR 1 R95C143[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.431 1.431 tNET RR 1 R95C143[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/CLK
1.378 -0.053 tHld 1 R95C143[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5

Path Statistics:

Clock Skew -0.273
Hold Relationship -40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.703, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.208, 56.831%; tC2Q: 0.158, 43.169%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.431, 100.000%

Path13

Path Summary:

Slack 40.692
Data Arrival Time 42.069
Data Required Time 1.378
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
41.703 1.703 tNET FF 1 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
41.861 0.158 tC2Q FR 57 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
42.069 0.208 tNET RR 1 R95C143[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.431 1.431 tNET RR 1 R95C143[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK
1.378 -0.053 tHld 1 R95C143[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1

Path Statistics:

Clock Skew -0.273
Hold Relationship -40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.703, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.208, 56.831%; tC2Q: 0.158, 43.169%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.431, 100.000%

Path14

Path Summary:

Slack 40.692
Data Arrival Time 42.069
Data Required Time 1.378
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
41.703 1.703 tNET FF 1 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
41.861 0.158 tC2Q FR 57 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
42.069 0.208 tNET RR 1 R95C143[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.431 1.431 tNET RR 1 R95C143[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK
1.378 -0.053 tHld 1 R95C143[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1

Path Statistics:

Clock Skew -0.273
Hold Relationship -40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.703, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.208, 56.831%; tC2Q: 0.158, 43.169%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.431, 100.000%

Path15

Path Summary:

Slack 40.692
Data Arrival Time 42.069
Data Required Time 1.378
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
41.703 1.703 tNET FF 1 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
41.861 0.158 tC2Q FR 57 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
42.069 0.208 tNET RR 1 R95C143[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.431 1.431 tNET RR 1 R95C143[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK
1.378 -0.053 tHld 1 R95C143[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1

Path Statistics:

Clock Skew -0.273
Hold Relationship -40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.703, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.208, 56.831%; tC2Q: 0.158, 43.169%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.431, 100.000%

Path16

Path Summary:

Slack 40.692
Data Arrival Time 42.069
Data Required Time 1.378
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
41.703 1.703 tNET FF 1 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
41.861 0.158 tC2Q FR 57 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
42.069 0.208 tNET RR 1 R95C143[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.431 1.431 tNET RR 1 R95C143[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/CLK
1.378 -0.053 tHld 1 R95C143[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1

Path Statistics:

Clock Skew -0.273
Hold Relationship -40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.703, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.208, 56.831%; tC2Q: 0.158, 43.169%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.431, 100.000%

Path17

Path Summary:

Slack 40.699
Data Arrival Time 42.075
Data Required Time 1.376
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
41.703 1.703 tNET FF 1 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
41.861 0.158 tC2Q FR 57 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
42.075 0.214 tNET RR 1 R96C145[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.429 1.429 tNET RR 1 R96C145[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
1.376 -0.053 tHld 1 R96C145[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1

Path Statistics:

Clock Skew -0.274
Hold Relationship -40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.703, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.214, 57.527%; tC2Q: 0.158, 42.473%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.429, 100.000%

Path18

Path Summary:

Slack 40.699
Data Arrival Time 42.075
Data Required Time 1.376
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
41.703 1.703 tNET FF 1 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
41.861 0.158 tC2Q FR 57 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
42.075 0.214 tNET RR 1 R96C145[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.429 1.429 tNET RR 1 R96C145[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK
1.376 -0.053 tHld 1 R96C145[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1

Path Statistics:

Clock Skew -0.274
Hold Relationship -40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.703, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.214, 57.527%; tC2Q: 0.158, 42.473%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.429, 100.000%

Path19

Path Summary:

Slack 40.703
Data Arrival Time 42.075
Data Required Time 1.372
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
41.703 1.703 tNET FF 1 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
41.861 0.158 tC2Q FR 57 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
42.075 0.214 tNET RR 1 R96C144[0][B] gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.425 1.425 tNET RR 1 R96C144[0][B] gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLK
1.372 -0.053 tHld 1 R96C144[0][B] gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1

Path Statistics:

Clock Skew -0.278
Hold Relationship -40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.703, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.214, 57.527%; tC2Q: 0.158, 42.473%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.425, 100.000%

Path20

Path Summary:

Slack 40.703
Data Arrival Time 42.075
Data Required Time 1.372
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
41.703 1.703 tNET FF 1 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
41.861 0.158 tC2Q FR 57 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
42.075 0.214 tNET RR 1 R96C144[1][B] gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.425 1.425 tNET RR 1 R96C144[1][B] gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLK
1.372 -0.053 tHld 1 R96C144[1][B] gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1

Path Statistics:

Clock Skew -0.278
Hold Relationship -40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.703, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.214, 57.527%; tC2Q: 0.158, 42.473%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.425, 100.000%

Path21

Path Summary:

Slack 40.703
Data Arrival Time 42.075
Data Required Time 1.372
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
41.703 1.703 tNET FF 1 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
41.861 0.158 tC2Q FR 57 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
42.075 0.214 tNET RR 1 R96C144[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.425 1.425 tNET RR 1 R96C144[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLK
1.372 -0.053 tHld 1 R96C144[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1

Path Statistics:

Clock Skew -0.278
Hold Relationship -40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.703, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.214, 57.527%; tC2Q: 0.158, 42.473%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.425, 100.000%

Path22

Path Summary:

Slack 40.770
Data Arrival Time 42.149
Data Required Time 1.379
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
41.703 1.703 tNET FF 1 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
41.861 0.158 tC2Q FR 57 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
42.149 0.288 tNET RR 1 R94C139[3][B] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.432 1.432 tNET RR 1 R94C139[3][B] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLK
1.379 -0.053 tHld 1 R94C139[3][B] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0

Path Statistics:

Clock Skew -0.271
Hold Relationship -40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.703, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.288, 64.574%; tC2Q: 0.158, 35.426%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.432, 100.000%

Path23

Path Summary:

Slack 40.770
Data Arrival Time 42.149
Data Required Time 1.379
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
41.703 1.703 tNET FF 1 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
41.861 0.158 tC2Q FR 57 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
42.149 0.288 tNET RR 1 R94C139[0][B] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.432 1.432 tNET RR 1 R94C139[0][B] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLK
1.379 -0.053 tHld 1 R94C139[0][B] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0

Path Statistics:

Clock Skew -0.271
Hold Relationship -40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.703, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.288, 64.574%; tC2Q: 0.158, 35.426%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.432, 100.000%

Path24

Path Summary:

Slack 40.770
Data Arrival Time 42.149
Data Required Time 1.379
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_0_s0
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
41.703 1.703 tNET FF 1 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
41.861 0.158 tC2Q FR 57 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
42.149 0.288 tNET RR 1 R94C139[2][B] gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.432 1.432 tNET RR 1 R94C139[2][B] gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_0_s0/CLK
1.379 -0.053 tHld 1 R94C139[2][B] gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_0_s0

Path Statistics:

Clock Skew -0.271
Hold Relationship -40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.703, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.288, 64.574%; tC2Q: 0.158, 35.426%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.432, 100.000%

Path25

Path Summary:

Slack 40.770
Data Arrival Time 42.149
Data Required Time 1.379
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
41.703 1.703 tNET FF 1 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
41.861 0.158 tC2Q FR 57 R94C143[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
42.149 0.288 tNET RR 1 R94C139[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 641 BOTTOMSIDE[7] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.432 1.432 tNET RR 1 R94C139[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLK
1.379 -0.053 tHld 1 R94C139[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0

Path Statistics:

Clock Skew -0.271
Hold Relationship -40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.703, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.288, 64.574%; tC2Q: 0.158, 35.426%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.432, 100.000%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack: 3.402
Actual Width: 3.652
Required Width: 0.250
Type: High Pulse Width
Clock: HS_CLK
Objects: MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_2_s0

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 HS_CLK
0.000 0.000 tCL RR MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
2.386 2.386 tNET RR MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_2_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 HS_CLK
5.000 0.000 tCL FF MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
6.038 1.038 tNET FF MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_2_s0/CLK

MPW2

MPW Summary:

Slack: 3.402
Actual Width: 3.652
Required Width: 0.250
Type: High Pulse Width
Clock: HS_CLK
Objects: MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 HS_CLK
0.000 0.000 tCL RR MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
2.386 2.386 tNET RR MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 HS_CLK
5.000 0.000 tCL FF MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
6.038 1.038 tNET FF MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0/CLK

MPW3

MPW Summary:

Slack: 3.402
Actual Width: 3.652
Required Width: 0.250
Type: High Pulse Width
Clock: HS_CLK
Objects: MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 HS_CLK
0.000 0.000 tCL RR MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
2.386 2.386 tNET RR MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 HS_CLK
5.000 0.000 tCL FF MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
6.038 1.038 tNET FF MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/CLK

MPW4

MPW Summary:

Slack: 3.402
Actual Width: 3.652
Required Width: 0.250
Type: High Pulse Width
Clock: HS_CLK
Objects: MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 HS_CLK
0.000 0.000 tCL RR MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
2.386 2.386 tNET RR MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 HS_CLK
5.000 0.000 tCL FF MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
6.038 1.038 tNET FF MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0/CLK

MPW5

MPW Summary:

Slack: 3.523
Actual Width: 3.773
Required Width: 0.250
Type: Low Pulse Width
Clock: HS_CLK
Objects: MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_2_s0

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 HS_CLK
5.000 0.000 tCL FF MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
7.127 2.127 tNET FF MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_2_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 HS_CLK
10.000 0.000 tCL RR MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
10.900 0.900 tNET RR MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_2_s0/CLK

MPW6

MPW Summary:

Slack: 3.523
Actual Width: 3.773
Required Width: 0.250
Type: Low Pulse Width
Clock: HS_CLK
Objects: MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 HS_CLK
5.000 0.000 tCL FF MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
7.127 2.127 tNET FF MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 HS_CLK
10.000 0.000 tCL RR MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
10.900 0.900 tNET RR MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0/CLK

MPW7

MPW Summary:

Slack: 3.523
Actual Width: 3.773
Required Width: 0.250
Type: Low Pulse Width
Clock: HS_CLK
Objects: MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 HS_CLK
5.000 0.000 tCL FF MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
7.127 2.127 tNET FF MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 HS_CLK
10.000 0.000 tCL RR MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
10.900 0.900 tNET RR MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/CLK

MPW8

MPW Summary:

Slack: 3.523
Actual Width: 3.773
Required Width: 0.250
Type: Low Pulse Width
Clock: HS_CLK
Objects: MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 HS_CLK
5.000 0.000 tCL FF MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
7.127 2.127 tNET FF MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 HS_CLK
10.000 0.000 tCL RR MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
10.900 0.900 tNET RR MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0/CLK

MPW9

MPW Summary:

Slack: 19.523
Actual Width: 20.523
Required Width: 1.000
Type: Low Pulse Width
Clock: tck_pad_i
Objects: gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Late clock Path:

AT DELAY TYPE RF NODE
25.000 0.000 active clock edge time
25.000 0.000 tck_pad_i
25.000 0.000 tCL FF gw_gao_inst_0/tck_ibuf/I
25.688 0.688 tINS FF gw_gao_inst_0/tck_ibuf/O
25.688 0.000 tNET FF gw_gao_inst_0/u_gw_jtag/tck_pad_i
26.375 0.688 tINS FF gw_gao_inst_0/u_gw_jtag/tck_o
33.923 7.548 tNET FF gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKB

Early clock Path:

AT DELAY TYPE RF NODE
50.000 0.000 active clock edge time
50.000 0.000 tck_pad_i
50.000 0.000 tCL RR gw_gao_inst_0/tck_ibuf/I
50.675 0.675 tINS RR gw_gao_inst_0/tck_ibuf/O
50.675 0.000 tNET RR gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.351 0.675 tINS RR gw_gao_inst_0/u_gw_jtag/tck_o
54.446 3.095 tNET RR gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKB

MPW10

MPW Summary:

Slack: 19.523
Actual Width: 20.523
Required Width: 1.000
Type: Low Pulse Width
Clock: tck_pad_i
Objects: gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s

Late clock Path:

AT DELAY TYPE RF NODE
25.000 0.000 active clock edge time
25.000 0.000 tck_pad_i
25.000 0.000 tCL FF gw_gao_inst_0/tck_ibuf/I
25.688 0.688 tINS FF gw_gao_inst_0/tck_ibuf/O
25.688 0.000 tNET FF gw_gao_inst_0/u_gw_jtag/tck_pad_i
26.375 0.688 tINS FF gw_gao_inst_0/u_gw_jtag/tck_o
33.923 7.548 tNET FF gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s/CLKA

Early clock Path:

AT DELAY TYPE RF NODE
50.000 0.000 active clock edge time
50.000 0.000 tck_pad_i
50.000 0.000 tCL RR gw_gao_inst_0/tck_ibuf/I
50.675 0.675 tINS RR gw_gao_inst_0/tck_ibuf/O
50.675 0.000 tNET RR gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.351 0.675 tINS RR gw_gao_inst_0/u_gw_jtag/tck_o
54.446 3.095 tNET RR gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s/CLKA

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT NET NAME WORST SLACK MAX DELAY
641 clk_byte_out 73.063 3.695
548 GND 3.105 1.004
252 control0[0] 17.589 8.042
57 rst_ao 38.419 1.111
55 n20_3 44.893 2.261
46 ready_d 76.849 2.918
45 n1001_5 43.076 1.568
38 op_reg_en 42.339 1.365
35 data_out_shift_reg_32_7 44.713 0.625
32 crc_28_7 44.634 0.620

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC ROUTE CONGESTIONS
R96C143 65.28%
R96C144 65.28%
R94C106 59.72%
R96C142 59.72%
R96C148 59.72%
R95C153 59.72%
R95C166 59.72%
R97C143 58.33%
R96C131 58.33%
R95C164 58.33%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type State Detail Command
TC_CLOCK Actived create_clock -name U0_IB -period 10 -waveform {0 5} [get_pins {MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/I}]
TC_CLOCK Actived create_clock -name U3_CLKDIV -period 800 -waveform {0 400} [get_pins {U3_CLKDIV/CLKOUT}]
TC_CLOCK Actived create_clock -name PLL_0 -period 50 -waveform {0 25} [get_pins {PLL_mipi_tx/CLKOUT0}]
TC_CLOCK Actived create_clock -name PLL_1 -period 50 -waveform {0 25} [get_pins {PLL_mipi_tx/CLKOUT1}]
TC_CLOCK Actived create_clock -name HS_CLK -period 10 -waveform {0 5} [get_nets {MIPI_RX_Advance_Top/DPHY_RX_INST/HS_CLK}]
TC_CLOCK Actived create_clock -name tck_pad_i -period 50 -waveform {0 25} [get_ports {tck_pad_i}]
TC_CLOCK Actived create_clock -name sys_clk -period 20 -waveform {0 10} [get_ports {clkx2x4}]
TC_CLOCK Actived create_clock -name Inst3_CLKDIV_OUT -period 80 -waveform {0 40} [get_pins {MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT}]
TC_CLOCK_GROUP Actived set_clock_groups -asynchronous -group [get_clocks {PLL_0 PLL_1}] -group [get_clocks {tck_pad_i}] -group [get_clocks {Inst3_CLKDIV_OUT}] -group [get_clocks {HS_CLK}] -group [get_clocks {U3_CLKDIV}]