Timing Messages

Report Title Timing Analysis Report
Design File E:\myWork\IP\releaseVerify\version\1.9.10.03\Gowin_MIPI_DPHY_Advance_RefDesign\MIPI_RefDesign_5a25_LVDS\MIPI_RefDesign\impl\gwsynthesis\MIPI_RefDesign.vg
Physical Constraints File E:\myWork\IP\releaseVerify\version\1.9.10.03\Gowin_MIPI_DPHY_Advance_RefDesign\MIPI_RefDesign_5a25_LVDS\MIPI_RefDesign\src\mipi.cst
Timing Constraint File E:\myWork\IP\releaseVerify\version\1.9.10.03\Gowin_MIPI_DPHY_Advance_RefDesign\MIPI_RefDesign_5a25_LVDS\MIPI_RefDesign\src\mipi.sdc
Tool Version V1.9.10.03 (64-bit)
Part Number GW5A-LV25UG324ES
Device GW5A-25
Device Version A
Created Time Thu Oct 24 14:08:50 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model Slow 0.855V 0C ES
Hold Delay Model Fast 0.945V 85C ES
Numbers of Paths Analyzed 2299
Numbers of Endpoints Analyzed 3930
Numbers of Falling Endpoints 11
Numbers of Setup Violated Endpoints 0
Numbers of Hold Violated Endpoints 0

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Objects
1 U0_IB Base 10.000 100.000 0.000 5.000 MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/I
2 sys_clk Base 20.000 50.000 0.000 10.000 clkx2x4
3 PLL_0 Base 100.000 10.000 0.000 50.000 PLLA_mipi_tx/CLKOUT0
4 PLL_1 Base 100.000 10.000 0.000 50.000 PLLA_mipi_tx/CLKOUT1
5 HS_CLK Base 10.000 100.000 0.000 5.000 MIPI_RX_Advance_Top/DPHY_RX_INST/HS_CLK GND
6 Inst3_CLKDIV_OUT Base 80.000 12.500 0.000 40.000 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
7 U3_CLKDIV Base 800.000 1.250 0.000 400.000 U3_CLKDIV/CLKOUT
8 tck_pad_i Base 50.000 20.000 0.000 25.000 tck_pad_i

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 HS_CLK 100.000(MHz) 142.166(MHz) 2 TOP
2 Inst3_CLKDIV_OUT 12.500(MHz) 133.522(MHz) 5 TOP
3 U3_CLKDIV 1.250(MHz) 171.776(MHz) 1 TOP
4 tck_pad_i 20.000(MHz) 71.415(MHz) 6 TOP

No timing paths to get frequency of U0_IB!

No timing paths to get frequency of sys_clk!

No timing paths to get frequency of PLL_0!

No timing paths to get frequency of PLL_1!

Total Negative Slack Summary:

Clock Name Analysis Type Endpoints TNS Number of Endpoints
U0_IB Setup 0.000 0
U0_IB Hold 0.000 0
sys_clk Setup 0.000 0
sys_clk Hold 0.000 0
PLL_0 Setup 0.000 0
PLL_0 Hold 0.000 0
PLL_1 Setup 0.000 0
PLL_1 Hold 0.000 0
HS_CLK Setup 0.000 0
HS_CLK Hold 0.000 0
Inst3_CLKDIV_OUT Setup 0.000 0
Inst3_CLKDIV_OUT Hold 0.000 0
U3_CLKDIV Setup 0.000 0
U3_CLKDIV Hold 0.000 0
tck_pad_i Setup 0.000 0
tck_pad_i Hold 0.000 0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 1.483 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/LUT4_0/I0 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CEN HS_CLK:[R] HS_CLK:[F] 5.000 0.000 3.335
2 8.090 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/Q MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0/CE HS_CLK:[R] HS_CLK:[R] 10.000 0.000 1.599
3 8.090 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/Q MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/CE HS_CLK:[R] HS_CLK:[R] 10.000 0.000 1.599
4 8.090 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/Q MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0/CE HS_CLK:[R] HS_CLK:[R] 10.000 0.000 1.599
5 8.090 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/Q MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_2_s0/CE HS_CLK:[R] HS_CLK:[R] 10.000 0.000 1.599
6 9.134 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_2_s0/Q MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/D HS_CLK:[R] HS_CLK:[R] 10.000 0.000 0.803
7 9.151 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/Q MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0/D HS_CLK:[R] HS_CLK:[R] 10.000 0.000 0.785
8 4.637 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_3/CALIB MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_3/CALIB HS_CLK:[F] HS_CLK:[R] 5.000 -0.184 0.548
9 4.884 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CALIB MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CALIB HS_CLK:[F] HS_CLK:[R] 5.000 -0.184 0.300
10 4.893 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_0/CALIB MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_0/CALIB HS_CLK:[F] HS_CLK:[R] 5.000 -0.184 0.291
11 4.893 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_1/CALIB MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_1/CALIB HS_CLK:[F] HS_CLK:[R] 5.000 -0.184 0.291
12 4.893 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_2/CALIB MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_2/CALIB HS_CLK:[F] HS_CLK:[R] 5.000 -0.184 0.291
13 17.999 gw_gao_inst_0/u_la0_top/module_state_1_s0/Q gw_gao_inst_0/u_la0_top/internal_reg_force_triger_s1/CE tck_pad_i:[R] tck_pad_i:[F] 25.000 -0.054 6.799
14 17.999 gw_gao_inst_0/u_la0_top/module_state_1_s0/Q gw_gao_inst_0/u_la0_top/internal_reg_start_s1/CE tck_pad_i:[R] tck_pad_i:[F] 25.000 -0.054 6.799
15 19.045 gw_gao_inst_0/u_la0_top/module_state_1_s0/Q gw_gao_inst_0/u_la0_top/internal_reg_force_triger_s1/D tck_pad_i:[R] tck_pad_i:[F] 25.000 -0.054 6.000
16 19.045 gw_gao_inst_0/u_la0_top/module_state_1_s0/Q gw_gao_inst_0/u_la0_top/internal_reg_start_s1/D tck_pad_i:[R] tck_pad_i:[F] 25.000 -0.054 6.000
17 41.421 gw_gao_inst_0/u_la0_top/module_state_1_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CEB tck_pad_i:[R] tck_pad_i:[R] 50.000 -0.033 8.521
18 21.052 gw_gao_inst_0/u_la0_top/internal_reg_start_s1/Q gw_gao_inst_0/u_la0_top/data_out_shift_reg_0_s1/D tck_pad_i:[F] tck_pad_i:[R] 25.000 0.013 3.871
19 42.157 gw_gao_inst_0/u_la0_top/module_state_1_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CEB tck_pad_i:[R] tck_pad_i:[R] 50.000 -0.042 7.794
20 42.494 gw_gao_inst_0/u_la0_top/module_state_1_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CEB tck_pad_i:[R] tck_pad_i:[R] 50.000 -0.024 7.439
21 42.539 gw_gao_inst_0/u_la0_top/module_state_1_s0/Q gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0/CE tck_pad_i:[R] tck_pad_i:[R] 50.000 -0.009 7.159
22 42.539 gw_gao_inst_0/u_la0_top/module_state_1_s0/Q gw_gao_inst_0/u_la0_top/capture_mem_addr_max_9_s0/CE tck_pad_i:[R] tck_pad_i:[R] 50.000 -0.009 7.159
23 42.539 gw_gao_inst_0/u_la0_top/module_state_1_s0/Q gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/CE tck_pad_i:[R] tck_pad_i:[R] 50.000 -0.009 7.159
24 42.733 gw_gao_inst_0/u_la0_top/module_state_1_s0/Q gw_gao_inst_0/u_la0_top/capture_mem_addr_max_0_s0/CE tck_pad_i:[R] tck_pad_i:[R] 50.000 -0.015 6.971
25 42.733 gw_gao_inst_0/u_la0_top/module_state_1_s0/Q gw_gao_inst_0/u_la0_top/capture_mem_addr_max_1_s0/CE tck_pad_i:[R] tck_pad_i:[R] 50.000 -0.015 6.971

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.012 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_0/CALIB MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_0/CALIB HS_CLK:[R] HS_CLK:[R] 0.000 -0.159 0.171
2 0.012 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_1/CALIB MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_1/CALIB HS_CLK:[R] HS_CLK:[R] 0.000 -0.159 0.171
3 0.012 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_2/CALIB MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_2/CALIB HS_CLK:[R] HS_CLK:[R] 0.000 -0.159 0.171
4 0.014 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CALIB MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CALIB HS_CLK:[R] HS_CLK:[R] 0.000 -0.159 0.173
5 0.185 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_3/CALIB MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_3/CALIB HS_CLK:[R] HS_CLK:[R] 0.000 -0.159 0.344
6 0.216 gw_gao_inst_0/u_la0_top/expression0_data_s0/Q gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s/DI[0] tck_pad_i:[R] tck_pad_i:[R] 0.000 0.010 0.243
7 0.275 MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/lane0_cnt_0_s1/Q MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/lane0_cnt_0_s1/D Inst3_CLKDIV_OUT:[R] Inst3_CLKDIV_OUT:[R] 0.000 0.000 0.300
8 0.275 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/D Inst3_CLKDIV_OUT:[R] Inst3_CLKDIV_OUT:[R] 0.000 0.000 0.300
9 0.275 gw_gao_inst_0/u_la0_top/word_count_7_s0/Q gw_gao_inst_0/u_la0_top/word_count_7_s0/D tck_pad_i:[R] tck_pad_i:[R] 0.000 0.000 0.300
10 0.275 gw_gao_inst_0/u_la0_top/word_count_11_s0/Q gw_gao_inst_0/u_la0_top/word_count_11_s0/D tck_pad_i:[R] tck_pad_i:[R] 0.000 0.000 0.300
11 0.275 gw_gao_inst_0/u_la0_top/address_counter_2_s0/Q gw_gao_inst_0/u_la0_top/address_counter_2_s0/D tck_pad_i:[R] tck_pad_i:[R] 0.000 0.000 0.300
12 0.275 gw_gao_inst_0/u_la0_top/address_counter_4_s0/Q gw_gao_inst_0/u_la0_top/address_counter_4_s0/D tck_pad_i:[R] tck_pad_i:[R] 0.000 0.000 0.300
13 0.275 gw_gao_inst_0/u_la0_top/address_counter_10_s0/Q gw_gao_inst_0/u_la0_top/address_counter_10_s0/D tck_pad_i:[R] tck_pad_i:[R] 0.000 0.000 0.300
14 0.275 MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/lane0_cnt_2_s0/Q MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/lane0_cnt_2_s0/D Inst3_CLKDIV_OUT:[R] Inst3_CLKDIV_OUT:[R] 0.000 0.000 0.300
15 0.278 gw_gao_inst_0/u_la0_top/word_count_1_s0/Q gw_gao_inst_0/u_la0_top/word_count_1_s0/D tck_pad_i:[R] tck_pad_i:[R] 0.000 0.000 0.303
16 0.278 gw_gao_inst_0/u_la0_top/word_count_4_s0/Q gw_gao_inst_0/u_la0_top/word_count_4_s0/D tck_pad_i:[R] tck_pad_i:[R] 0.000 0.000 0.303
17 0.278 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/D Inst3_CLKDIV_OUT:[R] Inst3_CLKDIV_OUT:[R] 0.000 0.000 0.303
18 0.278 gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s1/Q gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s1/D Inst3_CLKDIV_OUT:[R] Inst3_CLKDIV_OUT:[R] 0.000 0.000 0.303
19 0.278 gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/Q gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/D Inst3_CLKDIV_OUT:[R] Inst3_CLKDIV_OUT:[R] 0.000 0.000 0.303
20 0.281 gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/Q gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/D Inst3_CLKDIV_OUT:[R] Inst3_CLKDIV_OUT:[R] 0.000 0.000 0.306
21 0.281 gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/Q gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/D Inst3_CLKDIV_OUT:[R] Inst3_CLKDIV_OUT:[R] 0.000 0.000 0.306
22 0.281 MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/lane2_cnt_0_s1/Q MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/lane2_cnt_0_s1/D Inst3_CLKDIV_OUT:[R] Inst3_CLKDIV_OUT:[R] 0.000 0.000 0.306
23 0.296 u_ROM549x17/addr_1_s0/Q u_ROM549x17/dout_rom_1_s/AD[5] U3_CLKDIV:[R] U3_CLKDIV:[R] 0.000 0.010 0.321
24 0.296 u_ROM549x17/addr_0_s0/Q u_ROM549x17/dout_rom_1_s/AD[4] U3_CLKDIV:[R] U3_CLKDIV:[R] 0.000 0.010 0.321
25 0.306 gw_gao_inst_0/u_la0_top/expression0_addr_0_s0/Q gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s/ADA[0] tck_pad_i:[R] tck_pad_i:[R] 0.000 0.010 0.333

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 36.556 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] 40.000 -0.005 3.101
2 36.556 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] 40.000 -0.005 3.101
3 36.556 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] 40.000 -0.005 3.101
4 36.556 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/triger_s0/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] 40.000 -0.005 3.101
5 36.556 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/start_reg_s0/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] 40.000 -0.005 3.101
6 36.756 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] 40.000 -0.005 2.901
7 36.766 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] 40.000 -0.014 2.901
8 36.766 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] 40.000 -0.014 2.901
9 36.766 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] 40.000 -0.014 2.901
10 36.766 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] 40.000 -0.014 2.901
11 36.913 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] 40.000 -0.020 2.759
12 37.006 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s1/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] 40.000 -0.018 2.664
13 37.006 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] 40.000 -0.018 2.664
14 37.006 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] 40.000 -0.018 2.664
15 37.006 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] 40.000 -0.018 2.664
16 37.074 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] 40.000 -0.012 2.591
17 37.074 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] 40.000 -0.012 2.591
18 37.274 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] 40.000 -0.012 2.391
19 37.274 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] 40.000 -0.012 2.391
20 37.274 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] 40.000 -0.012 2.391
21 37.276 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] 40.000 -0.022 2.399
22 37.276 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_10_s1/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] 40.000 -0.022 2.399
23 37.283 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] 40.000 -0.022 2.391
24 37.283 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] 40.000 -0.022 2.391
25 37.392 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_0_s0/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] 40.000 -0.028 2.287

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 40.414 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] -40.000 0.009 0.352
2 40.563 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] -40.000 -0.018 0.528
3 40.563 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] -40.000 -0.018 0.528
4 40.575 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] -40.000 0.011 0.511
5 40.659 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] -40.000 -0.022 0.628
6 40.659 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] -40.000 -0.022 0.628
7 40.659 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] -40.000 -0.022 0.628
8 40.663 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] -40.000 -0.016 0.626
9 40.663 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_10_s1/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] -40.000 -0.016 0.626
10 40.675 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] -40.000 0.007 0.615
11 40.675 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] -40.000 0.007 0.615
12 40.675 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] -40.000 0.007 0.615
13 40.675 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] -40.000 0.007 0.615
14 40.679 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] -40.000 0.011 0.615
15 40.679 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] -40.000 0.011 0.615
16 40.679 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] -40.000 0.011 0.615
17 40.771 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] -40.000 -0.016 0.734
18 40.818 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] -40.000 -0.003 0.768
19 40.818 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] -40.000 -0.003 0.768
20 40.861 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] -40.000 -0.020 0.828
21 40.861 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] -40.000 -0.020 0.828
22 41.002 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] -40.000 -0.018 0.967
23 41.048 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] -40.000 -0.008 1.003
24 41.048 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] -40.000 -0.008 1.003
25 41.048 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR Inst3_CLKDIV_OUT:[F] Inst3_CLKDIV_OUT:[R] -40.000 -0.008 1.003

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number Slack Actual Width Required Width Type Clock Objects
1 3.507 3.757 0.250 Low Pulse Width HS_CLK MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_2_s0
2 3.507 3.757 0.250 Low Pulse Width HS_CLK MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0
3 3.507 3.757 0.250 Low Pulse Width HS_CLK MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0
4 3.507 3.757 0.250 Low Pulse Width HS_CLK MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0
5 3.512 3.762 0.250 High Pulse Width HS_CLK MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_2_s0
6 3.512 3.762 0.250 High Pulse Width HS_CLK MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0
7 3.512 3.762 0.250 High Pulse Width HS_CLK MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0
8 3.512 3.762 0.250 High Pulse Width HS_CLK MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0
9 22.199 23.199 1.000 Low Pulse Width tck_pad_i gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
10 22.205 23.205 1.000 Low Pulse Width tck_pad_i gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 1.483
Data Arrival Time 3.335
Data Required Time 4.818
From MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/LUT4_0
To MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN
Launch Clk HS_CLK:[R]
Latch Clk HS_CLK:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 HS_CLK
0.000 0.000 tCL RR 460 - GND_cZ/G
0.000 0.000 tNET RR 1 R20C32[0][B] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/LUT4_0/I0
0.526 0.526 tINS RR 1 R20C32[0][B] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/LUT4_0/F
3.335 2.809 tNET RR 1 - MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CEN

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 HS_CLK
5.000 0.000 tCL FF 5 IOL3 MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
5.000 0.000 tNET FF 3 - MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CLKIN
4.818 -0.182 tSu 1 - MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN

Path Statistics:

Clock Skew 0.000
Setup Relationship 5.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.526, 15.780%; route: 2.809, 84.220%; tC2Q: 0.000, 0.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path2

Path Summary:

Slack 8.090
Data Arrival Time 3.564
Data Required Time 11.654
From MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0
To MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0
Launch Clk HS_CLK:[R]
Latch Clk HS_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 HS_CLK
0.000 0.000 tCL RR 5 IOL3 MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
1.966 1.966 tNET RR 1 R20C32[2][B] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/CLK
2.348 0.382 tC2Q RR 2 R20C32[2][B] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/Q
2.488 0.140 tNET RR 1 R20C32[3][A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/LUT4_1/I2
2.753 0.265 tINS RR 4 R20C32[3][A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/LUT4_1/F
3.564 0.811 tNET RR 1 R20C32[2][A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 HS_CLK
10.000 0.000 tCL RR 5 IOL3 MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
11.966 1.966 tNET RR 1 R20C32[2][A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0/CLK
11.654 -0.311 tSu 1 R20C32[2][A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.966, 100.000%
Arrival Data Path Delay cell: 0.265, 16.575%; route: 0.951, 59.500%; tC2Q: 0.382, 23.925%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.966, 100.000%

Path3

Path Summary:

Slack 8.090
Data Arrival Time 3.564
Data Required Time 11.654
From MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0
To MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0
Launch Clk HS_CLK:[R]
Latch Clk HS_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 HS_CLK
0.000 0.000 tCL RR 5 IOL3 MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
1.966 1.966 tNET RR 1 R20C32[2][B] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/CLK
2.348 0.382 tC2Q RR 2 R20C32[2][B] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/Q
2.488 0.140 tNET RR 1 R20C32[3][A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/LUT4_1/I2
2.753 0.265 tINS RR 4 R20C32[3][A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/LUT4_1/F
3.564 0.811 tNET RR 1 R20C32[2][B] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 HS_CLK
10.000 0.000 tCL RR 5 IOL3 MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
11.966 1.966 tNET RR 1 R20C32[2][B] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/CLK
11.654 -0.311 tSu 1 R20C32[2][B] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.966, 100.000%
Arrival Data Path Delay cell: 0.265, 16.575%; route: 0.951, 59.500%; tC2Q: 0.382, 23.925%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.966, 100.000%

Path4

Path Summary:

Slack 8.090
Data Arrival Time 3.564
Data Required Time 11.654
From MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0
To MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0
Launch Clk HS_CLK:[R]
Latch Clk HS_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 HS_CLK
0.000 0.000 tCL RR 5 IOL3 MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
1.966 1.966 tNET RR 1 R20C32[2][B] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/CLK
2.348 0.382 tC2Q RR 2 R20C32[2][B] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/Q
2.488 0.140 tNET RR 1 R20C32[3][A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/LUT4_1/I2
2.753 0.265 tINS RR 4 R20C32[3][A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/LUT4_1/F
3.564 0.811 tNET RR 1 R20C32[1][B] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 HS_CLK
10.000 0.000 tCL RR 5 IOL3 MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
11.966 1.966 tNET RR 1 R20C32[1][B] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0/CLK
11.654 -0.311 tSu 1 R20C32[1][B] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.966, 100.000%
Arrival Data Path Delay cell: 0.265, 16.575%; route: 0.951, 59.500%; tC2Q: 0.382, 23.925%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.966, 100.000%

Path5

Path Summary:

Slack 8.090
Data Arrival Time 3.564
Data Required Time 11.654
From MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0
To MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_2_s0
Launch Clk HS_CLK:[R]
Latch Clk HS_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 HS_CLK
0.000 0.000 tCL RR 5 IOL3 MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
1.966 1.966 tNET RR 1 R20C32[2][B] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/CLK
2.348 0.382 tC2Q RR 2 R20C32[2][B] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/Q
2.488 0.140 tNET RR 1 R20C32[3][A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/LUT4_1/I2
2.753 0.265 tINS RR 4 R20C32[3][A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/LUT4_1/F
3.564 0.811 tNET RR 1 R20C32[1][A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_2_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 HS_CLK
10.000 0.000 tCL RR 5 IOL3 MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
11.966 1.966 tNET RR 1 R20C32[1][A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_2_s0/CLK
11.654 -0.311 tSu 1 R20C32[1][A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_2_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.966, 100.000%
Arrival Data Path Delay cell: 0.265, 16.575%; route: 0.951, 59.500%; tC2Q: 0.382, 23.925%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.966, 100.000%

Path6

Path Summary:

Slack 9.134
Data Arrival Time 2.768
Data Required Time 11.902
From MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_2_s0
To MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0
Launch Clk HS_CLK:[R]
Latch Clk HS_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 HS_CLK
0.000 0.000 tCL RR 5 IOL3 MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
1.966 1.966 tNET RR 1 R20C32[1][A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_2_s0/CLK
2.348 0.382 tC2Q RR 1 R20C32[1][A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_2_s0/Q
2.768 0.420 tNET RR 1 R20C32[2][B] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 HS_CLK
10.000 0.000 tCL RR 5 IOL3 MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
11.966 1.966 tNET RR 1 R20C32[2][B] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/CLK
11.902 -0.064 tSu 1 R20C32[2][B] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.966, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.420, 52.336%; tC2Q: 0.382, 47.664%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.966, 100.000%

Path7

Path Summary:

Slack 9.151
Data Arrival Time 2.751
Data Required Time 11.902
From MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0
To MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0
Launch Clk HS_CLK:[R]
Latch Clk HS_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 HS_CLK
0.000 0.000 tCL RR 5 IOL3 MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
1.966 1.966 tNET RR 1 R20C32[2][B] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/CLK
2.348 0.382 tC2Q RR 2 R20C32[2][B] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/Q
2.751 0.402 tNET RR 1 R20C32[2][A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 HS_CLK
10.000 0.000 tCL RR 5 IOL3 MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
11.966 1.966 tNET RR 1 R20C32[2][A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0/CLK
11.902 -0.064 tSu 1 R20C32[2][A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.966, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.402, 51.274%; tC2Q: 0.382, 48.726%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.966, 100.000%

Path8

Path Summary:

Slack 4.637
Data Arrival Time 5.547
Data Required Time 10.184
From MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_3
To MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_3
Launch Clk HS_CLK:[F]
Latch Clk HS_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 HS_CLK
5.000 0.000 tCL FF 460 - GND_cZ/G
5.548 0.548 tNET FF 1 IOL9[A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_3/CALIB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 HS_CLK
10.000 0.000 tCL RR 5 IOL3 MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
10.000 0.000 tNET RR 3 - MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CLKIN
10.182 0.182 tINS RR 5 - MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CLKOUT
10.184 0.003 tNET RR 1 IOL9[A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_3/FCLK
10.184 0.000 tSu 1 IOL9[A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_3

Path Statistics:

Clock Skew 0.184
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.548, 100.000%
Required Clock Path Delay cell: 0.182, 98.645%; route: 0.003, 1.355%

Path9

Path Summary:

Slack 4.884
Data Arrival Time 5.300
Data Required Time 10.184
From MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV
To MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV
Launch Clk HS_CLK:[F]
Latch Clk HS_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 HS_CLK
5.000 0.000 tCL FF 460 - GND_cZ/G
5.300 0.300 tNET FF 1 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CALIB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 HS_CLK
10.000 0.000 tCL RR 5 IOL3 MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
10.000 0.000 tNET RR 3 - MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CLKIN
10.182 0.182 tINS RR 5 - MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CLKOUT
10.184 0.003 tNET RR 5 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/HCLKIN
10.184 0.000 tSu 1 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV

Path Statistics:

Clock Skew 0.184
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.300, 100.000%
Required Clock Path Delay cell: 0.182, 98.645%; route: 0.003, 1.355%

Path10

Path Summary:

Slack 4.893
Data Arrival Time 5.291
Data Required Time 10.184
From MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_0
To MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_0
Launch Clk HS_CLK:[F]
Latch Clk HS_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 HS_CLK
5.000 0.000 tCL FF 460 - GND_cZ/G
5.291 0.291 tNET FF 1 IOT25[A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_0/CALIB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 HS_CLK
10.000 0.000 tCL RR 5 IOL3 MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
10.000 0.000 tNET RR 3 - MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CLKIN
10.182 0.182 tINS RR 5 - MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CLKOUT
10.184 0.003 tNET RR 1 IOT25[A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_0/FCLK
10.184 0.000 tSu 1 IOT25[A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_0

Path Statistics:

Clock Skew 0.184
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.291, 100.000%
Required Clock Path Delay cell: 0.182, 98.645%; route: 0.003, 1.355%

Path11

Path Summary:

Slack 4.893
Data Arrival Time 5.291
Data Required Time 10.184
From MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_1
To MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_1
Launch Clk HS_CLK:[F]
Latch Clk HS_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 HS_CLK
5.000 0.000 tCL FF 460 - GND_cZ/G
5.291 0.291 tNET FF 1 IOT27[A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_1/CALIB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 HS_CLK
10.000 0.000 tCL RR 5 IOL3 MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
10.000 0.000 tNET RR 3 - MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CLKIN
10.182 0.182 tINS RR 5 - MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CLKOUT
10.184 0.003 tNET RR 1 IOT27[A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_1/FCLK
10.184 0.000 tSu 1 IOT27[A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_1

Path Statistics:

Clock Skew 0.184
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.291, 100.000%
Required Clock Path Delay cell: 0.182, 98.645%; route: 0.003, 1.355%

Path12

Path Summary:

Slack 4.893
Data Arrival Time 5.291
Data Required Time 10.184
From MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_2
To MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_2
Launch Clk HS_CLK:[F]
Latch Clk HS_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 HS_CLK
5.000 0.000 tCL FF 460 - GND_cZ/G
5.291 0.291 tNET FF 1 IOL5[A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_2/CALIB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 HS_CLK
10.000 0.000 tCL RR 5 IOL3 MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
10.000 0.000 tNET RR 3 - MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CLKIN
10.182 0.182 tINS RR 5 - MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CLKOUT
10.184 0.003 tNET RR 1 IOL5[A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_2/FCLK
10.184 0.000 tSu 1 IOL5[A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_2

Path Statistics:

Clock Skew 0.184
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.291, 100.000%
Required Clock Path Delay cell: 0.182, 98.645%; route: 0.003, 1.355%

Path13

Path Summary:

Slack 17.999
Data Arrival Time 11.091
Data Required Time 29.090
From gw_gao_inst_0/u_la0_top/module_state_1_s0
To gw_gao_inst_0/u_la0_top/internal_reg_force_triger_s1
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.683 0.683 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.683 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365 0.683 tINS RR 250 - gw_gao_inst_0/u_gw_jtag/tck_o
4.292 2.927 tNET RR 1 R30C58[1][A] gw_gao_inst_0/u_la0_top/module_state_1_s0/CLK
4.675 0.382 tC2Q RR 24 R30C58[1][A] gw_gao_inst_0/u_la0_top/module_state_1_s0/Q
5.475 0.800 tNET RR 1 R29C55[2][B] gw_gao_inst_0/u_la0_top/data_to_word_counter_15_s2/I1
5.991 0.516 tINS RR 18 R29C55[2][B] gw_gao_inst_0/u_la0_top/data_to_word_counter_15_s2/F
6.131 0.140 tNET RR 1 R29C55[3][A] gw_gao_inst_0/u_la0_top/regsel_ld_en_s7/I3
6.652 0.521 tINS RR 19 R29C55[3][A] gw_gao_inst_0/u_la0_top/regsel_ld_en_s7/F
7.773 1.121 tNET RR 1 R25C54[2][B] gw_gao_inst_0/u_la0_top/internal_reg_start_s5/I0
8.300 0.526 tINS RR 1 R25C54[2][B] gw_gao_inst_0/u_la0_top/internal_reg_start_s5/F
8.302 0.003 tNET RR 1 R25C54[1][A] gw_gao_inst_0/u_la0_top/internal_reg_start_s4/I3
8.828 0.526 tINS RR 3 R25C54[1][A] gw_gao_inst_0/u_la0_top/internal_reg_start_s4/F
9.766 0.937 tNET RR 1 R20C57[1][B] gw_gao_inst_0/u_la0_top/internal_reg_start_s3/I2
10.282 0.516 tINS RR 2 R20C57[1][B] gw_gao_inst_0/u_la0_top/internal_reg_start_s3/F
11.091 0.809 tNET RR 1 R20C57[2][B] gw_gao_inst_0/u_la0_top/internal_reg_force_triger_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
25.000 25.000 active clock edge time
25.000 0.000 tck_pad_i
25.000 0.000 tCL FF 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
25.688 0.688 tINS FF 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
25.688 0.000 tNET FF 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
26.375 0.688 tINS FF 250 - gw_gao_inst_0/u_gw_jtag/tck_o
29.346 2.971 tNET FF 1 R20C57[2][B] gw_gao_inst_0/u_la0_top/internal_reg_force_triger_s1/CLK
29.090 -0.256 tSu 1 R20C57[2][B] gw_gao_inst_0/u_la0_top/internal_reg_force_triger_s1

Path Statistics:

Clock Skew 0.054
Setup Relationship 25.000
Logic Level 6
Arrival Clock Path Delay cell: 1.365, 31.802%; route: 2.927, 68.198%
Arrival Data Path Delay cell: 2.606, 38.334%; route: 3.810, 56.040%; tC2Q: 0.382, 5.626%
Required Clock Path Delay cell: 1.375, 31.639%; route: 2.971, 68.361%

Path14

Path Summary:

Slack 17.999
Data Arrival Time 11.091
Data Required Time 29.090
From gw_gao_inst_0/u_la0_top/module_state_1_s0
To gw_gao_inst_0/u_la0_top/internal_reg_start_s1
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.683 0.683 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.683 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365 0.683 tINS RR 250 - gw_gao_inst_0/u_gw_jtag/tck_o
4.292 2.927 tNET RR 1 R30C58[1][A] gw_gao_inst_0/u_la0_top/module_state_1_s0/CLK
4.675 0.382 tC2Q RR 24 R30C58[1][A] gw_gao_inst_0/u_la0_top/module_state_1_s0/Q
5.475 0.800 tNET RR 1 R29C55[2][B] gw_gao_inst_0/u_la0_top/data_to_word_counter_15_s2/I1
5.991 0.516 tINS RR 18 R29C55[2][B] gw_gao_inst_0/u_la0_top/data_to_word_counter_15_s2/F
6.131 0.140 tNET RR 1 R29C55[3][A] gw_gao_inst_0/u_la0_top/regsel_ld_en_s7/I3
6.652 0.521 tINS RR 19 R29C55[3][A] gw_gao_inst_0/u_la0_top/regsel_ld_en_s7/F
7.773 1.121 tNET RR 1 R25C54[2][B] gw_gao_inst_0/u_la0_top/internal_reg_start_s5/I0
8.300 0.526 tINS RR 1 R25C54[2][B] gw_gao_inst_0/u_la0_top/internal_reg_start_s5/F
8.302 0.003 tNET RR 1 R25C54[1][A] gw_gao_inst_0/u_la0_top/internal_reg_start_s4/I3
8.828 0.526 tINS RR 3 R25C54[1][A] gw_gao_inst_0/u_la0_top/internal_reg_start_s4/F
9.766 0.937 tNET RR 1 R20C57[1][B] gw_gao_inst_0/u_la0_top/internal_reg_start_s3/I2
10.282 0.516 tINS RR 2 R20C57[1][B] gw_gao_inst_0/u_la0_top/internal_reg_start_s3/F
11.091 0.809 tNET RR 1 R20C57[2][A] gw_gao_inst_0/u_la0_top/internal_reg_start_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
25.000 25.000 active clock edge time
25.000 0.000 tck_pad_i
25.000 0.000 tCL FF 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
25.688 0.688 tINS FF 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
25.688 0.000 tNET FF 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
26.375 0.688 tINS FF 250 - gw_gao_inst_0/u_gw_jtag/tck_o
29.346 2.971 tNET FF 1 R20C57[2][A] gw_gao_inst_0/u_la0_top/internal_reg_start_s1/CLK
29.090 -0.256 tSu 1 R20C57[2][A] gw_gao_inst_0/u_la0_top/internal_reg_start_s1

Path Statistics:

Clock Skew 0.054
Setup Relationship 25.000
Logic Level 6
Arrival Clock Path Delay cell: 1.365, 31.802%; route: 2.927, 68.198%
Arrival Data Path Delay cell: 2.606, 38.334%; route: 3.810, 56.040%; tC2Q: 0.382, 5.626%
Required Clock Path Delay cell: 1.375, 31.639%; route: 2.971, 68.361%

Path15

Path Summary:

Slack 19.045
Data Arrival Time 10.292
Data Required Time 29.337
From gw_gao_inst_0/u_la0_top/module_state_1_s0
To gw_gao_inst_0/u_la0_top/internal_reg_force_triger_s1
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.683 0.683 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.683 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365 0.683 tINS RR 250 - gw_gao_inst_0/u_gw_jtag/tck_o
4.292 2.927 tNET RR 1 R30C58[1][A] gw_gao_inst_0/u_la0_top/module_state_1_s0/CLK
4.675 0.382 tC2Q RR 24 R30C58[1][A] gw_gao_inst_0/u_la0_top/module_state_1_s0/Q
5.475 0.800 tNET RR 1 R29C55[2][B] gw_gao_inst_0/u_la0_top/data_to_word_counter_15_s2/I1
5.991 0.516 tINS RR 18 R29C55[2][B] gw_gao_inst_0/u_la0_top/data_to_word_counter_15_s2/F
6.131 0.140 tNET RR 1 R29C55[3][A] gw_gao_inst_0/u_la0_top/regsel_ld_en_s7/I3
6.652 0.521 tINS RR 19 R29C55[3][A] gw_gao_inst_0/u_la0_top/regsel_ld_en_s7/F
7.773 1.121 tNET RR 1 R25C54[2][B] gw_gao_inst_0/u_la0_top/internal_reg_start_s5/I0
8.300 0.526 tINS RR 1 R25C54[2][B] gw_gao_inst_0/u_la0_top/internal_reg_start_s5/F
8.302 0.003 tNET RR 1 R25C54[1][A] gw_gao_inst_0/u_la0_top/internal_reg_start_s4/I3
8.828 0.526 tINS RR 3 R25C54[1][A] gw_gao_inst_0/u_la0_top/internal_reg_start_s4/F
9.766 0.937 tNET RR 1 R20C57[2][B] gw_gao_inst_0/u_la0_top/n664_s1/I1
10.292 0.526 tINS RR 1 R20C57[2][B] gw_gao_inst_0/u_la0_top/n664_s1/F
10.292 0.000 tNET RR 1 R20C57[2][B] gw_gao_inst_0/u_la0_top/internal_reg_force_triger_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
25.000 25.000 active clock edge time
25.000 0.000 tck_pad_i
25.000 0.000 tCL FF 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
25.688 0.688 tINS FF 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
25.688 0.000 tNET FF 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
26.375 0.688 tINS FF 250 - gw_gao_inst_0/u_gw_jtag/tck_o
29.346 2.971 tNET FF 1 R20C57[2][B] gw_gao_inst_0/u_la0_top/internal_reg_force_triger_s1/CLK
29.337 -0.009 tSu 1 R20C57[2][B] gw_gao_inst_0/u_la0_top/internal_reg_force_triger_s1

Path Statistics:

Clock Skew 0.054
Setup Relationship 25.000
Logic Level 6
Arrival Clock Path Delay cell: 1.365, 31.802%; route: 2.927, 68.198%
Arrival Data Path Delay cell: 2.616, 43.604%; route: 3.001, 50.021%; tC2Q: 0.382, 6.375%
Required Clock Path Delay cell: 1.375, 31.639%; route: 2.971, 68.361%

Path16

Path Summary:

Slack 19.045
Data Arrival Time 10.292
Data Required Time 29.337
From gw_gao_inst_0/u_la0_top/module_state_1_s0
To gw_gao_inst_0/u_la0_top/internal_reg_start_s1
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.683 0.683 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.683 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365 0.683 tINS RR 250 - gw_gao_inst_0/u_gw_jtag/tck_o
4.292 2.927 tNET RR 1 R30C58[1][A] gw_gao_inst_0/u_la0_top/module_state_1_s0/CLK
4.675 0.382 tC2Q RR 24 R30C58[1][A] gw_gao_inst_0/u_la0_top/module_state_1_s0/Q
5.475 0.800 tNET RR 1 R29C55[2][B] gw_gao_inst_0/u_la0_top/data_to_word_counter_15_s2/I1
5.991 0.516 tINS RR 18 R29C55[2][B] gw_gao_inst_0/u_la0_top/data_to_word_counter_15_s2/F
6.131 0.140 tNET RR 1 R29C55[3][A] gw_gao_inst_0/u_la0_top/regsel_ld_en_s7/I3
6.652 0.521 tINS RR 19 R29C55[3][A] gw_gao_inst_0/u_la0_top/regsel_ld_en_s7/F
7.773 1.121 tNET RR 1 R25C54[2][B] gw_gao_inst_0/u_la0_top/internal_reg_start_s5/I0
8.300 0.526 tINS RR 1 R25C54[2][B] gw_gao_inst_0/u_la0_top/internal_reg_start_s5/F
8.302 0.003 tNET RR 1 R25C54[1][A] gw_gao_inst_0/u_la0_top/internal_reg_start_s4/I3
8.828 0.526 tINS RR 3 R25C54[1][A] gw_gao_inst_0/u_la0_top/internal_reg_start_s4/F
9.766 0.937 tNET RR 1 R20C57[2][A] gw_gao_inst_0/u_la0_top/n659_s1/I1
10.292 0.526 tINS RR 1 R20C57[2][A] gw_gao_inst_0/u_la0_top/n659_s1/F
10.292 0.000 tNET RR 1 R20C57[2][A] gw_gao_inst_0/u_la0_top/internal_reg_start_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
25.000 25.000 active clock edge time
25.000 0.000 tck_pad_i
25.000 0.000 tCL FF 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
25.688 0.688 tINS FF 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
25.688 0.000 tNET FF 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
26.375 0.688 tINS FF 250 - gw_gao_inst_0/u_gw_jtag/tck_o
29.346 2.971 tNET FF 1 R20C57[2][A] gw_gao_inst_0/u_la0_top/internal_reg_start_s1/CLK
29.337 -0.009 tSu 1 R20C57[2][A] gw_gao_inst_0/u_la0_top/internal_reg_start_s1

Path Statistics:

Clock Skew 0.054
Setup Relationship 25.000
Logic Level 6
Arrival Clock Path Delay cell: 1.365, 31.802%; route: 2.927, 68.198%
Arrival Data Path Delay cell: 2.616, 43.604%; route: 3.001, 50.021%; tC2Q: 0.382, 6.375%
Required Clock Path Delay cell: 1.375, 31.639%; route: 2.971, 68.361%

Path17

Path Summary:

Slack 41.421
Data Arrival Time 12.813
Data Required Time 54.234
From gw_gao_inst_0/u_la0_top/module_state_1_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.683 0.683 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.683 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365 0.683 tINS RR 250 - gw_gao_inst_0/u_gw_jtag/tck_o
4.292 2.927 tNET RR 1 R30C58[1][A] gw_gao_inst_0/u_la0_top/module_state_1_s0/CLK
4.675 0.382 tC2Q RR 24 R30C58[1][A] gw_gao_inst_0/u_la0_top/module_state_1_s0/Q
5.963 1.289 tNET RR 1 R23C57[3][A] gw_gao_inst_0/u_la0_top/jtag_strobe_i_s5/I1
6.378 0.415 tINS RR 2 R23C57[3][A] gw_gao_inst_0/u_la0_top/jtag_strobe_i_s5/F
6.918 0.540 tNET RR 1 R27C57[3][B] gw_gao_inst_0/u_la0_top/jtag_strobe_i_s6/I2
7.333 0.415 tINS RR 1 R27C57[3][B] gw_gao_inst_0/u_la0_top/jtag_strobe_i_s6/F
8.012 0.679 tNET RR 1 R29C57[2][B] gw_gao_inst_0/u_la0_top/jtag_strobe_i_s8/I2
8.473 0.461 tINS RR 1 R29C57[2][B] gw_gao_inst_0/u_la0_top/jtag_strobe_i_s8/F
8.476 0.003 tNET RR 1 R29C57[3][A] gw_gao_inst_0/u_la0_top/jtag_strobe_i_s1/I1
8.973 0.498 tINS RR 1 R29C57[3][A] gw_gao_inst_0/u_la0_top/jtag_strobe_i_s1/F
8.976 0.003 tNET RR 1 R29C57[2][A] gw_gao_inst_0/u_la0_top/jtag_strobe_i_s0/I0
9.437 0.461 tINS RR 4 R29C57[2][A] gw_gao_inst_0/u_la0_top/jtag_strobe_i_s0/F
12.813 3.376 tNET RR 1 BSRAM_R10[19] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CEB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
50.000 50.000 active clock edge time
50.000 0.000 tck_pad_i
50.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
50.682 0.683 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
50.682 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365 0.683 tINS RR 250 - gw_gao_inst_0/u_gw_jtag/tck_o
54.325 2.960 tNET RR 1 BSRAM_R10[19] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKB
54.234 -0.091 tSu 1 BSRAM_R10[19] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s

Path Statistics:

Clock Skew 0.033
Setup Relationship 50.000
Logic Level 6
Arrival Clock Path Delay cell: 1.365, 31.802%; route: 2.927, 68.198%
Arrival Data Path Delay cell: 2.250, 26.405%; route: 5.889, 69.107%; tC2Q: 0.382, 4.489%
Required Clock Path Delay cell: 1.365, 31.558%; route: 2.960, 68.442%

Path18

Path Summary:

Slack 21.052
Data Arrival Time 33.217
Data Required Time 54.269
From gw_gao_inst_0/u_la0_top/internal_reg_start_s1
To gw_gao_inst_0/u_la0_top/data_out_shift_reg_0_s1
Launch Clk tck_pad_i:[F]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
25.000 25.000 active clock edge time
25.000 0.000 tck_pad_i
25.000 0.000 tCL FF 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
25.688 0.688 tINS FF 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
25.688 0.000 tNET FF 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
26.375 0.688 tINS FF 250 - gw_gao_inst_0/u_gw_jtag/tck_o
29.346 2.971 tNET FF 1 R20C57[2][A] gw_gao_inst_0/u_la0_top/internal_reg_start_s1/CLK
29.780 0.434 tC2Q FR 2 R20C57[2][A] gw_gao_inst_0/u_la0_top/internal_reg_start_s1/Q
30.830 1.050 tNET RR 1 R18C54[0][B] gw_gao_inst_0/u_la0_top/n1026_s9/I0
31.291 0.461 tINS RR 1 R18C54[0][B] gw_gao_inst_0/u_la0_top/n1026_s9/F
31.293 0.003 tNET RR 1 R18C54[0][A] gw_gao_inst_0/u_la0_top/n1026_s6/I1
31.810 0.516 tINS RR 1 R18C54[0][A] gw_gao_inst_0/u_la0_top/n1026_s6/F
31.967 0.157 tNET RR 1 R17C54[1][B] gw_gao_inst_0/u_la0_top/n1026_s2/I0
32.483 0.516 tINS RR 1 R17C54[1][B] gw_gao_inst_0/u_la0_top/n1026_s2/F
32.701 0.218 tNET RR 1 R17C56[0][B] gw_gao_inst_0/u_la0_top/n1026_s0/I1
33.217 0.516 tINS RR 1 R17C56[0][B] gw_gao_inst_0/u_la0_top/n1026_s0/F
33.217 0.000 tNET RR 1 R17C56[0][B] gw_gao_inst_0/u_la0_top/data_out_shift_reg_0_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
50.000 50.000 active clock edge time
50.000 0.000 tck_pad_i
50.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
50.682 0.683 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
50.682 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365 0.683 tINS RR 250 - gw_gao_inst_0/u_gw_jtag/tck_o
54.333 2.967 tNET RR 1 R17C56[0][B] gw_gao_inst_0/u_la0_top/data_out_shift_reg_0_s1/CLK
54.269 -0.064 tSu 1 R17C56[0][B] gw_gao_inst_0/u_la0_top/data_out_shift_reg_0_s1

Path Statistics:

Clock Skew -0.013
Setup Relationship 25.000
Logic Level 5
Arrival Clock Path Delay cell: 1.375, 31.639%; route: 2.971, 68.361%
Arrival Data Path Delay cell: 2.010, 51.921%; route: 1.428, 36.874%; tC2Q: 0.434, 11.204%
Required Clock Path Delay cell: 1.365, 31.506%; route: 2.967, 68.494%

Path19

Path Summary:

Slack 42.157
Data Arrival Time 12.086
Data Required Time 54.243
From gw_gao_inst_0/u_la0_top/module_state_1_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.683 0.683 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.683 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365 0.683 tINS RR 250 - gw_gao_inst_0/u_gw_jtag/tck_o
4.292 2.927 tNET RR 1 R30C58[1][A] gw_gao_inst_0/u_la0_top/module_state_1_s0/CLK
4.675 0.382 tC2Q RR 24 R30C58[1][A] gw_gao_inst_0/u_la0_top/module_state_1_s0/Q
5.963 1.289 tNET RR 1 R23C57[3][A] gw_gao_inst_0/u_la0_top/jtag_strobe_i_s5/I1
6.378 0.415 tINS RR 2 R23C57[3][A] gw_gao_inst_0/u_la0_top/jtag_strobe_i_s5/F
6.918 0.540 tNET RR 1 R27C57[3][B] gw_gao_inst_0/u_la0_top/jtag_strobe_i_s6/I2
7.333 0.415 tINS RR 1 R27C57[3][B] gw_gao_inst_0/u_la0_top/jtag_strobe_i_s6/F
8.012 0.679 tNET RR 1 R29C57[2][B] gw_gao_inst_0/u_la0_top/jtag_strobe_i_s8/I2
8.473 0.461 tINS RR 1 R29C57[2][B] gw_gao_inst_0/u_la0_top/jtag_strobe_i_s8/F
8.476 0.003 tNET RR 1 R29C57[3][A] gw_gao_inst_0/u_la0_top/jtag_strobe_i_s1/I1
8.973 0.498 tINS RR 1 R29C57[3][A] gw_gao_inst_0/u_la0_top/jtag_strobe_i_s1/F
8.976 0.003 tNET RR 1 R29C57[2][A] gw_gao_inst_0/u_la0_top/jtag_strobe_i_s0/I0
9.437 0.461 tINS RR 4 R29C57[2][A] gw_gao_inst_0/u_la0_top/jtag_strobe_i_s0/F
12.086 2.649 tNET RR 1 BSRAM_R10[18] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CEB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
50.000 50.000 active clock edge time
50.000 0.000 tck_pad_i
50.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
50.682 0.683 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
50.682 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365 0.683 tINS RR 250 - gw_gao_inst_0/u_gw_jtag/tck_o
54.335 2.970 tNET RR 1 BSRAM_R10[18] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKB
54.243 -0.091 tSu 1 BSRAM_R10[18] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew 0.042
Setup Relationship 50.000
Logic Level 6
Arrival Clock Path Delay cell: 1.365, 31.802%; route: 2.927, 68.198%
Arrival Data Path Delay cell: 2.250, 28.869%; route: 5.161, 66.223%; tC2Q: 0.382, 4.908%
Required Clock Path Delay cell: 1.365, 31.490%; route: 2.970, 68.510%

Path20

Path Summary:

Slack 42.494
Data Arrival Time 11.731
Data Required Time 54.225
From gw_gao_inst_0/u_la0_top/module_state_1_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.683 0.683 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.683 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365 0.683 tINS RR 250 - gw_gao_inst_0/u_gw_jtag/tck_o
4.292 2.927 tNET RR 1 R30C58[1][A] gw_gao_inst_0/u_la0_top/module_state_1_s0/CLK
4.675 0.382 tC2Q RR 24 R30C58[1][A] gw_gao_inst_0/u_la0_top/module_state_1_s0/Q
5.963 1.289 tNET RR 1 R23C57[3][A] gw_gao_inst_0/u_la0_top/jtag_strobe_i_s5/I1
6.378 0.415 tINS RR 2 R23C57[3][A] gw_gao_inst_0/u_la0_top/jtag_strobe_i_s5/F
6.918 0.540 tNET RR 1 R27C57[3][B] gw_gao_inst_0/u_la0_top/jtag_strobe_i_s6/I2
7.333 0.415 tINS RR 1 R27C57[3][B] gw_gao_inst_0/u_la0_top/jtag_strobe_i_s6/F
8.012 0.679 tNET RR 1 R29C57[2][B] gw_gao_inst_0/u_la0_top/jtag_strobe_i_s8/I2
8.473 0.461 tINS RR 1 R29C57[2][B] gw_gao_inst_0/u_la0_top/jtag_strobe_i_s8/F
8.476 0.003 tNET RR 1 R29C57[3][A] gw_gao_inst_0/u_la0_top/jtag_strobe_i_s1/I1
8.973 0.498 tINS RR 1 R29C57[3][A] gw_gao_inst_0/u_la0_top/jtag_strobe_i_s1/F
8.976 0.003 tNET RR 1 R29C57[2][A] gw_gao_inst_0/u_la0_top/jtag_strobe_i_s0/I0
9.437 0.461 tINS RR 4 R29C57[2][A] gw_gao_inst_0/u_la0_top/jtag_strobe_i_s0/F
11.731 2.294 tNET RR 1 BSRAM_R10[16] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CEB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
50.000 50.000 active clock edge time
50.000 0.000 tck_pad_i
50.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
50.682 0.683 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
50.682 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365 0.683 tINS RR 250 - gw_gao_inst_0/u_gw_jtag/tck_o
54.316 2.951 tNET RR 1 BSRAM_R10[16] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKB
54.225 -0.091 tSu 1 BSRAM_R10[16] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew 0.024
Setup Relationship 50.000
Logic Level 6
Arrival Clock Path Delay cell: 1.365, 31.802%; route: 2.927, 68.198%
Arrival Data Path Delay cell: 2.250, 30.247%; route: 4.806, 64.611%; tC2Q: 0.382, 5.142%
Required Clock Path Delay cell: 1.365, 31.627%; route: 2.951, 68.373%

Path21

Path Summary:

Slack 42.539
Data Arrival Time 11.451
Data Required Time 53.990
From gw_gao_inst_0/u_la0_top/module_state_1_s0
To gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.683 0.683 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.683 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365 0.683 tINS RR 250 - gw_gao_inst_0/u_gw_jtag/tck_o
4.292 2.927 tNET RR 1 R30C58[1][A] gw_gao_inst_0/u_la0_top/module_state_1_s0/CLK
4.675 0.382 tC2Q RR 24 R30C58[1][A] gw_gao_inst_0/u_la0_top/module_state_1_s0/Q
5.475 0.800 tNET RR 1 R29C55[2][B] gw_gao_inst_0/u_la0_top/data_to_word_counter_15_s2/I1
5.991 0.516 tINS RR 18 R29C55[2][B] gw_gao_inst_0/u_la0_top/data_to_word_counter_15_s2/F
6.131 0.140 tNET RR 1 R29C55[3][A] gw_gao_inst_0/u_la0_top/regsel_ld_en_s7/I3
6.652 0.521 tINS RR 19 R29C55[3][A] gw_gao_inst_0/u_la0_top/regsel_ld_en_s7/F
7.773 1.121 tNET RR 1 R25C54[0][A] gw_gao_inst_0/u_la0_top/trig_level_max_reg_wr_s3/I0
8.290 0.516 tINS RR 4 R25C54[0][A] gw_gao_inst_0/u_la0_top/trig_level_max_reg_wr_s3/F
9.566 1.276 tNET RR 1 R16C54[2][A] gw_gao_inst_0/u_la0_top/trig_level_max_reg_wr_s1/I2
10.092 0.526 tINS RR 1 R16C54[2][A] gw_gao_inst_0/u_la0_top/trig_level_max_reg_wr_s1/F
10.095 0.003 tNET RR 1 R16C54[2][B] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_wr_s0/I1
10.556 0.461 tINS RR 16 R16C54[2][B] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_wr_s0/F
11.451 0.895 tNET RR 1 R12C55[1][A] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
50.000 50.000 active clock edge time
50.000 0.000 tck_pad_i
50.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
50.682 0.683 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
50.682 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365 0.683 tINS RR 250 - gw_gao_inst_0/u_gw_jtag/tck_o
54.302 2.937 tNET RR 1 R12C55[1][A] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0/CLK
53.990 -0.311 tSu 1 R12C55[1][A] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0

Path Statistics:

Clock Skew 0.009
Setup Relationship 50.000
Logic Level 6
Arrival Clock Path Delay cell: 1.365, 31.802%; route: 2.927, 68.198%
Arrival Data Path Delay cell: 2.541, 35.499%; route: 4.235, 59.158%; tC2Q: 0.382, 5.343%
Required Clock Path Delay cell: 1.365, 31.733%; route: 2.937, 68.267%

Path22

Path Summary:

Slack 42.539
Data Arrival Time 11.451
Data Required Time 53.990
From gw_gao_inst_0/u_la0_top/module_state_1_s0
To gw_gao_inst_0/u_la0_top/capture_mem_addr_max_9_s0
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.683 0.683 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.683 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365 0.683 tINS RR 250 - gw_gao_inst_0/u_gw_jtag/tck_o
4.292 2.927 tNET RR 1 R30C58[1][A] gw_gao_inst_0/u_la0_top/module_state_1_s0/CLK
4.675 0.382 tC2Q RR 24 R30C58[1][A] gw_gao_inst_0/u_la0_top/module_state_1_s0/Q
5.475 0.800 tNET RR 1 R29C55[2][B] gw_gao_inst_0/u_la0_top/data_to_word_counter_15_s2/I1
5.991 0.516 tINS RR 18 R29C55[2][B] gw_gao_inst_0/u_la0_top/data_to_word_counter_15_s2/F
6.131 0.140 tNET RR 1 R29C55[3][A] gw_gao_inst_0/u_la0_top/regsel_ld_en_s7/I3
6.652 0.521 tINS RR 19 R29C55[3][A] gw_gao_inst_0/u_la0_top/regsel_ld_en_s7/F
7.773 1.121 tNET RR 1 R25C54[0][A] gw_gao_inst_0/u_la0_top/trig_level_max_reg_wr_s3/I0
8.290 0.516 tINS RR 4 R25C54[0][A] gw_gao_inst_0/u_la0_top/trig_level_max_reg_wr_s3/F
9.566 1.276 tNET RR 1 R16C54[2][A] gw_gao_inst_0/u_la0_top/trig_level_max_reg_wr_s1/I2
10.092 0.526 tINS RR 1 R16C54[2][A] gw_gao_inst_0/u_la0_top/trig_level_max_reg_wr_s1/F
10.095 0.003 tNET RR 1 R16C54[2][B] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_wr_s0/I1
10.556 0.461 tINS RR 16 R16C54[2][B] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_wr_s0/F
11.451 0.895 tNET RR 1 R12C55[0][A] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_9_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
50.000 50.000 active clock edge time
50.000 0.000 tck_pad_i
50.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
50.682 0.683 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
50.682 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365 0.683 tINS RR 250 - gw_gao_inst_0/u_gw_jtag/tck_o
54.302 2.937 tNET RR 1 R12C55[0][A] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_9_s0/CLK
53.990 -0.311 tSu 1 R12C55[0][A] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_9_s0

Path Statistics:

Clock Skew 0.009
Setup Relationship 50.000
Logic Level 6
Arrival Clock Path Delay cell: 1.365, 31.802%; route: 2.927, 68.198%
Arrival Data Path Delay cell: 2.541, 35.499%; route: 4.235, 59.158%; tC2Q: 0.382, 5.343%
Required Clock Path Delay cell: 1.365, 31.733%; route: 2.937, 68.267%

Path23

Path Summary:

Slack 42.539
Data Arrival Time 11.451
Data Required Time 53.990
From gw_gao_inst_0/u_la0_top/module_state_1_s0
To gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.683 0.683 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.683 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365 0.683 tINS RR 250 - gw_gao_inst_0/u_gw_jtag/tck_o
4.292 2.927 tNET RR 1 R30C58[1][A] gw_gao_inst_0/u_la0_top/module_state_1_s0/CLK
4.675 0.382 tC2Q RR 24 R30C58[1][A] gw_gao_inst_0/u_la0_top/module_state_1_s0/Q
5.475 0.800 tNET RR 1 R29C55[2][B] gw_gao_inst_0/u_la0_top/data_to_word_counter_15_s2/I1
5.991 0.516 tINS RR 18 R29C55[2][B] gw_gao_inst_0/u_la0_top/data_to_word_counter_15_s2/F
6.131 0.140 tNET RR 1 R29C55[3][A] gw_gao_inst_0/u_la0_top/regsel_ld_en_s7/I3
6.652 0.521 tINS RR 19 R29C55[3][A] gw_gao_inst_0/u_la0_top/regsel_ld_en_s7/F
7.773 1.121 tNET RR 1 R25C54[0][A] gw_gao_inst_0/u_la0_top/trig_level_max_reg_wr_s3/I0
8.290 0.516 tINS RR 4 R25C54[0][A] gw_gao_inst_0/u_la0_top/trig_level_max_reg_wr_s3/F
9.566 1.276 tNET RR 1 R16C54[2][A] gw_gao_inst_0/u_la0_top/trig_level_max_reg_wr_s1/I2
10.092 0.526 tINS RR 1 R16C54[2][A] gw_gao_inst_0/u_la0_top/trig_level_max_reg_wr_s1/F
10.095 0.003 tNET RR 1 R16C54[2][B] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_wr_s0/I1
10.556 0.461 tINS RR 16 R16C54[2][B] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_wr_s0/F
11.451 0.895 tNET RR 1 R12C55[0][B] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
50.000 50.000 active clock edge time
50.000 0.000 tck_pad_i
50.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
50.682 0.683 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
50.682 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365 0.683 tINS RR 250 - gw_gao_inst_0/u_gw_jtag/tck_o
54.302 2.937 tNET RR 1 R12C55[0][B] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/CLK
53.990 -0.311 tSu 1 R12C55[0][B] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0

Path Statistics:

Clock Skew 0.009
Setup Relationship 50.000
Logic Level 6
Arrival Clock Path Delay cell: 1.365, 31.802%; route: 2.927, 68.198%
Arrival Data Path Delay cell: 2.541, 35.499%; route: 4.235, 59.158%; tC2Q: 0.382, 5.343%
Required Clock Path Delay cell: 1.365, 31.733%; route: 2.937, 68.267%

Path24

Path Summary:

Slack 42.733
Data Arrival Time 11.263
Data Required Time 53.996
From gw_gao_inst_0/u_la0_top/module_state_1_s0
To gw_gao_inst_0/u_la0_top/capture_mem_addr_max_0_s0
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.683 0.683 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.683 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365 0.683 tINS RR 250 - gw_gao_inst_0/u_gw_jtag/tck_o
4.292 2.927 tNET RR 1 R30C58[1][A] gw_gao_inst_0/u_la0_top/module_state_1_s0/CLK
4.675 0.382 tC2Q RR 24 R30C58[1][A] gw_gao_inst_0/u_la0_top/module_state_1_s0/Q
5.475 0.800 tNET RR 1 R29C55[2][B] gw_gao_inst_0/u_la0_top/data_to_word_counter_15_s2/I1
5.991 0.516 tINS RR 18 R29C55[2][B] gw_gao_inst_0/u_la0_top/data_to_word_counter_15_s2/F
6.131 0.140 tNET RR 1 R29C55[3][A] gw_gao_inst_0/u_la0_top/regsel_ld_en_s7/I3
6.652 0.521 tINS RR 19 R29C55[3][A] gw_gao_inst_0/u_la0_top/regsel_ld_en_s7/F
7.773 1.121 tNET RR 1 R25C54[0][A] gw_gao_inst_0/u_la0_top/trig_level_max_reg_wr_s3/I0
8.290 0.516 tINS RR 4 R25C54[0][A] gw_gao_inst_0/u_la0_top/trig_level_max_reg_wr_s3/F
9.566 1.276 tNET RR 1 R16C54[2][A] gw_gao_inst_0/u_la0_top/trig_level_max_reg_wr_s1/I2
10.092 0.526 tINS RR 1 R16C54[2][A] gw_gao_inst_0/u_la0_top/trig_level_max_reg_wr_s1/F
10.095 0.003 tNET RR 1 R16C54[2][B] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_wr_s0/I1
10.556 0.461 tINS RR 16 R16C54[2][B] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_wr_s0/F
11.263 0.707 tNET RR 1 R13C55[0][B] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_0_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
50.000 50.000 active clock edge time
50.000 0.000 tck_pad_i
50.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
50.682 0.683 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
50.682 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365 0.683 tINS RR 250 - gw_gao_inst_0/u_gw_jtag/tck_o
54.307 2.942 tNET RR 1 R13C55[0][B] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_0_s0/CLK
53.996 -0.311 tSu 1 R13C55[0][B] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_0_s0

Path Statistics:

Clock Skew 0.015
Setup Relationship 50.000
Logic Level 6
Arrival Clock Path Delay cell: 1.365, 31.802%; route: 2.927, 68.198%
Arrival Data Path Delay cell: 2.541, 36.453%; route: 4.048, 58.060%; tC2Q: 0.382, 5.487%
Required Clock Path Delay cell: 1.365, 31.689%; route: 2.942, 68.311%

Path25

Path Summary:

Slack 42.733
Data Arrival Time 11.263
Data Required Time 53.996
From gw_gao_inst_0/u_la0_top/module_state_1_s0
To gw_gao_inst_0/u_la0_top/capture_mem_addr_max_1_s0
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.683 0.683 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.683 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365 0.683 tINS RR 250 - gw_gao_inst_0/u_gw_jtag/tck_o
4.292 2.927 tNET RR 1 R30C58[1][A] gw_gao_inst_0/u_la0_top/module_state_1_s0/CLK
4.675 0.382 tC2Q RR 24 R30C58[1][A] gw_gao_inst_0/u_la0_top/module_state_1_s0/Q
5.475 0.800 tNET RR 1 R29C55[2][B] gw_gao_inst_0/u_la0_top/data_to_word_counter_15_s2/I1
5.991 0.516 tINS RR 18 R29C55[2][B] gw_gao_inst_0/u_la0_top/data_to_word_counter_15_s2/F
6.131 0.140 tNET RR 1 R29C55[3][A] gw_gao_inst_0/u_la0_top/regsel_ld_en_s7/I3
6.652 0.521 tINS RR 19 R29C55[3][A] gw_gao_inst_0/u_la0_top/regsel_ld_en_s7/F
7.773 1.121 tNET RR 1 R25C54[0][A] gw_gao_inst_0/u_la0_top/trig_level_max_reg_wr_s3/I0
8.290 0.516 tINS RR 4 R25C54[0][A] gw_gao_inst_0/u_la0_top/trig_level_max_reg_wr_s3/F
9.566 1.276 tNET RR 1 R16C54[2][A] gw_gao_inst_0/u_la0_top/trig_level_max_reg_wr_s1/I2
10.092 0.526 tINS RR 1 R16C54[2][A] gw_gao_inst_0/u_la0_top/trig_level_max_reg_wr_s1/F
10.095 0.003 tNET RR 1 R16C54[2][B] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_wr_s0/I1
10.556 0.461 tINS RR 16 R16C54[2][B] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_wr_s0/F
11.263 0.707 tNET RR 1 R13C55[1][A] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_1_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
50.000 50.000 active clock edge time
50.000 0.000 tck_pad_i
50.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
50.682 0.683 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
50.682 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365 0.683 tINS RR 250 - gw_gao_inst_0/u_gw_jtag/tck_o
54.307 2.942 tNET RR 1 R13C55[1][A] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_1_s0/CLK
53.996 -0.311 tSu 1 R13C55[1][A] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_1_s0

Path Statistics:

Clock Skew 0.015
Setup Relationship 50.000
Logic Level 6
Arrival Clock Path Delay cell: 1.365, 31.802%; route: 2.927, 68.198%
Arrival Data Path Delay cell: 2.541, 36.453%; route: 4.048, 58.060%; tC2Q: 0.382, 5.487%
Required Clock Path Delay cell: 1.365, 31.689%; route: 2.942, 68.311%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 0.012
Data Arrival Time 0.171
Data Required Time 0.159
From MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_0
To MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_0
Launch Clk HS_CLK:[R]
Latch Clk HS_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 HS_CLK
0.000 0.000 tCL RR 460 - GND_cZ/G
0.171 0.171 tNET RR 1 IOT25[A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_0/CALIB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 HS_CLK
0.000 0.000 tCL RR 5 IOL3 MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
0.000 0.000 tNET RR 3 - MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CLKIN
0.156 0.156 tINS RR 5 - MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CLKOUT
0.159 0.003 tNET RR 1 IOT25[A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_0/FCLK
0.159 0.000 tHld 1 IOT25[A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_0

Path Statistics:

Clock Skew 0.159
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.171, 100.000%
Required Clock Path Delay cell: 0.156, 98.113%; route: 0.003, 1.887%

Path2

Path Summary:

Slack 0.012
Data Arrival Time 0.171
Data Required Time 0.159
From MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_1
To MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_1
Launch Clk HS_CLK:[R]
Latch Clk HS_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 HS_CLK
0.000 0.000 tCL RR 460 - GND_cZ/G
0.171 0.171 tNET RR 1 IOT27[A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_1/CALIB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 HS_CLK
0.000 0.000 tCL RR 5 IOL3 MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
0.000 0.000 tNET RR 3 - MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CLKIN
0.156 0.156 tINS RR 5 - MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CLKOUT
0.159 0.003 tNET RR 1 IOT27[A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_1/FCLK
0.159 0.000 tHld 1 IOT27[A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_1

Path Statistics:

Clock Skew 0.159
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.171, 100.000%
Required Clock Path Delay cell: 0.156, 98.113%; route: 0.003, 1.887%

Path3

Path Summary:

Slack 0.012
Data Arrival Time 0.171
Data Required Time 0.159
From MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_2
To MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_2
Launch Clk HS_CLK:[R]
Latch Clk HS_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 HS_CLK
0.000 0.000 tCL RR 460 - GND_cZ/G
0.171 0.171 tNET RR 1 IOL5[A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_2/CALIB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 HS_CLK
0.000 0.000 tCL RR 5 IOL3 MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
0.000 0.000 tNET RR 3 - MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CLKIN
0.156 0.156 tINS RR 5 - MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CLKOUT
0.159 0.003 tNET RR 1 IOL5[A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_2/FCLK
0.159 0.000 tHld 1 IOL5[A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_2

Path Statistics:

Clock Skew 0.159
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.171, 100.000%
Required Clock Path Delay cell: 0.156, 98.113%; route: 0.003, 1.887%

Path4

Path Summary:

Slack 0.014
Data Arrival Time 0.173
Data Required Time 0.159
From MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV
To MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV
Launch Clk HS_CLK:[R]
Latch Clk HS_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 HS_CLK
0.000 0.000 tCL RR 460 - GND_cZ/G
0.173 0.173 tNET RR 1 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CALIB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 HS_CLK
0.000 0.000 tCL RR 5 IOL3 MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
0.000 0.000 tNET RR 3 - MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CLKIN
0.156 0.156 tINS RR 5 - MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CLKOUT
0.159 0.003 tNET RR 5 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/HCLKIN
0.159 0.000 tHld 1 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV

Path Statistics:

Clock Skew 0.159
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.173, 100.000%
Required Clock Path Delay cell: 0.156, 98.113%; route: 0.003, 1.887%

Path5

Path Summary:

Slack 0.185
Data Arrival Time 0.344
Data Required Time 0.159
From MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_3
To MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_3
Launch Clk HS_CLK:[R]
Latch Clk HS_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 HS_CLK
0.000 0.000 tCL RR 460 - GND_cZ/G
0.344 0.344 tNET RR 1 IOL9[A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_3/CALIB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 HS_CLK
0.000 0.000 tCL RR 5 IOL3 MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
0.000 0.000 tNET RR 3 - MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CLKIN
0.156 0.156 tINS RR 5 - MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CLKOUT
0.159 0.003 tNET RR 1 IOL9[A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_3/FCLK
0.159 0.000 tHld 1 IOL9[A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_3

Path Statistics:

Clock Skew 0.159
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.344, 100.000%
Required Clock Path Delay cell: 0.156, 98.113%; route: 0.003, 1.887%

Path6

Path Summary:

Slack 0.216
Data Arrival Time 2.768
Data Required Time 2.552
From gw_gao_inst_0/u_la0_top/expression0_data_s0
To gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 250 - gw_gao_inst_0/u_gw_jtag/tck_o
2.525 1.174 tNET RR 1 R26C53[0][A] gw_gao_inst_0/u_la0_top/expression0_data_s0/CLK
2.669 0.144 tC2Q RR 1 R26C53[0][A] gw_gao_inst_0/u_la0_top/expression0_data_s0/Q
2.768 0.099 tNET RR 1 BSRAM_R28[16] gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s/DI[0]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 250 - gw_gao_inst_0/u_gw_jtag/tck_o
2.515 1.164 tNET RR 1 BSRAM_R28[16] gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s/CLKA
2.552 0.037 tHld 1 BSRAM_R28[16] gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s

Path Statistics:

Clock Skew -0.010
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 1.351, 53.505%; route: 1.174, 46.495%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.099, 40.741%; tC2Q: 0.144, 59.259%
Required Clock Path Delay cell: 1.351, 53.718%; route: 1.164, 46.282%

Path7

Path Summary:

Slack 0.275
Data Arrival Time 1.012
Data Required Time 0.737
From MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/lane0_cnt_0_s1
To MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/lane0_cnt_0_s1
Launch Clk Inst3_CLKDIV_OUT:[R]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.712 0.712 tNET RR 1 R22C48[0][A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/lane0_cnt_0_s1/CLK
0.853 0.141 tC2Q RF 6 R22C48[0][A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/lane0_cnt_0_s1/Q
0.859 0.006 tNET FF 1 R22C48[0][A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/n23_s3/I0
1.012 0.153 tINS FF 1 R22C48[0][A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/n23_s3/F
1.012 0.000 tNET FF 1 R22C48[0][A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/lane0_cnt_0_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.712 0.712 tNET RR 1 R22C48[0][A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/lane0_cnt_0_s1/CLK
0.737 0.025 tHld 1 R22C48[0][A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/lane0_cnt_0_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.712, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.712, 100.000%

Path8

Path Summary:

Slack 0.275
Data Arrival Time 1.005
Data Required Time 0.730
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1
Launch Clk Inst3_CLKDIV_OUT:[R]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.705 0.705 tNET RR 1 R9C54[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLK
0.846 0.141 tC2Q RF 4 R9C54[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/Q
0.852 0.006 tNET FF 1 R9C54[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n283_s0/I1
1.005 0.153 tINS FF 1 R9C54[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n283_s0/F
1.005 0.000 tNET FF 1 R9C54[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.705 0.705 tNET RR 1 R9C54[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLK
0.730 0.025 tHld 1 R9C54[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.705, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.705, 100.000%

Path9

Path Summary:

Slack 0.275
Data Arrival Time 2.836
Data Required Time 2.561
From gw_gao_inst_0/u_la0_top/word_count_7_s0
To gw_gao_inst_0/u_la0_top/word_count_7_s0
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 250 - gw_gao_inst_0/u_gw_jtag/tck_o
2.536 1.185 tNET RR 1 R24C52[0][A] gw_gao_inst_0/u_la0_top/word_count_7_s0/CLK
2.677 0.141 tC2Q RF 2 R24C52[0][A] gw_gao_inst_0/u_la0_top/word_count_7_s0/Q
2.683 0.006 tNET FF 1 R24C52[0][A] gw_gao_inst_0/u_la0_top/data_to_word_counter_7_s0/I1
2.836 0.153 tINS FF 1 R24C52[0][A] gw_gao_inst_0/u_la0_top/data_to_word_counter_7_s0/F
2.836 0.000 tNET FF 1 R24C52[0][A] gw_gao_inst_0/u_la0_top/word_count_7_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 250 - gw_gao_inst_0/u_gw_jtag/tck_o
2.536 1.185 tNET RR 1 R24C52[0][A] gw_gao_inst_0/u_la0_top/word_count_7_s0/CLK
2.561 0.025 tHld 1 R24C52[0][A] gw_gao_inst_0/u_la0_top/word_count_7_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.351, 53.278%; route: 1.185, 46.722%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 1.351, 53.278%; route: 1.185, 46.722%

Path10

Path Summary:

Slack 0.275
Data Arrival Time 2.832
Data Required Time 2.557
From gw_gao_inst_0/u_la0_top/word_count_11_s0
To gw_gao_inst_0/u_la0_top/word_count_11_s0
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 250 - gw_gao_inst_0/u_gw_jtag/tck_o
2.532 1.181 tNET RR 1 R24C57[0][A] gw_gao_inst_0/u_la0_top/word_count_11_s0/CLK
2.673 0.141 tC2Q RF 2 R24C57[0][A] gw_gao_inst_0/u_la0_top/word_count_11_s0/Q
2.679 0.006 tNET FF 1 R24C57[0][A] gw_gao_inst_0/u_la0_top/data_to_word_counter_11_s0/I1
2.832 0.153 tINS FF 1 R24C57[0][A] gw_gao_inst_0/u_la0_top/data_to_word_counter_11_s0/F
2.832 0.000 tNET FF 1 R24C57[0][A] gw_gao_inst_0/u_la0_top/word_count_11_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 250 - gw_gao_inst_0/u_gw_jtag/tck_o
2.532 1.181 tNET RR 1 R24C57[0][A] gw_gao_inst_0/u_la0_top/word_count_11_s0/CLK
2.557 0.025 tHld 1 R24C57[0][A] gw_gao_inst_0/u_la0_top/word_count_11_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.351, 53.362%; route: 1.181, 46.638%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 1.351, 53.362%; route: 1.181, 46.638%

Path11

Path Summary:

Slack 0.275
Data Arrival Time 2.830
Data Required Time 2.555
From gw_gao_inst_0/u_la0_top/address_counter_2_s0
To gw_gao_inst_0/u_la0_top/address_counter_2_s0
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 250 - gw_gao_inst_0/u_gw_jtag/tck_o
2.530 1.179 tNET RR 1 R23C58[1][A] gw_gao_inst_0/u_la0_top/address_counter_2_s0/CLK
2.671 0.141 tC2Q RF 7 R23C58[1][A] gw_gao_inst_0/u_la0_top/address_counter_2_s0/Q
2.677 0.006 tNET FF 1 R23C58[1][A] gw_gao_inst_0/u_la0_top/data_to_addr_counter_2_s0/I1
2.830 0.153 tINS FF 1 R23C58[1][A] gw_gao_inst_0/u_la0_top/data_to_addr_counter_2_s0/F
2.830 0.000 tNET FF 1 R23C58[1][A] gw_gao_inst_0/u_la0_top/address_counter_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 250 - gw_gao_inst_0/u_gw_jtag/tck_o
2.530 1.179 tNET RR 1 R23C58[1][A] gw_gao_inst_0/u_la0_top/address_counter_2_s0/CLK
2.555 0.025 tHld 1 R23C58[1][A] gw_gao_inst_0/u_la0_top/address_counter_2_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.351, 53.410%; route: 1.179, 46.590%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 1.351, 53.410%; route: 1.179, 46.590%

Path12

Path Summary:

Slack 0.275
Data Arrival Time 2.830
Data Required Time 2.555
From gw_gao_inst_0/u_la0_top/address_counter_4_s0
To gw_gao_inst_0/u_la0_top/address_counter_4_s0
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 250 - gw_gao_inst_0/u_gw_jtag/tck_o
2.530 1.179 tNET RR 1 R23C58[0][A] gw_gao_inst_0/u_la0_top/address_counter_4_s0/CLK
2.671 0.141 tC2Q RF 8 R23C58[0][A] gw_gao_inst_0/u_la0_top/address_counter_4_s0/Q
2.677 0.006 tNET FF 1 R23C58[0][A] gw_gao_inst_0/u_la0_top/data_to_addr_counter_4_s0/I1
2.830 0.153 tINS FF 1 R23C58[0][A] gw_gao_inst_0/u_la0_top/data_to_addr_counter_4_s0/F
2.830 0.000 tNET FF 1 R23C58[0][A] gw_gao_inst_0/u_la0_top/address_counter_4_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 250 - gw_gao_inst_0/u_gw_jtag/tck_o
2.530 1.179 tNET RR 1 R23C58[0][A] gw_gao_inst_0/u_la0_top/address_counter_4_s0/CLK
2.555 0.025 tHld 1 R23C58[0][A] gw_gao_inst_0/u_la0_top/address_counter_4_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.351, 53.410%; route: 1.179, 46.590%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 1.351, 53.410%; route: 1.179, 46.590%

Path13

Path Summary:

Slack 0.275
Data Arrival Time 2.831
Data Required Time 2.556
From gw_gao_inst_0/u_la0_top/address_counter_10_s0
To gw_gao_inst_0/u_la0_top/address_counter_10_s0
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 250 - gw_gao_inst_0/u_gw_jtag/tck_o
2.531 1.180 tNET RR 1 R22C58[1][A] gw_gao_inst_0/u_la0_top/address_counter_10_s0/CLK
2.672 0.141 tC2Q RF 5 R22C58[1][A] gw_gao_inst_0/u_la0_top/address_counter_10_s0/Q
2.678 0.006 tNET FF 1 R22C58[1][A] gw_gao_inst_0/u_la0_top/data_to_addr_counter_10_s0/I1
2.831 0.153 tINS FF 1 R22C58[1][A] gw_gao_inst_0/u_la0_top/data_to_addr_counter_10_s0/F
2.831 0.000 tNET FF 1 R22C58[1][A] gw_gao_inst_0/u_la0_top/address_counter_10_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 250 - gw_gao_inst_0/u_gw_jtag/tck_o
2.531 1.180 tNET RR 1 R22C58[1][A] gw_gao_inst_0/u_la0_top/address_counter_10_s0/CLK
2.556 0.025 tHld 1 R22C58[1][A] gw_gao_inst_0/u_la0_top/address_counter_10_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.351, 53.373%; route: 1.180, 46.627%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 1.351, 53.373%; route: 1.180, 46.627%

Path14

Path Summary:

Slack 0.275
Data Arrival Time 1.016
Data Required Time 0.741
From MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/lane0_cnt_2_s0
To MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/lane0_cnt_2_s0
Launch Clk Inst3_CLKDIV_OUT:[R]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.716 0.716 tNET RR 1 R22C51[0][A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/lane0_cnt_2_s0/CLK
0.857 0.141 tC2Q RF 4 R22C51[0][A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/lane0_cnt_2_s0/Q
0.863 0.006 tNET FF 1 R22C51[0][A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/n21_s0/I2
1.016 0.153 tINS FF 1 R22C51[0][A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/n21_s0/F
1.016 0.000 tNET FF 1 R22C51[0][A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/lane0_cnt_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.716 0.716 tNET RR 1 R22C51[0][A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/lane0_cnt_2_s0/CLK
0.741 0.025 tHld 1 R22C51[0][A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/lane0_cnt_2_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.716, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.716, 100.000%

Path15

Path Summary:

Slack 0.278
Data Arrival Time 2.835
Data Required Time 2.557
From gw_gao_inst_0/u_la0_top/word_count_1_s0
To gw_gao_inst_0/u_la0_top/word_count_1_s0
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 250 - gw_gao_inst_0/u_gw_jtag/tck_o
2.532 1.181 tNET RR 1 R24C53[0][A] gw_gao_inst_0/u_la0_top/word_count_1_s0/CLK
2.673 0.141 tC2Q RF 5 R24C53[0][A] gw_gao_inst_0/u_la0_top/word_count_1_s0/Q
2.682 0.009 tNET FF 1 R24C53[0][A] gw_gao_inst_0/u_la0_top/data_to_word_counter_1_s0/I2
2.835 0.153 tINS FF 1 R24C53[0][A] gw_gao_inst_0/u_la0_top/data_to_word_counter_1_s0/F
2.835 0.000 tNET FF 1 R24C53[0][A] gw_gao_inst_0/u_la0_top/word_count_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 250 - gw_gao_inst_0/u_gw_jtag/tck_o
2.532 1.181 tNET RR 1 R24C53[0][A] gw_gao_inst_0/u_la0_top/word_count_1_s0/CLK
2.557 0.025 tHld 1 R24C53[0][A] gw_gao_inst_0/u_la0_top/word_count_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.351, 53.362%; route: 1.181, 46.638%
Arrival Data Path Delay cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay cell: 1.351, 53.362%; route: 1.181, 46.638%

Path16

Path Summary:

Slack 0.278
Data Arrival Time 2.842
Data Required Time 2.564
From gw_gao_inst_0/u_la0_top/word_count_4_s0
To gw_gao_inst_0/u_la0_top/word_count_4_s0
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 250 - gw_gao_inst_0/u_gw_jtag/tck_o
2.539 1.188 tNET RR 1 R20C53[0][A] gw_gao_inst_0/u_la0_top/word_count_4_s0/CLK
2.680 0.141 tC2Q RF 5 R20C53[0][A] gw_gao_inst_0/u_la0_top/word_count_4_s0/Q
2.689 0.009 tNET FF 1 R20C53[0][A] gw_gao_inst_0/u_la0_top/data_to_word_counter_4_s0/I1
2.842 0.153 tINS FF 1 R20C53[0][A] gw_gao_inst_0/u_la0_top/data_to_word_counter_4_s0/F
2.842 0.000 tNET FF 1 R20C53[0][A] gw_gao_inst_0/u_la0_top/word_count_4_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 250 - gw_gao_inst_0/u_gw_jtag/tck_o
2.539 1.188 tNET RR 1 R20C53[0][A] gw_gao_inst_0/u_la0_top/word_count_4_s0/CLK
2.564 0.025 tHld 1 R20C53[0][A] gw_gao_inst_0/u_la0_top/word_count_4_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.351, 53.215%; route: 1.188, 46.785%
Arrival Data Path Delay cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay cell: 1.351, 53.215%; route: 1.188, 46.785%

Path17

Path Summary:

Slack 0.278
Data Arrival Time 1.013
Data Required Time 0.735
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Launch Clk Inst3_CLKDIV_OUT:[R]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.710 0.710 tNET RR 1 R8C58[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
0.851 0.141 tC2Q RF 9 R8C58[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/Q
0.860 0.009 tNET FF 1 R8C58[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n388_s1/I1
1.013 0.153 tINS FF 1 R8C58[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n388_s1/F
1.013 0.000 tNET FF 1 R8C58[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.710 0.710 tNET RR 1 R8C58[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
0.735 0.025 tHld 1 R8C58[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.710, 100.000%
Arrival Data Path Delay cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.710, 100.000%

Path18

Path Summary:

Slack 0.278
Data Arrival Time 1.010
Data Required Time 0.732
From gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s1
To gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s1
Launch Clk Inst3_CLKDIV_OUT:[R]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.707 0.707 tNET RR 1 R25C52[0][A] gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s1/CLK
0.848 0.141 tC2Q RF 5 R25C52[0][A] gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s1/Q
0.857 0.009 tNET FF 1 R25C52[0][A] gw_gao_inst_0/u_la0_top/n2136_s1/I0
1.010 0.153 tINS FF 1 R25C52[0][A] gw_gao_inst_0/u_la0_top/n2136_s1/F
1.010 0.000 tNET FF 1 R25C52[0][A] gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.707 0.707 tNET RR 1 R25C52[0][A] gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s1/CLK
0.732 0.025 tHld 1 R25C52[0][A] gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.707, 100.000%
Arrival Data Path Delay cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.707, 100.000%

Path19

Path Summary:

Slack 0.278
Data Arrival Time 1.001
Data Required Time 0.723
From gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1
To gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1
Launch Clk Inst3_CLKDIV_OUT:[R]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.698 0.698 tNET RR 1 R18C53[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLK
0.839 0.141 tC2Q RF 13 R18C53[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/Q
0.848 0.009 tNET FF 1 R18C53[1][A] gw_gao_inst_0/u_la0_top/n2185_s1/I0
1.001 0.153 tINS FF 1 R18C53[1][A] gw_gao_inst_0/u_la0_top/n2185_s1/F
1.001 0.000 tNET FF 1 R18C53[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.698 0.698 tNET RR 1 R18C53[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLK
0.723 0.025 tHld 1 R18C53[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.698, 100.000%
Arrival Data Path Delay cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.698, 100.000%

Path20

Path Summary:

Slack 0.281
Data Arrival Time 1.030
Data Required Time 0.749
From gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1
To gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1
Launch Clk Inst3_CLKDIV_OUT:[R]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.724 0.724 tNET RR 1 R20C58[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLK
0.865 0.141 tC2Q RF 10 R20C58[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/Q
0.877 0.012 tNET FF 1 R20C58[0][A] gw_gao_inst_0/u_la0_top/n2182_s1/I0
1.030 0.153 tINS FF 1 R20C58[0][A] gw_gao_inst_0/u_la0_top/n2182_s1/F
1.030 0.000 tNET FF 1 R20C58[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.724 0.724 tNET RR 1 R20C58[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLK
0.749 0.025 tHld 1 R20C58[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.724, 100.000%
Arrival Data Path Delay cell: 0.153, 50.000%; route: 0.012, 3.922%; tC2Q: 0.141, 46.078%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.724, 100.000%

Path21

Path Summary:

Slack 0.281
Data Arrival Time 1.030
Data Required Time 0.749
From gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1
To gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1
Launch Clk Inst3_CLKDIV_OUT:[R]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.724 0.724 tNET RR 1 R20C58[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLK
0.865 0.141 tC2Q RF 6 R20C58[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/Q
0.877 0.012 tNET FF 1 R20C58[1][A] gw_gao_inst_0/u_la0_top/n2180_s1/I2
1.030 0.153 tINS FF 1 R20C58[1][A] gw_gao_inst_0/u_la0_top/n2180_s1/F
1.030 0.000 tNET FF 1 R20C58[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.724 0.724 tNET RR 1 R20C58[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLK
0.749 0.025 tHld 1 R20C58[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.724, 100.000%
Arrival Data Path Delay cell: 0.153, 50.000%; route: 0.012, 3.922%; tC2Q: 0.141, 46.078%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.724, 100.000%

Path22

Path Summary:

Slack 0.281
Data Arrival Time 1.022
Data Required Time 0.741
From MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/lane2_cnt_0_s1
To MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/lane2_cnt_0_s1
Launch Clk Inst3_CLKDIV_OUT:[R]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.716 0.716 tNET RR 1 R22C47[0][A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/lane2_cnt_0_s1/CLK
0.857 0.141 tC2Q RF 6 R22C47[0][A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/lane2_cnt_0_s1/Q
0.869 0.012 tNET FF 1 R22C47[0][A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/n251_s3/I1
1.022 0.153 tINS FF 1 R22C47[0][A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/n251_s3/F
1.022 0.000 tNET FF 1 R22C47[0][A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/lane2_cnt_0_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.716 0.716 tNET RR 1 R22C47[0][A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/lane2_cnt_0_s1/CLK
0.741 0.025 tHld 1 R22C47[0][A] MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/lane2_cnt_0_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.716, 100.000%
Arrival Data Path Delay cell: 0.153, 50.000%; route: 0.012, 3.922%; tC2Q: 0.141, 46.078%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.716, 100.000%

Path23

Path Summary:

Slack 0.296
Data Arrival Time 1.027
Data Required Time 0.731
From u_ROM549x17/addr_1_s0
To u_ROM549x17/dout_rom_1_s
Launch Clk U3_CLKDIV:[R]
Latch Clk U3_CLKDIV:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 U3_CLKDIV
0.000 0.000 tCL RR 27 LEFTSIDE[0] U3_CLKDIV/CLKOUT
0.706 0.706 tNET RR 1 R8C48[0][A] u_ROM549x17/addr_1_s0/CLK
0.850 0.144 tC2Q RR 2 R8C48[0][A] u_ROM549x17/addr_1_s0/Q
1.027 0.177 tNET RR 1 BSRAM_R10[14] u_ROM549x17/dout_rom_1_s/AD[5]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 U3_CLKDIV
0.000 0.000 tCL RR 27 LEFTSIDE[0] U3_CLKDIV/CLKOUT
0.696 0.696 tNET RR 1 BSRAM_R10[14] u_ROM549x17/dout_rom_1_s/CLK
0.731 0.035 tHld 1 BSRAM_R10[14] u_ROM549x17/dout_rom_1_s

Path Statistics:

Clock Skew -0.010
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.706, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.177, 55.140%; tC2Q: 0.144, 44.860%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.696, 100.000%

Path24

Path Summary:

Slack 0.296
Data Arrival Time 1.027
Data Required Time 0.731
From u_ROM549x17/addr_0_s0
To u_ROM549x17/dout_rom_1_s
Launch Clk U3_CLKDIV:[R]
Latch Clk U3_CLKDIV:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 U3_CLKDIV
0.000 0.000 tCL RR 27 LEFTSIDE[0] U3_CLKDIV/CLKOUT
0.706 0.706 tNET RR 1 R8C48[3][A] u_ROM549x17/addr_0_s0/CLK
0.850 0.144 tC2Q RR 3 R8C48[3][A] u_ROM549x17/addr_0_s0/Q
1.027 0.177 tNET RR 1 BSRAM_R10[14] u_ROM549x17/dout_rom_1_s/AD[4]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 U3_CLKDIV
0.000 0.000 tCL RR 27 LEFTSIDE[0] U3_CLKDIV/CLKOUT
0.696 0.696 tNET RR 1 BSRAM_R10[14] u_ROM549x17/dout_rom_1_s/CLK
0.731 0.035 tHld 1 BSRAM_R10[14] u_ROM549x17/dout_rom_1_s

Path Statistics:

Clock Skew -0.010
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.706, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.177, 55.140%; tC2Q: 0.144, 44.860%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.696, 100.000%

Path25

Path Summary:

Slack 0.306
Data Arrival Time 2.858
Data Required Time 2.552
From gw_gao_inst_0/u_la0_top/expression0_addr_0_s0
To gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 250 - gw_gao_inst_0/u_gw_jtag/tck_o
2.525 1.174 tNET RR 1 R26C53[1][A] gw_gao_inst_0/u_la0_top/expression0_addr_0_s0/CLK
2.669 0.144 tC2Q RR 1 R26C53[1][A] gw_gao_inst_0/u_la0_top/expression0_addr_0_s0/Q
2.858 0.189 tNET RR 1 BSRAM_R28[16] gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s/ADA[0]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 250 - gw_gao_inst_0/u_gw_jtag/tck_o
2.515 1.164 tNET RR 1 BSRAM_R28[16] gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s/CLKA
2.552 0.037 tHld 1 BSRAM_R28[16] gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s

Path Statistics:

Clock Skew -0.010
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 1.351, 53.505%; route: 1.174, 46.495%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.189, 56.757%; tC2Q: 0.144, 43.243%
Required Clock Path Delay cell: 1.351, 53.718%; route: 1.164, 46.282%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 36.556
Data Arrival Time 45.025
Data Required Time 81.581
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
41.924 1.924 tNET FF 1 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
42.366 0.442 tC2Q FF 57 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
45.025 2.659 tNET FF 1 R18C53[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
80.000 80.000 active clock edge time
80.000 0.000 Inst3_CLKDIV_OUT
80.000 0.000 tCL RR 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
81.929 1.929 tNET RR 1 R18C53[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLK
81.581 -0.347 tSu 1 R18C53[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1

Path Statistics:

Clock Skew 0.005
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.924, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.659, 85.732%; tC2Q: 0.442, 14.268%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.929, 100.000%

Path2

Path Summary:

Slack 36.556
Data Arrival Time 45.025
Data Required Time 81.581
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
41.924 1.924 tNET FF 1 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
42.366 0.442 tC2Q FF 57 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
45.025 2.659 tNET FF 1 R18C53[1][B] gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
80.000 80.000 active clock edge time
80.000 0.000 Inst3_CLKDIV_OUT
80.000 0.000 tCL RR 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
81.929 1.929 tNET RR 1 R18C53[1][B] gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLK
81.581 -0.347 tSu 1 R18C53[1][B] gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1

Path Statistics:

Clock Skew 0.005
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.924, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.659, 85.732%; tC2Q: 0.442, 14.268%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.929, 100.000%

Path3

Path Summary:

Slack 36.556
Data Arrival Time 45.025
Data Required Time 81.581
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/trigger_seq_start_s1
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
41.924 1.924 tNET FF 1 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
42.366 0.442 tC2Q FF 57 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
45.025 2.659 tNET FF 1 R18C53[2][A] gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
80.000 80.000 active clock edge time
80.000 0.000 Inst3_CLKDIV_OUT
80.000 0.000 tCL RR 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
81.929 1.929 tNET RR 1 R18C53[2][A] gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLK
81.581 -0.347 tSu 1 R18C53[2][A] gw_gao_inst_0/u_la0_top/trigger_seq_start_s1

Path Statistics:

Clock Skew 0.005
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.924, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.659, 85.732%; tC2Q: 0.442, 14.268%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.929, 100.000%

Path4

Path Summary:

Slack 36.556
Data Arrival Time 45.025
Data Required Time 81.581
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/triger_s0
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
41.924 1.924 tNET FF 1 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
42.366 0.442 tC2Q FF 57 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
45.025 2.659 tNET FF 1 R18C53[0][A] gw_gao_inst_0/u_la0_top/triger_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
80.000 80.000 active clock edge time
80.000 0.000 Inst3_CLKDIV_OUT
80.000 0.000 tCL RR 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
81.929 1.929 tNET RR 1 R18C53[0][A] gw_gao_inst_0/u_la0_top/triger_s0/CLK
81.581 -0.347 tSu 1 R18C53[0][A] gw_gao_inst_0/u_la0_top/triger_s0

Path Statistics:

Clock Skew 0.005
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.924, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.659, 85.732%; tC2Q: 0.442, 14.268%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.929, 100.000%

Path5

Path Summary:

Slack 36.556
Data Arrival Time 45.025
Data Required Time 81.581
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/start_reg_s0
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
41.924 1.924 tNET FF 1 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
42.366 0.442 tC2Q FF 57 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
45.025 2.659 tNET FF 1 R18C53[0][B] gw_gao_inst_0/u_la0_top/start_reg_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
80.000 80.000 active clock edge time
80.000 0.000 Inst3_CLKDIV_OUT
80.000 0.000 tCL RR 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
81.929 1.929 tNET RR 1 R18C53[0][B] gw_gao_inst_0/u_la0_top/start_reg_s0/CLK
81.581 -0.347 tSu 1 R18C53[0][B] gw_gao_inst_0/u_la0_top/start_reg_s0

Path Statistics:

Clock Skew 0.005
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.924, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.659, 85.732%; tC2Q: 0.442, 14.268%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.929, 100.000%

Path6

Path Summary:

Slack 36.756
Data Arrival Time 44.825
Data Required Time 81.581
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
41.924 1.924 tNET FF 1 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
42.366 0.442 tC2Q FF 57 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
44.825 2.459 tNET FF 1 R18C57[0][A] gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
80.000 80.000 active clock edge time
80.000 0.000 Inst3_CLKDIV_OUT
80.000 0.000 tCL RR 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
81.929 1.929 tNET RR 1 R18C57[0][A] gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLK
81.581 -0.347 tSu 1 R18C57[0][A] gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0

Path Statistics:

Clock Skew 0.005
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.924, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.459, 84.748%; tC2Q: 0.442, 15.252%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.929, 100.000%

Path7

Path Summary:

Slack 36.766
Data Arrival Time 44.825
Data Required Time 81.591
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
41.924 1.924 tNET FF 1 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
42.366 0.442 tC2Q FF 57 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
44.825 2.459 tNET FF 1 R18C58[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
80.000 80.000 active clock edge time
80.000 0.000 Inst3_CLKDIV_OUT
80.000 0.000 tCL RR 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
81.938 1.938 tNET RR 1 R18C58[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLK
81.591 -0.347 tSu 1 R18C58[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3

Path Statistics:

Clock Skew 0.014
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.924, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.459, 84.748%; tC2Q: 0.442, 15.252%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.938, 100.000%

Path8

Path Summary:

Slack 36.766
Data Arrival Time 44.825
Data Required Time 81.591
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
41.924 1.924 tNET FF 1 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
42.366 0.442 tC2Q FF 57 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
44.825 2.459 tNET FF 1 R18C58[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
80.000 80.000 active clock edge time
80.000 0.000 Inst3_CLKDIV_OUT
80.000 0.000 tCL RR 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
81.938 1.938 tNET RR 1 R18C58[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLK
81.591 -0.347 tSu 1 R18C58[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1

Path Statistics:

Clock Skew 0.014
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.924, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.459, 84.748%; tC2Q: 0.442, 15.252%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.938, 100.000%

Path9

Path Summary:

Slack 36.766
Data Arrival Time 44.825
Data Required Time 81.591
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
41.924 1.924 tNET FF 1 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
42.366 0.442 tC2Q FF 57 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
44.825 2.459 tNET FF 1 R18C58[1][B] gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
80.000 80.000 active clock edge time
80.000 0.000 Inst3_CLKDIV_OUT
80.000 0.000 tCL RR 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
81.938 1.938 tNET RR 1 R18C58[1][B] gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLK
81.591 -0.347 tSu 1 R18C58[1][B] gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0

Path Statistics:

Clock Skew 0.014
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.924, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.459, 84.748%; tC2Q: 0.442, 15.252%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.938, 100.000%

Path10

Path Summary:

Slack 36.766
Data Arrival Time 44.825
Data Required Time 81.591
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
41.924 1.924 tNET FF 1 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
42.366 0.442 tC2Q FF 57 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
44.825 2.459 tNET FF 1 R18C58[2][A] gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
80.000 80.000 active clock edge time
80.000 0.000 Inst3_CLKDIV_OUT
80.000 0.000 tCL RR 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
81.938 1.938 tNET RR 1 R18C58[2][A] gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLK
81.591 -0.347 tSu 1 R18C58[2][A] gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0

Path Statistics:

Clock Skew 0.014
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.924, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.459, 84.748%; tC2Q: 0.442, 15.252%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.938, 100.000%

Path11

Path Summary:

Slack 36.913
Data Arrival Time 44.683
Data Required Time 81.596
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
41.924 1.924 tNET FF 1 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
42.366 0.442 tC2Q FF 57 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
44.683 2.316 tNET FF 1 R8C57[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
80.000 80.000 active clock edge time
80.000 0.000 Inst3_CLKDIV_OUT
80.000 0.000 tCL RR 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
81.943 1.943 tNET RR 1 R8C57[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLK
81.596 -0.347 tSu 1 R8C57[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1

Path Statistics:

Clock Skew 0.020
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.924, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.316, 83.960%; tC2Q: 0.442, 16.040%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.943, 100.000%

Path12

Path Summary:

Slack 37.006
Data Arrival Time 44.588
Data Required Time 81.594
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s1
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
41.924 1.924 tNET FF 1 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
42.366 0.442 tC2Q FF 57 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
44.588 2.221 tNET FF 1 R25C52[0][A] gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
80.000 80.000 active clock edge time
80.000 0.000 Inst3_CLKDIV_OUT
80.000 0.000 tCL RR 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
81.941 1.941 tNET RR 1 R25C52[0][A] gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s1/CLK
81.594 -0.347 tSu 1 R25C52[0][A] gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s1

Path Statistics:

Clock Skew 0.018
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.924, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.221, 83.388%; tC2Q: 0.442, 16.612%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.941, 100.000%

Path13

Path Summary:

Slack 37.006
Data Arrival Time 44.588
Data Required Time 81.594
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
41.924 1.924 tNET FF 1 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
42.366 0.442 tC2Q FF 57 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
44.588 2.221 tNET FF 1 R25C52[0][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
80.000 80.000 active clock edge time
80.000 0.000 Inst3_CLKDIV_OUT
80.000 0.000 tCL RR 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
81.941 1.941 tNET RR 1 R25C52[0][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLK
81.594 -0.347 tSu 1 R25C52[0][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1

Path Statistics:

Clock Skew 0.018
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.924, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.221, 83.388%; tC2Q: 0.442, 16.612%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.941, 100.000%

Path14

Path Summary:

Slack 37.006
Data Arrival Time 44.588
Data Required Time 81.594
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
41.924 1.924 tNET FF 1 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
42.366 0.442 tC2Q FF 57 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
44.588 2.221 tNET FF 1 R25C52[1][A] gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
80.000 80.000 active clock edge time
80.000 0.000 Inst3_CLKDIV_OUT
80.000 0.000 tCL RR 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
81.941 1.941 tNET RR 1 R25C52[1][A] gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLK
81.594 -0.347 tSu 1 R25C52[1][A] gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1

Path Statistics:

Clock Skew 0.018
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.924, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.221, 83.388%; tC2Q: 0.442, 16.612%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.941, 100.000%

Path15

Path Summary:

Slack 37.006
Data Arrival Time 44.588
Data Required Time 81.594
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
41.924 1.924 tNET FF 1 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
42.366 0.442 tC2Q FF 57 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
44.588 2.221 tNET FF 1 R25C52[1][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
80.000 80.000 active clock edge time
80.000 0.000 Inst3_CLKDIV_OUT
80.000 0.000 tCL RR 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
81.941 1.941 tNET RR 1 R25C52[1][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLK
81.594 -0.347 tSu 1 R25C52[1][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1

Path Statistics:

Clock Skew 0.018
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.924, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.221, 83.388%; tC2Q: 0.442, 16.612%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.941, 100.000%

Path16

Path Summary:

Slack 37.074
Data Arrival Time 44.515
Data Required Time 81.589
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
41.924 1.924 tNET FF 1 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
42.366 0.442 tC2Q FF 57 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
44.515 2.149 tNET FF 1 R9C53[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
80.000 80.000 active clock edge time
80.000 0.000 Inst3_CLKDIV_OUT
80.000 0.000 tCL RR 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
81.936 1.936 tNET RR 1 R9C53[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLK
81.589 -0.347 tSu 1 R9C53[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1

Path Statistics:

Clock Skew 0.012
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.924, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.149, 82.923%; tC2Q: 0.442, 17.077%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.936, 100.000%

Path17

Path Summary:

Slack 37.074
Data Arrival Time 44.515
Data Required Time 81.589
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
41.924 1.924 tNET FF 1 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
42.366 0.442 tC2Q FF 57 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
44.515 2.149 tNET FF 1 R9C53[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
80.000 80.000 active clock edge time
80.000 0.000 Inst3_CLKDIV_OUT
80.000 0.000 tCL RR 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
81.936 1.936 tNET RR 1 R9C53[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLK
81.589 -0.347 tSu 1 R9C53[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1

Path Statistics:

Clock Skew 0.012
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.924, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.149, 82.923%; tC2Q: 0.442, 17.077%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.936, 100.000%

Path18

Path Summary:

Slack 37.274
Data Arrival Time 44.315
Data Required Time 81.589
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
41.924 1.924 tNET FF 1 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
42.366 0.442 tC2Q FF 57 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
44.315 1.949 tNET FF 1 R9C57[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
80.000 80.000 active clock edge time
80.000 0.000 Inst3_CLKDIV_OUT
80.000 0.000 tCL RR 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
81.936 1.936 tNET RR 1 R9C57[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK
81.589 -0.347 tSu 1 R9C57[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1

Path Statistics:

Clock Skew 0.012
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.924, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.949, 81.495%; tC2Q: 0.442, 18.505%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.936, 100.000%

Path19

Path Summary:

Slack 37.274
Data Arrival Time 44.315
Data Required Time 81.589
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
41.924 1.924 tNET FF 1 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
42.366 0.442 tC2Q FF 57 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
44.315 1.949 tNET FF 1 R9C57[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
80.000 80.000 active clock edge time
80.000 0.000 Inst3_CLKDIV_OUT
80.000 0.000 tCL RR 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
81.936 1.936 tNET RR 1 R9C57[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK
81.589 -0.347 tSu 1 R9C57[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1

Path Statistics:

Clock Skew 0.012
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.924, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.949, 81.495%; tC2Q: 0.442, 18.505%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.936, 100.000%

Path20

Path Summary:

Slack 37.274
Data Arrival Time 44.315
Data Required Time 81.589
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
41.924 1.924 tNET FF 1 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
42.366 0.442 tC2Q FF 57 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
44.315 1.949 tNET FF 1 R9C57[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
80.000 80.000 active clock edge time
80.000 0.000 Inst3_CLKDIV_OUT
80.000 0.000 tCL RR 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
81.936 1.936 tNET RR 1 R9C57[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK
81.589 -0.347 tSu 1 R9C57[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1

Path Statistics:

Clock Skew 0.012
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.924, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.949, 81.495%; tC2Q: 0.442, 18.505%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.936, 100.000%

Path21

Path Summary:

Slack 37.276
Data Arrival Time 44.323
Data Required Time 81.598
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
41.924 1.924 tNET FF 1 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
42.366 0.442 tC2Q FF 57 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
44.323 1.956 tNET FF 1 R9C54[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
80.000 80.000 active clock edge time
80.000 0.000 Inst3_CLKDIV_OUT
80.000 0.000 tCL RR 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
81.946 1.946 tNET RR 1 R9C54[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLK
81.598 -0.347 tSu 1 R9C54[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1

Path Statistics:

Clock Skew 0.022
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.924, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.956, 81.553%; tC2Q: 0.442, 18.447%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.946, 100.000%

Path22

Path Summary:

Slack 37.276
Data Arrival Time 44.323
Data Required Time 81.598
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_10_s1
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
41.924 1.924 tNET FF 1 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
42.366 0.442 tC2Q FF 57 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
44.323 1.956 tNET FF 1 R9C54[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_10_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
80.000 80.000 active clock edge time
80.000 0.000 Inst3_CLKDIV_OUT
80.000 0.000 tCL RR 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
81.946 1.946 tNET RR 1 R9C54[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_10_s1/CLK
81.598 -0.347 tSu 1 R9C54[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_10_s1

Path Statistics:

Clock Skew 0.022
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.924, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.956, 81.553%; tC2Q: 0.442, 18.447%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.946, 100.000%

Path23

Path Summary:

Slack 37.283
Data Arrival Time 44.315
Data Required Time 81.598
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
41.924 1.924 tNET FF 1 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
42.366 0.442 tC2Q FF 57 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
44.315 1.949 tNET FF 1 R9C58[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
80.000 80.000 active clock edge time
80.000 0.000 Inst3_CLKDIV_OUT
80.000 0.000 tCL RR 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
81.946 1.946 tNET RR 1 R9C58[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK
81.598 -0.347 tSu 1 R9C58[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1

Path Statistics:

Clock Skew 0.022
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.924, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.949, 81.495%; tC2Q: 0.442, 18.505%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.946, 100.000%

Path24

Path Summary:

Slack 37.283
Data Arrival Time 44.315
Data Required Time 81.598
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
41.924 1.924 tNET FF 1 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
42.366 0.442 tC2Q FF 57 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
44.315 1.949 tNET FF 1 R9C58[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
80.000 80.000 active clock edge time
80.000 0.000 Inst3_CLKDIV_OUT
80.000 0.000 tCL RR 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
81.946 1.946 tNET RR 1 R9C58[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK
81.598 -0.347 tSu 1 R9C58[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1

Path Statistics:

Clock Skew 0.022
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.924, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.949, 81.495%; tC2Q: 0.442, 18.505%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.946, 100.000%

Path25

Path Summary:

Slack 37.392
Data Arrival Time 44.211
Data Required Time 81.604
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_0_s0
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
41.924 1.924 tNET FF 1 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
42.366 0.442 tC2Q FF 57 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
44.211 1.845 tNET FF 1 R21C52[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
80.000 80.000 active clock edge time
80.000 0.000 Inst3_CLKDIV_OUT
80.000 0.000 tCL RR 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
81.951 1.951 tNET RR 1 R21C52[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_0_s0/CLK
81.604 -0.347 tSu 1 R21C52[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_0_s0

Path Statistics:

Clock Skew 0.028
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.924, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.845, 80.656%; tC2Q: 0.442, 19.344%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.951, 100.000%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 40.414
Data Arrival Time 41.054
Data Required Time 0.640
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
40.701 0.702 tNET FF 1 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
40.860 0.158 tC2Q FR 57 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
41.054 0.194 tNET RR 1 R17C56[1][A] gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.692 0.692 tNET RR 1 R17C56[1][A] gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLK
0.640 -0.053 tHld 1 R17C56[1][A] gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0

Path Statistics:

Clock Skew -0.009
Hold Relationship -40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.702, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.194, 55.114%; tC2Q: 0.158, 44.886%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.692, 100.000%

Path2

Path Summary:

Slack 40.563
Data Arrival Time 41.229
Data Required Time 0.667
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
40.701 0.702 tNET FF 1 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
40.860 0.158 tC2Q FR 57 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
41.229 0.370 tNET RR 1 R20C57[0][B] gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.720 0.720 tNET RR 1 R20C57[0][B] gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLK
0.667 -0.053 tHld 1 R20C57[0][B] gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1

Path Statistics:

Clock Skew 0.018
Hold Relationship -40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.702, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.370, 70.076%; tC2Q: 0.158, 29.924%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.720, 100.000%

Path3

Path Summary:

Slack 40.563
Data Arrival Time 41.229
Data Required Time 0.667
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
40.701 0.702 tNET FF 1 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
40.860 0.158 tC2Q FR 57 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
41.229 0.370 tNET RR 1 R20C57[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.720 0.720 tNET RR 1 R20C57[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLK
0.667 -0.053 tHld 1 R20C57[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1

Path Statistics:

Clock Skew 0.018
Hold Relationship -40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.702, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.370, 70.076%; tC2Q: 0.158, 29.924%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.720, 100.000%

Path4

Path Summary:

Slack 40.575
Data Arrival Time 41.213
Data Required Time 0.638
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_end_dly_s0
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
40.701 0.702 tNET FF 1 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
40.860 0.158 tC2Q FR 57 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
41.213 0.353 tNET RR 1 R11C55[1][A] gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.691 0.691 tNET RR 1 R11C55[1][A] gw_gao_inst_0/u_la0_top/capture_end_dly_s0/CLK
0.638 -0.053 tHld 1 R11C55[1][A] gw_gao_inst_0/u_la0_top/capture_end_dly_s0

Path Statistics:

Clock Skew -0.011
Hold Relationship -40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.702, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.353, 69.080%; tC2Q: 0.158, 30.920%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.691, 100.000%

Path5

Path Summary:

Slack 40.659
Data Arrival Time 41.330
Data Required Time 0.671
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
40.701 0.702 tNET FF 1 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
40.860 0.158 tC2Q FR 57 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
41.330 0.470 tNET RR 1 R20C58[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.724 0.724 tNET RR 1 R20C58[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLK
0.671 -0.053 tHld 1 R20C58[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1

Path Statistics:

Clock Skew 0.022
Hold Relationship -40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.702, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.470, 74.841%; tC2Q: 0.158, 25.159%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.724, 100.000%

Path6

Path Summary:

Slack 40.659
Data Arrival Time 41.330
Data Required Time 0.671
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
40.701 0.702 tNET FF 1 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
40.860 0.158 tC2Q FR 57 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
41.330 0.470 tNET RR 1 R20C58[0][B] gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.724 0.724 tNET RR 1 R20C58[0][B] gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLK
0.671 -0.053 tHld 1 R20C58[0][B] gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1

Path Statistics:

Clock Skew 0.022
Hold Relationship -40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.702, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.470, 74.841%; tC2Q: 0.158, 25.159%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.724, 100.000%

Path7

Path Summary:

Slack 40.659
Data Arrival Time 41.330
Data Required Time 0.671
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
40.701 0.702 tNET FF 1 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
40.860 0.158 tC2Q FR 57 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
41.330 0.470 tNET RR 1 R20C58[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.724 0.724 tNET RR 1 R20C58[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLK
0.671 -0.053 tHld 1 R20C58[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1

Path Statistics:

Clock Skew 0.022
Hold Relationship -40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.702, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.470, 74.841%; tC2Q: 0.158, 25.159%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.724, 100.000%

Path8

Path Summary:

Slack 40.663
Data Arrival Time 41.327
Data Required Time 0.665
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
40.701 0.702 tNET FF 1 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
40.860 0.158 tC2Q FR 57 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
41.327 0.468 tNET RR 1 R21C57[1][B] gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.718 0.718 tNET RR 1 R21C57[1][B] gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLK
0.665 -0.053 tHld 1 R21C57[1][B] gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1

Path Statistics:

Clock Skew 0.016
Hold Relationship -40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.702, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.468, 74.760%; tC2Q: 0.158, 25.240%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.718, 100.000%

Path9

Path Summary:

Slack 40.663
Data Arrival Time 41.327
Data Required Time 0.665
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_10_s1
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
40.701 0.702 tNET FF 1 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
40.860 0.158 tC2Q FR 57 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
41.327 0.468 tNET RR 1 R21C57[2][B] gw_gao_inst_0/u_la0_top/capture_window_sel_10_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.718 0.718 tNET RR 1 R21C57[2][B] gw_gao_inst_0/u_la0_top/capture_window_sel_10_s1/CLK
0.665 -0.053 tHld 1 R21C57[2][B] gw_gao_inst_0/u_la0_top/capture_window_sel_10_s1

Path Statistics:

Clock Skew 0.016
Hold Relationship -40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.702, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.468, 74.760%; tC2Q: 0.158, 25.240%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.718, 100.000%

Path10

Path Summary:

Slack 40.675
Data Arrival Time 41.317
Data Required Time 0.642
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
40.701 0.702 tNET FF 1 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
40.860 0.158 tC2Q FR 57 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
41.317 0.457 tNET RR 1 R11C54[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.695 0.695 tNET RR 1 R11C54[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLK
0.642 -0.053 tHld 1 R11C54[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1

Path Statistics:

Clock Skew -0.007
Hold Relationship -40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.702, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.457, 74.309%; tC2Q: 0.158, 25.691%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.695, 100.000%

Path11

Path Summary:

Slack 40.675
Data Arrival Time 41.317
Data Required Time 0.642
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
40.701 0.702 tNET FF 1 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
40.860 0.158 tC2Q FR 57 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
41.317 0.457 tNET RR 1 R11C54[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.695 0.695 tNET RR 1 R11C54[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLK
0.642 -0.053 tHld 1 R11C54[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1

Path Statistics:

Clock Skew -0.007
Hold Relationship -40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.702, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.457, 74.309%; tC2Q: 0.158, 25.691%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.695, 100.000%

Path12

Path Summary:

Slack 40.675
Data Arrival Time 41.317
Data Required Time 0.642
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
40.701 0.702 tNET FF 1 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
40.860 0.158 tC2Q FR 57 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
41.317 0.457 tNET RR 1 R11C54[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.695 0.695 tNET RR 1 R11C54[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLK
0.642 -0.053 tHld 1 R11C54[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1

Path Statistics:

Clock Skew -0.007
Hold Relationship -40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.702, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.457, 74.309%; tC2Q: 0.158, 25.691%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.695, 100.000%

Path13

Path Summary:

Slack 40.675
Data Arrival Time 41.317
Data Required Time 0.642
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
40.701 0.702 tNET FF 1 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
40.860 0.158 tC2Q FR 57 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
41.317 0.457 tNET RR 1 R11C54[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.695 0.695 tNET RR 1 R11C54[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLK
0.642 -0.053 tHld 1 R11C54[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1

Path Statistics:

Clock Skew -0.007
Hold Relationship -40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.702, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.457, 74.309%; tC2Q: 0.158, 25.691%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.695, 100.000%

Path14

Path Summary:

Slack 40.679
Data Arrival Time 41.317
Data Required Time 0.638
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
40.701 0.702 tNET FF 1 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
40.860 0.158 tC2Q FR 57 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
41.317 0.457 tNET RR 1 R11C53[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.691 0.691 tNET RR 1 R11C53[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLK
0.638 -0.053 tHld 1 R11C53[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1

Path Statistics:

Clock Skew -0.011
Hold Relationship -40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.702, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.457, 74.309%; tC2Q: 0.158, 25.691%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.691, 100.000%

Path15

Path Summary:

Slack 40.679
Data Arrival Time 41.317
Data Required Time 0.638
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
40.701 0.702 tNET FF 1 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
40.860 0.158 tC2Q FR 57 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
41.317 0.457 tNET RR 1 R11C53[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.691 0.691 tNET RR 1 R11C53[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLK
0.638 -0.053 tHld 1 R11C53[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1

Path Statistics:

Clock Skew -0.011
Hold Relationship -40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.702, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.457, 74.309%; tC2Q: 0.158, 25.691%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.691, 100.000%

Path16

Path Summary:

Slack 40.679
Data Arrival Time 41.317
Data Required Time 0.638
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
40.701 0.702 tNET FF 1 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
40.860 0.158 tC2Q FR 57 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
41.317 0.457 tNET RR 1 R11C53[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.691 0.691 tNET RR 1 R11C53[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLK
0.638 -0.053 tHld 1 R11C53[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1

Path Statistics:

Clock Skew -0.011
Hold Relationship -40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.702, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.457, 74.309%; tC2Q: 0.158, 25.691%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.691, 100.000%

Path17

Path Summary:

Slack 40.771
Data Arrival Time 41.436
Data Required Time 0.665
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
40.701 0.702 tNET FF 1 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
40.860 0.158 tC2Q FR 57 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
41.436 0.576 tNET RR 1 R21C55[0][A] gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.718 0.718 tNET RR 1 R21C55[0][A] gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLK
0.665 -0.053 tHld 1 R21C55[0][A] gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0

Path Statistics:

Clock Skew 0.016
Hold Relationship -40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.702, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.576, 78.474%; tC2Q: 0.158, 21.526%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.718, 100.000%

Path18

Path Summary:

Slack 40.818
Data Arrival Time 41.470
Data Required Time 0.652
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
40.701 0.702 tNET FF 1 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
40.860 0.158 tC2Q FR 57 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
41.470 0.610 tNET RR 1 R9C58[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.705 0.705 tNET RR 1 R9C58[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK
0.652 -0.053 tHld 1 R9C58[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1

Path Statistics:

Clock Skew 0.003
Hold Relationship -40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.702, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.610, 79.427%; tC2Q: 0.158, 20.573%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.705, 100.000%

Path19

Path Summary:

Slack 40.818
Data Arrival Time 41.470
Data Required Time 0.652
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
40.701 0.702 tNET FF 1 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
40.860 0.158 tC2Q FR 57 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
41.470 0.610 tNET RR 1 R9C58[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.705 0.705 tNET RR 1 R9C58[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/CLK
0.652 -0.053 tHld 1 R9C58[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1

Path Statistics:

Clock Skew 0.003
Hold Relationship -40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.702, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.610, 79.427%; tC2Q: 0.158, 20.573%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.705, 100.000%

Path20

Path Summary:

Slack 40.861
Data Arrival Time 41.529
Data Required Time 0.669
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
40.701 0.702 tNET FF 1 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
40.860 0.158 tC2Q FR 57 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
41.529 0.670 tNET RR 1 R21C54[0][B] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.722 0.722 tNET RR 1 R21C54[0][B] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLK
0.669 -0.053 tHld 1 R21C54[0][B] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0

Path Statistics:

Clock Skew 0.020
Hold Relationship -40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.702, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.670, 80.918%; tC2Q: 0.158, 19.082%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.722, 100.000%

Path21

Path Summary:

Slack 40.861
Data Arrival Time 41.529
Data Required Time 0.669
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
40.701 0.702 tNET FF 1 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
40.860 0.158 tC2Q FR 57 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
41.529 0.670 tNET RR 1 R21C54[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.722 0.722 tNET RR 1 R21C54[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLK
0.669 -0.053 tHld 1 R21C54[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0

Path Statistics:

Clock Skew 0.020
Hold Relationship -40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.702, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.670, 80.918%; tC2Q: 0.158, 19.082%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.722, 100.000%

Path22

Path Summary:

Slack 41.002
Data Arrival Time 41.668
Data Required Time 0.667
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
40.701 0.702 tNET FF 1 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
40.860 0.158 tC2Q FR 57 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
41.668 0.809 tNET RR 1 R20C53[1][A] gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.720 0.720 tNET RR 1 R20C53[1][A] gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLK
0.667 -0.053 tHld 1 R20C53[1][A] gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0

Path Statistics:

Clock Skew 0.018
Hold Relationship -40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.702, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.809, 83.661%; tC2Q: 0.158, 16.339%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.720, 100.000%

Path23

Path Summary:

Slack 41.048
Data Arrival Time 41.705
Data Required Time 0.657
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
40.701 0.702 tNET FF 1 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
40.860 0.158 tC2Q FR 57 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
41.705 0.845 tNET RR 1 R8C58[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.710 0.710 tNET RR 1 R8C58[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
0.657 -0.053 tHld 1 R8C58[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1

Path Statistics:

Clock Skew 0.008
Hold Relationship -40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.702, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.845, 84.247%; tC2Q: 0.158, 15.753%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.710, 100.000%

Path24

Path Summary:

Slack 41.048
Data Arrival Time 41.705
Data Required Time 0.657
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
40.701 0.702 tNET FF 1 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
40.860 0.158 tC2Q FR 57 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
41.705 0.845 tNET RR 1 R8C58[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.710 0.710 tNET RR 1 R8C58[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
0.657 -0.053 tHld 1 R8C58[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1

Path Statistics:

Clock Skew 0.008
Hold Relationship -40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.702, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.845, 84.247%; tC2Q: 0.158, 15.753%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.710, 100.000%

Path25

Path Summary:

Slack 41.048
Data Arrival Time 41.705
Data Required Time 0.657
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
Launch Clk Inst3_CLKDIV_OUT:[F]
Latch Clk Inst3_CLKDIV_OUT:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 Inst3_CLKDIV_OUT
40.000 0.000 tCL FF 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
40.701 0.702 tNET FF 1 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
40.860 0.158 tC2Q FR 57 R18C57[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
41.705 0.845 tNET RR 1 R8C58[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 Inst3_CLKDIV_OUT
0.000 0.000 tCL RR 939 LEFTSIDE[2] MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.710 0.710 tNET RR 1 R8C58[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK
0.657 -0.053 tHld 1 R8C58[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1

Path Statistics:

Clock Skew 0.008
Hold Relationship -40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.702, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.845, 84.247%; tC2Q: 0.158, 15.753%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.710, 100.000%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack: 3.507
Actual Width: 3.757
Required Width: 0.250
Type: Low Pulse Width
Clock: HS_CLK
Objects: MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_2_s0

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 HS_CLK
5.000 0.000 tCL FF MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
6.966 1.966 tNET FF MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_2_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 HS_CLK
10.000 0.000 tCL RR MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
10.723 0.723 tNET RR MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_2_s0/CLK

MPW2

MPW Summary:

Slack: 3.507
Actual Width: 3.757
Required Width: 0.250
Type: Low Pulse Width
Clock: HS_CLK
Objects: MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 HS_CLK
5.000 0.000 tCL FF MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
6.966 1.966 tNET FF MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 HS_CLK
10.000 0.000 tCL RR MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
10.723 0.723 tNET RR MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0/CLK

MPW3

MPW Summary:

Slack: 3.507
Actual Width: 3.757
Required Width: 0.250
Type: Low Pulse Width
Clock: HS_CLK
Objects: MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 HS_CLK
5.000 0.000 tCL FF MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
6.966 1.966 tNET FF MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 HS_CLK
10.000 0.000 tCL RR MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
10.723 0.723 tNET RR MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/CLK

MPW4

MPW Summary:

Slack: 3.507
Actual Width: 3.757
Required Width: 0.250
Type: Low Pulse Width
Clock: HS_CLK
Objects: MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 HS_CLK
5.000 0.000 tCL FF MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
6.966 1.966 tNET FF MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 HS_CLK
10.000 0.000 tCL RR MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
10.723 0.723 tNET RR MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0/CLK

MPW5

MPW Summary:

Slack: 3.512
Actual Width: 3.762
Required Width: 0.250
Type: High Pulse Width
Clock: HS_CLK
Objects: MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_2_s0

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 HS_CLK
0.000 0.000 tCL RR MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
1.966 1.966 tNET RR MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_2_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 HS_CLK
5.000 0.000 tCL FF MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
5.728 0.728 tNET FF MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_2_s0/CLK

MPW6

MPW Summary:

Slack: 3.512
Actual Width: 3.762
Required Width: 0.250
Type: High Pulse Width
Clock: HS_CLK
Objects: MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 HS_CLK
0.000 0.000 tCL RR MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
1.966 1.966 tNET RR MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 HS_CLK
5.000 0.000 tCL FF MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
5.728 0.728 tNET FF MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0/CLK

MPW7

MPW Summary:

Slack: 3.512
Actual Width: 3.762
Required Width: 0.250
Type: High Pulse Width
Clock: HS_CLK
Objects: MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 HS_CLK
0.000 0.000 tCL RR MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
1.966 1.966 tNET RR MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 HS_CLK
5.000 0.000 tCL FF MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
5.728 0.728 tNET FF MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0/CLK

MPW8

MPW Summary:

Slack: 3.512
Actual Width: 3.762
Required Width: 0.250
Type: High Pulse Width
Clock: HS_CLK
Objects: MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 HS_CLK
0.000 0.000 tCL RR MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
1.966 1.966 tNET RR MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 HS_CLK
5.000 0.000 tCL FF MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
5.728 0.728 tNET FF MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/CLK

MPW9

MPW Summary:

Slack: 22.199
Actual Width: 23.199
Required Width: 1.000
Type: Low Pulse Width
Clock: tck_pad_i
Objects: gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Late clock Path:

AT DELAY TYPE RF NODE
25.000 0.000 active clock edge time
25.000 0.000 tck_pad_i
25.000 0.000 tCL FF gw_gao_inst_0/tck_ibuf/I
25.688 0.688 tINS FF gw_gao_inst_0/tck_ibuf/O
25.688 0.000 tNET FF gw_gao_inst_0/u_gw_jtag/tck_pad_i
26.375 0.688 tINS FF gw_gao_inst_0/u_gw_jtag/tck_o
29.320 2.945 tNET FF gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKB

Early clock Path:

AT DELAY TYPE RF NODE
50.000 0.000 active clock edge time
50.000 0.000 tck_pad_i
50.000 0.000 tCL RR gw_gao_inst_0/tck_ibuf/I
50.675 0.675 tINS RR gw_gao_inst_0/tck_ibuf/O
50.675 0.000 tNET RR gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.351 0.675 tINS RR gw_gao_inst_0/u_gw_jtag/tck_o
52.519 1.168 tNET RR gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKB

MPW10

MPW Summary:

Slack: 22.205
Actual Width: 23.205
Required Width: 1.000
Type: Low Pulse Width
Clock: tck_pad_i
Objects: gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Late clock Path:

AT DELAY TYPE RF NODE
25.000 0.000 active clock edge time
25.000 0.000 tck_pad_i
25.000 0.000 tCL FF gw_gao_inst_0/tck_ibuf/I
25.688 0.688 tINS FF gw_gao_inst_0/tck_ibuf/O
25.688 0.000 tNET FF gw_gao_inst_0/u_gw_jtag/tck_pad_i
26.375 0.688 tINS FF gw_gao_inst_0/u_gw_jtag/tck_o
29.310 2.935 tNET FF gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKB

Early clock Path:

AT DELAY TYPE RF NODE
50.000 0.000 active clock edge time
50.000 0.000 tck_pad_i
50.000 0.000 tCL RR gw_gao_inst_0/tck_ibuf/I
50.675 0.675 tINS RR gw_gao_inst_0/tck_ibuf/O
50.675 0.000 tNET RR gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.351 0.675 tINS RR gw_gao_inst_0/u_gw_jtag/tck_o
52.515 1.164 tNET RR gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKB

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT NET NAME WORST SLACK MAX DELAY
939 clk_byte_out 72.511 1.974
460 GND 1.483 0.676
250 control0[0] 17.999 2.994
78 ready_d 76.393 3.404
57 rst_ao 36.556 2.770
54 n20_3 44.877 2.636
43 op_reg_en 43.078 1.511
41 shftamt[7] 75.066 2.772
36 n995_5 43.527 1.183
34 n995_13 43.720 1.841

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC ROUTE CONGESTIONS
R9C35 50.00%
R14C54 50.00%
R27C36 48.61%
R9C34 48.61%
R10C56 45.83%
R12C43 45.83%
R27C35 44.44%
R27C45 44.44%
R11C34 44.44%
R12C48 44.44%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type State Detail Command
TC_CLOCK Actived create_clock -name U0_IB -period 10 -waveform {0 5} [get_pins {MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/I}]
TC_CLOCK Actived create_clock -name sys_clk -period 20 -waveform {0 10} [get_ports {clkx2x4}]
TC_CLOCK Actived create_clock -name PLL_0 -period 100 -waveform {0 50} [get_pins {PLLA_mipi_tx/CLKOUT0}]
TC_CLOCK Actived create_clock -name PLL_1 -period 100 -waveform {0 50} [get_pins {PLLA_mipi_tx/CLKOUT1}]
TC_CLOCK Actived create_clock -name HS_CLK -period 10 -waveform {0 5} [get_nets {MIPI_RX_Advance_Top/DPHY_RX_INST/HS_CLK}]
TC_CLOCK Actived create_clock -name Inst3_CLKDIV_OUT -period 80 -waveform {0 40} [get_pins {MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT}]
TC_CLOCK Actived create_clock -name U3_CLKDIV -period 800 -waveform {0 400} [get_pins {U3_CLKDIV/CLKOUT}]
TC_CLOCK Actived create_clock -name tck_pad_i -period 50 -waveform {0 25} [get_ports {tck_pad_i}]
TC_FALSE_PATH Actived set_false_path -from [get_regs {MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0}]
TC_FALSE_PATH Actived set_false_path -from [get_regs {MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0}]
TC_CLOCK_GROUP Actived set_clock_groups -exclusive -group [get_clocks {PLL_0 PLL_1}] -group [get_clocks {U3_CLKDIV}] -group [get_clocks {tck_pad_i}] -group [get_clocks {Inst3_CLKDIV_OUT}] -group [get_clocks {U0_IB}] -group [get_clocks {sys_clk}] -group [get_clocks {HS_CLK}]