Synthesis Messages

Report Title GowinSynthesis Report
Design File E:\myWork\IP\releaseVerify\version\1.9.10.03\Gowin_MIPI_DPHY_Advance_RefDesign\MIPI_RefDesign_5a138_LVDS\MIPI_RefDesign\src\DPHY_TOP.v
E:\myWork\IP\releaseVerify\version\1.9.10.03\Gowin_MIPI_DPHY_Advance_RefDesign\MIPI_RefDesign_5a138_LVDS\MIPI_RefDesign\src\ROM549X17.v
E:\myWork\IP\releaseVerify\version\1.9.10.03\Gowin_MIPI_DPHY_Advance_RefDesign\MIPI_RefDesign_5a138_LVDS\MIPI_RefDesign\src\mipi_rx_advance\mipi_rx_advance.v
E:\myWork\IP\releaseVerify\version\1.9.10.03\Gowin_MIPI_DPHY_Advance_RefDesign\MIPI_RefDesign_5a138_LVDS\MIPI_RefDesign\src\mipi_tx_advance\mipi_tx_advance.v
C:\Gowin\Gowin_V1.9.10.03_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v
C:\Gowin\Gowin_V1.9.10.03_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v
C:\Gowin\Gowin_V1.9.10.03_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v
C:\Gowin\Gowin_V1.9.10.03_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v
C:\Gowin\Gowin_V1.9.10.03_x64\IDE\data\ipcores\GAO\GW_CON\gw_con_top_138.v
C:\Gowin\Gowin_V1.9.10.03_x64\IDE\data\ipcores\gw_jtag.v
E:\myWork\IP\releaseVerify\version\1.9.10.03\Gowin_MIPI_DPHY_Advance_RefDesign\MIPI_RefDesign_5a138_LVDS\MIPI_RefDesign\impl\gwsynthesis\RTL_GAO\gw_gao_top.v
GowinSynthesis Constraints File ---
Tool Version V1.9.10.03 (64-bit)
Part Number GW5AST-LV138FPG676AES
Device GW5AST-138
Device Version B
Created Time Thu Oct 24 14:15:05 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module DPHY_TOP
Synthesis Process Running parser:
    CPU time = 0h 0m 0.64s, Elapsed time = 0h 0m 0.587s, Peak memory usage = 1426.465MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.078s, Peak memory usage = 1426.465MB
    Optimizing Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.029s, Peak memory usage = 1426.465MB
    Optimizing Phase 2: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.088s, Peak memory usage = 1426.465MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.031s, Peak memory usage = 1426.465MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 1426.465MB
    Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 1426.465MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 1426.465MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.046s, Peak memory usage = 1426.465MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.014s, Peak memory usage = 1426.465MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 1426.465MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 2s, Peak memory usage = 1426.465MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.066s, Peak memory usage = 1426.465MB
Generate output files:
    CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.086s, Peak memory usage = 1426.465MB
Total Time and Memory Usage CPU time = 0h 0m 2s, Elapsed time = 0h 0m 3s, Peak memory usage = 1426.465MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 29
I/O Buf 19
    IBUF 4
    OBUF 5
    ELVDS_TBUF 5
    ELVDS_IOBUF 5
Register 901
    DFFRE 2
    DFFPE 37
    DFFCE 862
LUT 929
    LUT2 94
    LUT3 158
    LUT4 677
MUX 1
    MUX16 1
ALU 23
    ALU 23
INV 9
    INV 9
IOLOGIC 13
    IDES8 4
    OSER8 5
    IODELAY 4
BSRAM 6
    SDPB 1
    SDPX9B 4
    pROM 1
CLOCK 4
    PLL 1
    CLKDIV 2
    DHCE 1
Black Box 1
    GW_JTAG 1

Resource Utilization Summary

Resource Usage Utilization
Logic 969(946 LUT, 23 ALU) / 138240 <1%
Register 901 / 139140 <1%
  --Register as Latch 0 / 139140 0%
  --Register as FF 901 / 139140 <1%
BSRAM 6 / 340 2%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 clkx2x4 Base 20.000 50.0 0.000 10.000 clkx2x4_ibuf/I
2 MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/I Base 10.000 100.0 0.000 5.000 MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/I
3 MIPI_RX_Advance_Top/DPHY_RX_INST/HS_CLK Base 10.000 100.0 0.000 5.000 MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
4 PLL_mipi_tx/CLKOUT0.default_gen_clk Generated 50.000 20.0 0.000 25.000 clkx2x4_ibuf/I clkx2x4 PLL_mipi_tx/CLKOUT0
5 PLL_mipi_tx/CLKOUT1.default_gen_clk Generated 50.000 20.0 0.000 25.000 clkx2x4_ibuf/I clkx2x4 PLL_mipi_tx/CLKOUT1
6 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT.default_gen_clk Generated 40.000 25.0 0.000 20.000 MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O MIPI_RX_Advance_Top/DPHY_RX_INST/HS_CLK MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
7 U3_CLKDIV/CLKOUT.default_gen_clk Generated 200.000 5.0 0.000 100.000 PLL_mipi_tx/CLKOUT0 PLL_mipi_tx/CLKOUT0.default_gen_clk U3_CLKDIV/CLKOUT

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 MIPI_RX_Advance_Top/DPHY_RX_INST/HS_CLK 100.000(MHz) 259.808(MHz) 2 TOP
2 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT.default_gen_clk 25.000(MHz) 175.131(MHz) 6 TOP
3 U3_CLKDIV/CLKOUT.default_gen_clk 5.000(MHz) 405.678(MHz) 4 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 3.076
Data Arrival Time 2.128
Data Required Time 5.203
From MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0
To MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN
Launch Clk MIPI_RX_Advance_Top/DPHY_RX_INST/HS_CLK[F]
Latch Clk MIPI_RX_Advance_Top/DPHY_RX_INST/HS_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 MIPI_RX_Advance_Top/DPHY_RX_INST/HS_CLK
0.000 0.000 tCL RR 5 MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
0.413 0.413 tNET RR 1 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0/CLK
0.795 0.382 tC2Q RR 2 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0/Q
1.207 0.413 tNET RR 1 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/LUT4_0/I2
1.715 0.507 tINS RR 1 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/LUT4_0/F
2.128 0.413 tNET RR 1 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CEN
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
5.000 0.000 MIPI_RX_Advance_Top/DPHY_RX_INST/HS_CLK
5.000 0.000 tCL FF 5 MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
5.385 0.385 tNET FF 3 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CLKIN
5.203 -0.182 tSu 1 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN
Path Statistics:
Clock Skew: -0.028
Setup Relationship: 5.000
Logic Level: 2
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 0.507, 29.592%; route: 0.825, 48.105%; tC2Q: 0.382, 22.303%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 2

Path Summary:
Slack 7.974
Data Arrival Time 2.128
Data Required Time 10.101
From MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0
To MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0
Launch Clk MIPI_RX_Advance_Top/DPHY_RX_INST/HS_CLK[R]
Latch Clk MIPI_RX_Advance_Top/DPHY_RX_INST/HS_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 MIPI_RX_Advance_Top/DPHY_RX_INST/HS_CLK
0.000 0.000 tCL RR 5 MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
0.413 0.413 tNET RR 1 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/CLK
0.795 0.382 tC2Q RR 2 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/Q
1.207 0.413 tNET RR 1 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/LUT4_1/I2
1.715 0.507 tINS RR 4 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/LUT4_1/F
2.128 0.413 tNET RR 1 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 MIPI_RX_Advance_Top/DPHY_RX_INST/HS_CLK
10.000 0.000 tCL RR 5 MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
10.413 0.413 tNET RR 1 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0/CLK
10.101 -0.311 tSu 1 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 2
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 0.507, 29.592%; route: 0.825, 48.105%; tC2Q: 0.382, 22.303%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 3

Path Summary:
Slack 7.974
Data Arrival Time 2.128
Data Required Time 10.101
From MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0
To MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0
Launch Clk MIPI_RX_Advance_Top/DPHY_RX_INST/HS_CLK[R]
Latch Clk MIPI_RX_Advance_Top/DPHY_RX_INST/HS_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 MIPI_RX_Advance_Top/DPHY_RX_INST/HS_CLK
0.000 0.000 tCL RR 5 MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
0.413 0.413 tNET RR 1 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/CLK
0.795 0.382 tC2Q RR 2 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/Q
1.207 0.413 tNET RR 1 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/LUT4_1/I2
1.715 0.507 tINS RR 4 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/LUT4_1/F
2.128 0.413 tNET RR 1 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 MIPI_RX_Advance_Top/DPHY_RX_INST/HS_CLK
10.000 0.000 tCL RR 5 MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
10.413 0.413 tNET RR 1 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/CLK
10.101 -0.311 tSu 1 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 2
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 0.507, 29.592%; route: 0.825, 48.105%; tC2Q: 0.382, 22.303%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 4

Path Summary:
Slack 7.974
Data Arrival Time 2.128
Data Required Time 10.101
From MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0
To MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0
Launch Clk MIPI_RX_Advance_Top/DPHY_RX_INST/HS_CLK[R]
Latch Clk MIPI_RX_Advance_Top/DPHY_RX_INST/HS_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 MIPI_RX_Advance_Top/DPHY_RX_INST/HS_CLK
0.000 0.000 tCL RR 5 MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
0.413 0.413 tNET RR 1 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/CLK
0.795 0.382 tC2Q RR 2 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/Q
1.207 0.413 tNET RR 1 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/LUT4_1/I2
1.715 0.507 tINS RR 4 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/LUT4_1/F
2.128 0.413 tNET RR 1 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 MIPI_RX_Advance_Top/DPHY_RX_INST/HS_CLK
10.000 0.000 tCL RR 5 MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
10.413 0.413 tNET RR 1 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0/CLK
10.101 -0.311 tSu 1 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 2
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 0.507, 29.592%; route: 0.825, 48.105%; tC2Q: 0.382, 22.303%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 5

Path Summary:
Slack 7.974
Data Arrival Time 2.128
Data Required Time 10.101
From MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0
To MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_2_s0
Launch Clk MIPI_RX_Advance_Top/DPHY_RX_INST/HS_CLK[R]
Latch Clk MIPI_RX_Advance_Top/DPHY_RX_INST/HS_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 MIPI_RX_Advance_Top/DPHY_RX_INST/HS_CLK
0.000 0.000 tCL RR 5 MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
0.413 0.413 tNET RR 1 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/CLK
0.795 0.382 tC2Q RR 2 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/Q
1.207 0.413 tNET RR 1 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/LUT4_1/I2
1.715 0.507 tINS RR 4 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/LUT4_1/F
2.128 0.413 tNET RR 1 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_2_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 MIPI_RX_Advance_Top/DPHY_RX_INST/HS_CLK
10.000 0.000 tCL RR 5 MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
10.413 0.413 tNET RR 1 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_2_s0/CLK
10.101 -0.311 tSu 1 MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_2_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 2
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 0.507, 29.592%; route: 0.825, 48.105%; tC2Q: 0.382, 22.303%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%