Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | C:\Gowin\Gowin_V1.9.10.03_x64\IDE\ipcore\MIPI_RX_Advance\data\DPHY_RX.vp C:\Gowin\Gowin_V1.9.10.03_x64\IDE\ipcore\MIPI_RX_Advance\data\DPHY_RX_TOP.v |
GowinSynthesis Constraints File | --- |
Tool Version | V1.9.10.03 (64-bit) |
Part Number | GW5AST-LV138FPG676AES |
Device | GW5AST-138 |
Device Version | B |
Created Time | Thu Oct 24 14:14:53 2024 |
Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | MIPI_RX_Advance_Top |
Synthesis Process | Running parser: CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.22s, Peak memory usage = 107.672MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 107.672MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.015s, Peak memory usage = 107.672MB Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 107.672MB Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 107.672MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 107.672MB Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 107.672MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 107.672MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 107.672MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.015s, Peak memory usage = 107.672MB Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 107.672MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 107.672MB Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 132.145MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.054s, Peak memory usage = 132.145MB Generate output files: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.044s, Peak memory usage = 132.145MB |
Total Time and Memory Usage | CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 132.145MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 48 |
I/O Buf | 41 |
    IBUF | 2 |
    OBUF | 34 |
    ELVDS_IOBUF | 5 |
Register | 473 |
    DFFPE | 1 |
    DFFCE | 472 |
LUT | 466 |
    LUT2 | 27 |
    LUT3 | 56 |
    LUT4 | 383 |
INV | 1 |
    INV | 1 |
IOLOGIC | 8 |
    IDES8 | 4 |
    IODELAY | 4 |
CLOCK | 2 |
    CLKDIV | 1 |
    DHCE | 1 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 467(467 LUT, 0 ALU) / 138240 | <1% |
Register | 473 / 139140 | <1% |
  --Register as Latch | 0 / 139140 | 0% |
  --Register as FF | 473 / 139140 | <1% |
BSRAM | 0 / 340 | 0% |
Timing
Clock Summary:
NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|---|
1 | DPHY_RX_INST/U0_IB/I | Base | 10.000 | 100.0 | 0.000 | 5.000 | DPHY_RX_INST/U0_IB/I | ||
2 | DPHY_RX_INST/HS_CLK | Base | 10.000 | 100.0 | 0.000 | 5.000 | DPHY_RX_INST/U0_IB/O | ||
3 | DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT.default_gen_clk | Generated | 40.000 | 25.0 | 0.000 | 20.000 | DPHY_RX_INST/U0_IB/O | DPHY_RX_INST/HS_CLK | DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
Max Frequency Summary:
NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | DPHY_RX_INST/HS_CLK | 100.000(MHz) | 259.808(MHz) | 2 | TOP |
2 | DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT.default_gen_clk | 25.000(MHz) | 245.098(MHz) | 4 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | 3.076 |
Data Arrival Time | 2.128 |
Data Required Time | 5.203 |
From | DPHY_RX_INST/u_idesx8/opensync_1_s0 |
To | DPHY_RX_INST/u_idesx8/u_DHCEN |
Launch Clk | DPHY_RX_INST/HS_CLK[F] |
Latch Clk | DPHY_RX_INST/HS_CLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | DPHY_RX_INST/HS_CLK | |||
0.000 | 0.000 | tCL | RR | 5 | DPHY_RX_INST/U0_IB/O |
0.413 | 0.413 | tNET | RR | 1 | DPHY_RX_INST/u_idesx8/opensync_1_s0/CLK |
0.795 | 0.382 | tC2Q | RR | 2 | DPHY_RX_INST/u_idesx8/opensync_1_s0/Q |
1.207 | 0.413 | tNET | RR | 1 | DPHY_RX_INST/u_idesx8/LUT4_0/I2 |
1.715 | 0.507 | tINS | RR | 1 | DPHY_RX_INST/u_idesx8/LUT4_0/F |
2.128 | 0.413 | tNET | RR | 1 | DPHY_RX_INST/u_idesx8/u_DHCEN/CEN |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
5.000 | 0.000 | DPHY_RX_INST/HS_CLK | |||
5.000 | 0.000 | tCL | FF | 5 | DPHY_RX_INST/U0_IB/O |
5.385 | 0.385 | tNET | FF | 3 | DPHY_RX_INST/u_idesx8/u_DHCEN/CLKIN |
5.203 | -0.182 | tSu | 1 | DPHY_RX_INST/u_idesx8/u_DHCEN |
Clock Skew: | -0.028 |
Setup Relationship: | 5.000 |
Logic Level: | 2 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Arrival Data Path Delay: | cell: 0.507, 29.592%; route: 0.825, 48.105%; tC2Q: 0.382, 22.303% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 2
Path Summary:Slack | 7.974 |
Data Arrival Time | 2.128 |
Data Required Time | 10.101 |
From | DPHY_RX_INST/u_idesx8/opensync_3_s0 |
To | DPHY_RX_INST/u_idesx8/opensync_0_s0 |
Launch Clk | DPHY_RX_INST/HS_CLK[R] |
Latch Clk | DPHY_RX_INST/HS_CLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | DPHY_RX_INST/HS_CLK | |||
0.000 | 0.000 | tCL | RR | 5 | DPHY_RX_INST/U0_IB/O |
0.413 | 0.413 | tNET | RR | 1 | DPHY_RX_INST/u_idesx8/opensync_3_s0/CLK |
0.795 | 0.382 | tC2Q | RR | 2 | DPHY_RX_INST/u_idesx8/opensync_3_s0/Q |
1.207 | 0.413 | tNET | RR | 1 | DPHY_RX_INST/u_idesx8/LUT4_1/I2 |
1.715 | 0.507 | tINS | RR | 4 | DPHY_RX_INST/u_idesx8/LUT4_1/F |
2.128 | 0.413 | tNET | RR | 1 | DPHY_RX_INST/u_idesx8/opensync_0_s0/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | DPHY_RX_INST/HS_CLK | |||
10.000 | 0.000 | tCL | RR | 5 | DPHY_RX_INST/U0_IB/O |
10.413 | 0.413 | tNET | RR | 1 | DPHY_RX_INST/u_idesx8/opensync_0_s0/CLK |
10.101 | -0.311 | tSu | 1 | DPHY_RX_INST/u_idesx8/opensync_0_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 2 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Arrival Data Path Delay: | cell: 0.507, 29.592%; route: 0.825, 48.105%; tC2Q: 0.382, 22.303% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 3
Path Summary:Slack | 7.974 |
Data Arrival Time | 2.128 |
Data Required Time | 10.101 |
From | DPHY_RX_INST/u_idesx8/opensync_3_s0 |
To | DPHY_RX_INST/u_idesx8/opensync_3_s0 |
Launch Clk | DPHY_RX_INST/HS_CLK[R] |
Latch Clk | DPHY_RX_INST/HS_CLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | DPHY_RX_INST/HS_CLK | |||
0.000 | 0.000 | tCL | RR | 5 | DPHY_RX_INST/U0_IB/O |
0.413 | 0.413 | tNET | RR | 1 | DPHY_RX_INST/u_idesx8/opensync_3_s0/CLK |
0.795 | 0.382 | tC2Q | RR | 2 | DPHY_RX_INST/u_idesx8/opensync_3_s0/Q |
1.207 | 0.413 | tNET | RR | 1 | DPHY_RX_INST/u_idesx8/LUT4_1/I2 |
1.715 | 0.507 | tINS | RR | 4 | DPHY_RX_INST/u_idesx8/LUT4_1/F |
2.128 | 0.413 | tNET | RR | 1 | DPHY_RX_INST/u_idesx8/opensync_3_s0/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | DPHY_RX_INST/HS_CLK | |||
10.000 | 0.000 | tCL | RR | 5 | DPHY_RX_INST/U0_IB/O |
10.413 | 0.413 | tNET | RR | 1 | DPHY_RX_INST/u_idesx8/opensync_3_s0/CLK |
10.101 | -0.311 | tSu | 1 | DPHY_RX_INST/u_idesx8/opensync_3_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 2 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Arrival Data Path Delay: | cell: 0.507, 29.592%; route: 0.825, 48.105%; tC2Q: 0.382, 22.303% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 4
Path Summary:Slack | 7.974 |
Data Arrival Time | 2.128 |
Data Required Time | 10.101 |
From | DPHY_RX_INST/u_idesx8/opensync_3_s0 |
To | DPHY_RX_INST/u_idesx8/opensync_1_s0 |
Launch Clk | DPHY_RX_INST/HS_CLK[R] |
Latch Clk | DPHY_RX_INST/HS_CLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | DPHY_RX_INST/HS_CLK | |||
0.000 | 0.000 | tCL | RR | 5 | DPHY_RX_INST/U0_IB/O |
0.413 | 0.413 | tNET | RR | 1 | DPHY_RX_INST/u_idesx8/opensync_3_s0/CLK |
0.795 | 0.382 | tC2Q | RR | 2 | DPHY_RX_INST/u_idesx8/opensync_3_s0/Q |
1.207 | 0.413 | tNET | RR | 1 | DPHY_RX_INST/u_idesx8/LUT4_1/I2 |
1.715 | 0.507 | tINS | RR | 4 | DPHY_RX_INST/u_idesx8/LUT4_1/F |
2.128 | 0.413 | tNET | RR | 1 | DPHY_RX_INST/u_idesx8/opensync_1_s0/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | DPHY_RX_INST/HS_CLK | |||
10.000 | 0.000 | tCL | RR | 5 | DPHY_RX_INST/U0_IB/O |
10.413 | 0.413 | tNET | RR | 1 | DPHY_RX_INST/u_idesx8/opensync_1_s0/CLK |
10.101 | -0.311 | tSu | 1 | DPHY_RX_INST/u_idesx8/opensync_1_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 2 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Arrival Data Path Delay: | cell: 0.507, 29.592%; route: 0.825, 48.105%; tC2Q: 0.382, 22.303% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 5
Path Summary:Slack | 7.974 |
Data Arrival Time | 2.128 |
Data Required Time | 10.101 |
From | DPHY_RX_INST/u_idesx8/opensync_3_s0 |
To | DPHY_RX_INST/u_idesx8/opensync_2_s0 |
Launch Clk | DPHY_RX_INST/HS_CLK[R] |
Latch Clk | DPHY_RX_INST/HS_CLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | DPHY_RX_INST/HS_CLK | |||
0.000 | 0.000 | tCL | RR | 5 | DPHY_RX_INST/U0_IB/O |
0.413 | 0.413 | tNET | RR | 1 | DPHY_RX_INST/u_idesx8/opensync_3_s0/CLK |
0.795 | 0.382 | tC2Q | RR | 2 | DPHY_RX_INST/u_idesx8/opensync_3_s0/Q |
1.207 | 0.413 | tNET | RR | 1 | DPHY_RX_INST/u_idesx8/LUT4_1/I2 |
1.715 | 0.507 | tINS | RR | 4 | DPHY_RX_INST/u_idesx8/LUT4_1/F |
2.128 | 0.413 | tNET | RR | 1 | DPHY_RX_INST/u_idesx8/opensync_2_s0/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | DPHY_RX_INST/HS_CLK | |||
10.000 | 0.000 | tCL | RR | 5 | DPHY_RX_INST/U0_IB/O |
10.413 | 0.413 | tNET | RR | 1 | DPHY_RX_INST/u_idesx8/opensync_2_s0/CLK |
10.101 | -0.311 | tSu | 1 | DPHY_RX_INST/u_idesx8/opensync_2_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 2 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Arrival Data Path Delay: | cell: 0.507, 29.592%; route: 0.825, 48.105%; tC2Q: 0.382, 22.303% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |