Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Gowin\Gowin_V1.9.10.03_x64\IDE\ipcore\MIPI_RX_Advance\data\DPHY_RX.vp
C:\Gowin\Gowin_V1.9.10.03_x64\IDE\ipcore\MIPI_RX_Advance\data\DPHY_RX_TOP.v
GowinSynthesis Constraints File ---
Tool Version V1.9.10.03 (64-bit)
Part Number GW5A-LV25UG324ES
Device GW5A-25
Device Version A
Created Time Wed Oct 23 15:31:37 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module MIPI_RX_Advance_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.281s, Elapsed time = 0h 0m 0.253s, Peak memory usage = 108.316MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 108.316MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.031s, Peak memory usage = 108.316MB
    Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.018s, Peak memory usage = 108.316MB
    Optimizing Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.019s, Peak memory usage = 108.316MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.015s, Peak memory usage = 108.316MB
    Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.017s, Peak memory usage = 108.316MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 108.316MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 108.316MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.035s, Peak memory usage = 108.316MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 108.316MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 108.316MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 135.918MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.107s, Peak memory usage = 135.918MB
Generate output files:
    CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.101s, Peak memory usage = 135.918MB
Total Time and Memory Usage CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 135.918MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 80
I/O Buf 73
    IBUF 2
    OBUF 66
    ELVDS_IOBUF 5
Register 741
    DFFPE 1
    DFFCE 740
LUT 1481
    LUT2 119
    LUT3 192
    LUT4 1170
INV 1
    INV 1
IOLOGIC 8
    IDES16 4
    IODELAY 4
CLOCK 2
    CLKDIV 1
    DHCE 1

Resource Utilization Summary

Resource Usage Utilization
Logic 1482(1482 LUT, 0 ALU) / 23040 7%
Register 741 / 23685 4%
  --Register as Latch 0 / 23685 0%
  --Register as FF 741 / 23685 4%
BSRAM 0 / 56 0%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 DPHY_RX_INST/U0_IB/I Base 10.000 100.0 0.000 5.000 DPHY_RX_INST/U0_IB/I
2 DPHY_RX_INST/HS_CLK Base 10.000 100.0 0.000 5.000 DPHY_RX_INST/U0_IB/O
3 DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT.default_gen_clk Generated 80.000 12.5 0.000 40.000 DPHY_RX_INST/U0_IB/O DPHY_RX_INST/HS_CLK DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 DPHY_RX_INST/HS_CLK 100.000(MHz) 277.662(MHz) 2 TOP
2 DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT.default_gen_clk 12.500(MHz) 213.961(MHz) 5 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 3.199
Data Arrival Time 1.969
Data Required Time 5.168
From DPHY_RX_INST/u_idesx8/opensync_1_s0
To DPHY_RX_INST/u_idesx8/u_DHCEN
Launch Clk DPHY_RX_INST/HS_CLK[F]
Latch Clk DPHY_RX_INST/HS_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 DPHY_RX_INST/HS_CLK
0.000 0.000 tCL RR 5 DPHY_RX_INST/U0_IB/O
0.375 0.375 tNET RR 1 DPHY_RX_INST/u_idesx8/opensync_1_s0/CLK
0.757 0.382 tC2Q RR 2 DPHY_RX_INST/u_idesx8/opensync_1_s0/Q
1.132 0.375 tNET RR 1 DPHY_RX_INST/u_idesx8/LUT4_0/I2
1.594 0.461 tINS RR 1 DPHY_RX_INST/u_idesx8/LUT4_0/F
1.969 0.375 tNET RR 1 DPHY_RX_INST/u_idesx8/u_DHCEN/CEN
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
5.000 0.000 DPHY_RX_INST/HS_CLK
5.000 0.000 tCL FF 5 DPHY_RX_INST/U0_IB/O
5.350 0.350 tNET FF 3 DPHY_RX_INST/u_idesx8/u_DHCEN/CLKIN
5.168 -0.182 tSu 1 DPHY_RX_INST/u_idesx8/u_DHCEN
Path Statistics:
Clock Skew: -0.025
Setup Relationship: 5.000
Logic Level: 2
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 0.461, 28.941%; route: 0.750, 47.059%; tC2Q: 0.382, 24.000%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 2

Path Summary:
Slack 8.095
Data Arrival Time 1.969
Data Required Time 10.064
From DPHY_RX_INST/u_idesx8/opensync_3_s0
To DPHY_RX_INST/u_idesx8/opensync_0_s0
Launch Clk DPHY_RX_INST/HS_CLK[R]
Latch Clk DPHY_RX_INST/HS_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 DPHY_RX_INST/HS_CLK
0.000 0.000 tCL RR 5 DPHY_RX_INST/U0_IB/O
0.375 0.375 tNET RR 1 DPHY_RX_INST/u_idesx8/opensync_3_s0/CLK
0.757 0.382 tC2Q RR 2 DPHY_RX_INST/u_idesx8/opensync_3_s0/Q
1.132 0.375 tNET RR 1 DPHY_RX_INST/u_idesx8/LUT4_1/I2
1.594 0.461 tINS RR 4 DPHY_RX_INST/u_idesx8/LUT4_1/F
1.969 0.375 tNET RR 1 DPHY_RX_INST/u_idesx8/opensync_0_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 DPHY_RX_INST/HS_CLK
10.000 0.000 tCL RR 5 DPHY_RX_INST/U0_IB/O
10.375 0.375 tNET RR 1 DPHY_RX_INST/u_idesx8/opensync_0_s0/CLK
10.064 -0.311 tSu 1 DPHY_RX_INST/u_idesx8/opensync_0_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 2
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 0.461, 28.941%; route: 0.750, 47.059%; tC2Q: 0.382, 24.000%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 3

Path Summary:
Slack 8.095
Data Arrival Time 1.969
Data Required Time 10.064
From DPHY_RX_INST/u_idesx8/opensync_3_s0
To DPHY_RX_INST/u_idesx8/opensync_3_s0
Launch Clk DPHY_RX_INST/HS_CLK[R]
Latch Clk DPHY_RX_INST/HS_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 DPHY_RX_INST/HS_CLK
0.000 0.000 tCL RR 5 DPHY_RX_INST/U0_IB/O
0.375 0.375 tNET RR 1 DPHY_RX_INST/u_idesx8/opensync_3_s0/CLK
0.757 0.382 tC2Q RR 2 DPHY_RX_INST/u_idesx8/opensync_3_s0/Q
1.132 0.375 tNET RR 1 DPHY_RX_INST/u_idesx8/LUT4_1/I2
1.594 0.461 tINS RR 4 DPHY_RX_INST/u_idesx8/LUT4_1/F
1.969 0.375 tNET RR 1 DPHY_RX_INST/u_idesx8/opensync_3_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 DPHY_RX_INST/HS_CLK
10.000 0.000 tCL RR 5 DPHY_RX_INST/U0_IB/O
10.375 0.375 tNET RR 1 DPHY_RX_INST/u_idesx8/opensync_3_s0/CLK
10.064 -0.311 tSu 1 DPHY_RX_INST/u_idesx8/opensync_3_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 2
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 0.461, 28.941%; route: 0.750, 47.059%; tC2Q: 0.382, 24.000%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 4

Path Summary:
Slack 8.095
Data Arrival Time 1.969
Data Required Time 10.064
From DPHY_RX_INST/u_idesx8/opensync_3_s0
To DPHY_RX_INST/u_idesx8/opensync_1_s0
Launch Clk DPHY_RX_INST/HS_CLK[R]
Latch Clk DPHY_RX_INST/HS_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 DPHY_RX_INST/HS_CLK
0.000 0.000 tCL RR 5 DPHY_RX_INST/U0_IB/O
0.375 0.375 tNET RR 1 DPHY_RX_INST/u_idesx8/opensync_3_s0/CLK
0.757 0.382 tC2Q RR 2 DPHY_RX_INST/u_idesx8/opensync_3_s0/Q
1.132 0.375 tNET RR 1 DPHY_RX_INST/u_idesx8/LUT4_1/I2
1.594 0.461 tINS RR 4 DPHY_RX_INST/u_idesx8/LUT4_1/F
1.969 0.375 tNET RR 1 DPHY_RX_INST/u_idesx8/opensync_1_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 DPHY_RX_INST/HS_CLK
10.000 0.000 tCL RR 5 DPHY_RX_INST/U0_IB/O
10.375 0.375 tNET RR 1 DPHY_RX_INST/u_idesx8/opensync_1_s0/CLK
10.064 -0.311 tSu 1 DPHY_RX_INST/u_idesx8/opensync_1_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 2
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 0.461, 28.941%; route: 0.750, 47.059%; tC2Q: 0.382, 24.000%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 5

Path Summary:
Slack 8.095
Data Arrival Time 1.969
Data Required Time 10.064
From DPHY_RX_INST/u_idesx8/opensync_3_s0
To DPHY_RX_INST/u_idesx8/opensync_2_s0
Launch Clk DPHY_RX_INST/HS_CLK[R]
Latch Clk DPHY_RX_INST/HS_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 DPHY_RX_INST/HS_CLK
0.000 0.000 tCL RR 5 DPHY_RX_INST/U0_IB/O
0.375 0.375 tNET RR 1 DPHY_RX_INST/u_idesx8/opensync_3_s0/CLK
0.757 0.382 tC2Q RR 2 DPHY_RX_INST/u_idesx8/opensync_3_s0/Q
1.132 0.375 tNET RR 1 DPHY_RX_INST/u_idesx8/LUT4_1/I2
1.594 0.461 tINS RR 4 DPHY_RX_INST/u_idesx8/LUT4_1/F
1.969 0.375 tNET RR 1 DPHY_RX_INST/u_idesx8/opensync_2_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 DPHY_RX_INST/HS_CLK
10.000 0.000 tCL RR 5 DPHY_RX_INST/U0_IB/O
10.375 0.375 tNET RR 1 DPHY_RX_INST/u_idesx8/opensync_2_s0/CLK
10.064 -0.311 tSu 1 DPHY_RX_INST/u_idesx8/opensync_2_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 2
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 0.461, 28.941%; route: 0.750, 47.059%; tC2Q: 0.382, 24.000%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%