Timing Messages
Report Title | Timing Analysis Report |
Design File | E:\myWork\IP\releaseVerify\version\1.9.10.03\Gowin_MIPI_DPHY_Advance_RefDesign\MIPI_RefDesign_5a25_MIPI_IO\MIPI_RefDesign\impl\gwsynthesis\MIPI_RefDesign.vg |
Physical Constraints File | E:\myWork\IP\releaseVerify\version\1.9.10.03\Gowin_MIPI_DPHY_Advance_RefDesign\MIPI_RefDesign_5a25_MIPI_IO\MIPI_RefDesign\src\mipi.cst |
Timing Constraint File | E:\myWork\IP\releaseVerify\version\1.9.10.03\Gowin_MIPI_DPHY_Advance_RefDesign\MIPI_RefDesign_5a25_MIPI_IO\MIPI_RefDesign\src\mipi.sdc |
Tool Version | V1.9.10.03 (64-bit) |
Part Number | GW5A-LV25UG324ES |
Device | GW5A-25 |
Device Version | A |
Created Time | Thu Oct 24 15:37:59 2024 |
Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved. |
Timing Summaries
STA Tool Run Summary:
Setup Delay Model | Slow 0.855V 0C ES |
Hold Delay Model | Fast 0.945V 85C ES |
Numbers of Paths Analyzed | 3291 |
Numbers of Endpoints Analyzed | 4759 |
Numbers of Falling Endpoints | 13 |
Numbers of Setup Violated Endpoints | 0 |
Numbers of Hold Violated Endpoints | 0 |
Clock Summary:
NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Objects |
---|---|---|---|---|---|---|---|---|---|
1 | MIPI_CLK_RX_P | Base | 10.000 | 100.000 | 0.000 | 5.000 | MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/IO | ||
2 | HS_CLK | Base | 10.000 | 100.000 | 0.000 | 5.000 | MIPI_RX_Advance_Top/DPHY_RX_INST/HS_CLK | ||
3 | MIPI_CLK_RX_N | Base | 10.000 | 100.000 | 0.000 | 5.000 | MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/IOB | ||
4 | sys_clk | Base | 20.000 | 50.000 | 0.000 | 10.000 | clkx2x4 | ||
5 | tck_pad_i | Base | 50.000 | 20.000 | 0.000 | 25.000 | tck_pad_i | ||
6 | U3_CLKDIV | Base | 800.000 | 1.250 | 0.000 | 400.000 | U3_CLKDIV/CLKOUT | ||
7 | Inst3_CLKDIV_OUT | Base | 80.000 | 12.500 | 0.000 | 40.000 | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT | ||
8 | PLLA_mipi_tx/CLKOUT0.default_gen_clk | Generated | 100.000 | 10.000 | 0.000 | 50.000 | clkx2x4_ibuf/I | sys_clk | PLLA_mipi_tx/CLKOUT0 |
9 | PLLA_mipi_tx/CLKOUT1.default_gen_clk | Generated | 100.000 | 10.000 | 0.000 | 50.000 | clkx2x4_ibuf/I | sys_clk | PLLA_mipi_tx/CLKOUT1 |
Max Frequency Summary:
NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | HS_CLK | 100.000(MHz) | 392.156(MHz) | 2 | TOP |
2 | tck_pad_i | 20.000(MHz) | 73.553(MHz) | 6 | TOP |
3 | U3_CLKDIV | 1.250(MHz) | 159.315(MHz) | 2 | TOP |
4 | Inst3_CLKDIV_OUT | 12.500(MHz) | 120.066(MHz) | 6 | TOP |
No timing paths to get frequency of MIPI_CLK_RX_P!
No timing paths to get frequency of MIPI_CLK_RX_N!
No timing paths to get frequency of sys_clk!
No timing paths to get frequency of PLLA_mipi_tx/CLKOUT0.default_gen_clk!
No timing paths to get frequency of PLLA_mipi_tx/CLKOUT1.default_gen_clk!
Total Negative Slack Summary:
Clock Name | Analysis Type | Endpoints TNS | Number of Endpoints |
---|---|---|---|
MIPI_CLK_RX_P | Setup | 0.000 | 0 |
MIPI_CLK_RX_P | Hold | 0.000 | 0 |
HS_CLK | Setup | 0.000 | 0 |
HS_CLK | Hold | 0.000 | 0 |
MIPI_CLK_RX_N | Setup | 0.000 | 0 |
MIPI_CLK_RX_N | Hold | 0.000 | 0 |
sys_clk | Setup | 0.000 | 0 |
sys_clk | Hold | 0.000 | 0 |
tck_pad_i | Setup | 0.000 | 0 |
tck_pad_i | Hold | 0.000 | 0 |
U3_CLKDIV | Setup | 0.000 | 0 |
U3_CLKDIV | Hold | 0.000 | 0 |
Inst3_CLKDIV_OUT | Setup | 0.000 | 0 |
Inst3_CLKDIV_OUT | Hold | 0.000 | 0 |
PLLA_mipi_tx/CLKOUT0.default_gen_clk | Setup | 0.000 | 0 |
PLLA_mipi_tx/CLKOUT0.default_gen_clk | Hold | 0.000 | 0 |
PLLA_mipi_tx/CLKOUT1.default_gen_clk | Setup | 0.000 | 0 |
PLLA_mipi_tx/CLKOUT1.default_gen_clk | Hold | 0.000 | 0 |
Timing Details
Path Slacks Table:
Setup Paths Table
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 0.730 | gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_0_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CE | tck_pad_i:[R] | Inst3_CLKDIV_OUT:[R] | 10.000 | 2.409 | 6.515 |
2 | 1.474 | gw_gao_inst_0/u_la0_top/internal_reg_start_s1/Q | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/D | tck_pad_i:[F] | Inst3_CLKDIV_OUT:[R] | 5.000 | 2.381 | 1.046 |
3 | 1.507 | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_s1/Q | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/D | tck_pad_i:[F] | Inst3_CLKDIV_OUT:[R] | 5.000 | 2.398 | 0.769 |
4 | 1.552 | gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_0_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CE | tck_pad_i:[R] | Inst3_CLKDIV_OUT:[R] | 10.000 | 2.408 | 5.694 |
5 | 1.985 | gw_gao_inst_0/u_la0_top/capture_windows_num_8_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_7_s0/D | tck_pad_i:[R] | Inst3_CLKDIV_OUT:[R] | 10.000 | 2.398 | 5.519 |
6 | 2.189 | gw_gao_inst_0/u_la0_top/capture_windows_num_8_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_12_s0/D | tck_pad_i:[R] | Inst3_CLKDIV_OUT:[R] | 10.000 | 2.378 | 5.335 |
7 | 2.328 | gw_gao_inst_0/u_la0_top/capture_windows_num_8_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_6_s0/D | tck_pad_i:[R] | Inst3_CLKDIV_OUT:[R] | 10.000 | 2.394 | 5.179 |
8 | 2.391 | gw_gao_inst_0/u_la0_top/capture_windows_num_8_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_10_s0/D | tck_pad_i:[R] | Inst3_CLKDIV_OUT:[R] | 10.000 | 2.387 | 5.124 |
9 | 2.434 | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_11_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/D | tck_pad_i:[R] | Inst3_CLKDIV_OUT:[R] | 10.000 | 2.378 | 5.090 |
10 | 2.457 | gw_gao_inst_0/u_la0_top/capture_windows_num_5_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_8_s0/D | tck_pad_i:[R] | Inst3_CLKDIV_OUT:[R] | 10.000 | 2.355 | 5.090 |
11 | 2.479 | gw_gao_inst_0/u_la0_top/capture_windows_num_1_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_11_s0/D | tck_pad_i:[R] | Inst3_CLKDIV_OUT:[R] | 10.000 | 2.403 | 5.019 |
12 | 2.583 | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_11_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/D | tck_pad_i:[R] | Inst3_CLKDIV_OUT:[R] | 10.000 | 2.406 | 4.913 |
13 | 2.610 | gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_0_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/D | tck_pad_i:[R] | Inst3_CLKDIV_OUT:[R] | 10.000 | 2.408 | 4.884 |
14 | 2.658 | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_11_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CE | tck_pad_i:[R] | Inst3_CLKDIV_OUT:[R] | 10.000 | 2.401 | 4.595 |
15 | 2.783 | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_11_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/D | tck_pad_i:[R] | Inst3_CLKDIV_OUT:[R] | 10.000 | 2.406 | 4.713 |
16 | 2.783 | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_11_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/D | tck_pad_i:[R] | Inst3_CLKDIV_OUT:[R] | 10.000 | 2.406 | 4.713 |
17 | 2.916 | gw_gao_inst_0/u_la0_top/capture_windows_num_8_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_9_s0/D | tck_pad_i:[R] | Inst3_CLKDIV_OUT:[R] | 10.000 | 2.373 | 4.613 |
18 | 2.917 | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_11_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/D | tck_pad_i:[R] | Inst3_CLKDIV_OUT:[R] | 10.000 | 2.397 | 4.588 |
19 | 2.921 | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_11_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/D | tck_pad_i:[R] | Inst3_CLKDIV_OUT:[R] | 10.000 | 2.402 | 4.578 |
20 | 2.927 | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_11_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/D | tck_pad_i:[R] | Inst3_CLKDIV_OUT:[R] | 10.000 | 2.397 | 4.578 |
21 | 2.927 | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_11_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/D | tck_pad_i:[R] | Inst3_CLKDIV_OUT:[R] | 10.000 | 2.397 | 4.578 |
22 | 2.981 | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_11_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_11_s1/D | tck_pad_i:[R] | Inst3_CLKDIV_OUT:[R] | 10.000 | 2.402 | 4.518 |
23 | 2.981 | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_11_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_12_s1/D | tck_pad_i:[R] | Inst3_CLKDIV_OUT:[R] | 10.000 | 2.402 | 4.518 |
24 | 2.997 | gw_gao_inst_0/u_la0_top/capture_windows_num_7_s0/Q | gw_gao_inst_0/u_la0_top/start_reg_s0/D | tck_pad_i:[R] | Inst3_CLKDIV_OUT:[R] | 10.000 | 2.437 | 4.467 |
25 | 3.103 | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_11_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/D | tck_pad_i:[R] | Inst3_CLKDIV_OUT:[R] | 10.000 | 2.418 | 4.380 |
Hold Paths Table
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 0.148 | dout1_14_s0/Q | u_MIPI_TX_Advance_Top/DPHY_TX_INST/u_oserx4x8/U5_OSER16_0/D6 | U3_CLKDIV:[R] | U3_CLKDIV:[R] | 0.000 | 0.002 | 0.241 |
2 | 0.154 | dout1_15_s0/Q | u_MIPI_TX_Advance_Top/DPHY_TX_INST/u_oserx4x8/U5_OSER16_0/D15 | U3_CLKDIV:[R] | U3_CLKDIV:[R] | 0.000 | -0.002 | 0.239 |
3 | 0.164 | dout1_7_s0/Q | u_MIPI_TX_Advance_Top/DPHY_TX_INST/u_oserx4x8/U5_OSER16_0/D7 | U3_CLKDIV:[R] | U3_CLKDIV:[R] | 0.000 | 0.002 | 0.245 |
4 | 0.222 | gw_gao_inst_0/u_la0_top/address_counter_10_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_17_s/ADB[11] | tck_pad_i:[R] | tck_pad_i:[R] | 0.000 | 0.009 | 0.248 |
5 | 0.223 | gw_gao_inst_0/u_la0_top/address_counter_5_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_17_s/ADB[6] | tck_pad_i:[R] | tck_pad_i:[R] | 0.000 | 0.009 | 0.249 |
6 | 0.229 | dout1_12_s0/Q | u_MIPI_TX_Advance_Top/DPHY_TX_INST/u_oserx4x8/U5_OSER16_0/D4 | U3_CLKDIV:[R] | U3_CLKDIV:[R] | 0.000 | 0.002 | 0.322 |
7 | 0.234 | gw_gao_inst_0/u_la0_top/address_counter_7_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_17_s/ADB[8] | tck_pad_i:[R] | tck_pad_i:[R] | 0.000 | 0.013 | 0.255 |
8 | 0.239 | dout1_3_s0/Q | u_MIPI_TX_Advance_Top/DPHY_TX_INST/u_oserx4x8/U5_OSER16_0/D3 | U3_CLKDIV:[R] | U3_CLKDIV:[R] | 0.000 | 0.002 | 0.320 |
9 | 0.240 | dout1_2_s0/Q | u_MIPI_TX_Advance_Top/DPHY_TX_INST/u_oserx4x8/U5_OSER16_0/D0 | U3_CLKDIV:[R] | U3_CLKDIV:[R] | 0.000 | -0.002 | 0.337 |
10 | 0.244 | dout1_14_s0/Q | u_MIPI_TX_Advance_Top/DPHY_TX_INST/u_oserx4x8/U5_OSER16_0/D14 | U3_CLKDIV:[R] | U3_CLKDIV:[R] | 0.000 | 0.002 | 0.337 |
11 | 0.250 | dout1_1_s0/Q | u_MIPI_TX_Advance_Top/DPHY_TX_INST/u_oserx4x8/U5_OSER16_0/D1 | U3_CLKDIV:[R] | U3_CLKDIV:[R] | 0.000 | -0.002 | 0.335 |
12 | 0.254 | dout1_12_s0/Q | u_MIPI_TX_Advance_Top/DPHY_TX_INST/u_oserx4x8/U5_OSER16_0/D12 | U3_CLKDIV:[R] | U3_CLKDIV:[R] | 0.000 | 0.002 | 0.347 |
13 | 0.254 | dout1_12_s0/Q | u_MIPI_TX_Advance_Top/DPHY_TX_INST/u_oserx4x8/U5_OSER16_0/D10 | U3_CLKDIV:[R] | U3_CLKDIV:[R] | 0.000 | 0.002 | 0.347 |
14 | 0.254 | dout1_9_s0/Q | u_MIPI_TX_Advance_Top/DPHY_TX_INST/u_oserx4x8/U5_OSER16_0/D9 | U3_CLKDIV:[R] | U3_CLKDIV:[R] | 0.000 | 0.002 | 0.335 |
15 | 0.258 | dout1_13_s0/Q | u_MIPI_TX_Advance_Top/DPHY_TX_INST/u_oserx4x8/U5_OSER16_0/D13 | U3_CLKDIV:[R] | U3_CLKDIV:[R] | 0.000 | 0.002 | 0.339 |
16 | 0.275 | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_14_s3/Q | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_14_s3/D | tck_pad_i:[R] | tck_pad_i:[R] | 0.000 | 0.000 | 0.300 |
17 | 0.275 | gw_gao_inst_0/u_la0_top/word_count_11_s0/Q | gw_gao_inst_0/u_la0_top/word_count_11_s0/D | tck_pad_i:[R] | tck_pad_i:[R] | 0.000 | 0.000 | 0.300 |
18 | 0.275 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/D | Inst3_CLKDIV_OUT:[R] | Inst3_CLKDIV_OUT:[R] | 0.000 | 0.000 | 0.300 |
19 | 0.275 | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/lane1_cnt_2_s0/Q | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/lane1_cnt_2_s0/D | Inst3_CLKDIV_OUT:[R] | Inst3_CLKDIV_OUT:[R] | 0.000 | 0.000 | 0.300 |
20 | 0.275 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/D | Inst3_CLKDIV_OUT:[R] | Inst3_CLKDIV_OUT:[R] | 0.000 | 0.000 | 0.300 |
21 | 0.275 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_12_s1/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_12_s1/D | Inst3_CLKDIV_OUT:[R] | Inst3_CLKDIV_OUT:[R] | 0.000 | 0.000 | 0.300 |
22 | 0.275 | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_31_s3/Q | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_31_s3/D | tck_pad_i:[R] | tck_pad_i:[R] | 0.000 | 0.000 | 0.300 |
23 | 0.275 | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_1_s3/Q | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_1_s3/D | tck_pad_i:[R] | tck_pad_i:[R] | 0.000 | 0.000 | 0.300 |
24 | 0.275 | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_4_s3/Q | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_4_s3/D | tck_pad_i:[R] | tck_pad_i:[R] | 0.000 | 0.000 | 0.300 |
25 | 0.275 | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_6_s3/Q | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_6_s3/D | tck_pad_i:[R] | tck_pad_i:[R] | 0.000 | 0.000 | 0.300 |
Recovery Paths Table
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 6.062 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_end_tck_1_s0/CLEAR | Inst3_CLKDIV_OUT:[F] | tck_pad_i:[F] | 5.000 | -2.392 | 1.003 |
2 | 6.072 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0/CLEAR | Inst3_CLKDIV_OUT:[F] | tck_pad_i:[F] | 5.000 | -2.402 | 1.003 |
3 | 6.072 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_end_tck_2_s0/CLEAR | Inst3_CLKDIV_OUT:[F] | tck_pad_i:[F] | 5.000 | -2.402 | 1.003 |
4 | 36.361 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR | Inst3_CLKDIV_OUT:[F] | Inst3_CLKDIV_OUT:[R] | 40.000 | 0.018 | 3.274 |
5 | 36.412 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR | Inst3_CLKDIV_OUT:[F] | Inst3_CLKDIV_OUT:[R] | 40.000 | -0.020 | 3.261 |
6 | 36.412 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR | Inst3_CLKDIV_OUT:[F] | Inst3_CLKDIV_OUT:[R] | 40.000 | -0.020 | 3.261 |
7 | 36.599 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/CLEAR | Inst3_CLKDIV_OUT:[F] | Inst3_CLKDIV_OUT:[R] | 40.000 | -0.015 | 3.069 |
8 | 37.015 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR | Inst3_CLKDIV_OUT:[F] | Inst3_CLKDIV_OUT:[R] | 40.000 | 0.008 | 2.629 |
9 | 37.426 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR | Inst3_CLKDIV_OUT:[F] | Inst3_CLKDIV_OUT:[R] | 40.000 | 0.025 | 2.201 |
10 | 37.426 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR | Inst3_CLKDIV_OUT:[F] | Inst3_CLKDIV_OUT:[R] | 40.000 | 0.025 | 2.201 |
11 | 37.602 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLEAR | Inst3_CLKDIV_OUT:[F] | Inst3_CLKDIV_OUT:[R] | 40.000 | 0.013 | 2.037 |
12 | 37.602 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR | Inst3_CLKDIV_OUT:[F] | Inst3_CLKDIV_OUT:[R] | 40.000 | 0.013 | 2.037 |
13 | 37.631 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR | Inst3_CLKDIV_OUT:[F] | Inst3_CLKDIV_OUT:[R] | 40.000 | 0.013 | 2.009 |
14 | 37.631 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR | Inst3_CLKDIV_OUT:[F] | Inst3_CLKDIV_OUT:[R] | 40.000 | 0.013 | 2.009 |
15 | 37.631 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR | Inst3_CLKDIV_OUT:[F] | Inst3_CLKDIV_OUT:[R] | 40.000 | 0.013 | 2.009 |
16 | 37.640 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR | Inst3_CLKDIV_OUT:[F] | Inst3_CLKDIV_OUT:[R] | 40.000 | 0.004 | 2.009 |
17 | 37.640 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR | Inst3_CLKDIV_OUT:[F] | Inst3_CLKDIV_OUT:[R] | 40.000 | 0.004 | 2.009 |
18 | 37.640 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/CLEAR | Inst3_CLKDIV_OUT:[F] | Inst3_CLKDIV_OUT:[R] | 40.000 | 0.004 | 2.009 |
19 | 37.640 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET | Inst3_CLKDIV_OUT:[F] | Inst3_CLKDIV_OUT:[R] | 40.000 | 0.004 | 2.009 |
20 | 37.650 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR | Inst3_CLKDIV_OUT:[F] | Inst3_CLKDIV_OUT:[R] | 40.000 | 0.019 | 1.984 |
21 | 37.659 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR | Inst3_CLKDIV_OUT:[F] | Inst3_CLKDIV_OUT:[R] | 40.000 | 0.010 | 1.984 |
22 | 37.659 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR | Inst3_CLKDIV_OUT:[F] | Inst3_CLKDIV_OUT:[R] | 40.000 | 0.010 | 1.984 |
23 | 37.659 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_11_s1/CLEAR | Inst3_CLKDIV_OUT:[F] | Inst3_CLKDIV_OUT:[R] | 40.000 | 0.010 | 1.984 |
24 | 37.659 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_12_s1/CLEAR | Inst3_CLKDIV_OUT:[F] | Inst3_CLKDIV_OUT:[R] | 40.000 | 0.010 | 1.984 |
25 | 37.787 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR | Inst3_CLKDIV_OUT:[F] | Inst3_CLKDIV_OUT:[R] | 40.000 | -0.020 | 1.886 |
Removal Paths Table
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 1.798 | hactive_flag_s2/Q | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_3_s0/CLEAR | U3_CLKDIV:[R] | Inst3_CLKDIV_OUT:[R] | 0.000 | 0.000 | 1.780 |
2 | 1.798 | hactive_flag_s2/Q | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_2_s0/CLEAR | U3_CLKDIV:[R] | Inst3_CLKDIV_OUT:[R] | 0.000 | 0.000 | 1.780 |
3 | 1.798 | hactive_flag_s2/Q | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_0_s0/CLEAR | U3_CLKDIV:[R] | Inst3_CLKDIV_OUT:[R] | 0.000 | 0.000 | 1.780 |
4 | 1.802 | hactive_flag_s2/Q | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/q_in2_1_8_s0/CLEAR | U3_CLKDIV:[R] | Inst3_CLKDIV_OUT:[R] | 0.000 | 0.004 | 1.780 |
5 | 1.802 | hactive_flag_s2/Q | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/q_in2_0_1_s0/CLEAR | U3_CLKDIV:[R] | Inst3_CLKDIV_OUT:[R] | 0.000 | -0.015 | 1.799 |
6 | 1.802 | hactive_flag_s2/Q | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/q_in2_0_11_s0/CLEAR | U3_CLKDIV:[R] | Inst3_CLKDIV_OUT:[R] | 0.000 | 0.004 | 1.780 |
7 | 1.802 | hactive_flag_s2/Q | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/q_in1_0_1_s0/CLEAR | U3_CLKDIV:[R] | Inst3_CLKDIV_OUT:[R] | 0.000 | 0.004 | 1.780 |
8 | 1.802 | hactive_flag_s2/Q | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/dout_13_s0/CLEAR | U3_CLKDIV:[R] | Inst3_CLKDIV_OUT:[R] | 0.000 | 0.004 | 1.780 |
9 | 1.802 | hactive_flag_s2/Q | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/dout_14_s0/CLEAR | U3_CLKDIV:[R] | Inst3_CLKDIV_OUT:[R] | 0.000 | -0.015 | 1.799 |
10 | 1.802 | hactive_flag_s2/Q | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_5_s0/CLEAR | U3_CLKDIV:[R] | Inst3_CLKDIV_OUT:[R] | 0.000 | 0.004 | 1.780 |
11 | 1.802 | hactive_flag_s2/Q | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_4_s0/CLEAR | U3_CLKDIV:[R] | Inst3_CLKDIV_OUT:[R] | 0.000 | 0.004 | 1.780 |
12 | 1.802 | hactive_flag_s2/Q | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_1_s0/CLEAR | U3_CLKDIV:[R] | Inst3_CLKDIV_OUT:[R] | 0.000 | 0.004 | 1.780 |
13 | 1.802 | hactive_flag_s2/Q | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/reg4_0_s0/CLEAR | U3_CLKDIV:[R] | Inst3_CLKDIV_OUT:[R] | 0.000 | -0.015 | 1.799 |
14 | 1.802 | hactive_flag_s2/Q | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/reg3_1_s0/CLEAR | U3_CLKDIV:[R] | Inst3_CLKDIV_OUT:[R] | 0.000 | 0.004 | 1.780 |
15 | 1.802 | hactive_flag_s2/Q | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/reg3_4_s0/CLEAR | U3_CLKDIV:[R] | Inst3_CLKDIV_OUT:[R] | 0.000 | 0.004 | 1.780 |
16 | 1.802 | hactive_flag_s2/Q | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/reg2_0_s0/CLEAR | U3_CLKDIV:[R] | Inst3_CLKDIV_OUT:[R] | 0.000 | -0.015 | 1.799 |
17 | 1.802 | hactive_flag_s2/Q | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/reg1_4_s0/CLEAR | U3_CLKDIV:[R] | Inst3_CLKDIV_OUT:[R] | 0.000 | -0.015 | 1.799 |
18 | 1.802 | hactive_flag_s2/Q | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/reg0_3_s0/CLEAR | U3_CLKDIV:[R] | Inst3_CLKDIV_OUT:[R] | 0.000 | -0.015 | 1.799 |
19 | 1.802 | hactive_flag_s2/Q | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/dout_3_s0/CLEAR | U3_CLKDIV:[R] | Inst3_CLKDIV_OUT:[R] | 0.000 | 0.004 | 1.780 |
20 | 1.802 | hactive_flag_s2/Q | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/dout_14_s0/CLEAR | U3_CLKDIV:[R] | Inst3_CLKDIV_OUT:[R] | 0.000 | 0.004 | 1.780 |
21 | 1.802 | hactive_flag_s2/Q | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_15_s0/CLEAR | U3_CLKDIV:[R] | Inst3_CLKDIV_OUT:[R] | 0.000 | -0.015 | 1.799 |
22 | 1.802 | hactive_flag_s2/Q | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_13_s0/CLEAR | U3_CLKDIV:[R] | Inst3_CLKDIV_OUT:[R] | 0.000 | -0.015 | 1.799 |
23 | 1.802 | hactive_flag_s2/Q | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_11_s0/CLEAR | U3_CLKDIV:[R] | Inst3_CLKDIV_OUT:[R] | 0.000 | -0.015 | 1.799 |
24 | 1.802 | hactive_flag_s2/Q | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_7_s0/CLEAR | U3_CLKDIV:[R] | Inst3_CLKDIV_OUT:[R] | 0.000 | 0.004 | 1.780 |
25 | 1.802 | hactive_flag_s2/Q | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/q_in2_1_12_s0/CLEAR | U3_CLKDIV:[R] | Inst3_CLKDIV_OUT:[R] | 0.000 | -0.010 | 1.794 |
Minimum Pulse Width Table:
Number | Slack | Actual Width | Required Width | Type | Clock | Objects |
---|---|---|---|---|---|---|
1 | 3.503 | 3.753 | 0.250 | Low Pulse Width | HS_CLK | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_2_s0 |
2 | 3.503 | 3.753 | 0.250 | Low Pulse Width | HS_CLK | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0 |
3 | 3.503 | 3.753 | 0.250 | Low Pulse Width | HS_CLK | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0 |
4 | 3.503 | 3.753 | 0.250 | Low Pulse Width | HS_CLK | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0 |
5 | 3.503 | 3.753 | 0.250 | High Pulse Width | HS_CLK | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_2_s0 |
6 | 3.503 | 3.753 | 0.250 | High Pulse Width | HS_CLK | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0 |
7 | 3.503 | 3.753 | 0.250 | High Pulse Width | HS_CLK | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0 |
8 | 3.503 | 3.753 | 0.250 | High Pulse Width | HS_CLK | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0 |
9 | 22.193 | 23.193 | 1.000 | Low Pulse Width | tck_pad_i | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_14_s |
10 | 22.193 | 23.193 | 1.000 | Low Pulse Width | tck_pad_i | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_15_s |
Timing Report By Analysis Type:
Setup Analysis Report
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 0.730 |
Data Arrival Time | 160.835 |
Data Required Time | 161.565 |
From | gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_0_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | Inst3_CLKDIV_OUT:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
150.000 | 150.000 | active clock edge time | ||||
150.000 | 0.000 | tck_pad_i | ||||
150.000 | 0.000 | tCL | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
150.682 | 0.683 | tINS | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
150.682 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
151.365 | 0.683 | tINS | RR | 292 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
154.320 | 2.955 | tNET | RR | 1 | R30C47[1][A] | gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_0_s0/CLK |
154.703 | 0.382 | tC2Q | RR | 3 | R30C47[1][A] | gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_0_s0/Q |
156.527 | 1.824 | tNET | RR | 1 | R26C43[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s6/I0 |
157.043 | 0.516 | tINS | RR | 1 | R26C43[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s6/F |
157.425 | 0.382 | tNET | RR | 1 | R26C40[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s5/I0 |
157.942 | 0.516 | tINS | RR | 3 | R26C40[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s5/F |
158.678 | 0.736 | tNET | RR | 1 | R29C40[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s4/I3 |
159.204 | 0.526 | tINS | RR | 1 | R29C40[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s4/F |
159.587 | 0.382 | tNET | RR | 1 | R31C41[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s3/I2 |
160.108 | 0.521 | tINS | RR | 1 | R31C41[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s3/F |
160.835 | 0.728 | tNET | RR | 1 | R31C41[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
160.000 | 160.000 | active clock edge time | ||||
160.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
160.000 | 0.000 | tCL | RR | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
161.911 | 1.911 | tNET | RR | 1 | R31C41[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK |
161.876 | -0.035 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1 | |||
161.565 | -0.311 | tSu | 1 | R31C41[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1 |
Path Statistics:
Clock Skew | -2.409 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 1.365, 31.595%; route: 2.955, 68.405% |
Arrival Data Path Delay | cell: 2.080, 31.926%; route: 4.053, 62.203%; tC2Q: 0.382, 5.871% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.911, 100.000% |
Path2
Path Summary:
Slack | 1.474 |
Data Arrival Time | 80.380 |
Data Required Time | 81.854 |
From | gw_gao_inst_0/u_la0_top/internal_reg_start_s1 |
To | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0 |
Launch Clk | tck_pad_i:[F] |
Latch Clk | Inst3_CLKDIV_OUT:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
75.000 | 75.000 | active clock edge time | ||||
75.000 | 0.000 | tck_pad_i | ||||
75.000 | 0.000 | tCL | FF | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
75.688 | 0.688 | tINS | FF | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
75.688 | 0.000 | tNET | FF | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
76.375 | 0.688 | tINS | FF | 292 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
79.334 | 2.959 | tNET | FF | 1 | R26C48[0][B] | gw_gao_inst_0/u_la0_top/internal_reg_start_s1/CLK |
79.768 | 0.434 | tC2Q | FR | 2 | R26C48[0][B] | gw_gao_inst_0/u_la0_top/internal_reg_start_s1/Q |
80.380 | 0.612 | tNET | RR | 1 | R24C47[0][A] | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
80.000 | 80.000 | active clock edge time | ||||
80.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
80.000 | 0.000 | tCL | RR | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
81.953 | 1.953 | tNET | RR | 1 | R24C47[0][A] | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLK |
81.918 | -0.035 | tUnc | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0 | |||
81.854 | -0.064 | tSu | 1 | R24C47[0][A] | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0 |
Path Statistics:
Clock Skew | -2.381 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 1.375, 31.725%; route: 2.959, 68.275% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.612, 58.542%; tC2Q: 0.434, 41.458% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.953, 100.000% |
Path3
Path Summary:
Slack | 1.507 |
Data Arrival Time | 80.103 |
Data Required Time | 81.610 |
From | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_s1 |
To | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0 |
Launch Clk | tck_pad_i:[F] |
Latch Clk | Inst3_CLKDIV_OUT:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
75.000 | 75.000 | active clock edge time | ||||
75.000 | 0.000 | tck_pad_i | ||||
75.000 | 0.000 | tCL | FF | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
75.688 | 0.688 | tINS | FF | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
75.688 | 0.000 | tNET | FF | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
76.375 | 0.688 | tINS | FF | 292 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
79.334 | 2.959 | tNET | FF | 1 | R26C48[0][A] | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_s1/CLK |
79.777 | 0.442 | tC2Q | FF | 1 | R26C48[0][A] | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_s1/Q |
80.103 | 0.326 | tNET | FF | 1 | R27C49[0][B] | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
80.000 | 80.000 | active clock edge time | ||||
80.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
80.000 | 0.000 | tCL | RR | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
81.936 | 1.936 | tNET | RR | 1 | R27C49[0][B] | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLK |
81.901 | -0.035 | tUnc | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0 | |||
81.610 | -0.291 | tSu | 1 | R27C49[0][B] | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0 |
Path Statistics:
Clock Skew | -2.398 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 1.375, 31.725%; route: 2.959, 68.275% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.326, 42.439%; tC2Q: 0.442, 57.561% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.936, 100.000% |
Path4
Path Summary:
Slack | 1.552 |
Data Arrival Time | 160.014 |
Data Required Time | 161.566 |
From | gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_0_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | Inst3_CLKDIV_OUT:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
150.000 | 150.000 | active clock edge time | ||||
150.000 | 0.000 | tck_pad_i | ||||
150.000 | 0.000 | tCL | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
150.682 | 0.683 | tINS | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
150.682 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
151.365 | 0.683 | tINS | RR | 292 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
154.320 | 2.955 | tNET | RR | 1 | R30C47[1][A] | gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_0_s0/CLK |
154.703 | 0.382 | tC2Q | RR | 3 | R30C47[1][A] | gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_0_s0/Q |
156.527 | 1.824 | tNET | RR | 1 | R26C43[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s6/I0 |
157.043 | 0.516 | tINS | RR | 1 | R26C43[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s6/F |
157.425 | 0.382 | tNET | RR | 1 | R26C40[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s5/I0 |
157.942 | 0.516 | tINS | RR | 3 | R26C40[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s5/F |
158.678 | 0.736 | tNET | RR | 1 | R29C40[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s8/I1 |
159.204 | 0.526 | tINS | RR | 1 | R29C40[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s8/F |
160.014 | 0.810 | tNET | RR | 1 | R29C40[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
160.000 | 160.000 | active clock edge time | ||||
160.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
160.000 | 0.000 | tCL | RR | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
161.913 | 1.912 | tNET | RR | 1 | R29C40[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLK |
161.878 | -0.035 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1 | |||
161.566 | -0.311 | tSu | 1 | R29C40[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1 |
Path Statistics:
Clock Skew | -2.408 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 1.365, 31.595%; route: 2.955, 68.405% |
Arrival Data Path Delay | cell: 1.559, 27.377%; route: 3.753, 65.906%; tC2Q: 0.382, 6.718% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.912, 100.000% |
Path5
Path Summary:
Slack | 1.985 |
Data Arrival Time | 159.827 |
Data Required Time | 161.813 |
From | gw_gao_inst_0/u_la0_top/capture_windows_num_8_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_7_s0 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | Inst3_CLKDIV_OUT:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
150.000 | 150.000 | active clock edge time | ||||
150.000 | 0.000 | tck_pad_i | ||||
150.000 | 0.000 | tCL | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
150.682 | 0.683 | tINS | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
150.682 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
151.365 | 0.683 | tINS | RR | 292 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
154.309 | 2.944 | tNET | RR | 1 | R29C50[0][A] | gw_gao_inst_0/u_la0_top/capture_windows_num_8_s0/CLK |
154.691 | 0.382 | tC2Q | RR | 12 | R29C50[0][A] | gw_gao_inst_0/u_la0_top/capture_windows_num_8_s0/Q |
157.043 | 2.351 | tNET | RR | 1 | R26C42[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_10_s17/I0 |
157.540 | 0.498 | tINS | RR | 6 | R26C42[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_10_s17/F |
158.627 | 1.087 | tNET | RR | 1 | R30C41[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_7_s10/I3 |
159.154 | 0.526 | tINS | RR | 1 | R30C41[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_7_s10/F |
159.311 | 0.157 | tNET | RR | 1 | R31C41[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_7_s8/I1 |
159.827 | 0.516 | tINS | RR | 1 | R31C41[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_7_s8/F |
159.827 | 0.000 | tNET | RR | 1 | R31C41[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_7_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
160.000 | 160.000 | active clock edge time | ||||
160.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
160.000 | 0.000 | tCL | RR | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
161.911 | 1.911 | tNET | RR | 1 | R31C41[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_7_s0/CLK |
161.876 | -0.035 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_7_s0 | |||
161.813 | -0.064 | tSu | 1 | R31C41[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_7_s0 |
Path Statistics:
Clock Skew | -2.398 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 1.365, 31.680%; route: 2.944, 68.320% |
Arrival Data Path Delay | cell: 1.540, 27.905%; route: 3.596, 65.164%; tC2Q: 0.382, 6.931% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.911, 100.000% |
Path6
Path Summary:
Slack | 2.189 |
Data Arrival Time | 159.644 |
Data Required Time | 161.833 |
From | gw_gao_inst_0/u_la0_top/capture_windows_num_8_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_12_s0 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | Inst3_CLKDIV_OUT:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
150.000 | 150.000 | active clock edge time | ||||
150.000 | 0.000 | tck_pad_i | ||||
150.000 | 0.000 | tCL | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
150.682 | 0.683 | tINS | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
150.682 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
151.365 | 0.683 | tINS | RR | 292 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
154.309 | 2.944 | tNET | RR | 1 | R29C50[0][A] | gw_gao_inst_0/u_la0_top/capture_windows_num_8_s0/CLK |
154.691 | 0.382 | tC2Q | RR | 12 | R29C50[0][A] | gw_gao_inst_0/u_la0_top/capture_windows_num_8_s0/Q |
157.043 | 2.351 | tNET | RR | 1 | R26C42[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_8_s11/I2 |
157.559 | 0.516 | tINS | RR | 6 | R26C42[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_8_s11/F |
158.299 | 0.740 | tNET | RR | 1 | R30C42[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_12_s19/I3 |
158.760 | 0.461 | tINS | RR | 1 | R30C42[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_12_s19/F |
158.917 | 0.157 | tNET | RR | 1 | R29C42[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_12_s16/I2 |
159.379 | 0.461 | tINS | RR | 1 | R29C42[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_12_s16/F |
159.381 | 0.003 | tNET | RR | 1 | R29C42[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_12_s13/I3 |
159.644 | 0.262 | tINS | RR | 1 | R29C42[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_12_s13/F |
159.644 | 0.000 | tNET | RR | 1 | R29C42[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_12_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
160.000 | 160.000 | active clock edge time | ||||
160.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
160.000 | 0.000 | tCL | RR | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
161.931 | 1.931 | tNET | RR | 1 | R29C42[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_12_s0/CLK |
161.896 | -0.035 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_12_s0 | |||
161.832 | -0.064 | tSu | 1 | R29C42[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_12_s0 |
Path Statistics:
Clock Skew | -2.378 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 1.365, 31.680%; route: 2.944, 68.320% |
Arrival Data Path Delay | cell: 1.701, 31.888%; route: 3.251, 60.942%; tC2Q: 0.382, 7.170% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.931, 100.000% |
Path7
Path Summary:
Slack | 2.328 |
Data Arrival Time | 159.488 |
Data Required Time | 161.816 |
From | gw_gao_inst_0/u_la0_top/capture_windows_num_8_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_6_s0 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | Inst3_CLKDIV_OUT:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
150.000 | 150.000 | active clock edge time | ||||
150.000 | 0.000 | tck_pad_i | ||||
150.000 | 0.000 | tCL | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
150.682 | 0.683 | tINS | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
150.682 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
151.365 | 0.683 | tINS | RR | 292 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
154.309 | 2.944 | tNET | RR | 1 | R29C50[0][A] | gw_gao_inst_0/u_la0_top/capture_windows_num_8_s0/CLK |
154.691 | 0.382 | tC2Q | RR | 12 | R29C50[0][A] | gw_gao_inst_0/u_la0_top/capture_windows_num_8_s0/Q |
157.043 | 2.351 | tNET | RR | 1 | R26C42[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_10_s17/I0 |
157.540 | 0.498 | tINS | RR | 6 | R26C42[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_10_s17/F |
158.438 | 0.898 | tNET | RR | 1 | R30C42[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_6_s10/I1 |
158.959 | 0.521 | tINS | RR | 1 | R30C42[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_6_s10/F |
158.961 | 0.003 | tNET | RR | 1 | R30C42[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_6_s7/I3 |
159.487 | 0.526 | tINS | RR | 1 | R30C42[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_6_s7/F |
159.488 | 0.000 | tNET | RR | 1 | R30C42[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_6_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
160.000 | 160.000 | active clock edge time | ||||
160.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
160.000 | 0.000 | tCL | RR | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
161.915 | 1.915 | tNET | RR | 1 | R30C42[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_6_s0/CLK |
161.880 | -0.035 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_6_s0 | |||
161.816 | -0.064 | tSu | 1 | R30C42[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_6_s0 |
Path Statistics:
Clock Skew | -2.394 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 1.365, 31.680%; route: 2.944, 68.320% |
Arrival Data Path Delay | cell: 1.545, 29.833%; route: 3.251, 62.781%; tC2Q: 0.382, 7.386% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.915, 100.000% |
Path8
Path Summary:
Slack | 2.391 |
Data Arrival Time | 159.432 |
Data Required Time | 161.823 |
From | gw_gao_inst_0/u_la0_top/capture_windows_num_8_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_10_s0 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | Inst3_CLKDIV_OUT:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
150.000 | 150.000 | active clock edge time | ||||
150.000 | 0.000 | tck_pad_i | ||||
150.000 | 0.000 | tCL | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
150.682 | 0.683 | tINS | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
150.682 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
151.365 | 0.683 | tINS | RR | 292 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
154.309 | 2.944 | tNET | RR | 1 | R29C50[0][A] | gw_gao_inst_0/u_la0_top/capture_windows_num_8_s0/CLK |
154.691 | 0.382 | tC2Q | RR | 12 | R29C50[0][A] | gw_gao_inst_0/u_la0_top/capture_windows_num_8_s0/Q |
157.043 | 2.351 | tNET | RR | 1 | R26C42[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_10_s17/I0 |
157.540 | 0.498 | tINS | RR | 6 | R26C42[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_10_s17/F |
158.435 | 0.895 | tNET | RR | 1 | R29C41[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_10_s14/I3 |
158.932 | 0.498 | tINS | RR | 1 | R29C41[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_10_s14/F |
158.935 | 0.003 | tNET | RR | 1 | R29C41[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_10_s11/I2 |
159.432 | 0.498 | tINS | RR | 1 | R29C41[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_10_s11/F |
159.432 | 0.000 | tNET | RR | 1 | R29C41[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_10_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
160.000 | 160.000 | active clock edge time | ||||
160.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
160.000 | 0.000 | tCL | RR | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
161.922 | 1.922 | tNET | RR | 1 | R29C41[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_10_s0/CLK |
161.887 | -0.035 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_10_s0 | |||
161.823 | -0.064 | tSu | 1 | R29C41[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_10_s0 |
Path Statistics:
Clock Skew | -2.387 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 1.365, 31.680%; route: 2.944, 68.320% |
Arrival Data Path Delay | cell: 1.493, 29.129%; route: 3.249, 63.406%; tC2Q: 0.382, 7.465% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.922, 100.000% |
Path9
Path Summary:
Slack | 2.434 |
Data Arrival Time | 159.413 |
Data Required Time | 161.847 |
From | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_11_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | Inst3_CLKDIV_OUT:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
150.000 | 150.000 | active clock edge time | ||||
150.000 | 0.000 | tck_pad_i | ||||
150.000 | 0.000 | tCL | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
150.682 | 0.683 | tINS | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
150.682 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
151.365 | 0.683 | tINS | RR | 292 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
154.323 | 2.958 | tNET | RR | 1 | R27C50[2][A] | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_11_s0/CLK |
154.706 | 0.382 | tC2Q | RR | 2 | R27C50[2][A] | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_11_s0/Q |
156.454 | 1.749 | tNET | RR | 1 | R30C45[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n457_s8/I1 |
156.744 | 0.290 | tINS | RF | 1 | R30C45[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n457_s8/F |
156.749 | 0.005 | tNET | FF | 1 | R30C45[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n457_s5/I2 |
157.276 | 0.526 | tINS | FR | 1 | R30C45[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n457_s5/F |
157.278 | 0.003 | tNET | RR | 1 | R30C45[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n457_s4/I0 |
157.794 | 0.516 | tINS | RR | 14 | R30C45[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n457_s4/F |
158.916 | 1.121 | tNET | RR | 1 | R27C42[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n469_s3/I2 |
159.413 | 0.498 | tINS | RR | 1 | R27C42[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n469_s3/F |
159.413 | 0.000 | tNET | RR | 1 | R27C42[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
160.000 | 160.000 | active clock edge time | ||||
160.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
160.000 | 0.000 | tCL | RR | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
161.946 | 1.946 | tNET | RR | 1 | R27C42[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/CLK |
161.911 | -0.035 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5 | |||
161.847 | -0.064 | tSu | 1 | R27C42[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5 |
Path Statistics:
Clock Skew | -2.378 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 1.365, 31.574%; route: 2.958, 68.426% |
Arrival Data Path Delay | cell: 1.830, 35.953%; route: 2.878, 56.532%; tC2Q: 0.382, 7.515% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.946, 100.000% |
Path10
Path Summary:
Slack | 2.457 |
Data Arrival Time | 159.397 |
Data Required Time | 161.854 |
From | gw_gao_inst_0/u_la0_top/capture_windows_num_5_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_8_s0 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | Inst3_CLKDIV_OUT:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
150.000 | 150.000 | active clock edge time | ||||
150.000 | 0.000 | tck_pad_i | ||||
150.000 | 0.000 | tCL | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
150.682 | 0.683 | tINS | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
150.682 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
151.365 | 0.683 | tINS | RR | 292 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
154.307 | 2.942 | tNET | RR | 1 | R31C49[0][A] | gw_gao_inst_0/u_la0_top/capture_windows_num_5_s0/CLK |
154.690 | 0.382 | tC2Q | RR | 9 | R31C49[0][A] | gw_gao_inst_0/u_la0_top/capture_windows_num_5_s0/Q |
158.363 | 3.673 | tNET | RR | 1 | R26C42[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_8_s10/I3 |
158.879 | 0.516 | tINS | RR | 1 | R26C42[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_8_s10/F |
158.881 | 0.003 | tNET | RR | 1 | R26C42[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_8_s9/I0 |
159.398 | 0.516 | tINS | RR | 1 | R26C42[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_8_s9/F |
159.397 | 0.000 | tNET | RR | 1 | R26C42[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_8_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
160.000 | 160.000 | active clock edge time | ||||
160.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
160.000 | 0.000 | tCL | RR | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
161.953 | 1.953 | tNET | RR | 1 | R26C42[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_8_s0/CLK |
161.918 | -0.035 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_8_s0 | |||
161.854 | -0.064 | tSu | 1 | R26C42[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_8_s0 |
Path Statistics:
Clock Skew | -2.355 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 1.365, 31.689%; route: 2.942, 68.311% |
Arrival Data Path Delay | cell: 1.033, 20.285%; route: 3.675, 72.200%; tC2Q: 0.382, 7.515% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.953, 100.000% |
Path11
Path Summary:
Slack | 2.479 |
Data Arrival Time | 159.358 |
Data Required Time | 161.837 |
From | gw_gao_inst_0/u_la0_top/capture_windows_num_1_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_11_s0 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | Inst3_CLKDIV_OUT:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
150.000 | 150.000 | active clock edge time | ||||
150.000 | 0.000 | tck_pad_i | ||||
150.000 | 0.000 | tCL | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
150.682 | 0.683 | tINS | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
150.682 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
151.365 | 0.683 | tINS | RR | 292 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
154.340 | 2.975 | tNET | RR | 1 | R26C49[2][A] | gw_gao_inst_0/u_la0_top/capture_windows_num_1_s0/CLK |
154.722 | 0.382 | tC2Q | RR | 5 | R26C49[2][A] | gw_gao_inst_0/u_la0_top/capture_windows_num_1_s0/Q |
156.441 | 1.719 | tNET | RR | 1 | R29C42[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_11_s19/I0 |
156.967 | 0.526 | tINS | RR | 1 | R29C42[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_11_s19/F |
156.970 | 0.003 | tNET | RR | 1 | R29C42[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_11_s18/I0 |
157.486 | 0.516 | tINS | RR | 1 | R29C42[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_11_s18/F |
157.488 | 0.003 | tNET | RR | 1 | R29C42[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_11_s15/I0 |
157.903 | 0.415 | tINS | RR | 1 | R29C42[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_11_s15/F |
158.602 | 0.699 | tNET | RR | 1 | R27C41[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_11_s13/I0 |
158.892 | 0.290 | tINS | RF | 1 | R27C41[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_11_s13/F |
158.897 | 0.005 | tNET | FF | 1 | R27C41[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_11_s12/I0 |
159.358 | 0.461 | tINS | FR | 1 | R27C41[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_11_s12/F |
159.358 | 0.000 | tNET | RR | 1 | R27C41[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_11_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
160.000 | 160.000 | active clock edge time | ||||
160.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
160.000 | 0.000 | tCL | RR | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
161.936 | 1.936 | tNET | RR | 1 | R27C41[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_11_s0/CLK |
161.901 | -0.035 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_11_s0 | |||
161.837 | -0.064 | tSu | 1 | R27C41[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_11_s0 |
Path Statistics:
Clock Skew | -2.403 |
Setup Relationship | 10.000 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 1.365, 31.454%; route: 2.975, 68.546% |
Arrival Data Path Delay | cell: 2.209, 44.010%; route: 2.428, 48.369%; tC2Q: 0.382, 7.621% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.936, 100.000% |
Path12
Path Summary:
Slack | 2.583 |
Data Arrival Time | 159.236 |
Data Required Time | 161.818 |
From | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_11_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | Inst3_CLKDIV_OUT:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
150.000 | 150.000 | active clock edge time | ||||
150.000 | 0.000 | tck_pad_i | ||||
150.000 | 0.000 | tCL | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
150.682 | 0.683 | tINS | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
150.682 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
151.365 | 0.683 | tINS | RR | 292 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
154.323 | 2.958 | tNET | RR | 1 | R27C50[2][A] | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_11_s0/CLK |
154.706 | 0.382 | tC2Q | RR | 2 | R27C50[2][A] | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_11_s0/Q |
156.454 | 1.749 | tNET | RR | 1 | R30C45[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n457_s8/I1 |
156.744 | 0.290 | tINS | RF | 1 | R30C45[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n457_s8/F |
156.749 | 0.005 | tNET | FF | 1 | R30C45[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n457_s5/I2 |
157.276 | 0.526 | tINS | FR | 1 | R30C45[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n457_s5/F |
157.278 | 0.003 | tNET | RR | 1 | R30C45[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n457_s4/I0 |
157.794 | 0.516 | tINS | RR | 14 | R30C45[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n457_s4/F |
158.709 | 0.915 | tNET | RR | 1 | R32C41[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n464_s1/I2 |
159.236 | 0.526 | tINS | RR | 1 | R32C41[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n464_s1/F |
159.236 | 0.000 | tNET | RR | 1 | R32C41[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
160.000 | 160.000 | active clock edge time | ||||
160.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
160.000 | 0.000 | tCL | RR | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
161.917 | 1.917 | tNET | RR | 1 | R32C41[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK |
161.882 | -0.035 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1 | |||
161.818 | -0.064 | tSu | 1 | R32C41[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1 |
Path Statistics:
Clock Skew | -2.406 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 1.365, 31.574%; route: 2.958, 68.426% |
Arrival Data Path Delay | cell: 1.859, 37.837%; route: 2.671, 54.377%; tC2Q: 0.382, 7.786% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.917, 100.000% |
Path13
Path Summary:
Slack | 2.610 |
Data Arrival Time | 159.204 |
Data Required Time | 161.814 |
From | gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_0_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | Inst3_CLKDIV_OUT:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
150.000 | 150.000 | active clock edge time | ||||
150.000 | 0.000 | tck_pad_i | ||||
150.000 | 0.000 | tCL | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
150.682 | 0.683 | tINS | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
150.682 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
151.365 | 0.683 | tINS | RR | 292 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
154.320 | 2.955 | tNET | RR | 1 | R30C47[1][A] | gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_0_s0/CLK |
154.703 | 0.382 | tC2Q | RR | 3 | R30C47[1][A] | gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_0_s0/Q |
156.527 | 1.824 | tNET | RR | 1 | R26C43[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s6/I0 |
157.043 | 0.516 | tINS | RR | 1 | R26C43[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s6/F |
157.425 | 0.382 | tNET | RR | 1 | R26C40[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s5/I0 |
157.942 | 0.516 | tINS | RR | 3 | R26C40[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s5/F |
158.678 | 0.736 | tNET | RR | 1 | R29C40[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n316_s3/I1 |
159.204 | 0.526 | tINS | RR | 1 | R29C40[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n316_s3/F |
159.204 | 0.000 | tNET | RR | 1 | R29C40[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
160.000 | 160.000 | active clock edge time | ||||
160.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
160.000 | 0.000 | tCL | RR | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
161.913 | 1.912 | tNET | RR | 1 | R29C40[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLK |
161.878 | -0.035 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1 | |||
161.814 | -0.064 | tSu | 1 | R29C40[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1 |
Path Statistics:
Clock Skew | -2.408 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 1.365, 31.595%; route: 2.955, 68.405% |
Arrival Data Path Delay | cell: 1.559, 31.917%; route: 2.943, 60.251%; tC2Q: 0.382, 7.832% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.912, 100.000% |
Path14
Path Summary:
Slack | 2.658 |
Data Arrival Time | 158.918 |
Data Required Time | 161.576 |
From | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_11_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | Inst3_CLKDIV_OUT:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
150.000 | 150.000 | active clock edge time | ||||
150.000 | 0.000 | tck_pad_i | ||||
150.000 | 0.000 | tCL | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
150.682 | 0.683 | tINS | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
150.682 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
151.365 | 0.683 | tINS | RR | 292 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
154.323 | 2.958 | tNET | RR | 1 | R27C50[2][A] | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_11_s0/CLK |
154.706 | 0.382 | tC2Q | RR | 2 | R27C50[2][A] | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_11_s0/Q |
156.454 | 1.749 | tNET | RR | 1 | R30C45[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n457_s8/I1 |
156.744 | 0.290 | tINS | RF | 1 | R30C45[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n457_s8/F |
156.749 | 0.005 | tNET | FF | 1 | R30C45[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n457_s5/I2 |
157.276 | 0.526 | tINS | FR | 1 | R30C45[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n457_s5/F |
157.278 | 0.003 | tNET | RR | 1 | R30C45[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n457_s4/I0 |
157.794 | 0.516 | tINS | RR | 14 | R30C45[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n457_s4/F |
158.264 | 0.470 | tNET | RR | 1 | R29C43[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s4/I0 |
158.781 | 0.516 | tINS | RR | 1 | R29C43[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s4/F |
158.918 | 0.137 | tNET | RR | 1 | R29C43[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
160.000 | 160.000 | active clock edge time | ||||
160.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
160.000 | 0.000 | tCL | RR | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
161.922 | 1.922 | tNET | RR | 1 | R29C43[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK |
161.887 | -0.035 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1 | |||
161.576 | -0.311 | tSu | 1 | R29C43[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1 |
Path Statistics:
Clock Skew | -2.401 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 1.365, 31.574%; route: 2.958, 68.426% |
Arrival Data Path Delay | cell: 1.849, 40.234%; route: 2.364, 51.442%; tC2Q: 0.382, 8.324% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.922, 100.000% |
Path15
Path Summary:
Slack | 2.783 |
Data Arrival Time | 159.036 |
Data Required Time | 161.818 |
From | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_11_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | Inst3_CLKDIV_OUT:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
150.000 | 150.000 | active clock edge time | ||||
150.000 | 0.000 | tck_pad_i | ||||
150.000 | 0.000 | tCL | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
150.682 | 0.683 | tINS | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
150.682 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
151.365 | 0.683 | tINS | RR | 292 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
154.323 | 2.958 | tNET | RR | 1 | R27C50[2][A] | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_11_s0/CLK |
154.706 | 0.382 | tC2Q | RR | 2 | R27C50[2][A] | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_11_s0/Q |
156.454 | 1.749 | tNET | RR | 1 | R30C45[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n457_s8/I1 |
156.744 | 0.290 | tINS | RF | 1 | R30C45[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n457_s8/F |
156.749 | 0.005 | tNET | FF | 1 | R30C45[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n457_s5/I2 |
157.276 | 0.526 | tINS | FR | 1 | R30C45[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n457_s5/F |
157.278 | 0.003 | tNET | RR | 1 | R30C45[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n457_s4/I0 |
157.794 | 0.516 | tINS | RR | 14 | R30C45[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n457_s4/F |
158.574 | 0.780 | tNET | RR | 1 | R32C41[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n468_s1/I2 |
159.036 | 0.461 | tINS | RR | 1 | R32C41[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n468_s1/F |
159.036 | 0.000 | tNET | RR | 1 | R32C41[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
160.000 | 160.000 | active clock edge time | ||||
160.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
160.000 | 0.000 | tCL | RR | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
161.917 | 1.917 | tNET | RR | 1 | R32C41[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK |
161.882 | -0.035 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1 | |||
161.818 | -0.064 | tSu | 1 | R32C41[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1 |
Path Statistics:
Clock Skew | -2.406 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 1.365, 31.574%; route: 2.958, 68.426% |
Arrival Data Path Delay | cell: 1.794, 38.064%; route: 2.536, 53.820%; tC2Q: 0.382, 8.117% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.917, 100.000% |
Path16
Path Summary:
Slack | 2.783 |
Data Arrival Time | 159.036 |
Data Required Time | 161.818 |
From | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_11_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | Inst3_CLKDIV_OUT:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
150.000 | 150.000 | active clock edge time | ||||
150.000 | 0.000 | tck_pad_i | ||||
150.000 | 0.000 | tCL | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
150.682 | 0.683 | tINS | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
150.682 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
151.365 | 0.683 | tINS | RR | 292 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
154.323 | 2.958 | tNET | RR | 1 | R27C50[2][A] | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_11_s0/CLK |
154.706 | 0.382 | tC2Q | RR | 2 | R27C50[2][A] | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_11_s0/Q |
156.454 | 1.749 | tNET | RR | 1 | R30C45[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n457_s8/I1 |
156.744 | 0.290 | tINS | RF | 1 | R30C45[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n457_s8/F |
156.749 | 0.005 | tNET | FF | 1 | R30C45[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n457_s5/I2 |
157.276 | 0.526 | tINS | FR | 1 | R30C45[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n457_s5/F |
157.278 | 0.003 | tNET | RR | 1 | R30C45[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n457_s4/I0 |
157.794 | 0.516 | tINS | RR | 14 | R30C45[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n457_s4/F |
158.574 | 0.780 | tNET | RR | 1 | R32C41[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n461_s1/I2 |
159.036 | 0.461 | tINS | RR | 1 | R32C41[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n461_s1/F |
159.036 | 0.000 | tNET | RR | 1 | R32C41[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
160.000 | 160.000 | active clock edge time | ||||
160.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
160.000 | 0.000 | tCL | RR | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
161.917 | 1.917 | tNET | RR | 1 | R32C41[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK |
161.882 | -0.035 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1 | |||
161.818 | -0.064 | tSu | 1 | R32C41[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1 |
Path Statistics:
Clock Skew | -2.406 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 1.365, 31.574%; route: 2.958, 68.426% |
Arrival Data Path Delay | cell: 1.794, 38.064%; route: 2.536, 53.820%; tC2Q: 0.382, 8.117% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.917, 100.000% |
Path17
Path Summary:
Slack | 2.916 |
Data Arrival Time | 158.921 |
Data Required Time | 161.837 |
From | gw_gao_inst_0/u_la0_top/capture_windows_num_8_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_9_s0 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | Inst3_CLKDIV_OUT:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
150.000 | 150.000 | active clock edge time | ||||
150.000 | 0.000 | tck_pad_i | ||||
150.000 | 0.000 | tCL | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
150.682 | 0.683 | tINS | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
150.682 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
151.365 | 0.683 | tINS | RR | 292 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
154.309 | 2.944 | tNET | RR | 1 | R29C50[0][A] | gw_gao_inst_0/u_la0_top/capture_windows_num_8_s0/CLK |
154.691 | 0.382 | tC2Q | RR | 12 | R29C50[0][A] | gw_gao_inst_0/u_la0_top/capture_windows_num_8_s0/Q |
157.043 | 2.351 | tNET | RR | 1 | R26C42[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_8_s11/I2 |
157.559 | 0.516 | tINS | RR | 6 | R26C42[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_8_s11/F |
157.726 | 0.167 | tNET | RR | 1 | R27C42[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s11/I3 |
158.248 | 0.521 | tINS | RR | 1 | R27C42[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s11/F |
158.405 | 0.157 | tNET | RR | 1 | R27C41[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s10/I0 |
158.921 | 0.516 | tINS | RR | 1 | R27C41[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s10/F |
158.921 | 0.000 | tNET | RR | 1 | R27C41[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_9_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
160.000 | 160.000 | active clock edge time | ||||
160.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
160.000 | 0.000 | tCL | RR | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
161.936 | 1.936 | tNET | RR | 1 | R27C41[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_9_s0/CLK |
161.901 | -0.035 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_9_s0 | |||
161.837 | -0.064 | tSu | 1 | R27C41[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_9_s0 |
Path Statistics:
Clock Skew | -2.373 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 1.365, 31.680%; route: 2.944, 68.320% |
Arrival Data Path Delay | cell: 1.554, 33.686%; route: 2.676, 58.022%; tC2Q: 0.382, 8.293% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.936, 100.000% |
Path18
Path Summary:
Slack | 2.917 |
Data Arrival Time | 158.911 |
Data Required Time | 161.828 |
From | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_11_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | Inst3_CLKDIV_OUT:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
150.000 | 150.000 | active clock edge time | ||||
150.000 | 0.000 | tck_pad_i | ||||
150.000 | 0.000 | tCL | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
150.682 | 0.683 | tINS | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
150.682 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
151.365 | 0.683 | tINS | RR | 292 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
154.323 | 2.958 | tNET | RR | 1 | R27C50[2][A] | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_11_s0/CLK |
154.706 | 0.382 | tC2Q | RR | 2 | R27C50[2][A] | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_11_s0/Q |
156.454 | 1.749 | tNET | RR | 1 | R30C45[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n457_s8/I1 |
156.744 | 0.290 | tINS | RF | 1 | R30C45[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n457_s8/F |
156.749 | 0.005 | tNET | FF | 1 | R30C45[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n457_s5/I2 |
157.276 | 0.526 | tINS | FR | 1 | R30C45[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n457_s5/F |
157.278 | 0.003 | tNET | RR | 1 | R30C45[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n457_s4/I0 |
157.794 | 0.516 | tINS | RR | 14 | R30C45[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n457_s4/F |
158.384 | 0.590 | tNET | RR | 1 | R32C42[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n465_s1/I3 |
158.911 | 0.526 | tINS | RR | 1 | R32C42[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n465_s1/F |
158.911 | 0.000 | tNET | RR | 1 | R32C42[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
160.000 | 160.000 | active clock edge time | ||||
160.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
160.000 | 0.000 | tCL | RR | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
161.927 | 1.927 | tNET | RR | 1 | R32C42[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK |
161.892 | -0.035 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1 | |||
161.828 | -0.064 | tSu | 1 | R32C42[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1 |
Path Statistics:
Clock Skew | -2.397 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 1.365, 31.574%; route: 2.958, 68.426% |
Arrival Data Path Delay | cell: 1.859, 40.518%; route: 2.346, 51.144%; tC2Q: 0.382, 8.338% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.927, 100.000% |
Path19
Path Summary:
Slack | 2.921 |
Data Arrival Time | 158.901 |
Data Required Time | 161.822 |
From | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_11_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | Inst3_CLKDIV_OUT:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
150.000 | 150.000 | active clock edge time | ||||
150.000 | 0.000 | tck_pad_i | ||||
150.000 | 0.000 | tCL | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
150.682 | 0.683 | tINS | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
150.682 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
151.365 | 0.683 | tINS | RR | 292 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
154.323 | 2.958 | tNET | RR | 1 | R27C50[2][A] | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_11_s0/CLK |
154.706 | 0.382 | tC2Q | RR | 2 | R27C50[2][A] | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_11_s0/Q |
156.454 | 1.749 | tNET | RR | 1 | R30C45[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n457_s8/I1 |
156.744 | 0.290 | tINS | RF | 1 | R30C45[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n457_s8/F |
156.749 | 0.005 | tNET | FF | 1 | R30C45[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n457_s5/I2 |
157.276 | 0.526 | tINS | FR | 1 | R30C45[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n457_s5/F |
157.278 | 0.003 | tNET | RR | 1 | R30C45[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n457_s4/I0 |
157.794 | 0.516 | tINS | RR | 14 | R30C45[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n457_s4/F |
158.384 | 0.590 | tNET | RR | 1 | R31C42[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n463_s1/I2 |
158.901 | 0.516 | tINS | RR | 1 | R31C42[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n463_s1/F |
158.901 | 0.000 | tNET | RR | 1 | R31C42[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
160.000 | 160.000 | active clock edge time | ||||
160.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
160.000 | 0.000 | tCL | RR | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
161.921 | 1.921 | tNET | RR | 1 | R31C42[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK |
161.886 | -0.035 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1 | |||
161.822 | -0.064 | tSu | 1 | R31C42[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1 |
Path Statistics:
Clock Skew | -2.402 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 1.365, 31.574%; route: 2.958, 68.426% |
Arrival Data Path Delay | cell: 1.849, 40.388%; route: 2.346, 51.256%; tC2Q: 0.382, 8.356% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.921, 100.000% |
Path20
Path Summary:
Slack | 2.927 |
Data Arrival Time | 158.901 |
Data Required Time | 161.828 |
From | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_11_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | Inst3_CLKDIV_OUT:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
150.000 | 150.000 | active clock edge time | ||||
150.000 | 0.000 | tck_pad_i | ||||
150.000 | 0.000 | tCL | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
150.682 | 0.683 | tINS | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
150.682 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
151.365 | 0.683 | tINS | RR | 292 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
154.323 | 2.958 | tNET | RR | 1 | R27C50[2][A] | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_11_s0/CLK |
154.706 | 0.382 | tC2Q | RR | 2 | R27C50[2][A] | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_11_s0/Q |
156.454 | 1.749 | tNET | RR | 1 | R30C45[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n457_s8/I1 |
156.744 | 0.290 | tINS | RF | 1 | R30C45[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n457_s8/F |
156.749 | 0.005 | tNET | FF | 1 | R30C45[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n457_s5/I2 |
157.276 | 0.526 | tINS | FR | 1 | R30C45[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n457_s5/F |
157.278 | 0.003 | tNET | RR | 1 | R30C45[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n457_s4/I0 |
157.794 | 0.516 | tINS | RR | 14 | R30C45[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n457_s4/F |
158.384 | 0.590 | tNET | RR | 1 | R32C42[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n462_s1/I3 |
158.901 | 0.516 | tINS | RR | 1 | R32C42[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n462_s1/F |
158.901 | 0.000 | tNET | RR | 1 | R32C42[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
160.000 | 160.000 | active clock edge time | ||||
160.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
160.000 | 0.000 | tCL | RR | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
161.927 | 1.927 | tNET | RR | 1 | R32C42[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK |
161.892 | -0.035 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1 | |||
161.828 | -0.064 | tSu | 1 | R32C42[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1 |
Path Statistics:
Clock Skew | -2.397 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 1.365, 31.574%; route: 2.958, 68.426% |
Arrival Data Path Delay | cell: 1.849, 40.388%; route: 2.346, 51.256%; tC2Q: 0.382, 8.356% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.927, 100.000% |
Path21
Path Summary:
Slack | 2.927 |
Data Arrival Time | 158.901 |
Data Required Time | 161.828 |
From | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_11_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | Inst3_CLKDIV_OUT:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
150.000 | 150.000 | active clock edge time | ||||
150.000 | 0.000 | tck_pad_i | ||||
150.000 | 0.000 | tCL | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
150.682 | 0.683 | tINS | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
150.682 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
151.365 | 0.683 | tINS | RR | 292 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
154.323 | 2.958 | tNET | RR | 1 | R27C50[2][A] | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_11_s0/CLK |
154.706 | 0.382 | tC2Q | RR | 2 | R27C50[2][A] | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_11_s0/Q |
156.454 | 1.749 | tNET | RR | 1 | R30C45[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n457_s8/I1 |
156.744 | 0.290 | tINS | RF | 1 | R30C45[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n457_s8/F |
156.749 | 0.005 | tNET | FF | 1 | R30C45[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n457_s5/I2 |
157.276 | 0.526 | tINS | FR | 1 | R30C45[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n457_s5/F |
157.278 | 0.003 | tNET | RR | 1 | R30C45[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n457_s4/I0 |
157.794 | 0.516 | tINS | RR | 14 | R30C45[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n457_s4/F |
158.384 | 0.590 | tNET | RR | 1 | R32C42[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n459_s1/I2 |
158.901 | 0.516 | tINS | RR | 1 | R32C42[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n459_s1/F |
158.901 | 0.000 | tNET | RR | 1 | R32C42[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
160.000 | 160.000 | active clock edge time | ||||
160.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
160.000 | 0.000 | tCL | RR | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
161.927 | 1.927 | tNET | RR | 1 | R32C42[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/CLK |
161.892 | -0.035 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1 | |||
161.828 | -0.064 | tSu | 1 | R32C42[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1 |
Path Statistics:
Clock Skew | -2.397 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 1.365, 31.574%; route: 2.958, 68.426% |
Arrival Data Path Delay | cell: 1.849, 40.388%; route: 2.346, 51.256%; tC2Q: 0.382, 8.356% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.927, 100.000% |
Path22
Path Summary:
Slack | 2.981 |
Data Arrival Time | 158.841 |
Data Required Time | 161.822 |
From | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_11_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_11_s1 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | Inst3_CLKDIV_OUT:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
150.000 | 150.000 | active clock edge time | ||||
150.000 | 0.000 | tck_pad_i | ||||
150.000 | 0.000 | tCL | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
150.682 | 0.683 | tINS | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
150.682 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
151.365 | 0.683 | tINS | RR | 292 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
154.323 | 2.958 | tNET | RR | 1 | R27C50[2][A] | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_11_s0/CLK |
154.706 | 0.382 | tC2Q | RR | 2 | R27C50[2][A] | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_11_s0/Q |
156.454 | 1.749 | tNET | RR | 1 | R30C45[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n457_s8/I1 |
156.744 | 0.290 | tINS | RF | 1 | R30C45[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n457_s8/F |
156.749 | 0.005 | tNET | FF | 1 | R30C45[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n457_s5/I2 |
157.276 | 0.526 | tINS | FR | 1 | R30C45[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n457_s5/F |
157.278 | 0.003 | tNET | RR | 1 | R30C45[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n457_s4/I0 |
157.794 | 0.516 | tINS | RR | 14 | R30C45[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n457_s4/F |
158.379 | 0.585 | tNET | RR | 1 | R31C42[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n458_s1/I2 |
158.841 | 0.461 | tINS | RR | 1 | R31C42[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n458_s1/F |
158.841 | 0.000 | tNET | RR | 1 | R31C42[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_11_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
160.000 | 160.000 | active clock edge time | ||||
160.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
160.000 | 0.000 | tCL | RR | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
161.921 | 1.921 | tNET | RR | 1 | R31C42[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_11_s1/CLK |
161.886 | -0.035 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_11_s1 | |||
161.822 | -0.064 | tSu | 1 | R31C42[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_11_s1 |
Path Statistics:
Clock Skew | -2.402 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 1.365, 31.574%; route: 2.958, 68.426% |
Arrival Data Path Delay | cell: 1.794, 39.707%; route: 2.341, 51.826%; tC2Q: 0.382, 8.467% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.921, 100.000% |
Path23
Path Summary:
Slack | 2.981 |
Data Arrival Time | 158.841 |
Data Required Time | 161.822 |
From | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_11_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_12_s1 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | Inst3_CLKDIV_OUT:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
150.000 | 150.000 | active clock edge time | ||||
150.000 | 0.000 | tck_pad_i | ||||
150.000 | 0.000 | tCL | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
150.682 | 0.683 | tINS | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
150.682 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
151.365 | 0.683 | tINS | RR | 292 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
154.323 | 2.958 | tNET | RR | 1 | R27C50[2][A] | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_11_s0/CLK |
154.706 | 0.382 | tC2Q | RR | 2 | R27C50[2][A] | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_11_s0/Q |
156.454 | 1.749 | tNET | RR | 1 | R30C45[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n457_s8/I1 |
156.744 | 0.290 | tINS | RF | 1 | R30C45[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n457_s8/F |
156.749 | 0.005 | tNET | FF | 1 | R30C45[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n457_s5/I2 |
157.276 | 0.526 | tINS | FR | 1 | R30C45[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n457_s5/F |
157.278 | 0.003 | tNET | RR | 1 | R30C45[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n457_s4/I0 |
157.794 | 0.516 | tINS | RR | 14 | R30C45[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n457_s4/F |
158.379 | 0.585 | tNET | RR | 1 | R31C42[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n457_s2/I3 |
158.841 | 0.461 | tINS | RR | 1 | R31C42[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n457_s2/F |
158.841 | 0.000 | tNET | RR | 1 | R31C42[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_12_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
160.000 | 160.000 | active clock edge time | ||||
160.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
160.000 | 0.000 | tCL | RR | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
161.921 | 1.921 | tNET | RR | 1 | R31C42[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_12_s1/CLK |
161.886 | -0.035 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_12_s1 | |||
161.822 | -0.064 | tSu | 1 | R31C42[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_12_s1 |
Path Statistics:
Clock Skew | -2.402 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 1.365, 31.574%; route: 2.958, 68.426% |
Arrival Data Path Delay | cell: 1.794, 39.707%; route: 2.341, 51.826%; tC2Q: 0.382, 8.467% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.921, 100.000% |
Path24
Path Summary:
Slack | 2.997 |
Data Arrival Time | 158.817 |
Data Required Time | 161.814 |
From | gw_gao_inst_0/u_la0_top/capture_windows_num_7_s0 |
To | gw_gao_inst_0/u_la0_top/start_reg_s0 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | Inst3_CLKDIV_OUT:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
150.000 | 150.000 | active clock edge time | ||||
150.000 | 0.000 | tck_pad_i | ||||
150.000 | 0.000 | tCL | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
150.682 | 0.683 | tINS | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
150.682 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
151.365 | 0.683 | tINS | RR | 292 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
154.349 | 2.984 | tNET | RR | 1 | R26C48[3][B] | gw_gao_inst_0/u_la0_top/capture_windows_num_7_s0/CLK |
154.732 | 0.382 | tC2Q | RR | 8 | R26C48[3][B] | gw_gao_inst_0/u_la0_top/capture_windows_num_7_s0/Q |
156.210 | 1.479 | tNET | RR | 2 | R25C50[0][B] | gw_gao_inst_0/u_la0_top/n2360_s33/I0 |
156.767 | 0.556 | tINS | RF | 1 | R25C50[0][B] | gw_gao_inst_0/u_la0_top/n2360_s33/COUT |
156.767 | 0.000 | tNET | FF | 2 | R25C50[1][A] | gw_gao_inst_0/u_la0_top/n2360_s34/CIN |
156.817 | 0.050 | tINS | FR | 1 | R25C50[1][A] | gw_gao_inst_0/u_la0_top/n2360_s34/COUT |
156.817 | 0.000 | tNET | RR | 2 | R25C50[1][B] | gw_gao_inst_0/u_la0_top/n2360_s35/CIN |
156.867 | 0.050 | tINS | RR | 1 | R25C50[1][B] | gw_gao_inst_0/u_la0_top/n2360_s35/COUT |
156.867 | 0.000 | tNET | RR | 2 | R25C50[2][A] | gw_gao_inst_0/u_la0_top/n2360_s36/CIN |
156.917 | 0.050 | tINS | RR | 1 | R25C50[2][A] | gw_gao_inst_0/u_la0_top/n2360_s36/COUT |
156.917 | 0.000 | tNET | RR | 2 | R25C50[2][B] | gw_gao_inst_0/u_la0_top/n2360_s37/CIN |
156.967 | 0.050 | tINS | RF | 2 | R25C50[2][B] | gw_gao_inst_0/u_la0_top/n2360_s37/COUT |
157.408 | 0.441 | tNET | FF | 1 | R25C49[3][B] | gw_gao_inst_0/u_la0_top/start_reg1_s1/I1 |
157.673 | 0.265 | tINS | FR | 1 | R25C49[3][B] | gw_gao_inst_0/u_la0_top/start_reg1_s1/F |
158.554 | 0.881 | tNET | RR | 1 | R29C48[0][B] | gw_gao_inst_0/u_la0_top/start_reg1_s0/I1 |
158.817 | 0.262 | tINS | RR | 1 | R29C48[0][B] | gw_gao_inst_0/u_la0_top/start_reg1_s0/F |
158.817 | 0.000 | tNET | RR | 1 | R29C48[0][B] | gw_gao_inst_0/u_la0_top/start_reg_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
160.000 | 160.000 | active clock edge time | ||||
160.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
160.000 | 0.000 | tCL | RR | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
161.913 | 1.912 | tNET | RR | 1 | R29C48[0][B] | gw_gao_inst_0/u_la0_top/start_reg_s0/CLK |
161.878 | -0.035 | tUnc | gw_gao_inst_0/u_la0_top/start_reg_s0 | |||
161.814 | -0.064 | tSu | 1 | R29C48[0][B] | gw_gao_inst_0/u_la0_top/start_reg_s0 |
Path Statistics:
Clock Skew | -2.437 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 1.365, 31.386%; route: 2.984, 68.614% |
Arrival Data Path Delay | cell: 1.284, 28.735%; route: 2.801, 62.703%; tC2Q: 0.382, 8.562% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.912, 100.000% |
Path25
Path Summary:
Slack | 3.103 |
Data Arrival Time | 158.703 |
Data Required Time | 161.807 |
From | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_11_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | Inst3_CLKDIV_OUT:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
150.000 | 150.000 | active clock edge time | ||||
150.000 | 0.000 | tck_pad_i | ||||
150.000 | 0.000 | tCL | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
150.682 | 0.683 | tINS | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
150.682 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
151.365 | 0.683 | tINS | RR | 292 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
154.323 | 2.958 | tNET | RR | 1 | R27C50[2][A] | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_11_s0/CLK |
154.706 | 0.382 | tC2Q | RR | 2 | R27C50[2][A] | gw_gao_inst_0/u_la0_top/capture_mem_addr_max_11_s0/Q |
156.454 | 1.749 | tNET | RR | 1 | R30C45[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n457_s8/I1 |
156.744 | 0.290 | tINS | RF | 1 | R30C45[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n457_s8/F |
156.749 | 0.005 | tNET | FF | 1 | R30C45[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n457_s5/I2 |
157.276 | 0.526 | tINS | FR | 1 | R30C45[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n457_s5/F |
157.278 | 0.003 | tNET | RR | 1 | R30C45[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n457_s4/I0 |
157.794 | 0.516 | tINS | RR | 14 | R30C45[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n457_s4/F |
158.187 | 0.392 | tNET | RR | 1 | R30C41[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n466_s1/I2 |
158.703 | 0.516 | tINS | RR | 1 | R30C41[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n466_s1/F |
158.703 | 0.000 | tNET | RR | 1 | R30C41[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
160.000 | 160.000 | active clock edge time | ||||
160.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
160.000 | 0.000 | tCL | RR | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
161.905 | 1.905 | tNET | RR | 1 | R30C41[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK |
161.870 | -0.035 | tUnc | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1 | |||
161.807 | -0.064 | tSu | 1 | R30C41[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1 |
Path Statistics:
Clock Skew | -2.418 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 1.365, 31.574%; route: 2.958, 68.426% |
Arrival Data Path Delay | cell: 1.849, 42.209%; route: 2.149, 49.058%; tC2Q: 0.382, 8.733% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.905, 100.000% |
Hold Analysis Report
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 0.148 |
Data Arrival Time | 0.965 |
Data Required Time | 0.817 |
From | dout1_14_s0 |
To | u_MIPI_TX_Advance_Top/DPHY_TX_INST/u_oserx4x8/U5_OSER16_0 |
Launch Clk | U3_CLKDIV:[R] |
Latch Clk | U3_CLKDIV:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | U3_CLKDIV | ||||
0.000 | 0.000 | tCL | RR | 30 | LEFTSIDE[0] | U3_CLKDIV/CLKOUT |
0.724 | 0.724 | tNET | RR | 1 | R2C23[2][A] | dout1_14_s0/CLK |
0.868 | 0.144 | tC2Q | RR | 8 | R2C23[2][A] | dout1_14_s0/Q |
0.965 | 0.097 | tNET | RR | 1 | IOT23[A] | u_MIPI_TX_Advance_Top/DPHY_TX_INST/u_oserx4x8/U5_OSER16_0/D6 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | U3_CLKDIV | ||||
0.000 | 0.000 | tCL | RR | 30 | LEFTSIDE[0] | U3_CLKDIV/CLKOUT |
0.722 | 0.722 | tNET | RR | 1 | IOT23[A] | u_MIPI_TX_Advance_Top/DPHY_TX_INST/u_oserx4x8/U5_OSER16_0/PCLK |
0.817 | 0.095 | tHld | 1 | IOT23[A] | u_MIPI_TX_Advance_Top/DPHY_TX_INST/u_oserx4x8/U5_OSER16_0 |
Path Statistics:
Clock Skew | -0.002 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.724, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.097, 40.249%; tC2Q: 0.144, 59.751% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.722, 100.000% |
Path2
Path Summary:
Slack | 0.154 |
Data Arrival Time | 0.959 |
Data Required Time | 0.805 |
From | dout1_15_s0 |
To | u_MIPI_TX_Advance_Top/DPHY_TX_INST/u_oserx4x8/U5_OSER16_0 |
Launch Clk | U3_CLKDIV:[R] |
Latch Clk | U3_CLKDIV:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | U3_CLKDIV | ||||
0.000 | 0.000 | tCL | RR | 30 | LEFTSIDE[0] | U3_CLKDIV/CLKOUT |
0.720 | 0.720 | tNET | RR | 1 | R2C24[0][A] | dout1_15_s0/CLK |
0.864 | 0.144 | tC2Q | RR | 4 | R2C24[0][A] | dout1_15_s0/Q |
0.959 | 0.095 | tNET | RR | 1 | IOT23[A] | u_MIPI_TX_Advance_Top/DPHY_TX_INST/u_oserx4x8/U5_OSER16_0/D15 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | U3_CLKDIV | ||||
0.000 | 0.000 | tCL | RR | 30 | LEFTSIDE[0] | U3_CLKDIV/CLKOUT |
0.722 | 0.722 | tNET | RR | 1 | IOT23[A] | u_MIPI_TX_Advance_Top/DPHY_TX_INST/u_oserx4x8/U5_OSER16_0/PCLK |
0.805 | 0.083 | tHld | 1 | IOT23[A] | u_MIPI_TX_Advance_Top/DPHY_TX_INST/u_oserx4x8/U5_OSER16_0 |
Path Statistics:
Clock Skew | 0.002 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.720, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.095, 39.749%; tC2Q: 0.144, 60.251% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.722, 100.000% |
Path3
Path Summary:
Slack | 0.164 |
Data Arrival Time | 0.969 |
Data Required Time | 0.805 |
From | dout1_7_s0 |
To | u_MIPI_TX_Advance_Top/DPHY_TX_INST/u_oserx4x8/U5_OSER16_0 |
Launch Clk | U3_CLKDIV:[R] |
Latch Clk | U3_CLKDIV:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | U3_CLKDIV | ||||
0.000 | 0.000 | tCL | RR | 30 | LEFTSIDE[0] | U3_CLKDIV/CLKOUT |
0.724 | 0.724 | tNET | RR | 1 | R2C23[1][A] | dout1_7_s0/CLK |
0.868 | 0.144 | tC2Q | RR | 4 | R2C23[1][A] | dout1_7_s0/Q |
0.969 | 0.101 | tNET | RR | 1 | IOT23[A] | u_MIPI_TX_Advance_Top/DPHY_TX_INST/u_oserx4x8/U5_OSER16_0/D7 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | U3_CLKDIV | ||||
0.000 | 0.000 | tCL | RR | 30 | LEFTSIDE[0] | U3_CLKDIV/CLKOUT |
0.722 | 0.722 | tNET | RR | 1 | IOT23[A] | u_MIPI_TX_Advance_Top/DPHY_TX_INST/u_oserx4x8/U5_OSER16_0/PCLK |
0.805 | 0.083 | tHld | 1 | IOT23[A] | u_MIPI_TX_Advance_Top/DPHY_TX_INST/u_oserx4x8/U5_OSER16_0 |
Path Statistics:
Clock Skew | -0.002 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.724, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.101, 41.224%; tC2Q: 0.144, 58.776% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.722, 100.000% |
Path4
Path Summary:
Slack | 0.222 |
Data Arrival Time | 2.776 |
Data Required Time | 2.554 |
From | gw_gao_inst_0/u_la0_top/address_counter_10_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_17_s |
Launch Clk | tck_pad_i:[R] |
Latch Clk | tck_pad_i:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
0.675 | 0.675 | tINS | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
1.351 | 0.675 | tINS | RR | 292 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
2.528 | 1.177 | tNET | RR | 1 | R27C47[1][B] | gw_gao_inst_0/u_la0_top/address_counter_10_s0/CLK |
2.672 | 0.144 | tC2Q | RR | 25 | R27C47[1][B] | gw_gao_inst_0/u_la0_top/address_counter_10_s0/Q |
2.776 | 0.104 | tNET | RR | 1 | BSRAM_R28[14] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_17_s/ADB[11] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
0.675 | 0.675 | tINS | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
1.351 | 0.675 | tINS | RR | 292 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
2.519 | 1.168 | tNET | RR | 1 | BSRAM_R28[14] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_17_s/CLKB |
2.554 | 0.035 | tHld | 1 | BSRAM_R28[14] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_17_s |
Path Statistics:
Clock Skew | -0.009 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 1.351, 53.452%; route: 1.177, 46.548% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.104, 41.935%; tC2Q: 0.144, 58.065% |
Required Clock Path Delay | cell: 1.351, 53.632%; route: 1.168, 46.368% |
Path5
Path Summary:
Slack | 0.223 |
Data Arrival Time | 2.777 |
Data Required Time | 2.554 |
From | gw_gao_inst_0/u_la0_top/address_counter_5_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_17_s |
Launch Clk | tck_pad_i:[R] |
Latch Clk | tck_pad_i:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
0.675 | 0.675 | tINS | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
1.351 | 0.675 | tINS | RR | 292 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
2.528 | 1.177 | tNET | RR | 1 | R27C47[0][A] | gw_gao_inst_0/u_la0_top/address_counter_5_s0/CLK |
2.672 | 0.144 | tC2Q | RR | 25 | R27C47[0][A] | gw_gao_inst_0/u_la0_top/address_counter_5_s0/Q |
2.777 | 0.105 | tNET | RR | 1 | BSRAM_R28[14] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_17_s/ADB[6] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
0.675 | 0.675 | tINS | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
1.351 | 0.675 | tINS | RR | 292 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
2.519 | 1.168 | tNET | RR | 1 | BSRAM_R28[14] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_17_s/CLKB |
2.554 | 0.035 | tHld | 1 | BSRAM_R28[14] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_17_s |
Path Statistics:
Clock Skew | -0.009 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 1.351, 53.452%; route: 1.177, 46.548% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.105, 42.169%; tC2Q: 0.144, 57.831% |
Required Clock Path Delay | cell: 1.351, 53.632%; route: 1.168, 46.368% |
Path6
Path Summary:
Slack | 0.229 |
Data Arrival Time | 1.046 |
Data Required Time | 0.817 |
From | dout1_12_s0 |
To | u_MIPI_TX_Advance_Top/DPHY_TX_INST/u_oserx4x8/U5_OSER16_0 |
Launch Clk | U3_CLKDIV:[R] |
Latch Clk | U3_CLKDIV:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | U3_CLKDIV | ||||
0.000 | 0.000 | tCL | RR | 30 | LEFTSIDE[0] | U3_CLKDIV/CLKOUT |
0.724 | 0.724 | tNET | RR | 1 | R2C23[3][A] | dout1_12_s0/CLK |
0.868 | 0.144 | tC2Q | RR | 16 | R2C23[3][A] | dout1_12_s0/Q |
1.046 | 0.178 | tNET | RR | 1 | IOT23[A] | u_MIPI_TX_Advance_Top/DPHY_TX_INST/u_oserx4x8/U5_OSER16_0/D4 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | U3_CLKDIV | ||||
0.000 | 0.000 | tCL | RR | 30 | LEFTSIDE[0] | U3_CLKDIV/CLKOUT |
0.722 | 0.722 | tNET | RR | 1 | IOT23[A] | u_MIPI_TX_Advance_Top/DPHY_TX_INST/u_oserx4x8/U5_OSER16_0/PCLK |
0.817 | 0.095 | tHld | 1 | IOT23[A] | u_MIPI_TX_Advance_Top/DPHY_TX_INST/u_oserx4x8/U5_OSER16_0 |
Path Statistics:
Clock Skew | -0.002 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.724, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.178, 55.280%; tC2Q: 0.144, 44.721% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.722, 100.000% |
Path7
Path Summary:
Slack | 0.234 |
Data Arrival Time | 2.788 |
Data Required Time | 2.554 |
From | gw_gao_inst_0/u_la0_top/address_counter_7_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_17_s |
Launch Clk | tck_pad_i:[R] |
Latch Clk | tck_pad_i:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
0.675 | 0.675 | tINS | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
1.351 | 0.675 | tINS | RR | 292 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
2.533 | 1.182 | tNET | RR | 1 | R26C47[2][B] | gw_gao_inst_0/u_la0_top/address_counter_7_s0/CLK |
2.677 | 0.144 | tC2Q | RR | 25 | R26C47[2][B] | gw_gao_inst_0/u_la0_top/address_counter_7_s0/Q |
2.788 | 0.111 | tNET | RR | 1 | BSRAM_R28[14] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_17_s/ADB[8] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
0.675 | 0.675 | tINS | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
1.351 | 0.675 | tINS | RR | 292 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
2.519 | 1.168 | tNET | RR | 1 | BSRAM_R28[14] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_17_s/CLKB |
2.554 | 0.035 | tHld | 1 | BSRAM_R28[14] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_17_s |
Path Statistics:
Clock Skew | -0.013 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 1.351, 53.346%; route: 1.182, 46.654% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.111, 43.529%; tC2Q: 0.144, 56.471% |
Required Clock Path Delay | cell: 1.351, 53.632%; route: 1.168, 46.368% |
Path8
Path Summary:
Slack | 0.239 |
Data Arrival Time | 1.044 |
Data Required Time | 0.805 |
From | dout1_3_s0 |
To | u_MIPI_TX_Advance_Top/DPHY_TX_INST/u_oserx4x8/U5_OSER16_0 |
Launch Clk | U3_CLKDIV:[R] |
Latch Clk | U3_CLKDIV:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | U3_CLKDIV | ||||
0.000 | 0.000 | tCL | RR | 30 | LEFTSIDE[0] | U3_CLKDIV/CLKOUT |
0.724 | 0.724 | tNET | RR | 1 | R2C23[1][B] | dout1_3_s0/CLK |
0.868 | 0.144 | tC2Q | RR | 4 | R2C23[1][B] | dout1_3_s0/Q |
1.044 | 0.176 | tNET | RR | 1 | IOT23[A] | u_MIPI_TX_Advance_Top/DPHY_TX_INST/u_oserx4x8/U5_OSER16_0/D3 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | U3_CLKDIV | ||||
0.000 | 0.000 | tCL | RR | 30 | LEFTSIDE[0] | U3_CLKDIV/CLKOUT |
0.722 | 0.722 | tNET | RR | 1 | IOT23[A] | u_MIPI_TX_Advance_Top/DPHY_TX_INST/u_oserx4x8/U5_OSER16_0/PCLK |
0.805 | 0.083 | tHld | 1 | IOT23[A] | u_MIPI_TX_Advance_Top/DPHY_TX_INST/u_oserx4x8/U5_OSER16_0 |
Path Statistics:
Clock Skew | -0.002 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.724, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.176, 55.000%; tC2Q: 0.144, 45.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.722, 100.000% |
Path9
Path Summary:
Slack | 0.240 |
Data Arrival Time | 1.057 |
Data Required Time | 0.817 |
From | dout1_2_s0 |
To | u_MIPI_TX_Advance_Top/DPHY_TX_INST/u_oserx4x8/U5_OSER16_0 |
Launch Clk | U3_CLKDIV:[R] |
Latch Clk | U3_CLKDIV:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | U3_CLKDIV | ||||
0.000 | 0.000 | tCL | RR | 30 | LEFTSIDE[0] | U3_CLKDIV/CLKOUT |
0.720 | 0.720 | tNET | RR | 1 | R2C24[0][B] | dout1_2_s0/CLK |
0.864 | 0.144 | tC2Q | RR | 8 | R2C24[0][B] | dout1_2_s0/Q |
1.057 | 0.193 | tNET | RR | 1 | IOT23[A] | u_MIPI_TX_Advance_Top/DPHY_TX_INST/u_oserx4x8/U5_OSER16_0/D0 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | U3_CLKDIV | ||||
0.000 | 0.000 | tCL | RR | 30 | LEFTSIDE[0] | U3_CLKDIV/CLKOUT |
0.722 | 0.722 | tNET | RR | 1 | IOT23[A] | u_MIPI_TX_Advance_Top/DPHY_TX_INST/u_oserx4x8/U5_OSER16_0/PCLK |
0.817 | 0.095 | tHld | 1 | IOT23[A] | u_MIPI_TX_Advance_Top/DPHY_TX_INST/u_oserx4x8/U5_OSER16_0 |
Path Statistics:
Clock Skew | 0.002 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.720, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.193, 57.270%; tC2Q: 0.144, 42.730% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.722, 100.000% |
Path10
Path Summary:
Slack | 0.244 |
Data Arrival Time | 1.061 |
Data Required Time | 0.817 |
From | dout1_14_s0 |
To | u_MIPI_TX_Advance_Top/DPHY_TX_INST/u_oserx4x8/U5_OSER16_0 |
Launch Clk | U3_CLKDIV:[R] |
Latch Clk | U3_CLKDIV:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | U3_CLKDIV | ||||
0.000 | 0.000 | tCL | RR | 30 | LEFTSIDE[0] | U3_CLKDIV/CLKOUT |
0.724 | 0.724 | tNET | RR | 1 | R2C23[2][A] | dout1_14_s0/CLK |
0.868 | 0.144 | tC2Q | RR | 8 | R2C23[2][A] | dout1_14_s0/Q |
1.061 | 0.193 | tNET | RR | 1 | IOT23[A] | u_MIPI_TX_Advance_Top/DPHY_TX_INST/u_oserx4x8/U5_OSER16_0/D14 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | U3_CLKDIV | ||||
0.000 | 0.000 | tCL | RR | 30 | LEFTSIDE[0] | U3_CLKDIV/CLKOUT |
0.722 | 0.722 | tNET | RR | 1 | IOT23[A] | u_MIPI_TX_Advance_Top/DPHY_TX_INST/u_oserx4x8/U5_OSER16_0/PCLK |
0.817 | 0.095 | tHld | 1 | IOT23[A] | u_MIPI_TX_Advance_Top/DPHY_TX_INST/u_oserx4x8/U5_OSER16_0 |
Path Statistics:
Clock Skew | -0.002 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.724, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.193, 57.270%; tC2Q: 0.144, 42.730% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.722, 100.000% |
Path11
Path Summary:
Slack | 0.250 |
Data Arrival Time | 1.055 |
Data Required Time | 0.805 |
From | dout1_1_s0 |
To | u_MIPI_TX_Advance_Top/DPHY_TX_INST/u_oserx4x8/U5_OSER16_0 |
Launch Clk | U3_CLKDIV:[R] |
Latch Clk | U3_CLKDIV:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | U3_CLKDIV | ||||
0.000 | 0.000 | tCL | RR | 30 | LEFTSIDE[0] | U3_CLKDIV/CLKOUT |
0.720 | 0.720 | tNET | RR | 1 | R2C24[1][A] | dout1_1_s0/CLK |
0.864 | 0.144 | tC2Q | RR | 4 | R2C24[1][A] | dout1_1_s0/Q |
1.055 | 0.191 | tNET | RR | 1 | IOT23[A] | u_MIPI_TX_Advance_Top/DPHY_TX_INST/u_oserx4x8/U5_OSER16_0/D1 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | U3_CLKDIV | ||||
0.000 | 0.000 | tCL | RR | 30 | LEFTSIDE[0] | U3_CLKDIV/CLKOUT |
0.722 | 0.722 | tNET | RR | 1 | IOT23[A] | u_MIPI_TX_Advance_Top/DPHY_TX_INST/u_oserx4x8/U5_OSER16_0/PCLK |
0.805 | 0.083 | tHld | 1 | IOT23[A] | u_MIPI_TX_Advance_Top/DPHY_TX_INST/u_oserx4x8/U5_OSER16_0 |
Path Statistics:
Clock Skew | 0.002 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.720, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.191, 57.015%; tC2Q: 0.144, 42.985% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.722, 100.000% |
Path12
Path Summary:
Slack | 0.254 |
Data Arrival Time | 1.071 |
Data Required Time | 0.817 |
From | dout1_12_s0 |
To | u_MIPI_TX_Advance_Top/DPHY_TX_INST/u_oserx4x8/U5_OSER16_0 |
Launch Clk | U3_CLKDIV:[R] |
Latch Clk | U3_CLKDIV:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | U3_CLKDIV | ||||
0.000 | 0.000 | tCL | RR | 30 | LEFTSIDE[0] | U3_CLKDIV/CLKOUT |
0.724 | 0.724 | tNET | RR | 1 | R2C23[3][A] | dout1_12_s0/CLK |
0.868 | 0.144 | tC2Q | RR | 16 | R2C23[3][A] | dout1_12_s0/Q |
1.071 | 0.203 | tNET | RR | 1 | IOT23[A] | u_MIPI_TX_Advance_Top/DPHY_TX_INST/u_oserx4x8/U5_OSER16_0/D12 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | U3_CLKDIV | ||||
0.000 | 0.000 | tCL | RR | 30 | LEFTSIDE[0] | U3_CLKDIV/CLKOUT |
0.722 | 0.722 | tNET | RR | 1 | IOT23[A] | u_MIPI_TX_Advance_Top/DPHY_TX_INST/u_oserx4x8/U5_OSER16_0/PCLK |
0.817 | 0.095 | tHld | 1 | IOT23[A] | u_MIPI_TX_Advance_Top/DPHY_TX_INST/u_oserx4x8/U5_OSER16_0 |
Path Statistics:
Clock Skew | -0.002 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.724, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.203, 58.501%; tC2Q: 0.144, 41.499% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.722, 100.000% |
Path13
Path Summary:
Slack | 0.254 |
Data Arrival Time | 1.071 |
Data Required Time | 0.817 |
From | dout1_12_s0 |
To | u_MIPI_TX_Advance_Top/DPHY_TX_INST/u_oserx4x8/U5_OSER16_0 |
Launch Clk | U3_CLKDIV:[R] |
Latch Clk | U3_CLKDIV:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | U3_CLKDIV | ||||
0.000 | 0.000 | tCL | RR | 30 | LEFTSIDE[0] | U3_CLKDIV/CLKOUT |
0.724 | 0.724 | tNET | RR | 1 | R2C23[3][A] | dout1_12_s0/CLK |
0.868 | 0.144 | tC2Q | RR | 16 | R2C23[3][A] | dout1_12_s0/Q |
1.071 | 0.203 | tNET | RR | 1 | IOT23[A] | u_MIPI_TX_Advance_Top/DPHY_TX_INST/u_oserx4x8/U5_OSER16_0/D10 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | U3_CLKDIV | ||||
0.000 | 0.000 | tCL | RR | 30 | LEFTSIDE[0] | U3_CLKDIV/CLKOUT |
0.722 | 0.722 | tNET | RR | 1 | IOT23[A] | u_MIPI_TX_Advance_Top/DPHY_TX_INST/u_oserx4x8/U5_OSER16_0/PCLK |
0.817 | 0.095 | tHld | 1 | IOT23[A] | u_MIPI_TX_Advance_Top/DPHY_TX_INST/u_oserx4x8/U5_OSER16_0 |
Path Statistics:
Clock Skew | -0.002 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.724, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.203, 58.501%; tC2Q: 0.144, 41.499% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.722, 100.000% |
Path14
Path Summary:
Slack | 0.254 |
Data Arrival Time | 1.059 |
Data Required Time | 0.805 |
From | dout1_9_s0 |
To | u_MIPI_TX_Advance_Top/DPHY_TX_INST/u_oserx4x8/U5_OSER16_0 |
Launch Clk | U3_CLKDIV:[R] |
Latch Clk | U3_CLKDIV:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | U3_CLKDIV | ||||
0.000 | 0.000 | tCL | RR | 30 | LEFTSIDE[0] | U3_CLKDIV/CLKOUT |
0.724 | 0.724 | tNET | RR | 1 | R2C23[0][B] | dout1_9_s0/CLK |
0.868 | 0.144 | tC2Q | RR | 4 | R2C23[0][B] | dout1_9_s0/Q |
1.059 | 0.191 | tNET | RR | 1 | IOT23[A] | u_MIPI_TX_Advance_Top/DPHY_TX_INST/u_oserx4x8/U5_OSER16_0/D9 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | U3_CLKDIV | ||||
0.000 | 0.000 | tCL | RR | 30 | LEFTSIDE[0] | U3_CLKDIV/CLKOUT |
0.722 | 0.722 | tNET | RR | 1 | IOT23[A] | u_MIPI_TX_Advance_Top/DPHY_TX_INST/u_oserx4x8/U5_OSER16_0/PCLK |
0.805 | 0.083 | tHld | 1 | IOT23[A] | u_MIPI_TX_Advance_Top/DPHY_TX_INST/u_oserx4x8/U5_OSER16_0 |
Path Statistics:
Clock Skew | -0.002 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.724, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.191, 57.015%; tC2Q: 0.144, 42.985% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.722, 100.000% |
Path15
Path Summary:
Slack | 0.258 |
Data Arrival Time | 1.063 |
Data Required Time | 0.805 |
From | dout1_13_s0 |
To | u_MIPI_TX_Advance_Top/DPHY_TX_INST/u_oserx4x8/U5_OSER16_0 |
Launch Clk | U3_CLKDIV:[R] |
Latch Clk | U3_CLKDIV:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | U3_CLKDIV | ||||
0.000 | 0.000 | tCL | RR | 30 | LEFTSIDE[0] | U3_CLKDIV/CLKOUT |
0.724 | 0.724 | tNET | RR | 1 | R2C23[2][B] | dout1_13_s0/CLK |
0.868 | 0.144 | tC2Q | RR | 8 | R2C23[2][B] | dout1_13_s0/Q |
1.063 | 0.195 | tNET | RR | 1 | IOT23[A] | u_MIPI_TX_Advance_Top/DPHY_TX_INST/u_oserx4x8/U5_OSER16_0/D13 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | U3_CLKDIV | ||||
0.000 | 0.000 | tCL | RR | 30 | LEFTSIDE[0] | U3_CLKDIV/CLKOUT |
0.722 | 0.722 | tNET | RR | 1 | IOT23[A] | u_MIPI_TX_Advance_Top/DPHY_TX_INST/u_oserx4x8/U5_OSER16_0/PCLK |
0.805 | 0.083 | tHld | 1 | IOT23[A] | u_MIPI_TX_Advance_Top/DPHY_TX_INST/u_oserx4x8/U5_OSER16_0 |
Path Statistics:
Clock Skew | -0.002 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.724, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.195, 57.522%; tC2Q: 0.144, 42.478% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.722, 100.000% |
Path16
Path Summary:
Slack | 0.275 |
Data Arrival Time | 2.830 |
Data Required Time | 2.555 |
From | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_14_s3 |
To | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_14_s3 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | tck_pad_i:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
0.675 | 0.675 | tINS | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
1.351 | 0.675 | tINS | RR | 292 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
2.530 | 1.179 | tNET | RR | 1 | R25C55[1][A] | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_14_s3/CLK |
2.671 | 0.141 | tC2Q | RF | 2 | R25C55[1][A] | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_14_s3/Q |
2.677 | 0.006 | tNET | FF | 1 | R25C55[1][A] | gw_gao_inst_0/u_la0_top/u_ao_crc32/n99_s4/I2 |
2.830 | 0.153 | tINS | FF | 1 | R25C55[1][A] | gw_gao_inst_0/u_la0_top/u_ao_crc32/n99_s4/F |
2.830 | 0.000 | tNET | FF | 1 | R25C55[1][A] | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_14_s3/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
0.675 | 0.675 | tINS | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
1.351 | 0.675 | tINS | RR | 292 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
2.530 | 1.179 | tNET | RR | 1 | R25C55[1][A] | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_14_s3/CLK |
2.555 | 0.025 | tHld | 1 | R25C55[1][A] | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_14_s3 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.351, 53.399%; route: 1.179, 46.601% |
Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
Required Clock Path Delay | cell: 1.351, 53.399%; route: 1.179, 46.601% |
Path17
Path Summary:
Slack | 0.275 |
Data Arrival Time | 2.809 |
Data Required Time | 2.534 |
From | gw_gao_inst_0/u_la0_top/word_count_11_s0 |
To | gw_gao_inst_0/u_la0_top/word_count_11_s0 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | tck_pad_i:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
0.675 | 0.675 | tINS | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
1.351 | 0.675 | tINS | RR | 292 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
2.509 | 1.158 | tNET | RR | 1 | R32C55[1][A] | gw_gao_inst_0/u_la0_top/word_count_11_s0/CLK |
2.650 | 0.141 | tC2Q | RF | 2 | R32C55[1][A] | gw_gao_inst_0/u_la0_top/word_count_11_s0/Q |
2.656 | 0.006 | tNET | FF | 1 | R32C55[1][A] | gw_gao_inst_0/u_la0_top/data_to_word_counter_11_s0/I1 |
2.809 | 0.153 | tINS | FF | 1 | R32C55[1][A] | gw_gao_inst_0/u_la0_top/data_to_word_counter_11_s0/F |
2.809 | 0.000 | tNET | FF | 1 | R32C55[1][A] | gw_gao_inst_0/u_la0_top/word_count_11_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
0.675 | 0.675 | tINS | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
1.351 | 0.675 | tINS | RR | 292 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
2.509 | 1.158 | tNET | RR | 1 | R32C55[1][A] | gw_gao_inst_0/u_la0_top/word_count_11_s0/CLK |
2.534 | 0.025 | tHld | 1 | R32C55[1][A] | gw_gao_inst_0/u_la0_top/word_count_11_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.351, 53.846%; route: 1.158, 46.154% |
Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
Required Clock Path Delay | cell: 1.351, 53.846%; route: 1.158, 46.154% |
Path18
Path Summary:
Slack | 0.275 |
Data Arrival Time | 1.007 |
Data Required Time | 0.732 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1 |
Launch Clk | Inst3_CLKDIV_OUT:[R] |
Latch Clk | Inst3_CLKDIV_OUT:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
0.000 | 0.000 | tCL | RR | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.707 | 0.707 | tNET | RR | 1 | R25C40[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/CLK |
0.848 | 0.141 | tC2Q | RF | 3 | R25C40[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/Q |
0.854 | 0.006 | tNET | FF | 1 | R25C40[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n344_s0/I1 |
1.007 | 0.153 | tINS | FF | 1 | R25C40[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n344_s0/F |
1.007 | 0.000 | tNET | FF | 1 | R25C40[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
0.000 | 0.000 | tCL | RR | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.707 | 0.707 | tNET | RR | 1 | R25C40[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/CLK |
0.732 | 0.025 | tHld | 1 | R25C40[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.707, 100.000% |
Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.707, 100.000% |
Path19
Path Summary:
Slack | 0.275 |
Data Arrival Time | 1.002 |
Data Required Time | 0.727 |
From | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/lane1_cnt_2_s0 |
To | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/lane1_cnt_2_s0 |
Launch Clk | Inst3_CLKDIV_OUT:[R] |
Latch Clk | Inst3_CLKDIV_OUT:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
0.000 | 0.000 | tCL | RR | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.702 | 0.702 | tNET | RR | 1 | R18C54[0][A] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/lane1_cnt_2_s0/CLK |
0.843 | 0.141 | tC2Q | RF | 4 | R18C54[0][A] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/lane1_cnt_2_s0/Q |
0.849 | 0.006 | tNET | FF | 1 | R18C54[0][A] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/n135_s0/I2 |
1.002 | 0.153 | tINS | FF | 1 | R18C54[0][A] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/n135_s0/F |
1.002 | 0.000 | tNET | FF | 1 | R18C54[0][A] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/lane1_cnt_2_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
0.000 | 0.000 | tCL | RR | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.702 | 0.702 | tNET | RR | 1 | R18C54[0][A] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/lane1_cnt_2_s0/CLK |
0.727 | 0.025 | tHld | 1 | R18C54[0][A] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/lane1_cnt_2_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.702, 100.000% |
Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.702, 100.000% |
Path20
Path Summary:
Slack | 0.275 |
Data Arrival Time | 0.990 |
Data Required Time | 0.715 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1 |
Launch Clk | Inst3_CLKDIV_OUT:[R] |
Latch Clk | Inst3_CLKDIV_OUT:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
0.000 | 0.000 | tCL | RR | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.690 | 0.690 | tNET | RR | 1 | R32C41[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK |
0.831 | 0.141 | tC2Q | RF | 27 | R32C41[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/Q |
0.837 | 0.006 | tNET | FF | 1 | R32C41[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n468_s1/I1 |
0.990 | 0.153 | tINS | FF | 1 | R32C41[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n468_s1/F |
0.990 | 0.000 | tNET | FF | 1 | R32C41[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
0.000 | 0.000 | tCL | RR | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.690 | 0.690 | tNET | RR | 1 | R32C41[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK |
0.715 | 0.025 | tHld | 1 | R32C41[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.690, 100.000% |
Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.690, 100.000% |
Path21
Path Summary:
Slack | 0.275 |
Data Arrival Time | 0.990 |
Data Required Time | 0.715 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_12_s1 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_12_s1 |
Launch Clk | Inst3_CLKDIV_OUT:[R] |
Latch Clk | Inst3_CLKDIV_OUT:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
0.000 | 0.000 | tCL | RR | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.690 | 0.690 | tNET | RR | 1 | R31C42[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_12_s1/CLK |
0.831 | 0.141 | tC2Q | RF | 24 | R31C42[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_12_s1/Q |
0.837 | 0.006 | tNET | FF | 1 | R31C42[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n457_s2/I1 |
0.990 | 0.153 | tINS | FF | 1 | R31C42[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n457_s2/F |
0.990 | 0.000 | tNET | FF | 1 | R31C42[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_12_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
0.000 | 0.000 | tCL | RR | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.690 | 0.690 | tNET | RR | 1 | R31C42[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_12_s1/CLK |
0.715 | 0.025 | tHld | 1 | R31C42[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_12_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.690, 100.000% |
Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.690, 100.000% |
Path22
Path Summary:
Slack | 0.275 |
Data Arrival Time | 2.821 |
Data Required Time | 2.546 |
From | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_31_s3 |
To | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_31_s3 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | tck_pad_i:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
0.675 | 0.675 | tINS | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
1.351 | 0.675 | tINS | RR | 292 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
2.521 | 1.170 | tNET | RR | 1 | R26C54[0][A] | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_31_s3/CLK |
2.662 | 0.141 | tC2Q | RF | 2 | R26C54[0][A] | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_31_s3/Q |
2.668 | 0.006 | tNET | FF | 1 | R26C54[0][A] | gw_gao_inst_0/u_la0_top/u_ao_crc32/n82_s5/I2 |
2.821 | 0.153 | tINS | FF | 1 | R26C54[0][A] | gw_gao_inst_0/u_la0_top/u_ao_crc32/n82_s5/F |
2.821 | 0.000 | tNET | FF | 1 | R26C54[0][A] | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_31_s3/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
0.675 | 0.675 | tINS | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
1.351 | 0.675 | tINS | RR | 292 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
2.521 | 1.170 | tNET | RR | 1 | R26C54[0][A] | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_31_s3/CLK |
2.546 | 0.025 | tHld | 1 | R26C54[0][A] | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_31_s3 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.351, 53.590%; route: 1.170, 46.410% |
Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
Required Clock Path Delay | cell: 1.351, 53.590%; route: 1.170, 46.410% |
Path23
Path Summary:
Slack | 0.275 |
Data Arrival Time | 2.821 |
Data Required Time | 2.546 |
From | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_1_s3 |
To | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_1_s3 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | tck_pad_i:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
0.675 | 0.675 | tINS | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
1.351 | 0.675 | tINS | RR | 292 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
2.521 | 1.170 | tNET | RR | 1 | R26C54[1][A] | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_1_s3/CLK |
2.662 | 0.141 | tC2Q | RF | 2 | R26C54[1][A] | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_1_s3/Q |
2.668 | 0.006 | tNET | FF | 1 | R26C54[1][A] | gw_gao_inst_0/u_la0_top/u_ao_crc32/n112_s4/I3 |
2.821 | 0.153 | tINS | FF | 1 | R26C54[1][A] | gw_gao_inst_0/u_la0_top/u_ao_crc32/n112_s4/F |
2.821 | 0.000 | tNET | FF | 1 | R26C54[1][A] | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_1_s3/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
0.675 | 0.675 | tINS | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
1.351 | 0.675 | tINS | RR | 292 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
2.521 | 1.170 | tNET | RR | 1 | R26C54[1][A] | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_1_s3/CLK |
2.546 | 0.025 | tHld | 1 | R26C54[1][A] | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_1_s3 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.351, 53.590%; route: 1.170, 46.410% |
Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
Required Clock Path Delay | cell: 1.351, 53.590%; route: 1.170, 46.410% |
Path24
Path Summary:
Slack | 0.275 |
Data Arrival Time | 2.834 |
Data Required Time | 2.559 |
From | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_4_s3 |
To | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_4_s3 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | tck_pad_i:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
0.675 | 0.675 | tINS | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
1.351 | 0.675 | tINS | RR | 292 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
2.534 | 1.183 | tNET | RR | 1 | R25C56[0][A] | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_4_s3/CLK |
2.675 | 0.141 | tC2Q | RF | 2 | R25C56[0][A] | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_4_s3/Q |
2.681 | 0.006 | tNET | FF | 1 | R25C56[0][A] | gw_gao_inst_0/u_la0_top/u_ao_crc32/n109_s4/I2 |
2.834 | 0.153 | tINS | FF | 1 | R25C56[0][A] | gw_gao_inst_0/u_la0_top/u_ao_crc32/n109_s4/F |
2.834 | 0.000 | tNET | FF | 1 | R25C56[0][A] | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_4_s3/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
0.675 | 0.675 | tINS | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
1.351 | 0.675 | tINS | RR | 292 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
2.534 | 1.183 | tNET | RR | 1 | R25C56[0][A] | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_4_s3/CLK |
2.559 | 0.025 | tHld | 1 | R25C56[0][A] | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_4_s3 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.351, 53.315%; route: 1.183, 46.685% |
Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
Required Clock Path Delay | cell: 1.351, 53.315%; route: 1.183, 46.685% |
Path25
Path Summary:
Slack | 0.275 |
Data Arrival Time | 2.820 |
Data Required Time | 2.545 |
From | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_6_s3 |
To | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_6_s3 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | tck_pad_i:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
0.675 | 0.675 | tINS | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
1.351 | 0.675 | tINS | RR | 292 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
2.520 | 1.169 | tNET | RR | 1 | R27C55[0][A] | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_6_s3/CLK |
2.661 | 0.141 | tC2Q | RF | 2 | R27C55[0][A] | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_6_s3/Q |
2.667 | 0.006 | tNET | FF | 1 | R27C55[0][A] | gw_gao_inst_0/u_la0_top/u_ao_crc32/n107_s4/I3 |
2.820 | 0.153 | tINS | FF | 1 | R27C55[0][A] | gw_gao_inst_0/u_la0_top/u_ao_crc32/n107_s4/F |
2.820 | 0.000 | tNET | FF | 1 | R27C55[0][A] | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_6_s3/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
0.675 | 0.675 | tINS | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
1.351 | 0.675 | tINS | RR | 292 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
2.520 | 1.169 | tNET | RR | 1 | R27C55[0][A] | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_6_s3/CLK |
2.545 | 0.025 | tHld | 1 | R27C55[0][A] | gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_6_s3 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.351, 53.611%; route: 1.169, 46.389% |
Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
Required Clock Path Delay | cell: 1.351, 53.611%; route: 1.169, 46.389% |
Recovery Analysis Report
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 6.062 |
Data Arrival Time | 122.933 |
Data Required Time | 128.995 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_end_tck_1_s0 |
Launch Clk | Inst3_CLKDIV_OUT:[F] |
Latch Clk | tck_pad_i:[F] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
120.000 | 120.000 | active clock edge time | ||||
120.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
120.000 | 0.000 | tCL | FF | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
121.930 | 1.930 | tNET | FF | 1 | R26C48[1][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
122.373 | 0.442 | tC2Q | FF | 63 | R26C48[1][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
122.933 | 0.560 | tNET | FF | 1 | R25C50[3][A] | gw_gao_inst_0/u_la0_top/capture_end_tck_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
125.000 | 125.000 | active clock edge time | ||||
125.000 | 0.000 | tck_pad_i | ||||
125.000 | 0.000 | tCL | FF | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
125.688 | 0.688 | tINS | FF | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
125.688 | 0.000 | tNET | FF | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
126.375 | 0.688 | tINS | FF | 292 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
129.322 | 2.947 | tNET | FF | 1 | R25C50[3][A] | gw_gao_inst_0/u_la0_top/capture_end_tck_1_s0/CLK |
129.287 | -0.035 | tUnc | gw_gao_inst_0/u_la0_top/capture_end_tck_1_s0 | |||
128.995 | -0.292 | tSu | 1 | R25C50[3][A] | gw_gao_inst_0/u_la0_top/capture_end_tck_1_s0 |
Path Statistics:
Clock Skew | 2.392 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.930, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.560, 55.860%; tC2Q: 0.442, 44.140% |
Required Clock Path Delay | cell: 1.375, 31.810%; route: 2.947, 68.190% |
Path2
Path Summary:
Slack | 6.072 |
Data Arrival Time | 122.933 |
Data Required Time | 129.004 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0 |
Launch Clk | Inst3_CLKDIV_OUT:[F] |
Latch Clk | tck_pad_i:[F] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
120.000 | 120.000 | active clock edge time | ||||
120.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
120.000 | 0.000 | tCL | FF | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
121.930 | 1.930 | tNET | FF | 1 | R26C48[1][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
122.373 | 0.442 | tC2Q | FF | 63 | R26C48[1][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
122.933 | 0.560 | tNET | FF | 1 | R25C49[3][A] | gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
125.000 | 125.000 | active clock edge time | ||||
125.000 | 0.000 | tck_pad_i | ||||
125.000 | 0.000 | tCL | FF | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
125.688 | 0.688 | tINS | FF | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
125.688 | 0.000 | tNET | FF | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
126.375 | 0.688 | tINS | FF | 292 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
129.332 | 2.957 | tNET | FF | 1 | R25C49[3][A] | gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0/CLK |
129.297 | -0.035 | tUnc | gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0 | |||
129.004 | -0.292 | tSu | 1 | R25C49[3][A] | gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0 |
Path Statistics:
Clock Skew | 2.402 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.930, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.560, 55.860%; tC2Q: 0.442, 44.140% |
Required Clock Path Delay | cell: 1.375, 31.741%; route: 2.957, 68.259% |
Path3
Path Summary:
Slack | 6.072 |
Data Arrival Time | 122.933 |
Data Required Time | 129.004 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_end_tck_2_s0 |
Launch Clk | Inst3_CLKDIV_OUT:[F] |
Latch Clk | tck_pad_i:[F] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
120.000 | 120.000 | active clock edge time | ||||
120.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
120.000 | 0.000 | tCL | FF | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
121.930 | 1.930 | tNET | FF | 1 | R26C48[1][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
122.373 | 0.442 | tC2Q | FF | 63 | R26C48[1][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
122.933 | 0.560 | tNET | FF | 1 | R25C49[0][A] | gw_gao_inst_0/u_la0_top/capture_end_tck_2_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
125.000 | 125.000 | active clock edge time | ||||
125.000 | 0.000 | tck_pad_i | ||||
125.000 | 0.000 | tCL | FF | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
125.688 | 0.688 | tINS | FF | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
125.688 | 0.000 | tNET | FF | 1 | - | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
126.375 | 0.688 | tINS | FF | 292 | - | gw_gao_inst_0/u_gw_jtag/tck_o |
129.332 | 2.957 | tNET | FF | 1 | R25C49[0][A] | gw_gao_inst_0/u_la0_top/capture_end_tck_2_s0/CLK |
129.297 | -0.035 | tUnc | gw_gao_inst_0/u_la0_top/capture_end_tck_2_s0 | |||
129.004 | -0.292 | tSu | 1 | R25C49[0][A] | gw_gao_inst_0/u_la0_top/capture_end_tck_2_s0 |
Path Statistics:
Clock Skew | 2.402 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.930, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.560, 55.860%; tC2Q: 0.442, 44.140% |
Required Clock Path Delay | cell: 1.375, 31.741%; route: 2.957, 68.259% |
Path4
Path Summary:
Slack | 36.361 |
Data Arrival Time | 45.204 |
Data Required Time | 81.565 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1 |
Launch Clk | Inst3_CLKDIV_OUT:[F] |
Latch Clk | Inst3_CLKDIV_OUT:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.000 | 40.000 | active clock edge time | ||||
40.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
40.000 | 0.000 | tCL | FF | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
41.930 | 1.930 | tNET | FF | 1 | R26C48[1][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
42.373 | 0.442 | tC2Q | FF | 63 | R26C48[1][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
45.204 | 2.831 | tNET | FF | 1 | R29C40[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
80.000 | 80.000 | active clock edge time | ||||
80.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
80.000 | 0.000 | tCL | RR | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
81.912 | 1.912 | tNET | RR | 1 | R29C40[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLK |
81.565 | -0.347 | tSu | 1 | R29C40[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1 |
Path Statistics:
Clock Skew | -0.018 |
Setup Relationship | 40.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.930, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.831, 86.483%; tC2Q: 0.442, 13.517% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.912, 100.000% |
Path5
Path Summary:
Slack | 36.412 |
Data Arrival Time | 45.192 |
Data Required Time | 81.603 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1 |
Launch Clk | Inst3_CLKDIV_OUT:[F] |
Latch Clk | Inst3_CLKDIV_OUT:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.000 | 40.000 | active clock edge time | ||||
40.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
40.000 | 0.000 | tCL | FF | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
41.930 | 1.930 | tNET | FF | 1 | R26C48[1][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
42.373 | 0.442 | tC2Q | FF | 63 | R26C48[1][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
45.192 | 2.819 | tNET | FF | 1 | R25C43[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
80.000 | 80.000 | active clock edge time | ||||
80.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
80.000 | 0.000 | tCL | RR | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
81.951 | 1.951 | tNET | RR | 1 | R25C43[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLK |
81.603 | -0.347 | tSu | 1 | R25C43[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1 |
Path Statistics:
Clock Skew | 0.020 |
Setup Relationship | 40.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.930, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.819, 86.432%; tC2Q: 0.442, 13.568% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.951, 100.000% |
Path6
Path Summary:
Slack | 36.412 |
Data Arrival Time | 45.192 |
Data Required Time | 81.603 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1 |
Launch Clk | Inst3_CLKDIV_OUT:[F] |
Latch Clk | Inst3_CLKDIV_OUT:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.000 | 40.000 | active clock edge time | ||||
40.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
40.000 | 0.000 | tCL | FF | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
41.930 | 1.930 | tNET | FF | 1 | R26C48[1][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
42.373 | 0.442 | tC2Q | FF | 63 | R26C48[1][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
45.192 | 2.819 | tNET | FF | 1 | R25C43[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
80.000 | 80.000 | active clock edge time | ||||
80.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
80.000 | 0.000 | tCL | RR | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
81.951 | 1.951 | tNET | RR | 1 | R25C43[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLK |
81.603 | -0.347 | tSu | 1 | R25C43[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1 |
Path Statistics:
Clock Skew | 0.020 |
Setup Relationship | 40.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.930, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.819, 86.432%; tC2Q: 0.442, 13.568% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.951, 100.000% |
Path7
Path Summary:
Slack | 36.599 |
Data Arrival Time | 44.999 |
Data Required Time | 81.598 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5 |
Launch Clk | Inst3_CLKDIV_OUT:[F] |
Latch Clk | Inst3_CLKDIV_OUT:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.000 | 40.000 | active clock edge time | ||||
40.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
40.000 | 0.000 | tCL | FF | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
41.930 | 1.930 | tNET | FF | 1 | R26C48[1][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
42.373 | 0.442 | tC2Q | FF | 63 | R26C48[1][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
44.999 | 2.626 | tNET | FF | 1 | R27C42[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
80.000 | 80.000 | active clock edge time | ||||
80.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
80.000 | 0.000 | tCL | RR | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
81.946 | 1.946 | tNET | RR | 1 | R27C42[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/CLK |
81.598 | -0.347 | tSu | 1 | R27C42[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5 |
Path Statistics:
Clock Skew | 0.015 |
Setup Relationship | 40.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.930, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.626, 85.580%; tC2Q: 0.442, 14.420% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.946, 100.000% |
Path8
Path Summary:
Slack | 37.015 |
Data Arrival Time | 44.559 |
Data Required Time | 81.574 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1 |
Launch Clk | Inst3_CLKDIV_OUT:[F] |
Latch Clk | Inst3_CLKDIV_OUT:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.000 | 40.000 | active clock edge time | ||||
40.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
40.000 | 0.000 | tCL | FF | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
41.930 | 1.930 | tNET | FF | 1 | R26C48[1][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
42.373 | 0.442 | tC2Q | FF | 63 | R26C48[1][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
44.559 | 2.186 | tNET | FF | 1 | R29C43[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
80.000 | 80.000 | active clock edge time | ||||
80.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
80.000 | 0.000 | tCL | RR | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
81.922 | 1.922 | tNET | RR | 1 | R29C43[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK |
81.574 | -0.347 | tSu | 1 | R29C43[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1 |
Path Statistics:
Clock Skew | -0.008 |
Setup Relationship | 40.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.930, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.186, 83.167%; tC2Q: 0.442, 16.833% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.922, 100.000% |
Path9
Path Summary:
Slack | 37.426 |
Data Arrival Time | 44.132 |
Data Required Time | 81.558 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1 |
Launch Clk | Inst3_CLKDIV_OUT:[F] |
Latch Clk | Inst3_CLKDIV_OUT:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.000 | 40.000 | active clock edge time | ||||
40.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
40.000 | 0.000 | tCL | FF | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
41.930 | 1.930 | tNET | FF | 1 | R26C48[1][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
42.373 | 0.442 | tC2Q | FF | 63 | R26C48[1][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
44.132 | 1.759 | tNET | FF | 1 | R30C41[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
80.000 | 80.000 | active clock edge time | ||||
80.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
80.000 | 0.000 | tCL | RR | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
81.905 | 1.905 | tNET | RR | 1 | R30C41[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK |
81.558 | -0.347 | tSu | 1 | R30C41[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1 |
Path Statistics:
Clock Skew | -0.025 |
Setup Relationship | 40.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.930, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.759, 79.898%; tC2Q: 0.442, 20.102% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.905, 100.000% |
Path10
Path Summary:
Slack | 37.426 |
Data Arrival Time | 44.132 |
Data Required Time | 81.558 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1 |
Launch Clk | Inst3_CLKDIV_OUT:[F] |
Latch Clk | Inst3_CLKDIV_OUT:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.000 | 40.000 | active clock edge time | ||||
40.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
40.000 | 0.000 | tCL | FF | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
41.930 | 1.930 | tNET | FF | 1 | R26C48[1][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
42.373 | 0.442 | tC2Q | FF | 63 | R26C48[1][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
44.132 | 1.759 | tNET | FF | 1 | R30C41[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
80.000 | 80.000 | active clock edge time | ||||
80.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
80.000 | 0.000 | tCL | RR | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
81.905 | 1.905 | tNET | RR | 1 | R30C41[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK |
81.558 | -0.347 | tSu | 1 | R30C41[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1 |
Path Statistics:
Clock Skew | -0.025 |
Setup Relationship | 40.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.930, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.759, 79.898%; tC2Q: 0.442, 20.102% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.905, 100.000% |
Path11
Path Summary:
Slack | 37.602 |
Data Arrival Time | 43.968 |
Data Required Time | 81.570 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1 |
Launch Clk | Inst3_CLKDIV_OUT:[F] |
Latch Clk | Inst3_CLKDIV_OUT:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.000 | 40.000 | active clock edge time | ||||
40.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
40.000 | 0.000 | tCL | FF | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
41.930 | 1.930 | tNET | FF | 1 | R26C48[1][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
42.373 | 0.442 | tC2Q | FF | 63 | R26C48[1][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
43.968 | 1.595 | tNET | FF | 1 | R32C51[3][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
80.000 | 80.000 | active clock edge time | ||||
80.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
80.000 | 0.000 | tCL | RR | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
81.917 | 1.917 | tNET | RR | 1 | R32C51[3][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLK |
81.570 | -0.347 | tSu | 1 | R32C51[3][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1 |
Path Statistics:
Clock Skew | -0.013 |
Setup Relationship | 40.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.930, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.595, 78.282%; tC2Q: 0.442, 21.718% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.917, 100.000% |
Path12
Path Summary:
Slack | 37.602 |
Data Arrival Time | 43.968 |
Data Required Time | 81.570 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1 |
Launch Clk | Inst3_CLKDIV_OUT:[F] |
Latch Clk | Inst3_CLKDIV_OUT:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.000 | 40.000 | active clock edge time | ||||
40.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
40.000 | 0.000 | tCL | FF | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
41.930 | 1.930 | tNET | FF | 1 | R26C48[1][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
42.373 | 0.442 | tC2Q | FF | 63 | R26C48[1][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
43.968 | 1.595 | tNET | FF | 1 | R32C51[2][B] | gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
80.000 | 80.000 | active clock edge time | ||||
80.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
80.000 | 0.000 | tCL | RR | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
81.917 | 1.917 | tNET | RR | 1 | R32C51[2][B] | gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLK |
81.570 | -0.347 | tSu | 1 | R32C51[2][B] | gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1 |
Path Statistics:
Clock Skew | -0.013 |
Setup Relationship | 40.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.930, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.595, 78.282%; tC2Q: 0.442, 21.718% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.917, 100.000% |
Path13
Path Summary:
Slack | 37.631 |
Data Arrival Time | 43.939 |
Data Required Time | 81.570 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1 |
Launch Clk | Inst3_CLKDIV_OUT:[F] |
Latch Clk | Inst3_CLKDIV_OUT:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.000 | 40.000 | active clock edge time | ||||
40.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
40.000 | 0.000 | tCL | FF | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
41.930 | 1.930 | tNET | FF | 1 | R26C48[1][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
42.373 | 0.442 | tC2Q | FF | 63 | R26C48[1][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
43.939 | 1.566 | tNET | FF | 1 | R32C41[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
80.000 | 80.000 | active clock edge time | ||||
80.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
80.000 | 0.000 | tCL | RR | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
81.917 | 1.917 | tNET | RR | 1 | R32C41[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK |
81.570 | -0.347 | tSu | 1 | R32C41[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1 |
Path Statistics:
Clock Skew | -0.013 |
Setup Relationship | 40.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.930, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.566, 77.971%; tC2Q: 0.442, 22.029% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.917, 100.000% |
Path14
Path Summary:
Slack | 37.631 |
Data Arrival Time | 43.939 |
Data Required Time | 81.570 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1 |
Launch Clk | Inst3_CLKDIV_OUT:[F] |
Latch Clk | Inst3_CLKDIV_OUT:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.000 | 40.000 | active clock edge time | ||||
40.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
40.000 | 0.000 | tCL | FF | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
41.930 | 1.930 | tNET | FF | 1 | R26C48[1][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
42.373 | 0.442 | tC2Q | FF | 63 | R26C48[1][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
43.939 | 1.566 | tNET | FF | 1 | R32C41[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
80.000 | 80.000 | active clock edge time | ||||
80.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
80.000 | 0.000 | tCL | RR | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
81.917 | 1.917 | tNET | RR | 1 | R32C41[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK |
81.570 | -0.347 | tSu | 1 | R32C41[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1 |
Path Statistics:
Clock Skew | -0.013 |
Setup Relationship | 40.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.930, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.566, 77.971%; tC2Q: 0.442, 22.029% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.917, 100.000% |
Path15
Path Summary:
Slack | 37.631 |
Data Arrival Time | 43.939 |
Data Required Time | 81.570 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1 |
Launch Clk | Inst3_CLKDIV_OUT:[F] |
Latch Clk | Inst3_CLKDIV_OUT:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.000 | 40.000 | active clock edge time | ||||
40.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
40.000 | 0.000 | tCL | FF | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
41.930 | 1.930 | tNET | FF | 1 | R26C48[1][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
42.373 | 0.442 | tC2Q | FF | 63 | R26C48[1][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
43.939 | 1.566 | tNET | FF | 1 | R32C41[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
80.000 | 80.000 | active clock edge time | ||||
80.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
80.000 | 0.000 | tCL | RR | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
81.917 | 1.917 | tNET | RR | 1 | R32C41[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK |
81.570 | -0.347 | tSu | 1 | R32C41[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1 |
Path Statistics:
Clock Skew | -0.013 |
Setup Relationship | 40.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.930, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.566, 77.971%; tC2Q: 0.442, 22.029% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.917, 100.000% |
Path16
Path Summary:
Slack | 37.640 |
Data Arrival Time | 43.939 |
Data Required Time | 81.579 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1 |
Launch Clk | Inst3_CLKDIV_OUT:[F] |
Latch Clk | Inst3_CLKDIV_OUT:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.000 | 40.000 | active clock edge time | ||||
40.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
40.000 | 0.000 | tCL | FF | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
41.930 | 1.930 | tNET | FF | 1 | R26C48[1][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
42.373 | 0.442 | tC2Q | FF | 63 | R26C48[1][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
43.939 | 1.566 | tNET | FF | 1 | R32C42[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
80.000 | 80.000 | active clock edge time | ||||
80.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
80.000 | 0.000 | tCL | RR | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
81.927 | 1.927 | tNET | RR | 1 | R32C42[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK |
81.579 | -0.347 | tSu | 1 | R32C42[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1 |
Path Statistics:
Clock Skew | -0.004 |
Setup Relationship | 40.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.930, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.566, 77.971%; tC2Q: 0.442, 22.029% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.927, 100.000% |
Path17
Path Summary:
Slack | 37.640 |
Data Arrival Time | 43.939 |
Data Required Time | 81.579 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1 |
Launch Clk | Inst3_CLKDIV_OUT:[F] |
Latch Clk | Inst3_CLKDIV_OUT:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.000 | 40.000 | active clock edge time | ||||
40.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
40.000 | 0.000 | tCL | FF | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
41.930 | 1.930 | tNET | FF | 1 | R26C48[1][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
42.373 | 0.442 | tC2Q | FF | 63 | R26C48[1][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
43.939 | 1.566 | tNET | FF | 1 | R32C42[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
80.000 | 80.000 | active clock edge time | ||||
80.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
80.000 | 0.000 | tCL | RR | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
81.927 | 1.927 | tNET | RR | 1 | R32C42[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK |
81.579 | -0.347 | tSu | 1 | R32C42[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1 |
Path Statistics:
Clock Skew | -0.004 |
Setup Relationship | 40.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.930, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.566, 77.971%; tC2Q: 0.442, 22.029% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.927, 100.000% |
Path18
Path Summary:
Slack | 37.640 |
Data Arrival Time | 43.939 |
Data Required Time | 81.579 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1 |
Launch Clk | Inst3_CLKDIV_OUT:[F] |
Latch Clk | Inst3_CLKDIV_OUT:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.000 | 40.000 | active clock edge time | ||||
40.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
40.000 | 0.000 | tCL | FF | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
41.930 | 1.930 | tNET | FF | 1 | R26C48[1][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
42.373 | 0.442 | tC2Q | FF | 63 | R26C48[1][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
43.939 | 1.566 | tNET | FF | 1 | R32C42[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
80.000 | 80.000 | active clock edge time | ||||
80.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
80.000 | 0.000 | tCL | RR | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
81.927 | 1.927 | tNET | RR | 1 | R32C42[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/CLK |
81.579 | -0.347 | tSu | 1 | R32C42[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1 |
Path Statistics:
Clock Skew | -0.004 |
Setup Relationship | 40.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.930, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.566, 77.971%; tC2Q: 0.442, 22.029% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.927, 100.000% |
Path19
Path Summary:
Slack | 37.640 |
Data Arrival Time | 43.939 |
Data Required Time | 81.579 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_end_dly_s0 |
Launch Clk | Inst3_CLKDIV_OUT:[F] |
Latch Clk | Inst3_CLKDIV_OUT:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.000 | 40.000 | active clock edge time | ||||
40.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
40.000 | 0.000 | tCL | FF | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
41.930 | 1.930 | tNET | FF | 1 | R26C48[1][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
42.373 | 0.442 | tC2Q | FF | 63 | R26C48[1][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
43.939 | 1.566 | tNET | FF | 1 | R32C42[1][A] | gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
80.000 | 80.000 | active clock edge time | ||||
80.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
80.000 | 0.000 | tCL | RR | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
81.927 | 1.927 | tNET | RR | 1 | R32C42[1][A] | gw_gao_inst_0/u_la0_top/capture_end_dly_s0/CLK |
81.579 | -0.347 | tSu | 1 | R32C42[1][A] | gw_gao_inst_0/u_la0_top/capture_end_dly_s0 |
Path Statistics:
Clock Skew | -0.004 |
Setup Relationship | 40.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.930, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.566, 77.971%; tC2Q: 0.442, 22.029% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.927, 100.000% |
Path20
Path Summary:
Slack | 37.650 |
Data Arrival Time | 43.914 |
Data Required Time | 81.564 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1 |
Launch Clk | Inst3_CLKDIV_OUT:[F] |
Latch Clk | Inst3_CLKDIV_OUT:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.000 | 40.000 | active clock edge time | ||||
40.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
40.000 | 0.000 | tCL | FF | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
41.930 | 1.930 | tNET | FF | 1 | R26C48[1][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
42.373 | 0.442 | tC2Q | FF | 63 | R26C48[1][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
43.914 | 1.541 | tNET | FF | 1 | R31C41[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
80.000 | 80.000 | active clock edge time | ||||
80.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
80.000 | 0.000 | tCL | RR | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
81.911 | 1.911 | tNET | RR | 1 | R31C41[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK |
81.564 | -0.347 | tSu | 1 | R31C41[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1 |
Path Statistics:
Clock Skew | -0.019 |
Setup Relationship | 40.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.930, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.541, 77.694%; tC2Q: 0.442, 22.306% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.911, 100.000% |
Path21
Path Summary:
Slack | 37.659 |
Data Arrival Time | 43.914 |
Data Required Time | 81.573 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1 |
Launch Clk | Inst3_CLKDIV_OUT:[F] |
Latch Clk | Inst3_CLKDIV_OUT:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.000 | 40.000 | active clock edge time | ||||
40.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
40.000 | 0.000 | tCL | FF | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
41.930 | 1.930 | tNET | FF | 1 | R26C48[1][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
42.373 | 0.442 | tC2Q | FF | 63 | R26C48[1][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
43.914 | 1.541 | tNET | FF | 1 | R31C42[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
80.000 | 80.000 | active clock edge time | ||||
80.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
80.000 | 0.000 | tCL | RR | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
81.921 | 1.921 | tNET | RR | 1 | R31C42[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK |
81.573 | -0.347 | tSu | 1 | R31C42[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1 |
Path Statistics:
Clock Skew | -0.010 |
Setup Relationship | 40.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.930, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.541, 77.694%; tC2Q: 0.442, 22.306% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.921, 100.000% |
Path22
Path Summary:
Slack | 37.659 |
Data Arrival Time | 43.914 |
Data Required Time | 81.573 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1 |
Launch Clk | Inst3_CLKDIV_OUT:[F] |
Latch Clk | Inst3_CLKDIV_OUT:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.000 | 40.000 | active clock edge time | ||||
40.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
40.000 | 0.000 | tCL | FF | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
41.930 | 1.930 | tNET | FF | 1 | R26C48[1][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
42.373 | 0.442 | tC2Q | FF | 63 | R26C48[1][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
43.914 | 1.541 | tNET | FF | 1 | R31C42[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
80.000 | 80.000 | active clock edge time | ||||
80.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
80.000 | 0.000 | tCL | RR | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
81.921 | 1.921 | tNET | RR | 1 | R31C42[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK |
81.573 | -0.347 | tSu | 1 | R31C42[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1 |
Path Statistics:
Clock Skew | -0.010 |
Setup Relationship | 40.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.930, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.541, 77.694%; tC2Q: 0.442, 22.306% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.921, 100.000% |
Path23
Path Summary:
Slack | 37.659 |
Data Arrival Time | 43.914 |
Data Required Time | 81.573 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_11_s1 |
Launch Clk | Inst3_CLKDIV_OUT:[F] |
Latch Clk | Inst3_CLKDIV_OUT:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.000 | 40.000 | active clock edge time | ||||
40.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
40.000 | 0.000 | tCL | FF | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
41.930 | 1.930 | tNET | FF | 1 | R26C48[1][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
42.373 | 0.442 | tC2Q | FF | 63 | R26C48[1][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
43.914 | 1.541 | tNET | FF | 1 | R31C42[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_11_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
80.000 | 80.000 | active clock edge time | ||||
80.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
80.000 | 0.000 | tCL | RR | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
81.921 | 1.921 | tNET | RR | 1 | R31C42[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_11_s1/CLK |
81.573 | -0.347 | tSu | 1 | R31C42[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_11_s1 |
Path Statistics:
Clock Skew | -0.010 |
Setup Relationship | 40.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.930, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.541, 77.694%; tC2Q: 0.442, 22.306% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.921, 100.000% |
Path24
Path Summary:
Slack | 37.659 |
Data Arrival Time | 43.914 |
Data Required Time | 81.573 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_12_s1 |
Launch Clk | Inst3_CLKDIV_OUT:[F] |
Latch Clk | Inst3_CLKDIV_OUT:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.000 | 40.000 | active clock edge time | ||||
40.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
40.000 | 0.000 | tCL | FF | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
41.930 | 1.930 | tNET | FF | 1 | R26C48[1][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
42.373 | 0.442 | tC2Q | FF | 63 | R26C48[1][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
43.914 | 1.541 | tNET | FF | 1 | R31C42[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_12_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
80.000 | 80.000 | active clock edge time | ||||
80.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
80.000 | 0.000 | tCL | RR | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
81.921 | 1.921 | tNET | RR | 1 | R31C42[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_12_s1/CLK |
81.573 | -0.347 | tSu | 1 | R31C42[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_12_s1 |
Path Statistics:
Clock Skew | -0.010 |
Setup Relationship | 40.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.930, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.541, 77.694%; tC2Q: 0.442, 22.306% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.921, 100.000% |
Path25
Path Summary:
Slack | 37.787 |
Data Arrival Time | 43.817 |
Data Required Time | 81.603 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1 |
Launch Clk | Inst3_CLKDIV_OUT:[F] |
Latch Clk | Inst3_CLKDIV_OUT:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.000 | 40.000 | active clock edge time | ||||
40.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
40.000 | 0.000 | tCL | FF | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
41.930 | 1.930 | tNET | FF | 1 | R26C48[1][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
42.373 | 0.442 | tC2Q | FF | 63 | R26C48[1][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
43.817 | 1.444 | tNET | FF | 1 | R25C37[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
80.000 | 80.000 | active clock edge time | ||||
80.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
80.000 | 0.000 | tCL | RR | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
81.951 | 1.951 | tNET | RR | 1 | R25C37[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLK |
81.603 | -0.347 | tSu | 1 | R25C37[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1 |
Path Statistics:
Clock Skew | 0.020 |
Setup Relationship | 40.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.930, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.444, 76.541%; tC2Q: 0.442, 23.459% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.951, 100.000% |
Removal Analysis Report
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 1.798 |
Data Arrival Time | 2.475 |
Data Required Time | 0.677 |
From | hactive_flag_s2 |
To | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_3_s0 |
Launch Clk | U3_CLKDIV:[R] |
Latch Clk | Inst3_CLKDIV_OUT:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | U3_CLKDIV | ||||
0.000 | 0.000 | tCL | RR | 30 | LEFTSIDE[0] | U3_CLKDIV/CLKOUT |
0.695 | 0.695 | tNET | RR | 1 | R29C35[1][A] | hactive_flag_s2/CLK |
0.839 | 0.144 | tC2Q | RR | 23 | R29C35[1][A] | hactive_flag_s2/Q |
1.730 | 0.891 | tNET | RR | 1 | R17C38[3][B] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n38_s1/I0 |
1.878 | 0.148 | tINS | RR | 737 | R17C38[3][B] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n38_s1/F |
2.475 | 0.597 | tNET | RR | 1 | R11C54[0][B] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_3_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
0.000 | 0.000 | tCL | RR | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.695 | 0.695 | tNET | RR | 1 | R11C54[0][B] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_3_s0/CLK |
0.730 | 0.035 | tUnc | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_3_s0 | |||
0.677 | -0.053 | tHld | 1 | R11C54[0][B] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_3_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.695, 100.000% |
Arrival Data Path Delay | cell: 0.148, 8.315%; route: 1.488, 83.596%; tC2Q: 0.144, 8.090% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.695, 100.000% |
Path2
Path Summary:
Slack | 1.798 |
Data Arrival Time | 2.475 |
Data Required Time | 0.677 |
From | hactive_flag_s2 |
To | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_2_s0 |
Launch Clk | U3_CLKDIV:[R] |
Latch Clk | Inst3_CLKDIV_OUT:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | U3_CLKDIV | ||||
0.000 | 0.000 | tCL | RR | 30 | LEFTSIDE[0] | U3_CLKDIV/CLKOUT |
0.695 | 0.695 | tNET | RR | 1 | R29C35[1][A] | hactive_flag_s2/CLK |
0.839 | 0.144 | tC2Q | RR | 23 | R29C35[1][A] | hactive_flag_s2/Q |
1.730 | 0.891 | tNET | RR | 1 | R17C38[3][B] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n38_s1/I0 |
1.878 | 0.148 | tINS | RR | 737 | R17C38[3][B] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n38_s1/F |
2.475 | 0.597 | tNET | RR | 1 | R11C42[3][A] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_2_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
0.000 | 0.000 | tCL | RR | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.695 | 0.695 | tNET | RR | 1 | R11C42[3][A] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_2_s0/CLK |
0.730 | 0.035 | tUnc | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_2_s0 | |||
0.677 | -0.053 | tHld | 1 | R11C42[3][A] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_2_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.695, 100.000% |
Arrival Data Path Delay | cell: 0.148, 8.315%; route: 1.488, 83.596%; tC2Q: 0.144, 8.090% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.695, 100.000% |
Path3
Path Summary:
Slack | 1.798 |
Data Arrival Time | 2.475 |
Data Required Time | 0.677 |
From | hactive_flag_s2 |
To | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_0_s0 |
Launch Clk | U3_CLKDIV:[R] |
Latch Clk | Inst3_CLKDIV_OUT:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | U3_CLKDIV | ||||
0.000 | 0.000 | tCL | RR | 30 | LEFTSIDE[0] | U3_CLKDIV/CLKOUT |
0.695 | 0.695 | tNET | RR | 1 | R29C35[1][A] | hactive_flag_s2/CLK |
0.839 | 0.144 | tC2Q | RR | 23 | R29C35[1][A] | hactive_flag_s2/Q |
1.730 | 0.891 | tNET | RR | 1 | R17C38[3][B] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n38_s1/I0 |
1.878 | 0.148 | tINS | RR | 737 | R17C38[3][B] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n38_s1/F |
2.475 | 0.597 | tNET | RR | 1 | R11C42[1][A] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
0.000 | 0.000 | tCL | RR | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.695 | 0.695 | tNET | RR | 1 | R11C42[1][A] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_0_s0/CLK |
0.730 | 0.035 | tUnc | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_0_s0 | |||
0.677 | -0.053 | tHld | 1 | R11C42[1][A] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.695, 100.000% |
Arrival Data Path Delay | cell: 0.148, 8.315%; route: 1.488, 83.596%; tC2Q: 0.144, 8.090% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.695, 100.000% |
Path4
Path Summary:
Slack | 1.802 |
Data Arrival Time | 2.475 |
Data Required Time | 0.673 |
From | hactive_flag_s2 |
To | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/q_in2_1_8_s0 |
Launch Clk | U3_CLKDIV:[R] |
Latch Clk | Inst3_CLKDIV_OUT:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | U3_CLKDIV | ||||
0.000 | 0.000 | tCL | RR | 30 | LEFTSIDE[0] | U3_CLKDIV/CLKOUT |
0.695 | 0.695 | tNET | RR | 1 | R29C35[1][A] | hactive_flag_s2/CLK |
0.839 | 0.144 | tC2Q | RR | 23 | R29C35[1][A] | hactive_flag_s2/Q |
1.730 | 0.891 | tNET | RR | 1 | R17C38[3][B] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n38_s1/I0 |
1.878 | 0.148 | tINS | RR | 737 | R17C38[3][B] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n38_s1/F |
2.475 | 0.597 | tNET | RR | 1 | R11C51[1][A] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/q_in2_1_8_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
0.000 | 0.000 | tCL | RR | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.691 | 0.691 | tNET | RR | 1 | R11C51[1][A] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/q_in2_1_8_s0/CLK |
0.726 | 0.035 | tUnc | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/q_in2_1_8_s0 | |||
0.673 | -0.053 | tHld | 1 | R11C51[1][A] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/q_in2_1_8_s0 |
Path Statistics:
Clock Skew | -0.004 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.695, 100.000% |
Arrival Data Path Delay | cell: 0.148, 8.315%; route: 1.488, 83.596%; tC2Q: 0.144, 8.090% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.691, 100.000% |
Path5
Path Summary:
Slack | 1.802 |
Data Arrival Time | 2.494 |
Data Required Time | 0.692 |
From | hactive_flag_s2 |
To | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/q_in2_0_1_s0 |
Launch Clk | U3_CLKDIV:[R] |
Latch Clk | Inst3_CLKDIV_OUT:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | U3_CLKDIV | ||||
0.000 | 0.000 | tCL | RR | 30 | LEFTSIDE[0] | U3_CLKDIV/CLKOUT |
0.695 | 0.695 | tNET | RR | 1 | R29C35[1][A] | hactive_flag_s2/CLK |
0.839 | 0.144 | tC2Q | RR | 23 | R29C35[1][A] | hactive_flag_s2/Q |
1.730 | 0.891 | tNET | RR | 1 | R17C38[3][B] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n38_s1/I0 |
1.878 | 0.148 | tINS | RR | 737 | R17C38[3][B] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n38_s1/F |
2.494 | 0.616 | tNET | RR | 1 | R8C54[3][A] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/q_in2_0_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
0.000 | 0.000 | tCL | RR | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.710 | 0.710 | tNET | RR | 1 | R8C54[3][A] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/q_in2_0_1_s0/CLK |
0.745 | 0.035 | tUnc | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/q_in2_0_1_s0 | |||
0.692 | -0.053 | tHld | 1 | R8C54[3][A] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/q_in2_0_1_s0 |
Path Statistics:
Clock Skew | 0.015 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.695, 100.000% |
Arrival Data Path Delay | cell: 0.148, 8.227%; route: 1.507, 83.769%; tC2Q: 0.144, 8.004% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.710, 100.000% |
Path6
Path Summary:
Slack | 1.802 |
Data Arrival Time | 2.475 |
Data Required Time | 0.673 |
From | hactive_flag_s2 |
To | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/q_in2_0_11_s0 |
Launch Clk | U3_CLKDIV:[R] |
Latch Clk | Inst3_CLKDIV_OUT:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | U3_CLKDIV | ||||
0.000 | 0.000 | tCL | RR | 30 | LEFTSIDE[0] | U3_CLKDIV/CLKOUT |
0.695 | 0.695 | tNET | RR | 1 | R29C35[1][A] | hactive_flag_s2/CLK |
0.839 | 0.144 | tC2Q | RR | 23 | R29C35[1][A] | hactive_flag_s2/Q |
1.730 | 0.891 | tNET | RR | 1 | R17C38[3][B] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n38_s1/I0 |
1.878 | 0.148 | tINS | RR | 737 | R17C38[3][B] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n38_s1/F |
2.475 | 0.597 | tNET | RR | 1 | R11C51[0][B] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/q_in2_0_11_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
0.000 | 0.000 | tCL | RR | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.691 | 0.691 | tNET | RR | 1 | R11C51[0][B] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/q_in2_0_11_s0/CLK |
0.726 | 0.035 | tUnc | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/q_in2_0_11_s0 | |||
0.673 | -0.053 | tHld | 1 | R11C51[0][B] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/q_in2_0_11_s0 |
Path Statistics:
Clock Skew | -0.004 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.695, 100.000% |
Arrival Data Path Delay | cell: 0.148, 8.315%; route: 1.488, 83.596%; tC2Q: 0.144, 8.090% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.691, 100.000% |
Path7
Path Summary:
Slack | 1.802 |
Data Arrival Time | 2.475 |
Data Required Time | 0.673 |
From | hactive_flag_s2 |
To | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/q_in1_0_1_s0 |
Launch Clk | U3_CLKDIV:[R] |
Latch Clk | Inst3_CLKDIV_OUT:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | U3_CLKDIV | ||||
0.000 | 0.000 | tCL | RR | 30 | LEFTSIDE[0] | U3_CLKDIV/CLKOUT |
0.695 | 0.695 | tNET | RR | 1 | R29C35[1][A] | hactive_flag_s2/CLK |
0.839 | 0.144 | tC2Q | RR | 23 | R29C35[1][A] | hactive_flag_s2/Q |
1.730 | 0.891 | tNET | RR | 1 | R17C38[3][B] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n38_s1/I0 |
1.878 | 0.148 | tINS | RR | 737 | R17C38[3][B] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n38_s1/F |
2.475 | 0.597 | tNET | RR | 1 | R11C45[0][B] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/q_in1_0_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
0.000 | 0.000 | tCL | RR | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.691 | 0.691 | tNET | RR | 1 | R11C45[0][B] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/q_in1_0_1_s0/CLK |
0.726 | 0.035 | tUnc | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/q_in1_0_1_s0 | |||
0.673 | -0.053 | tHld | 1 | R11C45[0][B] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/q_in1_0_1_s0 |
Path Statistics:
Clock Skew | -0.004 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.695, 100.000% |
Arrival Data Path Delay | cell: 0.148, 8.315%; route: 1.488, 83.596%; tC2Q: 0.144, 8.090% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.691, 100.000% |
Path8
Path Summary:
Slack | 1.802 |
Data Arrival Time | 2.475 |
Data Required Time | 0.673 |
From | hactive_flag_s2 |
To | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/dout_13_s0 |
Launch Clk | U3_CLKDIV:[R] |
Latch Clk | Inst3_CLKDIV_OUT:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | U3_CLKDIV | ||||
0.000 | 0.000 | tCL | RR | 30 | LEFTSIDE[0] | U3_CLKDIV/CLKOUT |
0.695 | 0.695 | tNET | RR | 1 | R29C35[1][A] | hactive_flag_s2/CLK |
0.839 | 0.144 | tC2Q | RR | 23 | R29C35[1][A] | hactive_flag_s2/Q |
1.730 | 0.891 | tNET | RR | 1 | R17C38[3][B] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n38_s1/I0 |
1.878 | 0.148 | tINS | RR | 737 | R17C38[3][B] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n38_s1/F |
2.475 | 0.597 | tNET | RR | 1 | R11C53[1][A] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/dout_13_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
0.000 | 0.000 | tCL | RR | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.691 | 0.691 | tNET | RR | 1 | R11C53[1][A] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/dout_13_s0/CLK |
0.726 | 0.035 | tUnc | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/dout_13_s0 | |||
0.673 | -0.053 | tHld | 1 | R11C53[1][A] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/dout_13_s0 |
Path Statistics:
Clock Skew | -0.004 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.695, 100.000% |
Arrival Data Path Delay | cell: 0.148, 8.315%; route: 1.488, 83.596%; tC2Q: 0.144, 8.090% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.691, 100.000% |
Path9
Path Summary:
Slack | 1.802 |
Data Arrival Time | 2.494 |
Data Required Time | 0.692 |
From | hactive_flag_s2 |
To | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/dout_14_s0 |
Launch Clk | U3_CLKDIV:[R] |
Latch Clk | Inst3_CLKDIV_OUT:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | U3_CLKDIV | ||||
0.000 | 0.000 | tCL | RR | 30 | LEFTSIDE[0] | U3_CLKDIV/CLKOUT |
0.695 | 0.695 | tNET | RR | 1 | R29C35[1][A] | hactive_flag_s2/CLK |
0.839 | 0.144 | tC2Q | RR | 23 | R29C35[1][A] | hactive_flag_s2/Q |
1.730 | 0.891 | tNET | RR | 1 | R17C38[3][B] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n38_s1/I0 |
1.878 | 0.148 | tINS | RR | 737 | R17C38[3][B] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n38_s1/F |
2.494 | 0.616 | tNET | RR | 1 | R8C54[1][A] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/dout_14_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
0.000 | 0.000 | tCL | RR | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.710 | 0.710 | tNET | RR | 1 | R8C54[1][A] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/dout_14_s0/CLK |
0.745 | 0.035 | tUnc | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/dout_14_s0 | |||
0.692 | -0.053 | tHld | 1 | R8C54[1][A] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/dout_14_s0 |
Path Statistics:
Clock Skew | 0.015 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.695, 100.000% |
Arrival Data Path Delay | cell: 0.148, 8.227%; route: 1.507, 83.769%; tC2Q: 0.144, 8.004% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.710, 100.000% |
Path10
Path Summary:
Slack | 1.802 |
Data Arrival Time | 2.475 |
Data Required Time | 0.673 |
From | hactive_flag_s2 |
To | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_5_s0 |
Launch Clk | U3_CLKDIV:[R] |
Latch Clk | Inst3_CLKDIV_OUT:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | U3_CLKDIV | ||||
0.000 | 0.000 | tCL | RR | 30 | LEFTSIDE[0] | U3_CLKDIV/CLKOUT |
0.695 | 0.695 | tNET | RR | 1 | R29C35[1][A] | hactive_flag_s2/CLK |
0.839 | 0.144 | tC2Q | RR | 23 | R29C35[1][A] | hactive_flag_s2/Q |
1.730 | 0.891 | tNET | RR | 1 | R17C38[3][B] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n38_s1/I0 |
1.878 | 0.148 | tINS | RR | 737 | R17C38[3][B] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n38_s1/F |
2.475 | 0.597 | tNET | RR | 1 | R11C55[0][B] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_5_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
0.000 | 0.000 | tCL | RR | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.691 | 0.691 | tNET | RR | 1 | R11C55[0][B] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_5_s0/CLK |
0.726 | 0.035 | tUnc | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_5_s0 | |||
0.673 | -0.053 | tHld | 1 | R11C55[0][B] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_5_s0 |
Path Statistics:
Clock Skew | -0.004 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.695, 100.000% |
Arrival Data Path Delay | cell: 0.148, 8.315%; route: 1.488, 83.596%; tC2Q: 0.144, 8.090% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.691, 100.000% |
Path11
Path Summary:
Slack | 1.802 |
Data Arrival Time | 2.475 |
Data Required Time | 0.673 |
From | hactive_flag_s2 |
To | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_4_s0 |
Launch Clk | U3_CLKDIV:[R] |
Latch Clk | Inst3_CLKDIV_OUT:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | U3_CLKDIV | ||||
0.000 | 0.000 | tCL | RR | 30 | LEFTSIDE[0] | U3_CLKDIV/CLKOUT |
0.695 | 0.695 | tNET | RR | 1 | R29C35[1][A] | hactive_flag_s2/CLK |
0.839 | 0.144 | tC2Q | RR | 23 | R29C35[1][A] | hactive_flag_s2/Q |
1.730 | 0.891 | tNET | RR | 1 | R17C38[3][B] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n38_s1/I0 |
1.878 | 0.148 | tINS | RR | 737 | R17C38[3][B] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n38_s1/F |
2.475 | 0.597 | tNET | RR | 1 | R11C53[0][B] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_4_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
0.000 | 0.000 | tCL | RR | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.691 | 0.691 | tNET | RR | 1 | R11C53[0][B] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_4_s0/CLK |
0.726 | 0.035 | tUnc | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_4_s0 | |||
0.673 | -0.053 | tHld | 1 | R11C53[0][B] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_4_s0 |
Path Statistics:
Clock Skew | -0.004 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.695, 100.000% |
Arrival Data Path Delay | cell: 0.148, 8.315%; route: 1.488, 83.596%; tC2Q: 0.144, 8.090% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.691, 100.000% |
Path12
Path Summary:
Slack | 1.802 |
Data Arrival Time | 2.475 |
Data Required Time | 0.673 |
From | hactive_flag_s2 |
To | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_1_s0 |
Launch Clk | U3_CLKDIV:[R] |
Latch Clk | Inst3_CLKDIV_OUT:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | U3_CLKDIV | ||||
0.000 | 0.000 | tCL | RR | 30 | LEFTSIDE[0] | U3_CLKDIV/CLKOUT |
0.695 | 0.695 | tNET | RR | 1 | R29C35[1][A] | hactive_flag_s2/CLK |
0.839 | 0.144 | tC2Q | RR | 23 | R29C35[1][A] | hactive_flag_s2/Q |
1.730 | 0.891 | tNET | RR | 1 | R17C38[3][B] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n38_s1/I0 |
1.878 | 0.148 | tINS | RR | 737 | R17C38[3][B] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n38_s1/F |
2.475 | 0.597 | tNET | RR | 1 | R11C53[2][A] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
0.000 | 0.000 | tCL | RR | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.691 | 0.691 | tNET | RR | 1 | R11C53[2][A] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_1_s0/CLK |
0.726 | 0.035 | tUnc | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_1_s0 | |||
0.673 | -0.053 | tHld | 1 | R11C53[2][A] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_1_s0 |
Path Statistics:
Clock Skew | -0.004 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.695, 100.000% |
Arrival Data Path Delay | cell: 0.148, 8.315%; route: 1.488, 83.596%; tC2Q: 0.144, 8.090% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.691, 100.000% |
Path13
Path Summary:
Slack | 1.802 |
Data Arrival Time | 2.494 |
Data Required Time | 0.692 |
From | hactive_flag_s2 |
To | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/reg4_0_s0 |
Launch Clk | U3_CLKDIV:[R] |
Latch Clk | Inst3_CLKDIV_OUT:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | U3_CLKDIV | ||||
0.000 | 0.000 | tCL | RR | 30 | LEFTSIDE[0] | U3_CLKDIV/CLKOUT |
0.695 | 0.695 | tNET | RR | 1 | R29C35[1][A] | hactive_flag_s2/CLK |
0.839 | 0.144 | tC2Q | RR | 23 | R29C35[1][A] | hactive_flag_s2/Q |
1.730 | 0.891 | tNET | RR | 1 | R17C38[3][B] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n38_s1/I0 |
1.878 | 0.148 | tINS | RR | 737 | R17C38[3][B] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n38_s1/F |
2.494 | 0.616 | tNET | RR | 1 | R8C46[0][B] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/reg4_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
0.000 | 0.000 | tCL | RR | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.710 | 0.710 | tNET | RR | 1 | R8C46[0][B] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/reg4_0_s0/CLK |
0.745 | 0.035 | tUnc | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/reg4_0_s0 | |||
0.692 | -0.053 | tHld | 1 | R8C46[0][B] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/reg4_0_s0 |
Path Statistics:
Clock Skew | 0.015 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.695, 100.000% |
Arrival Data Path Delay | cell: 0.148, 8.227%; route: 1.507, 83.769%; tC2Q: 0.144, 8.004% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.710, 100.000% |
Path14
Path Summary:
Slack | 1.802 |
Data Arrival Time | 2.475 |
Data Required Time | 0.673 |
From | hactive_flag_s2 |
To | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/reg3_1_s0 |
Launch Clk | U3_CLKDIV:[R] |
Latch Clk | Inst3_CLKDIV_OUT:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | U3_CLKDIV | ||||
0.000 | 0.000 | tCL | RR | 30 | LEFTSIDE[0] | U3_CLKDIV/CLKOUT |
0.695 | 0.695 | tNET | RR | 1 | R29C35[1][A] | hactive_flag_s2/CLK |
0.839 | 0.144 | tC2Q | RR | 23 | R29C35[1][A] | hactive_flag_s2/Q |
1.730 | 0.891 | tNET | RR | 1 | R17C38[3][B] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n38_s1/I0 |
1.878 | 0.148 | tINS | RR | 737 | R17C38[3][B] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n38_s1/F |
2.475 | 0.597 | tNET | RR | 1 | R11C47[1][B] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/reg3_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
0.000 | 0.000 | tCL | RR | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.691 | 0.691 | tNET | RR | 1 | R11C47[1][B] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/reg3_1_s0/CLK |
0.726 | 0.035 | tUnc | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/reg3_1_s0 | |||
0.673 | -0.053 | tHld | 1 | R11C47[1][B] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/reg3_1_s0 |
Path Statistics:
Clock Skew | -0.004 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.695, 100.000% |
Arrival Data Path Delay | cell: 0.148, 8.315%; route: 1.488, 83.596%; tC2Q: 0.144, 8.090% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.691, 100.000% |
Path15
Path Summary:
Slack | 1.802 |
Data Arrival Time | 2.475 |
Data Required Time | 0.673 |
From | hactive_flag_s2 |
To | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/reg3_4_s0 |
Launch Clk | U3_CLKDIV:[R] |
Latch Clk | Inst3_CLKDIV_OUT:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | U3_CLKDIV | ||||
0.000 | 0.000 | tCL | RR | 30 | LEFTSIDE[0] | U3_CLKDIV/CLKOUT |
0.695 | 0.695 | tNET | RR | 1 | R29C35[1][A] | hactive_flag_s2/CLK |
0.839 | 0.144 | tC2Q | RR | 23 | R29C35[1][A] | hactive_flag_s2/Q |
1.730 | 0.891 | tNET | RR | 1 | R17C38[3][B] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n38_s1/I0 |
1.878 | 0.148 | tINS | RR | 737 | R17C38[3][B] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n38_s1/F |
2.475 | 0.597 | tNET | RR | 1 | R11C47[1][A] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/reg3_4_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
0.000 | 0.000 | tCL | RR | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.691 | 0.691 | tNET | RR | 1 | R11C47[1][A] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/reg3_4_s0/CLK |
0.726 | 0.035 | tUnc | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/reg3_4_s0 | |||
0.673 | -0.053 | tHld | 1 | R11C47[1][A] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/reg3_4_s0 |
Path Statistics:
Clock Skew | -0.004 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.695, 100.000% |
Arrival Data Path Delay | cell: 0.148, 8.315%; route: 1.488, 83.596%; tC2Q: 0.144, 8.090% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.691, 100.000% |
Path16
Path Summary:
Slack | 1.802 |
Data Arrival Time | 2.494 |
Data Required Time | 0.692 |
From | hactive_flag_s2 |
To | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/reg2_0_s0 |
Launch Clk | U3_CLKDIV:[R] |
Latch Clk | Inst3_CLKDIV_OUT:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | U3_CLKDIV | ||||
0.000 | 0.000 | tCL | RR | 30 | LEFTSIDE[0] | U3_CLKDIV/CLKOUT |
0.695 | 0.695 | tNET | RR | 1 | R29C35[1][A] | hactive_flag_s2/CLK |
0.839 | 0.144 | tC2Q | RR | 23 | R29C35[1][A] | hactive_flag_s2/Q |
1.730 | 0.891 | tNET | RR | 1 | R17C38[3][B] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n38_s1/I0 |
1.878 | 0.148 | tINS | RR | 737 | R17C38[3][B] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n38_s1/F |
2.494 | 0.616 | tNET | RR | 1 | R8C46[3][A] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/reg2_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
0.000 | 0.000 | tCL | RR | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.710 | 0.710 | tNET | RR | 1 | R8C46[3][A] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/reg2_0_s0/CLK |
0.745 | 0.035 | tUnc | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/reg2_0_s0 | |||
0.692 | -0.053 | tHld | 1 | R8C46[3][A] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/reg2_0_s0 |
Path Statistics:
Clock Skew | 0.015 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.695, 100.000% |
Arrival Data Path Delay | cell: 0.148, 8.227%; route: 1.507, 83.769%; tC2Q: 0.144, 8.004% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.710, 100.000% |
Path17
Path Summary:
Slack | 1.802 |
Data Arrival Time | 2.494 |
Data Required Time | 0.692 |
From | hactive_flag_s2 |
To | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/reg1_4_s0 |
Launch Clk | U3_CLKDIV:[R] |
Latch Clk | Inst3_CLKDIV_OUT:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | U3_CLKDIV | ||||
0.000 | 0.000 | tCL | RR | 30 | LEFTSIDE[0] | U3_CLKDIV/CLKOUT |
0.695 | 0.695 | tNET | RR | 1 | R29C35[1][A] | hactive_flag_s2/CLK |
0.839 | 0.144 | tC2Q | RR | 23 | R29C35[1][A] | hactive_flag_s2/Q |
1.730 | 0.891 | tNET | RR | 1 | R17C38[3][B] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n38_s1/I0 |
1.878 | 0.148 | tINS | RR | 737 | R17C38[3][B] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n38_s1/F |
2.494 | 0.616 | tNET | RR | 1 | R8C46[2][A] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/reg1_4_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
0.000 | 0.000 | tCL | RR | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.710 | 0.710 | tNET | RR | 1 | R8C46[2][A] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/reg1_4_s0/CLK |
0.745 | 0.035 | tUnc | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/reg1_4_s0 | |||
0.692 | -0.053 | tHld | 1 | R8C46[2][A] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/reg1_4_s0 |
Path Statistics:
Clock Skew | 0.015 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.695, 100.000% |
Arrival Data Path Delay | cell: 0.148, 8.227%; route: 1.507, 83.769%; tC2Q: 0.144, 8.004% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.710, 100.000% |
Path18
Path Summary:
Slack | 1.802 |
Data Arrival Time | 2.494 |
Data Required Time | 0.692 |
From | hactive_flag_s2 |
To | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/reg0_3_s0 |
Launch Clk | U3_CLKDIV:[R] |
Latch Clk | Inst3_CLKDIV_OUT:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | U3_CLKDIV | ||||
0.000 | 0.000 | tCL | RR | 30 | LEFTSIDE[0] | U3_CLKDIV/CLKOUT |
0.695 | 0.695 | tNET | RR | 1 | R29C35[1][A] | hactive_flag_s2/CLK |
0.839 | 0.144 | tC2Q | RR | 23 | R29C35[1][A] | hactive_flag_s2/Q |
1.730 | 0.891 | tNET | RR | 1 | R17C38[3][B] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n38_s1/I0 |
1.878 | 0.148 | tINS | RR | 737 | R17C38[3][B] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n38_s1/F |
2.494 | 0.616 | tNET | RR | 1 | R8C46[2][B] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/reg0_3_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
0.000 | 0.000 | tCL | RR | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.710 | 0.710 | tNET | RR | 1 | R8C46[2][B] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/reg0_3_s0/CLK |
0.745 | 0.035 | tUnc | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/reg0_3_s0 | |||
0.692 | -0.053 | tHld | 1 | R8C46[2][B] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/reg0_3_s0 |
Path Statistics:
Clock Skew | 0.015 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.695, 100.000% |
Arrival Data Path Delay | cell: 0.148, 8.227%; route: 1.507, 83.769%; tC2Q: 0.144, 8.004% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.710, 100.000% |
Path19
Path Summary:
Slack | 1.802 |
Data Arrival Time | 2.475 |
Data Required Time | 0.673 |
From | hactive_flag_s2 |
To | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/dout_3_s0 |
Launch Clk | U3_CLKDIV:[R] |
Latch Clk | Inst3_CLKDIV_OUT:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | U3_CLKDIV | ||||
0.000 | 0.000 | tCL | RR | 30 | LEFTSIDE[0] | U3_CLKDIV/CLKOUT |
0.695 | 0.695 | tNET | RR | 1 | R29C35[1][A] | hactive_flag_s2/CLK |
0.839 | 0.144 | tC2Q | RR | 23 | R29C35[1][A] | hactive_flag_s2/Q |
1.730 | 0.891 | tNET | RR | 1 | R17C38[3][B] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n38_s1/I0 |
1.878 | 0.148 | tINS | RR | 737 | R17C38[3][B] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n38_s1/F |
2.475 | 0.597 | tNET | RR | 1 | R11C35[1][B] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/dout_3_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
0.000 | 0.000 | tCL | RR | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.691 | 0.691 | tNET | RR | 1 | R11C35[1][B] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/dout_3_s0/CLK |
0.726 | 0.035 | tUnc | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/dout_3_s0 | |||
0.673 | -0.053 | tHld | 1 | R11C35[1][B] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/dout_3_s0 |
Path Statistics:
Clock Skew | -0.004 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.695, 100.000% |
Arrival Data Path Delay | cell: 0.148, 8.315%; route: 1.488, 83.596%; tC2Q: 0.144, 8.090% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.691, 100.000% |
Path20
Path Summary:
Slack | 1.802 |
Data Arrival Time | 2.475 |
Data Required Time | 0.673 |
From | hactive_flag_s2 |
To | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/dout_14_s0 |
Launch Clk | U3_CLKDIV:[R] |
Latch Clk | Inst3_CLKDIV_OUT:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | U3_CLKDIV | ||||
0.000 | 0.000 | tCL | RR | 30 | LEFTSIDE[0] | U3_CLKDIV/CLKOUT |
0.695 | 0.695 | tNET | RR | 1 | R29C35[1][A] | hactive_flag_s2/CLK |
0.839 | 0.144 | tC2Q | RR | 23 | R29C35[1][A] | hactive_flag_s2/Q |
1.730 | 0.891 | tNET | RR | 1 | R17C38[3][B] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n38_s1/I0 |
1.878 | 0.148 | tINS | RR | 737 | R17C38[3][B] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n38_s1/F |
2.475 | 0.597 | tNET | RR | 1 | R11C45[0][A] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/dout_14_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
0.000 | 0.000 | tCL | RR | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.691 | 0.691 | tNET | RR | 1 | R11C45[0][A] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/dout_14_s0/CLK |
0.726 | 0.035 | tUnc | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/dout_14_s0 | |||
0.673 | -0.053 | tHld | 1 | R11C45[0][A] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/dout_14_s0 |
Path Statistics:
Clock Skew | -0.004 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.695, 100.000% |
Arrival Data Path Delay | cell: 0.148, 8.315%; route: 1.488, 83.596%; tC2Q: 0.144, 8.090% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.691, 100.000% |
Path21
Path Summary:
Slack | 1.802 |
Data Arrival Time | 2.494 |
Data Required Time | 0.692 |
From | hactive_flag_s2 |
To | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_15_s0 |
Launch Clk | U3_CLKDIV:[R] |
Latch Clk | Inst3_CLKDIV_OUT:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | U3_CLKDIV | ||||
0.000 | 0.000 | tCL | RR | 30 | LEFTSIDE[0] | U3_CLKDIV/CLKOUT |
0.695 | 0.695 | tNET | RR | 1 | R29C35[1][A] | hactive_flag_s2/CLK |
0.839 | 0.144 | tC2Q | RR | 23 | R29C35[1][A] | hactive_flag_s2/Q |
1.730 | 0.891 | tNET | RR | 1 | R17C38[3][B] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n38_s1/I0 |
1.878 | 0.148 | tINS | RR | 737 | R17C38[3][B] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n38_s1/F |
2.494 | 0.616 | tNET | RR | 1 | R8C34[1][A] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_15_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
0.000 | 0.000 | tCL | RR | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.710 | 0.710 | tNET | RR | 1 | R8C34[1][A] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_15_s0/CLK |
0.745 | 0.035 | tUnc | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_15_s0 | |||
0.692 | -0.053 | tHld | 1 | R8C34[1][A] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_15_s0 |
Path Statistics:
Clock Skew | 0.015 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.695, 100.000% |
Arrival Data Path Delay | cell: 0.148, 8.227%; route: 1.507, 83.769%; tC2Q: 0.144, 8.004% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.710, 100.000% |
Path22
Path Summary:
Slack | 1.802 |
Data Arrival Time | 2.494 |
Data Required Time | 0.692 |
From | hactive_flag_s2 |
To | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_13_s0 |
Launch Clk | U3_CLKDIV:[R] |
Latch Clk | Inst3_CLKDIV_OUT:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | U3_CLKDIV | ||||
0.000 | 0.000 | tCL | RR | 30 | LEFTSIDE[0] | U3_CLKDIV/CLKOUT |
0.695 | 0.695 | tNET | RR | 1 | R29C35[1][A] | hactive_flag_s2/CLK |
0.839 | 0.144 | tC2Q | RR | 23 | R29C35[1][A] | hactive_flag_s2/Q |
1.730 | 0.891 | tNET | RR | 1 | R17C38[3][B] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n38_s1/I0 |
1.878 | 0.148 | tINS | RR | 737 | R17C38[3][B] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n38_s1/F |
2.494 | 0.616 | tNET | RR | 1 | R8C34[2][A] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_13_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
0.000 | 0.000 | tCL | RR | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.710 | 0.710 | tNET | RR | 1 | R8C34[2][A] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_13_s0/CLK |
0.745 | 0.035 | tUnc | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_13_s0 | |||
0.692 | -0.053 | tHld | 1 | R8C34[2][A] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_13_s0 |
Path Statistics:
Clock Skew | 0.015 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.695, 100.000% |
Arrival Data Path Delay | cell: 0.148, 8.227%; route: 1.507, 83.769%; tC2Q: 0.144, 8.004% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.710, 100.000% |
Path23
Path Summary:
Slack | 1.802 |
Data Arrival Time | 2.494 |
Data Required Time | 0.692 |
From | hactive_flag_s2 |
To | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_11_s0 |
Launch Clk | U3_CLKDIV:[R] |
Latch Clk | Inst3_CLKDIV_OUT:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | U3_CLKDIV | ||||
0.000 | 0.000 | tCL | RR | 30 | LEFTSIDE[0] | U3_CLKDIV/CLKOUT |
0.695 | 0.695 | tNET | RR | 1 | R29C35[1][A] | hactive_flag_s2/CLK |
0.839 | 0.144 | tC2Q | RR | 23 | R29C35[1][A] | hactive_flag_s2/Q |
1.730 | 0.891 | tNET | RR | 1 | R17C38[3][B] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n38_s1/I0 |
1.878 | 0.148 | tINS | RR | 737 | R17C38[3][B] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n38_s1/F |
2.494 | 0.616 | tNET | RR | 1 | R8C34[0][B] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_11_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
0.000 | 0.000 | tCL | RR | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.710 | 0.710 | tNET | RR | 1 | R8C34[0][B] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_11_s0/CLK |
0.745 | 0.035 | tUnc | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_11_s0 | |||
0.692 | -0.053 | tHld | 1 | R8C34[0][B] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_11_s0 |
Path Statistics:
Clock Skew | 0.015 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.695, 100.000% |
Arrival Data Path Delay | cell: 0.148, 8.227%; route: 1.507, 83.769%; tC2Q: 0.144, 8.004% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.710, 100.000% |
Path24
Path Summary:
Slack | 1.802 |
Data Arrival Time | 2.475 |
Data Required Time | 0.673 |
From | hactive_flag_s2 |
To | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_7_s0 |
Launch Clk | U3_CLKDIV:[R] |
Latch Clk | Inst3_CLKDIV_OUT:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | U3_CLKDIV | ||||
0.000 | 0.000 | tCL | RR | 30 | LEFTSIDE[0] | U3_CLKDIV/CLKOUT |
0.695 | 0.695 | tNET | RR | 1 | R29C35[1][A] | hactive_flag_s2/CLK |
0.839 | 0.144 | tC2Q | RR | 23 | R29C35[1][A] | hactive_flag_s2/Q |
1.730 | 0.891 | tNET | RR | 1 | R17C38[3][B] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n38_s1/I0 |
1.878 | 0.148 | tINS | RR | 737 | R17C38[3][B] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n38_s1/F |
2.475 | 0.597 | tNET | RR | 1 | R11C39[1][A] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_7_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
0.000 | 0.000 | tCL | RR | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.691 | 0.691 | tNET | RR | 1 | R11C39[1][A] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_7_s0/CLK |
0.726 | 0.035 | tUnc | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_7_s0 | |||
0.673 | -0.053 | tHld | 1 | R11C39[1][A] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_7_s0 |
Path Statistics:
Clock Skew | -0.004 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.695, 100.000% |
Arrival Data Path Delay | cell: 0.148, 8.315%; route: 1.488, 83.596%; tC2Q: 0.144, 8.090% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.691, 100.000% |
Path25
Path Summary:
Slack | 1.802 |
Data Arrival Time | 2.489 |
Data Required Time | 0.687 |
From | hactive_flag_s2 |
To | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/q_in2_1_12_s0 |
Launch Clk | U3_CLKDIV:[R] |
Latch Clk | Inst3_CLKDIV_OUT:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | U3_CLKDIV | ||||
0.000 | 0.000 | tCL | RR | 30 | LEFTSIDE[0] | U3_CLKDIV/CLKOUT |
0.695 | 0.695 | tNET | RR | 1 | R29C35[1][A] | hactive_flag_s2/CLK |
0.839 | 0.144 | tC2Q | RR | 23 | R29C35[1][A] | hactive_flag_s2/Q |
1.730 | 0.891 | tNET | RR | 1 | R17C38[3][B] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n38_s1/I0 |
1.878 | 0.148 | tINS | RR | 737 | R17C38[3][B] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n38_s1/F |
2.489 | 0.611 | tNET | RR | 1 | R9C50[1][B] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/q_in2_1_12_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Inst3_CLKDIV_OUT | ||||
0.000 | 0.000 | tCL | RR | 985 | LEFTSIDE[2] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
0.705 | 0.705 | tNET | RR | 1 | R9C50[1][B] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/q_in2_1_12_s0/CLK |
0.740 | 0.035 | tUnc | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/q_in2_1_12_s0 | |||
0.687 | -0.053 | tHld | 1 | R9C50[1][B] | MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/q_in2_1_12_s0 |
Path Statistics:
Clock Skew | 0.010 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.695, 100.000% |
Arrival Data Path Delay | cell: 0.148, 8.250%; route: 1.502, 83.724%; tC2Q: 0.144, 8.027% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.705, 100.000% |
Minimum Pulse Width Report:
Report Command:report_min_pulse_width -nworst 10 -detail
MPW1
MPW Summary:
Slack: | 3.503 |
Actual Width: | 3.753 |
Required Width: | 0.250 |
Type: | Low Pulse Width |
Clock: | HS_CLK |
Objects: | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_2_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | HS_CLK | ||
5.000 | 0.000 | tCL | FF | MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/OH |
6.966 | 1.966 | tNET | FF | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_2_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | HS_CLK | ||
10.000 | 0.000 | tCL | RR | MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/OH |
10.719 | 0.719 | tNET | RR | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_2_s0/CLK |
MPW2
MPW Summary:
Slack: | 3.503 |
Actual Width: | 3.753 |
Required Width: | 0.250 |
Type: | Low Pulse Width |
Clock: | HS_CLK |
Objects: | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | HS_CLK | ||
5.000 | 0.000 | tCL | FF | MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/OH |
6.966 | 1.966 | tNET | FF | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | HS_CLK | ||
10.000 | 0.000 | tCL | RR | MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/OH |
10.719 | 0.719 | tNET | RR | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0/CLK |
MPW3
MPW Summary:
Slack: | 3.503 |
Actual Width: | 3.753 |
Required Width: | 0.250 |
Type: | Low Pulse Width |
Clock: | HS_CLK |
Objects: | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | HS_CLK | ||
5.000 | 0.000 | tCL | FF | MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/OH |
6.966 | 1.966 | tNET | FF | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | HS_CLK | ||
10.000 | 0.000 | tCL | RR | MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/OH |
10.719 | 0.719 | tNET | RR | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/CLK |
MPW4
MPW Summary:
Slack: | 3.503 |
Actual Width: | 3.753 |
Required Width: | 0.250 |
Type: | Low Pulse Width |
Clock: | HS_CLK |
Objects: | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | HS_CLK | ||
5.000 | 0.000 | tCL | FF | MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/OH |
6.966 | 1.966 | tNET | FF | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | HS_CLK | ||
10.000 | 0.000 | tCL | RR | MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/OH |
10.719 | 0.719 | tNET | RR | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0/CLK |
MPW5
MPW Summary:
Slack: | 3.503 |
Actual Width: | 3.753 |
Required Width: | 0.250 |
Type: | High Pulse Width |
Clock: | HS_CLK |
Objects: | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_2_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||
0.000 | 0.000 | HS_CLK | ||
0.000 | 0.000 | tCL | RR | MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/OH |
1.969 | 1.969 | tNET | RR | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_2_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | HS_CLK | ||
5.000 | 0.000 | tCL | FF | MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/OH |
5.722 | 0.722 | tNET | FF | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_2_s0/CLK |
MPW6
MPW Summary:
Slack: | 3.503 |
Actual Width: | 3.753 |
Required Width: | 0.250 |
Type: | High Pulse Width |
Clock: | HS_CLK |
Objects: | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||
0.000 | 0.000 | HS_CLK | ||
0.000 | 0.000 | tCL | RR | MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/OH |
1.969 | 1.969 | tNET | RR | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | HS_CLK | ||
5.000 | 0.000 | tCL | FF | MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/OH |
5.722 | 0.722 | tNET | FF | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0/CLK |
MPW7
MPW Summary:
Slack: | 3.503 |
Actual Width: | 3.753 |
Required Width: | 0.250 |
Type: | High Pulse Width |
Clock: | HS_CLK |
Objects: | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||
0.000 | 0.000 | HS_CLK | ||
0.000 | 0.000 | tCL | RR | MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/OH |
1.969 | 1.969 | tNET | RR | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | HS_CLK | ||
5.000 | 0.000 | tCL | FF | MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/OH |
5.722 | 0.722 | tNET | FF | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/CLK |
MPW8
MPW Summary:
Slack: | 3.503 |
Actual Width: | 3.753 |
Required Width: | 0.250 |
Type: | High Pulse Width |
Clock: | HS_CLK |
Objects: | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||
0.000 | 0.000 | HS_CLK | ||
0.000 | 0.000 | tCL | RR | MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/OH |
1.969 | 1.969 | tNET | RR | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | HS_CLK | ||
5.000 | 0.000 | tCL | FF | MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/OH |
5.722 | 0.722 | tNET | FF | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0/CLK |
MPW9
MPW Summary:
Slack: | 22.193 |
Actual Width: | 23.193 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | tck_pad_i |
Objects: | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_14_s |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
25.000 | 0.000 | active clock edge time | ||
25.000 | 0.000 | tck_pad_i | ||
25.000 | 0.000 | tCL | FF | gw_gao_inst_0/tck_ibuf/I |
25.688 | 0.688 | tINS | FF | gw_gao_inst_0/tck_ibuf/O |
25.688 | 0.000 | tNET | FF | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
26.375 | 0.688 | tINS | FF | gw_gao_inst_0/u_gw_jtag/tck_o |
29.329 | 2.954 | tNET | FF | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_14_s/CLKB |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
50.000 | 0.000 | active clock edge time | ||
50.000 | 0.000 | tck_pad_i | ||
50.000 | 0.000 | tCL | RR | gw_gao_inst_0/tck_ibuf/I |
50.675 | 0.675 | tINS | RR | gw_gao_inst_0/tck_ibuf/O |
50.675 | 0.000 | tNET | RR | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
51.351 | 0.675 | tINS | RR | gw_gao_inst_0/u_gw_jtag/tck_o |
52.522 | 1.172 | tNET | RR | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_14_s/CLKB |
MPW10
MPW Summary:
Slack: | 22.193 |
Actual Width: | 23.193 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | tck_pad_i |
Objects: | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_15_s |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
25.000 | 0.000 | active clock edge time | ||
25.000 | 0.000 | tck_pad_i | ||
25.000 | 0.000 | tCL | FF | gw_gao_inst_0/tck_ibuf/I |
25.688 | 0.688 | tINS | FF | gw_gao_inst_0/tck_ibuf/O |
25.688 | 0.000 | tNET | FF | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
26.375 | 0.688 | tINS | FF | gw_gao_inst_0/u_gw_jtag/tck_o |
29.329 | 2.954 | tNET | FF | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_15_s/CLKB |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
50.000 | 0.000 | active clock edge time | ||
50.000 | 0.000 | tck_pad_i | ||
50.000 | 0.000 | tCL | RR | gw_gao_inst_0/tck_ibuf/I |
50.675 | 0.675 | tINS | RR | gw_gao_inst_0/tck_ibuf/O |
50.675 | 0.000 | tNET | RR | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
51.351 | 0.675 | tINS | RR | gw_gao_inst_0/u_gw_jtag/tck_o |
52.522 | 1.172 | tNET | RR | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_15_s/CLKB |
High Fanout Nets Report:
Report Command:report_high_fanout_nets -max_nets 10
FANOUT | NET NAME | WORST SLACK | MAX DELAY |
---|---|---|---|
985 | clk_byte_out | 3.902 | 1.974 |
737 | n38_5 | 75.403 | 1.585 |
292 | control0[0] | 0.730 | 3.010 |
77 | ready_d | 76.822 | 3.396 |
64 | n20_3 | 43.727 | 3.361 |
63 | rst_ao | 6.062 | 3.196 |
44 | n1051_4 | 42.673 | 2.399 |
43 | n1051_5 | 44.035 | 2.175 |
43 | data_out_shift_reg_41_7 | 44.035 | 1.780 |
37 | op_reg_en | 43.381 | 1.226 |
Route Congestions Report:
Report Command:report_route_congestion -max_grids 10
GRID LOC | ROUTE CONGESTIONS |
---|---|
R18C36 | 59.72% |
R18C35 | 52.78% |
R28C41 | 51.39% |
R10C41 | 50.00% |
R27C46 | 48.61% |
R28C42 | 48.61% |
R27C48 | 48.61% |
R9C42 | 48.61% |
R9C53 | 47.22% |
R17C45 | 47.22% |
Timing Exceptions Report:
Setup Analysis Report
Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Hold Analysis Report
Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Recovery Analysis Report
Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Removal Analysis Report
Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Timing Constraints Report:
SDC Command Type | State | Detail Command |
---|---|---|
TC_CLOCK | Actived | create_clock -name MIPI_CLK_RX_P -period 10 -waveform {0 5} [get_pins {MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/IO}] |
TC_CLOCK | Actived | create_clock -name HS_CLK -period 10 -waveform {0 5} [get_nets {MIPI_RX_Advance_Top/DPHY_RX_INST/HS_CLK}] |
TC_CLOCK | Actived | create_clock -name MIPI_CLK_RX_N -period 10 -waveform {0 5} [get_pins {MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/IOB}] |
TC_CLOCK | Actived | create_clock -name sys_clk -period 20 -waveform {0 10} [get_ports {clkx2x4}] |
TC_CLOCK | Actived | create_clock -name tck_pad_i -period 50 -waveform {0 25} [get_ports {tck_pad_i}] |
TC_CLOCK | Actived | create_clock -name U3_CLKDIV -period 800 -waveform {0 400} [get_pins {U3_CLKDIV/CLKOUT}] |
TC_CLOCK | Actived | create_clock -name Inst3_CLKDIV_OUT -period 80 -waveform {0 40} [get_pins {MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT}] |
TC_FALSE_PATH | Actived | set_false_path -from [get_regs {MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0}] |
TC_FALSE_PATH | Actived | set_false_path -from [get_regs {MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0}] |
TC_CLOCK_GROUP | Actived | set_clock_groups -asynchronous -group [get_clocks {U3_CLKDIV}] -group [get_clocks {HS_CLK}] |