#Build: Synplify Pro (R) P-2019.03G-1-Beta1, Build 387R, Dec  3 2019
#install: E:\Gowin\Gowin_V1.9.3Beta_37257_win\SynplifyPro
#OS: Windows 7 6.1
#Hostname: GW-SW-001

# Thu Mar 26 10:13:10 2020

#Implementation: rev_1


Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03G-1-Beta1
Install: E:\Gowin\Gowin_V1.9.3Beta_37257_win\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-001

Implementation : rev_1
Synopsys HDL Compiler, Version comp2019q1p1, Build 391R, Built Dec  3 2019 09:16:34

@N|Running in 64-bit mode
###########################################################[

Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03G-1-Beta1
Install: E:\Gowin\Gowin_V1.9.3Beta_37257_win\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-001

Implementation : rev_1
Synopsys Verilog Compiler, Version comp2019q1p1, Build 391R, Built Dec  3 2019 09:16:34

@N|Running in 64-bit mode
@N: CG1349 :	| Running Verilog Compiler in System Verilog mode

@N: CG1350 :	| Running Verilog Compiler in Multiple File Compilation Unit mode

@I::"E:\Gowin\Gowin_V1.9.3Beta_37257_win\SynplifyPro\lib\generic\gw1n.v" (library work)
@I::"E:\Gowin\Gowin_V1.9.3Beta_37257_win\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"E:\Gowin\Gowin_V1.9.3Beta_37257_win\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps)
@I::"E:\Gowin\Gowin_V1.9.3Beta_37257_win\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"E:\Gowin\Gowin_V1.9.3Beta_37257_win\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\temp\gao\ao_0\gw_ao_parameter.v" (library work)
@I::"E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\temp\gao\ao_0\gw_ao_top_define.v" (library work)
@I::"E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\temp\gao\ao_0\gw_ao_expression.v" (library work)
@I::"E:\Gowin\Gowin_V1.9.3Beta_37257_win\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v" (library work)
@I::"E:\Gowin\Gowin_V1.9.3Beta_37257_win\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_define.v" (library work)
@I::"E:\Gowin\Gowin_V1.9.3Beta_37257_win\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v" (library work)
@W: CG1337 :"E:\Gowin\Gowin_V1.9.3Beta_37257_win\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v":109:9:109:26|Net match_m0_en_reg_wr is not declared.
@W: CG1337 :"E:\Gowin\Gowin_V1.9.3Beta_37257_win\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v":110:9:110:26|Net match_m1_en_reg_wr is not declared.
@W: CG1337 :"E:\Gowin\Gowin_V1.9.3Beta_37257_win\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v":111:9:111:26|Net match_m2_en_reg_wr is not declared.
@W: CG1337 :"E:\Gowin\Gowin_V1.9.3Beta_37257_win\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v":112:9:112:27|Net match_ctl_en_reg_wr is not declared.
@W: CG1337 :"E:\Gowin\Gowin_V1.9.3Beta_37257_win\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v":113:9:113:24|Net match_cnt_reg_wr is not declared.
@I::"E:\Gowin\Gowin_V1.9.3Beta_37257_win\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v" (library work)
@W: CG1337 :"E:\Gowin\Gowin_V1.9.3Beta_37257_win\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v":122:9:122:27|Net capture_length_zero is not declared.
@I::"E:\Gowin\Gowin_V1.9.3Beta_37257_win\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v" (library work)
@W: CG1337 :"E:\Gowin\Gowin_V1.9.3Beta_37257_win\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v":500:9:500:20|Net start_reg_wr is not declared.
@W: CG1337 :"E:\Gowin\Gowin_V1.9.3Beta_37257_win\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v":503:9:503:29|Net trig_level_max_reg_wr is not declared.
@W: CG1337 :"E:\Gowin\Gowin_V1.9.3Beta_37257_win\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v":504:9:504:31|Net capture_mem_addr_max_wr is not declared.
@W: CG1337 :"E:\Gowin\Gowin_V1.9.3Beta_37257_win\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v":505:9:505:31|Net capture_mem_addr_rem_wr is not declared.
@W: CG1337 :"E:\Gowin\Gowin_V1.9.3Beta_37257_win\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v":506:9:506:30|Net capture_windows_num_wr is not declared.
@W: CG1337 :"E:\Gowin\Gowin_V1.9.3Beta_37257_win\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v":1717:9:1717:18|Net match_en_0 is not declared.
@W: CG1337 :"E:\Gowin\Gowin_V1.9.3Beta_37257_win\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v":1718:9:1718:18|Net match_en_1 is not declared.
@W: CG1337 :"E:\Gowin\Gowin_V1.9.3Beta_37257_win\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v":1719:9:1719:18|Net match_en_2 is not declared.
@W: CG1337 :"E:\Gowin\Gowin_V1.9.3Beta_37257_win\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v":1720:9:1720:18|Net match_en_3 is not declared.
@W: CG1337 :"E:\Gowin\Gowin_V1.9.3Beta_37257_win\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v":1721:9:1721:18|Net match_en_4 is not declared.
@W: CG1337 :"E:\Gowin\Gowin_V1.9.3Beta_37257_win\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v":1722:9:1722:18|Net match_en_5 is not declared.
@W: CG1337 :"E:\Gowin\Gowin_V1.9.3Beta_37257_win\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v":1723:9:1723:18|Net match_en_6 is not declared.
@W: CG1337 :"E:\Gowin\Gowin_V1.9.3Beta_37257_win\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v":1724:9:1724:18|Net match_en_7 is not declared.
@W: CG1337 :"E:\Gowin\Gowin_V1.9.3Beta_37257_win\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v":1725:9:1725:18|Net match_en_8 is not declared.
@W: CG1337 :"E:\Gowin\Gowin_V1.9.3Beta_37257_win\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v":1726:9:1726:18|Net match_en_9 is not declared.
@W: CG1337 :"E:\Gowin\Gowin_V1.9.3Beta_37257_win\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v":1727:9:1727:19|Net match_en_10 is not declared.
@W: CG1337 :"E:\Gowin\Gowin_V1.9.3Beta_37257_win\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v":1728:9:1728:19|Net match_en_11 is not declared.
@W: CG1337 :"E:\Gowin\Gowin_V1.9.3Beta_37257_win\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v":1729:9:1729:19|Net match_en_12 is not declared.
@W: CG1337 :"E:\Gowin\Gowin_V1.9.3Beta_37257_win\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v":1730:9:1730:19|Net match_en_13 is not declared.
@W: CG1337 :"E:\Gowin\Gowin_V1.9.3Beta_37257_win\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v":1731:9:1731:19|Net match_en_14 is not declared.
@W: CG1337 :"E:\Gowin\Gowin_V1.9.3Beta_37257_win\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v":1732:9:1732:19|Net match_en_15 is not declared.
@W: CG1337 :"E:\Gowin\Gowin_V1.9.3Beta_37257_win\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v":2213:9:2213:16|Net stop_reg is not declared.
Verilog syntax check successful!
@N: CG364 :"E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\temp\gao\ao_0\gw_ao_parameter.v":1:0:1:8|Synthesizing module work_E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\temp\gao\ao_0\gw_ao_parameter.v_unit in library work.
Selecting top level module ao_top_0
Running optimization stage 1 on ao_mem_ctrl_0_1024s_66s_10s .......
Running optimization stage 1 on ao_crc32_0 .......
Running optimization stage 1 on ao_match_0_0s_1s_66s_1_1_0_1_2_3_4 .......
Running optimization stage 1 on ao_top_0 .......
Running optimization stage 2 on ao_match_0_0s_1s_66s_1_1_0_1_2_3_4 .......
Running optimization stage 2 on ao_top_0 .......
Extracted state machine for register module_state
State machine has 11 reachable states with original encodings of:
   0000
   0001
   0010
   0011
   0100
   0101
   0110
   0111
   1001
   1010
   1011
Running optimization stage 2 on ao_crc32_0 .......
Running optimization stage 2 on ao_mem_ctrl_0_1024s_66s_10s .......

For a summary of runtime and memory usage per design unit, please see file:
==========================================================
@L: E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\temp\gao\ao_0\rev_1\synwork\layer0.rt.csv


At c_ver Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 101MB peak: 108MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Thu Mar 26 10:13:11 2020

###########################################################]
###########################################################[

Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03G-1-Beta1
Install: E:\Gowin\Gowin_V1.9.3Beta_37257_win\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-001

Implementation : rev_1
Synopsys Synopsys Netlist Linker, Version comp2019q1p1, Build 391R, Built Dec  3 2019 09:16:34

@N|Running in 64-bit mode

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 88MB peak: 88MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Thu Mar 26 10:13:11 2020

###########################################################]

For a summary of runtime and memory usage for all design units, please see file:
==========================================================
@L: E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\temp\gao\ao_0\rev_1\synwork\ao_0_comp.rt.csv

@END

At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 18MB peak: 18MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Thu Mar 26 10:13:11 2020

###########################################################]
###########################################################[

Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03G-1-Beta1
Install: E:\Gowin\Gowin_V1.9.3Beta_37257_win\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-001

Implementation : rev_1
Synopsys Synopsys Netlist Linker, Version comp2019q1p1, Build 391R, Built Dec  3 2019 09:16:34

@N|Running in 64-bit mode

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 89MB peak: 89MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Thu Mar 26 10:13:13 2020

###########################################################]
Premap Report

# Thu Mar 26 10:13:13 2020


Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03G-1-Beta1
Install: E:\Gowin\Gowin_V1.9.3Beta_37257_win\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-001

Implementation : rev_1
Synopsys Generic Technology Pre-mapping, Version mapgw2019q1p1, Build 007R, Built Dec  5 2019 10:27:23


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)

@A: MF827 |No constraint file specified.
@L: E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\temp\gao\ao_0\rev_1\ao_0_scck.rpt 
Printing clock  summary report in "E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\temp\gao\ao_0\rev_1\ao_0_scck.rpt" file 
@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 128MB)

@N: BN133 |Ignoring syn_hier=hard property on top-level design.

Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 128MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)

Encoding state machine module_state[10:0] (in view: work.ao_top_0(verilog))
original code -> new code
   0000 -> 00000000001
   0001 -> 00000000010
   0010 -> 00000000100
   0011 -> 00000001000
   0100 -> 00000010000
   0101 -> 00000100000
   0110 -> 00001000000
   0111 -> 00010000000
   1001 -> 00100000000
   1010 -> 01000000000
   1011 -> 10000000000

Starting clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 223MB peak: 223MB)


Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 223MB peak: 223MB)


Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 223MB peak: 223MB)


Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 223MB peak: 223MB)


Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 223MB peak: 224MB)



Clock Summary
******************

          Start                   Requested     Requested     Clock        Clock                     Clock
Level     Clock                   Frequency     Period        Type         Group                     Load 
----------------------------------------------------------------------------------------------------------
0 -       ao_top_0|control[0]     115.5 MHz     8.659         inferred     Autoconstr_clkgroup_1     402  
                                                                                                          
0 -       ao_top_0|clk_i          140.1 MHz     7.136         inferred     Autoconstr_clkgroup_0     174  
==========================================================================================================



Clock Load Summary
***********************

                        Clock     Source               Clock Pin                                Non-clock Pin     Non-clock Pin       
Clock                   Load      Pin                  Seq Example                              Seq Example       Comb Example        
--------------------------------------------------------------------------------------------------------------------------------------
ao_top_0|control[0]     402       control[0](port)     data_register[86:0].C                    -                 -                   
                                                                                                                                      
ao_top_0|clk_i          174       clk_i(port)          internal_reg_force_triger_syn[1:0].C     -                 clk_ao.I[0](keepbuf)
======================================================================================================================================


ICG Latch Removal Summary:
Number of ICG latches removed: 0
Number of ICG latches not removed:	0


@S |Clock Optimization Summary



#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[

2 non-gated/non-generated clock tree(s) driving 511 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks

=========================== Non-Gated/Non-Generated Clocks ============================
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
---------------------------------------------------------------------------------------
@KP:ckid0_0       ENCRYPTED           port                   109        ENCRYPTED      
@KP:ckid0_1       ENCRYPTED           IO_port                402        ENCRYPTED      
=======================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######

@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
Finished Pre Mapping Phase.
@N: BN225 |Writing default property annotation file E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\temp\gao\ao_0\rev_1\ao_0.sap.

Starting constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 224MB peak: 224MB)


Finished constraint checker preprocessing (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 224MB peak: 224MB)


Finished constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 225MB peak: 225MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 144MB peak: 225MB)

Process took 0h:00m:02s realtime, 0h:00m:02s cputime
# Thu Mar 26 10:13:15 2020

###########################################################]
Map & Optimize Report

# Thu Mar 26 10:13:16 2020


Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03G-1-Beta1
Install: E:\Gowin\Gowin_V1.9.3Beta_37257_win\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-001

Implementation : rev_1
Synopsys Generic Technology Mapper, Version mapgw2019q1p1, Build 007R, Built Dec  5 2019 10:27:23


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)

@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 119MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 119MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 122MB peak: 122MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 137MB)



Starting Optimization and Mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 217MB peak: 217MB)


Available hyper_sources - for debug and ip models
	None Found

@N: MT206 |Auto Constrain mode is enabled

Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 222MB peak: 222MB)


Starting factoring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 226MB peak: 226MB)


Finished factoring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 231MB peak: 231MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 232MB peak: 232MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 232MB peak: 232MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 232MB peak: 232MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 232MB peak: 232MB)


Finished preparing to map (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 232MB peak: 232MB)


Finished technology mapping (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 246MB peak: 246MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:03s		    -4.50ns		 460 /       438
   2		0h:00m:03s		    -4.50ns		 455 /       438
   3		0h:00m:03s		    -4.12ns		 454 /       438
   4		0h:00m:03s		    -4.43ns		 453 /       438
Timing driven replication report
Added 2 Registers via timing driven replication
Added 2 LUTs via timing driven replication

   5		0h:00m:04s		    -3.90ns		 466 /       440
   6		0h:00m:04s		    -4.16ns		 467 /       440
   7		0h:00m:04s		    -4.16ns		 470 /       440
   8		0h:00m:04s		    -4.16ns		 470 /       440
   9		0h:00m:04s		    -4.16ns		 470 /       440
Timing driven replication report
Added 1 Registers via timing driven replication
Added 1 LUTs via timing driven replication

Timing driven replication report
Added 0 Registers via timing driven replication
Added 1 LUTs via timing driven replication

  10		0h:00m:04s		    -3.78ns		 473 /       441
  11		0h:00m:04s		    -3.85ns		 473 /       441
  12		0h:00m:04s		    -3.54ns		 474 /       441
  13		0h:00m:04s		    -4.13ns		 474 /       441
  14		0h:00m:04s		    -4.13ns		 474 /       441

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 248MB peak: 248MB)

@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  

Finished restoring hierarchy (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 248MB peak: 248MB)


Start Writing Netlists (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:05s; Memory used current: 177MB peak: 249MB)

Writing Analyst data base E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\temp\gao\ao_0\rev_1\synwork\ao_0_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 250MB peak: 251MB)

Writing Verilog Simulation files

Writing scf file... (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:07s; Memory used current: 251MB peak: 251MB)

@N: BW103 |The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns.
@N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF 

Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:07s; Memory used current: 251MB peak: 251MB)


Start final timing analysis (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:08s; Memory used current: 248MB peak: 251MB)

@W: MT420 |Found inferred clock ao_top_0|clk_i with period 9.75ns. Please declare a user-defined clock on port clk_i.
@W: MT420 |Found inferred clock ao_top_0|control[0] with period 12.67ns. Please declare a user-defined clock on port control[0].


##### START OF TIMING REPORT #####[
# Timing report written on Thu Mar 26 10:13:25 2020
#


Top view:               ao_top_0
Requested Frequency:    78.9 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.

@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.



Performance Summary
*******************


Worst slack in design: -2.236

                        Requested     Estimated     Requested     Estimated                Clock        Clock                
Starting Clock          Frequency     Frequency     Period        Period        Slack      Type         Group                
-----------------------------------------------------------------------------------------------------------------------------
ao_top_0|clk_i          102.5 MHz     87.1 MHz      9.754         11.475        -1.721     inferred     Autoconstr_clkgroup_0
ao_top_0|control[0]     78.9 MHz      67.1 MHz      12.673        14.910        -2.236     inferred     Autoconstr_clkgroup_1
System                  100.0 MHz     196.8 MHz     10.000        5.081         4.919      system       system_clkgroup      
=============================================================================================================================





Clock Relationships
*******************

Clocks                                    |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
---------------------------------------------------------------------------------------------------------------------------------
Starting             Ending               |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
---------------------------------------------------------------------------------------------------------------------------------
System               ao_top_0|clk_i       |  9.754       4.919   |  No paths    -      |  No paths    -      |  No paths    -    
System               ao_top_0|control[0]  |  12.673      8.772   |  No paths    -      |  No paths    -      |  No paths    -    
ao_top_0|clk_i       System               |  9.754       8.088   |  No paths    -      |  No paths    -      |  No paths    -    
ao_top_0|clk_i       ao_top_0|clk_i       |  9.754       -1.721  |  9.754       7.929  |  No paths    -      |  4.877       3.052
ao_top_0|clk_i       ao_top_0|control[0]  |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -    
ao_top_0|control[0]  System               |  12.673      11.008  |  No paths    -      |  No paths    -      |  No paths    -    
ao_top_0|control[0]  ao_top_0|clk_i       |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -    
ao_top_0|control[0]  ao_top_0|control[0]  |  12.673      -2.236  |  No paths    -      |  No paths    -      |  No paths    -    
=================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: ao_top_0|clk_i
====================================



Starting Points with Worst Slack
********************************

                                     Starting                                                                 Arrival           
Instance                             Reference          Type     Pin     Net                                  Time        Slack 
                                     Clock                                                                                      
--------------------------------------------------------------------------------------------------------------------------------
capture_window_sel[1]                ao_top_0|clk_i     DFFC     Q       capture_window_sel[1]                0.440       -1.721
capture_window_sel[0]                ao_top_0|clk_i     DFFC     Q       capture_window_sel[0]                0.440       -1.641
triger_level_cnt[0]                  ao_top_0|clk_i     DFFC     Q       triger_level_cnt[0]                  0.440       -1.227
internal_reg_force_triger_syn[1]     ao_top_0|clk_i     DFFC     Q       internal_reg_force_triger_syn[1]     0.440       -1.146
triger_level_cnt[1]                  ao_top_0|clk_i     DFFC     Q       triger_level_cnt[1]                  0.440       -0.894
u_ao_mem_ctrl.capture_length[0]      ao_top_0|clk_i     DFFC     Q       capture_length[0]                    0.440       -0.831
u_ao_mem_ctrl.capture_length[1]      ao_top_0|clk_i     DFFC     Q       capture_length[1]                    0.440       -0.763
u_ao_mem_ctrl.capture_length[2]      ao_top_0|clk_i     DFFC     Q       capture_length[2]                    0.440       -0.694
u_ao_mem_ctrl.capture_length[3]      ao_top_0|clk_i     DFFP     Q       capture_length[3]                    0.440       -0.626
u_ao_mem_ctrl.capture_length[4]      ao_top_0|clk_i     DFFC     Q       capture_length[4]                    0.440       -0.557
================================================================================================================================


Ending Points with Worst Slack
******************************

                                      Starting                                                         Required           
Instance                              Reference          Type      Pin     Net                         Time         Slack 
                                      Clock                                                                               
--------------------------------------------------------------------------------------------------------------------------
u_ao_mem_ctrl.capture_mem_wr          ao_top_0|clk_i     DFFCE     CE      un1_start_reg               9.594        -1.721
u_ao_mem_ctrl.mem_addr_inc_en         ao_top_0|clk_i     DFFCE     CE      un1_capture_length_zero     9.594        -0.831
triger_level_cnt[3]                   ao_top_0|clk_i     DFFC      D       triger_level_cnt_4[3]       9.594        -0.303
triger_level_cnt[2]                   ao_top_0|clk_i     DFFC      D       triger_level_cnt_4[2]       9.594        0.029 
triger_level_cnt[0]                   ao_top_0|clk_i     DFFC      D       triger_level_cnt_4[0]       9.594        0.265 
u_ao_mem_ctrl.mem_addr_inc_en         ao_top_0|clk_i     DFFCE     D       mem_addr_inc_en7            9.594        0.346 
triger_level_cnt[1]                   ao_top_0|clk_i     DFFC      D       triger_level_cnt_4[1]       9.594        0.346 
u_ao_mem_ctrl.capture_loop            ao_top_0|clk_i     DFFCE     CE      un1_mem_addr_inc_en6        9.594        0.401 
u_ao_mem_ctrl.capture_mem_addr[0]     ao_top_0|clk_i     DFFCE     D       capture_mem_addr_lm[0]      9.594        0.401 
u_ao_mem_ctrl.capture_mem_addr[1]     ao_top_0|clk_i     DFFCE     D       capture_mem_addr_lm[1]      9.594        0.401 
==========================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      9.754
    - Setup time:                            0.160
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.594

    - Propagation time:                      11.315
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.721

    Number of logic level(s):                5
    Starting point:                          capture_window_sel[1] / Q
    Ending point:                            u_ao_mem_ctrl.capture_mem_wr / CE
    The start point is clocked by            ao_top_0|clk_i [rising] on pin CLK
    The end   point is clocked by            ao_top_0|clk_i [rising] on pin CLK

Instance / Net                                  Pin      Pin               Arrival     No. of    
Name                                  Type      Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------
capture_window_sel[1]                 DFFC      Q        Out     0.440     0.440       -         
capture_window_sel[1]                 Net       -        -       1.225     -           5         
un6_start_reg_c2                      LUT4      I1       In      -         1.666       -         
un6_start_reg_c2                      LUT4      F        Out     1.319     2.984       -         
un6_start_reg_c2                      Net       -        -       0.919     -           1         
un6_start_reg_ac0_5_0                 LUT4      I3       In      -         3.903       -         
un6_start_reg_ac0_5_0                 LUT4      F        Out     0.751     4.654       -         
un6_start_reg_ac0_5_0                 Net       -        -       1.225     -           4         
start_reg                             LUT3      I2       In      -         5.880       -         
start_reg                             LUT3      F        Out     0.986     6.866       -         
start_reg                             Net       -        -       1.225     -           2         
u_ao_mem_ctrl.un1_start_reg_N_3L3     LUT4      I1       In      -         8.091       -         
u_ao_mem_ctrl.un1_start_reg_N_3L3     LUT4      F        Out     1.319     9.410       -         
un1_start_reg_1                       Net       -        -       0.919     -           1         
u_ao_mem_ctrl.un1_start_reg           LUT4      I2       In      -         10.329      -         
u_ao_mem_ctrl.un1_start_reg           LUT4      F        Out     0.986     11.315      -         
un1_start_reg                         Net       -        -       0.000     -           1         
u_ao_mem_ctrl.capture_mem_wr          DFFCE     CE       In      -         11.315      -         
=================================================================================================
Total path delay (propagation time + setup) of 11.475 is 5.962(52.0%) logic and 5.513(48.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      9.754
    - Setup time:                            0.160
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.594

    - Propagation time:                      11.235
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.641

    Number of logic level(s):                5
    Starting point:                          capture_window_sel[0] / Q
    Ending point:                            u_ao_mem_ctrl.capture_mem_wr / CE
    The start point is clocked by            ao_top_0|clk_i [rising] on pin CLK
    The end   point is clocked by            ao_top_0|clk_i [rising] on pin CLK

Instance / Net                                  Pin      Pin               Arrival     No. of    
Name                                  Type      Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------
capture_window_sel[0]                 DFFC      Q        Out     0.440     0.440       -         
capture_window_sel[0]                 Net       -        -       1.225     -           7         
un6_start_reg_c2                      LUT4      I0       In      -         1.666       -         
un6_start_reg_c2                      LUT4      F        Out     1.238     2.904       -         
un6_start_reg_c2                      Net       -        -       0.919     -           1         
un6_start_reg_ac0_5_0                 LUT4      I3       In      -         3.823       -         
un6_start_reg_ac0_5_0                 LUT4      F        Out     0.751     4.574       -         
un6_start_reg_ac0_5_0                 Net       -        -       1.225     -           4         
start_reg                             LUT3      I2       In      -         5.799       -         
start_reg                             LUT3      F        Out     0.986     6.786       -         
start_reg                             Net       -        -       1.225     -           2         
u_ao_mem_ctrl.un1_start_reg_N_3L3     LUT4      I1       In      -         8.011       -         
u_ao_mem_ctrl.un1_start_reg_N_3L3     LUT4      F        Out     1.319     9.330       -         
un1_start_reg_1                       Net       -        -       0.919     -           1         
u_ao_mem_ctrl.un1_start_reg           LUT4      I2       In      -         10.249      -         
u_ao_mem_ctrl.un1_start_reg           LUT4      F        Out     0.986     11.235      -         
un1_start_reg                         Net       -        -       0.000     -           1         
u_ao_mem_ctrl.capture_mem_wr          DFFCE     CE       In      -         11.235      -         
=================================================================================================
Total path delay (propagation time + setup) of 11.395 is 5.881(51.6%) logic and 5.513(48.4%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      9.754
    - Setup time:                            0.160
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.594

    - Propagation time:                      10.821
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.227

    Number of logic level(s):                5
    Starting point:                          triger_level_cnt[0] / Q
    Ending point:                            u_ao_mem_ctrl.capture_mem_wr / CE
    The start point is clocked by            ao_top_0|clk_i [rising] on pin CLK
    The end   point is clocked by            ao_top_0|clk_i [rising] on pin CLK

Instance / Net                                  Pin      Pin               Arrival     No. of    
Name                                  Type      Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------
triger_level_cnt[0]                   DFFC      Q        Out     0.440     0.440       -         
triger_level_cnt[0]                   Net       -        -       1.225     -           4         
un1_match_final_3                     LUT3      I1       In      -         1.666       -         
un1_match_final_3                     LUT3      F        Out     1.319     2.984       -         
un1_match_final_3                     Net       -        -       0.919     -           1         
un1_match_final                       LUT4      I3       In      -         3.903       -         
un1_match_final                       LUT4      F        Out     0.751     4.654       -         
un1_match_final                       Net       -        -       1.225     -           4         
triger_level_cnt_0_sqmuxa             LUT4      I3       In      -         5.880       -         
triger_level_cnt_0_sqmuxa             LUT4      F        Out     0.751     6.631       -         
triger_level_cnt_0_sqmuxa             Net       -        -       1.298     -           15        
u_ao_mem_ctrl.un1_start_reg_N_3L3     LUT4      I2       In      -         7.929       -         
u_ao_mem_ctrl.un1_start_reg_N_3L3     LUT4      F        Out     0.986     8.916       -         
un1_start_reg_1                       Net       -        -       0.919     -           1         
u_ao_mem_ctrl.un1_start_reg           LUT4      I2       In      -         9.835       -         
u_ao_mem_ctrl.un1_start_reg           LUT4      F        Out     0.986     10.821      -         
un1_start_reg                         Net       -        -       0.000     -           1         
u_ao_mem_ctrl.capture_mem_wr          DFFCE     CE       In      -         10.821      -         
=================================================================================================
Total path delay (propagation time + setup) of 10.981 is 5.394(49.1%) logic and 5.587(50.9%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      9.754
    - Setup time:                            0.160
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.594

    - Propagation time:                      10.741
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.146

    Number of logic level(s):                5
    Starting point:                          internal_reg_force_triger_syn[1] / Q
    Ending point:                            u_ao_mem_ctrl.capture_mem_wr / CE
    The start point is clocked by            ao_top_0|clk_i [rising] on pin CLK
    The end   point is clocked by            ao_top_0|clk_i [rising] on pin CLK

Instance / Net                                  Pin      Pin               Arrival     No. of    
Name                                  Type      Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------
internal_reg_force_triger_syn[1]      DFFC      Q        Out     0.440     0.440       -         
internal_reg_force_triger_syn[1]      Net       -        -       1.225     -           1         
un1_match_final_3                     LUT3      I0       In      -         1.666       -         
un1_match_final_3                     LUT3      F        Out     1.238     2.904       -         
un1_match_final_3                     Net       -        -       0.919     -           1         
un1_match_final                       LUT4      I3       In      -         3.823       -         
un1_match_final                       LUT4      F        Out     0.751     4.574       -         
un1_match_final                       Net       -        -       1.225     -           4         
triger_level_cnt_0_sqmuxa             LUT4      I3       In      -         5.799       -         
triger_level_cnt_0_sqmuxa             LUT4      F        Out     0.751     6.551       -         
triger_level_cnt_0_sqmuxa             Net       -        -       1.298     -           15        
u_ao_mem_ctrl.un1_start_reg_N_3L3     LUT4      I2       In      -         7.849       -         
u_ao_mem_ctrl.un1_start_reg_N_3L3     LUT4      F        Out     0.986     8.835       -         
un1_start_reg_1                       Net       -        -       0.919     -           1         
u_ao_mem_ctrl.un1_start_reg           LUT4      I2       In      -         9.754       -         
u_ao_mem_ctrl.un1_start_reg           LUT4      F        Out     0.986     10.741      -         
un1_start_reg                         Net       -        -       0.000     -           1         
u_ao_mem_ctrl.capture_mem_wr          DFFCE     CE       In      -         10.741      -         
=================================================================================================
Total path delay (propagation time + setup) of 10.900 is 5.314(48.7%) logic and 5.587(51.3%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      9.754
    - Setup time:                            0.160
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.594

    - Propagation time:                      10.489
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.894

    Number of logic level(s):                5
    Starting point:                          triger_level_cnt[1] / Q
    Ending point:                            u_ao_mem_ctrl.capture_mem_wr / CE
    The start point is clocked by            ao_top_0|clk_i [rising] on pin CLK
    The end   point is clocked by            ao_top_0|clk_i [rising] on pin CLK

Instance / Net                                  Pin      Pin               Arrival     No. of    
Name                                  Type      Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------
triger_level_cnt[1]                   DFFC      Q        Out     0.440     0.440       -         
triger_level_cnt[1]                   Net       -        -       1.225     -           5         
un1_match_final_3                     LUT3      I2       In      -         1.666       -         
un1_match_final_3                     LUT3      F        Out     0.986     2.652       -         
un1_match_final_3                     Net       -        -       0.919     -           1         
un1_match_final                       LUT4      I3       In      -         3.571       -         
un1_match_final                       LUT4      F        Out     0.751     4.322       -         
un1_match_final                       Net       -        -       1.225     -           4         
triger_level_cnt_0_sqmuxa             LUT4      I3       In      -         5.547       -         
triger_level_cnt_0_sqmuxa             LUT4      F        Out     0.751     6.298       -         
triger_level_cnt_0_sqmuxa             Net       -        -       1.298     -           15        
u_ao_mem_ctrl.un1_start_reg_N_3L3     LUT4      I2       In      -         7.597       -         
u_ao_mem_ctrl.un1_start_reg_N_3L3     LUT4      F        Out     0.986     8.583       -         
un1_start_reg_1                       Net       -        -       0.919     -           1         
u_ao_mem_ctrl.un1_start_reg           LUT4      I2       In      -         9.502       -         
u_ao_mem_ctrl.un1_start_reg           LUT4      F        Out     0.986     10.489      -         
un1_start_reg                         Net       -        -       0.000     -           1         
u_ao_mem_ctrl.capture_mem_wr          DFFCE     CE       In      -         10.489      -         
=================================================================================================
Total path delay (propagation time + setup) of 10.648 is 5.062(47.5%) logic and 5.587(52.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: ao_top_0|control[0]
====================================



Starting Points with Worst Slack
********************************

                   Starting                                                     Arrival           
Instance           Reference               Type      Pin     Net                Time        Slack 
                   Clock                                                                          
--------------------------------------------------------------------------------------------------
bit_count[3]       ao_top_0|control[0]     DFFCE     Q       bit_count[3]       0.440       -2.236
word_count[7]      ao_top_0|control[0]     DFFCE     Q       word_count[7]      0.440       -2.184
bit_count[1]       ao_top_0|control[0]     DFFCE     Q       bit_count[1]       0.440       -2.156
word_count[3]      ao_top_0|control[0]     DFFCE     Q       word_count[3]      0.440       -2.104
word_count[6]      ao_top_0|control[0]     DFFCE     Q       word_count[6]      0.440       -2.104
word_count[2]      ao_top_0|control[0]     DFFCE     Q       word_count[2]      0.440       -2.023
bit_count[5]       ao_top_0|control[0]     DFFCE     Q       bit_count[5]       0.440       -1.904
word_count[8]      ao_top_0|control[0]     DFFCE     Q       word_count[8]      0.440       -1.852
word_count[13]     ao_top_0|control[0]     DFFCE     Q       word_count[13]     0.440       -1.852
word_count[1]      ao_top_0|control[0]     DFFCE     Q       word_count[1]      0.440       -1.772
==================================================================================================


Ending Points with Worst Slack
******************************

                       Starting                                                      Required           
Instance               Reference               Type      Pin     Net                 Time         Slack 
                       Clock                                                                            
--------------------------------------------------------------------------------------------------------
bit_count[0]           ao_top_0|control[0]     DFFCE     D       bit_count_lm[0]     12.514       -2.236
bit_count[1]           ao_top_0|control[0]     DFFCE     D       bit_count_lm[1]     12.514       -2.236
bit_count[2]           ao_top_0|control[0]     DFFCE     D       bit_count_lm[2]     12.514       -2.236
bit_count[3]           ao_top_0|control[0]     DFFCE     D       bit_count_lm[3]     12.514       -2.236
bit_count[4]           ao_top_0|control[0]     DFFCE     D       bit_count_lm[4]     12.514       -2.236
bit_count[5]           ao_top_0|control[0]     DFFCE     D       bit_count_lm[5]     12.514       -2.236
bit_count[6]           ao_top_0|control[0]     DFFCE     D       bit_count_lm[6]     12.514       -2.236
address_counter[0]     ao_top_0|control[0]     DFFCE     CE      addr_ct_en          12.514       -2.184
address_counter[1]     ao_top_0|control[0]     DFFCE     CE      addr_ct_en          12.514       -2.184
address_counter[2]     ao_top_0|control[0]     DFFCE     CE      addr_ct_en          12.514       -2.184
========================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      12.673
    - Setup time:                            0.160
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         12.514

    - Propagation time:                      14.750
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -2.236

    Number of logic level(s):                6
    Starting point:                          bit_count[3] / Q
    Ending point:                            bit_count[0] / D
    The start point is clocked by            ao_top_0|control[0] [rising] on pin CLK
    The end   point is clocked by            ao_top_0|control[0] [rising] on pin CLK

Instance / Net                            Pin      Pin               Arrival     No. of    
Name                            Type      Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------
bit_count[3]                    DFFCE     Q        Out     0.440     0.440       -         
bit_count[3]                    Net       -        -       1.225     -           4         
module_state_ns_0_a2_sx[10]     LUT4      I1       In      -         1.666       -         
module_state_ns_0_a2_sx[10]     LUT4      F        Out     1.319     2.984       -         
module_state_ns_0_a2_sx[10]     Net       -        -       0.919     -           1         
module_state_ns_0_a2[10]        LUT4      I3       In      -         3.903       -         
module_state_ns_0_a2[10]        LUT4      F        Out     0.751     4.654       -         
N_401                           Net       -        -       1.225     -           10        
bit_ct_rst_1                    LUT2      I1       In      -         5.880       -         
bit_ct_rst_1                    LUT2      F        Out     1.319     7.199       -         
N_440                           Net       -        -       1.225     -           2         
g0_14                           LUT3      I0       In      -         8.424       -         
g0_14                           LUT3      F        Out     1.238     9.662       -         
bit_ct_rst_u_N_2_3_0            Net       -        -       1.225     -           2         
g0_6                            LUT4      I1       In      -         10.887      -         
g0_6                            LUT4      F        Out     1.319     12.206      -         
bit_ct_rst                      Net       -        -       1.225     -           7         
bit_count_lm_0[0]               LUT2      I1       In      -         13.431      -         
bit_count_lm_0[0]               LUT2      F        Out     1.319     14.750      -         
bit_count_lm[0]                 Net       -        -       0.000     -           1         
bit_count[0]                    DFFCE     D        In      -         14.750      -         
===========================================================================================
Total path delay (propagation time + setup) of 14.910 is 7.865(52.7%) logic and 7.045(47.3%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      12.673
    - Setup time:                            0.160
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         12.514

    - Propagation time:                      14.750
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -2.236

    Number of logic level(s):                6
    Starting point:                          bit_count[3] / Q
    Ending point:                            bit_count[6] / D
    The start point is clocked by            ao_top_0|control[0] [rising] on pin CLK
    The end   point is clocked by            ao_top_0|control[0] [rising] on pin CLK

Instance / Net                            Pin      Pin               Arrival     No. of    
Name                            Type      Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------
bit_count[3]                    DFFCE     Q        Out     0.440     0.440       -         
bit_count[3]                    Net       -        -       1.225     -           4         
module_state_ns_0_a2_sx[10]     LUT4      I1       In      -         1.666       -         
module_state_ns_0_a2_sx[10]     LUT4      F        Out     1.319     2.984       -         
module_state_ns_0_a2_sx[10]     Net       -        -       0.919     -           1         
module_state_ns_0_a2[10]        LUT4      I3       In      -         3.903       -         
module_state_ns_0_a2[10]        LUT4      F        Out     0.751     4.654       -         
N_401                           Net       -        -       1.225     -           10        
bit_ct_rst_1                    LUT2      I1       In      -         5.880       -         
bit_ct_rst_1                    LUT2      F        Out     1.319     7.199       -         
N_440                           Net       -        -       1.225     -           2         
g0_14                           LUT3      I0       In      -         8.424       -         
g0_14                           LUT3      F        Out     1.238     9.662       -         
bit_ct_rst_u_N_2_3_0            Net       -        -       1.225     -           2         
g0_6                            LUT4      I1       In      -         10.887      -         
g0_6                            LUT4      F        Out     1.319     12.206      -         
bit_ct_rst                      Net       -        -       1.225     -           7         
bit_count_lm_0[6]               LUT2      I1       In      -         13.431      -         
bit_count_lm_0[6]               LUT2      F        Out     1.319     14.750      -         
bit_count_lm[6]                 Net       -        -       0.000     -           1         
bit_count[6]                    DFFCE     D        In      -         14.750      -         
===========================================================================================
Total path delay (propagation time + setup) of 14.910 is 7.865(52.7%) logic and 7.045(47.3%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      12.673
    - Setup time:                            0.160
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         12.514

    - Propagation time:                      14.750
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -2.236

    Number of logic level(s):                6
    Starting point:                          bit_count[3] / Q
    Ending point:                            bit_count[5] / D
    The start point is clocked by            ao_top_0|control[0] [rising] on pin CLK
    The end   point is clocked by            ao_top_0|control[0] [rising] on pin CLK

Instance / Net                            Pin      Pin               Arrival     No. of    
Name                            Type      Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------
bit_count[3]                    DFFCE     Q        Out     0.440     0.440       -         
bit_count[3]                    Net       -        -       1.225     -           4         
module_state_ns_0_a2_sx[10]     LUT4      I1       In      -         1.666       -         
module_state_ns_0_a2_sx[10]     LUT4      F        Out     1.319     2.984       -         
module_state_ns_0_a2_sx[10]     Net       -        -       0.919     -           1         
module_state_ns_0_a2[10]        LUT4      I3       In      -         3.903       -         
module_state_ns_0_a2[10]        LUT4      F        Out     0.751     4.654       -         
N_401                           Net       -        -       1.225     -           10        
bit_ct_rst_1                    LUT2      I1       In      -         5.880       -         
bit_ct_rst_1                    LUT2      F        Out     1.319     7.199       -         
N_440                           Net       -        -       1.225     -           2         
g0_14                           LUT3      I0       In      -         8.424       -         
g0_14                           LUT3      F        Out     1.238     9.662       -         
bit_ct_rst_u_N_2_3_0            Net       -        -       1.225     -           2         
g0_6                            LUT4      I1       In      -         10.887      -         
g0_6                            LUT4      F        Out     1.319     12.206      -         
bit_ct_rst                      Net       -        -       1.225     -           7         
bit_count_lm_0[5]               LUT2      I1       In      -         13.431      -         
bit_count_lm_0[5]               LUT2      F        Out     1.319     14.750      -         
bit_count_lm[5]                 Net       -        -       0.000     -           1         
bit_count[5]                    DFFCE     D        In      -         14.750      -         
===========================================================================================
Total path delay (propagation time + setup) of 14.910 is 7.865(52.7%) logic and 7.045(47.3%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      12.673
    - Setup time:                            0.160
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         12.514

    - Propagation time:                      14.750
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -2.236

    Number of logic level(s):                6
    Starting point:                          bit_count[3] / Q
    Ending point:                            bit_count[4] / D
    The start point is clocked by            ao_top_0|control[0] [rising] on pin CLK
    The end   point is clocked by            ao_top_0|control[0] [rising] on pin CLK

Instance / Net                            Pin      Pin               Arrival     No. of    
Name                            Type      Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------
bit_count[3]                    DFFCE     Q        Out     0.440     0.440       -         
bit_count[3]                    Net       -        -       1.225     -           4         
module_state_ns_0_a2_sx[10]     LUT4      I1       In      -         1.666       -         
module_state_ns_0_a2_sx[10]     LUT4      F        Out     1.319     2.984       -         
module_state_ns_0_a2_sx[10]     Net       -        -       0.919     -           1         
module_state_ns_0_a2[10]        LUT4      I3       In      -         3.903       -         
module_state_ns_0_a2[10]        LUT4      F        Out     0.751     4.654       -         
N_401                           Net       -        -       1.225     -           10        
bit_ct_rst_1                    LUT2      I1       In      -         5.880       -         
bit_ct_rst_1                    LUT2      F        Out     1.319     7.199       -         
N_440                           Net       -        -       1.225     -           2         
g0_14                           LUT3      I0       In      -         8.424       -         
g0_14                           LUT3      F        Out     1.238     9.662       -         
bit_ct_rst_u_N_2_3_0            Net       -        -       1.225     -           2         
g0_6                            LUT4      I1       In      -         10.887      -         
g0_6                            LUT4      F        Out     1.319     12.206      -         
bit_ct_rst                      Net       -        -       1.225     -           7         
bit_count_lm_0[4]               LUT2      I1       In      -         13.431      -         
bit_count_lm_0[4]               LUT2      F        Out     1.319     14.750      -         
bit_count_lm[4]                 Net       -        -       0.000     -           1         
bit_count[4]                    DFFCE     D        In      -         14.750      -         
===========================================================================================
Total path delay (propagation time + setup) of 14.910 is 7.865(52.7%) logic and 7.045(47.3%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      12.673
    - Setup time:                            0.160
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         12.514

    - Propagation time:                      14.750
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -2.236

    Number of logic level(s):                6
    Starting point:                          bit_count[3] / Q
    Ending point:                            bit_count[3] / D
    The start point is clocked by            ao_top_0|control[0] [rising] on pin CLK
    The end   point is clocked by            ao_top_0|control[0] [rising] on pin CLK

Instance / Net                            Pin      Pin               Arrival     No. of    
Name                            Type      Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------
bit_count[3]                    DFFCE     Q        Out     0.440     0.440       -         
bit_count[3]                    Net       -        -       1.225     -           4         
module_state_ns_0_a2_sx[10]     LUT4      I1       In      -         1.666       -         
module_state_ns_0_a2_sx[10]     LUT4      F        Out     1.319     2.984       -         
module_state_ns_0_a2_sx[10]     Net       -        -       0.919     -           1         
module_state_ns_0_a2[10]        LUT4      I3       In      -         3.903       -         
module_state_ns_0_a2[10]        LUT4      F        Out     0.751     4.654       -         
N_401                           Net       -        -       1.225     -           10        
bit_ct_rst_1                    LUT2      I1       In      -         5.880       -         
bit_ct_rst_1                    LUT2      F        Out     1.319     7.199       -         
N_440                           Net       -        -       1.225     -           2         
g0_14                           LUT3      I0       In      -         8.424       -         
g0_14                           LUT3      F        Out     1.238     9.662       -         
bit_ct_rst_u_N_2_3_0            Net       -        -       1.225     -           2         
g0_6                            LUT4      I1       In      -         10.887      -         
g0_6                            LUT4      F        Out     1.319     12.206      -         
bit_ct_rst                      Net       -        -       1.225     -           7         
bit_count_lm_0[3]               LUT2      I1       In      -         13.431      -         
bit_count_lm_0[3]               LUT2      F        Out     1.319     14.750      -         
bit_count_lm[3]                 Net       -        -       0.000     -           1         
bit_count[3]                    DFFCE     D        In      -         14.750      -         
===========================================================================================
Total path delay (propagation time + setup) of 14.910 is 7.865(52.7%) logic and 7.045(47.3%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: System
====================================



Starting Points with Worst Slack
********************************

                                   Starting                                           Arrival          
Instance                           Reference     Type     Pin     Net                 Time        Slack
                                   Clock                                                               
-------------------------------------------------------------------------------------------------------
u_ao_mem_ctrl.capture_mem_wr_i     System        INV      O       capture_end         0.000       4.919
module_state_i[0]                  System        INV      O       address_counter     0.000       8.772
=======================================================================================================


Ending Points with Worst Slack
******************************

                              Starting                                                        Required          
Instance                      Reference     Type      Pin     Net                             Time         Slack
                              Clock                                                                             
----------------------------------------------------------------------------------------------------------------
capture_window_sel[2]         System        DFFC      D       capture_window_sel_3[2]         9.594        4.919
capture_window_sel[3]         System        DFFC      D       capture_window_sel_3[3]         9.594        4.919
capture_window_sel[1]         System        DFFC      D       capture_window_sel_3[1]         9.594        5.460
capture_window_sel[0]         System        DFFC      D       capture_window_sel_3[0]         9.594        7.131
internal_reg_start_dly[0]     System        DFFC      D       internal_reg_start_dly_2[0]     9.594        7.131
capture_end_dly               System        DFFP      D       capture_end                     9.594        8.369
address_counter[9]            System        DFFCE     D       address_counter_s[9]            12.514       8.772
address_counter[8]            System        DFFCE     D       address_counter_s[8]            12.514       8.840
address_counter[7]            System        DFFCE     D       address_counter_s[7]            12.514       8.909
address_counter[6]            System        DFFCE     D       address_counter_s[6]            12.514       8.977
================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      9.754
    - Setup time:                            0.160
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.594

    - Propagation time:                      4.675
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 4.919

    Number of logic level(s):                2
    Starting point:                          u_ao_mem_ctrl.capture_mem_wr_i / O
    Ending point:                            capture_window_sel[2] / D
    The start point is clocked by            System [rising]
    The end   point is clocked by            ao_top_0|clk_i [rising] on pin CLK

Instance / Net                              Pin      Pin               Arrival     No. of    
Name                               Type     Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------
u_ao_mem_ctrl.capture_mem_wr_i     INV      O        Out     0.000     0.000       -         
capture_end                        Net      -        -       1.225     -           6         
un1_capture_window_sel_ac0_1       LUT4     I0       In      -         1.225       -         
un1_capture_window_sel_ac0_1       LUT4     F        Out     1.238     2.464       -         
un1_capture_window_sel_c2          Net      -        -       1.225     -           2         
capture_window_sel_3[2]            LUT3     I2       In      -         3.689       -         
capture_window_sel_3[2]            LUT3     F        Out     0.986     4.675       -         
capture_window_sel_3[2]            Net      -        -       0.000     -           1         
capture_window_sel[2]              DFFC     D        In      -         4.675       -         
=============================================================================================
Total path delay (propagation time + setup) of 4.835 is 2.384(49.3%) logic and 2.450(50.7%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

Timing exceptions that could not be applied

Finished final timing analysis (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:08s; Memory used current: 248MB peak: 251MB)


Finished timing report (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:08s; Memory used current: 248MB peak: 251MB)

---------------------------------------
Resource Usage Report for ao_top_0 

Mapping to part: gw1n_9pbga256-5
Cell usage:
ALU             71 uses
DFF             65 uses
DFFC            38 uses
DFFCE           299 uses
DFFNP           2 uses
DFFP            5 uses
DFFPE           32 uses
GSR             1 use
INV             2 uses
MUX2_LUT5       3 uses
SDPX9           4 uses
LUT2            52 uses
LUT3            89 uses
LUT4            279 uses

I/O ports: 77
I/O primitives: 77
IBUF           75 uses
OBUF           2 uses

I/O Register bits:                  0
Register bits not including I/Os:   441 of 6480 (6%)

RAM/ROM usage summary
Block Rams : 4 of 26 (15%)

Total load per clock:
   ao_top_0|clk_i: 1
   ao_top_0|control[0]: 337

@S |Mapping Summary:
Total  LUTs: 420 (4%)

Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:08s; Memory used current: 77MB peak: 251MB)

Process took 0h:00m:09s realtime, 0h:00m:08s cputime
# Thu Mar 26 10:13:25 2020

###########################################################]
