
Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03G-1-Beta1
Install: E:\Gowin\Gowin_V1.9.3Beta_37257_win\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-001

Implementation : rev_1

# Written on Thu Mar 26 10:12:24 2020

##### FILES SYNTAX CHECKED ##############################################
Constraint File(s):      (none)

#Run constraint checker to find more issues with constraints.
#########################################################################



No issues found in constraint syntax.



Clock Summary
*************

          Start      Requested     Requested     Clock      Clock               Clock
Level     Clock      Frequency     Period        Type       Group               Load 
-------------------------------------------------------------------------------------
0 -       System     936.0 MHz     1.068         system     system_clkgroup     14   
=====================================================================================


Clock Load Summary
******************

           Clock     Source     Clock Pin                        Non-clock Pin     Non-clock Pin
Clock      Load      Pin        Seq Example                      Seq Example       Comb Example 
------------------------------------------------------------------------------------------------
System     14        -          shift_dr_capture_dr_dly[0].C     -                 -            
================================================================================================
