#OPTIONS:"|-layerid|0|-orig_srs|E:\\GOWIN_WORK\\IP_Design\\MIPI\\MIPI_release_case\\MIPI_DPHY_Reference_Design\\MIPI_RefDesign\\impl\\synthesize\\rev_1\\synwork\\MIPI_RefDesign_comp.srs|-top|DPHY_TOP|-prodtype|synplify_pro|-primux|-fixsmult|-sdff_counter|-nram|-divnmod|-nostructver|-gowin|-infer_seqShift|-D_MULTIPLE_FILE_COMPILATION_UNIT_|-I|E:\\GOWIN_WORK\\IP_Design\\MIPI\\MIPI_release_case\\MIPI_DPHY_Reference_Design\\MIPI_RefDesign\\impl\\synthesize\\|-I|E:\\Gowin\\Gowin_V1.9.3Beta_37257_win\\SynplifyPro\\lib|-sysv|-devicelib|E:\\Gowin\\Gowin_V1.9.3Beta_37257_win\\SynplifyPro\\lib\\generic\\gw1n.v|-encrypt|-pro|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-D_MULTIPLE_FILE_COMPILATION_UNIT_|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work"
#CUR:"E:\\Gowin\\Gowin_V1.9.3Beta_37257_win\\SynplifyPro\\bin64\\c_ver.exe":1575393480
#CUR:"E:\\Gowin\\Gowin_V1.9.3Beta_37257_win\\SynplifyPro\\lib\\generic\\gw1n.v":1575572956
#CUR:"E:\\Gowin\\Gowin_V1.9.3Beta_37257_win\\SynplifyPro\\lib\\vlog\\hypermods.v":1575393232
#CUR:"E:\\Gowin\\Gowin_V1.9.3Beta_37257_win\\SynplifyPro\\lib\\vlog\\umr_capim.v":1575393232
#CUR:"E:\\Gowin\\Gowin_V1.9.3Beta_37257_win\\SynplifyPro\\lib\\vlog\\scemi_objects.v":1575393232
#CUR:"E:\\Gowin\\Gowin_V1.9.3Beta_37257_win\\SynplifyPro\\lib\\vlog\\scemi_pipes.svh":1575393232
#CUR:"E:\\GOWIN_WORK\\IP_Design\\MIPI\\MIPI_release_case\\MIPI_DPHY_Reference_Design\\MIPI_RefDesign\\src\\DPHY_TOP.v":1585201313
#CUR:"E:\\GOWIN_WORK\\IP_Design\\MIPI\\MIPI_release_case\\MIPI_DPHY_Reference_Design\\MIPI_RefDesign\\src\\gw_pll.v":1585188171
#CUR:"E:\\GOWIN_WORK\\IP_Design\\MIPI\\MIPI_release_case\\MIPI_DPHY_Reference_Design\\MIPI_RefDesign\\src\\ROM549X17.v":1585537271
#CUR:"E:\\GOWIN_WORK\\IP_Design\\MIPI\\MIPI_release_case\\MIPI_DPHY_Reference_Design\\MIPI_RefDesign\\src\\DPHY_RX_TOP\\DPHY_RX_TOP.v":1585201457
#CUR:"E:\\GOWIN_WORK\\IP_Design\\MIPI\\MIPI_release_case\\MIPI_DPHY_Reference_Design\\MIPI_RefDesign\\src\\DPHY_TX_TOP\\DPHY_TX_TOP.v":1585201514
#numinternalfiles:5
#defaultlanguage:verilog
0			"E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\src\DPHY_TOP.v" verilog
1			"E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\src\gw_pll.v" verilog
2			"E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\src\ROM549X17.v" verilog
3			"E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\src\DPHY_RX_TOP\DPHY_RX_TOP.v" verilog
4			"E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\src\DPHY_TX_TOP\DPHY_TX_TOP.v" verilog
#Dependency Lists(Uses List)
0 1 2 4 3
1 -1
2 -1
3 -1
4 -1
#Dependency Lists(Users Of)
0 -1
1 0
2 0
3 0
4 0
#Design Unit to File Association
module work GW_PLL 1
module work ROM549x17 2
module work DPHY_TX_TOP 4
module work DPHY_RX_TOP 3
module work DPHY_TOP 0
module work \~idesx8.DPHY_RX_TOP_ 3
module work \~word_aligner.DPHY_RX_TOP__6 3
module work \~word_aligner.DPHY_RX_TOP__6_0 3
module work \~word_aligner.DPHY_RX_TOP__6_1 3
module work \~word_aligner.DPHY_RX_TOP__6_2 3
module work \~lane_align_FIFO.DPHY_RX_TOP_ 3
module work \~lane_align_FIFO.DPHY_RX_TOP__3 3
module work \~lane_align_FIFO.DPHY_RX_TOP__4 3
module work \~lane_align_FIFO.DPHY_RX_TOP__5 3
module work \~lane_aligner.DPHY_RX_TOP__4s 3
module work \~Aligner.DPHY_RX_TOP__4s_1s_1s 3
module work \~DPHY_RX.DPHY_RX_TOP_ 3
module work \~pllx8.DPHY_TX_TOP_ 4
module work \~oserx8.DPHY_TX_TOP_ 4
module work \~DPHY_TX.DPHY_TX_TOP_ 4
