<?xml version="1" encoding="UTF-8"?>
<!DOCTYPE gowin-fpga-project>
<Project>
    <Template>FPGA</Template>
    <Version>5</Version>
    <Device>gw1n9-015</Device>
    <FileList>
        <File path="src/DPHY_TOP.v" type="file.verilog" enable="1"/>
        <File path="src/gw_pll.v" type="file.verilog" enable="1"/>
        <File path="src/ROM549X17.v" type="file.verilog" enable="1"/>
        <File path="src/DPHY_RX_TOP/DPHY_RX_TOP.v" type="file.verilog" enable="1"/>
        <File path="src/DPHY_TX_TOP/DPHY_TX_TOP.v" type="file.verilog" enable="1"/>
        <File path="src/mipi.cst" type="file.cst" enable="1"/>
        <File path="src/mipi.sdc" type="file.sdc" enable="1"/>
        <File path="src/mipi.gao" type="file.gao" enable="1"/>
    </FileList>
</Project>
