Timing Analysis Report

# Timing Messages

Report Title | Gowin Timing Analysis Report
Design File | E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\impl\synthesize\rev_1\MIPI_RefDesign.vm
Physical Constraints File | E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\src\mipi.cst
Timing Constraint File | E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\src\mipi.sdc
GOWIN version | V1.9.3Beta
Part Number | GW1N-LV9PG256C5/I4
Created Time | Mon Mar 30 11:17:39 2020
Legal Announcement | Copyright (C)2014-2019 Gowin Semiconductor Corporation. All rights reserved.

# Timing Summaries

## STA Tool Run Summary:

Setup Delay Model | Slow 1.14V 85C
Hold Delay Model | Fast 1.26V 0C
Numbers of Paths Analyzed | 3526
Numbers of Endpoints Analyzed | 3878
Numbers of Falling Endpoints | 1
Numbers of Setup Violated Endpoints | 98
Numbers of Hold Violated Endpoints | 0

## Clock Summary:

Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Objects
--- | --- | --- | --- | --- | --- | --- | --- | ---
clk_tx | Base | 10.000 | 100.000 | 0.000 | 5.000 |  |  | u_DPHY_TX_TOP/DPHY_TX_INST/u_oserx8/U3_CLKDIV/CLKOUT
clk_rx | Base | 10.000 | 100.000 | 0.000 | 5.000 |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
u_plld4/pll_inst/CLKIN.default_clk | Base | 20.000 | 50.000 | 0.000 | 10.000 |  |  |
u_plld4/pll_inst/CLKOUT.default_gen_clk | Generated | 320.000 | 3.125 | 0.000 | 160.000 |  | u_plld4/pll_inst/CLKIN.default_clk |
u_plld4/pll_inst/CLKOUTP.default_gen_clk | Generated | 320.000 | 3.125 | 0.000 | 160.000 |  | u_plld4/pll_inst/CLKIN.default_clk |
u_plld4/pll_inst/CLKOUTD.default_gen_clk | Generated | 640.000 | 1.563 | 0.000 | 320.000 |  | u_plld4/pll_inst/CLKIN.default_clk |
u_plld4/pll_inst/CLKOUTD3.default_gen_clk | Generated | 960.000 | 1.042 | 0.000 | 480.000 |  | u_plld4/pll_inst/CLKIN.default_clk |
u_DPHY_TX_TOP/DPHY_TX_INST/u_pllx8/pll_mipi_tx/CLKOUTP.default_gen_clk | Generated | 40.000 | 25.000 | 10.000 | 30.000 |  | u_plld4/pll_inst/CLKOUT.default_gen_clk |
u_DPHY_TX_TOP/DPHY_TX_INST/u_pllx8/pll_mipi_tx/CLKOUT.default_gen_clk | Generated | 40.000 | 25.000 | 0.000 | 20.000 |  | u_plld4/pll_inst/CLKOUT.default_gen_clk |
u_DPHY_TX_TOP/DPHY_TX_INST/u_pllx8/pll_mipi_tx/CLKOUTD.default_gen_clk | Generated | 80.000 | 12.500 | 0.000 | 40.000 |  | u_plld4/pll_inst/CLKOUT.default_gen_clk |
u_DPHY_TX_TOP/DPHY_TX_INST/u_pllx8/pll_mipi_tx/CLKOUTD3.default_gen_clk | Generated | 120.000 | 8.333 | 0.000 | 60.000 |  | u_plld4/pll_inst/CLKOUT.default_gen_clk |

## Max Frequency Summary:

NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity
--- | --- | --- | --- | --- | ---
1 | clk_tx | 100.000(MHz) | 213.053(MHz) | 1 | TOP
2 | clk_rx | 100.000(MHz) | 68.985(MHz) | 6 | TOP

#### No timing paths to get frequency of u_plld4/pll_inst/CLKIN.default_clk!

#### No timing paths to get frequency of u_plld4/pll_inst/CLKOUT.default_gen_clk!

#### No timing paths to get frequency of u_plld4/pll_inst/CLKOUTP.default_gen_clk!

#### No timing paths to get frequency of u_plld4/pll_inst/CLKOUTD.default_gen_clk!

#### No timing paths to get frequency of u_plld4/pll_inst/CLKOUTD3.default_gen_clk!

#### No timing paths to get frequency of u_DPHY_TX_TOP/DPHY_TX_INST/u_pllx8/pll_mipi_tx/CLKOUTP.default_gen_clk!

#### No timing paths to get frequency of u_DPHY_TX_TOP/DPHY_TX_INST/u_pllx8/pll_mipi_tx/CLKOUT.default_gen_clk!

#### No timing paths to get frequency of u_DPHY_TX_TOP/DPHY_TX_INST/u_pllx8/pll_mipi_tx/CLKOUTD.default_gen_clk!

#### No timing paths to get frequency of u_DPHY_TX_TOP/DPHY_TX_INST/u_pllx8/pll_mipi_tx/CLKOUTD3.default_gen_clk!

## Total Negative Slack Summary:

Clock Name | Analysis Type | Endpoints TNS | Number of Endpoints
--- | --- | --- | ---
clk_tx | Setup | 0.000 | 0
clk_tx | Hold | 0.000 | 0
clk_rx | Setup | -139.683 | 98
clk_rx | Hold | 0.000 | 0
u_plld4/pll_inst/CLKIN.default_clk | Setup | 0.000 | 0
u_plld4/pll_inst/CLKIN.default_clk | Hold | 0.000 | 0
u_plld4/pll_inst/CLKOUT.default_gen_clk | Setup | 0.000 | 0
u_plld4/pll_inst/CLKOUT.default_gen_clk | Hold | 0.000 | 0
u_plld4/pll_inst/CLKOUTP.default_gen_clk | Setup | 0.000 | 0
u_plld4/pll_inst/CLKOUTP.default_gen_clk | Hold | 0.000 | 0
u_plld4/pll_inst/CLKOUTD.default_gen_clk | Setup | 0.000 | 0
u_plld4/pll_inst/CLKOUTD.default_gen_clk | Hold | 0.000 | 0
u_plld4/pll_inst/CLKOUTD3.default_gen_clk | Setup | 0.000 | 0
u_plld4/pll_inst/CLKOUTD3.default_gen_clk | Hold | 0.000 | 0
u_DPHY_TX_TOP/DPHY_TX_INST/u_pllx8/pll_mipi_tx/CLKOUTP.default_gen_clk | Setup | 0.000 | 0
u_DPHY_TX_TOP/DPHY_TX_INST/u_pllx8/pll_mipi_tx/CLKOUTP.default_gen_clk | Hold | 0.000 | 0
u_DPHY_TX_TOP/DPHY_TX_INST/u_pllx8/pll_mipi_tx/CLKOUT.default_gen_clk | Setup | 0.000 | 0
u_DPHY_TX_TOP/DPHY_TX_INST/u_pllx8/pll_mipi_tx/CLKOUT.default_gen_clk | Hold | 0.000 | 0
u_DPHY_TX_TOP/DPHY_TX_INST/u_pllx8/pll_mipi_tx/CLKOUTD.default_gen_clk | Setup | 0.000 | 0
u_DPHY_TX_TOP/DPHY_TX_INST/u_pllx8/pll_mipi_tx/CLKOUTD.default_gen_clk | Hold | 0.000 | 0
u_DPHY_TX_TOP/DPHY_TX_INST/u_pllx8/pll_mipi_tx/CLKOUTD3.default_gen_clk | Setup | 0.000 | 0
u_DPHY_TX_TOP/DPHY_TX_INST/u_pllx8/pll_mipi_tx/CLKOUTD3.default_gen_clk | Hold | 0.000 | 0

# Timing Details

## Path Slacks Table:

### Setup Paths Table

#### Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay
--- | --- | --- | --- | --- | --- | --- | --- | ---
1 | -4.496 | u_la0_top/capture_window_sel_Z[1]/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CE | clk_rx:[R] | clk_rx:[R] | 10.000 | 0.000 | 14.244
2 | -3.980 | u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/Q | u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z/CE | clk_rx:[R] | clk_rx:[R] | 10.000 | 0.000 | 13.728
3 | -3.760 | u_la0_top/triger_level_cnt_Z[1]/Q | u_la0_top/triger_level_cnt_Z[3]/D | clk_rx:[R] | clk_rx:[R] | 10.000 | 0.000 | 13.080
4 | -2.822 | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/shftamt_Z[8]/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/shftamt_Z[4]/CE | clk_rx:[R] | clk_rx:[R] | 10.000 | 0.000 | 12.570
5 | -2.783 | u_la0_top/triger_level_cnt_Z[1]/Q | u_la0_top/triger_level_cnt_Z[0]/D | clk_rx:[R] | clk_rx:[R] | 10.000 | 0.000 | 12.103
6 | -2.783 | u_la0_top/triger_level_cnt_Z[1]/Q | u_la0_top/triger_level_cnt_Z[2]/D | clk_rx:[R] | clk_rx:[R] | 10.000 | 0.000 | 12.103
7 | -2.773 | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/shftamt_Z[3]/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/shftamt_Z[15]/CE | clk_rx:[R] | clk_rx:[R] | 10.000 | 0.000 | 12.521
8 | -2.677 | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/reg0_Z[9]/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/shftamt_Z[4]/CE | clk_rx:[R] | clk_rx:[R] | 10.000 | 0.000 | 12.425
9 | -2.675 | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/shftamt_Z[3]/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/shftamt_Z[5]/CE | clk_rx:[R] | clk_rx:[R] | 10.000 | 0.000 | 12.423
10 | -2.669 | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/reg2_Z[3]/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/shftamt_Z[14]/CE | clk_rx:[R] | clk_rx:[R] | 10.000 | 0.000 | 12.417
11 | -2.520 | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shftamt_Z[5]/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shftamt_Z[6]/CE | clk_rx:[R] | clk_rx:[R] | 10.000 | 0.000 | 12.268
12 | -2.420 | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shftamt_Z[5]/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shftamt_Z[8]/CE | clk_rx:[R] | clk_rx:[R] | 10.000 | 0.000 | 12.168
13 | -2.242 | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/reg1_Z[13]/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/shftamt_Z[9]/CE | clk_rx:[R] | clk_rx:[R] | 10.000 | 0.000 | 11.990
14 | -2.200 | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shftamt_Z[5]/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shftamt_Z[2]/CE | clk_rx:[R] | clk_rx:[R] | 10.000 | 0.000 | 11.948
15 | -2.200 | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shftamt_Z[5]/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shftamt_Z[3]/CE | clk_rx:[R] | clk_rx:[R] | 10.000 | 0.000 | 11.948
16 | -2.155 | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/reg1_Z[11]/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/shftamt_Z[5]/CE | clk_rx:[R] | clk_rx:[R] | 10.000 | 0.000 | 11.903
17 | -2.138 | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg2_Z[15]/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/shftamt_Z[11]/CE | clk_rx:[R] | clk_rx:[R] | 10.000 | 0.000 | 11.886
18 | -2.095 | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shftamt_Z[5]/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shftamt_Z[12]/CE | clk_rx:[R] | clk_rx:[R] | 10.000 | 0.000 | 11.843
19 | -2.064 | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg1_Z[14]/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/shftamt_Z[15]/CE | clk_rx:[R] | clk_rx:[R] | 10.000 | 0.000 | 11.812
20 | -2.055 | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/shftamt_Z[3]/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/shftamt_Z[7]/CE | clk_rx:[R] | clk_rx:[R] | 10.000 | 0.000 | 11.803
21 | -2.053 | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shftamt_Z[5]/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shftamt_Z[14]/CE | clk_rx:[R] | clk_rx:[R] | 10.000 | 0.000 | 11.801
22 | -2.053 | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shftamt_Z[5]/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shftamt_Z[15]/CE | clk_rx:[R] | clk_rx:[R] | 10.000 | 0.000 | 11.801
23 | -1.956 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/D | clk_rx:[R] | clk_rx:[R] | 10.000 | 0.000 | 11.276
24 | -1.956 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/D | clk_rx:[R] | clk_rx:[R] | 10.000 | 0.000 | 11.276
25 | -1.938 | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shftamt_Z[5]/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shftamt_Z[7]/CE | clk_rx:[R] | clk_rx:[R] | 10.000 | 0.000 | 11.686

### Hold Paths Table

#### Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay
--- | --- | --- | --- | --- | --- | --- | --- | ---
1 | 0.678 | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk10.U1/rptr_Z[0]/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk10.U1/wq1_rptr_Z[0]/D | clk_rx:[R] | clk_rx:[R] | 0.000 | 0.000 | 0.678
2 | 0.678 | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/rptr_Z[1]/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/wq1_rptr_Z[1]/D | clk_rx:[R] | clk_rx:[R] | 0.000 | 0.000 | 0.678
3 | 0.678 | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/rptr_Z[0]/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/wq1_rptr_Z[0]/D | clk_rx:[R] | clk_rx:[R] | 0.000 | 0.000 | 0.678
4 | 0.678 | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/out[9]/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk3.q_in2_0[6]/D | clk_rx:[R] | clk_rx:[R] | 0.000 | 0.000 | 0.678
5 | 0.679 | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk12.U3/wbin_Z[1]/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk12.U3/mem.mem_mem_0_0/WAD1 | clk_rx:[R] | clk_rx:[R] | 0.000 | 0.000 | 0.697
6 | 0.682 | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/reg1_Z[4]/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/reg2_Z[4]/D | clk_rx:[R] | clk_rx:[R] | 0.000 | 0.000 | 0.682
7 | 0.682 | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk12.U3/Q[4]/Q | data_out_reg_Z[52]/D | clk_rx:[R] | clk_rx:[R] | 0.000 | 0.000 | 0.682
8 | 0.684 | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk11.U2/wq1_rptr_Z[4]/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk11.U2/wq2_rptr_Z[4]/D | clk_rx:[R] | clk_rx:[R] | 0.000 | 0.000 | 0.684
9 | 0.684 | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk10.U1/rptr_Z[3]/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk10.U1/wq1_rptr_Z[3]/D | clk_rx:[R] | clk_rx:[R] | 0.000 | 0.000 | 0.684
10 | 0.684 | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk10.U1/wq1_rptr_Z[2]/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk10.U1/wq2_rptr_Z[2]/D | clk_rx:[R] | clk_rx:[R] | 0.000 | 0.000 | 0.684
11 | 0.684 | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk10.U1/wq1_rptr_Z[4]/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk10.U1/wq2_rptr_Z[4]/D | clk_rx:[R] | clk_rx:[R] | 0.000 | 0.000 | 0.684
12 | 0.684 | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk10.U1/wq1_rptr_Z[0]/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk10.U1/wq2_rptr_Z[0]/D | clk_rx:[R] | clk_rx:[R] | 0.000 | 0.000 | 0.684
13 | 0.684 | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/wq1_rptr_Z[0]/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/wq2_rptr_Z[0]/D | clk_rx:[R] | clk_rx:[R] | 0.000 | 0.000 | 0.684
14 | 0.684 | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk2.q_in1_0[11]/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk2.q_in1_1[11]/D | clk_rx:[R] | clk_rx:[R] | 0.000 | 0.000 | 0.684
15 | 0.684 | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk1.q_in0_0[15]/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk1.q_in0_1[15]/D | clk_rx:[R] | clk_rx:[R] | 0.000 | 0.000 | 0.684
16 | 0.684 | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk4.q_in3_0[11]/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk4.q_in3_1[11]/D | clk_rx:[R] | clk_rx:[R] | 0.000 | 0.000 | 0.684
17 | 0.684 | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk3.q_in2_0[8]/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk3.q_in2_1[8]/D | clk_rx:[R] | clk_rx:[R] | 0.000 | 0.000 | 0.684
18 | 0.685 | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk1.q_in0_1[15]/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk1.q_in0_2[15]/D | clk_rx:[R] | clk_rx:[R] | 0.000 | 0.000 | 0.685
19 | 0.685 | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk1.q_in0_1[4]/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk1.q_in0_2[4]/D | clk_rx:[R] | clk_rx:[R] | 0.000 | 0.000 | 0.685
20 | 0.685 | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/reg2_Z[0]/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/reg3_Z[0]/D | clk_rx:[R] | clk_rx:[R] | 0.000 | 0.000 | 0.685
21 | 0.685 | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk3.q_in2_1[3]/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk3.q_in2_2[3]/D | clk_rx:[R] | clk_rx:[R] | 0.000 | 0.000 | 0.685
22 | 0.685 | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/reg2_Z[14]/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/reg3_Z[14]/D | clk_rx:[R] | clk_rx:[R] | 0.000 | 0.000 | 0.685
23 | 0.685 | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg2_Z[11]/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg3_fast_Z[11]/D | clk_rx:[R] | clk_rx:[R] | 0.000 | 0.000 | 0.685
24 | 0.685 | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg1_Z[1]/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg2_Z[1]/D | clk_rx:[R] | clk_rx:[R] | 0.000 | 0.000 | 0.685
25 | 0.685 | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg0_Z[8]/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg1_Z[8]/D | clk_rx:[R] | clk_rx:[R] | 0.000 | 0.000 | 0.685

### Recovery Paths Table

#### Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay
--- | --- | --- | --- | --- | --- | --- | --- | ---
1 | 0.559 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLEAR | clk_rx:[F] | clk_rx:[R] | 5.000 | 0.053 | 4.136
2 | 0.559 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/CLEAR | clk_rx:[F] | clk_rx:[R] | 5.000 | 0.053 | 4.136
3 | 0.559 | u_la0_top/rst_ao_Z/Q | u_la0_top/capture_window_sel_Z[1]/CLEAR | clk_rx:[F] | clk_rx:[R] | 5.000 | 0.053 | 4.136
4 | 1.290 | dout1[16]/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg2_Z[1]/CLEAR | clk_tx:[R] | clk_rx:[R] | 10.000 | 0.000 | 8.258
5 | 1.290 | dout1[16]/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg2_Z[4]/CLEAR | clk_tx:[R] | clk_rx:[R] | 10.000 | 0.000 | 8.258
6 | 1.290 | dout1[16]/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg3_fast_Z[2]/CLEAR | clk_tx:[R] | clk_rx:[R] | 10.000 | 0.000 | 8.258
7 | 1.290 | dout1[16]/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/reg2_Z[9]/CLEAR | clk_tx:[R] | clk_rx:[R] | 10.000 | 0.000 | 8.258
8 | 1.290 | dout1[16]/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk4.q_in3_1[15]/CLEAR | clk_tx:[R] | clk_rx:[R] | 10.000 | 0.000 | 8.258
9 | 1.290 | dout1[16]/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk2.q_in1_0[3]/CLEAR | clk_tx:[R] | clk_rx:[R] | 10.000 | 0.000 | 8.258
10 | 1.290 | dout1[16]/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg3_fast_Z[10]/CLEAR | clk_tx:[R] | clk_rx:[R] | 10.000 | 0.000 | 8.258
11 | 1.290 | dout1[16]/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk4.q_in3_1[4]/CLEAR | clk_tx:[R] | clk_rx:[R] | 10.000 | 0.000 | 8.258
12 | 1.290 | dout1[16]/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/reg2_Z[10]/CLEAR | clk_tx:[R] | clk_rx:[R] | 10.000 | 0.000 | 8.258
13 | 1.290 | dout1[16]/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/reg3_fast_Z[10]/CLEAR | clk_tx:[R] | clk_rx:[R] | 10.000 | 0.000 | 8.258
14 | 1.290 | dout1[16]/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/reg3_Z[10]/CLEAR | clk_tx:[R] | clk_rx:[R] | 10.000 | 0.000 | 8.258
15 | 1.290 | dout1[16]/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/reg1_Z[10]/CLEAR | clk_tx:[R] | clk_rx:[R] | 10.000 | 0.000 | 8.258
16 | 1.290 | dout1[16]/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg3_fast_Z[3]/CLEAR | clk_tx:[R] | clk_rx:[R] | 10.000 | 0.000 | 8.258
17 | 1.290 | dout1[16]/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk4.q_in3_2[4]/CLEAR | clk_tx:[R] | clk_rx:[R] | 10.000 | 0.000 | 8.258
18 | 1.290 | dout1[16]/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk4.q_in3_0[15]/CLEAR | clk_tx:[R] | clk_rx:[R] | 10.000 | 0.000 | 8.258
19 | 1.290 | dout1[16]/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg4_fast_Z[2]/CLEAR | clk_tx:[R] | clk_rx:[R] | 10.000 | 0.000 | 8.258
20 | 1.290 | dout1[16]/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg2_Z[3]/CLEAR | clk_tx:[R] | clk_rx:[R] | 10.000 | 0.000 | 8.258
21 | 1.290 | dout1[16]/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/reg3_fast_Z[7]/CLEAR | clk_tx:[R] | clk_rx:[R] | 10.000 | 0.000 | 8.258
22 | 1.290 | dout1[16]/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg3_fast_Z[1]/CLEAR | clk_tx:[R] | clk_rx:[R] | 10.000 | 0.000 | 8.258
23 | 1.290 | dout1[16]/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg3_Z[4]/CLEAR | clk_tx:[R] | clk_rx:[R] | 10.000 | 0.000 | 8.258
24 | 1.290 | dout1[16]/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg1_Z[1]/CLEAR | clk_tx:[R] | clk_rx:[R] | 10.000 | 0.000 | 8.258
25 | 1.290 | dout1[16]/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg3_Z[3]/CLEAR | clk_tx:[R] | clk_rx:[R] | 10.000 | 0.000 | 8.258

### Removal Paths Table

#### Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay
--- | --- | --- | --- | --- | --- | --- | --- | ---
1 | 1.026 | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk3.sync2/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk11.U2/wq2_rptr_Z[3]/CLEAR | clk_rx:[R] | clk_rx:[R] | 0.000 | 0.000 | 1.044
2 | 1.026 | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk3.sync2/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk11.U2/wq1_rptr_Z[4]/CLEAR | clk_rx:[R] | clk_rx:[R] | 0.000 | 0.000 | 1.044
3 | 1.026 | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk3.sync2/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk11.U2/wbin_Z[0]/CLEAR | clk_rx:[R] | clk_rx:[R] | 0.000 | 0.000 | 1.044
4 | 1.026 | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk3.sync2/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk11.U2/wq2_rptr_Z[4]/CLEAR | clk_rx:[R] | clk_rx:[R] | 0.000 | 0.000 | 1.044
5 | 1.044 | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk4.sync3/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk12.U3/rbin_Z[3]/CLEAR | clk_rx:[R] | clk_rx:[R] | 0.000 | 0.000 | 1.062
6 | 1.056 | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk1.sync0/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/rbin_Z[0]/CLEAR | clk_rx:[R] | clk_rx:[R] | 0.000 | 0.000 | 1.074
7 | 1.056 | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk1.sync0/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/wq1_rptr_Z[2]/CLEAR | clk_rx:[R] | clk_rx:[R] | 0.000 | 0.000 | 1.074
8 | 1.056 | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk1.sync0/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/wq1_rptr_Z[0]/CLEAR | clk_rx:[R] | clk_rx:[R] | 0.000 | 0.000 | 1.074
9 | 1.056 | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk1.sync0/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/wq2_rptr_Z[0]/CLEAR | clk_rx:[R] | clk_rx:[R] | 0.000 | 0.000 | 1.074
10 | 1.056 | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk1.sync0/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/wbin_Z[4]/CLEAR | clk_rx:[R] | clk_rx:[R] | 0.000 | 0.000 | 1.074
11 | 1.056 | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk1.sync0/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/wbin_Z[3]/CLEAR | clk_rx:[R] | clk_rx:[R] | 0.000 | 0.000 | 1.074
12 | 1.056 | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk1.sync0/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/wbin_Z[1]/CLEAR | clk_rx:[R] | clk_rx:[R] | 0.000 | 0.000 | 1.074
13 | 1.056 | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk1.sync0/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/rptr_Z[2]/CLEAR | clk_rx:[R] | clk_rx:[R] | 0.000 | 0.000 | 1.074
14 | 1.056 | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk1.sync0/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/rptr_Z[0]/CLEAR | clk_rx:[R] | clk_rx:[R] | 0.000 | 0.000 | 1.074
15 | 1.056 | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk1.sync0/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/rbin_Z[3]/CLEAR | clk_rx:[R] | clk_rx:[R] | 0.000 | 0.000 | 1.074
16 | 1.056 | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk1.sync0/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/rbin_Z[2]/CLEAR | clk_rx:[R] | clk_rx:[R] | 0.000 | 0.000 | 1.074
17 | 1.056 | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk1.sync0/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/rbin_Z[1]/CLEAR | clk_rx:[R] | clk_rx:[R] | 0.000 | 0.000 | 1.074
18 | 1.329 | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk2.sync1/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk10.U1/rbin_Z[3]/CLEAR | clk_rx:[R] | clk_rx:[R] | 0.000 | 0.000 | 1.347
19 | 1.343 | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk3.sync2/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk11.U2/Full_Z/CLEAR | clk_rx:[R] | clk_rx:[R] | 0.000 | 0.000 | 1.361
20 | 1.343 | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk3.sync2/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk11.U2/wq2_rptr_Z[1]/CLEAR | clk_rx:[R] | clk_rx:[R] | 0.000 | 0.000 | 1.361
21 | 1.343 | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk3.sync2/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk11.U2/wq2_rptr_Z[0]/CLEAR | clk_rx:[R] | clk_rx:[R] | 0.000 | 0.000 | 1.361
22 | 1.343 | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk3.sync2/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk11.U2/wbin_Z[3]/CLEAR | clk_rx:[R] | clk_rx:[R] | 0.000 | 0.000 | 1.361
23 | 1.343 | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk3.sync2/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk11.U2/wbin_Z[2]/CLEAR | clk_rx:[R] | clk_rx:[R] | 0.000 | 0.000 | 1.361
24 | 1.343 | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk3.sync2/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk11.U2/wbin_Z[1]/CLEAR | clk_rx:[R] | clk_rx:[R] | 0.000 | 0.000 | 1.361
25 | 1.368 | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk1.sync0/Q | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/wbin_Z[0]/CLEAR | clk_rx:[R] | clk_rx:[R] | 0.000 | 0.000 | 1.386

## Minimum Pulse Width Table:

Number | Slack | Actual Width | Required Width | Type | Clock | Objects
--- | --- | --- | --- | --- | --- | ---

#### Report Command:report_min_pulse_width -nworst 10 -detail

1 | 2.877 | 4.377 | 1.500 | Low Pulse Width | clk_rx | data_out_reg_Z[3]
2 | 2.877 | 4.377 | 1.500 | Low Pulse Width | clk_rx | data_out_reg_Z[1]
3 | 2.877 | 4.377 | 1.500 | Low Pulse Width | clk_rx | data_out_reg_Z[16]
4 | 2.877 | 4.377 | 1.500 | Low Pulse Width | clk_rx | data_out_reg_Z[8]
5 | 2.877 | 4.377 | 1.500 | Low Pulse Width | clk_rx | data_out_reg_Z[22]
6 | 2.877 | 4.377 | 1.500 | Low Pulse Width | clk_rx | data_out_reg_Z[50]
7 | 2.877 | 4.377 | 1.500 | Low Pulse Width | clk_rx | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/reg3_Z[3]
8 | 2.877 | 4.377 | 1.500 | Low Pulse Width | clk_rx | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/reg1_Z[8]
9 | 2.877 | 4.377 | 1.500 | Low Pulse Width | clk_rx | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/out[7]
10 | 2.877 | 4.377 | 1.500 | Low Pulse Width | clk_tx | u_ROM549x17/addr_Z[6]

## Timing Report By Analysis Type:

### Setup Analysis Report

#### Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

### Path1

Path Summary:

Slack | -4.496
Data Arrival Time | 16.535
Data Required Time | 12.039
From | u_la0_top/capture_window_sel_Z[1]
To | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z
Launch Clk | clk_rx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
2.291 | 2.291 | tNET | RR | 1 | R8C4[1][A] | u_la0_top/capture_window_sel_Z[1]/CLK
2.841 | 0.550 | tC2Q | RF | 5 | R8C4[1][A] | u_la0_top/capture_window_sel_Z[1]/Q
5.204 | 2.363 | tNET | FF | 1 | R6C2[1][A] | u_la0_top/un6_start_reg_c2_cZ/I1
6.167 | 0.962 | tINS | FR | 1 | R6C2[1][A] | u_la0_top/un6_start_reg_c2_cZ/F
6.669 | 0.503 | tNET | RR | 1 | R6C2[1][B] | u_la0_top/un6_start_reg_ac0_5_0_cZ/I3
7.908 | 1.238 | tINS | RF | 4 | R6C2[1][B] | u_la0_top/un6_start_reg_ac0_5_0_cZ/F
10.443 | 2.535 | tNET | FF | 1 | R2C5[3][A] | u_la0_top/start_reg_cZ/I2
11.716 | 1.273 | tINS | FR | 2 | R2C5[3][A] | u_la0_top/start_reg_cZ/F
12.221 | 0.505 | tNET | RR | 1 | R3C5[2][B] | u_la0_top/u_ao_mem_ctrl/un1_start_reg_N_3L3/I1
13.459 | 1.238 | tINS | RF | 1 | R3C5[2][B] | u_la0_top/u_ao_mem_ctrl/un1_start_reg_N_3L3/F
13.863 | 0.404 | tNET | FF | 1 | R3C5[3][A] | u_la0_top/u_ao_mem_ctrl/un1_start_reg_cZ/I2
15.136 | 1.273 | tINS | FR | 1 | R3C5[3][A] | u_la0_top/u_ao_mem_ctrl/un1_start_reg_cZ/F
16.535 | 1.399 | tNET | RR | 1 | R4C5[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | clk_rx
10.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.291 | 2.291 | tNET | RR | 1 | R4C5[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLK
12.091 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z
12.039 | -0.052 | tSu |  | 1 | R4C5[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 6
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%
Arrival Data Path Delay | cell: 5.986, 42.022%; route: 7.708, 54.117%; tC2Q: 0.550, 3.861%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%

### Path2

Path Summary:

Slack | -3.980
Data Arrival Time | 16.019
Data Required Time | 12.039
From | u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]
To | u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z
Launch Clk | clk_rx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
2.291 | 2.291 | tNET | RR | 1 | R4C10[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/CLK
2.841 | 0.550 | tC2Q | RF | 2 | R4C10[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/Q
5.387 | 2.546 | tNET | FF | 2 | R2C2[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_zero_cry_1_0/I0
6.641 | 1.254 | tINS | FF | 1 | R2C2[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_zero_cry_1_0/COUT
6.641 | 0.000 | tNET | FF | 2 | R2C2[2][A] | u_la0_top/u_ao_mem_ctrl/capture_length_zero_cry_2_0/CIN
6.709 | 0.068 | tINS | FF | 1 | R2C2[2][A] | u_la0_top/u_ao_mem_ctrl/capture_length_zero_cry_2_0/COUT
6.709 | 0.000 | tNET | FF | 2 | R2C2[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_zero_cry_3_0/CIN
6.778 | 0.068 | tINS | FF | 1 | R2C2[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_zero_cry_3_0/COUT
6.778 | 0.000 | tNET | FF | 2 | R2C3[0][A] | u_la0_top/u_ao_mem_ctrl/capture_length_zero_cry_4_0/CIN
6.846 | 0.068 | tINS | FF | 1 | R2C3[0][A] | u_la0_top/u_ao_mem_ctrl/capture_length_zero_cry_4_0/COUT
6.846 | 0.000 | tNET | FF | 2 | R2C3[0][B] | u_la0_top/u_ao_mem_ctrl/capture_length_zero_cry_5_0/CIN
6.915 | 0.068 | tINS | FF | 1 | R2C3[0][B] | u_la0_top/u_ao_mem_ctrl/capture_length_zero_cry_5_0/COUT
6.915 | 0.000 | tNET | FF | 2 | R2C3[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_zero_cry_6_0/CIN
6.983 | 0.068 | tINS | FF | 1 | R2C3[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_zero_cry_6_0/COUT
6.983 | 0.000 | tNET | FF | 2 | R2C3[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_zero_cry_7_0/CIN
7.659 | 0.676 | tINS | FF | 1 | R2C3[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_zero_cry_7_0/SUM
8.828 | 1.170 | tNET | FF | 1 | R2C3[3][B] | u_la0_top/u_ao_mem_ctrl/capture_length_zero_1_6_cZ/I3
10.059 | 1.231 | tINS | FR | 2 | R2C3[3][B] | u_la0_top/u_ao_mem_ctrl/capture_length_zero_1_6_cZ/F
10.564 | 0.505 | tNET | RR | 1 | R2C3[3][A] | u_la0_top/u_ao_mem_ctrl/un1_capture_length_zero_1_cZ/I2
11.883 | 1.319 | tINS | RF | 1 | R2C3[3][A] | u_la0_top/u_ao_mem_ctrl/un1_capture_length_zero_1_cZ/F
12.848 | 0.965 | tNET | FF | 1 | R2C5[3][B] | u_la0_top/u_ao_mem_ctrl/un1_capture_length_zero_cZ/I2
14.121 | 1.273 | tINS | FR | 1 | R2C5[3][B] | u_la0_top/u_ao_mem_ctrl/un1_capture_length_zero_cZ/F
16.019 | 1.897 | tNET | RR | 1 | R5C4[2][A] | u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | clk_rx
10.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.291 | 2.291 | tNET | RR | 1 | R5C4[2][A] | u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z/CLK
12.091 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z
12.039 | -0.052 | tSu |  | 1 | R5C4[2][A] | u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 6
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%
Arrival Data Path Delay | cell: 6.095, 44.398%; route: 7.083, 51.596%; tC2Q: 0.550, 4.006%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%

### Path3

Path Summary:

Slack | -3.760
Data Arrival Time | 15.370
Data Required Time | 11.611
From | u_la0_top/triger_level_cnt_Z[1]
To | u_la0_top/triger_level_cnt_Z[3]
Launch Clk | clk_rx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
2.291 | 2.291 | tNET | RR | 1 | R4C9[1][A] | u_la0_top/triger_level_cnt_Z[1]/CLK
2.841 | 0.550 | tC2Q | RF | 5 | R4C9[1][A] | u_la0_top/triger_level_cnt_Z[1]/Q
5.204 | 2.363 | tNET | FF | 1 | R7C2[2][A] | u_la0_top/un1_match_final_3_cZ/I2
6.435 | 1.231 | tINS | FR | 1 | R7C2[2][A] | u_la0_top/un1_match_final_3_cZ/F
6.938 | 0.503 | tNET | RR | 1 | R7C3[1][A] | u_la0_top/un1_match_final_cZ/I3
8.257 | 1.319 | tINS | RF | 4 | R7C3[1][A] | u_la0_top/un1_match_final_cZ/F
9.830 | 1.573 | tNET | FF | 1 | R5C2[2][A] | u_la0_top/un1_triger_level_cnt12_cZ/I2
11.069 | 1.238 | tINS | FF | 3 | R5C2[2][A] | u_la0_top/un1_triger_level_cnt12_cZ/F
14.384 | 3.315 | tNET | FF | 1 | R7C6[0][B] | u_la0_top/triger_level_cnt_4_cZ[3]/I3
15.370 | 0.986 | tINS | FF | 1 | R7C6[0][B] | u_la0_top/triger_level_cnt_4_cZ[3]/F
15.370 | 0.000 | tNET | FF | 1 | R7C6[0][B] | u_la0_top/triger_level_cnt_Z[3]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | clk_rx
10.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.291 | 2.291 | tNET | RR | 1 | R7C6[0][B] | u_la0_top/triger_level_cnt_Z[3]/CLK
12.091 | -0.200 | tUnc |  |  |  | u_la0_top/triger_level_cnt_Z[3]
11.611 | -0.480 | tSu |  | 1 | R7C6[0][B] | u_la0_top/triger_level_cnt_Z[3]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 5
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%
Arrival Data Path Delay | cell: 4.775, 36.505%; route: 7.755, 59.290%; tC2Q: 0.550, 4.205%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%

### Path4

Path Summary:

Slack | -2.822
Data Arrival Time | 14.861
Data Required Time | 12.039
From | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/shftamt_Z[8]
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/shftamt_Z[4]
Launch Clk | clk_rx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
2.291 | 2.291 | tNET | RR | 1 | R13C18[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/shftamt_Z[8]/CLK
2.841 | 0.550 | tC2Q | RF | 19 | R13C18[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/shftamt_Z[8]/Q
4.452 | 1.612 | tNET | FF | 1 | R11C20[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/shiftflag_5_0_cZ/I2
5.771 | 1.319 | tINS | FF | 1 | R11C20[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/shiftflag_5_0_cZ/F
6.175 | 0.404 | tNET | FF | 1 | R11C20[1][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/shiftflag_cZ/I3
7.161 | 0.986 | tINS | FF | 19 | R11C20[1][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/shiftflag_cZ/F
8.198 | 1.037 | tNET | FF | 1 | R11C23[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/m56_0_a2_0_58_cZ/I2
9.517 | 1.319 | tINS | FF | 13 | R11C23[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/m56_0_a2_0_58_cZ/F
11.307 | 1.790 | tNET | FF | 1 | R13C18[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/m25_0_a2/I3
12.580 | 1.273 | tINS | FR | 1 | R13C18[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/m25_0_a2/F
14.861 | 2.281 | tNET | RR | 1 | R13C18[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/shftamt_Z[4]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | clk_rx
10.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.291 | 2.291 | tNET | RR | 1 | R13C18[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/shftamt_Z[4]/CLK
12.091 | -0.200 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/shftamt_Z[4]
12.039 | -0.052 | tSu |  | 1 | R13C18[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/shftamt_Z[4]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 5
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%
Arrival Data Path Delay | cell: 4.897, 38.960%; route: 7.123, 56.665%; tC2Q: 0.550, 4.376%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%

### Path5

Path Summary:

Slack | -2.783
Data Arrival Time | 14.394
Data Required Time | 11.611
From | u_la0_top/triger_level_cnt_Z[1]
To | u_la0_top/triger_level_cnt_Z[0]
Launch Clk | clk_rx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
2.291 | 2.291 | tNET | RR | 1 | R4C9[1][A] | u_la0_top/triger_level_cnt_Z[1]/CLK
2.841 | 0.550 | tC2Q | RF | 5 | R4C9[1][A] | u_la0_top/triger_level_cnt_Z[1]/Q
5.204 | 2.363 | tNET | FF | 1 | R7C2[2][A] | u_la0_top/un1_match_final_3_cZ/I2
6.435 | 1.231 | tINS | FR | 1 | R7C2[2][A] | u_la0_top/un1_match_final_3_cZ/F
6.938 | 0.503 | tNET | RR | 1 | R7C3[1][A] | u_la0_top/un1_match_final_cZ/I3
8.257 | 1.319 | tINS | RF | 4 | R7C3[1][A] | u_la0_top/un1_match_final_cZ/F
9.830 | 1.573 | tNET | FF | 1 | R5C2[2][A] | u_la0_top/un1_triger_level_cnt12_cZ/I2
11.069 | 1.238 | tINS | FF | 3 | R5C2[2][A] | u_la0_top/un1_triger_level_cnt12_cZ/F
13.408 | 2.339 | tNET | FF | 1 | R4C9[0][B] | u_la0_top/triger_level_cnt_4_cZ[0]/I3
14.394 | 0.986 | tINS | FF | 1 | R4C9[0][B] | u_la0_top/triger_level_cnt_4_cZ[0]/F
14.394 | 0.000 | tNET | FF | 1 | R4C9[0][B] | u_la0_top/triger_level_cnt_Z[0]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | clk_rx
10.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.291 | 2.291 | tNET | RR | 1 | R4C9[0][B] | u_la0_top/triger_level_cnt_Z[0]/CLK
12.091 | -0.200 | tUnc |  |  |  | u_la0_top/triger_level_cnt_Z[0]
11.611 | -0.480 | tSu |  | 1 | R4C9[0][B] | u_la0_top/triger_level_cnt_Z[0]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 5
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%
Arrival Data Path Delay | cell: 4.775, 39.451%; route: 6.778, 56.005%; tC2Q: 0.550, 4.544%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%

### Path6

Path Summary:

Slack | -2.783
Data Arrival Time | 14.394
Data Required Time | 11.611
From | u_la0_top/triger_level_cnt_Z[1]
To | u_la0_top/triger_level_cnt_Z[2]
Launch Clk | clk_rx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
2.291 | 2.291 | tNET | RR | 1 | R4C9[1][A] | u_la0_top/triger_level_cnt_Z[1]/CLK
2.841 | 0.550 | tC2Q | RF | 5 | R4C9[1][A] | u_la0_top/triger_level_cnt_Z[1]/Q
5.204 | 2.363 | tNET | FF | 1 | R7C2[2][A] | u_la0_top/un1_match_final_3_cZ/I2
6.435 | 1.231 | tINS | FR | 1 | R7C2[2][A] | u_la0_top/un1_match_final_3_cZ/F
6.938 | 0.503 | tNET | RR | 1 | R7C3[1][A] | u_la0_top/un1_match_final_cZ/I3
8.257 | 1.319 | tINS | RF | 4 | R7C3[1][A] | u_la0_top/un1_match_final_cZ/F
9.830 | 1.573 | tNET | FF | 1 | R5C2[2][A] | u_la0_top/un1_triger_level_cnt12_cZ/I2
11.069 | 1.238 | tINS | FF | 3 | R5C2[2][A] | u_la0_top/un1_triger_level_cnt12_cZ/F
13.408 | 2.339 | tNET | FF | 1 | R4C9[1][B] | u_la0_top/triger_level_cnt_4_cZ[2]/I2
14.394 | 0.986 | tINS | FF | 1 | R4C9[1][B] | u_la0_top/triger_level_cnt_4_cZ[2]/F
14.394 | 0.000 | tNET | FF | 1 | R4C9[1][B] | u_la0_top/triger_level_cnt_Z[2]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | clk_rx
10.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.291 | 2.291 | tNET | RR | 1 | R4C9[1][B] | u_la0_top/triger_level_cnt_Z[2]/CLK
12.091 | -0.200 | tUnc |  |  |  | u_la0_top/triger_level_cnt_Z[2]
11.611 | -0.480 | tSu |  | 1 | R4C9[1][B] | u_la0_top/triger_level_cnt_Z[2]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 5
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%
Arrival Data Path Delay | cell: 4.775, 39.451%; route: 6.778, 56.005%; tC2Q: 0.550, 4.544%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%

### Path7

Path Summary:

Slack | -2.773
Data Arrival Time | 14.812
Data Required Time | 12.039
From | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/shftamt_Z[3]
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/shftamt_Z[15]
Launch Clk | clk_rx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
2.291 | 2.291 | tNET | RR | 1 | R8C11[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/shftamt_Z[3]/CLK
2.841 | 0.550 | tC2Q | RF | 2 | R8C11[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/shftamt_Z[3]/Q
4.391 | 1.550 | tNET | FF | 1 | R11C10[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/shiftflag_3_0_cZ/I1
5.142 | 0.751 | tINS | FF | 1 | R11C10[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/shiftflag_3_0_cZ/F
6.127 | 0.985 | tNET | FF | 1 | R11C8[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/shiftflag_cZ/I1
7.446 | 1.319 | tINS | FF | 21 | R11C8[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/shiftflag_cZ/F
9.079 | 1.633 | tNET | FF | 1 | R11C13[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/m56_0_a2_0_58_cZ/I3
9.830 | 0.751 | tINS | FF | 11 | R11C13[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/m56_0_a2_0_58_cZ/F
12.182 | 2.352 | tNET | FF | 1 | R8C8[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/m56_0_a2/I1
13.413 | 1.231 | tINS | FR | 1 | R8C8[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/m56_0_a2/F
14.812 | 1.399 | tNET | RR | 1 | R11C8[2][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/shftamt_Z[15]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | clk_rx
10.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.291 | 2.291 | tNET | RR | 1 | R11C8[2][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/shftamt_Z[15]/CLK
12.091 | -0.200 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/shftamt_Z[15]
12.039 | -0.052 | tSu |  | 1 | R11C8[2][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/shftamt_Z[15]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 5
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%
Arrival Data Path Delay | cell: 4.052, 32.365%; route: 7.919, 63.242%; tC2Q: 0.550, 4.393%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%

### Path8

Path Summary:

Slack | -2.677
Data Arrival Time | 14.716
Data Required Time | 12.039
From | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/reg0_Z[9]
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/shftamt_Z[4]
Launch Clk | clk_rx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
2.291 | 2.291 | tNET | RR | 1 | R8C15[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/reg0_Z[9]/CLK
2.841 | 0.550 | tC2Q | RF | 8 | R8C15[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/reg0_Z[9]/Q
5.180 | 2.339 | tNET | FF | 1 | R17C12[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/m25_0_a2_1/I1
6.498 | 1.319 | tINS | FF | 3 | R17C12[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/m25_0_a2_1/F
9.617 | 3.119 | tNET | FF | 1 | R16C11[3][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/m25_0_a2_N_2L1/I0
10.855 | 1.238 | tINS | FF | 1 | R16C11[3][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/m25_0_a2_N_2L1/F
10.862 | 0.007 | tNET | FF | 1 | R16C11[1][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/m25_0_a2/I0
12.093 | 1.231 | tINS | FR | 1 | R16C11[1][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/m25_0_a2/F
14.716 | 2.623 | tNET | RR | 1 | R16C11[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/shftamt_Z[4]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | clk_rx
10.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.291 | 2.291 | tNET | RR | 1 | R16C11[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/shftamt_Z[4]/CLK
12.091 | -0.200 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/shftamt_Z[4]
12.039 | -0.052 | tSu |  | 1 | R16C11[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/shftamt_Z[4]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 4
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%
Arrival Data Path Delay | cell: 3.788, 30.490%; route: 8.087, 65.084%; tC2Q: 0.550, 4.427%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%

### Path9

Path Summary:

Slack | -2.675
Data Arrival Time | 14.714
Data Required Time | 12.039
From | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/shftamt_Z[3]
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/shftamt_Z[5]
Launch Clk | clk_rx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
2.291 | 2.291 | tNET | RR | 1 | R8C11[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/shftamt_Z[3]/CLK
2.841 | 0.550 | tC2Q | RF | 2 | R8C11[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/shftamt_Z[3]/Q
4.391 | 1.550 | tNET | FF | 1 | R11C10[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/shiftflag_3_0_cZ/I1
5.142 | 0.751 | tINS | FF | 1 | R11C10[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/shiftflag_3_0_cZ/F
6.127 | 0.985 | tNET | FF | 1 | R11C8[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/shiftflag_cZ/I1
7.446 | 1.319 | tINS | FF | 21 | R11C8[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/shiftflag_cZ/F
9.079 | 1.633 | tNET | FF | 1 | R11C13[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/m56_0_a2_0_58_cZ/I3
9.830 | 0.751 | tINS | FF | 11 | R11C13[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/m56_0_a2_0_58_cZ/F
11.031 | 1.201 | tNET | FF | 1 | R11C11[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/m71_0_a2/I1
11.994 | 0.962 | tINS | FR | 1 | R11C11[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/m71_0_a2/F
14.714 | 2.720 | tNET | RR | 1 | R11C11[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/shftamt_Z[5]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | clk_rx
10.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.291 | 2.291 | tNET | RR | 1 | R11C11[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/shftamt_Z[5]/CLK
12.091 | -0.200 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/shftamt_Z[5]
12.039 | -0.052 | tSu |  | 1 | R11C11[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/shftamt_Z[5]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 5
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%
Arrival Data Path Delay | cell: 3.784, 30.457%; route: 8.089, 65.116%; tC2Q: 0.550, 4.427%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%

### Path10

Path Summary:

Slack | -2.669
Data Arrival Time | 14.708
Data Required Time | 12.039
From | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/reg2_Z[3]
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/shftamt_Z[14]
Launch Clk | clk_rx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
2.291 | 2.291 | tNET | RR | 1 | R18C17[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/reg2_Z[3]/CLK
2.841 | 0.550 | tC2Q | RF | 3 | R18C17[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/reg2_Z[3]/Q
4.799 | 1.959 | tNET | FF | 1 | R18C12[1][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/m56_0_a2_0_56_17_cZ/I2
6.118 | 1.319 | tINS | FF | 1 | R18C12[1][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/m56_0_a2_0_56_17_cZ/F
7.103 | 0.985 | tNET | FF | 1 | R20C12[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/m56_0_a2_0_56_25_cZ/I1
8.090 | 0.986 | tINS | FF | 2 | R20C12[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/m56_0_a2_0_56_25_cZ/F
9.060 | 0.971 | tNET | FF | 1 | R18C11[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/m56_0_a2_0_58_cZ/I1
10.047 | 0.986 | tINS | FF | 13 | R18C11[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/m56_0_a2_0_58_cZ/F
11.065 | 1.018 | tNET | FF | 1 | R17C10[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/m61_0_a2/I1
12.027 | 0.962 | tINS | FR | 1 | R17C10[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/m61_0_a2/F
14.708 | 2.680 | tNET | RR | 1 | R17C11[2][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/shftamt_Z[14]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | clk_rx
10.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.291 | 2.291 | tNET | RR | 1 | R17C11[2][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/shftamt_Z[14]/CLK
12.091 | -0.200 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/shftamt_Z[14]
12.039 | -0.052 | tSu |  | 1 | R17C11[2][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/shftamt_Z[14]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 5
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%
Arrival Data Path Delay | cell: 4.254, 34.260%; route: 7.613, 61.311%; tC2Q: 0.550, 4.429%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%

### Path11

Path Summary:

Slack | -2.520
Data Arrival Time | 14.559
Data Required Time | 12.039
From | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shftamt_Z[5]
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shftamt_Z[6]
Launch Clk | clk_rx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
2.291 | 2.291 | tNET | RR | 1 | R18C22[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shftamt_Z[5]/CLK
2.841 | 0.550 | tC2Q | RF | 3 | R18C22[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shftamt_Z[5]/Q
5.170 | 2.329 | tNET | FF | 1 | R18C20[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shiftflag_3_0_cZ/I2
6.408 | 1.238 | tINS | FF | 1 | R18C20[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shiftflag_3_0_cZ/F
6.415 | 0.007 | tNET | FF | 1 | R18C20[1][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shiftflag_cZ/I1
7.733 | 1.319 | tINS | FF | 18 | R18C20[1][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shiftflag_cZ/F
9.353 | 1.620 | tNET | FF | 1 | R17C23[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/m56_0_a2_0_58_cZ/I2
10.592 | 1.238 | tINS | FF | 13 | R17C23[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/m56_0_a2_0_58_cZ/F
12.950 | 2.359 | tNET | FF | 1 | R20C18[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/m42_0_a2/I2
13.700 | 0.750 | tINS | FR | 1 | R20C18[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/m42_0_a2/F
14.559 | 0.858 | tNET | RR | 1 | R20C18[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shftamt_Z[6]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | clk_rx
10.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.291 | 2.291 | tNET | RR | 1 | R20C18[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shftamt_Z[6]/CLK
12.091 | -0.200 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shftamt_Z[6]
12.039 | -0.052 | tSu |  | 1 | R20C18[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shftamt_Z[6]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 5
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%
Arrival Data Path Delay | cell: 4.546, 37.053%; route: 7.172, 58.464%; tC2Q: 0.550, 4.483%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%

### Path12

Path Summary:

Slack | -2.420
Data Arrival Time | 14.458
Data Required Time | 12.039
From | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shftamt_Z[5]
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shftamt_Z[8]
Launch Clk | clk_rx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
2.291 | 2.291 | tNET | RR | 1 | R18C22[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shftamt_Z[5]/CLK
2.841 | 0.550 | tC2Q | RF | 3 | R18C22[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shftamt_Z[5]/Q
5.170 | 2.329 | tNET | FF | 1 | R18C20[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shiftflag_3_0_cZ/I2
6.408 | 1.238 | tINS | FF | 1 | R18C20[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shiftflag_3_0_cZ/F
6.415 | 0.007 | tNET | FF | 1 | R18C20[1][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shiftflag_cZ/I1
7.733 | 1.319 | tINS | FF | 18 | R18C20[1][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shiftflag_cZ/F
9.353 | 1.620 | tNET | FF | 1 | R17C23[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/m56_0_a2_0_58_cZ/I2
10.592 | 1.238 | tINS | FF | 13 | R17C23[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/m56_0_a2_0_58_cZ/F
12.369 | 1.777 | tNET | FF | 1 | R20C19[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/m53_m6_e/I3
13.600 | 1.231 | tINS | FR | 1 | R20C19[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/m53_m6_e/F
14.458 | 0.858 | tNET | RR | 1 | R20C19[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shftamt_Z[8]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | clk_rx
10.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.291 | 2.291 | tNET | RR | 1 | R20C19[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shftamt_Z[8]/CLK
12.091 | -0.200 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shftamt_Z[8]
12.039 | -0.052 | tSu |  | 1 | R20C19[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shftamt_Z[8]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 5
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%
Arrival Data Path Delay | cell: 5.027, 41.313%; route: 6.591, 54.167%; tC2Q: 0.550, 4.520%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%

### Path13

Path Summary:

Slack | -2.242
Data Arrival Time | 14.280
Data Required Time | 12.039
From | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/reg1_Z[13]
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/shftamt_Z[9]
Launch Clk | clk_rx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
2.291 | 2.291 | tNET | RR | 1 | R11C12[2][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/reg1_Z[13]/CLK
2.841 | 0.550 | tC2Q | RF | 2 | R11C12[2][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/reg1_Z[13]/Q
4.014 | 1.173 | tNET | FF | 1 | R11C16[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/m56_0_a2_0_57_21_cZ/I0
5.000 | 0.986 | tINS | FF | 1 | R11C16[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/m56_0_a2_0_57_21_cZ/F
5.965 | 0.965 | tNET | FF | 1 | R11C14[2][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/m56_0_a2_0_57_29_cZ/I1
7.204 | 1.238 | tINS | FF | 2 | R11C14[2][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/m56_0_a2_0_57_29_cZ/F
8.182 | 0.979 | tNET | FF | 1 | R11C11[2][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/m56_0_a2_0_57_cZ/I1
8.934 | 0.751 | tINS | FF | 8 | R11C11[2][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/m56_0_a2_0_57_cZ/F
10.327 | 1.394 | tNET | FF | 1 | R11C10[1][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/m100_0_a2/I2
11.558 | 1.231 | tINS | FR | 1 | R11C10[1][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/m100_0_a2/F
14.280 | 2.722 | tNET | RR | 1 | R11C9[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/shftamt_Z[9]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | clk_rx
10.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.291 | 2.291 | tNET | RR | 1 | R11C9[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/shftamt_Z[9]/CLK
12.091 | -0.200 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/shftamt_Z[9]
12.039 | -0.052 | tSu |  | 1 | R11C9[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/shftamt_Z[9]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 5
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%
Arrival Data Path Delay | cell: 4.207, 35.091%; route: 7.232, 60.322%; tC2Q: 0.550, 4.587%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%

### Path14

Path Summary:

Slack | -2.200
Data Arrival Time | 14.239
Data Required Time | 12.039
From | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shftamt_Z[5]
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shftamt_Z[2]
Launch Clk | clk_rx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
2.291 | 2.291 | tNET | RR | 1 | R18C22[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shftamt_Z[5]/CLK
2.841 | 0.550 | tC2Q | RF | 3 | R18C22[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shftamt_Z[5]/Q
5.170 | 2.329 | tNET | FF | 1 | R18C20[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shiftflag_3_0_cZ/I2
6.408 | 1.238 | tINS | FF | 1 | R18C20[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shiftflag_3_0_cZ/F
6.415 | 0.007 | tNET | FF | 1 | R18C20[1][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shiftflag_cZ/I1
7.733 | 1.319 | tINS | FF | 18 | R18C20[1][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shiftflag_cZ/F
9.353 | 1.620 | tNET | FF | 1 | R17C23[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/m56_0_a2_0_58_cZ/I2
10.592 | 1.238 | tINS | FF | 13 | R17C23[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/m56_0_a2_0_58_cZ/F
11.609 | 1.017 | tNET | FF | 1 | R20C23[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/m82_0_a2/I1
12.840 | 1.231 | tINS | FR | 1 | R20C23[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/m82_0_a2/F
14.239 | 1.399 | tNET | RR | 1 | R21C24[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shftamt_Z[2]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | clk_rx
10.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.291 | 2.291 | tNET | RR | 1 | R21C24[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shftamt_Z[2]/CLK
12.091 | -0.200 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shftamt_Z[2]
12.039 | -0.052 | tSu |  | 1 | R21C24[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shftamt_Z[2]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 5
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%
Arrival Data Path Delay | cell: 5.027, 42.073%; route: 6.371, 53.324%; tC2Q: 0.550, 4.603%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%

### Path15

Path Summary:

Slack | -2.200
Data Arrival Time | 14.239
Data Required Time | 12.039
From | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shftamt_Z[5]
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shftamt_Z[3]
Launch Clk | clk_rx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
2.291 | 2.291 | tNET | RR | 1 | R18C22[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shftamt_Z[5]/CLK
2.841 | 0.550 | tC2Q | RF | 3 | R18C22[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shftamt_Z[5]/Q
5.170 | 2.329 | tNET | FF | 1 | R18C20[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shiftflag_3_0_cZ/I2
6.408 | 1.238 | tINS | FF | 1 | R18C20[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shiftflag_3_0_cZ/F
6.415 | 0.007 | tNET | FF | 1 | R18C20[1][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shiftflag_cZ/I1
7.733 | 1.319 | tINS | FF | 18 | R18C20[1][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shiftflag_cZ/F
9.353 | 1.620 | tNET | FF | 1 | R17C23[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/m56_0_a2_0_58_cZ/I2
10.592 | 1.238 | tINS | FF | 13 | R17C23[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/m56_0_a2_0_58_cZ/F
11.609 | 1.017 | tNET | FF | 1 | R18C21[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/m31_0_a2/I3
12.840 | 1.231 | tINS | FR | 1 | R18C21[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/m31_0_a2/F
14.239 | 1.399 | tNET | RR | 1 | R18C20[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shftamt_Z[3]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | clk_rx
10.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.291 | 2.291 | tNET | RR | 1 | R18C20[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shftamt_Z[3]/CLK
12.091 | -0.200 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shftamt_Z[3]
12.039 | -0.052 | tSu |  | 1 | R18C20[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shftamt_Z[3]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 5
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%
Arrival Data Path Delay | cell: 5.027, 42.073%; route: 6.371, 53.324%; tC2Q: 0.550, 4.603%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%

### Path16

Path Summary:

Slack | -2.155
Data Arrival Time | 14.194
Data Required Time | 12.039
From | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/reg1_Z[11]
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/shftamt_Z[5]
Launch Clk | clk_rx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
2.291 | 2.291 | tNET | RR | 1 | R18C10[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/reg1_Z[11]/CLK
2.841 | 0.550 | tC2Q | RF | 2 | R18C10[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/reg1_Z[11]/Q
4.595 | 1.754 | tNET | FF | 1 | R18C15[2][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/m56_0_a2_0_57_19_cZ/I3
5.833 | 1.238 | tINS | FF | 1 | R18C15[2][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/m56_0_a2_0_57_19_cZ/F
6.799 | 0.965 | tNET | FF | 1 | R18C12[2][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/m56_0_a2_0_57_28_cZ/I3
8.117 | 1.319 | tINS | FF | 3 | R18C12[2][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/m56_0_a2_0_57_28_cZ/F
8.718 | 0.600 | tNET | FF | 1 | R18C10[2][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/m25_m6_e_3_cZ/I2
9.680 | 0.962 | tINS | FR | 8 | R18C10[2][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/m25_m6_e_3_cZ/F
10.199 | 0.519 | tNET | RR | 1 | R18C11[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/m71_0_a2/I0
11.472 | 1.273 | tINS | RR | 1 | R18C11[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/m71_0_a2/F
14.194 | 2.722 | tNET | RR | 1 | R18C11[2][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/shftamt_Z[5]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | clk_rx
10.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.291 | 2.291 | tNET | RR | 1 | R18C11[2][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/shftamt_Z[5]/CLK
12.091 | -0.200 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/shftamt_Z[5]
12.039 | -0.052 | tSu |  | 1 | R18C11[2][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/shftamt_Z[5]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 5
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%
Arrival Data Path Delay | cell: 4.793, 40.265%; route: 6.560, 55.115%; tC2Q: 0.550, 4.621%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%

### Path17

Path Summary:

Slack | -2.138
Data Arrival Time | 14.176
Data Required Time | 12.039
From | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg2_Z[15]
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/shftamt_Z[11]
Launch Clk | clk_rx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
2.291 | 2.291 | tNET | RR | 1 | R9C24[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg2_Z[15]/CLK
2.841 | 0.550 | tC2Q | RF | 4 | R9C24[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg2_Z[15]/Q
4.600 | 1.760 | tNET | FF | 1 | R14C23[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/m56_0_a2_0_56_14_cZ/I2
5.839 | 1.238 | tINS | FF | 1 | R14C23[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/m56_0_a2_0_56_14_cZ/F
6.804 | 0.965 | tNET | FF | 1 | R11C23[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/m56_0_a2_0_56_24_cZ/I0
8.123 | 1.319 | tINS | FF | 2 | R11C23[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/m56_0_a2_0_56_24_cZ/F
8.136 | 0.013 | tNET | FF | 1 | R11C23[2][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/m96_m3_e_4_cZ/I0
9.374 | 1.238 | tINS | FF | 3 | R11C23[2][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/m96_m3_e_4_cZ/F
10.933 | 1.559 | tNET | FF | 1 | R11C19[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/m96_0_a2/I1
11.896 | 0.962 | tINS | FR | 1 | R11C19[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/m96_0_a2/F
14.176 | 2.281 | tNET | RR | 1 | R11C19[2][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/shftamt_Z[11]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | clk_rx
10.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.291 | 2.291 | tNET | RR | 1 | R11C19[2][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/shftamt_Z[11]/CLK
12.091 | -0.200 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/shftamt_Z[11]
12.039 | -0.052 | tSu |  | 1 | R11C19[2][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/shftamt_Z[11]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 5
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%
Arrival Data Path Delay | cell: 4.758, 40.032%; route: 6.578, 55.341%; tC2Q: 0.550, 4.627%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%

### Path18

Path Summary:

Slack | -2.095
Data Arrival Time | 14.134
Data Required Time | 12.039
From | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shftamt_Z[5]
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shftamt_Z[12]
Launch Clk | clk_rx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
2.291 | 2.291 | tNET | RR | 1 | R18C22[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shftamt_Z[5]/CLK
2.841 | 0.550 | tC2Q | RF | 3 | R18C22[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shftamt_Z[5]/Q
5.170 | 2.329 | tNET | FF | 1 | R18C20[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shiftflag_3_0_cZ/I2
6.408 | 1.238 | tINS | FF | 1 | R18C20[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shiftflag_3_0_cZ/F
6.415 | 0.007 | tNET | FF | 1 | R18C20[1][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shiftflag_cZ/I1
7.733 | 1.319 | tINS | FF | 18 | R18C20[1][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shiftflag_cZ/F
9.353 | 1.620 | tNET | FF | 1 | R17C23[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/m56_0_a2_0_58_cZ/I2
10.592 | 1.238 | tINS | FF | 13 | R17C23[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/m56_0_a2_0_58_cZ/F
12.003 | 1.411 | tNET | FF | 1 | R18C19[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shftamt128_0_a2/I1
13.276 | 1.273 | tINS | FR | 1 | R18C19[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shftamt128_0_a2/F
14.134 | 0.858 | tNET | RR | 1 | R18C19[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shftamt_Z[12]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | clk_rx
10.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.291 | 2.291 | tNET | RR | 1 | R18C19[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shftamt_Z[12]/CLK
12.091 | -0.200 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shftamt_Z[12]
12.039 | -0.052 | tSu |  | 1 | R18C19[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shftamt_Z[12]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 5
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%
Arrival Data Path Delay | cell: 5.069, 42.799%; route: 6.225, 52.557%; tC2Q: 0.550, 4.644%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%

### Path19

Path Summary:

Slack | -2.064
Data Arrival Time | 14.102
Data Required Time | 12.039
From | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg1_Z[14]
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/shftamt_Z[15]
Launch Clk | clk_rx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
2.291 | 2.291 | tNET | RR | 1 | R11C23[2][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg1_Z[14]/CLK
2.841 | 0.550 | tC2Q | RF | 2 | R11C23[2][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg1_Z[14]/Q
5.374 | 2.533 | tNET | FF | 1 | R11C24[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/m56_0_a2_0_57_16_cZ/I1
6.124 | 0.750 | tINS | FR | 1 | R11C24[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/m56_0_a2_0_57_16_cZ/F
6.627 | 0.503 | tNET | RR | 1 | R11C25[3][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/m56_0_a2_0_57_28_cZ/I0
7.378 | 0.751 | tINS | RF | 3 | R11C25[3][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/m56_0_a2_0_57_28_cZ/F
7.977 | 0.599 | tNET | FF | 1 | R11C23[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/m56_0_a2_0_57_cZ/I0
9.215 | 1.238 | tINS | FF | 5 | R11C23[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/m56_0_a2_0_57_cZ/F
11.572 | 2.357 | tNET | FF | 1 | R13C18[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/m56_0_a2/I0
12.803 | 1.231 | tINS | FR | 1 | R13C18[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/m56_0_a2/F
14.102 | 1.299 | tNET | RR | 1 | R12C18[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/shftamt_Z[15]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | clk_rx
10.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.291 | 2.291 | tNET | RR | 1 | R12C18[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/shftamt_Z[15]/CLK
12.091 | -0.200 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/shftamt_Z[15]
12.039 | -0.052 | tSu |  | 1 | R12C18[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/shftamt_Z[15]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 5
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%
Arrival Data Path Delay | cell: 3.971, 33.618%; route: 7.291, 61.726%; tC2Q: 0.550, 4.656%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%

### Path20

Path Summary:

Slack | -2.055
Data Arrival Time | 14.094
Data Required Time | 12.039
From | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/shftamt_Z[3]
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/shftamt_Z[7]
Launch Clk | clk_rx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
2.291 | 2.291 | tNET | RR | 1 | R8C11[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/shftamt_Z[3]/CLK
2.841 | 0.550 | tC2Q | RF | 2 | R8C11[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/shftamt_Z[3]/Q
4.391 | 1.550 | tNET | FF | 1 | R11C10[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/shiftflag_3_0_cZ/I1
5.142 | 0.751 | tINS | FF | 1 | R11C10[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/shiftflag_3_0_cZ/F
6.127 | 0.985 | tNET | FF | 1 | R11C8[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/shiftflag_cZ/I1
7.446 | 1.319 | tINS | FF | 21 | R11C8[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/shiftflag_cZ/F
9.079 | 1.633 | tNET | FF | 1 | R11C13[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/m56_0_a2_0_58_cZ/I3
9.830 | 0.751 | tINS | FF | 11 | R11C13[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/m56_0_a2_0_58_cZ/F
10.450 | 0.620 | tNET | FF | 1 | R11C11[3][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/m57_0_a2/I1
11.200 | 0.750 | tINS | FR | 1 | R11C11[3][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/m57_0_a2/F
14.094 | 2.894 | tNET | RR | 1 | R11C10[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/shftamt_Z[7]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | clk_rx
10.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.291 | 2.291 | tNET | RR | 1 | R11C10[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/shftamt_Z[7]/CLK
12.091 | -0.200 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/shftamt_Z[7]
12.039 | -0.052 | tSu |  | 1 | R11C10[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/shftamt_Z[7]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 5
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%
Arrival Data Path Delay | cell: 3.571, 30.256%; route: 7.682, 65.084%; tC2Q: 0.550, 4.660%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%

### Path21

Path Summary:

Slack | -2.053
Data Arrival Time | 14.092
Data Required Time | 12.039
From | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shftamt_Z[5]
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shftamt_Z[14]
Launch Clk | clk_rx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
2.291 | 2.291 | tNET | RR | 1 | R18C22[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shftamt_Z[5]/CLK
2.841 | 0.550 | tC2Q | RF | 3 | R18C22[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shftamt_Z[5]/Q
5.170 | 2.329 | tNET | FF | 1 | R18C20[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shiftflag_3_0_cZ/I2
6.408 | 1.238 | tINS | FF | 1 | R18C20[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shiftflag_3_0_cZ/F
6.415 | 0.007 | tNET | FF | 1 | R18C20[1][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shiftflag_cZ/I1
7.733 | 1.319 | tINS | FF | 18 | R18C20[1][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shiftflag_cZ/F
9.353 | 1.620 | tNET | FF | 1 | R17C23[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/m56_0_a2_0_58_cZ/I2
10.592 | 1.238 | tINS | FF | 13 | R17C23[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/m56_0_a2_0_58_cZ/F
12.003 | 1.411 | tNET | FF | 1 | R18C19[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/m61_0_a2/I1
13.234 | 1.231 | tINS | FR | 1 | R18C19[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/m61_0_a2/F
14.092 | 0.858 | tNET | RR | 1 | R18C19[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shftamt_Z[14]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | clk_rx
10.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.291 | 2.291 | tNET | RR | 1 | R18C19[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shftamt_Z[14]/CLK
12.091 | -0.200 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shftamt_Z[14]
12.039 | -0.052 | tSu |  | 1 | R18C19[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shftamt_Z[14]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 5
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%
Arrival Data Path Delay | cell: 5.027, 42.595%; route: 6.225, 52.744%; tC2Q: 0.550, 4.660%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%

### Path22

Path Summary:

Slack | -2.053
Data Arrival Time | 14.092
Data Required Time | 12.039
From | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shftamt_Z[5]
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shftamt_Z[15]
Launch Clk | clk_rx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
2.291 | 2.291 | tNET | RR | 1 | R18C22[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shftamt_Z[5]/CLK
2.841 | 0.550 | tC2Q | RF | 3 | R18C22[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shftamt_Z[5]/Q
5.170 | 2.329 | tNET | FF | 1 | R18C20[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shiftflag_3_0_cZ/I2
6.408 | 1.238 | tINS | FF | 1 | R18C20[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shiftflag_3_0_cZ/F
6.415 | 0.007 | tNET | FF | 1 | R18C20[1][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shiftflag_cZ/I1
7.733 | 1.319 | tINS | FF | 18 | R18C20[1][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shiftflag_cZ/F
9.353 | 1.620 | tNET | FF | 1 | R17C23[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/m56_0_a2_0_58_cZ/I2
10.592 | 1.238 | tINS | FF | 13 | R17C23[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/m56_0_a2_0_58_cZ/F
12.003 | 1.411 | tNET | FF | 1 | R18C19[1][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/m56_0_a2/I1
13.234 | 1.231 | tINS | FR | 1 | R18C19[1][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/m56_0_a2/F
14.092 | 0.858 | tNET | RR | 1 | R18C19[2][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shftamt_Z[15]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | clk_rx
10.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.291 | 2.291 | tNET | RR | 1 | R18C19[2][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shftamt_Z[15]/CLK
12.091 | -0.200 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shftamt_Z[15]
12.039 | -0.052 | tSu |  | 1 | R18C19[2][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shftamt_Z[15]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 5
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%
Arrival Data Path Delay | cell: 5.027, 42.595%; route: 6.225, 52.744%; tC2Q: 0.550, 4.660%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%

### Path23

Path Summary:

Slack | -1.956
Data Arrival Time | 13.567
Data Required Time | 11.611
From | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]
Launch Clk | clk_rx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
2.291 | 2.291 | tNET | RR | 1 | R5C8[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLK
2.841 | 0.550 | tC2Q | RF | 6 | R5C8[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/Q
5.973 | 3.133 | tNET | FF | 1 | R2C2[3][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr8_0_I_8_cZ/I0
7.247 | 1.273 | tINS | FR | 1 | R2C2[3][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr8_0_I_8_cZ/F
7.749 | 0.503 | tNET | RR | 2 | R3C2[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr8_0_I_1_0/I1
8.409 | 0.660 | tINS | RR | 1 | R3C2[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr8_0_I_1_0/COUT
8.409 | 0.000 | tNET | RR | 2 | R3C2[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr8_0_I_9_0/CIN
8.478 | 0.068 | tINS | RF | 1 | R3C2[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr8_0_I_9_0/COUT
8.478 | 0.000 | tNET | FF | 2 | R3C2[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr8_0_I_15_0/CIN
8.546 | 0.068 | tINS | FF | 1 | R3C2[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr8_0_I_15_0/COUT
8.546 | 0.000 | tNET | FF | 2 | R3C2[2][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr8_0_I_27_0/CIN
8.614 | 0.068 | tINS | FF | 1 | R3C2[2][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr8_0_I_27_0/COUT
8.614 | 0.000 | tNET | FF | 2 | R3C3[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr8_0_I_45_0/CIN
8.683 | 0.068 | tINS | FF | 1 | R3C3[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr8_0_I_45_0/COUT
8.683 | 0.000 | tNET | FF | 2 | R3C3[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr8_0_I_33_0/CIN
8.751 | 0.068 | tINS | FF | 1 | R3C3[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr8_0_I_33_0/COUT
8.751 | 0.000 | tNET | FF | 2 | R3C3[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr8_0_I_39_0/CIN
8.820 | 0.068 | tINS | FF | 1 | R3C3[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr8_0_I_39_0/COUT
8.820 | 0.000 | tNET | FF | 2 | R3C3[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr8_0_I_21_0/CIN
8.888 | 0.068 | tINS | FF | 11 | R3C3[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr8_0_I_21_0/COUT
12.329 | 3.441 | tNET | FF | 1 | R8C5[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_lm_0[5]/I1
13.567 | 1.238 | tINS | FF | 1 | R8C5[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_lm_0[5]/F
13.567 | 0.000 | tNET | FF | 1 | R8C5[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | clk_rx
10.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.291 | 2.291 | tNET | RR | 1 | R8C5[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLK
12.091 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]
11.611 | -0.480 | tSu |  | 1 | R8C5[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 5
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%
Arrival Data Path Delay | cell: 3.650, 32.372%; route: 7.076, 62.750%; tC2Q: 0.550, 4.878%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%

### Path24

Path Summary:

Slack | -1.956
Data Arrival Time | 13.567
Data Required Time | 11.611
From | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]
Launch Clk | clk_rx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
2.291 | 2.291 | tNET | RR | 1 | R5C8[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLK
2.841 | 0.550 | tC2Q | RF | 6 | R5C8[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/Q
5.973 | 3.133 | tNET | FF | 1 | R2C2[3][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr8_0_I_8_cZ/I0
7.247 | 1.273 | tINS | FR | 1 | R2C2[3][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr8_0_I_8_cZ/F
7.749 | 0.503 | tNET | RR | 2 | R3C2[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr8_0_I_1_0/I1
8.409 | 0.660 | tINS | RR | 1 | R3C2[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr8_0_I_1_0/COUT
8.409 | 0.000 | tNET | RR | 2 | R3C2[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr8_0_I_9_0/CIN
8.478 | 0.068 | tINS | RF | 1 | R3C2[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr8_0_I_9_0/COUT
8.478 | 0.000 | tNET | FF | 2 | R3C2[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr8_0_I_15_0/CIN
8.546 | 0.068 | tINS | FF | 1 | R3C2[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr8_0_I_15_0/COUT
8.546 | 0.000 | tNET | FF | 2 | R3C2[2][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr8_0_I_27_0/CIN
8.614 | 0.068 | tINS | FF | 1 | R3C2[2][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr8_0_I_27_0/COUT
8.614 | 0.000 | tNET | FF | 2 | R3C3[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr8_0_I_45_0/CIN
8.683 | 0.068 | tINS | FF | 1 | R3C3[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr8_0_I_45_0/COUT
8.683 | 0.000 | tNET | FF | 2 | R3C3[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr8_0_I_33_0/CIN
8.751 | 0.068 | tINS | FF | 1 | R3C3[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr8_0_I_33_0/COUT
8.751 | 0.000 | tNET | FF | 2 | R3C3[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr8_0_I_39_0/CIN
8.820 | 0.068 | tINS | FF | 1 | R3C3[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr8_0_I_39_0/COUT
8.820 | 0.000 | tNET | FF | 2 | R3C3[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr8_0_I_21_0/CIN
8.888 | 0.068 | tINS | FF | 11 | R3C3[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr8_0_I_21_0/COUT
12.329 | 3.441 | tNET | FF | 1 | R8C5[2][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_lm_0[7]/I1
13.567 | 1.238 | tINS | FF | 1 | R8C5[2][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_lm_0[7]/F
13.567 | 0.000 | tNET | FF | 1 | R8C5[2][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | clk_rx
10.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.291 | 2.291 | tNET | RR | 1 | R8C5[2][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLK
12.091 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]
11.611 | -0.480 | tSu |  | 1 | R8C5[2][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 5
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%
Arrival Data Path Delay | cell: 3.650, 32.372%; route: 7.076, 62.750%; tC2Q: 0.550, 4.878%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%

### Path25

Path Summary:

Slack | -1.938
Data Arrival Time | 13.977
Data Required Time | 12.039
From | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shftamt_Z[5]
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shftamt_Z[7]
Launch Clk | clk_rx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
2.291 | 2.291 | tNET | RR | 1 | R18C22[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shftamt_Z[5]/CLK
2.841 | 0.550 | tC2Q | RF | 3 | R18C22[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shftamt_Z[5]/Q
5.170 | 2.329 | tNET | FF | 1 | R18C20[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shiftflag_3_0_cZ/I2
6.408 | 1.238 | tINS | FF | 1 | R18C20[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shiftflag_3_0_cZ/F
6.415 | 0.007 | tNET | FF | 1 | R18C20[1][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shiftflag_cZ/I1
7.733 | 1.319 | tINS | FF | 18 | R18C20[1][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shiftflag_cZ/F
9.353 | 1.620 | tNET | FF | 1 | R17C23[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/m56_0_a2_0_58_cZ/I2
10.592 | 1.238 | tINS | FF | 13 | R17C23[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/m56_0_a2_0_58_cZ/F
12.369 | 1.777 | tNET | FF | 1 | R18C18[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/m57_0_a2/I1
13.119 | 0.750 | tINS | FR | 1 | R18C18[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/m57_0_a2/F
13.977 | 0.858 | tNET | RR | 1 | R18C18[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shftamt_Z[7]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | clk_rx
10.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.291 | 2.291 | tNET | RR | 1 | R18C18[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shftamt_Z[7]/CLK
12.091 | -0.200 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shftamt_Z[7]
12.039 | -0.052 | tSu |  | 1 | R18C18[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/shftamt_Z[7]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 5
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%
Arrival Data Path Delay | cell: 4.546, 38.897%; route: 6.591, 56.397%; tC2Q: 0.550, 4.706%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%

### Hold Analysis Report

#### Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

### Path1

Path Summary:

Slack | 0.678
Data Arrival Time | 2.398
Data Required Time | 1.721
From | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk10.U1/rptr_Z[0]
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk10.U1/wq1_rptr_Z[0]
Launch Clk | clk_rx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R12C35[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk10.U1/rptr_Z[0]/CLK
2.121 | 0.400 | tC2Q | RF | 1 | R12C35[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk10.U1/rptr_Z[0]/Q
2.398 | 0.278 | tNET | FF | 1 | R12C35[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk10.U1/wq1_rptr_Z[0]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R12C35[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk10.U1/wq1_rptr_Z[0]/CLK
1.721 | 0.000 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk10.U1/wq1_rptr_Z[0]
1.721 | 0.000 | tHld |  | 1 | R12C35[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk10.U1/wq1_rptr_Z[0]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.278, 40.967%; tC2Q: 0.400, 59.033%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%

### Path2

Path Summary:

Slack | 0.678
Data Arrival Time | 2.398
Data Required Time | 1.721
From | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/rptr_Z[1]
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/wq1_rptr_Z[1]
Launch Clk | clk_rx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R17C36[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/rptr_Z[1]/CLK
2.121 | 0.400 | tC2Q | RF | 1 | R17C36[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/rptr_Z[1]/Q
2.398 | 0.278 | tNET | FF | 1 | R17C35[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/wq1_rptr_Z[1]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R17C35[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/wq1_rptr_Z[1]/CLK
1.721 | 0.000 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/wq1_rptr_Z[1]
1.721 | 0.000 | tHld |  | 1 | R17C35[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/wq1_rptr_Z[1]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.278, 40.967%; tC2Q: 0.400, 59.033%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%

### Path3

Path Summary:

Slack | 0.678
Data Arrival Time | 2.398
Data Required Time | 1.721
From | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/rptr_Z[0]
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/wq1_rptr_Z[0]
Launch Clk | clk_rx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R20C36[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/rptr_Z[0]/CLK
2.121 | 0.400 | tC2Q | RF | 1 | R20C36[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/rptr_Z[0]/Q
2.398 | 0.278 | tNET | FF | 1 | R20C35[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/wq1_rptr_Z[0]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R20C35[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/wq1_rptr_Z[0]/CLK
1.721 | 0.000 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/wq1_rptr_Z[0]
1.721 | 0.000 | tHld |  | 1 | R20C35[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/wq1_rptr_Z[0]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.278, 40.967%; tC2Q: 0.400, 59.033%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%

### Path4

Path Summary:

Slack | 0.678
Data Arrival Time | 2.398
Data Required Time | 1.721
From | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/out[9]
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk3.q_in2_0[6]
Launch Clk | clk_rx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R15C17[1][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/out[9]/CLK
2.121 | 0.400 | tC2Q | RF | 1 | R15C17[1][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/out[9]/Q
2.398 | 0.278 | tNET | FF | 1 | R15C18[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk3.q_in2_0[6]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R15C18[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk3.q_in2_0[6]/CLK
1.721 | 0.000 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk3.q_in2_0[6]
1.721 | 0.000 | tHld |  | 1 | R15C18[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk3.q_in2_0[6]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.278, 40.967%; tC2Q: 0.400, 59.033%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%

### Path5

Path Summary:

Slack | 0.679
Data Arrival Time | 2.418
Data Required Time | 1.739
From | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk12.U3/wbin_Z[1]
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk12.U3/mem.mem_mem_0_0
Launch Clk | clk_rx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R15C30[2][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk12.U3/wbin_Z[1]/CLK
2.121 | 0.400 | tC2Q | RF | 8 | R15C30[2][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk12.U3/wbin_Z[1]/Q
2.418 | 0.297 | tNET | FF | 1 | R14C30 | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk12.U3/mem.mem_mem_0_0/WAD1

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R14C30 | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk12.U3/mem.mem_mem_0_0/CLK
1.721 | 0.000 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk12.U3/mem.mem_mem_0_0
1.739 | 0.018 | tHld |  | 1 | R14C30 | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk12.U3/mem.mem_mem_0_0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.297, 42.642%; tC2Q: 0.400, 57.358%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%

### Path6

Path Summary:

Slack | 0.682
Data Arrival Time | 2.402
Data Required Time | 1.721
From | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/reg1_Z[4]
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/reg2_Z[4]
Launch Clk | clk_rx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R11C12[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/reg1_Z[4]/CLK
2.121 | 0.400 | tC2Q | RF | 2 | R11C12[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/reg1_Z[4]/Q
2.402 | 0.282 | tNET | FF | 1 | R11C12[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/reg2_Z[4]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R11C12[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/reg2_Z[4]/CLK
1.721 | 0.000 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/reg2_Z[4]
1.721 | 0.000 | tHld |  | 1 | R11C12[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/reg2_Z[4]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.282, 41.310%; tC2Q: 0.400, 58.690%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%

### Path7

Path Summary:

Slack | 0.682
Data Arrival Time | 2.402
Data Required Time | 1.721
From | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk12.U3/Q[4]
To | data_out_reg_Z[52]
Launch Clk | clk_rx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R15C32[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk12.U3/Q[4]/CLK
2.121 | 0.400 | tC2Q | RF | 2 | R15C32[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk12.U3/Q[4]/Q
2.402 | 0.282 | tNET | FF | 1 | R15C33[0][A] | data_out_reg_Z[52]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R15C33[0][A] | data_out_reg_Z[52]/CLK
1.721 | 0.000 | tUnc |  |  |  | data_out_reg_Z[52]
1.721 | 0.000 | tHld |  | 1 | R15C33[0][A] | data_out_reg_Z[52]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.282, 41.310%; tC2Q: 0.400, 58.690%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%

### Path8

Path Summary:

Slack | 0.684
Data Arrival Time | 2.404
Data Required Time | 1.721
From | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk11.U2/wq1_rptr_Z[4]
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk11.U2/wq2_rptr_Z[4]
Launch Clk | clk_rx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R16C36[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk11.U2/wq1_rptr_Z[4]/CLK
2.121 | 0.400 | tC2Q | RR | 1 | R16C36[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk11.U2/wq1_rptr_Z[4]/Q
2.404 | 0.284 | tNET | RR | 1 | R16C36[1][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk11.U2/wq2_rptr_Z[4]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R16C36[1][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk11.U2/wq2_rptr_Z[4]/CLK
1.721 | 0.000 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk11.U2/wq2_rptr_Z[4]
1.721 | 0.000 | tHld |  | 1 | R16C36[1][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk11.U2/wq2_rptr_Z[4]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.284, 41.492%; tC2Q: 0.400, 58.508%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%

### Path9

Path Summary:

Slack | 0.684
Data Arrival Time | 2.404
Data Required Time | 1.721
From | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk10.U1/rptr_Z[3]
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk10.U1/wq1_rptr_Z[3]
Launch Clk | clk_rx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R11C35[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk10.U1/rptr_Z[3]/CLK
2.121 | 0.400 | tC2Q | RR | 1 | R11C35[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk10.U1/rptr_Z[3]/Q
2.404 | 0.284 | tNET | RR | 1 | R11C35[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk10.U1/wq1_rptr_Z[3]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R11C35[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk10.U1/wq1_rptr_Z[3]/CLK
1.721 | 0.000 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk10.U1/wq1_rptr_Z[3]
1.721 | 0.000 | tHld |  | 1 | R11C35[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk10.U1/wq1_rptr_Z[3]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.284, 41.492%; tC2Q: 0.400, 58.508%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%

### Path10

Path Summary:

Slack | 0.684
Data Arrival Time | 2.404
Data Required Time | 1.721
From | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk10.U1/wq1_rptr_Z[2]
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk10.U1/wq2_rptr_Z[2]
Launch Clk | clk_rx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R12C34[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk10.U1/wq1_rptr_Z[2]/CLK
2.121 | 0.400 | tC2Q | RR | 1 | R12C34[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk10.U1/wq1_rptr_Z[2]/Q
2.404 | 0.284 | tNET | RR | 1 | R12C34[2][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk10.U1/wq2_rptr_Z[2]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R12C34[2][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk10.U1/wq2_rptr_Z[2]/CLK
1.721 | 0.000 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk10.U1/wq2_rptr_Z[2]
1.721 | 0.000 | tHld |  | 1 | R12C34[2][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk10.U1/wq2_rptr_Z[2]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.284, 41.492%; tC2Q: 0.400, 58.508%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%

### Path11

Path Summary:

Slack | 0.684
Data Arrival Time | 2.404
Data Required Time | 1.721
From | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk10.U1/wq1_rptr_Z[4]
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk10.U1/wq2_rptr_Z[4]
Launch Clk | clk_rx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R11C34[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk10.U1/wq1_rptr_Z[4]/CLK
2.121 | 0.400 | tC2Q | RR | 1 | R11C34[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk10.U1/wq1_rptr_Z[4]/Q
2.404 | 0.284 | tNET | RR | 1 | R11C34[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk10.U1/wq2_rptr_Z[4]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R11C34[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk10.U1/wq2_rptr_Z[4]/CLK
1.721 | 0.000 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk10.U1/wq2_rptr_Z[4]
1.721 | 0.000 | tHld |  | 1 | R11C34[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk10.U1/wq2_rptr_Z[4]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.284, 41.492%; tC2Q: 0.400, 58.508%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%

### Path12

Path Summary:

Slack | 0.684
Data Arrival Time | 2.404
Data Required Time | 1.721
From | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk10.U1/wq1_rptr_Z[0]
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk10.U1/wq2_rptr_Z[0]
Launch Clk | clk_rx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R12C35[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk10.U1/wq1_rptr_Z[0]/CLK
2.121 | 0.400 | tC2Q | RR | 1 | R12C35[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk10.U1/wq1_rptr_Z[0]/Q
2.404 | 0.284 | tNET | RR | 1 | R12C35[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk10.U1/wq2_rptr_Z[0]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R12C35[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk10.U1/wq2_rptr_Z[0]/CLK
1.721 | 0.000 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk10.U1/wq2_rptr_Z[0]
1.721 | 0.000 | tHld |  | 1 | R12C35[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk10.U1/wq2_rptr_Z[0]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.284, 41.492%; tC2Q: 0.400, 58.508%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%

### Path13

Path Summary:

Slack | 0.684
Data Arrival Time | 2.404
Data Required Time | 1.721
From | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/wq1_rptr_Z[0]
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/wq2_rptr_Z[0]
Launch Clk | clk_rx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R20C35[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/wq1_rptr_Z[0]/CLK
2.121 | 0.400 | tC2Q | RR | 1 | R20C35[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/wq1_rptr_Z[0]/Q
2.404 | 0.284 | tNET | RR | 1 | R20C35[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/wq2_rptr_Z[0]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R20C35[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/wq2_rptr_Z[0]/CLK
1.721 | 0.000 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/wq2_rptr_Z[0]
1.721 | 0.000 | tHld |  | 1 | R20C35[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/wq2_rptr_Z[0]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.284, 41.492%; tC2Q: 0.400, 58.508%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%

### Path14

Path Summary:

Slack | 0.684
Data Arrival Time | 2.404
Data Required Time | 1.721
From | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk2.q_in1_0[11]
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk2.q_in1_1[11]
Launch Clk | clk_rx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R12C28[1][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk2.q_in1_0[11]/CLK
2.121 | 0.400 | tC2Q | RR | 1 | R12C28[1][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk2.q_in1_0[11]/Q
2.404 | 0.284 | tNET | RR | 1 | R12C28[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk2.q_in1_1[11]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R12C28[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk2.q_in1_1[11]/CLK
1.721 | 0.000 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk2.q_in1_1[11]
1.721 | 0.000 | tHld |  | 1 | R12C28[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk2.q_in1_1[11]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.284, 41.492%; tC2Q: 0.400, 58.508%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%

### Path15

Path Summary:

Slack | 0.684
Data Arrival Time | 2.404
Data Required Time | 1.721
From | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk1.q_in0_0[15]
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk1.q_in0_1[15]
Launch Clk | clk_rx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R17C33[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk1.q_in0_0[15]/CLK
2.121 | 0.400 | tC2Q | RR | 1 | R17C33[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk1.q_in0_0[15]/Q
2.404 | 0.284 | tNET | RR | 1 | R17C33[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk1.q_in0_1[15]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R17C33[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk1.q_in0_1[15]/CLK
1.721 | 0.000 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk1.q_in0_1[15]
1.721 | 0.000 | tHld |  | 1 | R17C33[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk1.q_in0_1[15]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.284, 41.492%; tC2Q: 0.400, 58.508%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%

### Path16

Path Summary:

Slack | 0.684
Data Arrival Time | 2.404
Data Required Time | 1.721
From | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk4.q_in3_0[11]
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk4.q_in3_1[11]
Launch Clk | clk_rx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R11C32[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk4.q_in3_0[11]/CLK
2.121 | 0.400 | tC2Q | RR | 1 | R11C32[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk4.q_in3_0[11]/Q
2.404 | 0.284 | tNET | RR | 1 | R11C32[2][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk4.q_in3_1[11]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R11C32[2][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk4.q_in3_1[11]/CLK
1.721 | 0.000 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk4.q_in3_1[11]
1.721 | 0.000 | tHld |  | 1 | R11C32[2][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk4.q_in3_1[11]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.284, 41.492%; tC2Q: 0.400, 58.508%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%

### Path17

Path Summary:

Slack | 0.684
Data Arrival Time | 2.404
Data Required Time | 1.721
From | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk3.q_in2_0[8]
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk3.q_in2_1[8]
Launch Clk | clk_rx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R16C29[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk3.q_in2_0[8]/CLK
2.121 | 0.400 | tC2Q | RR | 1 | R16C29[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk3.q_in2_0[8]/Q
2.404 | 0.284 | tNET | RR | 1 | R16C29[2][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk3.q_in2_1[8]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R16C29[2][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk3.q_in2_1[8]/CLK
1.721 | 0.000 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk3.q_in2_1[8]
1.721 | 0.000 | tHld |  | 1 | R16C29[2][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk3.q_in2_1[8]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.284, 41.492%; tC2Q: 0.400, 58.508%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%

### Path18

Path Summary:

Slack | 0.685
Data Arrival Time | 2.406
Data Required Time | 1.721
From | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk1.q_in0_1[15]
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk1.q_in0_2[15]
Launch Clk | clk_rx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R17C33[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk1.q_in0_1[15]/CLK
2.121 | 0.400 | tC2Q | RR | 2 | R17C33[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk1.q_in0_1[15]/Q
2.406 | 0.285 | tNET | RR | 1 | R17C33[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk1.q_in0_2[15]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R17C33[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk1.q_in0_2[15]/CLK
1.721 | 0.000 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk1.q_in0_2[15]
1.721 | 0.000 | tHld |  | 1 | R17C33[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk1.q_in0_2[15]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.285, 41.613%; tC2Q: 0.400, 58.387%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%

### Path19

Path Summary:

Slack | 0.685
Data Arrival Time | 2.406
Data Required Time | 1.721
From | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk1.q_in0_1[4]
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk1.q_in0_2[4]
Launch Clk | clk_rx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R20C32[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk1.q_in0_1[4]/CLK
2.121 | 0.400 | tC2Q | RR | 2 | R20C32[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk1.q_in0_1[4]/Q
2.406 | 0.285 | tNET | RR | 1 | R20C32[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk1.q_in0_2[4]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R20C32[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk1.q_in0_2[4]/CLK
1.721 | 0.000 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk1.q_in0_2[4]
1.721 | 0.000 | tHld |  | 1 | R20C32[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk1.q_in0_2[4]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.285, 41.613%; tC2Q: 0.400, 58.387%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%

### Path20

Path Summary:

Slack | 0.685
Data Arrival Time | 2.406
Data Required Time | 1.721
From | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/reg2_Z[0]
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/reg3_Z[0]
Launch Clk | clk_rx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R20C24[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/reg2_Z[0]/CLK
2.121 | 0.400 | tC2Q | RR | 2 | R20C24[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/reg2_Z[0]/Q
2.406 | 0.285 | tNET | RR | 1 | R20C24[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/reg3_Z[0]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R20C24[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/reg3_Z[0]/CLK
1.721 | 0.000 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/reg3_Z[0]
1.721 | 0.000 | tHld |  | 1 | R20C24[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/reg3_Z[0]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.285, 41.613%; tC2Q: 0.400, 58.387%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%

### Path21

Path Summary:

Slack | 0.685
Data Arrival Time | 2.406
Data Required Time | 1.721
From | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk3.q_in2_1[3]
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk3.q_in2_2[3]
Launch Clk | clk_rx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R15C29[2][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk3.q_in2_1[3]/CLK
2.121 | 0.400 | tC2Q | RR | 2 | R15C29[2][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk3.q_in2_1[3]/Q
2.406 | 0.285 | tNET | RR | 1 | R15C29[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk3.q_in2_2[3]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R15C29[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk3.q_in2_2[3]/CLK
1.721 | 0.000 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk3.q_in2_2[3]
1.721 | 0.000 | tHld |  | 1 | R15C29[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk3.q_in2_2[3]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.285, 41.613%; tC2Q: 0.400, 58.387%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%

### Path22

Path Summary:

Slack | 0.685
Data Arrival Time | 2.406
Data Required Time | 1.721
From | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/reg2_Z[14]
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/reg3_Z[14]
Launch Clk | clk_rx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R17C23[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/reg2_Z[14]/CLK
2.121 | 0.400 | tC2Q | RR | 4 | R17C23[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/reg2_Z[14]/Q
2.406 | 0.285 | tNET | RR | 1 | R17C23[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/reg3_Z[14]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R17C23[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/reg3_Z[14]/CLK
1.721 | 0.000 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/reg3_Z[14]
1.721 | 0.000 | tHld |  | 1 | R17C23[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/reg3_Z[14]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.285, 41.613%; tC2Q: 0.400, 58.387%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%

### Path23

Path Summary:

Slack | 0.685
Data Arrival Time | 2.406
Data Required Time | 1.721
From | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg2_Z[11]
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg3_fast_Z[11]
Launch Clk | clk_rx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R11C24[1][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg2_Z[11]/CLK
2.121 | 0.400 | tC2Q | RR | 3 | R11C24[1][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg2_Z[11]/Q
2.406 | 0.285 | tNET | RR | 1 | R11C24[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg3_fast_Z[11]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R11C24[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg3_fast_Z[11]/CLK
1.721 | 0.000 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg3_fast_Z[11]
1.721 | 0.000 | tHld |  | 1 | R11C24[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg3_fast_Z[11]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.285, 41.613%; tC2Q: 0.400, 58.387%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%

### Path24

Path Summary:

Slack | 0.685
Data Arrival Time | 2.406
Data Required Time | 1.721
From | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg1_Z[1]
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg2_Z[1]
Launch Clk | clk_rx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R11C25[1][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg1_Z[1]/CLK
2.121 | 0.400 | tC2Q | RR | 5 | R11C25[1][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg1_Z[1]/Q
2.406 | 0.285 | tNET | RR | 1 | R11C25[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg2_Z[1]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R11C25[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg2_Z[1]/CLK
1.721 | 0.000 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg2_Z[1]
1.721 | 0.000 | tHld |  | 1 | R11C25[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg2_Z[1]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.285, 41.613%; tC2Q: 0.400, 58.387%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%

### Path25

Path Summary:

Slack | 0.685
Data Arrival Time | 2.406
Data Required Time | 1.721
From | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg0_Z[8]
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg1_Z[8]
Launch Clk | clk_rx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R9C25[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg0_Z[8]/CLK
2.121 | 0.400 | tC2Q | RR | 10 | R9C25[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg0_Z[8]/Q
2.406 | 0.285 | tNET | RR | 1 | R9C25[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg1_Z[8]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R9C25[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg1_Z[8]/CLK
1.721 | 0.000 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg1_Z[8]
1.721 | 0.000 | tHld |  | 1 | R9C25[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg1_Z[8]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.285, 41.613%; tC2Q: 0.400, 58.387%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%

### Recovery Analysis Report

#### Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

### Path1

Path Summary:

Slack | 0.559
Data Arrival Time | 11.480
Data Required Time | 12.039
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]
Launch Clk | clk_rx:[F]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | clk_rx
5.000 | 0.000 | tCL | FF | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
7.344 | 2.344 | tNET | FF | 1 | R4C4[1][A] | u_la0_top/rst_ao_Z/CLK
7.894 | 0.550 | tC2Q | FF | 44 | R4C4[1][A] | u_la0_top/rst_ao_Z/Q
11.480 | 3.586 | tNET | FF | 1 | R8C4[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | clk_rx
10.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.291 | 2.291 | tNET | RR | 1 | R8C4[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLK
12.091 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]
12.039 | -0.052 | tSu |  | 1 | R8C4[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]

Path Statistics:

Clock Skew | -0.053
Setup Relationship | 5.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.344, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.586, 86.703%; tC2Q: 0.550, 13.297%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%

### Path2

Path Summary:

Slack | 0.559
Data Arrival Time | 11.480
Data Required Time | 12.039
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]
Launch Clk | clk_rx:[F]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | clk_rx
5.000 | 0.000 | tCL | FF | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
7.344 | 2.344 | tNET | FF | 1 | R4C4[1][A] | u_la0_top/rst_ao_Z/CLK
7.894 | 0.550 | tC2Q | FF | 44 | R4C4[1][A] | u_la0_top/rst_ao_Z/Q
11.480 | 3.586 | tNET | FF | 1 | R8C4[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | clk_rx
10.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.291 | 2.291 | tNET | RR | 1 | R8C4[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/CLK
12.091 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]
12.039 | -0.052 | tSu |  | 1 | R8C4[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]

Path Statistics:

Clock Skew | -0.053
Setup Relationship | 5.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.344, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.586, 86.703%; tC2Q: 0.550, 13.297%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%

### Path3

Path Summary:

Slack | 0.559
Data Arrival Time | 11.480
Data Required Time | 12.039
From | u_la0_top/rst_ao_Z
To | u_la0_top/capture_window_sel_Z[1]
Launch Clk | clk_rx:[F]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | clk_rx
5.000 | 0.000 | tCL | FF | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
7.344 | 2.344 | tNET | FF | 1 | R4C4[1][A] | u_la0_top/rst_ao_Z/CLK
7.894 | 0.550 | tC2Q | FF | 44 | R4C4[1][A] | u_la0_top/rst_ao_Z/Q
11.480 | 3.586 | tNET | FF | 1 | R8C4[1][A] | u_la0_top/capture_window_sel_Z[1]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | clk_rx
10.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.291 | 2.291 | tNET | RR | 1 | R8C4[1][A] | u_la0_top/capture_window_sel_Z[1]/CLK
12.091 | -0.200 | tUnc |  |  |  | u_la0_top/capture_window_sel_Z[1]
12.039 | -0.052 | tSu |  | 1 | R8C4[1][A] | u_la0_top/capture_window_sel_Z[1]

Path Statistics:

Clock Skew | -0.053
Setup Relationship | 5.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.344, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.586, 86.703%; tC2Q: 0.550, 13.297%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%

### Path4

Path Summary:

Slack | 1.290
Data Arrival Time | 10.549
Data Required Time | 11.839
From | dout1[16]
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg2_Z[1]
Launch Clk | clk_tx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_tx
0.000 | 0.000 | tCL | RR | 34 | BOTTOMSIDE[0] | u_DPHY_TX_TOP/DPHY_TX_INST/u_oserx8/U3_CLKDIV/CLKOUT
2.291 | 2.291 | tNET | RR | 1 | R27C23[0][A] | dout1[16]/CLK
2.841 | 0.550 | tC2Q | RF | 7 | R27C23[0][A] | dout1[16]/Q
5.571 | 2.731 | tNET | FF | 1 | R21C29[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/en_align_i_cZ/I0
6.890 | 1.319 | tINS | FF | 774 | R21C29[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/en_align_i_cZ/F
10.549 | 3.659 | tNET | FF | 1 | R11C25[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg2_Z[1]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | clk_rx
10.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.291 | 2.291 | tNET | RR | 1 | R11C25[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg2_Z[1]/CLK
11.891 | -0.400 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg2_Z[1]
11.839 | -0.052 | tSu |  | 1 | R11C25[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg2_Z[1]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%
Arrival Data Path Delay | cell: 1.319, 15.969%; route: 6.389, 77.371%; tC2Q: 0.550, 6.660%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%

### Path5

Path Summary:

Slack | 1.290
Data Arrival Time | 10.549
Data Required Time | 11.839
From | dout1[16]
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg2_Z[4]
Launch Clk | clk_tx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_tx
0.000 | 0.000 | tCL | RR | 34 | BOTTOMSIDE[0] | u_DPHY_TX_TOP/DPHY_TX_INST/u_oserx8/U3_CLKDIV/CLKOUT
2.291 | 2.291 | tNET | RR | 1 | R27C23[0][A] | dout1[16]/CLK
2.841 | 0.550 | tC2Q | RF | 7 | R27C23[0][A] | dout1[16]/Q
5.571 | 2.731 | tNET | FF | 1 | R21C29[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/en_align_i_cZ/I0
6.890 | 1.319 | tINS | FF | 774 | R21C29[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/en_align_i_cZ/F
10.549 | 3.659 | tNET | FF | 1 | R13C25[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg2_Z[4]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | clk_rx
10.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.291 | 2.291 | tNET | RR | 1 | R13C25[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg2_Z[4]/CLK
11.891 | -0.400 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg2_Z[4]
11.839 | -0.052 | tSu |  | 1 | R13C25[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg2_Z[4]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%
Arrival Data Path Delay | cell: 1.319, 15.969%; route: 6.389, 77.371%; tC2Q: 0.550, 6.660%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%

### Path6

Path Summary:

Slack | 1.290
Data Arrival Time | 10.549
Data Required Time | 11.839
From | dout1[16]
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg3_fast_Z[2]
Launch Clk | clk_tx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_tx
0.000 | 0.000 | tCL | RR | 34 | BOTTOMSIDE[0] | u_DPHY_TX_TOP/DPHY_TX_INST/u_oserx8/U3_CLKDIV/CLKOUT
2.291 | 2.291 | tNET | RR | 1 | R27C23[0][A] | dout1[16]/CLK
2.841 | 0.550 | tC2Q | RF | 7 | R27C23[0][A] | dout1[16]/Q
5.571 | 2.731 | tNET | FF | 1 | R21C29[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/en_align_i_cZ/I0
6.890 | 1.319 | tINS | FF | 774 | R21C29[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/en_align_i_cZ/F
10.549 | 3.659 | tNET | FF | 1 | R11C25[2][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg3_fast_Z[2]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | clk_rx
10.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.291 | 2.291 | tNET | RR | 1 | R11C25[2][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg3_fast_Z[2]/CLK
11.891 | -0.400 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg3_fast_Z[2]
11.839 | -0.052 | tSu |  | 1 | R11C25[2][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg3_fast_Z[2]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%
Arrival Data Path Delay | cell: 1.319, 15.969%; route: 6.389, 77.371%; tC2Q: 0.550, 6.660%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%

### Path7

Path Summary:

Slack | 1.290
Data Arrival Time | 10.549
Data Required Time | 11.839
From | dout1[16]
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/reg2_Z[9]
Launch Clk | clk_tx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_tx
0.000 | 0.000 | tCL | RR | 34 | BOTTOMSIDE[0] | u_DPHY_TX_TOP/DPHY_TX_INST/u_oserx8/U3_CLKDIV/CLKOUT
2.291 | 2.291 | tNET | RR | 1 | R27C23[0][A] | dout1[16]/CLK
2.841 | 0.550 | tC2Q | RF | 7 | R27C23[0][A] | dout1[16]/Q
5.571 | 2.731 | tNET | FF | 1 | R21C29[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/en_align_i_cZ/I0
6.890 | 1.319 | tINS | FF | 774 | R21C29[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/en_align_i_cZ/F
10.549 | 3.659 | tNET | FF | 1 | R20C13[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/reg2_Z[9]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | clk_rx
10.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.291 | 2.291 | tNET | RR | 1 | R20C13[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/reg2_Z[9]/CLK
11.891 | -0.400 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/reg2_Z[9]
11.839 | -0.052 | tSu |  | 1 | R20C13[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/reg2_Z[9]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%
Arrival Data Path Delay | cell: 1.319, 15.969%; route: 6.389, 77.371%; tC2Q: 0.550, 6.660%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%

### Path8

Path Summary:

Slack | 1.290
Data Arrival Time | 10.549
Data Required Time | 11.839
From | dout1[16]
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk4.q_in3_1[15]
Launch Clk | clk_tx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_tx
0.000 | 0.000 | tCL | RR | 34 | BOTTOMSIDE[0] | u_DPHY_TX_TOP/DPHY_TX_INST/u_oserx8/U3_CLKDIV/CLKOUT
2.291 | 2.291 | tNET | RR | 1 | R27C23[0][A] | dout1[16]/CLK
2.841 | 0.550 | tC2Q | RF | 7 | R27C23[0][A] | dout1[16]/Q
5.571 | 2.731 | tNET | FF | 1 | R21C29[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/en_align_i_cZ/I0
6.890 | 1.319 | tINS | FF | 774 | R21C29[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/en_align_i_cZ/F
10.549 | 3.659 | tNET | FF | 1 | R11C33[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk4.q_in3_1[15]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | clk_rx
10.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.291 | 2.291 | tNET | RR | 1 | R11C33[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk4.q_in3_1[15]/CLK
11.891 | -0.400 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk4.q_in3_1[15]
11.839 | -0.052 | tSu |  | 1 | R11C33[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk4.q_in3_1[15]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%
Arrival Data Path Delay | cell: 1.319, 15.969%; route: 6.389, 77.371%; tC2Q: 0.550, 6.660%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%

### Path9

Path Summary:

Slack | 1.290
Data Arrival Time | 10.549
Data Required Time | 11.839
From | dout1[16]
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk2.q_in1_0[3]
Launch Clk | clk_tx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_tx
0.000 | 0.000 | tCL | RR | 34 | BOTTOMSIDE[0] | u_DPHY_TX_TOP/DPHY_TX_INST/u_oserx8/U3_CLKDIV/CLKOUT
2.291 | 2.291 | tNET | RR | 1 | R27C23[0][A] | dout1[16]/CLK
2.841 | 0.550 | tC2Q | RF | 7 | R27C23[0][A] | dout1[16]/Q
5.571 | 2.731 | tNET | FF | 1 | R21C29[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/en_align_i_cZ/I0
6.890 | 1.319 | tINS | FF | 774 | R21C29[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/en_align_i_cZ/F
10.549 | 3.659 | tNET | FF | 1 | R13C25[2][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk2.q_in1_0[3]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | clk_rx
10.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.291 | 2.291 | tNET | RR | 1 | R13C25[2][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk2.q_in1_0[3]/CLK
11.891 | -0.400 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk2.q_in1_0[3]
11.839 | -0.052 | tSu |  | 1 | R13C25[2][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk2.q_in1_0[3]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%
Arrival Data Path Delay | cell: 1.319, 15.969%; route: 6.389, 77.371%; tC2Q: 0.550, 6.660%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%

### Path10

Path Summary:

Slack | 1.290
Data Arrival Time | 10.549
Data Required Time | 11.839
From | dout1[16]
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg3_fast_Z[10]
Launch Clk | clk_tx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_tx
0.000 | 0.000 | tCL | RR | 34 | BOTTOMSIDE[0] | u_DPHY_TX_TOP/DPHY_TX_INST/u_oserx8/U3_CLKDIV/CLKOUT
2.291 | 2.291 | tNET | RR | 1 | R27C23[0][A] | dout1[16]/CLK
2.841 | 0.550 | tC2Q | RF | 7 | R27C23[0][A] | dout1[16]/Q
5.571 | 2.731 | tNET | FF | 1 | R21C29[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/en_align_i_cZ/I0
6.890 | 1.319 | tINS | FF | 774 | R21C29[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/en_align_i_cZ/F
10.549 | 3.659 | tNET | FF | 1 | R11C25[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg3_fast_Z[10]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | clk_rx
10.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.291 | 2.291 | tNET | RR | 1 | R11C25[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg3_fast_Z[10]/CLK
11.891 | -0.400 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg3_fast_Z[10]
11.839 | -0.052 | tSu |  | 1 | R11C25[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg3_fast_Z[10]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%
Arrival Data Path Delay | cell: 1.319, 15.969%; route: 6.389, 77.371%; tC2Q: 0.550, 6.660%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%

### Path11

Path Summary:

Slack | 1.290
Data Arrival Time | 10.549
Data Required Time | 11.839
From | dout1[16]
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk4.q_in3_1[4]
Launch Clk | clk_tx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_tx
0.000 | 0.000 | tCL | RR | 34 | BOTTOMSIDE[0] | u_DPHY_TX_TOP/DPHY_TX_INST/u_oserx8/U3_CLKDIV/CLKOUT
2.291 | 2.291 | tNET | RR | 1 | R27C23[0][A] | dout1[16]/CLK
2.841 | 0.550 | tC2Q | RF | 7 | R27C23[0][A] | dout1[16]/Q
5.571 | 2.731 | tNET | FF | 1 | R21C29[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/en_align_i_cZ/I0
6.890 | 1.319 | tINS | FF | 774 | R21C29[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/en_align_i_cZ/F
10.549 | 3.659 | tNET | FF | 1 | R11C33[2][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk4.q_in3_1[4]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | clk_rx
10.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.291 | 2.291 | tNET | RR | 1 | R11C33[2][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk4.q_in3_1[4]/CLK
11.891 | -0.400 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk4.q_in3_1[4]
11.839 | -0.052 | tSu |  | 1 | R11C33[2][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk4.q_in3_1[4]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%
Arrival Data Path Delay | cell: 1.319, 15.969%; route: 6.389, 77.371%; tC2Q: 0.550, 6.660%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%

### Path12

Path Summary:

Slack | 1.290
Data Arrival Time | 10.549
Data Required Time | 11.839
From | dout1[16]
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/reg2_Z[10]
Launch Clk | clk_tx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_tx
0.000 | 0.000 | tCL | RR | 34 | BOTTOMSIDE[0] | u_DPHY_TX_TOP/DPHY_TX_INST/u_oserx8/U3_CLKDIV/CLKOUT
2.291 | 2.291 | tNET | RR | 1 | R27C23[0][A] | dout1[16]/CLK
2.841 | 0.550 | tC2Q | RF | 7 | R27C23[0][A] | dout1[16]/Q
5.571 | 2.731 | tNET | FF | 1 | R21C29[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/en_align_i_cZ/I0
6.890 | 1.319 | tINS | FF | 774 | R21C29[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/en_align_i_cZ/F
10.549 | 3.659 | tNET | FF | 1 | R20C13[1][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/reg2_Z[10]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | clk_rx
10.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.291 | 2.291 | tNET | RR | 1 | R20C13[1][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/reg2_Z[10]/CLK
11.891 | -0.400 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/reg2_Z[10]
11.839 | -0.052 | tSu |  | 1 | R20C13[1][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/reg2_Z[10]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%
Arrival Data Path Delay | cell: 1.319, 15.969%; route: 6.389, 77.371%; tC2Q: 0.550, 6.660%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%

### Path13

Path Summary:

Slack | 1.290
Data Arrival Time | 10.549
Data Required Time | 11.839
From | dout1[16]
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/reg3_fast_Z[10]
Launch Clk | clk_tx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_tx
0.000 | 0.000 | tCL | RR | 34 | BOTTOMSIDE[0] | u_DPHY_TX_TOP/DPHY_TX_INST/u_oserx8/U3_CLKDIV/CLKOUT
2.291 | 2.291 | tNET | RR | 1 | R27C23[0][A] | dout1[16]/CLK
2.841 | 0.550 | tC2Q | RF | 7 | R27C23[0][A] | dout1[16]/Q
5.571 | 2.731 | tNET | FF | 1 | R21C29[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/en_align_i_cZ/I0
6.890 | 1.319 | tINS | FF | 774 | R21C29[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/en_align_i_cZ/F
10.549 | 3.659 | tNET | FF | 1 | R20C13[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/reg3_fast_Z[10]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | clk_rx
10.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.291 | 2.291 | tNET | RR | 1 | R20C13[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/reg3_fast_Z[10]/CLK
11.891 | -0.400 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/reg3_fast_Z[10]
11.839 | -0.052 | tSu |  | 1 | R20C13[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/reg3_fast_Z[10]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%
Arrival Data Path Delay | cell: 1.319, 15.969%; route: 6.389, 77.371%; tC2Q: 0.550, 6.660%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%

### Path14

Path Summary:

Slack | 1.290
Data Arrival Time | 10.549
Data Required Time | 11.839
From | dout1[16]
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/reg3_Z[10]
Launch Clk | clk_tx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_tx
0.000 | 0.000 | tCL | RR | 34 | BOTTOMSIDE[0] | u_DPHY_TX_TOP/DPHY_TX_INST/u_oserx8/U3_CLKDIV/CLKOUT
2.291 | 2.291 | tNET | RR | 1 | R27C23[0][A] | dout1[16]/CLK
2.841 | 0.550 | tC2Q | RF | 7 | R27C23[0][A] | dout1[16]/Q
5.571 | 2.731 | tNET | FF | 1 | R21C29[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/en_align_i_cZ/I0
6.890 | 1.319 | tINS | FF | 774 | R21C29[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/en_align_i_cZ/F
10.549 | 3.659 | tNET | FF | 1 | R20C13[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/reg3_Z[10]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | clk_rx
10.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.291 | 2.291 | tNET | RR | 1 | R20C13[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/reg3_Z[10]/CLK
11.891 | -0.400 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/reg3_Z[10]
11.839 | -0.052 | tSu |  | 1 | R20C13[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/reg3_Z[10]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%
Arrival Data Path Delay | cell: 1.319, 15.969%; route: 6.389, 77.371%; tC2Q: 0.550, 6.660%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%

### Path15

Path Summary:

Slack | 1.290
Data Arrival Time | 10.549
Data Required Time | 11.839
From | dout1[16]
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/reg1_Z[10]
Launch Clk | clk_tx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_tx
0.000 | 0.000 | tCL | RR | 34 | BOTTOMSIDE[0] | u_DPHY_TX_TOP/DPHY_TX_INST/u_oserx8/U3_CLKDIV/CLKOUT
2.291 | 2.291 | tNET | RR | 1 | R27C23[0][A] | dout1[16]/CLK
2.841 | 0.550 | tC2Q | RF | 7 | R27C23[0][A] | dout1[16]/Q
5.571 | 2.731 | tNET | FF | 1 | R21C29[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/en_align_i_cZ/I0
6.890 | 1.319 | tINS | FF | 774 | R21C29[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/en_align_i_cZ/F
10.549 | 3.659 | tNET | FF | 1 | R20C13[2][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/reg1_Z[10]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | clk_rx
10.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.291 | 2.291 | tNET | RR | 1 | R20C13[2][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/reg1_Z[10]/CLK
11.891 | -0.400 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/reg1_Z[10]
11.839 | -0.052 | tSu |  | 1 | R20C13[2][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/reg1_Z[10]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%
Arrival Data Path Delay | cell: 1.319, 15.969%; route: 6.389, 77.371%; tC2Q: 0.550, 6.660%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%

### Path16

Path Summary:

Slack | 1.290
Data Arrival Time | 10.549
Data Required Time | 11.839
From | dout1[16]
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg3_fast_Z[3]
Launch Clk | clk_tx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_tx
0.000 | 0.000 | tCL | RR | 34 | BOTTOMSIDE[0] | u_DPHY_TX_TOP/DPHY_TX_INST/u_oserx8/U3_CLKDIV/CLKOUT
2.291 | 2.291 | tNET | RR | 1 | R27C23[0][A] | dout1[16]/CLK
2.841 | 0.550 | tC2Q | RF | 7 | R27C23[0][A] | dout1[16]/Q
5.571 | 2.731 | tNET | FF | 1 | R21C29[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/en_align_i_cZ/I0
6.890 | 1.319 | tINS | FF | 774 | R21C29[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/en_align_i_cZ/F
10.549 | 3.659 | tNET | FF | 1 | R11C25[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg3_fast_Z[3]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | clk_rx
10.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.291 | 2.291 | tNET | RR | 1 | R11C25[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg3_fast_Z[3]/CLK
11.891 | -0.400 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg3_fast_Z[3]
11.839 | -0.052 | tSu |  | 1 | R11C25[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg3_fast_Z[3]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%
Arrival Data Path Delay | cell: 1.319, 15.969%; route: 6.389, 77.371%; tC2Q: 0.550, 6.660%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%

### Path17

Path Summary:

Slack | 1.290
Data Arrival Time | 10.549
Data Required Time | 11.839
From | dout1[16]
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk4.q_in3_2[4]
Launch Clk | clk_tx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_tx
0.000 | 0.000 | tCL | RR | 34 | BOTTOMSIDE[0] | u_DPHY_TX_TOP/DPHY_TX_INST/u_oserx8/U3_CLKDIV/CLKOUT
2.291 | 2.291 | tNET | RR | 1 | R27C23[0][A] | dout1[16]/CLK
2.841 | 0.550 | tC2Q | RF | 7 | R27C23[0][A] | dout1[16]/Q
5.571 | 2.731 | tNET | FF | 1 | R21C29[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/en_align_i_cZ/I0
6.890 | 1.319 | tINS | FF | 774 | R21C29[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/en_align_i_cZ/F
10.549 | 3.659 | tNET | FF | 1 | R11C33[1][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk4.q_in3_2[4]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | clk_rx
10.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.291 | 2.291 | tNET | RR | 1 | R11C33[1][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk4.q_in3_2[4]/CLK
11.891 | -0.400 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk4.q_in3_2[4]
11.839 | -0.052 | tSu |  | 1 | R11C33[1][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk4.q_in3_2[4]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%
Arrival Data Path Delay | cell: 1.319, 15.969%; route: 6.389, 77.371%; tC2Q: 0.550, 6.660%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%

### Path18

Path Summary:

Slack | 1.290
Data Arrival Time | 10.549
Data Required Time | 11.839
From | dout1[16]
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk4.q_in3_0[15]
Launch Clk | clk_tx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_tx
0.000 | 0.000 | tCL | RR | 34 | BOTTOMSIDE[0] | u_DPHY_TX_TOP/DPHY_TX_INST/u_oserx8/U3_CLKDIV/CLKOUT
2.291 | 2.291 | tNET | RR | 1 | R27C23[0][A] | dout1[16]/CLK
2.841 | 0.550 | tC2Q | RF | 7 | R27C23[0][A] | dout1[16]/Q
5.571 | 2.731 | tNET | FF | 1 | R21C29[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/en_align_i_cZ/I0
6.890 | 1.319 | tINS | FF | 774 | R21C29[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/en_align_i_cZ/F
10.549 | 3.659 | tNET | FF | 1 | R11C33[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk4.q_in3_0[15]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | clk_rx
10.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.291 | 2.291 | tNET | RR | 1 | R11C33[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk4.q_in3_0[15]/CLK
11.891 | -0.400 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk4.q_in3_0[15]
11.839 | -0.052 | tSu |  | 1 | R11C33[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk4.q_in3_0[15]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%
Arrival Data Path Delay | cell: 1.319, 15.969%; route: 6.389, 77.371%; tC2Q: 0.550, 6.660%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%

### Path19

Path Summary:

Slack | 1.290
Data Arrival Time | 10.549
Data Required Time | 11.839
From | dout1[16]
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg4_fast_Z[2]
Launch Clk | clk_tx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_tx
0.000 | 0.000 | tCL | RR | 34 | BOTTOMSIDE[0] | u_DPHY_TX_TOP/DPHY_TX_INST/u_oserx8/U3_CLKDIV/CLKOUT
2.291 | 2.291 | tNET | RR | 1 | R27C23[0][A] | dout1[16]/CLK
2.841 | 0.550 | tC2Q | RF | 7 | R27C23[0][A] | dout1[16]/Q
5.571 | 2.731 | tNET | FF | 1 | R21C29[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/en_align_i_cZ/I0
6.890 | 1.319 | tINS | FF | 774 | R21C29[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/en_align_i_cZ/F
10.549 | 3.659 | tNET | FF | 1 | R13C25[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg4_fast_Z[2]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | clk_rx
10.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.291 | 2.291 | tNET | RR | 1 | R13C25[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg4_fast_Z[2]/CLK
11.891 | -0.400 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg4_fast_Z[2]
11.839 | -0.052 | tSu |  | 1 | R13C25[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg4_fast_Z[2]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%
Arrival Data Path Delay | cell: 1.319, 15.969%; route: 6.389, 77.371%; tC2Q: 0.550, 6.660%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%

### Path20

Path Summary:

Slack | 1.290
Data Arrival Time | 10.549
Data Required Time | 11.839
From | dout1[16]
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg2_Z[3]
Launch Clk | clk_tx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_tx
0.000 | 0.000 | tCL | RR | 34 | BOTTOMSIDE[0] | u_DPHY_TX_TOP/DPHY_TX_INST/u_oserx8/U3_CLKDIV/CLKOUT
2.291 | 2.291 | tNET | RR | 1 | R27C23[0][A] | dout1[16]/CLK
2.841 | 0.550 | tC2Q | RF | 7 | R27C23[0][A] | dout1[16]/Q
5.571 | 2.731 | tNET | FF | 1 | R21C29[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/en_align_i_cZ/I0
6.890 | 1.319 | tINS | FF | 774 | R21C29[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/en_align_i_cZ/F
10.549 | 3.659 | tNET | FF | 1 | R13C25[1][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg2_Z[3]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | clk_rx
10.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.291 | 2.291 | tNET | RR | 1 | R13C25[1][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg2_Z[3]/CLK
11.891 | -0.400 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg2_Z[3]
11.839 | -0.052 | tSu |  | 1 | R13C25[1][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg2_Z[3]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%
Arrival Data Path Delay | cell: 1.319, 15.969%; route: 6.389, 77.371%; tC2Q: 0.550, 6.660%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%

### Path21

Path Summary:

Slack | 1.290
Data Arrival Time | 10.549
Data Required Time | 11.839
From | dout1[16]
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/reg3_fast_Z[7]
Launch Clk | clk_tx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_tx
0.000 | 0.000 | tCL | RR | 34 | BOTTOMSIDE[0] | u_DPHY_TX_TOP/DPHY_TX_INST/u_oserx8/U3_CLKDIV/CLKOUT
2.291 | 2.291 | tNET | RR | 1 | R27C23[0][A] | dout1[16]/CLK
2.841 | 0.550 | tC2Q | RF | 7 | R27C23[0][A] | dout1[16]/Q
5.571 | 2.731 | tNET | FF | 1 | R21C29[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/en_align_i_cZ/I0
6.890 | 1.319 | tINS | FF | 774 | R21C29[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/en_align_i_cZ/F
10.549 | 3.659 | tNET | FF | 1 | R20C13[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/reg3_fast_Z[7]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | clk_rx
10.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.291 | 2.291 | tNET | RR | 1 | R20C13[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/reg3_fast_Z[7]/CLK
11.891 | -0.400 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/reg3_fast_Z[7]
11.839 | -0.052 | tSu |  | 1 | R20C13[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/reg3_fast_Z[7]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%
Arrival Data Path Delay | cell: 1.319, 15.969%; route: 6.389, 77.371%; tC2Q: 0.550, 6.660%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%

### Path22

Path Summary:

Slack | 1.290
Data Arrival Time | 10.549
Data Required Time | 11.839
From | dout1[16]
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg3_fast_Z[1]
Launch Clk | clk_tx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_tx
0.000 | 0.000 | tCL | RR | 34 | BOTTOMSIDE[0] | u_DPHY_TX_TOP/DPHY_TX_INST/u_oserx8/U3_CLKDIV/CLKOUT
2.291 | 2.291 | tNET | RR | 1 | R27C23[0][A] | dout1[16]/CLK
2.841 | 0.550 | tC2Q | RF | 7 | R27C23[0][A] | dout1[16]/Q
5.571 | 2.731 | tNET | FF | 1 | R21C29[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/en_align_i_cZ/I0
6.890 | 1.319 | tINS | FF | 774 | R21C29[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/en_align_i_cZ/F
10.549 | 3.659 | tNET | FF | 1 | R11C25[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg3_fast_Z[1]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | clk_rx
10.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.291 | 2.291 | tNET | RR | 1 | R11C25[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg3_fast_Z[1]/CLK
11.891 | -0.400 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg3_fast_Z[1]
11.839 | -0.052 | tSu |  | 1 | R11C25[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg3_fast_Z[1]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%
Arrival Data Path Delay | cell: 1.319, 15.969%; route: 6.389, 77.371%; tC2Q: 0.550, 6.660%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%

### Path23

Path Summary:

Slack | 1.290
Data Arrival Time | 10.549
Data Required Time | 11.839
From | dout1[16]
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg3_Z[4]
Launch Clk | clk_tx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_tx
0.000 | 0.000 | tCL | RR | 34 | BOTTOMSIDE[0] | u_DPHY_TX_TOP/DPHY_TX_INST/u_oserx8/U3_CLKDIV/CLKOUT
2.291 | 2.291 | tNET | RR | 1 | R27C23[0][A] | dout1[16]/CLK
2.841 | 0.550 | tC2Q | RF | 7 | R27C23[0][A] | dout1[16]/Q
5.571 | 2.731 | tNET | FF | 1 | R21C29[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/en_align_i_cZ/I0
6.890 | 1.319 | tINS | FF | 774 | R21C29[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/en_align_i_cZ/F
10.549 | 3.659 | tNET | FF | 1 | R13C25[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg3_Z[4]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | clk_rx
10.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.291 | 2.291 | tNET | RR | 1 | R13C25[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg3_Z[4]/CLK
11.891 | -0.400 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg3_Z[4]
11.839 | -0.052 | tSu |  | 1 | R13C25[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg3_Z[4]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%
Arrival Data Path Delay | cell: 1.319, 15.969%; route: 6.389, 77.371%; tC2Q: 0.550, 6.660%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%

### Path24

Path Summary:

Slack | 1.290
Data Arrival Time | 10.549
Data Required Time | 11.839
From | dout1[16]
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg1_Z[1]
Launch Clk | clk_tx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_tx
0.000 | 0.000 | tCL | RR | 34 | BOTTOMSIDE[0] | u_DPHY_TX_TOP/DPHY_TX_INST/u_oserx8/U3_CLKDIV/CLKOUT
2.291 | 2.291 | tNET | RR | 1 | R27C23[0][A] | dout1[16]/CLK
2.841 | 0.550 | tC2Q | RF | 7 | R27C23[0][A] | dout1[16]/Q
5.571 | 2.731 | tNET | FF | 1 | R21C29[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/en_align_i_cZ/I0
6.890 | 1.319 | tINS | FF | 774 | R21C29[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/en_align_i_cZ/F
10.549 | 3.659 | tNET | FF | 1 | R11C25[1][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg1_Z[1]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | clk_rx
10.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.291 | 2.291 | tNET | RR | 1 | R11C25[1][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg1_Z[1]/CLK
11.891 | -0.400 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg1_Z[1]
11.839 | -0.052 | tSu |  | 1 | R11C25[1][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg1_Z[1]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%
Arrival Data Path Delay | cell: 1.319, 15.969%; route: 6.389, 77.371%; tC2Q: 0.550, 6.660%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%

### Path25

Path Summary:

Slack | 1.290
Data Arrival Time | 10.549
Data Required Time | 11.839
From | dout1[16]
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg3_Z[3]
Launch Clk | clk_tx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_tx
0.000 | 0.000 | tCL | RR | 34 | BOTTOMSIDE[0] | u_DPHY_TX_TOP/DPHY_TX_INST/u_oserx8/U3_CLKDIV/CLKOUT
2.291 | 2.291 | tNET | RR | 1 | R27C23[0][A] | dout1[16]/CLK
2.841 | 0.550 | tC2Q | RF | 7 | R27C23[0][A] | dout1[16]/Q
5.571 | 2.731 | tNET | FF | 1 | R21C29[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/en_align_i_cZ/I0
6.890 | 1.319 | tINS | FF | 774 | R21C29[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/en_align_i_cZ/F
10.549 | 3.659 | tNET | FF | 1 | R13C25[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg3_Z[3]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | clk_rx
10.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.291 | 2.291 | tNET | RR | 1 | R13C25[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg3_Z[3]/CLK
11.891 | -0.400 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg3_Z[3]
11.839 | -0.052 | tSu |  | 1 | R13C25[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk3.wd1/reg3_Z[3]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%
Arrival Data Path Delay | cell: 1.319, 15.969%; route: 6.389, 77.371%; tC2Q: 0.550, 6.660%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.291, 100.000%

### Removal Analysis Report

#### Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

### Path1

Path Summary:

Slack | 1.026
Data Arrival Time | 2.765
Data Required Time | 1.739
From | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk3.sync2
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk11.U2/wq2_rptr_Z[3]
Launch Clk | clk_rx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R16C36[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk3.sync2/CLK
2.121 | 0.400 | tC2Q | RR | 31 | R16C36[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk3.sync2/Q
2.765 | 0.644 | tNET | RR | 1 | R16C36[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk11.U2/wq2_rptr_Z[3]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R16C36[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk11.U2/wq2_rptr_Z[3]/CLK
1.721 | 0.000 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk11.U2/wq2_rptr_Z[3]
1.739 | 0.018 | tHld |  | 1 | R16C36[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk11.U2/wq2_rptr_Z[3]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.644, 61.696%; tC2Q: 0.400, 38.304%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%

### Path2

Path Summary:

Slack | 1.026
Data Arrival Time | 2.765
Data Required Time | 1.739
From | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk3.sync2
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk11.U2/wq1_rptr_Z[4]
Launch Clk | clk_rx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R16C36[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk3.sync2/CLK
2.121 | 0.400 | tC2Q | RR | 31 | R16C36[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk3.sync2/Q
2.765 | 0.644 | tNET | RR | 1 | R16C36[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk11.U2/wq1_rptr_Z[4]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R16C36[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk11.U2/wq1_rptr_Z[4]/CLK
1.721 | 0.000 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk11.U2/wq1_rptr_Z[4]
1.739 | 0.018 | tHld |  | 1 | R16C36[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk11.U2/wq1_rptr_Z[4]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.644, 61.696%; tC2Q: 0.400, 38.304%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%

### Path3

Path Summary:

Slack | 1.026
Data Arrival Time | 2.765
Data Required Time | 1.739
From | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk3.sync2
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk11.U2/wbin_Z[0]
Launch Clk | clk_rx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R16C36[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk3.sync2/CLK
2.121 | 0.400 | tC2Q | RR | 31 | R16C36[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk3.sync2/Q
2.765 | 0.644 | tNET | RR | 1 | R16C36[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk11.U2/wbin_Z[0]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R16C36[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk11.U2/wbin_Z[0]/CLK
1.721 | 0.000 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk11.U2/wbin_Z[0]
1.739 | 0.018 | tHld |  | 1 | R16C36[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk11.U2/wbin_Z[0]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.644, 61.696%; tC2Q: 0.400, 38.304%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%

### Path4

Path Summary:

Slack | 1.026
Data Arrival Time | 2.765
Data Required Time | 1.739
From | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk3.sync2
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk11.U2/wq2_rptr_Z[4]
Launch Clk | clk_rx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R16C36[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk3.sync2/CLK
2.121 | 0.400 | tC2Q | RR | 31 | R16C36[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk3.sync2/Q
2.765 | 0.644 | tNET | RR | 1 | R16C36[1][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk11.U2/wq2_rptr_Z[4]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R16C36[1][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk11.U2/wq2_rptr_Z[4]/CLK
1.721 | 0.000 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk11.U2/wq2_rptr_Z[4]
1.739 | 0.018 | tHld |  | 1 | R16C36[1][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk11.U2/wq2_rptr_Z[4]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.644, 61.696%; tC2Q: 0.400, 38.304%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%

### Path5

Path Summary:

Slack | 1.044
Data Arrival Time | 2.783
Data Required Time | 1.739
From | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk4.sync3
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk12.U3/rbin_Z[3]
Launch Clk | clk_rx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R13C30[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk4.sync3/CLK
2.121 | 0.400 | tC2Q | RR | 31 | R13C30[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk4.sync3/Q
2.783 | 0.662 | tNET | RR | 1 | R13C31[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk12.U3/rbin_Z[3]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R13C31[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk12.U3/rbin_Z[3]/CLK
1.721 | 0.000 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk12.U3/rbin_Z[3]
1.739 | 0.018 | tHld |  | 1 | R13C31[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk12.U3/rbin_Z[3]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.662, 62.342%; tC2Q: 0.400, 37.658%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%

### Path6

Path Summary:

Slack | 1.056
Data Arrival Time | 2.795
Data Required Time | 1.739
From | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk1.sync0
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/rbin_Z[0]
Launch Clk | clk_rx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R20C34[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk1.sync0/CLK
2.121 | 0.400 | tC2Q | RR | 31 | R20C34[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk1.sync0/Q
2.795 | 0.674 | tNET | RR | 1 | R20C36[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/rbin_Z[0]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R20C36[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/rbin_Z[0]/CLK
1.721 | 0.000 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/rbin_Z[0]
1.739 | 0.018 | tHld |  | 1 | R20C36[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/rbin_Z[0]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.674, 62.757%; tC2Q: 0.400, 37.243%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%

### Path7

Path Summary:

Slack | 1.056
Data Arrival Time | 2.795
Data Required Time | 1.739
From | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk1.sync0
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/wq1_rptr_Z[2]
Launch Clk | clk_rx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R20C34[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk1.sync0/CLK
2.121 | 0.400 | tC2Q | RR | 31 | R20C34[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk1.sync0/Q
2.795 | 0.674 | tNET | RR | 1 | R20C35[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/wq1_rptr_Z[2]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R20C35[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/wq1_rptr_Z[2]/CLK
1.721 | 0.000 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/wq1_rptr_Z[2]
1.739 | 0.018 | tHld |  | 1 | R20C35[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/wq1_rptr_Z[2]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.674, 62.757%; tC2Q: 0.400, 37.243%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%

### Path8

Path Summary:

Slack | 1.056
Data Arrival Time | 2.795
Data Required Time | 1.739
From | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk1.sync0
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/wq1_rptr_Z[0]
Launch Clk | clk_rx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R20C34[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk1.sync0/CLK
2.121 | 0.400 | tC2Q | RR | 31 | R20C34[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk1.sync0/Q
2.795 | 0.674 | tNET | RR | 1 | R20C35[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/wq1_rptr_Z[0]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R20C35[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/wq1_rptr_Z[0]/CLK
1.721 | 0.000 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/wq1_rptr_Z[0]
1.739 | 0.018 | tHld |  | 1 | R20C35[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/wq1_rptr_Z[0]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.674, 62.757%; tC2Q: 0.400, 37.243%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%

### Path9

Path Summary:

Slack | 1.056
Data Arrival Time | 2.795
Data Required Time | 1.739
From | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk1.sync0
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/wq2_rptr_Z[0]
Launch Clk | clk_rx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R20C34[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk1.sync0/CLK
2.121 | 0.400 | tC2Q | RR | 31 | R20C34[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk1.sync0/Q
2.795 | 0.674 | tNET | RR | 1 | R20C35[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/wq2_rptr_Z[0]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R20C35[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/wq2_rptr_Z[0]/CLK
1.721 | 0.000 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/wq2_rptr_Z[0]
1.739 | 0.018 | tHld |  | 1 | R20C35[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/wq2_rptr_Z[0]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.674, 62.757%; tC2Q: 0.400, 37.243%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%

### Path10

Path Summary:

Slack | 1.056
Data Arrival Time | 2.795
Data Required Time | 1.739
From | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk1.sync0
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/wbin_Z[4]
Launch Clk | clk_rx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R20C34[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk1.sync0/CLK
2.121 | 0.400 | tC2Q | RR | 31 | R20C34[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk1.sync0/Q
2.795 | 0.674 | tNET | RR | 1 | R20C35[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/wbin_Z[4]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R20C35[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/wbin_Z[4]/CLK
1.721 | 0.000 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/wbin_Z[4]
1.739 | 0.018 | tHld |  | 1 | R20C35[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/wbin_Z[4]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.674, 62.757%; tC2Q: 0.400, 37.243%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%

### Path11

Path Summary:

Slack | 1.056
Data Arrival Time | 2.795
Data Required Time | 1.739
From | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk1.sync0
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/wbin_Z[3]
Launch Clk | clk_rx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R20C34[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk1.sync0/CLK
2.121 | 0.400 | tC2Q | RR | 31 | R20C34[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk1.sync0/Q
2.795 | 0.674 | tNET | RR | 1 | R20C35[1][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/wbin_Z[3]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R20C35[1][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/wbin_Z[3]/CLK
1.721 | 0.000 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/wbin_Z[3]
1.739 | 0.018 | tHld |  | 1 | R20C35[1][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/wbin_Z[3]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.674, 62.757%; tC2Q: 0.400, 37.243%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%

### Path12

Path Summary:

Slack | 1.056
Data Arrival Time | 2.795
Data Required Time | 1.739
From | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk1.sync0
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/wbin_Z[1]
Launch Clk | clk_rx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R20C34[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk1.sync0/CLK
2.121 | 0.400 | tC2Q | RR | 31 | R20C34[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk1.sync0/Q
2.795 | 0.674 | tNET | RR | 1 | R20C35[2][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/wbin_Z[1]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R20C35[2][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/wbin_Z[1]/CLK
1.721 | 0.000 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/wbin_Z[1]
1.739 | 0.018 | tHld |  | 1 | R20C35[2][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/wbin_Z[1]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.674, 62.757%; tC2Q: 0.400, 37.243%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%

### Path13

Path Summary:

Slack | 1.056
Data Arrival Time | 2.795
Data Required Time | 1.739
From | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk1.sync0
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/rptr_Z[2]
Launch Clk | clk_rx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R20C34[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk1.sync0/CLK
2.121 | 0.400 | tC2Q | RR | 31 | R20C34[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk1.sync0/Q
2.795 | 0.674 | tNET | RR | 1 | R20C36[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/rptr_Z[2]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R20C36[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/rptr_Z[2]/CLK
1.721 | 0.000 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/rptr_Z[2]
1.739 | 0.018 | tHld |  | 1 | R20C36[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/rptr_Z[2]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.674, 62.757%; tC2Q: 0.400, 37.243%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%

### Path14

Path Summary:

Slack | 1.056
Data Arrival Time | 2.795
Data Required Time | 1.739
From | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk1.sync0
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/rptr_Z[0]
Launch Clk | clk_rx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R20C34[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk1.sync0/CLK
2.121 | 0.400 | tC2Q | RR | 31 | R20C34[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk1.sync0/Q
2.795 | 0.674 | tNET | RR | 1 | R20C36[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/rptr_Z[0]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R20C36[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/rptr_Z[0]/CLK
1.721 | 0.000 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/rptr_Z[0]
1.739 | 0.018 | tHld |  | 1 | R20C36[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/rptr_Z[0]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.674, 62.757%; tC2Q: 0.400, 37.243%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%

### Path15

Path Summary:

Slack | 1.056
Data Arrival Time | 2.795
Data Required Time | 1.739
From | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk1.sync0
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/rbin_Z[3]
Launch Clk | clk_rx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R20C34[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk1.sync0/CLK
2.121 | 0.400 | tC2Q | RR | 31 | R20C34[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk1.sync0/Q
2.795 | 0.674 | tNET | RR | 1 | R20C36[1][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/rbin_Z[3]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R20C36[1][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/rbin_Z[3]/CLK
1.721 | 0.000 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/rbin_Z[3]
1.739 | 0.018 | tHld |  | 1 | R20C36[1][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/rbin_Z[3]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.674, 62.757%; tC2Q: 0.400, 37.243%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%

### Path16

Path Summary:

Slack | 1.056
Data Arrival Time | 2.795
Data Required Time | 1.739
From | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk1.sync0
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/rbin_Z[2]
Launch Clk | clk_rx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R20C34[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk1.sync0/CLK
2.121 | 0.400 | tC2Q | RR | 31 | R20C34[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk1.sync0/Q
2.795 | 0.674 | tNET | RR | 1 | R20C36[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/rbin_Z[2]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R20C36[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/rbin_Z[2]/CLK
1.721 | 0.000 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/rbin_Z[2]
1.739 | 0.018 | tHld |  | 1 | R20C36[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/rbin_Z[2]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.674, 62.757%; tC2Q: 0.400, 37.243%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%

### Path17

Path Summary:

Slack | 1.056
Data Arrival Time | 2.795
Data Required Time | 1.739
From | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk1.sync0
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/rbin_Z[1]
Launch Clk | clk_rx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R20C34[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk1.sync0/CLK
2.121 | 0.400 | tC2Q | RR | 31 | R20C34[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk1.sync0/Q
2.795 | 0.674 | tNET | RR | 1 | R20C36[2][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/rbin_Z[1]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R20C36[2][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/rbin_Z[1]/CLK
1.721 | 0.000 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/rbin_Z[1]
1.739 | 0.018 | tHld |  | 1 | R20C36[2][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/rbin_Z[1]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.674, 62.757%; tC2Q: 0.400, 37.243%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%

### Path18

Path Summary:

Slack | 1.329
Data Arrival Time | 3.068
Data Required Time | 1.739
From | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk2.sync1
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk10.U1/rbin_Z[3]
Launch Clk | clk_rx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R9C34[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk2.sync1/CLK
2.121 | 0.400 | tC2Q | RR | 31 | R9C34[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk2.sync1/Q
3.068 | 0.947 | tNET | RR | 1 | R9C35[1][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk10.U1/rbin_Z[3]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R9C35[1][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk10.U1/rbin_Z[3]/CLK
1.721 | 0.000 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk10.U1/rbin_Z[3]
1.739 | 0.018 | tHld |  | 1 | R9C35[1][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk10.U1/rbin_Z[3]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.947, 70.311%; tC2Q: 0.400, 29.689%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%

### Path19

Path Summary:

Slack | 1.343
Data Arrival Time | 3.082
Data Required Time | 1.739
From | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk3.sync2
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk11.U2/Full_Z
Launch Clk | clk_rx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R16C36[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk3.sync2/CLK
2.121 | 0.400 | tC2Q | RR | 31 | R16C36[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk3.sync2/Q
3.082 | 0.961 | tNET | RR | 1 | R16C35[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk11.U2/Full_Z/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R16C35[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk11.U2/Full_Z/CLK
1.721 | 0.000 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk11.U2/Full_Z
1.739 | 0.018 | tHld |  | 1 | R16C35[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk11.U2/Full_Z

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.961, 70.605%; tC2Q: 0.400, 29.395%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%

### Path20

Path Summary:

Slack | 1.343
Data Arrival Time | 3.082
Data Required Time | 1.739
From | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk3.sync2
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk11.U2/wq2_rptr_Z[1]
Launch Clk | clk_rx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R16C36[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk3.sync2/CLK
2.121 | 0.400 | tC2Q | RR | 31 | R16C36[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk3.sync2/Q
3.082 | 0.961 | tNET | RR | 1 | R16C35[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk11.U2/wq2_rptr_Z[1]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R16C35[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk11.U2/wq2_rptr_Z[1]/CLK
1.721 | 0.000 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk11.U2/wq2_rptr_Z[1]
1.739 | 0.018 | tHld |  | 1 | R16C35[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk11.U2/wq2_rptr_Z[1]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.961, 70.605%; tC2Q: 0.400, 29.395%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%

### Path21

Path Summary:

Slack | 1.343
Data Arrival Time | 3.082
Data Required Time | 1.739
From | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk3.sync2
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk11.U2/wq2_rptr_Z[0]
Launch Clk | clk_rx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R16C36[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk3.sync2/CLK
2.121 | 0.400 | tC2Q | RR | 31 | R16C36[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk3.sync2/Q
3.082 | 0.961 | tNET | RR | 1 | R16C35[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk11.U2/wq2_rptr_Z[0]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R16C35[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk11.U2/wq2_rptr_Z[0]/CLK
1.721 | 0.000 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk11.U2/wq2_rptr_Z[0]
1.739 | 0.018 | tHld |  | 1 | R16C35[1][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk11.U2/wq2_rptr_Z[0]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.961, 70.605%; tC2Q: 0.400, 29.395%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%

### Path22

Path Summary:

Slack | 1.343
Data Arrival Time | 3.082
Data Required Time | 1.739
From | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk3.sync2
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk11.U2/wbin_Z[3]
Launch Clk | clk_rx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R16C36[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk3.sync2/CLK
2.121 | 0.400 | tC2Q | RR | 31 | R16C36[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk3.sync2/Q
3.082 | 0.961 | tNET | RR | 1 | R16C35[1][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk11.U2/wbin_Z[3]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R16C35[1][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk11.U2/wbin_Z[3]/CLK
1.721 | 0.000 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk11.U2/wbin_Z[3]
1.739 | 0.018 | tHld |  | 1 | R16C35[1][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk11.U2/wbin_Z[3]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.961, 70.605%; tC2Q: 0.400, 29.395%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%

### Path23

Path Summary:

Slack | 1.343
Data Arrival Time | 3.082
Data Required Time | 1.739
From | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk3.sync2
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk11.U2/wbin_Z[2]
Launch Clk | clk_rx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R16C36[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk3.sync2/CLK
2.121 | 0.400 | tC2Q | RR | 31 | R16C36[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk3.sync2/Q
3.082 | 0.961 | tNET | RR | 1 | R16C35[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk11.U2/wbin_Z[2]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R16C35[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk11.U2/wbin_Z[2]/CLK
1.721 | 0.000 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk11.U2/wbin_Z[2]
1.739 | 0.018 | tHld |  | 1 | R16C35[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk11.U2/wbin_Z[2]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.961, 70.605%; tC2Q: 0.400, 29.395%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%

### Path24

Path Summary:

Slack | 1.343
Data Arrival Time | 3.082
Data Required Time | 1.739
From | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk3.sync2
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk11.U2/wbin_Z[1]
Launch Clk | clk_rx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R16C36[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk3.sync2/CLK
2.121 | 0.400 | tC2Q | RR | 31 | R16C36[2][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk3.sync2/Q
3.082 | 0.961 | tNET | RR | 1 | R16C35[2][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk11.U2/wbin_Z[1]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R16C35[2][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk11.U2/wbin_Z[1]/CLK
1.721 | 0.000 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk11.U2/wbin_Z[1]
1.739 | 0.018 | tHld |  | 1 | R16C35[2][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk11.U2/wbin_Z[1]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.961, 70.605%; tC2Q: 0.400, 29.395%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%

### Path25

Path Summary:

Slack | 1.368
Data Arrival Time | 3.107
Data Required Time | 1.739
From | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk1.sync0
To | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/wbin_Z[0]
Launch Clk | clk_rx:[R]
Latch Clk | clk_rx:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R20C34[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk1.sync0/CLK
2.121 | 0.400 | tC2Q | RR | 31 | R20C34[0][B] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk1.sync0/Q
3.107 | 0.986 | tNET | RR | 1 | R18C36[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/wbin_Z[0]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | clk_rx
0.000 | 0.000 | tCL | RR | 1134 | TOPSIDE[0] | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.721 | 1.721 | tNET | RR | 1 | R18C36[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/wbin_Z[0]/CLK
1.721 | 0.000 | tUnc |  |  |  | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/wbin_Z[0]
1.739 | 0.018 | tHld |  | 1 | R18C36[0][A] | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk6.ln0/genblk9.U0/wbin_Z[0]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.986, 71.141%; tC2Q: 0.400, 28.859%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.721, 100.000%

## Minimum Pulse Width Report:

#### Report Command:report_min_pulse_width -nworst 10 -detail

### MPW1

MPW Summary:

Slack: | 2.877
Actual Width: | 4.377
Required Width: | 1.500
Type: | Low Pulse Width
Clock: | clk_rx
Objects: | data_out_reg_Z[3]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | clk_rx
5.000 | 0.000 | tCL | FF | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
7.344 | 2.344 | tNET | FF | data_out_reg_Z[3]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | clk_rx
10.000 | 0.000 | tCL | RR | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
11.721 | 1.721 | tNET | RR | data_out_reg_Z[3]/CLK

### MPW2

MPW Summary:

Slack: | 2.877
Actual Width: | 4.377
Required Width: | 1.500
Type: | Low Pulse Width
Clock: | clk_rx
Objects: | data_out_reg_Z[1]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | clk_rx
5.000 | 0.000 | tCL | FF | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
7.344 | 2.344 | tNET | FF | data_out_reg_Z[1]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | clk_rx
10.000 | 0.000 | tCL | RR | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
11.721 | 1.721 | tNET | RR | data_out_reg_Z[1]/CLK

### MPW3

MPW Summary:

Slack: | 2.877
Actual Width: | 4.377
Required Width: | 1.500
Type: | Low Pulse Width
Clock: | clk_rx
Objects: | data_out_reg_Z[16]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | clk_rx
5.000 | 0.000 | tCL | FF | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
7.344 | 2.344 | tNET | FF | data_out_reg_Z[16]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | clk_rx
10.000 | 0.000 | tCL | RR | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
11.721 | 1.721 | tNET | RR | data_out_reg_Z[16]/CLK

### MPW4

MPW Summary:

Slack: | 2.877
Actual Width: | 4.377
Required Width: | 1.500
Type: | Low Pulse Width
Clock: | clk_rx
Objects: | data_out_reg_Z[8]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | clk_rx
5.000 | 0.000 | tCL | FF | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
7.344 | 2.344 | tNET | FF | data_out_reg_Z[8]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | clk_rx
10.000 | 0.000 | tCL | RR | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
11.721 | 1.721 | tNET | RR | data_out_reg_Z[8]/CLK

### MPW5

MPW Summary:

Slack: | 2.877
Actual Width: | 4.377
Required Width: | 1.500
Type: | Low Pulse Width
Clock: | clk_rx
Objects: | data_out_reg_Z[22]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | clk_rx
5.000 | 0.000 | tCL | FF | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
7.344 | 2.344 | tNET | FF | data_out_reg_Z[22]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | clk_rx
10.000 | 0.000 | tCL | RR | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
11.721 | 1.721 | tNET | RR | data_out_reg_Z[22]/CLK

### MPW6

MPW Summary:

Slack: | 2.877
Actual Width: | 4.377
Required Width: | 1.500
Type: | Low Pulse Width
Clock: | clk_rx
Objects: | data_out_reg_Z[50]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | clk_rx
5.000 | 0.000 | tCL | FF | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
7.344 | 2.344 | tNET | FF | data_out_reg_Z[50]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | clk_rx
10.000 | 0.000 | tCL | RR | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
11.721 | 1.721 | tNET | RR | data_out_reg_Z[50]/CLK

### MPW7

MPW Summary:

Slack: | 2.877
Actual Width: | 4.377
Required Width: | 1.500
Type: | Low Pulse Width
Clock: | clk_rx
Objects: | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/reg3_Z[3]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | clk_rx
5.000 | 0.000 | tCL | FF | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
7.344 | 2.344 | tNET | FF | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/reg3_Z[3]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | clk_rx
10.000 | 0.000 | tCL | RR | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
11.721 | 1.721 | tNET | RR | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk1.wd3/reg3_Z[3]/CLK

### MPW8

MPW Summary:

Slack: | 2.877
Actual Width: | 4.377
Required Width: | 1.500
Type: | Low Pulse Width
Clock: | clk_rx
Objects: | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/reg1_Z[8]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | clk_rx
5.000 | 0.000 | tCL | FF | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
7.344 | 2.344 | tNET | FF | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/reg1_Z[8]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | clk_rx
10.000 | 0.000 | tCL | RR | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
11.721 | 1.721 | tNET | RR | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk2.wd2/reg1_Z[8]/CLK

### MPW9

MPW Summary:

Slack: | 2.877
Actual Width: | 4.377
Required Width: | 1.500
Type: | Low Pulse Width
Clock: | clk_rx
Objects: | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/out[7]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | clk_rx
5.000 | 0.000 | tCL | FF | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
7.344 | 2.344 | tNET | FF | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/out[7]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | clk_rx
10.000 | 0.000 | tCL | RR | u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
11.721 | 1.721 | tNET | RR | u_DPHY_RX_TOP/DPHY_RX_INST/u_Aligner/genblk4.wd0/out[7]/CLK

### MPW10

MPW Summary:

Slack: | 2.877
Actual Width: | 4.377
Required Width: | 1.500
Type: | Low Pulse Width
Clock: | clk_tx
Objects: | u_ROM549x17/addr_Z[6]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | clk_tx
5.000 | 0.000 | tCL | FF | u_DPHY_TX_TOP/DPHY_TX_INST/u_oserx8/U3_CLKDIV/CLKOUT
7.344 | 2.344 | tNET | FF | u_ROM549x17/addr_Z[6]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | clk_tx
10.000 | 0.000 | tCL | RR | u_DPHY_TX_TOP/DPHY_TX_INST/u_oserx8/U3_CLKDIV/CLKOUT
11.721 | 1.721 | tNET | RR | u_ROM549x17/addr_Z[6]/CLK

## High Fanout Nets Report:

#### Report Command:report_high_fanout_nets -max_nets 10

FANOUT | NET NAME | WORST SLACK | MAX DELAY
--- | --- | --- | ---
1134 | clk_byte_out | -2.822 | 2.344
774 | en_align_i | 1.290 | 3.659
34 | sclk_tx | 1.290 | 2.344
31 | sync0 | 6.051 | 2.629
31 | sync1 | 5.922 | 2.629
31 | sync2 | 6.189 | 2.036
31 | sync3 | 6.629 | 2.028
27 | ready_c | 5.877 | 3.721
23 | ready_rep1 | 6.840 | 2.813
23 | ready_rep2 | 7.345 | 2.406

## Route Congestions Report:

#### Report Command:report_route_congestion -max_grids 10

GRID LOC | ROUTE CONGESTIONS
--- | ---
R17C22 | 0.833
R17C10 | 0.806
R17C9 | 0.792
R11C20 | 0.778
R16C10 | 0.764
R18C21 | 0.750
R17C23 | 0.750
R11C8 | 0.722
R17C12 | 0.722
R18C20 | 0.708

## Timing Exceptions Report:

### Setup Analysis Report

#### Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

#### No timing exceptions to report!

### Hold Analysis Report

#### Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

#### No timing exceptions to report!

### Recovery Analysis Report

#### Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

#### No timing exceptions to report!

### Removal Analysis Report

#### Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

#### No timing exceptions to report!

## Timing Constraints Report:

SDC Command Type | State | Detail Command
--- | --- | ---
TC_CLOCK | Actived | create_clock -name clk_tx -period 10 -waveform {0 5} [get_pins {u_DPHY_TX_TOP/DPHY_TX_INST/u_oserx8/U3_CLKDIV/CLKOUT}]
TC_CLOCK | Actived | create_clock -name clk_rx -period 10 -waveform {0 5} [get_pins {u_DPHY_RX_TOP/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT}]