# Written by Synplify Pro version mapgw2019q1p1, Build 007R. Synopsys Run ID: sid1585201444 
# Top Level Design Parameters 

# Clocks 
create_clock -period 7.468 -waveform {0.000 3.734} -name {_~idesx8_DPHY_RX_TOP_|sclk_inferred_clock} [get_pins {DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT}] 
create_clock -period 3.038 -waveform {0.000 1.519} -name {_~DPHY_RX_DPHY_RX_TOP_|HS_CLK_inferred_clock} [get_pins {DPHY_RX_INST/U0_IB/O}] 

# Virtual Clocks 

# Generated Clocks 

# Paths Between Clocks 

# Multicycle Constraints 

# Point-to-point Delay Constraints 

# False Path Constraints 

# Output Load Constraints 

# Driving Cell Constraints 

# Input Delay Constraints 

# Output Delay Constraints 

# Wire Loads 

# Other Constraints 

# syn_hier Attributes 

# set_case Attributes 

# Clock Delay Constraints 
set Autoconstr_clkgroup_0 [list _~idesx8_DPHY_RX_TOP_|sclk_inferred_clock]
set Autoconstr_clkgroup_1 [list _~DPHY_RX_DPHY_RX_TOP_|HS_CLK_inferred_clock]
set_clock_groups -asynchronous -group $Autoconstr_clkgroup_0 -group $Autoconstr_clkgroup_1

# syn_mode Attributes 

# Cells 

# Port DRC Rules 

# Input Transition Constraints 

# Unused constraints (intentionally commented out) 

# Non-forward-annotatable constraints (intentionally commented out) 

# Block Path constraints 

