Selecting top level module DPHY_TOP
@N: CG364 :"E:\Gowin\Gowin_V1.9.3Beta_37257_win\SynplifyPro\lib\generic\gw1n.v":2313:7:2313:9|Synthesizing module PLL in library work.
Running optimization stage 1 on PLL .......
@N: CG364 :"E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\src\gw_pll.v":14:7:14:12|Synthesizing module GW_PLL in library work.
Running optimization stage 1 on GW_PLL .......
@N: CG364 :"E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\src\ROM549X17.v":20:7:20:15|Synthesizing module ROM549x17 in library work.
Running optimization stage 1 on ROM549x17 .......
@N: CG364 :"E:\Gowin\Gowin_V1.9.3Beta_37257_win\SynplifyPro\lib\generic\gw1n.v":2377:7:2377:9|Synthesizing module GSR in library work.
Running optimization stage 1 on GSR .......
Running optimization stage 1 on GND .......
Running optimization stage 1 on VCC .......
Running optimization stage 1 on \~pllx8.DPHY_TX_TOP_  .......
Running optimization stage 1 on INV .......
Running optimization stage 1 on ELVDS_TBUF .......
Running optimization stage 1 on CLKDIV .......
Running optimization stage 1 on OSER16 .......
Running optimization stage 1 on \~oserx8.DPHY_TX_TOP_  .......
Running optimization stage 1 on \~DPHY_TX.DPHY_TX_TOP_  .......
@N: CG364 :"E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\src\DPHY_TX_TOP\DPHY_TX_TOP.v":451:7:451:17|Synthesizing module DPHY_TX_TOP in library work.
Running optimization stage 1 on DPHY_TX_TOP .......
@W: CL168 :"E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\src\DPHY_TX_TOP\DPHY_TX_TOP.v":534:6:534:11|Removing instance GND_cZ because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
Running optimization stage 1 on ELVDS_IBUF .......
Running optimization stage 1 on LUT1 .......
Running optimization stage 1 on LUT2 .......
Running optimization stage 1 on DFFCE .......
Running optimization stage 1 on DFFPE .......
Running optimization stage 1 on IODELAY .......
Running optimization stage 1 on DHCEN .......
Running optimization stage 1 on IDES16 .......
Running optimization stage 1 on \~idesx8.DPHY_RX_TOP_  .......
Running optimization stage 1 on MUX2_LUT5 .......
Running optimization stage 1 on MUX2_LUT6 .......
Running optimization stage 1 on MUX2_LUT7 .......
Running optimization stage 1 on LUT4 .......
Running optimization stage 1 on LUT3 .......
Running optimization stage 1 on DFFC .......
Running optimization stage 1 on \~word_aligner.DPHY_RX_TOP__6  .......
Running optimization stage 1 on \~word_aligner.DPHY_RX_TOP__6_0  .......
Running optimization stage 1 on \~word_aligner.DPHY_RX_TOP__6_1  .......
Running optimization stage 1 on \~word_aligner.DPHY_RX_TOP__6_2  .......
Running optimization stage 1 on DFFE .......
Running optimization stage 1 on RAM16SDP4 .......
Running optimization stage 1 on \~lane_align_FIFO.DPHY_RX_TOP_  .......
Running optimization stage 1 on \~lane_align_FIFO.DPHY_RX_TOP__3  .......
Running optimization stage 1 on \~lane_align_FIFO.DPHY_RX_TOP__4  .......
Running optimization stage 1 on \~lane_align_FIFO.DPHY_RX_TOP__5  .......
Running optimization stage 1 on \~lane_aligner.DPHY_RX_TOP__4s  .......
Running optimization stage 1 on \~Aligner.DPHY_RX_TOP__4s_1s_1s  .......
Running optimization stage 1 on \~DPHY_RX.DPHY_RX_TOP_  .......
@N: CG364 :"E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\src\DPHY_RX_TOP\DPHY_RX_TOP.v":19809:7:19809:17|Synthesizing module DPHY_RX_TOP in library work.
Running optimization stage 1 on DPHY_RX_TOP .......
@N: CG364 :"E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\src\DPHY_TOP.v":99:7:99:14|Synthesizing module DPHY_TOP in library work.
@W: CG133 :"E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\src\DPHY_TOP.v":166:15:166:21|Object data_in is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\src\DPHY_TOP.v":167:15:167:19|Object data0 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\src\DPHY_TOP.v":167:22:167:26|Object data1 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\src\DPHY_TOP.v":167:29:167:33|Object data2 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\src\DPHY_TOP.v":167:36:167:40|Object data3 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\src\DPHY_TOP.v":168:15:168:18|Object dout is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\src\DPHY_TOP.v":169:15:169:23|Object data_cntr is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\src\DPHY_TOP.v":170:15:170:29|Object hactive_flag_RX is declared but not assigned. Either assign a value or remove the declaration.
@W: CG360 :"E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\src\DPHY_TOP.v":172:15:172:24|Removing wire lp_clk_out, as there is no assignment to it.
@W: CG360 :"E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\src\DPHY_TOP.v":172:26:172:37|Removing wire lp_data0_out, as there is no assignment to it.
@W: CG360 :"E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\src\DPHY_TOP.v":172:39:172:50|Removing wire lp_data1_out, as there is no assignment to it.
@W: CG360 :"E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\src\DPHY_TOP.v":172:52:172:63|Removing wire lp_data2_out, as there is no assignment to it.
@W: CG360 :"E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\src\DPHY_TOP.v":172:65:172:76|Removing wire lp_data3_out, as there is no assignment to it.
@W: CG133 :"E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\src\DPHY_TOP.v":195:16:195:20|Object hs_en is declared but not assigned. Either assign a value or remove the declaration.
Running optimization stage 1 on DPHY_TOP .......
Running optimization stage 2 on DPHY_TOP .......
@W: CL156 :"E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\src\DPHY_TOP.v":172:15:172:24|*Input lp_clk_out[1:0] to expression [ror] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
Running optimization stage 2 on DPHY_RX_TOP .......
@N: CL159 :"E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\src\DPHY_RX_TOP\DPHY_RX_TOP.v":19848:6:19848:12|Input term_en is unused.
Running optimization stage 2 on \~DPHY_RX.DPHY_RX_TOP_  .......
Running optimization stage 2 on \~Aligner.DPHY_RX_TOP__4s_1s_1s  .......
Running optimization stage 2 on \~lane_aligner.DPHY_RX_TOP__4s  .......
Running optimization stage 2 on \~lane_align_FIFO.DPHY_RX_TOP__5  .......
Running optimization stage 2 on \~lane_align_FIFO.DPHY_RX_TOP__4  .......
Running optimization stage 2 on \~lane_align_FIFO.DPHY_RX_TOP__3  .......
Running optimization stage 2 on \~lane_align_FIFO.DPHY_RX_TOP_  .......
Running optimization stage 2 on RAM16SDP4 .......
Running optimization stage 2 on DFFE .......
Running optimization stage 2 on \~word_aligner.DPHY_RX_TOP__6_2  .......
Running optimization stage 2 on \~word_aligner.DPHY_RX_TOP__6_1  .......
Running optimization stage 2 on \~word_aligner.DPHY_RX_TOP__6_0  .......
Running optimization stage 2 on \~word_aligner.DPHY_RX_TOP__6  .......
Running optimization stage 2 on DFFC .......
Running optimization stage 2 on LUT3 .......
Running optimization stage 2 on LUT4 .......
Running optimization stage 2 on MUX2_LUT7 .......
Running optimization stage 2 on MUX2_LUT6 .......
Running optimization stage 2 on MUX2_LUT5 .......
Running optimization stage 2 on \~idesx8.DPHY_RX_TOP_  .......
Running optimization stage 2 on IDES16 .......
Running optimization stage 2 on DHCEN .......
Running optimization stage 2 on IODELAY .......
Running optimization stage 2 on DFFPE .......
Running optimization stage 2 on DFFCE .......
Running optimization stage 2 on LUT2 .......
Running optimization stage 2 on LUT1 .......
Running optimization stage 2 on ELVDS_IBUF .......
Running optimization stage 2 on DPHY_TX_TOP .......
Running optimization stage 2 on \~DPHY_TX.DPHY_TX_TOP_  .......
Running optimization stage 2 on \~oserx8.DPHY_TX_TOP_  .......
Running optimization stage 2 on OSER16 .......
Running optimization stage 2 on CLKDIV .......
Running optimization stage 2 on ELVDS_TBUF .......
Running optimization stage 2 on INV .......
Running optimization stage 2 on \~pllx8.DPHY_TX_TOP_  .......
Running optimization stage 2 on VCC .......
Running optimization stage 2 on GND .......
Running optimization stage 2 on GSR .......
Running optimization stage 2 on ROM549x17 .......
Running optimization stage 2 on GW_PLL .......
Running optimization stage 2 on PLL .......

For a summary of runtime and memory usage per design unit, please see file:
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@L: E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\impl\synthesize\rev_1\synwork\layer0.rt.csv

