#Build: Synplify Pro (R) P-2019.03G-1-Beta1, Build 387R, Dec  3 2019
#install: E:\Gowin\Gowin_V1.9.3Beta_37257_win\SynplifyPro
#OS: Windows 7 6.1
#Hostname: GW-SW-001

# Thu Mar 26 13:43:58 2020

#Implementation: rev_1


Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03G-1-Beta1
Install: E:\Gowin\Gowin_V1.9.3Beta_37257_win\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-001

Implementation : rev_1
Synopsys HDL Compiler, Version comp2019q1p1, Build 391R, Built Dec  3 2019 09:16:34

@N|Running in 64-bit mode
###########################################################[

Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03G-1-Beta1
Install: E:\Gowin\Gowin_V1.9.3Beta_37257_win\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-001

Implementation : rev_1
Synopsys Verilog Compiler, Version comp2019q1p1, Build 391R, Built Dec  3 2019 09:16:34

@N|Running in 64-bit mode
@N: CG1349 :	| Running Verilog Compiler in System Verilog mode

@N: CG1350 :	| Running Verilog Compiler in Multiple File Compilation Unit mode

@I::"E:\Gowin\Gowin_V1.9.3Beta_37257_win\SynplifyPro\lib\generic\gw1n.v" (library work)
@I::"E:\Gowin\Gowin_V1.9.3Beta_37257_win\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"E:\Gowin\Gowin_V1.9.3Beta_37257_win\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps)
@I::"E:\Gowin\Gowin_V1.9.3Beta_37257_win\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"E:\Gowin\Gowin_V1.9.3Beta_37257_win\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"E:\Gowin\Gowin_V1.9.3Beta_37257_win\IDE\ipcore\MIPI_RX\data\DPHY_RX.v" (library work)
@I:"E:\Gowin\Gowin_V1.9.3Beta_37257_win\IDE\ipcore\MIPI_RX\data\DPHY_RX.v":"E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\src\DPHY_RX_TOP\temp\MIPI_Rx\dphy_define.v" (library work)
@W: CG1337 :"E:\Gowin\Gowin_V1.9.3Beta_37257_win\IDE\ipcore\MIPI_RX\data\DPHY_RX.v":3884:13:3884:23|Net arempty_val is not declared.
@W: CG1337 :"E:\Gowin\Gowin_V1.9.3Beta_37257_win\IDE\ipcore\MIPI_RX\data\DPHY_RX.v":3918:13:3918:22|Net awfull_val is not declared.
@W: CG1337 :"E:\Gowin\Gowin_V1.9.3Beta_37257_win\IDE\ipcore\MIPI_RX\data\DPHY_RX.v":4196:14:4196:21|Net clk_byte is not declared.
@W: CG1337 :"E:\Gowin\Gowin_V1.9.3Beta_37257_win\IDE\ipcore\MIPI_RX\data\DPHY_RX.v":4696:13:4696:23|Net arempty_val is not declared.
@W: CG1337 :"E:\Gowin\Gowin_V1.9.3Beta_37257_win\IDE\ipcore\MIPI_RX\data\DPHY_RX.v":4730:13:4730:22|Net awfull_val is not declared.
@I::"E:\Gowin\Gowin_V1.9.3Beta_37257_win\IDE\ipcore\MIPI_RX\data\DPHY_RX_TOP.v" (library work)
Verilog syntax check successful!
Selecting top level module DPHY_RX_TOP
Running optimization stage 1 on ELVDS_IBUF .......
Running optimization stage 1 on LUT4 .......
Running optimization stage 1 on IDES16 .......
Running optimization stage 1 on DHCEN .......
Running optimization stage 1 on CLKDIV .......
Running optimization stage 1 on IODELAY .......
Running optimization stage 1 on \~idesx8.DPHY_RX_TOP  .......
Running optimization stage 1 on \~word_aligner.DPHY_RX_TOP  .......
Running optimization stage 1 on \~lane_align_FIFO.DPHY_RX_TOP  .......
Running optimization stage 1 on \~lane_aligner.DPHY_RX_TOP _4s .......
Running optimization stage 1 on \~Aligner.DPHY_RX_TOP _4s_1s_1s .......
Running optimization stage 1 on \~DPHY_RX.DPHY_RX_TOP  .......
@N: CG364 :"E:\Gowin\Gowin_V1.9.3Beta_37257_win\IDE\ipcore\MIPI_RX\data\DPHY_RX_TOP.v":193:22:193:22|Synthesizing module DPHY_RX_TOP in library work.
Running optimization stage 1 on DPHY_RX_TOP .......
Running optimization stage 2 on DPHY_RX_TOP .......
Running optimization stage 2 on \~DPHY_RX.DPHY_RX_TOP  .......
Running optimization stage 2 on \~lane_align_FIFO.DPHY_RX_TOP  .......
Running optimization stage 2 on \~lane_aligner.DPHY_RX_TOP _4s .......
Running optimization stage 2 on \~word_aligner.DPHY_RX_TOP  .......
Running optimization stage 2 on \~Aligner.DPHY_RX_TOP _4s_1s_1s .......
Running optimization stage 2 on \~idesx8.DPHY_RX_TOP  .......
Running optimization stage 2 on IODELAY .......
Running optimization stage 2 on CLKDIV .......
Running optimization stage 2 on DHCEN .......
Running optimization stage 2 on IDES16 .......
Running optimization stage 2 on LUT4 .......
Running optimization stage 2 on ELVDS_IBUF .......

For a summary of runtime and memory usage per design unit, please see file:
==========================================================
@L: E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\src\DPHY_RX_TOP\temp\MIPI_Rx\rev_1\synwork\layer0.rt.csv


At c_ver Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 92MB peak: 98MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Thu Mar 26 13:43:59 2020

###########################################################]
###########################################################[

Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03G-1-Beta1
Install: E:\Gowin\Gowin_V1.9.3Beta_37257_win\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-001

Implementation : rev_1
Synopsys Synopsys Netlist Linker, Version comp2019q1p1, Build 391R, Built Dec  3 2019 09:16:34

@N|Running in 64-bit mode
@N: NF107 :"e:\gowin\gowin_v1.9.3beta_37257_win\ide\ipcore\mipi_rx\data\dphy_rx_top.v":193:22:193:22|Selected library: work cell: DPHY_RX_TOP view verilog as top level
@N: NF107 :"e:\gowin\gowin_v1.9.3beta_37257_win\ide\ipcore\mipi_rx\data\dphy_rx_top.v":193:22:193:22|Selected library: work cell: DPHY_RX_TOP view verilog as top level

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 88MB peak: 88MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Thu Mar 26 13:44:00 2020

###########################################################]

For a summary of runtime and memory usage for all design units, please see file:
==========================================================
@L: E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\src\DPHY_RX_TOP\temp\MIPI_Rx\rev_1\synwork\DPHY_RX_TOP_comp.rt.csv

@END

At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 18MB peak: 18MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Thu Mar 26 13:44:00 2020

###########################################################]
###########################################################[

Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03G-1-Beta1
Install: E:\Gowin\Gowin_V1.9.3Beta_37257_win\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-001

Implementation : rev_1
Synopsys Synopsys Netlist Linker, Version comp2019q1p1, Build 391R, Built Dec  3 2019 09:16:34

@N|Running in 64-bit mode
@N: NF107 :"e:\gowin\gowin_v1.9.3beta_37257_win\ide\ipcore\mipi_rx\data\dphy_rx_top.v":193:22:193:22|Selected library: work cell: DPHY_RX_TOP view verilog as top level
@N: NF107 :"e:\gowin\gowin_v1.9.3beta_37257_win\ide\ipcore\mipi_rx\data\dphy_rx_top.v":193:22:193:22|Selected library: work cell: DPHY_RX_TOP view verilog as top level

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 88MB peak: 88MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Thu Mar 26 13:44:01 2020

###########################################################]
Premap Report

# Thu Mar 26 13:44:02 2020


Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03G-1-Beta1
Install: E:\Gowin\Gowin_V1.9.3Beta_37257_win\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-001

Implementation : rev_1
Synopsys Generic Technology Pre-mapping, Version mapgw2019q1p1, Build 007R, Built Dec  5 2019 10:27:23


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)

@A: MF827 |No constraint file specified.
@L: E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\src\DPHY_RX_TOP\temp\MIPI_Rx\rev_1\DPHY_RX_TOP_scck.rpt 
Printing clock  summary report in "E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\src\DPHY_RX_TOP\temp\MIPI_Rx\rev_1\DPHY_RX_TOP_scck.rpt" file 
@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 128MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB)


Starting clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 222MB peak: 222MB)


Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 222MB peak: 222MB)


Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 222MB peak: 223MB)


Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 223MB peak: 223MB)


Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 223MB peak: 223MB)



Clock Summary
******************

          Start                                            Requested     Requested     Clock        Clock                     Clock
Level     Clock                                            Frequency     Period        Type         Group                     Load 
-----------------------------------------------------------------------------------------------------------------------------------
0 -       System                                           100.0 MHz     10.000        system       system_clkgroup           4    
                                                                                                                                   
0 -       _~idesx8_DPHY_RX_TOP_|sclk_inferred_clock        206.3 MHz     4.848         inferred     Autoconstr_clkgroup_0     877  
                                                                                                                                   
0 -       _~DPHY_RX_DPHY_RX_TOP_|HS_CLK_inferred_clock     563.4 MHz     1.775         inferred     Autoconstr_clkgroup_1     4    
===================================================================================================================================



Clock Load Summary
***********************

                                                 Clock     Source                                                Clock Pin                                                        Non-clock Pin     Non-clock Pin
Clock                                            Load      Pin                                                   Seq Example                                                      Seq Example       Comb Example 
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
System                                           4         -                                                     DPHY_RX_INST.u_idesx8.Inst4_IDES16_3.FCLK                        -                 -            
                                                                                                                                                                                                                 
_~idesx8_DPHY_RX_TOP_|sclk_inferred_clock        877       DPHY_RX_INST.u_idesx8.Inst3_CLKDIV.CLKOUT(CLKDIV)     DPHY_RX_INST.u_Aligner.genblk6\.ln0.genblk1\.q_in0_0[15:0].C     -                 -            
                                                                                                                                                                                                                 
_~DPHY_RX_DPHY_RX_TOP_|HS_CLK_inferred_clock     4         DPHY_RX_INST.U0_IB.O(ELVDS_IBUF)                      DPHY_RX_INST.u_idesx8.opensync[3:0].C                            -                 -            
=================================================================================================================================================================================================================


ICG Latch Removal Summary:
Number of ICG latches removed: 0
Number of ICG latches not removed:	0


@S |Clock Optimization Summary



#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[

0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
3 gated/generated clock tree(s) driving 825 clock pin(s) of sequential element(s)
0 instances converted, 825 sequential instances remain driven by gated/generated clocks

============================================================= Gated/Generated Clocks =============================================================
Clock Tree ID     Driving Element     Drive Element Type     Unconverted Fanout     Sample Instance     Explanation                               
--------------------------------------------------------------------------------------------------------------------------------------------------
@KP:ckid0_1       ENCRYPTED           CLKDIV                 817                    ENCRYPTED           Black box on clock path                   
@KP:ckid0_2       ENCRYPTED           ELVDS_IBUF             4                      ENCRYPTED           Derived clock on input (not legal for GCC)
@KP:ckid0_3       ENCRYPTED           DHCEN                  4                      ENCRYPTED           Black box on clock path                   
==================================================================================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######

@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
Finished Pre Mapping Phase.
@N: BN225 |Writing default property annotation file E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\src\DPHY_RX_TOP\temp\MIPI_Rx\rev_1\DPHY_RX_TOP.sap.

Starting constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 223MB peak: 223MB)


Finished constraint checker preprocessing (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 223MB peak: 223MB)


Finished constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 224MB peak: 224MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 145MB peak: 226MB)

Process took 0h:00m:02s realtime, 0h:00m:02s cputime
# Thu Mar 26 13:44:04 2020

###########################################################]
Map & Optimize Report

# Thu Mar 26 13:44:04 2020


Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03G-1-Beta1
Install: E:\Gowin\Gowin_V1.9.3Beta_37257_win\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-001

Implementation : rev_1
Synopsys Generic Technology Mapper, Version mapgw2019q1p1, Build 007R, Built Dec  5 2019 10:27:23


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)

@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 119MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 119MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 122MB peak: 122MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 137MB)



Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 217MB peak: 217MB)


Available hyper_sources - for debug and ip models
	None Found

@N: MT206 |Auto Constrain mode is enabled

Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 222MB peak: 222MB)


Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 227MB peak: 227MB)


Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 227MB peak: 227MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 230MB peak: 230MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 231MB peak: 231MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:03s; Memory used current: 232MB peak: 232MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 232MB peak: 232MB)


Finished preparing to map (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 232MB peak: 232MB)


Finished technology mapping (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 241MB peak: 241MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:04s		    -2.30ns		1022 /       817
Timing driven replication report
Added 125 Registers via timing driven replication
Added 0 LUTs via timing driven replication

   2		0h:00m:05s		    -2.30ns		1016 /       942

   3		0h:00m:05s		    -2.30ns		1016 /       942

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 242MB peak: 242MB)

@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  

Finished restoring hierarchy (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 242MB peak: 242MB)


Start Writing Netlists (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 167MB peak: 242MB)

Writing Analyst data base E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\src\DPHY_RX_TOP\temp\MIPI_Rx\rev_1\synwork\DPHY_RX_TOP_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 240MB peak: 242MB)

Writing Verilog Simulation files

Writing scf file... (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:08s; Memory used current: 240MB peak: 242MB)

@N: BW103 |The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns.
@N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF 

Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:08s; Memory used current: 240MB peak: 242MB)


Start final timing analysis (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:09s; Memory used current: 237MB peak: 242MB)

@W: MT246 :"e:\gowin\gowin_v1.9.3beta_37257_win\ide\ipcore\mipi_rx\data\dphy_rx.v":4357:11:4357:22|Blackbox CLKDIV is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W: MT246 :"e:\gowin\gowin_v1.9.3beta_37257_win\ide\ipcore\mipi_rx\data\dphy_rx.v":4354:10:4354:16|Blackbox DHCEN is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W: MT420 |Found inferred clock _~idesx8_DPHY_RX_TOP_|sclk_inferred_clock with period 7.47ns. Please declare a user-defined clock on net DPHY_RX_INST.u_idesx8.clk_byte_out.
@W: MT420 |Found inferred clock _~DPHY_RX_DPHY_RX_TOP_|HS_CLK_inferred_clock with period 3.04ns. Please declare a user-defined clock on net DPHY_RX_INST.HS_CLK.


##### START OF TIMING REPORT #####[
# Timing report written on Thu Mar 26 13:44:14 2020
#


Top view:               DPHY_RX_TOP
Requested Frequency:    133.9 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.

@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.



Performance Summary
*******************


Worst slack in design: -1.318

                                                 Requested     Estimated     Requested     Estimated                Clock        Clock                
Starting Clock                                   Frequency     Frequency     Period        Period        Slack      Type         Group                
------------------------------------------------------------------------------------------------------------------------------------------------------
_~DPHY_RX_DPHY_RX_TOP_|HS_CLK_inferred_clock     329.2 MHz     279.8 MHz     3.038         3.574         -0.536     inferred     Autoconstr_clkgroup_1
_~idesx8_DPHY_RX_TOP_|sclk_inferred_clock        133.9 MHz     113.8 MHz     7.468         8.786         -1.318     inferred     Autoconstr_clkgroup_0
System                                           288.1 MHz     244.9 MHz     3.471         4.083         -0.612     system       system_clkgroup      
======================================================================================================================================================





Clock Relationships
*******************

Clocks                                                                                      |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Starting                                      Ending                                        |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
System                                        System                                        |  3.471       -0.612  |  No paths    -      |  No paths    -      |  No paths    -    
System                                        _~idesx8_DPHY_RX_TOP_|sclk_inferred_clock     |  7.468       6.314   |  No paths    -      |  No paths    -      |  No paths    -    
_~idesx8_DPHY_RX_TOP_|sclk_inferred_clock     System                                        |  7.468       6.080   |  No paths    -      |  No paths    -      |  No paths    -    
_~idesx8_DPHY_RX_TOP_|sclk_inferred_clock     _~idesx8_DPHY_RX_TOP_|sclk_inferred_clock     |  7.468       -1.318  |  No paths    -      |  No paths    -      |  No paths    -    
_~DPHY_RX_DPHY_RX_TOP_|HS_CLK_inferred_clock  System                                        |  3.038       -0.470  |  No paths    -      |  No paths    -      |  No paths    -    
_~DPHY_RX_DPHY_RX_TOP_|HS_CLK_inferred_clock  _~DPHY_RX_DPHY_RX_TOP_|HS_CLK_inferred_clock  |  3.038       -0.536  |  No paths    -      |  No paths    -      |  No paths    -    
===================================================================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: _~DPHY_RX_DPHY_RX_TOP_|HS_CLK_inferred_clock
====================================



Starting Points with Worst Slack
********************************

                                      Starting                                                                           Arrival           
Instance                              Reference                                        Type      Pin     Net             Time        Slack 
                                      Clock                                                                                                
-------------------------------------------------------------------------------------------------------------------------------------------
DPHY_RX_INST.u_idesx8.opensync[3]     _~DPHY_RX_DPHY_RX_TOP_|HS_CLK_inferred_clock     DFFCE     Q       opensync[3]     0.367       -0.536
DPHY_RX_INST.u_idesx8.opensync[0]     _~DPHY_RX_DPHY_RX_TOP_|HS_CLK_inferred_clock     DFFPE     Q       opensync[0]     0.367       -0.470
DPHY_RX_INST.u_idesx8.opensync[1]     _~DPHY_RX_DPHY_RX_TOP_|HS_CLK_inferred_clock     DFFCE     Q       opensync[1]     0.367       -0.403
DPHY_RX_INST.u_idesx8.opensync[2]     _~DPHY_RX_DPHY_RX_TOP_|HS_CLK_inferred_clock     DFFCE     Q       opensync[2]     0.367       1.517 
===========================================================================================================================================


Ending Points with Worst Slack
******************************

                                      Starting                                                                             Required           
Instance                              Reference                                        Type      Pin     Net               Time         Slack 
                                      Clock                                                                                                   
----------------------------------------------------------------------------------------------------------------------------------------------
DPHY_RX_INST.u_idesx8.opensync[0]     _~DPHY_RX_DPHY_RX_TOP_|HS_CLK_inferred_clock     DFFPE     CE      opensync_cken     2.905        -0.536
DPHY_RX_INST.u_idesx8.opensync[1]     _~DPHY_RX_DPHY_RX_TOP_|HS_CLK_inferred_clock     DFFCE     CE      opensync_cken     2.905        -0.536
DPHY_RX_INST.u_idesx8.opensync[2]     _~DPHY_RX_DPHY_RX_TOP_|HS_CLK_inferred_clock     DFFCE     CE      opensync_cken     2.905        -0.536
DPHY_RX_INST.u_idesx8.opensync[3]     _~DPHY_RX_DPHY_RX_TOP_|HS_CLK_inferred_clock     DFFCE     CE      opensync_cken     2.905        -0.536
DPHY_RX_INST.u_idesx8.u_DHCEN         _~DPHY_RX_DPHY_RX_TOP_|HS_CLK_inferred_clock     DHCEN     CE      xstop             3.038        -0.470
DPHY_RX_INST.u_idesx8.opensync[0]     _~DPHY_RX_DPHY_RX_TOP_|HS_CLK_inferred_clock     DFFPE     D       opensync[3]       2.905        1.517 
DPHY_RX_INST.u_idesx8.opensync[1]     _~DPHY_RX_DPHY_RX_TOP_|HS_CLK_inferred_clock     DFFCE     D       opensync[0]       2.905        1.517 
DPHY_RX_INST.u_idesx8.opensync[2]     _~DPHY_RX_DPHY_RX_TOP_|HS_CLK_inferred_clock     DFFCE     D       opensync[1]       2.905        1.517 
DPHY_RX_INST.u_idesx8.opensync[3]     _~DPHY_RX_DPHY_RX_TOP_|HS_CLK_inferred_clock     DFFCE     D       opensync[2]       2.905        1.517 
==============================================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      3.038
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         2.905

    - Propagation time:                      3.441
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.536

    Number of logic level(s):                1
    Starting point:                          DPHY_RX_INST.u_idesx8.opensync[3] / Q
    Ending point:                            DPHY_RX_INST.u_idesx8.opensync[0] / CE
    The start point is clocked by            _~DPHY_RX_DPHY_RX_TOP_|HS_CLK_inferred_clock [rising] on pin CLK
    The end   point is clocked by            _~DPHY_RX_DPHY_RX_TOP_|HS_CLK_inferred_clock [rising] on pin CLK

Instance / Net                                  Pin      Pin               Arrival     No. of    
Name                                  Type      Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------
DPHY_RX_INST.u_idesx8.opensync[3]     DFFCE     Q        Out     0.367     0.367       -         
opensync[3]                           Net       -        -       1.021     -           2         
DPHY_RX_INST.u_idesx8.LUT4_1          LUT1      I0       In      -         1.388       -         
DPHY_RX_INST.u_idesx8.LUT4_1          LUT1      F        Out     1.032     2.420       -         
opensync_cken                         Net       -        -       1.021     -           4         
DPHY_RX_INST.u_idesx8.opensync[0]     DFFPE     CE       In      -         3.441       -         
=================================================================================================
Total path delay (propagation time + setup) of 3.574 is 1.532(42.9%) logic and 2.042(57.1%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      3.038
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         2.905

    - Propagation time:                      3.441
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.536

    Number of logic level(s):                1
    Starting point:                          DPHY_RX_INST.u_idesx8.opensync[3] / Q
    Ending point:                            DPHY_RX_INST.u_idesx8.opensync[1] / CE
    The start point is clocked by            _~DPHY_RX_DPHY_RX_TOP_|HS_CLK_inferred_clock [rising] on pin CLK
    The end   point is clocked by            _~DPHY_RX_DPHY_RX_TOP_|HS_CLK_inferred_clock [rising] on pin CLK

Instance / Net                                  Pin      Pin               Arrival     No. of    
Name                                  Type      Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------
DPHY_RX_INST.u_idesx8.opensync[3]     DFFCE     Q        Out     0.367     0.367       -         
opensync[3]                           Net       -        -       1.021     -           2         
DPHY_RX_INST.u_idesx8.LUT4_1          LUT1      I0       In      -         1.388       -         
DPHY_RX_INST.u_idesx8.LUT4_1          LUT1      F        Out     1.032     2.420       -         
opensync_cken                         Net       -        -       1.021     -           4         
DPHY_RX_INST.u_idesx8.opensync[1]     DFFCE     CE       In      -         3.441       -         
=================================================================================================
Total path delay (propagation time + setup) of 3.574 is 1.532(42.9%) logic and 2.042(57.1%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      3.038
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         2.905

    - Propagation time:                      3.441
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.536

    Number of logic level(s):                1
    Starting point:                          DPHY_RX_INST.u_idesx8.opensync[3] / Q
    Ending point:                            DPHY_RX_INST.u_idesx8.opensync[2] / CE
    The start point is clocked by            _~DPHY_RX_DPHY_RX_TOP_|HS_CLK_inferred_clock [rising] on pin CLK
    The end   point is clocked by            _~DPHY_RX_DPHY_RX_TOP_|HS_CLK_inferred_clock [rising] on pin CLK

Instance / Net                                  Pin      Pin               Arrival     No. of    
Name                                  Type      Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------
DPHY_RX_INST.u_idesx8.opensync[3]     DFFCE     Q        Out     0.367     0.367       -         
opensync[3]                           Net       -        -       1.021     -           2         
DPHY_RX_INST.u_idesx8.LUT4_1          LUT1      I0       In      -         1.388       -         
DPHY_RX_INST.u_idesx8.LUT4_1          LUT1      F        Out     1.032     2.420       -         
opensync_cken                         Net       -        -       1.021     -           4         
DPHY_RX_INST.u_idesx8.opensync[2]     DFFCE     CE       In      -         3.441       -         
=================================================================================================
Total path delay (propagation time + setup) of 3.574 is 1.532(42.9%) logic and 2.042(57.1%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      3.038
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         2.905

    - Propagation time:                      3.441
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.536

    Number of logic level(s):                1
    Starting point:                          DPHY_RX_INST.u_idesx8.opensync[3] / Q
    Ending point:                            DPHY_RX_INST.u_idesx8.opensync[3] / CE
    The start point is clocked by            _~DPHY_RX_DPHY_RX_TOP_|HS_CLK_inferred_clock [rising] on pin CLK
    The end   point is clocked by            _~DPHY_RX_DPHY_RX_TOP_|HS_CLK_inferred_clock [rising] on pin CLK

Instance / Net                                  Pin      Pin               Arrival     No. of    
Name                                  Type      Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------
DPHY_RX_INST.u_idesx8.opensync[3]     DFFCE     Q        Out     0.367     0.367       -         
opensync[3]                           Net       -        -       1.021     -           2         
DPHY_RX_INST.u_idesx8.LUT4_1          LUT1      I0       In      -         1.388       -         
DPHY_RX_INST.u_idesx8.LUT4_1          LUT1      F        Out     1.032     2.420       -         
opensync_cken                         Net       -        -       1.021     -           4         
DPHY_RX_INST.u_idesx8.opensync[3]     DFFCE     CE       In      -         3.441       -         
=================================================================================================
Total path delay (propagation time + setup) of 3.574 is 1.532(42.9%) logic and 2.042(57.1%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      3.038
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         3.038

    - Propagation time:                      3.508
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.470

    Number of logic level(s):                1
    Starting point:                          DPHY_RX_INST.u_idesx8.opensync[0] / Q
    Ending point:                            DPHY_RX_INST.u_idesx8.u_DHCEN / CE
    The start point is clocked by            _~DPHY_RX_DPHY_RX_TOP_|HS_CLK_inferred_clock [rising] on pin CLK
    The end   point is clocked by            System [rising]

Instance / Net                                  Pin      Pin               Arrival     No. of    
Name                                  Type      Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------
DPHY_RX_INST.u_idesx8.opensync[0]     DFFPE     Q        Out     0.367     0.367       -         
opensync[0]                           Net       -        -       1.021     -           2         
DPHY_RX_INST.u_idesx8.LUT4_0          LUT2      I1       In      -         1.388       -         
DPHY_RX_INST.u_idesx8.LUT4_0          LUT2      F        Out     1.099     2.487       -         
xstop                                 Net       -        -       1.021     -           1         
DPHY_RX_INST.u_idesx8.u_DHCEN         DHCEN     CE       In      -         3.508       -         
=================================================================================================
Total path delay (propagation time + setup) of 3.508 is 1.466(41.8%) logic and 2.042(58.2%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: _~idesx8_DPHY_RX_TOP_|sclk_inferred_clock
====================================



Starting Points with Worst Slack
********************************

                                                     Starting                                                                         Arrival           
Instance                                             Reference                                     Type      Pin     Net              Time        Slack 
                                                     Clock                                                                                              
--------------------------------------------------------------------------------------------------------------------------------------------------------
DPHY_RX_INST.u_Aligner.genblk2\.wd2.reg2[2]          _~idesx8_DPHY_RX_TOP_|sclk_inferred_clock     DFFC      Q       reg2[2]          0.367       -1.318
DPHY_RX_INST.u_Aligner.genblk4\.wd0.reg2[2]          _~idesx8_DPHY_RX_TOP_|sclk_inferred_clock     DFFC      Q       reg2[2]          0.367       -1.318
DPHY_RX_INST.u_Aligner.genblk3\.wd1.reg2[2]          _~idesx8_DPHY_RX_TOP_|sclk_inferred_clock     DFFC      Q       reg2[2]          0.367       -1.318
DPHY_RX_INST.u_Aligner.genblk1\.wd3.reg4_fast[8]     _~idesx8_DPHY_RX_TOP_|sclk_inferred_clock     DFFC      Q       reg4_fast[8]     0.367       -1.318
DPHY_RX_INST.u_Aligner.genblk4\.wd0.shftamt[3]       _~idesx8_DPHY_RX_TOP_|sclk_inferred_clock     DFFCE     Q       shftamt[3]       0.367       -1.318
DPHY_RX_INST.u_Aligner.genblk2\.wd2.shftamt[3]       _~idesx8_DPHY_RX_TOP_|sclk_inferred_clock     DFFCE     Q       shftamt[3]       0.367       -1.318
DPHY_RX_INST.u_Aligner.genblk1\.wd3.reg4[15]         _~idesx8_DPHY_RX_TOP_|sclk_inferred_clock     DFFC      Q       reg4[15]         0.367       -1.257
DPHY_RX_INST.u_Aligner.genblk3\.wd1.reg1[8]          _~idesx8_DPHY_RX_TOP_|sclk_inferred_clock     DFFC      Q       reg1[8]          0.367       -1.251
DPHY_RX_INST.u_Aligner.genblk2\.wd2.reg1[8]          _~idesx8_DPHY_RX_TOP_|sclk_inferred_clock     DFFC      Q       reg1[8]          0.367       -1.251
DPHY_RX_INST.u_Aligner.genblk4\.wd0.reg1[8]          _~idesx8_DPHY_RX_TOP_|sclk_inferred_clock     DFFC      Q       reg1[8]          0.367       -1.251
========================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                   Starting                                                                      Required           
Instance                                           Reference                                     Type      Pin     Net           Time         Slack 
                                                   Clock                                                                                            
----------------------------------------------------------------------------------------------------------------------------------------------------
DPHY_RX_INST.u_Aligner.genblk2\.wd2.shftamt[1]     _~idesx8_DPHY_RX_TOP_|sclk_inferred_clock     DFFCE     CE      shftamt18     7.335        -1.318
DPHY_RX_INST.u_Aligner.genblk4\.wd0.shftamt[1]     _~idesx8_DPHY_RX_TOP_|sclk_inferred_clock     DFFCE     CE      shftamt18     7.335        -1.318
DPHY_RX_INST.u_Aligner.genblk3\.wd1.shftamt[1]     _~idesx8_DPHY_RX_TOP_|sclk_inferred_clock     DFFCE     CE      shftamt18     7.335        -1.318
DPHY_RX_INST.u_Aligner.genblk2\.wd2.shftamt[2]     _~idesx8_DPHY_RX_TOP_|sclk_inferred_clock     DFFCE     CE      shftamt28     7.335        -1.318
DPHY_RX_INST.u_Aligner.genblk4\.wd0.shftamt[2]     _~idesx8_DPHY_RX_TOP_|sclk_inferred_clock     DFFCE     CE      shftamt28     7.335        -1.318
DPHY_RX_INST.u_Aligner.genblk1\.wd3.shftamt[2]     _~idesx8_DPHY_RX_TOP_|sclk_inferred_clock     DFFCE     CE      shftamt28     7.335        -1.318
DPHY_RX_INST.u_Aligner.genblk3\.wd1.shftamt[2]     _~idesx8_DPHY_RX_TOP_|sclk_inferred_clock     DFFCE     CE      shftamt28     7.335        -1.318
DPHY_RX_INST.u_Aligner.genblk1\.wd3.shftamt[5]     _~idesx8_DPHY_RX_TOP_|sclk_inferred_clock     DFFCE     CE      shftamt58     7.335        -1.318
DPHY_RX_INST.u_Aligner.genblk3\.wd1.shftamt[5]     _~idesx8_DPHY_RX_TOP_|sclk_inferred_clock     DFFCE     CE      shftamt58     7.335        -1.318
DPHY_RX_INST.u_Aligner.genblk2\.wd2.shftamt[5]     _~idesx8_DPHY_RX_TOP_|sclk_inferred_clock     DFFCE     CE      shftamt58     7.335        -1.318
====================================================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      7.468
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         7.335

    - Propagation time:                      8.653
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -1.318

    Number of logic level(s):                4
    Starting point:                          DPHY_RX_INST.u_Aligner.genblk2\.wd2.reg2[2] / Q
    Ending point:                            DPHY_RX_INST.u_Aligner.genblk2\.wd2.shftamt[15] / CE
    The start point is clocked by            _~idesx8_DPHY_RX_TOP_|sclk_inferred_clock [rising] on pin CLK
    The end   point is clocked by            _~idesx8_DPHY_RX_TOP_|sclk_inferred_clock [rising] on pin CLK

Instance / Net                                                     Pin      Pin               Arrival     No. of    
Name                                                     Type      Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------------
DPHY_RX_INST.u_Aligner.genblk2\.wd2.reg2[2]              DFFC      Q        Out     0.367     0.367       -         
reg2[2]                                                  Net       -        -       1.021     -           3         
DPHY_RX_INST.u_Aligner.genblk2\.wd2.m56_0_a2_0_56_17     LUT4      I1       In      -         1.388       -         
DPHY_RX_INST.u_Aligner.genblk2\.wd2.m56_0_a2_0_56_17     LUT4      F        Out     1.099     2.487       -         
m56_0_a2_0_56_17                                         Net       -        -       0.766     -           1         
DPHY_RX_INST.u_Aligner.genblk2\.wd2.m56_0_a2_0_56_25     LUT4      I1       In      -         3.253       -         
DPHY_RX_INST.u_Aligner.genblk2\.wd2.m56_0_a2_0_56_25     LUT4      F        Out     1.099     4.352       -         
m56_0_a2_0_56_25                                         Net       -        -       1.021     -           2         
DPHY_RX_INST.u_Aligner.genblk2\.wd2.m56_0_a2_0_58        LUT3      I1       In      -         5.373       -         
DPHY_RX_INST.u_Aligner.genblk2\.wd2.m56_0_a2_0_58        LUT3      F        Out     1.099     6.472       -         
m56_0_a2_0_58                                            Net       -        -       1.082     -           13        
DPHY_RX_INST.u_Aligner.genblk2\.wd2.m56_0_a2             LUT4      I1       In      -         7.554       -         
DPHY_RX_INST.u_Aligner.genblk2\.wd2.m56_0_a2             LUT4      F        Out     1.099     8.653       -         
shftamt158                                               Net       -        -       0.000     -           1         
DPHY_RX_INST.u_Aligner.genblk2\.wd2.shftamt[15]          DFFCE     CE       In      -         8.653       -         
====================================================================================================================
Total path delay (propagation time + setup) of 8.786 is 4.896(55.7%) logic and 3.890(44.3%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      7.468
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         7.335

    - Propagation time:                      8.653
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -1.318

    Number of logic level(s):                4
    Starting point:                          DPHY_RX_INST.u_Aligner.genblk4\.wd0.reg2[2] / Q
    Ending point:                            DPHY_RX_INST.u_Aligner.genblk4\.wd0.shftamt[15] / CE
    The start point is clocked by            _~idesx8_DPHY_RX_TOP_|sclk_inferred_clock [rising] on pin CLK
    The end   point is clocked by            _~idesx8_DPHY_RX_TOP_|sclk_inferred_clock [rising] on pin CLK

Instance / Net                                                     Pin      Pin               Arrival     No. of    
Name                                                     Type      Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------------
DPHY_RX_INST.u_Aligner.genblk4\.wd0.reg2[2]              DFFC      Q        Out     0.367     0.367       -         
reg2[2]                                                  Net       -        -       1.021     -           3         
DPHY_RX_INST.u_Aligner.genblk4\.wd0.m56_0_a2_0_56_17     LUT4      I1       In      -         1.388       -         
DPHY_RX_INST.u_Aligner.genblk4\.wd0.m56_0_a2_0_56_17     LUT4      F        Out     1.099     2.487       -         
m56_0_a2_0_56_17                                         Net       -        -       0.766     -           1         
DPHY_RX_INST.u_Aligner.genblk4\.wd0.m56_0_a2_0_56_25     LUT4      I1       In      -         3.253       -         
DPHY_RX_INST.u_Aligner.genblk4\.wd0.m56_0_a2_0_56_25     LUT4      F        Out     1.099     4.352       -         
m56_0_a2_0_56_25                                         Net       -        -       1.021     -           2         
DPHY_RX_INST.u_Aligner.genblk4\.wd0.m56_0_a2_0_58        LUT3      I1       In      -         5.373       -         
DPHY_RX_INST.u_Aligner.genblk4\.wd0.m56_0_a2_0_58        LUT3      F        Out     1.099     6.472       -         
m56_0_a2_0_58                                            Net       -        -       1.082     -           13        
DPHY_RX_INST.u_Aligner.genblk4\.wd0.m56_0_a2             LUT4      I1       In      -         7.554       -         
DPHY_RX_INST.u_Aligner.genblk4\.wd0.m56_0_a2             LUT4      F        Out     1.099     8.653       -         
shftamt158                                               Net       -        -       0.000     -           1         
DPHY_RX_INST.u_Aligner.genblk4\.wd0.shftamt[15]          DFFCE     CE       In      -         8.653       -         
====================================================================================================================
Total path delay (propagation time + setup) of 8.786 is 4.896(55.7%) logic and 3.890(44.3%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      7.468
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         7.335

    - Propagation time:                      8.653
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -1.318

    Number of logic level(s):                4
    Starting point:                          DPHY_RX_INST.u_Aligner.genblk3\.wd1.reg2[2] / Q
    Ending point:                            DPHY_RX_INST.u_Aligner.genblk3\.wd1.shftamt[15] / CE
    The start point is clocked by            _~idesx8_DPHY_RX_TOP_|sclk_inferred_clock [rising] on pin CLK
    The end   point is clocked by            _~idesx8_DPHY_RX_TOP_|sclk_inferred_clock [rising] on pin CLK

Instance / Net                                                     Pin      Pin               Arrival     No. of    
Name                                                     Type      Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------------
DPHY_RX_INST.u_Aligner.genblk3\.wd1.reg2[2]              DFFC      Q        Out     0.367     0.367       -         
reg2[2]                                                  Net       -        -       1.021     -           3         
DPHY_RX_INST.u_Aligner.genblk3\.wd1.m56_0_a2_0_56_17     LUT4      I1       In      -         1.388       -         
DPHY_RX_INST.u_Aligner.genblk3\.wd1.m56_0_a2_0_56_17     LUT4      F        Out     1.099     2.487       -         
m56_0_a2_0_56_17                                         Net       -        -       0.766     -           1         
DPHY_RX_INST.u_Aligner.genblk3\.wd1.m56_0_a2_0_56_25     LUT4      I1       In      -         3.253       -         
DPHY_RX_INST.u_Aligner.genblk3\.wd1.m56_0_a2_0_56_25     LUT4      F        Out     1.099     4.352       -         
m56_0_a2_0_56_25                                         Net       -        -       1.021     -           2         
DPHY_RX_INST.u_Aligner.genblk3\.wd1.m56_0_a2_0_58        LUT3      I1       In      -         5.373       -         
DPHY_RX_INST.u_Aligner.genblk3\.wd1.m56_0_a2_0_58        LUT3      F        Out     1.099     6.472       -         
m56_0_a2_0_58                                            Net       -        -       1.082     -           13        
DPHY_RX_INST.u_Aligner.genblk3\.wd1.m56_0_a2             LUT4      I1       In      -         7.554       -         
DPHY_RX_INST.u_Aligner.genblk3\.wd1.m56_0_a2             LUT4      F        Out     1.099     8.653       -         
shftamt158                                               Net       -        -       0.000     -           1         
DPHY_RX_INST.u_Aligner.genblk3\.wd1.shftamt[15]          DFFCE     CE       In      -         8.653       -         
====================================================================================================================
Total path delay (propagation time + setup) of 8.786 is 4.896(55.7%) logic and 3.890(44.3%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      7.468
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         7.335

    - Propagation time:                      8.653
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -1.318

    Number of logic level(s):                4
    Starting point:                          DPHY_RX_INST.u_Aligner.genblk1\.wd3.reg4_fast[8] / Q
    Ending point:                            DPHY_RX_INST.u_Aligner.genblk1\.wd3.shftamt[15] / CE
    The start point is clocked by            _~idesx8_DPHY_RX_TOP_|sclk_inferred_clock [rising] on pin CLK
    The end   point is clocked by            _~idesx8_DPHY_RX_TOP_|sclk_inferred_clock [rising] on pin CLK

Instance / Net                                                     Pin      Pin               Arrival     No. of    
Name                                                     Type      Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------------
DPHY_RX_INST.u_Aligner.genblk1\.wd3.reg4_fast[8]         DFFC      Q        Out     0.367     0.367       -         
reg4_fast[8]                                             Net       -        -       1.021     -           1         
DPHY_RX_INST.u_Aligner.genblk1\.wd3.m56_0_a2_0_56_15     LUT4      I1       In      -         1.388       -         
DPHY_RX_INST.u_Aligner.genblk1\.wd3.m56_0_a2_0_56_15     LUT4      F        Out     1.099     2.487       -         
m56_0_a2_0_56_15                                         Net       -        -       0.766     -           1         
DPHY_RX_INST.u_Aligner.genblk1\.wd3.m56_0_a2_0_56_21     LUT2      I1       In      -         3.253       -         
DPHY_RX_INST.u_Aligner.genblk1\.wd3.m56_0_a2_0_56_21     LUT2      F        Out     1.099     4.352       -         
m56_0_a2_0_56_21                                         Net       -        -       1.021     -           2         
DPHY_RX_INST.u_Aligner.genblk1\.wd3.m56_0_a2_0_58        LUT4      I1       In      -         5.373       -         
DPHY_RX_INST.u_Aligner.genblk1\.wd3.m56_0_a2_0_58        LUT4      F        Out     1.099     6.472       -         
m56_0_a2_0_58                                            Net       -        -       1.082     -           11        
DPHY_RX_INST.u_Aligner.genblk1\.wd3.m56_0_a2             LUT4      I1       In      -         7.554       -         
DPHY_RX_INST.u_Aligner.genblk1\.wd3.m56_0_a2             LUT4      F        Out     1.099     8.653       -         
shftamt158                                               Net       -        -       0.000     -           1         
DPHY_RX_INST.u_Aligner.genblk1\.wd3.shftamt[15]          DFFCE     CE       In      -         8.653       -         
====================================================================================================================
Total path delay (propagation time + setup) of 8.786 is 4.896(55.7%) logic and 3.890(44.3%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      7.468
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         7.335

    - Propagation time:                      8.653
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -1.318

    Number of logic level(s):                4
    Starting point:                          DPHY_RX_INST.u_Aligner.genblk4\.wd0.shftamt[3] / Q
    Ending point:                            DPHY_RX_INST.u_Aligner.genblk4\.wd0.shftamt[11] / CE
    The start point is clocked by            _~idesx8_DPHY_RX_TOP_|sclk_inferred_clock [rising] on pin CLK
    The end   point is clocked by            _~idesx8_DPHY_RX_TOP_|sclk_inferred_clock [rising] on pin CLK

Instance / Net                                                  Pin      Pin               Arrival     No. of    
Name                                                  Type      Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------
DPHY_RX_INST.u_Aligner.genblk4\.wd0.shftamt[3]        DFFCE     Q        Out     0.367     0.367       -         
shftamt[3]                                            Net       -        -       1.021     -           2         
DPHY_RX_INST.u_Aligner.genblk4\.wd0.shiftflag_3_0     LUT4      I1       In      -         1.388       -         
DPHY_RX_INST.u_Aligner.genblk4\.wd0.shiftflag_3_0     LUT4      F        Out     1.099     2.487       -         
shiftflag_3_0                                         Net       -        -       0.766     -           1         
DPHY_RX_INST.u_Aligner.genblk4\.wd0.shiftflag         LUT4      I1       In      -         3.253       -         
DPHY_RX_INST.u_Aligner.genblk4\.wd0.shiftflag         LUT4      F        Out     1.099     4.352       -         
shiftflag                                             Net       -        -       1.082     -           18        
DPHY_RX_INST.u_Aligner.genblk4\.wd0.m96_m3_e_3        LUT2      I1       In      -         5.434       -         
DPHY_RX_INST.u_Aligner.genblk4\.wd0.m96_m3_e_3        LUT2      F        Out     1.099     6.533       -         
m96_m3_e_3                                            Net       -        -       1.021     -           3         
DPHY_RX_INST.u_Aligner.genblk4\.wd0.m96_0_a2          LUT3      I1       In      -         7.554       -         
DPHY_RX_INST.u_Aligner.genblk4\.wd0.m96_0_a2          LUT3      F        Out     1.099     8.653       -         
shftamt118                                            Net       -        -       0.000     -           1         
DPHY_RX_INST.u_Aligner.genblk4\.wd0.shftamt[11]       DFFCE     CE       In      -         8.653       -         
=================================================================================================================
Total path delay (propagation time + setup) of 8.786 is 4.896(55.7%) logic and 3.890(44.3%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: System
====================================



Starting Points with Worst Slack
********************************

                                         Starting                                        Arrival           
Instance                                 Reference     Type       Pin        Net         Time        Slack 
                                         Clock                                                             
-----------------------------------------------------------------------------------------------------------
DPHY_RX_INST.u_idesx8.Inst3_CLKDIV       System        CLKDIV     CLKOUT     sclk_i      0.000       -0.612
DPHY_RX_INST.u_idesx8.u_DHCEN            System        DHCEN      CLKOUT     eclko       0.000       2.450 
DPHY_RX_INST.u_idesx8.Inst4_IDES16_0     System        IDES16     Q0         data[0]     0.000       6.314 
DPHY_RX_INST.u_idesx8.Inst4_IDES16_0     System        IDES16     Q0         data[0]     0.000       6.314 
DPHY_RX_INST.u_idesx8.Inst4_IDES16_0     System        IDES16     Q1         data[1]     0.000       6.314 
DPHY_RX_INST.u_idesx8.Inst4_IDES16_0     System        IDES16     Q1         data[1]     0.000       6.314 
DPHY_RX_INST.u_idesx8.Inst4_IDES16_0     System        IDES16     Q2         data[2]     0.000       6.314 
DPHY_RX_INST.u_idesx8.Inst4_IDES16_0     System        IDES16     Q2         data[2]     0.000       6.314 
DPHY_RX_INST.u_idesx8.Inst4_IDES16_0     System        IDES16     Q3         data[3]     0.000       6.314 
DPHY_RX_INST.u_idesx8.Inst4_IDES16_0     System        IDES16     Q3         data[3]     0.000       6.314 
===========================================================================================================


Ending Points with Worst Slack
******************************

                                                Starting                                         Required           
Instance                                        Reference     Type       Pin        Net          Time         Slack 
                                                Clock                                                               
--------------------------------------------------------------------------------------------------------------------
DPHY_RX_INST.u_idesx8.Inst4_IDES16_0            System        IDES16     PCLK       sclk_i       3.471        -0.612
DPHY_RX_INST.u_idesx8.Inst4_IDES16_0            System        IDES16     PCLK       sclk_i       3.471        -0.612
DPHY_RX_INST.u_idesx8.Inst4_IDES16_1            System        IDES16     PCLK       sclk_i       3.471        -0.612
DPHY_RX_INST.u_idesx8.Inst4_IDES16_1            System        IDES16     PCLK       sclk_i       3.471        -0.612
DPHY_RX_INST.u_idesx8.Inst4_IDES16_2            System        IDES16     PCLK       sclk_i       3.471        -0.612
DPHY_RX_INST.u_idesx8.Inst4_IDES16_2            System        IDES16     PCLK       sclk_i       3.471        -0.612
DPHY_RX_INST.u_idesx8.Inst4_IDES16_3            System        IDES16     PCLK       sclk_i       3.471        -0.612
DPHY_RX_INST.u_idesx8.Inst4_IDES16_3            System        IDES16     PCLK       sclk_i       3.471        -0.612
DPHY_RX_INST.u_idesx8.Inst3_CLKDIV              System        CLKDIV     HCLKIN     eclko        3.471        2.450 
DPHY_RX_INST.u_Aligner.genblk2\.wd2.reg0[0]     System        DFFC       D          data[47]     7.335        6.314 
====================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      3.471
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         3.471

    - Propagation time:                      4.083
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 -0.612

    Number of logic level(s):                0
    Starting point:                          DPHY_RX_INST.u_idesx8.Inst3_CLKDIV / CLKOUT
    Ending point:                            DPHY_RX_INST.u_idesx8.Inst4_IDES16_0 / PCLK
    The start point is clocked by            System [rising]
    The end   point is clocked by            System [rising]

Instance / Net                                      Pin        Pin               Arrival     No. of    
Name                                     Type       Name       Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------
DPHY_RX_INST.u_idesx8.Inst3_CLKDIV       CLKDIV     CLKOUT     Out     0.000     0.000       -         
sclk_i                                   Net        -          -       4.083     -           959       
DPHY_RX_INST.u_idesx8.Inst4_IDES16_0     IDES16     PCLK       In      -         4.083       -         
=======================================================================================================
Total path delay (propagation time + setup) of 4.083 is 0.000(0.0%) logic and 4.083(100.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      3.471
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         3.471

    - Propagation time:                      4.083
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 -0.612

    Number of logic level(s):                0
    Starting point:                          DPHY_RX_INST.u_idesx8.Inst3_CLKDIV / CLKOUT
    Ending point:                            DPHY_RX_INST.u_idesx8.Inst4_IDES16_3 / PCLK
    The start point is clocked by            System [rising]
    The end   point is clocked by            System [rising]

Instance / Net                                      Pin        Pin               Arrival     No. of    
Name                                     Type       Name       Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------
DPHY_RX_INST.u_idesx8.Inst3_CLKDIV       CLKDIV     CLKOUT     Out     0.000     0.000       -         
sclk_i                                   Net        -          -       4.083     -           959       
DPHY_RX_INST.u_idesx8.Inst4_IDES16_3     IDES16     PCLK       In      -         4.083       -         
=======================================================================================================
Total path delay (propagation time + setup) of 4.083 is 0.000(0.0%) logic and 4.083(100.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      3.471
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         3.471

    - Propagation time:                      4.083
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 -0.612

    Number of logic level(s):                0
    Starting point:                          DPHY_RX_INST.u_idesx8.Inst3_CLKDIV / CLKOUT
    Ending point:                            DPHY_RX_INST.u_idesx8.Inst4_IDES16_2 / PCLK
    The start point is clocked by            System [rising]
    The end   point is clocked by            System [rising]

Instance / Net                                      Pin        Pin               Arrival     No. of    
Name                                     Type       Name       Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------
DPHY_RX_INST.u_idesx8.Inst3_CLKDIV       CLKDIV     CLKOUT     Out     0.000     0.000       -         
sclk_i                                   Net        -          -       4.083     -           959       
DPHY_RX_INST.u_idesx8.Inst4_IDES16_2     IDES16     PCLK       In      -         4.083       -         
=======================================================================================================
Total path delay (propagation time + setup) of 4.083 is 0.000(0.0%) logic and 4.083(100.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      3.471
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         3.471

    - Propagation time:                      4.083
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 -0.612

    Number of logic level(s):                0
    Starting point:                          DPHY_RX_INST.u_idesx8.Inst3_CLKDIV / CLKOUT
    Ending point:                            DPHY_RX_INST.u_idesx8.Inst4_IDES16_1 / PCLK
    The start point is clocked by            System [rising]
    The end   point is clocked by            System [rising]

Instance / Net                                      Pin        Pin               Arrival     No. of    
Name                                     Type       Name       Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------
DPHY_RX_INST.u_idesx8.Inst3_CLKDIV       CLKDIV     CLKOUT     Out     0.000     0.000       -         
sclk_i                                   Net        -          -       4.083     -           959       
DPHY_RX_INST.u_idesx8.Inst4_IDES16_1     IDES16     PCLK       In      -         4.083       -         
=======================================================================================================
Total path delay (propagation time + setup) of 4.083 is 0.000(0.0%) logic and 4.083(100.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      3.471
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         3.471

    - Propagation time:                      1.021
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 2.450

    Number of logic level(s):                0
    Starting point:                          DPHY_RX_INST.u_idesx8.u_DHCEN / CLKOUT
    Ending point:                            DPHY_RX_INST.u_idesx8.Inst3_CLKDIV / HCLKIN
    The start point is clocked by            System [rising]
    The end   point is clocked by            System [rising]

Instance / Net                                    Pin        Pin               Arrival     No. of    
Name                                   Type       Name       Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------
DPHY_RX_INST.u_idesx8.u_DHCEN          DHCEN      CLKOUT     Out     0.000     0.000       -         
eclko                                  Net        -          -       1.021     -           5         
DPHY_RX_INST.u_idesx8.Inst3_CLKDIV     CLKDIV     HCLKIN     In      -         1.021       -         
=====================================================================================================
Total path delay (propagation time + setup) of 1.021 is 0.000(0.0%) logic and 1.021(100.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

Timing exceptions that could not be applied

Finished final timing analysis (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:09s; Memory used current: 238MB peak: 242MB)


Finished timing report (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:09s; Memory used current: 238MB peak: 242MB)

---------------------------------------
Resource Usage Report for DPHY_RX_TOP 

Mapping to part: gw1n_9pbga256-6
Cell usage:
CLKDIV          1 use
DFFC            738 uses
DFFCE           139 uses
DFFE            64 uses
DFFPE           1 use
DHCEN           1 use
GSR             1 use
IDES16          4 uses
INV             5 uses
IODELAY         4 uses
MUX2_LUT5       256 uses
MUX2_LUT6       128 uses
MUX2_LUT7       64 uses
RAM16SDP4       16 uses
LUT1            1 use
LUT2            70 uses
LUT3            595 uses
LUT4            344 uses

I/O ports: 79
I/O primitives: 5
ELVDS_IBUF     5 uses

I/O Register bits:                  0
Register bits not including I/Os:   942 of 6480 (14%)
Total load per clock:
   _~idesx8_DPHY_RX_TOP_|sclk_inferred_clock: 955

@S |Mapping Summary:
Total  LUTs: 1010 (11%)

Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:09s; Memory used current: 82MB peak: 242MB)

Process took 0h:00m:09s realtime, 0h:00m:09s cputime
# Thu Mar 26 13:44:14 2020

###########################################################]
