# Mon Mar 30 11:17:06 2020


Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03G-1-Beta1
Install: E:\Gowin\Gowin_V1.9.3Beta_37257_win\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-001

Implementation : rev_1
Synopsys Generic Technology Pre-mapping, Version mapgw2019q1p1, Build 007R, Built Dec  5 2019 10:27:23


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)

@A: MF827 |No constraint file specified.
@L: E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\impl\synthesize\rev_1\MIPI_RefDesign_scck.rpt 
Printing clock  summary report in "E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\impl\synthesize\rev_1\MIPI_RefDesign_scck.rpt" file 
@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 130MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 130MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 131MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB)


Starting clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 225MB peak: 225MB)


Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 225MB peak: 225MB)


Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 225MB peak: 225MB)


Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 225MB peak: 225MB)


Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 225MB peak: 226MB)



Clock Summary
******************

          Start                                                  Requested     Requested     Clock        Clock                     Clock
Level     Clock                                                  Frequency     Period        Type         Group                     Load 
-----------------------------------------------------------------------------------------------------------------------------------------
0 -       System                                                 100.0 MHz     10.000        system       system_clkgroup           9    
                                                                                                                                         
0 -       _~idesx8_DPHY_RX_TOP__|clk_byte_out_inferred_clock     172.5 MHz     5.796         inferred     Autoconstr_clkgroup_1     1018 
                                                                                                                                         
0 -       _~oserx8_DPHY_TX_TOP__|sclk_0_inferred_clock           229.0 MHz     4.367         inferred     Autoconstr_clkgroup_0     49   
                                                                                                                                         
0 -       _~DPHY_RX_DPHY_RX_TOP__|HS_CLK_inferred_clock          680.0 MHz     1.471         inferred     Autoconstr_clkgroup_2     4    
=========================================================================================================================================



Clock Load Summary
***********************

                                                       Clock     Source                                                              Clock Pin                                                     Non-clock Pin     Non-clock Pin             
Clock                                                  Load      Pin                                                                 Seq Example                                                   Seq Example       Comb Example              
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
System                                                 9         -                                                                   u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.Inst4_IDES16_0.FCLK       -                 -                         
                                                                                                                                                                                                                                               
_~idesx8_DPHY_RX_TOP__|clk_byte_out_inferred_clock     1018      u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.Inst3_CLKDIV.CLKOUT(CLKDIV)     data_out_reg[63:0].C                                          -                 clk_byte_out.I[0](keepbuf)
                                                                                                                                                                                                                                               
_~oserx8_DPHY_TX_TOP__|sclk_0_inferred_clock           49        u_DPHY_TX_TOP.DPHY_TX_INST.u_oserx8.U3_CLKDIV.CLKOUT(CLKDIV)        hactive_flag.C                                                -                 -                         
                                                                                                                                                                                                                                               
_~DPHY_RX_DPHY_RX_TOP__|HS_CLK_inferred_clock          4         u_DPHY_RX_TOP.DPHY_RX_INST.U0_IB.O(ELVDS_IBUF)                      u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.\\opensync_Z\[3\].CLK     -                 -                         
===============================================================================================================================================================================================================================================

@W: MT529 :"e:\gowin_work\ip_design\mipi\mipi_release_case\mipi_dphy_reference_design\mipi_refdesign\src\rom549x17.v":33:2:33:7|Found inferred clock _~oserx8_DPHY_TX_TOP__|sclk_0_inferred_clock which controls 49 sequential elements including u_ROM549x17.addr[9:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 

ICG Latch Removal Summary:
Number of ICG latches removed: 0
Number of ICG latches not removed:	0


@S |Clock Optimization Summary



#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[

0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
7 gated/generated clock tree(s) driving 1080 clock pin(s) of sequential element(s)
0 instances converted, 1080 sequential instances remain driven by gated/generated clocks

==================================================================== Gated/Generated Clocks ====================================================================
Clock Tree ID     Driving Element                Drive Element Type     Unconverted Fanout     Sample Instance        Explanation                               
----------------------------------------------------------------------------------------------------------------------------------------------------------------
@KP:ckid0_1       ENCRYPTED                      CLKDIV                 954                    ENCRYPTED              Black box on clock path                   
@KP:ckid0_2       ENCRYPTED                      DHCEN                  4                      ENCRYPTED              Black box on clock path                   
@KP:ckid0_3       ENCRYPTED                      ELVDS_IBUF             4                      ENCRYPTED              Derived clock on input (not legal for GCC)
@KP:ckid0_4       ENCRYPTED                      PLL                    1                      ENCRYPTED              Black box on clock path                   
@KP:ckid0_6       ENCRYPTED                      CLKDIV                 49                     ENCRYPTED              Black box on clock path                   
@KP:ckid0_7       ENCRYPTED                      PLL                    4                      ENCRYPTED              Black box on clock path                   
@KP:ckid0_8       u_DPHY_RX_TOP.clk_byte_out     DPHY_RX_TOP            64                     data_out_reg[63:0]     Black box on clock path                   
================================================================================================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######

@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
Finished Pre Mapping Phase.
@N: BN225 |Writing default property annotation file E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\impl\synthesize\rev_1\MIPI_RefDesign.sap.

Starting constraint checker (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 227MB peak: 227MB)


Finished constraint checker preprocessing (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 227MB peak: 227MB)


Finished constraint checker (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 227MB peak: 227MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 148MB peak: 228MB)

Process took 0h:00m:03s realtime, 0h:00m:03s cputime
# Mon Mar 30 11:17:10 2020

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