
Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03G-1-Beta1
Install: E:\Gowin\Gowin_V1.9.3Beta_37257_win\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-001

Implementation : rev_1
Synopsys HDL compiler and linker, Version comp2019q1p1, Build 391R, Built Dec  3 2019 09:16:34

Modified Files: 1
FID:  path (prevtimestamp, timestamp)
3        E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\src\ROM549X17.v (2020-03-26 10:02:08, 2020-03-30 11:01:11)

*******************************************************************
Modules that may have changed as a result of file changes: 1
MID:  lib.cell.view
4        work.ROM549x17.verilog may have changed because the following files changed:
                        E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\src\ROM549X17.v (2020-03-26 10:02:08, 2020-03-30 11:01:11) <-- (module definition)

*******************************************************************
Unmodified files: 9
FID:  path (timestamp)
0        E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\src\DPHY_RX_TOP\DPHY_RX_TOP.v (2020-03-26 13:44:17)
1        E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\src\DPHY_TOP.v (2020-03-26 13:41:53)
2        E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\src\DPHY_TX_TOP\DPHY_TX_TOP.v (2020-03-26 13:45:14)
4        E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\src\gw_pll.v (2020-03-26 10:02:51)
5        E:\Gowin\Gowin_V1.9.3Beta_37257_win\SynplifyPro\lib\generic\gw1n.v (2019-12-06 03:09:16)
6        E:\Gowin\Gowin_V1.9.3Beta_37257_win\SynplifyPro\lib\vlog\hypermods.v (2019-12-04 01:13:52)
7        E:\Gowin\Gowin_V1.9.3Beta_37257_win\SynplifyPro\lib\vlog\scemi_objects.v (2019-12-04 01:13:52)
8        E:\Gowin\Gowin_V1.9.3Beta_37257_win\SynplifyPro\lib\vlog\scemi_pipes.svh (2019-12-04 01:13:52)
9        E:\Gowin\Gowin_V1.9.3Beta_37257_win\SynplifyPro\lib\vlog\umr_capim.v (2019-12-04 01:13:52)

*******************************************************************
Unchanged modules: 19
MID:  lib.cell.view
0        work.DPHY_RX_TOP.verilog
1        work.DPHY_TOP.verilog
2        work.DPHY_TX_TOP.verilog
3        work.GW_PLL.verilog
5        work.\~Aligner.DPHY_RX_TOP__4s_1s_1s.verilog
6        work.\~DPHY_RX.DPHY_RX_TOP_.verilog
7        work.\~DPHY_TX.DPHY_TX_TOP_.verilog
8        work.\~idesx8.DPHY_RX_TOP_.verilog
9        work.\~lane_align_FIFO.DPHY_RX_TOP_.verilog
10       work.\~lane_align_FIFO.DPHY_RX_TOP__3.verilog
11       work.\~lane_align_FIFO.DPHY_RX_TOP__4.verilog
12       work.\~lane_align_FIFO.DPHY_RX_TOP__5.verilog
13       work.\~lane_aligner.DPHY_RX_TOP__4s.verilog
14       work.\~oserx8.DPHY_TX_TOP_.verilog
15       work.\~pllx8.DPHY_TX_TOP_.verilog
16       work.\~word_aligner.DPHY_RX_TOP__6.verilog
17       work.\~word_aligner.DPHY_RX_TOP__6_0.verilog
18       work.\~word_aligner.DPHY_RX_TOP__6_1.verilog
19       work.\~word_aligner.DPHY_RX_TOP__6_2.verilog
