
Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03G-1-Beta1
Install: E:\Gowin\Gowin_V1.9.3Beta_37257_win\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-001

Implementation : rev_1

# Written on Mon Mar 30 11:17:07 2020

##### FILES SYNTAX CHECKED ##############################################
Constraint File(s):      (none)

#Run constraint checker to find more issues with constraints.
#########################################################################



No issues found in constraint syntax.



Clock Summary
*************

          Start                                                  Requested     Requested     Clock        Clock                     Clock
Level     Clock                                                  Frequency     Period        Type         Group                     Load 
-----------------------------------------------------------------------------------------------------------------------------------------
0 -       System                                                 100.0 MHz     10.000        system       system_clkgroup           9    
                                                                                                                                         
0 -       _~idesx8_DPHY_RX_TOP__|clk_byte_out_inferred_clock     172.5 MHz     5.796         inferred     Autoconstr_clkgroup_1     1018 
                                                                                                                                         
0 -       _~oserx8_DPHY_TX_TOP__|sclk_0_inferred_clock           229.0 MHz     4.367         inferred     Autoconstr_clkgroup_0     49   
                                                                                                                                         
0 -       _~DPHY_RX_DPHY_RX_TOP__|HS_CLK_inferred_clock          680.0 MHz     1.471         inferred     Autoconstr_clkgroup_2     4    
=========================================================================================================================================


Clock Load Summary
******************

                                                       Clock     Source                                                              Clock Pin                                                     Non-clock Pin     Non-clock Pin             
Clock                                                  Load      Pin                                                                 Seq Example                                                   Seq Example       Comb Example              
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
System                                                 9         -                                                                   u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.Inst4_IDES16_0.FCLK       -                 -                         
                                                                                                                                                                                                                                               
_~idesx8_DPHY_RX_TOP__|clk_byte_out_inferred_clock     1018      u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.Inst3_CLKDIV.CLKOUT(CLKDIV)     data_out_reg[63:0].C                                          -                 clk_byte_out.I[0](keepbuf)
                                                                                                                                                                                                                                               
_~oserx8_DPHY_TX_TOP__|sclk_0_inferred_clock           49        u_DPHY_TX_TOP.DPHY_TX_INST.u_oserx8.U3_CLKDIV.CLKOUT(CLKDIV)        hactive_flag.C                                                -                 -                         
                                                                                                                                                                                                                                               
_~DPHY_RX_DPHY_RX_TOP__|HS_CLK_inferred_clock          4         u_DPHY_RX_TOP.DPHY_RX_INST.U0_IB.O(ELVDS_IBUF)                      u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.\\opensync_Z\[3\].CLK     -                 -                         
===============================================================================================================================================================================================================================================
