# Thu Mar 26 13:44:02 2020


Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03G-1-Beta1
Install: E:\Gowin\Gowin_V1.9.3Beta_37257_win\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-001

Implementation : rev_1
Synopsys Generic Technology Pre-mapping, Version mapgw2019q1p1, Build 007R, Built Dec  5 2019 10:27:23


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)

@A: MF827 |No constraint file specified.
@L: E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\src\DPHY_RX_TOP\temp\MIPI_Rx\rev_1\DPHY_RX_TOP_scck.rpt 
Printing clock  summary report in "E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\src\DPHY_RX_TOP\temp\MIPI_Rx\rev_1\DPHY_RX_TOP_scck.rpt" file 
@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 128MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB)


Starting clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 222MB peak: 222MB)


Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 222MB peak: 222MB)


Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 222MB peak: 223MB)


Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 223MB peak: 223MB)


Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 223MB peak: 223MB)



Clock Summary
******************

          Start                                            Requested     Requested     Clock        Clock                     Clock
Level     Clock                                            Frequency     Period        Type         Group                     Load 
-----------------------------------------------------------------------------------------------------------------------------------
0 -       System                                           100.0 MHz     10.000        system       system_clkgroup           4    
                                                                                                                                   
0 -       _~idesx8_DPHY_RX_TOP_|sclk_inferred_clock        206.3 MHz     4.848         inferred     Autoconstr_clkgroup_0     877  
                                                                                                                                   
0 -       _~DPHY_RX_DPHY_RX_TOP_|HS_CLK_inferred_clock     563.4 MHz     1.775         inferred     Autoconstr_clkgroup_1     4    
===================================================================================================================================



Clock Load Summary
***********************

                                                 Clock     Source                                                Clock Pin                                                        Non-clock Pin     Non-clock Pin
Clock                                            Load      Pin                                                   Seq Example                                                      Seq Example       Comb Example 
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
System                                           4         -                                                     DPHY_RX_INST.u_idesx8.Inst4_IDES16_3.FCLK                        -                 -            
                                                                                                                                                                                                                 
_~idesx8_DPHY_RX_TOP_|sclk_inferred_clock        877       DPHY_RX_INST.u_idesx8.Inst3_CLKDIV.CLKOUT(CLKDIV)     DPHY_RX_INST.u_Aligner.genblk6\.ln0.genblk1\.q_in0_0[15:0].C     -                 -            
                                                                                                                                                                                                                 
_~DPHY_RX_DPHY_RX_TOP_|HS_CLK_inferred_clock     4         DPHY_RX_INST.U0_IB.O(ELVDS_IBUF)                      DPHY_RX_INST.u_idesx8.opensync[3:0].C                            -                 -            
=================================================================================================================================================================================================================


ICG Latch Removal Summary:
Number of ICG latches removed: 0
Number of ICG latches not removed:	0


@S |Clock Optimization Summary



#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[

0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
3 gated/generated clock tree(s) driving 825 clock pin(s) of sequential element(s)
0 instances converted, 825 sequential instances remain driven by gated/generated clocks

============================================================= Gated/Generated Clocks =============================================================
Clock Tree ID     Driving Element     Drive Element Type     Unconverted Fanout     Sample Instance     Explanation                               
--------------------------------------------------------------------------------------------------------------------------------------------------
@KP:ckid0_1       ENCRYPTED           CLKDIV                 817                    ENCRYPTED           Black box on clock path                   
@KP:ckid0_2       ENCRYPTED           ELVDS_IBUF             4                      ENCRYPTED           Derived clock on input (not legal for GCC)
@KP:ckid0_3       ENCRYPTED           DHCEN                  4                      ENCRYPTED           Black box on clock path                   
==================================================================================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######

@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
Finished Pre Mapping Phase.
@N: BN225 |Writing default property annotation file E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\src\DPHY_RX_TOP\temp\MIPI_Rx\rev_1\DPHY_RX_TOP.sap.

Starting constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 223MB peak: 223MB)


Finished constraint checker preprocessing (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 223MB peak: 223MB)


Finished constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 224MB peak: 224MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 145MB peak: 226MB)

Process took 0h:00m:02s realtime, 0h:00m:02s cputime
# Thu Mar 26 13:44:04 2020

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