Selecting top level module DPHY_RX_TOP
Running optimization stage 1 on ELVDS_IBUF .......
Running optimization stage 1 on LUT4 .......
Running optimization stage 1 on IDES16 .......
Running optimization stage 1 on DHCEN .......
Running optimization stage 1 on CLKDIV .......
Running optimization stage 1 on IODELAY .......
Running optimization stage 1 on \~idesx8.DPHY_RX_TOP  .......
Running optimization stage 1 on \~word_aligner.DPHY_RX_TOP  .......
Running optimization stage 1 on \~lane_align_FIFO.DPHY_RX_TOP  .......
Running optimization stage 1 on \~lane_aligner.DPHY_RX_TOP _4s .......
Running optimization stage 1 on \~Aligner.DPHY_RX_TOP _4s_1s_1s .......
Running optimization stage 1 on \~DPHY_RX.DPHY_RX_TOP  .......
@N: CG364 :"E:\Gowin\Gowin_V1.9.3Beta_37257_win\IDE\ipcore\MIPI_RX\data\DPHY_RX_TOP.v":193:22:193:22|Synthesizing module DPHY_RX_TOP in library work.
Running optimization stage 1 on DPHY_RX_TOP .......
Running optimization stage 2 on DPHY_RX_TOP .......
Running optimization stage 2 on \~DPHY_RX.DPHY_RX_TOP  .......
Running optimization stage 2 on \~lane_align_FIFO.DPHY_RX_TOP  .......
Running optimization stage 2 on \~lane_aligner.DPHY_RX_TOP _4s .......
Running optimization stage 2 on \~word_aligner.DPHY_RX_TOP  .......
Running optimization stage 2 on \~Aligner.DPHY_RX_TOP _4s_1s_1s .......
Running optimization stage 2 on \~idesx8.DPHY_RX_TOP  .......
Running optimization stage 2 on IODELAY .......
Running optimization stage 2 on CLKDIV .......
Running optimization stage 2 on DHCEN .......
Running optimization stage 2 on IDES16 .......
Running optimization stage 2 on LUT4 .......
Running optimization stage 2 on ELVDS_IBUF .......

For a summary of runtime and memory usage per design unit, please see file:
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@L: E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\src\DPHY_RX_TOP\temp\MIPI_Rx\rev_1\synwork\layer0.rt.csv

