@W: MT246 :"e:\gowin_work\ip_design\mipi\mipi_release_case\mipi_dphy_reference_design\mipi_refdesign\src\dphy_rx_top\dphy_rx_top.v":150:8:150:14|Blackbox DHCEN is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W: MT246 :"e:\gowin_work\ip_design\mipi\mipi_release_case\mipi_dphy_reference_design\mipi_refdesign\src\dphy_rx_top\dphy_rx_top.v":142:9:142:20|Blackbox CLKDIV is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W: MT246 :"e:\gowin_work\ip_design\mipi\mipi_release_case\mipi_dphy_reference_design\mipi_refdesign\src\dphy_tx_top\dphy_tx_top.v":42:6:42:16|Blackbox PLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W: MT420 |Found inferred clock _~oserx8_DPHY_TX_TOP__|sclk_0_inferred_clock with period 4.61ns. Please declare a user-defined clock on net u_DPHY_TX_TOP.DPHY_TX_INST.u_oserx8.sclk.
@W: MT420 |Found inferred clock _~idesx8_DPHY_RX_TOP__|clk_byte_out_inferred_clock with period 8.96ns. Please declare a user-defined clock on net u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.clk_byte_out.
@W: MT420 |Found inferred clock _~DPHY_RX_DPHY_RX_TOP__|HS_CLK_inferred_clock with period 3.65ns. Please declare a user-defined clock on net u_DPHY_RX_TOP.DPHY_RX_INST.HS_CLK.
