`

    #Build: Synplify Pro (R) P-2019.03G-1-Beta1, Build 387R, Dec  3 2019
    #install: E:\Gowin\Gowin_V1.9.3Beta_37257_win\SynplifyPro
    #OS: Windows 7 6.1
    #Hostname: GW-SW-001

    # Thu Mar 26 13:45:03 2020

    #Implementation: rev_1

    Copyright (C) 1994-2019 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: P-2019.03G-1-Beta1
    Install: E:\Gowin\Gowin_V1.9.3Beta_37257_win\SynplifyPro
    OS: Windows 6.1

    Hostname: GW-SW-001

    Implementation : rev_1
    Synopsys HDL Compiler, Version comp2019q1p1, Build 391R, Built Dec  3 2019 09:16:34

    @N: :  | Running in 64-bit mode
    ###########################################################[

    Copyright (C) 1994-2019 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: P-2019.03G-1-Beta1
    Install: E:\Gowin\Gowin_V1.9.3Beta_37257_win\SynplifyPro
    OS: Windows 6.1

    Hostname: GW-SW-001

    Implementation : rev_1
    Synopsys Verilog Compiler, Version comp2019q1p1, Build 391R, Built Dec  3 2019 09:16:34

    @N: :  | Running in 64-bit mode
    @N:CG1349 :  | Running Verilog Compiler in System Verilog mode

    @N:CG1350 :  | Running Verilog Compiler in Multiple File Compilation Unit mode

    @I::"E:\Gowin\Gowin_V1.9.3Beta_37257_win\SynplifyPro\lib\generic\gw1n.v" (library work)
    @I::"E:\Gowin\Gowin_V1.9.3Beta_37257_win\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__)
    @I::"E:\Gowin\Gowin_V1.9.3Beta_37257_win\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps)
    @I::"E:\Gowin\Gowin_V1.9.3Beta_37257_win\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps)
    @I::"E:\Gowin\Gowin_V1.9.3Beta_37257_win\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps)
    @I::"E:\Gowin\Gowin_V1.9.3Beta_37257_win\IDE\ipcore\MIPI_TX\data\DPHY_TX.v" (library work)
    @I:"E:\Gowin\Gowin_V1.9.3Beta_37257_win\IDE\ipcore\MIPI_TX\data\DPHY_TX.v":"E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\src\DPHY_TX_TOP\temp\MIPI_Tx\dphy_define.v" (library work)
    @I:"E:\Gowin\Gowin_V1.9.3Beta_37257_win\IDE\ipcore\MIPI_TX\data\DPHY_TX.v":"E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\src\DPHY_TX_TOP\temp\MIPI_Tx\mipi_tx_pll_config.v" (library work)
    @I::"E:\Gowin\Gowin_V1.9.3Beta_37257_win\IDE\ipcore\MIPI_TX\data\DPHY_TX_TOP.v" (library work)
    Verilog syntax check successful!
    Selecting top level module DPHY_TX_TOP
    Running optimization stage 1 on PLL .......
    Running optimization stage 1 on \~pllx8.DPHY_TX_TOP  .......
    Running optimization stage 1 on LUT4 .......
    Running optimization stage 1 on OSER16 .......
    Running optimization stage 1 on CLKDIV .......
    Running optimization stage 1 on ELVDS_TBUF .......
    Running optimization stage 1 on \~oserx8.DPHY_TX_TOP  .......
    Running optimization stage 1 on \~DPHY_TX.DPHY_TX_TOP  .......
    @N:CG364 : DPHY_TX_TOP.v(165) | Synthesizing module DPHY_TX_TOP in library work.
    Running optimization stage 1 on DPHY_TX_TOP .......
    Running optimization stage 2 on DPHY_TX_TOP .......
    Running optimization stage 2 on \~DPHY_TX.DPHY_TX_TOP  .......
    Running optimization stage 2 on \~oserx8.DPHY_TX_TOP  .......
    Running optimization stage 2 on ELVDS_TBUF .......
    Running optimization stage 2 on CLKDIV .......
    Running optimization stage 2 on OSER16 .......
    Running optimization stage 2 on LUT4 .......
    Running optimization stage 2 on \~pllx8.DPHY_TX_TOP  .......
    Running optimization stage 2 on PLL .......

    For a summary of runtime and memory usage per design unit, please see file:
    ==========================================================
    Linked File:  layer0.rt.csv

    At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 88MB peak: 89MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Thu Mar 26 13:45:04 2020

    ###########################################################]
    ###########################################################[

    Copyright (C) 1994-2019 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: P-2019.03G-1-Beta1
    Install: E:\Gowin\Gowin_V1.9.3Beta_37257_win\SynplifyPro
    OS: Windows 6.1

    Hostname: GW-SW-001

    Implementation : rev_1
    Synopsys Synopsys Netlist Linker, Version comp2019q1p1, Build 391R, Built Dec  3 2019 09:16:34

    @N: :  | Running in 64-bit mode
    @N:NF107 : dphy_tx_top.v(165) | Selected library: work cell: DPHY_TX_TOP view verilog as top level
    @N:NF107 : dphy_tx_top.v(165) | Selected library: work cell: DPHY_TX_TOP view verilog as top level

    At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 87MB peak: 87MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Thu Mar 26 13:45:04 2020

    ###########################################################]

    For a summary of runtime and memory usage for all design units, please see file:
    ==========================================================
    Linked File:  DPHY_TX_TOP_comp.rt.csv

    @END

    At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 18MB peak: 18MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Thu Mar 26 13:45:04 2020

    ###########################################################]

`
`

    ###########################################################[

    Copyright (C) 1994-2019 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: P-2019.03G-1-Beta1
    Install: E:\Gowin\Gowin_V1.9.3Beta_37257_win\SynplifyPro
    OS: Windows 6.1

    Hostname: GW-SW-001

    Implementation : rev_1
    Synopsys Synopsys Netlist Linker, Version comp2019q1p1, Build 391R, Built Dec  3 2019 09:16:34

    @N: :  | Running in 64-bit mode
    @N:NF107 : dphy_tx_top.v(165) | Selected library: work cell: DPHY_TX_TOP view verilog as top level
    @N:NF107 : dphy_tx_top.v(165) | Selected library: work cell: DPHY_TX_TOP view verilog as top level

    At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 88MB peak: 88MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Thu Mar 26 13:45:05 2020

    ###########################################################]

`
`

    Premap Report

`
`

    # Thu Mar 26 13:45:06 2020

    Copyright (C) 1994-2019 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: P-2019.03G-1-Beta1
    Install: E:\Gowin\Gowin_V1.9.3Beta_37257_win\SynplifyPro
    OS: Windows 6.1

    Hostname: GW-SW-001

    Implementation : rev_1
    Synopsys Generic Technology Pre-mapping, Version mapgw2019q1p1, Build 007R, Built Dec  5 2019 10:27:23

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)

    @A:MF827 :  | No constraint file specified.
    Linked File:  DPHY_TX_TOP_scck.rpt
    Printing clock  summary report in "E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\src\DPHY_TX_TOP\temp\MIPI_Tx\rev_1\DPHY_TX_TOP_scck.rpt" file
    @N:MF916 :  | Option synthesis_strategy=base is enabled.
    @N:MF248 :  | Running in 64-bit mode.
    @N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 126MB peak: 126MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 126MB peak: 126MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 140MB)

    Starting clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 219MB peak: 219MB)

    Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 219MB peak: 219MB)

    Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 219MB peak: 220MB)

    Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 219MB peak: 220MB)

    Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 220MB peak: 220MB)

    Clock Summary
    ******************

              Start                                         Requested     Requested     Clock        Clock                     Clock
    Level     Clock                                         Frequency     Period        Type         Group                     Load
    --------------------------------------------------------------------------------------------------------------------------------
    0 -       System                                        100.0 MHz     10.000        system       system_clkgroup           5

    0 -       _~oserx8_DPHY_TX_TOP_|sclk_inferred_clock     563.4 MHz     1.775         inferred     Autoconstr_clkgroup_0     5
    ================================================================================================================================

    Clock Load Summary
    ***********************

                                                  Clock     Source                                             Clock Pin                                Non-clock Pin     Non-clock Pin
    Clock                                         Load      Pin                                                Seq Example                              Seq Example       Comb Example
    -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    System                                        5         -                                                  DPHY_TX_INST.u_oserx8.U6_OSER16.FCLK     -                 -

    _~oserx8_DPHY_TX_TOP_|sclk_inferred_clock     5         DPHY_TX_INST.u_oserx8.U3_CLKDIV.CLKOUT(CLKDIV)     DPHY_TX_INST.u_oserx8.U6_OSER16.PCLK     -                 -
    ===================================================================================================================================================================================

    ICG Latch Removal Summary:
    Number of ICG latches removed: 0
    Number of ICG latches not removed:	0

    @S |Clock Optimization Summary

    #### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[

    0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
    3 gated/generated clock tree(s) driving 10 clock pin(s) of sequential element(s)
    0 instances converted, 10 sequential instances remain driven by gated/generated clocks

    =================================================== Gated/Generated Clocks ====================================================
    Clock Tree ID     Driving Element     Drive Element Type     Unconverted Fanout     Sample Instance     Explanation
    -------------------------------------------------------------------------------------------------------------------------------
    ClockId_0_0       ENCRYPTED           PLL                    4                      ENCRYPTED           Black box on clock path
    ClockId_0_1       ENCRYPTED           CLKDIV                 5                      ENCRYPTED           Black box on clock path
    ClockId_0_2       ENCRYPTED           PLL                    1                      ENCRYPTED           Black box on clock path
    ===============================================================================================================================

    ##### END OF CLOCK OPTIMIZATION REPORT ######

    @N:FX1143 :  | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
    Finished Pre Mapping Phase.
    @N:BN225 :  | Writing default property annotation file E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\src\DPHY_TX_TOP\temp\MIPI_Tx\rev_1\DPHY_TX_TOP.sap.

    Starting constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 220MB peak: 220MB)

    Finished constraint checker preprocessing (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 220MB peak: 220MB)

    Finished constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 221MB peak: 221MB)

    Pre-mapping successful!

    At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 142MB peak: 222MB)

    Process took 0h:00m:02s realtime, 0h:00m:02s cputime
    # Thu Mar 26 13:45:08 2020

    ###########################################################]

`
`

    Map & Optimize Report

`
`

    # Thu Mar 26 13:45:08 2020

    Copyright (C) 1994-2019 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: P-2019.03G-1-Beta1
    Install: E:\Gowin\Gowin_V1.9.3Beta_37257_win\SynplifyPro
    OS: Windows 6.1

    Hostname: GW-SW-001

    Implementation : rev_1
    Synopsys Generic Technology Mapper, Version mapgw2019q1p1, Build 007R, Built Dec  5 2019 10:27:23

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)

    @N:MF916 :  | Option synthesis_strategy=base is enabled.
    @N:MF248 :  | Running in 64-bit mode.
    @N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 119MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 119MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 122MB peak: 122MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 137MB)

    Starting Optimization and Mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 216MB peak: 216MB)

    Available hyper_sources - for debug and ip models
    	None Found

    @N:MT206 :  | Auto Constrain mode is enabled

    Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 220MB peak: 220MB)

    Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 220MB peak: 220MB)

    Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 220MB peak: 220MB)

    Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 220MB peak: 220MB)

    Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 220MB peak: 221MB)

    Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 221MB peak: 221MB)

    Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 221MB peak: 221MB)

    Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 221MB peak: 221MB)

    Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 221MB peak: 221MB)

    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
       1		0h:00m:01s		    -0.36ns		   3 /         0

    Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 222MB peak: 222MB)

    @N:FX164 :  | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.

    Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 222MB peak: 222MB)

    Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 150MB peak: 222MB)

    Writing Analyst data base E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\src\DPHY_TX_TOP\temp\MIPI_Tx\rev_1\synwork\DPHY_TX_TOP_m.srm

    Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 222MB peak: 222MB)

    Writing Verilog Simulation files

    Writing scf file... (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 223MB peak: 223MB)

    @N:BW103 :  | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns.
    @N:BW107 :  | Synopsys Constraint File capacitance units using default value of 1pF

    Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 223MB peak: 223MB)

    Start final timing analysis (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 223MB peak: 223MB)

    @W:MT246 : dphy_tx.v(1822) | Blackbox CLKDIV is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
    @W:MT246 : dphy_tx.v(1896) | Blackbox PLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
    @W:MT420 :  | Found inferred clock _~oserx8_DPHY_TX_TOP_|sclk_inferred_clock with period 1.78ns. Please declare a user-defined clock on net DPHY_TX_INST.u_oserx8.sclk.

    ##### START OF TIMING REPORT #####[
    # Timing report written on Thu Mar 26 13:45:14 2020
    #

    Top view:               DPHY_TX_TOP
    Requested Frequency:    563.4 MHz
    Wire load mode:         top
    Paths requested:        5
    Constraint File(s):
    @N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.

    @N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock.

    Performance Summary
    *******************

    Worst slack in design: -0.153

                                                  Requested      Estimated     Requested     Estimated                Clock        Clock
    Starting Clock                                Frequency      Frequency     Period        Period        Slack      Type         Group
    ----------------------------------------------------------------------------------------------------------------------------------------------------
    _~oserx8_DPHY_TX_TOP_|sclk_inferred_clock     563.4 MHz      NA            1.775         NA            NA         inferred     Autoconstr_clkgroup_0
    System                                        1152.2 MHz     979.4 MHz     0.868         1.021         -0.153     system       system_clkgroup
    ====================================================================================================================================================
    Estimated period and frequency reported as NA means no slack depends directly on the clock waveform

    Clock Relationships
    *******************

    Clocks            |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise
    ---------------------------------------------------------------------------------------------------------
    Starting  Ending  |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
    ---------------------------------------------------------------------------------------------------------
    System    System  |  0.868       -0.153  |  No paths    -      |  No paths    -      |  No paths    -
    =========================================================================================================
     Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
           'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.

    Interface Information
    *********************

    No IO constraint found

    ====================================
    Detailed Report for Clock: System
    ====================================

    Starting Points with Worst Slack
    ********************************

                                         Starting                                        Arrival
    Instance                             Reference     Type     Pin        Net           Time        Slack
                                         Clock
    -------------------------------------------------------------------------------------------------------
    DPHY_TX_INST.u_pllx8.pll_mipi_tx     System        PLL      CLKOUT     clk_bit       0.000       -0.153
    DPHY_TX_INST.u_oserx8.reset_n_i      System        INV      O          reset_n_i     0.000       -0.153
    =======================================================================================================

    Ending Points with Worst Slack
    ******************************

                                         Starting                                          Required
    Instance                             Reference     Type       Pin        Net           Time         Slack
                                         Clock
    ----------------------------------------------------------------------------------------------------------
    DPHY_TX_INST.u_oserx8.U3_CLKDIV      System        CLKDIV     HCLKIN     clk_bit       0.868        -0.153
    DPHY_TX_INST.u_pllx8.pll_mipi_tx     System        PLL        RESET      reset_n_i     0.868        -0.153
    ==========================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      0.868
        - Setup time:                            0.000
        + Clock delay at ending point:           0.000 (ideal)
        + Estimated clock delay at ending point: 0.000
        = Required time:                         0.868

        - Propagation time:                      1.021
        - Clock delay at starting point:         0.000 (ideal)
        - Estimated clock delay at start point:  -0.000
        = Slack (critical) :                     -0.153

        Number of logic level(s):                0
        Starting point:                          DPHY_TX_INST.u_pllx8.pll_mipi_tx / CLKOUT
        Ending point:                            DPHY_TX_INST.u_oserx8.U3_CLKDIV / HCLKIN
        The start point is clocked by            System [rising]
        The end   point is clocked by            System [rising]

    Instance / Net                                  Pin        Pin               Arrival     No. of
    Name                                 Type       Name       Dir     Delay     Time        Fan Out(s)
    ---------------------------------------------------------------------------------------------------
    DPHY_TX_INST.u_pllx8.pll_mipi_tx     PLL        CLKOUT     Out     0.000     0.000       -
    clk_bit                              Net        -          -       1.021     -           5
    DPHY_TX_INST.u_oserx8.U3_CLKDIV      CLKDIV     HCLKIN     In      -         1.021       -
    ===================================================================================================
    Total path delay (propagation time + setup) of 1.021 is 0.000(0.0%) logic and 1.021(100.0%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 2:
          Requested Period:                      0.868
        - Setup time:                            0.000
        + Clock delay at ending point:           0.000 (ideal)
        + Estimated clock delay at ending point: 0.000
        = Required time:                         0.868

        - Propagation time:                      1.021
        - Clock delay at starting point:         0.000 (ideal)
        - Estimated clock delay at start point:  -0.000
        = Slack (critical) :                     -0.153

        Number of logic level(s):                0
        Starting point:                          DPHY_TX_INST.u_oserx8.reset_n_i / O
        Ending point:                            DPHY_TX_INST.u_pllx8.pll_mipi_tx / RESET
        The start point is clocked by            System [rising]
        The end   point is clocked by            System [rising]

    Instance / Net                                Pin       Pin               Arrival     No. of
    Name                                 Type     Name      Dir     Delay     Time        Fan Out(s)
    ------------------------------------------------------------------------------------------------
    DPHY_TX_INST.u_oserx8.reset_n_i      INV      O         Out     0.000     0.000       -
    reset_n_i                            Net      -         -       1.021     -           6
    DPHY_TX_INST.u_pllx8.pll_mipi_tx     PLL      RESET     In      -         1.021       -
    ================================================================================================
    Total path delay (propagation time + setup) of 1.021 is 0.000(0.0%) logic and 1.021(100.0%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ##### END OF TIMING REPORT #####]

    Timing exceptions that could not be applied

    Finished final timing analysis (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 223MB peak: 223MB)

    Finished timing report (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 223MB peak: 224MB)

    ---------------------------------------
    Resource Usage Report for DPHY_TX_TOP

    Mapping to part: gw1n_9pbga256-6
    Cell usage:
    CLKDIV          1 use
    GSR             1 use
    INV             3 uses
    OSER16          5 uses
    PLL             1 use

    I/O ports: 79
    I/O primitives: 5
    ELVDS_TBUF     5 uses

    I/O Register bits:                  0
    Register bits not including I/Os:   0 of 6480 (0%)
    Total load per clock:

    @S |Mapping Summary:
    Total  LUTs: 0 (0%)

    Mapper successful!

    At Mapper Exit (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 72MB peak: 224MB)

    Process took 0h:00m:05s realtime, 0h:00m:04s cputime
    # Thu Mar 26 13:45:14 2020

    ###########################################################]

`