Project Status Summary Page

Project Settings
Project Name | MIPI_RefDesign | Device Name | rev_1: GOWIN-GW1N : GW1N_9
Implementation Name | rev_1 | Top Module | DPHY_TOP
Pipelining | 1 | Retiming | 0
Resource Sharing | 1 | Fanout Guide | 10000
Disable I/O Insertion | 0 | Disable Sequential Optimizations | 0
Clock Conversion | 1 | FSM Compiler | 1

Run Status
Job Name | Status |  |  |  | CPU Time | Real Time | Memory | Date/Time
(compiler) | Complete | 13 | 16 | 0 | - | 00m:06s | - | 2020/3/30 11:17:03
(premap) | Complete | 5 | 1 | 0 | 0m:03s | 0m:03s | 228MB | 2020/3/30 11:17:10
(fpga_mapper) | Complete | 139 | 6 | 0 | 0m:07s | 0m:08s | 236MB | 2020/3/30 11:17:18
Multi-srs Generator | Complete |  |  |  | 00m:01s |  |  | 2020/3/30 11:17:05

Area Summary
I/O ports (io_port) | 26 | Non I/O Register bits (non_io_reg) | 1033 (15%)
I/O Register bits (total_io_reg) | 0 | Ultra Rams | 0
Block Rams (v_ram) | 2 (26) | Block Multipliers (dsp_used) | 0 (10)
LUTs (total_luts) | 1031 (11%) |  |

Timing Summary
Clock Name | Req Freq | Est Freq | Slack
--- | --- | --- | ---
_~DPHY_RX_DPHY_RX_TOP__|HS_CLK_inferred_clock | 274.3 MHz | 233.2 MHz | -0.643
_~idesx8_DPHY_RX_TOP__|clk_byte_out_inferred_clock | 111.6 MHz | 94.9 MHz | -1.581
_~oserx8_DPHY_TX_TOP__|sclk_0_inferred_clock | 216.9 MHz | 184.4 MHz | -0.813
System | 229.5 MHz | 195.1 MHz | -0.769

Optimizations Summary
Combined Clock Conversion | 0 / 7 |  |