@W: MT529 :"e:\gowin_work\ip_design\mipi\mipi_release_case\mipi_dphy_reference_design\mipi_refdesign\src\rom549x17.v":33:2:33:7|Found inferred clock _~oserx8_DPHY_TX_TOP__|sclk_0_inferred_clock which controls 49 sequential elements including u_ROM549x17.addr[9:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
