`

    #Build: Synplify Pro (R) P-2019.03G-1-Beta1, Build 387R, Dec  3 2019
    #install: E:\Gowin\Gowin_V1.9.3Beta_37257_win\SynplifyPro
    #OS: Windows 7 6.1
    #Hostname: GW-SW-001

    # Mon Mar 30 11:16:57 2020

    #Implementation: rev_1

    Copyright (C) 1994-2019 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: P-2019.03G-1-Beta1
    Install: E:\Gowin\Gowin_V1.9.3Beta_37257_win\SynplifyPro
    OS: Windows 6.1

    Hostname: GW-SW-001

    Implementation : rev_1
    Synopsys HDL Compiler, Version comp2019q1p1, Build 391R, Built Dec  3 2019 09:16:34

    @N: :  | Running in 64-bit mode
    ###########################################################[

    Copyright (C) 1994-2019 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: P-2019.03G-1-Beta1
    Install: E:\Gowin\Gowin_V1.9.3Beta_37257_win\SynplifyPro
    OS: Windows 6.1

    Hostname: GW-SW-001

    Implementation : rev_1
    Synopsys Verilog Compiler, Version comp2019q1p1, Build 391R, Built Dec  3 2019 09:16:34

    @N: :  | Running in 64-bit mode
    @N:CG1349 :  | Running Verilog Compiler in System Verilog mode

    @N:CG1350 :  | Running Verilog Compiler in Multiple File Compilation Unit mode

    @I::"E:\Gowin\Gowin_V1.9.3Beta_37257_win\SynplifyPro\lib\generic\gw1n.v" (library work)
    @I::"E:\Gowin\Gowin_V1.9.3Beta_37257_win\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__)
    @I::"E:\Gowin\Gowin_V1.9.3Beta_37257_win\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps)
    @I::"E:\Gowin\Gowin_V1.9.3Beta_37257_win\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps)
    @I::"E:\Gowin\Gowin_V1.9.3Beta_37257_win\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps)
    @I::"E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\src\DPHY_TOP.v" (library work)
    @I::"E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\src\gw_pll.v" (library work)
    @I::"E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\src\ROM549X17.v" (library work)
    @I::"E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\src\DPHY_RX_TOP\DPHY_RX_TOP.v" (library work)
    @I::"E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\src\DPHY_TX_TOP\DPHY_TX_TOP.v" (library work)
    Verilog syntax check successful!
    File E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\src\ROM549X17.v changed - recompiling
    Selecting top level module DPHY_TOP
    @N:CG364 : gw1n.v(2313) | Synthesizing module PLL in library work.
    Running optimization stage 1 on PLL .......
    @N:CG364 : gw_pll.v(14) | Synthesizing module GW_PLL in library work.
    Running optimization stage 1 on GW_PLL .......
    @N:CG364 : ROM549X17.v(20) | Synthesizing module ROM549x17 in library work.
    Running optimization stage 1 on ROM549x17 .......
    @N:CG364 : gw1n.v(2377) | Synthesizing module GSR in library work.
    Running optimization stage 1 on GSR .......
    Running optimization stage 1 on GND .......
    Running optimization stage 1 on VCC .......
    Running optimization stage 1 on \~pllx8.DPHY_TX_TOP_  .......
    Running optimization stage 1 on INV .......
    Running optimization stage 1 on ELVDS_TBUF .......
    Running optimization stage 1 on CLKDIV .......
    Running optimization stage 1 on OSER16 .......
    Running optimization stage 1 on \~oserx8.DPHY_TX_TOP_  .......
    Running optimization stage 1 on \~DPHY_TX.DPHY_TX_TOP_  .......
    @N:CG364 : DPHY_TX_TOP.v(451) | Synthesizing module DPHY_TX_TOP in library work.
    Running optimization stage 1 on DPHY_TX_TOP .......
    @W:CL168 : DPHY_TX_TOP.v(534) | Removing instance GND_cZ because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
    Running optimization stage 1 on ELVDS_IBUF .......
    Running optimization stage 1 on LUT1 .......
    Running optimization stage 1 on LUT2 .......
    Running optimization stage 1 on DFFCE .......
    Running optimization stage 1 on DFFPE .......
    Running optimization stage 1 on IODELAY .......
    Running optimization stage 1 on DHCEN .......
    Running optimization stage 1 on IDES16 .......
    Running optimization stage 1 on \~idesx8.DPHY_RX_TOP_  .......
    Running optimization stage 1 on MUX2_LUT5 .......
    Running optimization stage 1 on MUX2_LUT6 .......
    Running optimization stage 1 on MUX2_LUT7 .......
    Running optimization stage 1 on LUT4 .......
    Running optimization stage 1 on LUT3 .......
    Running optimization stage 1 on DFFC .......
    Running optimization stage 1 on \~word_aligner.DPHY_RX_TOP__6  .......
    Running optimization stage 1 on \~word_aligner.DPHY_RX_TOP__6_0  .......
    Running optimization stage 1 on \~word_aligner.DPHY_RX_TOP__6_1  .......
    Running optimization stage 1 on \~word_aligner.DPHY_RX_TOP__6_2  .......
    Running optimization stage 1 on DFFE .......
    Running optimization stage 1 on RAM16SDP4 .......
    Running optimization stage 1 on \~lane_align_FIFO.DPHY_RX_TOP_  .......
    Running optimization stage 1 on \~lane_align_FIFO.DPHY_RX_TOP__3  .......
    Running optimization stage 1 on \~lane_align_FIFO.DPHY_RX_TOP__4  .......
    Running optimization stage 1 on \~lane_align_FIFO.DPHY_RX_TOP__5  .......
    Running optimization stage 1 on \~lane_aligner.DPHY_RX_TOP__4s  .......
    Running optimization stage 1 on \~Aligner.DPHY_RX_TOP__4s_1s_1s  .......
    Running optimization stage 1 on \~DPHY_RX.DPHY_RX_TOP_  .......
    @N:CG364 : DPHY_RX_TOP.v(19809) | Synthesizing module DPHY_RX_TOP in library work.
    Running optimization stage 1 on DPHY_RX_TOP .......
    @N:CG364 : DPHY_TOP.v(99) | Synthesizing module DPHY_TOP in library work.
    @W:CG133 : DPHY_TOP.v(166) | Object data_in is declared but not assigned. Either assign a value or remove the declaration.
    @W:CG133 : DPHY_TOP.v(167) | Object data0 is declared but not assigned. Either assign a value or remove the declaration.
    @W:CG133 : DPHY_TOP.v(167) | Object data1 is declared but not assigned. Either assign a value or remove the declaration.
    @W:CG133 : DPHY_TOP.v(167) | Object data2 is declared but not assigned. Either assign a value or remove the declaration.
    @W:CG133 : DPHY_TOP.v(167) | Object data3 is declared but not assigned. Either assign a value or remove the declaration.
    @W:CG133 : DPHY_TOP.v(168) | Object dout is declared but not assigned. Either assign a value or remove the declaration.
    @W:CG133 : DPHY_TOP.v(169) | Object data_cntr is declared but not assigned. Either assign a value or remove the declaration.
    @W:CG133 : DPHY_TOP.v(170) | Object hactive_flag_RX is declared but not assigned. Either assign a value or remove the declaration.
    @W:CG360 : DPHY_TOP.v(172) | Removing wire lp_clk_out, as there is no assignment to it.
    @W:CG360 : DPHY_TOP.v(172) | Removing wire lp_data0_out, as there is no assignment to it.
    @W:CG360 : DPHY_TOP.v(172) | Removing wire lp_data1_out, as there is no assignment to it.
    @W:CG360 : DPHY_TOP.v(172) | Removing wire lp_data2_out, as there is no assignment to it.
    @W:CG360 : DPHY_TOP.v(172) | Removing wire lp_data3_out, as there is no assignment to it.
    @W:CG133 : DPHY_TOP.v(195) | Object hs_en is declared but not assigned. Either assign a value or remove the declaration.
    Running optimization stage 1 on DPHY_TOP .......
    Running optimization stage 2 on DPHY_TOP .......
    @W:CL156 : DPHY_TOP.v(172) | *Input lp_clk_out[1:0] to expression [ror] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
    Running optimization stage 2 on DPHY_RX_TOP .......
    @N:CL159 : DPHY_RX_TOP.v(19848) | Input term_en is unused.
    Running optimization stage 2 on \~DPHY_RX.DPHY_RX_TOP_  .......
    Running optimization stage 2 on \~Aligner.DPHY_RX_TOP__4s_1s_1s  .......
    Running optimization stage 2 on \~lane_aligner.DPHY_RX_TOP__4s  .......
    Running optimization stage 2 on \~lane_align_FIFO.DPHY_RX_TOP__5  .......
    Running optimization stage 2 on \~lane_align_FIFO.DPHY_RX_TOP__4  .......
    Running optimization stage 2 on \~lane_align_FIFO.DPHY_RX_TOP__3  .......
    Running optimization stage 2 on \~lane_align_FIFO.DPHY_RX_TOP_  .......
    Running optimization stage 2 on RAM16SDP4 .......
    Running optimization stage 2 on DFFE .......
    Running optimization stage 2 on \~word_aligner.DPHY_RX_TOP__6_2  .......
    Running optimization stage 2 on \~word_aligner.DPHY_RX_TOP__6_1  .......
    Running optimization stage 2 on \~word_aligner.DPHY_RX_TOP__6_0  .......
    Running optimization stage 2 on \~word_aligner.DPHY_RX_TOP__6  .......
    Running optimization stage 2 on DFFC .......
    Running optimization stage 2 on LUT3 .......
    Running optimization stage 2 on LUT4 .......
    Running optimization stage 2 on MUX2_LUT7 .......
    Running optimization stage 2 on MUX2_LUT6 .......
    Running optimization stage 2 on MUX2_LUT5 .......
    Running optimization stage 2 on \~idesx8.DPHY_RX_TOP_  .......
    Running optimization stage 2 on IDES16 .......
    Running optimization stage 2 on DHCEN .......
    Running optimization stage 2 on IODELAY .......
    Running optimization stage 2 on DFFPE .......
    Running optimization stage 2 on DFFCE .......
    Running optimization stage 2 on LUT2 .......
    Running optimization stage 2 on LUT1 .......
    Running optimization stage 2 on ELVDS_IBUF .......
    Running optimization stage 2 on DPHY_TX_TOP .......
    Running optimization stage 2 on \~DPHY_TX.DPHY_TX_TOP_  .......
    Running optimization stage 2 on \~oserx8.DPHY_TX_TOP_  .......
    Running optimization stage 2 on OSER16 .......
    Running optimization stage 2 on CLKDIV .......
    Running optimization stage 2 on ELVDS_TBUF .......
    Running optimization stage 2 on INV .......
    Running optimization stage 2 on \~pllx8.DPHY_TX_TOP_  .......
    Running optimization stage 2 on VCC .......
    Running optimization stage 2 on GND .......
    Running optimization stage 2 on GSR .......
    Running optimization stage 2 on ROM549x17 .......
    Running optimization stage 2 on GW_PLL .......
    Running optimization stage 2 on PLL .......

    For a summary of runtime and memory usage per design unit, please see file:
    ==========================================================
    Linked File:  layer0.rt.csv

    At c_ver Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 107MB peak: 107MB)

    Process took 0h:00m:02s realtime, 0h:00m:02s cputime

    Process completed successfully.
    # Mon Mar 30 11:17:02 2020

    ###########################################################]
    ###########################################################[

    Copyright (C) 1994-2019 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: P-2019.03G-1-Beta1
    Install: E:\Gowin\Gowin_V1.9.3Beta_37257_win\SynplifyPro
    OS: Windows 6.1

    Hostname: GW-SW-001

    Implementation : rev_1
    Synopsys Synopsys Netlist Linker, Version comp2019q1p1, Build 391R, Built Dec  3 2019 09:16:34

    @N: :  | Running in 64-bit mode

    At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 91MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Mon Mar 30 11:17:03 2020

    ###########################################################]

    For a summary of runtime and memory usage for all design units, please see file:
    ==========================================================
    Linked File:  MIPI_RefDesign_comp.rt.csv

    @END

    At c_hdl Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:02s; Memory used current: 18MB peak: 18MB)

    Process took 0h:00m:04s realtime, 0h:00m:02s cputime

    Process completed successfully.
    # Mon Mar 30 11:17:03 2020

    ###########################################################]

`
`

    ###########################################################[

    Copyright (C) 1994-2019 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: P-2019.03G-1-Beta1
    Install: E:\Gowin\Gowin_V1.9.3Beta_37257_win\SynplifyPro
    OS: Windows 6.1

    Hostname: GW-SW-001

    Implementation : rev_1
    Synopsys Synopsys Netlist Linker, Version comp2019q1p1, Build 391R, Built Dec  3 2019 09:16:34

    @N: :  | Running in 64-bit mode
    File E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\impl\synthesize\rev_1\synwork\MIPI_RefDesign_comp.srs changed - recompiling

    At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 92MB peak: 92MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Mon Mar 30 11:17:05 2020

    ###########################################################]

`
`

    # Mon Mar 30 11:17:06 2020

    Copyright (C) 1994-2019 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: P-2019.03G-1-Beta1
    Install: E:\Gowin\Gowin_V1.9.3Beta_37257_win\SynplifyPro
    OS: Windows 6.1

    Hostname: GW-SW-001

    Implementation : rev_1
    Synopsys Generic Technology Pre-mapping, Version mapgw2019q1p1, Build 007R, Built Dec  5 2019 10:27:23

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)

    @A:MF827 :  | No constraint file specified.
    Linked File:  MIPI_RefDesign_scck.rpt
    Printing clock  summary report in "E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\impl\synthesize\rev_1\MIPI_RefDesign_scck.rpt" file
    @N:MF916 :  | Option synthesis_strategy=base is enabled.
    @N:MF248 :  | Running in 64-bit mode.
    @N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 130MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 130MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 131MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB)

    Starting clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 225MB peak: 225MB)

    Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 225MB peak: 225MB)

    Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 225MB peak: 225MB)

    Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 225MB peak: 225MB)

    Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 225MB peak: 226MB)

    Clock Summary
    ******************

              Start                                                  Requested     Requested     Clock        Clock                     Clock
    Level     Clock                                                  Frequency     Period        Type         Group                     Load
    -----------------------------------------------------------------------------------------------------------------------------------------
    0 -       System                                                 100.0 MHz     10.000        system       system_clkgroup           9

    0 -       _~idesx8_DPHY_RX_TOP__|clk_byte_out_inferred_clock     172.5 MHz     5.796         inferred     Autoconstr_clkgroup_1     1018

    0 -       _~oserx8_DPHY_TX_TOP__|sclk_0_inferred_clock           229.0 MHz     4.367         inferred     Autoconstr_clkgroup_0     49

    0 -       _~DPHY_RX_DPHY_RX_TOP__|HS_CLK_inferred_clock          680.0 MHz     1.471         inferred     Autoconstr_clkgroup_2     4
    =========================================================================================================================================

    Clock Load Summary
    ***********************

                                                           Clock     Source                                                              Clock Pin                                                     Non-clock Pin     Non-clock Pin
    Clock                                                  Load      Pin                                                                 Seq Example                                                   Seq Example       Comb Example
    -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    System                                                 9         -                                                                   u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.Inst4_IDES16_0.FCLK       -                 -

    _~idesx8_DPHY_RX_TOP__|clk_byte_out_inferred_clock     1018      u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.Inst3_CLKDIV.CLKOUT(CLKDIV)     data_out_reg[63:0].C                                          -                 clk_byte_out.I[0](keepbuf)

    _~oserx8_DPHY_TX_TOP__|sclk_0_inferred_clock           49        u_DPHY_TX_TOP.DPHY_TX_INST.u_oserx8.U3_CLKDIV.CLKOUT(CLKDIV)        hactive_flag.C                                                -                 -

    _~DPHY_RX_DPHY_RX_TOP__|HS_CLK_inferred_clock          4         u_DPHY_RX_TOP.DPHY_RX_INST.U0_IB.O(ELVDS_IBUF)                      u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.\\opensync_Z\[3\].CLK     -                 -
    ===============================================================================================================================================================================================================================================

    @W:MT529 : rom549x17.v(33) | Found inferred clock _~oserx8_DPHY_TX_TOP__|sclk_0_inferred_clock which controls 49 sequential elements including u_ROM549x17.addr[9:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.

    ICG Latch Removal Summary:
    Number of ICG latches removed: 0
    Number of ICG latches not removed:	0

    @S |Clock Optimization Summary

    #### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[

    0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
    7 gated/generated clock tree(s) driving 1080 clock pin(s) of sequential element(s)
    0 instances converted, 1080 sequential instances remain driven by gated/generated clocks

    ==================================================================== Gated/Generated Clocks ====================================================================
    Clock Tree ID     Driving Element                Drive Element Type     Unconverted Fanout     Sample Instance        Explanation
    ----------------------------------------------------------------------------------------------------------------------------------------------------------------
    ClockId_0_1       ENCRYPTED                      CLKDIV                 954                    ENCRYPTED              Black box on clock path
    ClockId_0_2       ENCRYPTED                      DHCEN                  4                      ENCRYPTED              Black box on clock path
    ClockId_0_3       ENCRYPTED                      ELVDS_IBUF             4                      ENCRYPTED              Derived clock on input (not legal for GCC)
    ClockId_0_4       ENCRYPTED                      PLL                    1                      ENCRYPTED              Black box on clock path
    ClockId_0_6       ENCRYPTED                      CLKDIV                 49                     ENCRYPTED              Black box on clock path
    ClockId_0_7       ENCRYPTED                      PLL                    4                      ENCRYPTED              Black box on clock path
    ClockId_0_8       u_DPHY_RX_TOP.clk_byte_out     DPHY_RX_TOP            64                     data_out_reg[63:0]     Black box on clock path
    ================================================================================================================================================================

    ##### END OF CLOCK OPTIMIZATION REPORT ######

    @N:FX1143 :  | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
    Finished Pre Mapping Phase.
    @N:BN225 :  | Writing default property annotation file E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\impl\synthesize\rev_1\MIPI_RefDesign.sap.

    Starting constraint checker (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 227MB peak: 227MB)

    Finished constraint checker preprocessing (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 227MB peak: 227MB)

    Finished constraint checker (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 227MB peak: 227MB)

    Pre-mapping successful!

    At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 148MB peak: 228MB)

    Process took 0h:00m:03s realtime, 0h:00m:03s cputime
    # Mon Mar 30 11:17:10 2020

    ###########################################################]

`
`

    # Mon Mar 30 11:17:10 2020

    Copyright (C) 1994-2019 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: P-2019.03G-1-Beta1
    Install: E:\Gowin\Gowin_V1.9.3Beta_37257_win\SynplifyPro
    OS: Windows 6.1

    Hostname: GW-SW-001

    Implementation : rev_1
    Synopsys Generic Technology Mapper, Version mapgw2019q1p1, Build 007R, Built Dec  5 2019 10:27:23

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)

    @N:MF916 :  | Option synthesis_strategy=base is enabled.
    @N:MF248 :  | Running in 64-bit mode.
    @N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 119MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 119MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 122MB peak: 122MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 137MB)

    Starting Optimization and Mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 221MB peak: 221MB)

    Available hyper_sources - for debug and ip models
    	None Found

    @N:MT206 :  | Auto Constrain mode is enabled

    Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 233MB peak: 233MB)

    @N:MO231 : rom549x17.v(33) | Found counter in view:work.ROM549x17(verilog) instance addr[9:0]

    Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 234MB peak: 234MB)

    Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 234MB peak: 234MB)

    Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 235MB peak: 235MB)

    Starting Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 235MB peak: 235MB)

    Finished Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 235MB peak: 235MB)

    Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 235MB peak: 235MB)

    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_0.INIT_RAM_00 = 0000000000000000000000000000000000000000000000000000000000000000.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_0.INIT_RAM_01 = 0000000000000000000000000000000000000000000000000000000000000000.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_0.INIT_RAM_02 = 0000000000000000000000000000000000000000000000000000000000000000.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_0.INIT_RAM_03 = 0000000000000000000000000000000000000000000000000000000000000000.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_0.INIT_RAM_04 = 2020C0C0404080800000E0E06060A0A02020C0C04040808000002A2A37B80000.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_0.INIT_RAM_05 = 2020C0C0404080800000E0E06060A0A02020C0C0404080800000E0E06060A0A0.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_0.INIT_RAM_06 = 2020C0C0404080800000E0E06060A0A02020C0C0404080800000E0E06060A0A0.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_0.INIT_RAM_07 = 2020C0C0404080800000E0E06060A0A02020C0C0404080800000E0E06060A0A0.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_0.INIT_RAM_08 = 2020C0C0404080800000E0E06060A0A02020C0C0404080800000E0E06060A0A0.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_0.INIT_RAM_09 = 2020C0C0404080800000E0E06060A0A02020C0C0404080800000E0E06060A0A0.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_0.INIT_RAM_0A = 2020C0C0404080800000E0E06060A0A02020C0C0404080800000E0E06060A0A0.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_0.INIT_RAM_0B = 2020C0C0404080800000E0E06060A0A02020C0C0404080800000E0E06060A0A0.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_0.INIT_RAM_0C = 2020C0C0404080800000E0E06060A0A02020C0C0404080800000E0E06060A0A0.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_0.INIT_RAM_0D = 2020C0C0404080800000E0E06060A0A02020C0C0404080800000E0E06060A0A0.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_0.INIT_RAM_0E = 2020C0C0404080800000E0E06060A0A02020C0C0404080800000E0E06060A0A0.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_0.INIT_RAM_0F = 2020C0C0404080800000E0E06060A0A02020C0C0404080800000E0E06060A0A0.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_0.INIT_RAM_10 = 2020C0C0404080800000E0E06060A0A02020C0C0404080800000E0E06060A0A0.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_0.INIT_RAM_11 = 2020C0C0404080800000E0E06060A0A02020C0C0404080800000E0E06060A0A0.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_0.INIT_RAM_12 = 2020C0C0404080800000E0E06060A0A02020C0C0404080800000E0E06060A0A0.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_0.INIT_RAM_13 = 2020C0C0404080800000E0E06060A0A02020C0C0404080800000E0E06060A0A0.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_0.INIT_RAM_14 = 2020C0C0404080800000E0E06060A0A02020C0C0404080800000E0E06060A0A0.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_0.INIT_RAM_15 = 2020C0C0404080800000E0E06060A0A02020C0C0404080800000E0E06060A0A0.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_0.INIT_RAM_16 = 2020C0C0404080800000E0E06060A0A02020C0C0404080800000E0E06060A0A0.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_0.INIT_RAM_17 = 2020C0C0404080800000E0E06060A0A02020C0C0404080800000E0E06060A0A0.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_0.INIT_RAM_18 = 2020C0C0404080800000E0E06060A0A02020C0C0404080800000E0E06060A0A0.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_0.INIT_RAM_19 = 2020C0C0404080800000E0E06060A0A02020C0C0404080800000E0E06060A0A0.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_0.INIT_RAM_1A = 2020C0C0404080800000E0E06060A0A02020C0C0404080800000E0E06060A0A0.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_0.INIT_RAM_1B = 2020C0C0404080800000E0E06060A0A02020C0C0404080800000E0E06060A0A0.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_0.INIT_RAM_1C = 2020C0C0404080800000E0E06060A0A02020C0C0404080800000E0E06060A0A0.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_0.INIT_RAM_1D = 2020C0C0404080800000E0E06060A0A02020C0C0404080800000E0E06060A0A0.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_0.INIT_RAM_1E = 2020C0C0404080800000E0E06060A0A02020C0C0404080800000E0E06060A0A0.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_0.INIT_RAM_1F = 2020C0C0404080800000E0E06060A0A02020C0C0404080800000E0E06060A0A0.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_0.INIT_RAM_20 = 2020C0C0404080800000E0E06060A0A02020C0C0404080800000E0E06060A0A0.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_0.INIT_RAM_21 = 2020C0C0404080800000E0E06060A0A02020C0C0404080800000E0E06060A0A0.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_0.INIT_RAM_22 = 0000000000000000000000000000000000000000000037373737E0E06060A0A0.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_0.INIT_RAM_23 = 0000000000000000000000000000000000000000000000000000000000000000.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_0.INIT_RAM_24 = 0000000000000000000000000000000000000000000000000000000000000000.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_0.INIT_RAM_25 = 0000000000000000000000000000000000000000000000000000000000000000.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_0.INIT_RAM_26 = 0000000000000000000000000000000000000000000000000000000000000000.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_0.INIT_RAM_27 = 0000000000000000000000000000000000000000000000000000000000000000.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_0.INIT_RAM_28 = 0000000000000000000000000000000000000000000000000000000000000000.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_0.INIT_RAM_29 = 0000000000000000000000000000000000000000000000000000000000000000.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_0.INIT_RAM_2A = 0000000000000000000000000000000000000000000000000000000000000000.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_0.INIT_RAM_2B = 0000000000000000000000000000000000000000000000000000000000000000.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_0.INIT_RAM_2C = 0000000000000000000000000000000000000000000000000000000000000000.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_0.INIT_RAM_2D = 0000000000000000000000000000000000000000000000000000000000000000.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_0.INIT_RAM_2E = 0000000000000000000000000000000000000000000000000000000000000000.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_0.INIT_RAM_2F = 0000000000000000000000000000000000000000000000000000000000000000.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_0.INIT_RAM_30 = 0000000000000000000000000000000000000000000000000000000000000000.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_0.INIT_RAM_31 = 0000000000000000000000000000000000000000000000000000000000000000.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_0.INIT_RAM_32 = 0000000000000000000000000000000000000000000000000000000000000000.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_0.INIT_RAM_33 = 0000000000000000000000000000000000000000000000000000000000000000.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_0.INIT_RAM_34 = 0000000000000000000000000000000000000000000000000000000000000000.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_0.INIT_RAM_35 = 0000000000000000000000000000000000000000000000000000000000000000.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_0.INIT_RAM_36 = 0000000000000000000000000000000000000000000000000000000000000000.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_0.INIT_RAM_37 = 0000000000000000000000000000000000000000000000000000000000000000.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_0.INIT_RAM_38 = 0000000000000000000000000000000000000000000000000000000000000000.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_0.INIT_RAM_39 = 0000000000000000000000000000000000000000000000000000000000000000.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_0.INIT_RAM_3A = 0000000000000000000000000000000000000000000000000000000000000000.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_0.INIT_RAM_3B = 0000000000000000000000000000000000000000000000000000000000000000.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_0.INIT_RAM_3C = 0000000000000000000000000000000000000000000000000000000000000000.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_0.INIT_RAM_3D = 0000000000000000000000000000000000000000000000000000000000000000.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_0.INIT_RAM_3E = 0000000000000000000000000000000000000000000000000000000000000000.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_0.INIT_RAM_3F = 0000000000000000000000000000000000000000000000000000000000000000.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_1.INIT_RAM_00 = 0000000000000000000000000000000000000000000000000000000000000000.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_1.INIT_RAM_01 = 0000000000000000000000000000000000000000000000000000000000000000.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_1.INIT_RAM_02 = 0000000000000000000000000000000000000000000000000000000000000000.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_1.INIT_RAM_03 = 0001000100010001000100000000000000000000000000000000000000000000.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_1.INIT_RAM_04 = 0001000100010001000100010001000100010001000100010001000100010001.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_1.INIT_RAM_05 = 0001000100010001000100010001000100010001000100010001000100010001.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_1.INIT_RAM_06 = 0001000100010001000100010001000100010001000100010001000100010001.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_1.INIT_RAM_07 = 0001000100010001000100010001000100010001000100010001000100010001.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_1.INIT_RAM_08 = 0001000100010001000100010001000100010001000100010001000100010001.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_1.INIT_RAM_09 = 0001000100010001000100010001000100010001000100010001000100010001.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_1.INIT_RAM_0A = 0001000100010001000100010001000100010001000100010001000100010001.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_1.INIT_RAM_0B = 0001000100010001000100010001000100010001000100010001000100010001.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_1.INIT_RAM_0C = 0001000100010001000100010001000100010001000100010001000100010001.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_1.INIT_RAM_0D = 0001000100010001000100010001000100010001000100010001000100010001.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_1.INIT_RAM_0E = 0001000100010001000100010001000100010001000100010001000100010001.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_1.INIT_RAM_0F = 0001000100010001000100010001000100010001000100010001000100010001.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_1.INIT_RAM_10 = 0001000100010001000100010001000100010001000100010001000100010001.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_1.INIT_RAM_11 = 0001000100010001000100010001000100010001000100010001000100010001.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_1.INIT_RAM_12 = 0001000100010001000100010001000100010001000100010001000100010001.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_1.INIT_RAM_13 = 0001000100010001000100010001000100010001000100010001000100010001.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_1.INIT_RAM_14 = 0001000100010001000100010001000100010001000100010001000100010001.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_1.INIT_RAM_15 = 0001000100010001000100010001000100010001000100010001000100010001.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_1.INIT_RAM_16 = 0001000100010001000100010001000100010001000100010001000100010001.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_1.INIT_RAM_17 = 0001000100010001000100010001000100010001000100010001000100010001.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_1.INIT_RAM_18 = 0001000100010001000100010001000100010001000100010001000100010001.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_1.INIT_RAM_19 = 0001000100010001000100010001000100010001000100010001000100010001.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_1.INIT_RAM_1A = 0001000100010001000100010001000100010001000100010001000100010001.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_1.INIT_RAM_1B = 0001000100010001000100010001000100010001000100010001000100010001.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_1.INIT_RAM_1C = 0001000100010001000100010001000100010001000100010001000100010001.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_1.INIT_RAM_1D = 0001000100010001000100010001000100010001000100010001000100010001.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_1.INIT_RAM_1E = 0001000100010001000100010001000100010001000100010001000100010001.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_1.INIT_RAM_1F = 0001000100010001000100010001000100010001000100010001000100010001.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_1.INIT_RAM_20 = 0001000100010001000100010001000100010001000100010001000100010001.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_1.INIT_RAM_21 = 0001000100010001000100010001000100010001000100010001000100010001.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_1.INIT_RAM_22 = 0001000100010001000100010001000100010001000100010001000100010001.
    @N:FX276 : rom549x17.v(43) | Initial value u_ROM549x17.dout_2_0_1.INIT_RAM_23 = 0000000000000000000000010001000100010001000100010001000100010001.

    Only the first 100 messages of id 'FX276' are reported. To see all messages use 'report_messages -log E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\impl\synthesize\rev_1\synlog\MIPI_RefDesign_fpga_mapper.srr -id FX276' in the Tcl shell. To see all messages in future runs, use the command 'message_override -limit {FX276} -count unlimited' in the Tcl shell.
    @N:FX211 :  | Packed ROM u_ROM549x17.dout_2_0[16:0] (10 input, 17 output) to Block SelectRAM

    Finished preparing to map (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 235MB peak: 235MB)

    Finished technology mapping (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 235MB peak: 235MB)

    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
       1		0h:00m:02s		    -3.69ns		1041 /        91
       2		0h:00m:02s		    -3.69ns		1041 /        91

       3		0h:00m:03s		    -3.69ns		1041 /        91

       4		0h:00m:03s		    -3.69ns		1041 /        91

    Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 236MB peak: 236MB)

    @N:FX164 :  | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.

    Finished restoring hierarchy (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 236MB peak: 236MB)

    Start Writing Netlists (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 155MB peak: 236MB)

    Writing Analyst data base E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\impl\synthesize\rev_1\synwork\MIPI_RefDesign_m.srm

    Finished Writing Netlist Databases (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 232MB peak: 236MB)

    Writing Verilog Simulation files

    Writing scf file... (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 233MB peak: 236MB)

    @N:BW103 :  | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns.
    @N:BW107 :  | Synopsys Constraint File capacitance units using default value of 1pF

    Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 233MB peak: 236MB)

    Start final timing analysis (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 230MB peak: 236MB)

    @W:MT246 : dphy_rx_top.v(150) | Blackbox DHCEN is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
    @W:MT246 : dphy_rx_top.v(142) | Blackbox CLKDIV is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
    @W:MT246 : dphy_tx_top.v(42) | Blackbox PLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
    @W:MT420 :  | Found inferred clock _~oserx8_DPHY_TX_TOP__|sclk_0_inferred_clock with period 4.61ns. Please declare a user-defined clock on net u_DPHY_TX_TOP.DPHY_TX_INST.u_oserx8.sclk.
    @W:MT420 :  | Found inferred clock _~idesx8_DPHY_RX_TOP__|clk_byte_out_inferred_clock with period 8.96ns. Please declare a user-defined clock on net u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.clk_byte_out.
    @W:MT420 :  | Found inferred clock _~DPHY_RX_DPHY_RX_TOP__|HS_CLK_inferred_clock with period 3.65ns. Please declare a user-defined clock on net u_DPHY_RX_TOP.DPHY_RX_INST.HS_CLK.

    ##### START OF TIMING REPORT #####[
    # Timing report written on Mon Mar 30 11:17:18 2020
    #

    Top view:               DPHY_TOP
    Requested Frequency:    111.6 MHz
    Wire load mode:         top
    Paths requested:        5
    Constraint File(s):
    @N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.

    @N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock.

    Performance Summary
    *******************

    Worst slack in design: -1.581

                                                           Requested     Estimated     Requested     Estimated                Clock        Clock
    Starting Clock                                         Frequency     Frequency     Period        Period        Slack      Type         Group
    ------------------------------------------------------------------------------------------------------------------------------------------------------------
    _~DPHY_RX_DPHY_RX_TOP__|HS_CLK_inferred_clock          274.3 MHz     233.2 MHz     3.646         4.289         -0.643     inferred     Autoconstr_clkgroup_2
    _~idesx8_DPHY_RX_TOP__|clk_byte_out_inferred_clock     111.6 MHz     94.9 MHz      8.961         10.543        -1.581     inferred     Autoconstr_clkgroup_1
    _~oserx8_DPHY_TX_TOP__|sclk_0_inferred_clock           216.9 MHz     184.4 MHz     4.609         5.423         -0.813     inferred     Autoconstr_clkgroup_0
    System                                                 229.5 MHz     195.1 MHz     4.357         5.126         -0.769     system       system_clkgroup
    ============================================================================================================================================================

    Clock Relationships
    *******************

    Clocks                                                                                                  |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise
    -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    Starting                                            Ending                                              |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
    -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    System                                              System                                              |  4.357       -0.769  |  No paths    -      |  No paths    -      |  No paths    -
    System                                              _~idesx8_DPHY_RX_TOP__|clk_byte_out_inferred_clock  |  8.961       7.577   |  No paths    -      |  No paths    -      |  No paths    -
    _~oserx8_DPHY_TX_TOP__|sclk_0_inferred_clock        System                                              |  4.609       2.944   |  No paths    -      |  No paths    -      |  No paths    -
    _~oserx8_DPHY_TX_TOP__|sclk_0_inferred_clock        _~oserx8_DPHY_TX_TOP__|sclk_0_inferred_clock        |  4.609       -0.813  |  No paths    -      |  No paths    -      |  No paths    -
    _~idesx8_DPHY_RX_TOP__|clk_byte_out_inferred_clock  System                                              |  8.961       7.296   |  No paths    -      |  No paths    -      |  No paths    -
    _~idesx8_DPHY_RX_TOP__|clk_byte_out_inferred_clock  _~idesx8_DPHY_RX_TOP__|clk_byte_out_inferred_clock  |  8.961       -1.582  |  No paths    -      |  No paths    -      |  No paths    -
    _~DPHY_RX_DPHY_RX_TOP__|HS_CLK_inferred_clock       System                                              |  3.646       -0.564  |  No paths    -      |  No paths    -      |  No paths    -
    _~DPHY_RX_DPHY_RX_TOP__|HS_CLK_inferred_clock       _~DPHY_RX_DPHY_RX_TOP__|HS_CLK_inferred_clock       |  3.646       -0.643  |  No paths    -      |  No paths    -      |  No paths    -
    ===============================================================================================================================================================================================
     Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
           'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.

    Interface Information
    *********************

    No IO constraint found

    ====================================
    Detailed Report for Clock: _~DPHY_RX_DPHY_RX_TOP__|HS_CLK_inferred_clock
    ====================================

    Starting Points with Worst Slack
    ********************************

                                                              Starting                                                                            Arrival
    Instance                                                  Reference                                         Type      Pin     Net             Time        Slack
                                                              Clock
    ----------------------------------------------------------------------------------------------------------------------------------------------------------------
    u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.\\opensync_Z\[3\]     _~DPHY_RX_DPHY_RX_TOP__|HS_CLK_inferred_clock     DFFCE     Q       opensync[3]     0.440       -0.643
    u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.\\opensync_Z\[0\]     _~DPHY_RX_DPHY_RX_TOP__|HS_CLK_inferred_clock     DFFPE     Q       opensync[0]     0.440       -0.564
    u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.\\opensync_Z\[1\]     _~DPHY_RX_DPHY_RX_TOP__|HS_CLK_inferred_clock     DFFCE     Q       opensync[1]     0.440       -0.484
    u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.\\opensync_Z\[2\]     _~DPHY_RX_DPHY_RX_TOP__|HS_CLK_inferred_clock     DFFCE     Q       opensync[2]     0.440       1.820
    ================================================================================================================================================================

    Ending Points with Worst Slack
    ******************************

                                                              Starting                                                                              Required
    Instance                                                  Reference                                         Type      Pin     Net               Time         Slack
                                                              Clock
    -------------------------------------------------------------------------------------------------------------------------------------------------------------------
    u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.\\opensync_Z\[0\]     _~DPHY_RX_DPHY_RX_TOP__|HS_CLK_inferred_clock     DFFPE     CE      opensync_cken     3.486        -0.643
    u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.\\opensync_Z\[1\]     _~DPHY_RX_DPHY_RX_TOP__|HS_CLK_inferred_clock     DFFCE     CE      opensync_cken     3.486        -0.643
    u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.\\opensync_Z\[2\]     _~DPHY_RX_DPHY_RX_TOP__|HS_CLK_inferred_clock     DFFCE     CE      opensync_cken     3.486        -0.643
    u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.\\opensync_Z\[3\]     _~DPHY_RX_DPHY_RX_TOP__|HS_CLK_inferred_clock     DFFCE     CE      opensync_cken     3.486        -0.643
    u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.u_DHCEN               _~DPHY_RX_DPHY_RX_TOP__|HS_CLK_inferred_clock     DHCEN     CE      xstop             3.646        -0.564
    u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.\\opensync_Z\[0\]     _~DPHY_RX_DPHY_RX_TOP__|HS_CLK_inferred_clock     DFFPE     D       opensync[3]       3.486        1.820
    u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.\\opensync_Z\[1\]     _~DPHY_RX_DPHY_RX_TOP__|HS_CLK_inferred_clock     DFFCE     D       opensync[0]       3.486        1.820
    u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.\\opensync_Z\[2\]     _~DPHY_RX_DPHY_RX_TOP__|HS_CLK_inferred_clock     DFFCE     D       opensync[1]       3.486        1.820
    u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.\\opensync_Z\[3\]     _~DPHY_RX_DPHY_RX_TOP__|HS_CLK_inferred_clock     DFFCE     D       opensync[2]       3.486        1.820
    ===================================================================================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      3.646
        - Setup time:                            0.160
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         3.486

        - Propagation time:                      4.129
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.643

        Number of logic level(s):                1
        Starting point:                          u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.\\opensync_Z\[3\] / Q
        Ending point:                            u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.\\opensync_Z\[0\] / CE
        The start point is clocked by            _~DPHY_RX_DPHY_RX_TOP__|HS_CLK_inferred_clock [rising] on pin CLK
        The end   point is clocked by            _~DPHY_RX_DPHY_RX_TOP__|HS_CLK_inferred_clock [rising] on pin CLK

    Instance / Net                                                      Pin      Pin               Arrival     No. of
    Name                                                      Type      Name     Dir     Delay     Time        Fan Out(s)
    ---------------------------------------------------------------------------------------------------------------------
    u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.\\opensync_Z\[3\]     DFFCE     Q        Out     0.440     0.440       -
    opensync[3]                                               Net       -        -       1.225     -           2
    u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.LUT4_1                LUT1      I0       In      -         1.666       -
    u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.LUT4_1                LUT1      F        Out     1.238     2.904       -
    opensync_cken                                             Net       -        -       1.225     -           4
    u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.\\opensync_Z\[0\]     DFFPE     CE       In      -         4.129       -
    =====================================================================================================================
    Total path delay (propagation time + setup) of 4.289 is 1.838(42.9%) logic and 2.450(57.1%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 2:
          Requested Period:                      3.646
        - Setup time:                            0.160
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         3.486

        - Propagation time:                      4.129
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.643

        Number of logic level(s):                1
        Starting point:                          u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.\\opensync_Z\[3\] / Q
        Ending point:                            u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.\\opensync_Z\[3\] / CE
        The start point is clocked by            _~DPHY_RX_DPHY_RX_TOP__|HS_CLK_inferred_clock [rising] on pin CLK
        The end   point is clocked by            _~DPHY_RX_DPHY_RX_TOP__|HS_CLK_inferred_clock [rising] on pin CLK

    Instance / Net                                                      Pin      Pin               Arrival     No. of
    Name                                                      Type      Name     Dir     Delay     Time        Fan Out(s)
    ---------------------------------------------------------------------------------------------------------------------
    u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.\\opensync_Z\[3\]     DFFCE     Q        Out     0.440     0.440       -
    opensync[3]                                               Net       -        -       1.225     -           2
    u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.LUT4_1                LUT1      I0       In      -         1.666       -
    u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.LUT4_1                LUT1      F        Out     1.238     2.904       -
    opensync_cken                                             Net       -        -       1.225     -           4
    u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.\\opensync_Z\[3\]     DFFCE     CE       In      -         4.129       -
    =====================================================================================================================
    Total path delay (propagation time + setup) of 4.289 is 1.838(42.9%) logic and 2.450(57.1%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 3:
          Requested Period:                      3.646
        - Setup time:                            0.160
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         3.486

        - Propagation time:                      4.129
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.643

        Number of logic level(s):                1
        Starting point:                          u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.\\opensync_Z\[3\] / Q
        Ending point:                            u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.\\opensync_Z\[2\] / CE
        The start point is clocked by            _~DPHY_RX_DPHY_RX_TOP__|HS_CLK_inferred_clock [rising] on pin CLK
        The end   point is clocked by            _~DPHY_RX_DPHY_RX_TOP__|HS_CLK_inferred_clock [rising] on pin CLK

    Instance / Net                                                      Pin      Pin               Arrival     No. of
    Name                                                      Type      Name     Dir     Delay     Time        Fan Out(s)
    ---------------------------------------------------------------------------------------------------------------------
    u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.\\opensync_Z\[3\]     DFFCE     Q        Out     0.440     0.440       -
    opensync[3]                                               Net       -        -       1.225     -           2
    u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.LUT4_1                LUT1      I0       In      -         1.666       -
    u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.LUT4_1                LUT1      F        Out     1.238     2.904       -
    opensync_cken                                             Net       -        -       1.225     -           4
    u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.\\opensync_Z\[2\]     DFFCE     CE       In      -         4.129       -
    =====================================================================================================================
    Total path delay (propagation time + setup) of 4.289 is 1.838(42.9%) logic and 2.450(57.1%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 4:
          Requested Period:                      3.646
        - Setup time:                            0.160
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         3.486

        - Propagation time:                      4.129
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.643

        Number of logic level(s):                1
        Starting point:                          u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.\\opensync_Z\[3\] / Q
        Ending point:                            u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.\\opensync_Z\[1\] / CE
        The start point is clocked by            _~DPHY_RX_DPHY_RX_TOP__|HS_CLK_inferred_clock [rising] on pin CLK
        The end   point is clocked by            _~DPHY_RX_DPHY_RX_TOP__|HS_CLK_inferred_clock [rising] on pin CLK

    Instance / Net                                                      Pin      Pin               Arrival     No. of
    Name                                                      Type      Name     Dir     Delay     Time        Fan Out(s)
    ---------------------------------------------------------------------------------------------------------------------
    u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.\\opensync_Z\[3\]     DFFCE     Q        Out     0.440     0.440       -
    opensync[3]                                               Net       -        -       1.225     -           2
    u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.LUT4_1                LUT1      I0       In      -         1.666       -
    u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.LUT4_1                LUT1      F        Out     1.238     2.904       -
    opensync_cken                                             Net       -        -       1.225     -           4
    u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.\\opensync_Z\[1\]     DFFCE     CE       In      -         4.129       -
    =====================================================================================================================
    Total path delay (propagation time + setup) of 4.289 is 1.838(42.9%) logic and 2.450(57.1%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 5:
          Requested Period:                      3.646
        - Setup time:                            0.000
        + Clock delay at ending point:           0.000 (ideal)
        + Estimated clock delay at ending point: 0.000
        = Required time:                         3.646

        - Propagation time:                      4.210
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.564

        Number of logic level(s):                1
        Starting point:                          u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.\\opensync_Z\[0\] / Q
        Ending point:                            u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.u_DHCEN / CE
        The start point is clocked by            _~DPHY_RX_DPHY_RX_TOP__|HS_CLK_inferred_clock [rising] on pin CLK
        The end   point is clocked by            System [rising]

    Instance / Net                                                      Pin      Pin               Arrival     No. of
    Name                                                      Type      Name     Dir     Delay     Time        Fan Out(s)
    ---------------------------------------------------------------------------------------------------------------------
    u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.\\opensync_Z\[0\]     DFFPE     Q        Out     0.440     0.440       -
    opensync[0]                                               Net       -        -       1.225     -           2
    u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.LUT4_0                LUT2      I1       In      -         1.666       -
    u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.LUT4_0                LUT2      F        Out     1.319     2.984       -
    xstop                                                     Net       -        -       1.225     -           1
    u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.u_DHCEN               DHCEN     CE       In      -         4.210       -
    =====================================================================================================================
    Total path delay (propagation time + setup) of 4.210 is 1.759(41.8%) logic and 2.450(58.2%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ====================================
    Detailed Report for Clock: _~idesx8_DPHY_RX_TOP__|clk_byte_out_inferred_clock
    ====================================

    Starting Points with Worst Slack
    ********************************

                                                                               Starting                                                                                  Arrival
    Instance                                                                   Reference                                              Type      Pin     Net              Time        Slack
                                                                               Clock
    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    u_DPHY_RX_TOP.DPHY_RX_INST.u_Aligner.\\genblk4\.wd0.\\reg2_Z\[2\]          _~idesx8_DPHY_RX_TOP__|clk_byte_out_inferred_clock     DFFC      Q       reg2[2]          0.440       -1.581
    u_DPHY_RX_TOP.DPHY_RX_INST.u_Aligner.\\genblk2\.wd2.\\reg2_Z\[2\]          _~idesx8_DPHY_RX_TOP__|clk_byte_out_inferred_clock     DFFC      Q       reg2[2]          0.440       -1.581
    u_DPHY_RX_TOP.DPHY_RX_INST.u_Aligner.\\genblk3\.wd1.\\reg2_Z\[2\]          _~idesx8_DPHY_RX_TOP__|clk_byte_out_inferred_clock     DFFC      Q       reg2[2]          0.440       -1.581
    u_DPHY_RX_TOP.DPHY_RX_INST.u_Aligner.\\genblk1\.wd3.\\reg4_fast_Z\[8\]     _~idesx8_DPHY_RX_TOP__|clk_byte_out_inferred_clock     DFFC      Q       reg4_fast[8]     0.440       -1.581
    u_DPHY_RX_TOP.DPHY_RX_INST.u_Aligner.\\genblk4\.wd0.\\shftamt_Z\[3\]       _~idesx8_DPHY_RX_TOP__|clk_byte_out_inferred_clock     DFFCE     Q       shftamt[3]       0.440       -1.581
    u_DPHY_RX_TOP.DPHY_RX_INST.u_Aligner.\\genblk2\.wd2.\\shftamt_Z\[3\]       _~idesx8_DPHY_RX_TOP__|clk_byte_out_inferred_clock     DFFCE     Q       shftamt[3]       0.440       -1.581
    u_DPHY_RX_TOP.DPHY_RX_INST.u_Aligner.\\genblk1\.wd3.\\reg4_Z\[15\]         _~idesx8_DPHY_RX_TOP__|clk_byte_out_inferred_clock     DFFC      Q       reg4[15]         0.440       -1.508
    u_DPHY_RX_TOP.DPHY_RX_INST.u_Aligner.\\genblk2\.wd2.\\reg1_Z\[8\]          _~idesx8_DPHY_RX_TOP__|clk_byte_out_inferred_clock     DFFC      Q       reg1[8]          0.440       -1.501
    u_DPHY_RX_TOP.DPHY_RX_INST.u_Aligner.\\genblk4\.wd0.\\reg1_Z\[8\]          _~idesx8_DPHY_RX_TOP__|clk_byte_out_inferred_clock     DFFC      Q       reg1[8]          0.440       -1.501
    u_DPHY_RX_TOP.DPHY_RX_INST.u_Aligner.\\genblk3\.wd1.\\reg1_Z\[8\]          _~idesx8_DPHY_RX_TOP__|clk_byte_out_inferred_clock     DFFC      Q       reg1[8]          0.440       -1.501
    =======================================================================================================================================================================================

    Ending Points with Worst Slack
    ******************************

                                                                             Starting                                                                               Required
    Instance                                                                 Reference                                              Type      Pin     Net           Time         Slack
                                                                             Clock
    -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    u_DPHY_RX_TOP.DPHY_RX_INST.u_Aligner.\\genblk2\.wd2.\\shftamt_Z\[1\]     _~idesx8_DPHY_RX_TOP__|clk_byte_out_inferred_clock     DFFCE     CE      shftamt18     8.802        -1.581
    u_DPHY_RX_TOP.DPHY_RX_INST.u_Aligner.\\genblk3\.wd1.\\shftamt_Z\[1\]     _~idesx8_DPHY_RX_TOP__|clk_byte_out_inferred_clock     DFFCE     CE      shftamt18     8.802        -1.581
    u_DPHY_RX_TOP.DPHY_RX_INST.u_Aligner.\\genblk4\.wd0.\\shftamt_Z\[1\]     _~idesx8_DPHY_RX_TOP__|clk_byte_out_inferred_clock     DFFCE     CE      shftamt18     8.802        -1.581
    u_DPHY_RX_TOP.DPHY_RX_INST.u_Aligner.\\genblk3\.wd1.\\shftamt_Z\[2\]     _~idesx8_DPHY_RX_TOP__|clk_byte_out_inferred_clock     DFFCE     CE      shftamt28     8.802        -1.581
    u_DPHY_RX_TOP.DPHY_RX_INST.u_Aligner.\\genblk4\.wd0.\\shftamt_Z\[2\]     _~idesx8_DPHY_RX_TOP__|clk_byte_out_inferred_clock     DFFCE     CE      shftamt28     8.802        -1.581
    u_DPHY_RX_TOP.DPHY_RX_INST.u_Aligner.\\genblk1\.wd3.\\shftamt_Z\[2\]     _~idesx8_DPHY_RX_TOP__|clk_byte_out_inferred_clock     DFFCE     CE      shftamt28     8.802        -1.581
    u_DPHY_RX_TOP.DPHY_RX_INST.u_Aligner.\\genblk2\.wd2.\\shftamt_Z\[2\]     _~idesx8_DPHY_RX_TOP__|clk_byte_out_inferred_clock     DFFCE     CE      shftamt28     8.802        -1.581
    u_DPHY_RX_TOP.DPHY_RX_INST.u_Aligner.\\genblk1\.wd3.\\shftamt_Z\[5\]     _~idesx8_DPHY_RX_TOP__|clk_byte_out_inferred_clock     DFFCE     CE      shftamt58     8.802        -1.581
    u_DPHY_RX_TOP.DPHY_RX_INST.u_Aligner.\\genblk4\.wd0.\\shftamt_Z\[5\]     _~idesx8_DPHY_RX_TOP__|clk_byte_out_inferred_clock     DFFCE     CE      shftamt58     8.802        -1.581
    u_DPHY_RX_TOP.DPHY_RX_INST.u_Aligner.\\genblk2\.wd2.\\shftamt_Z\[5\]     _~idesx8_DPHY_RX_TOP__|clk_byte_out_inferred_clock     DFFCE     CE      shftamt58     8.802        -1.581
    ===================================================================================================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      8.961
        - Setup time:                            0.160
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         8.802

        - Propagation time:                      10.383
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -1.582

        Number of logic level(s):                4
        Starting point:                          u_DPHY_RX_TOP.DPHY_RX_INST.u_Aligner.\\genblk4\.wd0.\\reg2_Z\[2\] / Q
        Ending point:                            u_DPHY_RX_TOP.DPHY_RX_INST.u_Aligner.\\genblk4\.wd0.\\shftamt_Z\[15\] / CE
        The start point is clocked by            _~idesx8_DPHY_RX_TOP__|clk_byte_out_inferred_clock [rising] on pin CLK
        The end   point is clocked by            _~idesx8_DPHY_RX_TOP__|clk_byte_out_inferred_clock [rising] on pin CLK

    Instance / Net                                                                        Pin      Pin               Arrival     No. of
    Name                                                                        Type      Name     Dir     Delay     Time        Fan Out(s)
    ---------------------------------------------------------------------------------------------------------------------------------------
    u_DPHY_RX_TOP.DPHY_RX_INST.u_Aligner.\\genblk4\.wd0.\\reg2_Z\[2\]           DFFC      Q        Out     0.440     0.440       -
    reg2[2]                                                                     Net       -        -       1.225     -           3
    u_DPHY_RX_TOP.DPHY_RX_INST.u_Aligner.\\genblk4\.wd0.m56_0_a2_0_56_17_cZ     LUT4      I1       In      -         1.666       -
    u_DPHY_RX_TOP.DPHY_RX_INST.u_Aligner.\\genblk4\.wd0.m56_0_a2_0_56_17_cZ     LUT4      F        Out     1.319     2.984       -
    m56_0_a2_0_56_17                                                            Net       -        -       0.919     -           1
    u_DPHY_RX_TOP.DPHY_RX_INST.u_Aligner.\\genblk4\.wd0.m56_0_a2_0_56_25_cZ     LUT4      I1       In      -         3.903       -
    u_DPHY_RX_TOP.DPHY_RX_INST.u_Aligner.\\genblk4\.wd0.m56_0_a2_0_56_25_cZ     LUT4      F        Out     1.319     5.222       -
    m56_0_a2_0_56_25                                                            Net       -        -       1.225     -           2
    u_DPHY_RX_TOP.DPHY_RX_INST.u_Aligner.\\genblk4\.wd0.m56_0_a2_0_58_cZ        LUT3      I1       In      -         6.447       -
    u_DPHY_RX_TOP.DPHY_RX_INST.u_Aligner.\\genblk4\.wd0.m56_0_a2_0_58_cZ        LUT3      F        Out     1.319     7.766       -
    m56_0_a2_0_58                                                               Net       -        -       1.298     -           13
    u_DPHY_RX_TOP.DPHY_RX_INST.u_Aligner.\\genblk4\.wd0.m56_0_a2                LUT4      I1       In      -         9.065       -
    u_DPHY_RX_TOP.DPHY_RX_INST.u_Aligner.\\genblk4\.wd0.m56_0_a2                LUT4      F        Out     1.319     10.383      -
    shftamt158                                                                  Net       -        -       0.000     -           1
    u_DPHY_RX_TOP.DPHY_RX_INST.u_Aligner.\\genblk4\.wd0.\\shftamt_Z\[15\]       DFFCE     CE       In      -         10.383      -
    =======================================================================================================================================
    Total path delay (propagation time + setup) of 10.543 is 5.875(55.7%) logic and 4.668(44.3%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 2:
          Requested Period:                      8.961
        - Setup time:                            0.160
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         8.802

        - Propagation time:                      10.383
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -1.582

        Number of logic level(s):                4
        Starting point:                          u_DPHY_RX_TOP.DPHY_RX_INST.u_Aligner.\\genblk2\.wd2.\\reg2_Z\[2\] / Q
        Ending point:                            u_DPHY_RX_TOP.DPHY_RX_INST.u_Aligner.\\genblk2\.wd2.\\shftamt_Z\[15\] / CE
        The start point is clocked by            _~idesx8_DPHY_RX_TOP__|clk_byte_out_inferred_clock [rising] on pin CLK
        The end   point is clocked by            _~idesx8_DPHY_RX_TOP__|clk_byte_out_inferred_clock [rising] on pin CLK

    Instance / Net                                                                        Pin      Pin               Arrival     No. of
    Name                                                                        Type      Name     Dir     Delay     Time        Fan Out(s)
    ---------------------------------------------------------------------------------------------------------------------------------------
    u_DPHY_RX_TOP.DPHY_RX_INST.u_Aligner.\\genblk2\.wd2.\\reg2_Z\[2\]           DFFC      Q        Out     0.440     0.440       -
    reg2[2]                                                                     Net       -        -       1.225     -           3
    u_DPHY_RX_TOP.DPHY_RX_INST.u_Aligner.\\genblk2\.wd2.m56_0_a2_0_56_17_cZ     LUT4      I1       In      -         1.666       -
    u_DPHY_RX_TOP.DPHY_RX_INST.u_Aligner.\\genblk2\.wd2.m56_0_a2_0_56_17_cZ     LUT4      F        Out     1.319     2.984       -
    m56_0_a2_0_56_17                                                            Net       -        -       0.919     -           1
    u_DPHY_RX_TOP.DPHY_RX_INST.u_Aligner.\\genblk2\.wd2.m56_0_a2_0_56_25_cZ     LUT4      I1       In      -         3.903       -
    u_DPHY_RX_TOP.DPHY_RX_INST.u_Aligner.\\genblk2\.wd2.m56_0_a2_0_56_25_cZ     LUT4      F        Out     1.319     5.222       -
    m56_0_a2_0_56_25                                                            Net       -        -       1.225     -           2
    u_DPHY_RX_TOP.DPHY_RX_INST.u_Aligner.\\genblk2\.wd2.m56_0_a2_0_58_cZ        LUT3      I1       In      -         6.447       -
    u_DPHY_RX_TOP.DPHY_RX_INST.u_Aligner.\\genblk2\.wd2.m56_0_a2_0_58_cZ        LUT3      F        Out     1.319     7.766       -
    m56_0_a2_0_58                                                               Net       -        -       1.298     -           13
    u_DPHY_RX_TOP.DPHY_RX_INST.u_Aligner.\\genblk2\.wd2.m56_0_a2                LUT4      I1       In      -         9.065       -
    u_DPHY_RX_TOP.DPHY_RX_INST.u_Aligner.\\genblk2\.wd2.m56_0_a2                LUT4      F        Out     1.319     10.383      -
    shftamt158                                                                  Net       -        -       0.000     -           1
    u_DPHY_RX_TOP.DPHY_RX_INST.u_Aligner.\\genblk2\.wd2.\\shftamt_Z\[15\]       DFFCE     CE       In      -         10.383      -
    =======================================================================================================================================
    Total path delay (propagation time + setup) of 10.543 is 5.875(55.7%) logic and 4.668(44.3%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 3:
          Requested Period:                      8.961
        - Setup time:                            0.160
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         8.802

        - Propagation time:                      10.383
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -1.582

        Number of logic level(s):                4
        Starting point:                          u_DPHY_RX_TOP.DPHY_RX_INST.u_Aligner.\\genblk3\.wd1.\\reg2_Z\[2\] / Q
        Ending point:                            u_DPHY_RX_TOP.DPHY_RX_INST.u_Aligner.\\genblk3\.wd1.\\shftamt_Z\[15\] / CE
        The start point is clocked by            _~idesx8_DPHY_RX_TOP__|clk_byte_out_inferred_clock [rising] on pin CLK
        The end   point is clocked by            _~idesx8_DPHY_RX_TOP__|clk_byte_out_inferred_clock [rising] on pin CLK

    Instance / Net                                                                        Pin      Pin               Arrival     No. of
    Name                                                                        Type      Name     Dir     Delay     Time        Fan Out(s)
    ---------------------------------------------------------------------------------------------------------------------------------------
    u_DPHY_RX_TOP.DPHY_RX_INST.u_Aligner.\\genblk3\.wd1.\\reg2_Z\[2\]           DFFC      Q        Out     0.440     0.440       -
    reg2[2]                                                                     Net       -        -       1.225     -           3
    u_DPHY_RX_TOP.DPHY_RX_INST.u_Aligner.\\genblk3\.wd1.m56_0_a2_0_56_17_cZ     LUT4      I1       In      -         1.666       -
    u_DPHY_RX_TOP.DPHY_RX_INST.u_Aligner.\\genblk3\.wd1.m56_0_a2_0_56_17_cZ     LUT4      F        Out     1.319     2.984       -
    m56_0_a2_0_56_17                                                            Net       -        -       0.919     -           1
    u_DPHY_RX_TOP.DPHY_RX_INST.u_Aligner.\\genblk3\.wd1.m56_0_a2_0_56_25_cZ     LUT4      I1       In      -         3.903       -
    u_DPHY_RX_TOP.DPHY_RX_INST.u_Aligner.\\genblk3\.wd1.m56_0_a2_0_56_25_cZ     LUT4      F        Out     1.319     5.222       -
    m56_0_a2_0_56_25                                                            Net       -        -       1.225     -           2
    u_DPHY_RX_TOP.DPHY_RX_INST.u_Aligner.\\genblk3\.wd1.m56_0_a2_0_58_cZ        LUT3      I1       In      -         6.447       -
    u_DPHY_RX_TOP.DPHY_RX_INST.u_Aligner.\\genblk3\.wd1.m56_0_a2_0_58_cZ        LUT3      F        Out     1.319     7.766       -
    m56_0_a2_0_58                                                               Net       -        -       1.298     -           13
    u_DPHY_RX_TOP.DPHY_RX_INST.u_Aligner.\\genblk3\.wd1.m56_0_a2                LUT4      I1       In      -         9.065       -
    u_DPHY_RX_TOP.DPHY_RX_INST.u_Aligner.\\genblk3\.wd1.m56_0_a2                LUT4      F        Out     1.319     10.383      -
    shftamt158                                                                  Net       -        -       0.000     -           1
    u_DPHY_RX_TOP.DPHY_RX_INST.u_Aligner.\\genblk3\.wd1.\\shftamt_Z\[15\]       DFFCE     CE       In      -         10.383      -
    =======================================================================================================================================
    Total path delay (propagation time + setup) of 10.543 is 5.875(55.7%) logic and 4.668(44.3%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 4:
          Requested Period:                      8.961
        - Setup time:                            0.160
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         8.802

        - Propagation time:                      10.383
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -1.582

        Number of logic level(s):                4
        Starting point:                          u_DPHY_RX_TOP.DPHY_RX_INST.u_Aligner.\\genblk1\.wd3.\\reg4_fast_Z\[8\] / Q
        Ending point:                            u_DPHY_RX_TOP.DPHY_RX_INST.u_Aligner.\\genblk1\.wd3.\\shftamt_Z\[15\] / CE
        The start point is clocked by            _~idesx8_DPHY_RX_TOP__|clk_byte_out_inferred_clock [rising] on pin CLK
        The end   point is clocked by            _~idesx8_DPHY_RX_TOP__|clk_byte_out_inferred_clock [rising] on pin CLK

    Instance / Net                                                                        Pin      Pin               Arrival     No. of
    Name                                                                        Type      Name     Dir     Delay     Time        Fan Out(s)
    ---------------------------------------------------------------------------------------------------------------------------------------
    u_DPHY_RX_TOP.DPHY_RX_INST.u_Aligner.\\genblk1\.wd3.\\reg4_fast_Z\[8\]      DFFC      Q        Out     0.440     0.440       -
    reg4_fast[8]                                                                Net       -        -       1.225     -           1
    u_DPHY_RX_TOP.DPHY_RX_INST.u_Aligner.\\genblk1\.wd3.m56_0_a2_0_56_15_cZ     LUT4      I1       In      -         1.666       -
    u_DPHY_RX_TOP.DPHY_RX_INST.u_Aligner.\\genblk1\.wd3.m56_0_a2_0_56_15_cZ     LUT4      F        Out     1.319     2.984       -
    m56_0_a2_0_56_15                                                            Net       -        -       0.919     -           1
    u_DPHY_RX_TOP.DPHY_RX_INST.u_Aligner.\\genblk1\.wd3.m56_0_a2_0_56_21_cZ     LUT2      I1       In      -         3.903       -
    u_DPHY_RX_TOP.DPHY_RX_INST.u_Aligner.\\genblk1\.wd3.m56_0_a2_0_56_21_cZ     LUT2      F        Out     1.319     5.222       -
    m56_0_a2_0_56_21                                                            Net       -        -       1.225     -           2
    u_DPHY_RX_TOP.DPHY_RX_INST.u_Aligner.\\genblk1\.wd3.m56_0_a2_0_58_cZ        LUT4      I1       In      -         6.447       -
    u_DPHY_RX_TOP.DPHY_RX_INST.u_Aligner.\\genblk1\.wd3.m56_0_a2_0_58_cZ        LUT4      F        Out     1.319     7.766       -
    m56_0_a2_0_58                                                               Net       -        -       1.298     -           11
    u_DPHY_RX_TOP.DPHY_RX_INST.u_Aligner.\\genblk1\.wd3.m56_0_a2                LUT4      I1       In      -         9.065       -
    u_DPHY_RX_TOP.DPHY_RX_INST.u_Aligner.\\genblk1\.wd3.m56_0_a2                LUT4      F        Out     1.319     10.383      -
    shftamt158                                                                  Net       -        -       0.000     -           1
    u_DPHY_RX_TOP.DPHY_RX_INST.u_Aligner.\\genblk1\.wd3.\\shftamt_Z\[15\]       DFFCE     CE       In      -         10.383      -
    =======================================================================================================================================
    Total path delay (propagation time + setup) of 10.543 is 5.875(55.7%) logic and 4.668(44.3%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 5:
          Requested Period:                      8.961
        - Setup time:                            0.160
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         8.802

        - Propagation time:                      10.383
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -1.582

        Number of logic level(s):                4
        Starting point:                          u_DPHY_RX_TOP.DPHY_RX_INST.u_Aligner.\\genblk4\.wd0.\\shftamt_Z\[3\] / Q
        Ending point:                            u_DPHY_RX_TOP.DPHY_RX_INST.u_Aligner.\\genblk4\.wd0.\\shftamt_Z\[11\] / CE
        The start point is clocked by            _~idesx8_DPHY_RX_TOP__|clk_byte_out_inferred_clock [rising] on pin CLK
        The end   point is clocked by            _~idesx8_DPHY_RX_TOP__|clk_byte_out_inferred_clock [rising] on pin CLK

    Instance / Net                                                                      Pin      Pin               Arrival     No. of
    Name                                                                      Type      Name     Dir     Delay     Time        Fan Out(s)
    -------------------------------------------------------------------------------------------------------------------------------------
    u_DPHY_RX_TOP.DPHY_RX_INST.u_Aligner.\\genblk4\.wd0.\\shftamt_Z\[3\]      DFFCE     Q        Out     0.440     0.440       -
    shftamt[3]                                                                Net       -        -       1.225     -           2
    u_DPHY_RX_TOP.DPHY_RX_INST.u_Aligner.\\genblk4\.wd0.shiftflag_3_0_cZ      LUT4      I1       In      -         1.666       -
    u_DPHY_RX_TOP.DPHY_RX_INST.u_Aligner.\\genblk4\.wd0.shiftflag_3_0_cZ      LUT4      F        Out     1.319     2.984       -
    shiftflag_3_0                                                             Net       -        -       0.919     -           1
    u_DPHY_RX_TOP.DPHY_RX_INST.u_Aligner.\\genblk4\.wd0.shiftflag_cZ          LUT4      I1       In      -         3.903       -
    u_DPHY_RX_TOP.DPHY_RX_INST.u_Aligner.\\genblk4\.wd0.shiftflag_cZ          LUT4      F        Out     1.319     5.222       -
    shiftflag                                                                 Net       -        -       1.298     -           18
    u_DPHY_RX_TOP.DPHY_RX_INST.u_Aligner.\\genblk4\.wd0.m96_m3_e_3_cZ         LUT2      I1       In      -         6.521       -
    u_DPHY_RX_TOP.DPHY_RX_INST.u_Aligner.\\genblk4\.wd0.m96_m3_e_3_cZ         LUT2      F        Out     1.319     7.839       -
    m96_m3_e_3                                                                Net       -        -       1.225     -           3
    u_DPHY_RX_TOP.DPHY_RX_INST.u_Aligner.\\genblk4\.wd0.m96_0_a2              LUT3      I1       In      -         9.065       -
    u_DPHY_RX_TOP.DPHY_RX_INST.u_Aligner.\\genblk4\.wd0.m96_0_a2              LUT3      F        Out     1.319     10.383      -
    shftamt118                                                                Net       -        -       0.000     -           1
    u_DPHY_RX_TOP.DPHY_RX_INST.u_Aligner.\\genblk4\.wd0.\\shftamt_Z\[11\]     DFFCE     CE       In      -         10.383      -
    =====================================================================================================================================
    Total path delay (propagation time + setup) of 10.543 is 5.875(55.7%) logic and 4.668(44.3%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ====================================
    Detailed Report for Clock: _~oserx8_DPHY_TX_TOP__|sclk_0_inferred_clock
    ====================================

    Starting Points with Worst Slack
    ********************************

                            Starting                                                                      Arrival
    Instance                Reference                                        Type     Pin     Net         Time        Slack
                            Clock
    ------------------------------------------------------------------------------------------------------------------------
    u_ROM549x17.addr[0]     _~oserx8_DPHY_TX_TOP__|sclk_0_inferred_clock     DFFC     Q       addr[0]     0.440       -0.813
    u_ROM549x17.addr[1]     _~oserx8_DPHY_TX_TOP__|sclk_0_inferred_clock     DFFC     Q       addr[1]     0.440       -0.745
    u_ROM549x17.addr[2]     _~oserx8_DPHY_TX_TOP__|sclk_0_inferred_clock     DFFC     Q       addr[2]     0.440       -0.677
    u_ROM549x17.addr[3]     _~oserx8_DPHY_TX_TOP__|sclk_0_inferred_clock     DFFC     Q       addr[3]     0.440       -0.608
    u_ROM549x17.addr[4]     _~oserx8_DPHY_TX_TOP__|sclk_0_inferred_clock     DFFC     Q       addr[4]     0.440       -0.540
    u_ROM549x17.addr[5]     _~oserx8_DPHY_TX_TOP__|sclk_0_inferred_clock     DFFC     Q       addr[5]     0.440       -0.471
    u_ROM549x17.addr[6]     _~oserx8_DPHY_TX_TOP__|sclk_0_inferred_clock     DFFC     Q       addr[6]     0.440       -0.403
    u_ROM549x17.addr[7]     _~oserx8_DPHY_TX_TOP__|sclk_0_inferred_clock     DFFC     Q       addr[7]     0.440       -0.335
    u_ROM549x17.addr[8]     _~oserx8_DPHY_TX_TOP__|sclk_0_inferred_clock     DFFC     Q       addr[8]     0.440       -0.266
    u_ROM549x17.addr[9]     _~oserx8_DPHY_TX_TOP__|sclk_0_inferred_clock     DFFC     Q       addr[9]     0.440       0.366
    ========================================================================================================================

    Ending Points with Worst Slack
    ******************************

                            Starting                                                                        Required
    Instance                Reference                                        Type     Pin     Net           Time         Slack
                            Clock
    ---------------------------------------------------------------------------------------------------------------------------
    u_ROM549x17.addr[9]     _~oserx8_DPHY_TX_TOP__|sclk_0_inferred_clock     DFFC     D       addr_s[9]     4.450        -0.813
    u_ROM549x17.addr[8]     _~oserx8_DPHY_TX_TOP__|sclk_0_inferred_clock     DFFC     D       addr_s[8]     4.450        -0.745
    u_ROM549x17.addr[7]     _~oserx8_DPHY_TX_TOP__|sclk_0_inferred_clock     DFFC     D       addr_s[7]     4.450        -0.677
    u_ROM549x17.addr[6]     _~oserx8_DPHY_TX_TOP__|sclk_0_inferred_clock     DFFC     D       addr_s[6]     4.450        -0.608
    u_ROM549x17.addr[5]     _~oserx8_DPHY_TX_TOP__|sclk_0_inferred_clock     DFFC     D       addr_s[5]     4.450        -0.540
    u_ROM549x17.addr[4]     _~oserx8_DPHY_TX_TOP__|sclk_0_inferred_clock     DFFC     D       addr_s[4]     4.450        -0.471
    u_ROM549x17.addr[3]     _~oserx8_DPHY_TX_TOP__|sclk_0_inferred_clock     DFFC     D       addr_s[3]     4.450        -0.403
    u_ROM549x17.addr[2]     _~oserx8_DPHY_TX_TOP__|sclk_0_inferred_clock     DFFC     D       addr_s[2]     4.450        -0.335
    u_ROM549x17.addr[1]     _~oserx8_DPHY_TX_TOP__|sclk_0_inferred_clock     DFFC     D       addr_s[1]     4.450        -0.266
    u_ROM549x17.addr[0]     _~oserx8_DPHY_TX_TOP__|sclk_0_inferred_clock     DFFC     D       addr_s[0]     4.450        0.366
    ===========================================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      4.609
        - Setup time:                            0.160
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         4.450

        - Propagation time:                      5.263
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.813

        Number of logic level(s):                10
        Starting point:                          u_ROM549x17.addr[0] / Q
        Ending point:                            u_ROM549x17.addr[9] / D
        The start point is clocked by            _~oserx8_DPHY_TX_TOP__|sclk_0_inferred_clock [rising] on pin CLK
        The end   point is clocked by            _~oserx8_DPHY_TX_TOP__|sclk_0_inferred_clock [rising] on pin CLK

    Instance / Net                         Pin      Pin               Arrival     No. of
    Name                          Type     Name     Dir     Delay     Time        Fan Out(s)
    ----------------------------------------------------------------------------------------
    u_ROM549x17.addr[0]           DFFC     Q        Out     0.440     0.440       -
    addr[0]                       Net      -        -       1.225     -           3
    u_ROM549x17.addr_cry_0[0]     ALU      I0       In      -         1.666       -
    u_ROM549x17.addr_cry_0[0]     ALU      COUT     Out     1.150     2.815       -
    addr_cry[0]                   Net      -        -       0.000     -           1
    u_ROM549x17.addr_cry_0[1]     ALU      CIN      In      -         2.815       -
    u_ROM549x17.addr_cry_0[1]     ALU      COUT     Out     0.068     2.884       -
    addr_cry[1]                   Net      -        -       0.000     -           1
    u_ROM549x17.addr_cry_0[2]     ALU      CIN      In      -         2.884       -
    u_ROM549x17.addr_cry_0[2]     ALU      COUT     Out     0.068     2.952       -
    addr_cry[2]                   Net      -        -       0.000     -           1
    u_ROM549x17.addr_cry_0[3]     ALU      CIN      In      -         2.952       -
    u_ROM549x17.addr_cry_0[3]     ALU      COUT     Out     0.068     3.020       -
    addr_cry[3]                   Net      -        -       0.000     -           1
    u_ROM549x17.addr_cry_0[4]     ALU      CIN      In      -         3.020       -
    u_ROM549x17.addr_cry_0[4]     ALU      COUT     Out     0.068     3.089       -
    addr_cry[4]                   Net      -        -       0.000     -           1
    u_ROM549x17.addr_cry_0[5]     ALU      CIN      In      -         3.089       -
    u_ROM549x17.addr_cry_0[5]     ALU      COUT     Out     0.068     3.157       -
    addr_cry[5]                   Net      -        -       0.000     -           1
    u_ROM549x17.addr_cry_0[6]     ALU      CIN      In      -         3.157       -
    u_ROM549x17.addr_cry_0[6]     ALU      COUT     Out     0.068     3.226       -
    addr_cry[6]                   Net      -        -       0.000     -           1
    u_ROM549x17.addr_cry_0[7]     ALU      CIN      In      -         3.226       -
    u_ROM549x17.addr_cry_0[7]     ALU      COUT     Out     0.068     3.294       -
    addr_cry[7]                   Net      -        -       0.000     -           1
    u_ROM549x17.addr_cry_0[8]     ALU      CIN      In      -         3.294       -
    u_ROM549x17.addr_cry_0[8]     ALU      COUT     Out     0.068     3.362       -
    addr_cry[8]                   Net      -        -       0.000     -           1
    u_ROM549x17.addr_s_0[9]       ALU      CIN      In      -         3.362       -
    u_ROM549x17.addr_s_0[9]       ALU      SUM      Out     0.676     4.038       -
    addr_s[9]                     Net      -        -       1.225     -           1
    u_ROM549x17.addr[9]           DFFC     D        In      -         5.263       -
    ========================================================================================
    Total path delay (propagation time + setup) of 5.423 is 2.972(54.8%) logic and 2.450(45.2%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 2:
          Requested Period:                      4.609
        - Setup time:                            0.160
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         4.450

        - Propagation time:                      5.195
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.745

        Number of logic level(s):                9
        Starting point:                          u_ROM549x17.addr[1] / Q
        Ending point:                            u_ROM549x17.addr[9] / D
        The start point is clocked by            _~oserx8_DPHY_TX_TOP__|sclk_0_inferred_clock [rising] on pin CLK
        The end   point is clocked by            _~oserx8_DPHY_TX_TOP__|sclk_0_inferred_clock [rising] on pin CLK

    Instance / Net                         Pin      Pin               Arrival     No. of
    Name                          Type     Name     Dir     Delay     Time        Fan Out(s)
    ----------------------------------------------------------------------------------------
    u_ROM549x17.addr[1]           DFFC     Q        Out     0.440     0.440       -
    addr[1]                       Net      -        -       1.225     -           3
    u_ROM549x17.addr_cry_0[1]     ALU      I0       In      -         1.666       -
    u_ROM549x17.addr_cry_0[1]     ALU      COUT     Out     1.150     2.815       -
    addr_cry[1]                   Net      -        -       0.000     -           1
    u_ROM549x17.addr_cry_0[2]     ALU      CIN      In      -         2.815       -
    u_ROM549x17.addr_cry_0[2]     ALU      COUT     Out     0.068     2.884       -
    addr_cry[2]                   Net      -        -       0.000     -           1
    u_ROM549x17.addr_cry_0[3]     ALU      CIN      In      -         2.884       -
    u_ROM549x17.addr_cry_0[3]     ALU      COUT     Out     0.068     2.952       -
    addr_cry[3]                   Net      -        -       0.000     -           1
    u_ROM549x17.addr_cry_0[4]     ALU      CIN      In      -         2.952       -
    u_ROM549x17.addr_cry_0[4]     ALU      COUT     Out     0.068     3.020       -
    addr_cry[4]                   Net      -        -       0.000     -           1
    u_ROM549x17.addr_cry_0[5]     ALU      CIN      In      -         3.020       -
    u_ROM549x17.addr_cry_0[5]     ALU      COUT     Out     0.068     3.089       -
    addr_cry[5]                   Net      -        -       0.000     -           1
    u_ROM549x17.addr_cry_0[6]     ALU      CIN      In      -         3.089       -
    u_ROM549x17.addr_cry_0[6]     ALU      COUT     Out     0.068     3.157       -
    addr_cry[6]                   Net      -        -       0.000     -           1
    u_ROM549x17.addr_cry_0[7]     ALU      CIN      In      -         3.157       -
    u_ROM549x17.addr_cry_0[7]     ALU      COUT     Out     0.068     3.226       -
    addr_cry[7]                   Net      -        -       0.000     -           1
    u_ROM549x17.addr_cry_0[8]     ALU      CIN      In      -         3.226       -
    u_ROM549x17.addr_cry_0[8]     ALU      COUT     Out     0.068     3.294       -
    addr_cry[8]                   Net      -        -       0.000     -           1
    u_ROM549x17.addr_s_0[9]       ALU      CIN      In      -         3.294       -
    u_ROM549x17.addr_s_0[9]       ALU      SUM      Out     0.676     3.970       -
    addr_s[9]                     Net      -        -       1.225     -           1
    u_ROM549x17.addr[9]           DFFC     D        In      -         5.195       -
    ========================================================================================
    Total path delay (propagation time + setup) of 5.354 is 2.904(54.2%) logic and 2.450(45.8%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 3:
          Requested Period:                      4.609
        - Setup time:                            0.160
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         4.450

        - Propagation time:                      5.195
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.745

        Number of logic level(s):                9
        Starting point:                          u_ROM549x17.addr[0] / Q
        Ending point:                            u_ROM549x17.addr[8] / D
        The start point is clocked by            _~oserx8_DPHY_TX_TOP__|sclk_0_inferred_clock [rising] on pin CLK
        The end   point is clocked by            _~oserx8_DPHY_TX_TOP__|sclk_0_inferred_clock [rising] on pin CLK

    Instance / Net                         Pin      Pin               Arrival     No. of
    Name                          Type     Name     Dir     Delay     Time        Fan Out(s)
    ----------------------------------------------------------------------------------------
    u_ROM549x17.addr[0]           DFFC     Q        Out     0.440     0.440       -
    addr[0]                       Net      -        -       1.225     -           3
    u_ROM549x17.addr_cry_0[0]     ALU      I0       In      -         1.666       -
    u_ROM549x17.addr_cry_0[0]     ALU      COUT     Out     1.150     2.815       -
    addr_cry[0]                   Net      -        -       0.000     -           1
    u_ROM549x17.addr_cry_0[1]     ALU      CIN      In      -         2.815       -
    u_ROM549x17.addr_cry_0[1]     ALU      COUT     Out     0.068     2.884       -
    addr_cry[1]                   Net      -        -       0.000     -           1
    u_ROM549x17.addr_cry_0[2]     ALU      CIN      In      -         2.884       -
    u_ROM549x17.addr_cry_0[2]     ALU      COUT     Out     0.068     2.952       -
    addr_cry[2]                   Net      -        -       0.000     -           1
    u_ROM549x17.addr_cry_0[3]     ALU      CIN      In      -         2.952       -
    u_ROM549x17.addr_cry_0[3]     ALU      COUT     Out     0.068     3.020       -
    addr_cry[3]                   Net      -        -       0.000     -           1
    u_ROM549x17.addr_cry_0[4]     ALU      CIN      In      -         3.020       -
    u_ROM549x17.addr_cry_0[4]     ALU      COUT     Out     0.068     3.089       -
    addr_cry[4]                   Net      -        -       0.000     -           1
    u_ROM549x17.addr_cry_0[5]     ALU      CIN      In      -         3.089       -
    u_ROM549x17.addr_cry_0[5]     ALU      COUT     Out     0.068     3.157       -
    addr_cry[5]                   Net      -        -       0.000     -           1
    u_ROM549x17.addr_cry_0[6]     ALU      CIN      In      -         3.157       -
    u_ROM549x17.addr_cry_0[6]     ALU      COUT     Out     0.068     3.226       -
    addr_cry[6]                   Net      -        -       0.000     -           1
    u_ROM549x17.addr_cry_0[7]     ALU      CIN      In      -         3.226       -
    u_ROM549x17.addr_cry_0[7]     ALU      COUT     Out     0.068     3.294       -
    addr_cry[7]                   Net      -        -       0.000     -           1
    u_ROM549x17.addr_cry_0[8]     ALU      CIN      In      -         3.294       -
    u_ROM549x17.addr_cry_0[8]     ALU      SUM      Out     0.676     3.970       -
    addr_s[8]                     Net      -        -       1.225     -           1
    u_ROM549x17.addr[8]           DFFC     D        In      -         5.195       -
    ========================================================================================
    Total path delay (propagation time + setup) of 5.354 is 2.904(54.2%) logic and 2.450(45.8%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 4:
          Requested Period:                      4.609
        - Setup time:                            0.160
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         4.450

        - Propagation time:                      5.126
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.677

        Number of logic level(s):                8
        Starting point:                          u_ROM549x17.addr[2] / Q
        Ending point:                            u_ROM549x17.addr[9] / D
        The start point is clocked by            _~oserx8_DPHY_TX_TOP__|sclk_0_inferred_clock [rising] on pin CLK
        The end   point is clocked by            _~oserx8_DPHY_TX_TOP__|sclk_0_inferred_clock [rising] on pin CLK

    Instance / Net                         Pin      Pin               Arrival     No. of
    Name                          Type     Name     Dir     Delay     Time        Fan Out(s)
    ----------------------------------------------------------------------------------------
    u_ROM549x17.addr[2]           DFFC     Q        Out     0.440     0.440       -
    addr[2]                       Net      -        -       1.225     -           3
    u_ROM549x17.addr_cry_0[2]     ALU      I0       In      -         1.666       -
    u_ROM549x17.addr_cry_0[2]     ALU      COUT     Out     1.150     2.815       -
    addr_cry[2]                   Net      -        -       0.000     -           1
    u_ROM549x17.addr_cry_0[3]     ALU      CIN      In      -         2.815       -
    u_ROM549x17.addr_cry_0[3]     ALU      COUT     Out     0.068     2.884       -
    addr_cry[3]                   Net      -        -       0.000     -           1
    u_ROM549x17.addr_cry_0[4]     ALU      CIN      In      -         2.884       -
    u_ROM549x17.addr_cry_0[4]     ALU      COUT     Out     0.068     2.952       -
    addr_cry[4]                   Net      -        -       0.000     -           1
    u_ROM549x17.addr_cry_0[5]     ALU      CIN      In      -         2.952       -
    u_ROM549x17.addr_cry_0[5]     ALU      COUT     Out     0.068     3.020       -
    addr_cry[5]                   Net      -        -       0.000     -           1
    u_ROM549x17.addr_cry_0[6]     ALU      CIN      In      -         3.020       -
    u_ROM549x17.addr_cry_0[6]     ALU      COUT     Out     0.068     3.089       -
    addr_cry[6]                   Net      -        -       0.000     -           1
    u_ROM549x17.addr_cry_0[7]     ALU      CIN      In      -         3.089       -
    u_ROM549x17.addr_cry_0[7]     ALU      COUT     Out     0.068     3.157       -
    addr_cry[7]                   Net      -        -       0.000     -           1
    u_ROM549x17.addr_cry_0[8]     ALU      CIN      In      -         3.157       -
    u_ROM549x17.addr_cry_0[8]     ALU      COUT     Out     0.068     3.226       -
    addr_cry[8]                   Net      -        -       0.000     -           1
    u_ROM549x17.addr_s_0[9]       ALU      CIN      In      -         3.226       -
    u_ROM549x17.addr_s_0[9]       ALU      SUM      Out     0.676     3.901       -
    addr_s[9]                     Net      -        -       1.225     -           1
    u_ROM549x17.addr[9]           DFFC     D        In      -         5.126       -
    ========================================================================================
    Total path delay (propagation time + setup) of 5.286 is 2.836(53.6%) logic and 2.450(46.4%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 5:
          Requested Period:                      4.609
        - Setup time:                            0.160
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         4.450

        - Propagation time:                      5.126
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.677

        Number of logic level(s):                8
        Starting point:                          u_ROM549x17.addr[0] / Q
        Ending point:                            u_ROM549x17.addr[7] / D
        The start point is clocked by            _~oserx8_DPHY_TX_TOP__|sclk_0_inferred_clock [rising] on pin CLK
        The end   point is clocked by            _~oserx8_DPHY_TX_TOP__|sclk_0_inferred_clock [rising] on pin CLK

    Instance / Net                         Pin      Pin               Arrival     No. of
    Name                          Type     Name     Dir     Delay     Time        Fan Out(s)
    ----------------------------------------------------------------------------------------
    u_ROM549x17.addr[0]           DFFC     Q        Out     0.440     0.440       -
    addr[0]                       Net      -        -       1.225     -           3
    u_ROM549x17.addr_cry_0[0]     ALU      I0       In      -         1.666       -
    u_ROM549x17.addr_cry_0[0]     ALU      COUT     Out     1.150     2.815       -
    addr_cry[0]                   Net      -        -       0.000     -           1
    u_ROM549x17.addr_cry_0[1]     ALU      CIN      In      -         2.815       -
    u_ROM549x17.addr_cry_0[1]     ALU      COUT     Out     0.068     2.884       -
    addr_cry[1]                   Net      -        -       0.000     -           1
    u_ROM549x17.addr_cry_0[2]     ALU      CIN      In      -         2.884       -
    u_ROM549x17.addr_cry_0[2]     ALU      COUT     Out     0.068     2.952       -
    addr_cry[2]                   Net      -        -       0.000     -           1
    u_ROM549x17.addr_cry_0[3]     ALU      CIN      In      -         2.952       -
    u_ROM549x17.addr_cry_0[3]     ALU      COUT     Out     0.068     3.020       -
    addr_cry[3]                   Net      -        -       0.000     -           1
    u_ROM549x17.addr_cry_0[4]     ALU      CIN      In      -         3.020       -
    u_ROM549x17.addr_cry_0[4]     ALU      COUT     Out     0.068     3.089       -
    addr_cry[4]                   Net      -        -       0.000     -           1
    u_ROM549x17.addr_cry_0[5]     ALU      CIN      In      -         3.089       -
    u_ROM549x17.addr_cry_0[5]     ALU      COUT     Out     0.068     3.157       -
    addr_cry[5]                   Net      -        -       0.000     -           1
    u_ROM549x17.addr_cry_0[6]     ALU      CIN      In      -         3.157       -
    u_ROM549x17.addr_cry_0[6]     ALU      COUT     Out     0.068     3.226       -
    addr_cry[6]                   Net      -        -       0.000     -           1
    u_ROM549x17.addr_cry_0[7]     ALU      CIN      In      -         3.226       -
    u_ROM549x17.addr_cry_0[7]     ALU      SUM      Out     0.676     3.901       -
    addr_s[7]                     Net      -        -       1.225     -           1
    u_ROM549x17.addr[7]           DFFC     D        In      -         5.126       -
    ========================================================================================
    Total path delay (propagation time + setup) of 5.286 is 2.836(53.6%) logic and 2.450(46.4%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ====================================
    Detailed Report for Clock: System
    ====================================

    Starting Points with Worst Slack
    ********************************

                                                           Starting                                               Arrival
    Instance                                               Reference     Type       Pin        Net                Time        Slack
                                                           Clock
    --------------------------------------------------------------------------------------------------------------------------------
    u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.Inst3_CLKDIV       System        CLKDIV     CLKOUT     clk_byte_out_i     0.000       -0.769
    u_plld4.pll_inst                                       System        PLL        CLKOUT     clkx2              0.000       3.132
    u_DPHY_TX_TOP.DPHY_TX_INST.u_pllx8.pll_mipi_tx         System        PLL        CLKOUT     clk_bit            0.000       3.132
    u_DPHY_TX_TOP.DPHY_TX_INST.u_oserx8.reset_n_i          System        INV        O          reset_n_i          0.000       3.132
    u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.u_DHCEN            System        DHCEN      CLKOUT     eclko              0.000       3.132
    u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.Inst4_IDES16_0     System        IDES16     Q0         data[0]            0.000       7.577
    u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.Inst4_IDES16_0     System        IDES16     Q0         data[0]            0.000       7.577
    u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.Inst4_IDES16_0     System        IDES16     Q1         data[1]            0.000       7.577
    u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.Inst4_IDES16_0     System        IDES16     Q1         data[1]            0.000       7.577
    u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.Inst4_IDES16_0     System        IDES16     Q2         data[2]            0.000       7.577
    ================================================================================================================================

    Ending Points with Worst Slack
    ******************************

                                                           Starting                                               Required
    Instance                                               Reference     Type       Pin        Net                Time         Slack
                                                           Clock
    ---------------------------------------------------------------------------------------------------------------------------------
    u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.Inst4_IDES16_0     System        IDES16     PCLK       clk_byte_out_i     4.357        -0.769
    u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.Inst4_IDES16_0     System        IDES16     PCLK       clk_byte_out_i     4.357        -0.769
    u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.Inst4_IDES16_1     System        IDES16     PCLK       clk_byte_out_i     4.357        -0.769
    u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.Inst4_IDES16_1     System        IDES16     PCLK       clk_byte_out_i     4.357        -0.769
    u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.Inst4_IDES16_2     System        IDES16     PCLK       clk_byte_out_i     4.357        -0.769
    u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.Inst4_IDES16_2     System        IDES16     PCLK       clk_byte_out_i     4.357        -0.769
    u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.Inst4_IDES16_3     System        IDES16     PCLK       clk_byte_out_i     4.357        -0.769
    u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.Inst4_IDES16_3     System        IDES16     PCLK       clk_byte_out_i     4.357        -0.769
    u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.Inst3_CLKDIV       System        CLKDIV     HCLKIN     eclko              4.357        3.132
    u_DPHY_TX_TOP.DPHY_TX_INST.u_oserx8.U3_CLKDIV          System        CLKDIV     HCLKIN     clk_bit            4.357        3.132
    =================================================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      4.357
        - Setup time:                            0.000
        + Clock delay at ending point:           0.000 (ideal)
        + Estimated clock delay at ending point: 0.000
        = Required time:                         4.357

        - Propagation time:                      5.126
        - Clock delay at starting point:         0.000 (ideal)
        - Estimated clock delay at start point:  -0.000
        = Slack (non-critical) :                 -0.769

        Number of logic level(s):                0
        Starting point:                          u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.Inst3_CLKDIV / CLKOUT
        Ending point:                            u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.Inst4_IDES16_0 / PCLK
        The start point is clocked by            System [rising]
        The end   point is clocked by            System [rising]

    Instance / Net                                                    Pin        Pin               Arrival     No. of
    Name                                                   Type       Name       Dir     Delay     Time        Fan Out(s)
    ---------------------------------------------------------------------------------------------------------------------
    u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.Inst3_CLKDIV       CLKDIV     CLKOUT     Out     0.000     0.000       -
    clk_byte_out_i                                         Net        -          -       5.126     -           1022
    u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.Inst4_IDES16_0     IDES16     PCLK       In      -         5.126       -
    =====================================================================================================================
    Total path delay (propagation time + setup) of 5.126 is 0.000(0.0%) logic and 5.126(100.0%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 2:
          Requested Period:                      4.357
        - Setup time:                            0.000
        + Clock delay at ending point:           0.000 (ideal)
        + Estimated clock delay at ending point: 0.000
        = Required time:                         4.357

        - Propagation time:                      5.126
        - Clock delay at starting point:         0.000 (ideal)
        - Estimated clock delay at start point:  -0.000
        = Slack (non-critical) :                 -0.769

        Number of logic level(s):                0
        Starting point:                          u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.Inst3_CLKDIV / CLKOUT
        Ending point:                            u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.Inst4_IDES16_1 / PCLK
        The start point is clocked by            System [rising]
        The end   point is clocked by            System [rising]

    Instance / Net                                                    Pin        Pin               Arrival     No. of
    Name                                                   Type       Name       Dir     Delay     Time        Fan Out(s)
    ---------------------------------------------------------------------------------------------------------------------
    u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.Inst3_CLKDIV       CLKDIV     CLKOUT     Out     0.000     0.000       -
    clk_byte_out_i                                         Net        -          -       5.126     -           1022
    u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.Inst4_IDES16_1     IDES16     PCLK       In      -         5.126       -
    =====================================================================================================================
    Total path delay (propagation time + setup) of 5.126 is 0.000(0.0%) logic and 5.126(100.0%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 3:
          Requested Period:                      4.357
        - Setup time:                            0.000
        + Clock delay at ending point:           0.000 (ideal)
        + Estimated clock delay at ending point: 0.000
        = Required time:                         4.357

        - Propagation time:                      5.126
        - Clock delay at starting point:         0.000 (ideal)
        - Estimated clock delay at start point:  -0.000
        = Slack (non-critical) :                 -0.769

        Number of logic level(s):                0
        Starting point:                          u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.Inst3_CLKDIV / CLKOUT
        Ending point:                            u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.Inst4_IDES16_2 / PCLK
        The start point is clocked by            System [rising]
        The end   point is clocked by            System [rising]

    Instance / Net                                                    Pin        Pin               Arrival     No. of
    Name                                                   Type       Name       Dir     Delay     Time        Fan Out(s)
    ---------------------------------------------------------------------------------------------------------------------
    u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.Inst3_CLKDIV       CLKDIV     CLKOUT     Out     0.000     0.000       -
    clk_byte_out_i                                         Net        -          -       5.126     -           1022
    u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.Inst4_IDES16_2     IDES16     PCLK       In      -         5.126       -
    =====================================================================================================================
    Total path delay (propagation time + setup) of 5.126 is 0.000(0.0%) logic and 5.126(100.0%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 4:
          Requested Period:                      4.357
        - Setup time:                            0.000
        + Clock delay at ending point:           0.000 (ideal)
        + Estimated clock delay at ending point: 0.000
        = Required time:                         4.357

        - Propagation time:                      5.126
        - Clock delay at starting point:         0.000 (ideal)
        - Estimated clock delay at start point:  -0.000
        = Slack (non-critical) :                 -0.769

        Number of logic level(s):                0
        Starting point:                          u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.Inst3_CLKDIV / CLKOUT
        Ending point:                            u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.Inst4_IDES16_3 / PCLK
        The start point is clocked by            System [rising]
        The end   point is clocked by            System [rising]

    Instance / Net                                                    Pin        Pin               Arrival     No. of
    Name                                                   Type       Name       Dir     Delay     Time        Fan Out(s)
    ---------------------------------------------------------------------------------------------------------------------
    u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.Inst3_CLKDIV       CLKDIV     CLKOUT     Out     0.000     0.000       -
    clk_byte_out_i                                         Net        -          -       5.126     -           1022
    u_DPHY_RX_TOP.DPHY_RX_INST.u_idesx8.Inst4_IDES16_3     IDES16     PCLK       In      -         5.126       -
    =====================================================================================================================
    Total path delay (propagation time + setup) of 5.126 is 0.000(0.0%) logic and 5.126(100.0%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 5:
          Requested Period:                      4.357
        - Setup time:                            0.000
        + Clock delay at ending point:           0.000 (ideal)
        + Estimated clock delay at ending point: 0.000
        = Required time:                         4.357

        - Propagation time:                      1.225
        - Clock delay at starting point:         0.000 (ideal)
        - Estimated clock delay at start point:  -0.000
        = Slack (non-critical) :                 3.132

        Number of logic level(s):                0
        Starting point:                          u_plld4.pll_inst / CLKOUT
        Ending point:                            u_DPHY_TX_TOP.DPHY_TX_INST.u_pllx8.pll_mipi_tx / CLKIN
        The start point is clocked by            System [rising]
        The end   point is clocked by            System [rising]

    Instance / Net                                              Pin        Pin               Arrival     No. of
    Name                                               Type     Name       Dir     Delay     Time        Fan Out(s)
    ---------------------------------------------------------------------------------------------------------------
    u_plld4.pll_inst                                   PLL      CLKOUT     Out     0.000     0.000       -
    clkx2                                              Net      -          -       1.225     -           1
    u_DPHY_TX_TOP.DPHY_TX_INST.u_pllx8.pll_mipi_tx     PLL      CLKIN      In      -         1.225       -
    ===============================================================================================================
    Total path delay (propagation time + setup) of 1.225 is 0.000(0.0%) logic and 1.225(100.0%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ##### END OF TIMING REPORT #####]

    Timing exceptions that could not be applied

    Finished final timing analysis (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 231MB peak: 236MB)

    Finished timing report (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 231MB peak: 236MB)

    ---------------------------------------
    Resource Usage Report for DPHY_TOP

    Mapping to part: gw1n_9pbga256-5
    Cell usage:
    ALU             10 uses
    CLKDIV          2 uses
    DFFC            829 uses
    DFFCE           139 uses
    DFFE            64 uses
    DFFPE           1 use
    DHCEN           1 use
    GSR             2 uses
    IDES16          4 uses
    INV             9 uses
    IODELAY         4 uses
    MUX2_LUT5       256 uses
    MUX2_LUT6       128 uses
    MUX2_LUT7       64 uses
    OSER16          5 uses
    PLL             2 uses
    RAM16SDP4       16 uses
    pROM            2 uses
    LUT1            1 use
    LUT2            70 uses
    LUT3            595 uses
    LUT4            365 uses

    I/O ports: 26
    I/O primitives: 16
    ELVDS_IBUF     5 uses
    ELVDS_TBUF     5 uses
    IBUF           2 uses
    OBUF           4 uses

    I/O Register bits:                  0
    Register bits not including I/Os:   1033 of 6480 (15%)

    RAM/ROM usage summary
    Block Rams : 2 of 26 (7%)

    Total load per clock:
       _~oserx8_DPHY_TX_TOP__|sclk_0_inferred_clock: 34
       _~idesx8_DPHY_RX_TOP__|clk_byte_out_inferred_clock: 955

    @S |Mapping Summary:
    Total  LUTs: 1031 (11%)

    Mapper successful!

    At Mapper Exit (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 76MB peak: 236MB)

    Process took 0h:00m:08s realtime, 0h:00m:07s cputime
    # Mon Mar 30 11:17:18 2020

    ###########################################################]

`