@N|Running in 64-bit mode
@N|Running in 64-bit mode
@N: CG1349 :	| Running Verilog Compiler in System Verilog mode
@N: CG1350 :	| Running Verilog Compiler in Multiple File Compilation Unit mode
@N: CG364 :"E:\Gowin\Gowin_V1.9.3Beta_37257_win\IDE\ipcore\MIPI_TX\data\DPHY_TX_TOP.v":165:22:165:22|Synthesizing module DPHY_TX_TOP in library work.
@N|Running in 64-bit mode
@N: NF107 :"e:\gowin\gowin_v1.9.3beta_37257_win\ide\ipcore\mipi_tx\data\dphy_tx_top.v":165:22:165:22|Selected library: work cell: DPHY_TX_TOP view verilog as top level
@N: NF107 :"e:\gowin\gowin_v1.9.3beta_37257_win\ide\ipcore\mipi_tx\data\dphy_tx_top.v":165:22:165:22|Selected library: work cell: DPHY_TX_TOP view verilog as top level

