@N|Running in 64-bit mode
@N|Running in 64-bit mode
@N: CG1349 :	| Running Verilog Compiler in System Verilog mode
@N: CG1350 :	| Running Verilog Compiler in Multiple File Compilation Unit mode
@N: CG364 :"E:\Gowin\Gowin_V1.9.3Beta_37257_win\SynplifyPro\lib\generic\gw1n.v":2313:7:2313:9|Synthesizing module PLL in library work.
@N: CG364 :"E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\src\gw_pll.v":14:7:14:12|Synthesizing module GW_PLL in library work.
@N: CG364 :"E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\src\ROM549X17.v":20:7:20:15|Synthesizing module ROM549x17 in library work.
@N: CG364 :"E:\Gowin\Gowin_V1.9.3Beta_37257_win\SynplifyPro\lib\generic\gw1n.v":2377:7:2377:9|Synthesizing module GSR in library work.
@N: CG364 :"E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\src\DPHY_TX_TOP\DPHY_TX_TOP.v":451:7:451:17|Synthesizing module DPHY_TX_TOP in library work.
@N: CG364 :"E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\src\DPHY_RX_TOP\DPHY_RX_TOP.v":19809:7:19809:17|Synthesizing module DPHY_RX_TOP in library work.
@N: CG364 :"E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\src\DPHY_TOP.v":99:7:99:14|Synthesizing module DPHY_TOP in library work.
@N: CL159 :"E:\GOWIN_WORK\IP_Design\MIPI\MIPI_release_case\MIPI_DPHY_Reference_Design\MIPI_RefDesign\src\DPHY_RX_TOP\DPHY_RX_TOP.v":19848:6:19848:12|Input term_en is unused.
@N|Running in 64-bit mode

