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This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03G-1-Beta1
Install: E:\Gowin\Gowin_V1.9.3Beta_37257_win\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-001

Implementation : rev_1

# Written on Mon Mar 30 11:17:10 2020

##### DESIGN INFO #######################################################

Top View:                "DPHY_TOP"
Constraint File(s):      (none)




##### SUMMARY ############################################################

Found 0 issues in 0 out of 0 constraints


##### DETAILS ############################################################



Clock Relationships
*******************

Starting                                               Ending                                                 |     rise to rise     |     fall to fall     |     rise to fall     |     fall to rise                     
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
System                                                 System                                                 |     10.000           |     No paths         |     No paths         |     No paths                         
System                                                 _~idesx8_DPHY_RX_TOP__|clk_byte_out_inferred_clock     |     5.796            |     No paths         |     No paths         |     No paths                         
_~oserx8_DPHY_TX_TOP__|sclk_0_inferred_clock           System                                                 |     4.367            |     No paths         |     No paths         |     No paths                         
_~oserx8_DPHY_TX_TOP__|sclk_0_inferred_clock           _~oserx8_DPHY_TX_TOP__|sclk_0_inferred_clock           |     4.367            |     No paths         |     No paths         |     No paths                         
_~idesx8_DPHY_RX_TOP__|clk_byte_out_inferred_clock     System                                                 |     5.796            |     No paths         |     No paths         |     No paths                         
_~idesx8_DPHY_RX_TOP__|clk_byte_out_inferred_clock     _~idesx8_DPHY_RX_TOP__|clk_byte_out_inferred_clock     |     5.796            |     No paths         |     No paths         |     No paths                         
_~DPHY_RX_DPHY_RX_TOP__|HS_CLK_inferred_clock          System                                                 |     1.471            |     No paths         |     No paths         |     No paths                         
_~DPHY_RX_DPHY_RX_TOP__|HS_CLK_inferred_clock          _~DPHY_RX_DPHY_RX_TOP__|HS_CLK_inferred_clock          |     1.471            |     No paths         |     No paths         |     No paths                         
=========================================================================================================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.


Unconstrained Start/End Points
******************************

p:HS_CLK_RX_N
p:HS_CLK_RX_P
p:HS_CLK_TX_N
p:HS_CLK_TX_P
p:HS_DATA0_RX_N
p:HS_DATA0_RX_P
p:HS_DATA0_TX_N
p:HS_DATA0_TX_P
p:HS_DATA1_RX_N
p:HS_DATA1_RX_P
p:HS_DATA1_TX_N
p:HS_DATA1_TX_P
p:HS_DATA2_RX_N
p:HS_DATA2_RX_P
p:HS_DATA2_TX_N
p:HS_DATA2_TX_P
p:HS_DATA3_RX_N
p:HS_DATA3_RX_P
p:HS_DATA3_TX_N
p:HS_DATA3_TX_P
p:clkx2x4
p:hactive_flag
p:probe[0]
p:probe[1]
p:ready
p:rstn


Inapplicable constraints
************************

(none)


Applicable constraints with issues
**********************************

(none)


Constraints with matching wildcard expressions
**********************************************

(none)


Library Report
**************


# End of Constraint Checker Report
