Timing Messages
Report Title | Timing Analysis Report |
Design File | F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\DSI_Test_Pattern_1nr9\fpga_proj\impl\gwsynthesis\Dsi_test_pattern.vg |
Physical Constraints File | F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\DSI_Test_Pattern_1nr9\fpga_proj\src\dsi_test.cst |
Timing Constraint File | F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\DSI_Test_Pattern_1nr9\fpga_proj\src\dsi_test.sdc |
Tool Version | V1.9.9.01 (64-bit) |
Part Number | GW1NR-LV9MG100PC7/I6 |
Device | GW1NR-9 |
Device Version | C |
Created Time | Wed Mar 6 09:56:51 2024 |
Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved. |
Timing Summaries
STA Tool Run Summary:
Setup Delay Model | Slow 1.14V 85C C7/I6 |
Hold Delay Model | Fast 1.26V 0C C7/I6 |
Numbers of Paths Analyzed | 7092 |
Numbers of Endpoints Analyzed | 4481 |
Numbers of Falling Endpoints | 0 |
Numbers of Setup Violated Endpoints | 0 |
Numbers of Hold Violated Endpoints | 0 |
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Objects |
---|---|---|---|---|---|---|---|---|
clk_50 | Base | 20.000 | 50.000 | 0.000 | 10.000 | OSC_50M | ||
pixel_clk | Generated | 7.059 | 141.667 | 0.000 | 3.529 | OSC_50M | clk_50 | pixel_clk |
byte_clk | Generated | 18.824 | 53.125 | 0.000 | 9.412 | OSC_50M | clk_50 | byte_clk |
tck_pad_i | Base | 50.000 | 20.000 | 0.000 | 25.000 | tck_ibuf/I | ||
u_pll/rpll_inst/CLKOUT.default_gen_clk | Generated | 2.353 | 425.000 | 0.000 | 1.176 | OSC_50M_ibuf/I | clk_50 | u_pll/rpll_inst/CLKOUT |
u_pll/rpll_inst/CLKOUTP.default_gen_clk | Generated | 2.353 | 425.000 | 0.588 | 1.765 | OSC_50M_ibuf/I | clk_50 | u_pll/rpll_inst/CLKOUTP |
Max Frequency Summary:
NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | pixel_clk | 141.667(MHz) | 143.652(MHz) | 7 | TOP |
2 | byte_clk | 53.125(MHz) | 84.527(MHz) | 7 | TOP |
3 | tck_pad_i | 20.000(MHz) | 74.091(MHz) | 8 | TOP |
No timing paths to get frequency of clk_50!
No timing paths to get frequency of u_pll/rpll_inst/CLKOUT.default_gen_clk!
No timing paths to get frequency of u_pll/rpll_inst/CLKOUTP.default_gen_clk!
Total Negative Slack Summary:
Clock Name | Analysis Type | Endpoints TNS | Number of Endpoints |
---|---|---|---|
clk_50 | Setup | 0.000 | 0 |
clk_50 | Hold | 0.000 | 0 |
pixel_clk | Setup | 0.000 | 0 |
pixel_clk | Hold | 0.000 | 0 |
byte_clk | Setup | 0.000 | 0 |
byte_clk | Hold | 0.000 | 0 |
tck_pad_i | Setup | 0.000 | 0 |
tck_pad_i | Hold | 0.000 | 0 |
u_pll/rpll_inst/CLKOUT.default_gen_clk | Setup | 0.000 | 0 |
u_pll/rpll_inst/CLKOUT.default_gen_clk | Hold | 0.000 | 0 |
u_pll/rpll_inst/CLKOUTP.default_gen_clk | Setup | 0.000 | 0 |
u_pll/rpll_inst/CLKOUTP.default_gen_clk | Hold | 0.000 | 0 |
Timing Details
Path Slacks Table:
Setup Paths Table
Setup Paths Table[1]:
Report Command:report_timing -setup -from_clock [get_clocks {pixel_clk}] -max_paths 20 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 0.098 | u_p2b/u_p2b_0/u_mid_buf/rRPtrWsync_2_s0/Q | u_p2b/u_p2b_0/u_mid_buf/rFull_s0/D | pixel_clk:[R] | pixel_clk:[R] | 7.059 | 0.000 | 6.665 |
2 | 0.915 | u_test_gen/De_hcnt_3_s3/Q | u_test_gen/Data_tmp_13_s1/D | pixel_clk:[R] | pixel_clk:[R] | 7.059 | 0.000 | 5.848 |
3 | 0.976 | u_test_gen/De_hcnt_3_s3/Q | u_test_gen/Data_tmp_2_s1/D | pixel_clk:[R] | pixel_clk:[R] | 7.059 | 0.000 | 5.786 |
4 | 0.976 | u_test_gen/De_hcnt_3_s3/Q | u_test_gen/Data_tmp_11_s1/D | pixel_clk:[R] | pixel_clk:[R] | 7.059 | 0.000 | 5.786 |
5 | 1.052 | u_test_gen/De_hcnt_3_s3/Q | u_test_gen/Data_tmp_15_s1/D | pixel_clk:[R] | pixel_clk:[R] | 7.059 | 0.000 | 5.711 |
6 | 1.164 | u_test_gen/De_hcnt_3_s3/Q | u_test_gen/Data_tmp_0_s1/D | pixel_clk:[R] | pixel_clk:[R] | 7.059 | 0.000 | 5.598 |
7 | 1.164 | u_test_gen/De_hcnt_3_s3/Q | u_test_gen/Data_tmp_1_s1/D | pixel_clk:[R] | pixel_clk:[R] | 7.059 | 0.000 | 5.598 |
8 | 1.164 | u_test_gen/De_hcnt_3_s3/Q | u_test_gen/Data_tmp_9_s1/D | pixel_clk:[R] | pixel_clk:[R] | 7.059 | 0.000 | 5.598 |
9 | 1.176 | u_test_gen/De_hcnt_3_s3/Q | u_test_gen/Data_tmp_10_s1/D | pixel_clk:[R] | pixel_clk:[R] | 7.059 | 0.000 | 5.586 |
10 | 1.176 | u_test_gen/De_hcnt_3_s3/Q | u_test_gen/Data_tmp_12_s1/D | pixel_clk:[R] | pixel_clk:[R] | 7.059 | 0.000 | 5.586 |
11 | 1.301 | u_test_gen/De_hcnt_3_s3/Q | u_test_gen/Data_tmp_7_s1/D | pixel_clk:[R] | pixel_clk:[R] | 7.059 | 0.000 | 5.461 |
12 | 1.314 | u_test_gen/De_hcnt_0_s3/Q | u_test_gen/Net_h_trig_s0/D | pixel_clk:[R] | pixel_clk:[R] | 7.059 | 0.000 | 5.449 |
13 | 1.329 | u_test_gen/H_cnt_7_s0/Q | u_test_gen/V_cnt_4_s1/D | pixel_clk:[R] | pixel_clk:[R] | 7.059 | 0.000 | 5.433 |
14 | 1.329 | u_test_gen/H_cnt_7_s0/Q | u_test_gen/V_cnt_5_s1/D | pixel_clk:[R] | pixel_clk:[R] | 7.059 | 0.000 | 5.433 |
15 | 1.340 | u_test_gen/H_cnt_7_s0/Q | u_test_gen/V_cnt_6_s1/D | pixel_clk:[R] | pixel_clk:[R] | 7.059 | 0.000 | 5.422 |
16 | 1.340 | u_test_gen/H_cnt_7_s0/Q | u_test_gen/V_cnt_8_s1/D | pixel_clk:[R] | pixel_clk:[R] | 7.059 | 0.000 | 5.422 |
17 | 1.379 | u_test_gen/H_cnt_7_s0/Q | u_test_gen/V_cnt_9_s1/D | pixel_clk:[R] | pixel_clk:[R] | 7.059 | 0.000 | 5.383 |
18 | 1.379 | u_test_gen/H_cnt_7_s0/Q | u_test_gen/V_cnt_10_s1/D | pixel_clk:[R] | pixel_clk:[R] | 7.059 | 0.000 | 5.383 |
19 | 1.411 | u_test_gen/De_hcnt_3_s3/Q | u_test_gen/Data_tmp_8_s1/D | pixel_clk:[R] | pixel_clk:[R] | 7.059 | 0.000 | 5.352 |
20 | 1.444 | u_test_gen/De_hcnt_3_s3/Q | u_test_gen/Data_tmp_20_s1/D | pixel_clk:[R] | pixel_clk:[R] | 7.059 | 0.000 | 5.319 |
Setup Paths Table[2]:
Report Command:report_timing -setup -from_clock [get_clocks {byte_clk}] -max_paths 20 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 6.993 | u_dsi_tx/u_tx/u_dsi_tx/rLpCrc_4_s1/Q | u_dsi_tx/u_tx/u_dsi_tx/rLpCrc_15_s1/D | byte_clk:[R] | byte_clk:[R] | 18.824 | 0.000 | 11.534 |
2 | 6.994 | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[28] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_9_s1/D | byte_clk:[R] | byte_clk:[R] | 18.824 | 0.000 | 11.533 |
3 | 7.465 | u_dsi_tx/u_tx/u_dsi_tx/rCrcData_11_s0/Q | u_dsi_tx/u_tx/u_dsi_tx/rLpCrc_11_s1/D | byte_clk:[R] | byte_clk:[R] | 18.824 | 0.000 | 11.063 |
4 | 7.482 | u_dsi_tx/u_tx/u_dsi_tx/rCrcData_5_s0/Q | u_dsi_tx/u_tx/u_dsi_tx/rLpCrc_13_s1/D | byte_clk:[R] | byte_clk:[R] | 18.824 | 0.000 | 11.045 |
5 | 7.859 | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[28] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_8_s1/D | byte_clk:[R] | byte_clk:[R] | 18.824 | 0.000 | 10.668 |
6 | 7.928 | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[28] | hs_data1_r_11_s0/D | byte_clk:[R] | byte_clk:[R] | 18.824 | 0.000 | 10.599 |
7 | 7.966 | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[28] | hs_data3_r_8_s0/D | byte_clk:[R] | byte_clk:[R] | 18.824 | 0.000 | 10.561 |
8 | 8.004 | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[28] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rWrOffset_7_s1/D | byte_clk:[R] | byte_clk:[R] | 18.824 | 0.000 | 10.523 |
9 | 8.084 | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[28] | hs_data3_r_14_s0/D | byte_clk:[R] | byte_clk:[R] | 18.824 | 0.000 | 10.444 |
10 | 8.088 | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[28] | hs_data1_r_14_s0/D | byte_clk:[R] | byte_clk:[R] | 18.824 | 0.000 | 10.439 |
11 | 8.103 | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[28] | hs_data3_r_15_s0/D | byte_clk:[R] | byte_clk:[R] | 18.824 | 0.000 | 10.424 |
12 | 8.125 | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[28] | hs_data1_r_9_s0/D | byte_clk:[R] | byte_clk:[R] | 18.824 | 0.000 | 10.402 |
13 | 8.140 | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[28] | hs_data2_r_13_s0/D | byte_clk:[R] | byte_clk:[R] | 18.824 | 0.000 | 10.387 |
14 | 8.161 | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[28] | hs_data1_r_12_s0/D | byte_clk:[R] | byte_clk:[R] | 18.824 | 0.000 | 10.366 |
15 | 8.161 | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[28] | hs_data0_r_15_s0/D | byte_clk:[R] | byte_clk:[R] | 18.824 | 0.000 | 10.366 |
16 | 8.161 | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[28] | hs_data1_r_13_s0/D | byte_clk:[R] | byte_clk:[R] | 18.824 | 0.000 | 10.366 |
17 | 8.170 | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[28] | u_tx_phy/DPHY_TX_INST/u_oserx4x8/U5_OSER16_1/D13 | byte_clk:[R] | byte_clk:[R] | 18.824 | 0.000 | 10.620 |
18 | 8.217 | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[28] | hs_data3_r_13_s0/D | byte_clk:[R] | byte_clk:[R] | 18.824 | 0.000 | 10.310 |
19 | 8.250 | u_dsi_tx/u_tx/u_dsi_tx/rCrcData_36_s0/Q | u_dsi_tx/u_tx/u_dsi_tx/rLpCrc_4_s1/D | byte_clk:[R] | byte_clk:[R] | 18.824 | 0.000 | 10.277 |
20 | 8.256 | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[28] | hs_data3_r_9_s0/D | byte_clk:[R] | byte_clk:[R] | 18.824 | 0.000 | 10.271 |
Hold Paths Table
Hold Paths Table[1]:
Report Command:report_timing -hold -from_clock [get_clocks {pixel_clk}] -max_paths 20 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 0.407 | u_p2b/u_p2b_0/mid_data_28_s1/Q | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mSsram_mSsram_0_7_s/DI[0] | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.000 | 0.418 |
2 | 0.407 | u_p2b/u_p2b_0/mid_data_20_s1/Q | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mSsram_mSsram_0_5_s/DI[0] | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.000 | 0.418 |
3 | 0.411 | u_p2b/u_p2b_0/u_mid_buf/rRstWsync_s0/Q | u_p2b/u_p2b_0/u_mid_buf/rWrRst_s0/CE | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.000 | 0.422 |
4 | 0.524 | u_p2b/u_p2b_0/u_mid_buf/rWPtrGray_0_s1/Q | u_p2b/u_p2b_0/u_mid_buf/rWPtrGray_0_s1/D | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.000 | 0.524 |
5 | 0.524 | u_test_gen/Color_trig_num_4_s3/Q | u_test_gen/Color_trig_num_4_s3/D | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.000 | 0.524 |
6 | 0.524 | u_test_gen/De_vcnt_11_s1/Q | u_test_gen/De_vcnt_11_s1/D | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.000 | 0.524 |
7 | 0.524 | u_test_gen/H_cnt_3_s0/Q | u_test_gen/H_cnt_3_s0/D | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.000 | 0.524 |
8 | 0.524 | u_test_gen/H_cnt_5_s0/Q | u_test_gen/H_cnt_5_s0/D | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.000 | 0.524 |
9 | 0.524 | frame_led_s1/Q | frame_led_s1/D | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.000 | 0.524 |
10 | 0.524 | frame_3_s0/Q | frame_3_s0/D | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.000 | 0.524 |
11 | 0.525 | u_test_gen/Color_cnt_1_s3/Q | u_test_gen/Color_cnt_1_s3/D | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.000 | 0.525 |
12 | 0.525 | u_test_gen/Color_trig_num_8_s3/Q | u_test_gen/Color_trig_num_8_s3/D | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.000 | 0.525 |
13 | 0.525 | u_test_gen/De_hcnt_3_s3/Q | u_test_gen/De_hcnt_3_s3/D | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.000 | 0.525 |
14 | 0.525 | u_test_gen/De_vcnt_1_s1/Q | u_test_gen/De_vcnt_1_s1/D | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.000 | 0.525 |
15 | 0.525 | u_test_gen/De_vcnt_5_s1/Q | u_test_gen/De_vcnt_5_s1/D | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.000 | 0.525 |
16 | 0.525 | u_test_gen/De_vcnt_7_s1/Q | u_test_gen/De_vcnt_7_s1/D | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.000 | 0.525 |
17 | 0.525 | u_test_gen/De_vcnt_10_s1/Q | u_test_gen/De_vcnt_10_s1/D | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.000 | 0.525 |
18 | 0.525 | u_test_gen/H_cnt_0_s0/Q | u_test_gen/H_cnt_0_s0/D | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.000 | 0.525 |
19 | 0.525 | u_test_gen/H_cnt_4_s0/Q | u_test_gen/H_cnt_4_s0/D | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.000 | 0.525 |
20 | 0.525 | u_test_gen/H_cnt_9_s0/Q | u_test_gen/H_cnt_9_s0/D | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.000 | 0.525 |
Hold Paths Table[2]:
Report Command:report_timing -hold -from_clock [get_clocks {byte_clk}] -max_paths 20 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 0.355 | u_la0_top/u_ao_mem_ctrl/data_reg_20_s0/Q | u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[2] | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.418 |
2 | 0.355 | u_la0_top/u_ao_mem_ctrl/data_reg_11_s0/Q | u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[11] | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.418 |
3 | 0.355 | u_dsi_tx/u_tx/u_dsi_tx/rHsd_32_s0/Q | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_0_s/DI[32] | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.418 |
4 | 0.355 | u_dsi_tx/u_tx/u_dsi_tx/rHsd_1_s0/Q | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_0_s/DI[1] | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.418 |
5 | 0.384 | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/rHsDataEn_s0/Q | u_la0_top/u_ao_match_0/trig_dly_in_0_s0/D | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.137 | 0.247 |
6 | 0.384 | hs_data0_r_15_s0/Q | u_la0_top/u_ao_mem_ctrl/data_reg_dly_70_s0/D | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.137 | 0.247 |
7 | 0.384 | lp_data0_r_0_s0/Q | u_la0_top/u_ao_mem_ctrl/data_reg_dly_0_s0/D | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.137 | 0.247 |
8 | 0.384 | lp_data0_r_1_s0/Q | u_la0_top/u_ao_mem_ctrl/data_reg_dly_1_s0/D | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.137 | 0.247 |
9 | 0.384 | lp_clk_r_0_s0/Q | u_la0_top/u_ao_mem_ctrl/data_reg_dly_2_s0/D | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.137 | 0.247 |
10 | 0.384 | lp_clk_r_1_s0/Q | u_la0_top/u_ao_mem_ctrl/data_reg_dly_3_s0/D | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.137 | 0.247 |
11 | 0.384 | u_p2b/u_p2b_0/GEN_FOR_I[1].u_pulse_dly/rPulse_s0/Q | u_la0_top/u_ao_mem_ctrl/data_reg_dly_4_s0/D | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.137 | 0.247 |
12 | 0.384 | hs_data_en_r_s0/Q | u_la0_top/u_ao_mem_ctrl/data_reg_dly_5_s0/D | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.137 | 0.247 |
13 | 0.384 | hs_clk_en_r_s0/Q | u_la0_top/u_ao_mem_ctrl/data_reg_dly_6_s0/D | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.137 | 0.247 |
14 | 0.384 | hs_data3_r_0_s0/Q | u_la0_top/u_ao_mem_ctrl/data_reg_dly_7_s0/D | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.137 | 0.247 |
15 | 0.384 | hs_data3_r_1_s0/Q | u_la0_top/u_ao_mem_ctrl/data_reg_dly_8_s0/D | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.137 | 0.247 |
16 | 0.384 | hs_data3_r_2_s0/Q | u_la0_top/u_ao_mem_ctrl/data_reg_dly_9_s0/D | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.137 | 0.247 |
17 | 0.384 | hs_data3_r_3_s0/Q | u_la0_top/u_ao_mem_ctrl/data_reg_dly_10_s0/D | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.137 | 0.247 |
18 | 0.384 | hs_data3_r_4_s0/Q | u_la0_top/u_ao_mem_ctrl/data_reg_dly_11_s0/D | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.137 | 0.247 |
19 | 0.384 | hs_data3_r_5_s0/Q | u_la0_top/u_ao_mem_ctrl/data_reg_dly_12_s0/D | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.137 | 0.247 |
20 | 0.384 | hs_data3_r_6_s0/Q | u_la0_top/u_ao_mem_ctrl/data_reg_dly_13_s0/D | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.137 | 0.247 |
Recovery Paths Table
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 16.141 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR | byte_clk:[R] | byte_clk:[R] | 18.824 | 0.000 | 2.650 |
2 | 16.346 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR | byte_clk:[R] | byte_clk:[R] | 18.824 | 0.000 | 2.445 |
3 | 16.346 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR | byte_clk:[R] | byte_clk:[R] | 18.824 | 0.000 | 2.445 |
4 | 16.346 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR | byte_clk:[R] | byte_clk:[R] | 18.824 | 0.000 | 2.445 |
5 | 16.346 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR | byte_clk:[R] | byte_clk:[R] | 18.824 | 0.000 | 2.445 |
6 | 16.346 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR | byte_clk:[R] | byte_clk:[R] | 18.824 | 0.000 | 2.445 |
7 | 16.606 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR | byte_clk:[R] | byte_clk:[R] | 18.824 | 0.000 | 2.186 |
8 | 16.606 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR | byte_clk:[R] | byte_clk:[R] | 18.824 | 0.000 | 2.186 |
9 | 16.610 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR | byte_clk:[R] | byte_clk:[R] | 18.824 | 0.000 | 2.181 |
10 | 16.610 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR | byte_clk:[R] | byte_clk:[R] | 18.824 | 0.000 | 2.181 |
11 | 16.610 | u_la0_top/rst_ao_s0/Q | u_la0_top/internal_reg_start_syn_0_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 18.824 | 0.000 | 2.181 |
12 | 16.851 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR | byte_clk:[R] | byte_clk:[R] | 18.824 | 0.000 | 1.941 |
13 | 16.851 | u_la0_top/rst_ao_s0/Q | u_la0_top/capture_window_sel_4_s1/CLEAR | byte_clk:[R] | byte_clk:[R] | 18.824 | 0.000 | 1.941 |
14 | 16.851 | u_la0_top/rst_ao_s0/Q | u_la0_top/capture_window_sel_5_s1/CLEAR | byte_clk:[R] | byte_clk:[R] | 18.824 | 0.000 | 1.941 |
15 | 16.860 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET | byte_clk:[R] | byte_clk:[R] | 18.824 | 0.000 | 1.932 |
16 | 16.860 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR | byte_clk:[R] | byte_clk:[R] | 18.824 | 0.000 | 1.932 |
17 | 16.860 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR | byte_clk:[R] | byte_clk:[R] | 18.824 | 0.000 | 1.932 |
18 | 16.860 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR | byte_clk:[R] | byte_clk:[R] | 18.824 | 0.000 | 1.932 |
19 | 16.864 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_match_0/trig_dly_0_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 18.824 | 0.000 | 1.927 |
20 | 16.864 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 18.824 | 0.000 | 1.927 |
21 | 16.864 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR | byte_clk:[R] | byte_clk:[R] | 18.824 | 0.000 | 1.927 |
22 | 16.864 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR | byte_clk:[R] | byte_clk:[R] | 18.824 | 0.000 | 1.927 |
23 | 16.956 | u_la0_top/rst_ao_s0/Q | u_la0_top/capture_window_sel_6_s1/CLEAR | byte_clk:[R] | byte_clk:[R] | 18.824 | 0.000 | 1.835 |
24 | 16.956 | u_la0_top/rst_ao_s0/Q | u_la0_top/start_reg_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 18.824 | 0.000 | 1.835 |
25 | 16.956 | u_la0_top/rst_ao_s0/Q | u_la0_top/internal_reg_start_syn_1_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 18.824 | 0.000 | 1.835 |
Removal Paths Table
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 0.424 | u_la0_top/rst_ao_s0/Q | u_la0_top/capture_window_sel_8_s1/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.435 |
2 | 0.424 | u_la0_top/rst_ao_s0/Q | u_la0_top/triger_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.435 |
3 | 0.622 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.633 |
4 | 0.622 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.633 |
5 | 0.622 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.633 |
6 | 0.624 | u_la0_top/rst_ao_s0/Q | u_la0_top/capture_window_sel_7_s1/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.635 |
7 | 0.624 | u_la0_top/rst_ao_s0/Q | u_la0_top/capture_window_sel_9_s1/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.635 |
8 | 0.666 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.678 |
9 | 0.666 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.678 |
10 | 0.666 | u_la0_top/rst_ao_s0/Q | u_la0_top/triger_level_cnt_0_s3/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.678 |
11 | 0.667 | u_la0_top/rst_ao_s0/Q | u_la0_top/capture_end_dly_s0/PRESET | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.679 |
12 | 0.667 | u_la0_top/rst_ao_s0/Q | u_la0_top/internal_reg_start_dly_0_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.679 |
13 | 0.669 | u_la0_top/rst_ao_s0/Q | u_la0_top/trigger_seq_start_s1/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.680 |
14 | 0.830 | u_la0_top/rst_ao_s0/Q | u_la0_top/internal_reg_start_dly_1_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.841 |
15 | 0.830 | u_la0_top/rst_ao_s0/Q | u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.841 |
16 | 0.837 | u_la0_top/rst_ao_s0/Q | u_la0_top/capture_window_sel_2_s1/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.848 |
17 | 0.837 | u_la0_top/rst_ao_s0/Q | u_la0_top/capture_window_sel_3_s1/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.848 |
18 | 0.837 | u_la0_top/rst_ao_s0/Q | u_la0_top/triger_level_cnt_1_s1/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.848 |
19 | 0.876 | u_la0_top/rst_ao_s0/Q | u_la0_top/capture_window_sel_1_s1/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.887 |
20 | 0.878 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_match_0/match_sep_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.889 |
21 | 0.878 | u_la0_top/rst_ao_s0/Q | u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.889 |
22 | 0.881 | u_la0_top/rst_ao_s0/Q | u_la0_top/triger_level_cnt_2_s1/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.892 |
23 | 0.881 | u_la0_top/rst_ao_s0/Q | u_la0_top/triger_level_cnt_3_s1/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.892 |
24 | 1.030 | u_la0_top/rst_ao_s0/Q | u_la0_top/capture_window_sel_6_s1/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 1.041 |
25 | 1.030 | u_la0_top/rst_ao_s0/Q | u_la0_top/start_reg_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 1.041 |
Minimum Pulse Width Table:
Number | Slack | Actual Width | Required Width | Type | Clock | Objects |
---|---|---|---|---|---|---|
1 | 2.545 | 3.472 | 0.926 | Low Pulse Width | pixel_clk | run_cnt_25_s0 |
2 | 2.545 | 3.472 | 0.926 | Low Pulse Width | pixel_clk | run_cnt_24_s0 |
3 | 2.545 | 3.472 | 0.926 | Low Pulse Width | pixel_clk | run_cnt_8_s0 |
4 | 2.545 | 3.472 | 0.926 | Low Pulse Width | pixel_clk | u_test_gen/Gray_17_s0 |
5 | 2.545 | 3.472 | 0.926 | Low Pulse Width | pixel_clk | u_test_gen/Data_tmp_1_s1 |
6 | 2.545 | 3.472 | 0.926 | Low Pulse Width | pixel_clk | u_test_gen/De_hcnt_10_s1 |
7 | 2.545 | 3.472 | 0.926 | Low Pulse Width | pixel_clk | u_test_gen/De_vcnt_9_s1 |
8 | 2.545 | 3.472 | 0.926 | Low Pulse Width | pixel_clk | u_test_gen/De_vcnt_5_s1 |
9 | 2.545 | 3.472 | 0.926 | Low Pulse Width | pixel_clk | u_test_gen/De_vcnt_3_s1 |
10 | 2.545 | 3.472 | 0.926 | Low Pulse Width | pixel_clk | u_test_gen/De_vcnt_2_s1 |
Timing Report By Analysis Type:
Setup Analysis Report
Setup Analysis Report[1]:
Report Command:report_timing -setup -from_clock [get_clocks {pixel_clk}] -max_paths 20 -max_common_paths 1
Path1
Path Summary:
Slack | 0.098 |
Data Arrival Time | 6.846 |
Data Required Time | 6.943 |
From | u_p2b/u_p2b_0/u_mid_buf/rRPtrWsync_2_s0 |
To | u_p2b/u_p2b_0/u_mid_buf/rFull_s0 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 353 | PLL_R | u_pll/rpll_inst/CLKOUTD3 |
0.181 | 0.181 | tNET | RR | 1 | R7C10[2][B] | u_p2b/u_p2b_0/u_mid_buf/rRPtrWsync_2_s0/CLK |
0.520 | 0.340 | tC2Q | RF | 3 | R7C10[2][B] | u_p2b/u_p2b_0/u_mid_buf/rRPtrWsync_2_s0/Q |
1.726 | 1.205 | tNET | FF | 1 | R8C7[0][B] | u_p2b/u_p2b_0/u_mid_buf/wRPtrBinX_1_s0/I1 |
2.335 | 0.609 | tINS | FF | 3 | R8C7[0][B] | u_p2b/u_p2b_0/u_mid_buf/wRPtrBinX_1_s0/F |
2.939 | 0.604 | tNET | FF | 1 | R7C6[0][B] | u_p2b/u_p2b_0/u_mid_buf/wRPtrBinX_0_s0/I1 |
3.533 | 0.594 | tINS | FR | 1 | R7C6[0][B] | u_p2b/u_p2b_0/u_mid_buf/wRPtrBinX_0_s0/F |
3.844 | 0.310 | tNET | RR | 2 | R8C6[0][B] | u_p2b/u_p2b_0/u_mid_buf/n327_s0/I1 |
4.618 | 0.774 | tINS | RF | 1 | R8C6[0][B] | u_p2b/u_p2b_0/u_mid_buf/n327_s0/COUT |
4.618 | 0.000 | tNET | FF | 2 | R8C6[1][A] | u_p2b/u_p2b_0/u_mid_buf/n328_s0/CIN |
4.660 | 0.042 | tINS | FF | 1 | R8C6[1][A] | u_p2b/u_p2b_0/u_mid_buf/n328_s0/COUT |
4.660 | 0.000 | tNET | FF | 2 | R8C6[1][B] | u_p2b/u_p2b_0/u_mid_buf/n329_s0/CIN |
4.702 | 0.042 | tINS | FF | 1 | R8C6[1][B] | u_p2b/u_p2b_0/u_mid_buf/n329_s0/COUT |
4.702 | 0.000 | tNET | FF | 2 | R8C6[2][A] | u_p2b/u_p2b_0/u_mid_buf/n330_s0/CIN |
4.745 | 0.042 | tINS | FF | 1 | R8C6[2][A] | u_p2b/u_p2b_0/u_mid_buf/n330_s0/COUT |
5.166 | 0.421 | tNET | FF | 1 | R8C6[3][B] | u_p2b/u_p2b_0/u_mid_buf/n342_s4/I0 |
5.926 | 0.760 | tINS | FR | 1 | R8C6[3][B] | u_p2b/u_p2b_0/u_mid_buf/n342_s4/F |
6.237 | 0.310 | tNET | RR | 1 | R7C6[1][B] | u_p2b/u_p2b_0/u_mid_buf/n342_s0/I3 |
6.846 | 0.609 | tINS | RF | 1 | R7C6[1][B] | u_p2b/u_p2b_0/u_mid_buf/n342_s0/F |
6.846 | 0.000 | tNET | FF | 1 | R7C6[1][B] | u_p2b/u_p2b_0/u_mid_buf/rFull_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.059 | 7.059 | active clock edge time | ||||
7.059 | 0.000 | pixel_clk | ||||
7.059 | 0.000 | tCL | RR | 353 | PLL_R | u_pll/rpll_inst/CLKOUTD3 |
7.240 | 0.181 | tNET | RR | 1 | R7C6[1][B] | u_p2b/u_p2b_0/u_mid_buf/rFull_s0/CLK |
6.943 | -0.296 | tSu | 1 | R7C6[1][B] | u_p2b/u_p2b_0/u_mid_buf/rFull_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 7.059 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 3.474, 52.121%; route: 2.851, 42.783%; tC2Q: 0.340, 5.096% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Path2
Path Summary:
Slack | 0.915 |
Data Arrival Time | 6.028 |
Data Required Time | 6.943 |
From | u_test_gen/De_hcnt_3_s3 |
To | u_test_gen/Data_tmp_13_s1 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 353 | PLL_R | u_pll/rpll_inst/CLKOUTD3 |
0.181 | 0.181 | tNET | RR | 1 | R18C4[0][A] | u_test_gen/De_hcnt_3_s3/CLK |
0.520 | 0.340 | tC2Q | RF | 5 | R18C4[0][A] | u_test_gen/De_hcnt_3_s3/Q |
1.625 | 1.105 | tNET | FF | 1 | R22C6[0][A] | u_test_gen/n1245_s8/I2 |
2.088 | 0.463 | tINS | FR | 2 | R22C6[0][A] | u_test_gen/n1245_s8/F |
2.400 | 0.312 | tNET | RR | 1 | R23C6[2][B] | u_test_gen/n1245_s7/I1 |
3.009 | 0.609 | tINS | RF | 6 | R23C6[2][B] | u_test_gen/n1245_s7/F |
3.617 | 0.608 | tNET | FF | 1 | R24C8[0][B] | u_test_gen/n1245_s5/I1 |
4.081 | 0.464 | tINS | FF | 16 | R24C8[0][B] | u_test_gen/n1245_s5/F |
5.419 | 1.339 | tNET | FF | 1 | R21C5[0][A] | u_test_gen/n1233_s1/I2 |
6.028 | 0.609 | tINS | FF | 1 | R21C5[0][A] | u_test_gen/n1233_s1/F |
6.028 | 0.000 | tNET | FF | 1 | R21C5[0][A] | u_test_gen/Data_tmp_13_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.059 | 7.059 | active clock edge time | ||||
7.059 | 0.000 | pixel_clk | ||||
7.059 | 0.000 | tCL | RR | 353 | PLL_R | u_pll/rpll_inst/CLKOUTD3 |
7.240 | 0.181 | tNET | RR | 1 | R21C5[0][A] | u_test_gen/Data_tmp_13_s1/CLK |
6.943 | -0.296 | tSu | 1 | R21C5[0][A] | u_test_gen/Data_tmp_13_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 7.059 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 2.145, 36.685%; route: 3.363, 57.507%; tC2Q: 0.340, 5.808% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Path3
Path Summary:
Slack | 0.976 |
Data Arrival Time | 5.967 |
Data Required Time | 6.943 |
From | u_test_gen/De_hcnt_3_s3 |
To | u_test_gen/Data_tmp_2_s1 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 353 | PLL_R | u_pll/rpll_inst/CLKOUTD3 |
0.181 | 0.181 | tNET | RR | 1 | R18C4[0][A] | u_test_gen/De_hcnt_3_s3/CLK |
0.520 | 0.340 | tC2Q | RF | 5 | R18C4[0][A] | u_test_gen/De_hcnt_3_s3/Q |
1.625 | 1.105 | tNET | FF | 1 | R22C6[0][A] | u_test_gen/n1245_s8/I2 |
2.088 | 0.463 | tINS | FR | 2 | R22C6[0][A] | u_test_gen/n1245_s8/F |
2.400 | 0.312 | tNET | RR | 1 | R23C6[2][B] | u_test_gen/n1245_s7/I1 |
3.009 | 0.609 | tINS | RF | 6 | R23C6[2][B] | u_test_gen/n1245_s7/F |
3.617 | 0.608 | tNET | FF | 1 | R24C8[0][B] | u_test_gen/n1245_s5/I1 |
4.081 | 0.464 | tINS | FF | 16 | R24C8[0][B] | u_test_gen/n1245_s5/F |
5.202 | 1.122 | tNET | FF | 1 | R18C7[1][B] | u_test_gen/n1244_s1/I2 |
5.967 | 0.765 | tINS | FF | 1 | R18C7[1][B] | u_test_gen/n1244_s1/F |
5.967 | 0.000 | tNET | FF | 1 | R18C7[1][B] | u_test_gen/Data_tmp_2_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.059 | 7.059 | active clock edge time | ||||
7.059 | 0.000 | pixel_clk | ||||
7.059 | 0.000 | tCL | RR | 353 | PLL_R | u_pll/rpll_inst/CLKOUTD3 |
7.240 | 0.181 | tNET | RR | 1 | R18C7[1][B] | u_test_gen/Data_tmp_2_s1/CLK |
6.943 | -0.296 | tSu | 1 | R18C7[1][B] | u_test_gen/Data_tmp_2_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 7.059 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 2.301, 39.763%; route: 3.146, 54.367%; tC2Q: 0.340, 5.870% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Path4
Path Summary:
Slack | 0.976 |
Data Arrival Time | 5.967 |
Data Required Time | 6.943 |
From | u_test_gen/De_hcnt_3_s3 |
To | u_test_gen/Data_tmp_11_s1 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 353 | PLL_R | u_pll/rpll_inst/CLKOUTD3 |
0.181 | 0.181 | tNET | RR | 1 | R18C4[0][A] | u_test_gen/De_hcnt_3_s3/CLK |
0.520 | 0.340 | tC2Q | RF | 5 | R18C4[0][A] | u_test_gen/De_hcnt_3_s3/Q |
1.625 | 1.105 | tNET | FF | 1 | R22C6[0][A] | u_test_gen/n1245_s8/I2 |
2.088 | 0.463 | tINS | FR | 2 | R22C6[0][A] | u_test_gen/n1245_s8/F |
2.400 | 0.312 | tNET | RR | 1 | R23C6[2][B] | u_test_gen/n1245_s7/I1 |
3.009 | 0.609 | tINS | RF | 6 | R23C6[2][B] | u_test_gen/n1245_s7/F |
3.617 | 0.608 | tNET | FF | 1 | R24C8[0][B] | u_test_gen/n1245_s5/I1 |
4.081 | 0.464 | tINS | FF | 16 | R24C8[0][B] | u_test_gen/n1245_s5/F |
5.202 | 1.122 | tNET | FF | 1 | R18C7[0][B] | u_test_gen/n1235_s1/I2 |
5.967 | 0.765 | tINS | FF | 1 | R18C7[0][B] | u_test_gen/n1235_s1/F |
5.967 | 0.000 | tNET | FF | 1 | R18C7[0][B] | u_test_gen/Data_tmp_11_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.059 | 7.059 | active clock edge time | ||||
7.059 | 0.000 | pixel_clk | ||||
7.059 | 0.000 | tCL | RR | 353 | PLL_R | u_pll/rpll_inst/CLKOUTD3 |
7.240 | 0.181 | tNET | RR | 1 | R18C7[0][B] | u_test_gen/Data_tmp_11_s1/CLK |
6.943 | -0.296 | tSu | 1 | R18C7[0][B] | u_test_gen/Data_tmp_11_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 7.059 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 2.301, 39.763%; route: 3.146, 54.367%; tC2Q: 0.340, 5.870% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Path5
Path Summary:
Slack | 1.052 |
Data Arrival Time | 5.891 |
Data Required Time | 6.943 |
From | u_test_gen/De_hcnt_3_s3 |
To | u_test_gen/Data_tmp_15_s1 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 353 | PLL_R | u_pll/rpll_inst/CLKOUTD3 |
0.181 | 0.181 | tNET | RR | 1 | R18C4[0][A] | u_test_gen/De_hcnt_3_s3/CLK |
0.520 | 0.340 | tC2Q | RF | 5 | R18C4[0][A] | u_test_gen/De_hcnt_3_s3/Q |
1.625 | 1.105 | tNET | FF | 1 | R22C6[0][A] | u_test_gen/n1245_s8/I2 |
2.088 | 0.463 | tINS | FR | 2 | R22C6[0][A] | u_test_gen/n1245_s8/F |
2.400 | 0.312 | tNET | RR | 1 | R23C6[2][B] | u_test_gen/n1245_s7/I1 |
3.009 | 0.609 | tINS | RF | 6 | R23C6[2][B] | u_test_gen/n1245_s7/F |
3.617 | 0.608 | tNET | FF | 1 | R24C8[0][B] | u_test_gen/n1245_s5/I1 |
4.081 | 0.464 | tINS | FF | 16 | R24C8[0][B] | u_test_gen/n1245_s5/F |
5.077 | 0.996 | tNET | FF | 1 | R22C5[0][A] | u_test_gen/n1231_s1/I2 |
5.891 | 0.814 | tINS | FF | 1 | R22C5[0][A] | u_test_gen/n1231_s1/F |
5.891 | 0.000 | tNET | FF | 1 | R22C5[0][A] | u_test_gen/Data_tmp_15_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.059 | 7.059 | active clock edge time | ||||
7.059 | 0.000 | pixel_clk | ||||
7.059 | 0.000 | tCL | RR | 353 | PLL_R | u_pll/rpll_inst/CLKOUTD3 |
7.240 | 0.181 | tNET | RR | 1 | R22C5[0][A] | u_test_gen/Data_tmp_15_s1/CLK |
6.943 | -0.296 | tSu | 1 | R22C5[0][A] | u_test_gen/Data_tmp_15_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 7.059 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 2.350, 41.159%; route: 3.021, 52.893%; tC2Q: 0.340, 5.947% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Path6
Path Summary:
Slack | 1.164 |
Data Arrival Time | 5.779 |
Data Required Time | 6.943 |
From | u_test_gen/De_hcnt_3_s3 |
To | u_test_gen/Data_tmp_0_s1 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 353 | PLL_R | u_pll/rpll_inst/CLKOUTD3 |
0.181 | 0.181 | tNET | RR | 1 | R18C4[0][A] | u_test_gen/De_hcnt_3_s3/CLK |
0.520 | 0.340 | tC2Q | RF | 5 | R18C4[0][A] | u_test_gen/De_hcnt_3_s3/Q |
1.625 | 1.105 | tNET | FF | 1 | R22C6[0][A] | u_test_gen/n1245_s8/I2 |
2.088 | 0.463 | tINS | FR | 2 | R22C6[0][A] | u_test_gen/n1245_s8/F |
2.400 | 0.312 | tNET | RR | 1 | R23C6[2][B] | u_test_gen/n1245_s7/I1 |
3.009 | 0.609 | tINS | RF | 6 | R23C6[2][B] | u_test_gen/n1245_s7/F |
3.617 | 0.608 | tNET | FF | 1 | R24C8[0][B] | u_test_gen/n1245_s5/I1 |
4.081 | 0.464 | tINS | FF | 16 | R24C8[0][B] | u_test_gen/n1245_s5/F |
5.315 | 1.234 | tNET | FF | 1 | R18C6[1][A] | u_test_gen/n1246_s1/I2 |
5.779 | 0.464 | tINS | FF | 1 | R18C6[1][A] | u_test_gen/n1246_s1/F |
5.779 | 0.000 | tNET | FF | 1 | R18C6[1][A] | u_test_gen/Data_tmp_0_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.059 | 7.059 | active clock edge time | ||||
7.059 | 0.000 | pixel_clk | ||||
7.059 | 0.000 | tCL | RR | 353 | PLL_R | u_pll/rpll_inst/CLKOUTD3 |
7.240 | 0.181 | tNET | RR | 1 | R18C6[1][A] | u_test_gen/Data_tmp_0_s1/CLK |
6.943 | -0.296 | tSu | 1 | R18C6[1][A] | u_test_gen/Data_tmp_0_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 7.059 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 2.000, 35.725%; route: 3.259, 58.208%; tC2Q: 0.340, 6.067% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Path7
Path Summary:
Slack | 1.164 |
Data Arrival Time | 5.779 |
Data Required Time | 6.943 |
From | u_test_gen/De_hcnt_3_s3 |
To | u_test_gen/Data_tmp_1_s1 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 353 | PLL_R | u_pll/rpll_inst/CLKOUTD3 |
0.181 | 0.181 | tNET | RR | 1 | R18C4[0][A] | u_test_gen/De_hcnt_3_s3/CLK |
0.520 | 0.340 | tC2Q | RF | 5 | R18C4[0][A] | u_test_gen/De_hcnt_3_s3/Q |
1.625 | 1.105 | tNET | FF | 1 | R22C6[0][A] | u_test_gen/n1245_s8/I2 |
2.088 | 0.463 | tINS | FR | 2 | R22C6[0][A] | u_test_gen/n1245_s8/F |
2.400 | 0.312 | tNET | RR | 1 | R23C6[2][B] | u_test_gen/n1245_s7/I1 |
3.009 | 0.609 | tINS | RF | 6 | R23C6[2][B] | u_test_gen/n1245_s7/F |
3.617 | 0.608 | tNET | FF | 1 | R24C8[0][B] | u_test_gen/n1245_s5/I1 |
4.081 | 0.464 | tINS | FF | 16 | R24C8[0][B] | u_test_gen/n1245_s5/F |
5.315 | 1.234 | tNET | FF | 1 | R18C6[0][A] | u_test_gen/n1245_s2/I2 |
5.779 | 0.464 | tINS | FF | 1 | R18C6[0][A] | u_test_gen/n1245_s2/F |
5.779 | 0.000 | tNET | FF | 1 | R18C6[0][A] | u_test_gen/Data_tmp_1_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.059 | 7.059 | active clock edge time | ||||
7.059 | 0.000 | pixel_clk | ||||
7.059 | 0.000 | tCL | RR | 353 | PLL_R | u_pll/rpll_inst/CLKOUTD3 |
7.240 | 0.181 | tNET | RR | 1 | R18C6[0][A] | u_test_gen/Data_tmp_1_s1/CLK |
6.943 | -0.296 | tSu | 1 | R18C6[0][A] | u_test_gen/Data_tmp_1_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 7.059 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 2.000, 35.725%; route: 3.259, 58.208%; tC2Q: 0.340, 6.067% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Path8
Path Summary:
Slack | 1.164 |
Data Arrival Time | 5.779 |
Data Required Time | 6.943 |
From | u_test_gen/De_hcnt_3_s3 |
To | u_test_gen/Data_tmp_9_s1 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 353 | PLL_R | u_pll/rpll_inst/CLKOUTD3 |
0.181 | 0.181 | tNET | RR | 1 | R18C4[0][A] | u_test_gen/De_hcnt_3_s3/CLK |
0.520 | 0.340 | tC2Q | RF | 5 | R18C4[0][A] | u_test_gen/De_hcnt_3_s3/Q |
1.625 | 1.105 | tNET | FF | 1 | R22C6[0][A] | u_test_gen/n1245_s8/I2 |
2.088 | 0.463 | tINS | FR | 2 | R22C6[0][A] | u_test_gen/n1245_s8/F |
2.400 | 0.312 | tNET | RR | 1 | R23C6[2][B] | u_test_gen/n1245_s7/I1 |
3.009 | 0.609 | tINS | RF | 6 | R23C6[2][B] | u_test_gen/n1245_s7/F |
3.617 | 0.608 | tNET | FF | 1 | R24C8[0][B] | u_test_gen/n1245_s5/I1 |
4.081 | 0.464 | tINS | FF | 16 | R24C8[0][B] | u_test_gen/n1245_s5/F |
5.315 | 1.234 | tNET | FF | 1 | R18C6[1][B] | u_test_gen/n1237_s1/I2 |
5.779 | 0.464 | tINS | FF | 1 | R18C6[1][B] | u_test_gen/n1237_s1/F |
5.779 | 0.000 | tNET | FF | 1 | R18C6[1][B] | u_test_gen/Data_tmp_9_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.059 | 7.059 | active clock edge time | ||||
7.059 | 0.000 | pixel_clk | ||||
7.059 | 0.000 | tCL | RR | 353 | PLL_R | u_pll/rpll_inst/CLKOUTD3 |
7.240 | 0.181 | tNET | RR | 1 | R18C6[1][B] | u_test_gen/Data_tmp_9_s1/CLK |
6.943 | -0.296 | tSu | 1 | R18C6[1][B] | u_test_gen/Data_tmp_9_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 7.059 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 2.000, 35.725%; route: 3.259, 58.208%; tC2Q: 0.340, 6.067% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Path9
Path Summary:
Slack | 1.176 |
Data Arrival Time | 5.767 |
Data Required Time | 6.943 |
From | u_test_gen/De_hcnt_3_s3 |
To | u_test_gen/Data_tmp_10_s1 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 353 | PLL_R | u_pll/rpll_inst/CLKOUTD3 |
0.181 | 0.181 | tNET | RR | 1 | R18C4[0][A] | u_test_gen/De_hcnt_3_s3/CLK |
0.520 | 0.340 | tC2Q | RF | 5 | R18C4[0][A] | u_test_gen/De_hcnt_3_s3/Q |
1.625 | 1.105 | tNET | FF | 1 | R22C6[0][A] | u_test_gen/n1245_s8/I2 |
2.088 | 0.463 | tINS | FR | 2 | R22C6[0][A] | u_test_gen/n1245_s8/F |
2.400 | 0.312 | tNET | RR | 1 | R23C6[2][B] | u_test_gen/n1245_s7/I1 |
3.009 | 0.609 | tINS | RF | 6 | R23C6[2][B] | u_test_gen/n1245_s7/F |
3.617 | 0.608 | tNET | FF | 1 | R24C8[0][B] | u_test_gen/n1245_s5/I1 |
4.081 | 0.464 | tINS | FF | 16 | R24C8[0][B] | u_test_gen/n1245_s5/F |
4.953 | 0.872 | tNET | FF | 1 | R22C4[0][B] | u_test_gen/n1236_s2/I2 |
5.767 | 0.814 | tINS | FF | 1 | R22C4[0][B] | u_test_gen/n1236_s2/F |
5.767 | 0.000 | tNET | FF | 1 | R22C4[0][B] | u_test_gen/Data_tmp_10_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.059 | 7.059 | active clock edge time | ||||
7.059 | 0.000 | pixel_clk | ||||
7.059 | 0.000 | tCL | RR | 353 | PLL_R | u_pll/rpll_inst/CLKOUTD3 |
7.240 | 0.181 | tNET | RR | 1 | R22C4[0][B] | u_test_gen/Data_tmp_10_s1/CLK |
6.943 | -0.296 | tSu | 1 | R22C4[0][B] | u_test_gen/Data_tmp_10_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 7.059 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 2.350, 42.076%; route: 2.896, 51.845%; tC2Q: 0.340, 6.080% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Path10
Path Summary:
Slack | 1.176 |
Data Arrival Time | 5.767 |
Data Required Time | 6.943 |
From | u_test_gen/De_hcnt_3_s3 |
To | u_test_gen/Data_tmp_12_s1 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 353 | PLL_R | u_pll/rpll_inst/CLKOUTD3 |
0.181 | 0.181 | tNET | RR | 1 | R18C4[0][A] | u_test_gen/De_hcnt_3_s3/CLK |
0.520 | 0.340 | tC2Q | RF | 5 | R18C4[0][A] | u_test_gen/De_hcnt_3_s3/Q |
1.625 | 1.105 | tNET | FF | 1 | R22C6[0][A] | u_test_gen/n1245_s8/I2 |
2.088 | 0.463 | tINS | FR | 2 | R22C6[0][A] | u_test_gen/n1245_s8/F |
2.400 | 0.312 | tNET | RR | 1 | R23C6[2][B] | u_test_gen/n1245_s7/I1 |
3.009 | 0.609 | tINS | RF | 6 | R23C6[2][B] | u_test_gen/n1245_s7/F |
3.617 | 0.608 | tNET | FF | 1 | R24C8[0][B] | u_test_gen/n1245_s5/I1 |
4.081 | 0.464 | tINS | FF | 16 | R24C8[0][B] | u_test_gen/n1245_s5/F |
4.953 | 0.872 | tNET | FF | 1 | R22C4[0][A] | u_test_gen/n1234_s2/I2 |
5.767 | 0.814 | tINS | FF | 1 | R22C4[0][A] | u_test_gen/n1234_s2/F |
5.767 | 0.000 | tNET | FF | 1 | R22C4[0][A] | u_test_gen/Data_tmp_12_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.059 | 7.059 | active clock edge time | ||||
7.059 | 0.000 | pixel_clk | ||||
7.059 | 0.000 | tCL | RR | 353 | PLL_R | u_pll/rpll_inst/CLKOUTD3 |
7.240 | 0.181 | tNET | RR | 1 | R22C4[0][A] | u_test_gen/Data_tmp_12_s1/CLK |
6.943 | -0.296 | tSu | 1 | R22C4[0][A] | u_test_gen/Data_tmp_12_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 7.059 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 2.350, 42.076%; route: 2.896, 51.845%; tC2Q: 0.340, 6.080% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Path11
Path Summary:
Slack | 1.301 |
Data Arrival Time | 5.642 |
Data Required Time | 6.943 |
From | u_test_gen/De_hcnt_3_s3 |
To | u_test_gen/Data_tmp_7_s1 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 353 | PLL_R | u_pll/rpll_inst/CLKOUTD3 |
0.181 | 0.181 | tNET | RR | 1 | R18C4[0][A] | u_test_gen/De_hcnt_3_s3/CLK |
0.520 | 0.340 | tC2Q | RF | 5 | R18C4[0][A] | u_test_gen/De_hcnt_3_s3/Q |
1.625 | 1.105 | tNET | FF | 1 | R22C6[0][A] | u_test_gen/n1245_s8/I2 |
2.088 | 0.463 | tINS | FR | 2 | R22C6[0][A] | u_test_gen/n1245_s8/F |
2.400 | 0.312 | tNET | RR | 1 | R23C6[2][B] | u_test_gen/n1245_s7/I1 |
3.009 | 0.609 | tINS | RF | 6 | R23C6[2][B] | u_test_gen/n1245_s7/F |
3.617 | 0.608 | tNET | FF | 1 | R24C8[0][B] | u_test_gen/n1245_s5/I1 |
4.081 | 0.464 | tINS | FF | 16 | R24C8[0][B] | u_test_gen/n1245_s5/F |
4.827 | 0.747 | tNET | FF | 1 | R22C6[0][B] | u_test_gen/n1239_s2/I2 |
5.642 | 0.814 | tINS | FF | 1 | R22C6[0][B] | u_test_gen/n1239_s2/F |
5.642 | 0.000 | tNET | FF | 1 | R22C6[0][B] | u_test_gen/Data_tmp_7_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.059 | 7.059 | active clock edge time | ||||
7.059 | 0.000 | pixel_clk | ||||
7.059 | 0.000 | tCL | RR | 353 | PLL_R | u_pll/rpll_inst/CLKOUTD3 |
7.240 | 0.181 | tNET | RR | 1 | R22C6[0][B] | u_test_gen/Data_tmp_7_s1/CLK |
6.943 | -0.296 | tSu | 1 | R22C6[0][B] | u_test_gen/Data_tmp_7_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 7.059 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 2.350, 43.041%; route: 2.771, 50.740%; tC2Q: 0.340, 6.219% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Path12
Path Summary:
Slack | 1.314 |
Data Arrival Time | 5.629 |
Data Required Time | 6.943 |
From | u_test_gen/De_hcnt_0_s3 |
To | u_test_gen/Net_h_trig_s0 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 353 | PLL_R | u_pll/rpll_inst/CLKOUTD3 |
0.181 | 0.181 | tNET | RR | 1 | R18C4[1][B] | u_test_gen/De_hcnt_0_s3/CLK |
0.520 | 0.340 | tC2Q | RF | 7 | R18C4[1][B] | u_test_gen/De_hcnt_0_s3/Q |
1.869 | 1.348 | tNET | FF | 1 | R22C6[2][B] | u_test_gen/n501_s3/I0 |
2.332 | 0.464 | tINS | FF | 5 | R22C6[2][B] | u_test_gen/n501_s3/F |
2.941 | 0.608 | tNET | FF | 1 | R23C5[0][B] | u_test_gen/n498_s5/I0 |
3.727 | 0.786 | tINS | FR | 4 | R23C5[0][B] | u_test_gen/n498_s5/F |
4.042 | 0.315 | tNET | RR | 1 | R23C6[3][A] | u_test_gen/n849_s2/I3 |
4.505 | 0.463 | tINS | RR | 1 | R23C6[3][A] | u_test_gen/n849_s2/F |
4.815 | 0.310 | tNET | RR | 1 | R22C6[1][A] | u_test_gen/n849_s0/I2 |
5.629 | 0.814 | tINS | RF | 1 | R22C6[1][A] | u_test_gen/n849_s0/F |
5.629 | 0.000 | tNET | FF | 1 | R22C6[1][A] | u_test_gen/Net_h_trig_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.059 | 7.059 | active clock edge time | ||||
7.059 | 0.000 | pixel_clk | ||||
7.059 | 0.000 | tCL | RR | 353 | PLL_R | u_pll/rpll_inst/CLKOUTD3 |
7.240 | 0.181 | tNET | RR | 1 | R22C6[1][A] | u_test_gen/Net_h_trig_s0/CLK |
6.943 | -0.296 | tSu | 1 | R22C6[1][A] | u_test_gen/Net_h_trig_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 7.059 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 2.528, 46.388%; route: 2.582, 47.379%; tC2Q: 0.340, 6.233% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Path13
Path Summary:
Slack | 1.329 |
Data Arrival Time | 5.614 |
Data Required Time | 6.943 |
From | u_test_gen/H_cnt_7_s0 |
To | u_test_gen/V_cnt_4_s1 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 353 | PLL_R | u_pll/rpll_inst/CLKOUTD3 |
0.181 | 0.181 | tNET | RR | 1 | R18C8[2][A] | u_test_gen/H_cnt_7_s0/CLK |
0.520 | 0.340 | tC2Q | RF | 6 | R18C8[2][A] | u_test_gen/H_cnt_7_s0/Q |
1.484 | 0.963 | tNET | FF | 1 | R20C9[0][B] | u_test_gen/V_cnt_10_s6/I0 |
2.248 | 0.765 | tINS | FF | 1 | R20C9[0][B] | u_test_gen/V_cnt_10_s6/F |
2.252 | 0.004 | tNET | FF | 1 | R20C9[3][B] | u_test_gen/V_cnt_10_s3/I2 |
3.067 | 0.814 | tINS | FF | 24 | R20C9[3][B] | u_test_gen/V_cnt_10_s3/F |
3.694 | 0.627 | tNET | FF | 1 | R20C6[0][A] | u_test_gen/n63_s4/I3 |
4.158 | 0.464 | tINS | FF | 12 | R20C6[0][A] | u_test_gen/n63_s4/F |
4.800 | 0.642 | tNET | FF | 1 | R20C4[1][A] | u_test_gen/n70_s2/I0 |
5.614 | 0.814 | tINS | FF | 1 | R20C4[1][A] | u_test_gen/n70_s2/F |
5.614 | 0.000 | tNET | FF | 1 | R20C4[1][A] | u_test_gen/V_cnt_4_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.059 | 7.059 | active clock edge time | ||||
7.059 | 0.000 | pixel_clk | ||||
7.059 | 0.000 | tCL | RR | 353 | PLL_R | u_pll/rpll_inst/CLKOUTD3 |
7.240 | 0.181 | tNET | RR | 1 | R20C4[1][A] | u_test_gen/V_cnt_4_s1/CLK |
6.943 | -0.296 | tSu | 1 | R20C4[1][A] | u_test_gen/V_cnt_4_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 7.059 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 2.857, 52.590%; route: 2.236, 41.159%; tC2Q: 0.340, 6.251% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Path14
Path Summary:
Slack | 1.329 |
Data Arrival Time | 5.614 |
Data Required Time | 6.943 |
From | u_test_gen/H_cnt_7_s0 |
To | u_test_gen/V_cnt_5_s1 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 353 | PLL_R | u_pll/rpll_inst/CLKOUTD3 |
0.181 | 0.181 | tNET | RR | 1 | R18C8[2][A] | u_test_gen/H_cnt_7_s0/CLK |
0.520 | 0.340 | tC2Q | RF | 6 | R18C8[2][A] | u_test_gen/H_cnt_7_s0/Q |
1.484 | 0.963 | tNET | FF | 1 | R20C9[0][B] | u_test_gen/V_cnt_10_s6/I0 |
2.248 | 0.765 | tINS | FF | 1 | R20C9[0][B] | u_test_gen/V_cnt_10_s6/F |
2.252 | 0.004 | tNET | FF | 1 | R20C9[3][B] | u_test_gen/V_cnt_10_s3/I2 |
3.067 | 0.814 | tINS | FF | 24 | R20C9[3][B] | u_test_gen/V_cnt_10_s3/F |
3.694 | 0.627 | tNET | FF | 1 | R20C6[0][A] | u_test_gen/n63_s4/I3 |
4.158 | 0.464 | tINS | FF | 12 | R20C6[0][A] | u_test_gen/n63_s4/F |
4.800 | 0.642 | tNET | FF | 1 | R20C4[2][B] | u_test_gen/n69_s4/I0 |
5.614 | 0.814 | tINS | FF | 1 | R20C4[2][B] | u_test_gen/n69_s4/F |
5.614 | 0.000 | tNET | FF | 1 | R20C4[2][B] | u_test_gen/V_cnt_5_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.059 | 7.059 | active clock edge time | ||||
7.059 | 0.000 | pixel_clk | ||||
7.059 | 0.000 | tCL | RR | 353 | PLL_R | u_pll/rpll_inst/CLKOUTD3 |
7.240 | 0.181 | tNET | RR | 1 | R20C4[2][B] | u_test_gen/V_cnt_5_s1/CLK |
6.943 | -0.296 | tSu | 1 | R20C4[2][B] | u_test_gen/V_cnt_5_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 7.059 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 2.857, 52.590%; route: 2.236, 41.159%; tC2Q: 0.340, 6.251% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Path15
Path Summary:
Slack | 1.340 |
Data Arrival Time | 5.603 |
Data Required Time | 6.943 |
From | u_test_gen/H_cnt_7_s0 |
To | u_test_gen/V_cnt_6_s1 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 353 | PLL_R | u_pll/rpll_inst/CLKOUTD3 |
0.181 | 0.181 | tNET | RR | 1 | R18C8[2][A] | u_test_gen/H_cnt_7_s0/CLK |
0.520 | 0.340 | tC2Q | RF | 6 | R18C8[2][A] | u_test_gen/H_cnt_7_s0/Q |
1.484 | 0.963 | tNET | FF | 1 | R20C9[0][B] | u_test_gen/V_cnt_10_s6/I0 |
2.248 | 0.765 | tINS | FF | 1 | R20C9[0][B] | u_test_gen/V_cnt_10_s6/F |
2.252 | 0.004 | tNET | FF | 1 | R20C9[3][B] | u_test_gen/V_cnt_10_s3/I2 |
3.067 | 0.814 | tINS | FF | 24 | R20C9[3][B] | u_test_gen/V_cnt_10_s3/F |
3.694 | 0.627 | tNET | FF | 1 | R20C6[0][A] | u_test_gen/n63_s4/I3 |
4.158 | 0.464 | tINS | FF | 12 | R20C6[0][A] | u_test_gen/n63_s4/F |
4.789 | 0.631 | tNET | FF | 1 | R20C5[1][A] | u_test_gen/n68_s2/I0 |
5.603 | 0.814 | tINS | FF | 1 | R20C5[1][A] | u_test_gen/n68_s2/F |
5.603 | 0.000 | tNET | FF | 1 | R20C5[1][A] | u_test_gen/V_cnt_6_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.059 | 7.059 | active clock edge time | ||||
7.059 | 0.000 | pixel_clk | ||||
7.059 | 0.000 | tCL | RR | 353 | PLL_R | u_pll/rpll_inst/CLKOUTD3 |
7.240 | 0.181 | tNET | RR | 1 | R20C5[1][A] | u_test_gen/V_cnt_6_s1/CLK |
6.943 | -0.296 | tSu | 1 | R20C5[1][A] | u_test_gen/V_cnt_6_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 7.059 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 2.857, 52.694%; route: 2.226, 41.043%; tC2Q: 0.340, 6.263% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Path16
Path Summary:
Slack | 1.340 |
Data Arrival Time | 5.603 |
Data Required Time | 6.943 |
From | u_test_gen/H_cnt_7_s0 |
To | u_test_gen/V_cnt_8_s1 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 353 | PLL_R | u_pll/rpll_inst/CLKOUTD3 |
0.181 | 0.181 | tNET | RR | 1 | R18C8[2][A] | u_test_gen/H_cnt_7_s0/CLK |
0.520 | 0.340 | tC2Q | RF | 6 | R18C8[2][A] | u_test_gen/H_cnt_7_s0/Q |
1.484 | 0.963 | tNET | FF | 1 | R20C9[0][B] | u_test_gen/V_cnt_10_s6/I0 |
2.248 | 0.765 | tINS | FF | 1 | R20C9[0][B] | u_test_gen/V_cnt_10_s6/F |
2.252 | 0.004 | tNET | FF | 1 | R20C9[3][B] | u_test_gen/V_cnt_10_s3/I2 |
3.067 | 0.814 | tINS | FF | 24 | R20C9[3][B] | u_test_gen/V_cnt_10_s3/F |
3.694 | 0.627 | tNET | FF | 1 | R20C6[0][A] | u_test_gen/n63_s4/I3 |
4.158 | 0.464 | tINS | FF | 12 | R20C6[0][A] | u_test_gen/n63_s4/F |
4.789 | 0.631 | tNET | FF | 1 | R20C5[2][B] | u_test_gen/n66_s2/I2 |
5.603 | 0.814 | tINS | FF | 1 | R20C5[2][B] | u_test_gen/n66_s2/F |
5.603 | 0.000 | tNET | FF | 1 | R20C5[2][B] | u_test_gen/V_cnt_8_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.059 | 7.059 | active clock edge time | ||||
7.059 | 0.000 | pixel_clk | ||||
7.059 | 0.000 | tCL | RR | 353 | PLL_R | u_pll/rpll_inst/CLKOUTD3 |
7.240 | 0.181 | tNET | RR | 1 | R20C5[2][B] | u_test_gen/V_cnt_8_s1/CLK |
6.943 | -0.296 | tSu | 1 | R20C5[2][B] | u_test_gen/V_cnt_8_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 7.059 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 2.857, 52.694%; route: 2.226, 41.043%; tC2Q: 0.340, 6.263% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Path17
Path Summary:
Slack | 1.379 |
Data Arrival Time | 5.564 |
Data Required Time | 6.943 |
From | u_test_gen/H_cnt_7_s0 |
To | u_test_gen/V_cnt_9_s1 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 353 | PLL_R | u_pll/rpll_inst/CLKOUTD3 |
0.181 | 0.181 | tNET | RR | 1 | R18C8[2][A] | u_test_gen/H_cnt_7_s0/CLK |
0.520 | 0.340 | tC2Q | RF | 6 | R18C8[2][A] | u_test_gen/H_cnt_7_s0/Q |
1.484 | 0.963 | tNET | FF | 1 | R20C9[0][B] | u_test_gen/V_cnt_10_s6/I0 |
2.248 | 0.765 | tINS | FF | 1 | R20C9[0][B] | u_test_gen/V_cnt_10_s6/F |
2.252 | 0.004 | tNET | FF | 1 | R20C9[3][B] | u_test_gen/V_cnt_10_s3/I2 |
3.067 | 0.814 | tINS | FF | 24 | R20C9[3][B] | u_test_gen/V_cnt_10_s3/F |
3.694 | 0.627 | tNET | FF | 1 | R20C6[0][A] | u_test_gen/n63_s4/I3 |
4.158 | 0.464 | tINS | FF | 12 | R20C6[0][A] | u_test_gen/n63_s4/F |
4.800 | 0.642 | tNET | FF | 1 | R20C4[0][A] | u_test_gen/n65_s2/I0 |
5.564 | 0.765 | tINS | FF | 1 | R20C4[0][A] | u_test_gen/n65_s2/F |
5.564 | 0.000 | tNET | FF | 1 | R20C4[0][A] | u_test_gen/V_cnt_9_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.059 | 7.059 | active clock edge time | ||||
7.059 | 0.000 | pixel_clk | ||||
7.059 | 0.000 | tCL | RR | 353 | PLL_R | u_pll/rpll_inst/CLKOUTD3 |
7.240 | 0.181 | tNET | RR | 1 | R20C4[0][A] | u_test_gen/V_cnt_9_s1/CLK |
6.943 | -0.296 | tSu | 1 | R20C4[0][A] | u_test_gen/V_cnt_9_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 7.059 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 2.808, 52.153%; route: 2.236, 41.538%; tC2Q: 0.340, 6.309% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Path18
Path Summary:
Slack | 1.379 |
Data Arrival Time | 5.564 |
Data Required Time | 6.943 |
From | u_test_gen/H_cnt_7_s0 |
To | u_test_gen/V_cnt_10_s1 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 353 | PLL_R | u_pll/rpll_inst/CLKOUTD3 |
0.181 | 0.181 | tNET | RR | 1 | R18C8[2][A] | u_test_gen/H_cnt_7_s0/CLK |
0.520 | 0.340 | tC2Q | RF | 6 | R18C8[2][A] | u_test_gen/H_cnt_7_s0/Q |
1.484 | 0.963 | tNET | FF | 1 | R20C9[0][B] | u_test_gen/V_cnt_10_s6/I0 |
2.248 | 0.765 | tINS | FF | 1 | R20C9[0][B] | u_test_gen/V_cnt_10_s6/F |
2.252 | 0.004 | tNET | FF | 1 | R20C9[3][B] | u_test_gen/V_cnt_10_s3/I2 |
3.067 | 0.814 | tINS | FF | 24 | R20C9[3][B] | u_test_gen/V_cnt_10_s3/F |
3.694 | 0.627 | tNET | FF | 1 | R20C6[0][A] | u_test_gen/n63_s4/I3 |
4.158 | 0.464 | tINS | FF | 12 | R20C6[0][A] | u_test_gen/n63_s4/F |
4.800 | 0.642 | tNET | FF | 1 | R20C4[0][B] | u_test_gen/n64_s3/I0 |
5.564 | 0.765 | tINS | FF | 1 | R20C4[0][B] | u_test_gen/n64_s3/F |
5.564 | 0.000 | tNET | FF | 1 | R20C4[0][B] | u_test_gen/V_cnt_10_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.059 | 7.059 | active clock edge time | ||||
7.059 | 0.000 | pixel_clk | ||||
7.059 | 0.000 | tCL | RR | 353 | PLL_R | u_pll/rpll_inst/CLKOUTD3 |
7.240 | 0.181 | tNET | RR | 1 | R20C4[0][B] | u_test_gen/V_cnt_10_s1/CLK |
6.943 | -0.296 | tSu | 1 | R20C4[0][B] | u_test_gen/V_cnt_10_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 7.059 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 2.808, 52.153%; route: 2.236, 41.538%; tC2Q: 0.340, 6.309% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Path19
Path Summary:
Slack | 1.411 |
Data Arrival Time | 5.532 |
Data Required Time | 6.943 |
From | u_test_gen/De_hcnt_3_s3 |
To | u_test_gen/Data_tmp_8_s1 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 353 | PLL_R | u_pll/rpll_inst/CLKOUTD3 |
0.181 | 0.181 | tNET | RR | 1 | R18C4[0][A] | u_test_gen/De_hcnt_3_s3/CLK |
0.520 | 0.340 | tC2Q | RF | 5 | R18C4[0][A] | u_test_gen/De_hcnt_3_s3/Q |
1.625 | 1.105 | tNET | FF | 1 | R22C6[0][A] | u_test_gen/n1245_s8/I2 |
2.088 | 0.463 | tINS | FR | 2 | R22C6[0][A] | u_test_gen/n1245_s8/F |
2.400 | 0.312 | tNET | RR | 1 | R23C6[2][B] | u_test_gen/n1245_s7/I1 |
3.009 | 0.609 | tINS | RF | 6 | R23C6[2][B] | u_test_gen/n1245_s7/F |
3.617 | 0.608 | tNET | FF | 1 | R24C8[0][B] | u_test_gen/n1245_s5/I1 |
4.081 | 0.464 | tINS | FF | 16 | R24C8[0][B] | u_test_gen/n1245_s5/F |
5.069 | 0.988 | tNET | FF | 1 | R21C6[0][A] | u_test_gen/n1238_s2/I2 |
5.532 | 0.464 | tINS | FF | 1 | R21C6[0][A] | u_test_gen/n1238_s2/F |
5.532 | 0.000 | tNET | FF | 1 | R21C6[0][A] | u_test_gen/Data_tmp_8_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.059 | 7.059 | active clock edge time | ||||
7.059 | 0.000 | pixel_clk | ||||
7.059 | 0.000 | tCL | RR | 353 | PLL_R | u_pll/rpll_inst/CLKOUTD3 |
7.240 | 0.181 | tNET | RR | 1 | R21C6[0][A] | u_test_gen/Data_tmp_8_s1/CLK |
6.943 | -0.296 | tSu | 1 | R21C6[0][A] | u_test_gen/Data_tmp_8_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 7.059 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 2.000, 37.370%; route: 3.012, 56.284%; tC2Q: 0.340, 6.346% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Path20
Path Summary:
Slack | 1.444 |
Data Arrival Time | 5.499 |
Data Required Time | 6.943 |
From | u_test_gen/De_hcnt_3_s3 |
To | u_test_gen/Data_tmp_20_s1 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 353 | PLL_R | u_pll/rpll_inst/CLKOUTD3 |
0.181 | 0.181 | tNET | RR | 1 | R18C4[0][A] | u_test_gen/De_hcnt_3_s3/CLK |
0.520 | 0.340 | tC2Q | RF | 5 | R18C4[0][A] | u_test_gen/De_hcnt_3_s3/Q |
1.625 | 1.105 | tNET | FF | 1 | R22C6[0][A] | u_test_gen/n1245_s8/I2 |
2.088 | 0.463 | tINS | FR | 2 | R22C6[0][A] | u_test_gen/n1245_s8/F |
2.400 | 0.312 | tNET | RR | 1 | R23C6[2][B] | u_test_gen/n1245_s7/I1 |
3.009 | 0.609 | tINS | RF | 6 | R23C6[2][B] | u_test_gen/n1245_s7/F |
3.617 | 0.608 | tNET | FF | 1 | R21C7[0][A] | u_test_gen/n1230_s3/I1 |
4.081 | 0.464 | tINS | FF | 4 | R21C7[0][A] | u_test_gen/n1230_s3/F |
4.685 | 0.604 | tNET | FF | 1 | R24C7[0][B] | u_test_gen/n1226_s1/I2 |
5.499 | 0.814 | tINS | FF | 1 | R24C7[0][B] | u_test_gen/n1226_s1/F |
5.499 | 0.000 | tNET | FF | 1 | R24C7[0][B] | u_test_gen/Data_tmp_20_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.059 | 7.059 | active clock edge time | ||||
7.059 | 0.000 | pixel_clk | ||||
7.059 | 0.000 | tCL | RR | 353 | PLL_R | u_pll/rpll_inst/CLKOUTD3 |
7.240 | 0.181 | tNET | RR | 1 | R24C7[0][B] | u_test_gen/Data_tmp_20_s1/CLK |
6.943 | -0.296 | tSu | 1 | R24C7[0][B] | u_test_gen/Data_tmp_20_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 7.059 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 2.350, 44.194%; route: 2.628, 49.421%; tC2Q: 0.340, 6.386% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Setup Analysis Report[2]:
Report Command:report_timing -setup -from_clock [get_clocks {byte_clk}] -max_paths 20 -max_common_paths 1
Path1
Path Summary:
Slack | 6.993 |
Data Arrival Time | 11.715 |
Data Required Time | 18.708 |
From | u_dsi_tx/u_tx/u_dsi_tx/rLpCrc_4_s1 |
To | u_dsi_tx/u_tx/u_dsi_tx/rLpCrc_15_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.181 | 0.181 | tNET | RR | 1 | R22C18[0][A] | u_dsi_tx/u_tx/u_dsi_tx/rLpCrc_4_s1/CLK |
0.520 | 0.340 | tC2Q | RF | 31 | R22C18[0][A] | u_dsi_tx/u_tx/u_dsi_tx/rLpCrc_4_s1/Q |
1.873 | 1.353 | tNET | FF | 1 | R8C16[0][A] | u_dsi_tx/u_tx/u_dsi_tx/n4093_s24/I1 |
2.638 | 0.765 | tINS | FF | 2 | R8C16[0][A] | u_dsi_tx/u_tx/u_dsi_tx/n4093_s24/F |
4.445 | 1.807 | tNET | FF | 1 | R15C14[2][A] | u_dsi_tx/u_tx/u_dsi_tx/n4084_s34/I2 |
5.054 | 0.609 | tINS | FF | 1 | R15C14[2][A] | u_dsi_tx/u_tx/u_dsi_tx/n4084_s34/F |
7.095 | 2.040 | tNET | FF | 1 | R15C16[1][B] | u_dsi_tx/u_tx/u_dsi_tx/n4084_s17/I2 |
7.909 | 0.814 | tINS | FF | 1 | R15C16[1][B] | u_dsi_tx/u_tx/u_dsi_tx/n4084_s17/F |
8.517 | 0.608 | tNET | FF | 1 | R15C14[1][B] | u_dsi_tx/u_tx/u_dsi_tx/n4084_s9/I0 |
9.282 | 0.765 | tINS | FF | 1 | R15C14[1][B] | u_dsi_tx/u_tx/u_dsi_tx/n4084_s9/F |
9.890 | 0.608 | tNET | FF | 1 | R15C15[3][A] | u_dsi_tx/u_tx/u_dsi_tx/n4084_s4/I0 |
10.354 | 0.464 | tINS | FF | 1 | R15C15[3][A] | u_dsi_tx/u_tx/u_dsi_tx/n4084_s4/F |
10.950 | 0.596 | tNET | FF | 1 | R16C15[2][B] | u_dsi_tx/u_tx/u_dsi_tx/n4084_s2/I1 |
11.715 | 0.765 | tINS | FF | 1 | R16C15[2][B] | u_dsi_tx/u_tx/u_dsi_tx/n4084_s2/F |
11.715 | 0.000 | tNET | FF | 1 | R16C15[2][B] | u_dsi_tx/u_tx/u_dsi_tx/rLpCrc_15_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
18.824 | 18.824 | active clock edge time | ||||
18.824 | 0.000 | byte_clk | ||||
18.824 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
19.004 | 0.181 | tNET | RR | 1 | R16C15[2][B] | u_dsi_tx/u_tx/u_dsi_tx/rLpCrc_15_s1/CLK |
18.708 | -0.296 | tSu | 1 | R16C15[2][B] | u_dsi_tx/u_tx/u_dsi_tx/rLpCrc_15_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 18.824 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 4.181, 36.253%; route: 7.013, 60.803%; tC2Q: 0.340, 2.945% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Path2
Path Summary:
Slack | 6.994 |
Data Arrival Time | 11.714 |
Data Required Time | 18.708 |
From | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s |
To | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_9_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.181 | 0.181 | tNET | RR | 36 | BSRAM_R10[6] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/CLKB |
2.745 | 2.564 | tC2Q | RF | 3 | BSRAM_R10[6] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[28] |
4.308 | 1.563 | tNET | FF | 1 | R11C42[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s3/I1 |
4.772 | 0.464 | tINS | FF | 5 | R11C42[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s3/F |
4.788 | 0.016 | tNET | FF | 1 | R11C42[2][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s2/I0 |
5.397 | 0.609 | tINS | FF | 12 | R11C42[2][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s2/F |
6.013 | 0.617 | tNET | FF | 1 | R12C41[0][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n51_s3/I1 |
6.774 | 0.760 | tINS | FR | 3 | R12C41[0][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n51_s3/F |
7.086 | 0.312 | tNET | RR | 1 | R11C41[3][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n50_s3/I2 |
7.695 | 0.609 | tINS | RF | 3 | R11C41[3][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n50_s3/F |
8.654 | 0.959 | tNET | FF | 1 | R12C42[2][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n47_s2/I2 |
9.419 | 0.765 | tINS | FF | 3 | R12C42[2][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n47_s2/F |
10.034 | 0.616 | tNET | FF | 1 | R12C40[3][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n46_s1/I0 |
10.794 | 0.760 | tINS | FR | 1 | R12C40[3][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n46_s1/F |
11.105 | 0.310 | tNET | RR | 1 | R13C40[0][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n46_s0/I1 |
11.714 | 0.609 | tINS | RF | 1 | R13C40[0][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n46_s0/F |
11.714 | 0.000 | tNET | FF | 1 | R13C40[0][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_9_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
18.824 | 18.824 | active clock edge time | ||||
18.824 | 0.000 | byte_clk | ||||
18.824 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
19.004 | 0.181 | tNET | RR | 1 | R13C40[0][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_9_s1/CLK |
18.708 | -0.296 | tSu | 1 | R13C40[0][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_9_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 18.824 |
Logic Level | 8 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 4.576, 39.681%; route: 4.393, 38.089%; tC2Q: 2.564, 22.230% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Path3
Path Summary:
Slack | 7.465 |
Data Arrival Time | 11.243 |
Data Required Time | 18.708 |
From | u_dsi_tx/u_tx/u_dsi_tx/rCrcData_11_s0 |
To | u_dsi_tx/u_tx/u_dsi_tx/rLpCrc_11_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.181 | 0.181 | tNET | RR | 1 | R7C12[2][A] | u_dsi_tx/u_tx/u_dsi_tx/rCrcData_11_s0/CLK |
0.520 | 0.340 | tC2Q | RF | 20 | R7C12[2][A] | u_dsi_tx/u_tx/u_dsi_tx/rCrcData_11_s0/Q |
3.173 | 2.653 | tNET | FF | 1 | R13C20[2][A] | u_dsi_tx/u_tx/u_dsi_tx/n4088_s41/I0 |
3.938 | 0.765 | tINS | FF | 2 | R13C20[2][A] | u_dsi_tx/u_tx/u_dsi_tx/n4088_s41/F |
5.256 | 1.318 | tNET | FF | 1 | R14C20[3][A] | u_dsi_tx/u_tx/u_dsi_tx/n4088_s26/I3 |
5.720 | 0.464 | tINS | FF | 1 | R14C20[3][A] | u_dsi_tx/u_tx/u_dsi_tx/n4088_s26/F |
6.442 | 0.722 | tNET | FF | 1 | R14C16[3][A] | u_dsi_tx/u_tx/u_dsi_tx/n4088_s13/I3 |
7.207 | 0.765 | tINS | FF | 2 | R14C16[3][A] | u_dsi_tx/u_tx/u_dsi_tx/n4088_s13/F |
9.019 | 1.811 | tNET | FF | 1 | R13C16[0][A] | u_dsi_tx/u_tx/u_dsi_tx/n4088_s6/I2 |
9.833 | 0.814 | tINS | FF | 1 | R13C16[0][A] | u_dsi_tx/u_tx/u_dsi_tx/n4088_s6/F |
10.429 | 0.596 | tNET | FF | 1 | R14C17[0][A] | u_dsi_tx/u_tx/u_dsi_tx/n4088_s2/I3 |
11.243 | 0.814 | tINS | FF | 1 | R14C17[0][A] | u_dsi_tx/u_tx/u_dsi_tx/n4088_s2/F |
11.243 | 0.000 | tNET | FF | 1 | R14C17[0][A] | u_dsi_tx/u_tx/u_dsi_tx/rLpCrc_11_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
18.824 | 18.824 | active clock edge time | ||||
18.824 | 0.000 | byte_clk | ||||
18.824 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
19.004 | 0.181 | tNET | RR | 1 | R14C17[0][A] | u_dsi_tx/u_tx/u_dsi_tx/rLpCrc_11_s1/CLK |
18.708 | -0.296 | tSu | 1 | R14C17[0][A] | u_dsi_tx/u_tx/u_dsi_tx/rLpCrc_11_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 18.824 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 3.622, 32.741%; route: 7.101, 64.189%; tC2Q: 0.340, 3.070% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Path4
Path Summary:
Slack | 7.482 |
Data Arrival Time | 11.226 |
Data Required Time | 18.708 |
From | u_dsi_tx/u_tx/u_dsi_tx/rCrcData_5_s0 |
To | u_dsi_tx/u_tx/u_dsi_tx/rLpCrc_13_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.181 | 0.181 | tNET | RR | 1 | R5C14[2][A] | u_dsi_tx/u_tx/u_dsi_tx/rCrcData_5_s0/CLK |
0.520 | 0.340 | tC2Q | RF | 21 | R5C14[2][A] | u_dsi_tx/u_tx/u_dsi_tx/rCrcData_5_s0/Q |
2.587 | 2.067 | tNET | FF | 1 | R22C16[2][B] | u_dsi_tx/u_tx/u_dsi_tx/n4099_s20/I2 |
3.051 | 0.464 | tINS | FF | 6 | R22C16[2][B] | u_dsi_tx/u_tx/u_dsi_tx/n4099_s20/F |
4.629 | 1.578 | tNET | FF | 1 | R15C21[3][B] | u_dsi_tx/u_tx/u_dsi_tx/n4087_s50/I1 |
5.238 | 0.609 | tINS | FF | 2 | R15C21[3][B] | u_dsi_tx/u_tx/u_dsi_tx/n4087_s50/F |
7.164 | 1.925 | tNET | FF | 1 | R12C22[1][B] | u_dsi_tx/u_tx/u_dsi_tx/n4086_s18/I1 |
7.773 | 0.609 | tINS | FF | 1 | R12C22[1][B] | u_dsi_tx/u_tx/u_dsi_tx/n4086_s18/F |
7.777 | 0.004 | tNET | FF | 1 | R12C22[2][A] | u_dsi_tx/u_tx/u_dsi_tx/n4086_s7/I0 |
8.591 | 0.814 | tINS | FF | 1 | R12C22[2][A] | u_dsi_tx/u_tx/u_dsi_tx/n4086_s7/F |
9.546 | 0.955 | tNET | FF | 1 | R12C21[2][B] | u_dsi_tx/u_tx/u_dsi_tx/n4086_s3/I0 |
10.307 | 0.760 | tINS | FR | 1 | R12C21[2][B] | u_dsi_tx/u_tx/u_dsi_tx/n4086_s3/F |
10.617 | 0.310 | tNET | RR | 1 | R13C21[0][A] | u_dsi_tx/u_tx/u_dsi_tx/n4086_s2/I0 |
11.226 | 0.609 | tINS | RF | 1 | R13C21[0][A] | u_dsi_tx/u_tx/u_dsi_tx/n4086_s2/F |
11.226 | 0.000 | tNET | FF | 1 | R13C21[0][A] | u_dsi_tx/u_tx/u_dsi_tx/rLpCrc_13_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
18.824 | 18.824 | active clock edge time | ||||
18.824 | 0.000 | byte_clk | ||||
18.824 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
19.004 | 0.181 | tNET | RR | 1 | R13C21[0][A] | u_dsi_tx/u_tx/u_dsi_tx/rLpCrc_13_s1/CLK |
18.708 | -0.296 | tSu | 1 | R13C21[0][A] | u_dsi_tx/u_tx/u_dsi_tx/rLpCrc_13_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 18.824 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 3.866, 34.999%; route: 6.840, 61.926%; tC2Q: 0.340, 3.075% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Path5
Path Summary:
Slack | 7.859 |
Data Arrival Time | 10.848 |
Data Required Time | 18.708 |
From | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s |
To | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_8_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.181 | 0.181 | tNET | RR | 36 | BSRAM_R10[6] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/CLKB |
2.745 | 2.564 | tC2Q | RF | 3 | BSRAM_R10[6] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[28] |
4.308 | 1.563 | tNET | FF | 1 | R11C42[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s3/I1 |
4.772 | 0.464 | tINS | FF | 5 | R11C42[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s3/F |
4.788 | 0.016 | tNET | FF | 1 | R11C42[2][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s2/I0 |
5.397 | 0.609 | tINS | FF | 12 | R11C42[2][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s2/F |
6.013 | 0.617 | tNET | FF | 1 | R12C41[0][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n51_s3/I1 |
6.774 | 0.760 | tINS | FR | 3 | R12C41[0][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n51_s3/F |
7.086 | 0.312 | tNET | RR | 1 | R11C41[3][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n50_s3/I2 |
7.695 | 0.609 | tINS | RF | 3 | R11C41[3][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n50_s3/F |
8.654 | 0.959 | tNET | FF | 1 | R12C42[2][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n47_s2/I2 |
9.419 | 0.765 | tINS | FF | 3 | R12C42[2][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n47_s2/F |
10.034 | 0.616 | tNET | FF | 1 | R12C40[2][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n47_s0/I1 |
10.848 | 0.814 | tINS | FF | 1 | R12C40[2][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n47_s0/F |
10.848 | 0.000 | tNET | FF | 1 | R12C40[2][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_8_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
18.824 | 18.824 | active clock edge time | ||||
18.824 | 0.000 | byte_clk | ||||
18.824 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
19.004 | 0.181 | tNET | RR | 1 | R12C40[2][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_8_s1/CLK |
18.708 | -0.296 | tSu | 1 | R12C40[2][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_8_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 18.824 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 4.021, 37.697%; route: 4.082, 38.269%; tC2Q: 2.564, 24.034% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Path6
Path Summary:
Slack | 7.928 |
Data Arrival Time | 10.779 |
Data Required Time | 18.708 |
From | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s |
To | hs_data1_r_11_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.181 | 0.181 | tNET | RR | 36 | BSRAM_R10[6] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/CLKB |
2.745 | 2.564 | tC2Q | RF | 3 | BSRAM_R10[6] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[28] |
4.075 | 1.330 | tNET | FF | 1 | R9C40[0][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA3_d_15_s0/I1 |
4.839 | 0.765 | tINS | FF | 64 | R9C40[0][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA3_d_15_s0/F |
7.027 | 2.187 | tNET | FF | 1 | R9C26[0][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA1_d_11_s/I2 |
7.792 | 0.765 | tINS | FF | 2 | R9C26[0][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA1_d_11_s/F |
10.779 | 2.988 | tNET | FF | 1 | R25C13[0][B] | hs_data1_r_11_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
18.824 | 18.824 | active clock edge time | ||||
18.824 | 0.000 | byte_clk | ||||
18.824 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
19.004 | 0.181 | tNET | RR | 1 | R25C13[0][B] | hs_data1_r_11_s0/CLK |
18.708 | -0.296 | tSu | 1 | R25C13[0][B] | hs_data1_r_11_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 18.824 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 1.529, 14.430%; route: 6.505, 61.379%; tC2Q: 2.564, 24.190% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Path7
Path Summary:
Slack | 7.966 |
Data Arrival Time | 10.742 |
Data Required Time | 18.708 |
From | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s |
To | hs_data3_r_8_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.181 | 0.181 | tNET | RR | 36 | BSRAM_R10[6] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/CLKB |
2.745 | 2.564 | tC2Q | RF | 3 | BSRAM_R10[6] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[28] |
4.075 | 1.330 | tNET | FF | 1 | R9C40[0][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA3_d_15_s0/I1 |
4.839 | 0.765 | tINS | FF | 64 | R9C40[0][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA3_d_15_s0/F |
6.932 | 2.092 | tNET | FF | 1 | R9C25[1][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA3_d_8_s/I2 |
7.746 | 0.814 | tINS | FF | 2 | R9C25[1][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA3_d_8_s/F |
10.742 | 2.996 | tNET | FF | 1 | R22C13[1][B] | hs_data3_r_8_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
18.824 | 18.824 | active clock edge time | ||||
18.824 | 0.000 | byte_clk | ||||
18.824 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
19.004 | 0.181 | tNET | RR | 1 | R22C13[1][B] | hs_data3_r_8_s0/CLK |
18.708 | -0.296 | tSu | 1 | R22C13[1][B] | hs_data3_r_8_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 18.824 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 1.579, 14.951%; route: 6.419, 60.773%; tC2Q: 2.564, 24.276% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Path8
Path Summary:
Slack | 8.004 |
Data Arrival Time | 10.704 |
Data Required Time | 18.708 |
From | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s |
To | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rWrOffset_7_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.181 | 0.181 | tNET | RR | 36 | BSRAM_R10[6] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/CLKB |
2.745 | 2.564 | tC2Q | RF | 3 | BSRAM_R10[6] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[28] |
4.308 | 1.563 | tNET | FF | 1 | R11C42[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s3/I1 |
4.772 | 0.464 | tINS | FF | 5 | R11C42[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s3/F |
4.788 | 0.016 | tNET | FF | 1 | R11C42[2][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s2/I0 |
5.397 | 0.609 | tINS | FF | 12 | R11C42[2][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s2/F |
6.145 | 0.748 | tNET | FF | 1 | R12C40[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n122_s1/I0 |
6.959 | 0.814 | tINS | FF | 4 | R12C40[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n122_s1/F |
7.567 | 0.608 | tNET | FF | 1 | R12C41[2][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n121_s1/I3 |
8.031 | 0.464 | tINS | FF | 4 | R12C41[2][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n121_s1/F |
8.043 | 0.012 | tNET | FF | 1 | R12C41[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n117_s2/I3 |
8.808 | 0.765 | tINS | FF | 2 | R12C41[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n117_s2/F |
9.889 | 1.081 | tNET | FF | 1 | R7C42[0][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n118_s0/I1 |
10.704 | 0.814 | tINS | FF | 1 | R7C42[0][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n118_s0/F |
10.704 | 0.000 | tNET | FF | 1 | R7C42[0][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rWrOffset_7_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
18.824 | 18.824 | active clock edge time | ||||
18.824 | 0.000 | byte_clk | ||||
18.824 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
19.004 | 0.181 | tNET | RR | 1 | R7C42[0][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rWrOffset_7_s1/CLK |
18.708 | -0.296 | tSu | 1 | R7C42[0][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rWrOffset_7_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 18.824 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 3.930, 37.350%; route: 4.029, 38.285%; tC2Q: 2.564, 24.365% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Path9
Path Summary:
Slack | 8.084 |
Data Arrival Time | 10.624 |
Data Required Time | 18.708 |
From | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s |
To | hs_data3_r_14_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.181 | 0.181 | tNET | RR | 36 | BSRAM_R10[6] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/CLKB |
2.745 | 2.564 | tC2Q | RF | 3 | BSRAM_R10[6] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[28] |
4.075 | 1.330 | tNET | FF | 1 | R9C40[0][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA3_d_15_s0/I1 |
4.839 | 0.765 | tINS | FF | 64 | R9C40[0][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA3_d_15_s0/F |
6.932 | 2.092 | tNET | FF | 1 | R9C25[2][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA3_d_14_s/I2 |
7.746 | 0.814 | tINS | FF | 2 | R9C25[2][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA3_d_14_s/F |
10.624 | 2.878 | tNET | FF | 1 | R23C15[0][B] | hs_data3_r_14_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
18.824 | 18.824 | active clock edge time | ||||
18.824 | 0.000 | byte_clk | ||||
18.824 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
19.004 | 0.181 | tNET | RR | 1 | R23C15[0][B] | hs_data3_r_14_s0/CLK |
18.708 | -0.296 | tSu | 1 | R23C15[0][B] | hs_data3_r_14_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 18.824 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 1.579, 15.120%; route: 6.301, 60.331%; tC2Q: 2.564, 24.550% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Path10
Path Summary:
Slack | 8.088 |
Data Arrival Time | 10.619 |
Data Required Time | 18.708 |
From | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s |
To | hs_data1_r_14_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.181 | 0.181 | tNET | RR | 36 | BSRAM_R10[6] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/CLKB |
2.745 | 2.564 | tC2Q | RF | 3 | BSRAM_R10[6] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[28] |
4.075 | 1.330 | tNET | FF | 1 | R9C40[0][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA3_d_15_s0/I1 |
4.839 | 0.765 | tINS | FF | 64 | R9C40[0][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA3_d_15_s0/F |
6.939 | 2.100 | tNET | FF | 1 | R11C23[2][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA1_d_14_s/I2 |
7.753 | 0.814 | tINS | FF | 2 | R11C23[2][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA1_d_14_s/F |
10.619 | 2.866 | tNET | FF | 1 | R25C12[2][B] | hs_data1_r_14_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
18.824 | 18.824 | active clock edge time | ||||
18.824 | 0.000 | byte_clk | ||||
18.824 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
19.004 | 0.181 | tNET | RR | 1 | R25C12[2][B] | hs_data1_r_14_s0/CLK |
18.708 | -0.296 | tSu | 1 | R25C12[2][B] | hs_data1_r_14_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 18.824 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 1.579, 15.127%; route: 6.296, 60.312%; tC2Q: 2.564, 24.561% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Path11
Path Summary:
Slack | 8.103 |
Data Arrival Time | 10.605 |
Data Required Time | 18.708 |
From | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s |
To | hs_data3_r_15_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.181 | 0.181 | tNET | RR | 36 | BSRAM_R10[6] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/CLKB |
2.745 | 2.564 | tC2Q | RF | 3 | BSRAM_R10[6] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[28] |
4.075 | 1.330 | tNET | FF | 1 | R9C40[0][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA3_d_15_s0/I1 |
4.839 | 0.765 | tINS | FF | 64 | R9C40[0][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA3_d_15_s0/F |
6.925 | 2.085 | tNET | FF | 1 | R11C24[1][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA3_d_15_s/I2 |
7.739 | 0.814 | tINS | FF | 2 | R11C24[1][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA3_d_15_s/F |
10.605 | 2.866 | tNET | FF | 1 | R23C13[0][B] | hs_data3_r_15_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
18.824 | 18.824 | active clock edge time | ||||
18.824 | 0.000 | byte_clk | ||||
18.824 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
19.004 | 0.181 | tNET | RR | 1 | R23C13[0][B] | hs_data3_r_15_s0/CLK |
18.708 | -0.296 | tSu | 1 | R23C13[0][B] | hs_data3_r_15_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 18.824 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 1.579, 15.148%; route: 6.281, 60.256%; tC2Q: 2.564, 24.595% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Path12
Path Summary:
Slack | 8.125 |
Data Arrival Time | 10.582 |
Data Required Time | 18.708 |
From | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s |
To | hs_data1_r_9_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.181 | 0.181 | tNET | RR | 36 | BSRAM_R10[6] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/CLKB |
2.745 | 2.564 | tC2Q | RF | 3 | BSRAM_R10[6] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[28] |
4.075 | 1.330 | tNET | FF | 1 | R9C40[0][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA3_d_15_s0/I1 |
4.839 | 0.765 | tINS | FF | 64 | R9C40[0][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA3_d_15_s0/F |
6.939 | 2.100 | tNET | FF | 1 | R11C23[3][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA1_d_9_s/I2 |
7.704 | 0.765 | tINS | FF | 2 | R11C23[3][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA1_d_9_s/F |
10.582 | 2.879 | tNET | FF | 1 | R25C13[1][B] | hs_data1_r_9_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
18.824 | 18.824 | active clock edge time | ||||
18.824 | 0.000 | byte_clk | ||||
18.824 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
19.004 | 0.181 | tNET | RR | 1 | R25C13[1][B] | hs_data1_r_9_s0/CLK |
18.708 | -0.296 | tSu | 1 | R25C13[1][B] | hs_data1_r_9_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 18.824 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 1.529, 14.704%; route: 6.308, 60.648%; tC2Q: 2.564, 24.648% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Path13
Path Summary:
Slack | 8.140 |
Data Arrival Time | 10.568 |
Data Required Time | 18.708 |
From | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s |
To | hs_data2_r_13_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.181 | 0.181 | tNET | RR | 36 | BSRAM_R10[6] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/CLKB |
2.745 | 2.564 | tC2Q | RF | 3 | BSRAM_R10[6] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[28] |
4.075 | 1.330 | tNET | FF | 1 | R9C40[0][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA3_d_15_s0/I1 |
4.839 | 0.765 | tINS | FF | 64 | R9C40[0][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA3_d_15_s0/F |
6.925 | 2.085 | tNET | FF | 1 | R9C24[3][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA2_d_13_s/I2 |
7.689 | 0.765 | tINS | FF | 2 | R9C24[3][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA2_d_13_s/F |
10.568 | 2.879 | tNET | FF | 1 | R23C15[1][B] | hs_data2_r_13_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
18.824 | 18.824 | active clock edge time | ||||
18.824 | 0.000 | byte_clk | ||||
18.824 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
19.004 | 0.181 | tNET | RR | 1 | R23C15[1][B] | hs_data2_r_13_s0/CLK |
18.708 | -0.296 | tSu | 1 | R23C15[1][B] | hs_data2_r_13_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 18.824 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 1.529, 14.724%; route: 6.294, 60.593%; tC2Q: 2.564, 24.683% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Path14
Path Summary:
Slack | 8.161 |
Data Arrival Time | 10.547 |
Data Required Time | 18.708 |
From | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s |
To | hs_data1_r_12_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.181 | 0.181 | tNET | RR | 36 | BSRAM_R10[6] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/CLKB |
2.745 | 2.564 | tC2Q | RF | 3 | BSRAM_R10[6] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[28] |
4.075 | 1.330 | tNET | FF | 1 | R9C40[0][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA3_d_15_s0/I1 |
4.839 | 0.765 | tINS | FF | 64 | R9C40[0][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA3_d_15_s0/F |
7.027 | 2.187 | tNET | FF | 1 | R9C26[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA1_d_12_s/I2 |
7.792 | 0.765 | tINS | FF | 2 | R9C26[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA1_d_12_s/F |
10.547 | 2.755 | tNET | FF | 1 | R25C12[1][A] | hs_data1_r_12_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
18.824 | 18.824 | active clock edge time | ||||
18.824 | 0.000 | byte_clk | ||||
18.824 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
19.004 | 0.181 | tNET | RR | 1 | R25C12[1][A] | hs_data1_r_12_s0/CLK |
18.708 | -0.296 | tSu | 1 | R25C12[1][A] | hs_data1_r_12_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 18.824 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 1.529, 14.754%; route: 6.273, 60.513%; tC2Q: 2.564, 24.733% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Path15
Path Summary:
Slack | 8.161 |
Data Arrival Time | 10.547 |
Data Required Time | 18.708 |
From | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s |
To | hs_data0_r_15_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.181 | 0.181 | tNET | RR | 36 | BSRAM_R10[6] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/CLKB |
2.745 | 2.564 | tC2Q | RF | 3 | BSRAM_R10[6] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[28] |
4.075 | 1.330 | tNET | FF | 1 | R9C40[0][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA3_d_15_s0/I1 |
4.839 | 0.765 | tINS | FF | 64 | R9C40[0][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA3_d_15_s0/F |
7.027 | 2.187 | tNET | FF | 1 | R9C26[2][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA0_d_15_s/I2 |
7.792 | 0.765 | tINS | FF | 2 | R9C26[2][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA0_d_15_s/F |
10.547 | 2.755 | tNET | FF | 1 | R23C14[0][A] | hs_data0_r_15_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
18.824 | 18.824 | active clock edge time | ||||
18.824 | 0.000 | byte_clk | ||||
18.824 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
19.004 | 0.181 | tNET | RR | 1 | R23C14[0][A] | hs_data0_r_15_s0/CLK |
18.708 | -0.296 | tSu | 1 | R23C14[0][A] | hs_data0_r_15_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 18.824 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 1.529, 14.754%; route: 6.273, 60.513%; tC2Q: 2.564, 24.733% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Path16
Path Summary:
Slack | 8.161 |
Data Arrival Time | 10.547 |
Data Required Time | 18.708 |
From | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s |
To | hs_data1_r_13_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.181 | 0.181 | tNET | RR | 36 | BSRAM_R10[6] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/CLKB |
2.745 | 2.564 | tC2Q | RF | 3 | BSRAM_R10[6] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[28] |
4.075 | 1.330 | tNET | FF | 1 | R9C40[0][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA3_d_15_s0/I1 |
4.839 | 0.765 | tINS | FF | 64 | R9C40[0][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA3_d_15_s0/F |
7.027 | 2.187 | tNET | FF | 1 | R9C26[0][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA1_d_13_s/I2 |
7.792 | 0.765 | tINS | FF | 2 | R9C26[0][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA1_d_13_s/F |
10.547 | 2.755 | tNET | FF | 1 | R25C12[0][B] | hs_data1_r_13_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
18.824 | 18.824 | active clock edge time | ||||
18.824 | 0.000 | byte_clk | ||||
18.824 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
19.004 | 0.181 | tNET | RR | 1 | R25C12[0][B] | hs_data1_r_13_s0/CLK |
18.708 | -0.296 | tSu | 1 | R25C12[0][B] | hs_data1_r_13_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 18.824 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 1.529, 14.755%; route: 6.272, 60.511%; tC2Q: 2.564, 24.734% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Path17
Path Summary:
Slack | 8.170 |
Data Arrival Time | 10.801 |
Data Required Time | 18.971 |
From | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s |
To | u_tx_phy/DPHY_TX_INST/u_oserx4x8/U5_OSER16_1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.181 | 0.181 | tNET | RR | 36 | BSRAM_R10[6] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/CLKB |
2.745 | 2.564 | tC2Q | RF | 3 | BSRAM_R10[6] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[28] |
4.075 | 1.330 | tNET | FF | 1 | R9C40[0][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA3_d_15_s0/I1 |
4.839 | 0.765 | tINS | FF | 64 | R9C40[0][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA3_d_15_s0/F |
7.027 | 2.187 | tNET | FF | 1 | R9C26[0][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA1_d_13_s/I2 |
7.792 | 0.765 | tINS | FF | 2 | R9C26[0][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA1_d_13_s/F |
10.801 | 3.009 | tNET | FF | 1 | IOB39[A] | u_tx_phy/DPHY_TX_INST/u_oserx4x8/U5_OSER16_1/D13 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
18.824 | 18.824 | active clock edge time | ||||
18.824 | 0.000 | byte_clk | ||||
18.824 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
19.004 | 0.181 | tNET | RR | 1 | IOB39[A] | u_tx_phy/DPHY_TX_INST/u_oserx4x8/U5_OSER16_1/PCLK |
18.971 | -0.033 | tSu | 1 | IOB39[A] | u_tx_phy/DPHY_TX_INST/u_oserx4x8/U5_OSER16_1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 18.824 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 1.529, 14.401%; route: 6.527, 61.457%; tC2Q: 2.564, 24.142% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Path18
Path Summary:
Slack | 8.217 |
Data Arrival Time | 10.491 |
Data Required Time | 18.708 |
From | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s |
To | hs_data3_r_13_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.181 | 0.181 | tNET | RR | 36 | BSRAM_R10[6] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/CLKB |
2.745 | 2.564 | tC2Q | RF | 3 | BSRAM_R10[6] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[28] |
4.075 | 1.330 | tNET | FF | 1 | R9C40[0][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA3_d_15_s0/I1 |
4.839 | 0.765 | tINS | FF | 64 | R9C40[0][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA3_d_15_s0/F |
6.925 | 2.085 | tNET | FF | 1 | R11C24[1][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA3_d_13_s/I2 |
7.739 | 0.814 | tINS | FF | 2 | R11C24[1][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA3_d_13_s/F |
10.491 | 2.752 | tNET | FF | 1 | R23C13[2][B] | hs_data3_r_13_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
18.824 | 18.824 | active clock edge time | ||||
18.824 | 0.000 | byte_clk | ||||
18.824 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
19.004 | 0.181 | tNET | RR | 1 | R23C13[2][B] | hs_data3_r_13_s0/CLK |
18.708 | -0.296 | tSu | 1 | R23C13[2][B] | hs_data3_r_13_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 18.824 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 1.579, 15.316%; route: 6.167, 59.817%; tC2Q: 2.564, 24.867% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Path19
Path Summary:
Slack | 8.250 |
Data Arrival Time | 10.458 |
Data Required Time | 18.708 |
From | u_dsi_tx/u_tx/u_dsi_tx/rCrcData_36_s0 |
To | u_dsi_tx/u_tx/u_dsi_tx/rLpCrc_4_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.181 | 0.181 | tNET | RR | 1 | R5C13[0][A] | u_dsi_tx/u_tx/u_dsi_tx/rCrcData_36_s0/CLK |
0.520 | 0.340 | tC2Q | RF | 9 | R5C13[0][A] | u_dsi_tx/u_tx/u_dsi_tx/rCrcData_36_s0/Q |
2.450 | 1.929 | tNET | FF | 1 | R20C20[1][A] | u_dsi_tx/u_tx/u_dsi_tx/n4087_s39/I0 |
3.059 | 0.609 | tINS | FF | 4 | R20C20[1][A] | u_dsi_tx/u_tx/u_dsi_tx/n4087_s39/F |
4.756 | 1.698 | tNET | FF | 1 | R14C18[3][B] | u_dsi_tx/u_tx/u_dsi_tx/n4094_s42/I2 |
5.571 | 0.814 | tINS | FF | 2 | R14C18[3][B] | u_dsi_tx/u_tx/u_dsi_tx/n4094_s42/F |
6.530 | 0.959 | tNET | FF | 1 | R18C18[3][B] | u_dsi_tx/u_tx/u_dsi_tx/n4095_s25/I0 |
7.344 | 0.814 | tINS | FF | 1 | R18C18[3][B] | u_dsi_tx/u_tx/u_dsi_tx/n4095_s25/F |
8.312 | 0.967 | tNET | FF | 1 | R22C18[2][A] | u_dsi_tx/u_tx/u_dsi_tx/n4095_s12/I0 |
9.076 | 0.765 | tINS | FF | 1 | R22C18[2][A] | u_dsi_tx/u_tx/u_dsi_tx/n4095_s12/F |
9.080 | 0.004 | tNET | FF | 1 | R22C18[2][B] | u_dsi_tx/u_tx/u_dsi_tx/n4095_s5/I1 |
9.689 | 0.609 | tINS | FF | 1 | R22C18[2][B] | u_dsi_tx/u_tx/u_dsi_tx/n4095_s5/F |
9.694 | 0.004 | tNET | FF | 1 | R22C18[0][A] | u_dsi_tx/u_tx/u_dsi_tx/n4095_s2/I2 |
10.458 | 0.765 | tINS | FF | 1 | R22C18[0][A] | u_dsi_tx/u_tx/u_dsi_tx/n4095_s2/F |
10.458 | 0.000 | tNET | FF | 1 | R22C18[0][A] | u_dsi_tx/u_tx/u_dsi_tx/rLpCrc_4_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
18.824 | 18.824 | active clock edge time | ||||
18.824 | 0.000 | byte_clk | ||||
18.824 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
19.004 | 0.181 | tNET | RR | 1 | R22C18[0][A] | u_dsi_tx/u_tx/u_dsi_tx/rLpCrc_4_s1/CLK |
18.708 | -0.296 | tSu | 1 | R22C18[0][A] | u_dsi_tx/u_tx/u_dsi_tx/rLpCrc_4_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 18.824 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 4.376, 42.582%; route: 5.561, 54.113%; tC2Q: 0.340, 3.305% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Path20
Path Summary:
Slack | 8.256 |
Data Arrival Time | 10.452 |
Data Required Time | 18.708 |
From | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s |
To | hs_data3_r_9_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.181 | 0.181 | tNET | RR | 36 | BSRAM_R10[6] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/CLKB |
2.745 | 2.564 | tC2Q | RF | 3 | BSRAM_R10[6] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[28] |
4.075 | 1.330 | tNET | FF | 1 | R9C40[0][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA3_d_15_s0/I1 |
4.839 | 0.765 | tINS | FF | 64 | R9C40[0][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA3_d_15_s0/F |
6.932 | 2.092 | tNET | FF | 1 | R9C25[3][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA3_d_9_s/I2 |
7.697 | 0.765 | tINS | FF | 2 | R9C25[3][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA3_d_9_s/F |
10.452 | 2.755 | tNET | FF | 1 | R22C13[1][A] | hs_data3_r_9_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
18.824 | 18.824 | active clock edge time | ||||
18.824 | 0.000 | byte_clk | ||||
18.824 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
19.004 | 0.181 | tNET | RR | 1 | R22C13[1][A] | hs_data3_r_9_s0/CLK |
18.708 | -0.296 | tSu | 1 | R22C13[1][A] | hs_data3_r_9_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 18.824 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 1.529, 14.891%; route: 6.177, 60.146%; tC2Q: 2.564, 24.963% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Hold Analysis Report
Hold Analysis Report[1]:
Report Command:report_timing -hold -from_clock [get_clocks {pixel_clk}] -max_paths 20 -max_common_paths 1
Path1
Path Summary:
Slack | 0.407 |
Data Arrival Time | 0.555 |
Data Required Time | 0.148 |
From | u_p2b/u_p2b_0/mid_data_28_s1 |
To | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mSsram_mSsram_0_7_s |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 353 | PLL_R | u_pll/rpll_inst/CLKOUTD3 |
0.137 | 0.137 | tNET | RR | 1 | R15C9[0][A] | u_p2b/u_p2b_0/mid_data_28_s1/CLK |
0.384 | 0.247 | tC2Q | RF | 1 | R15C9[0][A] | u_p2b/u_p2b_0/mid_data_28_s1/Q |
0.555 | 0.171 | tNET | FF | 1 | R15C8 | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mSsram_mSsram_0_7_s/DI[0] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 353 | PLL_R | u_pll/rpll_inst/CLKOUTD3 |
0.137 | 0.137 | tNET | RR | 1 | R15C8 | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mSsram_mSsram_0_7_s/CLK |
0.148 | 0.011 | tHld | 1 | R15C8 | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mSsram_mSsram_0_7_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.171, 40.960%; tC2Q: 0.247, 59.040% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path2
Path Summary:
Slack | 0.407 |
Data Arrival Time | 0.555 |
Data Required Time | 0.148 |
From | u_p2b/u_p2b_0/mid_data_20_s1 |
To | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mSsram_mSsram_0_5_s |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 353 | PLL_R | u_pll/rpll_inst/CLKOUTD3 |
0.137 | 0.137 | tNET | RR | 1 | R15C9[0][B] | u_p2b/u_p2b_0/mid_data_20_s1/CLK |
0.384 | 0.247 | tC2Q | RF | 1 | R15C9[0][B] | u_p2b/u_p2b_0/mid_data_20_s1/Q |
0.555 | 0.171 | tNET | FF | 1 | R14C9 | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mSsram_mSsram_0_5_s/DI[0] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 353 | PLL_R | u_pll/rpll_inst/CLKOUTD3 |
0.137 | 0.137 | tNET | RR | 1 | R14C9 | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mSsram_mSsram_0_5_s/CLK |
0.148 | 0.011 | tHld | 1 | R14C9 | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mSsram_mSsram_0_5_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.171, 40.960%; tC2Q: 0.247, 59.040% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path3
Path Summary:
Slack | 0.411 |
Data Arrival Time | 0.559 |
Data Required Time | 0.148 |
From | u_p2b/u_p2b_0/u_mid_buf/rRstWsync_s0 |
To | u_p2b/u_p2b_0/u_mid_buf/rWrRst_s0 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 353 | PLL_R | u_pll/rpll_inst/CLKOUTD3 |
0.137 | 0.137 | tNET | RR | 1 | R6C5[1][A] | u_p2b/u_p2b_0/u_mid_buf/rRstWsync_s0/CLK |
0.384 | 0.247 | tC2Q | RR | 1 | R6C5[1][A] | u_p2b/u_p2b_0/u_mid_buf/rRstWsync_s0/Q |
0.559 | 0.175 | tNET | RR | 1 | R6C5[0][A] | u_p2b/u_p2b_0/u_mid_buf/rWrRst_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 353 | PLL_R | u_pll/rpll_inst/CLKOUTD3 |
0.137 | 0.137 | tNET | RR | 1 | R6C5[0][A] | u_p2b/u_p2b_0/u_mid_buf/rWrRst_s0/CLK |
0.148 | 0.011 | tHld | 1 | R6C5[0][A] | u_p2b/u_p2b_0/u_mid_buf/rWrRst_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.175, 41.492%; tC2Q: 0.247, 58.508% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path4
Path Summary:
Slack | 0.524 |
Data Arrival Time | 0.661 |
Data Required Time | 0.137 |
From | u_p2b/u_p2b_0/u_mid_buf/rWPtrGray_0_s1 |
To | u_p2b/u_p2b_0/u_mid_buf/rWPtrGray_0_s1 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 353 | PLL_R | u_pll/rpll_inst/CLKOUTD3 |
0.137 | 0.137 | tNET | RR | 1 | R7C6[1][A] | u_p2b/u_p2b_0/u_mid_buf/rWPtrGray_0_s1/CLK |
0.384 | 0.247 | tC2Q | RR | 2 | R7C6[1][A] | u_p2b/u_p2b_0/u_mid_buf/rWPtrGray_0_s1/Q |
0.386 | 0.002 | tNET | RR | 1 | R7C6[1][A] | u_p2b/u_p2b_0/u_mid_buf/wWPtrGrayNext_0_s3/I0 |
0.661 | 0.276 | tINS | RF | 1 | R7C6[1][A] | u_p2b/u_p2b_0/u_mid_buf/wWPtrGrayNext_0_s3/F |
0.661 | 0.000 | tNET | FF | 1 | R7C6[1][A] | u_p2b/u_p2b_0/u_mid_buf/rWPtrGray_0_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 353 | PLL_R | u_pll/rpll_inst/CLKOUTD3 |
0.137 | 0.137 | tNET | RR | 1 | R7C6[1][A] | u_p2b/u_p2b_0/u_mid_buf/rWPtrGray_0_s1/CLK |
0.137 | 0.000 | tHld | 1 | R7C6[1][A] | u_p2b/u_p2b_0/u_mid_buf/rWPtrGray_0_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path5
Path Summary:
Slack | 0.524 |
Data Arrival Time | 0.661 |
Data Required Time | 0.137 |
From | u_test_gen/Color_trig_num_4_s3 |
To | u_test_gen/Color_trig_num_4_s3 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 353 | PLL_R | u_pll/rpll_inst/CLKOUTD3 |
0.137 | 0.137 | tNET | RR | 1 | R24C4[0][A] | u_test_gen/Color_trig_num_4_s3/CLK |
0.384 | 0.247 | tC2Q | RR | 7 | R24C4[0][A] | u_test_gen/Color_trig_num_4_s3/Q |
0.386 | 0.002 | tNET | RR | 1 | R24C4[0][A] | u_test_gen/n611_s4/I2 |
0.661 | 0.276 | tINS | RF | 1 | R24C4[0][A] | u_test_gen/n611_s4/F |
0.661 | 0.000 | tNET | FF | 1 | R24C4[0][A] | u_test_gen/Color_trig_num_4_s3/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 353 | PLL_R | u_pll/rpll_inst/CLKOUTD3 |
0.137 | 0.137 | tNET | RR | 1 | R24C4[0][A] | u_test_gen/Color_trig_num_4_s3/CLK |
0.137 | 0.000 | tHld | 1 | R24C4[0][A] | u_test_gen/Color_trig_num_4_s3 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path6
Path Summary:
Slack | 0.524 |
Data Arrival Time | 0.661 |
Data Required Time | 0.137 |
From | u_test_gen/De_vcnt_11_s1 |
To | u_test_gen/De_vcnt_11_s1 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 353 | PLL_R | u_pll/rpll_inst/CLKOUTD3 |
0.137 | 0.137 | tNET | RR | 1 | R23C7[1][A] | u_test_gen/De_vcnt_11_s1/CLK |
0.384 | 0.247 | tC2Q | RR | 2 | R23C7[1][A] | u_test_gen/De_vcnt_11_s1/Q |
0.386 | 0.002 | tNET | RR | 1 | R23C7[1][A] | u_test_gen/n548_s2/I3 |
0.661 | 0.276 | tINS | RF | 1 | R23C7[1][A] | u_test_gen/n548_s2/F |
0.661 | 0.000 | tNET | FF | 1 | R23C7[1][A] | u_test_gen/De_vcnt_11_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 353 | PLL_R | u_pll/rpll_inst/CLKOUTD3 |
0.137 | 0.137 | tNET | RR | 1 | R23C7[1][A] | u_test_gen/De_vcnt_11_s1/CLK |
0.137 | 0.000 | tHld | 1 | R23C7[1][A] | u_test_gen/De_vcnt_11_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path7
Path Summary:
Slack | 0.524 |
Data Arrival Time | 0.661 |
Data Required Time | 0.137 |
From | u_test_gen/H_cnt_3_s0 |
To | u_test_gen/H_cnt_3_s0 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 353 | PLL_R | u_pll/rpll_inst/CLKOUTD3 |
0.137 | 0.137 | tNET | RR | 1 | R18C9[0][A] | u_test_gen/H_cnt_3_s0/CLK |
0.384 | 0.247 | tC2Q | RR | 4 | R18C9[0][A] | u_test_gen/H_cnt_3_s0/Q |
0.386 | 0.002 | tNET | RR | 1 | R18C9[0][A] | u_test_gen/n137_s2/I3 |
0.661 | 0.276 | tINS | RF | 1 | R18C9[0][A] | u_test_gen/n137_s2/F |
0.661 | 0.000 | tNET | FF | 1 | R18C9[0][A] | u_test_gen/H_cnt_3_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 353 | PLL_R | u_pll/rpll_inst/CLKOUTD3 |
0.137 | 0.137 | tNET | RR | 1 | R18C9[0][A] | u_test_gen/H_cnt_3_s0/CLK |
0.137 | 0.000 | tHld | 1 | R18C9[0][A] | u_test_gen/H_cnt_3_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path8
Path Summary:
Slack | 0.524 |
Data Arrival Time | 0.661 |
Data Required Time | 0.137 |
From | u_test_gen/H_cnt_5_s0 |
To | u_test_gen/H_cnt_5_s0 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 353 | PLL_R | u_pll/rpll_inst/CLKOUTD3 |
0.137 | 0.137 | tNET | RR | 1 | R21C9[1][A] | u_test_gen/H_cnt_5_s0/CLK |
0.384 | 0.247 | tC2Q | RR | 3 | R21C9[1][A] | u_test_gen/H_cnt_5_s0/Q |
0.386 | 0.002 | tNET | RR | 1 | R21C9[1][A] | u_test_gen/n135_s2/I3 |
0.661 | 0.276 | tINS | RF | 1 | R21C9[1][A] | u_test_gen/n135_s2/F |
0.661 | 0.000 | tNET | FF | 1 | R21C9[1][A] | u_test_gen/H_cnt_5_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 353 | PLL_R | u_pll/rpll_inst/CLKOUTD3 |
0.137 | 0.137 | tNET | RR | 1 | R21C9[1][A] | u_test_gen/H_cnt_5_s0/CLK |
0.137 | 0.000 | tHld | 1 | R21C9[1][A] | u_test_gen/H_cnt_5_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path9
Path Summary:
Slack | 0.524 |
Data Arrival Time | 0.661 |
Data Required Time | 0.137 |
From | frame_led_s1 |
To | frame_led_s1 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 353 | PLL_R | u_pll/rpll_inst/CLKOUTD3 |
0.137 | 0.137 | tNET | RR | 1 | R22C10[1][A] | frame_led_s1/CLK |
0.384 | 0.247 | tC2Q | RR | 2 | R22C10[1][A] | frame_led_s1/Q |
0.386 | 0.002 | tNET | RR | 1 | R22C10[1][A] | n203_s2/I0 |
0.661 | 0.276 | tINS | RF | 1 | R22C10[1][A] | n203_s2/F |
0.661 | 0.000 | tNET | FF | 1 | R22C10[1][A] | frame_led_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 353 | PLL_R | u_pll/rpll_inst/CLKOUTD3 |
0.137 | 0.137 | tNET | RR | 1 | R22C10[1][A] | frame_led_s1/CLK |
0.137 | 0.000 | tHld | 1 | R22C10[1][A] | frame_led_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path10
Path Summary:
Slack | 0.524 |
Data Arrival Time | 0.661 |
Data Required Time | 0.137 |
From | frame_3_s0 |
To | frame_3_s0 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 353 | PLL_R | u_pll/rpll_inst/CLKOUTD3 |
0.137 | 0.137 | tNET | RR | 1 | R21C9[0][A] | frame_3_s0/CLK |
0.384 | 0.247 | tC2Q | RR | 3 | R21C9[0][A] | frame_3_s0/Q |
0.386 | 0.002 | tNET | RR | 1 | R21C9[0][A] | n181_s2/I3 |
0.661 | 0.276 | tINS | RF | 1 | R21C9[0][A] | n181_s2/F |
0.661 | 0.000 | tNET | FF | 1 | R21C9[0][A] | frame_3_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 353 | PLL_R | u_pll/rpll_inst/CLKOUTD3 |
0.137 | 0.137 | tNET | RR | 1 | R21C9[0][A] | frame_3_s0/CLK |
0.137 | 0.000 | tHld | 1 | R21C9[0][A] | frame_3_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path11
Path Summary:
Slack | 0.525 |
Data Arrival Time | 0.662 |
Data Required Time | 0.137 |
From | u_test_gen/Color_cnt_1_s3 |
To | u_test_gen/Color_cnt_1_s3 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 353 | PLL_R | u_pll/rpll_inst/CLKOUTD3 |
0.137 | 0.137 | tNET | RR | 1 | R21C4[1][A] | u_test_gen/Color_cnt_1_s3/CLK |
0.384 | 0.247 | tC2Q | RR | 4 | R21C4[1][A] | u_test_gen/Color_cnt_1_s3/Q |
0.386 | 0.003 | tNET | RR | 1 | R21C4[1][A] | u_test_gen/n685_s3/I2 |
0.662 | 0.276 | tINS | RF | 1 | R21C4[1][A] | u_test_gen/n685_s3/F |
0.662 | 0.000 | tNET | FF | 1 | R21C4[1][A] | u_test_gen/Color_cnt_1_s3/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 353 | PLL_R | u_pll/rpll_inst/CLKOUTD3 |
0.137 | 0.137 | tNET | RR | 1 | R21C4[1][A] | u_test_gen/Color_cnt_1_s3/CLK |
0.137 | 0.000 | tHld | 1 | R21C4[1][A] | u_test_gen/Color_cnt_1_s3 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path12
Path Summary:
Slack | 0.525 |
Data Arrival Time | 0.662 |
Data Required Time | 0.137 |
From | u_test_gen/Color_trig_num_8_s3 |
To | u_test_gen/Color_trig_num_8_s3 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 353 | PLL_R | u_pll/rpll_inst/CLKOUTD3 |
0.137 | 0.137 | tNET | RR | 1 | R23C5[1][A] | u_test_gen/Color_trig_num_8_s3/CLK |
0.384 | 0.247 | tC2Q | RR | 6 | R23C5[1][A] | u_test_gen/Color_trig_num_8_s3/Q |
0.386 | 0.003 | tNET | RR | 1 | R23C5[1][A] | u_test_gen/n607_s4/I2 |
0.662 | 0.276 | tINS | RF | 1 | R23C5[1][A] | u_test_gen/n607_s4/F |
0.662 | 0.000 | tNET | FF | 1 | R23C5[1][A] | u_test_gen/Color_trig_num_8_s3/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 353 | PLL_R | u_pll/rpll_inst/CLKOUTD3 |
0.137 | 0.137 | tNET | RR | 1 | R23C5[1][A] | u_test_gen/Color_trig_num_8_s3/CLK |
0.137 | 0.000 | tHld | 1 | R23C5[1][A] | u_test_gen/Color_trig_num_8_s3 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path13
Path Summary:
Slack | 0.525 |
Data Arrival Time | 0.662 |
Data Required Time | 0.137 |
From | u_test_gen/De_hcnt_3_s3 |
To | u_test_gen/De_hcnt_3_s3 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 353 | PLL_R | u_pll/rpll_inst/CLKOUTD3 |
0.137 | 0.137 | tNET | RR | 1 | R18C4[0][A] | u_test_gen/De_hcnt_3_s3/CLK |
0.384 | 0.247 | tC2Q | RR | 5 | R18C4[0][A] | u_test_gen/De_hcnt_3_s3/Q |
0.386 | 0.003 | tNET | RR | 1 | R18C4[0][A] | u_test_gen/n502_s6/I2 |
0.662 | 0.276 | tINS | RF | 1 | R18C4[0][A] | u_test_gen/n502_s6/F |
0.662 | 0.000 | tNET | FF | 1 | R18C4[0][A] | u_test_gen/De_hcnt_3_s3/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 353 | PLL_R | u_pll/rpll_inst/CLKOUTD3 |
0.137 | 0.137 | tNET | RR | 1 | R18C4[0][A] | u_test_gen/De_hcnt_3_s3/CLK |
0.137 | 0.000 | tHld | 1 | R18C4[0][A] | u_test_gen/De_hcnt_3_s3 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path14
Path Summary:
Slack | 0.525 |
Data Arrival Time | 0.662 |
Data Required Time | 0.137 |
From | u_test_gen/De_vcnt_1_s1 |
To | u_test_gen/De_vcnt_1_s1 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 353 | PLL_R | u_pll/rpll_inst/CLKOUTD3 |
0.137 | 0.137 | tNET | RR | 1 | R22C7[0][A] | u_test_gen/De_vcnt_1_s1/CLK |
0.384 | 0.247 | tC2Q | RR | 4 | R22C7[0][A] | u_test_gen/De_vcnt_1_s1/Q |
0.386 | 0.003 | tNET | RR | 1 | R22C7[0][A] | u_test_gen/n558_s3/I3 |
0.662 | 0.276 | tINS | RF | 1 | R22C7[0][A] | u_test_gen/n558_s3/F |
0.662 | 0.000 | tNET | FF | 1 | R22C7[0][A] | u_test_gen/De_vcnt_1_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 353 | PLL_R | u_pll/rpll_inst/CLKOUTD3 |
0.137 | 0.137 | tNET | RR | 1 | R22C7[0][A] | u_test_gen/De_vcnt_1_s1/CLK |
0.137 | 0.000 | tHld | 1 | R22C7[0][A] | u_test_gen/De_vcnt_1_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path15
Path Summary:
Slack | 0.525 |
Data Arrival Time | 0.662 |
Data Required Time | 0.137 |
From | u_test_gen/De_vcnt_5_s1 |
To | u_test_gen/De_vcnt_5_s1 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 353 | PLL_R | u_pll/rpll_inst/CLKOUTD3 |
0.137 | 0.137 | tNET | RR | 1 | R23C9[1][A] | u_test_gen/De_vcnt_5_s1/CLK |
0.384 | 0.247 | tC2Q | RR | 3 | R23C9[1][A] | u_test_gen/De_vcnt_5_s1/Q |
0.386 | 0.003 | tNET | RR | 1 | R23C9[1][A] | u_test_gen/n554_s2/I3 |
0.662 | 0.276 | tINS | RF | 1 | R23C9[1][A] | u_test_gen/n554_s2/F |
0.662 | 0.000 | tNET | FF | 1 | R23C9[1][A] | u_test_gen/De_vcnt_5_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 353 | PLL_R | u_pll/rpll_inst/CLKOUTD3 |
0.137 | 0.137 | tNET | RR | 1 | R23C9[1][A] | u_test_gen/De_vcnt_5_s1/CLK |
0.137 | 0.000 | tHld | 1 | R23C9[1][A] | u_test_gen/De_vcnt_5_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path16
Path Summary:
Slack | 0.525 |
Data Arrival Time | 0.662 |
Data Required Time | 0.137 |
From | u_test_gen/De_vcnt_7_s1 |
To | u_test_gen/De_vcnt_7_s1 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 353 | PLL_R | u_pll/rpll_inst/CLKOUTD3 |
0.137 | 0.137 | tNET | RR | 1 | R23C9[0][A] | u_test_gen/De_vcnt_7_s1/CLK |
0.384 | 0.247 | tC2Q | RR | 4 | R23C9[0][A] | u_test_gen/De_vcnt_7_s1/Q |
0.386 | 0.003 | tNET | RR | 1 | R23C9[0][A] | u_test_gen/n552_s2/I3 |
0.662 | 0.276 | tINS | RF | 1 | R23C9[0][A] | u_test_gen/n552_s2/F |
0.662 | 0.000 | tNET | FF | 1 | R23C9[0][A] | u_test_gen/De_vcnt_7_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 353 | PLL_R | u_pll/rpll_inst/CLKOUTD3 |
0.137 | 0.137 | tNET | RR | 1 | R23C9[0][A] | u_test_gen/De_vcnt_7_s1/CLK |
0.137 | 0.000 | tHld | 1 | R23C9[0][A] | u_test_gen/De_vcnt_7_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path17
Path Summary:
Slack | 0.525 |
Data Arrival Time | 0.662 |
Data Required Time | 0.137 |
From | u_test_gen/De_vcnt_10_s1 |
To | u_test_gen/De_vcnt_10_s1 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 353 | PLL_R | u_pll/rpll_inst/CLKOUTD3 |
0.137 | 0.137 | tNET | RR | 1 | R22C7[1][A] | u_test_gen/De_vcnt_10_s1/CLK |
0.384 | 0.247 | tC2Q | RR | 3 | R22C7[1][A] | u_test_gen/De_vcnt_10_s1/Q |
0.386 | 0.003 | tNET | RR | 1 | R22C7[1][A] | u_test_gen/n549_s4/I2 |
0.662 | 0.276 | tINS | RF | 1 | R22C7[1][A] | u_test_gen/n549_s4/F |
0.662 | 0.000 | tNET | FF | 1 | R22C7[1][A] | u_test_gen/De_vcnt_10_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 353 | PLL_R | u_pll/rpll_inst/CLKOUTD3 |
0.137 | 0.137 | tNET | RR | 1 | R22C7[1][A] | u_test_gen/De_vcnt_10_s1/CLK |
0.137 | 0.000 | tHld | 1 | R22C7[1][A] | u_test_gen/De_vcnt_10_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path18
Path Summary:
Slack | 0.525 |
Data Arrival Time | 0.662 |
Data Required Time | 0.137 |
From | u_test_gen/H_cnt_0_s0 |
To | u_test_gen/H_cnt_0_s0 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 353 | PLL_R | u_pll/rpll_inst/CLKOUTD3 |
0.137 | 0.137 | tNET | RR | 1 | R18C9[1][A] | u_test_gen/H_cnt_0_s0/CLK |
0.384 | 0.247 | tC2Q | RR | 5 | R18C9[1][A] | u_test_gen/H_cnt_0_s0/Q |
0.386 | 0.003 | tNET | RR | 1 | R18C9[1][A] | u_test_gen/n140_s3/I0 |
0.662 | 0.276 | tINS | RF | 1 | R18C9[1][A] | u_test_gen/n140_s3/F |
0.662 | 0.000 | tNET | FF | 1 | R18C9[1][A] | u_test_gen/H_cnt_0_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 353 | PLL_R | u_pll/rpll_inst/CLKOUTD3 |
0.137 | 0.137 | tNET | RR | 1 | R18C9[1][A] | u_test_gen/H_cnt_0_s0/CLK |
0.137 | 0.000 | tHld | 1 | R18C9[1][A] | u_test_gen/H_cnt_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path19
Path Summary:
Slack | 0.525 |
Data Arrival Time | 0.662 |
Data Required Time | 0.137 |
From | u_test_gen/H_cnt_4_s0 |
To | u_test_gen/H_cnt_4_s0 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 353 | PLL_R | u_pll/rpll_inst/CLKOUTD3 |
0.137 | 0.137 | tNET | RR | 1 | R18C8[1][A] | u_test_gen/H_cnt_4_s0/CLK |
0.384 | 0.247 | tC2Q | RR | 4 | R18C8[1][A] | u_test_gen/H_cnt_4_s0/Q |
0.386 | 0.003 | tNET | RR | 1 | R18C8[1][A] | u_test_gen/n136_s2/I1 |
0.662 | 0.276 | tINS | RF | 1 | R18C8[1][A] | u_test_gen/n136_s2/F |
0.662 | 0.000 | tNET | FF | 1 | R18C8[1][A] | u_test_gen/H_cnt_4_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 353 | PLL_R | u_pll/rpll_inst/CLKOUTD3 |
0.137 | 0.137 | tNET | RR | 1 | R18C8[1][A] | u_test_gen/H_cnt_4_s0/CLK |
0.137 | 0.000 | tHld | 1 | R18C8[1][A] | u_test_gen/H_cnt_4_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path20
Path Summary:
Slack | 0.525 |
Data Arrival Time | 0.662 |
Data Required Time | 0.137 |
From | u_test_gen/H_cnt_9_s0 |
To | u_test_gen/H_cnt_9_s0 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 353 | PLL_R | u_pll/rpll_inst/CLKOUTD3 |
0.137 | 0.137 | tNET | RR | 1 | R18C8[0][A] | u_test_gen/H_cnt_9_s0/CLK |
0.384 | 0.247 | tC2Q | RR | 5 | R18C8[0][A] | u_test_gen/H_cnt_9_s0/Q |
0.386 | 0.003 | tNET | RR | 1 | R18C8[0][A] | u_test_gen/n131_s2/I1 |
0.662 | 0.276 | tINS | RF | 1 | R18C8[0][A] | u_test_gen/n131_s2/F |
0.662 | 0.000 | tNET | FF | 1 | R18C8[0][A] | u_test_gen/H_cnt_9_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 353 | PLL_R | u_pll/rpll_inst/CLKOUTD3 |
0.137 | 0.137 | tNET | RR | 1 | R18C8[0][A] | u_test_gen/H_cnt_9_s0/CLK |
0.137 | 0.000 | tHld | 1 | R18C8[0][A] | u_test_gen/H_cnt_9_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Hold Analysis Report[2]:
Report Command:report_timing -hold -from_clock [get_clocks {byte_clk}] -max_paths 20 -max_common_paths 1
Path1
Path Summary:
Slack | 0.355 |
Data Arrival Time | 0.418 |
Data Required Time | 0.064 |
From | u_la0_top/u_ao_mem_ctrl/data_reg_20_s0 |
To | u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R9C8[0][B] | u_la0_top/u_ao_mem_ctrl/data_reg_20_s0/CLK |
0.247 | 0.247 | tC2Q | RF | 1 | R9C8[0][B] | u_la0_top/u_ao_mem_ctrl/data_reg_20_s0/Q |
0.418 | 0.171 | tNET | FF | 1 | BSRAM_R10[1] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[2] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | BSRAM_R10[1] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA |
0.064 | 0.064 | tHld | 1 | BSRAM_R10[1] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.171, 40.960%; tC2Q: 0.247, 59.040% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path2
Path Summary:
Slack | 0.355 |
Data Arrival Time | 0.418 |
Data Required Time | 0.064 |
From | u_la0_top/u_ao_mem_ctrl/data_reg_11_s0 |
To | u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R9C6[2][B] | u_la0_top/u_ao_mem_ctrl/data_reg_11_s0/CLK |
0.247 | 0.247 | tC2Q | RF | 1 | R9C6[2][B] | u_la0_top/u_ao_mem_ctrl/data_reg_11_s0/Q |
0.418 | 0.171 | tNET | FF | 1 | BSRAM_R10[0] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[11] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | BSRAM_R10[0] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA |
0.064 | 0.064 | tHld | 1 | BSRAM_R10[0] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.171, 40.960%; tC2Q: 0.247, 59.040% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path3
Path Summary:
Slack | 0.355 |
Data Arrival Time | 0.555 |
Data Required Time | 0.201 |
From | u_dsi_tx/u_tx/u_dsi_tx/rHsd_32_s0 |
To | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_0_s |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.137 | 0.137 | tNET | RR | 1 | R9C34[0][A] | u_dsi_tx/u_tx/u_dsi_tx/rHsd_32_s0/CLK |
0.384 | 0.247 | tC2Q | RF | 1 | R9C34[0][A] | u_dsi_tx/u_tx/u_dsi_tx/rHsd_32_s0/Q |
0.555 | 0.171 | tNET | FF | 1 | BSRAM_R10[7] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_0_s/DI[32] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.137 | 0.137 | tNET | RR | 1 | BSRAM_R10[7] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_0_s/CLKA |
0.201 | 0.064 | tHld | 1 | BSRAM_R10[7] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_0_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.171, 40.960%; tC2Q: 0.247, 59.040% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path4
Path Summary:
Slack | 0.355 |
Data Arrival Time | 0.555 |
Data Required Time | 0.201 |
From | u_dsi_tx/u_tx/u_dsi_tx/rHsd_1_s0 |
To | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_0_s |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.137 | 0.137 | tNET | RR | 1 | R11C32[0][A] | u_dsi_tx/u_tx/u_dsi_tx/rHsd_1_s0/CLK |
0.384 | 0.247 | tC2Q | RF | 1 | R11C32[0][A] | u_dsi_tx/u_tx/u_dsi_tx/rHsd_1_s0/Q |
0.555 | 0.171 | tNET | FF | 1 | BSRAM_R10[7] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_0_s/DI[1] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.137 | 0.137 | tNET | RR | 1 | BSRAM_R10[7] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_0_s/CLKA |
0.201 | 0.064 | tHld | 1 | BSRAM_R10[7] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_0_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.171, 40.960%; tC2Q: 0.247, 59.040% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path5
Path Summary:
Slack | 0.384 |
Data Arrival Time | 0.384 |
Data Required Time | 0.000 |
From | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/rHsDataEn_s0 |
To | u_la0_top/u_ao_match_0/trig_dly_in_0_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.137 | 0.137 | tNET | RR | 1 | R20C40[1][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/rHsDataEn_s0/CLK |
0.384 | 0.247 | tC2Q | RR | 14 | R20C40[1][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/rHsDataEn_s0/Q |
0.384 | 0.000 | tNET | RR | 1 | R9C8[1][A] | u_la0_top/u_ao_match_0/trig_dly_in_0_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R9C8[1][A] | u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLK |
0.000 | 0.000 | tHld | 1 | R9C8[1][A] | u_la0_top/u_ao_match_0/trig_dly_in_0_s0 |
Path Statistics:
Clock Skew | -0.137 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.247, 100.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path6
Path Summary:
Slack | 0.384 |
Data Arrival Time | 0.384 |
Data Required Time | 0.000 |
From | hs_data0_r_15_s0 |
To | u_la0_top/u_ao_mem_ctrl/data_reg_dly_70_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.137 | 0.137 | tNET | RR | 1 | R23C14[0][A] | hs_data0_r_15_s0/CLK |
0.384 | 0.247 | tC2Q | RR | 2 | R23C14[0][A] | hs_data0_r_15_s0/Q |
0.384 | 0.000 | tNET | RR | 1 | R12C7[0][A] | u_la0_top/u_ao_mem_ctrl/data_reg_dly_70_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R12C7[0][A] | u_la0_top/u_ao_mem_ctrl/data_reg_dly_70_s0/CLK |
0.000 | 0.000 | tHld | 1 | R12C7[0][A] | u_la0_top/u_ao_mem_ctrl/data_reg_dly_70_s0 |
Path Statistics:
Clock Skew | -0.137 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.247, 100.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path7
Path Summary:
Slack | 0.384 |
Data Arrival Time | 0.384 |
Data Required Time | 0.000 |
From | lp_data0_r_0_s0 |
To | u_la0_top/u_ao_mem_ctrl/data_reg_dly_0_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.137 | 0.137 | tNET | RR | 1 | R22C11[0][A] | lp_data0_r_0_s0/CLK |
0.384 | 0.247 | tC2Q | RR | 2 | R22C11[0][A] | lp_data0_r_0_s0/Q |
0.384 | 0.000 | tNET | RR | 1 | R11C14[0][B] | u_la0_top/u_ao_mem_ctrl/data_reg_dly_0_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R11C14[0][B] | u_la0_top/u_ao_mem_ctrl/data_reg_dly_0_s0/CLK |
0.000 | 0.000 | tHld | 1 | R11C14[0][B] | u_la0_top/u_ao_mem_ctrl/data_reg_dly_0_s0 |
Path Statistics:
Clock Skew | -0.137 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.247, 100.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path8
Path Summary:
Slack | 0.384 |
Data Arrival Time | 0.384 |
Data Required Time | 0.000 |
From | lp_data0_r_1_s0 |
To | u_la0_top/u_ao_mem_ctrl/data_reg_dly_1_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.137 | 0.137 | tNET | RR | 1 | R22C11[0][B] | lp_data0_r_1_s0/CLK |
0.384 | 0.247 | tC2Q | RR | 2 | R22C11[0][B] | lp_data0_r_1_s0/Q |
0.384 | 0.000 | tNET | RR | 1 | R11C14[1][A] | u_la0_top/u_ao_mem_ctrl/data_reg_dly_1_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R11C14[1][A] | u_la0_top/u_ao_mem_ctrl/data_reg_dly_1_s0/CLK |
0.000 | 0.000 | tHld | 1 | R11C14[1][A] | u_la0_top/u_ao_mem_ctrl/data_reg_dly_1_s0 |
Path Statistics:
Clock Skew | -0.137 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.247, 100.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path9
Path Summary:
Slack | 0.384 |
Data Arrival Time | 0.384 |
Data Required Time | 0.000 |
From | lp_clk_r_0_s0 |
To | u_la0_top/u_ao_mem_ctrl/data_reg_dly_2_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.137 | 0.137 | tNET | RR | 1 | R20C12[0][B] | lp_clk_r_0_s0/CLK |
0.384 | 0.247 | tC2Q | RR | 2 | R20C12[0][B] | lp_clk_r_0_s0/Q |
0.384 | 0.000 | tNET | RR | 1 | R11C11[1][A] | u_la0_top/u_ao_mem_ctrl/data_reg_dly_2_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R11C11[1][A] | u_la0_top/u_ao_mem_ctrl/data_reg_dly_2_s0/CLK |
0.000 | 0.000 | tHld | 1 | R11C11[1][A] | u_la0_top/u_ao_mem_ctrl/data_reg_dly_2_s0 |
Path Statistics:
Clock Skew | -0.137 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.247, 100.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path10
Path Summary:
Slack | 0.384 |
Data Arrival Time | 0.384 |
Data Required Time | 0.000 |
From | lp_clk_r_1_s0 |
To | u_la0_top/u_ao_mem_ctrl/data_reg_dly_3_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.137 | 0.137 | tNET | RR | 1 | R20C12[0][A] | lp_clk_r_1_s0/CLK |
0.384 | 0.247 | tC2Q | RR | 2 | R20C12[0][A] | lp_clk_r_1_s0/Q |
0.384 | 0.000 | tNET | RR | 1 | R11C11[1][B] | u_la0_top/u_ao_mem_ctrl/data_reg_dly_3_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R11C11[1][B] | u_la0_top/u_ao_mem_ctrl/data_reg_dly_3_s0/CLK |
0.000 | 0.000 | tHld | 1 | R11C11[1][B] | u_la0_top/u_ao_mem_ctrl/data_reg_dly_3_s0 |
Path Statistics:
Clock Skew | -0.137 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.247, 100.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path11
Path Summary:
Slack | 0.384 |
Data Arrival Time | 0.384 |
Data Required Time | 0.000 |
From | u_p2b/u_p2b_0/GEN_FOR_I[1].u_pulse_dly/rPulse_s0 |
To | u_la0_top/u_ao_mem_ctrl/data_reg_dly_4_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.137 | 0.137 | tNET | RR | 1 | R14C5[2][B] | u_p2b/u_p2b_0/GEN_FOR_I[1].u_pulse_dly/rPulse_s0/CLK |
0.384 | 0.247 | tC2Q | RR | 2 | R14C5[2][B] | u_p2b/u_p2b_0/GEN_FOR_I[1].u_pulse_dly/rPulse_s0/Q |
0.384 | 0.000 | tNET | RR | 1 | R13C3[0][B] | u_la0_top/u_ao_mem_ctrl/data_reg_dly_4_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R13C3[0][B] | u_la0_top/u_ao_mem_ctrl/data_reg_dly_4_s0/CLK |
0.000 | 0.000 | tHld | 1 | R13C3[0][B] | u_la0_top/u_ao_mem_ctrl/data_reg_dly_4_s0 |
Path Statistics:
Clock Skew | -0.137 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.247, 100.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path12
Path Summary:
Slack | 0.384 |
Data Arrival Time | 0.384 |
Data Required Time | 0.000 |
From | hs_data_en_r_s0 |
To | u_la0_top/u_ao_mem_ctrl/data_reg_dly_5_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.137 | 0.137 | tNET | RR | 1 | R20C12[2][A] | hs_data_en_r_s0/CLK |
0.384 | 0.247 | tC2Q | RR | 2 | R20C12[2][A] | hs_data_en_r_s0/Q |
0.384 | 0.000 | tNET | RR | 1 | R11C11[2][A] | u_la0_top/u_ao_mem_ctrl/data_reg_dly_5_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R11C11[2][A] | u_la0_top/u_ao_mem_ctrl/data_reg_dly_5_s0/CLK |
0.000 | 0.000 | tHld | 1 | R11C11[2][A] | u_la0_top/u_ao_mem_ctrl/data_reg_dly_5_s0 |
Path Statistics:
Clock Skew | -0.137 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.247, 100.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path13
Path Summary:
Slack | 0.384 |
Data Arrival Time | 0.384 |
Data Required Time | 0.000 |
From | hs_clk_en_r_s0 |
To | u_la0_top/u_ao_mem_ctrl/data_reg_dly_6_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.137 | 0.137 | tNET | RR | 1 | R20C12[1][B] | hs_clk_en_r_s0/CLK |
0.384 | 0.247 | tC2Q | RR | 2 | R20C12[1][B] | hs_clk_en_r_s0/Q |
0.384 | 0.000 | tNET | RR | 1 | R11C11[2][B] | u_la0_top/u_ao_mem_ctrl/data_reg_dly_6_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R11C11[2][B] | u_la0_top/u_ao_mem_ctrl/data_reg_dly_6_s0/CLK |
0.000 | 0.000 | tHld | 1 | R11C11[2][B] | u_la0_top/u_ao_mem_ctrl/data_reg_dly_6_s0 |
Path Statistics:
Clock Skew | -0.137 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.247, 100.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path14
Path Summary:
Slack | 0.384 |
Data Arrival Time | 0.384 |
Data Required Time | 0.000 |
From | hs_data3_r_0_s0 |
To | u_la0_top/u_ao_mem_ctrl/data_reg_dly_7_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.137 | 0.137 | tNET | RR | 1 | R24C13[0][B] | hs_data3_r_0_s0/CLK |
0.384 | 0.247 | tC2Q | RR | 2 | R24C13[0][B] | hs_data3_r_0_s0/Q |
0.384 | 0.000 | tNET | RR | 1 | R12C14[0][A] | u_la0_top/u_ao_mem_ctrl/data_reg_dly_7_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R12C14[0][A] | u_la0_top/u_ao_mem_ctrl/data_reg_dly_7_s0/CLK |
0.000 | 0.000 | tHld | 1 | R12C14[0][A] | u_la0_top/u_ao_mem_ctrl/data_reg_dly_7_s0 |
Path Statistics:
Clock Skew | -0.137 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.247, 100.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path15
Path Summary:
Slack | 0.384 |
Data Arrival Time | 0.384 |
Data Required Time | 0.000 |
From | hs_data3_r_1_s0 |
To | u_la0_top/u_ao_mem_ctrl/data_reg_dly_8_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.137 | 0.137 | tNET | RR | 1 | R24C12[1][B] | hs_data3_r_1_s0/CLK |
0.384 | 0.247 | tC2Q | RR | 2 | R24C12[1][B] | hs_data3_r_1_s0/Q |
0.384 | 0.000 | tNET | RR | 1 | R12C14[0][B] | u_la0_top/u_ao_mem_ctrl/data_reg_dly_8_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R12C14[0][B] | u_la0_top/u_ao_mem_ctrl/data_reg_dly_8_s0/CLK |
0.000 | 0.000 | tHld | 1 | R12C14[0][B] | u_la0_top/u_ao_mem_ctrl/data_reg_dly_8_s0 |
Path Statistics:
Clock Skew | -0.137 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.247, 100.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path16
Path Summary:
Slack | 0.384 |
Data Arrival Time | 0.384 |
Data Required Time | 0.000 |
From | hs_data3_r_2_s0 |
To | u_la0_top/u_ao_mem_ctrl/data_reg_dly_9_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.137 | 0.137 | tNET | RR | 1 | R24C12[0][B] | hs_data3_r_2_s0/CLK |
0.384 | 0.247 | tC2Q | RR | 2 | R24C12[0][B] | hs_data3_r_2_s0/Q |
0.384 | 0.000 | tNET | RR | 1 | R11C10[0][A] | u_la0_top/u_ao_mem_ctrl/data_reg_dly_9_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R11C10[0][A] | u_la0_top/u_ao_mem_ctrl/data_reg_dly_9_s0/CLK |
0.000 | 0.000 | tHld | 1 | R11C10[0][A] | u_la0_top/u_ao_mem_ctrl/data_reg_dly_9_s0 |
Path Statistics:
Clock Skew | -0.137 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.247, 100.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path17
Path Summary:
Slack | 0.384 |
Data Arrival Time | 0.384 |
Data Required Time | 0.000 |
From | hs_data3_r_3_s0 |
To | u_la0_top/u_ao_mem_ctrl/data_reg_dly_10_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.137 | 0.137 | tNET | RR | 1 | R24C12[0][A] | hs_data3_r_3_s0/CLK |
0.384 | 0.247 | tC2Q | RR | 2 | R24C12[0][A] | hs_data3_r_3_s0/Q |
0.384 | 0.000 | tNET | RR | 1 | R11C12[1][A] | u_la0_top/u_ao_mem_ctrl/data_reg_dly_10_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R11C12[1][A] | u_la0_top/u_ao_mem_ctrl/data_reg_dly_10_s0/CLK |
0.000 | 0.000 | tHld | 1 | R11C12[1][A] | u_la0_top/u_ao_mem_ctrl/data_reg_dly_10_s0 |
Path Statistics:
Clock Skew | -0.137 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.247, 100.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path18
Path Summary:
Slack | 0.384 |
Data Arrival Time | 0.384 |
Data Required Time | 0.000 |
From | hs_data3_r_4_s0 |
To | u_la0_top/u_ao_mem_ctrl/data_reg_dly_11_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.137 | 0.137 | tNET | RR | 1 | R24C13[2][B] | hs_data3_r_4_s0/CLK |
0.384 | 0.247 | tC2Q | RR | 2 | R24C13[2][B] | hs_data3_r_4_s0/Q |
0.384 | 0.000 | tNET | RR | 1 | R12C14[1][A] | u_la0_top/u_ao_mem_ctrl/data_reg_dly_11_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R12C14[1][A] | u_la0_top/u_ao_mem_ctrl/data_reg_dly_11_s0/CLK |
0.000 | 0.000 | tHld | 1 | R12C14[1][A] | u_la0_top/u_ao_mem_ctrl/data_reg_dly_11_s0 |
Path Statistics:
Clock Skew | -0.137 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.247, 100.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path19
Path Summary:
Slack | 0.384 |
Data Arrival Time | 0.384 |
Data Required Time | 0.000 |
From | hs_data3_r_5_s0 |
To | u_la0_top/u_ao_mem_ctrl/data_reg_dly_12_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.137 | 0.137 | tNET | RR | 1 | R24C13[2][A] | hs_data3_r_5_s0/CLK |
0.384 | 0.247 | tC2Q | RR | 2 | R24C13[2][A] | hs_data3_r_5_s0/Q |
0.384 | 0.000 | tNET | RR | 1 | R12C14[1][B] | u_la0_top/u_ao_mem_ctrl/data_reg_dly_12_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R12C14[1][B] | u_la0_top/u_ao_mem_ctrl/data_reg_dly_12_s0/CLK |
0.000 | 0.000 | tHld | 1 | R12C14[1][B] | u_la0_top/u_ao_mem_ctrl/data_reg_dly_12_s0 |
Path Statistics:
Clock Skew | -0.137 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.247, 100.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path20
Path Summary:
Slack | 0.384 |
Data Arrival Time | 0.384 |
Data Required Time | 0.000 |
From | hs_data3_r_6_s0 |
To | u_la0_top/u_ao_mem_ctrl/data_reg_dly_13_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.137 | 0.137 | tNET | RR | 1 | R24C13[1][B] | hs_data3_r_6_s0/CLK |
0.384 | 0.247 | tC2Q | RR | 2 | R24C13[1][B] | hs_data3_r_6_s0/Q |
0.384 | 0.000 | tNET | RR | 1 | R12C14[2][A] | u_la0_top/u_ao_mem_ctrl/data_reg_dly_13_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R12C14[2][A] | u_la0_top/u_ao_mem_ctrl/data_reg_dly_13_s0/CLK |
0.000 | 0.000 | tHld | 1 | R12C14[2][A] | u_la0_top/u_ao_mem_ctrl/data_reg_dly_13_s0 |
Path Statistics:
Clock Skew | -0.137 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.247, 100.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Recovery Analysis Report
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 16.141 |
Data Arrival Time | 2.650 |
Data Required Time | 18.791 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R16C3[0][A] | u_la0_top/rst_ao_s0/CLK |
0.340 | 0.340 | tC2Q | RF | 54 | R16C3[0][A] | u_la0_top/rst_ao_s0/Q |
2.650 | 2.310 | tNET | FF | 1 | R3C10[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
18.824 | 18.824 | active clock edge time | ||||
18.824 | 0.000 | byte_clk | ||||
18.824 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
18.824 | 0.000 | tNET | RR | 1 | R3C10[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK |
18.791 | -0.032 | tSu | 1 | R3C10[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 18.824 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.310, 87.184%; tC2Q: 0.340, 12.816% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path2
Path Summary:
Slack | 16.346 |
Data Arrival Time | 2.445 |
Data Required Time | 18.791 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R16C3[0][A] | u_la0_top/rst_ao_s0/CLK |
0.340 | 0.340 | tC2Q | RF | 54 | R16C3[0][A] | u_la0_top/rst_ao_s0/Q |
2.445 | 2.106 | tNET | FF | 1 | R3C11[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
18.824 | 18.824 | active clock edge time | ||||
18.824 | 0.000 | byte_clk | ||||
18.824 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
18.824 | 0.000 | tNET | RR | 1 | R3C11[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK |
18.791 | -0.032 | tSu | 1 | R3C11[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 18.824 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.106, 86.111%; tC2Q: 0.340, 13.889% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path3
Path Summary:
Slack | 16.346 |
Data Arrival Time | 2.445 |
Data Required Time | 18.791 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R16C3[0][A] | u_la0_top/rst_ao_s0/CLK |
0.340 | 0.340 | tC2Q | RF | 54 | R16C3[0][A] | u_la0_top/rst_ao_s0/Q |
2.445 | 2.106 | tNET | FF | 1 | R3C11[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
18.824 | 18.824 | active clock edge time | ||||
18.824 | 0.000 | byte_clk | ||||
18.824 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
18.824 | 0.000 | tNET | RR | 1 | R3C11[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK |
18.791 | -0.032 | tSu | 1 | R3C11[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 18.824 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.106, 86.111%; tC2Q: 0.340, 13.889% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path4
Path Summary:
Slack | 16.346 |
Data Arrival Time | 2.445 |
Data Required Time | 18.791 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R16C3[0][A] | u_la0_top/rst_ao_s0/CLK |
0.340 | 0.340 | tC2Q | RF | 54 | R16C3[0][A] | u_la0_top/rst_ao_s0/Q |
2.445 | 2.106 | tNET | FF | 1 | R3C11[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
18.824 | 18.824 | active clock edge time | ||||
18.824 | 0.000 | byte_clk | ||||
18.824 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
18.824 | 0.000 | tNET | RR | 1 | R3C11[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK |
18.791 | -0.032 | tSu | 1 | R3C11[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 18.824 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.106, 86.111%; tC2Q: 0.340, 13.889% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path5
Path Summary:
Slack | 16.346 |
Data Arrival Time | 2.445 |
Data Required Time | 18.791 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R16C3[0][A] | u_la0_top/rst_ao_s0/CLK |
0.340 | 0.340 | tC2Q | RF | 54 | R16C3[0][A] | u_la0_top/rst_ao_s0/Q |
2.445 | 2.106 | tNET | FF | 1 | R3C11[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
18.824 | 18.824 | active clock edge time | ||||
18.824 | 0.000 | byte_clk | ||||
18.824 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
18.824 | 0.000 | tNET | RR | 1 | R3C11[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK |
18.791 | -0.032 | tSu | 1 | R3C11[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 18.824 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.106, 86.111%; tC2Q: 0.340, 13.889% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path6
Path Summary:
Slack | 16.346 |
Data Arrival Time | 2.445 |
Data Required Time | 18.791 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R16C3[0][A] | u_la0_top/rst_ao_s0/CLK |
0.340 | 0.340 | tC2Q | RF | 54 | R16C3[0][A] | u_la0_top/rst_ao_s0/Q |
2.445 | 2.106 | tNET | FF | 1 | R3C11[2][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
18.824 | 18.824 | active clock edge time | ||||
18.824 | 0.000 | byte_clk | ||||
18.824 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
18.824 | 0.000 | tNET | RR | 1 | R3C11[2][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK |
18.791 | -0.032 | tSu | 1 | R3C11[2][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 18.824 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.106, 86.111%; tC2Q: 0.340, 13.889% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path7
Path Summary:
Slack | 16.606 |
Data Arrival Time | 2.186 |
Data Required Time | 18.791 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_mem_ctrl/capture_length_1_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R16C3[0][A] | u_la0_top/rst_ao_s0/CLK |
0.340 | 0.340 | tC2Q | RF | 54 | R16C3[0][A] | u_la0_top/rst_ao_s0/Q |
2.186 | 1.846 | tNET | FF | 1 | R4C12[0][A] | u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
18.824 | 18.824 | active clock edge time | ||||
18.824 | 0.000 | byte_clk | ||||
18.824 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
18.824 | 0.000 | tNET | RR | 1 | R4C12[0][A] | u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLK |
18.791 | -0.032 | tSu | 1 | R4C12[0][A] | u_la0_top/u_ao_mem_ctrl/capture_length_1_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 18.824 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.846, 84.461%; tC2Q: 0.340, 15.539% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path8
Path Summary:
Slack | 16.606 |
Data Arrival Time | 2.186 |
Data Required Time | 18.791 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_mem_ctrl/capture_length_2_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R16C3[0][A] | u_la0_top/rst_ao_s0/CLK |
0.340 | 0.340 | tC2Q | RF | 54 | R16C3[0][A] | u_la0_top/rst_ao_s0/Q |
2.186 | 1.846 | tNET | FF | 1 | R4C12[0][B] | u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
18.824 | 18.824 | active clock edge time | ||||
18.824 | 0.000 | byte_clk | ||||
18.824 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
18.824 | 0.000 | tNET | RR | 1 | R4C12[0][B] | u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLK |
18.791 | -0.032 | tSu | 1 | R4C12[0][B] | u_la0_top/u_ao_mem_ctrl/capture_length_2_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 18.824 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.846, 84.461%; tC2Q: 0.340, 15.539% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path9
Path Summary:
Slack | 16.610 |
Data Arrival Time | 2.181 |
Data Required Time | 18.791 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R16C3[0][A] | u_la0_top/rst_ao_s0/CLK |
0.340 | 0.340 | tC2Q | RF | 54 | R16C3[0][A] | u_la0_top/rst_ao_s0/Q |
2.181 | 1.841 | tNET | FF | 1 | R4C7[1][A] | u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
18.824 | 18.824 | active clock edge time | ||||
18.824 | 0.000 | byte_clk | ||||
18.824 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
18.824 | 0.000 | tNET | RR | 1 | R4C7[1][A] | u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLK |
18.791 | -0.032 | tSu | 1 | R4C7[1][A] | u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 18.824 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.841, 84.429%; tC2Q: 0.340, 15.571% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path10
Path Summary:
Slack | 16.610 |
Data Arrival Time | 2.181 |
Data Required Time | 18.791 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R16C3[0][A] | u_la0_top/rst_ao_s0/CLK |
0.340 | 0.340 | tC2Q | RF | 54 | R16C3[0][A] | u_la0_top/rst_ao_s0/Q |
2.181 | 1.841 | tNET | FF | 1 | R4C8[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
18.824 | 18.824 | active clock edge time | ||||
18.824 | 0.000 | byte_clk | ||||
18.824 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
18.824 | 0.000 | tNET | RR | 1 | R4C8[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK |
18.791 | -0.032 | tSu | 1 | R4C8[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 18.824 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.841, 84.429%; tC2Q: 0.340, 15.571% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path11
Path Summary:
Slack | 16.610 |
Data Arrival Time | 2.181 |
Data Required Time | 18.791 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/internal_reg_start_syn_0_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R16C3[0][A] | u_la0_top/rst_ao_s0/CLK |
0.340 | 0.340 | tC2Q | RF | 54 | R16C3[0][A] | u_la0_top/rst_ao_s0/Q |
2.181 | 1.841 | tNET | FF | 1 | R4C5[1][A] | u_la0_top/internal_reg_start_syn_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
18.824 | 18.824 | active clock edge time | ||||
18.824 | 0.000 | byte_clk | ||||
18.824 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
18.824 | 0.000 | tNET | RR | 1 | R4C5[1][A] | u_la0_top/internal_reg_start_syn_0_s0/CLK |
18.791 | -0.032 | tSu | 1 | R4C5[1][A] | u_la0_top/internal_reg_start_syn_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 18.824 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.841, 84.429%; tC2Q: 0.340, 15.571% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path12
Path Summary:
Slack | 16.851 |
Data Arrival Time | 1.941 |
Data Required Time | 18.791 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_mem_ctrl/capture_length_7_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R16C3[0][A] | u_la0_top/rst_ao_s0/CLK |
0.340 | 0.340 | tC2Q | RF | 54 | R16C3[0][A] | u_la0_top/rst_ao_s0/Q |
1.941 | 1.601 | tNET | FF | 1 | R11C13[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
18.824 | 18.824 | active clock edge time | ||||
18.824 | 0.000 | byte_clk | ||||
18.824 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
18.824 | 0.000 | tNET | RR | 1 | R11C13[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLK |
18.791 | -0.032 | tSu | 1 | R11C13[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_7_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 18.824 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.601, 82.500%; tC2Q: 0.340, 17.500% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path13
Path Summary:
Slack | 16.851 |
Data Arrival Time | 1.941 |
Data Required Time | 18.791 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/capture_window_sel_4_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R16C3[0][A] | u_la0_top/rst_ao_s0/CLK |
0.340 | 0.340 | tC2Q | RF | 54 | R16C3[0][A] | u_la0_top/rst_ao_s0/Q |
1.941 | 1.601 | tNET | FF | 1 | R9C6[0][A] | u_la0_top/capture_window_sel_4_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
18.824 | 18.824 | active clock edge time | ||||
18.824 | 0.000 | byte_clk | ||||
18.824 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
18.824 | 0.000 | tNET | RR | 1 | R9C6[0][A] | u_la0_top/capture_window_sel_4_s1/CLK |
18.791 | -0.032 | tSu | 1 | R9C6[0][A] | u_la0_top/capture_window_sel_4_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 18.824 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.601, 82.500%; tC2Q: 0.340, 17.500% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path14
Path Summary:
Slack | 16.851 |
Data Arrival Time | 1.941 |
Data Required Time | 18.791 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/capture_window_sel_5_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R16C3[0][A] | u_la0_top/rst_ao_s0/CLK |
0.340 | 0.340 | tC2Q | RF | 54 | R16C3[0][A] | u_la0_top/rst_ao_s0/Q |
1.941 | 1.601 | tNET | FF | 1 | R9C6[0][B] | u_la0_top/capture_window_sel_5_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
18.824 | 18.824 | active clock edge time | ||||
18.824 | 0.000 | byte_clk | ||||
18.824 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
18.824 | 0.000 | tNET | RR | 1 | R9C6[0][B] | u_la0_top/capture_window_sel_5_s1/CLK |
18.791 | -0.032 | tSu | 1 | R9C6[0][B] | u_la0_top/capture_window_sel_5_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 18.824 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.601, 82.500%; tC2Q: 0.340, 17.500% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path15
Path Summary:
Slack | 16.860 |
Data Arrival Time | 1.932 |
Data Required Time | 18.791 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_mem_ctrl/capture_length_3_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R16C3[0][A] | u_la0_top/rst_ao_s0/CLK |
0.340 | 0.340 | tC2Q | RF | 54 | R16C3[0][A] | u_la0_top/rst_ao_s0/Q |
1.932 | 1.592 | tNET | FF | 1 | R9C9[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
18.824 | 18.824 | active clock edge time | ||||
18.824 | 0.000 | byte_clk | ||||
18.824 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
18.824 | 0.000 | tNET | RR | 1 | R9C9[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/CLK |
18.791 | -0.032 | tSu | 1 | R9C9[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_3_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 18.824 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.592, 82.420%; tC2Q: 0.340, 17.580% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path16
Path Summary:
Slack | 16.860 |
Data Arrival Time | 1.932 |
Data Required Time | 18.791 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_mem_ctrl/capture_length_4_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R16C3[0][A] | u_la0_top/rst_ao_s0/CLK |
0.340 | 0.340 | tC2Q | RF | 54 | R16C3[0][A] | u_la0_top/rst_ao_s0/Q |
1.932 | 1.592 | tNET | FF | 1 | R9C9[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
18.824 | 18.824 | active clock edge time | ||||
18.824 | 0.000 | byte_clk | ||||
18.824 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
18.824 | 0.000 | tNET | RR | 1 | R9C9[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLK |
18.791 | -0.032 | tSu | 1 | R9C9[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_4_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 18.824 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.592, 82.420%; tC2Q: 0.340, 17.580% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path17
Path Summary:
Slack | 16.860 |
Data Arrival Time | 1.932 |
Data Required Time | 18.791 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_mem_ctrl/capture_length_5_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R16C3[0][A] | u_la0_top/rst_ao_s0/CLK |
0.340 | 0.340 | tC2Q | RF | 54 | R16C3[0][A] | u_la0_top/rst_ao_s0/Q |
1.932 | 1.592 | tNET | FF | 1 | R9C9[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
18.824 | 18.824 | active clock edge time | ||||
18.824 | 0.000 | byte_clk | ||||
18.824 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
18.824 | 0.000 | tNET | RR | 1 | R9C9[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLK |
18.791 | -0.032 | tSu | 1 | R9C9[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_5_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 18.824 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.592, 82.420%; tC2Q: 0.340, 17.580% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path18
Path Summary:
Slack | 16.860 |
Data Arrival Time | 1.932 |
Data Required Time | 18.791 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_mem_ctrl/capture_length_8_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R16C3[0][A] | u_la0_top/rst_ao_s0/CLK |
0.340 | 0.340 | tC2Q | RF | 54 | R16C3[0][A] | u_la0_top/rst_ao_s0/Q |
1.932 | 1.592 | tNET | FF | 1 | R9C9[2][A] | u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
18.824 | 18.824 | active clock edge time | ||||
18.824 | 0.000 | byte_clk | ||||
18.824 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
18.824 | 0.000 | tNET | RR | 1 | R9C9[2][A] | u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLK |
18.791 | -0.032 | tSu | 1 | R9C9[2][A] | u_la0_top/u_ao_mem_ctrl/capture_length_8_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 18.824 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.592, 82.420%; tC2Q: 0.340, 17.580% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path19
Path Summary:
Slack | 16.864 |
Data Arrival Time | 1.927 |
Data Required Time | 18.791 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_match_0/trig_dly_0_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R16C3[0][A] | u_la0_top/rst_ao_s0/CLK |
0.340 | 0.340 | tC2Q | RF | 54 | R16C3[0][A] | u_la0_top/rst_ao_s0/Q |
1.927 | 1.588 | tNET | FF | 1 | R9C8[1][B] | u_la0_top/u_ao_match_0/trig_dly_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
18.824 | 18.824 | active clock edge time | ||||
18.824 | 0.000 | byte_clk | ||||
18.824 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
18.824 | 0.000 | tNET | RR | 1 | R9C8[1][B] | u_la0_top/u_ao_match_0/trig_dly_0_s0/CLK |
18.791 | -0.032 | tSu | 1 | R9C8[1][B] | u_la0_top/u_ao_match_0/trig_dly_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 18.824 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.588, 82.378%; tC2Q: 0.340, 17.622% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path20
Path Summary:
Slack | 16.864 |
Data Arrival Time | 1.927 |
Data Required Time | 18.791 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_match_0/trig_dly_in_0_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R16C3[0][A] | u_la0_top/rst_ao_s0/CLK |
0.340 | 0.340 | tC2Q | RF | 54 | R16C3[0][A] | u_la0_top/rst_ao_s0/Q |
1.927 | 1.588 | tNET | FF | 1 | R9C8[1][A] | u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
18.824 | 18.824 | active clock edge time | ||||
18.824 | 0.000 | byte_clk | ||||
18.824 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
18.824 | 0.000 | tNET | RR | 1 | R9C8[1][A] | u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLK |
18.791 | -0.032 | tSu | 1 | R9C8[1][A] | u_la0_top/u_ao_match_0/trig_dly_in_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 18.824 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.588, 82.378%; tC2Q: 0.340, 17.622% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path21
Path Summary:
Slack | 16.864 |
Data Arrival Time | 1.927 |
Data Required Time | 18.791 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_mem_ctrl/capture_length_0_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R16C3[0][A] | u_la0_top/rst_ao_s0/CLK |
0.340 | 0.340 | tC2Q | RF | 54 | R16C3[0][A] | u_la0_top/rst_ao_s0/Q |
1.927 | 1.588 | tNET | FF | 1 | R9C8[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
18.824 | 18.824 | active clock edge time | ||||
18.824 | 0.000 | byte_clk | ||||
18.824 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
18.824 | 0.000 | tNET | RR | 1 | R9C8[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLK |
18.791 | -0.032 | tSu | 1 | R9C8[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_0_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 18.824 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.588, 82.378%; tC2Q: 0.340, 17.622% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path22
Path Summary:
Slack | 16.864 |
Data Arrival Time | 1.927 |
Data Required Time | 18.791 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_mem_ctrl/capture_length_6_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R16C3[0][A] | u_la0_top/rst_ao_s0/CLK |
0.340 | 0.340 | tC2Q | RF | 54 | R16C3[0][A] | u_la0_top/rst_ao_s0/Q |
1.927 | 1.588 | tNET | FF | 1 | R9C8[2][A] | u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
18.824 | 18.824 | active clock edge time | ||||
18.824 | 0.000 | byte_clk | ||||
18.824 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
18.824 | 0.000 | tNET | RR | 1 | R9C8[2][A] | u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLK |
18.791 | -0.032 | tSu | 1 | R9C8[2][A] | u_la0_top/u_ao_mem_ctrl/capture_length_6_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 18.824 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.588, 82.378%; tC2Q: 0.340, 17.622% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path23
Path Summary:
Slack | 16.956 |
Data Arrival Time | 1.835 |
Data Required Time | 18.791 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/capture_window_sel_6_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R16C3[0][A] | u_la0_top/rst_ao_s0/CLK |
0.340 | 0.340 | tC2Q | RF | 54 | R16C3[0][A] | u_la0_top/rst_ao_s0/Q |
1.835 | 1.495 | tNET | FF | 1 | R8C7[2][B] | u_la0_top/capture_window_sel_6_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
18.824 | 18.824 | active clock edge time | ||||
18.824 | 0.000 | byte_clk | ||||
18.824 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
18.824 | 0.000 | tNET | RR | 1 | R8C7[2][B] | u_la0_top/capture_window_sel_6_s1/CLK |
18.791 | -0.032 | tSu | 1 | R8C7[2][B] | u_la0_top/capture_window_sel_6_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 18.824 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.495, 81.493%; tC2Q: 0.340, 18.507% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path24
Path Summary:
Slack | 16.956 |
Data Arrival Time | 1.835 |
Data Required Time | 18.791 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/start_reg_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R16C3[0][A] | u_la0_top/rst_ao_s0/CLK |
0.340 | 0.340 | tC2Q | RF | 54 | R16C3[0][A] | u_la0_top/rst_ao_s0/Q |
1.835 | 1.495 | tNET | FF | 1 | R8C7[1][B] | u_la0_top/start_reg_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
18.824 | 18.824 | active clock edge time | ||||
18.824 | 0.000 | byte_clk | ||||
18.824 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
18.824 | 0.000 | tNET | RR | 1 | R8C7[1][B] | u_la0_top/start_reg_s0/CLK |
18.791 | -0.032 | tSu | 1 | R8C7[1][B] | u_la0_top/start_reg_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 18.824 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.495, 81.493%; tC2Q: 0.340, 18.507% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path25
Path Summary:
Slack | 16.956 |
Data Arrival Time | 1.835 |
Data Required Time | 18.791 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/internal_reg_start_syn_1_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R16C3[0][A] | u_la0_top/rst_ao_s0/CLK |
0.340 | 0.340 | tC2Q | RF | 54 | R16C3[0][A] | u_la0_top/rst_ao_s0/Q |
1.835 | 1.495 | tNET | FF | 1 | R8C7[1][A] | u_la0_top/internal_reg_start_syn_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
18.824 | 18.824 | active clock edge time | ||||
18.824 | 0.000 | byte_clk | ||||
18.824 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
18.824 | 0.000 | tNET | RR | 1 | R8C7[1][A] | u_la0_top/internal_reg_start_syn_1_s0/CLK |
18.791 | -0.032 | tSu | 1 | R8C7[1][A] | u_la0_top/internal_reg_start_syn_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 18.824 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.495, 81.493%; tC2Q: 0.340, 18.507% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Removal Analysis Report
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 0.424 |
Data Arrival Time | 0.435 |
Data Required Time | 0.011 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/capture_window_sel_8_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R16C3[0][A] | u_la0_top/rst_ao_s0/CLK |
0.247 | 0.247 | tC2Q | RR | 54 | R16C3[0][A] | u_la0_top/rst_ao_s0/Q |
0.435 | 0.188 | tNET | RR | 1 | R16C3[2][A] | u_la0_top/capture_window_sel_8_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R16C3[2][A] | u_la0_top/capture_window_sel_8_s1/CLK |
0.011 | 0.011 | tHld | 1 | R16C3[2][A] | u_la0_top/capture_window_sel_8_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.188, 43.172%; tC2Q: 0.247, 56.828% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path2
Path Summary:
Slack | 0.424 |
Data Arrival Time | 0.435 |
Data Required Time | 0.011 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/triger_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R16C3[0][A] | u_la0_top/rst_ao_s0/CLK |
0.247 | 0.247 | tC2Q | RR | 54 | R16C3[0][A] | u_la0_top/rst_ao_s0/Q |
0.435 | 0.188 | tNET | RR | 1 | R16C3[1][A] | u_la0_top/triger_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R16C3[1][A] | u_la0_top/triger_s0/CLK |
0.011 | 0.011 | tHld | 1 | R16C3[1][A] | u_la0_top/triger_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.188, 43.172%; tC2Q: 0.247, 56.828% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path3
Path Summary:
Slack | 0.622 |
Data Arrival Time | 0.633 |
Data Required Time | 0.011 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R16C3[0][A] | u_la0_top/rst_ao_s0/CLK |
0.247 | 0.247 | tC2Q | RR | 54 | R16C3[0][A] | u_la0_top/rst_ao_s0/Q |
0.633 | 0.386 | tNET | RR | 1 | R14C3[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R14C3[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK |
0.011 | 0.011 | tHld | 1 | R14C3[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.386, 60.971%; tC2Q: 0.247, 39.029% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path4
Path Summary:
Slack | 0.622 |
Data Arrival Time | 0.633 |
Data Required Time | 0.011 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R16C3[0][A] | u_la0_top/rst_ao_s0/CLK |
0.247 | 0.247 | tC2Q | RR | 54 | R16C3[0][A] | u_la0_top/rst_ao_s0/Q |
0.633 | 0.386 | tNET | RR | 1 | R14C3[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R14C3[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK |
0.011 | 0.011 | tHld | 1 | R14C3[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.386, 60.971%; tC2Q: 0.247, 39.029% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path5
Path Summary:
Slack | 0.622 |
Data Arrival Time | 0.633 |
Data Required Time | 0.011 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R16C3[0][A] | u_la0_top/rst_ao_s0/CLK |
0.247 | 0.247 | tC2Q | RR | 54 | R16C3[0][A] | u_la0_top/rst_ao_s0/Q |
0.633 | 0.386 | tNET | RR | 1 | R14C3[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R14C3[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK |
0.011 | 0.011 | tHld | 1 | R14C3[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.386, 60.971%; tC2Q: 0.247, 39.029% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path6
Path Summary:
Slack | 0.624 |
Data Arrival Time | 0.635 |
Data Required Time | 0.011 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/capture_window_sel_7_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R16C3[0][A] | u_la0_top/rst_ao_s0/CLK |
0.247 | 0.247 | tC2Q | RR | 54 | R16C3[0][A] | u_la0_top/rst_ao_s0/Q |
0.635 | 0.388 | tNET | RR | 1 | R16C2[0][B] | u_la0_top/capture_window_sel_7_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R16C2[0][B] | u_la0_top/capture_window_sel_7_s1/CLK |
0.011 | 0.011 | tHld | 1 | R16C2[0][B] | u_la0_top/capture_window_sel_7_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.388, 61.083%; tC2Q: 0.247, 38.917% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path7
Path Summary:
Slack | 0.624 |
Data Arrival Time | 0.635 |
Data Required Time | 0.011 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/capture_window_sel_9_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R16C3[0][A] | u_la0_top/rst_ao_s0/CLK |
0.247 | 0.247 | tC2Q | RR | 54 | R16C3[0][A] | u_la0_top/rst_ao_s0/Q |
0.635 | 0.388 | tNET | RR | 1 | R16C2[0][A] | u_la0_top/capture_window_sel_9_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R16C2[0][A] | u_la0_top/capture_window_sel_9_s1/CLK |
0.011 | 0.011 | tHld | 1 | R16C2[0][A] | u_la0_top/capture_window_sel_9_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.388, 61.083%; tC2Q: 0.247, 38.917% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path8
Path Summary:
Slack | 0.666 |
Data Arrival Time | 0.678 |
Data Required Time | 0.011 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R16C3[0][A] | u_la0_top/rst_ao_s0/CLK |
0.247 | 0.247 | tC2Q | RR | 54 | R16C3[0][A] | u_la0_top/rst_ao_s0/Q |
0.678 | 0.431 | tNET | RR | 1 | R13C3[2][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R13C3[2][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/CLK |
0.011 | 0.011 | tHld | 1 | R13C3[2][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.431, 63.544%; tC2Q: 0.247, 36.456% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path9
Path Summary:
Slack | 0.666 |
Data Arrival Time | 0.678 |
Data Required Time | 0.011 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_mem_ctrl/capture_loop_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R16C3[0][A] | u_la0_top/rst_ao_s0/CLK |
0.247 | 0.247 | tC2Q | RR | 54 | R16C3[0][A] | u_la0_top/rst_ao_s0/Q |
0.678 | 0.431 | tNET | RR | 1 | R15C3[0][A] | u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R15C3[0][A] | u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK |
0.011 | 0.011 | tHld | 1 | R15C3[0][A] | u_la0_top/u_ao_mem_ctrl/capture_loop_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.431, 63.544%; tC2Q: 0.247, 36.456% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path10
Path Summary:
Slack | 0.666 |
Data Arrival Time | 0.678 |
Data Required Time | 0.011 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/triger_level_cnt_0_s3 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R16C3[0][A] | u_la0_top/rst_ao_s0/CLK |
0.247 | 0.247 | tC2Q | RR | 54 | R16C3[0][A] | u_la0_top/rst_ao_s0/Q |
0.678 | 0.431 | tNET | RR | 1 | R13C3[2][A] | u_la0_top/triger_level_cnt_0_s3/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R13C3[2][A] | u_la0_top/triger_level_cnt_0_s3/CLK |
0.011 | 0.011 | tHld | 1 | R13C3[2][A] | u_la0_top/triger_level_cnt_0_s3 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.431, 63.544%; tC2Q: 0.247, 36.456% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path11
Path Summary:
Slack | 0.667 |
Data Arrival Time | 0.679 |
Data Required Time | 0.011 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/capture_end_dly_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R16C3[0][A] | u_la0_top/rst_ao_s0/CLK |
0.247 | 0.247 | tC2Q | RR | 54 | R16C3[0][A] | u_la0_top/rst_ao_s0/Q |
0.679 | 0.432 | tNET | RR | 1 | R14C2[2][A] | u_la0_top/capture_end_dly_s0/PRESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R14C2[2][A] | u_la0_top/capture_end_dly_s0/CLK |
0.011 | 0.011 | tHld | 1 | R14C2[2][A] | u_la0_top/capture_end_dly_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.432, 63.602%; tC2Q: 0.247, 36.398% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path12
Path Summary:
Slack | 0.667 |
Data Arrival Time | 0.679 |
Data Required Time | 0.011 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/internal_reg_start_dly_0_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R16C3[0][A] | u_la0_top/rst_ao_s0/CLK |
0.247 | 0.247 | tC2Q | RR | 54 | R16C3[0][A] | u_la0_top/rst_ao_s0/Q |
0.679 | 0.432 | tNET | RR | 1 | R14C2[2][B] | u_la0_top/internal_reg_start_dly_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R14C2[2][B] | u_la0_top/internal_reg_start_dly_0_s0/CLK |
0.011 | 0.011 | tHld | 1 | R14C2[2][B] | u_la0_top/internal_reg_start_dly_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.432, 63.602%; tC2Q: 0.247, 36.398% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path13
Path Summary:
Slack | 0.669 |
Data Arrival Time | 0.680 |
Data Required Time | 0.011 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/trigger_seq_start_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R16C3[0][A] | u_la0_top/rst_ao_s0/CLK |
0.247 | 0.247 | tC2Q | RR | 54 | R16C3[0][A] | u_la0_top/rst_ao_s0/Q |
0.680 | 0.433 | tNET | RR | 1 | R15C2[1][A] | u_la0_top/trigger_seq_start_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R15C2[1][A] | u_la0_top/trigger_seq_start_s1/CLK |
0.011 | 0.011 | tHld | 1 | R15C2[1][A] | u_la0_top/trigger_seq_start_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.433, 63.660%; tC2Q: 0.247, 36.340% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path14
Path Summary:
Slack | 0.830 |
Data Arrival Time | 0.841 |
Data Required Time | 0.011 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/internal_reg_start_dly_1_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R16C3[0][A] | u_la0_top/rst_ao_s0/CLK |
0.247 | 0.247 | tC2Q | RR | 54 | R16C3[0][A] | u_la0_top/rst_ao_s0/Q |
0.841 | 0.594 | tNET | RR | 1 | R9C3[0][A] | u_la0_top/internal_reg_start_dly_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R9C3[0][A] | u_la0_top/internal_reg_start_dly_1_s0/CLK |
0.011 | 0.011 | tHld | 1 | R9C3[0][A] | u_la0_top/internal_reg_start_dly_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.594, 70.641%; tC2Q: 0.247, 29.359% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path15
Path Summary:
Slack | 0.830 |
Data Arrival Time | 0.841 |
Data Required Time | 0.011 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/internal_reg_force_triger_syn_1_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R16C3[0][A] | u_la0_top/rst_ao_s0/CLK |
0.247 | 0.247 | tC2Q | RR | 54 | R16C3[0][A] | u_la0_top/rst_ao_s0/Q |
0.841 | 0.594 | tNET | RR | 1 | R9C3[0][B] | u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R9C3[0][B] | u_la0_top/internal_reg_force_triger_syn_1_s0/CLK |
0.011 | 0.011 | tHld | 1 | R9C3[0][B] | u_la0_top/internal_reg_force_triger_syn_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.594, 70.641%; tC2Q: 0.247, 29.359% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path16
Path Summary:
Slack | 0.837 |
Data Arrival Time | 0.848 |
Data Required Time | 0.011 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/capture_window_sel_2_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R16C3[0][A] | u_la0_top/rst_ao_s0/CLK |
0.247 | 0.247 | tC2Q | RR | 54 | R16C3[0][A] | u_la0_top/rst_ao_s0/Q |
0.848 | 0.601 | tNET | RR | 1 | R12C2[1][B] | u_la0_top/capture_window_sel_2_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R12C2[1][B] | u_la0_top/capture_window_sel_2_s1/CLK |
0.011 | 0.011 | tHld | 1 | R12C2[1][B] | u_la0_top/capture_window_sel_2_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.601, 70.860%; tC2Q: 0.247, 29.140% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path17
Path Summary:
Slack | 0.837 |
Data Arrival Time | 0.848 |
Data Required Time | 0.011 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/capture_window_sel_3_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R16C3[0][A] | u_la0_top/rst_ao_s0/CLK |
0.247 | 0.247 | tC2Q | RR | 54 | R16C3[0][A] | u_la0_top/rst_ao_s0/Q |
0.848 | 0.601 | tNET | RR | 1 | R12C2[1][A] | u_la0_top/capture_window_sel_3_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R12C2[1][A] | u_la0_top/capture_window_sel_3_s1/CLK |
0.011 | 0.011 | tHld | 1 | R12C2[1][A] | u_la0_top/capture_window_sel_3_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.601, 70.860%; tC2Q: 0.247, 29.140% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path18
Path Summary:
Slack | 0.837 |
Data Arrival Time | 0.848 |
Data Required Time | 0.011 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/triger_level_cnt_1_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R16C3[0][A] | u_la0_top/rst_ao_s0/CLK |
0.247 | 0.247 | tC2Q | RR | 54 | R16C3[0][A] | u_la0_top/rst_ao_s0/Q |
0.848 | 0.601 | tNET | RR | 1 | R12C2[0][A] | u_la0_top/triger_level_cnt_1_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R12C2[0][A] | u_la0_top/triger_level_cnt_1_s1/CLK |
0.011 | 0.011 | tHld | 1 | R12C2[0][A] | u_la0_top/triger_level_cnt_1_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.601, 70.860%; tC2Q: 0.247, 29.140% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path19
Path Summary:
Slack | 0.876 |
Data Arrival Time | 0.887 |
Data Required Time | 0.011 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/capture_window_sel_1_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R16C3[0][A] | u_la0_top/rst_ao_s0/CLK |
0.247 | 0.247 | tC2Q | RR | 54 | R16C3[0][A] | u_la0_top/rst_ao_s0/Q |
0.887 | 0.640 | tNET | RR | 1 | R9C5[2][A] | u_la0_top/capture_window_sel_1_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R9C5[2][A] | u_la0_top/capture_window_sel_1_s1/CLK |
0.011 | 0.011 | tHld | 1 | R9C5[2][A] | u_la0_top/capture_window_sel_1_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.640, 72.156%; tC2Q: 0.247, 27.844% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path20
Path Summary:
Slack | 0.878 |
Data Arrival Time | 0.889 |
Data Required Time | 0.011 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_match_0/match_sep_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R16C3[0][A] | u_la0_top/rst_ao_s0/CLK |
0.247 | 0.247 | tC2Q | RR | 54 | R16C3[0][A] | u_la0_top/rst_ao_s0/Q |
0.889 | 0.642 | tNET | RR | 1 | R9C2[2][B] | u_la0_top/u_ao_match_0/match_sep_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R9C2[2][B] | u_la0_top/u_ao_match_0/match_sep_s0/CLK |
0.011 | 0.011 | tHld | 1 | R9C2[2][B] | u_la0_top/u_ao_match_0/match_sep_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.642, 72.222%; tC2Q: 0.247, 27.778% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path21
Path Summary:
Slack | 0.878 |
Data Arrival Time | 0.889 |
Data Required Time | 0.011 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/internal_reg_force_triger_syn_0_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R16C3[0][A] | u_la0_top/rst_ao_s0/CLK |
0.247 | 0.247 | tC2Q | RR | 54 | R16C3[0][A] | u_la0_top/rst_ao_s0/Q |
0.889 | 0.642 | tNET | RR | 1 | R9C2[2][A] | u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R9C2[2][A] | u_la0_top/internal_reg_force_triger_syn_0_s0/CLK |
0.011 | 0.011 | tHld | 1 | R9C2[2][A] | u_la0_top/internal_reg_force_triger_syn_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.642, 72.222%; tC2Q: 0.247, 27.778% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path22
Path Summary:
Slack | 0.881 |
Data Arrival Time | 0.892 |
Data Required Time | 0.011 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/triger_level_cnt_2_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R16C3[0][A] | u_la0_top/rst_ao_s0/CLK |
0.247 | 0.247 | tC2Q | RR | 54 | R16C3[0][A] | u_la0_top/rst_ao_s0/Q |
0.892 | 0.645 | tNET | RR | 1 | R11C5[2][B] | u_la0_top/triger_level_cnt_2_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R11C5[2][B] | u_la0_top/triger_level_cnt_2_s1/CLK |
0.011 | 0.011 | tHld | 1 | R11C5[2][B] | u_la0_top/triger_level_cnt_2_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.645, 72.311%; tC2Q: 0.247, 27.689% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path23
Path Summary:
Slack | 0.881 |
Data Arrival Time | 0.892 |
Data Required Time | 0.011 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/triger_level_cnt_3_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R16C3[0][A] | u_la0_top/rst_ao_s0/CLK |
0.247 | 0.247 | tC2Q | RR | 54 | R16C3[0][A] | u_la0_top/rst_ao_s0/Q |
0.892 | 0.645 | tNET | RR | 1 | R11C5[2][A] | u_la0_top/triger_level_cnt_3_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R11C5[2][A] | u_la0_top/triger_level_cnt_3_s1/CLK |
0.011 | 0.011 | tHld | 1 | R11C5[2][A] | u_la0_top/triger_level_cnt_3_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.645, 72.311%; tC2Q: 0.247, 27.689% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path24
Path Summary:
Slack | 1.030 |
Data Arrival Time | 1.041 |
Data Required Time | 0.011 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/capture_window_sel_6_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R16C3[0][A] | u_la0_top/rst_ao_s0/CLK |
0.247 | 0.247 | tC2Q | RR | 54 | R16C3[0][A] | u_la0_top/rst_ao_s0/Q |
1.041 | 0.794 | tNET | RR | 1 | R8C7[2][B] | u_la0_top/capture_window_sel_6_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R8C7[2][B] | u_la0_top/capture_window_sel_6_s1/CLK |
0.011 | 0.011 | tHld | 1 | R8C7[2][B] | u_la0_top/capture_window_sel_6_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.794, 76.281%; tC2Q: 0.247, 23.719% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path25
Path Summary:
Slack | 1.030 |
Data Arrival Time | 1.041 |
Data Required Time | 0.011 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/start_reg_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R16C3[0][A] | u_la0_top/rst_ao_s0/CLK |
0.247 | 0.247 | tC2Q | RR | 54 | R16C3[0][A] | u_la0_top/rst_ao_s0/Q |
1.041 | 0.794 | tNET | RR | 1 | R8C7[1][B] | u_la0_top/start_reg_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1094 | PLL_R | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R8C7[1][B] | u_la0_top/start_reg_s0/CLK |
0.011 | 0.011 | tHld | 1 | R8C7[1][B] | u_la0_top/start_reg_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.794, 76.281%; tC2Q: 0.247, 23.719% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Minimum Pulse Width Report:
Report Command:report_min_pulse_width -nworst 10 -detail
MPW1
MPW Summary:
Slack: | 2.545 |
Actual Width: | 3.472 |
Required Width: | 0.926 |
Type: | Low Pulse Width |
Clock: | pixel_clk |
Objects: | run_cnt_25_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
3.529 | 0.000 | active clock edge time | ||
3.529 | 0.000 | pixel_clk | ||
3.529 | 0.000 | tCL | FF | u_pll/rpll_inst/CLKOUTD3 |
3.724 | 0.195 | tNET | FF | run_cnt_25_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
7.059 | 0.000 | active clock edge time | ||
7.059 | 0.000 | pixel_clk | ||
7.059 | 0.000 | tCL | RR | u_pll/rpll_inst/CLKOUTD3 |
7.196 | 0.137 | tNET | RR | run_cnt_25_s0/CLK |
MPW2
MPW Summary:
Slack: | 2.545 |
Actual Width: | 3.472 |
Required Width: | 0.926 |
Type: | Low Pulse Width |
Clock: | pixel_clk |
Objects: | run_cnt_24_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
3.529 | 0.000 | active clock edge time | ||
3.529 | 0.000 | pixel_clk | ||
3.529 | 0.000 | tCL | FF | u_pll/rpll_inst/CLKOUTD3 |
3.724 | 0.195 | tNET | FF | run_cnt_24_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
7.059 | 0.000 | active clock edge time | ||
7.059 | 0.000 | pixel_clk | ||
7.059 | 0.000 | tCL | RR | u_pll/rpll_inst/CLKOUTD3 |
7.196 | 0.137 | tNET | RR | run_cnt_24_s0/CLK |
MPW3
MPW Summary:
Slack: | 2.545 |
Actual Width: | 3.472 |
Required Width: | 0.926 |
Type: | Low Pulse Width |
Clock: | pixel_clk |
Objects: | run_cnt_8_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
3.529 | 0.000 | active clock edge time | ||
3.529 | 0.000 | pixel_clk | ||
3.529 | 0.000 | tCL | FF | u_pll/rpll_inst/CLKOUTD3 |
3.724 | 0.195 | tNET | FF | run_cnt_8_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
7.059 | 0.000 | active clock edge time | ||
7.059 | 0.000 | pixel_clk | ||
7.059 | 0.000 | tCL | RR | u_pll/rpll_inst/CLKOUTD3 |
7.196 | 0.137 | tNET | RR | run_cnt_8_s0/CLK |
MPW4
MPW Summary:
Slack: | 2.545 |
Actual Width: | 3.472 |
Required Width: | 0.926 |
Type: | Low Pulse Width |
Clock: | pixel_clk |
Objects: | u_test_gen/Gray_17_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
3.529 | 0.000 | active clock edge time | ||
3.529 | 0.000 | pixel_clk | ||
3.529 | 0.000 | tCL | FF | u_pll/rpll_inst/CLKOUTD3 |
3.724 | 0.195 | tNET | FF | u_test_gen/Gray_17_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
7.059 | 0.000 | active clock edge time | ||
7.059 | 0.000 | pixel_clk | ||
7.059 | 0.000 | tCL | RR | u_pll/rpll_inst/CLKOUTD3 |
7.196 | 0.137 | tNET | RR | u_test_gen/Gray_17_s0/CLK |
MPW5
MPW Summary:
Slack: | 2.545 |
Actual Width: | 3.472 |
Required Width: | 0.926 |
Type: | Low Pulse Width |
Clock: | pixel_clk |
Objects: | u_test_gen/Data_tmp_1_s1 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
3.529 | 0.000 | active clock edge time | ||
3.529 | 0.000 | pixel_clk | ||
3.529 | 0.000 | tCL | FF | u_pll/rpll_inst/CLKOUTD3 |
3.724 | 0.195 | tNET | FF | u_test_gen/Data_tmp_1_s1/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
7.059 | 0.000 | active clock edge time | ||
7.059 | 0.000 | pixel_clk | ||
7.059 | 0.000 | tCL | RR | u_pll/rpll_inst/CLKOUTD3 |
7.196 | 0.137 | tNET | RR | u_test_gen/Data_tmp_1_s1/CLK |
MPW6
MPW Summary:
Slack: | 2.545 |
Actual Width: | 3.472 |
Required Width: | 0.926 |
Type: | Low Pulse Width |
Clock: | pixel_clk |
Objects: | u_test_gen/De_hcnt_10_s1 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
3.529 | 0.000 | active clock edge time | ||
3.529 | 0.000 | pixel_clk | ||
3.529 | 0.000 | tCL | FF | u_pll/rpll_inst/CLKOUTD3 |
3.724 | 0.195 | tNET | FF | u_test_gen/De_hcnt_10_s1/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
7.059 | 0.000 | active clock edge time | ||
7.059 | 0.000 | pixel_clk | ||
7.059 | 0.000 | tCL | RR | u_pll/rpll_inst/CLKOUTD3 |
7.196 | 0.137 | tNET | RR | u_test_gen/De_hcnt_10_s1/CLK |
MPW7
MPW Summary:
Slack: | 2.545 |
Actual Width: | 3.472 |
Required Width: | 0.926 |
Type: | Low Pulse Width |
Clock: | pixel_clk |
Objects: | u_test_gen/De_vcnt_9_s1 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
3.529 | 0.000 | active clock edge time | ||
3.529 | 0.000 | pixel_clk | ||
3.529 | 0.000 | tCL | FF | u_pll/rpll_inst/CLKOUTD3 |
3.724 | 0.195 | tNET | FF | u_test_gen/De_vcnt_9_s1/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
7.059 | 0.000 | active clock edge time | ||
7.059 | 0.000 | pixel_clk | ||
7.059 | 0.000 | tCL | RR | u_pll/rpll_inst/CLKOUTD3 |
7.196 | 0.137 | tNET | RR | u_test_gen/De_vcnt_9_s1/CLK |
MPW8
MPW Summary:
Slack: | 2.545 |
Actual Width: | 3.472 |
Required Width: | 0.926 |
Type: | Low Pulse Width |
Clock: | pixel_clk |
Objects: | u_test_gen/De_vcnt_5_s1 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
3.529 | 0.000 | active clock edge time | ||
3.529 | 0.000 | pixel_clk | ||
3.529 | 0.000 | tCL | FF | u_pll/rpll_inst/CLKOUTD3 |
3.724 | 0.195 | tNET | FF | u_test_gen/De_vcnt_5_s1/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
7.059 | 0.000 | active clock edge time | ||
7.059 | 0.000 | pixel_clk | ||
7.059 | 0.000 | tCL | RR | u_pll/rpll_inst/CLKOUTD3 |
7.196 | 0.137 | tNET | RR | u_test_gen/De_vcnt_5_s1/CLK |
MPW9
MPW Summary:
Slack: | 2.545 |
Actual Width: | 3.472 |
Required Width: | 0.926 |
Type: | Low Pulse Width |
Clock: | pixel_clk |
Objects: | u_test_gen/De_vcnt_3_s1 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
3.529 | 0.000 | active clock edge time | ||
3.529 | 0.000 | pixel_clk | ||
3.529 | 0.000 | tCL | FF | u_pll/rpll_inst/CLKOUTD3 |
3.724 | 0.195 | tNET | FF | u_test_gen/De_vcnt_3_s1/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
7.059 | 0.000 | active clock edge time | ||
7.059 | 0.000 | pixel_clk | ||
7.059 | 0.000 | tCL | RR | u_pll/rpll_inst/CLKOUTD3 |
7.196 | 0.137 | tNET | RR | u_test_gen/De_vcnt_3_s1/CLK |
MPW10
MPW Summary:
Slack: | 2.545 |
Actual Width: | 3.472 |
Required Width: | 0.926 |
Type: | Low Pulse Width |
Clock: | pixel_clk |
Objects: | u_test_gen/De_vcnt_2_s1 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
3.529 | 0.000 | active clock edge time | ||
3.529 | 0.000 | pixel_clk | ||
3.529 | 0.000 | tCL | FF | u_pll/rpll_inst/CLKOUTD3 |
3.724 | 0.195 | tNET | FF | u_test_gen/De_vcnt_2_s1/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
7.059 | 0.000 | active clock edge time | ||
7.059 | 0.000 | pixel_clk | ||
7.059 | 0.000 | tCL | RR | u_pll/rpll_inst/CLKOUTD3 |
7.196 | 0.137 | tNET | RR | u_test_gen/De_vcnt_2_s1/CLK |
High Fanout Nets Report:
Report Command:report_high_fanout_nets -max_nets 10
FANOUT | NET NAME | WORST SLACK | MAX DELAY |
---|---|---|---|
1094 | byte_clk | 6.993 | 0.195 |
353 | pixel_clk | 0.098 | 0.195 |
129 | mid_sel[0] | 1.549 | 2.894 |
129 | mid_sel[1] | 2.421 | 2.083 |
121 | n4769_3 | 12.491 | 2.327 |
120 | n5297_9 | 9.358 | 3.529 |
120 | n5809_12 | 11.021 | 2.487 |
120 | n5809_15 | 8.909 | 5.325 |
120 | n5178_11 | 9.996 | 2.463 |
120 | n5690_16 | 9.166 | 4.386 |
Route Congestions Report:
Report Command:report_route_congestion -max_grids 10
GRID LOC | ROUTE CONGESTIONS |
---|---|
R13C30 | 88.89% |
R13C21 | 81.94% |
R13C31 | 79.17% |
R14C16 | 77.78% |
R11C30 | 76.39% |
R15C21 | 75.00% |
R15C13 | 73.61% |
R15C17 | 73.61% |
R14C17 | 73.61% |
R16C19 | 72.22% |
Timing Exceptions Report:
Setup Analysis Report
Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Hold Analysis Report
Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Recovery Analysis Report
Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Removal Analysis Report
Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Timing Constraints Report:
SDC Command Type | State | Detail Command |
---|---|---|
TC_CLOCK | Actived | create_clock -name clk_50 -period 20 -waveform {0 10} [get_ports {OSC_50M}] |
TC_GENERATED_CLOCK | Actived | create_generated_clock -name pixel_clk -source [get_ports {OSC_50M}] -master_clock clk_50 -divide_by 6 -multiply_by 17 [get_nets {pixel_clk}] |
TC_GENERATED_CLOCK | Actived | create_generated_clock -name byte_clk -source [get_ports {OSC_50M}] -master_clock clk_50 -divide_by 16 -multiply_by 17 [get_nets {byte_clk}] |
TC_CLOCK_GROUP | Actived | set_clock_groups -exclusive -group [get_clocks {pixel_clk}] -group [get_clocks {byte_clk}] |
TC_REPORT_TIMING | Actived | report_timing -setup -from_clock [get_clocks {pixel_clk}] -max_paths 20 -max_common_paths 1 |
TC_REPORT_TIMING | Actived | report_timing -setup -from_clock [get_clocks {byte_clk}] -max_paths 20 -max_common_paths 1 |
TC_REPORT_TIMING | Actived | report_timing -hold -from_clock [get_clocks {pixel_clk}] -max_paths 20 -max_common_paths 1 |
TC_REPORT_TIMING | Actived | report_timing -hold -from_clock [get_clocks {byte_clk}] -max_paths 20 -max_common_paths 1 |