Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Programs\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\MIPI_DSI_CSI2_TX\data\dsi_csi2_tx_wrap.v
D:\Programs\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\MIPI_DSI_CSI2_TX\data\dsi_csi2_tx.v
GowinSynthesis Constraints File ---
Tool Version V1.9.9.01 (64-bit)
Part Number GW2A-LV18QN88C7/I6
Device GW2A-18
Device Version C
Created Time Wed Mar 6 10:13:34 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module DSI_TX_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.218s, Peak memory usage = 110.938MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 110.938MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.047s, Peak memory usage = 110.938MB
    Optimizing Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.026s, Peak memory usage = 110.938MB
    Optimizing Phase 2: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.078s, Peak memory usage = 110.938MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.015s, Peak memory usage = 110.938MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 110.938MB
    Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 110.938MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 110.938MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.099s, Peak memory usage = 110.938MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 110.938MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.014s, Peak memory usage = 110.938MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s, Peak memory usage = 140.484MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.076s, Peak memory usage = 140.484MB
Generate output files:
    CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.141s, Peak memory usage = 140.484MB
Total Time and Memory Usage CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s, Peak memory usage = 140.484MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 109
I/O Buf 109
    IBUF 63
    OBUF 46
Register 479
    DFF 65
    DFFE 180
    DFFS 6
    DFFSE 16
    DFFR 84
    DFFRE 20
    DFFP 1
    DFFPE 17
    DFFC 61
    DFFCE 29
LUT 1246
    LUT2 85
    LUT3 561
    LUT4 600
ALU 4
    ALU 4
SSRAM 4
    RAM16SDP4 4
INV 5
    INV 5
BSRAM 2
    SDPX9B 2

Resource Utilization Summary

Resource Usage Utilization
Logic 1279(1251 LUT, 4 ALU, 4 RAM16) / 20736 7%
Register 479 / 15750 4%
  --Register as Latch 0 / 15750 0%
  --Register as FF 479 / 15750 4%
BSRAM 2 / 46 5%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
I_BYTE_CLK Base 10.000 100.0 0.000 5.000 I_BYTE_CLK_ibuf/I

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 I_BYTE_CLK 100.000(MHz) 108.137(MHz) 8 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 0.753
Data Arrival Time 10.507
Data Required Time 11.259
From u_tx/u_dsi_tx/u_dphy/u_data_buf/rEmpty_s1
To u_tx/u_dsi_tx/u_dphy/u_data_buf/rWrOffset_8_s1
Launch Clk I_BYTE_CLK[R]
Latch Clk I_BYTE_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_BYTE_CLK
0.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
0.853 0.853 tINS RR 487 I_BYTE_CLK_ibuf/O
1.303 0.450 tNET RR 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/rEmpty_s1/CLK
1.593 0.290 tC2Q RF 9 u_tx/u_dsi_tx/u_dphy/u_data_buf/rEmpty_s1/Q
2.186 0.593 tNET FF 1 u_tx/u_dsi_tx/u_dphy/wDataRd_s3/I0
2.832 0.646 tINS FF 4 u_tx/u_dsi_tx/u_dphy/wDataRd_s3/F
3.424 0.593 tNET FF 1 u_tx/u_dsi_tx/u_dphy/wDataRd_s2/I1
4.118 0.694 tINS FF 10 u_tx/u_dsi_tx/u_dphy/wDataRd_s2/F
4.711 0.593 tNET FF 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n58_s2/I0
5.357 0.646 tINS FF 4 u_tx/u_dsi_tx/u_dphy/u_data_buf/n58_s2/F
5.949 0.593 tNET FF 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n128_s1/I3
6.413 0.464 tINS FF 4 u_tx/u_dsi_tx/u_dphy/u_data_buf/n128_s1/F
7.006 0.593 tNET FF 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n125_s1/I2
7.572 0.566 tINS FF 3 u_tx/u_dsi_tx/u_dphy/u_data_buf/n125_s1/F
8.164 0.593 tNET FF 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n123_s1/I3
8.628 0.464 tINS FF 2 u_tx/u_dsi_tx/u_dphy/u_data_buf/n123_s1/F
9.221 0.593 tNET FF 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n124_s0/I1
9.914 0.694 tINS FF 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n124_s0/F
10.507 0.593 tNET FF 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/rWrOffset_8_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_BYTE_CLK
10.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
10.853 0.853 tINS RR 487 I_BYTE_CLK_ibuf/O
11.303 0.450 tNET RR 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/rWrOffset_8_s1/CLK
11.259 -0.044 tSu 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/rWrOffset_8_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 8
Arrival Clock Path Delay: cell: 0.853, 65.468%; route: 0.450, 34.532%
Arrival Data Path Delay: cell: 4.174, 45.348%; route: 4.740, 51.501%; tC2Q: 0.290, 3.151%
Required Clock Path Delay: cell: 0.853, 65.468%; route: 0.450, 34.532%

Path 2

Path Summary:
Slack 0.753
Data Arrival Time 10.507
Data Required Time 11.259
From u_tx/u_dsi_tx/u_dphy/u_data_buf/rEmpty_s1
To u_tx/u_dsi_tx/u_dphy/u_data_buf/rWrOffset_9_s1
Launch Clk I_BYTE_CLK[R]
Latch Clk I_BYTE_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_BYTE_CLK
0.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
0.853 0.853 tINS RR 487 I_BYTE_CLK_ibuf/O
1.303 0.450 tNET RR 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/rEmpty_s1/CLK
1.593 0.290 tC2Q RF 9 u_tx/u_dsi_tx/u_dphy/u_data_buf/rEmpty_s1/Q
2.186 0.593 tNET FF 1 u_tx/u_dsi_tx/u_dphy/wDataRd_s3/I0
2.832 0.646 tINS FF 4 u_tx/u_dsi_tx/u_dphy/wDataRd_s3/F
3.424 0.593 tNET FF 1 u_tx/u_dsi_tx/u_dphy/wDataRd_s2/I1
4.118 0.694 tINS FF 10 u_tx/u_dsi_tx/u_dphy/wDataRd_s2/F
4.711 0.593 tNET FF 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n58_s2/I0
5.357 0.646 tINS FF 4 u_tx/u_dsi_tx/u_dphy/u_data_buf/n58_s2/F
5.949 0.593 tNET FF 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n128_s1/I3
6.413 0.464 tINS FF 4 u_tx/u_dsi_tx/u_dphy/u_data_buf/n128_s1/F
7.006 0.593 tNET FF 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n125_s1/I2
7.572 0.566 tINS FF 3 u_tx/u_dsi_tx/u_dphy/u_data_buf/n125_s1/F
8.164 0.593 tNET FF 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n123_s1/I3
8.628 0.464 tINS FF 2 u_tx/u_dsi_tx/u_dphy/u_data_buf/n123_s1/F
9.221 0.593 tNET FF 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n123_s0/I1
9.914 0.694 tINS FF 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n123_s0/F
10.507 0.593 tNET FF 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/rWrOffset_9_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_BYTE_CLK
10.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
10.853 0.853 tINS RR 487 I_BYTE_CLK_ibuf/O
11.303 0.450 tNET RR 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/rWrOffset_9_s1/CLK
11.259 -0.044 tSu 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/rWrOffset_9_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 8
Arrival Clock Path Delay: cell: 0.853, 65.468%; route: 0.450, 34.532%
Arrival Data Path Delay: cell: 4.174, 45.348%; route: 4.740, 51.501%; tC2Q: 0.290, 3.151%
Required Clock Path Delay: cell: 0.853, 65.468%; route: 0.450, 34.532%

Path 3

Path Summary:
Slack 1.579
Data Arrival Time 9.681
Data Required Time 11.259
From u_tx/u_dsi_tx/u_dphy/u_data_buf/rEmpty_s1
To u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_10_s1
Launch Clk I_BYTE_CLK[R]
Latch Clk I_BYTE_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_BYTE_CLK
0.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
0.853 0.853 tINS RR 487 I_BYTE_CLK_ibuf/O
1.303 0.450 tNET RR 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/rEmpty_s1/CLK
1.593 0.290 tC2Q RF 9 u_tx/u_dsi_tx/u_dphy/u_data_buf/rEmpty_s1/Q
2.186 0.593 tNET FF 1 u_tx/u_dsi_tx/u_dphy/wDataRd_s3/I0
2.832 0.646 tINS FF 4 u_tx/u_dsi_tx/u_dphy/wDataRd_s3/F
3.424 0.593 tNET FF 1 u_tx/u_dsi_tx/u_dphy/wDataRd_s2/I1
4.118 0.694 tINS FF 10 u_tx/u_dsi_tx/u_dphy/wDataRd_s2/F
4.711 0.593 tNET FF 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n58_s1/I1
5.404 0.694 tINS FF 4 u_tx/u_dsi_tx/u_dphy/u_data_buf/n58_s1/F
5.997 0.593 tNET FF 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n53_s2/I2
6.563 0.566 tINS FF 5 u_tx/u_dsi_tx/u_dphy/u_data_buf/n53_s2/F
7.156 0.593 tNET FF 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n49_s2/I0
7.802 0.646 tINS FF 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n49_s2/F
8.394 0.593 tNET FF 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n49_s0/I1
9.088 0.694 tINS FF 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n49_s0/F
9.681 0.593 tNET FF 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_10_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_BYTE_CLK
10.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
10.853 0.853 tINS RR 487 I_BYTE_CLK_ibuf/O
11.303 0.450 tNET RR 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_10_s1/CLK
11.259 -0.044 tSu 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_10_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.853, 65.468%; route: 0.450, 34.532%
Arrival Data Path Delay: cell: 3.940, 47.031%; route: 4.148, 49.507%; tC2Q: 0.290, 3.462%
Required Clock Path Delay: cell: 0.853, 65.468%; route: 0.450, 34.532%

Path 4

Path Summary:
Slack 1.659
Data Arrival Time 9.601
Data Required Time 11.259
From u_tx/u_dsi_tx/u_dphy/u_data_buf/rEmpty_s1
To u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_4_s1
Launch Clk I_BYTE_CLK[R]
Latch Clk I_BYTE_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_BYTE_CLK
0.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
0.853 0.853 tINS RR 487 I_BYTE_CLK_ibuf/O
1.303 0.450 tNET RR 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/rEmpty_s1/CLK
1.593 0.290 tC2Q RF 9 u_tx/u_dsi_tx/u_dphy/u_data_buf/rEmpty_s1/Q
2.186 0.593 tNET FF 1 u_tx/u_dsi_tx/u_dphy/wDataRd_s3/I0
2.832 0.646 tINS FF 4 u_tx/u_dsi_tx/u_dphy/wDataRd_s3/F
3.424 0.593 tNET FF 1 u_tx/u_dsi_tx/u_dphy/wDataRd_s2/I1
4.118 0.694 tINS FF 10 u_tx/u_dsi_tx/u_dphy/wDataRd_s2/F
4.711 0.593 tNET FF 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/rFull_s4/I2
5.277 0.566 tINS FF 6 u_tx/u_dsi_tx/u_dphy/u_data_buf/rFull_s4/F
5.869 0.593 tNET FF 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n56_s1/I2
6.436 0.566 tINS FF 4 u_tx/u_dsi_tx/u_dphy/u_data_buf/n56_s1/F
7.028 0.593 tNET FF 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n55_s1/I1
7.722 0.694 tINS FF 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n55_s1/F
8.314 0.593 tNET FF 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n55_s0/I1
9.008 0.694 tINS FF 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n55_s0/F
9.601 0.593 tNET FF 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_4_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_BYTE_CLK
10.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
10.853 0.853 tINS RR 487 I_BYTE_CLK_ibuf/O
11.303 0.450 tNET RR 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_4_s1/CLK
11.259 -0.044 tSu 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_4_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.853, 65.468%; route: 0.450, 34.532%
Arrival Data Path Delay: cell: 3.860, 46.520%; route: 4.148, 49.985%; tC2Q: 0.290, 3.495%
Required Clock Path Delay: cell: 0.853, 65.468%; route: 0.450, 34.532%

Path 5

Path Summary:
Slack 1.659
Data Arrival Time 9.601
Data Required Time 11.259
From u_tx/u_dsi_tx/u_dphy/u_data_buf/rEmpty_s1
To u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_8_s1
Launch Clk I_BYTE_CLK[R]
Latch Clk I_BYTE_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_BYTE_CLK
0.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
0.853 0.853 tINS RR 487 I_BYTE_CLK_ibuf/O
1.303 0.450 tNET RR 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/rEmpty_s1/CLK
1.593 0.290 tC2Q RF 9 u_tx/u_dsi_tx/u_dphy/u_data_buf/rEmpty_s1/Q
2.186 0.593 tNET FF 1 u_tx/u_dsi_tx/u_dphy/wDataRd_s3/I0
2.832 0.646 tINS FF 4 u_tx/u_dsi_tx/u_dphy/wDataRd_s3/F
3.424 0.593 tNET FF 1 u_tx/u_dsi_tx/u_dphy/wDataRd_s2/I1
4.118 0.694 tINS FF 10 u_tx/u_dsi_tx/u_dphy/wDataRd_s2/F
4.711 0.593 tNET FF 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n58_s1/I1
5.404 0.694 tINS FF 4 u_tx/u_dsi_tx/u_dphy/u_data_buf/n58_s1/F
5.997 0.593 tNET FF 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n53_s2/I2
6.563 0.566 tINS FF 5 u_tx/u_dsi_tx/u_dphy/u_data_buf/n53_s2/F
7.156 0.593 tNET FF 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n51_s2/I2
7.722 0.566 tINS FF 2 u_tx/u_dsi_tx/u_dphy/u_data_buf/n51_s2/F
8.314 0.593 tNET FF 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n51_s0/I1
9.008 0.694 tINS FF 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n51_s0/F
9.601 0.593 tNET FF 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_8_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_BYTE_CLK
10.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
10.853 0.853 tINS RR 487 I_BYTE_CLK_ibuf/O
11.303 0.450 tNET RR 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_8_s1/CLK
11.259 -0.044 tSu 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_8_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.853, 65.468%; route: 0.450, 34.532%
Arrival Data Path Delay: cell: 3.860, 46.520%; route: 4.148, 49.985%; tC2Q: 0.290, 3.495%
Required Clock Path Delay: cell: 0.853, 65.468%; route: 0.450, 34.532%