Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Programs\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\MIPI_DSI_CSI2_TX\data\dsi_csi2_tx_wrap.v
D:\Programs\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\MIPI_DSI_CSI2_TX\data\dsi_csi2_tx.v
GowinSynthesis Constraints File ---
Tool Version V1.9.9.01 (64-bit)
Part Number GW1NR-LV9MG100PC7/I6
Device GW1NR-9
Device Version C
Created Time Wed Mar 6 09:51:12 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module DSI_TX_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.338s, Peak memory usage = 116.402MB
Running netlist conversion:
    CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.025s, Peak memory usage = 116.402MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.098s, Peak memory usage = 116.402MB
    Optimizing Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.047s, Peak memory usage = 116.402MB
    Optimizing Phase 2: CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.168s, Peak memory usage = 116.402MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.037s, Peak memory usage = 116.402MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 116.402MB
    Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 116.402MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 116.402MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.187s, Elapsed time = 0h 0m 0.189s, Peak memory usage = 116.402MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.021s, Peak memory usage = 116.402MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.041s, Peak memory usage = 116.402MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 14s, Elapsed time = 0h 0m 14s, Peak memory usage = 148.652MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.129s, Peak memory usage = 148.652MB
Generate output files:
    CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.29s, Peak memory usage = 148.652MB
Total Time and Memory Usage CPU time = 0h 0m 15s, Elapsed time = 0h 0m 15s, Peak memory usage = 148.652MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 181
I/O Buf 181
    IBUF 95
    OBUF 86
Register 628
    DFF 129
    DFFE 236
    DFFS 6
    DFFSE 16
    DFFR 110
    DFFRE 26
    DFFPE 18
    DFFC 58
    DFFCE 29
LUT 2442
    LUT2 168
    LUT3 1032
    LUT4 1242
ALU 4
    ALU 4
SSRAM 4
    RAM16SDP4 4
INV 4
    INV 4
BSRAM 2
    SDPX9B 2

Resource Utilization Summary

Resource Usage Utilization
Logic 2474(2446 LUT, 4 ALU, 4 RAM16) / 8640 29%
Register 628 / 6741 10%
  --Register as Latch 0 / 6741 0%
  --Register as FF 628 / 6741 10%
BSRAM 2 / 26 8%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
I_BYTE_CLK Base 20.000 50.0 0.000 10.000 I_BYTE_CLK_ibuf/I

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 I_BYTE_CLK 50.000(MHz) 75.160(MHz) 9 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 6.695
Data Arrival Time 14.274
Data Required Time 20.969
From u_tx/u_dsi_tx/u_dphy/u_data_buf/rEmpty_s1
To u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_9_s1
Launch Clk I_BYTE_CLK[R]
Latch Clk I_BYTE_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_BYTE_CLK
0.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
0.728 0.728 tINS RR 636 I_BYTE_CLK_ibuf/O
1.266 0.538 tNET RR 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/rEmpty_s1/CLK
1.605 0.340 tC2Q RF 9 u_tx/u_dsi_tx/u_dphy/u_data_buf/rEmpty_s1/Q
2.317 0.711 tNET FF 1 u_tx/u_dsi_tx/u_dphy/wDataRd_s3/I0
3.081 0.765 tINS FF 5 u_tx/u_dsi_tx/u_dphy/wDataRd_s3/F
3.793 0.711 tNET FF 1 u_tx/u_dsi_tx/u_dphy/wDataRd_s2/I0
4.557 0.765 tINS FF 12 u_tx/u_dsi_tx/u_dphy/wDataRd_s2/F
5.269 0.711 tNET FF 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n54_s1/I1
6.083 0.814 tINS FF 5 u_tx/u_dsi_tx/u_dphy/u_data_buf/n54_s1/F
6.794 0.711 tNET FF 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n92_s6/I0
7.559 0.765 tINS FF 2 u_tx/u_dsi_tx/u_dphy/u_data_buf/n92_s6/F
8.270 0.711 tNET FF 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n50_s5/I0
9.035 0.765 tINS FF 6 u_tx/u_dsi_tx/u_dphy/u_data_buf/n50_s5/F
9.747 0.711 tNET FF 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n47_s1/I0
10.511 0.765 tINS FF 2 u_tx/u_dsi_tx/u_dphy/u_data_buf/n47_s1/F
11.223 0.711 tNET FF 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n46_s1/I1
12.037 0.814 tINS FF 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n46_s1/F
12.748 0.711 tNET FF 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n46_s0/I1
13.563 0.814 tINS FF 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n46_s0/F
14.274 0.711 tNET FF 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_9_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 I_BYTE_CLK
20.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
20.728 0.728 tINS RR 636 I_BYTE_CLK_ibuf/O
21.266 0.538 tNET RR 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_9_s1/CLK
20.969 -0.296 tSu 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_9_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.728, 57.491%; route: 0.538, 42.509%
Arrival Data Path Delay: cell: 6.267, 48.173%; route: 6.402, 49.216%; tC2Q: 0.340, 2.611%
Required Clock Path Delay: cell: 0.728, 57.491%; route: 0.538, 42.509%

Path 2

Path Summary:
Slack 8.221
Data Arrival Time 12.748
Data Required Time 20.969
From u_tx/u_dsi_tx/u_dphy/u_data_buf/rEmpty_s1
To u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_6_s1
Launch Clk I_BYTE_CLK[R]
Latch Clk I_BYTE_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_BYTE_CLK
0.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
0.728 0.728 tINS RR 636 I_BYTE_CLK_ibuf/O
1.266 0.538 tNET RR 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/rEmpty_s1/CLK
1.605 0.340 tC2Q RF 9 u_tx/u_dsi_tx/u_dphy/u_data_buf/rEmpty_s1/Q
2.317 0.711 tNET FF 1 u_tx/u_dsi_tx/u_dphy/wDataRd_s3/I0
3.081 0.765 tINS FF 5 u_tx/u_dsi_tx/u_dphy/wDataRd_s3/F
3.793 0.711 tNET FF 1 u_tx/u_dsi_tx/u_dphy/wDataRd_s2/I0
4.557 0.765 tINS FF 12 u_tx/u_dsi_tx/u_dphy/wDataRd_s2/F
5.269 0.711 tNET FF 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n54_s1/I1
6.083 0.814 tINS FF 5 u_tx/u_dsi_tx/u_dphy/u_data_buf/n54_s1/F
6.794 0.711 tNET FF 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n92_s6/I0
7.559 0.765 tINS FF 2 u_tx/u_dsi_tx/u_dphy/u_data_buf/n92_s6/F
8.270 0.711 tNET FF 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n50_s5/I0
9.035 0.765 tINS FF 6 u_tx/u_dsi_tx/u_dphy/u_data_buf/n50_s5/F
9.747 0.711 tNET FF 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n49_s1/I0
10.511 0.765 tINS FF 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n49_s1/F
11.223 0.711 tNET FF 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n49_s0/I1
12.037 0.814 tINS FF 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n49_s0/F
12.748 0.711 tNET FF 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_6_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 I_BYTE_CLK
20.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
20.728 0.728 tINS RR 636 I_BYTE_CLK_ibuf/O
21.266 0.538 tNET RR 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_6_s1/CLK
20.969 -0.296 tSu 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_6_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 8
Arrival Clock Path Delay: cell: 0.728, 57.491%; route: 0.538, 42.509%
Arrival Data Path Delay: cell: 5.452, 47.482%; route: 5.691, 49.560%; tC2Q: 0.340, 2.958%
Required Clock Path Delay: cell: 0.728, 57.491%; route: 0.538, 42.509%

Path 3

Path Summary:
Slack 8.270
Data Arrival Time 12.699
Data Required Time 20.969
From u_tx/u_dsi_tx/u_dphy/u_data_buf/rEmpty_s1
To u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_8_s1
Launch Clk I_BYTE_CLK[R]
Latch Clk I_BYTE_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_BYTE_CLK
0.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
0.728 0.728 tINS RR 636 I_BYTE_CLK_ibuf/O
1.266 0.538 tNET RR 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/rEmpty_s1/CLK
1.605 0.340 tC2Q RF 9 u_tx/u_dsi_tx/u_dphy/u_data_buf/rEmpty_s1/Q
2.317 0.711 tNET FF 1 u_tx/u_dsi_tx/u_dphy/wDataRd_s3/I0
3.081 0.765 tINS FF 5 u_tx/u_dsi_tx/u_dphy/wDataRd_s3/F
3.793 0.711 tNET FF 1 u_tx/u_dsi_tx/u_dphy/wDataRd_s2/I0
4.557 0.765 tINS FF 12 u_tx/u_dsi_tx/u_dphy/wDataRd_s2/F
5.269 0.711 tNET FF 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n54_s1/I1
6.083 0.814 tINS FF 5 u_tx/u_dsi_tx/u_dphy/u_data_buf/n54_s1/F
6.794 0.711 tNET FF 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n92_s6/I0
7.559 0.765 tINS FF 2 u_tx/u_dsi_tx/u_dphy/u_data_buf/n92_s6/F
8.270 0.711 tNET FF 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n50_s5/I0
9.035 0.765 tINS FF 6 u_tx/u_dsi_tx/u_dphy/u_data_buf/n50_s5/F
9.747 0.711 tNET FF 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n47_s1/I0
10.511 0.765 tINS FF 2 u_tx/u_dsi_tx/u_dphy/u_data_buf/n47_s1/F
11.223 0.711 tNET FF 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n47_s0/I0
11.987 0.765 tINS FF 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n47_s0/F
12.699 0.711 tNET FF 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_8_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 I_BYTE_CLK
20.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
20.728 0.728 tINS RR 636 I_BYTE_CLK_ibuf/O
21.266 0.538 tNET RR 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_8_s1/CLK
20.969 -0.296 tSu 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_8_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 8
Arrival Clock Path Delay: cell: 0.728, 57.491%; route: 0.538, 42.509%
Arrival Data Path Delay: cell: 5.403, 47.254%; route: 5.691, 49.775%; tC2Q: 0.340, 2.971%
Required Clock Path Delay: cell: 0.728, 57.491%; route: 0.538, 42.509%

Path 4

Path Summary:
Slack 9.647
Data Arrival Time 11.322
Data Required Time 20.969
From u_tx/u_dsi_tx/rLpCrc_4_s1
To u_tx/u_dsi_tx/rLpCrc_13_s1
Launch Clk I_BYTE_CLK[R]
Latch Clk I_BYTE_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_BYTE_CLK
0.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
0.728 0.728 tINS RR 636 I_BYTE_CLK_ibuf/O
1.266 0.538 tNET RR 1 u_tx/u_dsi_tx/rLpCrc_4_s1/CLK
1.605 0.340 tC2Q RF 31 u_tx/u_dsi_tx/rLpCrc_4_s1/Q
2.317 0.711 tNET FF 1 u_tx/u_dsi_tx/n4099_s20/I1
3.131 0.814 tINS FF 6 u_tx/u_dsi_tx/n4099_s20/F
3.842 0.711 tNET FF 1 u_tx/u_dsi_tx/n4087_s50/I1
4.657 0.814 tINS FF 2 u_tx/u_dsi_tx/n4087_s50/F
5.368 0.711 tNET FF 1 u_tx/u_dsi_tx/n4086_s18/I1
6.182 0.814 tINS FF 1 u_tx/u_dsi_tx/n4086_s18/F
6.894 0.711 tNET FF 1 u_tx/u_dsi_tx/n4086_s7/I0
7.658 0.765 tINS FF 1 u_tx/u_dsi_tx/n4086_s7/F
8.370 0.711 tNET FF 1 u_tx/u_dsi_tx/n4086_s3/I0
9.134 0.765 tINS FF 1 u_tx/u_dsi_tx/n4086_s3/F
9.846 0.711 tNET FF 1 u_tx/u_dsi_tx/n4086_s2/I0
10.611 0.765 tINS FF 1 u_tx/u_dsi_tx/n4086_s2/F
11.322 0.711 tNET FF 1 u_tx/u_dsi_tx/rLpCrc_13_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 I_BYTE_CLK
20.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
20.728 0.728 tINS RR 636 I_BYTE_CLK_ibuf/O
21.266 0.538 tNET RR 1 u_tx/u_dsi_tx/rLpCrc_13_s1/CLK
20.969 -0.296 tSu 1 u_tx/u_dsi_tx/rLpCrc_13_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.728, 57.491%; route: 0.538, 42.509%
Arrival Data Path Delay: cell: 4.737, 47.107%; route: 4.980, 49.516%; tC2Q: 0.340, 3.377%
Required Clock Path Delay: cell: 0.728, 57.491%; route: 0.538, 42.509%

Path 5

Path Summary:
Slack 9.697
Data Arrival Time 11.272
Data Required Time 20.969
From u_tx/u_dsi_tx/u_dphy/u_data_buf/rEmpty_s1
To u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_3_s1
Launch Clk I_BYTE_CLK[R]
Latch Clk I_BYTE_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_BYTE_CLK
0.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
0.728 0.728 tINS RR 636 I_BYTE_CLK_ibuf/O
1.266 0.538 tNET RR 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/rEmpty_s1/CLK
1.605 0.340 tC2Q RF 9 u_tx/u_dsi_tx/u_dphy/u_data_buf/rEmpty_s1/Q
2.317 0.711 tNET FF 1 u_tx/u_dsi_tx/u_dphy/wDataRd_s3/I0
3.081 0.765 tINS FF 5 u_tx/u_dsi_tx/u_dphy/wDataRd_s3/F
3.793 0.711 tNET FF 1 u_tx/u_dsi_tx/u_dphy/wDataRd_s2/I0
4.557 0.765 tINS FF 12 u_tx/u_dsi_tx/u_dphy/wDataRd_s2/F
5.269 0.711 tNET FF 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n54_s1/I1
6.083 0.814 tINS FF 5 u_tx/u_dsi_tx/u_dphy/u_data_buf/n54_s1/F
6.794 0.711 tNET FF 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n92_s6/I0
7.559 0.765 tINS FF 2 u_tx/u_dsi_tx/u_dphy/u_data_buf/n92_s6/F
8.270 0.711 tNET FF 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n50_s5/I0
9.035 0.765 tINS FF 6 u_tx/u_dsi_tx/u_dphy/u_data_buf/n50_s5/F
9.747 0.711 tNET FF 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n52_s0/I1
10.561 0.814 tINS FF 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n52_s0/F
11.272 0.711 tNET FF 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_3_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 I_BYTE_CLK
20.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
20.728 0.728 tINS RR 636 I_BYTE_CLK_ibuf/O
21.266 0.538 tNET RR 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_3_s1/CLK
20.969 -0.296 tSu 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_3_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.728, 57.491%; route: 0.538, 42.509%
Arrival Data Path Delay: cell: 4.688, 46.844%; route: 4.980, 49.762%; tC2Q: 0.340, 3.394%
Required Clock Path Delay: cell: 0.728, 57.491%; route: 0.538, 42.509%