Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Programs\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\MIPI_DSI_CSI2_TX\data\dsi_csi2_tx_wrap.v
D:\Programs\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\MIPI_DSI_CSI2_TX\data\dsi_csi2_tx.v
GowinSynthesis Constraints File ---
Tool Version V1.9.9.01 (64-bit)
Part Number GW5A-LV25MG121NC1/I0
Device GW5A-25
Device Version A
Created Time Wed Mar 6 16:44:53 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module MIPI_DSI_TX_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.296s, Elapsed time = 0h 0m 0.311s, Peak memory usage = 118.547MB
Running netlist conversion:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 118.547MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.047s, Peak memory usage = 118.547MB
    Optimizing Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.027s, Peak memory usage = 118.547MB
    Optimizing Phase 2: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.08s, Peak memory usage = 118.547MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 118.547MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 118.547MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 118.547MB
    Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 118.547MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.094s, Peak memory usage = 118.547MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 118.547MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.015s, Peak memory usage = 118.547MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 5s, Elapsed time = 0h 0m 5s, Peak memory usage = 146.242MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.077s, Peak memory usage = 146.242MB
Generate output files:
    CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.115s, Peak memory usage = 146.242MB
Total Time and Memory Usage CPU time = 0h 0m 5s, Elapsed time = 0h 0m 5s, Peak memory usage = 146.242MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 109
I/O Buf 109
    IBUF 63
    OBUF 46
Register 477
    DFFSE 22
    DFFRE 279
    DFFPE 18
    DFFCE 158
LUT 1249
    LUT2 85
    LUT3 528
    LUT4 636
ALU 4
    ALU 4
INV 5
    INV 5
BSRAM 3
    SDPB 1
    SDPX9B 2

Resource Utilization Summary

Resource Usage Utilization
Logic 1258(1254 LUT, 4 ALU) / 23040 6%
Register 477 / 23280 3%
  --Register as Latch 0 / 23280 0%
  --Register as FF 477 / 23280 3%
BSRAM 3 / 56 6%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
I_BYTE_CLK Base 10.000 100.0 0.000 5.000 I_BYTE_CLK_ibuf/I

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 I_BYTE_CLK 100.000(MHz) 145.852(MHz) 8 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 3.144
Data Arrival Time 7.850
Data Required Time 10.994
From u_tx/u_dsi_tx/u_dphy/u_data_buf/rEmpty_s1
To u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_10_s1
Launch Clk I_BYTE_CLK[R]
Latch Clk I_BYTE_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_BYTE_CLK
0.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
0.683 0.683 tINS RR 483 I_BYTE_CLK_ibuf/O
1.058 0.375 tNET RR 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/rEmpty_s1/CLK
1.440 0.382 tC2Q RR 10 u_tx/u_dsi_tx/u_dphy/u_data_buf/rEmpty_s1/Q
1.815 0.375 tNET RR 1 u_tx/u_dsi_tx/u_dphy/wDataRd_s3/I0
2.341 0.526 tINS RR 3 u_tx/u_dsi_tx/u_dphy/wDataRd_s3/F
2.716 0.375 tNET RR 1 u_tx/u_dsi_tx/u_dphy/wDataRd_s2/I0
3.242 0.526 tINS RR 12 u_tx/u_dsi_tx/u_dphy/wDataRd_s2/F
3.617 0.375 tNET RR 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n58_s1/I1
4.134 0.516 tINS RR 2 u_tx/u_dsi_tx/u_dphy/u_data_buf/n58_s1/F
4.509 0.375 tNET RR 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n56_s2/I3
4.771 0.262 tINS RR 4 u_tx/u_dsi_tx/u_dphy/u_data_buf/n56_s2/F
5.146 0.375 tNET RR 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n53_s2/I0
5.672 0.526 tINS RR 6 u_tx/u_dsi_tx/u_dphy/u_data_buf/n53_s2/F
6.047 0.375 tNET RR 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n49_s1/I0
6.574 0.526 tINS RR 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n49_s1/F
6.949 0.375 tNET RR 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n49_s0/I0
7.475 0.526 tINS RR 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n49_s0/F
7.850 0.375 tNET RR 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_10_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_BYTE_CLK
10.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
10.682 0.683 tINS RR 483 I_BYTE_CLK_ibuf/O
11.057 0.375 tNET RR 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_10_s1/CLK
10.994 -0.064 tSu 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_10_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 8
Arrival Clock Path Delay: cell: 0.683, 64.539%; route: 0.375, 35.461%
Arrival Data Path Delay: cell: 3.410, 50.203%; route: 3.000, 44.166%; tC2Q: 0.382, 5.631%
Required Clock Path Delay: cell: 0.683, 64.539%; route: 0.375, 35.461%

Path 2

Path Summary:
Slack 3.144
Data Arrival Time 7.850
Data Required Time 10.994
From u_tx/u_dsi_tx/u_dphy/u_data_buf/rEmpty_s1
To u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_7_s1
Launch Clk I_BYTE_CLK[R]
Latch Clk I_BYTE_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_BYTE_CLK
0.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
0.683 0.683 tINS RR 483 I_BYTE_CLK_ibuf/O
1.058 0.375 tNET RR 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/rEmpty_s1/CLK
1.440 0.382 tC2Q RR 10 u_tx/u_dsi_tx/u_dphy/u_data_buf/rEmpty_s1/Q
1.815 0.375 tNET RR 1 u_tx/u_dsi_tx/u_dphy/wDataRd_s3/I0
2.341 0.526 tINS RR 3 u_tx/u_dsi_tx/u_dphy/wDataRd_s3/F
2.716 0.375 tNET RR 1 u_tx/u_dsi_tx/u_dphy/wDataRd_s2/I0
3.242 0.526 tINS RR 12 u_tx/u_dsi_tx/u_dphy/wDataRd_s2/F
3.617 0.375 tNET RR 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n58_s1/I1
4.134 0.516 tINS RR 2 u_tx/u_dsi_tx/u_dphy/u_data_buf/n58_s1/F
4.509 0.375 tNET RR 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n56_s2/I3
4.771 0.262 tINS RR 4 u_tx/u_dsi_tx/u_dphy/u_data_buf/n56_s2/F
5.146 0.375 tNET RR 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n53_s2/I0
5.672 0.526 tINS RR 6 u_tx/u_dsi_tx/u_dphy/u_data_buf/n53_s2/F
6.047 0.375 tNET RR 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n52_s1/I0
6.574 0.526 tINS RR 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n52_s1/F
6.949 0.375 tNET RR 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n52_s0/I0
7.475 0.526 tINS RR 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n52_s0/F
7.850 0.375 tNET RR 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_7_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_BYTE_CLK
10.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
10.682 0.683 tINS RR 483 I_BYTE_CLK_ibuf/O
11.057 0.375 tNET RR 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_7_s1/CLK
10.994 -0.064 tSu 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_7_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 8
Arrival Clock Path Delay: cell: 0.683, 64.539%; route: 0.375, 35.461%
Arrival Data Path Delay: cell: 3.410, 50.203%; route: 3.000, 44.166%; tC2Q: 0.382, 5.631%
Required Clock Path Delay: cell: 0.683, 64.539%; route: 0.375, 35.461%

Path 3

Path Summary:
Slack 3.209
Data Arrival Time 7.785
Data Required Time 10.994
From u_tx/u_dsi_tx/u_dphy/u_data_buf/rEmpty_s1
To u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_8_s1
Launch Clk I_BYTE_CLK[R]
Latch Clk I_BYTE_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_BYTE_CLK
0.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
0.683 0.683 tINS RR 483 I_BYTE_CLK_ibuf/O
1.058 0.375 tNET RR 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/rEmpty_s1/CLK
1.440 0.382 tC2Q RR 10 u_tx/u_dsi_tx/u_dphy/u_data_buf/rEmpty_s1/Q
1.815 0.375 tNET RR 1 u_tx/u_dsi_tx/u_dphy/wDataRd_s3/I0
2.341 0.526 tINS RR 3 u_tx/u_dsi_tx/u_dphy/wDataRd_s3/F
2.716 0.375 tNET RR 1 u_tx/u_dsi_tx/u_dphy/wDataRd_s2/I0
3.242 0.526 tINS RR 12 u_tx/u_dsi_tx/u_dphy/wDataRd_s2/F
3.617 0.375 tNET RR 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n58_s1/I1
4.134 0.516 tINS RR 2 u_tx/u_dsi_tx/u_dphy/u_data_buf/n58_s1/F
4.509 0.375 tNET RR 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n56_s2/I3
4.771 0.262 tINS RR 4 u_tx/u_dsi_tx/u_dphy/u_data_buf/n56_s2/F
5.146 0.375 tNET RR 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n53_s2/I0
5.672 0.526 tINS RR 6 u_tx/u_dsi_tx/u_dphy/u_data_buf/n53_s2/F
6.047 0.375 tNET RR 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n51_s2/I0
6.574 0.526 tINS RR 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n51_s2/F
6.949 0.375 tNET RR 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n51_s0/I2
7.410 0.461 tINS RR 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n51_s0/F
7.785 0.375 tNET RR 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_8_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_BYTE_CLK
10.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
10.682 0.683 tINS RR 483 I_BYTE_CLK_ibuf/O
11.057 0.375 tNET RR 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_8_s1/CLK
10.994 -0.064 tSu 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_8_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 8
Arrival Clock Path Delay: cell: 0.683, 64.539%; route: 0.375, 35.461%
Arrival Data Path Delay: cell: 3.345, 49.721%; route: 3.000, 44.593%; tC2Q: 0.382, 5.686%
Required Clock Path Delay: cell: 0.683, 64.539%; route: 0.375, 35.461%

Path 4

Path Summary:
Slack 3.911
Data Arrival Time 7.082
Data Required Time 10.994
From u_tx/u_dsi_tx/u_dphy/u_data_buf/rEmpty_s1
To u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_4_s1
Launch Clk I_BYTE_CLK[R]
Latch Clk I_BYTE_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_BYTE_CLK
0.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
0.683 0.683 tINS RR 483 I_BYTE_CLK_ibuf/O
1.058 0.375 tNET RR 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/rEmpty_s1/CLK
1.440 0.382 tC2Q RR 10 u_tx/u_dsi_tx/u_dphy/u_data_buf/rEmpty_s1/Q
1.815 0.375 tNET RR 1 u_tx/u_dsi_tx/u_dphy/wDataRd_s3/I0
2.341 0.526 tINS RR 3 u_tx/u_dsi_tx/u_dphy/wDataRd_s3/F
2.716 0.375 tNET RR 1 u_tx/u_dsi_tx/u_dphy/wDataRd_s2/I0
3.242 0.526 tINS RR 12 u_tx/u_dsi_tx/u_dphy/wDataRd_s2/F
3.617 0.375 tNET RR 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/rFull_s4/I2
4.079 0.461 tINS RR 4 u_tx/u_dsi_tx/u_dphy/u_data_buf/rFull_s4/F
4.454 0.375 tNET RR 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n56_s1/I2
4.915 0.461 tINS RR 4 u_tx/u_dsi_tx/u_dphy/u_data_buf/n56_s1/F
5.290 0.375 tNET RR 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n55_s1/I1
5.806 0.516 tINS RR 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n55_s1/F
6.181 0.375 tNET RR 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n55_s0/I0
6.707 0.526 tINS RR 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n55_s0/F
7.082 0.375 tNET RR 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_4_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_BYTE_CLK
10.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
10.682 0.683 tINS RR 483 I_BYTE_CLK_ibuf/O
11.057 0.375 tNET RR 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_4_s1/CLK
10.994 -0.064 tSu 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_4_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.683, 64.539%; route: 0.375, 35.461%
Arrival Data Path Delay: cell: 3.017, 50.083%; route: 2.625, 43.568%; tC2Q: 0.382, 6.349%
Required Clock Path Delay: cell: 0.683, 64.539%; route: 0.375, 35.461%

Path 5

Path Summary:
Slack 4.045
Data Arrival Time 6.949
Data Required Time 10.994
From u_tx/u_dsi_tx/u_dphy/u_data_buf/rEmpty_s1
To u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_5_s1
Launch Clk I_BYTE_CLK[R]
Latch Clk I_BYTE_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_BYTE_CLK
0.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
0.683 0.683 tINS RR 483 I_BYTE_CLK_ibuf/O
1.058 0.375 tNET RR 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/rEmpty_s1/CLK
1.440 0.382 tC2Q RR 10 u_tx/u_dsi_tx/u_dphy/u_data_buf/rEmpty_s1/Q
1.815 0.375 tNET RR 1 u_tx/u_dsi_tx/u_dphy/wDataRd_s3/I0
2.341 0.526 tINS RR 3 u_tx/u_dsi_tx/u_dphy/wDataRd_s3/F
2.716 0.375 tNET RR 1 u_tx/u_dsi_tx/u_dphy/wDataRd_s2/I0
3.242 0.526 tINS RR 12 u_tx/u_dsi_tx/u_dphy/wDataRd_s2/F
3.617 0.375 tNET RR 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n58_s1/I1
4.134 0.516 tINS RR 2 u_tx/u_dsi_tx/u_dphy/u_data_buf/n58_s1/F
4.509 0.375 tNET RR 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n56_s2/I3
4.771 0.262 tINS RR 4 u_tx/u_dsi_tx/u_dphy/u_data_buf/n56_s2/F
5.146 0.375 tNET RR 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n53_s2/I0
5.672 0.526 tINS RR 6 u_tx/u_dsi_tx/u_dphy/u_data_buf/n53_s2/F
6.047 0.375 tNET RR 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n54_s0/I0
6.574 0.526 tINS RR 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/n54_s0/F
6.949 0.375 tNET RR 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_5_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_BYTE_CLK
10.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
10.682 0.683 tINS RR 483 I_BYTE_CLK_ibuf/O
11.057 0.375 tNET RR 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_5_s1/CLK
10.994 -0.064 tSu 1 u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_5_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.683, 64.539%; route: 0.375, 35.461%
Arrival Data Path Delay: cell: 2.884, 48.949%; route: 2.625, 44.558%; tC2Q: 0.382, 6.493%
Required Clock Path Delay: cell: 0.683, 64.539%; route: 0.375, 35.461%