Power Messages

Report Title Power Analysis Report
Design File F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\DSI_Test_Pattern_1nr9\fpga_proj\impl\gwsynthesis\Dsi_test_pattern.vg
Physical Constraints File F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\DSI_Test_Pattern_1nr9\fpga_proj\src\dsi_test.cst
Timing Constraints File F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\DSI_Test_Pattern_1nr9\fpga_proj\src\dsi_test.sdc
Tool Version V1.9.9.01 (64-bit)
Part Number GW1NR-LV9MG100PC7/I6
Device GW1NR-9
Device Version C
Created Time Wed Mar 6 09:56:51 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

Power Summary

Power Information:

Total Power (mW) 23.287
Quiescent Power (mW) 8.482
Dynamic Power (mW) 14.805
Psram Power (mW) 172.000

Thermal Information:

Junction Temperature 26.166
Theta JA 49.470
Max Allowed Ambient Temperature 83.834

Configure Information:

Default IO Toggle Rate 0.125
Default Remain Toggle Rate 0.125
Use Vectorless Estimation false
Filter Glitches false
Related Vcd File
Related Saif File
Use Custom Theta JA false
Air Flow LFM_0
Heat Sink None
Use Custom Theta SA false
Board Thermal Model None
Use Custom Theta JB false
Ambient Temperature 25.000

Supply Information:

Voltage Source Voltage Dynamic Current(mA) Quiescent Current(mA) Power(mW)
VCC 1.200 12.013 1.964 16.773
VCCX 2.500 0.091 2.424 6.288
VCCIO18 1.800 0.090 0.036 0.227

Power Details

Power By Block Type:

Block Type Total Power(mW) Static Power(mW) Average Toggle Rate(millions of transitions/sec)
Logic 0.742 NA 8.613
IO 0.697 0.198 21.953
BSRAM 4.641 NA NA
PLL 8.896 NA NA

Power By Hierarchy:

Hierarchy Entity Total Power(mW) Block Dynamic Power(mW)
DsiTest_Top 14.279 14.279(14.159)
DsiTest_Top/u_dsi_tx/ 5.036 5.036(5.036)
DsiTest_Top/u_dsi_tx/u_tx/ 5.036 5.036(5.034)
DsiTest_Top/u_dsi_tx/u_tx/u_dsi_tx/ 5.034 5.034(4.686)
DsiTest_Top/u_dsi_tx/u_tx/u_dsi_tx/u_dphy/ 4.686 4.686(4.665)
DsiTest_Top/u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/ 0.013 0.013(0.004)
DsiTest_Top/u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/ 0.004 0.004(0.000)
DsiTest_Top/u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/ 4.651 4.651(4.641)
DsiTest_Top/u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/ 4.641 4.641(0.000)
DsiTest_Top/u_p2b/ 0.133 0.133(0.133)
DsiTest_Top/u_p2b/u_p2b_0/ 0.133 0.133(0.047)
DsiTest_Top/u_p2b/u_p2b_0/GEN_FOR_I[0].u_pulse_dly/ 0.000 0.000(0.000)
DsiTest_Top/u_p2b/u_p2b_0/GEN_FOR_I[1].u_pulse_dly/ 0.000 0.000(0.000)
DsiTest_Top/u_p2b/u_p2b_0/GEN_FOR_I[2].u_pulse_dly/ 0.000 0.000(0.000)
DsiTest_Top/u_p2b/u_p2b_0/GEN_FOR_I[3].u_pulse_dly/ 0.000 0.000(0.000)
DsiTest_Top/u_p2b/u_p2b_0/u_mid_buf/ 0.046 0.046(0.014)
DsiTest_Top/u_p2b/u_p2b_0/u_mid_buf/u_dpram/ 0.014 0.014(0.000)
DsiTest_Top/u_pll/ 8.896 8.896(0.000)
DsiTest_Top/u_test_gen/ 0.093 0.093(0.000)
DsiTest_Top/u_tx_phy/ 0.001 0.001(0.001)
DsiTest_Top/u_tx_phy/DPHY_TX_INST/ 0.001 0.001(0.001)
DsiTest_Top/u_tx_phy/DPHY_TX_INST/u_oserx4x8/ 0.001 0.001(0.000)

Power By Clock Domain:

Clock Domain Clock Frequency(Mhz) Total Dynamic Power(mW)
byte_clk 53.125 5.084
pixel_clk 141.667 0.310
NO CLOCK DOMAIN 0.000 0.000
u_pll/rpll_inst/CLKOUT.default_gen_clk 425.000 0.008
u_pll/rpll_inst/CLKOUTP.default_gen_clk 425.000 0.008
clk_50 50.000 8.896