Hierarchy Module Resource

MODULE NAME REG NUMBER ALU NUMBER LUT NUMBER DSP NUMBER BSRAM NUMBER SSRAM NUMBER
DsiTest_Top (F:/mySrc/MIPI_modular_IP/Ref_Design/Saved/DSI_Test_Pattern_1nr9/fpga_proj/src/top.v) 121 34 37 - - -
    |--u_pll (F:/mySrc/MIPI_modular_IP/Ref_Design/Saved/DSI_Test_Pattern_1nr9/fpga_proj/src/top.v) - - - - - -
    |--u_test_gen (F:/mySrc/MIPI_modular_IP/Ref_Design/Saved/DSI_Test_Pattern_1nr9/fpga_proj/src/top.v) 122 - 183 - - -
    |--u_p2b (F:/mySrc/MIPI_modular_IP/Ref_Design/Saved/DSI_Test_Pattern_1nr9/fpga_proj/src/top.v) 340 14 192 - - 16
    |--u_dsi_tx (F:/mySrc/MIPI_modular_IP/Ref_Design/Saved/DSI_Test_Pattern_1nr9/fpga_proj/src/top.v) 628 4 2446 - 2 4
    |--u_tx_phy (F:/mySrc/MIPI_modular_IP/Ref_Design/Saved/DSI_Test_Pattern_1nr9/fpga_proj/src/top.v) - - 11 - - -