Timing Messages
Report Title | Timing Analysis Report |
Design File | F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\Dsi_Test_pattern_2a18\fpga_proj\impl\gwsynthesis\Dsi_test_pattern_2a18.vg |
Physical Constraints File | F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\Dsi_Test_pattern_2a18\fpga_proj\src\DK_START_Gw2A18_V2.cst |
Timing Constraint File | F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\Dsi_Test_pattern_2a18\fpga_proj\src\dsi_test.sdc |
Tool Version | V1.9.9.01 (64-bit) |
Part Number | GW2A-LV18PG256C8/I7 |
Device | GW2A-18 |
Device Version | C |
Created Time | Wed Mar 6 11:19:28 2024 |
Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved. |
Timing Summaries
STA Tool Run Summary:
Setup Delay Model | Slow 0.95V 85C C8/I7 |
Hold Delay Model | Fast 1.05V 0C C8/I7 |
Numbers of Paths Analyzed | 7462 |
Numbers of Endpoints Analyzed | 5252 |
Numbers of Falling Endpoints | 0 |
Numbers of Setup Violated Endpoints | 0 |
Numbers of Hold Violated Endpoints | 0 |
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Objects |
---|---|---|---|---|---|---|---|---|
clk_50 | Base | 20.000 | 50.000 | 0.000 | 10.000 | OSC_50M | ||
pixel_clk | Generated | 7.059 | 141.667 | 0.000 | 3.529 | OSC_50M | clk_50 | pixel_clk |
byte_clk | Generated | 9.412 | 106.250 | 0.000 | 4.706 | OSC_50M | clk_50 | byte_clk |
tck_pad_i | Base | 50.000 | 20.000 | 0.000 | 25.000 | tck_ibuf/I | ||
u_pll/rpll_inst/CLKOUT.default_gen_clk | Generated | 2.353 | 425.000 | 0.000 | 1.176 | OSC_50M_ibuf/I | clk_50 | u_pll/rpll_inst/CLKOUT |
u_pll/rpll_inst/CLKOUTP.default_gen_clk | Generated | 2.353 | 425.000 | 0.588 | 1.765 | OSC_50M_ibuf/I | clk_50 | u_pll/rpll_inst/CLKOUTP |
Max Frequency Summary:
NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | pixel_clk | 141.667(MHz) | 204.893(MHz) | 7 | TOP |
2 | byte_clk | 106.250(MHz) | 130.540(MHz) | 8 | TOP |
3 | tck_pad_i | 20.000(MHz) | 119.034(MHz) | 6 | TOP |
No timing paths to get frequency of clk_50!
No timing paths to get frequency of u_pll/rpll_inst/CLKOUT.default_gen_clk!
No timing paths to get frequency of u_pll/rpll_inst/CLKOUTP.default_gen_clk!
Total Negative Slack Summary:
Clock Name | Analysis Type | Endpoints TNS | Number of Endpoints |
---|---|---|---|
clk_50 | Setup | 0.000 | 0 |
clk_50 | Hold | 0.000 | 0 |
pixel_clk | Setup | 0.000 | 0 |
pixel_clk | Hold | 0.000 | 0 |
byte_clk | Setup | 0.000 | 0 |
byte_clk | Hold | 0.000 | 0 |
tck_pad_i | Setup | 0.000 | 0 |
tck_pad_i | Hold | 0.000 | 0 |
u_pll/rpll_inst/CLKOUT.default_gen_clk | Setup | 0.000 | 0 |
u_pll/rpll_inst/CLKOUT.default_gen_clk | Hold | 0.000 | 0 |
u_pll/rpll_inst/CLKOUTP.default_gen_clk | Setup | 0.000 | 0 |
u_pll/rpll_inst/CLKOUTP.default_gen_clk | Hold | 0.000 | 0 |
Timing Details
Path Slacks Table:
Setup Paths Table
Setup Paths Table[1]:
Report Command:report_timing -setup -from_clock [get_clocks {pixel_clk}] -max_paths 20 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 2.178 | u_p2b/u_p2b_0/u_mid_buf/rRPtrWsync_3_s0/Q | u_p2b/u_p2b_0/u_mid_buf/rFull_s0/D | pixel_clk:[R] | pixel_clk:[R] | 7.059 | 0.000 | 4.846 |
2 | 2.660 | u_test_gen/De_hcnt_0_s3/Q | u_test_gen/Net_h_trig_s0/D | pixel_clk:[R] | pixel_clk:[R] | 7.059 | 0.000 | 4.363 |
3 | 2.843 | u_test_gen/H_cnt_5_s0/Q | u_test_gen/V_cnt_2_s1/D | pixel_clk:[R] | pixel_clk:[R] | 7.059 | 0.000 | 4.180 |
4 | 2.864 | u_test_gen/H_cnt_5_s0/Q | u_test_gen/V_cnt_6_s1/D | pixel_clk:[R] | pixel_clk:[R] | 7.059 | 0.000 | 4.159 |
5 | 2.864 | u_test_gen/H_cnt_5_s0/Q | u_test_gen/V_cnt_7_s1/D | pixel_clk:[R] | pixel_clk:[R] | 7.059 | 0.000 | 4.159 |
6 | 2.864 | u_test_gen/H_cnt_5_s0/Q | u_test_gen/V_cnt_8_s1/D | pixel_clk:[R] | pixel_clk:[R] | 7.059 | 0.000 | 4.159 |
7 | 2.882 | u_test_gen/H_cnt_5_s0/Q | u_test_gen/V_cnt_1_s1/D | pixel_clk:[R] | pixel_clk:[R] | 7.059 | 0.000 | 4.142 |
8 | 3.085 | u_test_gen/H_cnt_5_s0/Q | u_test_gen/V_cnt_11_s1/D | pixel_clk:[R] | pixel_clk:[R] | 7.059 | 0.000 | 3.939 |
9 | 3.085 | u_test_gen/H_cnt_5_s0/Q | u_test_gen/V_cnt_0_s1/D | pixel_clk:[R] | pixel_clk:[R] | 7.059 | 0.000 | 3.939 |
10 | 3.133 | u_test_gen/H_cnt_5_s0/Q | u_test_gen/V_cnt_3_s1/D | pixel_clk:[R] | pixel_clk:[R] | 7.059 | 0.000 | 3.890 |
11 | 3.133 | u_test_gen/H_cnt_5_s0/Q | u_test_gen/V_cnt_5_s1/D | pixel_clk:[R] | pixel_clk:[R] | 7.059 | 0.000 | 3.890 |
12 | 3.188 | u_test_gen/De_hcnt_0_s3/Q | u_test_gen/De_hcnt_9_s1/D | pixel_clk:[R] | pixel_clk:[R] | 7.059 | 0.000 | 3.836 |
13 | 3.279 | u_test_gen/De_hcnt_0_s3/Q | u_test_gen/De_hcnt_11_s1/D | pixel_clk:[R] | pixel_clk:[R] | 7.059 | 0.000 | 3.745 |
14 | 3.284 | u_test_gen/H_cnt_5_s0/Q | u_test_gen/V_cnt_4_s1/D | pixel_clk:[R] | pixel_clk:[R] | 7.059 | 0.000 | 3.740 |
15 | 3.284 | u_test_gen/H_cnt_5_s0/Q | u_test_gen/V_cnt_10_s1/D | pixel_clk:[R] | pixel_clk:[R] | 7.059 | 0.000 | 3.740 |
16 | 3.286 | u_test_gen/De_hcnt_0_s3/Q | u_test_gen/De_hcnt_10_s1/D | pixel_clk:[R] | pixel_clk:[R] | 7.059 | 0.000 | 3.737 |
17 | 3.383 | vs_cnt_9_s0/Q | u_test_gen/Data_tmp_7_s1/D | pixel_clk:[R] | pixel_clk:[R] | 7.059 | 0.000 | 3.641 |
18 | 3.386 | u_test_gen/H_cnt_5_s0/Q | u_test_gen/V_cnt_9_s1/D | pixel_clk:[R] | pixel_clk:[R] | 7.059 | 0.000 | 3.637 |
19 | 3.440 | vs_cnt_9_s0/Q | u_test_gen/Data_tmp_0_s1/D | pixel_clk:[R] | pixel_clk:[R] | 7.059 | 0.000 | 3.584 |
20 | 3.440 | vs_cnt_9_s0/Q | u_test_gen/Data_tmp_1_s1/D | pixel_clk:[R] | pixel_clk:[R] | 7.059 | 0.000 | 3.584 |
Setup Paths Table[2]:
Report Command:report_timing -setup -from_clock [get_clocks {byte_clk}] -max_paths 20 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 1.751 | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rWrOffset_8_s1/D | byte_clk:[R] | byte_clk:[R] | 9.412 | 0.000 | 7.625 |
2 | 1.751 | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rWrOffset_9_s1/D | byte_clk:[R] | byte_clk:[R] | 9.412 | 0.000 | 7.625 |
3 | 1.940 | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_4_s1/D | byte_clk:[R] | byte_clk:[R] | 9.412 | 0.000 | 7.436 |
4 | 2.066 | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rRdOffset_8_s1/D | byte_clk:[R] | byte_clk:[R] | 9.412 | 0.000 | 7.311 |
5 | 2.066 | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rRdOffset_9_s1/D | byte_clk:[R] | byte_clk:[R] | 9.412 | 0.000 | 7.311 |
6 | 2.092 | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_5_s1/D | byte_clk:[R] | byte_clk:[R] | 9.412 | 0.000 | 7.285 |
7 | 2.092 | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_6_s1/D | byte_clk:[R] | byte_clk:[R] | 9.412 | 0.000 | 7.285 |
8 | 2.216 | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rWrOffset_6_s1/D | byte_clk:[R] | byte_clk:[R] | 9.412 | 0.000 | 7.161 |
9 | 2.216 | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rWrOffset_7_s1/D | byte_clk:[R] | byte_clk:[R] | 9.412 | 0.000 | 7.161 |
10 | 2.223 | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rRdOffset_6_s1/D | byte_clk:[R] | byte_clk:[R] | 9.412 | 0.000 | 7.153 |
11 | 2.285 | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14] | u_tx_phy/DPHY_TX_INST/u_oserx4x8/U5_OSER82/D4 | byte_clk:[R] | byte_clk:[R] | 9.412 | 0.000 | 6.958 |
12 | 2.288 | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14] | u_tx_phy/DPHY_TX_INST/u_oserx4x8/U5_OSER82/D5 | byte_clk:[R] | byte_clk:[R] | 9.412 | 0.000 | 6.958 |
13 | 2.288 | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14] | u_tx_phy/DPHY_TX_INST/u_oserx4x8/U5_OSER82/D3 | byte_clk:[R] | byte_clk:[R] | 9.412 | 0.000 | 6.958 |
14 | 2.304 | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14] | u_tx_phy/DPHY_TX_INST/u_oserx4x8/U5_OSER81/D0 | byte_clk:[R] | byte_clk:[R] | 9.412 | 0.000 | 6.939 |
15 | 2.307 | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14] | u_tx_phy/DPHY_TX_INST/u_oserx4x8/U5_OSER81/D1 | byte_clk:[R] | byte_clk:[R] | 9.412 | 0.000 | 6.939 |
16 | 2.314 | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rRdOffset_7_s1/D | byte_clk:[R] | byte_clk:[R] | 9.412 | 0.000 | 7.062 |
17 | 2.339 | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rRdOffset_5_s1/D | byte_clk:[R] | byte_clk:[R] | 9.412 | 0.000 | 7.038 |
18 | 2.358 | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14] | u_tx_phy/DPHY_TX_INST/u_oserx4x8/U5_OSER80/D4 | byte_clk:[R] | byte_clk:[R] | 9.412 | 0.000 | 6.885 |
19 | 2.358 | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14] | u_tx_phy/DPHY_TX_INST/u_oserx4x8/U5_OSER80/D2 | byte_clk:[R] | byte_clk:[R] | 9.412 | 0.000 | 6.885 |
20 | 2.358 | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14] | u_tx_phy/DPHY_TX_INST/u_oserx4x8/U5_OSER80/D0 | byte_clk:[R] | byte_clk:[R] | 9.412 | 0.000 | 6.885 |
Hold Paths Table
Hold Paths Table[1]:
Report Command:report_timing -hold -from_clock [get_clocks {pixel_clk}] -max_paths 20 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 0.311 | u_p2b/u_p2b_0/mid_data_2_s1/Q | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mSsram_mSsram_0_0_s/DI[2] | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.000 | 0.323 |
2 | 0.318 | u_p2b/u_p2b_0/u_mid_buf/rRstWsync_s0/Q | u_p2b/u_p2b_0/u_mid_buf/rWrRst_s0/CE | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.000 | 0.329 |
3 | 0.334 | u_p2b/u_p2b_0/u_mid_buf/rWPtrBin_2_s0/Q | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mSsram_mSsram_0_7_s/WAD[2] | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.000 | 0.346 |
4 | 0.424 | run_cnt_2_s0/Q | run_cnt_2_s0/D | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.000 | 0.435 |
5 | 0.424 | run_cnt_6_s0/Q | run_cnt_6_s0/D | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.000 | 0.435 |
6 | 0.424 | run_cnt_8_s0/Q | run_cnt_8_s0/D | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.000 | 0.435 |
7 | 0.424 | run_cnt_12_s0/Q | run_cnt_12_s0/D | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.000 | 0.435 |
8 | 0.424 | run_cnt_14_s0/Q | run_cnt_14_s0/D | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.000 | 0.435 |
9 | 0.424 | run_cnt_18_s0/Q | run_cnt_18_s0/D | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.000 | 0.435 |
10 | 0.424 | run_cnt_20_s0/Q | run_cnt_20_s0/D | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.000 | 0.435 |
11 | 0.424 | run_cnt_24_s0/Q | run_cnt_24_s0/D | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.000 | 0.435 |
12 | 0.425 | u_p2b/u_p2b_0/loop_cnt_0_s0/Q | u_p2b/u_p2b_0/loop_cnt_0_s0/D | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.000 | 0.436 |
13 | 0.425 | u_test_gen/Color_cnt_1_s3/Q | u_test_gen/Color_cnt_1_s3/D | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.000 | 0.436 |
14 | 0.425 | u_test_gen/Color_trig_num_7_s3/Q | u_test_gen/Color_trig_num_7_s3/D | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.000 | 0.436 |
15 | 0.425 | u_test_gen/Color_cnt_3_s1/Q | u_test_gen/Color_cnt_3_s1/D | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.000 | 0.436 |
16 | 0.425 | u_test_gen/Color_trig_num_11_s1/Q | u_test_gen/Color_trig_num_11_s1/D | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.000 | 0.436 |
17 | 0.425 | u_test_gen/De_vcnt_9_s1/Q | u_test_gen/De_vcnt_9_s1/D | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.000 | 0.436 |
18 | 0.425 | u_test_gen/De_hcnt_9_s1/Q | u_test_gen/De_hcnt_9_s1/D | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.000 | 0.436 |
19 | 0.425 | frame_led_s1/Q | frame_led_s1/D | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.000 | 0.436 |
20 | 0.425 | vs_cnt_2_s0/Q | vs_cnt_2_s0/D | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.000 | 0.436 |
Hold Paths Table[2]:
Report Command:report_timing -hold -from_clock [get_clocks {byte_clk}] -max_paths 20 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 0.198 | u_la0_top/u_ao_mem_ctrl/data_reg_110_s0/Q | u_la0_top/u_ao_mem_ctrl/mem_mem_0_12_s/DI[2] | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.447 |
2 | 0.213 | u_la0_top/u_ao_mem_ctrl/data_reg_114_s0/Q | u_la0_top/u_ao_mem_ctrl/mem_mem_0_12_s/DI[6] | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.462 |
3 | 0.213 | u_la0_top/u_ao_mem_ctrl/data_reg_113_s0/Q | u_la0_top/u_ao_mem_ctrl/mem_mem_0_12_s/DI[5] | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.462 |
4 | 0.213 | u_la0_top/u_ao_mem_ctrl/data_reg_112_s0/Q | u_la0_top/u_ao_mem_ctrl/mem_mem_0_12_s/DI[4] | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.462 |
5 | 0.213 | u_la0_top/u_ao_mem_ctrl/data_reg_36_s0/Q | u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/DI[0] | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.462 |
6 | 0.213 | u_la0_top/u_ao_mem_ctrl/data_reg_9_s0/Q | u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[0] | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.462 |
7 | 0.225 | u_la0_top/u_ao_mem_ctrl/data_reg_97_s0/Q | u_la0_top/u_ao_mem_ctrl/mem_mem_0_10_s/DI[7] | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.474 |
8 | 0.307 | u_la0_top/u_ao_mem_ctrl/data_reg_dly_69_s0/Q | u_la0_top/u_ao_mem_ctrl/data_reg_69_s0/D | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.318 |
9 | 0.307 | u_la0_top/u_ao_mem_ctrl/data_reg_dly_86_s0/Q | u_la0_top/u_ao_mem_ctrl/data_reg_86_s0/D | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.318 |
10 | 0.307 | u_la0_top/u_ao_mem_ctrl/data_reg_dly_97_s0/Q | u_la0_top/u_ao_mem_ctrl/data_reg_97_s0/D | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.318 |
11 | 0.307 | u_la0_top/rst_ao_syn_s0/Q | u_la0_top/rst_ao_s0/D | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.318 |
12 | 0.318 | u_p2b/u_p2b_0/u_mid_buf/rRstRsync_s0/Q | u_p2b/u_p2b_0/u_mid_buf/rRdRst_s0/CE | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.329 |
13 | 0.320 | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/rWrOffset_1_s1/Q | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mSsram_mSsram_1_0_s/WAD[1] | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.332 |
14 | 0.324 | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/rWrOffset_2_s1/Q | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mSsram_mSsram_1_0_s/WAD[2] | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.336 |
15 | 0.324 | u_la0_top/u_ao_mem_ctrl/data_reg_71_s0/Q | u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s/DI[8] | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.573 |
16 | 0.325 | u_dsi_tx/u_tx/u_dsi_tx/rCtrl_14_s0/Q | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mSsram_mSsram_0_1_s/DI[2] | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.337 |
17 | 0.326 | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/rWrOffset_1_s1/Q | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mSsram_mSsram_1_1_s/WAD[1] | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.338 |
18 | 0.326 | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/rWrOffset_3_s1/Q | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mSsram_mSsram_1_0_s/WAD[3] | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.338 |
19 | 0.330 | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/rWrOffset_0_s1/Q | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mSsram_mSsram_1_1_s/WAD[0] | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.342 |
20 | 0.335 | u_la0_top/u_ao_mem_ctrl/data_reg_116_s0/Q | u_la0_top/u_ao_mem_ctrl/mem_mem_0_12_s/DI[8] | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.584 |
Recovery Paths Table
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 7.875 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_match_3/match_cnt_3_s1/CLEAR | byte_clk:[R] | byte_clk:[R] | 9.412 | 0.000 | 1.502 |
2 | 7.875 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_match_0/matched_s7/CLEAR | byte_clk:[R] | byte_clk:[R] | 9.412 | 0.000 | 1.502 |
3 | 7.875 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_match_0/match_cnt_3_s1/CLEAR | byte_clk:[R] | byte_clk:[R] | 9.412 | 0.000 | 1.502 |
4 | 7.898 | u_la0_top/rst_ao_s0/Q | u_la0_top/capture_end_dly_s0/PRESET | byte_clk:[R] | byte_clk:[R] | 9.412 | 0.000 | 1.479 |
5 | 7.914 | u_la0_top/rst_ao_s0/Q | u_la0_top/start_reg_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 9.412 | 0.000 | 1.463 |
6 | 8.020 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR | byte_clk:[R] | byte_clk:[R] | 9.412 | 0.000 | 1.357 |
7 | 8.115 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_match_0/match_cnt_5_s1/CLEAR | byte_clk:[R] | byte_clk:[R] | 9.412 | 0.000 | 1.262 |
8 | 8.141 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_match_4/match_bitwise_pre_reg_0_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 9.412 | 0.000 | 1.236 |
9 | 8.141 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_match_0/match_cnt_0_s1/CLEAR | byte_clk:[R] | byte_clk:[R] | 9.412 | 0.000 | 1.236 |
10 | 8.141 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_match_0/match_cnt_2_s1/CLEAR | byte_clk:[R] | byte_clk:[R] | 9.412 | 0.000 | 1.236 |
11 | 8.141 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_match_0/trig_dly_0_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 9.412 | 0.000 | 1.236 |
12 | 8.141 | u_la0_top/rst_ao_s0/Q | u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 9.412 | 0.000 | 1.236 |
13 | 8.142 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR | byte_clk:[R] | byte_clk:[R] | 9.412 | 0.000 | 1.235 |
14 | 8.147 | u_la0_top/rst_ao_s0/Q | u_la0_top/internal_reg_start_dly_0_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 9.412 | 0.000 | 1.230 |
15 | 8.147 | u_la0_top/rst_ao_s0/Q | u_la0_top/internal_reg_start_syn_1_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 9.412 | 0.000 | 1.230 |
16 | 8.148 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_match_4/match_sep_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 9.412 | 0.000 | 1.229 |
17 | 8.148 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_match_3/matched_s1/CLEAR | byte_clk:[R] | byte_clk:[R] | 9.412 | 0.000 | 1.229 |
18 | 8.148 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_match_2/match_sep_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 9.412 | 0.000 | 1.229 |
19 | 8.148 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_match_1/match_sep_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 9.412 | 0.000 | 1.229 |
20 | 8.148 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_match_0/match_sep_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 9.412 | 0.000 | 1.229 |
21 | 8.154 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_match_4/trig_dly_in_0_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 9.412 | 0.000 | 1.223 |
22 | 8.154 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_match_3/trig_dly_in_0_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 9.412 | 0.000 | 1.223 |
23 | 8.154 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_match_3/trig_dly_in_1_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 9.412 | 0.000 | 1.223 |
24 | 8.155 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/CLEAR | byte_clk:[R] | byte_clk:[R] | 9.412 | 0.000 | 1.221 |
25 | 8.155 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR | byte_clk:[R] | byte_clk:[R] | 9.412 | 0.000 | 1.221 |
Removal Paths Table
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 0.328 | u_la0_top/rst_ao_s0/Q | u_la0_top/capture_window_sel_10_s1/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.339 |
2 | 0.450 | u_la0_top/rst_ao_s0/Q | u_la0_top/capture_window_sel_0_s3/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.461 |
3 | 0.450 | u_la0_top/rst_ao_s0/Q | u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.461 |
4 | 0.572 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.583 |
5 | 0.595 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.606 |
6 | 0.595 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.606 |
7 | 0.604 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.615 |
8 | 0.604 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_mem_ctrl/capture_length_10_s1/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.615 |
9 | 0.610 | u_la0_top/rst_ao_s0/Q | u_la0_top/internal_reg_start_syn_0_s0/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.621 |
10 | 0.612 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_match_3/match_cnt_11_s1/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.623 |
11 | 0.612 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.623 |
12 | 0.613 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.624 |
13 | 0.613 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.624 |
14 | 0.613 | u_la0_top/rst_ao_s0/Q | u_la0_top/capture_window_sel_5_s1/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.624 |
15 | 0.613 | u_la0_top/rst_ao_s0/Q | u_la0_top/capture_window_sel_6_s1/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.624 |
16 | 0.613 | u_la0_top/rst_ao_s0/Q | u_la0_top/capture_window_sel_7_s1/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.624 |
17 | 0.613 | u_la0_top/rst_ao_s0/Q | u_la0_top/capture_window_sel_8_s1/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.624 |
18 | 0.613 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_match_3/match_cnt_5_s1/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.624 |
19 | 0.613 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_match_3/match_cnt_6_s1/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.624 |
20 | 0.613 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_match_3/match_cnt_7_s1/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.624 |
21 | 0.613 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.624 |
22 | 0.618 | u_la0_top/rst_ao_s0/Q | u_la0_top/capture_window_sel_1_s1/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.629 |
23 | 0.618 | u_la0_top/rst_ao_s0/Q | u_la0_top/triger_level_cnt_1_s1/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.629 |
24 | 0.618 | u_la0_top/rst_ao_s0/Q | u_la0_top/triger_level_cnt_2_s1/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.629 |
25 | 0.619 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_match_3/match_cnt_1_s1/CLEAR | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.630 |
Minimum Pulse Width Table:
Number | Slack | Actual Width | Required Width | Type | Clock | Objects |
---|---|---|---|---|---|---|
1 | 1.766 | 2.766 | 1.000 | Low Pulse Width | pixel_clk | run_cnt_25_s0 |
2 | 1.766 | 2.766 | 1.000 | Low Pulse Width | pixel_clk | u_test_gen/De_vcnt_9_s1 |
3 | 1.766 | 2.766 | 1.000 | Low Pulse Width | pixel_clk | u_p2b/u_p2b_0/u_mid_buf/rRPtrWsync_2_s0 |
4 | 1.766 | 2.766 | 1.000 | Low Pulse Width | pixel_clk | u_p2b/u_p2b_0/u_mid_buf/rRPtrWsync_1_s0 |
5 | 1.766 | 2.766 | 1.000 | Low Pulse Width | pixel_clk | u_p2b/u_p2b_0/u_mid_buf/rRPtrWsync_0_s0 |
6 | 1.766 | 2.766 | 1.000 | Low Pulse Width | pixel_clk | u_p2b/u_p2b_0/u_mid_buf/rFull_s0 |
7 | 1.766 | 2.766 | 1.000 | Low Pulse Width | pixel_clk | u_p2b/u_p2b_0/u_mid_buf/rWPtrGray_0_s1 |
8 | 1.766 | 2.766 | 1.000 | Low Pulse Width | pixel_clk | u_test_gen/De_vcnt_8_s1 |
9 | 1.766 | 2.766 | 1.000 | Low Pulse Width | pixel_clk | u_p2b/u_p2b_0/shift_data_94_s0 |
10 | 1.766 | 2.766 | 1.000 | Low Pulse Width | pixel_clk | u_p2b/u_p2b_0/mid_data_17_s1 |
Timing Report By Analysis Type:
Setup Analysis Report
Setup Analysis Report[1]:
Report Command:report_timing -setup -from_clock [get_clocks {pixel_clk}] -max_paths 20 -max_common_paths 1
Path1
Path Summary:
Slack | 2.178 |
Data Arrival Time | 7.117 |
Data Required Time | 9.295 |
From | u_p2b/u_p2b_0/u_mid_buf/rRPtrWsync_3_s0 |
To | u_p2b/u_p2b_0/u_mid_buf/rFull_s0 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 279 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD3 |
2.271 | 2.271 | tNET | RR | 1 | R21C45[2][A] | u_p2b/u_p2b_0/u_mid_buf/rRPtrWsync_3_s0/CLK |
2.503 | 0.232 | tC2Q | RF | 3 | R21C45[2][A] | u_p2b/u_p2b_0/u_mid_buf/rRPtrWsync_3_s0/Q |
3.027 | 0.523 | tNET | FF | 1 | R15C45[3][B] | u_p2b/u_p2b_0/u_mid_buf/wRPtrBinX_1_s0/I2 |
3.398 | 0.371 | tINS | FF | 3 | R15C45[3][B] | u_p2b/u_p2b_0/u_mid_buf/wRPtrBinX_1_s0/F |
3.577 | 0.179 | tNET | FF | 1 | R15C46[0][A] | u_p2b/u_p2b_0/u_mid_buf/wRPtrBinX_0_s0/I1 |
3.948 | 0.371 | tINS | FF | 1 | R15C46[0][A] | u_p2b/u_p2b_0/u_mid_buf/wRPtrBinX_0_s0/F |
4.604 | 0.656 | tNET | FF | 2 | R18C45[0][B] | u_p2b/u_p2b_0/u_mid_buf/n327_s0/I1 |
5.174 | 0.570 | tINS | FR | 1 | R18C45[0][B] | u_p2b/u_p2b_0/u_mid_buf/n327_s0/COUT |
5.174 | 0.000 | tNET | RR | 2 | R18C45[1][A] | u_p2b/u_p2b_0/u_mid_buf/n328_s0/CIN |
5.209 | 0.035 | tINS | RF | 1 | R18C45[1][A] | u_p2b/u_p2b_0/u_mid_buf/n328_s0/COUT |
5.209 | 0.000 | tNET | FF | 2 | R18C45[1][B] | u_p2b/u_p2b_0/u_mid_buf/n329_s0/CIN |
5.244 | 0.035 | tINS | FF | 1 | R18C45[1][B] | u_p2b/u_p2b_0/u_mid_buf/n329_s0/COUT |
5.244 | 0.000 | tNET | FF | 2 | R18C45[2][A] | u_p2b/u_p2b_0/u_mid_buf/n330_s0/CIN |
5.279 | 0.035 | tINS | FF | 1 | R18C45[2][A] | u_p2b/u_p2b_0/u_mid_buf/n330_s0/COUT |
5.997 | 0.717 | tNET | FF | 1 | R17C45[2][B] | u_p2b/u_p2b_0/u_mid_buf/n342_s4/I0 |
6.567 | 0.570 | tINS | FR | 1 | R17C45[2][B] | u_p2b/u_p2b_0/u_mid_buf/n342_s4/F |
6.568 | 0.001 | tNET | RR | 1 | R17C45[0][A] | u_p2b/u_p2b_0/u_mid_buf/n342_s0/I3 |
7.117 | 0.549 | tINS | RR | 1 | R17C45[0][A] | u_p2b/u_p2b_0/u_mid_buf/n342_s0/F |
7.117 | 0.000 | tNET | RR | 1 | R17C45[0][A] | u_p2b/u_p2b_0/u_mid_buf/rFull_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.059 | 7.059 | active clock edge time | ||||
7.059 | 0.000 | pixel_clk | ||||
7.059 | 0.000 | tCL | RR | 279 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD3 |
9.330 | 2.271 | tNET | RR | 1 | R17C45[0][A] | u_p2b/u_p2b_0/u_mid_buf/rFull_s0/CLK |
9.295 | -0.035 | tSu | 1 | R17C45[0][A] | u_p2b/u_p2b_0/u_mid_buf/rFull_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 7.059 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 2.537, 52.348%; route: 2.077, 42.864%; tC2Q: 0.232, 4.788% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path2
Path Summary:
Slack | 2.660 |
Data Arrival Time | 6.635 |
Data Required Time | 9.295 |
From | u_test_gen/De_hcnt_0_s3 |
To | u_test_gen/Net_h_trig_s0 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 279 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD3 |
2.271 | 2.271 | tNET | RR | 1 | R20C37[0][B] | u_test_gen/De_hcnt_0_s3/CLK |
2.503 | 0.232 | tC2Q | RF | 7 | R20C37[0][B] | u_test_gen/De_hcnt_0_s3/Q |
3.177 | 0.674 | tNET | FF | 1 | R20C38[0][A] | u_test_gen/n501_s3/I0 |
3.548 | 0.371 | tINS | FF | 5 | R20C38[0][A] | u_test_gen/n501_s3/F |
3.985 | 0.437 | tNET | FF | 1 | R17C38[3][A] | u_test_gen/n498_s3/I3 |
4.356 | 0.371 | tINS | FF | 4 | R17C38[3][A] | u_test_gen/n498_s3/F |
5.025 | 0.669 | tNET | FF | 1 | R15C37[1][A] | u_test_gen/n849_s2/I2 |
5.580 | 0.555 | tINS | FF | 1 | R15C37[1][A] | u_test_gen/n849_s2/F |
6.264 | 0.684 | tNET | FF | 1 | R20C38[1][B] | u_test_gen/n849_s0/I2 |
6.635 | 0.371 | tINS | FF | 1 | R20C38[1][B] | u_test_gen/n849_s0/F |
6.635 | 0.000 | tNET | FF | 1 | R20C38[1][B] | u_test_gen/Net_h_trig_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.059 | 7.059 | active clock edge time | ||||
7.059 | 0.000 | pixel_clk | ||||
7.059 | 0.000 | tCL | RR | 279 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD3 |
9.330 | 2.271 | tNET | RR | 1 | R20C38[1][B] | u_test_gen/Net_h_trig_s0/CLK |
9.295 | -0.035 | tSu | 1 | R20C38[1][B] | u_test_gen/Net_h_trig_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 7.059 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 1.668, 38.227%; route: 2.463, 56.456%; tC2Q: 0.232, 5.317% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path3
Path Summary:
Slack | 2.843 |
Data Arrival Time | 6.452 |
Data Required Time | 9.295 |
From | u_test_gen/H_cnt_5_s0 |
To | u_test_gen/V_cnt_2_s1 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 279 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD3 |
2.271 | 2.271 | tNET | RR | 1 | R24C39[2][A] | u_test_gen/H_cnt_5_s0/CLK |
2.503 | 0.232 | tC2Q | RF | 4 | R24C39[2][A] | u_test_gen/H_cnt_5_s0/Q |
2.688 | 0.185 | tNET | FF | 1 | R24C38[3][B] | u_test_gen/V_cnt_10_s5/I1 |
3.243 | 0.555 | tINS | FF | 5 | R24C38[3][B] | u_test_gen/V_cnt_10_s5/F |
3.653 | 0.410 | tNET | FF | 1 | R23C38[3][B] | u_test_gen/V_cnt_10_s3/I1 |
4.024 | 0.371 | tINS | FF | 24 | R23C38[3][B] | u_test_gen/V_cnt_10_s3/F |
5.054 | 1.029 | tNET | FF | 1 | R12C38[3][A] | u_test_gen/n63_s4/I3 |
5.425 | 0.371 | tINS | FF | 12 | R12C38[3][A] | u_test_gen/n63_s4/F |
5.882 | 0.457 | tNET | FF | 1 | R13C39[2][B] | u_test_gen/n72_s4/I0 |
6.452 | 0.570 | tINS | FR | 1 | R13C39[2][B] | u_test_gen/n72_s4/F |
6.452 | 0.000 | tNET | RR | 1 | R13C39[2][B] | u_test_gen/V_cnt_2_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.059 | 7.059 | active clock edge time | ||||
7.059 | 0.000 | pixel_clk | ||||
7.059 | 0.000 | tCL | RR | 279 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD3 |
9.330 | 2.271 | tNET | RR | 1 | R13C39[2][B] | u_test_gen/V_cnt_2_s1/CLK |
9.295 | -0.035 | tSu | 1 | R13C39[2][B] | u_test_gen/V_cnt_2_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 7.059 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 1.867, 44.661%; route: 2.081, 49.790%; tC2Q: 0.232, 5.550% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path4
Path Summary:
Slack | 2.864 |
Data Arrival Time | 6.431 |
Data Required Time | 9.295 |
From | u_test_gen/H_cnt_5_s0 |
To | u_test_gen/V_cnt_6_s1 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 279 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD3 |
2.271 | 2.271 | tNET | RR | 1 | R24C39[2][A] | u_test_gen/H_cnt_5_s0/CLK |
2.503 | 0.232 | tC2Q | RF | 4 | R24C39[2][A] | u_test_gen/H_cnt_5_s0/Q |
2.688 | 0.185 | tNET | FF | 1 | R24C38[3][B] | u_test_gen/V_cnt_10_s5/I1 |
3.243 | 0.555 | tINS | FF | 5 | R24C38[3][B] | u_test_gen/V_cnt_10_s5/F |
3.653 | 0.410 | tNET | FF | 1 | R23C38[3][B] | u_test_gen/V_cnt_10_s3/I1 |
4.024 | 0.371 | tINS | FF | 24 | R23C38[3][B] | u_test_gen/V_cnt_10_s3/F |
5.054 | 1.029 | tNET | FF | 1 | R12C38[3][A] | u_test_gen/n63_s4/I3 |
5.425 | 0.371 | tINS | FF | 12 | R12C38[3][A] | u_test_gen/n63_s4/F |
5.882 | 0.457 | tNET | FF | 1 | R13C39[0][B] | u_test_gen/n68_s2/I2 |
6.431 | 0.549 | tINS | FR | 1 | R13C39[0][B] | u_test_gen/n68_s2/F |
6.431 | 0.000 | tNET | RR | 1 | R13C39[0][B] | u_test_gen/V_cnt_6_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.059 | 7.059 | active clock edge time | ||||
7.059 | 0.000 | pixel_clk | ||||
7.059 | 0.000 | tCL | RR | 279 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD3 |
9.330 | 2.271 | tNET | RR | 1 | R13C39[0][B] | u_test_gen/V_cnt_6_s1/CLK |
9.295 | -0.035 | tSu | 1 | R13C39[0][B] | u_test_gen/V_cnt_6_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 7.059 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 1.846, 44.381%; route: 2.081, 50.041%; tC2Q: 0.232, 5.578% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path5
Path Summary:
Slack | 2.864 |
Data Arrival Time | 6.431 |
Data Required Time | 9.295 |
From | u_test_gen/H_cnt_5_s0 |
To | u_test_gen/V_cnt_7_s1 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 279 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD3 |
2.271 | 2.271 | tNET | RR | 1 | R24C39[2][A] | u_test_gen/H_cnt_5_s0/CLK |
2.503 | 0.232 | tC2Q | RF | 4 | R24C39[2][A] | u_test_gen/H_cnt_5_s0/Q |
2.688 | 0.185 | tNET | FF | 1 | R24C38[3][B] | u_test_gen/V_cnt_10_s5/I1 |
3.243 | 0.555 | tINS | FF | 5 | R24C38[3][B] | u_test_gen/V_cnt_10_s5/F |
3.653 | 0.410 | tNET | FF | 1 | R23C38[3][B] | u_test_gen/V_cnt_10_s3/I1 |
4.024 | 0.371 | tINS | FF | 24 | R23C38[3][B] | u_test_gen/V_cnt_10_s3/F |
5.054 | 1.029 | tNET | FF | 1 | R12C38[3][A] | u_test_gen/n63_s4/I3 |
5.425 | 0.371 | tINS | FF | 12 | R12C38[3][A] | u_test_gen/n63_s4/F |
5.882 | 0.457 | tNET | FF | 1 | R13C39[0][A] | u_test_gen/n67_s2/I0 |
6.431 | 0.549 | tINS | FR | 1 | R13C39[0][A] | u_test_gen/n67_s2/F |
6.431 | 0.000 | tNET | RR | 1 | R13C39[0][A] | u_test_gen/V_cnt_7_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.059 | 7.059 | active clock edge time | ||||
7.059 | 0.000 | pixel_clk | ||||
7.059 | 0.000 | tCL | RR | 279 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD3 |
9.330 | 2.271 | tNET | RR | 1 | R13C39[0][A] | u_test_gen/V_cnt_7_s1/CLK |
9.295 | -0.035 | tSu | 1 | R13C39[0][A] | u_test_gen/V_cnt_7_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 7.059 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 1.846, 44.381%; route: 2.081, 50.041%; tC2Q: 0.232, 5.578% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path6
Path Summary:
Slack | 2.864 |
Data Arrival Time | 6.431 |
Data Required Time | 9.295 |
From | u_test_gen/H_cnt_5_s0 |
To | u_test_gen/V_cnt_8_s1 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 279 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD3 |
2.271 | 2.271 | tNET | RR | 1 | R24C39[2][A] | u_test_gen/H_cnt_5_s0/CLK |
2.503 | 0.232 | tC2Q | RF | 4 | R24C39[2][A] | u_test_gen/H_cnt_5_s0/Q |
2.688 | 0.185 | tNET | FF | 1 | R24C38[3][B] | u_test_gen/V_cnt_10_s5/I1 |
3.243 | 0.555 | tINS | FF | 5 | R24C38[3][B] | u_test_gen/V_cnt_10_s5/F |
3.653 | 0.410 | tNET | FF | 1 | R23C38[3][B] | u_test_gen/V_cnt_10_s3/I1 |
4.024 | 0.371 | tINS | FF | 24 | R23C38[3][B] | u_test_gen/V_cnt_10_s3/F |
5.054 | 1.029 | tNET | FF | 1 | R12C38[3][A] | u_test_gen/n63_s4/I3 |
5.425 | 0.371 | tINS | FF | 12 | R12C38[3][A] | u_test_gen/n63_s4/F |
5.882 | 0.457 | tNET | FF | 1 | R13C39[1][B] | u_test_gen/n66_s2/I2 |
6.431 | 0.549 | tINS | FR | 1 | R13C39[1][B] | u_test_gen/n66_s2/F |
6.431 | 0.000 | tNET | RR | 1 | R13C39[1][B] | u_test_gen/V_cnt_8_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.059 | 7.059 | active clock edge time | ||||
7.059 | 0.000 | pixel_clk | ||||
7.059 | 0.000 | tCL | RR | 279 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD3 |
9.330 | 2.271 | tNET | RR | 1 | R13C39[1][B] | u_test_gen/V_cnt_8_s1/CLK |
9.295 | -0.035 | tSu | 1 | R13C39[1][B] | u_test_gen/V_cnt_8_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 7.059 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 1.846, 44.381%; route: 2.081, 50.041%; tC2Q: 0.232, 5.578% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path7
Path Summary:
Slack | 2.882 |
Data Arrival Time | 6.414 |
Data Required Time | 9.295 |
From | u_test_gen/H_cnt_5_s0 |
To | u_test_gen/V_cnt_1_s1 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 279 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD3 |
2.271 | 2.271 | tNET | RR | 1 | R24C39[2][A] | u_test_gen/H_cnt_5_s0/CLK |
2.503 | 0.232 | tC2Q | RF | 4 | R24C39[2][A] | u_test_gen/H_cnt_5_s0/Q |
2.688 | 0.185 | tNET | FF | 1 | R24C38[3][B] | u_test_gen/V_cnt_10_s5/I1 |
3.243 | 0.555 | tINS | FF | 5 | R24C38[3][B] | u_test_gen/V_cnt_10_s5/F |
3.653 | 0.410 | tNET | FF | 1 | R23C38[3][B] | u_test_gen/V_cnt_10_s3/I1 |
4.024 | 0.371 | tINS | FF | 24 | R23C38[3][B] | u_test_gen/V_cnt_10_s3/F |
5.054 | 1.029 | tNET | FF | 1 | R12C38[3][A] | u_test_gen/n63_s4/I3 |
5.425 | 0.371 | tINS | FF | 12 | R12C38[3][A] | u_test_gen/n63_s4/F |
5.865 | 0.440 | tNET | FF | 1 | R13C39[2][A] | u_test_gen/n73_s2/I0 |
6.414 | 0.549 | tINS | FR | 1 | R13C39[2][A] | u_test_gen/n73_s2/F |
6.414 | 0.000 | tNET | RR | 1 | R13C39[2][A] | u_test_gen/V_cnt_1_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.059 | 7.059 | active clock edge time | ||||
7.059 | 0.000 | pixel_clk | ||||
7.059 | 0.000 | tCL | RR | 279 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD3 |
9.330 | 2.271 | tNET | RR | 1 | R13C39[2][A] | u_test_gen/V_cnt_1_s1/CLK |
9.295 | -0.035 | tSu | 1 | R13C39[2][A] | u_test_gen/V_cnt_1_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 7.059 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 1.846, 44.565%; route: 2.064, 49.834%; tC2Q: 0.232, 5.601% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path8
Path Summary:
Slack | 3.085 |
Data Arrival Time | 6.210 |
Data Required Time | 9.295 |
From | u_test_gen/H_cnt_5_s0 |
To | u_test_gen/V_cnt_11_s1 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 279 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD3 |
2.271 | 2.271 | tNET | RR | 1 | R24C39[2][A] | u_test_gen/H_cnt_5_s0/CLK |
2.503 | 0.232 | tC2Q | RF | 4 | R24C39[2][A] | u_test_gen/H_cnt_5_s0/Q |
2.688 | 0.185 | tNET | FF | 1 | R24C38[3][B] | u_test_gen/V_cnt_10_s5/I1 |
3.243 | 0.555 | tINS | FF | 5 | R24C38[3][B] | u_test_gen/V_cnt_10_s5/F |
3.653 | 0.410 | tNET | FF | 1 | R23C38[3][B] | u_test_gen/V_cnt_10_s3/I1 |
4.024 | 0.371 | tINS | FF | 24 | R23C38[3][B] | u_test_gen/V_cnt_10_s3/F |
5.054 | 1.029 | tNET | FF | 1 | R12C38[3][A] | u_test_gen/n63_s4/I3 |
5.425 | 0.371 | tINS | FF | 12 | R12C38[3][A] | u_test_gen/n63_s4/F |
5.640 | 0.215 | tNET | FF | 1 | R13C38[2][A] | u_test_gen/n63_s2/I2 |
6.210 | 0.570 | tINS | FR | 1 | R13C38[2][A] | u_test_gen/n63_s2/F |
6.210 | 0.000 | tNET | RR | 1 | R13C38[2][A] | u_test_gen/V_cnt_11_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.059 | 7.059 | active clock edge time | ||||
7.059 | 0.000 | pixel_clk | ||||
7.059 | 0.000 | tCL | RR | 279 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD3 |
9.330 | 2.271 | tNET | RR | 1 | R13C38[2][A] | u_test_gen/V_cnt_11_s1/CLK |
9.295 | -0.035 | tSu | 1 | R13C38[2][A] | u_test_gen/V_cnt_11_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 7.059 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 1.867, 47.403%; route: 1.840, 46.707%; tC2Q: 0.232, 5.890% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path9
Path Summary:
Slack | 3.085 |
Data Arrival Time | 6.210 |
Data Required Time | 9.295 |
From | u_test_gen/H_cnt_5_s0 |
To | u_test_gen/V_cnt_0_s1 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 279 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD3 |
2.271 | 2.271 | tNET | RR | 1 | R24C39[2][A] | u_test_gen/H_cnt_5_s0/CLK |
2.503 | 0.232 | tC2Q | RF | 4 | R24C39[2][A] | u_test_gen/H_cnt_5_s0/Q |
2.688 | 0.185 | tNET | FF | 1 | R24C38[3][B] | u_test_gen/V_cnt_10_s5/I1 |
3.243 | 0.555 | tINS | FF | 5 | R24C38[3][B] | u_test_gen/V_cnt_10_s5/F |
3.653 | 0.410 | tNET | FF | 1 | R23C38[3][B] | u_test_gen/V_cnt_10_s3/I1 |
4.024 | 0.371 | tINS | FF | 24 | R23C38[3][B] | u_test_gen/V_cnt_10_s3/F |
5.054 | 1.029 | tNET | FF | 1 | R12C38[3][A] | u_test_gen/n63_s4/I3 |
5.425 | 0.371 | tINS | FF | 12 | R12C38[3][A] | u_test_gen/n63_s4/F |
5.640 | 0.215 | tNET | FF | 1 | R13C38[2][B] | u_test_gen/n74_s2/I1 |
6.210 | 0.570 | tINS | FR | 1 | R13C38[2][B] | u_test_gen/n74_s2/F |
6.210 | 0.000 | tNET | RR | 1 | R13C38[2][B] | u_test_gen/V_cnt_0_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.059 | 7.059 | active clock edge time | ||||
7.059 | 0.000 | pixel_clk | ||||
7.059 | 0.000 | tCL | RR | 279 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD3 |
9.330 | 2.271 | tNET | RR | 1 | R13C38[2][B] | u_test_gen/V_cnt_0_s1/CLK |
9.295 | -0.035 | tSu | 1 | R13C38[2][B] | u_test_gen/V_cnt_0_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 7.059 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 1.867, 47.403%; route: 1.840, 46.707%; tC2Q: 0.232, 5.890% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path10
Path Summary:
Slack | 3.133 |
Data Arrival Time | 6.162 |
Data Required Time | 9.295 |
From | u_test_gen/H_cnt_5_s0 |
To | u_test_gen/V_cnt_3_s1 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 279 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD3 |
2.271 | 2.271 | tNET | RR | 1 | R24C39[2][A] | u_test_gen/H_cnt_5_s0/CLK |
2.503 | 0.232 | tC2Q | RF | 4 | R24C39[2][A] | u_test_gen/H_cnt_5_s0/Q |
2.688 | 0.185 | tNET | FF | 1 | R24C38[3][B] | u_test_gen/V_cnt_10_s5/I1 |
3.243 | 0.555 | tINS | FF | 5 | R24C38[3][B] | u_test_gen/V_cnt_10_s5/F |
3.653 | 0.410 | tNET | FF | 1 | R23C38[3][B] | u_test_gen/V_cnt_10_s3/I1 |
4.024 | 0.371 | tINS | FF | 24 | R23C38[3][B] | u_test_gen/V_cnt_10_s3/F |
5.054 | 1.029 | tNET | FF | 1 | R12C38[3][A] | u_test_gen/n63_s4/I3 |
5.425 | 0.371 | tINS | FF | 12 | R12C38[3][A] | u_test_gen/n63_s4/F |
5.613 | 0.188 | tNET | FF | 1 | R12C39[1][B] | u_test_gen/n71_s2/I2 |
6.162 | 0.549 | tINS | FR | 1 | R12C39[1][B] | u_test_gen/n71_s2/F |
6.162 | 0.000 | tNET | RR | 1 | R12C39[1][B] | u_test_gen/V_cnt_3_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.059 | 7.059 | active clock edge time | ||||
7.059 | 0.000 | pixel_clk | ||||
7.059 | 0.000 | tCL | RR | 279 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD3 |
9.330 | 2.271 | tNET | RR | 1 | R12C39[1][B] | u_test_gen/V_cnt_3_s1/CLK |
9.295 | -0.035 | tSu | 1 | R12C39[1][B] | u_test_gen/V_cnt_3_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 7.059 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 1.846, 47.450%; route: 1.812, 46.587%; tC2Q: 0.232, 5.963% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path11
Path Summary:
Slack | 3.133 |
Data Arrival Time | 6.162 |
Data Required Time | 9.295 |
From | u_test_gen/H_cnt_5_s0 |
To | u_test_gen/V_cnt_5_s1 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 279 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD3 |
2.271 | 2.271 | tNET | RR | 1 | R24C39[2][A] | u_test_gen/H_cnt_5_s0/CLK |
2.503 | 0.232 | tC2Q | RF | 4 | R24C39[2][A] | u_test_gen/H_cnt_5_s0/Q |
2.688 | 0.185 | tNET | FF | 1 | R24C38[3][B] | u_test_gen/V_cnt_10_s5/I1 |
3.243 | 0.555 | tINS | FF | 5 | R24C38[3][B] | u_test_gen/V_cnt_10_s5/F |
3.653 | 0.410 | tNET | FF | 1 | R23C38[3][B] | u_test_gen/V_cnt_10_s3/I1 |
4.024 | 0.371 | tINS | FF | 24 | R23C38[3][B] | u_test_gen/V_cnt_10_s3/F |
5.054 | 1.029 | tNET | FF | 1 | R12C38[3][A] | u_test_gen/n63_s4/I3 |
5.425 | 0.371 | tINS | FF | 12 | R12C38[3][A] | u_test_gen/n63_s4/F |
5.613 | 0.188 | tNET | FF | 1 | R13C38[1][A] | u_test_gen/n69_s4/I0 |
6.162 | 0.549 | tINS | FR | 1 | R13C38[1][A] | u_test_gen/n69_s4/F |
6.162 | 0.000 | tNET | RR | 1 | R13C38[1][A] | u_test_gen/V_cnt_5_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.059 | 7.059 | active clock edge time | ||||
7.059 | 0.000 | pixel_clk | ||||
7.059 | 0.000 | tCL | RR | 279 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD3 |
9.330 | 2.271 | tNET | RR | 1 | R13C38[1][A] | u_test_gen/V_cnt_5_s1/CLK |
9.295 | -0.035 | tSu | 1 | R13C38[1][A] | u_test_gen/V_cnt_5_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 7.059 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 1.846, 47.450%; route: 1.812, 46.587%; tC2Q: 0.232, 5.963% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path12
Path Summary:
Slack | 3.188 |
Data Arrival Time | 6.108 |
Data Required Time | 9.295 |
From | u_test_gen/De_hcnt_0_s3 |
To | u_test_gen/De_hcnt_9_s1 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 279 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD3 |
2.271 | 2.271 | tNET | RR | 1 | R20C37[0][B] | u_test_gen/De_hcnt_0_s3/CLK |
2.503 | 0.232 | tC2Q | RF | 7 | R20C37[0][B] | u_test_gen/De_hcnt_0_s3/Q |
3.177 | 0.674 | tNET | FF | 1 | R20C38[0][A] | u_test_gen/n501_s3/I0 |
3.548 | 0.371 | tINS | FF | 5 | R20C38[0][A] | u_test_gen/n501_s3/F |
3.985 | 0.437 | tNET | FF | 1 | R17C38[3][A] | u_test_gen/n498_s3/I3 |
4.356 | 0.371 | tINS | FF | 4 | R17C38[3][A] | u_test_gen/n498_s3/F |
4.782 | 0.426 | tNET | FF | 1 | R16C37[2][B] | u_test_gen/n497_s3/I1 |
5.235 | 0.453 | tINS | FF | 3 | R16C37[2][B] | u_test_gen/n497_s3/F |
5.646 | 0.411 | tNET | FF | 1 | R14C37[1][A] | u_test_gen/n496_s2/I1 |
6.108 | 0.462 | tINS | FR | 1 | R14C37[1][A] | u_test_gen/n496_s2/F |
6.108 | 0.000 | tNET | RR | 1 | R14C37[1][A] | u_test_gen/De_hcnt_9_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.059 | 7.059 | active clock edge time | ||||
7.059 | 0.000 | pixel_clk | ||||
7.059 | 0.000 | tCL | RR | 279 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD3 |
9.330 | 2.271 | tNET | RR | 1 | R14C37[1][A] | u_test_gen/De_hcnt_9_s1/CLK |
9.295 | -0.035 | tSu | 1 | R14C37[1][A] | u_test_gen/De_hcnt_9_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 7.059 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 1.657, 43.194%; route: 1.947, 50.759%; tC2Q: 0.232, 6.048% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path13
Path Summary:
Slack | 3.279 |
Data Arrival Time | 6.017 |
Data Required Time | 9.295 |
From | u_test_gen/De_hcnt_0_s3 |
To | u_test_gen/De_hcnt_11_s1 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 279 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD3 |
2.271 | 2.271 | tNET | RR | 1 | R20C37[0][B] | u_test_gen/De_hcnt_0_s3/CLK |
2.503 | 0.232 | tC2Q | RF | 7 | R20C37[0][B] | u_test_gen/De_hcnt_0_s3/Q |
3.177 | 0.674 | tNET | FF | 1 | R20C38[0][A] | u_test_gen/n501_s3/I0 |
3.548 | 0.371 | tINS | FF | 5 | R20C38[0][A] | u_test_gen/n501_s3/F |
3.985 | 0.437 | tNET | FF | 1 | R17C38[3][A] | u_test_gen/n498_s3/I3 |
4.356 | 0.371 | tINS | FF | 4 | R17C38[3][A] | u_test_gen/n498_s3/F |
4.782 | 0.426 | tNET | FF | 1 | R16C37[2][B] | u_test_gen/n497_s3/I1 |
5.235 | 0.453 | tINS | FF | 3 | R16C37[2][B] | u_test_gen/n497_s3/F |
5.646 | 0.411 | tNET | FF | 1 | R14C37[2][A] | u_test_gen/n494_s2/I1 |
6.017 | 0.371 | tINS | FF | 1 | R14C37[2][A] | u_test_gen/n494_s2/F |
6.017 | 0.000 | tNET | FF | 1 | R14C37[2][A] | u_test_gen/De_hcnt_11_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.059 | 7.059 | active clock edge time | ||||
7.059 | 0.000 | pixel_clk | ||||
7.059 | 0.000 | tCL | RR | 279 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD3 |
9.330 | 2.271 | tNET | RR | 1 | R14C37[2][A] | u_test_gen/De_hcnt_11_s1/CLK |
9.295 | -0.035 | tSu | 1 | R14C37[2][A] | u_test_gen/De_hcnt_11_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 7.059 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 1.566, 41.813%; route: 1.947, 51.992%; tC2Q: 0.232, 6.195% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path14
Path Summary:
Slack | 3.284 |
Data Arrival Time | 6.011 |
Data Required Time | 9.295 |
From | u_test_gen/H_cnt_5_s0 |
To | u_test_gen/V_cnt_4_s1 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 279 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD3 |
2.271 | 2.271 | tNET | RR | 1 | R24C39[2][A] | u_test_gen/H_cnt_5_s0/CLK |
2.503 | 0.232 | tC2Q | RF | 4 | R24C39[2][A] | u_test_gen/H_cnt_5_s0/Q |
2.688 | 0.185 | tNET | FF | 1 | R24C38[3][B] | u_test_gen/V_cnt_10_s5/I1 |
3.243 | 0.555 | tINS | FF | 5 | R24C38[3][B] | u_test_gen/V_cnt_10_s5/F |
3.653 | 0.410 | tNET | FF | 1 | R23C38[3][B] | u_test_gen/V_cnt_10_s3/I1 |
4.024 | 0.371 | tINS | FF | 24 | R23C38[3][B] | u_test_gen/V_cnt_10_s3/F |
5.054 | 1.029 | tNET | FF | 1 | R12C38[3][A] | u_test_gen/n63_s4/I3 |
5.425 | 0.371 | tINS | FF | 12 | R12C38[3][A] | u_test_gen/n63_s4/F |
5.640 | 0.215 | tNET | FF | 1 | R13C38[0][B] | u_test_gen/n70_s2/I0 |
6.011 | 0.371 | tINS | FF | 1 | R13C38[0][B] | u_test_gen/n70_s2/F |
6.011 | 0.000 | tNET | FF | 1 | R13C38[0][B] | u_test_gen/V_cnt_4_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.059 | 7.059 | active clock edge time | ||||
7.059 | 0.000 | pixel_clk | ||||
7.059 | 0.000 | tCL | RR | 279 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD3 |
9.330 | 2.271 | tNET | RR | 1 | R13C38[0][B] | u_test_gen/V_cnt_4_s1/CLK |
9.295 | -0.035 | tSu | 1 | R13C38[0][B] | u_test_gen/V_cnt_4_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 7.059 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 1.668, 44.604%; route: 1.840, 49.192%; tC2Q: 0.232, 6.204% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path15
Path Summary:
Slack | 3.284 |
Data Arrival Time | 6.011 |
Data Required Time | 9.295 |
From | u_test_gen/H_cnt_5_s0 |
To | u_test_gen/V_cnt_10_s1 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 279 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD3 |
2.271 | 2.271 | tNET | RR | 1 | R24C39[2][A] | u_test_gen/H_cnt_5_s0/CLK |
2.503 | 0.232 | tC2Q | RF | 4 | R24C39[2][A] | u_test_gen/H_cnt_5_s0/Q |
2.688 | 0.185 | tNET | FF | 1 | R24C38[3][B] | u_test_gen/V_cnt_10_s5/I1 |
3.243 | 0.555 | tINS | FF | 5 | R24C38[3][B] | u_test_gen/V_cnt_10_s5/F |
3.653 | 0.410 | tNET | FF | 1 | R23C38[3][B] | u_test_gen/V_cnt_10_s3/I1 |
4.024 | 0.371 | tINS | FF | 24 | R23C38[3][B] | u_test_gen/V_cnt_10_s3/F |
5.054 | 1.029 | tNET | FF | 1 | R12C38[3][A] | u_test_gen/n63_s4/I3 |
5.425 | 0.371 | tINS | FF | 12 | R12C38[3][A] | u_test_gen/n63_s4/F |
5.640 | 0.215 | tNET | FF | 1 | R13C38[1][B] | u_test_gen/n64_s2/I0 |
6.011 | 0.371 | tINS | FF | 1 | R13C38[1][B] | u_test_gen/n64_s2/F |
6.011 | 0.000 | tNET | FF | 1 | R13C38[1][B] | u_test_gen/V_cnt_10_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.059 | 7.059 | active clock edge time | ||||
7.059 | 0.000 | pixel_clk | ||||
7.059 | 0.000 | tCL | RR | 279 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD3 |
9.330 | 2.271 | tNET | RR | 1 | R13C38[1][B] | u_test_gen/V_cnt_10_s1/CLK |
9.295 | -0.035 | tSu | 1 | R13C38[1][B] | u_test_gen/V_cnt_10_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 7.059 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 1.668, 44.604%; route: 1.840, 49.192%; tC2Q: 0.232, 6.204% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path16
Path Summary:
Slack | 3.286 |
Data Arrival Time | 6.009 |
Data Required Time | 9.295 |
From | u_test_gen/De_hcnt_0_s3 |
To | u_test_gen/De_hcnt_10_s1 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 279 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD3 |
2.271 | 2.271 | tNET | RR | 1 | R20C37[0][B] | u_test_gen/De_hcnt_0_s3/CLK |
2.503 | 0.232 | tC2Q | RF | 7 | R20C37[0][B] | u_test_gen/De_hcnt_0_s3/Q |
3.177 | 0.674 | tNET | FF | 1 | R20C38[0][A] | u_test_gen/n501_s3/I0 |
3.548 | 0.371 | tINS | FF | 5 | R20C38[0][A] | u_test_gen/n501_s3/F |
3.985 | 0.437 | tNET | FF | 1 | R17C38[3][A] | u_test_gen/n498_s3/I3 |
4.356 | 0.371 | tINS | FF | 4 | R17C38[3][A] | u_test_gen/n498_s3/F |
4.782 | 0.426 | tNET | FF | 1 | R16C37[2][B] | u_test_gen/n497_s3/I1 |
5.235 | 0.453 | tINS | FF | 3 | R16C37[2][B] | u_test_gen/n497_s3/F |
5.638 | 0.403 | tNET | FF | 1 | R14C37[1][B] | u_test_gen/n495_s2/I1 |
6.009 | 0.371 | tINS | FF | 1 | R14C37[1][B] | u_test_gen/n495_s2/F |
6.009 | 0.000 | tNET | FF | 1 | R14C37[1][B] | u_test_gen/De_hcnt_10_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.059 | 7.059 | active clock edge time | ||||
7.059 | 0.000 | pixel_clk | ||||
7.059 | 0.000 | tCL | RR | 279 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD3 |
9.330 | 2.271 | tNET | RR | 1 | R14C37[1][B] | u_test_gen/De_hcnt_10_s1/CLK |
9.295 | -0.035 | tSu | 1 | R14C37[1][B] | u_test_gen/De_hcnt_10_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 7.059 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 1.566, 41.901%; route: 1.939, 51.891%; tC2Q: 0.232, 6.208% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path17
Path Summary:
Slack | 3.383 |
Data Arrival Time | 5.912 |
Data Required Time | 9.295 |
From | vs_cnt_9_s0 |
To | u_test_gen/Data_tmp_7_s1 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 279 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD3 |
2.271 | 2.271 | tNET | RR | 1 | R16C13[1][B] | vs_cnt_9_s0/CLK |
2.503 | 0.232 | tC2Q | RF | 28 | R16C13[1][B] | vs_cnt_9_s0/Q |
4.188 | 1.684 | tNET | FF | 1 | R16C38[1][B] | u_test_gen/Data_sel_7_s1/I2 |
4.705 | 0.517 | tINS | FF | 8 | R16C38[1][B] | u_test_gen/Data_sel_7_s1/F |
5.363 | 0.659 | tNET | FF | 1 | R17C37[1][A] | u_test_gen/Data_sel_7_s2/I3 |
5.912 | 0.549 | tINS | FR | 1 | R17C37[1][A] | u_test_gen/Data_sel_7_s2/F |
5.912 | 0.000 | tNET | RR | 1 | R17C37[1][A] | u_test_gen/Data_tmp_7_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.059 | 7.059 | active clock edge time | ||||
7.059 | 0.000 | pixel_clk | ||||
7.059 | 0.000 | tCL | RR | 279 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD3 |
9.330 | 2.271 | tNET | RR | 1 | R17C37[1][A] | u_test_gen/Data_tmp_7_s1/CLK |
9.295 | -0.035 | tSu | 1 | R17C37[1][A] | u_test_gen/Data_tmp_7_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 7.059 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 1.066, 29.279%; route: 2.343, 64.349%; tC2Q: 0.232, 6.372% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path18
Path Summary:
Slack | 3.386 |
Data Arrival Time | 5.909 |
Data Required Time | 9.295 |
From | u_test_gen/H_cnt_5_s0 |
To | u_test_gen/V_cnt_9_s1 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 279 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD3 |
2.271 | 2.271 | tNET | RR | 1 | R24C39[2][A] | u_test_gen/H_cnt_5_s0/CLK |
2.503 | 0.232 | tC2Q | RF | 4 | R24C39[2][A] | u_test_gen/H_cnt_5_s0/Q |
2.688 | 0.185 | tNET | FF | 1 | R24C38[3][B] | u_test_gen/V_cnt_10_s5/I1 |
3.243 | 0.555 | tINS | FF | 5 | R24C38[3][B] | u_test_gen/V_cnt_10_s5/F |
3.653 | 0.410 | tNET | FF | 1 | R23C38[3][B] | u_test_gen/V_cnt_10_s3/I1 |
4.024 | 0.371 | tINS | FF | 24 | R23C38[3][B] | u_test_gen/V_cnt_10_s3/F |
5.054 | 1.029 | tNET | FF | 1 | R12C38[3][A] | u_test_gen/n63_s4/I3 |
5.425 | 0.371 | tINS | FF | 12 | R12C38[3][A] | u_test_gen/n63_s4/F |
5.447 | 0.022 | tNET | FF | 1 | R12C38[1][B] | u_test_gen/n65_s2/I0 |
5.909 | 0.462 | tINS | FR | 1 | R12C38[1][B] | u_test_gen/n65_s2/F |
5.909 | 0.000 | tNET | RR | 1 | R12C38[1][B] | u_test_gen/V_cnt_9_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.059 | 7.059 | active clock edge time | ||||
7.059 | 0.000 | pixel_clk | ||||
7.059 | 0.000 | tCL | RR | 279 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD3 |
9.330 | 2.271 | tNET | RR | 1 | R12C38[1][B] | u_test_gen/V_cnt_9_s1/CLK |
9.295 | -0.035 | tSu | 1 | R12C38[1][B] | u_test_gen/V_cnt_9_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 7.059 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 1.759, 48.359%; route: 1.646, 45.263%; tC2Q: 0.232, 6.378% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path19
Path Summary:
Slack | 3.440 |
Data Arrival Time | 5.855 |
Data Required Time | 9.295 |
From | vs_cnt_9_s0 |
To | u_test_gen/Data_tmp_0_s1 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 279 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD3 |
2.271 | 2.271 | tNET | RR | 1 | R16C13[1][B] | vs_cnt_9_s0/CLK |
2.503 | 0.232 | tC2Q | RF | 28 | R16C13[1][B] | vs_cnt_9_s0/Q |
4.188 | 1.684 | tNET | FF | 1 | R16C38[1][B] | u_test_gen/Data_sel_7_s1/I2 |
4.705 | 0.517 | tINS | FF | 8 | R16C38[1][B] | u_test_gen/Data_sel_7_s1/F |
5.393 | 0.689 | tNET | FF | 1 | R22C38[0][A] | u_test_gen/Data_sel_0_s1/I3 |
5.855 | 0.462 | tINS | FR | 1 | R22C38[0][A] | u_test_gen/Data_sel_0_s1/F |
5.855 | 0.000 | tNET | RR | 1 | R22C38[0][A] | u_test_gen/Data_tmp_0_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.059 | 7.059 | active clock edge time | ||||
7.059 | 0.000 | pixel_clk | ||||
7.059 | 0.000 | tCL | RR | 279 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD3 |
9.330 | 2.271 | tNET | RR | 1 | R22C38[0][A] | u_test_gen/Data_tmp_0_s1/CLK |
9.295 | -0.035 | tSu | 1 | R22C38[0][A] | u_test_gen/Data_tmp_0_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 7.059 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 0.979, 27.315%; route: 2.373, 66.212%; tC2Q: 0.232, 6.473% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path20
Path Summary:
Slack | 3.440 |
Data Arrival Time | 5.855 |
Data Required Time | 9.295 |
From | vs_cnt_9_s0 |
To | u_test_gen/Data_tmp_1_s1 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 279 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD3 |
2.271 | 2.271 | tNET | RR | 1 | R16C13[1][B] | vs_cnt_9_s0/CLK |
2.503 | 0.232 | tC2Q | RF | 28 | R16C13[1][B] | vs_cnt_9_s0/Q |
4.188 | 1.684 | tNET | FF | 1 | R16C38[1][B] | u_test_gen/Data_sel_7_s1/I2 |
4.705 | 0.517 | tINS | FF | 8 | R16C38[1][B] | u_test_gen/Data_sel_7_s1/F |
5.393 | 0.689 | tNET | FF | 1 | R22C38[0][B] | u_test_gen/Data_sel_1_s1/I3 |
5.855 | 0.462 | tINS | FR | 1 | R22C38[0][B] | u_test_gen/Data_sel_1_s1/F |
5.855 | 0.000 | tNET | RR | 1 | R22C38[0][B] | u_test_gen/Data_tmp_1_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.059 | 7.059 | active clock edge time | ||||
7.059 | 0.000 | pixel_clk | ||||
7.059 | 0.000 | tCL | RR | 279 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD3 |
9.330 | 2.271 | tNET | RR | 1 | R22C38[0][B] | u_test_gen/Data_tmp_1_s1/CLK |
9.295 | -0.035 | tSu | 1 | R22C38[0][B] | u_test_gen/Data_tmp_1_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 7.059 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 0.979, 27.315%; route: 2.373, 66.212%; tC2Q: 0.232, 6.473% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Setup Analysis Report[2]:
Report Command:report_timing -setup -from_clock [get_clocks {byte_clk}] -max_paths 20 -max_common_paths 1
Path1
Path Summary:
Slack | 1.751 |
Data Arrival Time | 9.897 |
Data Required Time | 11.648 |
From | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s |
To | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rWrOffset_8_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
2.271 | 2.271 | tNET | RR | 18 | BSRAM_R28[5] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/CLKB |
4.531 | 2.260 | tC2Q | RF | 2 | BSRAM_R28[5] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14] |
5.477 | 0.945 | tNET | FF | 1 | R21C15[2][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s3/I1 |
5.848 | 0.371 | tINS | FF | 4 | R21C15[2][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s3/F |
5.865 | 0.018 | tNET | FF | 1 | R21C15[1][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s2/I1 |
6.318 | 0.453 | tINS | FF | 11 | R21C15[1][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s2/F |
6.783 | 0.465 | tNET | FF | 1 | R22C17[2][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n58_s2/I0 |
7.300 | 0.517 | tINS | FF | 4 | R22C17[2][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n58_s2/F |
7.706 | 0.406 | tNET | FF | 1 | R23C17[1][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n128_s1/I3 |
8.077 | 0.371 | tINS | FF | 4 | R23C17[1][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n128_s1/F |
8.499 | 0.422 | tNET | FF | 1 | R25C18[2][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n125_s1/I2 |
8.870 | 0.371 | tINS | FF | 3 | R25C18[2][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n125_s1/F |
8.883 | 0.013 | tNET | FF | 1 | R25C18[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n123_s1/I3 |
9.432 | 0.549 | tINS | FR | 2 | R25C18[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n123_s1/F |
9.435 | 0.003 | tNET | RR | 1 | R25C18[1][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n124_s0/I1 |
9.897 | 0.462 | tINS | RR | 1 | R25C18[1][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n124_s0/F |
9.897 | 0.000 | tNET | RR | 1 | R25C18[1][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rWrOffset_8_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
11.683 | 2.271 | tNET | RR | 1 | R25C18[1][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rWrOffset_8_s1/CLK |
11.648 | -0.035 | tSu | 1 | R25C18[1][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rWrOffset_8_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 9.412 |
Logic Level | 8 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 3.094, 40.575%; route: 2.271, 29.788%; tC2Q: 2.260, 29.638% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path2
Path Summary:
Slack | 1.751 |
Data Arrival Time | 9.897 |
Data Required Time | 11.648 |
From | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s |
To | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rWrOffset_9_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
2.271 | 2.271 | tNET | RR | 18 | BSRAM_R28[5] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/CLKB |
4.531 | 2.260 | tC2Q | RF | 2 | BSRAM_R28[5] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14] |
5.477 | 0.945 | tNET | FF | 1 | R21C15[2][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s3/I1 |
5.848 | 0.371 | tINS | FF | 4 | R21C15[2][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s3/F |
5.865 | 0.018 | tNET | FF | 1 | R21C15[1][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s2/I1 |
6.318 | 0.453 | tINS | FF | 11 | R21C15[1][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s2/F |
6.783 | 0.465 | tNET | FF | 1 | R22C17[2][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n58_s2/I0 |
7.300 | 0.517 | tINS | FF | 4 | R22C17[2][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n58_s2/F |
7.706 | 0.406 | tNET | FF | 1 | R23C17[1][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n128_s1/I3 |
8.077 | 0.371 | tINS | FF | 4 | R23C17[1][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n128_s1/F |
8.499 | 0.422 | tNET | FF | 1 | R25C18[2][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n125_s1/I2 |
8.870 | 0.371 | tINS | FF | 3 | R25C18[2][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n125_s1/F |
8.883 | 0.013 | tNET | FF | 1 | R25C18[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n123_s1/I3 |
9.432 | 0.549 | tINS | FR | 2 | R25C18[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n123_s1/F |
9.435 | 0.003 | tNET | RR | 1 | R25C18[1][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n123_s0/I1 |
9.897 | 0.462 | tINS | RR | 1 | R25C18[1][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n123_s0/F |
9.897 | 0.000 | tNET | RR | 1 | R25C18[1][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rWrOffset_9_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
11.683 | 2.271 | tNET | RR | 1 | R25C18[1][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rWrOffset_9_s1/CLK |
11.648 | -0.035 | tSu | 1 | R25C18[1][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rWrOffset_9_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 9.412 |
Logic Level | 8 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 3.094, 40.575%; route: 2.271, 29.788%; tC2Q: 2.260, 29.638% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path3
Path Summary:
Slack | 1.940 |
Data Arrival Time | 9.708 |
Data Required Time | 11.648 |
From | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s |
To | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_4_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
2.271 | 2.271 | tNET | RR | 18 | BSRAM_R28[5] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/CLKB |
4.531 | 2.260 | tC2Q | RF | 2 | BSRAM_R28[5] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14] |
5.477 | 0.945 | tNET | FF | 1 | R21C15[2][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s3/I1 |
5.848 | 0.371 | tINS | FF | 4 | R21C15[2][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s3/F |
5.865 | 0.018 | tNET | FF | 1 | R21C15[1][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s2/I1 |
6.318 | 0.453 | tINS | FF | 11 | R21C15[1][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s2/F |
6.772 | 0.453 | tNET | FF | 1 | R22C17[0][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rFull_s4/I2 |
7.327 | 0.555 | tINS | FF | 6 | R22C17[0][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rFull_s4/F |
7.773 | 0.446 | tNET | FF | 1 | R21C18[2][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n56_s1/I2 |
8.226 | 0.453 | tINS | FF | 4 | R21C18[2][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n56_s1/F |
8.239 | 0.013 | tNET | FF | 1 | R21C18[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n55_s1/I1 |
8.756 | 0.517 | tINS | FF | 1 | R21C18[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n55_s1/F |
9.246 | 0.490 | tNET | FF | 1 | R22C17[0][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n55_s0/I1 |
9.708 | 0.462 | tINS | FR | 1 | R22C17[0][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n55_s0/F |
9.708 | 0.000 | tNET | RR | 1 | R22C17[0][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_4_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
11.683 | 2.271 | tNET | RR | 1 | R22C17[0][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_4_s1/CLK |
11.648 | -0.035 | tSu | 1 | R22C17[0][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_4_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 9.412 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 2.811, 37.801%; route: 2.365, 31.807%; tC2Q: 2.260, 30.392% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path4
Path Summary:
Slack | 2.066 |
Data Arrival Time | 9.582 |
Data Required Time | 11.648 |
From | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s |
To | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rRdOffset_8_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
2.271 | 2.271 | tNET | RR | 18 | BSRAM_R28[5] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/CLKB |
4.531 | 2.260 | tC2Q | RF | 2 | BSRAM_R28[5] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14] |
5.477 | 0.945 | tNET | FF | 1 | R21C15[2][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s3/I1 |
5.848 | 0.371 | tINS | FF | 4 | R21C15[2][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s3/F |
5.865 | 0.018 | tNET | FF | 1 | R21C15[1][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s2/I1 |
6.318 | 0.453 | tINS | FF | 11 | R21C15[1][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s2/F |
7.026 | 0.708 | tNET | FF | 1 | R24C17[1][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n167_s2/I3 |
7.581 | 0.555 | tINS | FF | 4 | R24C17[1][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n167_s2/F |
7.994 | 0.413 | tNET | FF | 1 | R24C18[2][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n164_s1/I3 |
8.564 | 0.570 | tINS | FR | 4 | R24C18[2][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n164_s1/F |
8.568 | 0.004 | tNET | RR | 1 | R24C18[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n162_s1/I3 |
9.117 | 0.549 | tINS | RR | 2 | R24C18[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n162_s1/F |
9.120 | 0.003 | tNET | RR | 1 | R24C18[1][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n163_s0/I1 |
9.582 | 0.462 | tINS | RR | 1 | R24C18[1][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n163_s0/F |
9.582 | 0.000 | tNET | RR | 1 | R24C18[1][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rRdOffset_8_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
11.683 | 2.271 | tNET | RR | 1 | R24C18[1][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rRdOffset_8_s1/CLK |
11.648 | -0.035 | tSu | 1 | R24C18[1][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rRdOffset_8_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 9.412 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 2.960, 40.490%; route: 2.091, 28.596%; tC2Q: 2.260, 30.914% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path5
Path Summary:
Slack | 2.066 |
Data Arrival Time | 9.582 |
Data Required Time | 11.648 |
From | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s |
To | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rRdOffset_9_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
2.271 | 2.271 | tNET | RR | 18 | BSRAM_R28[5] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/CLKB |
4.531 | 2.260 | tC2Q | RF | 2 | BSRAM_R28[5] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14] |
5.477 | 0.945 | tNET | FF | 1 | R21C15[2][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s3/I1 |
5.848 | 0.371 | tINS | FF | 4 | R21C15[2][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s3/F |
5.865 | 0.018 | tNET | FF | 1 | R21C15[1][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s2/I1 |
6.318 | 0.453 | tINS | FF | 11 | R21C15[1][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s2/F |
7.026 | 0.708 | tNET | FF | 1 | R24C17[1][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n167_s2/I3 |
7.581 | 0.555 | tINS | FF | 4 | R24C17[1][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n167_s2/F |
7.994 | 0.413 | tNET | FF | 1 | R24C18[2][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n164_s1/I3 |
8.564 | 0.570 | tINS | FR | 4 | R24C18[2][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n164_s1/F |
8.568 | 0.004 | tNET | RR | 1 | R24C18[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n162_s1/I3 |
9.117 | 0.549 | tINS | RR | 2 | R24C18[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n162_s1/F |
9.120 | 0.003 | tNET | RR | 1 | R24C18[1][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n162_s0/I1 |
9.582 | 0.462 | tINS | RR | 1 | R24C18[1][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n162_s0/F |
9.582 | 0.000 | tNET | RR | 1 | R24C18[1][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rRdOffset_9_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
11.683 | 2.271 | tNET | RR | 1 | R24C18[1][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rRdOffset_9_s1/CLK |
11.648 | -0.035 | tSu | 1 | R24C18[1][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rRdOffset_9_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 9.412 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 2.960, 40.490%; route: 2.091, 28.596%; tC2Q: 2.260, 30.914% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path6
Path Summary:
Slack | 2.092 |
Data Arrival Time | 9.557 |
Data Required Time | 11.648 |
From | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s |
To | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_5_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
2.271 | 2.271 | tNET | RR | 18 | BSRAM_R28[5] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/CLKB |
4.531 | 2.260 | tC2Q | RF | 2 | BSRAM_R28[5] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14] |
5.477 | 0.945 | tNET | FF | 1 | R21C15[2][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s3/I1 |
5.848 | 0.371 | tINS | FF | 4 | R21C15[2][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s3/F |
5.865 | 0.018 | tNET | FF | 1 | R21C15[1][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s2/I1 |
6.318 | 0.453 | tINS | FF | 11 | R21C15[1][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s2/F |
6.772 | 0.453 | tNET | FF | 1 | R22C17[0][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rFull_s4/I2 |
7.327 | 0.555 | tINS | FF | 6 | R22C17[0][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rFull_s4/F |
7.773 | 0.446 | tNET | FF | 1 | R21C18[2][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n56_s1/I2 |
8.226 | 0.453 | tINS | FF | 4 | R21C18[2][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n56_s1/F |
8.414 | 0.188 | tNET | FF | 1 | R21C17[0][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n53_s1/I3 |
8.984 | 0.570 | tINS | FR | 2 | R21C17[0][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n53_s1/F |
8.987 | 0.003 | tNET | RR | 1 | R21C17[1][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n54_s0/I1 |
9.557 | 0.570 | tINS | RR | 1 | R21C17[1][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n54_s0/F |
9.557 | 0.000 | tNET | RR | 1 | R21C17[1][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_5_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
11.683 | 2.271 | tNET | RR | 1 | R21C17[1][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_5_s1/CLK |
11.648 | -0.035 | tSu | 1 | R21C17[1][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_5_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 9.412 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 2.972, 40.795%; route: 2.053, 28.183%; tC2Q: 2.260, 31.022% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path7
Path Summary:
Slack | 2.092 |
Data Arrival Time | 9.557 |
Data Required Time | 11.648 |
From | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s |
To | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_6_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
2.271 | 2.271 | tNET | RR | 18 | BSRAM_R28[5] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/CLKB |
4.531 | 2.260 | tC2Q | RF | 2 | BSRAM_R28[5] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14] |
5.477 | 0.945 | tNET | FF | 1 | R21C15[2][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s3/I1 |
5.848 | 0.371 | tINS | FF | 4 | R21C15[2][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s3/F |
5.865 | 0.018 | tNET | FF | 1 | R21C15[1][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s2/I1 |
6.318 | 0.453 | tINS | FF | 11 | R21C15[1][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s2/F |
6.772 | 0.453 | tNET | FF | 1 | R22C17[0][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rFull_s4/I2 |
7.327 | 0.555 | tINS | FF | 6 | R22C17[0][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rFull_s4/F |
7.773 | 0.446 | tNET | FF | 1 | R21C18[2][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n56_s1/I2 |
8.226 | 0.453 | tINS | FF | 4 | R21C18[2][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n56_s1/F |
8.414 | 0.188 | tNET | FF | 1 | R21C17[0][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n53_s1/I3 |
8.984 | 0.570 | tINS | FR | 2 | R21C17[0][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n53_s1/F |
8.987 | 0.003 | tNET | RR | 1 | R21C17[2][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n53_s0/I0 |
9.557 | 0.570 | tINS | RR | 1 | R21C17[2][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n53_s0/F |
9.557 | 0.000 | tNET | RR | 1 | R21C17[2][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_6_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
11.683 | 2.271 | tNET | RR | 1 | R21C17[2][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_6_s1/CLK |
11.648 | -0.035 | tSu | 1 | R21C17[2][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_6_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 9.412 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 2.972, 40.795%; route: 2.053, 28.183%; tC2Q: 2.260, 31.022% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path8
Path Summary:
Slack | 2.216 |
Data Arrival Time | 9.432 |
Data Required Time | 11.648 |
From | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s |
To | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rWrOffset_6_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
2.271 | 2.271 | tNET | RR | 18 | BSRAM_R28[5] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/CLKB |
4.531 | 2.260 | tC2Q | RF | 2 | BSRAM_R28[5] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14] |
5.477 | 0.945 | tNET | FF | 1 | R21C15[2][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s3/I1 |
5.848 | 0.371 | tINS | FF | 4 | R21C15[2][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s3/F |
5.865 | 0.018 | tNET | FF | 1 | R21C15[1][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s2/I1 |
6.318 | 0.453 | tINS | FF | 11 | R21C15[1][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s2/F |
6.783 | 0.465 | tNET | FF | 1 | R22C17[2][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n58_s2/I0 |
7.300 | 0.517 | tINS | FF | 4 | R22C17[2][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n58_s2/F |
7.706 | 0.406 | tNET | FF | 1 | R23C17[1][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n128_s1/I3 |
8.077 | 0.371 | tINS | FF | 4 | R23C17[1][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n128_s1/F |
8.499 | 0.422 | tNET | FF | 1 | R25C18[2][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n125_s1/I2 |
8.870 | 0.371 | tINS | FF | 3 | R25C18[2][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n125_s1/F |
8.883 | 0.013 | tNET | FF | 1 | R25C18[0][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n126_s0/I1 |
9.432 | 0.549 | tINS | FR | 1 | R25C18[0][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n126_s0/F |
9.432 | 0.000 | tNET | RR | 1 | R25C18[0][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rWrOffset_6_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
11.683 | 2.271 | tNET | RR | 1 | R25C18[0][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rWrOffset_6_s1/CLK |
11.648 | -0.035 | tSu | 1 | R25C18[0][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rWrOffset_6_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 9.412 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 2.632, 36.756%; route: 2.269, 31.684%; tC2Q: 2.260, 31.561% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path9
Path Summary:
Slack | 2.216 |
Data Arrival Time | 9.432 |
Data Required Time | 11.648 |
From | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s |
To | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rWrOffset_7_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
2.271 | 2.271 | tNET | RR | 18 | BSRAM_R28[5] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/CLKB |
4.531 | 2.260 | tC2Q | RF | 2 | BSRAM_R28[5] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14] |
5.477 | 0.945 | tNET | FF | 1 | R21C15[2][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s3/I1 |
5.848 | 0.371 | tINS | FF | 4 | R21C15[2][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s3/F |
5.865 | 0.018 | tNET | FF | 1 | R21C15[1][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s2/I1 |
6.318 | 0.453 | tINS | FF | 11 | R21C15[1][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s2/F |
6.783 | 0.465 | tNET | FF | 1 | R22C17[2][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n58_s2/I0 |
7.300 | 0.517 | tINS | FF | 4 | R22C17[2][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n58_s2/F |
7.706 | 0.406 | tNET | FF | 1 | R23C17[1][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n128_s1/I3 |
8.077 | 0.371 | tINS | FF | 4 | R23C17[1][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n128_s1/F |
8.499 | 0.422 | tNET | FF | 1 | R25C18[2][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n125_s1/I2 |
8.870 | 0.371 | tINS | FF | 3 | R25C18[2][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n125_s1/F |
8.883 | 0.013 | tNET | FF | 1 | R25C18[0][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n125_s0/I2 |
9.432 | 0.549 | tINS | FR | 1 | R25C18[0][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n125_s0/F |
9.432 | 0.000 | tNET | RR | 1 | R25C18[0][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rWrOffset_7_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
11.683 | 2.271 | tNET | RR | 1 | R25C18[0][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rWrOffset_7_s1/CLK |
11.648 | -0.035 | tSu | 1 | R25C18[0][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rWrOffset_7_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 9.412 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 2.632, 36.756%; route: 2.269, 31.684%; tC2Q: 2.260, 31.561% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path10
Path Summary:
Slack | 2.223 |
Data Arrival Time | 9.425 |
Data Required Time | 11.648 |
From | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s |
To | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rRdOffset_6_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
2.271 | 2.271 | tNET | RR | 18 | BSRAM_R28[5] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/CLKB |
4.531 | 2.260 | tC2Q | RF | 2 | BSRAM_R28[5] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14] |
5.477 | 0.945 | tNET | FF | 1 | R21C15[2][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s3/I1 |
5.848 | 0.371 | tINS | FF | 4 | R21C15[2][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s3/F |
5.865 | 0.018 | tNET | FF | 1 | R21C15[1][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s2/I1 |
6.318 | 0.453 | tINS | FF | 11 | R21C15[1][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s2/F |
7.026 | 0.708 | tNET | FF | 1 | R24C17[1][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n167_s2/I3 |
7.581 | 0.555 | tINS | FF | 4 | R24C17[1][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n167_s2/F |
7.994 | 0.413 | tNET | FF | 1 | R24C18[2][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n164_s1/I3 |
8.549 | 0.555 | tINS | FF | 4 | R24C18[2][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n164_s1/F |
8.963 | 0.414 | tNET | FF | 1 | R23C18[2][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n165_s0/I1 |
9.425 | 0.462 | tINS | FR | 1 | R23C18[2][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n165_s0/F |
9.425 | 0.000 | tNET | RR | 1 | R23C18[2][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rRdOffset_6_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
11.683 | 2.271 | tNET | RR | 1 | R23C18[2][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rRdOffset_6_s1/CLK |
11.648 | -0.035 | tSu | 1 | R23C18[2][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rRdOffset_6_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 9.412 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 2.396, 33.494%; route: 2.497, 34.912%; tC2Q: 2.260, 31.593% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path11
Path Summary:
Slack | 2.285 |
Data Arrival Time | 9.230 |
Data Required Time | 11.515 |
From | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s |
To | u_tx_phy/DPHY_TX_INST/u_oserx4x8/U5_OSER82 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
2.271 | 2.271 | tNET | RR | 18 | BSRAM_R28[5] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/CLKB |
4.531 | 2.260 | tC2Q | RF | 2 | BSRAM_R28[5] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14] |
5.477 | 0.945 | tNET | FF | 1 | R21C15[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA3_d_7_s0/I1 |
5.848 | 0.371 | tINS | FF | 33 | R21C15[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA3_d_7_s0/F |
6.090 | 0.242 | tNET | FF | 1 | R22C15[0][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA2_d_4_s/I2 |
6.645 | 0.555 | tINS | FF | 2 | R22C15[0][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA2_d_4_s/F |
9.230 | 2.585 | tNET | FF | 1 | IOT52[A] | u_tx_phy/DPHY_TX_INST/u_oserx4x8/U5_OSER82/D4 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
11.683 | 2.271 | tNET | RR | 1 | IOT52[A] | u_tx_phy/DPHY_TX_INST/u_oserx4x8/U5_OSER82/PCLK |
11.515 | -0.168 | tSu | 1 | IOT52[A] | u_tx_phy/DPHY_TX_INST/u_oserx4x8/U5_OSER82 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 9.412 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 0.926, 13.308%; route: 3.772, 54.214%; tC2Q: 2.260, 32.479% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path12
Path Summary:
Slack | 2.288 |
Data Arrival Time | 9.230 |
Data Required Time | 11.518 |
From | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s |
To | u_tx_phy/DPHY_TX_INST/u_oserx4x8/U5_OSER82 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
2.271 | 2.271 | tNET | RR | 18 | BSRAM_R28[5] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/CLKB |
4.531 | 2.260 | tC2Q | RF | 2 | BSRAM_R28[5] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14] |
5.477 | 0.945 | tNET | FF | 1 | R21C15[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA3_d_7_s0/I1 |
5.848 | 0.371 | tINS | FF | 33 | R21C15[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA3_d_7_s0/F |
6.090 | 0.242 | tNET | FF | 1 | R22C15[1][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA2_d_5_s/I2 |
6.645 | 0.555 | tINS | FF | 2 | R22C15[1][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA2_d_5_s/F |
9.230 | 2.585 | tNET | FF | 1 | IOT52[A] | u_tx_phy/DPHY_TX_INST/u_oserx4x8/U5_OSER82/D5 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
11.683 | 2.271 | tNET | RR | 1 | IOT52[A] | u_tx_phy/DPHY_TX_INST/u_oserx4x8/U5_OSER82/PCLK |
11.518 | -0.165 | tSu | 1 | IOT52[A] | u_tx_phy/DPHY_TX_INST/u_oserx4x8/U5_OSER82 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 9.412 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 0.926, 13.308%; route: 3.772, 54.214%; tC2Q: 2.260, 32.479% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path13
Path Summary:
Slack | 2.288 |
Data Arrival Time | 9.230 |
Data Required Time | 11.518 |
From | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s |
To | u_tx_phy/DPHY_TX_INST/u_oserx4x8/U5_OSER82 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
2.271 | 2.271 | tNET | RR | 18 | BSRAM_R28[5] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/CLKB |
4.531 | 2.260 | tC2Q | RF | 2 | BSRAM_R28[5] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14] |
5.477 | 0.945 | tNET | FF | 1 | R21C15[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA3_d_7_s0/I1 |
5.848 | 0.371 | tINS | FF | 33 | R21C15[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA3_d_7_s0/F |
6.090 | 0.242 | tNET | FF | 1 | R22C15[0][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA2_d_3_s/I2 |
6.645 | 0.555 | tINS | FF | 2 | R22C15[0][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA2_d_3_s/F |
9.230 | 2.585 | tNET | FF | 1 | IOT52[A] | u_tx_phy/DPHY_TX_INST/u_oserx4x8/U5_OSER82/D3 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
11.683 | 2.271 | tNET | RR | 1 | IOT52[A] | u_tx_phy/DPHY_TX_INST/u_oserx4x8/U5_OSER82/PCLK |
11.518 | -0.165 | tSu | 1 | IOT52[A] | u_tx_phy/DPHY_TX_INST/u_oserx4x8/U5_OSER82 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 9.412 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 0.926, 13.308%; route: 3.772, 54.214%; tC2Q: 2.260, 32.479% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path14
Path Summary:
Slack | 2.304 |
Data Arrival Time | 9.211 |
Data Required Time | 11.515 |
From | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s |
To | u_tx_phy/DPHY_TX_INST/u_oserx4x8/U5_OSER81 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
2.271 | 2.271 | tNET | RR | 18 | BSRAM_R28[5] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/CLKB |
4.531 | 2.260 | tC2Q | RF | 2 | BSRAM_R28[5] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14] |
5.477 | 0.945 | tNET | FF | 1 | R21C15[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA3_d_7_s0/I1 |
5.848 | 0.371 | tINS | FF | 33 | R21C15[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA3_d_7_s0/F |
6.367 | 0.519 | tNET | FF | 1 | R22C14[1][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA1_d_0_s/I2 |
6.820 | 0.453 | tINS | FF | 2 | R22C14[1][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA1_d_0_s/F |
9.211 | 2.390 | tNET | FF | 1 | IOT48[A] | u_tx_phy/DPHY_TX_INST/u_oserx4x8/U5_OSER81/D0 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
11.683 | 2.271 | tNET | RR | 1 | IOT48[A] | u_tx_phy/DPHY_TX_INST/u_oserx4x8/U5_OSER81/PCLK |
11.515 | -0.168 | tSu | 1 | IOT48[A] | u_tx_phy/DPHY_TX_INST/u_oserx4x8/U5_OSER81 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 9.412 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 0.824, 11.874%; route: 3.855, 55.558%; tC2Q: 2.260, 32.568% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path15
Path Summary:
Slack | 2.307 |
Data Arrival Time | 9.211 |
Data Required Time | 11.518 |
From | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s |
To | u_tx_phy/DPHY_TX_INST/u_oserx4x8/U5_OSER81 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
2.271 | 2.271 | tNET | RR | 18 | BSRAM_R28[5] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/CLKB |
4.531 | 2.260 | tC2Q | RF | 2 | BSRAM_R28[5] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14] |
5.477 | 0.945 | tNET | FF | 1 | R21C15[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA3_d_7_s0/I1 |
5.848 | 0.371 | tINS | FF | 33 | R21C15[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA3_d_7_s0/F |
6.367 | 0.519 | tNET | FF | 1 | R23C14[1][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA1_d_1_s/I2 |
6.820 | 0.453 | tINS | FF | 2 | R23C14[1][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA1_d_1_s/F |
9.211 | 2.390 | tNET | FF | 1 | IOT48[A] | u_tx_phy/DPHY_TX_INST/u_oserx4x8/U5_OSER81/D1 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
11.683 | 2.271 | tNET | RR | 1 | IOT48[A] | u_tx_phy/DPHY_TX_INST/u_oserx4x8/U5_OSER81/PCLK |
11.518 | -0.165 | tSu | 1 | IOT48[A] | u_tx_phy/DPHY_TX_INST/u_oserx4x8/U5_OSER81 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 9.412 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 0.824, 11.874%; route: 3.855, 55.558%; tC2Q: 2.260, 32.568% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path16
Path Summary:
Slack | 2.314 |
Data Arrival Time | 9.334 |
Data Required Time | 11.648 |
From | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s |
To | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rRdOffset_7_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
2.271 | 2.271 | tNET | RR | 18 | BSRAM_R28[5] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/CLKB |
4.531 | 2.260 | tC2Q | RF | 2 | BSRAM_R28[5] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14] |
5.477 | 0.945 | tNET | FF | 1 | R21C15[2][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s3/I1 |
5.848 | 0.371 | tINS | FF | 4 | R21C15[2][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s3/F |
5.865 | 0.018 | tNET | FF | 1 | R21C15[1][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s2/I1 |
6.318 | 0.453 | tINS | FF | 11 | R21C15[1][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s2/F |
7.026 | 0.708 | tNET | FF | 1 | R24C17[1][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n167_s2/I3 |
7.581 | 0.555 | tINS | FF | 4 | R24C17[1][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n167_s2/F |
7.994 | 0.413 | tNET | FF | 1 | R24C18[2][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n164_s1/I3 |
8.549 | 0.555 | tINS | FF | 4 | R24C18[2][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n164_s1/F |
8.963 | 0.414 | tNET | FF | 1 | R23C18[1][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n164_s0/I2 |
9.334 | 0.371 | tINS | FF | 1 | R23C18[1][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n164_s0/F |
9.334 | 0.000 | tNET | FF | 1 | R23C18[1][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rRdOffset_7_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
11.683 | 2.271 | tNET | RR | 1 | R23C18[1][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rRdOffset_7_s1/CLK |
11.648 | -0.035 | tSu | 1 | R23C18[1][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rRdOffset_7_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 9.412 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 2.305, 32.637%; route: 2.497, 35.362%; tC2Q: 2.260, 32.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path17
Path Summary:
Slack | 2.339 |
Data Arrival Time | 9.309 |
Data Required Time | 11.648 |
From | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s |
To | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rRdOffset_5_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
2.271 | 2.271 | tNET | RR | 18 | BSRAM_R28[5] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/CLKB |
4.531 | 2.260 | tC2Q | RF | 2 | BSRAM_R28[5] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14] |
5.477 | 0.945 | tNET | FF | 1 | R21C15[2][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s3/I1 |
5.848 | 0.371 | tINS | FF | 4 | R21C15[2][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s3/F |
5.865 | 0.018 | tNET | FF | 1 | R21C15[1][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s2/I1 |
6.318 | 0.453 | tINS | FF | 11 | R21C15[1][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s2/F |
7.026 | 0.708 | tNET | FF | 1 | R24C17[1][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n167_s2/I3 |
7.581 | 0.555 | tINS | FF | 4 | R24C17[1][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n167_s2/F |
7.994 | 0.413 | tNET | FF | 1 | R24C18[2][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n164_s1/I3 |
8.564 | 0.570 | tINS | FR | 4 | R24C18[2][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n164_s1/F |
8.739 | 0.175 | tNET | RR | 1 | R23C18[2][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n166_s0/I1 |
9.309 | 0.570 | tINS | RR | 1 | R23C18[2][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n166_s0/F |
9.309 | 0.000 | tNET | RR | 1 | R23C18[2][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rRdOffset_5_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
11.683 | 2.271 | tNET | RR | 1 | R23C18[2][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rRdOffset_5_s1/CLK |
11.648 | -0.035 | tSu | 1 | R23C18[2][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rRdOffset_5_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 9.412 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 2.519, 35.791%; route: 2.259, 32.097%; tC2Q: 2.260, 32.111% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path18
Path Summary:
Slack | 2.358 |
Data Arrival Time | 9.157 |
Data Required Time | 11.515 |
From | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s |
To | u_tx_phy/DPHY_TX_INST/u_oserx4x8/U5_OSER80 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
2.271 | 2.271 | tNET | RR | 18 | BSRAM_R28[5] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/CLKB |
4.531 | 2.260 | tC2Q | RF | 2 | BSRAM_R28[5] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14] |
5.477 | 0.945 | tNET | FF | 1 | R21C15[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA3_d_7_s0/I1 |
5.848 | 0.371 | tINS | FF | 33 | R21C15[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA3_d_7_s0/F |
6.367 | 0.519 | tNET | FF | 1 | R23C14[3][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA0_d_4_s/I2 |
6.738 | 0.371 | tINS | FF | 2 | R23C14[3][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA0_d_4_s/F |
9.157 | 2.419 | tNET | FF | 1 | IOT54[A] | u_tx_phy/DPHY_TX_INST/u_oserx4x8/U5_OSER80/D4 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
11.683 | 2.271 | tNET | RR | 1 | IOT54[A] | u_tx_phy/DPHY_TX_INST/u_oserx4x8/U5_OSER80/PCLK |
11.515 | -0.168 | tSu | 1 | IOT54[A] | u_tx_phy/DPHY_TX_INST/u_oserx4x8/U5_OSER80 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 9.412 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 0.742, 10.776%; route: 3.883, 56.401%; tC2Q: 2.260, 32.823% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path19
Path Summary:
Slack | 2.358 |
Data Arrival Time | 9.157 |
Data Required Time | 11.515 |
From | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s |
To | u_tx_phy/DPHY_TX_INST/u_oserx4x8/U5_OSER80 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
2.271 | 2.271 | tNET | RR | 18 | BSRAM_R28[5] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/CLKB |
4.531 | 2.260 | tC2Q | RF | 2 | BSRAM_R28[5] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14] |
5.477 | 0.945 | tNET | FF | 1 | R21C15[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA3_d_7_s0/I1 |
5.848 | 0.371 | tINS | FF | 33 | R21C15[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA3_d_7_s0/F |
6.367 | 0.519 | tNET | FF | 1 | R22C14[3][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA0_d_2_s/I2 |
6.738 | 0.371 | tINS | FF | 2 | R22C14[3][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA0_d_2_s/F |
9.157 | 2.419 | tNET | FF | 1 | IOT54[A] | u_tx_phy/DPHY_TX_INST/u_oserx4x8/U5_OSER80/D2 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
11.683 | 2.271 | tNET | RR | 1 | IOT54[A] | u_tx_phy/DPHY_TX_INST/u_oserx4x8/U5_OSER80/PCLK |
11.515 | -0.168 | tSu | 1 | IOT54[A] | u_tx_phy/DPHY_TX_INST/u_oserx4x8/U5_OSER80 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 9.412 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 0.742, 10.776%; route: 3.883, 56.401%; tC2Q: 2.260, 32.823% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path20
Path Summary:
Slack | 2.358 |
Data Arrival Time | 9.157 |
Data Required Time | 11.515 |
From | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s |
To | u_tx_phy/DPHY_TX_INST/u_oserx4x8/U5_OSER80 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
2.271 | 2.271 | tNET | RR | 18 | BSRAM_R28[5] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/CLKB |
4.531 | 2.260 | tC2Q | RF | 2 | BSRAM_R28[5] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14] |
5.477 | 0.945 | tNET | FF | 1 | R21C15[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA3_d_7_s0/I1 |
5.848 | 0.371 | tINS | FF | 33 | R21C15[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA3_d_7_s0/F |
6.367 | 0.519 | tNET | FF | 1 | R22C14[2][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA0_d_0_s/I2 |
6.738 | 0.371 | tINS | FF | 2 | R22C14[2][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA0_d_0_s/F |
9.157 | 2.419 | tNET | FF | 1 | IOT54[A] | u_tx_phy/DPHY_TX_INST/u_oserx4x8/U5_OSER80/D0 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
11.683 | 2.271 | tNET | RR | 1 | IOT54[A] | u_tx_phy/DPHY_TX_INST/u_oserx4x8/U5_OSER80/PCLK |
11.515 | -0.168 | tSu | 1 | IOT54[A] | u_tx_phy/DPHY_TX_INST/u_oserx4x8/U5_OSER80 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 9.412 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 0.742, 10.776%; route: 3.883, 56.401%; tC2Q: 2.260, 32.823% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Hold Analysis Report
Hold Analysis Report[1]:
Report Command:report_timing -hold -from_clock [get_clocks {pixel_clk}] -max_paths 20 -max_common_paths 1
Path1
Path Summary:
Slack | 0.311 |
Data Arrival Time | 1.834 |
Data Required Time | 1.523 |
From | u_p2b/u_p2b_0/mid_data_2_s1 |
To | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mSsram_mSsram_0_0_s |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 279 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD3 |
1.511 | 1.511 | tNET | RR | 1 | R16C41[0][B] | u_p2b/u_p2b_0/mid_data_2_s1/CLK |
1.712 | 0.201 | tC2Q | RF | 1 | R16C41[0][B] | u_p2b/u_p2b_0/mid_data_2_s1/Q |
1.834 | 0.122 | tNET | FF | 1 | R15C41 | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mSsram_mSsram_0_0_s/DI[2] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 279 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD3 |
1.511 | 1.511 | tNET | RR | 1 | R15C41 | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mSsram_mSsram_0_0_s/CLK |
1.523 | 0.012 | tHld | 1 | R15C41 | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mSsram_mSsram_0_0_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.122, 37.751%; tC2Q: 0.201, 62.249% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path2
Path Summary:
Slack | 0.318 |
Data Arrival Time | 1.840 |
Data Required Time | 1.522 |
From | u_p2b/u_p2b_0/u_mid_buf/rRstWsync_s0 |
To | u_p2b/u_p2b_0/u_mid_buf/rWrRst_s0 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 279 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD3 |
1.511 | 1.511 | tNET | RR | 1 | R25C45[0][A] | u_p2b/u_p2b_0/u_mid_buf/rRstWsync_s0/CLK |
1.713 | 0.202 | tC2Q | RR | 1 | R25C45[0][A] | u_p2b/u_p2b_0/u_mid_buf/rRstWsync_s0/Q |
1.840 | 0.127 | tNET | RR | 1 | R25C45[1][B] | u_p2b/u_p2b_0/u_mid_buf/rWrRst_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 279 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD3 |
1.511 | 1.511 | tNET | RR | 1 | R25C45[1][B] | u_p2b/u_p2b_0/u_mid_buf/rWrRst_s0/CLK |
1.522 | 0.011 | tHld | 1 | R25C45[1][B] | u_p2b/u_p2b_0/u_mid_buf/rWrRst_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.127, 38.638%; tC2Q: 0.202, 61.362% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path3
Path Summary:
Slack | 0.334 |
Data Arrival Time | 1.857 |
Data Required Time | 1.523 |
From | u_p2b/u_p2b_0/u_mid_buf/rWPtrBin_2_s0 |
To | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mSsram_mSsram_0_7_s |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 279 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD3 |
1.511 | 1.511 | tNET | RR | 1 | R16C45[2][A] | u_p2b/u_p2b_0/u_mid_buf/rWPtrBin_2_s0/CLK |
1.712 | 0.201 | tC2Q | RF | 14 | R16C45[2][A] | u_p2b/u_p2b_0/u_mid_buf/rWPtrBin_2_s0/Q |
1.857 | 0.145 | tNET | FF | 1 | R15C45 | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mSsram_mSsram_0_7_s/WAD[2] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 279 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD3 |
1.511 | 1.511 | tNET | RR | 1 | R15C45 | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mSsram_mSsram_0_7_s/CLK |
1.523 | 0.012 | tHld | 1 | R15C45 | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mSsram_mSsram_0_7_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.145, 41.881%; tC2Q: 0.201, 58.119% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path4
Path Summary:
Slack | 0.424 |
Data Arrival Time | 1.946 |
Data Required Time | 1.522 |
From | run_cnt_2_s0 |
To | run_cnt_2_s0 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 279 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD3 |
1.511 | 1.511 | tNET | RR | 1 | R12C12[1][A] | run_cnt_2_s0/CLK |
1.713 | 0.202 | tC2Q | RR | 1 | R12C12[1][A] | run_cnt_2_s0/Q |
1.714 | 0.001 | tNET | RR | 2 | R12C12[1][A] | n67_s/I1 |
1.946 | 0.232 | tINS | RF | 1 | R12C12[1][A] | n67_s/SUM |
1.946 | 0.000 | tNET | FF | 1 | R12C12[1][A] | run_cnt_2_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 279 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD3 |
1.511 | 1.511 | tNET | RR | 1 | R12C12[1][A] | run_cnt_2_s0/CLK |
1.522 | 0.011 | tHld | 1 | R12C12[1][A] | run_cnt_2_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.232, 53.306%; route: 0.001, 0.281%; tC2Q: 0.202, 46.413% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path5
Path Summary:
Slack | 0.424 |
Data Arrival Time | 1.946 |
Data Required Time | 1.522 |
From | run_cnt_6_s0 |
To | run_cnt_6_s0 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 279 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD3 |
1.511 | 1.511 | tNET | RR | 1 | R12C13[0][A] | run_cnt_6_s0/CLK |
1.713 | 0.202 | tC2Q | RR | 1 | R12C13[0][A] | run_cnt_6_s0/Q |
1.714 | 0.001 | tNET | RR | 2 | R12C13[0][A] | n63_s/I1 |
1.946 | 0.232 | tINS | RF | 1 | R12C13[0][A] | n63_s/SUM |
1.946 | 0.000 | tNET | FF | 1 | R12C13[0][A] | run_cnt_6_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 279 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD3 |
1.511 | 1.511 | tNET | RR | 1 | R12C13[0][A] | run_cnt_6_s0/CLK |
1.522 | 0.011 | tHld | 1 | R12C13[0][A] | run_cnt_6_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.232, 53.306%; route: 0.001, 0.281%; tC2Q: 0.202, 46.413% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path6
Path Summary:
Slack | 0.424 |
Data Arrival Time | 1.946 |
Data Required Time | 1.522 |
From | run_cnt_8_s0 |
To | run_cnt_8_s0 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 279 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD3 |
1.511 | 1.511 | tNET | RR | 1 | R12C13[1][A] | run_cnt_8_s0/CLK |
1.713 | 0.202 | tC2Q | RR | 1 | R12C13[1][A] | run_cnt_8_s0/Q |
1.714 | 0.001 | tNET | RR | 2 | R12C13[1][A] | n61_s/I1 |
1.946 | 0.232 | tINS | RF | 1 | R12C13[1][A] | n61_s/SUM |
1.946 | 0.000 | tNET | FF | 1 | R12C13[1][A] | run_cnt_8_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 279 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD3 |
1.511 | 1.511 | tNET | RR | 1 | R12C13[1][A] | run_cnt_8_s0/CLK |
1.522 | 0.011 | tHld | 1 | R12C13[1][A] | run_cnt_8_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.232, 53.306%; route: 0.001, 0.281%; tC2Q: 0.202, 46.413% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path7
Path Summary:
Slack | 0.424 |
Data Arrival Time | 1.946 |
Data Required Time | 1.522 |
From | run_cnt_12_s0 |
To | run_cnt_12_s0 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 279 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD3 |
1.511 | 1.511 | tNET | RR | 1 | R12C14[0][A] | run_cnt_12_s0/CLK |
1.713 | 0.202 | tC2Q | RR | 1 | R12C14[0][A] | run_cnt_12_s0/Q |
1.714 | 0.001 | tNET | RR | 2 | R12C14[0][A] | n57_s/I1 |
1.946 | 0.232 | tINS | RF | 1 | R12C14[0][A] | n57_s/SUM |
1.946 | 0.000 | tNET | FF | 1 | R12C14[0][A] | run_cnt_12_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 279 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD3 |
1.511 | 1.511 | tNET | RR | 1 | R12C14[0][A] | run_cnt_12_s0/CLK |
1.522 | 0.011 | tHld | 1 | R12C14[0][A] | run_cnt_12_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.232, 53.306%; route: 0.001, 0.281%; tC2Q: 0.202, 46.413% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path8
Path Summary:
Slack | 0.424 |
Data Arrival Time | 1.946 |
Data Required Time | 1.522 |
From | run_cnt_14_s0 |
To | run_cnt_14_s0 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 279 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD3 |
1.511 | 1.511 | tNET | RR | 1 | R12C14[1][A] | run_cnt_14_s0/CLK |
1.713 | 0.202 | tC2Q | RR | 1 | R12C14[1][A] | run_cnt_14_s0/Q |
1.714 | 0.001 | tNET | RR | 2 | R12C14[1][A] | n55_s/I1 |
1.946 | 0.232 | tINS | RF | 1 | R12C14[1][A] | n55_s/SUM |
1.946 | 0.000 | tNET | FF | 1 | R12C14[1][A] | run_cnt_14_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 279 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD3 |
1.511 | 1.511 | tNET | RR | 1 | R12C14[1][A] | run_cnt_14_s0/CLK |
1.522 | 0.011 | tHld | 1 | R12C14[1][A] | run_cnt_14_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.232, 53.306%; route: 0.001, 0.281%; tC2Q: 0.202, 46.413% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path9
Path Summary:
Slack | 0.424 |
Data Arrival Time | 1.946 |
Data Required Time | 1.522 |
From | run_cnt_18_s0 |
To | run_cnt_18_s0 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 279 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD3 |
1.511 | 1.511 | tNET | RR | 1 | R12C15[0][A] | run_cnt_18_s0/CLK |
1.713 | 0.202 | tC2Q | RR | 1 | R12C15[0][A] | run_cnt_18_s0/Q |
1.714 | 0.001 | tNET | RR | 2 | R12C15[0][A] | n51_s/I1 |
1.946 | 0.232 | tINS | RF | 1 | R12C15[0][A] | n51_s/SUM |
1.946 | 0.000 | tNET | FF | 1 | R12C15[0][A] | run_cnt_18_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 279 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD3 |
1.511 | 1.511 | tNET | RR | 1 | R12C15[0][A] | run_cnt_18_s0/CLK |
1.522 | 0.011 | tHld | 1 | R12C15[0][A] | run_cnt_18_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.232, 53.306%; route: 0.001, 0.281%; tC2Q: 0.202, 46.413% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path10
Path Summary:
Slack | 0.424 |
Data Arrival Time | 1.946 |
Data Required Time | 1.522 |
From | run_cnt_20_s0 |
To | run_cnt_20_s0 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 279 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD3 |
1.511 | 1.511 | tNET | RR | 1 | R12C15[1][A] | run_cnt_20_s0/CLK |
1.713 | 0.202 | tC2Q | RR | 1 | R12C15[1][A] | run_cnt_20_s0/Q |
1.714 | 0.001 | tNET | RR | 2 | R12C15[1][A] | n49_s/I1 |
1.946 | 0.232 | tINS | RF | 1 | R12C15[1][A] | n49_s/SUM |
1.946 | 0.000 | tNET | FF | 1 | R12C15[1][A] | run_cnt_20_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 279 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD3 |
1.511 | 1.511 | tNET | RR | 1 | R12C15[1][A] | run_cnt_20_s0/CLK |
1.522 | 0.011 | tHld | 1 | R12C15[1][A] | run_cnt_20_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.232, 53.306%; route: 0.001, 0.281%; tC2Q: 0.202, 46.413% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path11
Path Summary:
Slack | 0.424 |
Data Arrival Time | 1.946 |
Data Required Time | 1.522 |
From | run_cnt_24_s0 |
To | run_cnt_24_s0 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 279 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD3 |
1.511 | 1.511 | tNET | RR | 1 | R12C16[0][A] | run_cnt_24_s0/CLK |
1.713 | 0.202 | tC2Q | RR | 1 | R12C16[0][A] | run_cnt_24_s0/Q |
1.714 | 0.001 | tNET | RR | 2 | R12C16[0][A] | n45_s/I1 |
1.946 | 0.232 | tINS | RF | 1 | R12C16[0][A] | n45_s/SUM |
1.946 | 0.000 | tNET | FF | 1 | R12C16[0][A] | run_cnt_24_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 279 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD3 |
1.511 | 1.511 | tNET | RR | 1 | R12C16[0][A] | run_cnt_24_s0/CLK |
1.522 | 0.011 | tHld | 1 | R12C16[0][A] | run_cnt_24_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.232, 53.306%; route: 0.001, 0.281%; tC2Q: 0.202, 46.413% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path12
Path Summary:
Slack | 0.425 |
Data Arrival Time | 1.948 |
Data Required Time | 1.522 |
From | u_p2b/u_p2b_0/loop_cnt_0_s0 |
To | u_p2b/u_p2b_0/loop_cnt_0_s0 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 279 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD3 |
1.511 | 1.511 | tNET | RR | 1 | R24C41[0][A] | u_p2b/u_p2b_0/loop_cnt_0_s0/CLK |
1.713 | 0.202 | tC2Q | RR | 3 | R24C41[0][A] | u_p2b/u_p2b_0/loop_cnt_0_s0/Q |
1.716 | 0.002 | tNET | RR | 1 | R24C41[0][A] | u_p2b/u_p2b_0/n81_s3/I0 |
1.948 | 0.232 | tINS | RF | 1 | R24C41[0][A] | u_p2b/u_p2b_0/n81_s3/F |
1.948 | 0.000 | tNET | FF | 1 | R24C41[0][A] | u_p2b/u_p2b_0/loop_cnt_0_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 279 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD3 |
1.511 | 1.511 | tNET | RR | 1 | R24C41[0][A] | u_p2b/u_p2b_0/loop_cnt_0_s0/CLK |
1.522 | 0.011 | tHld | 1 | R24C41[0][A] | u_p2b/u_p2b_0/loop_cnt_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path13
Path Summary:
Slack | 0.425 |
Data Arrival Time | 1.948 |
Data Required Time | 1.522 |
From | u_test_gen/Color_cnt_1_s3 |
To | u_test_gen/Color_cnt_1_s3 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 279 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD3 |
1.511 | 1.511 | tNET | RR | 1 | R16C37[0][A] | u_test_gen/Color_cnt_1_s3/CLK |
1.713 | 0.202 | tC2Q | RR | 4 | R16C37[0][A] | u_test_gen/Color_cnt_1_s3/Q |
1.716 | 0.002 | tNET | RR | 1 | R16C37[0][A] | u_test_gen/n685_s3/I2 |
1.948 | 0.232 | tINS | RF | 1 | R16C37[0][A] | u_test_gen/n685_s3/F |
1.948 | 0.000 | tNET | FF | 1 | R16C37[0][A] | u_test_gen/Color_cnt_1_s3/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 279 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD3 |
1.511 | 1.511 | tNET | RR | 1 | R16C37[0][A] | u_test_gen/Color_cnt_1_s3/CLK |
1.522 | 0.011 | tHld | 1 | R16C37[0][A] | u_test_gen/Color_cnt_1_s3 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path14
Path Summary:
Slack | 0.425 |
Data Arrival Time | 1.948 |
Data Required Time | 1.522 |
From | u_test_gen/Color_trig_num_7_s3 |
To | u_test_gen/Color_trig_num_7_s3 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 279 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD3 |
1.511 | 1.511 | tNET | RR | 1 | R14C39[1][A] | u_test_gen/Color_trig_num_7_s3/CLK |
1.713 | 0.202 | tC2Q | RR | 3 | R14C39[1][A] | u_test_gen/Color_trig_num_7_s3/Q |
1.716 | 0.002 | tNET | RR | 1 | R14C39[1][A] | u_test_gen/n608_s5/I2 |
1.948 | 0.232 | tINS | RF | 1 | R14C39[1][A] | u_test_gen/n608_s5/F |
1.948 | 0.000 | tNET | FF | 1 | R14C39[1][A] | u_test_gen/Color_trig_num_7_s3/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 279 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD3 |
1.511 | 1.511 | tNET | RR | 1 | R14C39[1][A] | u_test_gen/Color_trig_num_7_s3/CLK |
1.522 | 0.011 | tHld | 1 | R14C39[1][A] | u_test_gen/Color_trig_num_7_s3 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path15
Path Summary:
Slack | 0.425 |
Data Arrival Time | 1.948 |
Data Required Time | 1.522 |
From | u_test_gen/Color_cnt_3_s1 |
To | u_test_gen/Color_cnt_3_s1 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 279 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD3 |
1.511 | 1.511 | tNET | RR | 1 | R16C37[1][A] | u_test_gen/Color_cnt_3_s1/CLK |
1.713 | 0.202 | tC2Q | RR | 4 | R16C37[1][A] | u_test_gen/Color_cnt_3_s1/Q |
1.716 | 0.002 | tNET | RR | 1 | R16C37[1][A] | u_test_gen/n683_s1/I2 |
1.948 | 0.232 | tINS | RF | 1 | R16C37[1][A] | u_test_gen/n683_s1/F |
1.948 | 0.000 | tNET | FF | 1 | R16C37[1][A] | u_test_gen/Color_cnt_3_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 279 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD3 |
1.511 | 1.511 | tNET | RR | 1 | R16C37[1][A] | u_test_gen/Color_cnt_3_s1/CLK |
1.522 | 0.011 | tHld | 1 | R16C37[1][A] | u_test_gen/Color_cnt_3_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path16
Path Summary:
Slack | 0.425 |
Data Arrival Time | 1.948 |
Data Required Time | 1.522 |
From | u_test_gen/Color_trig_num_11_s1 |
To | u_test_gen/Color_trig_num_11_s1 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 279 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD3 |
1.511 | 1.511 | tNET | RR | 1 | R14C38[0][A] | u_test_gen/Color_trig_num_11_s1/CLK |
1.713 | 0.202 | tC2Q | RR | 2 | R14C38[0][A] | u_test_gen/Color_trig_num_11_s1/Q |
1.716 | 0.002 | tNET | RR | 1 | R14C38[0][A] | u_test_gen/n604_s1/I2 |
1.948 | 0.232 | tINS | RF | 1 | R14C38[0][A] | u_test_gen/n604_s1/F |
1.948 | 0.000 | tNET | FF | 1 | R14C38[0][A] | u_test_gen/Color_trig_num_11_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 279 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD3 |
1.511 | 1.511 | tNET | RR | 1 | R14C38[0][A] | u_test_gen/Color_trig_num_11_s1/CLK |
1.522 | 0.011 | tHld | 1 | R14C38[0][A] | u_test_gen/Color_trig_num_11_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path17
Path Summary:
Slack | 0.425 |
Data Arrival Time | 1.948 |
Data Required Time | 1.522 |
From | u_test_gen/De_vcnt_9_s1 |
To | u_test_gen/De_vcnt_9_s1 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 279 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD3 |
1.511 | 1.511 | tNET | RR | 1 | R21C39[0][A] | u_test_gen/De_vcnt_9_s1/CLK |
1.713 | 0.202 | tC2Q | RR | 3 | R21C39[0][A] | u_test_gen/De_vcnt_9_s1/Q |
1.716 | 0.002 | tNET | RR | 1 | R21C39[0][A] | u_test_gen/n550_s5/I2 |
1.948 | 0.232 | tINS | RF | 1 | R21C39[0][A] | u_test_gen/n550_s5/F |
1.948 | 0.000 | tNET | FF | 1 | R21C39[0][A] | u_test_gen/De_vcnt_9_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 279 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD3 |
1.511 | 1.511 | tNET | RR | 1 | R21C39[0][A] | u_test_gen/De_vcnt_9_s1/CLK |
1.522 | 0.011 | tHld | 1 | R21C39[0][A] | u_test_gen/De_vcnt_9_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path18
Path Summary:
Slack | 0.425 |
Data Arrival Time | 1.948 |
Data Required Time | 1.522 |
From | u_test_gen/De_hcnt_9_s1 |
To | u_test_gen/De_hcnt_9_s1 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 279 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD3 |
1.511 | 1.511 | tNET | RR | 1 | R14C37[1][A] | u_test_gen/De_hcnt_9_s1/CLK |
1.713 | 0.202 | tC2Q | RR | 4 | R14C37[1][A] | u_test_gen/De_hcnt_9_s1/Q |
1.716 | 0.002 | tNET | RR | 1 | R14C37[1][A] | u_test_gen/n496_s2/I3 |
1.948 | 0.232 | tINS | RF | 1 | R14C37[1][A] | u_test_gen/n496_s2/F |
1.948 | 0.000 | tNET | FF | 1 | R14C37[1][A] | u_test_gen/De_hcnt_9_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 279 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD3 |
1.511 | 1.511 | tNET | RR | 1 | R14C37[1][A] | u_test_gen/De_hcnt_9_s1/CLK |
1.522 | 0.011 | tHld | 1 | R14C37[1][A] | u_test_gen/De_hcnt_9_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path19
Path Summary:
Slack | 0.425 |
Data Arrival Time | 1.948 |
Data Required Time | 1.522 |
From | frame_led_s1 |
To | frame_led_s1 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 279 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD3 |
1.511 | 1.511 | tNET | RR | 1 | R16C11[0][A] | frame_led_s1/CLK |
1.713 | 0.202 | tC2Q | RR | 2 | R16C11[0][A] | frame_led_s1/Q |
1.716 | 0.002 | tNET | RR | 1 | R16C11[0][A] | n203_s2/I0 |
1.948 | 0.232 | tINS | RF | 1 | R16C11[0][A] | n203_s2/F |
1.948 | 0.000 | tNET | FF | 1 | R16C11[0][A] | frame_led_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 279 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD3 |
1.511 | 1.511 | tNET | RR | 1 | R16C11[0][A] | frame_led_s1/CLK |
1.522 | 0.011 | tHld | 1 | R16C11[0][A] | frame_led_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path20
Path Summary:
Slack | 0.425 |
Data Arrival Time | 1.948 |
Data Required Time | 1.522 |
From | vs_cnt_2_s0 |
To | vs_cnt_2_s0 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 279 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD3 |
1.511 | 1.511 | tNET | RR | 1 | R16C12[1][A] | vs_cnt_2_s0/CLK |
1.713 | 0.202 | tC2Q | RR | 2 | R16C12[1][A] | vs_cnt_2_s0/Q |
1.716 | 0.002 | tNET | RR | 2 | R16C12[1][A] | n144_s/I1 |
1.948 | 0.232 | tINS | RF | 1 | R16C12[1][A] | n144_s/SUM |
1.948 | 0.000 | tNET | FF | 1 | R16C12[1][A] | vs_cnt_2_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 279 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD3 |
1.511 | 1.511 | tNET | RR | 1 | R16C12[1][A] | vs_cnt_2_s0/CLK |
1.522 | 0.011 | tHld | 1 | R16C12[1][A] | vs_cnt_2_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Hold Analysis Report[2]:
Report Command:report_timing -hold -from_clock [get_clocks {byte_clk}] -max_paths 20 -max_common_paths 1
Path1
Path Summary:
Slack | 0.198 |
Data Arrival Time | 0.447 |
Data Required Time | 0.249 |
From | u_la0_top/u_ao_mem_ctrl/data_reg_110_s0 |
To | u_la0_top/u_ao_mem_ctrl/mem_mem_0_12_s |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R8C16[1][A] | u_la0_top/u_ao_mem_ctrl/data_reg_110_s0/CLK |
0.202 | 0.202 | tC2Q | RR | 1 | R8C16[1][A] | u_la0_top/u_ao_mem_ctrl/data_reg_110_s0/Q |
0.447 | 0.245 | tNET | RR | 1 | BSRAM_R10[4] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_12_s/DI[2] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | BSRAM_R10[4] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_12_s/CLKA |
0.249 | 0.249 | tHld | 1 | BSRAM_R10[4] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_12_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.245, 54.832%; tC2Q: 0.202, 45.168% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path2
Path Summary:
Slack | 0.213 |
Data Arrival Time | 0.462 |
Data Required Time | 0.249 |
From | u_la0_top/u_ao_mem_ctrl/data_reg_114_s0 |
To | u_la0_top/u_ao_mem_ctrl/mem_mem_0_12_s |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R9C15[2][B] | u_la0_top/u_ao_mem_ctrl/data_reg_114_s0/CLK |
0.202 | 0.202 | tC2Q | RR | 1 | R9C15[2][B] | u_la0_top/u_ao_mem_ctrl/data_reg_114_s0/Q |
0.462 | 0.260 | tNET | RR | 1 | BSRAM_R10[4] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_12_s/DI[6] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | BSRAM_R10[4] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_12_s/CLKA |
0.249 | 0.249 | tHld | 1 | BSRAM_R10[4] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_12_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path3
Path Summary:
Slack | 0.213 |
Data Arrival Time | 0.462 |
Data Required Time | 0.249 |
From | u_la0_top/u_ao_mem_ctrl/data_reg_113_s0 |
To | u_la0_top/u_ao_mem_ctrl/mem_mem_0_12_s |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R8C16[2][B] | u_la0_top/u_ao_mem_ctrl/data_reg_113_s0/CLK |
0.202 | 0.202 | tC2Q | RR | 1 | R8C16[2][B] | u_la0_top/u_ao_mem_ctrl/data_reg_113_s0/Q |
0.462 | 0.260 | tNET | RR | 1 | BSRAM_R10[4] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_12_s/DI[5] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | BSRAM_R10[4] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_12_s/CLKA |
0.249 | 0.249 | tHld | 1 | BSRAM_R10[4] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_12_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path4
Path Summary:
Slack | 0.213 |
Data Arrival Time | 0.462 |
Data Required Time | 0.249 |
From | u_la0_top/u_ao_mem_ctrl/data_reg_112_s0 |
To | u_la0_top/u_ao_mem_ctrl/mem_mem_0_12_s |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R8C16[2][A] | u_la0_top/u_ao_mem_ctrl/data_reg_112_s0/CLK |
0.202 | 0.202 | tC2Q | RR | 1 | R8C16[2][A] | u_la0_top/u_ao_mem_ctrl/data_reg_112_s0/Q |
0.462 | 0.260 | tNET | RR | 1 | BSRAM_R10[4] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_12_s/DI[4] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | BSRAM_R10[4] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_12_s/CLKA |
0.249 | 0.249 | tHld | 1 | BSRAM_R10[4] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_12_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path5
Path Summary:
Slack | 0.213 |
Data Arrival Time | 0.462 |
Data Required Time | 0.249 |
From | u_la0_top/u_ao_mem_ctrl/data_reg_36_s0 |
To | u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R12C9[0][B] | u_la0_top/u_ao_mem_ctrl/data_reg_36_s0/CLK |
0.202 | 0.202 | tC2Q | RR | 1 | R12C9[0][B] | u_la0_top/u_ao_mem_ctrl/data_reg_36_s0/Q |
0.462 | 0.260 | tNET | RR | 1 | BSRAM_R10[1] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/DI[0] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | BSRAM_R10[1] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CLKA |
0.249 | 0.249 | tHld | 1 | BSRAM_R10[1] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path6
Path Summary:
Slack | 0.213 |
Data Arrival Time | 0.462 |
Data Required Time | 0.249 |
From | u_la0_top/u_ao_mem_ctrl/data_reg_9_s0 |
To | u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R9C6[1][A] | u_la0_top/u_ao_mem_ctrl/data_reg_9_s0/CLK |
0.202 | 0.202 | tC2Q | RR | 1 | R9C6[1][A] | u_la0_top/u_ao_mem_ctrl/data_reg_9_s0/Q |
0.462 | 0.260 | tNET | RR | 1 | BSRAM_R10[0] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[0] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | BSRAM_R10[0] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA |
0.249 | 0.249 | tHld | 1 | BSRAM_R10[0] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path7
Path Summary:
Slack | 0.225 |
Data Arrival Time | 0.474 |
Data Required Time | 0.249 |
From | u_la0_top/u_ao_mem_ctrl/data_reg_97_s0 |
To | u_la0_top/u_ao_mem_ctrl/mem_mem_0_10_s |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R8C10[2][A] | u_la0_top/u_ao_mem_ctrl/data_reg_97_s0/CLK |
0.202 | 0.202 | tC2Q | RR | 1 | R8C10[2][A] | u_la0_top/u_ao_mem_ctrl/data_reg_97_s0/Q |
0.474 | 0.272 | tNET | RR | 1 | BSRAM_R10[3] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_10_s/DI[7] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | BSRAM_R10[3] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_10_s/CLKA |
0.249 | 0.249 | tHld | 1 | BSRAM_R10[3] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_10_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.272, 57.427%; tC2Q: 0.202, 42.573% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path8
Path Summary:
Slack | 0.307 |
Data Arrival Time | 0.318 |
Data Required Time | 0.011 |
From | u_la0_top/u_ao_mem_ctrl/data_reg_dly_69_s0 |
To | u_la0_top/u_ao_mem_ctrl/data_reg_69_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R4C13[1][A] | u_la0_top/u_ao_mem_ctrl/data_reg_dly_69_s0/CLK |
0.201 | 0.201 | tC2Q | RF | 1 | R4C13[1][A] | u_la0_top/u_ao_mem_ctrl/data_reg_dly_69_s0/Q |
0.318 | 0.117 | tNET | FF | 1 | R4C13[0][A] | u_la0_top/u_ao_mem_ctrl/data_reg_69_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R4C13[0][A] | u_la0_top/u_ao_mem_ctrl/data_reg_69_s0/CLK |
0.011 | 0.011 | tHld | 1 | R4C13[0][A] | u_la0_top/u_ao_mem_ctrl/data_reg_69_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.117, 36.787%; tC2Q: 0.201, 63.213% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path9
Path Summary:
Slack | 0.307 |
Data Arrival Time | 0.318 |
Data Required Time | 0.011 |
From | u_la0_top/u_ao_mem_ctrl/data_reg_dly_86_s0 |
To | u_la0_top/u_ao_mem_ctrl/data_reg_86_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R7C10[1][B] | u_la0_top/u_ao_mem_ctrl/data_reg_dly_86_s0/CLK |
0.201 | 0.201 | tC2Q | RF | 1 | R7C10[1][B] | u_la0_top/u_ao_mem_ctrl/data_reg_dly_86_s0/Q |
0.318 | 0.117 | tNET | FF | 1 | R7C10[1][A] | u_la0_top/u_ao_mem_ctrl/data_reg_86_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R7C10[1][A] | u_la0_top/u_ao_mem_ctrl/data_reg_86_s0/CLK |
0.011 | 0.011 | tHld | 1 | R7C10[1][A] | u_la0_top/u_ao_mem_ctrl/data_reg_86_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.117, 36.787%; tC2Q: 0.201, 63.213% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path10
Path Summary:
Slack | 0.307 |
Data Arrival Time | 0.318 |
Data Required Time | 0.011 |
From | u_la0_top/u_ao_mem_ctrl/data_reg_dly_97_s0 |
To | u_la0_top/u_ao_mem_ctrl/data_reg_97_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R8C10[0][A] | u_la0_top/u_ao_mem_ctrl/data_reg_dly_97_s0/CLK |
0.201 | 0.201 | tC2Q | RF | 1 | R8C10[0][A] | u_la0_top/u_ao_mem_ctrl/data_reg_dly_97_s0/Q |
0.318 | 0.117 | tNET | FF | 1 | R8C10[2][A] | u_la0_top/u_ao_mem_ctrl/data_reg_97_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R8C10[2][A] | u_la0_top/u_ao_mem_ctrl/data_reg_97_s0/CLK |
0.011 | 0.011 | tHld | 1 | R8C10[2][A] | u_la0_top/u_ao_mem_ctrl/data_reg_97_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.117, 36.787%; tC2Q: 0.201, 63.213% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path11
Path Summary:
Slack | 0.307 |
Data Arrival Time | 0.318 |
Data Required Time | 0.011 |
From | u_la0_top/rst_ao_syn_s0 |
To | u_la0_top/rst_ao_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R9C3[2][A] | u_la0_top/rst_ao_syn_s0/CLK |
0.201 | 0.201 | tC2Q | RF | 1 | R9C3[2][A] | u_la0_top/rst_ao_syn_s0/Q |
0.318 | 0.117 | tNET | FF | 1 | R9C3[2][B] | u_la0_top/rst_ao_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R9C3[2][B] | u_la0_top/rst_ao_s0/CLK |
0.011 | 0.011 | tHld | 1 | R9C3[2][B] | u_la0_top/rst_ao_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.117, 36.787%; tC2Q: 0.201, 63.213% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path12
Path Summary:
Slack | 0.318 |
Data Arrival Time | 1.840 |
Data Required Time | 1.522 |
From | u_p2b/u_p2b_0/u_mid_buf/rRstRsync_s0 |
To | u_p2b/u_p2b_0/u_mid_buf/rRdRst_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
1.511 | 1.511 | tNET | RR | 1 | R20C43[0][B] | u_p2b/u_p2b_0/u_mid_buf/rRstRsync_s0/CLK |
1.713 | 0.202 | tC2Q | RR | 1 | R20C43[0][B] | u_p2b/u_p2b_0/u_mid_buf/rRstRsync_s0/Q |
1.840 | 0.127 | tNET | RR | 1 | R20C43[1][A] | u_p2b/u_p2b_0/u_mid_buf/rRdRst_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
1.511 | 1.511 | tNET | RR | 1 | R20C43[1][A] | u_p2b/u_p2b_0/u_mid_buf/rRdRst_s0/CLK |
1.522 | 0.011 | tHld | 1 | R20C43[1][A] | u_p2b/u_p2b_0/u_mid_buf/rRdRst_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.127, 38.638%; tC2Q: 0.202, 61.362% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path13
Path Summary:
Slack | 0.320 |
Data Arrival Time | 1.843 |
Data Required Time | 1.523 |
From | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/rWrOffset_1_s1 |
To | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mSsram_mSsram_1_0_s |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
1.511 | 1.511 | tNET | RR | 1 | R14C18[0][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/rWrOffset_1_s1/CLK |
1.713 | 0.202 | tC2Q | RR | 7 | R14C18[0][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/rWrOffset_1_s1/Q |
1.843 | 0.130 | tNET | RR | 1 | R14C16 | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mSsram_mSsram_1_0_s/WAD[1] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
1.511 | 1.511 | tNET | RR | 1 | R14C16 | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mSsram_mSsram_1_0_s/CLK |
1.523 | 0.012 | tHld | 1 | R14C16 | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mSsram_mSsram_1_0_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.130, 39.136%; tC2Q: 0.202, 60.864% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path14
Path Summary:
Slack | 0.324 |
Data Arrival Time | 1.847 |
Data Required Time | 1.523 |
From | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/rWrOffset_2_s1 |
To | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mSsram_mSsram_1_0_s |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
1.511 | 1.511 | tNET | RR | 1 | R13C16[0][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/rWrOffset_2_s1/CLK |
1.712 | 0.201 | tC2Q | RF | 6 | R13C16[0][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/rWrOffset_2_s1/Q |
1.847 | 0.135 | tNET | FF | 1 | R14C16 | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mSsram_mSsram_1_0_s/WAD[2] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
1.511 | 1.511 | tNET | RR | 1 | R14C16 | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mSsram_mSsram_1_0_s/CLK |
1.523 | 0.012 | tHld | 1 | R14C16 | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mSsram_mSsram_1_0_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.135, 40.180%; tC2Q: 0.201, 59.820% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path15
Path Summary:
Slack | 0.324 |
Data Arrival Time | 0.573 |
Data Required Time | 0.249 |
From | u_la0_top/u_ao_mem_ctrl/data_reg_71_s0 |
To | u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R6C11[0][A] | u_la0_top/u_ao_mem_ctrl/data_reg_71_s0/CLK |
0.202 | 0.202 | tC2Q | RR | 1 | R6C11[0][A] | u_la0_top/u_ao_mem_ctrl/data_reg_71_s0/Q |
0.573 | 0.371 | tNET | RR | 1 | BSRAM_R10[2] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s/DI[8] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | BSRAM_R10[2] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s/CLKA |
0.249 | 0.249 | tHld | 1 | BSRAM_R10[2] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.371, 64.759%; tC2Q: 0.202, 35.241% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path16
Path Summary:
Slack | 0.325 |
Data Arrival Time | 1.849 |
Data Required Time | 1.523 |
From | u_dsi_tx/u_tx/u_dsi_tx/rCtrl_14_s0 |
To | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mSsram_mSsram_0_1_s |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
1.511 | 1.511 | tNET | RR | 1 | R13C15[1][A] | u_dsi_tx/u_tx/u_dsi_tx/rCtrl_14_s0/CLK |
1.712 | 0.201 | tC2Q | RF | 4 | R13C15[1][A] | u_dsi_tx/u_tx/u_dsi_tx/rCtrl_14_s0/Q |
1.849 | 0.136 | tNET | FF | 1 | R14C15 | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mSsram_mSsram_0_1_s/DI[2] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
1.511 | 1.511 | tNET | RR | 1 | R14C15 | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mSsram_mSsram_0_1_s/CLK |
1.523 | 0.012 | tHld | 1 | R14C15 | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mSsram_mSsram_0_1_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.136, 40.429%; tC2Q: 0.201, 59.571% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path17
Path Summary:
Slack | 0.326 |
Data Arrival Time | 1.850 |
Data Required Time | 1.523 |
From | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/rWrOffset_1_s1 |
To | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mSsram_mSsram_1_1_s |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
1.511 | 1.511 | tNET | RR | 1 | R14C18[0][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/rWrOffset_1_s1/CLK |
1.712 | 0.201 | tC2Q | RF | 7 | R14C18[0][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/rWrOffset_1_s1/Q |
1.850 | 0.137 | tNET | FF | 1 | R14C17 | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mSsram_mSsram_1_1_s/WAD[1] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
1.511 | 1.511 | tNET | RR | 1 | R14C17 | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mSsram_mSsram_1_1_s/CLK |
1.523 | 0.012 | tHld | 1 | R14C17 | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mSsram_mSsram_1_1_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.137, 40.594%; tC2Q: 0.201, 59.406% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path18
Path Summary:
Slack | 0.326 |
Data Arrival Time | 1.850 |
Data Required Time | 1.523 |
From | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/rWrOffset_3_s1 |
To | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mSsram_mSsram_1_0_s |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
1.511 | 1.511 | tNET | RR | 1 | R13C16[1][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/rWrOffset_3_s1/CLK |
1.712 | 0.201 | tC2Q | RF | 6 | R13C16[1][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/rWrOffset_3_s1/Q |
1.850 | 0.137 | tNET | FF | 1 | R14C16 | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mSsram_mSsram_1_0_s/WAD[3] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
1.511 | 1.511 | tNET | RR | 1 | R14C16 | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mSsram_mSsram_1_0_s/CLK |
1.523 | 0.012 | tHld | 1 | R14C16 | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mSsram_mSsram_1_0_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.137, 40.594%; tC2Q: 0.201, 59.406% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path19
Path Summary:
Slack | 0.330 |
Data Arrival Time | 1.853 |
Data Required Time | 1.523 |
From | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/rWrOffset_0_s1 |
To | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mSsram_mSsram_1_1_s |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
1.511 | 1.511 | tNET | RR | 1 | R14C18[1][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/rWrOffset_0_s1/CLK |
1.712 | 0.201 | tC2Q | RF | 8 | R14C18[1][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/rWrOffset_0_s1/Q |
1.853 | 0.141 | tNET | FF | 1 | R14C17 | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mSsram_mSsram_1_1_s/WAD[0] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
1.511 | 1.511 | tNET | RR | 1 | R14C17 | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mSsram_mSsram_1_1_s/CLK |
1.523 | 0.012 | tHld | 1 | R14C17 | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mSsram_mSsram_1_1_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.141, 41.164%; tC2Q: 0.201, 58.836% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path20
Path Summary:
Slack | 0.335 |
Data Arrival Time | 0.584 |
Data Required Time | 0.249 |
From | u_la0_top/u_ao_mem_ctrl/data_reg_116_s0 |
To | u_la0_top/u_ao_mem_ctrl/mem_mem_0_12_s |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R11C14[1][A] | u_la0_top/u_ao_mem_ctrl/data_reg_116_s0/CLK |
0.202 | 0.202 | tC2Q | RR | 1 | R11C14[1][A] | u_la0_top/u_ao_mem_ctrl/data_reg_116_s0/Q |
0.584 | 0.382 | tNET | RR | 1 | BSRAM_R10[4] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_12_s/DI[8] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | BSRAM_R10[4] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_12_s/CLKA |
0.249 | 0.249 | tHld | 1 | BSRAM_R10[4] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_12_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.382, 65.434%; tC2Q: 0.202, 34.566% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Recovery Analysis Report
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 7.875 |
Data Arrival Time | 1.502 |
Data Required Time | 9.377 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_match_3/match_cnt_3_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R9C3[2][B] | u_la0_top/rst_ao_s0/CLK |
0.232 | 0.232 | tC2Q | RF | 95 | R9C3[2][B] | u_la0_top/rst_ao_s0/Q |
1.502 | 1.270 | tNET | FF | 1 | R2C15[0][A] | u_la0_top/u_ao_match_3/match_cnt_3_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
9.412 | 0.000 | tNET | RR | 1 | R2C15[0][A] | u_la0_top/u_ao_match_3/match_cnt_3_s1/CLK |
9.377 | -0.035 | tSu | 1 | R2C15[0][A] | u_la0_top/u_ao_match_3/match_cnt_3_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 9.412 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.270, 84.554%; tC2Q: 0.232, 15.446% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path2
Path Summary:
Slack | 7.875 |
Data Arrival Time | 1.502 |
Data Required Time | 9.377 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_match_0/matched_s7 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R9C3[2][B] | u_la0_top/rst_ao_s0/CLK |
0.232 | 0.232 | tC2Q | RF | 95 | R9C3[2][B] | u_la0_top/rst_ao_s0/Q |
1.502 | 1.270 | tNET | FF | 1 | R2C15[1][A] | u_la0_top/u_ao_match_0/matched_s7/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
9.412 | 0.000 | tNET | RR | 1 | R2C15[1][A] | u_la0_top/u_ao_match_0/matched_s7/CLK |
9.377 | -0.035 | tSu | 1 | R2C15[1][A] | u_la0_top/u_ao_match_0/matched_s7 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 9.412 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.270, 84.554%; tC2Q: 0.232, 15.446% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path3
Path Summary:
Slack | 7.875 |
Data Arrival Time | 1.502 |
Data Required Time | 9.377 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_match_0/match_cnt_3_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R9C3[2][B] | u_la0_top/rst_ao_s0/CLK |
0.232 | 0.232 | tC2Q | RF | 95 | R9C3[2][B] | u_la0_top/rst_ao_s0/Q |
1.502 | 1.270 | tNET | FF | 1 | R2C15[2][A] | u_la0_top/u_ao_match_0/match_cnt_3_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
9.412 | 0.000 | tNET | RR | 1 | R2C15[2][A] | u_la0_top/u_ao_match_0/match_cnt_3_s1/CLK |
9.377 | -0.035 | tSu | 1 | R2C15[2][A] | u_la0_top/u_ao_match_0/match_cnt_3_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 9.412 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.270, 84.554%; tC2Q: 0.232, 15.446% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path4
Path Summary:
Slack | 7.898 |
Data Arrival Time | 1.479 |
Data Required Time | 9.377 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/capture_end_dly_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R9C3[2][B] | u_la0_top/rst_ao_s0/CLK |
0.232 | 0.232 | tC2Q | RF | 95 | R9C3[2][B] | u_la0_top/rst_ao_s0/Q |
1.479 | 1.247 | tNET | FF | 1 | R3C14[0][B] | u_la0_top/capture_end_dly_s0/PRESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
9.412 | 0.000 | tNET | RR | 1 | R3C14[0][B] | u_la0_top/capture_end_dly_s0/CLK |
9.377 | -0.035 | tSu | 1 | R3C14[0][B] | u_la0_top/capture_end_dly_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 9.412 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.247, 84.316%; tC2Q: 0.232, 15.684% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path5
Path Summary:
Slack | 7.914 |
Data Arrival Time | 1.463 |
Data Required Time | 9.377 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/start_reg_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R9C3[2][B] | u_la0_top/rst_ao_s0/CLK |
0.232 | 0.232 | tC2Q | RF | 95 | R9C3[2][B] | u_la0_top/rst_ao_s0/Q |
1.463 | 1.231 | tNET | FF | 1 | R3C13[1][A] | u_la0_top/start_reg_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
9.412 | 0.000 | tNET | RR | 1 | R3C13[1][A] | u_la0_top/start_reg_s0/CLK |
9.377 | -0.035 | tSu | 1 | R3C13[1][A] | u_la0_top/start_reg_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 9.412 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.231, 84.142%; tC2Q: 0.232, 15.858% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path6
Path Summary:
Slack | 8.020 |
Data Arrival Time | 1.357 |
Data Required Time | 9.377 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R9C3[2][B] | u_la0_top/rst_ao_s0/CLK |
0.232 | 0.232 | tC2Q | RF | 95 | R9C3[2][B] | u_la0_top/rst_ao_s0/Q |
1.357 | 1.125 | tNET | FF | 1 | R7C8[0][A] | u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
9.412 | 0.000 | tNET | RR | 1 | R7C8[0][A] | u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLK |
9.377 | -0.035 | tSu | 1 | R7C8[0][A] | u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 9.412 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.125, 82.900%; tC2Q: 0.232, 17.100% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path7
Path Summary:
Slack | 8.115 |
Data Arrival Time | 1.262 |
Data Required Time | 9.377 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_match_0/match_cnt_5_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R9C3[2][B] | u_la0_top/rst_ao_s0/CLK |
0.232 | 0.232 | tC2Q | RF | 95 | R9C3[2][B] | u_la0_top/rst_ao_s0/Q |
1.262 | 1.030 | tNET | FF | 1 | R12C6[0][A] | u_la0_top/u_ao_match_0/match_cnt_5_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
9.412 | 0.000 | tNET | RR | 1 | R12C6[0][A] | u_la0_top/u_ao_match_0/match_cnt_5_s1/CLK |
9.377 | -0.035 | tSu | 1 | R12C6[0][A] | u_la0_top/u_ao_match_0/match_cnt_5_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 9.412 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.030, 81.616%; tC2Q: 0.232, 18.384% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path8
Path Summary:
Slack | 8.141 |
Data Arrival Time | 1.236 |
Data Required Time | 9.377 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_match_4/match_bitwise_pre_reg_0_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R9C3[2][B] | u_la0_top/rst_ao_s0/CLK |
0.232 | 0.232 | tC2Q | RF | 95 | R9C3[2][B] | u_la0_top/rst_ao_s0/Q |
1.236 | 1.004 | tNET | FF | 1 | R4C12[2][A] | u_la0_top/u_ao_match_4/match_bitwise_pre_reg_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
9.412 | 0.000 | tNET | RR | 1 | R4C12[2][A] | u_la0_top/u_ao_match_4/match_bitwise_pre_reg_0_s0/CLK |
9.377 | -0.035 | tSu | 1 | R4C12[2][A] | u_la0_top/u_ao_match_4/match_bitwise_pre_reg_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 9.412 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.004, 81.228%; tC2Q: 0.232, 18.772% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path9
Path Summary:
Slack | 8.141 |
Data Arrival Time | 1.236 |
Data Required Time | 9.377 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_match_0/match_cnt_0_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R9C3[2][B] | u_la0_top/rst_ao_s0/CLK |
0.232 | 0.232 | tC2Q | RF | 95 | R9C3[2][B] | u_la0_top/rst_ao_s0/Q |
1.236 | 1.004 | tNET | FF | 1 | R6C10[0][A] | u_la0_top/u_ao_match_0/match_cnt_0_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
9.412 | 0.000 | tNET | RR | 1 | R6C10[0][A] | u_la0_top/u_ao_match_0/match_cnt_0_s1/CLK |
9.377 | -0.035 | tSu | 1 | R6C10[0][A] | u_la0_top/u_ao_match_0/match_cnt_0_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 9.412 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.004, 81.228%; tC2Q: 0.232, 18.772% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path10
Path Summary:
Slack | 8.141 |
Data Arrival Time | 1.236 |
Data Required Time | 9.377 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_match_0/match_cnt_2_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R9C3[2][B] | u_la0_top/rst_ao_s0/CLK |
0.232 | 0.232 | tC2Q | RF | 95 | R9C3[2][B] | u_la0_top/rst_ao_s0/Q |
1.236 | 1.004 | tNET | FF | 1 | R4C12[1][A] | u_la0_top/u_ao_match_0/match_cnt_2_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
9.412 | 0.000 | tNET | RR | 1 | R4C12[1][A] | u_la0_top/u_ao_match_0/match_cnt_2_s1/CLK |
9.377 | -0.035 | tSu | 1 | R4C12[1][A] | u_la0_top/u_ao_match_0/match_cnt_2_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 9.412 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.004, 81.228%; tC2Q: 0.232, 18.772% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path11
Path Summary:
Slack | 8.141 |
Data Arrival Time | 1.236 |
Data Required Time | 9.377 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_match_0/trig_dly_0_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R9C3[2][B] | u_la0_top/rst_ao_s0/CLK |
0.232 | 0.232 | tC2Q | RF | 95 | R9C3[2][B] | u_la0_top/rst_ao_s0/Q |
1.236 | 1.004 | tNET | FF | 1 | R6C10[2][A] | u_la0_top/u_ao_match_0/trig_dly_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
9.412 | 0.000 | tNET | RR | 1 | R6C10[2][A] | u_la0_top/u_ao_match_0/trig_dly_0_s0/CLK |
9.377 | -0.035 | tSu | 1 | R6C10[2][A] | u_la0_top/u_ao_match_0/trig_dly_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 9.412 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.004, 81.228%; tC2Q: 0.232, 18.772% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path12
Path Summary:
Slack | 8.141 |
Data Arrival Time | 1.236 |
Data Required Time | 9.377 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/internal_reg_force_triger_syn_1_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R9C3[2][B] | u_la0_top/rst_ao_s0/CLK |
0.232 | 0.232 | tC2Q | RF | 95 | R9C3[2][B] | u_la0_top/rst_ao_s0/Q |
1.236 | 1.004 | tNET | FF | 1 | R6C10[2][B] | u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
9.412 | 0.000 | tNET | RR | 1 | R6C10[2][B] | u_la0_top/internal_reg_force_triger_syn_1_s0/CLK |
9.377 | -0.035 | tSu | 1 | R6C10[2][B] | u_la0_top/internal_reg_force_triger_syn_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 9.412 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.004, 81.228%; tC2Q: 0.232, 18.772% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path13
Path Summary:
Slack | 8.142 |
Data Arrival Time | 1.235 |
Data Required Time | 9.377 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R9C3[2][B] | u_la0_top/rst_ao_s0/CLK |
0.232 | 0.232 | tC2Q | RF | 95 | R9C3[2][B] | u_la0_top/rst_ao_s0/Q |
1.235 | 1.003 | tNET | FF | 1 | R16C8[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
9.412 | 0.000 | tNET | RR | 1 | R16C8[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK |
9.377 | -0.035 | tSu | 1 | R16C8[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 9.412 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.003, 81.215%; tC2Q: 0.232, 18.785% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path14
Path Summary:
Slack | 8.147 |
Data Arrival Time | 1.230 |
Data Required Time | 9.377 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/internal_reg_start_dly_0_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R9C3[2][B] | u_la0_top/rst_ao_s0/CLK |
0.232 | 0.232 | tC2Q | RF | 95 | R9C3[2][B] | u_la0_top/rst_ao_s0/Q |
1.230 | 0.998 | tNET | FF | 1 | R4C13[2][A] | u_la0_top/internal_reg_start_dly_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
9.412 | 0.000 | tNET | RR | 1 | R4C13[2][A] | u_la0_top/internal_reg_start_dly_0_s0/CLK |
9.377 | -0.035 | tSu | 1 | R4C13[2][A] | u_la0_top/internal_reg_start_dly_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 9.412 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.998, 81.141%; tC2Q: 0.232, 18.859% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path15
Path Summary:
Slack | 8.147 |
Data Arrival Time | 1.230 |
Data Required Time | 9.377 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/internal_reg_start_syn_1_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R9C3[2][B] | u_la0_top/rst_ao_s0/CLK |
0.232 | 0.232 | tC2Q | RF | 95 | R9C3[2][B] | u_la0_top/rst_ao_s0/Q |
1.230 | 0.998 | tNET | FF | 1 | R4C13[2][B] | u_la0_top/internal_reg_start_syn_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
9.412 | 0.000 | tNET | RR | 1 | R4C13[2][B] | u_la0_top/internal_reg_start_syn_1_s0/CLK |
9.377 | -0.035 | tSu | 1 | R4C13[2][B] | u_la0_top/internal_reg_start_syn_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 9.412 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.998, 81.141%; tC2Q: 0.232, 18.859% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path16
Path Summary:
Slack | 8.148 |
Data Arrival Time | 1.229 |
Data Required Time | 9.377 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_match_4/match_sep_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R9C3[2][B] | u_la0_top/rst_ao_s0/CLK |
0.232 | 0.232 | tC2Q | RF | 95 | R9C3[2][B] | u_la0_top/rst_ao_s0/Q |
1.229 | 0.997 | tNET | FF | 1 | R5C12[1][A] | u_la0_top/u_ao_match_4/match_sep_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
9.412 | 0.000 | tNET | RR | 1 | R5C12[1][A] | u_la0_top/u_ao_match_4/match_sep_s0/CLK |
9.377 | -0.035 | tSu | 1 | R5C12[1][A] | u_la0_top/u_ao_match_4/match_sep_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 9.412 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.997, 81.120%; tC2Q: 0.232, 18.880% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path17
Path Summary:
Slack | 8.148 |
Data Arrival Time | 1.229 |
Data Required Time | 9.377 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_match_3/matched_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R9C3[2][B] | u_la0_top/rst_ao_s0/CLK |
0.232 | 0.232 | tC2Q | RF | 95 | R9C3[2][B] | u_la0_top/rst_ao_s0/Q |
1.229 | 0.997 | tNET | FF | 1 | R5C12[0][A] | u_la0_top/u_ao_match_3/matched_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
9.412 | 0.000 | tNET | RR | 1 | R5C12[0][A] | u_la0_top/u_ao_match_3/matched_s1/CLK |
9.377 | -0.035 | tSu | 1 | R5C12[0][A] | u_la0_top/u_ao_match_3/matched_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 9.412 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.997, 81.120%; tC2Q: 0.232, 18.880% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path18
Path Summary:
Slack | 8.148 |
Data Arrival Time | 1.229 |
Data Required Time | 9.377 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_match_2/match_sep_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R9C3[2][B] | u_la0_top/rst_ao_s0/CLK |
0.232 | 0.232 | tC2Q | RF | 95 | R9C3[2][B] | u_la0_top/rst_ao_s0/Q |
1.229 | 0.997 | tNET | FF | 1 | R5C12[1][B] | u_la0_top/u_ao_match_2/match_sep_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
9.412 | 0.000 | tNET | RR | 1 | R5C12[1][B] | u_la0_top/u_ao_match_2/match_sep_s0/CLK |
9.377 | -0.035 | tSu | 1 | R5C12[1][B] | u_la0_top/u_ao_match_2/match_sep_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 9.412 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.997, 81.120%; tC2Q: 0.232, 18.880% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path19
Path Summary:
Slack | 8.148 |
Data Arrival Time | 1.229 |
Data Required Time | 9.377 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_match_1/match_sep_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R9C3[2][B] | u_la0_top/rst_ao_s0/CLK |
0.232 | 0.232 | tC2Q | RF | 95 | R9C3[2][B] | u_la0_top/rst_ao_s0/Q |
1.229 | 0.997 | tNET | FF | 1 | R5C12[2][A] | u_la0_top/u_ao_match_1/match_sep_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
9.412 | 0.000 | tNET | RR | 1 | R5C12[2][A] | u_la0_top/u_ao_match_1/match_sep_s0/CLK |
9.377 | -0.035 | tSu | 1 | R5C12[2][A] | u_la0_top/u_ao_match_1/match_sep_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 9.412 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.997, 81.120%; tC2Q: 0.232, 18.880% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path20
Path Summary:
Slack | 8.148 |
Data Arrival Time | 1.229 |
Data Required Time | 9.377 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_match_0/match_sep_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R9C3[2][B] | u_la0_top/rst_ao_s0/CLK |
0.232 | 0.232 | tC2Q | RF | 95 | R9C3[2][B] | u_la0_top/rst_ao_s0/Q |
1.229 | 0.997 | tNET | FF | 1 | R5C12[2][B] | u_la0_top/u_ao_match_0/match_sep_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
9.412 | 0.000 | tNET | RR | 1 | R5C12[2][B] | u_la0_top/u_ao_match_0/match_sep_s0/CLK |
9.377 | -0.035 | tSu | 1 | R5C12[2][B] | u_la0_top/u_ao_match_0/match_sep_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 9.412 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.997, 81.120%; tC2Q: 0.232, 18.880% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path21
Path Summary:
Slack | 8.154 |
Data Arrival Time | 1.223 |
Data Required Time | 9.377 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_match_4/trig_dly_in_0_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R9C3[2][B] | u_la0_top/rst_ao_s0/CLK |
0.232 | 0.232 | tC2Q | RF | 95 | R9C3[2][B] | u_la0_top/rst_ao_s0/Q |
1.223 | 0.991 | tNET | FF | 1 | R9C16[1][A] | u_la0_top/u_ao_match_4/trig_dly_in_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
9.412 | 0.000 | tNET | RR | 1 | R9C16[1][A] | u_la0_top/u_ao_match_4/trig_dly_in_0_s0/CLK |
9.377 | -0.035 | tSu | 1 | R9C16[1][A] | u_la0_top/u_ao_match_4/trig_dly_in_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 9.412 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.991, 81.032%; tC2Q: 0.232, 18.968% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path22
Path Summary:
Slack | 8.154 |
Data Arrival Time | 1.223 |
Data Required Time | 9.377 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_match_3/trig_dly_in_0_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R9C3[2][B] | u_la0_top/rst_ao_s0/CLK |
0.232 | 0.232 | tC2Q | RF | 95 | R9C3[2][B] | u_la0_top/rst_ao_s0/Q |
1.223 | 0.991 | tNET | FF | 1 | R9C16[1][B] | u_la0_top/u_ao_match_3/trig_dly_in_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
9.412 | 0.000 | tNET | RR | 1 | R9C16[1][B] | u_la0_top/u_ao_match_3/trig_dly_in_0_s0/CLK |
9.377 | -0.035 | tSu | 1 | R9C16[1][B] | u_la0_top/u_ao_match_3/trig_dly_in_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 9.412 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.991, 81.032%; tC2Q: 0.232, 18.968% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path23
Path Summary:
Slack | 8.154 |
Data Arrival Time | 1.223 |
Data Required Time | 9.377 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_match_3/trig_dly_in_1_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R9C3[2][B] | u_la0_top/rst_ao_s0/CLK |
0.232 | 0.232 | tC2Q | RF | 95 | R9C3[2][B] | u_la0_top/rst_ao_s0/Q |
1.223 | 0.991 | tNET | FF | 1 | R9C16[2][A] | u_la0_top/u_ao_match_3/trig_dly_in_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
9.412 | 0.000 | tNET | RR | 1 | R9C16[2][A] | u_la0_top/u_ao_match_3/trig_dly_in_1_s0/CLK |
9.377 | -0.035 | tSu | 1 | R9C16[2][A] | u_la0_top/u_ao_match_3/trig_dly_in_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 9.412 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.991, 81.032%; tC2Q: 0.232, 18.968% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path24
Path Summary:
Slack | 8.155 |
Data Arrival Time | 1.221 |
Data Required Time | 9.377 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R9C3[2][B] | u_la0_top/rst_ao_s0/CLK |
0.232 | 0.232 | tC2Q | RF | 95 | R9C3[2][B] | u_la0_top/rst_ao_s0/Q |
1.221 | 0.989 | tNET | FF | 1 | R15C6[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
9.412 | 0.000 | tNET | RR | 1 | R15C6[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/CLK |
9.377 | -0.035 | tSu | 1 | R15C6[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 9.412 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.989, 81.004%; tC2Q: 0.232, 18.996% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path25
Path Summary:
Slack | 8.155 |
Data Arrival Time | 1.221 |
Data Required Time | 9.377 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R9C3[2][B] | u_la0_top/rst_ao_s0/CLK |
0.232 | 0.232 | tC2Q | RF | 95 | R9C3[2][B] | u_la0_top/rst_ao_s0/Q |
1.221 | 0.989 | tNET | FF | 1 | R15C6[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
9.412 | 0.000 | tNET | RR | 1 | R15C6[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK |
9.377 | -0.035 | tSu | 1 | R15C6[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 9.412 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.989, 81.004%; tC2Q: 0.232, 18.996% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Removal Analysis Report
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 0.328 |
Data Arrival Time | 0.339 |
Data Required Time | 0.011 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/capture_window_sel_10_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R9C3[2][B] | u_la0_top/rst_ao_s0/CLK |
0.202 | 0.202 | tC2Q | RR | 95 | R9C3[2][B] | u_la0_top/rst_ao_s0/Q |
0.339 | 0.137 | tNET | RR | 1 | R9C3[0][A] | u_la0_top/capture_window_sel_10_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R9C3[0][A] | u_la0_top/capture_window_sel_10_s1/CLK |
0.011 | 0.011 | tHld | 1 | R9C3[0][A] | u_la0_top/capture_window_sel_10_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.137, 40.408%; tC2Q: 0.202, 59.592% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path2
Path Summary:
Slack | 0.450 |
Data Arrival Time | 0.461 |
Data Required Time | 0.011 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/capture_window_sel_0_s3 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R9C3[2][B] | u_la0_top/rst_ao_s0/CLK |
0.202 | 0.202 | tC2Q | RR | 95 | R9C3[2][B] | u_la0_top/rst_ao_s0/Q |
0.461 | 0.259 | tNET | RR | 1 | R9C2[0][B] | u_la0_top/capture_window_sel_0_s3/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R9C2[0][B] | u_la0_top/capture_window_sel_0_s3/CLK |
0.011 | 0.011 | tHld | 1 | R9C2[0][B] | u_la0_top/capture_window_sel_0_s3 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.259, 56.179%; tC2Q: 0.202, 43.821% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path3
Path Summary:
Slack | 0.450 |
Data Arrival Time | 0.461 |
Data Required Time | 0.011 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/internal_reg_force_triger_syn_0_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R9C3[2][B] | u_la0_top/rst_ao_s0/CLK |
0.202 | 0.202 | tC2Q | RR | 95 | R9C3[2][B] | u_la0_top/rst_ao_s0/Q |
0.461 | 0.259 | tNET | RR | 1 | R9C2[0][A] | u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R9C2[0][A] | u_la0_top/internal_reg_force_triger_syn_0_s0/CLK |
0.011 | 0.011 | tHld | 1 | R9C2[0][A] | u_la0_top/internal_reg_force_triger_syn_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.259, 56.179%; tC2Q: 0.202, 43.821% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path4
Path Summary:
Slack | 0.572 |
Data Arrival Time | 0.583 |
Data Required Time | 0.011 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_mem_ctrl/capture_length_9_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R9C3[2][B] | u_la0_top/rst_ao_s0/CLK |
0.202 | 0.202 | tC2Q | RR | 95 | R9C3[2][B] | u_la0_top/rst_ao_s0/Q |
0.583 | 0.381 | tNET | RR | 1 | R9C7[2][A] | u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R9C7[2][A] | u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLK |
0.011 | 0.011 | tHld | 1 | R9C7[2][A] | u_la0_top/u_ao_mem_ctrl/capture_length_9_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.381, 65.350%; tC2Q: 0.202, 34.650% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path5
Path Summary:
Slack | 0.595 |
Data Arrival Time | 0.606 |
Data Required Time | 0.011 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_mem_ctrl/capture_length_7_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R9C3[2][B] | u_la0_top/rst_ao_s0/CLK |
0.202 | 0.202 | tC2Q | RR | 95 | R9C3[2][B] | u_la0_top/rst_ao_s0/Q |
0.606 | 0.404 | tNET | RR | 1 | R17C6[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R17C6[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLK |
0.011 | 0.011 | tHld | 1 | R17C6[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_7_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.404, 66.681%; tC2Q: 0.202, 33.319% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path6
Path Summary:
Slack | 0.595 |
Data Arrival Time | 0.606 |
Data Required Time | 0.011 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_mem_ctrl/capture_length_8_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R9C3[2][B] | u_la0_top/rst_ao_s0/CLK |
0.202 | 0.202 | tC2Q | RR | 95 | R9C3[2][B] | u_la0_top/rst_ao_s0/Q |
0.606 | 0.404 | tNET | RR | 1 | R17C6[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R17C6[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLK |
0.011 | 0.011 | tHld | 1 | R17C6[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_8_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.404, 66.681%; tC2Q: 0.202, 33.319% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path7
Path Summary:
Slack | 0.604 |
Data Arrival Time | 0.615 |
Data Required Time | 0.011 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_mem_ctrl/capture_length_0_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R9C3[2][B] | u_la0_top/rst_ao_s0/CLK |
0.202 | 0.202 | tC2Q | RR | 95 | R9C3[2][B] | u_la0_top/rst_ao_s0/Q |
0.615 | 0.413 | tNET | RR | 1 | R8C7[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R8C7[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLK |
0.011 | 0.011 | tHld | 1 | R8C7[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_0_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.413, 67.140%; tC2Q: 0.202, 32.860% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path8
Path Summary:
Slack | 0.604 |
Data Arrival Time | 0.615 |
Data Required Time | 0.011 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_mem_ctrl/capture_length_10_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R9C3[2][B] | u_la0_top/rst_ao_s0/CLK |
0.202 | 0.202 | tC2Q | RR | 95 | R9C3[2][B] | u_la0_top/rst_ao_s0/Q |
0.615 | 0.413 | tNET | RR | 1 | R8C7[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_10_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R8C7[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_10_s1/CLK |
0.011 | 0.011 | tHld | 1 | R8C7[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_10_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.413, 67.140%; tC2Q: 0.202, 32.860% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path9
Path Summary:
Slack | 0.610 |
Data Arrival Time | 0.621 |
Data Required Time | 0.011 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/internal_reg_start_syn_0_s0 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R9C3[2][B] | u_la0_top/rst_ao_s0/CLK |
0.202 | 0.202 | tC2Q | RR | 95 | R9C3[2][B] | u_la0_top/rst_ao_s0/Q |
0.621 | 0.419 | tNET | RR | 1 | R5C11[0][A] | u_la0_top/internal_reg_start_syn_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R5C11[0][A] | u_la0_top/internal_reg_start_syn_0_s0/CLK |
0.011 | 0.011 | tHld | 1 | R5C11[0][A] | u_la0_top/internal_reg_start_syn_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.419, 67.447%; tC2Q: 0.202, 32.553% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path10
Path Summary:
Slack | 0.612 |
Data Arrival Time | 0.623 |
Data Required Time | 0.011 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_match_3/match_cnt_11_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R9C3[2][B] | u_la0_top/rst_ao_s0/CLK |
0.202 | 0.202 | tC2Q | RR | 95 | R9C3[2][B] | u_la0_top/rst_ao_s0/Q |
0.623 | 0.421 | tNET | RR | 1 | R11C7[2][A] | u_la0_top/u_ao_match_3/match_cnt_11_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R11C7[2][A] | u_la0_top/u_ao_match_3/match_cnt_11_s1/CLK |
0.011 | 0.011 | tHld | 1 | R11C7[2][A] | u_la0_top/u_ao_match_3/match_cnt_11_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.421, 67.561%; tC2Q: 0.202, 32.439% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path11
Path Summary:
Slack | 0.612 |
Data Arrival Time | 0.623 |
Data Required Time | 0.011 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R9C3[2][B] | u_la0_top/rst_ao_s0/CLK |
0.202 | 0.202 | tC2Q | RR | 95 | R9C3[2][B] | u_la0_top/rst_ao_s0/Q |
0.623 | 0.421 | tNET | RR | 1 | R11C7[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R11C7[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK |
0.011 | 0.011 | tHld | 1 | R11C7[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.421, 67.561%; tC2Q: 0.202, 32.439% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path12
Path Summary:
Slack | 0.613 |
Data Arrival Time | 0.624 |
Data Required Time | 0.011 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_mem_ctrl/capture_length_4_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R9C3[2][B] | u_la0_top/rst_ao_s0/CLK |
0.202 | 0.202 | tC2Q | RR | 95 | R9C3[2][B] | u_la0_top/rst_ao_s0/Q |
0.624 | 0.422 | tNET | RR | 1 | R16C4[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R16C4[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLK |
0.011 | 0.011 | tHld | 1 | R16C4[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_4_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.422, 67.615%; tC2Q: 0.202, 32.385% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path13
Path Summary:
Slack | 0.613 |
Data Arrival Time | 0.624 |
Data Required Time | 0.011 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_mem_ctrl/capture_length_6_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R9C3[2][B] | u_la0_top/rst_ao_s0/CLK |
0.202 | 0.202 | tC2Q | RR | 95 | R9C3[2][B] | u_la0_top/rst_ao_s0/Q |
0.624 | 0.422 | tNET | RR | 1 | R16C4[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R16C4[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLK |
0.011 | 0.011 | tHld | 1 | R16C4[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_6_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.422, 67.615%; tC2Q: 0.202, 32.385% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path14
Path Summary:
Slack | 0.613 |
Data Arrival Time | 0.624 |
Data Required Time | 0.011 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/capture_window_sel_5_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R9C3[2][B] | u_la0_top/rst_ao_s0/CLK |
0.202 | 0.202 | tC2Q | RR | 95 | R9C3[2][B] | u_la0_top/rst_ao_s0/Q |
0.624 | 0.422 | tNET | RR | 1 | R3C3[2][B] | u_la0_top/capture_window_sel_5_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R3C3[2][B] | u_la0_top/capture_window_sel_5_s1/CLK |
0.011 | 0.011 | tHld | 1 | R3C3[2][B] | u_la0_top/capture_window_sel_5_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.422, 67.639%; tC2Q: 0.202, 32.361% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path15
Path Summary:
Slack | 0.613 |
Data Arrival Time | 0.624 |
Data Required Time | 0.011 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/capture_window_sel_6_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R9C3[2][B] | u_la0_top/rst_ao_s0/CLK |
0.202 | 0.202 | tC2Q | RR | 95 | R9C3[2][B] | u_la0_top/rst_ao_s0/Q |
0.624 | 0.422 | tNET | RR | 1 | R3C3[2][A] | u_la0_top/capture_window_sel_6_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R3C3[2][A] | u_la0_top/capture_window_sel_6_s1/CLK |
0.011 | 0.011 | tHld | 1 | R3C3[2][A] | u_la0_top/capture_window_sel_6_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.422, 67.639%; tC2Q: 0.202, 32.361% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path16
Path Summary:
Slack | 0.613 |
Data Arrival Time | 0.624 |
Data Required Time | 0.011 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/capture_window_sel_7_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R9C3[2][B] | u_la0_top/rst_ao_s0/CLK |
0.202 | 0.202 | tC2Q | RR | 95 | R9C3[2][B] | u_la0_top/rst_ao_s0/Q |
0.624 | 0.422 | tNET | RR | 1 | R3C3[1][B] | u_la0_top/capture_window_sel_7_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R3C3[1][B] | u_la0_top/capture_window_sel_7_s1/CLK |
0.011 | 0.011 | tHld | 1 | R3C3[1][B] | u_la0_top/capture_window_sel_7_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.422, 67.639%; tC2Q: 0.202, 32.361% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path17
Path Summary:
Slack | 0.613 |
Data Arrival Time | 0.624 |
Data Required Time | 0.011 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/capture_window_sel_8_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R9C3[2][B] | u_la0_top/rst_ao_s0/CLK |
0.202 | 0.202 | tC2Q | RR | 95 | R9C3[2][B] | u_la0_top/rst_ao_s0/Q |
0.624 | 0.422 | tNET | RR | 1 | R3C3[1][A] | u_la0_top/capture_window_sel_8_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R3C3[1][A] | u_la0_top/capture_window_sel_8_s1/CLK |
0.011 | 0.011 | tHld | 1 | R3C3[1][A] | u_la0_top/capture_window_sel_8_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.422, 67.639%; tC2Q: 0.202, 32.361% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path18
Path Summary:
Slack | 0.613 |
Data Arrival Time | 0.624 |
Data Required Time | 0.011 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_match_3/match_cnt_5_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R9C3[2][B] | u_la0_top/rst_ao_s0/CLK |
0.202 | 0.202 | tC2Q | RR | 95 | R9C3[2][B] | u_la0_top/rst_ao_s0/Q |
0.624 | 0.422 | tNET | RR | 1 | R12C7[1][A] | u_la0_top/u_ao_match_3/match_cnt_5_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R12C7[1][A] | u_la0_top/u_ao_match_3/match_cnt_5_s1/CLK |
0.011 | 0.011 | tHld | 1 | R12C7[1][A] | u_la0_top/u_ao_match_3/match_cnt_5_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.422, 67.650%; tC2Q: 0.202, 32.350% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path19
Path Summary:
Slack | 0.613 |
Data Arrival Time | 0.624 |
Data Required Time | 0.011 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_match_3/match_cnt_6_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R9C3[2][B] | u_la0_top/rst_ao_s0/CLK |
0.202 | 0.202 | tC2Q | RR | 95 | R9C3[2][B] | u_la0_top/rst_ao_s0/Q |
0.624 | 0.422 | tNET | RR | 1 | R12C7[1][B] | u_la0_top/u_ao_match_3/match_cnt_6_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R12C7[1][B] | u_la0_top/u_ao_match_3/match_cnt_6_s1/CLK |
0.011 | 0.011 | tHld | 1 | R12C7[1][B] | u_la0_top/u_ao_match_3/match_cnt_6_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.422, 67.650%; tC2Q: 0.202, 32.350% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path20
Path Summary:
Slack | 0.613 |
Data Arrival Time | 0.624 |
Data Required Time | 0.011 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_match_3/match_cnt_7_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R9C3[2][B] | u_la0_top/rst_ao_s0/CLK |
0.202 | 0.202 | tC2Q | RR | 95 | R9C3[2][B] | u_la0_top/rst_ao_s0/Q |
0.624 | 0.422 | tNET | RR | 1 | R12C7[2][A] | u_la0_top/u_ao_match_3/match_cnt_7_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R12C7[2][A] | u_la0_top/u_ao_match_3/match_cnt_7_s1/CLK |
0.011 | 0.011 | tHld | 1 | R12C7[2][A] | u_la0_top/u_ao_match_3/match_cnt_7_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.422, 67.650%; tC2Q: 0.202, 32.350% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path21
Path Summary:
Slack | 0.613 |
Data Arrival Time | 0.624 |
Data Required Time | 0.011 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R9C3[2][B] | u_la0_top/rst_ao_s0/CLK |
0.202 | 0.202 | tC2Q | RR | 95 | R9C3[2][B] | u_la0_top/rst_ao_s0/Q |
0.624 | 0.422 | tNET | RR | 1 | R9C10[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R9C10[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK |
0.011 | 0.011 | tHld | 1 | R9C10[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.422, 67.654%; tC2Q: 0.202, 32.346% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path22
Path Summary:
Slack | 0.618 |
Data Arrival Time | 0.629 |
Data Required Time | 0.011 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/capture_window_sel_1_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R9C3[2][B] | u_la0_top/rst_ao_s0/CLK |
0.202 | 0.202 | tC2Q | RR | 95 | R9C3[2][B] | u_la0_top/rst_ao_s0/Q |
0.629 | 0.427 | tNET | RR | 1 | R7C11[0][A] | u_la0_top/capture_window_sel_1_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R7C11[0][A] | u_la0_top/capture_window_sel_1_s1/CLK |
0.011 | 0.011 | tHld | 1 | R7C11[0][A] | u_la0_top/capture_window_sel_1_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.427, 67.909%; tC2Q: 0.202, 32.091% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path23
Path Summary:
Slack | 0.618 |
Data Arrival Time | 0.629 |
Data Required Time | 0.011 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/triger_level_cnt_1_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R9C3[2][B] | u_la0_top/rst_ao_s0/CLK |
0.202 | 0.202 | tC2Q | RR | 95 | R9C3[2][B] | u_la0_top/rst_ao_s0/Q |
0.629 | 0.427 | tNET | RR | 1 | R7C11[1][B] | u_la0_top/triger_level_cnt_1_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R7C11[1][B] | u_la0_top/triger_level_cnt_1_s1/CLK |
0.011 | 0.011 | tHld | 1 | R7C11[1][B] | u_la0_top/triger_level_cnt_1_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.427, 67.909%; tC2Q: 0.202, 32.091% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path24
Path Summary:
Slack | 0.618 |
Data Arrival Time | 0.629 |
Data Required Time | 0.011 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/triger_level_cnt_2_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R9C3[2][B] | u_la0_top/rst_ao_s0/CLK |
0.202 | 0.202 | tC2Q | RR | 95 | R9C3[2][B] | u_la0_top/rst_ao_s0/Q |
0.629 | 0.427 | tNET | RR | 1 | R7C11[1][A] | u_la0_top/triger_level_cnt_2_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R7C11[1][A] | u_la0_top/triger_level_cnt_2_s1/CLK |
0.011 | 0.011 | tHld | 1 | R7C11[1][A] | u_la0_top/triger_level_cnt_2_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.427, 67.909%; tC2Q: 0.202, 32.091% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path25
Path Summary:
Slack | 0.619 |
Data Arrival Time | 0.630 |
Data Required Time | 0.011 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_match_3/match_cnt_1_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R9C3[2][B] | u_la0_top/rst_ao_s0/CLK |
0.202 | 0.202 | tC2Q | RR | 95 | R9C3[2][B] | u_la0_top/rst_ao_s0/Q |
0.630 | 0.428 | tNET | RR | 1 | R16C5[0][A] | u_la0_top/u_ao_match_3/match_cnt_1_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 1090 | PLL_L[0] | u_pll/rpll_inst/CLKOUTD |
0.000 | 0.000 | tNET | RR | 1 | R16C5[0][A] | u_la0_top/u_ao_match_3/match_cnt_1_s1/CLK |
0.011 | 0.011 | tHld | 1 | R16C5[0][A] | u_la0_top/u_ao_match_3/match_cnt_1_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.428, 67.924%; tC2Q: 0.202, 32.076% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Minimum Pulse Width Report:
Report Command:report_min_pulse_width -nworst 10 -detail
MPW1
MPW Summary:
Slack: | 1.766 |
Actual Width: | 2.766 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | pixel_clk |
Objects: | run_cnt_25_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
3.529 | 0.000 | active clock edge time | ||
3.529 | 0.000 | pixel_clk | ||
3.529 | 0.000 | tCL | FF | u_pll/rpll_inst/CLKOUTD3 |
5.804 | 2.274 | tNET | FF | run_cnt_25_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
7.059 | 0.000 | active clock edge time | ||
7.059 | 0.000 | pixel_clk | ||
7.059 | 0.000 | tCL | RR | u_pll/rpll_inst/CLKOUTD3 |
8.570 | 1.511 | tNET | RR | run_cnt_25_s0/CLK |
MPW2
MPW Summary:
Slack: | 1.766 |
Actual Width: | 2.766 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | pixel_clk |
Objects: | u_test_gen/De_vcnt_9_s1 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
3.529 | 0.000 | active clock edge time | ||
3.529 | 0.000 | pixel_clk | ||
3.529 | 0.000 | tCL | FF | u_pll/rpll_inst/CLKOUTD3 |
5.804 | 2.274 | tNET | FF | u_test_gen/De_vcnt_9_s1/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
7.059 | 0.000 | active clock edge time | ||
7.059 | 0.000 | pixel_clk | ||
7.059 | 0.000 | tCL | RR | u_pll/rpll_inst/CLKOUTD3 |
8.570 | 1.511 | tNET | RR | u_test_gen/De_vcnt_9_s1/CLK |
MPW3
MPW Summary:
Slack: | 1.766 |
Actual Width: | 2.766 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | pixel_clk |
Objects: | u_p2b/u_p2b_0/u_mid_buf/rRPtrWsync_2_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
3.529 | 0.000 | active clock edge time | ||
3.529 | 0.000 | pixel_clk | ||
3.529 | 0.000 | tCL | FF | u_pll/rpll_inst/CLKOUTD3 |
5.804 | 2.274 | tNET | FF | u_p2b/u_p2b_0/u_mid_buf/rRPtrWsync_2_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
7.059 | 0.000 | active clock edge time | ||
7.059 | 0.000 | pixel_clk | ||
7.059 | 0.000 | tCL | RR | u_pll/rpll_inst/CLKOUTD3 |
8.570 | 1.511 | tNET | RR | u_p2b/u_p2b_0/u_mid_buf/rRPtrWsync_2_s0/CLK |
MPW4
MPW Summary:
Slack: | 1.766 |
Actual Width: | 2.766 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | pixel_clk |
Objects: | u_p2b/u_p2b_0/u_mid_buf/rRPtrWsync_1_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
3.529 | 0.000 | active clock edge time | ||
3.529 | 0.000 | pixel_clk | ||
3.529 | 0.000 | tCL | FF | u_pll/rpll_inst/CLKOUTD3 |
5.804 | 2.274 | tNET | FF | u_p2b/u_p2b_0/u_mid_buf/rRPtrWsync_1_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
7.059 | 0.000 | active clock edge time | ||
7.059 | 0.000 | pixel_clk | ||
7.059 | 0.000 | tCL | RR | u_pll/rpll_inst/CLKOUTD3 |
8.570 | 1.511 | tNET | RR | u_p2b/u_p2b_0/u_mid_buf/rRPtrWsync_1_s0/CLK |
MPW5
MPW Summary:
Slack: | 1.766 |
Actual Width: | 2.766 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | pixel_clk |
Objects: | u_p2b/u_p2b_0/u_mid_buf/rRPtrWsync_0_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
3.529 | 0.000 | active clock edge time | ||
3.529 | 0.000 | pixel_clk | ||
3.529 | 0.000 | tCL | FF | u_pll/rpll_inst/CLKOUTD3 |
5.804 | 2.274 | tNET | FF | u_p2b/u_p2b_0/u_mid_buf/rRPtrWsync_0_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
7.059 | 0.000 | active clock edge time | ||
7.059 | 0.000 | pixel_clk | ||
7.059 | 0.000 | tCL | RR | u_pll/rpll_inst/CLKOUTD3 |
8.570 | 1.511 | tNET | RR | u_p2b/u_p2b_0/u_mid_buf/rRPtrWsync_0_s0/CLK |
MPW6
MPW Summary:
Slack: | 1.766 |
Actual Width: | 2.766 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | pixel_clk |
Objects: | u_p2b/u_p2b_0/u_mid_buf/rFull_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
3.529 | 0.000 | active clock edge time | ||
3.529 | 0.000 | pixel_clk | ||
3.529 | 0.000 | tCL | FF | u_pll/rpll_inst/CLKOUTD3 |
5.804 | 2.274 | tNET | FF | u_p2b/u_p2b_0/u_mid_buf/rFull_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
7.059 | 0.000 | active clock edge time | ||
7.059 | 0.000 | pixel_clk | ||
7.059 | 0.000 | tCL | RR | u_pll/rpll_inst/CLKOUTD3 |
8.570 | 1.511 | tNET | RR | u_p2b/u_p2b_0/u_mid_buf/rFull_s0/CLK |
MPW7
MPW Summary:
Slack: | 1.766 |
Actual Width: | 2.766 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | pixel_clk |
Objects: | u_p2b/u_p2b_0/u_mid_buf/rWPtrGray_0_s1 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
3.529 | 0.000 | active clock edge time | ||
3.529 | 0.000 | pixel_clk | ||
3.529 | 0.000 | tCL | FF | u_pll/rpll_inst/CLKOUTD3 |
5.804 | 2.274 | tNET | FF | u_p2b/u_p2b_0/u_mid_buf/rWPtrGray_0_s1/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
7.059 | 0.000 | active clock edge time | ||
7.059 | 0.000 | pixel_clk | ||
7.059 | 0.000 | tCL | RR | u_pll/rpll_inst/CLKOUTD3 |
8.570 | 1.511 | tNET | RR | u_p2b/u_p2b_0/u_mid_buf/rWPtrGray_0_s1/CLK |
MPW8
MPW Summary:
Slack: | 1.766 |
Actual Width: | 2.766 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | pixel_clk |
Objects: | u_test_gen/De_vcnt_8_s1 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
3.529 | 0.000 | active clock edge time | ||
3.529 | 0.000 | pixel_clk | ||
3.529 | 0.000 | tCL | FF | u_pll/rpll_inst/CLKOUTD3 |
5.804 | 2.274 | tNET | FF | u_test_gen/De_vcnt_8_s1/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
7.059 | 0.000 | active clock edge time | ||
7.059 | 0.000 | pixel_clk | ||
7.059 | 0.000 | tCL | RR | u_pll/rpll_inst/CLKOUTD3 |
8.570 | 1.511 | tNET | RR | u_test_gen/De_vcnt_8_s1/CLK |
MPW9
MPW Summary:
Slack: | 1.766 |
Actual Width: | 2.766 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | pixel_clk |
Objects: | u_p2b/u_p2b_0/shift_data_94_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
3.529 | 0.000 | active clock edge time | ||
3.529 | 0.000 | pixel_clk | ||
3.529 | 0.000 | tCL | FF | u_pll/rpll_inst/CLKOUTD3 |
5.804 | 2.274 | tNET | FF | u_p2b/u_p2b_0/shift_data_94_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
7.059 | 0.000 | active clock edge time | ||
7.059 | 0.000 | pixel_clk | ||
7.059 | 0.000 | tCL | RR | u_pll/rpll_inst/CLKOUTD3 |
8.570 | 1.511 | tNET | RR | u_p2b/u_p2b_0/shift_data_94_s0/CLK |
MPW10
MPW Summary:
Slack: | 1.766 |
Actual Width: | 2.766 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | pixel_clk |
Objects: | u_p2b/u_p2b_0/mid_data_17_s1 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
3.529 | 0.000 | active clock edge time | ||
3.529 | 0.000 | pixel_clk | ||
3.529 | 0.000 | tCL | FF | u_pll/rpll_inst/CLKOUTD3 |
5.804 | 2.274 | tNET | FF | u_p2b/u_p2b_0/mid_data_17_s1/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
7.059 | 0.000 | active clock edge time | ||
7.059 | 0.000 | pixel_clk | ||
7.059 | 0.000 | tCL | RR | u_pll/rpll_inst/CLKOUTD3 |
8.570 | 1.511 | tNET | RR | u_p2b/u_p2b_0/mid_data_17_s1/CLK |
High Fanout Nets Report:
Report Command:report_high_fanout_nets -max_nets 10
FANOUT | NET NAME | WORST SLACK | MAX DELAY |
---|---|---|---|
1090 | byte_clk | 1.751 | 2.274 |
279 | pixel_clk | 2.178 | 2.274 |
99 | n2707_3 | 5.004 | 1.721 |
96 | n3116_11 | 4.006 | 1.762 |
96 | n3211_9 | 3.921 | 2.538 |
96 | n2860_6 | 4.429 | 1.573 |
94 | rRegData_125_10 | 5.004 | 1.523 |
68 | rOffset[0] | 4.630 | 1.969 |
66 | loop_cnt[1] | 4.414 | 0.905 |
65 | mid_sel[0] | 4.213 | 0.997 |
Route Congestions Report:
Report Command:report_route_congestion -max_grids 10
GRID LOC | ROUTE CONGESTIONS |
---|---|
R14C20 | 65.28% |
R17C32 | 63.89% |
R16C33 | 62.50% |
R20C22 | 61.11% |
R16C34 | 61.11% |
R14C23 | 56.94% |
R15C24 | 56.94% |
R22C34 | 56.94% |
R20C32 | 55.56% |
R18C32 | 55.56% |
Timing Exceptions Report:
Setup Analysis Report
Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Hold Analysis Report
Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Recovery Analysis Report
Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Removal Analysis Report
Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Timing Constraints Report:
SDC Command Type | State | Detail Command |
---|---|---|
TC_CLOCK | Actived | create_clock -name clk_50 -period 20 -waveform {0 10} [get_ports {OSC_50M}] |
TC_GENERATED_CLOCK | Actived | create_generated_clock -name pixel_clk -source [get_ports {OSC_50M}] -master_clock clk_50 -divide_by 6 -multiply_by 17 [get_nets {pixel_clk}] |
TC_GENERATED_CLOCK | Actived | create_generated_clock -name byte_clk -source [get_ports {OSC_50M}] -master_clock clk_50 -divide_by 8 -multiply_by 17 [get_nets {byte_clk}] |
TC_CLOCK_GROUP | Actived | set_clock_groups -exclusive -group [get_clocks {pixel_clk}] -group [get_clocks {byte_clk}] |
TC_REPORT_TIMING | Actived | report_timing -setup -from_clock [get_clocks {pixel_clk}] -max_paths 20 -max_common_paths 1 |
TC_REPORT_TIMING | Actived | report_timing -setup -from_clock [get_clocks {byte_clk}] -max_paths 20 -max_common_paths 1 |
TC_REPORT_TIMING | Actived | report_timing -hold -from_clock [get_clocks {pixel_clk}] -max_paths 20 -max_common_paths 1 |
TC_REPORT_TIMING | Actived | report_timing -hold -from_clock [get_clocks {byte_clk}] -max_paths 20 -max_common_paths 1 |