PnR Messages

Report Title PnR Report
Design File F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\Dsi_Test_pattern_2a18\fpga_proj\impl\gwsynthesis\Dsi_test_pattern_2a18.vg
Gao Design File F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\Dsi_Test_pattern_2a18\fpga_proj\impl\gao\gao.v
Physical Constraints File F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\Dsi_Test_pattern_2a18\fpga_proj\src\DK_START_Gw2A18_V2.cst
Timing Constraints File F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\Dsi_Test_pattern_2a18\fpga_proj\src\dsi_test.sdc
Tool Version V1.9.9.01 (64-bit)
Part Number GW2A-LV18PG256C8/I7
Device GW2A-18
Device Version C
Created Time Wed Mar 6 11:19:28 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

PnR Details

Place & Route Process Running placement: Placement Phase 0: CPU time = 0h 0m 0.132s, Elapsed time = 0h 0m 0.133s Placement Phase 1: CPU time = 0h 0m 0.246s, Elapsed time = 0h 0m 0.246s Placement Phase 2: CPU time = 0h 0m 0.221s, Elapsed time = 0h 0m 0.221s Placement Phase 3: CPU time = 0h 0m 0.845s, Elapsed time = 0h 0m 0.845s Placement Phase GAO : CPU time = 0h 0m 0.113s, Elapsed time = 0h 0m 0.113s Total Placement: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s Running routing: Routing Phase 0: CPU time = 0h 0m 0.002s, Elapsed time = 0h 0m 0.001s Routing Phase 1: CPU time = 0h 0m 0.399s, Elapsed time = 0h 0m 0.4s Routing Phase 2: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s Routing Phase 3: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s Total Routing: CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s Generate output files: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s
Total Time and Memory Usage CPU time = 0h 0m 8s, Elapsed time = 0h 0m 8s, Peak memory usage = 563MB

Resource

Resource Usage Summary:

Resource Usage Utilization
Logic 1695/20736 9%
    --LUT,ALU,ROM16 1623(1563 LUT, 60 ALU, 0 ROM16) -
    --SSRAM(RAM16) 12 -
Register 896/16173 6%
    --Logic Register as Latch 0/15552 0%
    --Logic Register as FF 895/15552 6%
    --I/O Register as Latch 0/621 0%
    --I/O Register as FF 1/621 <1%
CLS 1118/10368 11%
I/O Port 17 -
I/O Buf 12 -
    --Input Buf 2 -
    --Output Buf 8 -
    --Inout Buf 2 -
IOLOGIC 5 OSER8
5%
BSRAM 2 SDPX9B
5%
DSP 00%
PLL 1/4 25%
DCS 0/8 0%
DQCE 0/24 0%
OSC 0/1 0%
CLKDIV 0/8 0%
DLLDLY 0/8 0%
DQS 0/9 0%
DHCEN 0/16 0%

GAO Resource Usage Summary:

Resource Usage
Logic 723
    --LUT,ALU,ROM16 723(709 LUT, 14 ALU, 0 ROM16)
    --SSRAM(RAM16) 0
Register 982
I/O Port 170
I/O Buf 4
    --Input Buf 3
    --Output Buf 1
    --Inout Buf 0
BSRAM 19

I/O Bank Usage Summary:

I/O Bank Usage
bank 0 4/29(13%)
bank 1 10/20(50%)
bank 2 0/20(0%)
bank 3 1/32(3%)
bank 4 0/36(0%)
bank 5 0/36(0%)
bank 6 0/18(0%)
bank 7 2/16(12%)

Global Clock Usage Summary:

Global Clock Usage
PRIMARY 2/8(25%)
LW 4/8(50%)
GCLK_PIN 2/8(25%)
PLL 1/4(25%)
CLKDIV 0/8(0%)
DLLDLY 0/8(0%)

Global Clock Signals:

Signal Global Clock Location
byte_clk PRIMARY TR TL
pixel_clk PRIMARY TR TL
RESET_N_d LW -
n158_6 LW -
u_dsi_tx/u_tx/u_dsi_tx/n2707_3 LW -
u_dsi_tx/u_tx/u_dsi_tx/rRegData_125_10 LW -
OSC_50M_d HCLK TOP[0]
bit_clk HCLK TOP[1]
bit_clk_90 HCLK TOP[0]

Pinout by Port Name:

Port Name Diff Pair Loc./Bank Constraint Dir. Site IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Vref Single Resistor Diff Resistor BankVccio
RESET_N T10/3 Y in IOR35[B] LVCMOS33 NA UP ON NONE NA NA OFF NA 1.2
OSC_50M H11/0 Y in IOT27[A] LVCMOS25 NA UP ON NONE NA NA NA NA 2.5
HS_CLK_P HS_CLK_N K14,K15/1 Y out IOT30 LVDS25 3.5 NA NA NA NA NA NA NA 2.5
HS_DATA3_P HS_DATA3_N L16,L14/1 Y out IOT34 LVDS25 3.5 NA NA NA NA NA NA NA 2.5
HS_DATA2_P HS_DATA2_N N16,N14/1 Y out IOT52 LVDS25 3.5 NA NA NA NA NA NA NA 2.5
HS_DATA1_P HS_DATA1_N N15,P16/1 Y out IOT48 LVDS25 3.5 NA NA NA NA NA NA NA 2.5
HS_DATA0_P HS_DATA0_N P15,R16/1 Y out IOT54 LVDS25 3.5 NA NA NA NA NA NA NA 2.5
led[0] F16/0 Y out IOT9[B] LVCMOS25 8 UP NA NA OFF NA NA NA 2.5
led[1] G12/0 Y out IOT8[B] LVCMOS25 8 UP NA NA OFF NA NA NA 2.5
led[2] F13/0 Y out IOT8[A] LVCMOS25 8 UP NA NA OFF NA NA NA 2.5
LP_DATA0[0] B12/7 Y io IOL7[B] LVCMOS12 8 UP NA NONE OFF NA OFF NA 1.2
LP_DATA0[1] B13/7 Y io IOL8[A] LVCMOS12 8 UP NA NONE OFF NA OFF NA 1.2

All Package Pins:

Loc./Bank Signal Dir. Site IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Vref Single Resistor Diff Resistor Bank Vccio
L15/0 - in IOT2[A] LVCMOS18 NA UP ON NONE NA NA NA NA 2.5
D16/0 - in IOT4[A] LVCMOS18 NA UP ON NONE NA NA NA NA 2.5
E14/0 - in IOT4[B] LVCMOS18 NA UP ON NONE NA NA NA NA 2.5
C16/0 - in IOT5[A] LVCMOS18 NA UP ON NONE NA NA NA NA 2.5
D15/0 - in IOT5[B] LVCMOS18 NA UP ON NONE NA NA NA NA 2.5
E16/0 - in IOT6[A] LVCMOS18 NA UP ON NONE NA NA NA NA 2.5
F15/0 - in IOT6[B] LVCMOS18 NA UP ON NONE NA NA NA NA 2.5
F13/0 led[2] out IOT8[A] LVCMOS25 8 UP NA NA OFF NA NA NA 2.5
G12/0 led[1] out IOT8[B] LVCMOS25 8 UP NA NA OFF NA NA NA 2.5
F14/0 - in IOT9[A] LVCMOS18 NA UP ON NONE NA NA NA NA 2.5
F16/0 led[0] out IOT9[B] LVCMOS25 8 UP NA NA OFF NA NA NA 2.5
F12/0 - in IOT12[A] LVCMOS18 NA UP ON NONE NA NA NA NA 2.5
G13/0 - in IOT12[B] LVCMOS18 NA UP ON NONE NA NA NA NA 2.5
G15/0 - in IOT13[A] LVCMOS18 NA UP ON NONE NA NA NA NA 2.5
G14/0 - in IOT13[B] LVCMOS18 NA UP ON NONE NA NA NA NA 2.5
G11/0 - in IOT14[A] LVCMOS18 NA UP ON NONE NA NA NA NA 2.5
H12/0 - in IOT14[B] LVCMOS18 NA UP ON NONE NA NA NA NA 2.5
G16/0 - in IOT16[A] LVCMOS18 NA UP ON NONE NA NA NA NA 2.5
H15/0 - in IOT16[B] LVCMOS18 NA UP ON NONE NA NA NA NA 2.5
H13/0 - in IOT18[A] LVCMOS18 NA UP ON NONE NA NA NA NA 2.5
J12/0 - in IOT18[B] LVCMOS18 NA UP ON NONE NA NA NA NA 2.5
H14/0 - in IOT20[A] LVCMOS18 NA UP ON NONE NA NA NA NA 2.5
H16/0 - in IOT20[B] LVCMOS18 NA UP ON NONE NA NA NA NA 2.5
J16/0 - in IOT22[A] LVCMOS18 NA UP ON NONE NA NA NA NA 2.5
J14/0 - in IOT22[B] LVCMOS18 NA UP ON NONE NA NA NA NA 2.5
J15/0 - in IOT24[A] LVCMOS18 NA UP ON NONE NA NA NA NA 2.5
K16/0 - in IOT24[B] LVCMOS18 NA UP ON NONE NA NA NA NA 2.5
H11/0 OSC_50M in IOT27[A] LVCMOS25 NA UP ON NONE NA NA NA NA 2.5
J13/0 - in IOT27[B] LVCMOS18 NA UP ON NONE NA NA NA NA 2.5
K14/1 HS_CLK_P out IOT30[A] LVDS25 3.5 NA NA NA NA NA NA NA 2.5
K15/1 HS_CLK_N out IOT30[B] LVDS25 3.5 NA NA NA NA NA NA NA 2.5
J11/1 - in IOT32[A] LVCMOS18 NA UP ON NONE NA NA NA NA 2.5
L12/1 - in IOT32[B] LVCMOS18 NA UP ON NONE NA NA NA NA 2.5
L16/1 HS_DATA3_P out IOT34[A] LVDS25 3.5 NA NA NA NA NA NA NA 2.5
L14/1 HS_DATA3_N out IOT34[B] LVDS25 3.5 NA NA NA NA NA NA NA 2.5
K13/1 - in IOT36[A] LVCMOS18 NA UP ON NONE NA NA NA NA 2.5
K12/1 - in IOT36[B] LVCMOS18 NA UP ON NONE NA NA NA NA 2.5
K11/1 - in IOT38[A] LVCMOS18 NA UP ON NONE NA NA NA NA 2.5
L13/1 - in IOT38[B] LVCMOS18 NA UP ON NONE NA NA NA NA 2.5
M14/1 - in IOT40[A] LVCMOS18 NA UP ON NONE NA NA NA NA 2.5
M15/1 - in IOT40[B] LVCMOS18 NA UP ON NONE NA NA NA NA 2.5
D14/1 - in IOT44[A] LVCMOS18 NA UP ON NONE NA NA NA NA 2.5
E15/1 - in IOT44[B] LVCMOS18 NA UP ON NONE NA NA NA NA 2.5
N15/1 HS_DATA1_P out IOT48[A] LVDS25 3.5 NA NA NA NA NA NA NA 2.5
P16/1 HS_DATA1_N out IOT48[B] LVDS25 3.5 NA NA NA NA NA NA NA 2.5
N16/1 HS_DATA2_P out IOT52[A] LVDS25 3.5 NA NA NA NA NA NA NA 2.5
N14/1 HS_DATA2_N out IOT52[B] LVDS25 3.5 NA NA NA NA NA NA NA 2.5
P15/1 HS_DATA0_P out IOT54[A] LVDS25 3.5 NA NA NA NA NA NA NA 2.5
R16/1 HS_DATA0_N out IOT54[B] LVDS25 3.5 NA NA NA NA NA NA NA 2.5
A4/5 - in IOB2[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
C5/5 - in IOB2[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
D6/5 - in IOB3[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
E7/5 - in IOB3[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
A3/5 - in IOB4[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
B4/5 - in IOB4[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
A5/5 - in IOB7[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
B6/5 - in IOB7[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
B1/5 - in IOB8[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
C2/5 - in IOB8[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
D3/5 - in IOB9[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
D1/5 - in IOB9[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
E2/5 - in IOB12[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
E3/5 - in IOB12[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
B3/5 - in IOB13[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
A2/5 - in IOB13[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
C1/5 - in IOB14[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
D2/5 - in IOB14[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
E1/5 - in IOB16[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
F2/5 - in IOB16[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
F4/5 - in IOB18[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
G6/5 - in IOB18[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
F3/5 - in IOB19[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
F1/5 - in IOB19[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
G5/5 - in IOB20[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
G4/5 - in IOB20[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
G2/5 - in IOB21[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
G3/5 - in IOB21[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
F5/5 - in IOB22[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
H6/5 - in IOB22[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
G1/5 - in IOB24[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
H2/5 - in IOB24[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
H4/5 - in IOB26[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
J6/5 - in IOB26[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
J1/5 - in IOB27[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
J3/5 - in IOB27[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
L2/4 - in IOB30[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
M1/4 - in IOB30[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
H3/4 - in IOB32[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
H1/4 - in IOB32[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
J2/4 - in IOB34[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
K1/4 - in IOB34[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
H5/4 - in IOB35[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
J4/4 - in IOB35[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
K3/4 - in IOB36[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
K2/4 - in IOB36[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
J5/4 - in IOB37[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
K6/4 - in IOB37[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
L1/4 - in IOB38[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
L3/4 - in IOB38[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
K4/4 - in IOB39[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
L5/4 - in IOB39[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
K5/4 - in IOB40[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
L4/4 - in IOB40[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
N2/4 - in IOB41[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
P1/4 - in IOB41[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
M3/4 - in IOB42[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
N1/4 - in IOB42[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
M2/4 - in IOB43[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
N3/4 - in IOB43[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
R1/4 - in IOB44[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
P2/4 - in IOB44[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
P4/4 - in IOB45[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
T4/4 - in IOB45[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
R3/4 - in IOB48[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
T2/4 - in IOB48[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
P5/4 - in IOB50[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
R5/4 - in IOB50[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
R4/4 - in IOB52[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
T3/4 - in IOB52[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
R6/4 - in IOB54[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
T5/4 - in IOB54[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
B14/7 - in IOL2[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
A15/7 - in IOL2[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
C12/7 - in IOL7[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
B12/7 LP_DATA0[0] io IOL7[B] LVCMOS12 8 UP NA NONE OFF NA OFF NA 1.2
B13/7 LP_DATA0[1] io IOL8[A] LVCMOS12 8 UP NA NONE OFF NA OFF NA 1.2
A14/7 - in IOL8[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
F10/7 - in IOL11[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
B11/7 - in IOL13[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
A12/7 - in IOL13[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
A11/7 - in IOL15[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
C11/7 - in IOL15[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
D10/7 - in IOL17[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
E10/7 - in IOL17[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
D11/7 - in IOL22[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
A9/7 - in IOL27[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
C9/7 - in IOL27[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
C8/6 - in IOL29[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
A8/6 - in IOL29[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
F9/6 - in IOL31[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
E11/6 - in IOL31[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
B9/6 - in IOL33[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
A10/6 - in IOL33[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
F8/6 - in IOL35[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
D9/6 - in IOL35[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
D8/6 - in IOL38[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
E9/6 - in IOL38[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
B7/6 - in IOL40[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
C7/6 - in IOL40[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
F7/6 - in IOL45[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
E8/6 - in IOL45[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
C4/6 - in IOL47[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
B5/6 - in IOL47[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
E6/6 - in IOL53[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
D7/6 - in IOL53[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
T15/2 - in IOR7[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
R14/2 - in IOR7[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
P12/2 - in IOR8[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
T13/2 - in IOR8[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
R12/2 - in IOR11[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
P13/2 - in IOR11[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
R11/2 - in IOR17[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
T12/2 - in IOR17[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
R13/2 - in IOR20[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
T14/2 - in IOR20[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
M10/2 - in IOR22[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
N11/2 - in IOR22[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
T11/2 - in IOR24[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
P11/2 - in IOR24[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
C6/2 tdo_pad_o out IOR25[A] LVCMOS18 8 UP NA NA OFF NA NA NA 1.8
B8/2 tms_pad_i in IOR25[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
A7/2 tck_pad_i in IOR26[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
A6/2 tdi_pad_i in IOR26[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
N10/2 - in IOR27[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
M11/2 - in IOR27[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
T7/3 - in IOR29[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
R8/3 - in IOR29[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
M16/3 - in IOR30[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
B16/3 - in IOR30[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
C15/3 - in IOR31[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
B10/3 - in IOR31[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
A13/3 - in IOR32[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
C13/3 - in IOR32[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
P10/3 - in IOR33[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
R10/3 - in IOR33[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
M9/3 - in IOR34[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
L10/3 - in IOR34[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
R9/3 - in IOR35[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
T10/3 RESET_N in IOR35[B] LVCMOS33 NA UP ON NONE NA NA OFF NA 1.2
M8/3 - in IOR36[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
N9/3 - in IOR36[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
T9/3 - in IOR38[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
P9/3 - in IOR38[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
C10/3 - in IOR39[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
N8/3 - in IOR40[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
L9/3 - in IOR40[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
P8/3 - in IOR42[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
T8/3 - in IOR42[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
M6/3 - in IOR44[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
L8/3 - in IOR44[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
M7/3 - in IOR47[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
N7/3 - in IOR47[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
R7/3 - in IOR49[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
P7/3 - in IOR49[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
N6/3 - in IOR51[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
P6/3 - in IOR53[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
T6/3 - in IOR53[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2