Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Programs\Gowin\Gowin_V1.9.9.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v
D:\Programs\Gowin\Gowin_V1.9.9.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v
D:\Programs\Gowin\Gowin_V1.9.9.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v
D:\Programs\Gowin\Gowin_V1.9.9.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v
D:\Programs\Gowin\Gowin_V1.9.9.01_x64\IDE\data\ipcores\GAO\GW_CON\gw_con_top.v
D:\Programs\Gowin\Gowin_V1.9.9.01_x64\IDE\data\ipcores\gw_jtag.v
F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\DSI_Test_Pattern_5a25\fpga_proj\impl\gao\gw_gao_top.v
GowinSynthesis Constraints File ---
Tool Version V1.9.9.01 (64-bit)
Part Number GW5A-LV25UG324ES
Device GW5A-25
Device Version A
Created Time Wed Mar 6 13:47:44 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module gw_gao
Synthesis Process Running parser:
    CPU time = 0h 0m 0.312s, Elapsed time = 0h 0m 0.377s, Peak memory usage = 115.008MB
Running netlist conversion:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 115.008MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.037s, Peak memory usage = 115.008MB
    Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.017s, Peak memory usage = 115.008MB
    Optimizing Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.04s, Peak memory usage = 115.008MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 115.008MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 115.008MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 115.008MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 115.008MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.031s, Peak memory usage = 115.008MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 115.008MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 115.008MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 142.281MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.046s, Peak memory usage = 142.281MB
Generate output files:
    CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.188s, Peak memory usage = 142.281MB
Total Time and Memory Usage CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 142.281MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 74
I/O Buf 74
    IBUF 73
    OBUF 1
Register 591
    DFFRE 1
    DFFPE 36
    DFFCE 554
LUT 598
    LUT2 78
    LUT3 117
    LUT4 403
MUX 1
    MUX16 1
ALU 14
    ALU 14
INV 4
    INV 4
BSRAM 8
    SDPX9B 8
Black Box 1
    GW_JTAG 1

Resource Utilization Summary

Resource Usage Utilization
Logic 624(610 LUT, 14 ALU) / 23040 3%
Register 591 / 23685 3%
  --Register as Latch 0 / 23685 0%
  --Register as FF 591 / 23685 3%
BSRAM 8 / 56 15%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
byte_clk Base 10.000 100.0 0.000 5.000 byte_clk_ibuf/I
u_icon_top/n19_6 Base 10.000 100.0 0.000 5.000 u_icon_top/n19_s2/O
u_la0_top/n15_6 Base 10.000 100.0 0.000 5.000 u_la0_top/n15_s2/O

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 byte_clk 100.000(MHz) 189.125(MHz) 6 TOP
2 u_icon_top/n19_6 100.000(MHz) 1217.656(MHz) 1 TOP
3 u_la0_top/n15_6 100.000(MHz) 1217.656(MHz) 1 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 4.713
Data Arrival Time 6.281
Data Required Time 10.994
From u_la0_top/capture_window_sel_0_s3
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_10_s0
Launch Clk byte_clk[R]
Latch Clk byte_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 byte_clk
0.000 0.000 tCL RR 1 byte_clk_ibuf/I
0.683 0.683 tINS RR 245 byte_clk_ibuf/O
1.058 0.375 tNET RR 1 u_la0_top/capture_window_sel_0_s3/CLK
1.440 0.382 tC2Q RR 15 u_la0_top/capture_window_sel_0_s3/Q
1.815 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_10_s19/I1
2.331 0.516 tINS RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_10_s19/F
2.706 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_10_s18/I1
3.223 0.516 tINS RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_10_s18/F
3.598 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_10_s17/I0
4.124 0.526 tINS RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_10_s17/F
4.499 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_10_s13/I1
5.015 0.516 tINS RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_10_s13/F
5.390 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_10_s11/I1
5.906 0.516 tINS RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_10_s11/F
6.281 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_10_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 byte_clk
10.000 0.000 tCL RR 1 byte_clk_ibuf/I
10.682 0.683 tINS RR 245 byte_clk_ibuf/O
11.057 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_10_s0/CLK
10.994 -0.064 tSu 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_10_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.683, 64.539%; route: 0.375, 35.461%
Arrival Data Path Delay: cell: 2.591, 49.605%; route: 2.250, 43.073%; tC2Q: 0.382, 7.322%
Required Clock Path Delay: cell: 0.683, 64.539%; route: 0.375, 35.461%

Path 2

Path Summary:
Slack 4.767
Data Arrival Time 6.226
Data Required Time 10.994
From u_la0_top/capture_window_sel_0_s3
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_9_s0
Launch Clk byte_clk[R]
Latch Clk byte_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 byte_clk
0.000 0.000 tCL RR 1 byte_clk_ibuf/I
0.683 0.683 tINS RR 245 byte_clk_ibuf/O
1.058 0.375 tNET RR 1 u_la0_top/capture_window_sel_0_s3/CLK
1.440 0.382 tC2Q RR 15 u_la0_top/capture_window_sel_0_s3/Q
1.815 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s16/I1
2.331 0.516 tINS RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s16/F
2.706 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s15/I1
3.223 0.516 tINS RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s15/F
3.598 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s14/I0
4.124 0.526 tINS RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s14/F
4.499 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s12/I1
5.015 0.516 tINS RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s12/F
5.390 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s10/I2
5.851 0.461 tINS RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s10/F
6.226 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_9_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 byte_clk
10.000 0.000 tCL RR 1 byte_clk_ibuf/I
10.682 0.683 tINS RR 245 byte_clk_ibuf/O
11.057 0.375 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_9_s0/CLK
10.994 -0.064 tSu 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_9_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.683, 64.539%; route: 0.375, 35.461%
Arrival Data Path Delay: cell: 2.536, 49.069%; route: 2.250, 43.531%; tC2Q: 0.382, 7.400%
Required Clock Path Delay: cell: 0.683, 64.539%; route: 0.375, 35.461%

Path 3

Path Summary:
Slack 4.819
Data Arrival Time 5.927
Data Required Time 10.746
From u_la0_top/u_ao_match_0/match_cnt_0_s1
To u_la0_top/triger_level_cnt_0_s1
Launch Clk byte_clk[R]
Latch Clk byte_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 byte_clk
0.000 0.000 tCL RR 1 byte_clk_ibuf/I
0.683 0.683 tINS RR 245 byte_clk_ibuf/O
1.058 0.375 tNET RR 1 u_la0_top/u_ao_match_0/match_cnt_0_s1/CLK
1.440 0.382 tC2Q RR 5 u_la0_top/u_ao_match_0/match_cnt_0_s1/Q
1.815 0.375 tNET RR 1 u_la0_top/u_ao_match_0/n291_s3/I0
2.341 0.526 tINS RR 4 u_la0_top/u_ao_match_0/n291_s3/F
2.716 0.375 tNET RR 1 u_la0_top/u_ao_match_0/n288_s3/I3
2.979 0.262 tINS RR 3 u_la0_top/u_ao_match_0/n288_s3/F
3.354 0.375 tNET RR 1 u_la0_top/u_ao_match_0/n286_s5/I2
3.815 0.461 tINS RR 6 u_la0_top/u_ao_match_0/n286_s5/F
4.190 0.375 tNET RR 1 u_la0_top/n3273_s1/I2
4.651 0.461 tINS RR 3 u_la0_top/n3273_s1/F
5.026 0.375 tNET RR 1 u_la0_top/triger_level_cnt_3_s3/I0
5.552 0.526 tINS RR 4 u_la0_top/triger_level_cnt_3_s3/F
5.927 0.375 tNET RR 1 u_la0_top/triger_level_cnt_0_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 byte_clk
10.000 0.000 tCL RR 1 byte_clk_ibuf/I
10.682 0.683 tINS RR 245 byte_clk_ibuf/O
11.057 0.375 tNET RR 1 u_la0_top/triger_level_cnt_0_s1/CLK
10.746 -0.311 tSu 1 u_la0_top/triger_level_cnt_0_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.683, 64.539%; route: 0.375, 35.461%
Arrival Data Path Delay: cell: 2.237, 45.945%; route: 2.250, 46.201%; tC2Q: 0.382, 7.854%
Required Clock Path Delay: cell: 0.683, 64.539%; route: 0.375, 35.461%

Path 4

Path Summary:
Slack 4.819
Data Arrival Time 5.927
Data Required Time 10.746
From u_la0_top/u_ao_match_0/match_cnt_0_s1
To u_la0_top/triger_level_cnt_1_s1
Launch Clk byte_clk[R]
Latch Clk byte_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 byte_clk
0.000 0.000 tCL RR 1 byte_clk_ibuf/I
0.683 0.683 tINS RR 245 byte_clk_ibuf/O
1.058 0.375 tNET RR 1 u_la0_top/u_ao_match_0/match_cnt_0_s1/CLK
1.440 0.382 tC2Q RR 5 u_la0_top/u_ao_match_0/match_cnt_0_s1/Q
1.815 0.375 tNET RR 1 u_la0_top/u_ao_match_0/n291_s3/I0
2.341 0.526 tINS RR 4 u_la0_top/u_ao_match_0/n291_s3/F
2.716 0.375 tNET RR 1 u_la0_top/u_ao_match_0/n288_s3/I3
2.979 0.262 tINS RR 3 u_la0_top/u_ao_match_0/n288_s3/F
3.354 0.375 tNET RR 1 u_la0_top/u_ao_match_0/n286_s5/I2
3.815 0.461 tINS RR 6 u_la0_top/u_ao_match_0/n286_s5/F
4.190 0.375 tNET RR 1 u_la0_top/n3273_s1/I2
4.651 0.461 tINS RR 3 u_la0_top/n3273_s1/F
5.026 0.375 tNET RR 1 u_la0_top/triger_level_cnt_3_s3/I0
5.552 0.526 tINS RR 4 u_la0_top/triger_level_cnt_3_s3/F
5.927 0.375 tNET RR 1 u_la0_top/triger_level_cnt_1_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 byte_clk
10.000 0.000 tCL RR 1 byte_clk_ibuf/I
10.682 0.683 tINS RR 245 byte_clk_ibuf/O
11.057 0.375 tNET RR 1 u_la0_top/triger_level_cnt_1_s1/CLK
10.746 -0.311 tSu 1 u_la0_top/triger_level_cnt_1_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.683, 64.539%; route: 0.375, 35.461%
Arrival Data Path Delay: cell: 2.237, 45.945%; route: 2.250, 46.201%; tC2Q: 0.382, 7.854%
Required Clock Path Delay: cell: 0.683, 64.539%; route: 0.375, 35.461%

Path 5

Path Summary:
Slack 4.819
Data Arrival Time 5.927
Data Required Time 10.746
From u_la0_top/u_ao_match_0/match_cnt_0_s1
To u_la0_top/triger_level_cnt_2_s1
Launch Clk byte_clk[R]
Latch Clk byte_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 byte_clk
0.000 0.000 tCL RR 1 byte_clk_ibuf/I
0.683 0.683 tINS RR 245 byte_clk_ibuf/O
1.058 0.375 tNET RR 1 u_la0_top/u_ao_match_0/match_cnt_0_s1/CLK
1.440 0.382 tC2Q RR 5 u_la0_top/u_ao_match_0/match_cnt_0_s1/Q
1.815 0.375 tNET RR 1 u_la0_top/u_ao_match_0/n291_s3/I0
2.341 0.526 tINS RR 4 u_la0_top/u_ao_match_0/n291_s3/F
2.716 0.375 tNET RR 1 u_la0_top/u_ao_match_0/n288_s3/I3
2.979 0.262 tINS RR 3 u_la0_top/u_ao_match_0/n288_s3/F
3.354 0.375 tNET RR 1 u_la0_top/u_ao_match_0/n286_s5/I2
3.815 0.461 tINS RR 6 u_la0_top/u_ao_match_0/n286_s5/F
4.190 0.375 tNET RR 1 u_la0_top/n3273_s1/I2
4.651 0.461 tINS RR 3 u_la0_top/n3273_s1/F
5.026 0.375 tNET RR 1 u_la0_top/triger_level_cnt_3_s3/I0
5.552 0.526 tINS RR 4 u_la0_top/triger_level_cnt_3_s3/F
5.927 0.375 tNET RR 1 u_la0_top/triger_level_cnt_2_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 byte_clk
10.000 0.000 tCL RR 1 byte_clk_ibuf/I
10.682 0.683 tINS RR 245 byte_clk_ibuf/O
11.057 0.375 tNET RR 1 u_la0_top/triger_level_cnt_2_s1/CLK
10.746 -0.311 tSu 1 u_la0_top/triger_level_cnt_2_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.683, 64.539%; route: 0.375, 35.461%
Arrival Data Path Delay: cell: 2.237, 45.945%; route: 2.250, 46.201%; tC2Q: 0.382, 7.854%
Required Clock Path Delay: cell: 0.683, 64.539%; route: 0.375, 35.461%