Synthesis Messages

Report Title GowinSynthesis Report
Design File F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\DSI_Test_Pattern_5a25\fpga_proj\src\gowin_mipi_dphy\gowin_mipi_dphy_tx.v
F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\DSI_Test_Pattern_5a25\fpga_proj\src\gowin_pll\gowin_pll.v
F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\DSI_Test_Pattern_5a25\fpga_proj\src\mipi_dsi_tx\mipi_dsi_tx.v
F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\DSI_Test_Pattern_5a25\fpga_proj\src\pixel_to_byte\pixel_to_byte.v
F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\DSI_Test_Pattern_5a25\fpga_proj\src\testpattern.v
F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\DSI_Test_Pattern_5a25\fpga_proj\src\top.v
GowinSynthesis Constraints File ---
Tool Version V1.9.9.01 (64-bit)
Part Number GW5A-LV25UG324ES
Device GW5A-25
Device Version A
Created Time Wed Mar 6 16:51:11 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module DsiTest_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.437s, Elapsed time = 0h 0m 0.408s, Peak memory usage = 619.602MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.034s, Peak memory usage = 619.602MB
    Optimizing Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.029s, Peak memory usage = 619.602MB
    Optimizing Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.05s, Peak memory usage = 619.602MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.021s, Peak memory usage = 619.602MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 619.602MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 619.602MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 619.602MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.043s, Peak memory usage = 619.602MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.015s, Peak memory usage = 619.602MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 619.602MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.531s, Elapsed time = 0h 0m 0.577s, Peak memory usage = 619.602MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.075s, Peak memory usage = 619.602MB
Generate output files:
    CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.212s, Peak memory usage = 619.602MB
Total Time and Memory Usage CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 619.602MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 15
I/O Buf 5
    IBUF 2
    OBUF 3
Register 877
    DFFSE 24
    DFFRE 315
    DFFPE 30
    DFFCE 508
LUT 1600
    LUT2 131
    LUT3 629
    LUT4 840
ALU 58
    ALU 58
INV 16
    INV 16
BSRAM 4
    SDPB 2
    SDPX9B 2
CLOCK 1
    PLLA 1
MIPI_DPHY 1

Resource Utilization Summary

Resource Usage Utilization
Logic 1674(1616 LUT, 58 ALU) / 23040 8%
Register 877 / 23685 4%
  --Register as Latch 0 / 23685 0%
  --Register as FF 877 / 23685 4%
BSRAM 4 / 56 8%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
OSC_50M Base 20.000 50.0 0.000 10.000 OSC_50M_ibuf/I
u_dphy_tx_ip/PLLA_inst/CLKOUT4.default_gen_clk Generated 7.059 141.7 0.000 3.529 OSC_50M_ibuf/I OSC_50M u_dphy_tx_ip/PLLA_inst/CLKOUT4

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 u_dphy_tx_ip/PLLA_inst/CLKOUT4.default_gen_clk 141.667(MHz) 190.840(MHz) 7 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 1.819
Data Arrival Time 6.535
Data Required Time 8.354
From u_p2b/u_p2b/u_mid_buf/rRPtrWsync_3_s0
To u_p2b/u_p2b/u_mid_buf/rFull_s0
Launch Clk u_dphy_tx_ip/PLLA_inst/CLKOUT4.default_gen_clk[R]
Latch Clk u_dphy_tx_ip/PLLA_inst/CLKOUT4.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 u_dphy_tx_ip/PLLA_inst/CLKOUT4.default_gen_clk
0.984 0.984 tCL RR 278 u_dphy_tx_ip/PLLA_inst/CLKOUT4
1.359 0.375 tNET RR 1 u_p2b/u_p2b/u_mid_buf/rRPtrWsync_3_s0/CLK
1.741 0.382 tC2Q RR 1 u_p2b/u_p2b/u_mid_buf/rRPtrWsync_3_s0/Q
2.116 0.375 tNET RR 1 u_p2b/u_p2b/u_mid_buf/wRPtrBinX_3_s0/I0
2.643 0.526 tINS RR 5 u_p2b/u_p2b/u_mid_buf/wRPtrBinX_3_s0/F
3.018 0.375 tNET RR 1 u_p2b/u_p2b/u_mid_buf/wRPtrBinX_2_s0/I1
3.534 0.516 tINS RR 2 u_p2b/u_p2b/u_mid_buf/wRPtrBinX_2_s0/F
3.909 0.375 tNET RR 2 u_p2b/u_p2b/u_mid_buf/n385_s0/I1
4.471 0.562 tINS RF 1 u_p2b/u_p2b/u_mid_buf/n385_s0/COUT
4.471 0.000 tNET FF 2 u_p2b/u_p2b/u_mid_buf/n386_s0/CIN
4.522 0.050 tINS FR 1 u_p2b/u_p2b/u_mid_buf/n386_s0/COUT
4.522 0.000 tNET RR 2 u_p2b/u_p2b/u_mid_buf/n387_s0/CIN
4.572 0.050 tINS RR 1 u_p2b/u_p2b/u_mid_buf/n387_s0/COUT
4.572 0.000 tNET RR 2 u_p2b/u_p2b/u_mid_buf/n388_s0/CIN
4.622 0.050 tINS RR 1 u_p2b/u_p2b/u_mid_buf/n388_s0/COUT
4.997 0.375 tNET RR 1 u_p2b/u_p2b/u_mid_buf/n402_s4/I0
5.523 0.526 tINS RR 1 u_p2b/u_p2b/u_mid_buf/n402_s4/F
5.898 0.375 tNET RR 1 u_p2b/u_p2b/u_mid_buf/n402_s0/I3
6.160 0.262 tINS RR 1 u_p2b/u_p2b/u_mid_buf/n402_s0/F
6.535 0.375 tNET RR 1 u_p2b/u_p2b/u_mid_buf/rFull_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
7.059 0.000 u_dphy_tx_ip/PLLA_inst/CLKOUT4.default_gen_clk
8.043 0.984 tCL RR 278 u_dphy_tx_ip/PLLA_inst/CLKOUT4
8.418 0.375 tNET RR 1 u_p2b/u_p2b/u_mid_buf/rFull_s0/CLK
8.354 -0.064 tSu 1 u_p2b/u_p2b/u_mid_buf/rFull_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 7.059
Logic Level: 7
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 2.544, 49.142%; route: 2.250, 43.468%; tC2Q: 0.382, 7.390%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 2

Path Summary:
Slack 2.633
Data Arrival Time 5.721
Data Required Time 8.354
From u_test_gen/V_cnt_0_s1
To u_test_gen/V_cnt_1_s1
Launch Clk u_dphy_tx_ip/PLLA_inst/CLKOUT4.default_gen_clk[R]
Latch Clk u_dphy_tx_ip/PLLA_inst/CLKOUT4.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 u_dphy_tx_ip/PLLA_inst/CLKOUT4.default_gen_clk
0.984 0.984 tCL RR 278 u_dphy_tx_ip/PLLA_inst/CLKOUT4
1.359 0.375 tNET RR 1 u_test_gen/V_cnt_0_s1/CLK
1.741 0.382 tC2Q RR 6 u_test_gen/V_cnt_0_s1/Q
2.116 0.375 tNET RR 1 u_test_gen/n63_s6/I0
2.643 0.526 tINS RR 1 u_test_gen/n63_s6/F
3.018 0.375 tNET RR 1 u_test_gen/n63_s5/I0
3.544 0.526 tINS RR 1 u_test_gen/n63_s5/F
3.919 0.375 tNET RR 1 u_test_gen/n63_s4/I0
4.445 0.526 tINS RR 12 u_test_gen/n63_s4/F
4.820 0.375 tNET RR 1 u_test_gen/n73_s2/I0
5.346 0.526 tINS RR 1 u_test_gen/n73_s2/F
5.721 0.375 tNET RR 1 u_test_gen/V_cnt_1_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
7.059 0.000 u_dphy_tx_ip/PLLA_inst/CLKOUT4.default_gen_clk
8.043 0.984 tCL RR 278 u_dphy_tx_ip/PLLA_inst/CLKOUT4
8.418 0.375 tNET RR 1 u_test_gen/V_cnt_1_s1/CLK
8.354 -0.064 tSu 1 u_test_gen/V_cnt_1_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 7.059
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 2.105, 48.252%; route: 1.875, 42.980%; tC2Q: 0.382, 8.768%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 3

Path Summary:
Slack 2.633
Data Arrival Time 5.721
Data Required Time 8.354
From u_test_gen/V_cnt_0_s1
To u_test_gen/V_cnt_2_s1
Launch Clk u_dphy_tx_ip/PLLA_inst/CLKOUT4.default_gen_clk[R]
Latch Clk u_dphy_tx_ip/PLLA_inst/CLKOUT4.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 u_dphy_tx_ip/PLLA_inst/CLKOUT4.default_gen_clk
0.984 0.984 tCL RR 278 u_dphy_tx_ip/PLLA_inst/CLKOUT4
1.359 0.375 tNET RR 1 u_test_gen/V_cnt_0_s1/CLK
1.741 0.382 tC2Q RR 6 u_test_gen/V_cnt_0_s1/Q
2.116 0.375 tNET RR 1 u_test_gen/n63_s6/I0
2.643 0.526 tINS RR 1 u_test_gen/n63_s6/F
3.018 0.375 tNET RR 1 u_test_gen/n63_s5/I0
3.544 0.526 tINS RR 1 u_test_gen/n63_s5/F
3.919 0.375 tNET RR 1 u_test_gen/n63_s4/I0
4.445 0.526 tINS RR 12 u_test_gen/n63_s4/F
4.820 0.375 tNET RR 1 u_test_gen/n72_s4/I0
5.346 0.526 tINS RR 1 u_test_gen/n72_s4/F
5.721 0.375 tNET RR 1 u_test_gen/V_cnt_2_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
7.059 0.000 u_dphy_tx_ip/PLLA_inst/CLKOUT4.default_gen_clk
8.043 0.984 tCL RR 278 u_dphy_tx_ip/PLLA_inst/CLKOUT4
8.418 0.375 tNET RR 1 u_test_gen/V_cnt_2_s1/CLK
8.354 -0.064 tSu 1 u_test_gen/V_cnt_2_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 7.059
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 2.105, 48.252%; route: 1.875, 42.980%; tC2Q: 0.382, 8.768%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 4

Path Summary:
Slack 2.633
Data Arrival Time 5.721
Data Required Time 8.354
From u_test_gen/V_cnt_0_s1
To u_test_gen/V_cnt_4_s1
Launch Clk u_dphy_tx_ip/PLLA_inst/CLKOUT4.default_gen_clk[R]
Latch Clk u_dphy_tx_ip/PLLA_inst/CLKOUT4.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 u_dphy_tx_ip/PLLA_inst/CLKOUT4.default_gen_clk
0.984 0.984 tCL RR 278 u_dphy_tx_ip/PLLA_inst/CLKOUT4
1.359 0.375 tNET RR 1 u_test_gen/V_cnt_0_s1/CLK
1.741 0.382 tC2Q RR 6 u_test_gen/V_cnt_0_s1/Q
2.116 0.375 tNET RR 1 u_test_gen/n63_s6/I0
2.643 0.526 tINS RR 1 u_test_gen/n63_s6/F
3.018 0.375 tNET RR 1 u_test_gen/n63_s5/I0
3.544 0.526 tINS RR 1 u_test_gen/n63_s5/F
3.919 0.375 tNET RR 1 u_test_gen/n63_s4/I0
4.445 0.526 tINS RR 12 u_test_gen/n63_s4/F
4.820 0.375 tNET RR 1 u_test_gen/n70_s2/I0
5.346 0.526 tINS RR 1 u_test_gen/n70_s2/F
5.721 0.375 tNET RR 1 u_test_gen/V_cnt_4_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
7.059 0.000 u_dphy_tx_ip/PLLA_inst/CLKOUT4.default_gen_clk
8.043 0.984 tCL RR 278 u_dphy_tx_ip/PLLA_inst/CLKOUT4
8.418 0.375 tNET RR 1 u_test_gen/V_cnt_4_s1/CLK
8.354 -0.064 tSu 1 u_test_gen/V_cnt_4_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 7.059
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 2.105, 48.252%; route: 1.875, 42.980%; tC2Q: 0.382, 8.768%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 5

Path Summary:
Slack 2.633
Data Arrival Time 5.721
Data Required Time 8.354
From u_test_gen/V_cnt_0_s1
To u_test_gen/V_cnt_5_s1
Launch Clk u_dphy_tx_ip/PLLA_inst/CLKOUT4.default_gen_clk[R]
Latch Clk u_dphy_tx_ip/PLLA_inst/CLKOUT4.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 u_dphy_tx_ip/PLLA_inst/CLKOUT4.default_gen_clk
0.984 0.984 tCL RR 278 u_dphy_tx_ip/PLLA_inst/CLKOUT4
1.359 0.375 tNET RR 1 u_test_gen/V_cnt_0_s1/CLK
1.741 0.382 tC2Q RR 6 u_test_gen/V_cnt_0_s1/Q
2.116 0.375 tNET RR 1 u_test_gen/n63_s6/I0
2.643 0.526 tINS RR 1 u_test_gen/n63_s6/F
3.018 0.375 tNET RR 1 u_test_gen/n63_s5/I0
3.544 0.526 tINS RR 1 u_test_gen/n63_s5/F
3.919 0.375 tNET RR 1 u_test_gen/n63_s4/I0
4.445 0.526 tINS RR 12 u_test_gen/n63_s4/F
4.820 0.375 tNET RR 1 u_test_gen/n69_s4/I0
5.346 0.526 tINS RR 1 u_test_gen/n69_s4/F
5.721 0.375 tNET RR 1 u_test_gen/V_cnt_5_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
7.059 0.000 u_dphy_tx_ip/PLLA_inst/CLKOUT4.default_gen_clk
8.043 0.984 tCL RR 278 u_dphy_tx_ip/PLLA_inst/CLKOUT4
8.418 0.375 tNET RR 1 u_test_gen/V_cnt_5_s1/CLK
8.354 -0.064 tSu 1 u_test_gen/V_cnt_5_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 7.059
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 2.105, 48.252%; route: 1.875, 42.980%; tC2Q: 0.382, 8.768%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%