Timing Messages
Report Title | Timing Analysis Report |
Design File | F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\DSI_Test_Pattern_5a25\fpga_proj\impl\gwsynthesis\DSI_Test_Pattern_5a25.vg |
Physical Constraints File | F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\DSI_Test_Pattern_5a25\fpga_proj\src\DK_START_GW5A_LV25UG324_V1P1.cst |
Timing Constraint File | F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\DSI_Test_Pattern_5a25\fpga_proj\src\dsi_test.sdc |
Tool Version | V1.9.9.01 (64-bit) |
Part Number | GW5A-LV25UG324ES |
Device | GW5A-25 |
Device Version | A |
Created Time | Wed Mar 6 16:51:23 2024 |
Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved. |
Timing Summaries
STA Tool Run Summary:
Setup Delay Model | Slow 0.855V 0C ES |
Hold Delay Model | Fast 0.945V 85C ES |
Numbers of Paths Analyzed | 4092 |
Numbers of Endpoints Analyzed | 4934 |
Numbers of Falling Endpoints | 3 |
Numbers of Setup Violated Endpoints | 0 |
Numbers of Hold Violated Endpoints | 0 |
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Objects |
---|---|---|---|---|---|---|---|---|
clk_50 | Base | 20.000 | 50.000 | 0.000 | 10.000 | OSC_50M | ||
byte_clk | Base | 9.412 | 106.247 | 0.000 | 4.706 | byte_clk | ||
pixel_clk | Generated | 7.059 | 141.667 | 0.000 | 3.529 | OSC_50M | clk_50 | pixel_clk |
tck_pad_i | Base | 50.000 | 20.000 | 0.000 | 25.000 | tck_ibuf/I | ||
u_dphy_tx_ip/PLLA_inst/CLKOUT0.default_gen_clk | Generated | 1.176 | 850.000 | 0.000 | 0.588 | OSC_50M_ibuf/I | clk_50 | u_dphy_tx_ip/PLLA_inst/CLKOUT0 |
u_dphy_tx_ip/PLLA_inst/CLKOUT1.default_gen_clk | Generated | 1.176 | 850.000 | 0.000 | 0.588 | OSC_50M_ibuf/I | clk_50 | u_dphy_tx_ip/PLLA_inst/CLKOUT1 |
u_dphy_tx_ip/PLLA_inst/CLKOUT2.default_gen_clk | Generated | 1.176 | 850.000 | 0.000 | 0.588 | OSC_50M_ibuf/I | clk_50 | u_dphy_tx_ip/PLLA_inst/CLKOUT2 |
u_dphy_tx_ip/PLLA_inst/CLKOUT3.default_gen_clk | Generated | 1.176 | 850.000 | 0.000 | 0.588 | OSC_50M_ibuf/I | clk_50 | u_dphy_tx_ip/PLLA_inst/CLKOUT3 |
Max Frequency Summary:
NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | byte_clk | 106.247(MHz) | 109.390(MHz) | 6 | TOP |
2 | pixel_clk | 141.667(MHz) | 164.229(MHz) | 7 | TOP |
3 | tck_pad_i | 20.000(MHz) | 94.462(MHz) | 5 | TOP |
No timing paths to get frequency of clk_50!
No timing paths to get frequency of u_dphy_tx_ip/PLLA_inst/CLKOUT0.default_gen_clk!
No timing paths to get frequency of u_dphy_tx_ip/PLLA_inst/CLKOUT1.default_gen_clk!
No timing paths to get frequency of u_dphy_tx_ip/PLLA_inst/CLKOUT2.default_gen_clk!
No timing paths to get frequency of u_dphy_tx_ip/PLLA_inst/CLKOUT3.default_gen_clk!
Total Negative Slack Summary:
Clock Name | Analysis Type | Endpoints TNS | Number of Endpoints |
---|---|---|---|
clk_50 | Setup | 0.000 | 0 |
clk_50 | Hold | 0.000 | 0 |
byte_clk | Setup | 0.000 | 0 |
byte_clk | Hold | 0.000 | 0 |
pixel_clk | Setup | 0.000 | 0 |
pixel_clk | Hold | 0.000 | 0 |
tck_pad_i | Setup | 0.000 | 0 |
tck_pad_i | Hold | 0.000 | 0 |
u_dphy_tx_ip/PLLA_inst/CLKOUT0.default_gen_clk | Setup | 0.000 | 0 |
u_dphy_tx_ip/PLLA_inst/CLKOUT0.default_gen_clk | Hold | 0.000 | 0 |
u_dphy_tx_ip/PLLA_inst/CLKOUT1.default_gen_clk | Setup | 0.000 | 0 |
u_dphy_tx_ip/PLLA_inst/CLKOUT1.default_gen_clk | Hold | 0.000 | 0 |
u_dphy_tx_ip/PLLA_inst/CLKOUT2.default_gen_clk | Setup | 0.000 | 0 |
u_dphy_tx_ip/PLLA_inst/CLKOUT2.default_gen_clk | Hold | 0.000 | 0 |
u_dphy_tx_ip/PLLA_inst/CLKOUT3.default_gen_clk | Setup | 0.000 | 0 |
u_dphy_tx_ip/PLLA_inst/CLKOUT3.default_gen_clk | Hold | 0.000 | 0 |
Timing Details
Path Slacks Table:
Setup Paths Table
Setup Paths Table[1]:
Report Command:report_timing -setup -from_clock [get_clocks {pixel_clk}] -max_paths 20 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 0.970 | u_p2b/u_p2b_0/u_mid_buf/rRPtrWsync_4_s0/Q | u_p2b/u_p2b_0/u_mid_buf/rFull_s0/D | pixel_clk:[R] | pixel_clk:[R] | 7.059 | 0.017 | 6.009 |
2 | 1.581 | u_test_gen/De_hcnt_1_s3/Q | u_test_gen/Data_tmp_0_s1/D | pixel_clk:[R] | pixel_clk:[R] | 7.059 | -0.029 | 5.443 |
3 | 1.591 | u_test_gen/De_hcnt_1_s3/Q | u_test_gen/Data_tmp_2_s1/D | pixel_clk:[R] | pixel_clk:[R] | 7.059 | -0.029 | 5.433 |
4 | 1.596 | u_test_gen/De_hcnt_1_s3/Q | u_test_gen/Data_tmp_6_s1/D | pixel_clk:[R] | pixel_clk:[R] | 7.059 | -0.029 | 5.428 |
5 | 1.646 | u_test_gen/De_hcnt_1_s3/Q | u_test_gen/Data_tmp_4_s1/D | pixel_clk:[R] | pixel_clk:[R] | 7.059 | -0.029 | 5.378 |
6 | 1.974 | u_test_gen/De_hcnt_1_s3/Q | u_test_gen/Data_tmp_8_s1/D | pixel_clk:[R] | pixel_clk:[R] | 7.059 | -0.031 | 5.053 |
7 | 1.974 | u_test_gen/De_hcnt_1_s3/Q | u_test_gen/Data_tmp_12_s1/D | pixel_clk:[R] | pixel_clk:[R] | 7.059 | -0.031 | 5.053 |
8 | 2.052 | u_test_gen/De_hcnt_1_s3/Q | u_test_gen/Data_tmp_15_s1/D | pixel_clk:[R] | pixel_clk:[R] | 7.059 | -0.038 | 4.981 |
9 | 2.366 | u_test_gen/De_hcnt_1_s3/Q | u_test_gen/Data_tmp_5_s1/D | pixel_clk:[R] | pixel_clk:[R] | 7.059 | -0.031 | 4.660 |
10 | 2.372 | u_test_gen/De_hcnt_1_s3/Q | u_test_gen/Data_tmp_10_s1/D | pixel_clk:[R] | pixel_clk:[R] | 7.059 | -0.031 | 4.654 |
11 | 2.372 | u_test_gen/De_hcnt_1_s3/Q | u_test_gen/Data_tmp_14_s1/D | pixel_clk:[R] | pixel_clk:[R] | 7.059 | -0.031 | 4.654 |
12 | 2.376 | u_p2b/u_p2b_0/u_mid_buf/rWPtrBin_0_s0/Q | u_p2b/u_p2b_0/u_mid_buf/rWPtrGray_5_s0/D | pixel_clk:[R] | pixel_clk:[R] | 7.059 | -0.031 | 4.650 |
13 | 2.382 | u_test_gen/De_hcnt_1_s3/Q | u_test_gen/Data_tmp_13_s1/D | pixel_clk:[R] | pixel_clk:[R] | 7.059 | -0.040 | 4.654 |
14 | 2.499 | u_test_gen/De_hcnt_1_s3/Q | u_test_gen/De_hcnt_9_s1/D | pixel_clk:[R] | pixel_clk:[R] | 7.059 | -0.017 | 4.513 |
15 | 2.505 | u_p2b/u_p2b_0/u_mid_buf/rWPtrBin_0_s0/Q | u_p2b/u_p2b_0/u_mid_buf/rWPtrGray_6_s0/D | pixel_clk:[R] | pixel_clk:[R] | 7.059 | -0.031 | 4.521 |
16 | 2.545 | u_test_gen/De_hcnt_1_s3/Q | u_test_gen/De_hcnt_8_s3/D | pixel_clk:[R] | pixel_clk:[R] | 7.059 | -0.017 | 4.466 |
17 | 2.566 | u_test_gen/De_hcnt_1_s3/Q | u_test_gen/Data_tmp_11_s1/D | pixel_clk:[R] | pixel_clk:[R] | 7.059 | -0.031 | 4.460 |
18 | 2.621 | u_test_gen/H_cnt_3_s0/Q | u_test_gen/V_cnt_11_s1/D | pixel_clk:[R] | pixel_clk:[R] | 7.059 | 0.011 | 4.364 |
19 | 2.621 | u_test_gen/H_cnt_3_s0/Q | u_test_gen/V_cnt_4_s1/D | pixel_clk:[R] | pixel_clk:[R] | 7.059 | 0.011 | 4.364 |
20 | 2.621 | u_test_gen/H_cnt_3_s0/Q | u_test_gen/V_cnt_5_s1/D | pixel_clk:[R] | pixel_clk:[R] | 7.059 | 0.011 | 4.364 |
Setup Paths Table[2]:
Report Command:report_timing -setup -from_clock [get_clocks {byte_clk}] -max_paths 20 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 0.270 | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rRdOffset_6_s1/D | byte_clk:[R] | byte_clk:[R] | 9.412 | 0.000 | 9.078 |
2 | 0.914 | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rWrOffset_7_s1/D | byte_clk:[R] | byte_clk:[R] | 9.412 | 0.000 | 8.434 |
3 | 0.916 | u_la0_top/u_ao_match_3/matched_s1/Q | u_la0_top/u_ao_match_0/match_cnt_3_s1/CE | byte_clk:[R] | byte_clk:[R] | 9.412 | 0.000 | 8.185 |
4 | 0.938 | u_la0_top/u_ao_match_3/matched_s1/Q | u_la0_top/u_ao_match_0/matched_s1/CE | byte_clk:[R] | byte_clk:[R] | 9.412 | 0.000 | 8.162 |
5 | 0.950 | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_4_s1/D | byte_clk:[R] | byte_clk:[R] | 9.412 | 0.000 | 8.398 |
6 | 0.957 | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_7_s1/D | byte_clk:[R] | byte_clk:[R] | 9.412 | 0.000 | 8.391 |
7 | 1.057 | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rWrOffset_9_s1/D | byte_clk:[R] | byte_clk:[R] | 9.412 | 0.010 | 8.281 |
8 | 1.095 | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rWrOffset_8_s1/D | byte_clk:[R] | byte_clk:[R] | 9.412 | 0.010 | 8.244 |
9 | 1.097 | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rRdOffset_5_s1/D | byte_clk:[R] | byte_clk:[R] | 9.412 | -0.032 | 8.283 |
10 | 1.116 | u_la0_top/u_ao_match_3/matched_s1/Q | u_la0_top/u_ao_match_0/match_cnt_1_s1/CE | byte_clk:[R] | byte_clk:[R] | 9.412 | 0.000 | 7.985 |
11 | 1.195 | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rRdOffset_9_s1/D | byte_clk:[R] | byte_clk:[R] | 9.412 | -0.034 | 8.188 |
12 | 1.247 | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_10_s1/D | byte_clk:[R] | byte_clk:[R] | 9.412 | -0.009 | 8.110 |
13 | 1.250 | u_la0_top/u_ao_match_3/matched_s1/Q | u_la0_top/u_ao_match_3/match_cnt_1_s1/CE | byte_clk:[R] | byte_clk:[R] | 9.412 | 0.000 | 7.851 |
14 | 1.273 | u_la0_top/u_ao_match_3/matched_s1/Q | u_la0_top/u_ao_match_0/match_cnt_0_s1/CE | byte_clk:[R] | byte_clk:[R] | 9.412 | 0.000 | 7.827 |
15 | 1.310 | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_8_s1/D | byte_clk:[R] | byte_clk:[R] | 9.412 | 0.000 | 8.038 |
16 | 1.367 | u_la0_top/u_ao_match_3/matched_s1/Q | u_la0_top/u_ao_match_0/match_cnt_7_s1/CE | byte_clk:[R] | byte_clk:[R] | 9.412 | 0.000 | 7.734 |
17 | 1.367 | u_la0_top/u_ao_match_3/matched_s1/Q | u_la0_top/u_ao_match_0/match_cnt_8_s1/CE | byte_clk:[R] | byte_clk:[R] | 9.412 | 0.000 | 7.734 |
18 | 1.392 | u_la0_top/u_ao_match_3/matched_s1/Q | u_la0_top/u_ao_match_0/match_cnt_4_s1/CE | byte_clk:[R] | byte_clk:[R] | 9.412 | 0.000 | 7.709 |
19 | 1.394 | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rRdOffset_8_s1/D | byte_clk:[R] | byte_clk:[R] | 9.412 | -0.034 | 7.989 |
20 | 1.398 | u_la0_top/u_ao_match_3/matched_s1/Q | u_la0_top/u_ao_match_3/match_cnt_2_s1/CE | byte_clk:[R] | byte_clk:[R] | 9.412 | 0.000 | 7.703 |
Hold Paths Table
Hold Paths Table[1]:
Report Command:report_timing -hold -from_clock [get_clocks {pixel_clk}] -max_paths 20 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 0.174 | u_p2b/u_p2b_0/mid_data_31_s1/Q | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s/DI[31] | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.006 | 0.416 |
2 | 0.178 | u_p2b/u_p2b_0/mid_data_27_s1/Q | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s/DI[27] | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.011 | 0.416 |
3 | 0.178 | u_p2b/u_p2b_0/mid_data_19_s1/Q | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s/DI[19] | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.011 | 0.416 |
4 | 0.192 | u_p2b/u_p2b_0/mid_data_11_s1/Q | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s/DI[11] | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.018 | 0.424 |
5 | 0.297 | u_p2b/u_p2b_0/mid_data_10_s1/Q | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s/DI[10] | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.011 | 0.535 |
6 | 0.300 | u_p2b/u_p2b_0/mid_data_15_s1/Q | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s/DI[15] | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.013 | 0.536 |
7 | 0.305 | u_p2b/u_p2b_0/mid_data_24_s1/Q | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s/DI[24] | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.018 | 0.536 |
8 | 0.312 | u_p2b/u_p2b_0/mid_data_3_s1/Q | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s/DI[3] | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.018 | 0.544 |
9 | 0.316 | u_p2b/u_p2b_0/u_mid_buf/rWPtrBin_5_s0/Q | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s/ADA[10] | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.011 | 0.422 |
10 | 0.343 | u_p2b/u_p2b_0/mid_data_23_s1/Q | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s/DI[23] | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.006 | 0.586 |
11 | 0.351 | u_p2b/u_p2b_0/mid_data_4_s1/Q | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s/DI[4] | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.006 | 0.594 |
12 | 0.355 | u_p2b/u_p2b_0/mid_data_7_s1/Q | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s/DI[7] | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.013 | 0.591 |
13 | 0.356 | u_p2b/u_p2b_0/mid_data_20_s1/Q | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s/DI[20] | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.011 | 0.594 |
14 | 0.371 | u_p2b/u_p2b_0/u_mid_buf/rWPtrBin_2_s0/Q | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s/ADA[7] | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.013 | 0.476 |
15 | 0.371 | u_p2b/u_p2b_0/mid_data_29_s1/Q | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s/DI[29] | pixel_clk:[R] | pixel_clk:[R] | 0.000 | -0.013 | 0.632 |
16 | 0.374 | u_p2b/u_p2b_0/mid_data_25_s1/Q | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s/DI[25] | pixel_clk:[R] | pixel_clk:[R] | 0.000 | -0.018 | 0.640 |
17 | 0.374 | u_p2b/u_p2b_0/u_mid_buf/rWPtrGray_0_s1/Q | u_p2b/u_p2b_0/u_mid_buf/rWPtrGray_0_s1/D | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.000 | 0.375 |
18 | 0.374 | u_test_gen/De_hcnt_4_s3/Q | u_test_gen/De_hcnt_4_s3/D | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.000 | 0.375 |
19 | 0.374 | u_test_gen/De_hcnt_10_s3/Q | u_test_gen/De_hcnt_10_s3/D | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.000 | 0.375 |
20 | 0.374 | u_test_gen/De_vcnt_2_s1/Q | u_test_gen/De_vcnt_2_s1/D | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.000 | 0.375 |
Hold Paths Table[2]:
Report Command:report_timing -hold -from_clock [get_clocks {byte_clk}] -max_paths 20 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 0.068 | u_dsi_tx/u_tx/u_dsi_tx/rHsd_30_s0/Q | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DI[12] | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.011 | 0.306 |
2 | 0.068 | u_dsi_tx/u_tx/u_dsi_tx/rHsd_29_s0/Q | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DI[11] | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.011 | 0.306 |
3 | 0.151 | u_la0_top/u_ao_mem_ctrl/data_reg_0_s0/Q | u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[0] | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.400 |
4 | 0.167 | u_la0_top/u_ao_mem_ctrl/data_reg_56_s0/Q | u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/DI[2] | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.416 |
5 | 0.193 | u_dsi_tx/u_tx/u_dsi_tx/rHsd_27_s0/Q | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DI[9] | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.015 | 0.426 |
6 | 0.217 | u_la0_top/u_ao_mem_ctrl/data_reg_59_s0/Q | u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/DI[5] | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.466 |
7 | 0.240 | u_dsi_tx/u_tx/u_dsi_tx/rHsd_28_s0/Q | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DI[10] | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.013 | 0.476 |
8 | 0.261 | u_la0_top/u_ao_mem_ctrl/data_reg_61_s0/Q | u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/DI[7] | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.510 |
9 | 0.270 | u_la0_top/u_ao_mem_ctrl/data_reg_41_s0/Q | u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/DI[5] | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.519 |
10 | 0.270 | u_la0_top/u_ao_mem_ctrl/data_reg_39_s0/Q | u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/DI[3] | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.519 |
11 | 0.271 | u_la0_top/u_ao_mem_ctrl/data_reg_40_s0/Q | u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/DI[4] | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.520 |
12 | 0.290 | u_la0_top/u_ao_mem_ctrl/data_reg_1_s0/Q | u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[1] | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.539 |
13 | 0.295 | u_la0_top/u_ao_mem_ctrl/data_reg_3_s0/Q | u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[3] | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.544 |
14 | 0.297 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/Q | u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/ADA[3] | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.415 |
15 | 0.306 | u_la0_top/u_ao_mem_ctrl/data_reg_26_s0/Q | u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[8] | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.555 |
16 | 0.306 | u_la0_top/u_ao_mem_ctrl/data_reg_24_s0/Q | u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[6] | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.555 |
17 | 0.311 | u_la0_top/u_ao_mem_ctrl/data_reg_54_s0/Q | u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/DI[0] | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.560 |
18 | 0.318 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/Q | u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/ADA[8] | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.436 |
19 | 0.318 | u_la0_top/u_ao_mem_ctrl/data_reg_62_s0/Q | u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/DI[8] | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.000 | 0.567 |
20 | 0.330 | u_dsi_tx/u_tx/u_dsi_tx/rHsd_25_s0/Q | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DI[7] | byte_clk:[R] | byte_clk:[R] | 0.000 | 0.023 | 0.556 |
Recovery Paths Table
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 0.384 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_match_0/match_cnt_2_s1/CLEAR | byte_clk:[F] | byte_clk:[R] | 4.706 | 0.000 | 3.975 |
2 | 0.384 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_match_0/match_cnt_5_s1/CLEAR | byte_clk:[F] | byte_clk:[R] | 4.706 | 0.000 | 3.975 |
3 | 0.384 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_match_0/match_cnt_6_s1/CLEAR | byte_clk:[F] | byte_clk:[R] | 4.706 | 0.000 | 3.975 |
4 | 0.384 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR | byte_clk:[F] | byte_clk:[R] | 4.706 | 0.000 | 3.975 |
5 | 0.384 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR | byte_clk:[F] | byte_clk:[R] | 4.706 | 0.000 | 3.975 |
6 | 0.384 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR | byte_clk:[F] | byte_clk:[R] | 4.706 | 0.000 | 3.975 |
7 | 0.393 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_match_3/match_cnt_10_s1/CLEAR | byte_clk:[F] | byte_clk:[R] | 4.706 | 0.000 | 3.965 |
8 | 0.393 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_match_3/trig_dly_in_0_s0/CLEAR | byte_clk:[F] | byte_clk:[R] | 4.706 | 0.000 | 3.965 |
9 | 0.393 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_mem_ctrl/capture_length_10_s1/CLEAR | byte_clk:[F] | byte_clk:[R] | 4.706 | 0.000 | 3.965 |
10 | 0.393 | u_la0_top/rst_ao_s0/Q | u_la0_top/internal_reg_start_syn_1_s0/CLEAR | byte_clk:[F] | byte_clk:[R] | 4.706 | 0.000 | 3.965 |
11 | 0.654 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_match_0/matched_s1/CLEAR | byte_clk:[F] | byte_clk:[R] | 4.706 | 0.000 | 3.704 |
12 | 0.654 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR | byte_clk:[F] | byte_clk:[R] | 4.706 | 0.000 | 3.704 |
13 | 0.654 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR | byte_clk:[F] | byte_clk:[R] | 4.706 | 0.000 | 3.704 |
14 | 0.654 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR | byte_clk:[F] | byte_clk:[R] | 4.706 | 0.000 | 3.704 |
15 | 0.657 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_match_3/matched_s1/CLEAR | byte_clk:[F] | byte_clk:[R] | 4.706 | 0.000 | 3.702 |
16 | 0.657 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_match_0/match_sep_s0/CLEAR | byte_clk:[F] | byte_clk:[R] | 4.706 | 0.000 | 3.702 |
17 | 0.657 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR | byte_clk:[F] | byte_clk:[R] | 4.706 | 0.000 | 3.702 |
18 | 0.657 | u_la0_top/rst_ao_s0/Q | u_la0_top/internal_reg_start_dly_1_s0/CLEAR | byte_clk:[F] | byte_clk:[R] | 4.706 | 0.000 | 3.702 |
19 | 0.670 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR | byte_clk:[F] | byte_clk:[R] | 4.706 | 0.000 | 3.688 |
20 | 0.670 | u_la0_top/rst_ao_s0/Q | u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR | byte_clk:[F] | byte_clk:[R] | 4.706 | 0.000 | 3.688 |
21 | 0.674 | u_la0_top/rst_ao_s0/Q | u_la0_top/capture_window_sel_2_s1/CLEAR | byte_clk:[F] | byte_clk:[R] | 4.706 | 0.000 | 3.684 |
22 | 0.674 | u_la0_top/rst_ao_s0/Q | u_la0_top/capture_window_sel_3_s1/CLEAR | byte_clk:[F] | byte_clk:[R] | 4.706 | 0.000 | 3.684 |
23 | 0.674 | u_la0_top/rst_ao_s0/Q | u_la0_top/capture_window_sel_8_s1/CLEAR | byte_clk:[F] | byte_clk:[R] | 4.706 | 0.000 | 3.684 |
24 | 0.674 | u_la0_top/rst_ao_s0/Q | u_la0_top/capture_window_sel_9_s1/CLEAR | byte_clk:[F] | byte_clk:[R] | 4.706 | 0.000 | 3.684 |
25 | 0.677 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_match_3/match_bitwise_pre_reg_1_s0/CLEAR | byte_clk:[F] | byte_clk:[R] | 4.706 | 0.000 | 3.682 |
Removal Paths Table
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 6.847 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR | byte_clk:[F] | byte_clk:[R] | -4.706 | 0.000 | 1.952 |
2 | 6.847 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR | byte_clk:[F] | byte_clk:[R] | -4.706 | 0.000 | 1.952 |
3 | 6.847 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR | byte_clk:[F] | byte_clk:[R] | -4.706 | 0.000 | 1.952 |
4 | 6.857 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_match_3/match_cnt_0_s1/CLEAR | byte_clk:[F] | byte_clk:[R] | -4.706 | 0.000 | 1.962 |
5 | 6.857 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_match_3/match_cnt_5_s1/CLEAR | byte_clk:[F] | byte_clk:[R] | -4.706 | 0.000 | 1.962 |
6 | 6.857 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_match_3/match_cnt_6_s1/CLEAR | byte_clk:[F] | byte_clk:[R] | -4.706 | 0.000 | 1.962 |
7 | 6.857 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_match_3/match_cnt_9_s1/CLEAR | byte_clk:[F] | byte_clk:[R] | -4.706 | 0.000 | 1.962 |
8 | 6.857 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_match_3/match_cnt_11_s1/CLEAR | byte_clk:[F] | byte_clk:[R] | -4.706 | 0.000 | 1.962 |
9 | 6.857 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_match_3/match_sep_s0/CLEAR | byte_clk:[F] | byte_clk:[R] | -4.706 | 0.000 | 1.962 |
10 | 6.857 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_match_3/match_bitwise_pre_reg_0_s0/CLEAR | byte_clk:[F] | byte_clk:[R] | -4.706 | 0.000 | 1.962 |
11 | 6.857 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_match_1/trig_dly_in_0_s0/CLEAR | byte_clk:[F] | byte_clk:[R] | -4.706 | 0.000 | 1.962 |
12 | 6.857 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_match_0/match_cnt_9_s1/CLEAR | byte_clk:[F] | byte_clk:[R] | -4.706 | 0.000 | 1.962 |
13 | 6.857 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR | byte_clk:[F] | byte_clk:[R] | -4.706 | 0.000 | 1.962 |
14 | 6.857 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/CLEAR | byte_clk:[F] | byte_clk:[R] | -4.706 | 0.000 | 1.962 |
15 | 6.857 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR | byte_clk:[F] | byte_clk:[R] | -4.706 | 0.000 | 1.962 |
16 | 6.857 | u_la0_top/rst_ao_s0/Q | u_la0_top/start_reg_s0/CLEAR | byte_clk:[F] | byte_clk:[R] | -4.706 | 0.000 | 1.962 |
17 | 6.865 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR | byte_clk:[F] | byte_clk:[R] | -4.706 | 0.000 | 1.970 |
18 | 6.865 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR | byte_clk:[F] | byte_clk:[R] | -4.706 | 0.000 | 1.970 |
19 | 6.870 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_match_0/match_cnt_7_s1/CLEAR | byte_clk:[F] | byte_clk:[R] | -4.706 | 0.000 | 1.975 |
20 | 6.870 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_match_0/match_cnt_8_s1/CLEAR | byte_clk:[F] | byte_clk:[R] | -4.706 | 0.000 | 1.975 |
21 | 6.870 | u_la0_top/rst_ao_s0/Q | u_la0_top/capture_window_sel_0_s3/CLEAR | byte_clk:[F] | byte_clk:[R] | -4.706 | 0.000 | 1.975 |
22 | 6.870 | u_la0_top/rst_ao_s0/Q | u_la0_top/triger_s0/CLEAR | byte_clk:[F] | byte_clk:[R] | -4.706 | 0.000 | 1.975 |
23 | 6.872 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_match_3/trig_dly_in_1_s0/CLEAR | byte_clk:[F] | byte_clk:[R] | -4.706 | 0.000 | 1.977 |
24 | 6.876 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_match_1/match_sep_s0/CLEAR | byte_clk:[F] | byte_clk:[R] | -4.706 | 0.000 | 1.981 |
25 | 6.876 | u_la0_top/rst_ao_s0/Q | u_la0_top/capture_end_dly_s0/PRESET | byte_clk:[F] | byte_clk:[R] | -4.706 | 0.000 | 1.981 |
Minimum Pulse Width Table:
Number | Slack | Actual Width | Required Width | Type | Clock | Objects |
---|---|---|---|---|---|---|
1 | 2.037 | 3.037 | 1.000 | Low Pulse Width | pixel_clk | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s |
2 | 2.039 | 3.039 | 1.000 | High Pulse Width | pixel_clk | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s |
3 | 2.772 | 3.022 | 0.250 | Low Pulse Width | pixel_clk | running_s0 |
4 | 2.777 | 3.027 | 0.250 | Low Pulse Width | pixel_clk | u_test_gen/H_cnt_6_s0 |
5 | 2.777 | 3.027 | 0.250 | Low Pulse Width | pixel_clk | u_test_gen/O_hs_s0 |
6 | 2.777 | 3.027 | 0.250 | Low Pulse Width | pixel_clk | u_test_gen/H_cnt_5_s0 |
7 | 2.777 | 3.027 | 0.250 | Low Pulse Width | pixel_clk | u_p2b/u_p2b_0/mid_en_s0 |
8 | 2.777 | 3.027 | 0.250 | Low Pulse Width | pixel_clk | u_p2b/u_p2b_0/rCtrlSync_3_s0 |
9 | 2.777 | 3.027 | 0.250 | Low Pulse Width | pixel_clk | u_test_gen/H_cnt_4_s0 |
10 | 2.777 | 3.027 | 0.250 | Low Pulse Width | pixel_clk | u_p2b/u_p2b_0/shift_data_96_s0 |
Timing Report By Analysis Type:
Setup Analysis Report
Setup Analysis Report[1]:
Report Command:report_timing -setup -from_clock [get_clocks {pixel_clk}] -max_paths 20 -max_common_paths 1
Path1
Path Summary:
Slack | 0.970 |
Data Arrival Time | 6.871 |
Data Required Time | 7.840 |
From | u_p2b/u_p2b_0/u_mid_buf/rRPtrWsync_4_s0 |
To | u_p2b/u_p2b_0/u_mid_buf/rFull_s0 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 278 | PLL_L[1] | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
0.862 | 0.862 | tNET | RR | 1 | R11C18[3][A] | u_p2b/u_p2b_0/u_mid_buf/rRPtrWsync_4_s0/CLK |
1.244 | 0.382 | tC2Q | RR | 3 | R11C18[3][A] | u_p2b/u_p2b_0/u_mid_buf/rRPtrWsync_4_s0/Q |
1.657 | 0.412 | tNET | RR | 1 | R12C19[3][B] | u_p2b/u_p2b_0/u_mid_buf/wRPtrBinX_3_s0/I1 |
1.922 | 0.265 | tINS | RR | 5 | R12C19[3][B] | u_p2b/u_p2b_0/u_mid_buf/wRPtrBinX_3_s0/F |
2.629 | 0.708 | tNET | RR | 1 | R11C22[1][B] | u_p2b/u_p2b_0/u_mid_buf/wRPtrBinX_1_s1/I2 |
3.146 | 0.516 | tINS | RR | 1 | R11C22[1][B] | u_p2b/u_p2b_0/u_mid_buf/wRPtrBinX_1_s1/F |
3.979 | 0.834 | tNET | RR | 2 | R9C23[0][B] | u_p2b/u_p2b_0/u_mid_buf/n384_s0/I1 |
4.542 | 0.562 | tINS | RF | 1 | R9C23[0][B] | u_p2b/u_p2b_0/u_mid_buf/n384_s0/COUT |
4.542 | 0.000 | tNET | FF | 2 | R9C23[1][A] | u_p2b/u_p2b_0/u_mid_buf/n385_s0/CIN |
4.592 | 0.050 | tINS | FR | 1 | R9C23[1][A] | u_p2b/u_p2b_0/u_mid_buf/n385_s0/COUT |
4.592 | 0.000 | tNET | RR | 2 | R9C23[1][B] | u_p2b/u_p2b_0/u_mid_buf/n386_s0/CIN |
4.642 | 0.050 | tINS | RR | 1 | R9C23[1][B] | u_p2b/u_p2b_0/u_mid_buf/n386_s0/COUT |
4.642 | 0.000 | tNET | RR | 2 | R9C23[2][A] | u_p2b/u_p2b_0/u_mid_buf/n387_s0/CIN |
4.692 | 0.050 | tINS | RR | 1 | R9C23[2][A] | u_p2b/u_p2b_0/u_mid_buf/n387_s0/COUT |
4.692 | 0.000 | tNET | RR | 2 | R9C23[2][B] | u_p2b/u_p2b_0/u_mid_buf/n388_s0/CIN |
4.742 | 0.050 | tINS | RR | 1 | R9C23[2][B] | u_p2b/u_p2b_0/u_mid_buf/n388_s0/COUT |
5.909 | 1.168 | tNET | RR | 1 | R12C22[3][A] | u_p2b/u_p2b_0/u_mid_buf/n402_s4/I0 |
6.407 | 0.498 | tINS | RR | 1 | R12C22[3][A] | u_p2b/u_p2b_0/u_mid_buf/n402_s4/F |
6.409 | 0.003 | tNET | RR | 1 | R12C22[0][A] | u_p2b/u_p2b_0/u_mid_buf/n402_s0/I3 |
6.871 | 0.461 | tINS | RR | 1 | R12C22[0][A] | u_p2b/u_p2b_0/u_mid_buf/n402_s0/F |
6.871 | 0.000 | tNET | RR | 1 | R12C22[0][A] | u_p2b/u_p2b_0/u_mid_buf/rFull_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.059 | 7.059 | active clock edge time | ||||
7.059 | 0.000 | pixel_clk | ||||
7.059 | 0.000 | tCL | RR | 278 | PLL_L[1] | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
7.904 | 0.845 | tNET | RR | 1 | R12C22[0][A] | u_p2b/u_p2b_0/u_mid_buf/rFull_s0/CLK |
7.840 | -0.064 | tSu | 1 | R12C22[0][A] | u_p2b/u_p2b_0/u_mid_buf/rFull_s0 |
Path Statistics:
Clock Skew | -0.017 |
Setup Relationship | 7.059 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.862, 100.000% |
Arrival Data Path Delay | cell: 2.502, 41.648%; route: 3.124, 51.987%; tC2Q: 0.382, 6.366% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.845, 100.000% |
Path2
Path Summary:
Slack | 1.581 |
Data Arrival Time | 6.288 |
Data Required Time | 7.869 |
From | u_test_gen/De_hcnt_1_s3 |
To | u_test_gen/Data_tmp_0_s1 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 278 | PLL_L[1] | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
0.845 | 0.845 | tNET | RR | 1 | R12C40[1][A] | u_test_gen/De_hcnt_1_s3/CLK |
1.228 | 0.382 | tC2Q | RR | 7 | R12C40[1][A] | u_test_gen/De_hcnt_1_s3/Q |
2.532 | 1.304 | tNET | RR | 1 | R8C38[3][A] | u_test_gen/n1245_s9/I1 |
2.947 | 0.415 | tINS | RR | 2 | R8C38[3][A] | u_test_gen/n1245_s9/F |
3.087 | 0.140 | tNET | RR | 1 | R8C38[0][B] | u_test_gen/n1245_s8/I1 |
3.603 | 0.516 | tINS | RR | 9 | R8C38[0][B] | u_test_gen/n1245_s8/F |
4.023 | 0.420 | tNET | RR | 1 | R8C35[0][B] | u_test_gen/n1245_s5/I1 |
4.484 | 0.461 | tINS | RR | 16 | R8C35[0][B] | u_test_gen/n1245_s5/F |
5.762 | 1.277 | tNET | RR | 1 | R8C31[0][B] | u_test_gen/n1246_s1/I2 |
6.288 | 0.526 | tINS | RR | 1 | R8C31[0][B] | u_test_gen/n1246_s1/F |
6.288 | 0.000 | tNET | RR | 1 | R8C31[0][B] | u_test_gen/Data_tmp_0_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.059 | 7.059 | active clock edge time | ||||
7.059 | 0.000 | pixel_clk | ||||
7.059 | 0.000 | tCL | RR | 278 | PLL_L[1] | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
7.933 | 0.874 | tNET | RR | 1 | R8C31[0][B] | u_test_gen/Data_tmp_0_s1/CLK |
7.869 | -0.064 | tSu | 1 | R8C31[0][B] | u_test_gen/Data_tmp_0_s1 |
Path Statistics:
Clock Skew | 0.029 |
Setup Relationship | 7.059 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.845, 100.000% |
Arrival Data Path Delay | cell: 1.919, 35.255%; route: 3.141, 57.717%; tC2Q: 0.382, 7.028% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.874, 100.000% |
Path3
Path Summary:
Slack | 1.591 |
Data Arrival Time | 6.278 |
Data Required Time | 7.869 |
From | u_test_gen/De_hcnt_1_s3 |
To | u_test_gen/Data_tmp_2_s1 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 278 | PLL_L[1] | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
0.845 | 0.845 | tNET | RR | 1 | R12C40[1][A] | u_test_gen/De_hcnt_1_s3/CLK |
1.228 | 0.382 | tC2Q | RR | 7 | R12C40[1][A] | u_test_gen/De_hcnt_1_s3/Q |
2.532 | 1.304 | tNET | RR | 1 | R8C38[3][A] | u_test_gen/n1245_s9/I1 |
2.947 | 0.415 | tINS | RR | 2 | R8C38[3][A] | u_test_gen/n1245_s9/F |
3.087 | 0.140 | tNET | RR | 1 | R8C38[0][B] | u_test_gen/n1245_s8/I1 |
3.603 | 0.516 | tINS | RR | 9 | R8C38[0][B] | u_test_gen/n1245_s8/F |
4.023 | 0.420 | tNET | RR | 1 | R8C35[0][B] | u_test_gen/n1245_s5/I1 |
4.484 | 0.461 | tINS | RR | 16 | R8C35[0][B] | u_test_gen/n1245_s5/F |
5.762 | 1.277 | tNET | RR | 1 | R8C31[1][B] | u_test_gen/n1244_s1/I2 |
6.278 | 0.516 | tINS | RR | 1 | R8C31[1][B] | u_test_gen/n1244_s1/F |
6.278 | 0.000 | tNET | RR | 1 | R8C31[1][B] | u_test_gen/Data_tmp_2_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.059 | 7.059 | active clock edge time | ||||
7.059 | 0.000 | pixel_clk | ||||
7.059 | 0.000 | tCL | RR | 278 | PLL_L[1] | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
7.933 | 0.874 | tNET | RR | 1 | R8C31[1][B] | u_test_gen/Data_tmp_2_s1/CLK |
7.869 | -0.064 | tSu | 1 | R8C31[1][B] | u_test_gen/Data_tmp_2_s1 |
Path Statistics:
Clock Skew | 0.029 |
Setup Relationship | 7.059 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.845, 100.000% |
Arrival Data Path Delay | cell: 1.909, 35.136%; route: 3.141, 57.823%; tC2Q: 0.382, 7.041% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.874, 100.000% |
Path4
Path Summary:
Slack | 1.596 |
Data Arrival Time | 6.273 |
Data Required Time | 7.869 |
From | u_test_gen/De_hcnt_1_s3 |
To | u_test_gen/Data_tmp_6_s1 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 278 | PLL_L[1] | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
0.845 | 0.845 | tNET | RR | 1 | R12C40[1][A] | u_test_gen/De_hcnt_1_s3/CLK |
1.228 | 0.382 | tC2Q | RR | 7 | R12C40[1][A] | u_test_gen/De_hcnt_1_s3/Q |
2.532 | 1.304 | tNET | RR | 1 | R8C38[3][A] | u_test_gen/n1245_s9/I1 |
2.947 | 0.415 | tINS | RR | 2 | R8C38[3][A] | u_test_gen/n1245_s9/F |
3.087 | 0.140 | tNET | RR | 1 | R8C38[0][B] | u_test_gen/n1245_s8/I1 |
3.603 | 0.516 | tINS | RR | 9 | R8C38[0][B] | u_test_gen/n1245_s8/F |
4.023 | 0.420 | tNET | RR | 1 | R8C35[0][B] | u_test_gen/n1245_s5/I1 |
4.484 | 0.461 | tINS | RR | 16 | R8C35[0][B] | u_test_gen/n1245_s5/F |
5.812 | 1.327 | tNET | RR | 1 | R8C31[2][B] | u_test_gen/n1240_s1/I2 |
6.273 | 0.461 | tINS | RR | 1 | R8C31[2][B] | u_test_gen/n1240_s1/F |
6.273 | 0.000 | tNET | RR | 1 | R8C31[2][B] | u_test_gen/Data_tmp_6_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.059 | 7.059 | active clock edge time | ||||
7.059 | 0.000 | pixel_clk | ||||
7.059 | 0.000 | tCL | RR | 278 | PLL_L[1] | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
7.933 | 0.874 | tNET | RR | 1 | R8C31[2][B] | u_test_gen/Data_tmp_6_s1/CLK |
7.869 | -0.064 | tSu | 1 | R8C31[2][B] | u_test_gen/Data_tmp_6_s1 |
Path Statistics:
Clock Skew | 0.029 |
Setup Relationship | 7.059 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.845, 100.000% |
Arrival Data Path Delay | cell: 1.854, 34.155%; route: 3.191, 58.798%; tC2Q: 0.382, 7.047% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.874, 100.000% |
Path5
Path Summary:
Slack | 1.646 |
Data Arrival Time | 6.223 |
Data Required Time | 7.869 |
From | u_test_gen/De_hcnt_1_s3 |
To | u_test_gen/Data_tmp_4_s1 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 278 | PLL_L[1] | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
0.845 | 0.845 | tNET | RR | 1 | R12C40[1][A] | u_test_gen/De_hcnt_1_s3/CLK |
1.228 | 0.382 | tC2Q | RR | 7 | R12C40[1][A] | u_test_gen/De_hcnt_1_s3/Q |
2.532 | 1.304 | tNET | RR | 1 | R8C38[3][A] | u_test_gen/n1245_s9/I1 |
2.947 | 0.415 | tINS | RR | 2 | R8C38[3][A] | u_test_gen/n1245_s9/F |
3.087 | 0.140 | tNET | RR | 1 | R8C38[0][B] | u_test_gen/n1245_s8/I1 |
3.603 | 0.516 | tINS | RR | 9 | R8C38[0][B] | u_test_gen/n1245_s8/F |
4.023 | 0.420 | tNET | RR | 1 | R8C35[0][B] | u_test_gen/n1245_s5/I1 |
4.484 | 0.461 | tINS | RR | 16 | R8C35[0][B] | u_test_gen/n1245_s5/F |
5.762 | 1.277 | tNET | RR | 1 | R8C31[0][A] | u_test_gen/n1242_s1/I2 |
6.223 | 0.461 | tINS | RR | 1 | R8C31[0][A] | u_test_gen/n1242_s1/F |
6.223 | 0.000 | tNET | RR | 1 | R8C31[0][A] | u_test_gen/Data_tmp_4_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.059 | 7.059 | active clock edge time | ||||
7.059 | 0.000 | pixel_clk | ||||
7.059 | 0.000 | tCL | RR | 278 | PLL_L[1] | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
7.933 | 0.874 | tNET | RR | 1 | R8C31[0][A] | u_test_gen/Data_tmp_4_s1/CLK |
7.869 | -0.064 | tSu | 1 | R8C31[0][A] | u_test_gen/Data_tmp_4_s1 |
Path Statistics:
Clock Skew | 0.029 |
Setup Relationship | 7.059 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.845, 100.000% |
Arrival Data Path Delay | cell: 1.854, 34.472%; route: 3.141, 58.415%; tC2Q: 0.382, 7.113% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.874, 100.000% |
Path6
Path Summary:
Slack | 1.974 |
Data Arrival Time | 5.898 |
Data Required Time | 7.871 |
From | u_test_gen/De_hcnt_1_s3 |
To | u_test_gen/Data_tmp_8_s1 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 278 | PLL_L[1] | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
0.845 | 0.845 | tNET | RR | 1 | R12C40[1][A] | u_test_gen/De_hcnt_1_s3/CLK |
1.228 | 0.382 | tC2Q | RR | 7 | R12C40[1][A] | u_test_gen/De_hcnt_1_s3/Q |
2.532 | 1.304 | tNET | RR | 1 | R8C38[3][A] | u_test_gen/n1245_s9/I1 |
2.947 | 0.415 | tINS | RR | 2 | R8C38[3][A] | u_test_gen/n1245_s9/F |
3.087 | 0.140 | tNET | RR | 1 | R8C38[0][B] | u_test_gen/n1245_s8/I1 |
3.603 | 0.516 | tINS | RR | 9 | R8C38[0][B] | u_test_gen/n1245_s8/F |
4.023 | 0.420 | tNET | RR | 1 | R8C35[0][B] | u_test_gen/n1245_s5/I1 |
4.484 | 0.461 | tINS | RR | 16 | R8C35[0][B] | u_test_gen/n1245_s5/F |
5.372 | 0.887 | tNET | RR | 1 | R9C32[1][B] | u_test_gen/n1238_s2/I2 |
5.898 | 0.526 | tINS | RR | 1 | R9C32[1][B] | u_test_gen/n1238_s2/F |
5.898 | 0.000 | tNET | RR | 1 | R9C32[1][B] | u_test_gen/Data_tmp_8_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.059 | 7.059 | active clock edge time | ||||
7.059 | 0.000 | pixel_clk | ||||
7.059 | 0.000 | tCL | RR | 278 | PLL_L[1] | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
7.935 | 0.876 | tNET | RR | 1 | R9C32[1][B] | u_test_gen/Data_tmp_8_s1/CLK |
7.871 | -0.064 | tSu | 1 | R9C32[1][B] | u_test_gen/Data_tmp_8_s1 |
Path Statistics:
Clock Skew | 0.031 |
Setup Relationship | 7.059 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.845, 100.000% |
Arrival Data Path Delay | cell: 1.919, 37.976%; route: 2.751, 54.453%; tC2Q: 0.382, 7.571% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.876, 100.000% |
Path7
Path Summary:
Slack | 1.974 |
Data Arrival Time | 5.898 |
Data Required Time | 7.871 |
From | u_test_gen/De_hcnt_1_s3 |
To | u_test_gen/Data_tmp_12_s1 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 278 | PLL_L[1] | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
0.845 | 0.845 | tNET | RR | 1 | R12C40[1][A] | u_test_gen/De_hcnt_1_s3/CLK |
1.228 | 0.382 | tC2Q | RR | 7 | R12C40[1][A] | u_test_gen/De_hcnt_1_s3/Q |
2.532 | 1.304 | tNET | RR | 1 | R8C38[3][A] | u_test_gen/n1245_s9/I1 |
2.947 | 0.415 | tINS | RR | 2 | R8C38[3][A] | u_test_gen/n1245_s9/F |
3.087 | 0.140 | tNET | RR | 1 | R8C38[0][B] | u_test_gen/n1245_s8/I1 |
3.603 | 0.516 | tINS | RR | 9 | R8C38[0][B] | u_test_gen/n1245_s8/F |
4.023 | 0.420 | tNET | RR | 1 | R8C35[0][B] | u_test_gen/n1245_s5/I1 |
4.484 | 0.461 | tINS | RR | 16 | R8C35[0][B] | u_test_gen/n1245_s5/F |
5.372 | 0.887 | tNET | RR | 1 | R9C32[0][B] | u_test_gen/n1234_s2/I2 |
5.898 | 0.526 | tINS | RR | 1 | R9C32[0][B] | u_test_gen/n1234_s2/F |
5.898 | 0.000 | tNET | RR | 1 | R9C32[0][B] | u_test_gen/Data_tmp_12_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.059 | 7.059 | active clock edge time | ||||
7.059 | 0.000 | pixel_clk | ||||
7.059 | 0.000 | tCL | RR | 278 | PLL_L[1] | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
7.935 | 0.876 | tNET | RR | 1 | R9C32[0][B] | u_test_gen/Data_tmp_12_s1/CLK |
7.871 | -0.064 | tSu | 1 | R9C32[0][B] | u_test_gen/Data_tmp_12_s1 |
Path Statistics:
Clock Skew | 0.031 |
Setup Relationship | 7.059 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.845, 100.000% |
Arrival Data Path Delay | cell: 1.919, 37.976%; route: 2.751, 54.453%; tC2Q: 0.382, 7.571% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.876, 100.000% |
Path8
Path Summary:
Slack | 2.052 |
Data Arrival Time | 5.827 |
Data Required Time | 7.879 |
From | u_test_gen/De_hcnt_1_s3 |
To | u_test_gen/Data_tmp_15_s1 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 278 | PLL_L[1] | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
0.845 | 0.845 | tNET | RR | 1 | R12C40[1][A] | u_test_gen/De_hcnt_1_s3/CLK |
1.228 | 0.382 | tC2Q | RR | 7 | R12C40[1][A] | u_test_gen/De_hcnt_1_s3/Q |
2.532 | 1.304 | tNET | RR | 1 | R8C38[3][A] | u_test_gen/n1245_s9/I1 |
2.947 | 0.415 | tINS | RR | 2 | R8C38[3][A] | u_test_gen/n1245_s9/F |
3.087 | 0.140 | tNET | RR | 1 | R8C38[0][B] | u_test_gen/n1245_s8/I1 |
3.603 | 0.516 | tINS | RR | 9 | R8C38[0][B] | u_test_gen/n1245_s8/F |
4.023 | 0.420 | tNET | RR | 1 | R8C35[0][B] | u_test_gen/n1245_s5/I1 |
4.484 | 0.461 | tINS | RR | 16 | R8C35[0][B] | u_test_gen/n1245_s5/F |
5.564 | 1.080 | tNET | RR | 1 | R8C32[2][A] | u_test_gen/n1231_s1/I2 |
5.827 | 0.262 | tINS | RR | 1 | R8C32[2][A] | u_test_gen/n1231_s1/F |
5.827 | 0.000 | tNET | RR | 1 | R8C32[2][A] | u_test_gen/Data_tmp_15_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.059 | 7.059 | active clock edge time | ||||
7.059 | 0.000 | pixel_clk | ||||
7.059 | 0.000 | tCL | RR | 278 | PLL_L[1] | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
7.942 | 0.883 | tNET | RR | 1 | R8C32[2][A] | u_test_gen/Data_tmp_15_s1/CLK |
7.879 | -0.064 | tSu | 1 | R8C32[2][A] | u_test_gen/Data_tmp_15_s1 |
Path Statistics:
Clock Skew | 0.038 |
Setup Relationship | 7.059 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.845, 100.000% |
Arrival Data Path Delay | cell: 1.655, 33.225%; route: 2.944, 59.097%; tC2Q: 0.382, 7.679% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.883, 100.000% |
Path9
Path Summary:
Slack | 2.366 |
Data Arrival Time | 5.505 |
Data Required Time | 7.871 |
From | u_test_gen/De_hcnt_1_s3 |
To | u_test_gen/Data_tmp_5_s1 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 278 | PLL_L[1] | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
0.845 | 0.845 | tNET | RR | 1 | R12C40[1][A] | u_test_gen/De_hcnt_1_s3/CLK |
1.228 | 0.382 | tC2Q | RR | 7 | R12C40[1][A] | u_test_gen/De_hcnt_1_s3/Q |
2.532 | 1.304 | tNET | RR | 1 | R8C38[3][A] | u_test_gen/n1245_s9/I1 |
2.947 | 0.415 | tINS | RR | 2 | R8C38[3][A] | u_test_gen/n1245_s9/F |
3.087 | 0.140 | tNET | RR | 1 | R8C38[0][B] | u_test_gen/n1245_s8/I1 |
3.603 | 0.516 | tINS | RR | 9 | R8C38[0][B] | u_test_gen/n1245_s8/F |
4.023 | 0.420 | tNET | RR | 1 | R8C35[0][B] | u_test_gen/n1245_s5/I1 |
4.484 | 0.461 | tINS | RR | 16 | R8C35[0][B] | u_test_gen/n1245_s5/F |
4.979 | 0.495 | tNET | RR | 1 | R9C36[2][B] | u_test_gen/n1241_s2/I2 |
5.505 | 0.526 | tINS | RR | 1 | R9C36[2][B] | u_test_gen/n1241_s2/F |
5.505 | 0.000 | tNET | RR | 1 | R9C36[2][B] | u_test_gen/Data_tmp_5_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.059 | 7.059 | active clock edge time | ||||
7.059 | 0.000 | pixel_clk | ||||
7.059 | 0.000 | tCL | RR | 278 | PLL_L[1] | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
7.935 | 0.876 | tNET | RR | 1 | R9C36[2][B] | u_test_gen/Data_tmp_5_s1/CLK |
7.871 | -0.064 | tSu | 1 | R9C36[2][B] | u_test_gen/Data_tmp_5_s1 |
Path Statistics:
Clock Skew | 0.031 |
Setup Relationship | 7.059 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.845, 100.000% |
Arrival Data Path Delay | cell: 1.919, 41.175%; route: 2.359, 50.617%; tC2Q: 0.382, 8.208% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.876, 100.000% |
Path10
Path Summary:
Slack | 2.372 |
Data Arrival Time | 5.499 |
Data Required Time | 7.871 |
From | u_test_gen/De_hcnt_1_s3 |
To | u_test_gen/Data_tmp_10_s1 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 278 | PLL_L[1] | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
0.845 | 0.845 | tNET | RR | 1 | R12C40[1][A] | u_test_gen/De_hcnt_1_s3/CLK |
1.228 | 0.382 | tC2Q | RR | 7 | R12C40[1][A] | u_test_gen/De_hcnt_1_s3/Q |
2.532 | 1.304 | tNET | RR | 1 | R8C38[3][A] | u_test_gen/n1245_s9/I1 |
2.947 | 0.415 | tINS | RR | 2 | R8C38[3][A] | u_test_gen/n1245_s9/F |
3.087 | 0.140 | tNET | RR | 1 | R8C38[0][B] | u_test_gen/n1245_s8/I1 |
3.603 | 0.516 | tINS | RR | 9 | R8C38[0][B] | u_test_gen/n1245_s8/F |
4.023 | 0.420 | tNET | RR | 1 | R8C35[0][B] | u_test_gen/n1245_s5/I1 |
4.484 | 0.461 | tINS | RR | 16 | R8C35[0][B] | u_test_gen/n1245_s5/F |
5.237 | 0.752 | tNET | RR | 1 | R9C32[1][A] | u_test_gen/n1236_s2/I2 |
5.499 | 0.262 | tINS | RR | 1 | R9C32[1][A] | u_test_gen/n1236_s2/F |
5.499 | 0.000 | tNET | RR | 1 | R9C32[1][A] | u_test_gen/Data_tmp_10_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.059 | 7.059 | active clock edge time | ||||
7.059 | 0.000 | pixel_clk | ||||
7.059 | 0.000 | tCL | RR | 278 | PLL_L[1] | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
7.935 | 0.876 | tNET | RR | 1 | R9C32[1][A] | u_test_gen/Data_tmp_10_s1/CLK |
7.871 | -0.064 | tSu | 1 | R9C32[1][A] | u_test_gen/Data_tmp_10_s1 |
Path Statistics:
Clock Skew | 0.031 |
Setup Relationship | 7.059 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.845, 100.000% |
Arrival Data Path Delay | cell: 1.655, 35.563%; route: 2.616, 56.218%; tC2Q: 0.382, 8.219% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.876, 100.000% |
Path11
Path Summary:
Slack | 2.372 |
Data Arrival Time | 5.499 |
Data Required Time | 7.871 |
From | u_test_gen/De_hcnt_1_s3 |
To | u_test_gen/Data_tmp_14_s1 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 278 | PLL_L[1] | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
0.845 | 0.845 | tNET | RR | 1 | R12C40[1][A] | u_test_gen/De_hcnt_1_s3/CLK |
1.228 | 0.382 | tC2Q | RR | 7 | R12C40[1][A] | u_test_gen/De_hcnt_1_s3/Q |
2.532 | 1.304 | tNET | RR | 1 | R8C38[3][A] | u_test_gen/n1245_s9/I1 |
2.947 | 0.415 | tINS | RR | 2 | R8C38[3][A] | u_test_gen/n1245_s9/F |
3.087 | 0.140 | tNET | RR | 1 | R8C38[0][B] | u_test_gen/n1245_s8/I1 |
3.603 | 0.516 | tINS | RR | 9 | R8C38[0][B] | u_test_gen/n1245_s8/F |
4.023 | 0.420 | tNET | RR | 1 | R8C35[0][B] | u_test_gen/n1245_s5/I1 |
4.484 | 0.461 | tINS | RR | 16 | R8C35[0][B] | u_test_gen/n1245_s5/F |
5.237 | 0.752 | tNET | RR | 1 | R9C32[0][A] | u_test_gen/n1232_s2/I2 |
5.499 | 0.262 | tINS | RR | 1 | R9C32[0][A] | u_test_gen/n1232_s2/F |
5.499 | 0.000 | tNET | RR | 1 | R9C32[0][A] | u_test_gen/Data_tmp_14_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.059 | 7.059 | active clock edge time | ||||
7.059 | 0.000 | pixel_clk | ||||
7.059 | 0.000 | tCL | RR | 278 | PLL_L[1] | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
7.935 | 0.876 | tNET | RR | 1 | R9C32[0][A] | u_test_gen/Data_tmp_14_s1/CLK |
7.871 | -0.064 | tSu | 1 | R9C32[0][A] | u_test_gen/Data_tmp_14_s1 |
Path Statistics:
Clock Skew | 0.031 |
Setup Relationship | 7.059 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.845, 100.000% |
Arrival Data Path Delay | cell: 1.655, 35.563%; route: 2.616, 56.218%; tC2Q: 0.382, 8.219% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.876, 100.000% |
Path12
Path Summary:
Slack | 2.376 |
Data Arrival Time | 5.502 |
Data Required Time | 7.879 |
From | u_p2b/u_p2b_0/u_mid_buf/rWPtrBin_0_s0 |
To | u_p2b/u_p2b_0/u_mid_buf/rWPtrGray_5_s0 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 278 | PLL_L[1] | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
0.852 | 0.852 | tNET | RR | 1 | R11C23[1][B] | u_p2b/u_p2b_0/u_mid_buf/rWPtrBin_0_s0/CLK |
1.235 | 0.382 | tC2Q | RR | 11 | R11C23[1][B] | u_p2b/u_p2b_0/u_mid_buf/rWPtrBin_0_s0/Q |
2.330 | 1.095 | tNET | RR | 1 | R8C23[3][B] | u_p2b/u_p2b_0/u_mid_buf/wWPtrBinNext_4_s4/I0 |
2.595 | 0.265 | tINS | RR | 7 | R8C23[3][B] | u_p2b/u_p2b_0/u_mid_buf/wWPtrBinNext_4_s4/F |
3.339 | 0.744 | tNET | RR | 1 | R11C23[2][A] | u_p2b/u_p2b_0/u_mid_buf/wWPtrBinNext_6_s2/I2 |
3.855 | 0.516 | tINS | RR | 4 | R11C23[2][A] | u_p2b/u_p2b_0/u_mid_buf/wWPtrBinNext_6_s2/F |
4.976 | 1.121 | tNET | RR | 1 | R8C22[1][A] | u_p2b/u_p2b_0/u_mid_buf/wWPtrGrayNext_5_s1/I3 |
5.503 | 0.526 | tINS | RR | 1 | R8C22[1][A] | u_p2b/u_p2b_0/u_mid_buf/wWPtrGrayNext_5_s1/F |
5.503 | 0.000 | tNET | RR | 1 | R8C22[1][A] | u_p2b/u_p2b_0/u_mid_buf/rWPtrGray_5_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.059 | 7.059 | active clock edge time | ||||
7.059 | 0.000 | pixel_clk | ||||
7.059 | 0.000 | tCL | RR | 278 | PLL_L[1] | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
7.942 | 0.883 | tNET | RR | 1 | R8C22[1][A] | u_p2b/u_p2b_0/u_mid_buf/rWPtrGray_5_s0/CLK |
7.879 | -0.064 | tSu | 1 | R8C22[1][A] | u_p2b/u_p2b_0/u_mid_buf/rWPtrGray_5_s0 |
Path Statistics:
Clock Skew | 0.031 |
Setup Relationship | 7.059 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.852, 100.000% |
Arrival Data Path Delay | cell: 1.308, 28.118%; route: 2.960, 63.656%; tC2Q: 0.382, 8.226% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.883, 100.000% |
Path13
Path Summary:
Slack | 2.382 |
Data Arrival Time | 5.499 |
Data Required Time | 7.881 |
From | u_test_gen/De_hcnt_1_s3 |
To | u_test_gen/Data_tmp_13_s1 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 278 | PLL_L[1] | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
0.845 | 0.845 | tNET | RR | 1 | R12C40[1][A] | u_test_gen/De_hcnt_1_s3/CLK |
1.228 | 0.382 | tC2Q | RR | 7 | R12C40[1][A] | u_test_gen/De_hcnt_1_s3/Q |
2.532 | 1.304 | tNET | RR | 1 | R8C38[3][A] | u_test_gen/n1245_s9/I1 |
2.947 | 0.415 | tINS | RR | 2 | R8C38[3][A] | u_test_gen/n1245_s9/F |
3.087 | 0.140 | tNET | RR | 1 | R8C38[0][B] | u_test_gen/n1245_s8/I1 |
3.603 | 0.516 | tINS | RR | 9 | R8C38[0][B] | u_test_gen/n1245_s8/F |
4.023 | 0.420 | tNET | RR | 1 | R8C35[0][B] | u_test_gen/n1245_s5/I1 |
4.484 | 0.461 | tINS | RR | 16 | R8C35[0][B] | u_test_gen/n1245_s5/F |
5.237 | 0.752 | tNET | RR | 1 | R9C33[2][A] | u_test_gen/n1233_s1/I2 |
5.499 | 0.262 | tINS | RR | 1 | R9C33[2][A] | u_test_gen/n1233_s1/F |
5.499 | 0.000 | tNET | RR | 1 | R9C33[2][A] | u_test_gen/Data_tmp_13_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.059 | 7.059 | active clock edge time | ||||
7.059 | 0.000 | pixel_clk | ||||
7.059 | 0.000 | tCL | RR | 278 | PLL_L[1] | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
7.944 | 0.886 | tNET | RR | 1 | R9C33[2][A] | u_test_gen/Data_tmp_13_s1/CLK |
7.881 | -0.064 | tSu | 1 | R9C33[2][A] | u_test_gen/Data_tmp_13_s1 |
Path Statistics:
Clock Skew | 0.040 |
Setup Relationship | 7.059 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.845, 100.000% |
Arrival Data Path Delay | cell: 1.655, 35.563%; route: 2.616, 56.218%; tC2Q: 0.382, 8.219% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.886, 100.000% |
Path14
Path Summary:
Slack | 2.499 |
Data Arrival Time | 5.358 |
Data Required Time | 7.857 |
From | u_test_gen/De_hcnt_1_s3 |
To | u_test_gen/De_hcnt_9_s1 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 278 | PLL_L[1] | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
0.845 | 0.845 | tNET | RR | 1 | R12C40[1][A] | u_test_gen/De_hcnt_1_s3/CLK |
1.228 | 0.382 | tC2Q | RR | 7 | R12C40[1][A] | u_test_gen/De_hcnt_1_s3/Q |
2.534 | 1.306 | tNET | RR | 1 | R8C37[0][A] | u_test_gen/n501_s3/I1 |
2.797 | 0.262 | tINS | RR | 5 | R8C37[0][A] | u_test_gen/n501_s3/F |
3.174 | 0.377 | tNET | RR | 1 | R9C38[0][B] | u_test_gen/n498_s5/I0 |
3.635 | 0.461 | tINS | RR | 4 | R9C38[0][B] | u_test_gen/n498_s5/F |
4.375 | 0.740 | tNET | RR | 1 | R11C40[2][A] | u_test_gen/n497_s3/I1 |
4.892 | 0.516 | tINS | RR | 2 | R11C40[2][A] | u_test_gen/n497_s3/F |
4.897 | 0.005 | tNET | RR | 1 | R11C40[1][B] | u_test_gen/n496_s2/I1 |
5.358 | 0.461 | tINS | RR | 1 | R11C40[1][B] | u_test_gen/n496_s2/F |
5.358 | 0.000 | tNET | RR | 1 | R11C40[1][B] | u_test_gen/De_hcnt_9_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.059 | 7.059 | active clock edge time | ||||
7.059 | 0.000 | pixel_clk | ||||
7.059 | 0.000 | tCL | RR | 278 | PLL_L[1] | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
7.921 | 0.862 | tNET | RR | 1 | R11C40[1][B] | u_test_gen/De_hcnt_9_s1/CLK |
7.857 | -0.064 | tSu | 1 | R11C40[1][B] | u_test_gen/De_hcnt_9_s1 |
Path Statistics:
Clock Skew | 0.017 |
Setup Relationship | 7.059 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.845, 100.000% |
Arrival Data Path Delay | cell: 1.701, 37.701%; route: 2.429, 53.823%; tC2Q: 0.382, 8.476% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.862, 100.000% |
Path15
Path Summary:
Slack | 2.505 |
Data Arrival Time | 5.374 |
Data Required Time | 7.879 |
From | u_p2b/u_p2b_0/u_mid_buf/rWPtrBin_0_s0 |
To | u_p2b/u_p2b_0/u_mid_buf/rWPtrGray_6_s0 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 278 | PLL_L[1] | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
0.852 | 0.852 | tNET | RR | 1 | R11C23[1][B] | u_p2b/u_p2b_0/u_mid_buf/rWPtrBin_0_s0/CLK |
1.235 | 0.382 | tC2Q | RR | 11 | R11C23[1][B] | u_p2b/u_p2b_0/u_mid_buf/rWPtrBin_0_s0/Q |
2.330 | 1.095 | tNET | RR | 1 | R8C23[3][B] | u_p2b/u_p2b_0/u_mid_buf/wWPtrBinNext_4_s4/I0 |
2.595 | 0.265 | tINS | RR | 7 | R8C23[3][B] | u_p2b/u_p2b_0/u_mid_buf/wWPtrBinNext_4_s4/F |
3.339 | 0.744 | tNET | RR | 1 | R11C23[2][A] | u_p2b/u_p2b_0/u_mid_buf/wWPtrBinNext_6_s2/I2 |
3.855 | 0.516 | tINS | RR | 4 | R11C23[2][A] | u_p2b/u_p2b_0/u_mid_buf/wWPtrBinNext_6_s2/F |
5.374 | 1.519 | tNET | RR | 1 | R8C22[1][B] | u_p2b/u_p2b_0/u_mid_buf/rWPtrGray_6_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.059 | 7.059 | active clock edge time | ||||
7.059 | 0.000 | pixel_clk | ||||
7.059 | 0.000 | tCL | RR | 278 | PLL_L[1] | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
7.942 | 0.883 | tNET | RR | 1 | R8C22[1][B] | u_p2b/u_p2b_0/u_mid_buf/rWPtrGray_6_s0/CLK |
7.879 | -0.064 | tSu | 1 | R8C22[1][B] | u_p2b/u_p2b_0/u_mid_buf/rWPtrGray_6_s0 |
Path Statistics:
Clock Skew | 0.031 |
Setup Relationship | 7.059 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.852, 100.000% |
Arrival Data Path Delay | cell: 0.781, 17.280%; route: 3.357, 74.260%; tC2Q: 0.382, 8.460% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.883, 100.000% |
Path16
Path Summary:
Slack | 2.545 |
Data Arrival Time | 5.312 |
Data Required Time | 7.857 |
From | u_test_gen/De_hcnt_1_s3 |
To | u_test_gen/De_hcnt_8_s3 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 278 | PLL_L[1] | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
0.845 | 0.845 | tNET | RR | 1 | R12C40[1][A] | u_test_gen/De_hcnt_1_s3/CLK |
1.228 | 0.382 | tC2Q | RR | 7 | R12C40[1][A] | u_test_gen/De_hcnt_1_s3/Q |
2.534 | 1.306 | tNET | RR | 1 | R8C37[0][A] | u_test_gen/n501_s3/I1 |
2.797 | 0.262 | tINS | RR | 5 | R8C37[0][A] | u_test_gen/n501_s3/F |
3.174 | 0.377 | tNET | RR | 1 | R9C38[0][B] | u_test_gen/n498_s5/I0 |
3.635 | 0.461 | tINS | RR | 4 | R9C38[0][B] | u_test_gen/n498_s5/F |
4.375 | 0.740 | tNET | RR | 1 | R11C40[2][A] | u_test_gen/n497_s3/I1 |
4.892 | 0.516 | tINS | RR | 2 | R11C40[2][A] | u_test_gen/n497_s3/F |
4.897 | 0.005 | tNET | RR | 1 | R11C40[3][A] | u_test_gen/n497_s6/I3 |
5.312 | 0.415 | tINS | RR | 1 | R11C40[3][A] | u_test_gen/n497_s6/F |
5.312 | 0.000 | tNET | RR | 1 | R11C40[3][A] | u_test_gen/De_hcnt_8_s3/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.059 | 7.059 | active clock edge time | ||||
7.059 | 0.000 | pixel_clk | ||||
7.059 | 0.000 | tCL | RR | 278 | PLL_L[1] | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
7.921 | 0.862 | tNET | RR | 1 | R11C40[3][A] | u_test_gen/De_hcnt_8_s3/CLK |
7.857 | -0.064 | tSu | 1 | R11C40[3][A] | u_test_gen/De_hcnt_8_s3 |
Path Statistics:
Clock Skew | 0.017 |
Setup Relationship | 7.059 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.845, 100.000% |
Arrival Data Path Delay | cell: 1.655, 37.056%; route: 2.429, 54.380%; tC2Q: 0.382, 8.564% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.862, 100.000% |
Path17
Path Summary:
Slack | 2.566 |
Data Arrival Time | 5.305 |
Data Required Time | 7.871 |
From | u_test_gen/De_hcnt_1_s3 |
To | u_test_gen/Data_tmp_11_s1 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 278 | PLL_L[1] | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
0.845 | 0.845 | tNET | RR | 1 | R12C40[1][A] | u_test_gen/De_hcnt_1_s3/CLK |
1.228 | 0.382 | tC2Q | RR | 7 | R12C40[1][A] | u_test_gen/De_hcnt_1_s3/Q |
2.532 | 1.304 | tNET | RR | 1 | R8C38[3][A] | u_test_gen/n1245_s9/I1 |
2.947 | 0.415 | tINS | RR | 2 | R8C38[3][A] | u_test_gen/n1245_s9/F |
3.087 | 0.140 | tNET | RR | 1 | R8C38[0][B] | u_test_gen/n1245_s8/I1 |
3.603 | 0.516 | tINS | RR | 9 | R8C38[0][B] | u_test_gen/n1245_s8/F |
4.023 | 0.420 | tNET | RR | 1 | R8C35[0][B] | u_test_gen/n1245_s5/I1 |
4.484 | 0.461 | tINS | RR | 16 | R8C35[0][B] | u_test_gen/n1245_s5/F |
4.844 | 0.360 | tNET | RR | 1 | R9C36[0][B] | u_test_gen/n1235_s1/I2 |
5.305 | 0.461 | tINS | RR | 1 | R9C36[0][B] | u_test_gen/n1235_s1/F |
5.305 | 0.000 | tNET | RR | 1 | R9C36[0][B] | u_test_gen/Data_tmp_11_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.059 | 7.059 | active clock edge time | ||||
7.059 | 0.000 | pixel_clk | ||||
7.059 | 0.000 | tCL | RR | 278 | PLL_L[1] | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
7.935 | 0.876 | tNET | RR | 1 | R9C36[0][B] | u_test_gen/Data_tmp_11_s1/CLK |
7.871 | -0.064 | tSu | 1 | R9C36[0][B] | u_test_gen/Data_tmp_11_s1 |
Path Statistics:
Clock Skew | 0.031 |
Setup Relationship | 7.059 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.845, 100.000% |
Arrival Data Path Delay | cell: 1.854, 41.564%; route: 2.224, 49.860%; tC2Q: 0.382, 8.576% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.876, 100.000% |
Path18
Path Summary:
Slack | 2.621 |
Data Arrival Time | 5.216 |
Data Required Time | 7.837 |
From | u_test_gen/H_cnt_3_s0 |
To | u_test_gen/V_cnt_11_s1 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 278 | PLL_L[1] | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
0.852 | 0.852 | tNET | RR | 1 | R11C35[1][A] | u_test_gen/H_cnt_3_s0/CLK |
1.235 | 0.382 | tC2Q | RR | 4 | R11C35[1][A] | u_test_gen/H_cnt_3_s0/Q |
2.111 | 0.876 | tNET | RR | 1 | R9C34[3][A] | u_test_gen/V_cnt_10_s4/I2 |
2.526 | 0.415 | tINS | RR | 1 | R9C34[3][A] | u_test_gen/V_cnt_10_s4/F |
2.529 | 0.003 | tNET | RR | 1 | R9C34[3][B] | u_test_gen/V_cnt_10_s3/I0 |
2.944 | 0.415 | tINS | RR | 24 | R9C34[3][B] | u_test_gen/V_cnt_10_s3/F |
4.210 | 1.266 | tNET | RR | 1 | R13C34[3][A] | u_test_gen/n63_s4/I3 |
4.500 | 0.290 | tINS | RF | 12 | R13C34[3][A] | u_test_gen/n63_s4/F |
4.690 | 0.190 | tNET | FF | 1 | R13C35[0][A] | u_test_gen/n63_s2/I2 |
5.216 | 0.526 | tINS | FR | 1 | R13C35[0][A] | u_test_gen/n63_s2/F |
5.216 | 0.000 | tNET | RR | 1 | R13C35[0][A] | u_test_gen/V_cnt_11_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.059 | 7.059 | active clock edge time | ||||
7.059 | 0.000 | pixel_clk | ||||
7.059 | 0.000 | tCL | RR | 278 | PLL_L[1] | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
7.901 | 0.842 | tNET | RR | 1 | R13C35[0][A] | u_test_gen/V_cnt_11_s1/CLK |
7.837 | -0.064 | tSu | 1 | R13C35[0][A] | u_test_gen/V_cnt_11_s1 |
Path Statistics:
Clock Skew | -0.011 |
Setup Relationship | 7.059 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.852, 100.000% |
Arrival Data Path Delay | cell: 1.646, 37.726%; route: 2.335, 53.509%; tC2Q: 0.382, 8.765% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.842, 100.000% |
Path19
Path Summary:
Slack | 2.621 |
Data Arrival Time | 5.216 |
Data Required Time | 7.837 |
From | u_test_gen/H_cnt_3_s0 |
To | u_test_gen/V_cnt_4_s1 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 278 | PLL_L[1] | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
0.852 | 0.852 | tNET | RR | 1 | R11C35[1][A] | u_test_gen/H_cnt_3_s0/CLK |
1.235 | 0.382 | tC2Q | RR | 4 | R11C35[1][A] | u_test_gen/H_cnt_3_s0/Q |
2.111 | 0.876 | tNET | RR | 1 | R9C34[3][A] | u_test_gen/V_cnt_10_s4/I2 |
2.526 | 0.415 | tINS | RR | 1 | R9C34[3][A] | u_test_gen/V_cnt_10_s4/F |
2.529 | 0.003 | tNET | RR | 1 | R9C34[3][B] | u_test_gen/V_cnt_10_s3/I0 |
2.944 | 0.415 | tINS | RR | 24 | R9C34[3][B] | u_test_gen/V_cnt_10_s3/F |
4.210 | 1.266 | tNET | RR | 1 | R13C34[3][A] | u_test_gen/n63_s4/I3 |
4.500 | 0.290 | tINS | RF | 12 | R13C34[3][A] | u_test_gen/n63_s4/F |
4.690 | 0.190 | tNET | FF | 1 | R13C35[1][A] | u_test_gen/n70_s2/I0 |
5.216 | 0.526 | tINS | FR | 1 | R13C35[1][A] | u_test_gen/n70_s2/F |
5.216 | 0.000 | tNET | RR | 1 | R13C35[1][A] | u_test_gen/V_cnt_4_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.059 | 7.059 | active clock edge time | ||||
7.059 | 0.000 | pixel_clk | ||||
7.059 | 0.000 | tCL | RR | 278 | PLL_L[1] | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
7.901 | 0.842 | tNET | RR | 1 | R13C35[1][A] | u_test_gen/V_cnt_4_s1/CLK |
7.837 | -0.064 | tSu | 1 | R13C35[1][A] | u_test_gen/V_cnt_4_s1 |
Path Statistics:
Clock Skew | -0.011 |
Setup Relationship | 7.059 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.852, 100.000% |
Arrival Data Path Delay | cell: 1.646, 37.726%; route: 2.335, 53.509%; tC2Q: 0.382, 8.765% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.842, 100.000% |
Path20
Path Summary:
Slack | 2.621 |
Data Arrival Time | 5.216 |
Data Required Time | 7.837 |
From | u_test_gen/H_cnt_3_s0 |
To | u_test_gen/V_cnt_5_s1 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 278 | PLL_L[1] | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
0.852 | 0.852 | tNET | RR | 1 | R11C35[1][A] | u_test_gen/H_cnt_3_s0/CLK |
1.235 | 0.382 | tC2Q | RR | 4 | R11C35[1][A] | u_test_gen/H_cnt_3_s0/Q |
2.111 | 0.876 | tNET | RR | 1 | R9C34[3][A] | u_test_gen/V_cnt_10_s4/I2 |
2.526 | 0.415 | tINS | RR | 1 | R9C34[3][A] | u_test_gen/V_cnt_10_s4/F |
2.529 | 0.003 | tNET | RR | 1 | R9C34[3][B] | u_test_gen/V_cnt_10_s3/I0 |
2.944 | 0.415 | tINS | RR | 24 | R9C34[3][B] | u_test_gen/V_cnt_10_s3/F |
4.210 | 1.266 | tNET | RR | 1 | R13C34[3][A] | u_test_gen/n63_s4/I3 |
4.500 | 0.290 | tINS | RF | 12 | R13C34[3][A] | u_test_gen/n63_s4/F |
4.690 | 0.190 | tNET | FF | 1 | R13C35[1][B] | u_test_gen/n69_s4/I0 |
5.216 | 0.526 | tINS | FR | 1 | R13C35[1][B] | u_test_gen/n69_s4/F |
5.216 | 0.000 | tNET | RR | 1 | R13C35[1][B] | u_test_gen/V_cnt_5_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.059 | 7.059 | active clock edge time | ||||
7.059 | 0.000 | pixel_clk | ||||
7.059 | 0.000 | tCL | RR | 278 | PLL_L[1] | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
7.901 | 0.842 | tNET | RR | 1 | R13C35[1][B] | u_test_gen/V_cnt_5_s1/CLK |
7.837 | -0.064 | tSu | 1 | R13C35[1][B] | u_test_gen/V_cnt_5_s1 |
Path Statistics:
Clock Skew | -0.011 |
Setup Relationship | 7.059 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.852, 100.000% |
Arrival Data Path Delay | cell: 1.646, 37.726%; route: 2.335, 53.509%; tC2Q: 0.382, 8.765% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.842, 100.000% |
Setup Analysis Report[2]:
Report Command:report_timing -setup -from_clock [get_clocks {byte_clk}] -max_paths 20 -max_common_paths 1
Path1
Path Summary:
Slack | 0.270 |
Data Arrival Time | 9.947 |
Data Required Time | 10.217 |
From | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s |
To | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rRdOffset_6_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.869 | 0.869 | tNET | RR | 18 | BSRAM_R28[9] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/CLKB |
3.129 | 2.260 | tC2Q | RR | 2 | BSRAM_R28[9] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14] |
4.477 | 1.348 | tNET | RR | 1 | R20C34[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s3/I1 |
4.892 | 0.415 | tINS | RR | 3 | R20C34[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s3/F |
5.437 | 0.545 | tNET | RR | 1 | R18C34[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s2/I0 |
5.702 | 0.265 | tINS | RR | 12 | R18C34[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s2/F |
7.123 | 1.421 | tNET | RR | 1 | R21C35[2][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n169_s2/I3 |
7.385 | 0.262 | tINS | RR | 5 | R21C35[2][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n169_s2/F |
7.822 | 0.436 | tNET | RR | 1 | R20C34[0][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n164_s2/I3 |
8.338 | 0.516 | tINS | RR | 3 | R20C34[0][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n164_s2/F |
9.420 | 1.082 | tNET | RR | 1 | R18C35[0][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n165_s0/I1 |
9.947 | 0.526 | tINS | RR | 1 | R18C35[0][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n165_s0/F |
9.947 | 0.000 | tNET | RR | 1 | R18C35[0][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rRdOffset_6_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
10.281 | 0.869 | tNET | RR | 1 | R18C35[0][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rRdOffset_6_s1/CLK |
10.217 | -0.064 | tSu | 1 | R18C35[0][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rRdOffset_6_s1 |
Path Statistics:
Clock Skew | -0.000 |
Setup Relationship | 9.412 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.869, 100.000% |
Arrival Data Path Delay | cell: 1.985, 21.867%; route: 4.832, 53.236%; tC2Q: 2.260, 24.897% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.869, 100.000% |
Path2
Path Summary:
Slack | 0.914 |
Data Arrival Time | 9.303 |
Data Required Time | 10.217 |
From | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s |
To | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rWrOffset_7_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.869 | 0.869 | tNET | RR | 18 | BSRAM_R28[9] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/CLKB |
3.129 | 2.260 | tC2Q | RR | 2 | BSRAM_R28[9] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14] |
4.477 | 1.348 | tNET | RR | 1 | R20C34[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s3/I1 |
4.892 | 0.415 | tINS | RR | 3 | R20C34[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s3/F |
5.437 | 0.545 | tNET | RR | 1 | R18C34[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s2/I0 |
5.702 | 0.265 | tINS | RR | 12 | R18C34[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s2/F |
6.605 | 0.904 | tNET | RR | 1 | R20C33[0][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n130_s2/I1 |
7.132 | 0.526 | tINS | RR | 5 | R20C33[0][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n130_s2/F |
7.139 | 0.008 | tNET | RR | 1 | R20C33[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n129_s1/I2 |
7.429 | 0.290 | tINS | RF | 1 | R20C33[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n129_s1/F |
7.434 | 0.005 | tNET | FF | 1 | R20C33[3][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n124_s1/I3 |
7.849 | 0.415 | tINS | FR | 3 | R20C33[3][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n124_s1/F |
8.777 | 0.928 | tNET | RR | 1 | R18C35[0][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n125_s0/I1 |
9.303 | 0.526 | tINS | RR | 1 | R18C35[0][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n125_s0/F |
9.303 | 0.000 | tNET | RR | 1 | R18C35[0][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rWrOffset_7_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
10.281 | 0.869 | tNET | RR | 1 | R18C35[0][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rWrOffset_7_s1/CLK |
10.217 | -0.064 | tSu | 1 | R18C35[0][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rWrOffset_7_s1 |
Path Statistics:
Clock Skew | -0.000 |
Setup Relationship | 9.412 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.869, 100.000% |
Arrival Data Path Delay | cell: 2.438, 28.902%; route: 3.736, 44.301%; tC2Q: 2.260, 26.797% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.869, 100.000% |
Path3
Path Summary:
Slack | 0.916 |
Data Arrival Time | 8.185 |
Data Required Time | 9.101 |
From | u_la0_top/u_ao_match_3/matched_s1 |
To | u_la0_top/u_ao_match_0/match_cnt_3_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.000 | 0.000 | tNET | RR | 1 | R5C10[2][A] | u_la0_top/u_ao_match_3/matched_s1/CLK |
0.382 | 0.382 | tC2Q | RR | 2 | R5C10[2][A] | u_la0_top/u_ao_match_3/matched_s1/Q |
1.923 | 1.540 | tNET | RR | 1 | R12C3[2][A] | u_la0_top/n3273_s5/I1 |
2.449 | 0.526 | tINS | RR | 1 | R12C3[2][A] | u_la0_top/n3273_s5/F |
3.714 | 1.265 | tNET | RR | 1 | R5C11[0][A] | u_la0_top/n3273_s2/I3 |
4.175 | 0.461 | tINS | RR | 2 | R5C11[0][A] | u_la0_top/n3273_s2/F |
4.562 | 0.387 | tNET | RR | 1 | R6C10[3][B] | u_la0_top/u_ao_match_0/matched_s5/I0 |
4.827 | 0.265 | tINS | RR | 6 | R6C10[3][B] | u_la0_top/u_ao_match_0/matched_s5/F |
6.224 | 1.396 | tNET | RR | 1 | R12C4[3][B] | u_la0_top/u_ao_match_0/match_cnt_9_s3/I3 |
6.639 | 0.415 | tINS | RR | 10 | R12C4[3][B] | u_la0_top/u_ao_match_0/match_cnt_9_s3/F |
8.185 | 1.546 | tNET | RR | 1 | R8C5[0][A] | u_la0_top/u_ao_match_0/match_cnt_3_s1/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
9.412 | 0.000 | tNET | RR | 1 | R8C5[0][A] | u_la0_top/u_ao_match_0/match_cnt_3_s1/CLK |
9.101 | -0.311 | tSu | 1 | R8C5[0][A] | u_la0_top/u_ao_match_0/match_cnt_3_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 9.412 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 1.667, 20.373%; route: 6.135, 74.954%; tC2Q: 0.382, 4.673% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path4
Path Summary:
Slack | 0.938 |
Data Arrival Time | 8.162 |
Data Required Time | 9.101 |
From | u_la0_top/u_ao_match_3/matched_s1 |
To | u_la0_top/u_ao_match_0/matched_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.000 | 0.000 | tNET | RR | 1 | R5C10[2][A] | u_la0_top/u_ao_match_3/matched_s1/CLK |
0.382 | 0.382 | tC2Q | RR | 2 | R5C10[2][A] | u_la0_top/u_ao_match_3/matched_s1/Q |
1.923 | 1.540 | tNET | RR | 1 | R12C3[2][A] | u_la0_top/n3273_s5/I1 |
2.449 | 0.526 | tINS | RR | 1 | R12C3[2][A] | u_la0_top/n3273_s5/F |
3.714 | 1.265 | tNET | RR | 1 | R5C11[0][A] | u_la0_top/n3273_s2/I3 |
4.175 | 0.461 | tINS | RR | 2 | R5C11[0][A] | u_la0_top/n3273_s2/F |
4.562 | 0.387 | tNET | RR | 1 | R6C10[3][B] | u_la0_top/u_ao_match_0/matched_s5/I0 |
4.852 | 0.290 | tINS | RF | 6 | R6C10[3][B] | u_la0_top/u_ao_match_0/matched_s5/F |
6.276 | 1.424 | tNET | FF | 1 | R13C3[3][A] | u_la0_top/u_ao_match_0/matched_s3/I2 |
6.797 | 0.521 | tINS | FR | 1 | R13C3[3][A] | u_la0_top/u_ao_match_0/matched_s3/F |
8.162 | 1.365 | tNET | RR | 1 | R4C10[0][A] | u_la0_top/u_ao_match_0/matched_s1/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
9.412 | 0.000 | tNET | RR | 1 | R4C10[0][A] | u_la0_top/u_ao_match_0/matched_s1/CLK |
9.101 | -0.311 | tSu | 1 | R4C10[0][A] | u_la0_top/u_ao_match_0/matched_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 9.412 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 1.799, 22.037%; route: 5.981, 73.277%; tC2Q: 0.382, 4.686% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path5
Path Summary:
Slack | 0.950 |
Data Arrival Time | 9.267 |
Data Required Time | 10.217 |
From | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s |
To | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_4_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.869 | 0.869 | tNET | RR | 18 | BSRAM_R28[9] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/CLKB |
3.129 | 2.260 | tC2Q | RR | 2 | BSRAM_R28[9] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14] |
4.477 | 1.348 | tNET | RR | 1 | R20C34[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s3/I1 |
4.892 | 0.415 | tINS | RR | 3 | R20C34[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s3/F |
5.437 | 0.545 | tNET | RR | 1 | R18C34[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s2/I0 |
5.727 | 0.290 | tINS | RF | 12 | R18C34[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s2/F |
6.094 | 0.367 | tNET | FF | 1 | R18C31[1][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n58_s1/I1 |
6.610 | 0.516 | tINS | FR | 2 | R18C31[1][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n58_s1/F |
6.615 | 0.005 | tNET | RR | 1 | R18C31[2][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n56_s2/I3 |
7.132 | 0.516 | tINS | RR | 4 | R18C31[2][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n56_s2/F |
7.657 | 0.525 | tNET | RR | 1 | R18C34[3][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n55_s1/I0 |
8.178 | 0.521 | tINS | RR | 1 | R18C34[3][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n55_s1/F |
8.740 | 0.562 | tNET | RR | 1 | R18C37[1][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n55_s0/I0 |
9.267 | 0.526 | tINS | RR | 1 | R18C37[1][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n55_s0/F |
9.267 | 0.000 | tNET | RR | 1 | R18C37[1][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_4_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
10.281 | 0.869 | tNET | RR | 1 | R18C37[1][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_4_s1/CLK |
10.217 | -0.064 | tSu | 1 | R18C37[1][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_4_s1 |
Path Statistics:
Clock Skew | -0.000 |
Setup Relationship | 9.412 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.869, 100.000% |
Arrival Data Path Delay | cell: 2.785, 33.165%; route: 3.353, 39.923%; tC2Q: 2.260, 26.913% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.869, 100.000% |
Path6
Path Summary:
Slack | 0.957 |
Data Arrival Time | 9.260 |
Data Required Time | 10.217 |
From | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s |
To | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_7_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.869 | 0.869 | tNET | RR | 18 | BSRAM_R28[9] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/CLKB |
3.129 | 2.260 | tC2Q | RR | 2 | BSRAM_R28[9] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14] |
4.477 | 1.348 | tNET | RR | 1 | R20C34[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s3/I1 |
4.892 | 0.415 | tINS | RR | 3 | R20C34[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s3/F |
5.437 | 0.545 | tNET | RR | 1 | R18C34[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s2/I0 |
5.727 | 0.290 | tINS | RF | 12 | R18C34[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s2/F |
5.884 | 0.157 | tNET | FF | 1 | R18C33[0][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rFull_s4/I2 |
6.410 | 0.526 | tINS | FR | 4 | R18C33[0][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rFull_s4/F |
6.745 | 0.335 | tNET | RR | 1 | R18C31[3][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n56_s1/I2 |
7.010 | 0.265 | tINS | RR | 4 | R18C31[3][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n56_s1/F |
7.500 | 0.490 | tNET | RR | 1 | R18C34[1][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n51_s1/I3 |
8.027 | 0.526 | tINS | RR | 4 | R18C34[1][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n51_s1/F |
8.382 | 0.355 | tNET | RR | 1 | R18C35[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n52_s1/I1 |
8.797 | 0.415 | tINS | RR | 1 | R18C35[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n52_s1/F |
8.799 | 0.003 | tNET | RR | 1 | R18C35[2][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n52_s0/I0 |
9.260 | 0.461 | tINS | RR | 1 | R18C35[2][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n52_s0/F |
9.260 | 0.000 | tNET | RR | 1 | R18C35[2][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_7_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
10.281 | 0.869 | tNET | RR | 1 | R18C35[2][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_7_s1/CLK |
10.217 | -0.064 | tSu | 1 | R18C35[2][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_7_s1 |
Path Statistics:
Clock Skew | -0.000 |
Setup Relationship | 9.412 |
Logic Level | 8 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.869, 100.000% |
Arrival Data Path Delay | cell: 2.899, 34.545%; route: 3.233, 38.522%; tC2Q: 2.260, 26.933% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.869, 100.000% |
Path7
Path Summary:
Slack | 1.057 |
Data Arrival Time | 9.150 |
Data Required Time | 10.208 |
From | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s |
To | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rWrOffset_9_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.869 | 0.869 | tNET | RR | 18 | BSRAM_R28[9] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/CLKB |
3.129 | 2.260 | tC2Q | RR | 2 | BSRAM_R28[9] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14] |
4.477 | 1.348 | tNET | RR | 1 | R20C34[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s3/I1 |
4.892 | 0.415 | tINS | RR | 3 | R20C34[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s3/F |
5.437 | 0.545 | tNET | RR | 1 | R18C34[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s2/I0 |
5.702 | 0.265 | tINS | RR | 12 | R18C34[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s2/F |
6.605 | 0.904 | tNET | RR | 1 | R20C33[0][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n130_s2/I1 |
7.132 | 0.526 | tINS | RR | 5 | R20C33[0][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n130_s2/F |
7.489 | 0.357 | tNET | RR | 1 | R20C34[2][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n123_s3/I3 |
7.950 | 0.461 | tINS | RR | 3 | R20C34[2][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n123_s3/F |
8.634 | 0.684 | tNET | RR | 1 | R18C34[1][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n123_s0/I2 |
9.150 | 0.516 | tINS | RR | 1 | R18C34[1][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n123_s0/F |
9.150 | 0.000 | tNET | RR | 1 | R18C34[1][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rWrOffset_9_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
10.271 | 0.859 | tNET | RR | 1 | R18C34[1][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rWrOffset_9_s1/CLK |
10.208 | -0.064 | tSu | 1 | R18C34[1][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rWrOffset_9_s1 |
Path Statistics:
Clock Skew | -0.010 |
Setup Relationship | 9.412 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.869, 100.000% |
Arrival Data Path Delay | cell: 2.184, 26.370%; route: 3.838, 46.340%; tC2Q: 2.260, 27.291% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.859, 100.000% |
Path8
Path Summary:
Slack | 1.095 |
Data Arrival Time | 9.113 |
Data Required Time | 10.208 |
From | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s |
To | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rWrOffset_8_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.869 | 0.869 | tNET | RR | 18 | BSRAM_R28[9] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/CLKB |
3.129 | 2.260 | tC2Q | RR | 2 | BSRAM_R28[9] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14] |
4.477 | 1.348 | tNET | RR | 1 | R20C34[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s3/I1 |
4.892 | 0.415 | tINS | RR | 3 | R20C34[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s3/F |
5.437 | 0.545 | tNET | RR | 1 | R18C34[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s2/I0 |
5.702 | 0.265 | tINS | RR | 12 | R18C34[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s2/F |
6.605 | 0.904 | tNET | RR | 1 | R20C33[0][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n130_s2/I1 |
7.132 | 0.526 | tINS | RR | 5 | R20C33[0][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n130_s2/F |
7.139 | 0.008 | tNET | RR | 1 | R20C33[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n129_s1/I2 |
7.429 | 0.290 | tINS | RF | 1 | R20C33[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n129_s1/F |
7.434 | 0.005 | tNET | FF | 1 | R20C33[3][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n124_s1/I3 |
7.849 | 0.415 | tINS | FR | 3 | R20C33[3][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n124_s1/F |
8.587 | 0.738 | tNET | RR | 1 | R18C34[0][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n124_s0/I2 |
9.113 | 0.526 | tINS | RR | 1 | R18C34[0][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n124_s0/F |
9.113 | 0.000 | tNET | RR | 1 | R18C34[0][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rWrOffset_8_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
10.271 | 0.859 | tNET | RR | 1 | R18C34[0][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rWrOffset_8_s1/CLK |
10.208 | -0.064 | tSu | 1 | R18C34[0][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rWrOffset_8_s1 |
Path Statistics:
Clock Skew | -0.010 |
Setup Relationship | 9.412 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.869, 100.000% |
Arrival Data Path Delay | cell: 2.438, 29.568%; route: 3.546, 43.017%; tC2Q: 2.260, 27.415% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.859, 100.000% |
Path9
Path Summary:
Slack | 1.097 |
Data Arrival Time | 9.152 |
Data Required Time | 10.249 |
From | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s |
To | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rRdOffset_5_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.869 | 0.869 | tNET | RR | 18 | BSRAM_R28[9] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/CLKB |
3.129 | 2.260 | tC2Q | RR | 2 | BSRAM_R28[9] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14] |
4.477 | 1.348 | tNET | RR | 1 | R20C34[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s3/I1 |
4.892 | 0.415 | tINS | RR | 3 | R20C34[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s3/F |
5.437 | 0.545 | tNET | RR | 1 | R18C34[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s2/I0 |
5.702 | 0.265 | tINS | RR | 12 | R18C34[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s2/F |
7.123 | 1.421 | tNET | RR | 1 | R21C35[2][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n169_s2/I3 |
7.385 | 0.262 | tINS | RR | 5 | R21C35[2][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n169_s2/F |
7.822 | 0.436 | tNET | RR | 1 | R20C34[0][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n164_s2/I3 |
8.338 | 0.516 | tINS | RR | 3 | R20C34[0][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n164_s2/F |
8.690 | 0.352 | tNET | RR | 1 | R21C35[0][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n166_s0/I1 |
9.152 | 0.461 | tINS | RR | 1 | R21C35[0][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n166_s0/F |
9.152 | 0.000 | tNET | RR | 1 | R21C35[0][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rRdOffset_5_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
10.313 | 0.901 | tNET | RR | 1 | R21C35[0][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rRdOffset_5_s1/CLK |
10.249 | -0.064 | tSu | 1 | R21C35[0][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rRdOffset_5_s1 |
Path Statistics:
Clock Skew | 0.032 |
Setup Relationship | 9.412 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.869, 100.000% |
Arrival Data Path Delay | cell: 1.920, 23.181%; route: 4.102, 49.532%; tC2Q: 2.260, 27.286% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.901, 100.000% |
Path10
Path Summary:
Slack | 1.116 |
Data Arrival Time | 7.985 |
Data Required Time | 9.101 |
From | u_la0_top/u_ao_match_3/matched_s1 |
To | u_la0_top/u_ao_match_0/match_cnt_1_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.000 | 0.000 | tNET | RR | 1 | R5C10[2][A] | u_la0_top/u_ao_match_3/matched_s1/CLK |
0.382 | 0.382 | tC2Q | RR | 2 | R5C10[2][A] | u_la0_top/u_ao_match_3/matched_s1/Q |
1.923 | 1.540 | tNET | RR | 1 | R12C3[2][A] | u_la0_top/n3273_s5/I1 |
2.449 | 0.526 | tINS | RR | 1 | R12C3[2][A] | u_la0_top/n3273_s5/F |
3.714 | 1.265 | tNET | RR | 1 | R5C11[0][A] | u_la0_top/n3273_s2/I3 |
4.175 | 0.461 | tINS | RR | 2 | R5C11[0][A] | u_la0_top/n3273_s2/F |
4.562 | 0.387 | tNET | RR | 1 | R6C10[3][B] | u_la0_top/u_ao_match_0/matched_s5/I0 |
4.827 | 0.265 | tINS | RR | 6 | R6C10[3][B] | u_la0_top/u_ao_match_0/matched_s5/F |
6.224 | 1.396 | tNET | RR | 1 | R12C4[3][B] | u_la0_top/u_ao_match_0/match_cnt_9_s3/I3 |
6.639 | 0.415 | tINS | RR | 10 | R12C4[3][B] | u_la0_top/u_ao_match_0/match_cnt_9_s3/F |
7.985 | 1.346 | tNET | RR | 1 | R6C9[2][A] | u_la0_top/u_ao_match_0/match_cnt_1_s1/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
9.412 | 0.000 | tNET | RR | 1 | R6C9[2][A] | u_la0_top/u_ao_match_0/match_cnt_1_s1/CLK |
9.101 | -0.311 | tSu | 1 | R6C9[2][A] | u_la0_top/u_ao_match_0/match_cnt_1_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 9.412 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 1.667, 20.883%; route: 5.935, 74.327%; tC2Q: 0.382, 4.790% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path11
Path Summary:
Slack | 1.195 |
Data Arrival Time | 9.057 |
Data Required Time | 10.251 |
From | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s |
To | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rRdOffset_9_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.869 | 0.869 | tNET | RR | 18 | BSRAM_R28[9] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/CLKB |
3.129 | 2.260 | tC2Q | RR | 2 | BSRAM_R28[9] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14] |
4.477 | 1.348 | tNET | RR | 1 | R20C34[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s3/I1 |
4.892 | 0.415 | tINS | RR | 3 | R20C34[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s3/F |
5.437 | 0.545 | tNET | RR | 1 | R18C34[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s2/I0 |
5.702 | 0.265 | tINS | RR | 12 | R18C34[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s2/F |
7.123 | 1.421 | tNET | RR | 1 | R21C35[2][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n169_s2/I3 |
7.385 | 0.262 | tINS | RR | 5 | R21C35[2][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n169_s2/F |
7.390 | 0.005 | tNET | RR | 1 | R21C35[1][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n163_s2/I1 |
7.917 | 0.526 | tINS | RR | 1 | R21C35[1][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n163_s2/F |
7.919 | 0.003 | tNET | RR | 1 | R21C35[2][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n163_s0/I2 |
8.435 | 0.516 | tINS | RR | 2 | R21C35[2][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n163_s0/F |
8.595 | 0.160 | tNET | RR | 1 | R20C35[0][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n162_s0/I2 |
9.057 | 0.461 | tINS | RR | 1 | R20C35[0][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n162_s0/F |
9.057 | 0.000 | tNET | RR | 1 | R20C35[0][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rRdOffset_9_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
10.315 | 0.903 | tNET | RR | 1 | R20C35[0][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rRdOffset_9_s1/CLK |
10.251 | -0.064 | tSu | 1 | R20C35[0][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rRdOffset_9_s1 |
Path Statistics:
Clock Skew | 0.034 |
Setup Relationship | 9.412 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.869, 100.000% |
Arrival Data Path Delay | cell: 2.446, 29.878%; route: 3.481, 42.519%; tC2Q: 2.260, 27.603% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.903, 100.000% |
Path12
Path Summary:
Slack | 1.247 |
Data Arrival Time | 8.979 |
Data Required Time | 10.226 |
From | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s |
To | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_10_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.869 | 0.869 | tNET | RR | 18 | BSRAM_R28[9] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/CLKB |
3.129 | 2.260 | tC2Q | RR | 2 | BSRAM_R28[9] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14] |
4.477 | 1.348 | tNET | RR | 1 | R20C34[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s3/I1 |
4.892 | 0.415 | tINS | RR | 3 | R20C34[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s3/F |
5.437 | 0.545 | tNET | RR | 1 | R18C34[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s2/I0 |
5.727 | 0.290 | tINS | RF | 12 | R18C34[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s2/F |
6.094 | 0.367 | tNET | FF | 1 | R18C31[1][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n58_s1/I1 |
6.610 | 0.516 | tINS | FR | 2 | R18C31[1][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n58_s1/F |
6.615 | 0.005 | tNET | RR | 1 | R18C31[2][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n56_s2/I3 |
7.132 | 0.516 | tINS | RR | 4 | R18C31[2][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n56_s2/F |
7.327 | 0.195 | tNET | RR | 1 | R18C33[0][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n53_s2/I0 |
7.788 | 0.461 | tINS | RR | 6 | R18C33[0][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n53_s2/F |
7.953 | 0.165 | tNET | RR | 1 | R18C32[3][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n49_s1/I0 |
8.450 | 0.498 | tINS | RR | 1 | R18C32[3][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n49_s1/F |
8.453 | 0.003 | tNET | RR | 1 | R18C32[2][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n49_s0/I0 |
8.979 | 0.526 | tINS | RR | 1 | R18C32[2][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n49_s0/F |
8.979 | 0.000 | tNET | RR | 1 | R18C32[2][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_10_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
10.290 | 0.878 | tNET | RR | 1 | R18C32[2][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_10_s1/CLK |
10.226 | -0.064 | tSu | 1 | R18C32[2][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_10_s1 |
Path Statistics:
Clock Skew | 0.009 |
Setup Relationship | 9.412 |
Logic Level | 8 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.869, 100.000% |
Arrival Data Path Delay | cell: 3.222, 39.735%; route: 2.628, 32.398%; tC2Q: 2.260, 27.867% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.878, 100.000% |
Path13
Path Summary:
Slack | 1.250 |
Data Arrival Time | 7.851 |
Data Required Time | 9.101 |
From | u_la0_top/u_ao_match_3/matched_s1 |
To | u_la0_top/u_ao_match_3/match_cnt_1_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.000 | 0.000 | tNET | RR | 1 | R5C10[2][A] | u_la0_top/u_ao_match_3/matched_s1/CLK |
0.382 | 0.382 | tC2Q | RR | 2 | R5C10[2][A] | u_la0_top/u_ao_match_3/matched_s1/Q |
1.923 | 1.540 | tNET | RR | 1 | R12C3[2][A] | u_la0_top/n3273_s5/I1 |
2.449 | 0.526 | tINS | RR | 1 | R12C3[2][A] | u_la0_top/n3273_s5/F |
3.714 | 1.265 | tNET | RR | 1 | R5C11[0][A] | u_la0_top/n3273_s2/I3 |
4.175 | 0.461 | tINS | RR | 2 | R5C11[0][A] | u_la0_top/n3273_s2/F |
4.562 | 0.387 | tNET | RR | 1 | R6C10[3][B] | u_la0_top/u_ao_match_0/matched_s5/I0 |
4.852 | 0.290 | tINS | RF | 6 | R6C10[3][B] | u_la0_top/u_ao_match_0/matched_s5/F |
6.219 | 1.366 | tNET | FF | 1 | R12C2[0][A] | u_la0_top/u_ao_match_3/match_cnt_11_s3/I3 |
6.680 | 0.461 | tINS | FR | 12 | R12C2[0][A] | u_la0_top/u_ao_match_3/match_cnt_11_s3/F |
7.851 | 1.171 | tNET | RR | 1 | R6C9[0][A] | u_la0_top/u_ao_match_3/match_cnt_1_s1/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
9.412 | 0.000 | tNET | RR | 1 | R6C9[0][A] | u_la0_top/u_ao_match_3/match_cnt_1_s1/CLK |
9.101 | -0.311 | tSu | 1 | R6C9[0][A] | u_la0_top/u_ao_match_3/match_cnt_1_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 9.412 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 1.739, 22.146%; route: 5.730, 72.982%; tC2Q: 0.382, 4.872% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path14
Path Summary:
Slack | 1.273 |
Data Arrival Time | 7.827 |
Data Required Time | 9.101 |
From | u_la0_top/u_ao_match_3/matched_s1 |
To | u_la0_top/u_ao_match_0/match_cnt_0_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.000 | 0.000 | tNET | RR | 1 | R5C10[2][A] | u_la0_top/u_ao_match_3/matched_s1/CLK |
0.382 | 0.382 | tC2Q | RR | 2 | R5C10[2][A] | u_la0_top/u_ao_match_3/matched_s1/Q |
1.923 | 1.540 | tNET | RR | 1 | R12C3[2][A] | u_la0_top/n3273_s5/I1 |
2.449 | 0.526 | tINS | RR | 1 | R12C3[2][A] | u_la0_top/n3273_s5/F |
3.714 | 1.265 | tNET | RR | 1 | R5C11[0][A] | u_la0_top/n3273_s2/I3 |
4.175 | 0.461 | tINS | RR | 2 | R5C11[0][A] | u_la0_top/n3273_s2/F |
4.562 | 0.387 | tNET | RR | 1 | R6C10[3][B] | u_la0_top/u_ao_match_0/matched_s5/I0 |
4.827 | 0.265 | tINS | RR | 6 | R6C10[3][B] | u_la0_top/u_ao_match_0/matched_s5/F |
6.224 | 1.396 | tNET | RR | 1 | R12C4[3][B] | u_la0_top/u_ao_match_0/match_cnt_9_s3/I3 |
6.639 | 0.415 | tINS | RR | 10 | R12C4[3][B] | u_la0_top/u_ao_match_0/match_cnt_9_s3/F |
7.827 | 1.189 | tNET | RR | 1 | R7C8[2][A] | u_la0_top/u_ao_match_0/match_cnt_0_s1/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
9.412 | 0.000 | tNET | RR | 1 | R7C8[2][A] | u_la0_top/u_ao_match_0/match_cnt_0_s1/CLK |
9.101 | -0.311 | tSu | 1 | R7C8[2][A] | u_la0_top/u_ao_match_0/match_cnt_0_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 9.412 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 1.667, 21.303%; route: 5.778, 73.810%; tC2Q: 0.382, 4.887% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path15
Path Summary:
Slack | 1.310 |
Data Arrival Time | 8.907 |
Data Required Time | 10.217 |
From | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s |
To | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_8_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.869 | 0.869 | tNET | RR | 18 | BSRAM_R28[9] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/CLKB |
3.129 | 2.260 | tC2Q | RR | 2 | BSRAM_R28[9] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14] |
4.477 | 1.348 | tNET | RR | 1 | R20C34[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s3/I1 |
4.892 | 0.415 | tINS | RR | 3 | R20C34[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s3/F |
5.437 | 0.545 | tNET | RR | 1 | R18C34[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s2/I0 |
5.727 | 0.290 | tINS | RF | 12 | R18C34[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s2/F |
6.094 | 0.367 | tNET | FF | 1 | R18C31[1][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n58_s1/I1 |
6.610 | 0.516 | tINS | FR | 2 | R18C31[1][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n58_s1/F |
6.615 | 0.005 | tNET | RR | 1 | R18C31[2][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n56_s2/I3 |
7.132 | 0.516 | tINS | RR | 4 | R18C31[2][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n56_s2/F |
7.327 | 0.195 | tNET | RR | 1 | R18C33[0][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n53_s2/I0 |
7.788 | 0.461 | tINS | RR | 6 | R18C33[0][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n53_s2/F |
7.988 | 0.200 | tNET | RR | 1 | R18C35[3][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n51_s2/I0 |
8.278 | 0.290 | tINS | RF | 1 | R18C35[3][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n51_s2/F |
8.390 | 0.113 | tNET | FF | 1 | R18C35[2][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n51_s0/I2 |
8.907 | 0.516 | tINS | FR | 1 | R18C35[2][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n51_s0/F |
8.907 | 0.000 | tNET | RR | 1 | R18C35[2][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_8_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
10.281 | 0.869 | tNET | RR | 1 | R18C35[2][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_8_s1/CLK |
10.217 | -0.064 | tSu | 1 | R18C35[2][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_8_s1 |
Path Statistics:
Clock Skew | -0.000 |
Setup Relationship | 9.412 |
Logic Level | 8 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.869, 100.000% |
Arrival Data Path Delay | cell: 3.005, 37.387%; route: 2.773, 34.495%; tC2Q: 2.260, 28.118% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.869, 100.000% |
Path16
Path Summary:
Slack | 1.367 |
Data Arrival Time | 7.734 |
Data Required Time | 9.101 |
From | u_la0_top/u_ao_match_3/matched_s1 |
To | u_la0_top/u_ao_match_0/match_cnt_7_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.000 | 0.000 | tNET | RR | 1 | R5C10[2][A] | u_la0_top/u_ao_match_3/matched_s1/CLK |
0.382 | 0.382 | tC2Q | RR | 2 | R5C10[2][A] | u_la0_top/u_ao_match_3/matched_s1/Q |
1.923 | 1.540 | tNET | RR | 1 | R12C3[2][A] | u_la0_top/n3273_s5/I1 |
2.449 | 0.526 | tINS | RR | 1 | R12C3[2][A] | u_la0_top/n3273_s5/F |
3.714 | 1.265 | tNET | RR | 1 | R5C11[0][A] | u_la0_top/n3273_s2/I3 |
4.175 | 0.461 | tINS | RR | 2 | R5C11[0][A] | u_la0_top/n3273_s2/F |
4.562 | 0.387 | tNET | RR | 1 | R6C10[3][B] | u_la0_top/u_ao_match_0/matched_s5/I0 |
4.827 | 0.265 | tINS | RR | 6 | R6C10[3][B] | u_la0_top/u_ao_match_0/matched_s5/F |
6.224 | 1.396 | tNET | RR | 1 | R12C4[3][B] | u_la0_top/u_ao_match_0/match_cnt_9_s3/I3 |
6.639 | 0.415 | tINS | RR | 10 | R12C4[3][B] | u_la0_top/u_ao_match_0/match_cnt_9_s3/F |
7.734 | 1.095 | tNET | RR | 1 | R9C8[0][A] | u_la0_top/u_ao_match_0/match_cnt_7_s1/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
9.412 | 0.000 | tNET | RR | 1 | R9C8[0][A] | u_la0_top/u_ao_match_0/match_cnt_7_s1/CLK |
9.101 | -0.311 | tSu | 1 | R9C8[0][A] | u_la0_top/u_ao_match_0/match_cnt_7_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 9.412 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 1.667, 21.561%; route: 5.684, 73.493%; tC2Q: 0.382, 4.946% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path17
Path Summary:
Slack | 1.367 |
Data Arrival Time | 7.734 |
Data Required Time | 9.101 |
From | u_la0_top/u_ao_match_3/matched_s1 |
To | u_la0_top/u_ao_match_0/match_cnt_8_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.000 | 0.000 | tNET | RR | 1 | R5C10[2][A] | u_la0_top/u_ao_match_3/matched_s1/CLK |
0.382 | 0.382 | tC2Q | RR | 2 | R5C10[2][A] | u_la0_top/u_ao_match_3/matched_s1/Q |
1.923 | 1.540 | tNET | RR | 1 | R12C3[2][A] | u_la0_top/n3273_s5/I1 |
2.449 | 0.526 | tINS | RR | 1 | R12C3[2][A] | u_la0_top/n3273_s5/F |
3.714 | 1.265 | tNET | RR | 1 | R5C11[0][A] | u_la0_top/n3273_s2/I3 |
4.175 | 0.461 | tINS | RR | 2 | R5C11[0][A] | u_la0_top/n3273_s2/F |
4.562 | 0.387 | tNET | RR | 1 | R6C10[3][B] | u_la0_top/u_ao_match_0/matched_s5/I0 |
4.827 | 0.265 | tINS | RR | 6 | R6C10[3][B] | u_la0_top/u_ao_match_0/matched_s5/F |
6.224 | 1.396 | tNET | RR | 1 | R12C4[3][B] | u_la0_top/u_ao_match_0/match_cnt_9_s3/I3 |
6.639 | 0.415 | tINS | RR | 10 | R12C4[3][B] | u_la0_top/u_ao_match_0/match_cnt_9_s3/F |
7.734 | 1.095 | tNET | RR | 1 | R9C8[0][B] | u_la0_top/u_ao_match_0/match_cnt_8_s1/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
9.412 | 0.000 | tNET | RR | 1 | R9C8[0][B] | u_la0_top/u_ao_match_0/match_cnt_8_s1/CLK |
9.101 | -0.311 | tSu | 1 | R9C8[0][B] | u_la0_top/u_ao_match_0/match_cnt_8_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 9.412 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 1.667, 21.561%; route: 5.684, 73.493%; tC2Q: 0.382, 4.946% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path18
Path Summary:
Slack | 1.392 |
Data Arrival Time | 7.709 |
Data Required Time | 9.101 |
From | u_la0_top/u_ao_match_3/matched_s1 |
To | u_la0_top/u_ao_match_0/match_cnt_4_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.000 | 0.000 | tNET | RR | 1 | R5C10[2][A] | u_la0_top/u_ao_match_3/matched_s1/CLK |
0.382 | 0.382 | tC2Q | RR | 2 | R5C10[2][A] | u_la0_top/u_ao_match_3/matched_s1/Q |
1.923 | 1.540 | tNET | RR | 1 | R12C3[2][A] | u_la0_top/n3273_s5/I1 |
2.449 | 0.526 | tINS | RR | 1 | R12C3[2][A] | u_la0_top/n3273_s5/F |
3.714 | 1.265 | tNET | RR | 1 | R5C11[0][A] | u_la0_top/n3273_s2/I3 |
4.175 | 0.461 | tINS | RR | 2 | R5C11[0][A] | u_la0_top/n3273_s2/F |
4.562 | 0.387 | tNET | RR | 1 | R6C10[3][B] | u_la0_top/u_ao_match_0/matched_s5/I0 |
4.827 | 0.265 | tINS | RR | 6 | R6C10[3][B] | u_la0_top/u_ao_match_0/matched_s5/F |
6.224 | 1.396 | tNET | RR | 1 | R12C4[3][B] | u_la0_top/u_ao_match_0/match_cnt_9_s3/I3 |
6.639 | 0.415 | tINS | RR | 10 | R12C4[3][B] | u_la0_top/u_ao_match_0/match_cnt_9_s3/F |
7.709 | 1.070 | tNET | RR | 1 | R7C7[2][A] | u_la0_top/u_ao_match_0/match_cnt_4_s1/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
9.412 | 0.000 | tNET | RR | 1 | R7C7[2][A] | u_la0_top/u_ao_match_0/match_cnt_4_s1/CLK |
9.101 | -0.311 | tSu | 1 | R7C7[2][A] | u_la0_top/u_ao_match_0/match_cnt_4_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 9.412 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 1.667, 21.631%; route: 5.659, 73.407%; tC2Q: 0.382, 4.962% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path19
Path Summary:
Slack | 1.394 |
Data Arrival Time | 8.858 |
Data Required Time | 10.251 |
From | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s |
To | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rRdOffset_8_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.869 | 0.869 | tNET | RR | 18 | BSRAM_R28[9] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/CLKB |
3.129 | 2.260 | tC2Q | RR | 2 | BSRAM_R28[9] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14] |
4.477 | 1.348 | tNET | RR | 1 | R20C34[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s3/I1 |
4.892 | 0.415 | tINS | RR | 3 | R20C34[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s3/F |
5.437 | 0.545 | tNET | RR | 1 | R18C34[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s2/I0 |
5.702 | 0.265 | tINS | RR | 12 | R18C34[3][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s2/F |
7.123 | 1.421 | tNET | RR | 1 | R21C35[2][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n169_s2/I3 |
7.385 | 0.262 | tINS | RR | 5 | R21C35[2][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n169_s2/F |
7.390 | 0.005 | tNET | RR | 1 | R21C35[1][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n163_s2/I1 |
7.917 | 0.526 | tINS | RR | 1 | R21C35[1][B] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n163_s2/F |
7.919 | 0.003 | tNET | RR | 1 | R21C35[2][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n163_s0/I2 |
8.435 | 0.516 | tINS | RR | 2 | R21C35[2][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n163_s0/F |
8.858 | 0.422 | tNET | RR | 1 | R20C35[0][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rRdOffset_8_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
10.315 | 0.903 | tNET | RR | 1 | R20C35[0][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rRdOffset_8_s1/CLK |
10.251 | -0.064 | tSu | 1 | R20C35[0][A] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rRdOffset_8_s1 |
Path Statistics:
Clock Skew | 0.034 |
Setup Relationship | 9.412 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.869, 100.000% |
Arrival Data Path Delay | cell: 1.985, 24.847%; route: 3.744, 46.863%; tC2Q: 2.260, 28.290% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.903, 100.000% |
Path20
Path Summary:
Slack | 1.398 |
Data Arrival Time | 7.702 |
Data Required Time | 9.101 |
From | u_la0_top/u_ao_match_3/matched_s1 |
To | u_la0_top/u_ao_match_3/match_cnt_2_s1 |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.000 | 0.000 | tNET | RR | 1 | R5C10[2][A] | u_la0_top/u_ao_match_3/matched_s1/CLK |
0.382 | 0.382 | tC2Q | RR | 2 | R5C10[2][A] | u_la0_top/u_ao_match_3/matched_s1/Q |
1.923 | 1.540 | tNET | RR | 1 | R12C3[2][A] | u_la0_top/n3273_s5/I1 |
2.449 | 0.526 | tINS | RR | 1 | R12C3[2][A] | u_la0_top/n3273_s5/F |
3.714 | 1.265 | tNET | RR | 1 | R5C11[0][A] | u_la0_top/n3273_s2/I3 |
4.175 | 0.461 | tINS | RR | 2 | R5C11[0][A] | u_la0_top/n3273_s2/F |
4.562 | 0.387 | tNET | RR | 1 | R6C10[3][B] | u_la0_top/u_ao_match_0/matched_s5/I0 |
4.852 | 0.290 | tINS | RF | 6 | R6C10[3][B] | u_la0_top/u_ao_match_0/matched_s5/F |
6.219 | 1.366 | tNET | FF | 1 | R12C2[0][A] | u_la0_top/u_ao_match_3/match_cnt_11_s3/I3 |
6.680 | 0.461 | tINS | FR | 12 | R12C2[0][A] | u_la0_top/u_ao_match_3/match_cnt_11_s3/F |
7.702 | 1.023 | tNET | RR | 1 | R8C7[2][A] | u_la0_top/u_ao_match_3/match_cnt_2_s1/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
9.412 | 0.000 | tNET | RR | 1 | R8C7[2][A] | u_la0_top/u_ao_match_3/match_cnt_2_s1/CLK |
9.101 | -0.311 | tSu | 1 | R8C7[2][A] | u_la0_top/u_ao_match_3/match_cnt_2_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 9.412 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 1.739, 22.574%; route: 5.581, 72.460%; tC2Q: 0.382, 4.966% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Hold Analysis Report
Hold Analysis Report[1]:
Report Command:report_timing -hold -from_clock [get_clocks {pixel_clk}] -max_paths 20 -max_common_paths 1
Path1
Path Summary:
Slack | 0.174 |
Data Arrival Time | 0.786 |
Data Required Time | 0.613 |
From | u_p2b/u_p2b_0/mid_data_31_s1 |
To | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 278 | PLL_L[1] | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
0.370 | 0.370 | tNET | RR | 1 | R9C27[0][B] | u_p2b/u_p2b_0/mid_data_31_s1/CLK |
0.550 | 0.180 | tC2Q | RR | 1 | R9C27[0][B] | u_p2b/u_p2b_0/mid_data_31_s1/Q |
0.786 | 0.236 | tNET | RR | 1 | BSRAM_R10[6] | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s/DI[31] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 278 | PLL_L[1] | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
0.364 | 0.364 | tNET | RR | 1 | BSRAM_R10[6] | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s/CLKA |
0.613 | 0.249 | tHld | 1 | BSRAM_R10[6] | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s |
Path Statistics:
Clock Skew | -0.006 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.370, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.236, 56.757%; tC2Q: 0.180, 43.243% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.364, 100.000% |
Path2
Path Summary:
Slack | 0.178 |
Data Arrival Time | 0.791 |
Data Required Time | 0.613 |
From | u_p2b/u_p2b_0/mid_data_27_s1 |
To | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 278 | PLL_L[1] | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
0.375 | 0.375 | tNET | RR | 1 | R9C26[0][B] | u_p2b/u_p2b_0/mid_data_27_s1/CLK |
0.555 | 0.180 | tC2Q | RR | 1 | R9C26[0][B] | u_p2b/u_p2b_0/mid_data_27_s1/Q |
0.791 | 0.236 | tNET | RR | 1 | BSRAM_R10[6] | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s/DI[27] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 278 | PLL_L[1] | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
0.364 | 0.364 | tNET | RR | 1 | BSRAM_R10[6] | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s/CLKA |
0.613 | 0.249 | tHld | 1 | BSRAM_R10[6] | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s |
Path Statistics:
Clock Skew | -0.011 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.236, 56.757%; tC2Q: 0.180, 43.243% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.364, 100.000% |
Path3
Path Summary:
Slack | 0.178 |
Data Arrival Time | 0.791 |
Data Required Time | 0.613 |
From | u_p2b/u_p2b_0/mid_data_19_s1 |
To | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 278 | PLL_L[1] | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
0.375 | 0.375 | tNET | RR | 1 | R9C26[0][A] | u_p2b/u_p2b_0/mid_data_19_s1/CLK |
0.555 | 0.180 | tC2Q | RR | 1 | R9C26[0][A] | u_p2b/u_p2b_0/mid_data_19_s1/Q |
0.791 | 0.236 | tNET | RR | 1 | BSRAM_R10[6] | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s/DI[19] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 278 | PLL_L[1] | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
0.364 | 0.364 | tNET | RR | 1 | BSRAM_R10[6] | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s/CLKA |
0.613 | 0.249 | tHld | 1 | BSRAM_R10[6] | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s |
Path Statistics:
Clock Skew | -0.011 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.236, 56.757%; tC2Q: 0.180, 43.243% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.364, 100.000% |
Path4
Path Summary:
Slack | 0.192 |
Data Arrival Time | 0.805 |
Data Required Time | 0.613 |
From | u_p2b/u_p2b_0/mid_data_11_s1 |
To | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 278 | PLL_L[1] | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
0.381 | 0.381 | tNET | RR | 1 | R8C26[0][B] | u_p2b/u_p2b_0/mid_data_11_s1/CLK |
0.561 | 0.180 | tC2Q | RR | 1 | R8C26[0][B] | u_p2b/u_p2b_0/mid_data_11_s1/Q |
0.805 | 0.244 | tNET | RR | 1 | BSRAM_R10[6] | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s/DI[11] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 278 | PLL_L[1] | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
0.364 | 0.364 | tNET | RR | 1 | BSRAM_R10[6] | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s/CLKA |
0.613 | 0.249 | tHld | 1 | BSRAM_R10[6] | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s |
Path Statistics:
Clock Skew | -0.018 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.381, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.244, 57.522%; tC2Q: 0.180, 42.478% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.364, 100.000% |
Path5
Path Summary:
Slack | 0.297 |
Data Arrival Time | 0.910 |
Data Required Time | 0.613 |
From | u_p2b/u_p2b_0/mid_data_10_s1 |
To | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 278 | PLL_L[1] | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
0.375 | 0.375 | tNET | RR | 1 | R9C28[0][B] | u_p2b/u_p2b_0/mid_data_10_s1/CLK |
0.555 | 0.180 | tC2Q | RR | 1 | R9C28[0][B] | u_p2b/u_p2b_0/mid_data_10_s1/Q |
0.910 | 0.355 | tNET | RR | 1 | BSRAM_R10[6] | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s/DI[10] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 278 | PLL_L[1] | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
0.364 | 0.364 | tNET | RR | 1 | BSRAM_R10[6] | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s/CLKA |
0.613 | 0.249 | tHld | 1 | BSRAM_R10[6] | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s |
Path Statistics:
Clock Skew | -0.011 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.355, 66.355%; tC2Q: 0.180, 33.645% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.364, 100.000% |
Path6
Path Summary:
Slack | 0.300 |
Data Arrival Time | 0.913 |
Data Required Time | 0.613 |
From | u_p2b/u_p2b_0/mid_data_15_s1 |
To | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 278 | PLL_L[1] | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
0.376 | 0.376 | tNET | RR | 1 | R8C27[0][B] | u_p2b/u_p2b_0/mid_data_15_s1/CLK |
0.556 | 0.180 | tC2Q | RR | 1 | R8C27[0][B] | u_p2b/u_p2b_0/mid_data_15_s1/Q |
0.913 | 0.356 | tNET | RR | 1 | BSRAM_R10[6] | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s/DI[15] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 278 | PLL_L[1] | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
0.364 | 0.364 | tNET | RR | 1 | BSRAM_R10[6] | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s/CLKA |
0.613 | 0.249 | tHld | 1 | BSRAM_R10[6] | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s |
Path Statistics:
Clock Skew | -0.013 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.376, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.356, 66.434%; tC2Q: 0.180, 33.566% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.364, 100.000% |
Path7
Path Summary:
Slack | 0.305 |
Data Arrival Time | 0.918 |
Data Required Time | 0.613 |
From | u_p2b/u_p2b_0/mid_data_24_s1 |
To | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 278 | PLL_L[1] | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
0.381 | 0.381 | tNET | RR | 1 | R8C28[1][A] | u_p2b/u_p2b_0/mid_data_24_s1/CLK |
0.561 | 0.180 | tC2Q | RR | 1 | R8C28[1][A] | u_p2b/u_p2b_0/mid_data_24_s1/Q |
0.918 | 0.356 | tNET | RR | 1 | BSRAM_R10[6] | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s/DI[24] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 278 | PLL_L[1] | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
0.364 | 0.364 | tNET | RR | 1 | BSRAM_R10[6] | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s/CLKA |
0.613 | 0.249 | tHld | 1 | BSRAM_R10[6] | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s |
Path Statistics:
Clock Skew | -0.018 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.381, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.356, 66.434%; tC2Q: 0.180, 33.566% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.364, 100.000% |
Path8
Path Summary:
Slack | 0.312 |
Data Arrival Time | 0.925 |
Data Required Time | 0.613 |
From | u_p2b/u_p2b_0/mid_data_3_s1 |
To | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 278 | PLL_L[1] | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
0.381 | 0.381 | tNET | RR | 1 | R8C26[0][A] | u_p2b/u_p2b_0/mid_data_3_s1/CLK |
0.561 | 0.180 | tC2Q | RR | 1 | R8C26[0][A] | u_p2b/u_p2b_0/mid_data_3_s1/Q |
0.925 | 0.364 | tNET | RR | 1 | BSRAM_R10[6] | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s/DI[3] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 278 | PLL_L[1] | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
0.364 | 0.364 | tNET | RR | 1 | BSRAM_R10[6] | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s/CLKA |
0.613 | 0.249 | tHld | 1 | BSRAM_R10[6] | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s |
Path Statistics:
Clock Skew | -0.018 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.381, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.364, 66.897%; tC2Q: 0.180, 33.103% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.364, 100.000% |
Path9
Path Summary:
Slack | 0.316 |
Data Arrival Time | 0.798 |
Data Required Time | 0.482 |
From | u_p2b/u_p2b_0/u_mid_buf/rWPtrBin_5_s0 |
To | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 278 | PLL_L[1] | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
0.375 | 0.375 | tNET | RR | 1 | R9C22[1][B] | u_p2b/u_p2b_0/u_mid_buf/rWPtrBin_5_s0/CLK |
0.555 | 0.180 | tC2Q | RR | 5 | R9C22[1][B] | u_p2b/u_p2b_0/u_mid_buf/rWPtrBin_5_s0/Q |
0.798 | 0.242 | tNET | RR | 1 | BSRAM_R10[6] | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s/ADA[10] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 278 | PLL_L[1] | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
0.364 | 0.364 | tNET | RR | 1 | BSRAM_R10[6] | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s/CLKA |
0.482 | 0.118 | tHld | 1 | BSRAM_R10[6] | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s |
Path Statistics:
Clock Skew | -0.011 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.242, 57.396%; tC2Q: 0.180, 42.604% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.364, 100.000% |
Path10
Path Summary:
Slack | 0.343 |
Data Arrival Time | 0.956 |
Data Required Time | 0.613 |
From | u_p2b/u_p2b_0/mid_data_23_s1 |
To | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 278 | PLL_L[1] | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
0.370 | 0.370 | tNET | RR | 1 | R9C27[0][A] | u_p2b/u_p2b_0/mid_data_23_s1/CLK |
0.550 | 0.180 | tC2Q | RR | 1 | R9C27[0][A] | u_p2b/u_p2b_0/mid_data_23_s1/Q |
0.956 | 0.406 | tNET | RR | 1 | BSRAM_R10[6] | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s/DI[23] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 278 | PLL_L[1] | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
0.364 | 0.364 | tNET | RR | 1 | BSRAM_R10[6] | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s/CLKA |
0.613 | 0.249 | tHld | 1 | BSRAM_R10[6] | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s |
Path Statistics:
Clock Skew | -0.006 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.370, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.406, 69.296%; tC2Q: 0.180, 30.704% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.364, 100.000% |
Path11
Path Summary:
Slack | 0.351 |
Data Arrival Time | 0.964 |
Data Required Time | 0.613 |
From | u_p2b/u_p2b_0/mid_data_4_s1 |
To | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 278 | PLL_L[1] | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
0.370 | 0.370 | tNET | RR | 1 | R9C27[1][A] | u_p2b/u_p2b_0/mid_data_4_s1/CLK |
0.550 | 0.180 | tC2Q | RR | 1 | R9C27[1][A] | u_p2b/u_p2b_0/mid_data_4_s1/Q |
0.964 | 0.414 | tNET | RR | 1 | BSRAM_R10[6] | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s/DI[4] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 278 | PLL_L[1] | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
0.364 | 0.364 | tNET | RR | 1 | BSRAM_R10[6] | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s/CLKA |
0.613 | 0.249 | tHld | 1 | BSRAM_R10[6] | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s |
Path Statistics:
Clock Skew | -0.006 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.370, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.414, 69.684%; tC2Q: 0.180, 30.316% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.364, 100.000% |
Path12
Path Summary:
Slack | 0.355 |
Data Arrival Time | 0.968 |
Data Required Time | 0.613 |
From | u_p2b/u_p2b_0/mid_data_7_s1 |
To | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 278 | PLL_L[1] | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
0.376 | 0.376 | tNET | RR | 1 | R8C27[0][A] | u_p2b/u_p2b_0/mid_data_7_s1/CLK |
0.556 | 0.180 | tC2Q | RR | 1 | R8C27[0][A] | u_p2b/u_p2b_0/mid_data_7_s1/Q |
0.968 | 0.411 | tNET | RR | 1 | BSRAM_R10[6] | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s/DI[7] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 278 | PLL_L[1] | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
0.364 | 0.364 | tNET | RR | 1 | BSRAM_R10[6] | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s/CLKA |
0.613 | 0.249 | tHld | 1 | BSRAM_R10[6] | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s |
Path Statistics:
Clock Skew | -0.013 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.376, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.411, 69.556%; tC2Q: 0.180, 30.444% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.364, 100.000% |
Path13
Path Summary:
Slack | 0.356 |
Data Arrival Time | 0.969 |
Data Required Time | 0.613 |
From | u_p2b/u_p2b_0/mid_data_20_s1 |
To | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 278 | PLL_L[1] | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
0.375 | 0.375 | tNET | RR | 1 | R9C28[1][A] | u_p2b/u_p2b_0/mid_data_20_s1/CLK |
0.555 | 0.180 | tC2Q | RR | 1 | R9C28[1][A] | u_p2b/u_p2b_0/mid_data_20_s1/Q |
0.969 | 0.414 | tNET | RR | 1 | BSRAM_R10[6] | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s/DI[20] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 278 | PLL_L[1] | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
0.364 | 0.364 | tNET | RR | 1 | BSRAM_R10[6] | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s/CLKA |
0.613 | 0.249 | tHld | 1 | BSRAM_R10[6] | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s |
Path Statistics:
Clock Skew | -0.011 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.414, 69.684%; tC2Q: 0.180, 30.316% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.364, 100.000% |
Path14
Path Summary:
Slack | 0.371 |
Data Arrival Time | 0.853 |
Data Required Time | 0.482 |
From | u_p2b/u_p2b_0/u_mid_buf/rWPtrBin_2_s0 |
To | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 278 | PLL_L[1] | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
0.376 | 0.376 | tNET | RR | 1 | R8C23[0][A] | u_p2b/u_p2b_0/u_mid_buf/rWPtrBin_2_s0/CLK |
0.556 | 0.180 | tC2Q | RR | 6 | R8C23[0][A] | u_p2b/u_p2b_0/u_mid_buf/rWPtrBin_2_s0/Q |
0.853 | 0.296 | tNET | RR | 1 | BSRAM_R10[6] | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s/ADA[7] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 278 | PLL_L[1] | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
0.364 | 0.364 | tNET | RR | 1 | BSRAM_R10[6] | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s/CLKA |
0.482 | 0.118 | tHld | 1 | BSRAM_R10[6] | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s |
Path Statistics:
Clock Skew | -0.013 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.376, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.296, 62.205%; tC2Q: 0.180, 37.795% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.364, 100.000% |
Path15
Path Summary:
Slack | 0.371 |
Data Arrival Time | 0.984 |
Data Required Time | 0.613 |
From | u_p2b/u_p2b_0/mid_data_29_s1 |
To | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 278 | PLL_L[1] | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
0.351 | 0.351 | tNET | RR | 1 | R12C26[0][A] | u_p2b/u_p2b_0/mid_data_29_s1/CLK |
0.531 | 0.180 | tC2Q | RR | 1 | R12C26[0][A] | u_p2b/u_p2b_0/mid_data_29_s1/Q |
0.984 | 0.453 | tNET | RR | 1 | BSRAM_R10[6] | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s/DI[29] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 278 | PLL_L[1] | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
0.364 | 0.364 | tNET | RR | 1 | BSRAM_R10[6] | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s/CLKA |
0.613 | 0.249 | tHld | 1 | BSRAM_R10[6] | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s |
Path Statistics:
Clock Skew | 0.013 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.351, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.453, 71.542%; tC2Q: 0.180, 28.458% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.364, 100.000% |
Path16
Path Summary:
Slack | 0.374 |
Data Arrival Time | 0.986 |
Data Required Time | 0.613 |
From | u_p2b/u_p2b_0/mid_data_25_s1 |
To | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 278 | PLL_L[1] | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
0.346 | 0.346 | tNET | RR | 1 | R12C27[0][B] | u_p2b/u_p2b_0/mid_data_25_s1/CLK |
0.526 | 0.180 | tC2Q | RR | 1 | R12C27[0][B] | u_p2b/u_p2b_0/mid_data_25_s1/Q |
0.986 | 0.460 | tNET | RR | 1 | BSRAM_R10[6] | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s/DI[25] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 278 | PLL_L[1] | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
0.364 | 0.364 | tNET | RR | 1 | BSRAM_R10[6] | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s/CLKA |
0.613 | 0.249 | tHld | 1 | BSRAM_R10[6] | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s |
Path Statistics:
Clock Skew | 0.018 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.346, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.460, 71.875%; tC2Q: 0.180, 28.125% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.364, 100.000% |
Path17
Path Summary:
Slack | 0.374 |
Data Arrival Time | 0.751 |
Data Required Time | 0.378 |
From | u_p2b/u_p2b_0/u_mid_buf/rWPtrGray_0_s1 |
To | u_p2b/u_p2b_0/u_mid_buf/rWPtrGray_0_s1 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 278 | PLL_L[1] | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
0.376 | 0.376 | tNET | RR | 1 | R8C23[1][A] | u_p2b/u_p2b_0/u_mid_buf/rWPtrGray_0_s1/CLK |
0.553 | 0.176 | tC2Q | RF | 2 | R8C23[1][A] | u_p2b/u_p2b_0/u_mid_buf/rWPtrGray_0_s1/Q |
0.560 | 0.008 | tNET | FF | 1 | R8C23[1][A] | u_p2b/u_p2b_0/u_mid_buf/wWPtrGrayNext_0_s3/I0 |
0.751 | 0.191 | tINS | FF | 1 | R8C23[1][A] | u_p2b/u_p2b_0/u_mid_buf/wWPtrGrayNext_0_s3/F |
0.751 | 0.000 | tNET | FF | 1 | R8C23[1][A] | u_p2b/u_p2b_0/u_mid_buf/rWPtrGray_0_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 278 | PLL_L[1] | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
0.376 | 0.376 | tNET | RR | 1 | R8C23[1][A] | u_p2b/u_p2b_0/u_mid_buf/rWPtrGray_0_s1/CLK |
0.378 | 0.001 | tHld | 1 | R8C23[1][A] | u_p2b/u_p2b_0/u_mid_buf/rWPtrGray_0_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.376, 100.000% |
Arrival Data Path Delay | cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.376, 100.000% |
Path18
Path Summary:
Slack | 0.374 |
Data Arrival Time | 0.756 |
Data Required Time | 0.383 |
From | u_test_gen/De_hcnt_4_s3 |
To | u_test_gen/De_hcnt_4_s3 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 278 | PLL_L[1] | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
0.381 | 0.381 | tNET | RR | 1 | R8C40[0][A] | u_test_gen/De_hcnt_4_s3/CLK |
0.558 | 0.176 | tC2Q | RF | 9 | R8C40[0][A] | u_test_gen/De_hcnt_4_s3/Q |
0.565 | 0.008 | tNET | FF | 1 | R8C40[0][A] | u_test_gen/n501_s6/I2 |
0.756 | 0.191 | tINS | FF | 1 | R8C40[0][A] | u_test_gen/n501_s6/F |
0.756 | 0.000 | tNET | FF | 1 | R8C40[0][A] | u_test_gen/De_hcnt_4_s3/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 278 | PLL_L[1] | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
0.381 | 0.381 | tNET | RR | 1 | R8C40[0][A] | u_test_gen/De_hcnt_4_s3/CLK |
0.383 | 0.001 | tHld | 1 | R8C40[0][A] | u_test_gen/De_hcnt_4_s3 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.381, 100.000% |
Arrival Data Path Delay | cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.381, 100.000% |
Path19
Path Summary:
Slack | 0.374 |
Data Arrival Time | 0.745 |
Data Required Time | 0.371 |
From | u_test_gen/De_hcnt_10_s3 |
To | u_test_gen/De_hcnt_10_s3 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 278 | PLL_L[1] | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
0.370 | 0.370 | tNET | RR | 1 | R9C35[0][A] | u_test_gen/De_hcnt_10_s3/CLK |
0.546 | 0.176 | tC2Q | RF | 5 | R9C35[0][A] | u_test_gen/De_hcnt_10_s3/Q |
0.554 | 0.008 | tNET | FF | 1 | R9C35[0][A] | u_test_gen/n495_s6/I0 |
0.745 | 0.191 | tINS | FF | 1 | R9C35[0][A] | u_test_gen/n495_s6/F |
0.745 | 0.000 | tNET | FF | 1 | R9C35[0][A] | u_test_gen/De_hcnt_10_s3/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 278 | PLL_L[1] | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
0.370 | 0.370 | tNET | RR | 1 | R9C35[0][A] | u_test_gen/De_hcnt_10_s3/CLK |
0.371 | 0.001 | tHld | 1 | R9C35[0][A] | u_test_gen/De_hcnt_10_s3 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.370, 100.000% |
Arrival Data Path Delay | cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.370, 100.000% |
Path20
Path Summary:
Slack | 0.374 |
Data Arrival Time | 0.750 |
Data Required Time | 0.376 |
From | u_test_gen/De_vcnt_2_s1 |
To | u_test_gen/De_vcnt_2_s1 |
Launch Clk | pixel_clk:[R] |
Latch Clk | pixel_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 278 | PLL_L[1] | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
0.375 | 0.375 | tNET | RR | 1 | R9C40[0][A] | u_test_gen/De_vcnt_2_s1/CLK |
0.551 | 0.176 | tC2Q | RF | 4 | R9C40[0][A] | u_test_gen/De_vcnt_2_s1/Q |
0.559 | 0.008 | tNET | FF | 1 | R9C40[0][A] | u_test_gen/n557_s2/I3 |
0.750 | 0.191 | tINS | FF | 1 | R9C40[0][A] | u_test_gen/n557_s2/F |
0.750 | 0.000 | tNET | FF | 1 | R9C40[0][A] | u_test_gen/De_vcnt_2_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pixel_clk | ||||
0.000 | 0.000 | tCL | RR | 278 | PLL_L[1] | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
0.375 | 0.375 | tNET | RR | 1 | R9C40[0][A] | u_test_gen/De_vcnt_2_s1/CLK |
0.376 | 0.001 | tHld | 1 | R9C40[0][A] | u_test_gen/De_vcnt_2_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Arrival Data Path Delay | cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Hold Analysis Report[2]:
Report Command:report_timing -hold -from_clock [get_clocks {byte_clk}] -max_paths 20 -max_common_paths 1
Path1
Path Summary:
Slack | 0.068 |
Data Arrival Time | 0.691 |
Data Required Time | 0.623 |
From | u_dsi_tx/u_tx/u_dsi_tx/rHsd_30_s0 |
To | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.385 | 0.385 | tNET | RR | 1 | R24C34[1][A] | u_dsi_tx/u_tx/u_dsi_tx/rHsd_30_s0/CLK |
0.565 | 0.180 | tC2Q | RR | 1 | R24C34[1][A] | u_dsi_tx/u_tx/u_dsi_tx/rHsd_30_s0/Q |
0.691 | 0.126 | tNET | RR | 1 | BSRAM_R28[9] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DI[12] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.374 | 0.374 | tNET | RR | 1 | BSRAM_R28[9] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/CLKA |
0.623 | 0.249 | tHld | 1 | BSRAM_R28[9] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s |
Path Statistics:
Clock Skew | -0.011 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.385, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.126, 41.224%; tC2Q: 0.180, 58.776% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.374, 100.000% |
Path2
Path Summary:
Slack | 0.068 |
Data Arrival Time | 0.691 |
Data Required Time | 0.623 |
From | u_dsi_tx/u_tx/u_dsi_tx/rHsd_29_s0 |
To | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.385 | 0.385 | tNET | RR | 1 | R24C34[0][A] | u_dsi_tx/u_tx/u_dsi_tx/rHsd_29_s0/CLK |
0.565 | 0.180 | tC2Q | RR | 1 | R24C34[0][A] | u_dsi_tx/u_tx/u_dsi_tx/rHsd_29_s0/Q |
0.691 | 0.126 | tNET | RR | 1 | BSRAM_R28[9] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DI[11] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.374 | 0.374 | tNET | RR | 1 | BSRAM_R28[9] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/CLKA |
0.623 | 0.249 | tHld | 1 | BSRAM_R28[9] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s |
Path Statistics:
Clock Skew | -0.011 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.385, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.126, 41.224%; tC2Q: 0.180, 58.776% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.374, 100.000% |
Path3
Path Summary:
Slack | 0.151 |
Data Arrival Time | 0.400 |
Data Required Time | 0.249 |
From | u_la0_top/u_ao_mem_ctrl/data_reg_0_s0 |
To | u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.000 | 0.000 | tNET | RR | 1 | R6C7[2][A] | u_la0_top/u_ao_mem_ctrl/data_reg_0_s0/CLK |
0.180 | 0.180 | tC2Q | RR | 1 | R6C7[2][A] | u_la0_top/u_ao_mem_ctrl/data_reg_0_s0/Q |
0.400 | 0.220 | tNET | RR | 1 | BSRAM_R10[0] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[0] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.000 | 0.000 | tNET | RR | 1 | BSRAM_R10[0] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA |
0.249 | 0.249 | tHld | 1 | BSRAM_R10[0] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.220, 55.000%; tC2Q: 0.180, 45.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path4
Path Summary:
Slack | 0.167 |
Data Arrival Time | 0.416 |
Data Required Time | 0.249 |
From | u_la0_top/u_ao_mem_ctrl/data_reg_56_s0 |
To | u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.000 | 0.000 | tNET | RR | 1 | R9C13[1][B] | u_la0_top/u_ao_mem_ctrl/data_reg_56_s0/CLK |
0.180 | 0.180 | tC2Q | RR | 1 | R9C13[1][B] | u_la0_top/u_ao_mem_ctrl/data_reg_56_s0/Q |
0.416 | 0.236 | tNET | RR | 1 | BSRAM_R10[3] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/DI[2] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.000 | 0.000 | tNET | RR | 1 | BSRAM_R10[3] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/CLKA |
0.249 | 0.249 | tHld | 1 | BSRAM_R10[3] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.236, 56.757%; tC2Q: 0.180, 43.243% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path5
Path Summary:
Slack | 0.193 |
Data Arrival Time | 0.815 |
Data Required Time | 0.623 |
From | u_dsi_tx/u_tx/u_dsi_tx/rHsd_27_s0 |
To | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.389 | 0.389 | tNET | RR | 1 | R22C30[0][A] | u_dsi_tx/u_tx/u_dsi_tx/rHsd_27_s0/CLK |
0.569 | 0.180 | tC2Q | RR | 1 | R22C30[0][A] | u_dsi_tx/u_tx/u_dsi_tx/rHsd_27_s0/Q |
0.815 | 0.246 | tNET | RR | 1 | BSRAM_R28[9] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DI[9] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.374 | 0.374 | tNET | RR | 1 | BSRAM_R28[9] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/CLKA |
0.623 | 0.249 | tHld | 1 | BSRAM_R28[9] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s |
Path Statistics:
Clock Skew | -0.015 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.389, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.246, 57.771%; tC2Q: 0.180, 42.229% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.374, 100.000% |
Path6
Path Summary:
Slack | 0.217 |
Data Arrival Time | 0.466 |
Data Required Time | 0.249 |
From | u_la0_top/u_ao_mem_ctrl/data_reg_59_s0 |
To | u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.000 | 0.000 | tNET | RR | 1 | R9C13[2][A] | u_la0_top/u_ao_mem_ctrl/data_reg_59_s0/CLK |
0.180 | 0.180 | tC2Q | RR | 1 | R9C13[2][A] | u_la0_top/u_ao_mem_ctrl/data_reg_59_s0/Q |
0.466 | 0.286 | tNET | RR | 1 | BSRAM_R10[3] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/DI[5] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.000 | 0.000 | tNET | RR | 1 | BSRAM_R10[3] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/CLKA |
0.249 | 0.249 | tHld | 1 | BSRAM_R10[3] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.286, 61.394%; tC2Q: 0.180, 38.606% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path7
Path Summary:
Slack | 0.240 |
Data Arrival Time | 0.863 |
Data Required Time | 0.623 |
From | u_dsi_tx/u_tx/u_dsi_tx/rHsd_28_s0 |
To | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.387 | 0.387 | tNET | RR | 1 | R23C34[0][A] | u_dsi_tx/u_tx/u_dsi_tx/rHsd_28_s0/CLK |
0.567 | 0.180 | tC2Q | RR | 1 | R23C34[0][A] | u_dsi_tx/u_tx/u_dsi_tx/rHsd_28_s0/Q |
0.863 | 0.296 | tNET | RR | 1 | BSRAM_R28[9] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DI[10] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.374 | 0.374 | tNET | RR | 1 | BSRAM_R28[9] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/CLKA |
0.623 | 0.249 | tHld | 1 | BSRAM_R28[9] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s |
Path Statistics:
Clock Skew | -0.013 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.387, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.296, 62.205%; tC2Q: 0.180, 37.795% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.374, 100.000% |
Path8
Path Summary:
Slack | 0.261 |
Data Arrival Time | 0.510 |
Data Required Time | 0.249 |
From | u_la0_top/u_ao_mem_ctrl/data_reg_61_s0 |
To | u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.000 | 0.000 | tNET | RR | 1 | R9C13[2][B] | u_la0_top/u_ao_mem_ctrl/data_reg_61_s0/CLK |
0.180 | 0.180 | tC2Q | RR | 1 | R9C13[2][B] | u_la0_top/u_ao_mem_ctrl/data_reg_61_s0/Q |
0.510 | 0.330 | tNET | RR | 1 | BSRAM_R10[3] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/DI[7] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.000 | 0.000 | tNET | RR | 1 | BSRAM_R10[3] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/CLKA |
0.249 | 0.249 | tHld | 1 | BSRAM_R10[3] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.330, 64.706%; tC2Q: 0.180, 35.294% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path9
Path Summary:
Slack | 0.270 |
Data Arrival Time | 0.519 |
Data Required Time | 0.249 |
From | u_la0_top/u_ao_mem_ctrl/data_reg_41_s0 |
To | u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.000 | 0.000 | tNET | RR | 1 | R11C11[2][B] | u_la0_top/u_ao_mem_ctrl/data_reg_41_s0/CLK |
0.180 | 0.180 | tC2Q | RR | 1 | R11C11[2][B] | u_la0_top/u_ao_mem_ctrl/data_reg_41_s0/Q |
0.519 | 0.339 | tNET | RR | 1 | BSRAM_R10[2] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/DI[5] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.000 | 0.000 | tNET | RR | 1 | BSRAM_R10[2] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CLKA |
0.249 | 0.249 | tHld | 1 | BSRAM_R10[2] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.339, 65.301%; tC2Q: 0.180, 34.699% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path10
Path Summary:
Slack | 0.270 |
Data Arrival Time | 0.519 |
Data Required Time | 0.249 |
From | u_la0_top/u_ao_mem_ctrl/data_reg_39_s0 |
To | u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.000 | 0.000 | tNET | RR | 1 | R11C11[1][B] | u_la0_top/u_ao_mem_ctrl/data_reg_39_s0/CLK |
0.180 | 0.180 | tC2Q | RR | 1 | R11C11[1][B] | u_la0_top/u_ao_mem_ctrl/data_reg_39_s0/Q |
0.519 | 0.339 | tNET | RR | 1 | BSRAM_R10[2] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/DI[3] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.000 | 0.000 | tNET | RR | 1 | BSRAM_R10[2] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CLKA |
0.249 | 0.249 | tHld | 1 | BSRAM_R10[2] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.339, 65.301%; tC2Q: 0.180, 34.699% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path11
Path Summary:
Slack | 0.271 |
Data Arrival Time | 0.520 |
Data Required Time | 0.249 |
From | u_la0_top/u_ao_mem_ctrl/data_reg_40_s0 |
To | u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.000 | 0.000 | tNET | RR | 1 | R11C11[2][A] | u_la0_top/u_ao_mem_ctrl/data_reg_40_s0/CLK |
0.180 | 0.180 | tC2Q | RR | 1 | R11C11[2][A] | u_la0_top/u_ao_mem_ctrl/data_reg_40_s0/Q |
0.520 | 0.340 | tNET | RR | 1 | BSRAM_R10[2] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/DI[4] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.000 | 0.000 | tNET | RR | 1 | BSRAM_R10[2] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CLKA |
0.249 | 0.249 | tHld | 1 | BSRAM_R10[2] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.340, 65.385%; tC2Q: 0.180, 34.615% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path12
Path Summary:
Slack | 0.290 |
Data Arrival Time | 0.539 |
Data Required Time | 0.249 |
From | u_la0_top/u_ao_mem_ctrl/data_reg_1_s0 |
To | u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.000 | 0.000 | tNET | RR | 1 | R5C8[2][A] | u_la0_top/u_ao_mem_ctrl/data_reg_1_s0/CLK |
0.180 | 0.180 | tC2Q | RR | 1 | R5C8[2][A] | u_la0_top/u_ao_mem_ctrl/data_reg_1_s0/Q |
0.539 | 0.359 | tNET | RR | 1 | BSRAM_R10[0] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[1] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.000 | 0.000 | tNET | RR | 1 | BSRAM_R10[0] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA |
0.249 | 0.249 | tHld | 1 | BSRAM_R10[0] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.359, 66.589%; tC2Q: 0.180, 33.411% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path13
Path Summary:
Slack | 0.295 |
Data Arrival Time | 0.544 |
Data Required Time | 0.249 |
From | u_la0_top/u_ao_mem_ctrl/data_reg_3_s0 |
To | u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.000 | 0.000 | tNET | RR | 1 | R6C7[2][B] | u_la0_top/u_ao_mem_ctrl/data_reg_3_s0/CLK |
0.180 | 0.180 | tC2Q | RR | 1 | R6C7[2][B] | u_la0_top/u_ao_mem_ctrl/data_reg_3_s0/Q |
0.544 | 0.364 | tNET | RR | 1 | BSRAM_R10[0] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[3] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.000 | 0.000 | tNET | RR | 1 | BSRAM_R10[0] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA |
0.249 | 0.249 | tHld | 1 | BSRAM_R10[0] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.364, 66.897%; tC2Q: 0.180, 33.103% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path14
Path Summary:
Slack | 0.297 |
Data Arrival Time | 0.415 |
Data Required Time | 0.118 |
From | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5 |
To | u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.000 | 0.000 | tNET | RR | 1 | R8C7[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/CLK |
0.180 | 0.180 | tC2Q | RR | 14 | R8C7[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/Q |
0.415 | 0.235 | tNET | RR | 1 | BSRAM_R10[0] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/ADA[3] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.000 | 0.000 | tNET | RR | 1 | BSRAM_R10[0] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA |
0.118 | 0.118 | tHld | 1 | BSRAM_R10[0] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.235, 56.627%; tC2Q: 0.180, 43.373% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path15
Path Summary:
Slack | 0.306 |
Data Arrival Time | 0.555 |
Data Required Time | 0.249 |
From | u_la0_top/u_ao_mem_ctrl/data_reg_26_s0 |
To | u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.000 | 0.000 | tNET | RR | 1 | R9C12[2][A] | u_la0_top/u_ao_mem_ctrl/data_reg_26_s0/CLK |
0.180 | 0.180 | tC2Q | RR | 1 | R9C12[2][A] | u_la0_top/u_ao_mem_ctrl/data_reg_26_s0/Q |
0.555 | 0.375 | tNET | RR | 1 | BSRAM_R10[1] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[8] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.000 | 0.000 | tNET | RR | 1 | BSRAM_R10[1] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA |
0.249 | 0.249 | tHld | 1 | BSRAM_R10[1] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.375, 67.568%; tC2Q: 0.180, 32.432% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path16
Path Summary:
Slack | 0.306 |
Data Arrival Time | 0.555 |
Data Required Time | 0.249 |
From | u_la0_top/u_ao_mem_ctrl/data_reg_24_s0 |
To | u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.000 | 0.000 | tNET | RR | 1 | R9C12[1][A] | u_la0_top/u_ao_mem_ctrl/data_reg_24_s0/CLK |
0.180 | 0.180 | tC2Q | RR | 1 | R9C12[1][A] | u_la0_top/u_ao_mem_ctrl/data_reg_24_s0/Q |
0.555 | 0.375 | tNET | RR | 1 | BSRAM_R10[1] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[6] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.000 | 0.000 | tNET | RR | 1 | BSRAM_R10[1] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA |
0.249 | 0.249 | tHld | 1 | BSRAM_R10[1] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.375, 67.568%; tC2Q: 0.180, 32.432% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path17
Path Summary:
Slack | 0.311 |
Data Arrival Time | 0.560 |
Data Required Time | 0.249 |
From | u_la0_top/u_ao_mem_ctrl/data_reg_54_s0 |
To | u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.000 | 0.000 | tNET | RR | 1 | R9C13[1][A] | u_la0_top/u_ao_mem_ctrl/data_reg_54_s0/CLK |
0.180 | 0.180 | tC2Q | RR | 1 | R9C13[1][A] | u_la0_top/u_ao_mem_ctrl/data_reg_54_s0/Q |
0.560 | 0.380 | tNET | RR | 1 | BSRAM_R10[3] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/DI[0] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.000 | 0.000 | tNET | RR | 1 | BSRAM_R10[3] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/CLKA |
0.249 | 0.249 | tHld | 1 | BSRAM_R10[3] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.380, 67.857%; tC2Q: 0.180, 32.143% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path18
Path Summary:
Slack | 0.318 |
Data Arrival Time | 0.436 |
Data Required Time | 0.118 |
From | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1 |
To | u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.000 | 0.000 | tNET | RR | 1 | R7C8[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK |
0.180 | 0.180 | tC2Q | RR | 12 | R7C8[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/Q |
0.436 | 0.256 | tNET | RR | 1 | BSRAM_R10[1] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/ADA[8] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.000 | 0.000 | tNET | RR | 1 | BSRAM_R10[1] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA |
0.118 | 0.118 | tHld | 1 | BSRAM_R10[1] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.256, 58.739%; tC2Q: 0.180, 41.261% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path19
Path Summary:
Slack | 0.318 |
Data Arrival Time | 0.567 |
Data Required Time | 0.249 |
From | u_la0_top/u_ao_mem_ctrl/data_reg_62_s0 |
To | u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.000 | 0.000 | tNET | RR | 1 | R9C13[3][A] | u_la0_top/u_ao_mem_ctrl/data_reg_62_s0/CLK |
0.180 | 0.180 | tC2Q | RR | 1 | R9C13[3][A] | u_la0_top/u_ao_mem_ctrl/data_reg_62_s0/Q |
0.567 | 0.388 | tNET | RR | 1 | BSRAM_R10[3] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/DI[8] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.000 | 0.000 | tNET | RR | 1 | BSRAM_R10[3] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/CLKA |
0.249 | 0.249 | tHld | 1 | BSRAM_R10[3] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.388, 68.282%; tC2Q: 0.180, 31.718% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path20
Path Summary:
Slack | 0.330 |
Data Arrival Time | 0.953 |
Data Required Time | 0.623 |
From | u_dsi_tx/u_tx/u_dsi_tx/rHsd_25_s0 |
To | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s |
Launch Clk | byte_clk:[R] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.397 | 0.397 | tNET | RR | 1 | R23C28[3][A] | u_dsi_tx/u_tx/u_dsi_tx/rHsd_25_s0/CLK |
0.577 | 0.180 | tC2Q | RR | 1 | R23C28[3][A] | u_dsi_tx/u_tx/u_dsi_tx/rHsd_25_s0/Q |
0.953 | 0.376 | tNET | RR | 1 | BSRAM_R28[9] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DI[7] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.374 | 0.374 | tNET | RR | 1 | BSRAM_R28[9] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/CLKA |
0.623 | 0.249 | tHld | 1 | BSRAM_R28[9] | u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s |
Path Statistics:
Clock Skew | -0.023 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.397, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.376, 67.640%; tC2Q: 0.180, 32.360% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.374, 100.000% |
Recovery Analysis Report
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 0.384 |
Data Arrival Time | 8.681 |
Data Required Time | 9.064 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_match_0/match_cnt_2_s1 |
Launch Clk | byte_clk:[F] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
4.706 | 4.706 | active clock edge time | ||||
4.706 | 0.000 | byte_clk | ||||
4.706 | 0.000 | tCL | FF | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
4.706 | 0.000 | tNET | FF | 1 | R3C4[2][A] | u_la0_top/rst_ao_s0/CLK |
5.148 | 0.442 | tC2Q | FF | 92 | R3C4[2][A] | u_la0_top/rst_ao_s0/Q |
8.681 | 3.532 | tNET | FF | 1 | R11C3[0][A] | u_la0_top/u_ao_match_0/match_cnt_2_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
9.412 | 0.000 | tNET | RR | 1 | R11C3[0][A] | u_la0_top/u_ao_match_0/match_cnt_2_s1/CLK |
9.064 | -0.347 | tSu | 1 | R11C3[0][A] | u_la0_top/u_ao_match_0/match_cnt_2_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 4.706 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.532, 88.867%; tC2Q: 0.442, 11.133% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path2
Path Summary:
Slack | 0.384 |
Data Arrival Time | 8.681 |
Data Required Time | 9.064 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_match_0/match_cnt_5_s1 |
Launch Clk | byte_clk:[F] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
4.706 | 4.706 | active clock edge time | ||||
4.706 | 0.000 | byte_clk | ||||
4.706 | 0.000 | tCL | FF | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
4.706 | 0.000 | tNET | FF | 1 | R3C4[2][A] | u_la0_top/rst_ao_s0/CLK |
5.148 | 0.442 | tC2Q | FF | 92 | R3C4[2][A] | u_la0_top/rst_ao_s0/Q |
8.681 | 3.532 | tNET | FF | 1 | R11C3[0][B] | u_la0_top/u_ao_match_0/match_cnt_5_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
9.412 | 0.000 | tNET | RR | 1 | R11C3[0][B] | u_la0_top/u_ao_match_0/match_cnt_5_s1/CLK |
9.064 | -0.347 | tSu | 1 | R11C3[0][B] | u_la0_top/u_ao_match_0/match_cnt_5_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 4.706 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.532, 88.867%; tC2Q: 0.442, 11.133% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path3
Path Summary:
Slack | 0.384 |
Data Arrival Time | 8.681 |
Data Required Time | 9.064 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_match_0/match_cnt_6_s1 |
Launch Clk | byte_clk:[F] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
4.706 | 4.706 | active clock edge time | ||||
4.706 | 0.000 | byte_clk | ||||
4.706 | 0.000 | tCL | FF | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
4.706 | 0.000 | tNET | FF | 1 | R3C4[2][A] | u_la0_top/rst_ao_s0/CLK |
5.148 | 0.442 | tC2Q | FF | 92 | R3C4[2][A] | u_la0_top/rst_ao_s0/Q |
8.681 | 3.532 | tNET | FF | 1 | R11C3[1][A] | u_la0_top/u_ao_match_0/match_cnt_6_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
9.412 | 0.000 | tNET | RR | 1 | R11C3[1][A] | u_la0_top/u_ao_match_0/match_cnt_6_s1/CLK |
9.064 | -0.347 | tSu | 1 | R11C3[1][A] | u_la0_top/u_ao_match_0/match_cnt_6_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 4.706 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.532, 88.867%; tC2Q: 0.442, 11.133% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path4
Path Summary:
Slack | 0.384 |
Data Arrival Time | 8.681 |
Data Required Time | 9.064 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_mem_ctrl/capture_length_0_s1 |
Launch Clk | byte_clk:[F] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
4.706 | 4.706 | active clock edge time | ||||
4.706 | 0.000 | byte_clk | ||||
4.706 | 0.000 | tCL | FF | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
4.706 | 0.000 | tNET | FF | 1 | R3C4[2][A] | u_la0_top/rst_ao_s0/CLK |
5.148 | 0.442 | tC2Q | FF | 92 | R3C4[2][A] | u_la0_top/rst_ao_s0/Q |
8.681 | 3.532 | tNET | FF | 1 | R11C3[3][A] | u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
9.412 | 0.000 | tNET | RR | 1 | R11C3[3][A] | u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLK |
9.064 | -0.347 | tSu | 1 | R11C3[3][A] | u_la0_top/u_ao_mem_ctrl/capture_length_0_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 4.706 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.532, 88.867%; tC2Q: 0.442, 11.133% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path5
Path Summary:
Slack | 0.384 |
Data Arrival Time | 8.681 |
Data Required Time | 9.064 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_mem_ctrl/capture_length_5_s1 |
Launch Clk | byte_clk:[F] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
4.706 | 4.706 | active clock edge time | ||||
4.706 | 0.000 | byte_clk | ||||
4.706 | 0.000 | tCL | FF | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
4.706 | 0.000 | tNET | FF | 1 | R3C4[2][A] | u_la0_top/rst_ao_s0/CLK |
5.148 | 0.442 | tC2Q | FF | 92 | R3C4[2][A] | u_la0_top/rst_ao_s0/Q |
8.681 | 3.532 | tNET | FF | 1 | R11C3[2][A] | u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
9.412 | 0.000 | tNET | RR | 1 | R11C3[2][A] | u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLK |
9.064 | -0.347 | tSu | 1 | R11C3[2][A] | u_la0_top/u_ao_mem_ctrl/capture_length_5_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 4.706 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.532, 88.867%; tC2Q: 0.442, 11.133% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path6
Path Summary:
Slack | 0.384 |
Data Arrival Time | 8.681 |
Data Required Time | 9.064 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_mem_ctrl/capture_length_6_s1 |
Launch Clk | byte_clk:[F] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
4.706 | 4.706 | active clock edge time | ||||
4.706 | 0.000 | byte_clk | ||||
4.706 | 0.000 | tCL | FF | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
4.706 | 0.000 | tNET | FF | 1 | R3C4[2][A] | u_la0_top/rst_ao_s0/CLK |
5.148 | 0.442 | tC2Q | FF | 92 | R3C4[2][A] | u_la0_top/rst_ao_s0/Q |
8.681 | 3.532 | tNET | FF | 1 | R11C3[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
9.412 | 0.000 | tNET | RR | 1 | R11C3[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLK |
9.064 | -0.347 | tSu | 1 | R11C3[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_6_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 4.706 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.532, 88.867%; tC2Q: 0.442, 11.133% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path7
Path Summary:
Slack | 0.393 |
Data Arrival Time | 8.671 |
Data Required Time | 9.064 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_match_3/match_cnt_10_s1 |
Launch Clk | byte_clk:[F] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
4.706 | 4.706 | active clock edge time | ||||
4.706 | 0.000 | byte_clk | ||||
4.706 | 0.000 | tCL | FF | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
4.706 | 0.000 | tNET | FF | 1 | R3C4[2][A] | u_la0_top/rst_ao_s0/CLK |
5.148 | 0.442 | tC2Q | FF | 92 | R3C4[2][A] | u_la0_top/rst_ao_s0/Q |
8.671 | 3.523 | tNET | FF | 1 | R11C5[0][A] | u_la0_top/u_ao_match_3/match_cnt_10_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
9.412 | 0.000 | tNET | RR | 1 | R11C5[0][A] | u_la0_top/u_ao_match_3/match_cnt_10_s1/CLK |
9.064 | -0.347 | tSu | 1 | R11C5[0][A] | u_la0_top/u_ao_match_3/match_cnt_10_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 4.706 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.523, 88.841%; tC2Q: 0.442, 11.159% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path8
Path Summary:
Slack | 0.393 |
Data Arrival Time | 8.671 |
Data Required Time | 9.064 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_match_3/trig_dly_in_0_s0 |
Launch Clk | byte_clk:[F] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
4.706 | 4.706 | active clock edge time | ||||
4.706 | 0.000 | byte_clk | ||||
4.706 | 0.000 | tCL | FF | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
4.706 | 0.000 | tNET | FF | 1 | R3C4[2][A] | u_la0_top/rst_ao_s0/CLK |
5.148 | 0.442 | tC2Q | FF | 92 | R3C4[2][A] | u_la0_top/rst_ao_s0/Q |
8.671 | 3.523 | tNET | FF | 1 | R11C5[2][A] | u_la0_top/u_ao_match_3/trig_dly_in_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
9.412 | 0.000 | tNET | RR | 1 | R11C5[2][A] | u_la0_top/u_ao_match_3/trig_dly_in_0_s0/CLK |
9.064 | -0.347 | tSu | 1 | R11C5[2][A] | u_la0_top/u_ao_match_3/trig_dly_in_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 4.706 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.523, 88.841%; tC2Q: 0.442, 11.159% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path9
Path Summary:
Slack | 0.393 |
Data Arrival Time | 8.671 |
Data Required Time | 9.064 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_mem_ctrl/capture_length_10_s1 |
Launch Clk | byte_clk:[F] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
4.706 | 4.706 | active clock edge time | ||||
4.706 | 0.000 | byte_clk | ||||
4.706 | 0.000 | tCL | FF | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
4.706 | 0.000 | tNET | FF | 1 | R3C4[2][A] | u_la0_top/rst_ao_s0/CLK |
5.148 | 0.442 | tC2Q | FF | 92 | R3C4[2][A] | u_la0_top/rst_ao_s0/Q |
8.671 | 3.523 | tNET | FF | 1 | R11C5[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_10_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
9.412 | 0.000 | tNET | RR | 1 | R11C5[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_10_s1/CLK |
9.064 | -0.347 | tSu | 1 | R11C5[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_10_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 4.706 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.523, 88.841%; tC2Q: 0.442, 11.159% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path10
Path Summary:
Slack | 0.393 |
Data Arrival Time | 8.671 |
Data Required Time | 9.064 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/internal_reg_start_syn_1_s0 |
Launch Clk | byte_clk:[F] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
4.706 | 4.706 | active clock edge time | ||||
4.706 | 0.000 | byte_clk | ||||
4.706 | 0.000 | tCL | FF | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
4.706 | 0.000 | tNET | FF | 1 | R3C4[2][A] | u_la0_top/rst_ao_s0/CLK |
5.148 | 0.442 | tC2Q | FF | 92 | R3C4[2][A] | u_la0_top/rst_ao_s0/Q |
8.671 | 3.523 | tNET | FF | 1 | R11C5[2][B] | u_la0_top/internal_reg_start_syn_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
9.412 | 0.000 | tNET | RR | 1 | R11C5[2][B] | u_la0_top/internal_reg_start_syn_1_s0/CLK |
9.064 | -0.347 | tSu | 1 | R11C5[2][B] | u_la0_top/internal_reg_start_syn_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 4.706 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.523, 88.841%; tC2Q: 0.442, 11.159% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path11
Path Summary:
Slack | 0.654 |
Data Arrival Time | 8.410 |
Data Required Time | 9.064 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_match_0/matched_s1 |
Launch Clk | byte_clk:[F] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
4.706 | 4.706 | active clock edge time | ||||
4.706 | 0.000 | byte_clk | ||||
4.706 | 0.000 | tCL | FF | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
4.706 | 0.000 | tNET | FF | 1 | R3C4[2][A] | u_la0_top/rst_ao_s0/CLK |
5.148 | 0.442 | tC2Q | FF | 92 | R3C4[2][A] | u_la0_top/rst_ao_s0/Q |
8.410 | 3.262 | tNET | FF | 1 | R4C10[0][A] | u_la0_top/u_ao_match_0/matched_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
9.412 | 0.000 | tNET | RR | 1 | R4C10[0][A] | u_la0_top/u_ao_match_0/matched_s1/CLK |
9.064 | -0.347 | tSu | 1 | R4C10[0][A] | u_la0_top/u_ao_match_0/matched_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 4.706 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.262, 88.055%; tC2Q: 0.442, 11.945% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path12
Path Summary:
Slack | 0.654 |
Data Arrival Time | 8.410 |
Data Required Time | 9.064 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1 |
Launch Clk | byte_clk:[F] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
4.706 | 4.706 | active clock edge time | ||||
4.706 | 0.000 | byte_clk | ||||
4.706 | 0.000 | tCL | FF | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
4.706 | 0.000 | tNET | FF | 1 | R3C4[2][A] | u_la0_top/rst_ao_s0/CLK |
5.148 | 0.442 | tC2Q | FF | 92 | R3C4[2][A] | u_la0_top/rst_ao_s0/Q |
8.410 | 3.262 | tNET | FF | 1 | R4C10[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
9.412 | 0.000 | tNET | RR | 1 | R4C10[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK |
9.064 | -0.347 | tSu | 1 | R4C10[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 4.706 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.262, 88.055%; tC2Q: 0.442, 11.945% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path13
Path Summary:
Slack | 0.654 |
Data Arrival Time | 8.410 |
Data Required Time | 9.064 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1 |
Launch Clk | byte_clk:[F] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
4.706 | 4.706 | active clock edge time | ||||
4.706 | 0.000 | byte_clk | ||||
4.706 | 0.000 | tCL | FF | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
4.706 | 0.000 | tNET | FF | 1 | R3C4[2][A] | u_la0_top/rst_ao_s0/CLK |
5.148 | 0.442 | tC2Q | FF | 92 | R3C4[2][A] | u_la0_top/rst_ao_s0/Q |
8.410 | 3.262 | tNET | FF | 1 | R4C10[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
9.412 | 0.000 | tNET | RR | 1 | R4C10[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK |
9.064 | -0.347 | tSu | 1 | R4C10[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 4.706 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.262, 88.055%; tC2Q: 0.442, 11.945% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path14
Path Summary:
Slack | 0.654 |
Data Arrival Time | 8.410 |
Data Required Time | 9.064 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1 |
Launch Clk | byte_clk:[F] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
4.706 | 4.706 | active clock edge time | ||||
4.706 | 0.000 | byte_clk | ||||
4.706 | 0.000 | tCL | FF | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
4.706 | 0.000 | tNET | FF | 1 | R3C4[2][A] | u_la0_top/rst_ao_s0/CLK |
5.148 | 0.442 | tC2Q | FF | 92 | R3C4[2][A] | u_la0_top/rst_ao_s0/Q |
8.410 | 3.262 | tNET | FF | 1 | R4C10[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
9.412 | 0.000 | tNET | RR | 1 | R4C10[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK |
9.064 | -0.347 | tSu | 1 | R4C10[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 4.706 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.262, 88.055%; tC2Q: 0.442, 11.945% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path15
Path Summary:
Slack | 0.657 |
Data Arrival Time | 8.408 |
Data Required Time | 9.064 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_match_3/matched_s1 |
Launch Clk | byte_clk:[F] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
4.706 | 4.706 | active clock edge time | ||||
4.706 | 0.000 | byte_clk | ||||
4.706 | 0.000 | tCL | FF | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
4.706 | 0.000 | tNET | FF | 1 | R3C4[2][A] | u_la0_top/rst_ao_s0/CLK |
5.148 | 0.442 | tC2Q | FF | 92 | R3C4[2][A] | u_la0_top/rst_ao_s0/Q |
8.408 | 3.259 | tNET | FF | 1 | R5C10[2][A] | u_la0_top/u_ao_match_3/matched_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
9.412 | 0.000 | tNET | RR | 1 | R5C10[2][A] | u_la0_top/u_ao_match_3/matched_s1/CLK |
9.064 | -0.347 | tSu | 1 | R5C10[2][A] | u_la0_top/u_ao_match_3/matched_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 4.706 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.259, 88.046%; tC2Q: 0.442, 11.954% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path16
Path Summary:
Slack | 0.657 |
Data Arrival Time | 8.408 |
Data Required Time | 9.064 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_match_0/match_sep_s0 |
Launch Clk | byte_clk:[F] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
4.706 | 4.706 | active clock edge time | ||||
4.706 | 0.000 | byte_clk | ||||
4.706 | 0.000 | tCL | FF | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
4.706 | 0.000 | tNET | FF | 1 | R3C4[2][A] | u_la0_top/rst_ao_s0/CLK |
5.148 | 0.442 | tC2Q | FF | 92 | R3C4[2][A] | u_la0_top/rst_ao_s0/Q |
8.408 | 3.259 | tNET | FF | 1 | R5C10[0][A] | u_la0_top/u_ao_match_0/match_sep_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
9.412 | 0.000 | tNET | RR | 1 | R5C10[0][A] | u_la0_top/u_ao_match_0/match_sep_s0/CLK |
9.064 | -0.347 | tSu | 1 | R5C10[0][A] | u_la0_top/u_ao_match_0/match_sep_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 4.706 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.259, 88.046%; tC2Q: 0.442, 11.954% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path17
Path Summary:
Slack | 0.657 |
Data Arrival Time | 8.408 |
Data Required Time | 9.064 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_mem_ctrl/capture_loop_s1 |
Launch Clk | byte_clk:[F] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
4.706 | 4.706 | active clock edge time | ||||
4.706 | 0.000 | byte_clk | ||||
4.706 | 0.000 | tCL | FF | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
4.706 | 0.000 | tNET | FF | 1 | R3C4[2][A] | u_la0_top/rst_ao_s0/CLK |
5.148 | 0.442 | tC2Q | FF | 92 | R3C4[2][A] | u_la0_top/rst_ao_s0/Q |
8.408 | 3.259 | tNET | FF | 1 | R5C10[1][A] | u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
9.412 | 0.000 | tNET | RR | 1 | R5C10[1][A] | u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK |
9.064 | -0.347 | tSu | 1 | R5C10[1][A] | u_la0_top/u_ao_mem_ctrl/capture_loop_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 4.706 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.259, 88.046%; tC2Q: 0.442, 11.954% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path18
Path Summary:
Slack | 0.657 |
Data Arrival Time | 8.408 |
Data Required Time | 9.064 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/internal_reg_start_dly_1_s0 |
Launch Clk | byte_clk:[F] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
4.706 | 4.706 | active clock edge time | ||||
4.706 | 0.000 | byte_clk | ||||
4.706 | 0.000 | tCL | FF | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
4.706 | 0.000 | tNET | FF | 1 | R3C4[2][A] | u_la0_top/rst_ao_s0/CLK |
5.148 | 0.442 | tC2Q | FF | 92 | R3C4[2][A] | u_la0_top/rst_ao_s0/Q |
8.408 | 3.259 | tNET | FF | 1 | R5C10[0][B] | u_la0_top/internal_reg_start_dly_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
9.412 | 0.000 | tNET | RR | 1 | R5C10[0][B] | u_la0_top/internal_reg_start_dly_1_s0/CLK |
9.064 | -0.347 | tSu | 1 | R5C10[0][B] | u_la0_top/internal_reg_start_dly_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 4.706 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.259, 88.046%; tC2Q: 0.442, 11.954% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path19
Path Summary:
Slack | 0.670 |
Data Arrival Time | 8.394 |
Data Required Time | 9.064 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1 |
Launch Clk | byte_clk:[F] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
4.706 | 4.706 | active clock edge time | ||||
4.706 | 0.000 | byte_clk | ||||
4.706 | 0.000 | tCL | FF | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
4.706 | 0.000 | tNET | FF | 1 | R3C4[2][A] | u_la0_top/rst_ao_s0/CLK |
5.148 | 0.442 | tC2Q | FF | 92 | R3C4[2][A] | u_la0_top/rst_ao_s0/Q |
8.394 | 3.246 | tNET | FF | 1 | R3C3[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
9.412 | 0.000 | tNET | RR | 1 | R3C3[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK |
9.064 | -0.347 | tSu | 1 | R3C3[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 4.706 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.246, 88.003%; tC2Q: 0.442, 11.997% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path20
Path Summary:
Slack | 0.670 |
Data Arrival Time | 8.394 |
Data Required Time | 9.064 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/internal_reg_force_triger_syn_0_s0 |
Launch Clk | byte_clk:[F] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
4.706 | 4.706 | active clock edge time | ||||
4.706 | 0.000 | byte_clk | ||||
4.706 | 0.000 | tCL | FF | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
4.706 | 0.000 | tNET | FF | 1 | R3C4[2][A] | u_la0_top/rst_ao_s0/CLK |
5.148 | 0.442 | tC2Q | FF | 92 | R3C4[2][A] | u_la0_top/rst_ao_s0/Q |
8.394 | 3.246 | tNET | FF | 1 | R3C4[1][A] | u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
9.412 | 0.000 | tNET | RR | 1 | R3C4[1][A] | u_la0_top/internal_reg_force_triger_syn_0_s0/CLK |
9.064 | -0.347 | tSu | 1 | R3C4[1][A] | u_la0_top/internal_reg_force_triger_syn_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 4.706 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.246, 88.003%; tC2Q: 0.442, 11.997% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path21
Path Summary:
Slack | 0.674 |
Data Arrival Time | 8.390 |
Data Required Time | 9.064 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/capture_window_sel_2_s1 |
Launch Clk | byte_clk:[F] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
4.706 | 4.706 | active clock edge time | ||||
4.706 | 0.000 | byte_clk | ||||
4.706 | 0.000 | tCL | FF | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
4.706 | 0.000 | tNET | FF | 1 | R3C4[2][A] | u_la0_top/rst_ao_s0/CLK |
5.148 | 0.442 | tC2Q | FF | 92 | R3C4[2][A] | u_la0_top/rst_ao_s0/Q |
8.390 | 3.242 | tNET | FF | 1 | R2C3[3][B] | u_la0_top/capture_window_sel_2_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
9.412 | 0.000 | tNET | RR | 1 | R2C3[3][B] | u_la0_top/capture_window_sel_2_s1/CLK |
9.064 | -0.347 | tSu | 1 | R2C3[3][B] | u_la0_top/capture_window_sel_2_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 4.706 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.242, 87.990%; tC2Q: 0.442, 12.010% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path22
Path Summary:
Slack | 0.674 |
Data Arrival Time | 8.390 |
Data Required Time | 9.064 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/capture_window_sel_3_s1 |
Launch Clk | byte_clk:[F] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
4.706 | 4.706 | active clock edge time | ||||
4.706 | 0.000 | byte_clk | ||||
4.706 | 0.000 | tCL | FF | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
4.706 | 0.000 | tNET | FF | 1 | R3C4[2][A] | u_la0_top/rst_ao_s0/CLK |
5.148 | 0.442 | tC2Q | FF | 92 | R3C4[2][A] | u_la0_top/rst_ao_s0/Q |
8.390 | 3.242 | tNET | FF | 1 | R2C3[3][A] | u_la0_top/capture_window_sel_3_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
9.412 | 0.000 | tNET | RR | 1 | R2C3[3][A] | u_la0_top/capture_window_sel_3_s1/CLK |
9.064 | -0.347 | tSu | 1 | R2C3[3][A] | u_la0_top/capture_window_sel_3_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 4.706 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.242, 87.990%; tC2Q: 0.442, 12.010% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path23
Path Summary:
Slack | 0.674 |
Data Arrival Time | 8.390 |
Data Required Time | 9.064 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/capture_window_sel_8_s1 |
Launch Clk | byte_clk:[F] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
4.706 | 4.706 | active clock edge time | ||||
4.706 | 0.000 | byte_clk | ||||
4.706 | 0.000 | tCL | FF | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
4.706 | 0.000 | tNET | FF | 1 | R3C4[2][A] | u_la0_top/rst_ao_s0/CLK |
5.148 | 0.442 | tC2Q | FF | 92 | R3C4[2][A] | u_la0_top/rst_ao_s0/Q |
8.390 | 3.242 | tNET | FF | 1 | R2C2[3][B] | u_la0_top/capture_window_sel_8_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
9.412 | 0.000 | tNET | RR | 1 | R2C2[3][B] | u_la0_top/capture_window_sel_8_s1/CLK |
9.064 | -0.347 | tSu | 1 | R2C2[3][B] | u_la0_top/capture_window_sel_8_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 4.706 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.242, 87.990%; tC2Q: 0.442, 12.010% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path24
Path Summary:
Slack | 0.674 |
Data Arrival Time | 8.390 |
Data Required Time | 9.064 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/capture_window_sel_9_s1 |
Launch Clk | byte_clk:[F] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
4.706 | 4.706 | active clock edge time | ||||
4.706 | 0.000 | byte_clk | ||||
4.706 | 0.000 | tCL | FF | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
4.706 | 0.000 | tNET | FF | 1 | R3C4[2][A] | u_la0_top/rst_ao_s0/CLK |
5.148 | 0.442 | tC2Q | FF | 92 | R3C4[2][A] | u_la0_top/rst_ao_s0/Q |
8.390 | 3.242 | tNET | FF | 1 | R2C2[3][A] | u_la0_top/capture_window_sel_9_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
9.412 | 0.000 | tNET | RR | 1 | R2C2[3][A] | u_la0_top/capture_window_sel_9_s1/CLK |
9.064 | -0.347 | tSu | 1 | R2C2[3][A] | u_la0_top/capture_window_sel_9_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 4.706 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.242, 87.990%; tC2Q: 0.442, 12.010% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path25
Path Summary:
Slack | 0.677 |
Data Arrival Time | 8.388 |
Data Required Time | 9.064 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_match_3/match_bitwise_pre_reg_1_s0 |
Launch Clk | byte_clk:[F] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
4.706 | 4.706 | active clock edge time | ||||
4.706 | 0.000 | byte_clk | ||||
4.706 | 0.000 | tCL | FF | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
4.706 | 0.000 | tNET | FF | 1 | R3C4[2][A] | u_la0_top/rst_ao_s0/CLK |
5.148 | 0.442 | tC2Q | FF | 92 | R3C4[2][A] | u_la0_top/rst_ao_s0/Q |
8.388 | 3.239 | tNET | FF | 1 | R7C8[1][B] | u_la0_top/u_ao_match_3/match_bitwise_pre_reg_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
9.412 | 9.412 | active clock edge time | ||||
9.412 | 0.000 | byte_clk | ||||
9.412 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
9.412 | 0.000 | tNET | RR | 1 | R7C8[1][B] | u_la0_top/u_ao_match_3/match_bitwise_pre_reg_1_s0/CLK |
9.064 | -0.347 | tSu | 1 | R7C8[1][B] | u_la0_top/u_ao_match_3/match_bitwise_pre_reg_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 4.706 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.239, 87.981%; tC2Q: 0.442, 12.019% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Removal Analysis Report
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 6.847 |
Data Arrival Time | 6.659 |
Data Required Time | -0.189 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1 |
Launch Clk | byte_clk:[F] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
4.706 | 4.706 | active clock edge time | ||||
4.706 | 0.000 | byte_clk | ||||
4.706 | 0.000 | tCL | FF | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
4.706 | 0.000 | tNET | FF | 1 | R3C4[2][A] | u_la0_top/rst_ao_s0/CLK |
4.904 | 0.198 | tC2Q | FR | 92 | R3C4[2][A] | u_la0_top/rst_ao_s0/Q |
6.658 | 1.755 | tNET | RR | 1 | R13C4[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.000 | 0.000 | tNET | RR | 1 | R13C4[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK |
-0.189 | -0.189 | tHld | 1 | R13C4[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | -4.706 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.755, 89.885%; tC2Q: 0.198, 10.115% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path2
Path Summary:
Slack | 6.847 |
Data Arrival Time | 6.659 |
Data Required Time | -0.189 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1 |
Launch Clk | byte_clk:[F] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
4.706 | 4.706 | active clock edge time | ||||
4.706 | 0.000 | byte_clk | ||||
4.706 | 0.000 | tCL | FF | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
4.706 | 0.000 | tNET | FF | 1 | R3C4[2][A] | u_la0_top/rst_ao_s0/CLK |
4.904 | 0.198 | tC2Q | FR | 92 | R3C4[2][A] | u_la0_top/rst_ao_s0/Q |
6.658 | 1.755 | tNET | RR | 1 | R13C4[2][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.000 | 0.000 | tNET | RR | 1 | R13C4[2][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK |
-0.189 | -0.189 | tHld | 1 | R13C4[2][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | -4.706 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.755, 89.885%; tC2Q: 0.198, 10.115% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path3
Path Summary:
Slack | 6.847 |
Data Arrival Time | 6.659 |
Data Required Time | -0.189 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1 |
Launch Clk | byte_clk:[F] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
4.706 | 4.706 | active clock edge time | ||||
4.706 | 0.000 | byte_clk | ||||
4.706 | 0.000 | tCL | FF | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
4.706 | 0.000 | tNET | FF | 1 | R3C4[2][A] | u_la0_top/rst_ao_s0/CLK |
4.904 | 0.198 | tC2Q | FR | 92 | R3C4[2][A] | u_la0_top/rst_ao_s0/Q |
6.658 | 1.755 | tNET | RR | 1 | R13C4[3][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.000 | 0.000 | tNET | RR | 1 | R13C4[3][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK |
-0.189 | -0.189 | tHld | 1 | R13C4[3][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | -4.706 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.755, 89.885%; tC2Q: 0.198, 10.115% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path4
Path Summary:
Slack | 6.857 |
Data Arrival Time | 6.668 |
Data Required Time | -0.189 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_match_3/match_cnt_0_s1 |
Launch Clk | byte_clk:[F] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
4.706 | 4.706 | active clock edge time | ||||
4.706 | 0.000 | byte_clk | ||||
4.706 | 0.000 | tCL | FF | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
4.706 | 0.000 | tNET | FF | 1 | R3C4[2][A] | u_la0_top/rst_ao_s0/CLK |
4.904 | 0.198 | tC2Q | FR | 92 | R3C4[2][A] | u_la0_top/rst_ao_s0/Q |
6.668 | 1.765 | tNET | RR | 1 | R11C2[2][A] | u_la0_top/u_ao_match_3/match_cnt_0_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.000 | 0.000 | tNET | RR | 1 | R11C2[2][A] | u_la0_top/u_ao_match_3/match_cnt_0_s1/CLK |
-0.189 | -0.189 | tHld | 1 | R11C2[2][A] | u_la0_top/u_ao_match_3/match_cnt_0_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | -4.706 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.765, 89.936%; tC2Q: 0.198, 10.064% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path5
Path Summary:
Slack | 6.857 |
Data Arrival Time | 6.668 |
Data Required Time | -0.189 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_match_3/match_cnt_5_s1 |
Launch Clk | byte_clk:[F] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
4.706 | 4.706 | active clock edge time | ||||
4.706 | 0.000 | byte_clk | ||||
4.706 | 0.000 | tCL | FF | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
4.706 | 0.000 | tNET | FF | 1 | R3C4[2][A] | u_la0_top/rst_ao_s0/CLK |
4.904 | 0.198 | tC2Q | FR | 92 | R3C4[2][A] | u_la0_top/rst_ao_s0/Q |
6.668 | 1.765 | tNET | RR | 1 | R11C4[2][A] | u_la0_top/u_ao_match_3/match_cnt_5_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.000 | 0.000 | tNET | RR | 1 | R11C4[2][A] | u_la0_top/u_ao_match_3/match_cnt_5_s1/CLK |
-0.189 | -0.189 | tHld | 1 | R11C4[2][A] | u_la0_top/u_ao_match_3/match_cnt_5_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | -4.706 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.765, 89.936%; tC2Q: 0.198, 10.064% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path6
Path Summary:
Slack | 6.857 |
Data Arrival Time | 6.668 |
Data Required Time | -0.189 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_match_3/match_cnt_6_s1 |
Launch Clk | byte_clk:[F] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
4.706 | 4.706 | active clock edge time | ||||
4.706 | 0.000 | byte_clk | ||||
4.706 | 0.000 | tCL | FF | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
4.706 | 0.000 | tNET | FF | 1 | R3C4[2][A] | u_la0_top/rst_ao_s0/CLK |
4.904 | 0.198 | tC2Q | FR | 92 | R3C4[2][A] | u_la0_top/rst_ao_s0/Q |
6.668 | 1.765 | tNET | RR | 1 | R11C4[2][B] | u_la0_top/u_ao_match_3/match_cnt_6_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.000 | 0.000 | tNET | RR | 1 | R11C4[2][B] | u_la0_top/u_ao_match_3/match_cnt_6_s1/CLK |
-0.189 | -0.189 | tHld | 1 | R11C4[2][B] | u_la0_top/u_ao_match_3/match_cnt_6_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | -4.706 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.765, 89.936%; tC2Q: 0.198, 10.064% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path7
Path Summary:
Slack | 6.857 |
Data Arrival Time | 6.668 |
Data Required Time | -0.189 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_match_3/match_cnt_9_s1 |
Launch Clk | byte_clk:[F] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
4.706 | 4.706 | active clock edge time | ||||
4.706 | 0.000 | byte_clk | ||||
4.706 | 0.000 | tCL | FF | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
4.706 | 0.000 | tNET | FF | 1 | R3C4[2][A] | u_la0_top/rst_ao_s0/CLK |
4.904 | 0.198 | tC2Q | FR | 92 | R3C4[2][A] | u_la0_top/rst_ao_s0/Q |
6.668 | 1.765 | tNET | RR | 1 | R13C3[0][A] | u_la0_top/u_ao_match_3/match_cnt_9_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.000 | 0.000 | tNET | RR | 1 | R13C3[0][A] | u_la0_top/u_ao_match_3/match_cnt_9_s1/CLK |
-0.189 | -0.189 | tHld | 1 | R13C3[0][A] | u_la0_top/u_ao_match_3/match_cnt_9_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | -4.706 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.765, 89.936%; tC2Q: 0.198, 10.064% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path8
Path Summary:
Slack | 6.857 |
Data Arrival Time | 6.668 |
Data Required Time | -0.189 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_match_3/match_cnt_11_s1 |
Launch Clk | byte_clk:[F] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
4.706 | 4.706 | active clock edge time | ||||
4.706 | 0.000 | byte_clk | ||||
4.706 | 0.000 | tCL | FF | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
4.706 | 0.000 | tNET | FF | 1 | R3C4[2][A] | u_la0_top/rst_ao_s0/CLK |
4.904 | 0.198 | tC2Q | FR | 92 | R3C4[2][A] | u_la0_top/rst_ao_s0/Q |
6.668 | 1.765 | tNET | RR | 1 | R11C2[2][B] | u_la0_top/u_ao_match_3/match_cnt_11_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.000 | 0.000 | tNET | RR | 1 | R11C2[2][B] | u_la0_top/u_ao_match_3/match_cnt_11_s1/CLK |
-0.189 | -0.189 | tHld | 1 | R11C2[2][B] | u_la0_top/u_ao_match_3/match_cnt_11_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | -4.706 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.765, 89.936%; tC2Q: 0.198, 10.064% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path9
Path Summary:
Slack | 6.857 |
Data Arrival Time | 6.668 |
Data Required Time | -0.189 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_match_3/match_sep_s0 |
Launch Clk | byte_clk:[F] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
4.706 | 4.706 | active clock edge time | ||||
4.706 | 0.000 | byte_clk | ||||
4.706 | 0.000 | tCL | FF | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
4.706 | 0.000 | tNET | FF | 1 | R3C4[2][A] | u_la0_top/rst_ao_s0/CLK |
4.904 | 0.198 | tC2Q | FR | 92 | R3C4[2][A] | u_la0_top/rst_ao_s0/Q |
6.668 | 1.765 | tNET | RR | 1 | R11C2[1][B] | u_la0_top/u_ao_match_3/match_sep_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.000 | 0.000 | tNET | RR | 1 | R11C2[1][B] | u_la0_top/u_ao_match_3/match_sep_s0/CLK |
-0.189 | -0.189 | tHld | 1 | R11C2[1][B] | u_la0_top/u_ao_match_3/match_sep_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | -4.706 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.765, 89.936%; tC2Q: 0.198, 10.064% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path10
Path Summary:
Slack | 6.857 |
Data Arrival Time | 6.668 |
Data Required Time | -0.189 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_match_3/match_bitwise_pre_reg_0_s0 |
Launch Clk | byte_clk:[F] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
4.706 | 4.706 | active clock edge time | ||||
4.706 | 0.000 | byte_clk | ||||
4.706 | 0.000 | tCL | FF | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
4.706 | 0.000 | tNET | FF | 1 | R3C4[2][A] | u_la0_top/rst_ao_s0/CLK |
4.904 | 0.198 | tC2Q | FR | 92 | R3C4[2][A] | u_la0_top/rst_ao_s0/Q |
6.668 | 1.765 | tNET | RR | 1 | R12C3[0][A] | u_la0_top/u_ao_match_3/match_bitwise_pre_reg_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.000 | 0.000 | tNET | RR | 1 | R12C3[0][A] | u_la0_top/u_ao_match_3/match_bitwise_pre_reg_0_s0/CLK |
-0.189 | -0.189 | tHld | 1 | R12C3[0][A] | u_la0_top/u_ao_match_3/match_bitwise_pre_reg_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | -4.706 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.765, 89.936%; tC2Q: 0.198, 10.064% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path11
Path Summary:
Slack | 6.857 |
Data Arrival Time | 6.668 |
Data Required Time | -0.189 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_match_1/trig_dly_in_0_s0 |
Launch Clk | byte_clk:[F] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
4.706 | 4.706 | active clock edge time | ||||
4.706 | 0.000 | byte_clk | ||||
4.706 | 0.000 | tCL | FF | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
4.706 | 0.000 | tNET | FF | 1 | R3C4[2][A] | u_la0_top/rst_ao_s0/CLK |
4.904 | 0.198 | tC2Q | FR | 92 | R3C4[2][A] | u_la0_top/rst_ao_s0/Q |
6.668 | 1.765 | tNET | RR | 1 | R12C3[0][B] | u_la0_top/u_ao_match_1/trig_dly_in_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.000 | 0.000 | tNET | RR | 1 | R12C3[0][B] | u_la0_top/u_ao_match_1/trig_dly_in_0_s0/CLK |
-0.189 | -0.189 | tHld | 1 | R12C3[0][B] | u_la0_top/u_ao_match_1/trig_dly_in_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | -4.706 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.765, 89.936%; tC2Q: 0.198, 10.064% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path12
Path Summary:
Slack | 6.857 |
Data Arrival Time | 6.668 |
Data Required Time | -0.189 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_match_0/match_cnt_9_s1 |
Launch Clk | byte_clk:[F] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
4.706 | 4.706 | active clock edge time | ||||
4.706 | 0.000 | byte_clk | ||||
4.706 | 0.000 | tCL | FF | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
4.706 | 0.000 | tNET | FF | 1 | R3C4[2][A] | u_la0_top/rst_ao_s0/CLK |
4.904 | 0.198 | tC2Q | FR | 92 | R3C4[2][A] | u_la0_top/rst_ao_s0/Q |
6.668 | 1.765 | tNET | RR | 1 | R13C3[1][A] | u_la0_top/u_ao_match_0/match_cnt_9_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.000 | 0.000 | tNET | RR | 1 | R13C3[1][A] | u_la0_top/u_ao_match_0/match_cnt_9_s1/CLK |
-0.189 | -0.189 | tHld | 1 | R13C3[1][A] | u_la0_top/u_ao_match_0/match_cnt_9_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | -4.706 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.765, 89.936%; tC2Q: 0.198, 10.064% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path13
Path Summary:
Slack | 6.857 |
Data Arrival Time | 6.668 |
Data Required Time | -0.189 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1 |
Launch Clk | byte_clk:[F] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
4.706 | 4.706 | active clock edge time | ||||
4.706 | 0.000 | byte_clk | ||||
4.706 | 0.000 | tCL | FF | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
4.706 | 0.000 | tNET | FF | 1 | R3C4[2][A] | u_la0_top/rst_ao_s0/CLK |
4.904 | 0.198 | tC2Q | FR | 92 | R3C4[2][A] | u_la0_top/rst_ao_s0/Q |
6.668 | 1.765 | tNET | RR | 1 | R11C2[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.000 | 0.000 | tNET | RR | 1 | R11C2[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK |
-0.189 | -0.189 | tHld | 1 | R11C2[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | -4.706 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.765, 89.936%; tC2Q: 0.198, 10.064% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path14
Path Summary:
Slack | 6.857 |
Data Arrival Time | 6.668 |
Data Required Time | -0.189 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1 |
Launch Clk | byte_clk:[F] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
4.706 | 4.706 | active clock edge time | ||||
4.706 | 0.000 | byte_clk | ||||
4.706 | 0.000 | tCL | FF | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
4.706 | 0.000 | tNET | FF | 1 | R3C4[2][A] | u_la0_top/rst_ao_s0/CLK |
4.904 | 0.198 | tC2Q | FR | 92 | R3C4[2][A] | u_la0_top/rst_ao_s0/Q |
6.668 | 1.765 | tNET | RR | 1 | R11C2[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.000 | 0.000 | tNET | RR | 1 | R11C2[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/CLK |
-0.189 | -0.189 | tHld | 1 | R11C2[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | -4.706 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.765, 89.936%; tC2Q: 0.198, 10.064% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path15
Path Summary:
Slack | 6.857 |
Data Arrival Time | 6.668 |
Data Required Time | -0.189 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_mem_ctrl/capture_length_9_s1 |
Launch Clk | byte_clk:[F] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
4.706 | 4.706 | active clock edge time | ||||
4.706 | 0.000 | byte_clk | ||||
4.706 | 0.000 | tCL | FF | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
4.706 | 0.000 | tNET | FF | 1 | R3C4[2][A] | u_la0_top/rst_ao_s0/CLK |
4.904 | 0.198 | tC2Q | FR | 92 | R3C4[2][A] | u_la0_top/rst_ao_s0/Q |
6.668 | 1.765 | tNET | RR | 1 | R13C3[2][A] | u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.000 | 0.000 | tNET | RR | 1 | R13C3[2][A] | u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLK |
-0.189 | -0.189 | tHld | 1 | R13C3[2][A] | u_la0_top/u_ao_mem_ctrl/capture_length_9_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | -4.706 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.765, 89.936%; tC2Q: 0.198, 10.064% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path16
Path Summary:
Slack | 6.857 |
Data Arrival Time | 6.668 |
Data Required Time | -0.189 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/start_reg_s0 |
Launch Clk | byte_clk:[F] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
4.706 | 4.706 | active clock edge time | ||||
4.706 | 0.000 | byte_clk | ||||
4.706 | 0.000 | tCL | FF | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
4.706 | 0.000 | tNET | FF | 1 | R3C4[2][A] | u_la0_top/rst_ao_s0/CLK |
4.904 | 0.198 | tC2Q | FR | 92 | R3C4[2][A] | u_la0_top/rst_ao_s0/Q |
6.668 | 1.765 | tNET | RR | 1 | R11C2[1][A] | u_la0_top/start_reg_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.000 | 0.000 | tNET | RR | 1 | R11C2[1][A] | u_la0_top/start_reg_s0/CLK |
-0.189 | -0.189 | tHld | 1 | R11C2[1][A] | u_la0_top/start_reg_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | -4.706 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.765, 89.936%; tC2Q: 0.198, 10.064% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path17
Path Summary:
Slack | 6.865 |
Data Arrival Time | 6.676 |
Data Required Time | -0.189 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_mem_ctrl/capture_length_7_s1 |
Launch Clk | byte_clk:[F] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
4.706 | 4.706 | active clock edge time | ||||
4.706 | 0.000 | byte_clk | ||||
4.706 | 0.000 | tCL | FF | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
4.706 | 0.000 | tNET | FF | 1 | R3C4[2][A] | u_la0_top/rst_ao_s0/CLK |
4.904 | 0.198 | tC2Q | FR | 92 | R3C4[2][A] | u_la0_top/rst_ao_s0/Q |
6.676 | 1.773 | tNET | RR | 1 | R9C8[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.000 | 0.000 | tNET | RR | 1 | R9C8[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLK |
-0.189 | -0.189 | tHld | 1 | R9C8[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_7_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | -4.706 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.773, 89.975%; tC2Q: 0.198, 10.025% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path18
Path Summary:
Slack | 6.865 |
Data Arrival Time | 6.676 |
Data Required Time | -0.189 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_mem_ctrl/capture_length_8_s1 |
Launch Clk | byte_clk:[F] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
4.706 | 4.706 | active clock edge time | ||||
4.706 | 0.000 | byte_clk | ||||
4.706 | 0.000 | tCL | FF | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
4.706 | 0.000 | tNET | FF | 1 | R3C4[2][A] | u_la0_top/rst_ao_s0/CLK |
4.904 | 0.198 | tC2Q | FR | 92 | R3C4[2][A] | u_la0_top/rst_ao_s0/Q |
6.676 | 1.773 | tNET | RR | 1 | R9C8[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.000 | 0.000 | tNET | RR | 1 | R9C8[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLK |
-0.189 | -0.189 | tHld | 1 | R9C8[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_8_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | -4.706 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.773, 89.975%; tC2Q: 0.198, 10.025% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path19
Path Summary:
Slack | 6.870 |
Data Arrival Time | 6.681 |
Data Required Time | -0.189 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_match_0/match_cnt_7_s1 |
Launch Clk | byte_clk:[F] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
4.706 | 4.706 | active clock edge time | ||||
4.706 | 0.000 | byte_clk | ||||
4.706 | 0.000 | tCL | FF | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
4.706 | 0.000 | tNET | FF | 1 | R3C4[2][A] | u_la0_top/rst_ao_s0/CLK |
4.904 | 0.198 | tC2Q | FR | 92 | R3C4[2][A] | u_la0_top/rst_ao_s0/Q |
6.681 | 1.777 | tNET | RR | 1 | R9C8[0][A] | u_la0_top/u_ao_match_0/match_cnt_7_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.000 | 0.000 | tNET | RR | 1 | R9C8[0][A] | u_la0_top/u_ao_match_0/match_cnt_7_s1/CLK |
-0.189 | -0.189 | tHld | 1 | R9C8[0][A] | u_la0_top/u_ao_match_0/match_cnt_7_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | -4.706 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.777, 90.000%; tC2Q: 0.198, 10.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path20
Path Summary:
Slack | 6.870 |
Data Arrival Time | 6.681 |
Data Required Time | -0.189 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_match_0/match_cnt_8_s1 |
Launch Clk | byte_clk:[F] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
4.706 | 4.706 | active clock edge time | ||||
4.706 | 0.000 | byte_clk | ||||
4.706 | 0.000 | tCL | FF | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
4.706 | 0.000 | tNET | FF | 1 | R3C4[2][A] | u_la0_top/rst_ao_s0/CLK |
4.904 | 0.198 | tC2Q | FR | 92 | R3C4[2][A] | u_la0_top/rst_ao_s0/Q |
6.681 | 1.777 | tNET | RR | 1 | R9C8[0][B] | u_la0_top/u_ao_match_0/match_cnt_8_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.000 | 0.000 | tNET | RR | 1 | R9C8[0][B] | u_la0_top/u_ao_match_0/match_cnt_8_s1/CLK |
-0.189 | -0.189 | tHld | 1 | R9C8[0][B] | u_la0_top/u_ao_match_0/match_cnt_8_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | -4.706 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.777, 90.000%; tC2Q: 0.198, 10.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path21
Path Summary:
Slack | 6.870 |
Data Arrival Time | 6.681 |
Data Required Time | -0.189 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/capture_window_sel_0_s3 |
Launch Clk | byte_clk:[F] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
4.706 | 4.706 | active clock edge time | ||||
4.706 | 0.000 | byte_clk | ||||
4.706 | 0.000 | tCL | FF | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
4.706 | 0.000 | tNET | FF | 1 | R3C4[2][A] | u_la0_top/rst_ao_s0/CLK |
4.904 | 0.198 | tC2Q | FR | 92 | R3C4[2][A] | u_la0_top/rst_ao_s0/Q |
6.681 | 1.777 | tNET | RR | 1 | R9C2[2][A] | u_la0_top/capture_window_sel_0_s3/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.000 | 0.000 | tNET | RR | 1 | R9C2[2][A] | u_la0_top/capture_window_sel_0_s3/CLK |
-0.189 | -0.189 | tHld | 1 | R9C2[2][A] | u_la0_top/capture_window_sel_0_s3 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | -4.706 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.777, 90.000%; tC2Q: 0.198, 10.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path22
Path Summary:
Slack | 6.870 |
Data Arrival Time | 6.681 |
Data Required Time | -0.189 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/triger_s0 |
Launch Clk | byte_clk:[F] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
4.706 | 4.706 | active clock edge time | ||||
4.706 | 0.000 | byte_clk | ||||
4.706 | 0.000 | tCL | FF | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
4.706 | 0.000 | tNET | FF | 1 | R3C4[2][A] | u_la0_top/rst_ao_s0/CLK |
4.904 | 0.198 | tC2Q | FR | 92 | R3C4[2][A] | u_la0_top/rst_ao_s0/Q |
6.681 | 1.777 | tNET | RR | 1 | R9C2[2][B] | u_la0_top/triger_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.000 | 0.000 | tNET | RR | 1 | R9C2[2][B] | u_la0_top/triger_s0/CLK |
-0.189 | -0.189 | tHld | 1 | R9C2[2][B] | u_la0_top/triger_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | -4.706 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.777, 90.000%; tC2Q: 0.198, 10.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path23
Path Summary:
Slack | 6.872 |
Data Arrival Time | 6.684 |
Data Required Time | -0.189 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_match_3/trig_dly_in_1_s0 |
Launch Clk | byte_clk:[F] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
4.706 | 4.706 | active clock edge time | ||||
4.706 | 0.000 | byte_clk | ||||
4.706 | 0.000 | tCL | FF | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
4.706 | 0.000 | tNET | FF | 1 | R3C4[2][A] | u_la0_top/rst_ao_s0/CLK |
4.904 | 0.198 | tC2Q | FR | 92 | R3C4[2][A] | u_la0_top/rst_ao_s0/Q |
6.684 | 1.780 | tNET | RR | 1 | R14C4[0][A] | u_la0_top/u_ao_match_3/trig_dly_in_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.000 | 0.000 | tNET | RR | 1 | R14C4[0][A] | u_la0_top/u_ao_match_3/trig_dly_in_1_s0/CLK |
-0.189 | -0.189 | tHld | 1 | R14C4[0][A] | u_la0_top/u_ao_match_3/trig_dly_in_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | -4.706 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.780, 90.013%; tC2Q: 0.198, 9.987% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path24
Path Summary:
Slack | 6.876 |
Data Arrival Time | 6.687 |
Data Required Time | -0.189 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_match_1/match_sep_s0 |
Launch Clk | byte_clk:[F] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
4.706 | 4.706 | active clock edge time | ||||
4.706 | 0.000 | byte_clk | ||||
4.706 | 0.000 | tCL | FF | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
4.706 | 0.000 | tNET | FF | 1 | R3C4[2][A] | u_la0_top/rst_ao_s0/CLK |
4.904 | 0.198 | tC2Q | FR | 92 | R3C4[2][A] | u_la0_top/rst_ao_s0/Q |
6.687 | 1.784 | tNET | RR | 1 | R8C7[1][B] | u_la0_top/u_ao_match_1/match_sep_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.000 | 0.000 | tNET | RR | 1 | R8C7[1][B] | u_la0_top/u_ao_match_1/match_sep_s0/CLK |
-0.189 | -0.189 | tHld | 1 | R8C7[1][B] | u_la0_top/u_ao_match_1/match_sep_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | -4.706 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.784, 90.032%; tC2Q: 0.198, 9.968% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Path25
Path Summary:
Slack | 6.876 |
Data Arrival Time | 6.687 |
Data Required Time | -0.189 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/capture_end_dly_s0 |
Launch Clk | byte_clk:[F] |
Latch Clk | byte_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
4.706 | 4.706 | active clock edge time | ||||
4.706 | 0.000 | byte_clk | ||||
4.706 | 0.000 | tCL | FF | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
4.706 | 0.000 | tNET | FF | 1 | R3C4[2][A] | u_la0_top/rst_ao_s0/CLK |
4.904 | 0.198 | tC2Q | FR | 92 | R3C4[2][A] | u_la0_top/rst_ao_s0/Q |
6.687 | 1.784 | tNET | RR | 1 | R8C7[1][A] | u_la0_top/capture_end_dly_s0/PRESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | byte_clk | ||||
0.000 | 0.000 | tCL | RR | 853 | - | u_dphy_tx_ip/mipi_dphy_inst/TX_CLK_O |
0.000 | 0.000 | tNET | RR | 1 | R8C7[1][A] | u_la0_top/capture_end_dly_s0/CLK |
-0.189 | -0.189 | tHld | 1 | R8C7[1][A] | u_la0_top/capture_end_dly_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | -4.706 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.784, 90.032%; tC2Q: 0.198, 9.968% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Minimum Pulse Width Report:
Report Command:report_min_pulse_width -nworst 10 -detail
MPW1
MPW Summary:
Slack: | 2.037 |
Actual Width: | 3.037 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | pixel_clk |
Objects: | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
3.529 | 0.000 | active clock edge time | ||
3.529 | 0.000 | pixel_clk | ||
3.529 | 0.000 | tCL | FF | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
4.385 | 0.856 | tNET | FF | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s/CLKA |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
7.059 | 0.000 | active clock edge time | ||
7.059 | 0.000 | pixel_clk | ||
7.059 | 0.000 | tCL | RR | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
7.423 | 0.364 | tNET | RR | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s/CLKA |
MPW2
MPW Summary:
Slack: | 2.039 |
Actual Width: | 3.039 |
Required Width: | 1.000 |
Type: | High Pulse Width |
Clock: | pixel_clk |
Objects: | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||
0.000 | 0.000 | pixel_clk | ||
0.000 | 0.000 | tCL | RR | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
0.860 | 0.860 | tNET | RR | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s/CLKA |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
3.529 | 0.000 | active clock edge time | ||
3.529 | 0.000 | pixel_clk | ||
3.529 | 0.000 | tCL | FF | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
3.899 | 0.370 | tNET | FF | u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s/CLKA |
MPW3
MPW Summary:
Slack: | 2.772 |
Actual Width: | 3.022 |
Required Width: | 0.250 |
Type: | Low Pulse Width |
Clock: | pixel_clk |
Objects: | running_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
3.529 | 0.000 | active clock edge time | ||
3.529 | 0.000 | pixel_clk | ||
3.529 | 0.000 | tCL | FF | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
4.443 | 0.913 | tNET | FF | running_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
7.059 | 0.000 | active clock edge time | ||
7.059 | 0.000 | pixel_clk | ||
7.059 | 0.000 | tCL | RR | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
7.464 | 0.406 | tNET | RR | running_s0/CLK |
MPW4
MPW Summary:
Slack: | 2.777 |
Actual Width: | 3.027 |
Required Width: | 0.250 |
Type: | Low Pulse Width |
Clock: | pixel_clk |
Objects: | u_test_gen/H_cnt_6_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
3.529 | 0.000 | active clock edge time | ||
3.529 | 0.000 | pixel_clk | ||
3.529 | 0.000 | tCL | FF | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
4.418 | 0.889 | tNET | FF | u_test_gen/H_cnt_6_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
7.059 | 0.000 | active clock edge time | ||
7.059 | 0.000 | pixel_clk | ||
7.059 | 0.000 | tCL | RR | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
7.445 | 0.386 | tNET | RR | u_test_gen/H_cnt_6_s0/CLK |
MPW5
MPW Summary:
Slack: | 2.777 |
Actual Width: | 3.027 |
Required Width: | 0.250 |
Type: | Low Pulse Width |
Clock: | pixel_clk |
Objects: | u_test_gen/O_hs_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
3.529 | 0.000 | active clock edge time | ||
3.529 | 0.000 | pixel_clk | ||
3.529 | 0.000 | tCL | FF | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
4.418 | 0.889 | tNET | FF | u_test_gen/O_hs_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
7.059 | 0.000 | active clock edge time | ||
7.059 | 0.000 | pixel_clk | ||
7.059 | 0.000 | tCL | RR | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
7.445 | 0.386 | tNET | RR | u_test_gen/O_hs_s0/CLK |
MPW6
MPW Summary:
Slack: | 2.777 |
Actual Width: | 3.027 |
Required Width: | 0.250 |
Type: | Low Pulse Width |
Clock: | pixel_clk |
Objects: | u_test_gen/H_cnt_5_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
3.529 | 0.000 | active clock edge time | ||
3.529 | 0.000 | pixel_clk | ||
3.529 | 0.000 | tCL | FF | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
4.418 | 0.889 | tNET | FF | u_test_gen/H_cnt_5_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
7.059 | 0.000 | active clock edge time | ||
7.059 | 0.000 | pixel_clk | ||
7.059 | 0.000 | tCL | RR | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
7.445 | 0.386 | tNET | RR | u_test_gen/H_cnt_5_s0/CLK |
MPW7
MPW Summary:
Slack: | 2.777 |
Actual Width: | 3.027 |
Required Width: | 0.250 |
Type: | Low Pulse Width |
Clock: | pixel_clk |
Objects: | u_p2b/u_p2b_0/mid_en_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
3.529 | 0.000 | active clock edge time | ||
3.529 | 0.000 | pixel_clk | ||
3.529 | 0.000 | tCL | FF | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
4.418 | 0.889 | tNET | FF | u_p2b/u_p2b_0/mid_en_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
7.059 | 0.000 | active clock edge time | ||
7.059 | 0.000 | pixel_clk | ||
7.059 | 0.000 | tCL | RR | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
7.445 | 0.386 | tNET | RR | u_p2b/u_p2b_0/mid_en_s0/CLK |
MPW8
MPW Summary:
Slack: | 2.777 |
Actual Width: | 3.027 |
Required Width: | 0.250 |
Type: | Low Pulse Width |
Clock: | pixel_clk |
Objects: | u_p2b/u_p2b_0/rCtrlSync_3_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
3.529 | 0.000 | active clock edge time | ||
3.529 | 0.000 | pixel_clk | ||
3.529 | 0.000 | tCL | FF | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
4.418 | 0.889 | tNET | FF | u_p2b/u_p2b_0/rCtrlSync_3_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
7.059 | 0.000 | active clock edge time | ||
7.059 | 0.000 | pixel_clk | ||
7.059 | 0.000 | tCL | RR | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
7.445 | 0.386 | tNET | RR | u_p2b/u_p2b_0/rCtrlSync_3_s0/CLK |
MPW9
MPW Summary:
Slack: | 2.777 |
Actual Width: | 3.027 |
Required Width: | 0.250 |
Type: | Low Pulse Width |
Clock: | pixel_clk |
Objects: | u_test_gen/H_cnt_4_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
3.529 | 0.000 | active clock edge time | ||
3.529 | 0.000 | pixel_clk | ||
3.529 | 0.000 | tCL | FF | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
4.418 | 0.889 | tNET | FF | u_test_gen/H_cnt_4_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
7.059 | 0.000 | active clock edge time | ||
7.059 | 0.000 | pixel_clk | ||
7.059 | 0.000 | tCL | RR | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
7.445 | 0.386 | tNET | RR | u_test_gen/H_cnt_4_s0/CLK |
MPW10
MPW Summary:
Slack: | 2.777 |
Actual Width: | 3.027 |
Required Width: | 0.250 |
Type: | Low Pulse Width |
Clock: | pixel_clk |
Objects: | u_p2b/u_p2b_0/shift_data_96_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
3.529 | 0.000 | active clock edge time | ||
3.529 | 0.000 | pixel_clk | ||
3.529 | 0.000 | tCL | FF | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
4.418 | 0.889 | tNET | FF | u_p2b/u_p2b_0/shift_data_96_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
7.059 | 0.000 | active clock edge time | ||
7.059 | 0.000 | pixel_clk | ||
7.059 | 0.000 | tCL | RR | u_dphy_tx_ip/PLLA_inst/CLKOUT4 |
7.445 | 0.386 | tNET | RR | u_p2b/u_p2b_0/shift_data_96_s0/CLK |
High Fanout Nets Report:
Report Command:report_high_fanout_nets -max_nets 10
FANOUT | NET NAME | WORST SLACK | MAX DELAY |
---|---|---|---|
853 | byte_clk | 0.270 | 0.913 |
278 | pixel_clk | 0.970 | 0.915 |
99 | n3118_11 | 2.390 | 2.545 |
99 | n3372_6 | 3.247 | 2.368 |
96 | n2862_6 | 4.384 | 2.180 |
94 | rRegData_125_8 | 3.247 | 2.073 |
94 | n3211_9 | 2.390 | 1.910 |
75 | rOffset[1] | 3.836 | 2.371 |
66 | rOffset[0] | 3.587 | 1.931 |
65 | mid_sel[0] | 3.897 | 1.348 |
Route Congestions Report:
Report Command:report_route_congestion -max_grids 10
GRID LOC | ROUTE CONGESTIONS |
---|---|
R23C28 | 54.17% |
R17C21 | 51.39% |
R26C30 | 51.39% |
R18C21 | 51.39% |
R24C29 | 50.00% |
R20C34 | 50.00% |
R22C27 | 50.00% |
R18C19 | 50.00% |
R18C20 | 50.00% |
R17C20 | 48.61% |
Timing Exceptions Report:
Setup Analysis Report
Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Hold Analysis Report
Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Recovery Analysis Report
Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Removal Analysis Report
Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Timing Constraints Report:
SDC Command Type | State | Detail Command |
---|---|---|
TC_CLOCK | Actived | create_clock -name clk_50 -period 20 -waveform {0 10} [get_ports {OSC_50M}] |
TC_CLOCK | Actived | create_clock -name byte_clk -period 9.412 -waveform {0 4.706} [get_nets {byte_clk}] |
TC_GENERATED_CLOCK | Actived | create_generated_clock -name pixel_clk -source [get_ports {OSC_50M}] -master_clock clk_50 -divide_by 6 -multiply_by 17 [get_nets {pixel_clk}] |
TC_CLOCK_GROUP | Actived | set_clock_groups -exclusive -group [get_clocks {pixel_clk}] -group [get_clocks {byte_clk}] |
TC_REPORT_TIMING | Actived | report_timing -setup -from_clock [get_clocks {pixel_clk}] -max_paths 20 -max_common_paths 1 |
TC_REPORT_TIMING | Actived | report_timing -setup -from_clock [get_clocks {byte_clk}] -max_paths 20 -max_common_paths 1 |
TC_REPORT_TIMING | Actived | report_timing -hold -from_clock [get_clocks {pixel_clk}] -max_paths 20 -max_common_paths 1 |
TC_REPORT_TIMING | Actived | report_timing -hold -from_clock [get_clocks {byte_clk}] -max_paths 20 -max_common_paths 1 |