Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | D:\Programs\Gowin\Gowin_V1.9.9.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v D:\Programs\Gowin\Gowin_V1.9.9.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v D:\Programs\Gowin\Gowin_V1.9.9.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v D:\Programs\Gowin\Gowin_V1.9.9.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v D:\Programs\Gowin\Gowin_V1.9.9.01_x64\IDE\data\ipcores\GAO\GW_CON\gw_con_top.v D:\Programs\Gowin\Gowin_V1.9.9.01_x64\IDE\data\ipcores\gw_jtag.v F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\DSI_Test_Pattern_5a25_soft\fpga_proj\impl\gao\gw_gao_top.v |
GowinSynthesis Constraints File | --- |
Tool Version | V1.9.9.01 (64-bit) |
Part Number | GW5A-LV25UG324ES |
Device | GW5A-25 |
Device Version | A |
Created Time | Wed Mar 6 17:43:53 2024 |
Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | gw_gao |
Synthesis Process | Running parser: CPU time = 0h 0m 0.281s, Elapsed time = 0h 0m 0.315s, Peak memory usage = 112.195MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 112.195MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.022s, Peak memory usage = 112.195MB Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 112.195MB Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.023s, Peak memory usage = 112.195MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 112.195MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 112.195MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 112.195MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 112.195MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.019s, Peak memory usage = 112.195MB Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 112.195MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 112.195MB Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 137.500MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.035s, Peak memory usage = 137.500MB Generate output files: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.065s, Peak memory usage = 137.500MB |
Total Time and Memory Usage | CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 137.500MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 44 |
I/O Buf | 44 |
    IBUF | 43 |
    OBUF | 1 |
Register | 394 |
    DFFRE | 1 |
    DFFPE | 36 |
    DFFCE | 357 |
LUT | 430 |
    LUT2 | 55 |
    LUT3 | 129 |
    LUT4 | 246 |
MUX | 1 |
    MUX16 | 1 |
ALU | 13 |
    ALU | 13 |
INV | 4 |
    INV | 4 |
BSRAM | 3 |
    SDPB | 3 |
Black Box | 1 |
    GW_JTAG | 1 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 455(442 LUT, 13 ALU) / 23040 | 2% |
Register | 394 / 23685 | 2% |
  --Register as Latch | 0 / 23685 | 0% |
  --Register as FF | 394 / 23685 | 2% |
BSRAM | 3 / 56 | 6% |
Timing
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|
byte_clk | Base | 10.000 | 100.0 | 0.000 | 5.000 | byte_clk_ibuf/I | ||
u_icon_top/n19_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 | u_icon_top/n19_s2/O | ||
u_la0_top/n15_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 | u_la0_top/n15_s2/O |
Max Frequency Summary:
No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | byte_clk | 100.000(MHz) | 190.386(MHz) | 6 | TOP |
2 | u_icon_top/n19_6 | 100.000(MHz) | 1217.656(MHz) | 1 | TOP |
3 | u_la0_top/n15_6 | 100.000(MHz) | 1217.656(MHz) | 1 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | 4.747 |
Data Arrival Time | 6.246 |
Data Required Time | 10.994 |
From | u_la0_top/capture_window_sel_0_s3 |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_9_s0 |
Launch Clk | byte_clk[R] |
Latch Clk | byte_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | byte_clk | |||
0.000 | 0.000 | tCL | RR | 1 | byte_clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 141 | byte_clk_ibuf/O |
1.058 | 0.375 | tNET | RR | 1 | u_la0_top/capture_window_sel_0_s3/CLK |
1.440 | 0.382 | tC2Q | RR | 14 | u_la0_top/capture_window_sel_0_s3/Q |
1.815 | 0.375 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s16/I1 |
2.331 | 0.516 | tINS | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s16/F |
2.706 | 0.375 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s15/I0 |
3.233 | 0.526 | tINS | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s15/F |
3.608 | 0.375 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s14/I0 |
4.134 | 0.526 | tINS | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s14/F |
4.509 | 0.375 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s12/I0 |
5.035 | 0.526 | tINS | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s12/F |
5.410 | 0.375 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s10/I2 |
5.871 | 0.461 | tINS | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s10/F |
6.246 | 0.375 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_9_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | byte_clk | |||
10.000 | 0.000 | tCL | RR | 1 | byte_clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 141 | byte_clk_ibuf/O |
11.057 | 0.375 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_9_s0/CLK |
10.994 | -0.064 | tSu | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_9_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 6 |
Arrival Clock Path Delay: | cell: 0.683, 64.539%; route: 0.375, 35.461% |
Arrival Data Path Delay: | cell: 2.556, 49.265%; route: 2.250, 43.363%; tC2Q: 0.382, 7.372% |
Required Clock Path Delay: | cell: 0.683, 64.539%; route: 0.375, 35.461% |
Path 2
Path Summary:Slack | 5.336 |
Data Arrival Time | 5.410 |
Data Required Time | 10.746 |
From | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1 |
To | u_la0_top/u_ao_mem_ctrl/capture_loop_s1 |
Launch Clk | byte_clk[R] |
Latch Clk | byte_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | byte_clk | |||
0.000 | 0.000 | tCL | RR | 1 | byte_clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 141 | byte_clk_ibuf/O |
1.058 | 0.375 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK |
1.440 | 0.382 | tC2Q | RR | 6 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/Q |
1.815 | 0.375 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/n400_s9/I0 |
2.341 | 0.526 | tINS | RR | 1 | u_la0_top/u_ao_mem_ctrl/n400_s9/F |
2.716 | 0.375 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/n400_s6/I0 |
3.242 | 0.526 | tINS | RR | 2 | u_la0_top/u_ao_mem_ctrl/n400_s6/F |
3.617 | 0.375 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/n400_s4/I1 |
4.134 | 0.516 | tINS | RR | 10 | u_la0_top/u_ao_mem_ctrl/n400_s4/F |
4.509 | 0.375 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_loop_s4/I0 |
5.035 | 0.526 | tINS | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_loop_s4/F |
5.410 | 0.375 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | byte_clk | |||
10.000 | 0.000 | tCL | RR | 1 | byte_clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 141 | byte_clk_ibuf/O |
11.057 | 0.375 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK |
10.746 | -0.311 | tSu | 1 | u_la0_top/u_ao_mem_ctrl/capture_loop_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.683, 64.539%; route: 0.375, 35.461% |
Arrival Data Path Delay: | cell: 2.095, 48.133%; route: 1.875, 43.079%; tC2Q: 0.382, 8.788% |
Required Clock Path Delay: | cell: 0.683, 64.539%; route: 0.375, 35.461% |
Path 3
Path Summary:Slack | 5.466 |
Data Arrival Time | 5.280 |
Data Required Time | 10.746 |
From | u_la0_top/u_ao_mem_ctrl/capture_length_4_s1 |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1 |
Launch Clk | byte_clk[R] |
Latch Clk | byte_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | byte_clk | |||
0.000 | 0.000 | tCL | RR | 1 | byte_clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 141 | byte_clk_ibuf/O |
1.058 | 0.375 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLK |
1.440 | 0.382 | tC2Q | RR | 4 | u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/Q |
1.815 | 0.375 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/n306_s2/I0 |
2.341 | 0.526 | tINS | RR | 3 | u_la0_top/u_ao_mem_ctrl/n306_s2/F |
2.716 | 0.375 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s4/I2 |
3.178 | 0.461 | tINS | RR | 2 | u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s4/F |
3.553 | 0.375 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s4/I1 |
4.069 | 0.516 | tINS | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s4/F |
4.444 | 0.375 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s3/I2 |
4.905 | 0.461 | tINS | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s3/F |
5.280 | 0.375 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | byte_clk | |||
10.000 | 0.000 | tCL | RR | 1 | byte_clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 141 | byte_clk_ibuf/O |
11.057 | 0.375 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK |
10.746 | -0.311 | tSu | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.683, 64.539%; route: 0.375, 35.461% |
Arrival Data Path Delay: | cell: 1.965, 46.536%; route: 1.875, 44.405%; tC2Q: 0.382, 9.059% |
Required Clock Path Delay: | cell: 0.683, 64.539%; route: 0.375, 35.461% |
Path 4
Path Summary:Slack | 5.604 |
Data Arrival Time | 5.390 |
Data Required Time | 10.994 |
From | u_la0_top/capture_window_sel_3_s1 |
To | u_la0_top/capture_window_sel_8_s1 |
Launch Clk | byte_clk[R] |
Latch Clk | byte_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | byte_clk | |||
0.000 | 0.000 | tCL | RR | 1 | byte_clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 141 | byte_clk_ibuf/O |
1.058 | 0.375 | tNET | RR | 1 | u_la0_top/capture_window_sel_3_s1/CLK |
1.440 | 0.382 | tC2Q | RR | 8 | u_la0_top/capture_window_sel_3_s1/Q |
1.815 | 0.375 | tNET | RR | 1 | u_la0_top/n2056_s3/I0 |
2.341 | 0.526 | tINS | RR | 3 | u_la0_top/n2056_s3/F |
2.716 | 0.375 | tNET | RR | 1 | u_la0_top/n2055_s2/I1 |
3.233 | 0.516 | tINS | RR | 3 | u_la0_top/n2055_s2/F |
3.608 | 0.375 | tNET | RR | 1 | u_la0_top/n2052_s3/I1 |
4.124 | 0.516 | tINS | RR | 2 | u_la0_top/n2052_s3/F |
4.499 | 0.375 | tNET | RR | 1 | u_la0_top/n2052_s1/I1 |
5.015 | 0.516 | tINS | RR | 1 | u_la0_top/n2052_s1/F |
5.390 | 0.375 | tNET | RR | 1 | u_la0_top/capture_window_sel_8_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | byte_clk | |||
10.000 | 0.000 | tCL | RR | 1 | byte_clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 141 | byte_clk_ibuf/O |
11.057 | 0.375 | tNET | RR | 1 | u_la0_top/capture_window_sel_8_s1/CLK |
10.994 | -0.064 | tSu | 1 | u_la0_top/capture_window_sel_8_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.683, 64.539%; route: 0.375, 35.461% |
Arrival Data Path Delay: | cell: 2.075, 47.893%; route: 1.875, 43.278%; tC2Q: 0.382, 8.829% |
Required Clock Path Delay: | cell: 0.683, 64.539%; route: 0.375, 35.461% |
Path 5
Path Summary:Slack | 5.604 |
Data Arrival Time | 5.390 |
Data Required Time | 10.994 |
From | u_la0_top/capture_window_sel_3_s1 |
To | u_la0_top/capture_window_sel_9_s1 |
Launch Clk | byte_clk[R] |
Latch Clk | byte_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | byte_clk | |||
0.000 | 0.000 | tCL | RR | 1 | byte_clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 141 | byte_clk_ibuf/O |
1.058 | 0.375 | tNET | RR | 1 | u_la0_top/capture_window_sel_3_s1/CLK |
1.440 | 0.382 | tC2Q | RR | 8 | u_la0_top/capture_window_sel_3_s1/Q |
1.815 | 0.375 | tNET | RR | 1 | u_la0_top/n2056_s3/I0 |
2.341 | 0.526 | tINS | RR | 3 | u_la0_top/n2056_s3/F |
2.716 | 0.375 | tNET | RR | 1 | u_la0_top/n2055_s2/I1 |
3.233 | 0.516 | tINS | RR | 3 | u_la0_top/n2055_s2/F |
3.608 | 0.375 | tNET | RR | 1 | u_la0_top/n2052_s3/I1 |
4.124 | 0.516 | tINS | RR | 2 | u_la0_top/n2052_s3/F |
4.499 | 0.375 | tNET | RR | 1 | u_la0_top/n2051_s1/I1 |
5.015 | 0.516 | tINS | RR | 1 | u_la0_top/n2051_s1/F |
5.390 | 0.375 | tNET | RR | 1 | u_la0_top/capture_window_sel_9_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | byte_clk | |||
10.000 | 0.000 | tCL | RR | 1 | byte_clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 141 | byte_clk_ibuf/O |
11.057 | 0.375 | tNET | RR | 1 | u_la0_top/capture_window_sel_9_s1/CLK |
10.994 | -0.064 | tSu | 1 | u_la0_top/capture_window_sel_9_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.683, 64.539%; route: 0.375, 35.461% |
Arrival Data Path Delay: | cell: 2.075, 47.893%; route: 1.875, 43.278%; tC2Q: 0.382, 8.829% |
Required Clock Path Delay: | cell: 0.683, 64.539%; route: 0.375, 35.461% |