Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\DSI_Test_Pattern_5a25_soft\fpga_proj\src\gowin_pll\gowin_pll.v F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\DSI_Test_Pattern_5a25_soft\fpga_proj\src\mipi_dsi_tx\mipi_dsi_tx.v F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\DSI_Test_Pattern_5a25_soft\fpga_proj\src\mipi_tx\mipi_tx.v F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\DSI_Test_Pattern_5a25_soft\fpga_proj\src\pixel_to_byte\pixel_to_byte.v F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\DSI_Test_Pattern_5a25_soft\fpga_proj\src\testpattern.v F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\DSI_Test_Pattern_5a25_soft\fpga_proj\src\top.v |
GowinSynthesis Constraints File | --- |
Tool Version | V1.9.9.01 (64-bit) |
Part Number | GW5A-LV25UG324ES |
Device | GW5A-25 |
Device Version | A |
Created Time | Wed Mar 6 17:37:07 2024 |
Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | DsiTest_Top |
Synthesis Process | Running parser: CPU time = 0h 0m 0.421s, Elapsed time = 0h 0m 0.404s, Peak memory usage = 283.594MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.028s, Peak memory usage = 283.594MB Optimizing Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.027s, Peak memory usage = 283.594MB Optimizing Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.048s, Peak memory usage = 283.594MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.021s, Peak memory usage = 283.594MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 283.594MB Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 283.594MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 283.594MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.041s, Peak memory usage = 283.594MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 283.594MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 283.594MB Tech-Mapping Phase 3: CPU time = 0h 0m 0.546s, Elapsed time = 0h 0m 0.601s, Peak memory usage = 299.707MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.055s, Peak memory usage = 299.707MB Generate output files: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.144s, Peak memory usage = 299.707MB |
Total Time and Memory Usage | CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 299.707MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 15 |
I/O Buf | 10 |
    IBUF | 2 |
    OBUF | 3 |
    MIPI_OBUF_A | 5 |
Register | 878 |
    DFFSE | 24 |
    DFFRE | 316 |
    DFFPE | 30 |
    DFFCE | 508 |
LUT | 1610 |
    LUT2 | 140 |
    LUT3 | 631 |
    LUT4 | 839 |
ALU | 58 |
    ALU | 58 |
INV | 20 |
    INV | 20 |
IOLOGIC | 5 |
    OSER8 | 5 |
BSRAM | 4 |
    SDPB | 1 |
    SDPX9B | 3 |
CLOCK | 1 |
    PLLA | 1 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 1688(1630 LUT, 58 ALU) / 23040 | 8% |
Register | 878 / 23685 | 4% |
  --Register as Latch | 0 / 23685 | 0% |
  --Register as FF | 878 / 23685 | 4% |
BSRAM | 4 / 56 | 8% |
Timing
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|
OSC_50M | Base | 20.000 | 50.0 | 0.000 | 10.000 | OSC_50M_ibuf/I | ||
u_pll/PLLA_inst/CLKOUT0.default_gen_clk | Generated | 2.353 | 425.0 | 0.000 | 1.176 | OSC_50M_ibuf/I | OSC_50M | u_pll/PLLA_inst/CLKOUT0 |
u_pll/PLLA_inst/CLKOUT1.default_gen_clk | Generated | 2.353 | 425.0 | 0.000 | 1.176 | OSC_50M_ibuf/I | OSC_50M | u_pll/PLLA_inst/CLKOUT1 |
u_pll/PLLA_inst/CLKOUT2.default_gen_clk | Generated | 9.412 | 106.2 | 0.000 | 4.706 | OSC_50M_ibuf/I | OSC_50M | u_pll/PLLA_inst/CLKOUT2 |
u_pll/PLLA_inst/CLKOUT3.default_gen_clk | Generated | 7.059 | 141.7 | 0.000 | 3.529 | OSC_50M_ibuf/I | OSC_50M | u_pll/PLLA_inst/CLKOUT3 |
Max Frequency Summary:
No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | u_pll/PLLA_inst/CLKOUT2.default_gen_clk | 106.250(MHz) | 145.852(MHz) | 8 | TOP |
2 | u_pll/PLLA_inst/CLKOUT3.default_gen_clk | 141.667(MHz) | 190.840(MHz) | 7 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | 0.595 |
Data Arrival Time | 10.077 |
Data Required Time | 10.672 |
From | u_p2b/u_p2b/rCtrlSync_3_s0 |
To | u_p2b/u_p2b/GEN_FOR_I[3].u_pulse_dly/rCnt_0_s3 |
Launch Clk | u_pll/PLLA_inst/CLKOUT3.default_gen_clk[R] |
Latch Clk | u_pll/PLLA_inst/CLKOUT2.default_gen_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
7.059 | 0.000 | u_pll/PLLA_inst/CLKOUT3.default_gen_clk | |||
8.043 | 0.984 | tCL | RR | 278 | u_pll/PLLA_inst/CLKOUT3 |
8.418 | 0.375 | tNET | RR | 1 | u_p2b/u_p2b/rCtrlSync_3_s0/CLK |
8.800 | 0.382 | tC2Q | RR | 3 | u_p2b/u_p2b/rCtrlSync_3_s0/Q |
9.175 | 0.375 | tNET | RR | 1 | u_p2b/u_p2b/GEN_FOR_I[3].u_pulse_dly/n32_s6/I0 |
9.702 | 0.526 | tINS | RR | 1 | u_p2b/u_p2b/GEN_FOR_I[3].u_pulse_dly/n32_s6/F |
10.077 | 0.375 | tNET | RR | 1 | u_p2b/u_p2b/GEN_FOR_I[3].u_pulse_dly/rCnt_0_s3/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
9.412 | 0.000 | u_pll/PLLA_inst/CLKOUT2.default_gen_clk | |||
10.396 | 0.984 | tCL | RR | 613 | u_pll/PLLA_inst/CLKOUT2 |
10.771 | 0.375 | tNET | RR | 1 | u_p2b/u_p2b/GEN_FOR_I[3].u_pulse_dly/rCnt_0_s3/CLK |
10.736 | -0.035 | tUnc | u_p2b/u_p2b/GEN_FOR_I[3].u_pulse_dly/rCnt_0_s3 | ||
10.672 | -0.064 | tSu | 1 | u_p2b/u_p2b/GEN_FOR_I[3].u_pulse_dly/rCnt_0_s3 |
Clock Skew: | 0.000 |
Setup Relationship: | 2.353 |
Logic Level: | 2 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Arrival Data Path Delay: | cell: 0.526, 31.726%; route: 0.750, 45.214%; tC2Q: 0.382, 23.060% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 2
Path Summary:Slack | 0.595 |
Data Arrival Time | 10.077 |
Data Required Time | 10.672 |
From | u_p2b/u_p2b/rCtrlSync_2_s0 |
To | u_p2b/u_p2b/GEN_FOR_I[1].u_pulse_dly/rCnt_0_s3 |
Launch Clk | u_pll/PLLA_inst/CLKOUT3.default_gen_clk[R] |
Latch Clk | u_pll/PLLA_inst/CLKOUT2.default_gen_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
7.059 | 0.000 | u_pll/PLLA_inst/CLKOUT3.default_gen_clk | |||
8.043 | 0.984 | tCL | RR | 278 | u_pll/PLLA_inst/CLKOUT3 |
8.418 | 0.375 | tNET | RR | 1 | u_p2b/u_p2b/rCtrlSync_2_s0/CLK |
8.800 | 0.382 | tC2Q | RR | 3 | u_p2b/u_p2b/rCtrlSync_2_s0/Q |
9.175 | 0.375 | tNET | RR | 1 | u_p2b/u_p2b/GEN_FOR_I[1].u_pulse_dly/n32_s6/I0 |
9.702 | 0.526 | tINS | RR | 1 | u_p2b/u_p2b/GEN_FOR_I[1].u_pulse_dly/n32_s6/F |
10.077 | 0.375 | tNET | RR | 1 | u_p2b/u_p2b/GEN_FOR_I[1].u_pulse_dly/rCnt_0_s3/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
9.412 | 0.000 | u_pll/PLLA_inst/CLKOUT2.default_gen_clk | |||
10.396 | 0.984 | tCL | RR | 613 | u_pll/PLLA_inst/CLKOUT2 |
10.771 | 0.375 | tNET | RR | 1 | u_p2b/u_p2b/GEN_FOR_I[1].u_pulse_dly/rCnt_0_s3/CLK |
10.736 | -0.035 | tUnc | u_p2b/u_p2b/GEN_FOR_I[1].u_pulse_dly/rCnt_0_s3 | ||
10.672 | -0.064 | tSu | 1 | u_p2b/u_p2b/GEN_FOR_I[1].u_pulse_dly/rCnt_0_s3 |
Clock Skew: | 0.000 |
Setup Relationship: | 2.353 |
Logic Level: | 2 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Arrival Data Path Delay: | cell: 0.526, 31.726%; route: 0.750, 45.214%; tC2Q: 0.382, 23.060% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 3
Path Summary:Slack | 0.605 |
Data Arrival Time | 10.067 |
Data Required Time | 10.672 |
From | u_p2b/u_p2b/rCtrlSync_3_s0 |
To | u_p2b/u_p2b/GEN_FOR_I[2].u_pulse_dly/rCnt_0_s3 |
Launch Clk | u_pll/PLLA_inst/CLKOUT3.default_gen_clk[R] |
Latch Clk | u_pll/PLLA_inst/CLKOUT2.default_gen_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
7.059 | 0.000 | u_pll/PLLA_inst/CLKOUT3.default_gen_clk | |||
8.043 | 0.984 | tCL | RR | 278 | u_pll/PLLA_inst/CLKOUT3 |
8.418 | 0.375 | tNET | RR | 1 | u_p2b/u_p2b/rCtrlSync_3_s0/CLK |
8.800 | 0.382 | tC2Q | RR | 3 | u_p2b/u_p2b/rCtrlSync_3_s0/Q |
9.175 | 0.375 | tNET | RR | 1 | u_p2b/u_p2b/GEN_FOR_I[2].u_pulse_dly/n32_s6/I1 |
9.692 | 0.516 | tINS | RR | 1 | u_p2b/u_p2b/GEN_FOR_I[2].u_pulse_dly/n32_s6/F |
10.067 | 0.375 | tNET | RR | 1 | u_p2b/u_p2b/GEN_FOR_I[2].u_pulse_dly/rCnt_0_s3/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
9.412 | 0.000 | u_pll/PLLA_inst/CLKOUT2.default_gen_clk | |||
10.396 | 0.984 | tCL | RR | 613 | u_pll/PLLA_inst/CLKOUT2 |
10.771 | 0.375 | tNET | RR | 1 | u_p2b/u_p2b/GEN_FOR_I[2].u_pulse_dly/rCnt_0_s3/CLK |
10.736 | -0.035 | tUnc | u_p2b/u_p2b/GEN_FOR_I[2].u_pulse_dly/rCnt_0_s3 | ||
10.672 | -0.064 | tSu | 1 | u_p2b/u_p2b/GEN_FOR_I[2].u_pulse_dly/rCnt_0_s3 |
Clock Skew: | 0.000 |
Setup Relationship: | 2.353 |
Logic Level: | 2 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Arrival Data Path Delay: | cell: 0.516, 31.312%; route: 0.750, 45.489%; tC2Q: 0.382, 23.199% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 4
Path Summary:Slack | 0.605 |
Data Arrival Time | 10.067 |
Data Required Time | 10.672 |
From | u_p2b/u_p2b/rCtrlSync_2_s0 |
To | u_p2b/u_p2b/GEN_FOR_I[0].u_pulse_dly/rCnt_0_s3 |
Launch Clk | u_pll/PLLA_inst/CLKOUT3.default_gen_clk[R] |
Latch Clk | u_pll/PLLA_inst/CLKOUT2.default_gen_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
7.059 | 0.000 | u_pll/PLLA_inst/CLKOUT3.default_gen_clk | |||
8.043 | 0.984 | tCL | RR | 278 | u_pll/PLLA_inst/CLKOUT3 |
8.418 | 0.375 | tNET | RR | 1 | u_p2b/u_p2b/rCtrlSync_2_s0/CLK |
8.800 | 0.382 | tC2Q | RR | 3 | u_p2b/u_p2b/rCtrlSync_2_s0/Q |
9.175 | 0.375 | tNET | RR | 1 | u_p2b/u_p2b/GEN_FOR_I[0].u_pulse_dly/n32_s6/I1 |
9.692 | 0.516 | tINS | RR | 1 | u_p2b/u_p2b/GEN_FOR_I[0].u_pulse_dly/n32_s6/F |
10.067 | 0.375 | tNET | RR | 1 | u_p2b/u_p2b/GEN_FOR_I[0].u_pulse_dly/rCnt_0_s3/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
9.412 | 0.000 | u_pll/PLLA_inst/CLKOUT2.default_gen_clk | |||
10.396 | 0.984 | tCL | RR | 613 | u_pll/PLLA_inst/CLKOUT2 |
10.771 | 0.375 | tNET | RR | 1 | u_p2b/u_p2b/GEN_FOR_I[0].u_pulse_dly/rCnt_0_s3/CLK |
10.736 | -0.035 | tUnc | u_p2b/u_p2b/GEN_FOR_I[0].u_pulse_dly/rCnt_0_s3 | ||
10.672 | -0.064 | tSu | 1 | u_p2b/u_p2b/GEN_FOR_I[0].u_pulse_dly/rCnt_0_s3 |
Clock Skew: | 0.000 |
Setup Relationship: | 2.353 |
Logic Level: | 2 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Arrival Data Path Delay: | cell: 0.516, 31.312%; route: 0.750, 45.489%; tC2Q: 0.382, 23.199% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 5
Path Summary:Slack | 1.497 |
Data Arrival Time | 20.940 |
Data Required Time | 22.437 |
From | u_p2b/u_p2b/u_mid_buf/rRPtrGray_0_s1 |
To | u_p2b/u_p2b/u_mid_buf/rRPtrWsync_0_s0 |
Launch Clk | u_pll/PLLA_inst/CLKOUT2.default_gen_clk[R] |
Latch Clk | u_pll/PLLA_inst/CLKOUT3.default_gen_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
18.824 | 0.000 | u_pll/PLLA_inst/CLKOUT2.default_gen_clk | |||
19.808 | 0.984 | tCL | RR | 613 | u_pll/PLLA_inst/CLKOUT2 |
20.183 | 0.375 | tNET | RR | 1 | u_p2b/u_p2b/u_mid_buf/rRPtrGray_0_s1/CLK |
20.565 | 0.382 | tC2Q | RR | 2 | u_p2b/u_p2b/u_mid_buf/rRPtrGray_0_s1/Q |
20.940 | 0.375 | tNET | RR | 1 | u_p2b/u_p2b/u_mid_buf/rRPtrWsync_0_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
21.176 | 0.000 | u_pll/PLLA_inst/CLKOUT3.default_gen_clk | |||
22.160 | 0.984 | tCL | RR | 278 | u_pll/PLLA_inst/CLKOUT3 |
22.535 | 0.375 | tNET | RR | 1 | u_p2b/u_p2b/u_mid_buf/rRPtrWsync_0_s0/CLK |
22.500 | -0.035 | tUnc | u_p2b/u_p2b/u_mid_buf/rRPtrWsync_0_s0 | ||
22.437 | -0.064 | tSu | 1 | u_p2b/u_p2b/u_mid_buf/rRPtrWsync_0_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 2.353 |
Logic Level: | 1 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.375, 49.505%; tC2Q: 0.382, 50.495% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |