Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Programs\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\MIPI_PIXEL_TO_BYTE\data\pixel_to_byte.v
D:\Programs\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\MIPI_PIXEL_TO_BYTE\data\pixel_to_byte_wrap.v
GowinSynthesis Constraints File ---
Tool Version V1.9.9.01 (64-bit)
Part Number GW5A-LV25UG324ES
Device GW5A-25
Device Version A
Created Time Wed Mar 6 17:19:11 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module Pixel_to_Byte_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.228s, Peak memory usage = 111.500MB
Running netlist conversion:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 111.500MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 111.500MB
    Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 111.500MB
    Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 111.500MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 111.500MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 111.500MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 111.500MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 111.500MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 111.500MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 111.500MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 111.500MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.406s, Elapsed time = 0h 0m 0.43s, Peak memory usage = 135.184MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.034s, Peak memory usage = 135.184MB
Generate output files:
    CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.043s, Peak memory usage = 135.184MB
Total Time and Memory Usage CPU time = 0h 0m 0.746s, Elapsed time = 0h 0m 0.793s, Peak memory usage = 135.184MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 67
I/O Buf 67
    IBUF 30
    OBUF 37
Register 192
    DFFSE 2
    DFFRE 36
    DFFPE 4
    DFFCE 150
LUT 139
    LUT2 18
    LUT3 56
    LUT4 65
ALU 20
    ALU 20
INV 5
    INV 5
BSRAM 1
    SDPB 1

Resource Utilization Summary

Resource Usage Utilization
Logic 164(144 LUT, 20 ALU) / 23040 <1%
Register 192 / 23685 <1%
  --Register as Latch 0 / 23685 0%
  --Register as FF 192 / 23685 <1%
BSRAM 1 / 56 2%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
I_PIXEL_CLK Base 10.000 100.0 0.000 5.000 I_PIXEL_CLK_ibuf/I
I_BYTE_CLK Base 10.000 100.0 0.000 5.000 I_BYTE_CLK_ibuf/I

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 I_PIXEL_CLK 100.000(MHz) 190.840(MHz) 7 TOP
2 I_BYTE_CLK 100.000(MHz) 227.467(MHz) 5 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 4.760
Data Arrival Time 6.234
Data Required Time 10.994
From u_p2b/u_mid_buf/rRPtrWsync_3_s0
To u_p2b/u_mid_buf/rFull_s0
Launch Clk I_PIXEL_CLK[R]
Latch Clk I_PIXEL_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_PIXEL_CLK
0.000 0.000 tCL RR 1 I_PIXEL_CLK_ibuf/I
0.683 0.683 tINS RR 113 I_PIXEL_CLK_ibuf/O
1.058 0.375 tNET RR 1 u_p2b/u_mid_buf/rRPtrWsync_3_s0/CLK
1.440 0.382 tC2Q RR 1 u_p2b/u_mid_buf/rRPtrWsync_3_s0/Q
1.815 0.375 tNET RR 1 u_p2b/u_mid_buf/wRPtrBinX_3_s0/I0
2.341 0.526 tINS RR 5 u_p2b/u_mid_buf/wRPtrBinX_3_s0/F
2.716 0.375 tNET RR 1 u_p2b/u_mid_buf/wRPtrBinX_2_s0/I1
3.233 0.516 tINS RR 2 u_p2b/u_mid_buf/wRPtrBinX_2_s0/F
3.608 0.375 tNET RR 2 u_p2b/u_mid_buf/n385_s0/I1
4.170 0.562 tINS RF 1 u_p2b/u_mid_buf/n385_s0/COUT
4.170 0.000 tNET FF 2 u_p2b/u_mid_buf/n386_s0/CIN
4.220 0.050 tINS FR 1 u_p2b/u_mid_buf/n386_s0/COUT
4.220 0.000 tNET RR 2 u_p2b/u_mid_buf/n387_s0/CIN
4.270 0.050 tINS RR 1 u_p2b/u_mid_buf/n387_s0/COUT
4.270 0.000 tNET RR 2 u_p2b/u_mid_buf/n388_s0/CIN
4.320 0.050 tINS RR 1 u_p2b/u_mid_buf/n388_s0/COUT
4.695 0.375 tNET RR 1 u_p2b/u_mid_buf/n402_s4/I0
5.221 0.526 tINS RR 1 u_p2b/u_mid_buf/n402_s4/F
5.596 0.375 tNET RR 1 u_p2b/u_mid_buf/n402_s0/I3
5.859 0.262 tINS RR 1 u_p2b/u_mid_buf/n402_s0/F
6.234 0.375 tNET RR 1 u_p2b/u_mid_buf/rFull_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_PIXEL_CLK
10.000 0.000 tCL RR 1 I_PIXEL_CLK_ibuf/I
10.682 0.683 tINS RR 113 I_PIXEL_CLK_ibuf/O
11.057 0.375 tNET RR 1 u_p2b/u_mid_buf/rFull_s0/CLK
10.994 -0.064 tSu 1 u_p2b/u_mid_buf/rFull_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.683, 64.539%; route: 0.375, 35.461%
Arrival Data Path Delay: cell: 2.544, 49.142%; route: 2.250, 43.468%; tC2Q: 0.382, 7.390%
Required Clock Path Delay: cell: 0.683, 64.539%; route: 0.375, 35.461%

Path 2

Path Summary:
Slack 5.604
Data Arrival Time 5.390
Data Required Time 10.994
From u_p2b/u_mid_buf/rRPtrBin_0_s0
To u_p2b/u_mid_buf/rEmpty_s0
Launch Clk I_BYTE_CLK[R]
Latch Clk I_BYTE_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_BYTE_CLK
0.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
0.683 0.683 tINS RR 81 I_BYTE_CLK_ibuf/O
1.058 0.375 tNET RR 1 u_p2b/u_mid_buf/rRPtrBin_0_s0/CLK
1.440 0.382 tC2Q RR 13 u_p2b/u_mid_buf/rRPtrBin_0_s0/Q
1.815 0.375 tNET RR 1 u_p2b/u_mid_buf/wRPtrBinNext_4_s4/I0
2.341 0.526 tINS RR 8 u_p2b/u_mid_buf/wRPtrBinNext_4_s4/F
2.716 0.375 tNET RR 1 u_p2b/u_mid_buf/wRPtrBinNext_5_s4/I1
3.233 0.516 tINS RR 1 u_p2b/u_mid_buf/wRPtrBinNext_5_s4/F
3.608 0.375 tNET RR 1 u_p2b/u_mid_buf/n370_s2/I1
4.124 0.516 tINS RR 1 u_p2b/u_mid_buf/n370_s2/F
4.499 0.375 tNET RR 1 u_p2b/u_mid_buf/n370_s0/I1
5.015 0.516 tINS RR 1 u_p2b/u_mid_buf/n370_s0/F
5.390 0.375 tNET RR 1 u_p2b/u_mid_buf/rEmpty_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_BYTE_CLK
10.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
10.682 0.683 tINS RR 81 I_BYTE_CLK_ibuf/O
11.057 0.375 tNET RR 1 u_p2b/u_mid_buf/rEmpty_s0/CLK
10.994 -0.064 tSu 1 u_p2b/u_mid_buf/rEmpty_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.683, 64.539%; route: 0.375, 35.461%
Arrival Data Path Delay: cell: 2.075, 47.893%; route: 1.875, 43.278%; tC2Q: 0.382, 8.829%
Required Clock Path Delay: cell: 0.683, 64.539%; route: 0.375, 35.461%

Path 3

Path Summary:
Slack 6.061
Data Arrival Time 4.932
Data Required Time 10.994
From u_p2b/u_mid_buf/rWPtrRsync_3_s0
To u_p2b/u_mid_buf/rRdDiff_6_s0
Launch Clk I_BYTE_CLK[R]
Latch Clk I_BYTE_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_BYTE_CLK
0.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
0.683 0.683 tINS RR 81 I_BYTE_CLK_ibuf/O
1.058 0.375 tNET RR 1 u_p2b/u_mid_buf/rWPtrRsync_3_s0/CLK
1.440 0.382 tC2Q RR 1 u_p2b/u_mid_buf/rWPtrRsync_3_s0/Q
1.815 0.375 tNET RR 1 u_p2b/u_mid_buf/wWPtrBinX_3_s0/I0
2.341 0.526 tINS RR 7 u_p2b/u_mid_buf/wWPtrBinX_3_s0/F
2.716 0.375 tNET RR 1 u_p2b/u_mid_buf/wWPtrBinX_2_s0/I1
3.233 0.516 tINS RR 2 u_p2b/u_mid_buf/wWPtrBinX_2_s0/F
3.608 0.375 tNET RR 2 u_p2b/u_mid_buf/wRdDiff_2_s/I0
4.164 0.556 tINS RF 1 u_p2b/u_mid_buf/wRdDiff_2_s/COUT
4.164 0.000 tNET FF 2 u_p2b/u_mid_buf/wRdDiff_3_s/CIN
4.214 0.050 tINS FR 1 u_p2b/u_mid_buf/wRdDiff_3_s/COUT
4.214 0.000 tNET RR 2 u_p2b/u_mid_buf/wRdDiff_4_s/CIN
4.264 0.050 tINS RR 1 u_p2b/u_mid_buf/wRdDiff_4_s/COUT
4.264 0.000 tNET RR 2 u_p2b/u_mid_buf/wRdDiff_5_s/CIN
4.314 0.050 tINS RR 1 u_p2b/u_mid_buf/wRdDiff_5_s/COUT
4.314 0.000 tNET RR 2 u_p2b/u_mid_buf/wRdDiff_6_s/CIN
4.558 0.244 tINS RR 1 u_p2b/u_mid_buf/wRdDiff_6_s/SUM
4.933 0.375 tNET RR 1 u_p2b/u_mid_buf/rRdDiff_6_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_BYTE_CLK
10.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
10.682 0.683 tINS RR 81 I_BYTE_CLK_ibuf/O
11.057 0.375 tNET RR 1 u_p2b/u_mid_buf/rRdDiff_6_s0/CLK
10.994 -0.064 tSu 1 u_p2b/u_mid_buf/rRdDiff_6_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.683, 64.539%; route: 0.375, 35.461%
Arrival Data Path Delay: cell: 1.992, 51.419%; route: 1.500, 38.710%; tC2Q: 0.382, 9.871%
Required Clock Path Delay: cell: 0.683, 64.539%; route: 0.375, 35.461%

Path 4

Path Summary:
Slack 6.111
Data Arrival Time 4.882
Data Required Time 10.994
From u_p2b/u_mid_buf/rWPtrRsync_3_s0
To u_p2b/u_mid_buf/rRdDiff_5_s0
Launch Clk I_BYTE_CLK[R]
Latch Clk I_BYTE_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_BYTE_CLK
0.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
0.683 0.683 tINS RR 81 I_BYTE_CLK_ibuf/O
1.058 0.375 tNET RR 1 u_p2b/u_mid_buf/rWPtrRsync_3_s0/CLK
1.440 0.382 tC2Q RR 1 u_p2b/u_mid_buf/rWPtrRsync_3_s0/Q
1.815 0.375 tNET RR 1 u_p2b/u_mid_buf/wWPtrBinX_3_s0/I0
2.341 0.526 tINS RR 7 u_p2b/u_mid_buf/wWPtrBinX_3_s0/F
2.716 0.375 tNET RR 1 u_p2b/u_mid_buf/wWPtrBinX_2_s0/I1
3.233 0.516 tINS RR 2 u_p2b/u_mid_buf/wWPtrBinX_2_s0/F
3.608 0.375 tNET RR 2 u_p2b/u_mid_buf/wRdDiff_2_s/I0
4.164 0.556 tINS RF 1 u_p2b/u_mid_buf/wRdDiff_2_s/COUT
4.164 0.000 tNET FF 2 u_p2b/u_mid_buf/wRdDiff_3_s/CIN
4.214 0.050 tINS FR 1 u_p2b/u_mid_buf/wRdDiff_3_s/COUT
4.214 0.000 tNET RR 2 u_p2b/u_mid_buf/wRdDiff_4_s/CIN
4.264 0.050 tINS RR 1 u_p2b/u_mid_buf/wRdDiff_4_s/COUT
4.264 0.000 tNET RR 2 u_p2b/u_mid_buf/wRdDiff_5_s/CIN
4.508 0.244 tINS RR 1 u_p2b/u_mid_buf/wRdDiff_5_s/SUM
4.883 0.375 tNET RR 1 u_p2b/u_mid_buf/rRdDiff_5_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_BYTE_CLK
10.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
10.682 0.683 tINS RR 81 I_BYTE_CLK_ibuf/O
11.057 0.375 tNET RR 1 u_p2b/u_mid_buf/rRdDiff_5_s0/CLK
10.994 -0.064 tSu 1 u_p2b/u_mid_buf/rRdDiff_5_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.683, 64.539%; route: 0.375, 35.461%
Arrival Data Path Delay: cell: 1.942, 50.784%; route: 1.500, 39.216%; tC2Q: 0.382, 10.000%
Required Clock Path Delay: cell: 0.683, 64.539%; route: 0.375, 35.461%

Path 5

Path Summary:
Slack 6.161
Data Arrival Time 4.832
Data Required Time 10.994
From u_p2b/u_mid_buf/rWPtrRsync_3_s0
To u_p2b/u_mid_buf/rRdDiff_4_s0
Launch Clk I_BYTE_CLK[R]
Latch Clk I_BYTE_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_BYTE_CLK
0.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
0.683 0.683 tINS RR 81 I_BYTE_CLK_ibuf/O
1.058 0.375 tNET RR 1 u_p2b/u_mid_buf/rWPtrRsync_3_s0/CLK
1.440 0.382 tC2Q RR 1 u_p2b/u_mid_buf/rWPtrRsync_3_s0/Q
1.815 0.375 tNET RR 1 u_p2b/u_mid_buf/wWPtrBinX_3_s0/I0
2.341 0.526 tINS RR 7 u_p2b/u_mid_buf/wWPtrBinX_3_s0/F
2.716 0.375 tNET RR 1 u_p2b/u_mid_buf/wWPtrBinX_2_s0/I1
3.233 0.516 tINS RR 2 u_p2b/u_mid_buf/wWPtrBinX_2_s0/F
3.608 0.375 tNET RR 2 u_p2b/u_mid_buf/wRdDiff_2_s/I0
4.164 0.556 tINS RF 1 u_p2b/u_mid_buf/wRdDiff_2_s/COUT
4.164 0.000 tNET FF 2 u_p2b/u_mid_buf/wRdDiff_3_s/CIN
4.214 0.050 tINS FR 1 u_p2b/u_mid_buf/wRdDiff_3_s/COUT
4.214 0.000 tNET RR 2 u_p2b/u_mid_buf/wRdDiff_4_s/CIN
4.458 0.244 tINS RR 1 u_p2b/u_mid_buf/wRdDiff_4_s/SUM
4.833 0.375 tNET RR 1 u_p2b/u_mid_buf/rRdDiff_4_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_BYTE_CLK
10.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
10.682 0.683 tINS RR 81 I_BYTE_CLK_ibuf/O
11.057 0.375 tNET RR 1 u_p2b/u_mid_buf/rRdDiff_4_s0/CLK
10.994 -0.064 tSu 1 u_p2b/u_mid_buf/rRdDiff_4_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.683, 64.539%; route: 0.375, 35.461%
Arrival Data Path Delay: cell: 1.892, 50.133%; route: 1.500, 39.735%; tC2Q: 0.382, 10.132%
Required Clock Path Delay: cell: 0.683, 64.539%; route: 0.375, 35.461%