Timing Messages

Report Title Timing Analysis Report
Design File F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\DSI_Test_Pattern_5a25_soft\fpga_proj\impl\gwsynthesis\Dsi_test_pattern_5a25_soft.vg
Physical Constraints File F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\DSI_Test_Pattern_5a25_soft\fpga_proj\src\DK_START_GW5A_LV25UG324_V1P1.cst
Timing Constraint File F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\DSI_Test_Pattern_5a25_soft\fpga_proj\src\dsi_test.sdc
Tool Version V1.9.9.01 (64-bit)
Part Number GW5A-LV25UG324ES
Device GW5A-25
Device Version A
Created Time Wed Mar 6 17:44:05 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model Slow 0.855V 0C ES
Hold Delay Model Fast 0.945V 85C ES
Numbers of Paths Analyzed 5090
Numbers of Endpoints Analyzed 4222
Numbers of Falling Endpoints 3
Numbers of Setup Violated Endpoints 0
Numbers of Hold Violated Endpoints 0

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Objects
clk_50 Base 20.000 50.000 0.000 10.000 OSC_50M
pixel_clk Generated 7.059 141.667 0.000 3.529 OSC_50M clk_50 pixel_clk
byte_clk Generated 9.412 106.250 0.000 4.706 OSC_50M clk_50 byte_clk
tck_pad_i Base 50.000 20.000 0.000 25.000 tck_ibuf/I
u_pll/PLLA_inst/CLKOUT0.default_gen_clk Generated 2.353 425.000 0.000 1.176 OSC_50M_ibuf/I clk_50 u_pll/PLLA_inst/CLKOUT0
u_pll/PLLA_inst/CLKOUT1.default_gen_clk Generated 2.353 425.000 0.000 1.176 OSC_50M_ibuf/I clk_50 u_pll/PLLA_inst/CLKOUT1

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 pixel_clk 141.667(MHz) 206.199(MHz) 7 TOP
2 byte_clk 106.250(MHz) 124.606(MHz) 8 TOP
3 tck_pad_i 20.000(MHz) 97.522(MHz) 5 TOP

No timing paths to get frequency of clk_50!

No timing paths to get frequency of u_pll/PLLA_inst/CLKOUT0.default_gen_clk!

No timing paths to get frequency of u_pll/PLLA_inst/CLKOUT1.default_gen_clk!

Total Negative Slack Summary:

Clock Name Analysis Type Endpoints TNS Number of Endpoints
clk_50 Setup 0.000 0
clk_50 Hold 0.000 0
pixel_clk Setup 0.000 0
pixel_clk Hold 0.000 0
byte_clk Setup 0.000 0
byte_clk Hold 0.000 0
tck_pad_i Setup 0.000 0
tck_pad_i Hold 0.000 0
u_pll/PLLA_inst/CLKOUT0.default_gen_clk Setup 0.000 0
u_pll/PLLA_inst/CLKOUT0.default_gen_clk Hold 0.000 0
u_pll/PLLA_inst/CLKOUT1.default_gen_clk Setup 0.000 0
u_pll/PLLA_inst/CLKOUT1.default_gen_clk Hold 0.000 0

Timing Details

Path Slacks Table:

Setup Paths Table

Setup Paths Table[1]:

Report Command:report_timing -setup -from_clock [get_clocks {pixel_clk}] -max_paths 20 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 2.209 u_p2b/u_p2b_0/u_mid_buf/rRPtrWsync_6_s0/Q u_p2b/u_p2b_0/u_mid_buf/rFull_s0/D pixel_clk:[R] pixel_clk:[R] 7.059 0.031 4.755
2 2.774 u_test_gen/De_hcnt_1_s3/Q u_test_gen/Data_tmp_15_s1/D pixel_clk:[R] pixel_clk:[R] 7.059 0.019 4.202
3 2.784 u_test_gen/De_hcnt_1_s3/Q u_test_gen/Data_tmp_8_s1/D pixel_clk:[R] pixel_clk:[R] 7.059 0.019 4.193
4 3.122 u_test_gen/De_hcnt_1_s3/Q u_test_gen/Data_tmp_12_s1/D pixel_clk:[R] pixel_clk:[R] 7.059 0.009 3.864
5 3.122 u_test_gen/De_hcnt_1_s3/Q u_test_gen/Data_tmp_14_s1/D pixel_clk:[R] pixel_clk:[R] 7.059 0.009 3.864
6 3.135 u_test_gen/De_hcnt_1_s3/Q u_test_gen/Data_tmp_6_s1/D pixel_clk:[R] pixel_clk:[R] 7.059 0.010 3.850
7 3.150 u_test_gen/De_hcnt_1_s3/Q u_test_gen/Data_tmp_4_s1/D pixel_clk:[R] pixel_clk:[R] 7.059 0.000 3.845
8 3.151 u_test_gen/De_hcnt_1_s3/Q u_test_gen/Data_tmp_10_s1/D pixel_clk:[R] pixel_clk:[R] 7.059 0.019 3.825
9 3.168 u_test_gen/De_hcnt_1_s3/Q u_test_gen/Data_tmp_9_s1/D pixel_clk:[R] pixel_clk:[R] 7.059 0.009 3.817
10 3.179 vs_cnt_9_s0/Q u_test_gen/Data_tmp_7_s1/D pixel_clk:[R] pixel_clk:[R] 7.059 0.024 3.792
11 3.188 u_test_gen/De_hcnt_1_s3/Q u_test_gen/Data_tmp_11_s1/D pixel_clk:[R] pixel_clk:[R] 7.059 0.019 3.789
12 3.244 u_test_gen/De_hcnt_1_s3/Q u_test_gen/Data_tmp_0_s1/D pixel_clk:[R] pixel_clk:[R] 7.059 0.009 3.741
13 3.246 u_test_gen/De_hcnt_1_s3/Q u_test_gen/Data_tmp_2_s1/D pixel_clk:[R] pixel_clk:[R] 7.059 0.017 3.732
14 3.260 u_test_gen/H_cnt_7_s0/Q u_test_gen/V_cnt_0_s1/D pixel_clk:[R] pixel_clk:[R] 7.059 0.000 3.735
15 3.260 u_test_gen/H_cnt_7_s0/Q u_test_gen/V_cnt_1_s1/D pixel_clk:[R] pixel_clk:[R] 7.059 0.000 3.735
16 3.260 u_test_gen/H_cnt_7_s0/Q u_test_gen/V_cnt_4_s1/D pixel_clk:[R] pixel_clk:[R] 7.059 0.000 3.735
17 3.260 u_test_gen/H_cnt_7_s0/Q u_test_gen/V_cnt_5_s1/D pixel_clk:[R] pixel_clk:[R] 7.059 0.000 3.735
18 3.311 u_test_gen/H_cnt_7_s0/Q u_test_gen/V_cnt_2_s1/D pixel_clk:[R] pixel_clk:[R] 7.059 0.000 3.684
19 3.311 u_test_gen/H_cnt_7_s0/Q u_test_gen/V_cnt_6_s1/D pixel_clk:[R] pixel_clk:[R] 7.059 0.000 3.684
20 3.376 u_test_gen/V_cnt_1_s1/Q u_test_gen/V_cnt_11_s1/D pixel_clk:[R] pixel_clk:[R] 7.059 -0.003 3.621

Setup Paths Table[2]:

Report Command:report_timing -setup -from_clock [get_clocks {byte_clk}] -max_paths 20 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 1.386 u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_7_s1/D byte_clk:[R] byte_clk:[R] 9.412 0.000 7.961
2 1.697 u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rWrOffset_9_s1/D byte_clk:[R] byte_clk:[R] 9.412 0.002 7.649
3 1.816 u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mBsram_mBsram_0_0_s/DO[2] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/rCount_8_s1/D byte_clk:[R] byte_clk:[R] 9.412 0.002 7.530
4 1.863 u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_10_s1/D byte_clk:[R] byte_clk:[R] 9.412 0.004 7.481
5 1.888 u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_8_s1/D byte_clk:[R] byte_clk:[R] 9.412 0.004 7.456
6 1.956 u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_9_s1/D byte_clk:[R] byte_clk:[R] 9.412 0.004 7.387
7 1.962 u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rWrOffset_6_s1/D byte_clk:[R] byte_clk:[R] 9.412 0.002 7.384
8 1.962 u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rWrOffset_7_s1/D byte_clk:[R] byte_clk:[R] 9.412 0.002 7.384
9 1.962 u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rWrOffset_8_s1/D byte_clk:[R] byte_clk:[R] 9.412 0.002 7.384
10 2.159 u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_4_s1/D byte_clk:[R] byte_clk:[R] 9.412 0.004 7.185
11 2.216 u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_5_s1/D byte_clk:[R] byte_clk:[R] 9.412 0.004 7.128
12 2.216 u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_6_s1/D byte_clk:[R] byte_clk:[R] 9.412 0.004 7.128
13 2.275 u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mBsram_mBsram_0_0_s/DO[2] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/rCount_7_s1/D byte_clk:[R] byte_clk:[R] 9.412 0.002 7.071
14 2.292 u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mBsram_mBsram_0_0_s/DO[2] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/rCount_5_s1/D byte_clk:[R] byte_clk:[R] 9.412 0.033 7.022
15 2.292 u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mBsram_mBsram_0_0_s/DO[2] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/rCount_6_s1/D byte_clk:[R] byte_clk:[R] 9.412 0.033 7.022
16 2.307 u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mBsram_mBsram_0_0_s/DO[2] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/rCount_10_s1/D byte_clk:[R] byte_clk:[R] 9.412 0.043 6.999
17 2.311 u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mBsram_mBsram_0_0_s/DO[2] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/rCount_11_s1/D byte_clk:[R] byte_clk:[R] 9.412 0.026 7.011
18 2.395 u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rRdOffset_8_s1/D byte_clk:[R] byte_clk:[R] 9.412 0.002 6.951
19 2.401 u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14] u_tx_phy/DPHY_TX_INST/u_oserx4x8/U5_OSER83/D5 byte_clk:[R] byte_clk:[R] 9.412 -0.046 6.891
20 2.456 u_dsi_tx/u_tx/u_dsi_tx/rRemainder_3_s0/Q u_dsi_tx/u_tx/u_dsi_tx/rRegData_112_s1/D byte_clk:[R] byte_clk:[R] 9.412 0.010 6.882

Hold Paths Table

Hold Paths Table[1]:

Report Command:report_timing -hold -from_clock [get_clocks {pixel_clk}] -max_paths 20 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.199 u_p2b/u_p2b_0/u_mid_buf/rWPtrBin_5_s0/Q u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s/ADA[10] pixel_clk:[R] pixel_clk:[R] 0.000 0.006 0.311
2 0.277 u_p2b/u_p2b_0/mid_data_27_s1/Q u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s/DI[27] pixel_clk:[R] pixel_clk:[R] 0.000 -0.008 0.534
3 0.277 u_p2b/u_p2b_0/mid_data_19_s1/Q u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s/DI[19] pixel_clk:[R] pixel_clk:[R] 0.000 -0.008 0.534
4 0.290 u_p2b/u_p2b_0/mid_data_26_s1/Q u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s/DI[26] pixel_clk:[R] pixel_clk:[R] 0.000 -0.008 0.546
5 0.374 frame_led_s2/Q frame_led_s2/D pixel_clk:[R] pixel_clk:[R] 0.000 0.000 0.375
6 0.374 u_p2b/u_p2b_0/loop_cnt_0_s0/Q u_p2b/u_p2b_0/loop_cnt_0_s0/D pixel_clk:[R] pixel_clk:[R] 0.000 0.000 0.375
7 0.376 u_p2b/u_p2b_0/mid_data_3_s1/Q u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s/DI[3] pixel_clk:[R] pixel_clk:[R] 0.000 -0.002 0.627
8 0.378 u_test_gen/H_cnt_2_s0/Q u_test_gen/H_cnt_2_s0/D pixel_clk:[R] pixel_clk:[R] 0.000 0.000 0.379
9 0.378 u_test_gen/H_cnt_8_s0/Q u_test_gen/H_cnt_8_s0/D pixel_clk:[R] pixel_clk:[R] 0.000 0.000 0.379
10 0.377 u_test_gen/De_hcnt_1_s3/Q u_test_gen/De_hcnt_1_s3/D pixel_clk:[R] pixel_clk:[R] 0.000 0.000 0.379
11 0.378 u_test_gen/Color_trig_num_4_s3/Q u_test_gen/Color_trig_num_4_s3/D pixel_clk:[R] pixel_clk:[R] 0.000 0.000 0.379
12 0.378 u_test_gen/Color_trig_num_8_s3/Q u_test_gen/Color_trig_num_8_s3/D pixel_clk:[R] pixel_clk:[R] 0.000 0.000 0.379
13 0.381 u_test_gen/De_hcnt_9_s1/Q u_test_gen/De_hcnt_9_s1/D pixel_clk:[R] pixel_clk:[R] 0.000 0.000 0.382
14 0.381 u_test_gen/V_cnt_4_s1/Q u_test_gen/V_cnt_4_s1/D pixel_clk:[R] pixel_clk:[R] 0.000 0.000 0.382
15 0.381 u_test_gen/Color_trig_num_5_s3/Q u_test_gen/Color_trig_num_5_s3/D pixel_clk:[R] pixel_clk:[R] 0.000 0.000 0.382
16 0.389 u_test_gen/V_cnt_0_s1/Q u_test_gen/V_cnt_0_s1/D pixel_clk:[R] pixel_clk:[R] 0.000 0.000 0.390
17 0.390 u_p2b/u_p2b_0/mid_data_7_s1/Q u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s/DI[7] pixel_clk:[R] pixel_clk:[R] 0.000 -0.007 0.646
18 0.392 u_test_gen/H_cnt_7_s0/Q u_test_gen/H_cnt_7_s0/D pixel_clk:[R] pixel_clk:[R] 0.000 0.000 0.394
19 0.393 u_p2b/u_p2b_0/u_mid_buf/rWPtrBin_1_s0/Q u_p2b/u_p2b_0/u_mid_buf/rWPtrBin_1_s0/D pixel_clk:[R] pixel_clk:[R] 0.000 0.000 0.394
20 0.393 u_p2b/u_p2b_0/u_mid_buf/rWPtrBin_4_s0/Q u_p2b/u_p2b_0/u_mid_buf/rWPtrBin_4_s0/D pixel_clk:[R] pixel_clk:[R] 0.000 0.000 0.394

Hold Paths Table[2]:

Report Command:report_timing -hold -from_clock [get_clocks {byte_clk}] -max_paths 20 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.264 u_dsi_tx/u_tx/u_dsi_tx/rCtrl_3_s0/Q u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mBsram_mBsram_0_0_s/DI[3] byte_clk:[R] byte_clk:[R] 0.000 0.013 0.500
2 0.264 u_dsi_tx/u_tx/u_dsi_tx/rCtrl_1_s0/Q u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mBsram_mBsram_0_0_s/DI[1] byte_clk:[R] byte_clk:[R] 0.000 0.013 0.500
3 0.270 u_la0_top/u_ao_mem_ctrl/data_reg_37_s0/Q u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[5] byte_clk:[R] byte_clk:[R] 0.000 0.000 0.519
4 0.287 u_la0_top/u_ao_mem_ctrl/data_reg_6_s0/Q u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[6] byte_clk:[R] byte_clk:[R] 0.000 0.000 0.536
5 0.287 u_la0_top/u_ao_mem_ctrl/data_reg_2_s0/Q u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[2] byte_clk:[R] byte_clk:[R] 0.000 0.000 0.536
6 0.287 u_la0_top/u_ao_mem_ctrl/data_reg_0_s0/Q u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[0] byte_clk:[R] byte_clk:[R] 0.000 0.000 0.536
7 0.299 u_dsi_tx/u_tx/u_dsi_tx/rCtrl_2_s0/Q u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mBsram_mBsram_0_0_s/DI[2] byte_clk:[R] byte_clk:[R] 0.000 0.008 0.540
8 0.306 u_la0_top/u_ao_mem_ctrl/data_reg_35_s0/Q u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[3] byte_clk:[R] byte_clk:[R] 0.000 0.000 0.555
9 0.306 u_la0_top/u_ao_mem_ctrl/data_reg_34_s0/Q u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[2] byte_clk:[R] byte_clk:[R] 0.000 0.000 0.555
10 0.308 u_dsi_tx/u_tx/u_dsi_tx/rCtrl_0_s0/Q u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mBsram_mBsram_0_0_s/DI[0] byte_clk:[R] byte_clk:[R] 0.000 0.006 0.551
11 0.311 u_dsi_tx/u_tx/u_dsi_tx/rCtrl_13_s0/Q u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mBsram_mBsram_0_0_s/DI[6] byte_clk:[R] byte_clk:[R] 0.000 0.013 0.547
12 0.312 u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/rWrOffset_1_s1/Q u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mBsram_mBsram_0_0_s/ADA[4] byte_clk:[R] byte_clk:[R] 0.000 0.006 0.424
13 0.317 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/Q u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/ADA[7] byte_clk:[R] byte_clk:[R] 0.000 0.000 0.435
14 0.319 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/Q u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/ADA[5] byte_clk:[R] byte_clk:[R] 0.000 0.000 0.438
15 0.319 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/Q u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/ADA[5] byte_clk:[R] byte_clk:[R] 0.000 0.000 0.438
16 0.326 u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/rWrOffset_4_s1/Q u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mBsram_mBsram_0_0_s/ADA[7] byte_clk:[R] byte_clk:[R] 0.000 0.011 0.433
17 0.329 u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/rWrOffset_3_s1/Q u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mBsram_mBsram_0_0_s/ADA[6] byte_clk:[R] byte_clk:[R] 0.000 0.011 0.436
18 0.337 u_la0_top/u_ao_mem_ctrl/data_reg_9_s0/Q u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[9] byte_clk:[R] byte_clk:[R] 0.000 0.000 0.586
19 0.337 u_la0_top/u_ao_mem_ctrl/data_reg_8_s0/Q u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[8] byte_clk:[R] byte_clk:[R] 0.000 0.000 0.586
20 0.337 u_la0_top/u_ao_mem_ctrl/data_reg_3_s0/Q u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[3] byte_clk:[R] byte_clk:[R] 0.000 0.000 0.586

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.839 u_la0_top/rst_ao_s0/Q u_la0_top/internal_reg_start_syn_0_s0/CLEAR byte_clk:[F] byte_clk:[R] 4.706 0.000 3.519
2 0.865 u_la0_top/rst_ao_s0/Q u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR byte_clk:[F] byte_clk:[R] 4.706 0.000 3.494
3 0.865 u_la0_top/rst_ao_s0/Q u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR byte_clk:[F] byte_clk:[R] 4.706 0.000 3.494
4 0.865 u_la0_top/rst_ao_s0/Q u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR byte_clk:[F] byte_clk:[R] 4.706 0.000 3.494
5 0.865 u_la0_top/rst_ao_s0/Q u_la0_top/start_reg_s0/CLEAR byte_clk:[F] byte_clk:[R] 4.706 0.000 3.494
6 0.865 u_la0_top/rst_ao_s0/Q u_la0_top/internal_reg_start_dly_0_s0/CLEAR byte_clk:[F] byte_clk:[R] 4.706 0.000 3.494
7 0.868 u_la0_top/rst_ao_s0/Q u_la0_top/capture_window_sel_2_s1/CLEAR byte_clk:[F] byte_clk:[R] 4.706 0.000 3.490
8 0.868 u_la0_top/rst_ao_s0/Q u_la0_top/capture_window_sel_3_s1/CLEAR byte_clk:[F] byte_clk:[R] 4.706 0.000 3.490
9 0.868 u_la0_top/rst_ao_s0/Q u_la0_top/capture_window_sel_4_s1/CLEAR byte_clk:[F] byte_clk:[R] 4.706 0.000 3.490
10 0.868 u_la0_top/rst_ao_s0/Q u_la0_top/capture_window_sel_5_s1/CLEAR byte_clk:[F] byte_clk:[R] 4.706 0.000 3.490
11 0.868 u_la0_top/rst_ao_s0/Q u_la0_top/capture_window_sel_6_s1/CLEAR byte_clk:[F] byte_clk:[R] 4.706 0.000 3.490
12 0.868 u_la0_top/rst_ao_s0/Q u_la0_top/capture_window_sel_7_s1/CLEAR byte_clk:[F] byte_clk:[R] 4.706 0.000 3.490
13 0.868 u_la0_top/rst_ao_s0/Q u_la0_top/capture_window_sel_8_s1/CLEAR byte_clk:[F] byte_clk:[R] 4.706 0.000 3.490
14 0.876 u_la0_top/rst_ao_s0/Q u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR byte_clk:[F] byte_clk:[R] 4.706 0.000 3.482
15 0.876 u_la0_top/rst_ao_s0/Q u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR byte_clk:[F] byte_clk:[R] 4.706 0.000 3.482
16 0.876 u_la0_top/rst_ao_s0/Q u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR byte_clk:[F] byte_clk:[R] 4.706 0.000 3.482
17 0.876 u_la0_top/rst_ao_s0/Q u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR byte_clk:[F] byte_clk:[R] 4.706 0.000 3.482
18 0.880 u_la0_top/rst_ao_s0/Q u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR byte_clk:[F] byte_clk:[R] 4.706 0.000 3.478
19 0.880 u_la0_top/rst_ao_s0/Q u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET byte_clk:[F] byte_clk:[R] 4.706 0.000 3.478
20 0.880 u_la0_top/rst_ao_s0/Q u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR byte_clk:[F] byte_clk:[R] 4.706 0.000 3.478
21 0.880 u_la0_top/rst_ao_s0/Q u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR byte_clk:[F] byte_clk:[R] 4.706 0.000 3.478
22 0.880 u_la0_top/rst_ao_s0/Q u_la0_top/capture_end_dly_s0/PRESET byte_clk:[F] byte_clk:[R] 4.706 0.000 3.478
23 0.882 u_la0_top/rst_ao_s0/Q u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLEAR byte_clk:[F] byte_clk:[R] 4.706 0.000 3.476
24 0.882 u_la0_top/rst_ao_s0/Q u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR byte_clk:[F] byte_clk:[R] 4.706 0.000 3.476
25 0.882 u_la0_top/rst_ao_s0/Q u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR byte_clk:[F] byte_clk:[R] 4.706 0.000 3.476

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 6.482 u_la0_top/rst_ao_s0/Q u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR byte_clk:[F] byte_clk:[R] -4.706 0.000 1.587
2 6.506 u_la0_top/rst_ao_s0/Q u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR byte_clk:[F] byte_clk:[R] -4.706 0.000 1.611
3 6.506 u_la0_top/rst_ao_s0/Q u_la0_top/trigger_seq_start_s1/CLEAR byte_clk:[F] byte_clk:[R] -4.706 0.000 1.611
4 6.506 u_la0_top/rst_ao_s0/Q u_la0_top/internal_reg_start_dly_1_s0/CLEAR byte_clk:[F] byte_clk:[R] -4.706 0.000 1.611
5 6.506 u_la0_top/rst_ao_s0/Q u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR byte_clk:[F] byte_clk:[R] -4.706 0.000 1.611
6 6.508 u_la0_top/rst_ao_s0/Q u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR byte_clk:[F] byte_clk:[R] -4.706 0.000 1.614
7 6.508 u_la0_top/rst_ao_s0/Q u_la0_top/internal_reg_start_syn_1_s0/CLEAR byte_clk:[F] byte_clk:[R] -4.706 0.000 1.614
8 6.517 u_la0_top/rst_ao_s0/Q u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR byte_clk:[F] byte_clk:[R] -4.706 0.000 1.622
9 6.517 u_la0_top/rst_ao_s0/Q u_la0_top/u_ao_match_0/match_sep_s0/CLEAR byte_clk:[F] byte_clk:[R] -4.706 0.000 1.623
10 6.517 u_la0_top/rst_ao_s0/Q u_la0_top/u_ao_match_0/trig_dly_0_s0/CLEAR byte_clk:[F] byte_clk:[R] -4.706 0.000 1.623
11 6.517 u_la0_top/rst_ao_s0/Q u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR byte_clk:[F] byte_clk:[R] -4.706 0.000 1.623
12 6.518 u_la0_top/rst_ao_s0/Q u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR byte_clk:[F] byte_clk:[R] -4.706 0.000 1.623
13 6.520 u_la0_top/rst_ao_s0/Q u_la0_top/triger_level_cnt_0_s3/CLEAR byte_clk:[F] byte_clk:[R] -4.706 0.000 1.625
14 6.520 u_la0_top/rst_ao_s0/Q u_la0_top/capture_window_sel_9_s1/CLEAR byte_clk:[F] byte_clk:[R] -4.706 0.000 1.625
15 6.520 u_la0_top/rst_ao_s0/Q u_la0_top/triger_level_cnt_1_s1/CLEAR byte_clk:[F] byte_clk:[R] -4.706 0.000 1.625
16 6.520 u_la0_top/rst_ao_s0/Q u_la0_top/triger_level_cnt_2_s1/CLEAR byte_clk:[F] byte_clk:[R] -4.706 0.000 1.625
17 6.520 u_la0_top/rst_ao_s0/Q u_la0_top/triger_level_cnt_3_s1/CLEAR byte_clk:[F] byte_clk:[R] -4.706 0.000 1.625
18 6.520 u_la0_top/rst_ao_s0/Q u_la0_top/triger_s0/CLEAR byte_clk:[F] byte_clk:[R] -4.706 0.000 1.625
19 6.521 u_la0_top/rst_ao_s0/Q u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLEAR byte_clk:[F] byte_clk:[R] -4.706 0.000 1.626
20 6.521 u_la0_top/rst_ao_s0/Q u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR byte_clk:[F] byte_clk:[R] -4.706 0.000 1.626
21 6.521 u_la0_top/rst_ao_s0/Q u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR byte_clk:[F] byte_clk:[R] -4.706 0.000 1.626
22 6.521 u_la0_top/rst_ao_s0/Q u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR byte_clk:[F] byte_clk:[R] -4.706 0.000 1.626
23 6.521 u_la0_top/rst_ao_s0/Q u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR byte_clk:[F] byte_clk:[R] -4.706 0.000 1.626
24 6.522 u_la0_top/rst_ao_s0/Q u_la0_top/capture_window_sel_0_s3/CLEAR byte_clk:[F] byte_clk:[R] -4.706 0.000 1.627
25 6.522 u_la0_top/rst_ao_s0/Q u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR byte_clk:[F] byte_clk:[R] -4.706 0.000 1.627

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number Slack Actual Width Required Width Type Clock Objects
1 2.033 3.033 1.000 Low Pulse Width pixel_clk u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s
2 2.035 3.035 1.000 High Pulse Width pixel_clk u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s
3 2.773 3.023 0.250 Low Pulse Width pixel_clk u_p2b/u_p2b_0/shift_data_117_s0
4 2.773 3.023 0.250 Low Pulse Width pixel_clk vs_cnt_6_s0
5 2.773 3.023 0.250 Low Pulse Width pixel_clk vs_cnt_5_s0
6 2.773 3.023 0.250 Low Pulse Width pixel_clk vs_cnt_4_s0
7 2.773 3.023 0.250 Low Pulse Width pixel_clk vs_cnt_3_s0
8 2.773 3.023 0.250 Low Pulse Width pixel_clk vs_cnt_2_s0
9 2.773 3.023 0.250 Low Pulse Width pixel_clk vs_cnt_1_s0
10 2.773 3.023 0.250 Low Pulse Width pixel_clk vs_cnt_0_s0

Timing Report By Analysis Type:

Setup Analysis Report

Setup Analysis Report[1]:

Report Command:report_timing -setup -from_clock [get_clocks {pixel_clk}] -max_paths 20 -max_common_paths 1

Path1

Path Summary:

Slack 2.209
Data Arrival Time 5.622
Data Required Time 7.831
From u_p2b/u_p2b_0/u_mid_buf/rRPtrWsync_6_s0
To u_p2b/u_p2b_0/u_mid_buf/rFull_s0
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 278 PLL_B u_pll/PLLA_inst/CLKOUT3
0.867 0.867 tNET RR 1 R9C38[2][B] u_p2b/u_p2b_0/u_mid_buf/rRPtrWsync_6_s0/CLK
1.249 0.382 tC2Q RR 5 R9C38[2][B] u_p2b/u_p2b_0/u_mid_buf/rRPtrWsync_6_s0/Q
1.801 0.551 tNET RR 1 R11C38[3][A] u_p2b/u_p2b_0/u_mid_buf/wRPtrBinX_3_s0/I3
2.322 0.521 tINS RR 5 R11C38[3][A] u_p2b/u_p2b_0/u_mid_buf/wRPtrBinX_3_s0/F
2.677 0.355 tNET RR 1 R12C38[3][A] u_p2b/u_p2b_0/u_mid_buf/wRPtrBinX_0_s1/I3
3.174 0.498 tINS RR 1 R12C38[3][A] u_p2b/u_p2b_0/u_mid_buf/wRPtrBinX_0_s1/F
3.547 0.373 tNET RR 2 R13C37[0][A] u_p2b/u_p2b_0/u_mid_buf/n383_s0/I1
4.109 0.562 tINS RF 1 R13C37[0][A] u_p2b/u_p2b_0/u_mid_buf/n383_s0/COUT
4.109 0.000 tNET FF 2 R13C37[0][B] u_p2b/u_p2b_0/u_mid_buf/n384_s0/CIN
4.159 0.050 tINS FR 1 R13C37[0][B] u_p2b/u_p2b_0/u_mid_buf/n384_s0/COUT
4.159 0.000 tNET RR 2 R13C37[1][A] u_p2b/u_p2b_0/u_mid_buf/n385_s0/CIN
4.209 0.050 tINS RR 1 R13C37[1][A] u_p2b/u_p2b_0/u_mid_buf/n385_s0/COUT
4.209 0.000 tNET RR 2 R13C37[1][B] u_p2b/u_p2b_0/u_mid_buf/n386_s0/CIN
4.259 0.050 tINS RR 1 R13C37[1][B] u_p2b/u_p2b_0/u_mid_buf/n386_s0/COUT
4.259 0.000 tNET RR 2 R13C37[2][A] u_p2b/u_p2b_0/u_mid_buf/n387_s0/CIN
4.309 0.050 tINS RR 1 R13C37[2][A] u_p2b/u_p2b_0/u_mid_buf/n387_s0/COUT
4.309 0.000 tNET RR 2 R13C37[2][B] u_p2b/u_p2b_0/u_mid_buf/n388_s0/CIN
4.359 0.050 tINS RR 1 R13C37[2][B] u_p2b/u_p2b_0/u_mid_buf/n388_s0/COUT
4.761 0.401 tNET RR 1 R12C38[2][B] u_p2b/u_p2b_0/u_mid_buf/n402_s4/I0
5.023 0.262 tINS RR 1 R12C38[2][B] u_p2b/u_p2b_0/u_mid_buf/n402_s4/F
5.161 0.137 tNET RR 1 R12C38[0][A] u_p2b/u_p2b_0/u_mid_buf/n402_s0/I3
5.622 0.461 tINS RR 1 R12C38[0][A] u_p2b/u_p2b_0/u_mid_buf/n402_s0/F
5.622 0.000 tNET RR 1 R12C38[0][A] u_p2b/u_p2b_0/u_mid_buf/rFull_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.059 7.059 active clock edge time
7.059 0.000 pixel_clk
7.059 0.000 tCL RR 278 PLL_B u_pll/PLLA_inst/CLKOUT3
7.895 0.836 tNET RR 1 R12C38[0][A] u_p2b/u_p2b_0/u_mid_buf/rFull_s0/CLK
7.831 -0.064 tSu 1 R12C38[0][A] u_p2b/u_p2b_0/u_mid_buf/rFull_s0

Path Statistics:

Clock Skew -0.031
Setup Relationship 7.059
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.867, 100.000%
Arrival Data Path Delay cell: 2.555, 53.733%; route: 1.817, 38.223%; tC2Q: 0.382, 8.044%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.836, 100.000%

Path2

Path Summary:

Slack 2.774
Data Arrival Time 5.105
Data Required Time 7.879
From u_test_gen/De_hcnt_1_s3
To u_test_gen/Data_tmp_15_s1
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 278 PLL_B u_pll/PLLA_inst/CLKOUT3
0.902 0.902 tNET RR 1 R24C40[1][A] u_test_gen/De_hcnt_1_s3/CLK
1.285 0.382 tC2Q RR 7 R24C40[1][A] u_test_gen/De_hcnt_1_s3/Q
1.860 0.575 tNET RR 1 R25C37[0][A] u_test_gen/n1245_s9/I1
2.376 0.516 tINS RR 2 R25C37[0][A] u_test_gen/n1245_s9/F
2.786 0.410 tNET RR 1 R26C38[0][B] u_test_gen/n1245_s8/I1
3.049 0.262 tINS RR 9 R26C38[0][B] u_test_gen/n1245_s8/F
3.412 0.364 tNET RR 1 R27C39[3][B] u_test_gen/n1245_s5/I1
3.702 0.290 tINS RF 16 R27C39[3][B] u_test_gen/n1245_s5/F
4.579 0.876 tNET FF 1 R24C34[2][B] u_test_gen/n1231_s1/I2
5.105 0.526 tINS FR 1 R24C34[2][B] u_test_gen/n1231_s1/F
5.105 0.000 tNET RR 1 R24C34[2][B] u_test_gen/Data_tmp_15_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.059 7.059 active clock edge time
7.059 0.000 pixel_clk
7.059 0.000 tCL RR 278 PLL_B u_pll/PLLA_inst/CLKOUT3
7.943 0.884 tNET RR 1 R24C34[2][B] u_test_gen/Data_tmp_15_s1/CLK
7.879 -0.064 tSu 1 R24C34[2][B] u_test_gen/Data_tmp_15_s1

Path Statistics:

Clock Skew -0.019
Setup Relationship 7.059
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay cell: 1.595, 37.954%; route: 2.225, 52.945%; tC2Q: 0.382, 9.102%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.884, 100.000%

Path3

Path Summary:

Slack 2.784
Data Arrival Time 5.095
Data Required Time 7.879
From u_test_gen/De_hcnt_1_s3
To u_test_gen/Data_tmp_8_s1
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 278 PLL_B u_pll/PLLA_inst/CLKOUT3
0.902 0.902 tNET RR 1 R24C40[1][A] u_test_gen/De_hcnt_1_s3/CLK
1.285 0.382 tC2Q RR 7 R24C40[1][A] u_test_gen/De_hcnt_1_s3/Q
1.860 0.575 tNET RR 1 R25C37[0][A] u_test_gen/n1245_s9/I1
2.376 0.516 tINS RR 2 R25C37[0][A] u_test_gen/n1245_s9/F
2.786 0.410 tNET RR 1 R26C38[0][B] u_test_gen/n1245_s8/I1
3.049 0.262 tINS RR 9 R26C38[0][B] u_test_gen/n1245_s8/F
3.412 0.364 tNET RR 1 R27C39[3][B] u_test_gen/n1245_s5/I1
3.702 0.290 tINS RF 16 R27C39[3][B] u_test_gen/n1245_s5/F
4.579 0.876 tNET FF 1 R24C34[0][B] u_test_gen/n1238_s2/I2
5.095 0.516 tINS FR 1 R24C34[0][B] u_test_gen/n1238_s2/F
5.095 0.000 tNET RR 1 R24C34[0][B] u_test_gen/Data_tmp_8_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.059 7.059 active clock edge time
7.059 0.000 pixel_clk
7.059 0.000 tCL RR 278 PLL_B u_pll/PLLA_inst/CLKOUT3
7.943 0.884 tNET RR 1 R24C34[0][B] u_test_gen/Data_tmp_8_s1/CLK
7.879 -0.064 tSu 1 R24C34[0][B] u_test_gen/Data_tmp_8_s1

Path Statistics:

Clock Skew -0.019
Setup Relationship 7.059
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay cell: 1.585, 37.806%; route: 2.225, 53.071%; tC2Q: 0.382, 9.123%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.884, 100.000%

Path4

Path Summary:

Slack 3.122
Data Arrival Time 4.766
Data Required Time 7.888
From u_test_gen/De_hcnt_1_s3
To u_test_gen/Data_tmp_12_s1
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 278 PLL_B u_pll/PLLA_inst/CLKOUT3
0.902 0.902 tNET RR 1 R24C40[1][A] u_test_gen/De_hcnt_1_s3/CLK
1.285 0.382 tC2Q RR 7 R24C40[1][A] u_test_gen/De_hcnt_1_s3/Q
1.860 0.575 tNET RR 1 R25C37[0][A] u_test_gen/n1245_s9/I1
2.376 0.516 tINS RR 2 R25C37[0][A] u_test_gen/n1245_s9/F
2.786 0.410 tNET RR 1 R26C38[0][B] u_test_gen/n1245_s8/I1
3.049 0.262 tINS RR 9 R26C38[0][B] u_test_gen/n1245_s8/F
3.412 0.364 tNET RR 1 R27C39[3][B] u_test_gen/n1245_s5/I1
3.702 0.290 tINS RF 16 R27C39[3][B] u_test_gen/n1245_s5/F
4.305 0.603 tNET FF 1 R24C37[1][B] u_test_gen/n1234_s2/I2
4.766 0.461 tINS FR 1 R24C37[1][B] u_test_gen/n1234_s2/F
4.766 0.000 tNET RR 1 R24C37[1][B] u_test_gen/Data_tmp_12_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.059 7.059 active clock edge time
7.059 0.000 pixel_clk
7.059 0.000 tCL RR 278 PLL_B u_pll/PLLA_inst/CLKOUT3
7.952 0.893 tNET RR 1 R24C37[1][B] u_test_gen/Data_tmp_12_s1/CLK
7.888 -0.064 tSu 1 R24C37[1][B] u_test_gen/Data_tmp_12_s1

Path Statistics:

Clock Skew -0.009
Setup Relationship 7.059
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay cell: 1.530, 39.599%; route: 1.951, 50.501%; tC2Q: 0.382, 9.900%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.893, 100.000%

Path5

Path Summary:

Slack 3.122
Data Arrival Time 4.766
Data Required Time 7.888
From u_test_gen/De_hcnt_1_s3
To u_test_gen/Data_tmp_14_s1
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 278 PLL_B u_pll/PLLA_inst/CLKOUT3
0.902 0.902 tNET RR 1 R24C40[1][A] u_test_gen/De_hcnt_1_s3/CLK
1.285 0.382 tC2Q RR 7 R24C40[1][A] u_test_gen/De_hcnt_1_s3/Q
1.860 0.575 tNET RR 1 R25C37[0][A] u_test_gen/n1245_s9/I1
2.376 0.516 tINS RR 2 R25C37[0][A] u_test_gen/n1245_s9/F
2.786 0.410 tNET RR 1 R26C38[0][B] u_test_gen/n1245_s8/I1
3.049 0.262 tINS RR 9 R26C38[0][B] u_test_gen/n1245_s8/F
3.412 0.364 tNET RR 1 R27C39[3][B] u_test_gen/n1245_s5/I1
3.702 0.290 tINS RF 16 R27C39[3][B] u_test_gen/n1245_s5/F
4.305 0.603 tNET FF 1 R24C37[1][A] u_test_gen/n1232_s2/I2
4.766 0.461 tINS FR 1 R24C37[1][A] u_test_gen/n1232_s2/F
4.766 0.000 tNET RR 1 R24C37[1][A] u_test_gen/Data_tmp_14_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.059 7.059 active clock edge time
7.059 0.000 pixel_clk
7.059 0.000 tCL RR 278 PLL_B u_pll/PLLA_inst/CLKOUT3
7.952 0.893 tNET RR 1 R24C37[1][A] u_test_gen/Data_tmp_14_s1/CLK
7.888 -0.064 tSu 1 R24C37[1][A] u_test_gen/Data_tmp_14_s1

Path Statistics:

Clock Skew -0.009
Setup Relationship 7.059
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay cell: 1.530, 39.599%; route: 1.951, 50.501%; tC2Q: 0.382, 9.900%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.893, 100.000%

Path6

Path Summary:

Slack 3.135
Data Arrival Time 4.752
Data Required Time 7.888
From u_test_gen/De_hcnt_1_s3
To u_test_gen/Data_tmp_6_s1
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 278 PLL_B u_pll/PLLA_inst/CLKOUT3
0.902 0.902 tNET RR 1 R24C40[1][A] u_test_gen/De_hcnt_1_s3/CLK
1.285 0.382 tC2Q RR 7 R24C40[1][A] u_test_gen/De_hcnt_1_s3/Q
1.860 0.575 tNET RR 1 R25C37[0][A] u_test_gen/n1245_s9/I1
2.376 0.516 tINS RR 2 R25C37[0][A] u_test_gen/n1245_s9/F
2.786 0.410 tNET RR 1 R26C38[0][B] u_test_gen/n1245_s8/I1
3.049 0.262 tINS RR 9 R26C38[0][B] u_test_gen/n1245_s8/F
3.412 0.364 tNET RR 1 R27C39[3][B] u_test_gen/n1245_s5/I1
3.702 0.290 tINS RF 16 R27C39[3][B] u_test_gen/n1245_s5/F
4.291 0.589 tNET FF 1 R26C36[0][B] u_test_gen/n1240_s1/I2
4.752 0.461 tINS FR 1 R26C36[0][B] u_test_gen/n1240_s1/F
4.752 0.000 tNET RR 1 R26C36[0][B] u_test_gen/Data_tmp_6_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.059 7.059 active clock edge time
7.059 0.000 pixel_clk
7.059 0.000 tCL RR 278 PLL_B u_pll/PLLA_inst/CLKOUT3
7.952 0.893 tNET RR 1 R26C36[0][B] u_test_gen/Data_tmp_6_s1/CLK
7.888 -0.064 tSu 1 R26C36[0][B] u_test_gen/Data_tmp_6_s1

Path Statistics:

Clock Skew -0.010
Setup Relationship 7.059
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay cell: 1.530, 39.740%; route: 1.938, 50.325%; tC2Q: 0.382, 9.935%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.893, 100.000%

Path7

Path Summary:

Slack 3.150
Data Arrival Time 4.747
Data Required Time 7.898
From u_test_gen/De_hcnt_1_s3
To u_test_gen/Data_tmp_4_s1
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 278 PLL_B u_pll/PLLA_inst/CLKOUT3
0.902 0.902 tNET RR 1 R24C40[1][A] u_test_gen/De_hcnt_1_s3/CLK
1.285 0.382 tC2Q RR 7 R24C40[1][A] u_test_gen/De_hcnt_1_s3/Q
1.860 0.575 tNET RR 1 R25C37[0][A] u_test_gen/n1245_s9/I1
2.376 0.516 tINS RR 2 R25C37[0][A] u_test_gen/n1245_s9/F
2.786 0.410 tNET RR 1 R26C38[0][B] u_test_gen/n1245_s8/I1
3.049 0.262 tINS RR 9 R26C38[0][B] u_test_gen/n1245_s8/F
3.412 0.364 tNET RR 1 R27C39[3][B] u_test_gen/n1245_s5/I1
3.702 0.290 tINS RF 16 R27C39[3][B] u_test_gen/n1245_s5/F
4.485 0.783 tNET FF 1 R24C36[2][B] u_test_gen/n1242_s1/I2
4.747 0.262 tINS FR 1 R24C36[2][B] u_test_gen/n1242_s1/F
4.747 0.000 tNET RR 1 R24C36[2][B] u_test_gen/Data_tmp_4_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.059 7.059 active clock edge time
7.059 0.000 pixel_clk
7.059 0.000 tCL RR 278 PLL_B u_pll/PLLA_inst/CLKOUT3
7.961 0.902 tNET RR 1 R24C36[2][B] u_test_gen/Data_tmp_4_s1/CLK
7.898 -0.064 tSu 1 R24C36[2][B] u_test_gen/Data_tmp_4_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 7.059
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay cell: 1.331, 34.623%; route: 2.131, 55.429%; tC2Q: 0.382, 9.948%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Path8

Path Summary:

Slack 3.151
Data Arrival Time 4.727
Data Required Time 7.879
From u_test_gen/De_hcnt_1_s3
To u_test_gen/Data_tmp_10_s1
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 278 PLL_B u_pll/PLLA_inst/CLKOUT3
0.902 0.902 tNET RR 1 R24C40[1][A] u_test_gen/De_hcnt_1_s3/CLK
1.285 0.382 tC2Q RR 7 R24C40[1][A] u_test_gen/De_hcnt_1_s3/Q
1.860 0.575 tNET RR 1 R25C37[0][A] u_test_gen/n1245_s9/I1
2.376 0.516 tINS RR 2 R25C37[0][A] u_test_gen/n1245_s9/F
2.786 0.410 tNET RR 1 R26C38[0][B] u_test_gen/n1245_s8/I1
3.049 0.262 tINS RR 9 R26C38[0][B] u_test_gen/n1245_s8/F
3.412 0.364 tNET RR 1 R27C39[3][B] u_test_gen/n1245_s5/I1
3.702 0.290 tINS RF 16 R27C39[3][B] u_test_gen/n1245_s5/F
4.266 0.564 tNET FF 1 R24C38[1][B] u_test_gen/n1236_s2/I2
4.727 0.461 tINS FR 1 R24C38[1][B] u_test_gen/n1236_s2/F
4.727 0.000 tNET RR 1 R24C38[1][B] u_test_gen/Data_tmp_10_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.059 7.059 active clock edge time
7.059 0.000 pixel_clk
7.059 0.000 tCL RR 278 PLL_B u_pll/PLLA_inst/CLKOUT3
7.943 0.884 tNET RR 1 R24C38[1][B] u_test_gen/Data_tmp_10_s1/CLK
7.879 -0.064 tSu 1 R24C38[1][B] u_test_gen/Data_tmp_10_s1

Path Statistics:

Clock Skew -0.019
Setup Relationship 7.059
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay cell: 1.530, 40.000%; route: 1.912, 50.000%; tC2Q: 0.382, 10.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.884, 100.000%

Path9

Path Summary:

Slack 3.168
Data Arrival Time 4.720
Data Required Time 7.888
From u_test_gen/De_hcnt_1_s3
To u_test_gen/Data_tmp_9_s1
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 278 PLL_B u_pll/PLLA_inst/CLKOUT3
0.902 0.902 tNET RR 1 R24C40[1][A] u_test_gen/De_hcnt_1_s3/CLK
1.285 0.382 tC2Q RR 7 R24C40[1][A] u_test_gen/De_hcnt_1_s3/Q
1.860 0.575 tNET RR 1 R25C37[0][A] u_test_gen/n1245_s9/I1
2.376 0.516 tINS RR 2 R25C37[0][A] u_test_gen/n1245_s9/F
2.786 0.410 tNET RR 1 R26C38[0][B] u_test_gen/n1245_s8/I1
3.049 0.262 tINS RR 9 R26C38[0][B] u_test_gen/n1245_s8/F
3.412 0.364 tNET RR 1 R27C39[3][B] u_test_gen/n1245_s5/I1
3.702 0.290 tINS RF 16 R27C39[3][B] u_test_gen/n1245_s5/F
4.305 0.603 tNET FF 1 R24C37[3][B] u_test_gen/n1237_s1/I2
4.720 0.415 tINS FR 1 R24C37[3][B] u_test_gen/n1237_s1/F
4.720 0.000 tNET RR 1 R24C37[3][B] u_test_gen/Data_tmp_9_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.059 7.059 active clock edge time
7.059 0.000 pixel_clk
7.059 0.000 tCL RR 278 PLL_B u_pll/PLLA_inst/CLKOUT3
7.952 0.893 tNET RR 1 R24C37[3][B] u_test_gen/Data_tmp_9_s1/CLK
7.888 -0.064 tSu 1 R24C37[3][B] u_test_gen/Data_tmp_9_s1

Path Statistics:

Clock Skew -0.009
Setup Relationship 7.059
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay cell: 1.484, 38.867%; route: 1.951, 51.113%; tC2Q: 0.382, 10.020%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.893, 100.000%

Path10

Path Summary:

Slack 3.179
Data Arrival Time 4.692
Data Required Time 7.871
From vs_cnt_9_s0
To u_test_gen/Data_tmp_7_s1
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 278 PLL_B u_pll/PLLA_inst/CLKOUT3
0.901 0.901 tNET RR 1 R21C41[1][A] vs_cnt_9_s0/CLK
1.283 0.382 tC2Q RR 19 R21C41[1][A] vs_cnt_9_s0/Q
2.877 1.594 tNET RR 1 R24C35[1][A] u_test_gen/n1239_s4/I2
3.393 0.516 tINS RR 2 R24C35[1][A] u_test_gen/n1239_s4/F
4.176 0.783 tNET RR 1 R27C39[0][A] u_test_gen/n1239_s2/I1
4.692 0.516 tINS RR 1 R27C39[0][A] u_test_gen/n1239_s2/F
4.692 0.000 tNET RR 1 R27C39[0][A] u_test_gen/Data_tmp_7_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.059 7.059 active clock edge time
7.059 0.000 pixel_clk
7.059 0.000 tCL RR 278 PLL_B u_pll/PLLA_inst/CLKOUT3
7.935 0.876 tNET RR 1 R27C39[0][A] u_test_gen/Data_tmp_7_s1/CLK
7.871 -0.064 tSu 1 R27C39[0][A] u_test_gen/Data_tmp_7_s1

Path Statistics:

Clock Skew -0.024
Setup Relationship 7.059
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.901, 100.000%
Arrival Data Path Delay cell: 1.033, 27.232%; route: 2.377, 62.680%; tC2Q: 0.382, 10.088%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.876, 100.000%

Path11

Path Summary:

Slack 3.188
Data Arrival Time 4.691
Data Required Time 7.879
From u_test_gen/De_hcnt_1_s3
To u_test_gen/Data_tmp_11_s1
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 278 PLL_B u_pll/PLLA_inst/CLKOUT3
0.902 0.902 tNET RR 1 R24C40[1][A] u_test_gen/De_hcnt_1_s3/CLK
1.285 0.382 tC2Q RR 7 R24C40[1][A] u_test_gen/De_hcnt_1_s3/Q
1.860 0.575 tNET RR 1 R25C37[0][A] u_test_gen/n1245_s9/I1
2.376 0.516 tINS RR 2 R25C37[0][A] u_test_gen/n1245_s9/F
2.786 0.410 tNET RR 1 R26C38[0][B] u_test_gen/n1245_s8/I1
3.049 0.262 tINS RR 9 R26C38[0][B] u_test_gen/n1245_s8/F
3.412 0.364 tNET RR 1 R27C39[3][B] u_test_gen/n1245_s5/I1
3.702 0.290 tINS RF 16 R27C39[3][B] u_test_gen/n1245_s5/F
4.276 0.574 tNET FF 1 R24C38[3][A] u_test_gen/n1235_s1/I2
4.691 0.415 tINS FR 1 R24C38[3][A] u_test_gen/n1235_s1/F
4.691 0.000 tNET RR 1 R24C38[3][A] u_test_gen/Data_tmp_11_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.059 7.059 active clock edge time
7.059 0.000 pixel_clk
7.059 0.000 tCL RR 278 PLL_B u_pll/PLLA_inst/CLKOUT3
7.943 0.884 tNET RR 1 R24C38[3][A] u_test_gen/Data_tmp_11_s1/CLK
7.879 -0.064 tSu 1 R24C38[3][A] u_test_gen/Data_tmp_11_s1

Path Statistics:

Clock Skew -0.019
Setup Relationship 7.059
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay cell: 1.484, 39.162%; route: 1.923, 50.742%; tC2Q: 0.382, 10.096%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.884, 100.000%

Path12

Path Summary:

Slack 3.244
Data Arrival Time 4.644
Data Required Time 7.888
From u_test_gen/De_hcnt_1_s3
To u_test_gen/Data_tmp_0_s1
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 278 PLL_B u_pll/PLLA_inst/CLKOUT3
0.902 0.902 tNET RR 1 R24C40[1][A] u_test_gen/De_hcnt_1_s3/CLK
1.285 0.382 tC2Q RR 7 R24C40[1][A] u_test_gen/De_hcnt_1_s3/Q
1.860 0.575 tNET RR 1 R25C37[0][A] u_test_gen/n1245_s9/I1
2.376 0.516 tINS RR 2 R25C37[0][A] u_test_gen/n1245_s9/F
2.786 0.410 tNET RR 1 R26C38[0][B] u_test_gen/n1245_s8/I1
3.049 0.262 tINS RR 9 R26C38[0][B] u_test_gen/n1245_s8/F
3.412 0.364 tNET RR 1 R27C39[3][B] u_test_gen/n1245_s5/I1
3.702 0.290 tINS RF 16 R27C39[3][B] u_test_gen/n1245_s5/F
4.381 0.679 tNET FF 1 R24C35[0][B] u_test_gen/n1246_s1/I2
4.644 0.262 tINS FR 1 R24C35[0][B] u_test_gen/n1246_s1/F
4.644 0.000 tNET RR 1 R24C35[0][B] u_test_gen/Data_tmp_0_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.059 7.059 active clock edge time
7.059 0.000 pixel_clk
7.059 0.000 tCL RR 278 PLL_B u_pll/PLLA_inst/CLKOUT3
7.952 0.893 tNET RR 1 R24C35[0][B] u_test_gen/Data_tmp_0_s1/CLK
7.888 -0.064 tSu 1 R24C35[0][B] u_test_gen/Data_tmp_0_s1

Path Statistics:

Clock Skew -0.009
Setup Relationship 7.059
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay cell: 1.331, 35.583%; route: 2.027, 54.193%; tC2Q: 0.382, 10.224%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.893, 100.000%

Path13

Path Summary:

Slack 3.246
Data Arrival Time 4.635
Data Required Time 7.881
From u_test_gen/De_hcnt_1_s3
To u_test_gen/Data_tmp_2_s1
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 278 PLL_B u_pll/PLLA_inst/CLKOUT3
0.902 0.902 tNET RR 1 R24C40[1][A] u_test_gen/De_hcnt_1_s3/CLK
1.285 0.382 tC2Q RR 7 R24C40[1][A] u_test_gen/De_hcnt_1_s3/Q
1.860 0.575 tNET RR 1 R25C37[0][A] u_test_gen/n1245_s9/I1
2.376 0.516 tINS RR 2 R25C37[0][A] u_test_gen/n1245_s9/F
2.786 0.410 tNET RR 1 R26C38[0][B] u_test_gen/n1245_s8/I1
3.049 0.262 tINS RR 9 R26C38[0][B] u_test_gen/n1245_s8/F
3.412 0.364 tNET RR 1 R27C39[3][B] u_test_gen/n1245_s5/I1
3.702 0.290 tINS RF 16 R27C39[3][B] u_test_gen/n1245_s5/F
4.109 0.406 tNET FF 1 R27C36[0][B] u_test_gen/n1244_s1/I2
4.635 0.526 tINS FR 1 R27C36[0][B] u_test_gen/n1244_s1/F
4.635 0.000 tNET RR 1 R27C36[0][B] u_test_gen/Data_tmp_2_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.059 7.059 active clock edge time
7.059 0.000 pixel_clk
7.059 0.000 tCL RR 278 PLL_B u_pll/PLLA_inst/CLKOUT3
7.944 0.886 tNET RR 1 R27C36[0][B] u_test_gen/Data_tmp_2_s1/CLK
7.881 -0.064 tSu 1 R27C36[0][B] u_test_gen/Data_tmp_2_s1

Path Statistics:

Clock Skew -0.017
Setup Relationship 7.059
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay cell: 1.595, 42.733%; route: 1.755, 47.019%; tC2Q: 0.382, 10.248%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.886, 100.000%

Path14

Path Summary:

Slack 3.260
Data Arrival Time 4.640
Data Required Time 7.900
From u_test_gen/H_cnt_7_s0
To u_test_gen/V_cnt_0_s1
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 278 PLL_B u_pll/PLLA_inst/CLKOUT3
0.905 0.905 tNET RR 1 R23C40[1][A] u_test_gen/H_cnt_7_s0/CLK
1.287 0.382 tC2Q RR 7 R23C40[1][A] u_test_gen/H_cnt_7_s0/Q
1.847 0.560 tNET RR 1 R22C38[2][A] u_test_gen/V_cnt_10_s6/I0
2.374 0.526 tINS RR 1 R22C38[2][A] u_test_gen/V_cnt_10_s6/F
2.566 0.192 tNET RR 1 R22C38[3][A] u_test_gen/V_cnt_10_s3/I2
3.087 0.521 tINS RR 25 R22C38[3][A] u_test_gen/V_cnt_10_s3/F
3.487 0.400 tNET RR 1 R22C35[3][B] u_test_gen/n63_s4/I3
3.777 0.290 tINS RF 12 R22C35[3][B] u_test_gen/n63_s4/F
4.179 0.401 tNET FF 1 R23C36[0][A] u_test_gen/n74_s2/I1
4.640 0.461 tINS FR 1 R23C36[0][A] u_test_gen/n74_s2/F
4.640 0.000 tNET RR 1 R23C36[0][A] u_test_gen/V_cnt_0_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.059 7.059 active clock edge time
7.059 0.000 pixel_clk
7.059 0.000 tCL RR 278 PLL_B u_pll/PLLA_inst/CLKOUT3
7.964 0.905 tNET RR 1 R23C36[0][A] u_test_gen/V_cnt_0_s1/CLK
7.900 -0.064 tSu 1 R23C36[0][A] u_test_gen/V_cnt_0_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 7.059
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.905, 100.000%
Arrival Data Path Delay cell: 1.799, 48.159%; route: 1.554, 41.600%; tC2Q: 0.382, 10.241%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.905, 100.000%

Path15

Path Summary:

Slack 3.260
Data Arrival Time 4.640
Data Required Time 7.900
From u_test_gen/H_cnt_7_s0
To u_test_gen/V_cnt_1_s1
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 278 PLL_B u_pll/PLLA_inst/CLKOUT3
0.905 0.905 tNET RR 1 R23C40[1][A] u_test_gen/H_cnt_7_s0/CLK
1.287 0.382 tC2Q RR 7 R23C40[1][A] u_test_gen/H_cnt_7_s0/Q
1.847 0.560 tNET RR 1 R22C38[2][A] u_test_gen/V_cnt_10_s6/I0
2.374 0.526 tINS RR 1 R22C38[2][A] u_test_gen/V_cnt_10_s6/F
2.566 0.192 tNET RR 1 R22C38[3][A] u_test_gen/V_cnt_10_s3/I2
3.087 0.521 tINS RR 25 R22C38[3][A] u_test_gen/V_cnt_10_s3/F
3.487 0.400 tNET RR 1 R22C35[3][B] u_test_gen/n63_s4/I3
3.777 0.290 tINS RF 12 R22C35[3][B] u_test_gen/n63_s4/F
4.179 0.401 tNET FF 1 R23C36[0][B] u_test_gen/n73_s2/I0
4.640 0.461 tINS FR 1 R23C36[0][B] u_test_gen/n73_s2/F
4.640 0.000 tNET RR 1 R23C36[0][B] u_test_gen/V_cnt_1_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.059 7.059 active clock edge time
7.059 0.000 pixel_clk
7.059 0.000 tCL RR 278 PLL_B u_pll/PLLA_inst/CLKOUT3
7.964 0.905 tNET RR 1 R23C36[0][B] u_test_gen/V_cnt_1_s1/CLK
7.900 -0.064 tSu 1 R23C36[0][B] u_test_gen/V_cnt_1_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 7.059
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.905, 100.000%
Arrival Data Path Delay cell: 1.799, 48.159%; route: 1.554, 41.600%; tC2Q: 0.382, 10.241%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.905, 100.000%

Path16

Path Summary:

Slack 3.260
Data Arrival Time 4.640
Data Required Time 7.900
From u_test_gen/H_cnt_7_s0
To u_test_gen/V_cnt_4_s1
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 278 PLL_B u_pll/PLLA_inst/CLKOUT3
0.905 0.905 tNET RR 1 R23C40[1][A] u_test_gen/H_cnt_7_s0/CLK
1.287 0.382 tC2Q RR 7 R23C40[1][A] u_test_gen/H_cnt_7_s0/Q
1.847 0.560 tNET RR 1 R22C38[2][A] u_test_gen/V_cnt_10_s6/I0
2.374 0.526 tINS RR 1 R22C38[2][A] u_test_gen/V_cnt_10_s6/F
2.566 0.192 tNET RR 1 R22C38[3][A] u_test_gen/V_cnt_10_s3/I2
3.087 0.521 tINS RR 25 R22C38[3][A] u_test_gen/V_cnt_10_s3/F
3.487 0.400 tNET RR 1 R22C35[3][B] u_test_gen/n63_s4/I3
3.777 0.290 tINS RF 12 R22C35[3][B] u_test_gen/n63_s4/F
4.179 0.401 tNET FF 1 R23C36[1][A] u_test_gen/n70_s2/I0
4.640 0.461 tINS FR 1 R23C36[1][A] u_test_gen/n70_s2/F
4.640 0.000 tNET RR 1 R23C36[1][A] u_test_gen/V_cnt_4_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.059 7.059 active clock edge time
7.059 0.000 pixel_clk
7.059 0.000 tCL RR 278 PLL_B u_pll/PLLA_inst/CLKOUT3
7.964 0.905 tNET RR 1 R23C36[1][A] u_test_gen/V_cnt_4_s1/CLK
7.900 -0.064 tSu 1 R23C36[1][A] u_test_gen/V_cnt_4_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 7.059
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.905, 100.000%
Arrival Data Path Delay cell: 1.799, 48.159%; route: 1.554, 41.600%; tC2Q: 0.382, 10.241%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.905, 100.000%

Path17

Path Summary:

Slack 3.260
Data Arrival Time 4.640
Data Required Time 7.900
From u_test_gen/H_cnt_7_s0
To u_test_gen/V_cnt_5_s1
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 278 PLL_B u_pll/PLLA_inst/CLKOUT3
0.905 0.905 tNET RR 1 R23C40[1][A] u_test_gen/H_cnt_7_s0/CLK
1.287 0.382 tC2Q RR 7 R23C40[1][A] u_test_gen/H_cnt_7_s0/Q
1.847 0.560 tNET RR 1 R22C38[2][A] u_test_gen/V_cnt_10_s6/I0
2.374 0.526 tINS RR 1 R22C38[2][A] u_test_gen/V_cnt_10_s6/F
2.566 0.192 tNET RR 1 R22C38[3][A] u_test_gen/V_cnt_10_s3/I2
3.087 0.521 tINS RR 25 R22C38[3][A] u_test_gen/V_cnt_10_s3/F
3.487 0.400 tNET RR 1 R22C35[3][B] u_test_gen/n63_s4/I3
3.777 0.290 tINS RF 12 R22C35[3][B] u_test_gen/n63_s4/F
4.179 0.401 tNET FF 1 R23C36[1][B] u_test_gen/n69_s2/I2
4.640 0.461 tINS FR 1 R23C36[1][B] u_test_gen/n69_s2/F
4.640 0.000 tNET RR 1 R23C36[1][B] u_test_gen/V_cnt_5_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.059 7.059 active clock edge time
7.059 0.000 pixel_clk
7.059 0.000 tCL RR 278 PLL_B u_pll/PLLA_inst/CLKOUT3
7.964 0.905 tNET RR 1 R23C36[1][B] u_test_gen/V_cnt_5_s1/CLK
7.900 -0.064 tSu 1 R23C36[1][B] u_test_gen/V_cnt_5_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 7.059
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.905, 100.000%
Arrival Data Path Delay cell: 1.799, 48.159%; route: 1.554, 41.600%; tC2Q: 0.382, 10.241%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.905, 100.000%

Path18

Path Summary:

Slack 3.311
Data Arrival Time 4.589
Data Required Time 7.900
From u_test_gen/H_cnt_7_s0
To u_test_gen/V_cnt_2_s1
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 278 PLL_B u_pll/PLLA_inst/CLKOUT3
0.905 0.905 tNET RR 1 R23C40[1][A] u_test_gen/H_cnt_7_s0/CLK
1.287 0.382 tC2Q RR 7 R23C40[1][A] u_test_gen/H_cnt_7_s0/Q
1.847 0.560 tNET RR 1 R22C38[2][A] u_test_gen/V_cnt_10_s6/I0
2.374 0.526 tINS RR 1 R22C38[2][A] u_test_gen/V_cnt_10_s6/F
2.566 0.192 tNET RR 1 R22C38[3][A] u_test_gen/V_cnt_10_s3/I2
3.087 0.521 tINS RR 25 R22C38[3][A] u_test_gen/V_cnt_10_s3/F
3.487 0.400 tNET RR 1 R22C35[3][B] u_test_gen/n63_s4/I3
3.777 0.290 tINS RF 12 R22C35[3][B] u_test_gen/n63_s4/F
4.128 0.350 tNET FF 1 R23C36[2][B] u_test_gen/n72_s4/I0
4.589 0.461 tINS FR 1 R23C36[2][B] u_test_gen/n72_s4/F
4.589 0.000 tNET RR 1 R23C36[2][B] u_test_gen/V_cnt_2_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.059 7.059 active clock edge time
7.059 0.000 pixel_clk
7.059 0.000 tCL RR 278 PLL_B u_pll/PLLA_inst/CLKOUT3
7.964 0.905 tNET RR 1 R23C36[2][B] u_test_gen/V_cnt_2_s1/CLK
7.900 -0.064 tSu 1 R23C36[2][B] u_test_gen/V_cnt_2_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 7.059
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.905, 100.000%
Arrival Data Path Delay cell: 1.799, 48.829%; route: 1.503, 40.787%; tC2Q: 0.382, 10.383%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.905, 100.000%

Path19

Path Summary:

Slack 3.311
Data Arrival Time 4.589
Data Required Time 7.900
From u_test_gen/H_cnt_7_s0
To u_test_gen/V_cnt_6_s1
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 278 PLL_B u_pll/PLLA_inst/CLKOUT3
0.905 0.905 tNET RR 1 R23C40[1][A] u_test_gen/H_cnt_7_s0/CLK
1.287 0.382 tC2Q RR 7 R23C40[1][A] u_test_gen/H_cnt_7_s0/Q
1.847 0.560 tNET RR 1 R22C38[2][A] u_test_gen/V_cnt_10_s6/I0
2.374 0.526 tINS RR 1 R22C38[2][A] u_test_gen/V_cnt_10_s6/F
2.566 0.192 tNET RR 1 R22C38[3][A] u_test_gen/V_cnt_10_s3/I2
3.087 0.521 tINS RR 25 R22C38[3][A] u_test_gen/V_cnt_10_s3/F
3.487 0.400 tNET RR 1 R22C35[3][B] u_test_gen/n63_s4/I3
3.777 0.290 tINS RF 12 R22C35[3][B] u_test_gen/n63_s4/F
4.128 0.350 tNET FF 1 R23C36[2][A] u_test_gen/n68_s2/I2
4.589 0.461 tINS FR 1 R23C36[2][A] u_test_gen/n68_s2/F
4.589 0.000 tNET RR 1 R23C36[2][A] u_test_gen/V_cnt_6_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.059 7.059 active clock edge time
7.059 0.000 pixel_clk
7.059 0.000 tCL RR 278 PLL_B u_pll/PLLA_inst/CLKOUT3
7.964 0.905 tNET RR 1 R23C36[2][A] u_test_gen/V_cnt_6_s1/CLK
7.900 -0.064 tSu 1 R23C36[2][A] u_test_gen/V_cnt_6_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 7.059
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.905, 100.000%
Arrival Data Path Delay cell: 1.799, 48.829%; route: 1.503, 40.787%; tC2Q: 0.382, 10.383%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.905, 100.000%

Path20

Path Summary:

Slack 3.376
Data Arrival Time 4.526
Data Required Time 7.903
From u_test_gen/V_cnt_1_s1
To u_test_gen/V_cnt_11_s1
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 278 PLL_B u_pll/PLLA_inst/CLKOUT3
0.905 0.905 tNET RR 1 R23C36[0][B] u_test_gen/V_cnt_1_s1/CLK
1.287 0.382 tC2Q RR 5 R23C36[0][B] u_test_gen/V_cnt_1_s1/Q
2.168 0.880 tNET RR 1 R22C36[3][B] u_test_gen/n70_s3/I0
2.457 0.290 tINS RF 4 R22C36[3][B] u_test_gen/n70_s3/F
2.473 0.015 tNET FF 1 R22C36[1][A] u_test_gen/n67_s4/I1
2.999 0.526 tINS FR 4 R22C36[1][A] u_test_gen/n67_s4/F
3.334 0.335 tNET RR 1 R22C35[2][A] u_test_gen/n63_s9/I1
3.850 0.516 tINS RR 2 R22C35[2][A] u_test_gen/n63_s9/F
4.010 0.160 tNET RR 1 R22C36[1][B] u_test_gen/n63_s2/I1
4.526 0.516 tINS RR 1 R22C36[1][B] u_test_gen/n63_s2/F
4.526 0.000 tNET RR 1 R22C36[1][B] u_test_gen/V_cnt_11_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.059 7.059 active clock edge time
7.059 0.000 pixel_clk
7.059 0.000 tCL RR 278 PLL_B u_pll/PLLA_inst/CLKOUT3
7.966 0.908 tNET RR 1 R22C36[1][B] u_test_gen/V_cnt_11_s1/CLK
7.903 -0.064 tSu 1 R22C36[1][B] u_test_gen/V_cnt_11_s1

Path Statistics:

Clock Skew 0.003
Setup Relationship 7.059
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.905, 100.000%
Arrival Data Path Delay cell: 1.849, 51.053%; route: 1.390, 38.385%; tC2Q: 0.382, 10.563%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.908, 100.000%

Setup Analysis Report[2]:

Report Command:report_timing -setup -from_clock [get_clocks {byte_clk}] -max_paths 20 -max_common_paths 1

Path1

Path Summary:

Slack 1.386
Data Arrival Time 8.830
Data Required Time 10.217
From u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s
To u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_7_s1
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.869 0.869 tNET RR 18 BSRAM_R10[6] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/CLKB
3.129 2.260 tC2Q RF 2 BSRAM_R10[6] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14]
4.154 1.025 tNET FF 1 R14C20[1][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s3/I1
4.417 0.262 tINS FR 3 R14C20[1][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s3/F
4.424 0.008 tNET RR 1 R14C20[3][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s2/I0
4.945 0.521 tINS RR 11 R14C20[3][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s2/F
5.343 0.397 tNET RR 1 R16C19[0][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rFull_s4/I2
5.859 0.516 tINS RR 4 R16C19[0][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rFull_s4/F
6.237 0.377 tNET RR 1 R17C20[3][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n56_s2/I2
6.758 0.521 tINS RR 4 R17C20[3][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n56_s2/F
7.110 0.352 tNET RR 1 R16C22[3][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n51_s1/I3
7.525 0.415 tINS RR 4 R16C22[3][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n51_s1/F
7.690 0.165 tNET RR 1 R17C22[3][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n52_s1/I1
8.212 0.521 tINS RR 1 R17C22[3][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n52_s1/F
8.369 0.157 tNET RR 1 R18C22[1][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n52_s0/I0
8.830 0.461 tINS RR 1 R18C22[1][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n52_s0/F
8.830 0.000 tNET RR 1 R18C22[1][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_7_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9.412 9.412 active clock edge time
9.412 0.000 byte_clk
9.412 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
10.281 0.869 tNET RR 1 R18C22[1][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_7_s1/CLK
10.217 -0.064 tSu 1 R18C22[1][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_7_s1

Path Statistics:

Clock Skew -0.000
Setup Relationship 9.412
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.869, 100.000%
Arrival Data Path Delay cell: 3.219, 40.430%; route: 2.483, 31.182%; tC2Q: 2.260, 28.388%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.869, 100.000%

Path2

Path Summary:

Slack 1.697
Data Arrival Time 8.518
Data Required Time 10.215
From u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s
To u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rWrOffset_9_s1
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.869 0.869 tNET RR 18 BSRAM_R10[6] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/CLKB
3.129 2.260 tC2Q RF 2 BSRAM_R10[6] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14]
4.154 1.025 tNET FF 1 R14C20[1][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s3/I1
4.417 0.262 tINS FR 3 R14C20[1][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s3/F
4.424 0.008 tNET RR 1 R14C20[3][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s2/I0
4.945 0.521 tINS RR 11 R14C20[3][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s2/F
5.343 0.397 tNET RR 1 R16C19[0][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n58_s2/I0
5.859 0.516 tINS RR 4 R16C19[0][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n58_s2/F
6.239 0.380 tNET RR 1 R16C20[2][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n127_s1/I3
6.755 0.516 tINS RR 4 R16C20[2][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n127_s1/F
6.920 0.165 tNET RR 1 R16C21[1][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n124_s1/I3
7.437 0.516 tINS RR 4 R16C21[1][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n124_s1/F
7.792 0.355 tNET RR 1 R17C22[2][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n123_s1/I3
8.054 0.262 tINS RR 1 R17C22[2][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n123_s1/F
8.057 0.003 tNET RR 1 R17C22[1][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n123_s0/I0
8.518 0.461 tINS RR 1 R17C22[1][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n123_s0/F
8.518 0.000 tNET RR 1 R17C22[1][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rWrOffset_9_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9.412 9.412 active clock edge time
9.412 0.000 byte_clk
9.412 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
10.279 0.867 tNET RR 1 R17C22[1][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rWrOffset_9_s1/CLK
10.215 -0.064 tSu 1 R17C22[1][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rWrOffset_9_s1

Path Statistics:

Clock Skew -0.002
Setup Relationship 9.412
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.869, 100.000%
Arrival Data Path Delay cell: 3.056, 39.958%; route: 2.332, 30.495%; tC2Q: 2.260, 29.547%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.867, 100.000%

Path3

Path Summary:

Slack 1.816
Data Arrival Time 8.408
Data Required Time 10.224
From u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mBsram_mBsram_0_0_s
To u_dsi_tx/u_tx/u_dsi_tx/u_dphy/rCount_8_s1
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.878 0.878 tNET RR 9 BSRAM_R10[5] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mBsram_mBsram_0_0_s/CLKB
3.138 2.260 tC2Q RR 1 BSRAM_R10[5] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mBsram_mBsram_0_0_s/DO[2]
3.837 0.699 tNET RR 1 R11C20[3][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/wCBufQo_2_s/I0
4.102 0.265 tINS RR 3 R11C20[3][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/wCBufQo_2_s/F
4.830 0.728 tNET RR 1 R9C19[2][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/n115_s2/I1
5.291 0.461 tINS RR 4 R9C19[2][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/n115_s2/F
5.997 0.706 tNET RR 1 R11C18[3][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/n111_s4/I2
6.412 0.415 tINS RR 3 R11C18[3][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/n111_s4/F
6.417 0.005 tNET RR 1 R11C18[2][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/n111_s2/I2
6.878 0.461 tINS RR 2 R11C18[2][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/n111_s2/F
7.423 0.545 tNET RR 1 R9C18[3][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/n110_s1/I1
7.945 0.521 tINS RR 1 R9C18[3][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/n110_s1/F
7.947 0.003 tNET RR 1 R9C18[1][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/n110_s0/I0
8.408 0.461 tINS RR 1 R9C18[1][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/n110_s0/F
8.408 0.000 tNET RR 1 R9C18[1][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/rCount_8_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9.412 9.412 active clock edge time
9.412 0.000 byte_clk
9.412 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
10.288 0.876 tNET RR 1 R9C18[1][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/rCount_8_s1/CLK
10.224 -0.064 tSu 1 R9C18[1][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/rCount_8_s1

Path Statistics:

Clock Skew -0.002
Setup Relationship 9.412
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.878, 100.000%
Arrival Data Path Delay cell: 2.585, 34.329%; route: 2.685, 35.657%; tC2Q: 2.260, 30.013%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.876, 100.000%

Path4

Path Summary:

Slack 1.863
Data Arrival Time 8.350
Data Required Time 10.213
From u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s
To u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_10_s1
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.869 0.869 tNET RR 18 BSRAM_R10[6] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/CLKB
3.129 2.260 tC2Q RF 2 BSRAM_R10[6] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14]
4.154 1.025 tNET FF 1 R14C20[1][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s3/I1
4.417 0.262 tINS FR 3 R14C20[1][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s3/F
4.424 0.008 tNET RR 1 R14C20[3][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s2/I0
4.945 0.521 tINS RR 11 R14C20[3][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s2/F
5.515 0.570 tNET RR 1 R17C19[0][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n58_s1/I1
6.042 0.526 tINS RR 2 R17C19[0][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n58_s1/F
6.417 0.375 tNET RR 1 R17C22[3][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n56_s1/I3
6.707 0.290 tINS RF 4 R17C22[3][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n56_s1/F
6.864 0.157 tNET FF 1 R16C22[0][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n50_s3/I0
7.380 0.516 tINS FR 5 R16C22[0][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n50_s3/F
7.589 0.209 tNET RR 1 R16C20[3][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n50_s0/I0
7.879 0.290 tINS RF 2 R16C20[3][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n50_s0/F
7.889 0.010 tNET FF 1 R16C20[1][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n49_s0/I3
8.350 0.461 tINS FR 1 R16C20[1][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n49_s0/F
8.350 0.000 tNET RR 1 R16C20[1][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_10_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9.412 9.412 active clock edge time
9.412 0.000 byte_clk
9.412 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
10.277 0.865 tNET RR 1 R16C20[1][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_10_s1/CLK
10.213 -0.064 tSu 1 R16C20[1][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_10_s1

Path Statistics:

Clock Skew -0.004
Setup Relationship 9.412
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.869, 100.000%
Arrival Data Path Delay cell: 2.868, 38.329%; route: 2.354, 31.462%; tC2Q: 2.260, 30.209%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.865, 100.000%

Path5

Path Summary:

Slack 1.888
Data Arrival Time 8.325
Data Required Time 10.213
From u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s
To u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_8_s1
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.869 0.869 tNET RR 18 BSRAM_R10[6] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/CLKB
3.129 2.260 tC2Q RF 2 BSRAM_R10[6] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14]
4.154 1.025 tNET FF 1 R14C20[1][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s3/I1
4.417 0.262 tINS FR 3 R14C20[1][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s3/F
4.424 0.008 tNET RR 1 R14C20[3][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s2/I0
4.945 0.521 tINS RR 11 R14C20[3][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s2/F
5.515 0.570 tNET RR 1 R17C19[0][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n58_s1/I1
6.042 0.526 tINS RR 2 R17C19[0][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n58_s1/F
6.417 0.375 tNET RR 1 R17C22[3][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n56_s1/I3
6.707 0.290 tINS RF 4 R17C22[3][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n56_s1/F
6.864 0.157 tNET FF 1 R16C22[0][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n50_s3/I0
7.380 0.516 tINS FR 5 R16C22[0][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n50_s3/F
7.399 0.019 tNET RR 1 R16C22[2][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n51_s2/I0
7.662 0.262 tINS RR 1 R16C22[2][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n51_s2/F
7.799 0.137 tNET RR 1 R16C22[2][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n51_s0/I2
8.325 0.526 tINS RR 1 R16C22[2][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n51_s0/F
8.325 0.000 tNET RR 1 R16C22[2][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_8_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9.412 9.412 active clock edge time
9.412 0.000 byte_clk
9.412 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
10.277 0.865 tNET RR 1 R16C22[2][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_8_s1/CLK
10.213 -0.064 tSu 1 R16C22[2][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_8_s1

Path Statistics:

Clock Skew -0.004
Setup Relationship 9.412
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.869, 100.000%
Arrival Data Path Delay cell: 2.905, 38.961%; route: 2.291, 30.729%; tC2Q: 2.260, 30.310%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.865, 100.000%

Path6

Path Summary:

Slack 1.956
Data Arrival Time 8.257
Data Required Time 10.213
From u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s
To u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_9_s1
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.869 0.869 tNET RR 18 BSRAM_R10[6] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/CLKB
3.129 2.260 tC2Q RF 2 BSRAM_R10[6] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14]
4.154 1.025 tNET FF 1 R14C20[1][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s3/I1
4.417 0.262 tINS FR 3 R14C20[1][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s3/F
4.424 0.008 tNET RR 1 R14C20[3][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s2/I0
4.945 0.521 tINS RR 11 R14C20[3][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s2/F
5.515 0.570 tNET RR 1 R17C19[0][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n58_s1/I1
6.042 0.526 tINS RR 2 R17C19[0][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n58_s1/F
6.417 0.375 tNET RR 1 R17C22[3][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n56_s1/I3
6.707 0.290 tINS RF 4 R17C22[3][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n56_s1/F
6.864 0.157 tNET FF 1 R16C22[0][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n50_s3/I0
7.380 0.516 tINS FR 5 R16C22[0][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n50_s3/F
7.589 0.209 tNET RR 1 R16C20[3][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n50_s0/I0
7.854 0.265 tINS RR 2 R16C20[3][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n50_s0/F
8.257 0.402 tNET RR 1 R16C20[0][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_9_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9.412 9.412 active clock edge time
9.412 0.000 byte_clk
9.412 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
10.277 0.865 tNET RR 1 R16C20[0][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_9_s1/CLK
10.213 -0.064 tSu 1 R16C20[0][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_9_s1

Path Statistics:

Clock Skew -0.004
Setup Relationship 9.412
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.869, 100.000%
Arrival Data Path Delay cell: 2.381, 32.234%; route: 2.746, 37.174%; tC2Q: 2.260, 30.592%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.865, 100.000%

Path7

Path Summary:

Slack 1.962
Data Arrival Time 8.253
Data Required Time 10.215
From u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s
To u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rWrOffset_6_s1
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.869 0.869 tNET RR 18 BSRAM_R10[6] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/CLKB
3.129 2.260 tC2Q RF 2 BSRAM_R10[6] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14]
4.154 1.025 tNET FF 1 R14C20[1][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s3/I1
4.417 0.262 tINS FR 3 R14C20[1][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s3/F
4.424 0.008 tNET RR 1 R14C20[3][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s2/I0
4.945 0.521 tINS RR 11 R14C20[3][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s2/F
5.343 0.397 tNET RR 1 R16C19[0][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n58_s2/I0
5.859 0.516 tINS RR 4 R16C19[0][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n58_s2/F
6.239 0.380 tNET RR 1 R16C20[2][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n127_s1/I3
6.755 0.516 tINS RR 4 R16C20[2][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n127_s1/F
6.920 0.165 tNET RR 1 R16C21[1][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n124_s1/I3
7.437 0.516 tINS RR 4 R16C21[1][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n124_s1/F
7.792 0.355 tNET RR 1 R17C22[0][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n126_s0/I1
8.253 0.461 tINS RR 1 R17C22[0][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n126_s0/F
8.253 0.000 tNET RR 1 R17C22[0][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rWrOffset_6_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9.412 9.412 active clock edge time
9.412 0.000 byte_clk
9.412 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
10.279 0.867 tNET RR 1 R17C22[0][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rWrOffset_6_s1/CLK
10.215 -0.064 tSu 1 R17C22[0][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rWrOffset_6_s1

Path Statistics:

Clock Skew -0.002
Setup Relationship 9.412
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.869, 100.000%
Arrival Data Path Delay cell: 2.794, 37.836%; route: 2.330, 31.556%; tC2Q: 2.260, 30.608%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.867, 100.000%

Path8

Path Summary:

Slack 1.962
Data Arrival Time 8.253
Data Required Time 10.215
From u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s
To u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rWrOffset_7_s1
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.869 0.869 tNET RR 18 BSRAM_R10[6] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/CLKB
3.129 2.260 tC2Q RF 2 BSRAM_R10[6] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14]
4.154 1.025 tNET FF 1 R14C20[1][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s3/I1
4.417 0.262 tINS FR 3 R14C20[1][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s3/F
4.424 0.008 tNET RR 1 R14C20[3][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s2/I0
4.945 0.521 tINS RR 11 R14C20[3][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s2/F
5.343 0.397 tNET RR 1 R16C19[0][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n58_s2/I0
5.859 0.516 tINS RR 4 R16C19[0][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n58_s2/F
6.239 0.380 tNET RR 1 R16C20[2][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n127_s1/I3
6.755 0.516 tINS RR 4 R16C20[2][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n127_s1/F
6.920 0.165 tNET RR 1 R16C21[1][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n124_s1/I3
7.437 0.516 tINS RR 4 R16C21[1][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n124_s1/F
7.792 0.355 tNET RR 1 R17C22[0][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n125_s0/I1
8.253 0.461 tINS RR 1 R17C22[0][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n125_s0/F
8.253 0.000 tNET RR 1 R17C22[0][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rWrOffset_7_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9.412 9.412 active clock edge time
9.412 0.000 byte_clk
9.412 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
10.279 0.867 tNET RR 1 R17C22[0][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rWrOffset_7_s1/CLK
10.215 -0.064 tSu 1 R17C22[0][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rWrOffset_7_s1

Path Statistics:

Clock Skew -0.002
Setup Relationship 9.412
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.869, 100.000%
Arrival Data Path Delay cell: 2.794, 37.836%; route: 2.330, 31.556%; tC2Q: 2.260, 30.608%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.867, 100.000%

Path9

Path Summary:

Slack 1.962
Data Arrival Time 8.253
Data Required Time 10.215
From u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s
To u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rWrOffset_8_s1
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.869 0.869 tNET RR 18 BSRAM_R10[6] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/CLKB
3.129 2.260 tC2Q RF 2 BSRAM_R10[6] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14]
4.154 1.025 tNET FF 1 R14C20[1][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s3/I1
4.417 0.262 tINS FR 3 R14C20[1][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s3/F
4.424 0.008 tNET RR 1 R14C20[3][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s2/I0
4.945 0.521 tINS RR 11 R14C20[3][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s2/F
5.343 0.397 tNET RR 1 R16C19[0][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n58_s2/I0
5.859 0.516 tINS RR 4 R16C19[0][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n58_s2/F
6.239 0.380 tNET RR 1 R16C20[2][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n127_s1/I3
6.755 0.516 tINS RR 4 R16C20[2][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n127_s1/F
6.920 0.165 tNET RR 1 R16C21[1][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n124_s1/I3
7.437 0.516 tINS RR 4 R16C21[1][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n124_s1/F
7.792 0.355 tNET RR 1 R17C22[1][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n124_s0/I2
8.253 0.461 tINS RR 1 R17C22[1][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n124_s0/F
8.253 0.000 tNET RR 1 R17C22[1][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rWrOffset_8_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9.412 9.412 active clock edge time
9.412 0.000 byte_clk
9.412 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
10.279 0.867 tNET RR 1 R17C22[1][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rWrOffset_8_s1/CLK
10.215 -0.064 tSu 1 R17C22[1][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rWrOffset_8_s1

Path Statistics:

Clock Skew -0.002
Setup Relationship 9.412
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.869, 100.000%
Arrival Data Path Delay cell: 2.794, 37.836%; route: 2.330, 31.556%; tC2Q: 2.260, 30.608%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.867, 100.000%

Path10

Path Summary:

Slack 2.159
Data Arrival Time 8.054
Data Required Time 10.213
From u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s
To u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_4_s1
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.869 0.869 tNET RR 18 BSRAM_R10[6] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/CLKB
3.129 2.260 tC2Q RF 2 BSRAM_R10[6] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14]
4.154 1.025 tNET FF 1 R14C20[1][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s3/I1
4.417 0.262 tINS FR 3 R14C20[1][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s3/F
4.424 0.008 tNET RR 1 R14C20[3][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s2/I0
4.945 0.521 tINS RR 11 R14C20[3][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s2/F
5.343 0.397 tNET RR 1 R16C19[0][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rFull_s4/I2
5.859 0.516 tINS RR 4 R16C19[0][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rFull_s4/F
6.237 0.377 tNET RR 1 R17C20[3][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n56_s2/I2
6.758 0.521 tINS RR 4 R17C20[3][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n56_s2/F
7.110 0.352 tNET RR 1 R16C22[3][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n55_s1/I1
7.525 0.415 tINS RR 1 R16C22[3][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n55_s1/F
7.528 0.003 tNET RR 1 R16C22[0][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n55_s0/I0
8.054 0.526 tINS RR 1 R16C22[0][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n55_s0/F
8.054 0.000 tNET RR 1 R16C22[0][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_4_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9.412 9.412 active clock edge time
9.412 0.000 byte_clk
9.412 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
10.277 0.865 tNET RR 1 R16C22[0][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_4_s1/CLK
10.213 -0.064 tSu 1 R16C22[0][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_4_s1

Path Statistics:

Clock Skew -0.004
Setup Relationship 9.412
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.869, 100.000%
Arrival Data Path Delay cell: 2.762, 38.448%; route: 2.163, 30.097%; tC2Q: 2.260, 31.454%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.865, 100.000%

Path11

Path Summary:

Slack 2.216
Data Arrival Time 7.997
Data Required Time 10.213
From u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s
To u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_5_s1
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.869 0.869 tNET RR 18 BSRAM_R10[6] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/CLKB
3.129 2.260 tC2Q RF 2 BSRAM_R10[6] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14]
4.154 1.025 tNET FF 1 R14C20[1][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s3/I1
4.417 0.262 tINS FR 3 R14C20[1][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s3/F
4.424 0.008 tNET RR 1 R14C20[3][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s2/I0
4.945 0.521 tINS RR 11 R14C20[3][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s2/F
5.343 0.397 tNET RR 1 R16C19[0][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rFull_s4/I2
5.859 0.516 tINS RR 4 R16C19[0][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rFull_s4/F
6.237 0.377 tNET RR 1 R17C20[3][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n56_s2/I2
6.758 0.521 tINS RR 4 R17C20[3][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n56_s2/F
7.110 0.352 tNET RR 1 R16C22[3][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n51_s1/I3
7.525 0.415 tINS RR 4 R16C22[3][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n51_s1/F
7.535 0.010 tNET RR 1 R16C22[1][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n54_s0/I1
7.997 0.461 tINS RR 1 R16C22[1][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n54_s0/F
7.997 0.000 tNET RR 1 R16C22[1][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_5_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9.412 9.412 active clock edge time
9.412 0.000 byte_clk
9.412 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
10.277 0.865 tNET RR 1 R16C22[1][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_5_s1/CLK
10.213 -0.064 tSu 1 R16C22[1][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_5_s1

Path Statistics:

Clock Skew -0.004
Setup Relationship 9.412
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.869, 100.000%
Arrival Data Path Delay cell: 2.697, 37.846%; route: 2.170, 30.445%; tC2Q: 2.260, 31.708%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.865, 100.000%

Path12

Path Summary:

Slack 2.216
Data Arrival Time 7.997
Data Required Time 10.213
From u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s
To u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_6_s1
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.869 0.869 tNET RR 18 BSRAM_R10[6] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/CLKB
3.129 2.260 tC2Q RF 2 BSRAM_R10[6] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14]
4.154 1.025 tNET FF 1 R14C20[1][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s3/I1
4.417 0.262 tINS FR 3 R14C20[1][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s3/F
4.424 0.008 tNET RR 1 R14C20[3][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s2/I0
4.945 0.521 tINS RR 11 R14C20[3][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s2/F
5.343 0.397 tNET RR 1 R16C19[0][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rFull_s4/I2
5.859 0.516 tINS RR 4 R16C19[0][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rFull_s4/F
6.237 0.377 tNET RR 1 R17C20[3][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n56_s2/I2
6.758 0.521 tINS RR 4 R17C20[3][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n56_s2/F
7.110 0.352 tNET RR 1 R16C22[3][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n51_s1/I3
7.525 0.415 tINS RR 4 R16C22[3][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n51_s1/F
7.535 0.010 tNET RR 1 R16C22[1][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n53_s0/I0
7.997 0.461 tINS RR 1 R16C22[1][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n53_s0/F
7.997 0.000 tNET RR 1 R16C22[1][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_6_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9.412 9.412 active clock edge time
9.412 0.000 byte_clk
9.412 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
10.277 0.865 tNET RR 1 R16C22[1][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_6_s1/CLK
10.213 -0.064 tSu 1 R16C22[1][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rCnt_6_s1

Path Statistics:

Clock Skew -0.004
Setup Relationship 9.412
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.869, 100.000%
Arrival Data Path Delay cell: 2.697, 37.846%; route: 2.170, 30.445%; tC2Q: 2.260, 31.708%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.865, 100.000%

Path13

Path Summary:

Slack 2.275
Data Arrival Time 7.950
Data Required Time 10.224
From u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mBsram_mBsram_0_0_s
To u_dsi_tx/u_tx/u_dsi_tx/u_dphy/rCount_7_s1
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.878 0.878 tNET RR 9 BSRAM_R10[5] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mBsram_mBsram_0_0_s/CLKB
3.138 2.260 tC2Q RR 1 BSRAM_R10[5] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mBsram_mBsram_0_0_s/DO[2]
3.837 0.699 tNET RR 1 R11C20[3][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/wCBufQo_2_s/I0
4.102 0.265 tINS RR 3 R11C20[3][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/wCBufQo_2_s/F
4.830 0.728 tNET RR 1 R9C19[2][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/n115_s2/I1
5.291 0.461 tINS RR 4 R9C19[2][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/n115_s2/F
5.997 0.706 tNET RR 1 R11C18[3][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/n111_s4/I2
6.412 0.415 tINS RR 3 R11C18[3][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/n111_s4/F
6.417 0.005 tNET RR 1 R11C18[2][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/n111_s2/I2
6.878 0.461 tINS RR 2 R11C18[2][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/n111_s2/F
7.423 0.545 tNET RR 1 R9C18[0][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/n111_s0/I2
7.950 0.526 tINS RR 1 R9C18[0][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/n111_s0/F
7.950 0.000 tNET RR 1 R9C18[0][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/rCount_7_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9.412 9.412 active clock edge time
9.412 0.000 byte_clk
9.412 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
10.288 0.876 tNET RR 1 R9C18[0][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/rCount_7_s1/CLK
10.224 -0.064 tSu 1 R9C18[0][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/rCount_7_s1

Path Statistics:

Clock Skew -0.002
Setup Relationship 9.412
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.878, 100.000%
Arrival Data Path Delay cell: 2.129, 30.104%; route: 2.683, 37.935%; tC2Q: 2.260, 31.960%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.876, 100.000%

Path14

Path Summary:

Slack 2.292
Data Arrival Time 7.901
Data Required Time 10.193
From u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mBsram_mBsram_0_0_s
To u_dsi_tx/u_tx/u_dsi_tx/u_dphy/rCount_5_s1
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.878 0.878 tNET RR 9 BSRAM_R10[5] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mBsram_mBsram_0_0_s/CLKB
3.138 2.260 tC2Q RR 1 BSRAM_R10[5] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mBsram_mBsram_0_0_s/DO[2]
3.837 0.699 tNET RR 1 R11C20[3][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/wCBufQo_2_s/I0
4.102 0.265 tINS RR 3 R11C20[3][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/wCBufQo_2_s/F
4.830 0.728 tNET RR 1 R9C19[2][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/n115_s2/I1
5.291 0.461 tINS RR 4 R9C19[2][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/n115_s2/F
5.997 0.706 tNET RR 1 R11C18[3][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/n111_s4/I2
6.412 0.415 tINS RR 3 R11C18[3][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/n111_s4/F
6.691 0.279 tNET RR 1 R11C18[1][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/n113_s1/I1
7.217 0.526 tINS RR 1 R11C18[1][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/n113_s1/F
7.375 0.157 tNET RR 1 R12C18[2][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/n113_s0/I0
7.901 0.526 tINS RR 1 R12C18[2][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/n113_s0/F
7.901 0.000 tNET RR 1 R12C18[2][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/rCount_5_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9.412 9.412 active clock edge time
9.412 0.000 byte_clk
9.412 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
10.257 0.845 tNET RR 1 R12C18[2][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/rCount_5_s1/CLK
10.193 -0.064 tSu 1 R12C18[2][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/rCount_5_s1

Path Statistics:

Clock Skew -0.033
Setup Relationship 9.412
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.878, 100.000%
Arrival Data Path Delay cell: 2.194, 31.239%; route: 2.569, 36.579%; tC2Q: 2.260, 32.182%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.845, 100.000%

Path15

Path Summary:

Slack 2.292
Data Arrival Time 7.901
Data Required Time 10.193
From u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mBsram_mBsram_0_0_s
To u_dsi_tx/u_tx/u_dsi_tx/u_dphy/rCount_6_s1
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.878 0.878 tNET RR 9 BSRAM_R10[5] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mBsram_mBsram_0_0_s/CLKB
3.138 2.260 tC2Q RR 1 BSRAM_R10[5] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mBsram_mBsram_0_0_s/DO[2]
3.837 0.699 tNET RR 1 R11C20[3][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/wCBufQo_2_s/I0
4.102 0.265 tINS RR 3 R11C20[3][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/wCBufQo_2_s/F
4.830 0.728 tNET RR 1 R9C19[2][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/n115_s2/I1
5.291 0.461 tINS RR 4 R9C19[2][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/n115_s2/F
5.997 0.706 tNET RR 1 R11C18[3][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/n111_s4/I2
6.412 0.415 tINS RR 3 R11C18[3][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/n111_s4/F
6.691 0.279 tNET RR 1 R11C18[1][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/n112_s1/I1
7.217 0.526 tINS RR 1 R11C18[1][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/n112_s1/F
7.375 0.157 tNET RR 1 R12C18[1][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/n112_s0/I0
7.901 0.526 tINS RR 1 R12C18[1][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/n112_s0/F
7.901 0.000 tNET RR 1 R12C18[1][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/rCount_6_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9.412 9.412 active clock edge time
9.412 0.000 byte_clk
9.412 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
10.257 0.845 tNET RR 1 R12C18[1][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/rCount_6_s1/CLK
10.193 -0.064 tSu 1 R12C18[1][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/rCount_6_s1

Path Statistics:

Clock Skew -0.033
Setup Relationship 9.412
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.878, 100.000%
Arrival Data Path Delay cell: 2.194, 31.239%; route: 2.569, 36.579%; tC2Q: 2.260, 32.182%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.845, 100.000%

Path16

Path Summary:

Slack 2.307
Data Arrival Time 7.877
Data Required Time 10.184
From u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mBsram_mBsram_0_0_s
To u_dsi_tx/u_tx/u_dsi_tx/u_dphy/rCount_10_s1
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.878 0.878 tNET RR 9 BSRAM_R10[5] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mBsram_mBsram_0_0_s/CLKB
3.138 2.260 tC2Q RR 1 BSRAM_R10[5] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mBsram_mBsram_0_0_s/DO[2]
3.837 0.699 tNET RR 1 R11C20[3][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/wCBufQo_2_s/I0
4.102 0.265 tINS RR 3 R11C20[3][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/wCBufQo_2_s/F
4.830 0.728 tNET RR 1 R9C19[2][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/n115_s2/I1
5.291 0.461 tINS RR 4 R9C19[2][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/n115_s2/F
5.840 0.549 tNET RR 1 R11C19[3][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/n107_s4/I2
6.361 0.521 tINS RR 3 R11C19[3][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/n107_s4/F
6.501 0.140 tNET RR 1 R11C19[0][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/n108_s1/I1
6.763 0.262 tINS RR 1 R11C19[0][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/n108_s1/F
7.351 0.588 tNET RR 1 R12C19[2][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/n108_s0/I0
7.877 0.526 tINS RR 1 R12C19[2][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/n108_s0/F
7.877 0.000 tNET RR 1 R12C19[2][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/rCount_10_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9.412 9.412 active clock edge time
9.412 0.000 byte_clk
9.412 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
10.248 0.836 tNET RR 1 R12C19[2][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/rCount_10_s1/CLK
10.184 -0.064 tSu 1 R12C19[2][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/rCount_10_s1

Path Statistics:

Clock Skew -0.043
Setup Relationship 9.412
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.878, 100.000%
Arrival Data Path Delay cell: 2.036, 29.094%; route: 2.702, 38.614%; tC2Q: 2.260, 32.291%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.836, 100.000%

Path17

Path Summary:

Slack 2.311
Data Arrival Time 7.890
Data Required Time 10.201
From u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mBsram_mBsram_0_0_s
To u_dsi_tx/u_tx/u_dsi_tx/u_dphy/rCount_11_s1
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.878 0.878 tNET RR 9 BSRAM_R10[5] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mBsram_mBsram_0_0_s/CLKB
3.138 2.260 tC2Q RR 1 BSRAM_R10[5] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mBsram_mBsram_0_0_s/DO[2]
3.837 0.699 tNET RR 1 R11C20[3][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/wCBufQo_2_s/I0
4.102 0.265 tINS RR 3 R11C20[3][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/wCBufQo_2_s/F
4.830 0.728 tNET RR 1 R9C19[2][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/n115_s2/I1
5.291 0.461 tINS RR 4 R9C19[2][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/n115_s2/F
5.840 0.549 tNET RR 1 R11C19[3][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/n107_s4/I2
6.361 0.521 tINS RR 3 R11C19[3][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/n107_s4/F
6.523 0.162 tNET RR 1 R11C18[3][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/n107_s1/I2
7.021 0.498 tINS RR 1 R11C18[3][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/n107_s1/F
7.373 0.352 tNET RR 1 R11C19[0][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/n107_s0/I0
7.890 0.516 tINS RR 1 R11C19[0][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/n107_s0/F
7.890 0.000 tNET RR 1 R11C19[0][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/rCount_11_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9.412 9.412 active clock edge time
9.412 0.000 byte_clk
9.412 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
10.264 0.852 tNET RR 1 R11C19[0][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/rCount_11_s1/CLK
10.201 -0.064 tSu 1 R11C19[0][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/rCount_11_s1

Path Statistics:

Clock Skew -0.026
Setup Relationship 9.412
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.878, 100.000%
Arrival Data Path Delay cell: 2.261, 32.252%; route: 2.490, 35.514%; tC2Q: 2.260, 32.234%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.852, 100.000%

Path18

Path Summary:

Slack 2.395
Data Arrival Time 7.820
Data Required Time 10.215
From u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s
To u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rRdOffset_8_s1
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.869 0.869 tNET RR 18 BSRAM_R10[6] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/CLKB
3.129 2.260 tC2Q RF 2 BSRAM_R10[6] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14]
4.154 1.025 tNET FF 1 R14C20[1][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s3/I1
4.417 0.262 tINS FR 3 R14C20[1][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s3/F
4.424 0.008 tNET RR 1 R14C20[3][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s2/I0
4.945 0.521 tINS RR 11 R14C20[3][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/wDataRd_s2/F
5.145 0.200 tNET RR 1 R16C20[1][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n167_s2/I3
5.607 0.461 tINS RR 4 R16C20[1][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n167_s2/F
6.152 0.545 tNET RR 1 R16C21[0][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n164_s1/I3
6.668 0.516 tINS RR 4 R16C21[0][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n164_s1/F
6.673 0.005 tNET RR 1 R16C21[3][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n162_s1/I3
6.963 0.290 tINS RF 2 R16C21[3][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n162_s1/F
7.294 0.331 tNET FF 1 R17C20[2][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n163_s0/I0
7.820 0.526 tINS FR 1 R17C20[2][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/n163_s0/F
7.820 0.000 tNET RR 1 R17C20[2][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rRdOffset_8_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9.412 9.412 active clock edge time
9.412 0.000 byte_clk
9.412 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
10.279 0.867 tNET RR 1 R17C20[2][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rRdOffset_8_s1/CLK
10.215 -0.064 tSu 1 R17C20[2][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/rRdOffset_8_s1

Path Statistics:

Clock Skew -0.002
Setup Relationship 9.412
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.869, 100.000%
Arrival Data Path Delay cell: 2.577, 37.080%; route: 2.114, 30.408%; tC2Q: 2.260, 32.512%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.867, 100.000%

Path19

Path Summary:

Slack 2.401
Data Arrival Time 7.760
Data Required Time 10.162
From u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s
To u_tx_phy/DPHY_TX_INST/u_oserx4x8/U5_OSER83
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.869 0.869 tNET RR 18 BSRAM_R10[6] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/CLKB
3.129 2.260 tC2Q RF 2 BSRAM_R10[6] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/mBsram_mBsram_0_1_s/DO[14]
4.154 1.025 tNET FF 1 R14C20[3][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA3_d_7_s0/I1
4.444 0.290 tINS FF 33 R14C20[3][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA3_d_7_s0/F
4.858 0.414 tNET FF 1 R13C22[3][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA3_d_5_s/I2
5.379 0.521 tINS FR 2 R13C22[3][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/O_HS_DATA3_d_5_s/F
6.498 1.119 tNET RR 1 R8C19[3][B] u_tx_phy/DPHY_TX_INST/u_oserx4x8/lane3_d5_s0/I0
7.019 0.521 tINS RR 2 R8C19[3][B] u_tx_phy/DPHY_TX_INST/u_oserx4x8/lane3_d5_s0/F
7.760 0.741 tNET RR 1 IOT13[A] u_tx_phy/DPHY_TX_INST/u_oserx4x8/U5_OSER83/D5

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9.412 9.412 active clock edge time
9.412 0.000 byte_clk
9.412 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
10.327 0.915 tNET RR 1 IOT13[A] u_tx_phy/DPHY_TX_INST/u_oserx4x8/U5_OSER83/PCLK
10.162 -0.165 tSu 1 IOT13[A] u_tx_phy/DPHY_TX_INST/u_oserx4x8/U5_OSER83

Path Statistics:

Clock Skew 0.046
Setup Relationship 9.412
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.869, 100.000%
Arrival Data Path Delay cell: 1.332, 19.336%; route: 3.299, 47.869%; tC2Q: 2.260, 32.795%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.915, 100.000%

Path20

Path Summary:

Slack 2.456
Data Arrival Time 7.764
Data Required Time 10.219
From u_dsi_tx/u_tx/u_dsi_tx/rRemainder_3_s0
To u_dsi_tx/u_tx/u_dsi_tx/rRegData_112_s1
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.881 0.881 tNET RR 1 R25C31[0][A] u_dsi_tx/u_tx/u_dsi_tx/rRemainder_3_s0/CLK
1.264 0.382 tC2Q RR 6 R25C31[0][A] u_dsi_tx/u_tx/u_dsi_tx/rRemainder_3_s0/Q
1.846 0.582 tNET RR 1 R24C28[1][B] u_dsi_tx/u_tx/u_dsi_tx/n3126_s7/I2
2.307 0.461 tINS RR 99 R24C28[1][B] u_dsi_tx/u_tx/u_dsi_tx/n3126_s7/F
3.773 1.465 tNET RR 1 R16C25[2][A] u_dsi_tx/u_tx/u_dsi_tx/n3126_s6/I0
4.035 0.262 tINS RR 94 R16C25[2][A] u_dsi_tx/u_tx/u_dsi_tx/n3126_s6/F
5.856 1.821 tNET RR 1 R22C23[2][A] u_dsi_tx/u_tx/u_dsi_tx/n3139_s4/S0
6.109 0.252 tINS RR 1 R22C23[2][A] u_dsi_tx/u_tx/u_dsi_tx/n3139_s4/O
7.237 1.129 tNET RR 1 R29C21[1][A] u_dsi_tx/u_tx/u_dsi_tx/n3395_s2/I1
7.764 0.526 tINS RR 1 R29C21[1][A] u_dsi_tx/u_tx/u_dsi_tx/n3395_s2/F
7.764 0.000 tNET RR 1 R29C21[1][A] u_dsi_tx/u_tx/u_dsi_tx/rRegData_112_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9.412 9.412 active clock edge time
9.412 0.000 byte_clk
9.412 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
10.283 0.871 tNET RR 1 R29C21[1][A] u_dsi_tx/u_tx/u_dsi_tx/rRegData_112_s1/CLK
10.219 -0.064 tSu 1 R29C21[1][A] u_dsi_tx/u_tx/u_dsi_tx/rRegData_112_s1

Path Statistics:

Clock Skew -0.010
Setup Relationship 9.412
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.881, 100.000%
Arrival Data Path Delay cell: 1.503, 21.831%; route: 4.997, 72.612%; tC2Q: 0.382, 5.558%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.871, 100.000%

Hold Analysis Report

Hold Analysis Report[1]:

Report Command:report_timing -hold -from_clock [get_clocks {pixel_clk}] -max_paths 20 -max_common_paths 1

Path1

Path Summary:

Slack 0.199
Data Arrival Time 0.686
Data Required Time 0.487
From u_p2b/u_p2b_0/u_mid_buf/rWPtrBin_5_s0
To u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 278 PLL_B u_pll/PLLA_inst/CLKOUT3
0.375 0.375 tNET RR 1 R9C35[0][B] u_p2b/u_p2b_0/u_mid_buf/rWPtrBin_5_s0/CLK
0.555 0.180 tC2Q RR 5 R9C35[0][B] u_p2b/u_p2b_0/u_mid_buf/rWPtrBin_5_s0/Q
0.686 0.131 tNET RR 1 BSRAM_R10[10] u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s/ADA[10]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 278 PLL_B u_pll/PLLA_inst/CLKOUT3
0.369 0.369 tNET RR 1 BSRAM_R10[10] u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s/CLKA
0.487 0.118 tHld 1 BSRAM_R10[10] u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s

Path Statistics:

Clock Skew -0.006
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.131, 42.169%; tC2Q: 0.180, 57.831%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.369, 100.000%

Path2

Path Summary:

Slack 0.277
Data Arrival Time 0.895
Data Required Time 0.618
From u_p2b/u_p2b_0/mid_data_27_s1
To u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 278 PLL_B u_pll/PLLA_inst/CLKOUT3
0.361 0.361 tNET RR 1 R14C35[0][B] u_p2b/u_p2b_0/mid_data_27_s1/CLK
0.541 0.180 tC2Q RR 1 R14C35[0][B] u_p2b/u_p2b_0/mid_data_27_s1/Q
0.895 0.354 tNET RR 1 BSRAM_R10[10] u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s/DI[27]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 278 PLL_B u_pll/PLLA_inst/CLKOUT3
0.369 0.369 tNET RR 1 BSRAM_R10[10] u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s/CLKA
0.618 0.249 tHld 1 BSRAM_R10[10] u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s

Path Statistics:

Clock Skew 0.008
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.361, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.354, 66.276%; tC2Q: 0.180, 33.724%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.369, 100.000%

Path3

Path Summary:

Slack 0.277
Data Arrival Time 0.895
Data Required Time 0.618
From u_p2b/u_p2b_0/mid_data_19_s1
To u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 278 PLL_B u_pll/PLLA_inst/CLKOUT3
0.361 0.361 tNET RR 1 R14C35[0][A] u_p2b/u_p2b_0/mid_data_19_s1/CLK
0.541 0.180 tC2Q RR 1 R14C35[0][A] u_p2b/u_p2b_0/mid_data_19_s1/Q
0.895 0.354 tNET RR 1 BSRAM_R10[10] u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s/DI[19]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 278 PLL_B u_pll/PLLA_inst/CLKOUT3
0.369 0.369 tNET RR 1 BSRAM_R10[10] u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s/CLKA
0.618 0.249 tHld 1 BSRAM_R10[10] u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s

Path Statistics:

Clock Skew 0.008
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.361, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.354, 66.276%; tC2Q: 0.180, 33.724%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.369, 100.000%

Path4

Path Summary:

Slack 0.290
Data Arrival Time 0.907
Data Required Time 0.618
From u_p2b/u_p2b_0/mid_data_26_s1
To u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 278 PLL_B u_pll/PLLA_inst/CLKOUT3
0.361 0.361 tNET RR 1 R14C39[0][B] u_p2b/u_p2b_0/mid_data_26_s1/CLK
0.541 0.180 tC2Q RR 1 R14C39[0][B] u_p2b/u_p2b_0/mid_data_26_s1/Q
0.907 0.366 tNET RR 1 BSRAM_R10[10] u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s/DI[26]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 278 PLL_B u_pll/PLLA_inst/CLKOUT3
0.369 0.369 tNET RR 1 BSRAM_R10[10] u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s/CLKA
0.618 0.249 tHld 1 BSRAM_R10[10] u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s

Path Statistics:

Clock Skew 0.008
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.361, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.366, 67.048%; tC2Q: 0.180, 32.952%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.369, 100.000%

Path5

Path Summary:

Slack 0.374
Data Arrival Time 0.771
Data Required Time 0.398
From frame_led_s2
To frame_led_s2
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 278 PLL_B u_pll/PLLA_inst/CLKOUT3
0.396 0.396 tNET RR 1 R21C39[1][A] frame_led_s2/CLK
0.572 0.176 tC2Q RF 2 R21C39[1][A] frame_led_s2/Q
0.580 0.008 tNET FF 1 R21C39[1][A] n203_s3/I0
0.771 0.191 tINS FF 1 R21C39[1][A] n203_s3/F
0.771 0.000 tNET FF 1 R21C39[1][A] frame_led_s2/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 278 PLL_B u_pll/PLLA_inst/CLKOUT3
0.396 0.396 tNET RR 1 R21C39[1][A] frame_led_s2/CLK
0.398 0.001 tHld 1 R21C39[1][A] frame_led_s2

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.396, 100.000%
Arrival Data Path Delay cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.396, 100.000%

Path6

Path Summary:

Slack 0.374
Data Arrival Time 0.741
Data Required Time 0.368
From u_p2b/u_p2b_0/loop_cnt_0_s0
To u_p2b/u_p2b_0/loop_cnt_0_s0
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 278 PLL_B u_pll/PLLA_inst/CLKOUT3
0.366 0.366 tNET RR 1 R15C37[0][A] u_p2b/u_p2b_0/loop_cnt_0_s0/CLK
0.543 0.176 tC2Q RF 3 R15C37[0][A] u_p2b/u_p2b_0/loop_cnt_0_s0/Q
0.550 0.008 tNET FF 1 R15C37[0][A] u_p2b/u_p2b_0/n81_s3/I0
0.741 0.191 tINS FF 1 R15C37[0][A] u_p2b/u_p2b_0/n81_s3/F
0.741 0.000 tNET FF 1 R15C37[0][A] u_p2b/u_p2b_0/loop_cnt_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 278 PLL_B u_pll/PLLA_inst/CLKOUT3
0.366 0.366 tNET RR 1 R15C37[0][A] u_p2b/u_p2b_0/loop_cnt_0_s0/CLK
0.368 0.001 tHld 1 R15C37[0][A] u_p2b/u_p2b_0/loop_cnt_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.366, 100.000%
Arrival Data Path Delay cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.366, 100.000%

Path7

Path Summary:

Slack 0.376
Data Arrival Time 0.994
Data Required Time 0.618
From u_p2b/u_p2b_0/mid_data_3_s1
To u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 278 PLL_B u_pll/PLLA_inst/CLKOUT3
0.366 0.366 tNET RR 1 R14C36[0][A] u_p2b/u_p2b_0/mid_data_3_s1/CLK
0.546 0.180 tC2Q RR 1 R14C36[0][A] u_p2b/u_p2b_0/mid_data_3_s1/Q
0.994 0.447 tNET RR 1 BSRAM_R10[10] u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s/DI[3]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 278 PLL_B u_pll/PLLA_inst/CLKOUT3
0.369 0.369 tNET RR 1 BSRAM_R10[10] u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s/CLKA
0.618 0.249 tHld 1 BSRAM_R10[10] u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s

Path Statistics:

Clock Skew 0.002
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.366, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.447, 71.315%; tC2Q: 0.180, 28.685%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.369, 100.000%

Path8

Path Summary:

Slack 0.378
Data Arrival Time 0.778
Data Required Time 0.400
From u_test_gen/H_cnt_2_s0
To u_test_gen/H_cnt_2_s0
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 278 PLL_B u_pll/PLLA_inst/CLKOUT3
0.399 0.399 tNET RR 1 R22C40[0][A] u_test_gen/H_cnt_2_s0/CLK
0.575 0.176 tC2Q RF 5 R22C40[0][A] u_test_gen/H_cnt_2_s0/Q
0.587 0.011 tNET FF 1 R22C40[0][A] u_test_gen/n138_s4/I1
0.778 0.191 tINS FF 1 R22C40[0][A] u_test_gen/n138_s4/F
0.778 0.000 tNET FF 1 R22C40[0][A] u_test_gen/H_cnt_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 278 PLL_B u_pll/PLLA_inst/CLKOUT3
0.399 0.399 tNET RR 1 R22C40[0][A] u_test_gen/H_cnt_2_s0/CLK
0.400 0.001 tHld 1 R22C40[0][A] u_test_gen/H_cnt_2_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.399, 100.000%
Arrival Data Path Delay cell: 0.191, 50.495%; route: 0.011, 2.970%; tC2Q: 0.176, 46.535%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.399, 100.000%

Path9

Path Summary:

Slack 0.378
Data Arrival Time 0.776
Data Required Time 0.398
From u_test_gen/H_cnt_8_s0
To u_test_gen/H_cnt_8_s0
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 278 PLL_B u_pll/PLLA_inst/CLKOUT3
0.397 0.397 tNET RR 1 R23C40[0][A] u_test_gen/H_cnt_8_s0/CLK
0.573 0.176 tC2Q RF 5 R23C40[0][A] u_test_gen/H_cnt_8_s0/Q
0.584 0.011 tNET FF 1 R23C40[0][A] u_test_gen/n132_s4/I1
0.776 0.191 tINS FF 1 R23C40[0][A] u_test_gen/n132_s4/F
0.776 0.000 tNET FF 1 R23C40[0][A] u_test_gen/H_cnt_8_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 278 PLL_B u_pll/PLLA_inst/CLKOUT3
0.397 0.397 tNET RR 1 R23C40[0][A] u_test_gen/H_cnt_8_s0/CLK
0.398 0.001 tHld 1 R23C40[0][A] u_test_gen/H_cnt_8_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.397, 100.000%
Arrival Data Path Delay cell: 0.191, 50.495%; route: 0.011, 2.970%; tC2Q: 0.176, 46.535%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.397, 100.000%

Path10

Path Summary:

Slack 0.377
Data Arrival Time 0.773
Data Required Time 0.396
From u_test_gen/De_hcnt_1_s3
To u_test_gen/De_hcnt_1_s3
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 278 PLL_B u_pll/PLLA_inst/CLKOUT3
0.395 0.395 tNET RR 1 R24C40[1][A] u_test_gen/De_hcnt_1_s3/CLK
0.571 0.176 tC2Q RF 7 R24C40[1][A] u_test_gen/De_hcnt_1_s3/Q
0.582 0.011 tNET FF 1 R24C40[1][A] u_test_gen/n504_s5/I2
0.773 0.191 tINS FF 1 R24C40[1][A] u_test_gen/n504_s5/F
0.773 0.000 tNET FF 1 R24C40[1][A] u_test_gen/De_hcnt_1_s3/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 278 PLL_B u_pll/PLLA_inst/CLKOUT3
0.395 0.395 tNET RR 1 R24C40[1][A] u_test_gen/De_hcnt_1_s3/CLK
0.396 0.001 tHld 1 R24C40[1][A] u_test_gen/De_hcnt_1_s3

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.395, 100.000%
Arrival Data Path Delay cell: 0.191, 50.495%; route: 0.011, 2.970%; tC2Q: 0.176, 46.535%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.395, 100.000%

Path11

Path Summary:

Slack 0.378
Data Arrival Time 0.766
Data Required Time 0.389
From u_test_gen/Color_trig_num_4_s3
To u_test_gen/Color_trig_num_4_s3
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 278 PLL_B u_pll/PLLA_inst/CLKOUT3
0.387 0.387 tNET RR 1 R25C39[1][A] u_test_gen/Color_trig_num_4_s3/CLK
0.564 0.176 tC2Q RF 6 R25C39[1][A] u_test_gen/Color_trig_num_4_s3/Q
0.575 0.011 tNET FF 1 R25C39[1][A] u_test_gen/n611_s4/I2
0.766 0.191 tINS FF 1 R25C39[1][A] u_test_gen/n611_s4/F
0.766 0.000 tNET FF 1 R25C39[1][A] u_test_gen/Color_trig_num_4_s3/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 278 PLL_B u_pll/PLLA_inst/CLKOUT3
0.387 0.387 tNET RR 1 R25C39[1][A] u_test_gen/Color_trig_num_4_s3/CLK
0.389 0.001 tHld 1 R25C39[1][A] u_test_gen/Color_trig_num_4_s3

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.387, 100.000%
Arrival Data Path Delay cell: 0.191, 50.495%; route: 0.011, 2.970%; tC2Q: 0.176, 46.535%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.387, 100.000%

Path12

Path Summary:

Slack 0.378
Data Arrival Time 0.761
Data Required Time 0.384
From u_test_gen/Color_trig_num_8_s3
To u_test_gen/Color_trig_num_8_s3
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 278 PLL_B u_pll/PLLA_inst/CLKOUT3
0.382 0.382 tNET RR 1 R25C38[1][A] u_test_gen/Color_trig_num_8_s3/CLK
0.559 0.176 tC2Q RF 5 R25C38[1][A] u_test_gen/Color_trig_num_8_s3/Q
0.570 0.011 tNET FF 1 R25C38[1][A] u_test_gen/n607_s4/I1
0.761 0.191 tINS FF 1 R25C38[1][A] u_test_gen/n607_s4/F
0.761 0.000 tNET FF 1 R25C38[1][A] u_test_gen/Color_trig_num_8_s3/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 278 PLL_B u_pll/PLLA_inst/CLKOUT3
0.382 0.382 tNET RR 1 R25C38[1][A] u_test_gen/Color_trig_num_8_s3/CLK
0.384 0.001 tHld 1 R25C38[1][A] u_test_gen/Color_trig_num_8_s3

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.382, 100.000%
Arrival Data Path Delay cell: 0.191, 50.495%; route: 0.011, 2.970%; tC2Q: 0.176, 46.535%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.382, 100.000%

Path13

Path Summary:

Slack 0.381
Data Arrival Time 0.764
Data Required Time 0.383
From u_test_gen/De_hcnt_9_s1
To u_test_gen/De_hcnt_9_s1
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 278 PLL_B u_pll/PLLA_inst/CLKOUT3
0.381 0.381 tNET RR 1 R26C39[1][A] u_test_gen/De_hcnt_9_s1/CLK
0.558 0.176 tC2Q RF 5 R26C39[1][A] u_test_gen/De_hcnt_9_s1/Q
0.572 0.015 tNET FF 1 R26C39[1][A] u_test_gen/n496_s2/I3
0.764 0.191 tINS FF 1 R26C39[1][A] u_test_gen/n496_s2/F
0.764 0.000 tNET FF 1 R26C39[1][A] u_test_gen/De_hcnt_9_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 278 PLL_B u_pll/PLLA_inst/CLKOUT3
0.381 0.381 tNET RR 1 R26C39[1][A] u_test_gen/De_hcnt_9_s1/CLK
0.383 0.001 tHld 1 R26C39[1][A] u_test_gen/De_hcnt_9_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.381, 100.000%
Arrival Data Path Delay cell: 0.191, 50.000%; route: 0.015, 3.922%; tC2Q: 0.176, 46.078%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.381, 100.000%

Path14

Path Summary:

Slack 0.381
Data Arrival Time 0.779
Data Required Time 0.398
From u_test_gen/V_cnt_4_s1
To u_test_gen/V_cnt_4_s1
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 278 PLL_B u_pll/PLLA_inst/CLKOUT3
0.397 0.397 tNET RR 1 R23C36[1][A] u_test_gen/V_cnt_4_s1/CLK
0.573 0.176 tC2Q RF 6 R23C36[1][A] u_test_gen/V_cnt_4_s1/Q
0.588 0.015 tNET FF 1 R23C36[1][A] u_test_gen/n70_s2/I1
0.779 0.191 tINS FF 1 R23C36[1][A] u_test_gen/n70_s2/F
0.779 0.000 tNET FF 1 R23C36[1][A] u_test_gen/V_cnt_4_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 278 PLL_B u_pll/PLLA_inst/CLKOUT3
0.397 0.397 tNET RR 1 R23C36[1][A] u_test_gen/V_cnt_4_s1/CLK
0.398 0.001 tHld 1 R23C36[1][A] u_test_gen/V_cnt_4_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.397, 100.000%
Arrival Data Path Delay cell: 0.191, 50.000%; route: 0.015, 3.922%; tC2Q: 0.176, 46.078%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.397, 100.000%

Path15

Path Summary:

Slack 0.381
Data Arrival Time 0.767
Data Required Time 0.386
From u_test_gen/Color_trig_num_5_s3
To u_test_gen/Color_trig_num_5_s3
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 278 PLL_B u_pll/PLLA_inst/CLKOUT3
0.385 0.385 tNET RR 1 R24C38[1][A] u_test_gen/Color_trig_num_5_s3/CLK
0.561 0.176 tC2Q RF 5 R24C38[1][A] u_test_gen/Color_trig_num_5_s3/Q
0.576 0.015 tNET FF 1 R24C38[1][A] u_test_gen/n610_s4/I2
0.767 0.191 tINS FF 1 R24C38[1][A] u_test_gen/n610_s4/F
0.767 0.000 tNET FF 1 R24C38[1][A] u_test_gen/Color_trig_num_5_s3/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 278 PLL_B u_pll/PLLA_inst/CLKOUT3
0.385 0.385 tNET RR 1 R24C38[1][A] u_test_gen/Color_trig_num_5_s3/CLK
0.386 0.001 tHld 1 R24C38[1][A] u_test_gen/Color_trig_num_5_s3

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.385, 100.000%
Arrival Data Path Delay cell: 0.191, 50.000%; route: 0.015, 3.922%; tC2Q: 0.176, 46.078%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.385, 100.000%

Path16

Path Summary:

Slack 0.389
Data Arrival Time 0.787
Data Required Time 0.398
From u_test_gen/V_cnt_0_s1
To u_test_gen/V_cnt_0_s1
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 278 PLL_B u_pll/PLLA_inst/CLKOUT3
0.397 0.397 tNET RR 1 R23C36[0][A] u_test_gen/V_cnt_0_s1/CLK
0.577 0.180 tC2Q RR 6 R23C36[0][A] u_test_gen/V_cnt_0_s1/Q
0.596 0.019 tNET RR 1 R23C36[0][A] u_test_gen/n74_s2/I0
0.787 0.191 tINS RF 1 R23C36[0][A] u_test_gen/n74_s2/F
0.787 0.000 tNET FF 1 R23C36[0][A] u_test_gen/V_cnt_0_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 278 PLL_B u_pll/PLLA_inst/CLKOUT3
0.397 0.397 tNET RR 1 R23C36[0][A] u_test_gen/V_cnt_0_s1/CLK
0.398 0.001 tHld 1 R23C36[0][A] u_test_gen/V_cnt_0_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.397, 100.000%
Arrival Data Path Delay cell: 0.191, 49.038%; route: 0.019, 4.808%; tC2Q: 0.180, 46.154%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.397, 100.000%

Path17

Path Summary:

Slack 0.390
Data Arrival Time 1.007
Data Required Time 0.618
From u_p2b/u_p2b_0/mid_data_7_s1
To u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 278 PLL_B u_pll/PLLA_inst/CLKOUT3
0.361 0.361 tNET RR 1 R15C34[0][A] u_p2b/u_p2b_0/mid_data_7_s1/CLK
0.541 0.180 tC2Q RR 1 R15C34[0][A] u_p2b/u_p2b_0/mid_data_7_s1/Q
1.007 0.466 tNET RR 1 BSRAM_R10[10] u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s/DI[7]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 278 PLL_B u_pll/PLLA_inst/CLKOUT3
0.369 0.369 tNET RR 1 BSRAM_R10[10] u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s/CLKA
0.618 0.249 tHld 1 BSRAM_R10[10] u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s

Path Statistics:

Clock Skew 0.007
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.361, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.466, 72.147%; tC2Q: 0.180, 27.853%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.369, 100.000%

Path18

Path Summary:

Slack 0.392
Data Arrival Time 0.791
Data Required Time 0.398
From u_test_gen/H_cnt_7_s0
To u_test_gen/H_cnt_7_s0
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 278 PLL_B u_pll/PLLA_inst/CLKOUT3
0.397 0.397 tNET RR 1 R23C40[1][A] u_test_gen/H_cnt_7_s0/CLK
0.577 0.180 tC2Q RR 7 R23C40[1][A] u_test_gen/H_cnt_7_s0/Q
0.599 0.023 tNET RR 1 R23C40[1][A] u_test_gen/n133_s2/I1
0.791 0.191 tINS RF 1 R23C40[1][A] u_test_gen/n133_s2/F
0.791 0.000 tNET FF 1 R23C40[1][A] u_test_gen/H_cnt_7_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 278 PLL_B u_pll/PLLA_inst/CLKOUT3
0.397 0.397 tNET RR 1 R23C40[1][A] u_test_gen/H_cnt_7_s0/CLK
0.398 0.001 tHld 1 R23C40[1][A] u_test_gen/H_cnt_7_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.397, 100.000%
Arrival Data Path Delay cell: 0.191, 48.571%; route: 0.023, 5.714%; tC2Q: 0.180, 45.714%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.397, 100.000%

Path19

Path Summary:

Slack 0.393
Data Arrival Time 0.750
Data Required Time 0.357
From u_p2b/u_p2b_0/u_mid_buf/rWPtrBin_1_s0
To u_p2b/u_p2b_0/u_mid_buf/rWPtrBin_1_s0
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 278 PLL_B u_pll/PLLA_inst/CLKOUT3
0.356 0.356 tNET RR 1 R12C36[0][A] u_p2b/u_p2b_0/u_mid_buf/rWPtrBin_1_s0/CLK
0.536 0.180 tC2Q RR 10 R12C36[0][A] u_p2b/u_p2b_0/u_mid_buf/rWPtrBin_1_s0/Q
0.559 0.023 tNET RR 1 R12C36[0][A] u_p2b/u_p2b_0/u_mid_buf/wWPtrBinNext_1_s3/I1
0.750 0.191 tINS RF 1 R12C36[0][A] u_p2b/u_p2b_0/u_mid_buf/wWPtrBinNext_1_s3/F
0.750 0.000 tNET FF 1 R12C36[0][A] u_p2b/u_p2b_0/u_mid_buf/rWPtrBin_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 278 PLL_B u_pll/PLLA_inst/CLKOUT3
0.356 0.356 tNET RR 1 R12C36[0][A] u_p2b/u_p2b_0/u_mid_buf/rWPtrBin_1_s0/CLK
0.357 0.001 tHld 1 R12C36[0][A] u_p2b/u_p2b_0/u_mid_buf/rWPtrBin_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.356, 100.000%
Arrival Data Path Delay cell: 0.191, 48.571%; route: 0.023, 5.714%; tC2Q: 0.180, 45.714%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.356, 100.000%

Path20

Path Summary:

Slack 0.393
Data Arrival Time 0.745
Data Required Time 0.352
From u_p2b/u_p2b_0/u_mid_buf/rWPtrBin_4_s0
To u_p2b/u_p2b_0/u_mid_buf/rWPtrBin_4_s0
Launch Clk pixel_clk:[R]
Latch Clk pixel_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 278 PLL_B u_pll/PLLA_inst/CLKOUT3
0.351 0.351 tNET RR 1 R12C35[0][A] u_p2b/u_p2b_0/u_mid_buf/rWPtrBin_4_s0/CLK
0.531 0.180 tC2Q RR 9 R12C35[0][A] u_p2b/u_p2b_0/u_mid_buf/rWPtrBin_4_s0/Q
0.554 0.023 tNET RR 1 R12C35[0][A] u_p2b/u_p2b_0/u_mid_buf/wWPtrBinNext_4_s3/I0
0.745 0.191 tINS RF 1 R12C35[0][A] u_p2b/u_p2b_0/u_mid_buf/wWPtrBinNext_4_s3/F
0.745 0.000 tNET FF 1 R12C35[0][A] u_p2b/u_p2b_0/u_mid_buf/rWPtrBin_4_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR 278 PLL_B u_pll/PLLA_inst/CLKOUT3
0.351 0.351 tNET RR 1 R12C35[0][A] u_p2b/u_p2b_0/u_mid_buf/rWPtrBin_4_s0/CLK
0.352 0.001 tHld 1 R12C35[0][A] u_p2b/u_p2b_0/u_mid_buf/rWPtrBin_4_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.351, 100.000%
Arrival Data Path Delay cell: 0.191, 48.571%; route: 0.023, 5.714%; tC2Q: 0.180, 45.714%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.351, 100.000%

Hold Analysis Report[2]:

Report Command:report_timing -hold -from_clock [get_clocks {byte_clk}] -max_paths 20 -max_common_paths 1

Path1

Path Summary:

Slack 0.264
Data Arrival Time 0.881
Data Required Time 0.618
From u_dsi_tx/u_tx/u_dsi_tx/rCtrl_3_s0
To u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mBsram_mBsram_0_0_s
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.381 0.381 tNET RR 1 R8C24[1][A] u_dsi_tx/u_tx/u_dsi_tx/rCtrl_3_s0/CLK
0.561 0.180 tC2Q RR 2 R8C24[1][A] u_dsi_tx/u_tx/u_dsi_tx/rCtrl_3_s0/Q
0.881 0.320 tNET RR 1 BSRAM_R10[5] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mBsram_mBsram_0_0_s/DI[3]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.369 0.369 tNET RR 1 BSRAM_R10[5] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mBsram_mBsram_0_0_s/CLKA
0.618 0.249 tHld 1 BSRAM_R10[5] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mBsram_mBsram_0_0_s

Path Statistics:

Clock Skew -0.013
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.381, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.320, 64.000%; tC2Q: 0.180, 36.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.369, 100.000%

Path2

Path Summary:

Slack 0.264
Data Arrival Time 0.881
Data Required Time 0.618
From u_dsi_tx/u_tx/u_dsi_tx/rCtrl_1_s0
To u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mBsram_mBsram_0_0_s
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.381 0.381 tNET RR 1 R8C24[0][A] u_dsi_tx/u_tx/u_dsi_tx/rCtrl_1_s0/CLK
0.561 0.180 tC2Q RR 2 R8C24[0][A] u_dsi_tx/u_tx/u_dsi_tx/rCtrl_1_s0/Q
0.881 0.320 tNET RR 1 BSRAM_R10[5] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mBsram_mBsram_0_0_s/DI[1]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.369 0.369 tNET RR 1 BSRAM_R10[5] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mBsram_mBsram_0_0_s/CLKA
0.618 0.249 tHld 1 BSRAM_R10[5] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mBsram_mBsram_0_0_s

Path Statistics:

Clock Skew -0.013
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.381, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.320, 64.000%; tC2Q: 0.180, 36.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.369, 100.000%

Path3

Path Summary:

Slack 0.270
Data Arrival Time 0.519
Data Required Time 0.249
From u_la0_top/u_ao_mem_ctrl/data_reg_37_s0
To u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.000 0.000 tNET RR 1 R11C8[0][A] u_la0_top/u_ao_mem_ctrl/data_reg_37_s0/CLK
0.180 0.180 tC2Q RR 1 R11C8[0][A] u_la0_top/u_ao_mem_ctrl/data_reg_37_s0/Q
0.519 0.339 tNET RR 1 BSRAM_R10[1] u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[5]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.000 0.000 tNET RR 1 BSRAM_R10[1] u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA
0.249 0.249 tHld 1 BSRAM_R10[1] u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.339, 65.301%; tC2Q: 0.180, 34.699%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path4

Path Summary:

Slack 0.287
Data Arrival Time 0.536
Data Required Time 0.249
From u_la0_top/u_ao_mem_ctrl/data_reg_6_s0
To u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.000 0.000 tNET RR 1 R9C9[1][A] u_la0_top/u_ao_mem_ctrl/data_reg_6_s0/CLK
0.180 0.180 tC2Q RR 1 R9C9[1][A] u_la0_top/u_ao_mem_ctrl/data_reg_6_s0/Q
0.536 0.356 tNET RR 1 BSRAM_R10[0] u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[6]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.000 0.000 tNET RR 1 BSRAM_R10[0] u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
0.249 0.249 tHld 1 BSRAM_R10[0] u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.356, 66.434%; tC2Q: 0.180, 33.566%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path5

Path Summary:

Slack 0.287
Data Arrival Time 0.536
Data Required Time 0.249
From u_la0_top/u_ao_mem_ctrl/data_reg_2_s0
To u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.000 0.000 tNET RR 1 R9C8[1][A] u_la0_top/u_ao_mem_ctrl/data_reg_2_s0/CLK
0.180 0.180 tC2Q RR 1 R9C8[1][A] u_la0_top/u_ao_mem_ctrl/data_reg_2_s0/Q
0.536 0.356 tNET RR 1 BSRAM_R10[0] u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[2]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.000 0.000 tNET RR 1 BSRAM_R10[0] u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
0.249 0.249 tHld 1 BSRAM_R10[0] u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.356, 66.434%; tC2Q: 0.180, 33.566%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path6

Path Summary:

Slack 0.287
Data Arrival Time 0.536
Data Required Time 0.249
From u_la0_top/u_ao_mem_ctrl/data_reg_0_s0
To u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.000 0.000 tNET RR 1 R9C8[0][A] u_la0_top/u_ao_mem_ctrl/data_reg_0_s0/CLK
0.180 0.180 tC2Q RR 1 R9C8[0][A] u_la0_top/u_ao_mem_ctrl/data_reg_0_s0/Q
0.536 0.356 tNET RR 1 BSRAM_R10[0] u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[0]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.000 0.000 tNET RR 1 BSRAM_R10[0] u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
0.249 0.249 tHld 1 BSRAM_R10[0] u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.356, 66.434%; tC2Q: 0.180, 33.566%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path7

Path Summary:

Slack 0.299
Data Arrival Time 0.916
Data Required Time 0.618
From u_dsi_tx/u_tx/u_dsi_tx/rCtrl_2_s0
To u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mBsram_mBsram_0_0_s
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.376 0.376 tNET RR 1 R8C23[0][A] u_dsi_tx/u_tx/u_dsi_tx/rCtrl_2_s0/CLK
0.556 0.180 tC2Q RR 2 R8C23[0][A] u_dsi_tx/u_tx/u_dsi_tx/rCtrl_2_s0/Q
0.916 0.360 tNET RR 1 BSRAM_R10[5] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mBsram_mBsram_0_0_s/DI[2]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.369 0.369 tNET RR 1 BSRAM_R10[5] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mBsram_mBsram_0_0_s/CLKA
0.618 0.249 tHld 1 BSRAM_R10[5] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mBsram_mBsram_0_0_s

Path Statistics:

Clock Skew -0.008
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.376, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.360, 66.667%; tC2Q: 0.180, 33.333%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.369, 100.000%

Path8

Path Summary:

Slack 0.306
Data Arrival Time 0.555
Data Required Time 0.249
From u_la0_top/u_ao_mem_ctrl/data_reg_35_s0
To u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.000 0.000 tNET RR 1 R8C11[2][B] u_la0_top/u_ao_mem_ctrl/data_reg_35_s0/CLK
0.180 0.180 tC2Q RR 1 R8C11[2][B] u_la0_top/u_ao_mem_ctrl/data_reg_35_s0/Q
0.555 0.375 tNET RR 1 BSRAM_R10[1] u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[3]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.000 0.000 tNET RR 1 BSRAM_R10[1] u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA
0.249 0.249 tHld 1 BSRAM_R10[1] u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.375, 67.568%; tC2Q: 0.180, 32.432%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path9

Path Summary:

Slack 0.306
Data Arrival Time 0.555
Data Required Time 0.249
From u_la0_top/u_ao_mem_ctrl/data_reg_34_s0
To u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.000 0.000 tNET RR 1 R8C11[2][A] u_la0_top/u_ao_mem_ctrl/data_reg_34_s0/CLK
0.180 0.180 tC2Q RR 1 R8C11[2][A] u_la0_top/u_ao_mem_ctrl/data_reg_34_s0/Q
0.555 0.375 tNET RR 1 BSRAM_R10[1] u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[2]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.000 0.000 tNET RR 1 BSRAM_R10[1] u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA
0.249 0.249 tHld 1 BSRAM_R10[1] u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.375, 67.568%; tC2Q: 0.180, 32.432%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path10

Path Summary:

Slack 0.308
Data Arrival Time 0.926
Data Required Time 0.618
From u_dsi_tx/u_tx/u_dsi_tx/rCtrl_0_s0
To u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mBsram_mBsram_0_0_s
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.375 0.375 tNET RR 1 R9C24[0][A] u_dsi_tx/u_tx/u_dsi_tx/rCtrl_0_s0/CLK
0.555 0.180 tC2Q RR 2 R9C24[0][A] u_dsi_tx/u_tx/u_dsi_tx/rCtrl_0_s0/Q
0.926 0.371 tNET RR 1 BSRAM_R10[5] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mBsram_mBsram_0_0_s/DI[0]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.369 0.369 tNET RR 1 BSRAM_R10[5] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mBsram_mBsram_0_0_s/CLKA
0.618 0.249 tHld 1 BSRAM_R10[5] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mBsram_mBsram_0_0_s

Path Statistics:

Clock Skew -0.006
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.371, 67.347%; tC2Q: 0.180, 32.653%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.369, 100.000%

Path11

Path Summary:

Slack 0.311
Data Arrival Time 0.929
Data Required Time 0.618
From u_dsi_tx/u_tx/u_dsi_tx/rCtrl_13_s0
To u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mBsram_mBsram_0_0_s
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.381 0.381 tNET RR 1 R8C24[0][B] u_dsi_tx/u_tx/u_dsi_tx/rCtrl_13_s0/CLK
0.561 0.180 tC2Q RR 2 R8C24[0][B] u_dsi_tx/u_tx/u_dsi_tx/rCtrl_13_s0/Q
0.929 0.367 tNET RR 1 BSRAM_R10[5] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mBsram_mBsram_0_0_s/DI[6]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.369 0.369 tNET RR 1 BSRAM_R10[5] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mBsram_mBsram_0_0_s/CLKA
0.618 0.249 tHld 1 BSRAM_R10[5] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mBsram_mBsram_0_0_s

Path Statistics:

Clock Skew -0.013
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.381, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.367, 67.123%; tC2Q: 0.180, 32.877%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.369, 100.000%

Path12

Path Summary:

Slack 0.312
Data Arrival Time 0.799
Data Required Time 0.487
From u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/rWrOffset_1_s1
To u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mBsram_mBsram_0_0_s
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.375 0.375 tNET RR 1 R9C22[0][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/rWrOffset_1_s1/CLK
0.555 0.180 tC2Q RR 4 R9C22[0][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/rWrOffset_1_s1/Q
0.799 0.244 tNET RR 1 BSRAM_R10[5] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mBsram_mBsram_0_0_s/ADA[4]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.369 0.369 tNET RR 1 BSRAM_R10[5] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mBsram_mBsram_0_0_s/CLKA
0.487 0.118 tHld 1 BSRAM_R10[5] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mBsram_mBsram_0_0_s

Path Statistics:

Clock Skew -0.006
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.244, 57.522%; tC2Q: 0.180, 42.478%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.369, 100.000%

Path13

Path Summary:

Slack 0.317
Data Arrival Time 0.435
Data Required Time 0.118
From u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
To u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.000 0.000 tNET RR 1 R5C8[1][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK
0.180 0.180 tC2Q RR 6 R5C8[1][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/Q
0.435 0.255 tNET RR 1 BSRAM_R10[1] u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/ADA[7]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.000 0.000 tNET RR 1 BSRAM_R10[1] u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA
0.118 0.118 tHld 1 BSRAM_R10[1] u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.255, 58.621%; tC2Q: 0.180, 41.379%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path14

Path Summary:

Slack 0.319
Data Arrival Time 0.438
Data Required Time 0.118
From u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
To u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.000 0.000 tNET RR 1 R5C8[0][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
0.180 0.180 tC2Q RR 8 R5C8[0][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/Q
0.438 0.257 tNET RR 1 BSRAM_R10[1] u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/ADA[5]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.000 0.000 tNET RR 1 BSRAM_R10[1] u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA
0.118 0.118 tHld 1 BSRAM_R10[1] u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.257, 58.857%; tC2Q: 0.180, 41.143%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path15

Path Summary:

Slack 0.319
Data Arrival Time 0.438
Data Required Time 0.118
From u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
To u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.000 0.000 tNET RR 1 R5C8[0][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
0.180 0.180 tC2Q RR 8 R5C8[0][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/Q
0.438 0.257 tNET RR 1 BSRAM_R10[0] u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/ADA[5]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.000 0.000 tNET RR 1 BSRAM_R10[0] u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
0.118 0.118 tHld 1 BSRAM_R10[0] u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.257, 58.857%; tC2Q: 0.180, 41.143%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path16

Path Summary:

Slack 0.326
Data Arrival Time 0.812
Data Required Time 0.487
From u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/rWrOffset_4_s1
To u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mBsram_mBsram_0_0_s
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.380 0.380 tNET RR 1 R9C21[2][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/rWrOffset_4_s1/CLK
0.560 0.180 tC2Q RR 3 R9C21[2][B] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/rWrOffset_4_s1/Q
0.812 0.252 tNET RR 1 BSRAM_R10[5] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mBsram_mBsram_0_0_s/ADA[7]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.369 0.369 tNET RR 1 BSRAM_R10[5] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mBsram_mBsram_0_0_s/CLKA
0.487 0.118 tHld 1 BSRAM_R10[5] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mBsram_mBsram_0_0_s

Path Statistics:

Clock Skew -0.011
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.380, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.252, 58.382%; tC2Q: 0.180, 41.618%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.369, 100.000%

Path17

Path Summary:

Slack 0.329
Data Arrival Time 0.816
Data Required Time 0.487
From u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/rWrOffset_3_s1
To u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mBsram_mBsram_0_0_s
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.380 0.380 tNET RR 1 R9C21[2][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/rWrOffset_3_s1/CLK
0.560 0.180 tC2Q RR 4 R9C21[2][A] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/rWrOffset_3_s1/Q
0.816 0.256 tNET RR 1 BSRAM_R10[5] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mBsram_mBsram_0_0_s/ADA[6]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.369 0.369 tNET RR 1 BSRAM_R10[5] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mBsram_mBsram_0_0_s/CLKA
0.487 0.118 tHld 1 BSRAM_R10[5] u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/mBsram_mBsram_0_0_s

Path Statistics:

Clock Skew -0.011
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.380, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.256, 58.739%; tC2Q: 0.180, 41.261%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.369, 100.000%

Path18

Path Summary:

Slack 0.337
Data Arrival Time 0.586
Data Required Time 0.249
From u_la0_top/u_ao_mem_ctrl/data_reg_9_s0
To u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.000 0.000 tNET RR 1 R9C9[1][B] u_la0_top/u_ao_mem_ctrl/data_reg_9_s0/CLK
0.180 0.180 tC2Q RR 1 R9C9[1][B] u_la0_top/u_ao_mem_ctrl/data_reg_9_s0/Q
0.586 0.406 tNET RR 1 BSRAM_R10[0] u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[9]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.000 0.000 tNET RR 1 BSRAM_R10[0] u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
0.249 0.249 tHld 1 BSRAM_R10[0] u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.406, 69.296%; tC2Q: 0.180, 30.704%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path19

Path Summary:

Slack 0.337
Data Arrival Time 0.586
Data Required Time 0.249
From u_la0_top/u_ao_mem_ctrl/data_reg_8_s0
To u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.000 0.000 tNET RR 1 R9C8[2][A] u_la0_top/u_ao_mem_ctrl/data_reg_8_s0/CLK
0.180 0.180 tC2Q RR 1 R9C8[2][A] u_la0_top/u_ao_mem_ctrl/data_reg_8_s0/Q
0.586 0.406 tNET RR 1 BSRAM_R10[0] u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[8]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.000 0.000 tNET RR 1 BSRAM_R10[0] u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
0.249 0.249 tHld 1 BSRAM_R10[0] u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.406, 69.296%; tC2Q: 0.180, 30.704%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path20

Path Summary:

Slack 0.337
Data Arrival Time 0.586
Data Required Time 0.249
From u_la0_top/u_ao_mem_ctrl/data_reg_3_s0
To u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk byte_clk:[R]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.000 0.000 tNET RR 1 R9C8[1][B] u_la0_top/u_ao_mem_ctrl/data_reg_3_s0/CLK
0.180 0.180 tC2Q RR 1 R9C8[1][B] u_la0_top/u_ao_mem_ctrl/data_reg_3_s0/Q
0.586 0.406 tNET RR 1 BSRAM_R10[0] u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[3]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.000 0.000 tNET RR 1 BSRAM_R10[0] u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
0.249 0.249 tHld 1 BSRAM_R10[0] u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.406, 69.296%; tC2Q: 0.180, 30.704%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 0.839
Data Arrival Time 8.225
Data Required Time 9.064
From u_la0_top/rst_ao_s0
To u_la0_top/internal_reg_start_syn_0_s0
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.706 4.706 active clock edge time
4.706 0.000 byte_clk
4.706 0.000 tCL FF 755 PLL_B u_pll/PLLA_inst/CLKOUT2
4.706 0.000 tNET FF 1 R5C3[1][A] u_la0_top/rst_ao_s0/CLK
5.148 0.442 tC2Q FF 54 R5C3[1][A] u_la0_top/rst_ao_s0/Q
8.225 3.077 tNET FF 1 R2C10[1][A] u_la0_top/internal_reg_start_syn_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9.412 9.412 active clock edge time
9.412 0.000 byte_clk
9.412 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
9.412 0.000 tNET RR 1 R2C10[1][A] u_la0_top/internal_reg_start_syn_0_s0/CLK
9.064 -0.347 tSu 1 R2C10[1][A] u_la0_top/internal_reg_start_syn_0_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 4.706
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.077, 87.427%; tC2Q: 0.442, 12.573%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path2

Path Summary:

Slack 0.865
Data Arrival Time 8.200
Data Required Time 9.064
From u_la0_top/rst_ao_s0
To u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.706 4.706 active clock edge time
4.706 0.000 byte_clk
4.706 0.000 tCL FF 755 PLL_B u_pll/PLLA_inst/CLKOUT2
4.706 0.000 tNET FF 1 R5C3[1][A] u_la0_top/rst_ao_s0/CLK
5.148 0.442 tC2Q FF 54 R5C3[1][A] u_la0_top/rst_ao_s0/Q
8.200 3.051 tNET FF 1 R2C11[2][A] u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9.412 9.412 active clock edge time
9.412 0.000 byte_clk
9.412 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
9.412 0.000 tNET RR 1 R2C11[2][A] u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLK
9.064 -0.347 tSu 1 R2C11[2][A] u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 4.706
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.051, 87.335%; tC2Q: 0.442, 12.665%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path3

Path Summary:

Slack 0.865
Data Arrival Time 8.200
Data Required Time 9.064
From u_la0_top/rst_ao_s0
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.706 4.706 active clock edge time
4.706 0.000 byte_clk
4.706 0.000 tCL FF 755 PLL_B u_pll/PLLA_inst/CLKOUT2
4.706 0.000 tNET FF 1 R5C3[1][A] u_la0_top/rst_ao_s0/CLK
5.148 0.442 tC2Q FF 54 R5C3[1][A] u_la0_top/rst_ao_s0/Q
8.200 3.051 tNET FF 1 R2C11[0][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9.412 9.412 active clock edge time
9.412 0.000 byte_clk
9.412 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
9.412 0.000 tNET RR 1 R2C11[0][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK
9.064 -0.347 tSu 1 R2C11[0][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 4.706
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.051, 87.335%; tC2Q: 0.442, 12.665%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path4

Path Summary:

Slack 0.865
Data Arrival Time 8.200
Data Required Time 9.064
From u_la0_top/rst_ao_s0
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.706 4.706 active clock edge time
4.706 0.000 byte_clk
4.706 0.000 tCL FF 755 PLL_B u_pll/PLLA_inst/CLKOUT2
4.706 0.000 tNET FF 1 R5C3[1][A] u_la0_top/rst_ao_s0/CLK
5.148 0.442 tC2Q FF 54 R5C3[1][A] u_la0_top/rst_ao_s0/Q
8.200 3.051 tNET FF 1 R2C11[0][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9.412 9.412 active clock edge time
9.412 0.000 byte_clk
9.412 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
9.412 0.000 tNET RR 1 R2C11[0][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK
9.064 -0.347 tSu 1 R2C11[0][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 4.706
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.051, 87.335%; tC2Q: 0.442, 12.665%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path5

Path Summary:

Slack 0.865
Data Arrival Time 8.200
Data Required Time 9.064
From u_la0_top/rst_ao_s0
To u_la0_top/start_reg_s0
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.706 4.706 active clock edge time
4.706 0.000 byte_clk
4.706 0.000 tCL FF 755 PLL_B u_pll/PLLA_inst/CLKOUT2
4.706 0.000 tNET FF 1 R5C3[1][A] u_la0_top/rst_ao_s0/CLK
5.148 0.442 tC2Q FF 54 R5C3[1][A] u_la0_top/rst_ao_s0/Q
8.200 3.051 tNET FF 1 R2C11[1][A] u_la0_top/start_reg_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9.412 9.412 active clock edge time
9.412 0.000 byte_clk
9.412 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
9.412 0.000 tNET RR 1 R2C11[1][A] u_la0_top/start_reg_s0/CLK
9.064 -0.347 tSu 1 R2C11[1][A] u_la0_top/start_reg_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 4.706
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.051, 87.335%; tC2Q: 0.442, 12.665%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path6

Path Summary:

Slack 0.865
Data Arrival Time 8.200
Data Required Time 9.064
From u_la0_top/rst_ao_s0
To u_la0_top/internal_reg_start_dly_0_s0
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.706 4.706 active clock edge time
4.706 0.000 byte_clk
4.706 0.000 tCL FF 755 PLL_B u_pll/PLLA_inst/CLKOUT2
4.706 0.000 tNET FF 1 R5C3[1][A] u_la0_top/rst_ao_s0/CLK
5.148 0.442 tC2Q FF 54 R5C3[1][A] u_la0_top/rst_ao_s0/Q
8.200 3.051 tNET FF 1 R2C11[1][B] u_la0_top/internal_reg_start_dly_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9.412 9.412 active clock edge time
9.412 0.000 byte_clk
9.412 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
9.412 0.000 tNET RR 1 R2C11[1][B] u_la0_top/internal_reg_start_dly_0_s0/CLK
9.064 -0.347 tSu 1 R2C11[1][B] u_la0_top/internal_reg_start_dly_0_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 4.706
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.051, 87.335%; tC2Q: 0.442, 12.665%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path7

Path Summary:

Slack 0.868
Data Arrival Time 8.196
Data Required Time 9.064
From u_la0_top/rst_ao_s0
To u_la0_top/capture_window_sel_2_s1
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.706 4.706 active clock edge time
4.706 0.000 byte_clk
4.706 0.000 tCL FF 755 PLL_B u_pll/PLLA_inst/CLKOUT2
4.706 0.000 tNET FF 1 R5C3[1][A] u_la0_top/rst_ao_s0/CLK
5.148 0.442 tC2Q FF 54 R5C3[1][A] u_la0_top/rst_ao_s0/Q
8.196 3.048 tNET FF 1 R2C4[3][A] u_la0_top/capture_window_sel_2_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9.412 9.412 active clock edge time
9.412 0.000 byte_clk
9.412 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
9.412 0.000 tNET RR 1 R2C4[3][A] u_la0_top/capture_window_sel_2_s1/CLK
9.064 -0.347 tSu 1 R2C4[3][A] u_la0_top/capture_window_sel_2_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 4.706
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.048, 87.321%; tC2Q: 0.442, 12.679%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path8

Path Summary:

Slack 0.868
Data Arrival Time 8.196
Data Required Time 9.064
From u_la0_top/rst_ao_s0
To u_la0_top/capture_window_sel_3_s1
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.706 4.706 active clock edge time
4.706 0.000 byte_clk
4.706 0.000 tCL FF 755 PLL_B u_pll/PLLA_inst/CLKOUT2
4.706 0.000 tNET FF 1 R5C3[1][A] u_la0_top/rst_ao_s0/CLK
5.148 0.442 tC2Q FF 54 R5C3[1][A] u_la0_top/rst_ao_s0/Q
8.196 3.048 tNET FF 1 R2C4[2][B] u_la0_top/capture_window_sel_3_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9.412 9.412 active clock edge time
9.412 0.000 byte_clk
9.412 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
9.412 0.000 tNET RR 1 R2C4[2][B] u_la0_top/capture_window_sel_3_s1/CLK
9.064 -0.347 tSu 1 R2C4[2][B] u_la0_top/capture_window_sel_3_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 4.706
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.048, 87.321%; tC2Q: 0.442, 12.679%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path9

Path Summary:

Slack 0.868
Data Arrival Time 8.196
Data Required Time 9.064
From u_la0_top/rst_ao_s0
To u_la0_top/capture_window_sel_4_s1
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.706 4.706 active clock edge time
4.706 0.000 byte_clk
4.706 0.000 tCL FF 755 PLL_B u_pll/PLLA_inst/CLKOUT2
4.706 0.000 tNET FF 1 R5C3[1][A] u_la0_top/rst_ao_s0/CLK
5.148 0.442 tC2Q FF 54 R5C3[1][A] u_la0_top/rst_ao_s0/Q
8.196 3.048 tNET FF 1 R2C4[2][A] u_la0_top/capture_window_sel_4_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9.412 9.412 active clock edge time
9.412 0.000 byte_clk
9.412 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
9.412 0.000 tNET RR 1 R2C4[2][A] u_la0_top/capture_window_sel_4_s1/CLK
9.064 -0.347 tSu 1 R2C4[2][A] u_la0_top/capture_window_sel_4_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 4.706
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.048, 87.321%; tC2Q: 0.442, 12.679%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path10

Path Summary:

Slack 0.868
Data Arrival Time 8.196
Data Required Time 9.064
From u_la0_top/rst_ao_s0
To u_la0_top/capture_window_sel_5_s1
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.706 4.706 active clock edge time
4.706 0.000 byte_clk
4.706 0.000 tCL FF 755 PLL_B u_pll/PLLA_inst/CLKOUT2
4.706 0.000 tNET FF 1 R5C3[1][A] u_la0_top/rst_ao_s0/CLK
5.148 0.442 tC2Q FF 54 R5C3[1][A] u_la0_top/rst_ao_s0/Q
8.196 3.048 tNET FF 1 R2C4[1][B] u_la0_top/capture_window_sel_5_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9.412 9.412 active clock edge time
9.412 0.000 byte_clk
9.412 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
9.412 0.000 tNET RR 1 R2C4[1][B] u_la0_top/capture_window_sel_5_s1/CLK
9.064 -0.347 tSu 1 R2C4[1][B] u_la0_top/capture_window_sel_5_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 4.706
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.048, 87.321%; tC2Q: 0.442, 12.679%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path11

Path Summary:

Slack 0.868
Data Arrival Time 8.196
Data Required Time 9.064
From u_la0_top/rst_ao_s0
To u_la0_top/capture_window_sel_6_s1
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.706 4.706 active clock edge time
4.706 0.000 byte_clk
4.706 0.000 tCL FF 755 PLL_B u_pll/PLLA_inst/CLKOUT2
4.706 0.000 tNET FF 1 R5C3[1][A] u_la0_top/rst_ao_s0/CLK
5.148 0.442 tC2Q FF 54 R5C3[1][A] u_la0_top/rst_ao_s0/Q
8.196 3.048 tNET FF 1 R2C4[1][A] u_la0_top/capture_window_sel_6_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9.412 9.412 active clock edge time
9.412 0.000 byte_clk
9.412 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
9.412 0.000 tNET RR 1 R2C4[1][A] u_la0_top/capture_window_sel_6_s1/CLK
9.064 -0.347 tSu 1 R2C4[1][A] u_la0_top/capture_window_sel_6_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 4.706
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.048, 87.321%; tC2Q: 0.442, 12.679%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path12

Path Summary:

Slack 0.868
Data Arrival Time 8.196
Data Required Time 9.064
From u_la0_top/rst_ao_s0
To u_la0_top/capture_window_sel_7_s1
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.706 4.706 active clock edge time
4.706 0.000 byte_clk
4.706 0.000 tCL FF 755 PLL_B u_pll/PLLA_inst/CLKOUT2
4.706 0.000 tNET FF 1 R5C3[1][A] u_la0_top/rst_ao_s0/CLK
5.148 0.442 tC2Q FF 54 R5C3[1][A] u_la0_top/rst_ao_s0/Q
8.196 3.048 tNET FF 1 R2C4[0][B] u_la0_top/capture_window_sel_7_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9.412 9.412 active clock edge time
9.412 0.000 byte_clk
9.412 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
9.412 0.000 tNET RR 1 R2C4[0][B] u_la0_top/capture_window_sel_7_s1/CLK
9.064 -0.347 tSu 1 R2C4[0][B] u_la0_top/capture_window_sel_7_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 4.706
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.048, 87.321%; tC2Q: 0.442, 12.679%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path13

Path Summary:

Slack 0.868
Data Arrival Time 8.196
Data Required Time 9.064
From u_la0_top/rst_ao_s0
To u_la0_top/capture_window_sel_8_s1
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.706 4.706 active clock edge time
4.706 0.000 byte_clk
4.706 0.000 tCL FF 755 PLL_B u_pll/PLLA_inst/CLKOUT2
4.706 0.000 tNET FF 1 R5C3[1][A] u_la0_top/rst_ao_s0/CLK
5.148 0.442 tC2Q FF 54 R5C3[1][A] u_la0_top/rst_ao_s0/Q
8.196 3.048 tNET FF 1 R2C4[0][A] u_la0_top/capture_window_sel_8_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9.412 9.412 active clock edge time
9.412 0.000 byte_clk
9.412 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
9.412 0.000 tNET RR 1 R2C4[0][A] u_la0_top/capture_window_sel_8_s1/CLK
9.064 -0.347 tSu 1 R2C4[0][A] u_la0_top/capture_window_sel_8_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 4.706
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.048, 87.321%; tC2Q: 0.442, 12.679%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path14

Path Summary:

Slack 0.876
Data Arrival Time 8.188
Data Required Time 9.064
From u_la0_top/rst_ao_s0
To u_la0_top/u_ao_mem_ctrl/capture_length_4_s1
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.706 4.706 active clock edge time
4.706 0.000 byte_clk
4.706 0.000 tCL FF 755 PLL_B u_pll/PLLA_inst/CLKOUT2
4.706 0.000 tNET FF 1 R5C3[1][A] u_la0_top/rst_ao_s0/CLK
5.148 0.442 tC2Q FF 54 R5C3[1][A] u_la0_top/rst_ao_s0/Q
8.188 3.040 tNET FF 1 R3C7[0][A] u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9.412 9.412 active clock edge time
9.412 0.000 byte_clk
9.412 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
9.412 0.000 tNET RR 1 R3C7[0][A] u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLK
9.064 -0.347 tSu 1 R3C7[0][A] u_la0_top/u_ao_mem_ctrl/capture_length_4_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 4.706
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.040, 87.292%; tC2Q: 0.442, 12.708%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path15

Path Summary:

Slack 0.876
Data Arrival Time 8.188
Data Required Time 9.064
From u_la0_top/rst_ao_s0
To u_la0_top/u_ao_mem_ctrl/capture_length_5_s1
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.706 4.706 active clock edge time
4.706 0.000 byte_clk
4.706 0.000 tCL FF 755 PLL_B u_pll/PLLA_inst/CLKOUT2
4.706 0.000 tNET FF 1 R5C3[1][A] u_la0_top/rst_ao_s0/CLK
5.148 0.442 tC2Q FF 54 R5C3[1][A] u_la0_top/rst_ao_s0/Q
8.188 3.040 tNET FF 1 R3C7[0][B] u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9.412 9.412 active clock edge time
9.412 0.000 byte_clk
9.412 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
9.412 0.000 tNET RR 1 R3C7[0][B] u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLK
9.064 -0.347 tSu 1 R3C7[0][B] u_la0_top/u_ao_mem_ctrl/capture_length_5_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 4.706
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.040, 87.292%; tC2Q: 0.442, 12.708%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path16

Path Summary:

Slack 0.876
Data Arrival Time 8.188
Data Required Time 9.064
From u_la0_top/rst_ao_s0
To u_la0_top/u_ao_mem_ctrl/capture_length_6_s1
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.706 4.706 active clock edge time
4.706 0.000 byte_clk
4.706 0.000 tCL FF 755 PLL_B u_pll/PLLA_inst/CLKOUT2
4.706 0.000 tNET FF 1 R5C3[1][A] u_la0_top/rst_ao_s0/CLK
5.148 0.442 tC2Q FF 54 R5C3[1][A] u_la0_top/rst_ao_s0/Q
8.188 3.040 tNET FF 1 R3C7[1][A] u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9.412 9.412 active clock edge time
9.412 0.000 byte_clk
9.412 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
9.412 0.000 tNET RR 1 R3C7[1][A] u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLK
9.064 -0.347 tSu 1 R3C7[1][A] u_la0_top/u_ao_mem_ctrl/capture_length_6_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 4.706
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.040, 87.292%; tC2Q: 0.442, 12.708%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path17

Path Summary:

Slack 0.876
Data Arrival Time 8.188
Data Required Time 9.064
From u_la0_top/rst_ao_s0
To u_la0_top/u_ao_mem_ctrl/capture_length_7_s1
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.706 4.706 active clock edge time
4.706 0.000 byte_clk
4.706 0.000 tCL FF 755 PLL_B u_pll/PLLA_inst/CLKOUT2
4.706 0.000 tNET FF 1 R5C3[1][A] u_la0_top/rst_ao_s0/CLK
5.148 0.442 tC2Q FF 54 R5C3[1][A] u_la0_top/rst_ao_s0/Q
8.188 3.040 tNET FF 1 R3C7[1][B] u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9.412 9.412 active clock edge time
9.412 0.000 byte_clk
9.412 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
9.412 0.000 tNET RR 1 R3C7[1][B] u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLK
9.064 -0.347 tSu 1 R3C7[1][B] u_la0_top/u_ao_mem_ctrl/capture_length_7_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 4.706
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.040, 87.292%; tC2Q: 0.442, 12.708%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path18

Path Summary:

Slack 0.880
Data Arrival Time 8.184
Data Required Time 9.064
From u_la0_top/rst_ao_s0
To u_la0_top/u_ao_match_0/trig_dly_in_0_s0
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.706 4.706 active clock edge time
4.706 0.000 byte_clk
4.706 0.000 tCL FF 755 PLL_B u_pll/PLLA_inst/CLKOUT2
4.706 0.000 tNET FF 1 R5C3[1][A] u_la0_top/rst_ao_s0/CLK
5.148 0.442 tC2Q FF 54 R5C3[1][A] u_la0_top/rst_ao_s0/Q
8.184 3.036 tNET FF 1 R3C9[1][B] u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9.412 9.412 active clock edge time
9.412 0.000 byte_clk
9.412 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
9.412 0.000 tNET RR 1 R3C9[1][B] u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLK
9.064 -0.347 tSu 1 R3C9[1][B] u_la0_top/u_ao_match_0/trig_dly_in_0_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 4.706
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.036, 87.279%; tC2Q: 0.442, 12.721%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path19

Path Summary:

Slack 0.880
Data Arrival Time 8.184
Data Required Time 9.064
From u_la0_top/rst_ao_s0
To u_la0_top/u_ao_mem_ctrl/capture_length_3_s1
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.706 4.706 active clock edge time
4.706 0.000 byte_clk
4.706 0.000 tCL FF 755 PLL_B u_pll/PLLA_inst/CLKOUT2
4.706 0.000 tNET FF 1 R5C3[1][A] u_la0_top/rst_ao_s0/CLK
5.148 0.442 tC2Q FF 54 R5C3[1][A] u_la0_top/rst_ao_s0/Q
8.184 3.036 tNET FF 1 R3C9[2][A] u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9.412 9.412 active clock edge time
9.412 0.000 byte_clk
9.412 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
9.412 0.000 tNET RR 1 R3C9[2][A] u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/CLK
9.064 -0.347 tSu 1 R3C9[2][A] u_la0_top/u_ao_mem_ctrl/capture_length_3_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 4.706
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.036, 87.279%; tC2Q: 0.442, 12.721%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path20

Path Summary:

Slack 0.880
Data Arrival Time 8.184
Data Required Time 9.064
From u_la0_top/rst_ao_s0
To u_la0_top/u_ao_mem_ctrl/capture_length_1_s1
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.706 4.706 active clock edge time
4.706 0.000 byte_clk
4.706 0.000 tCL FF 755 PLL_B u_pll/PLLA_inst/CLKOUT2
4.706 0.000 tNET FF 1 R5C3[1][A] u_la0_top/rst_ao_s0/CLK
5.148 0.442 tC2Q FF 54 R5C3[1][A] u_la0_top/rst_ao_s0/Q
8.184 3.036 tNET FF 1 R3C9[2][B] u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9.412 9.412 active clock edge time
9.412 0.000 byte_clk
9.412 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
9.412 0.000 tNET RR 1 R3C9[2][B] u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLK
9.064 -0.347 tSu 1 R3C9[2][B] u_la0_top/u_ao_mem_ctrl/capture_length_1_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 4.706
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.036, 87.279%; tC2Q: 0.442, 12.721%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path21

Path Summary:

Slack 0.880
Data Arrival Time 8.184
Data Required Time 9.064
From u_la0_top/rst_ao_s0
To u_la0_top/u_ao_mem_ctrl/capture_length_2_s1
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.706 4.706 active clock edge time
4.706 0.000 byte_clk
4.706 0.000 tCL FF 755 PLL_B u_pll/PLLA_inst/CLKOUT2
4.706 0.000 tNET FF 1 R5C3[1][A] u_la0_top/rst_ao_s0/CLK
5.148 0.442 tC2Q FF 54 R5C3[1][A] u_la0_top/rst_ao_s0/Q
8.184 3.036 tNET FF 1 R3C9[3][A] u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9.412 9.412 active clock edge time
9.412 0.000 byte_clk
9.412 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
9.412 0.000 tNET RR 1 R3C9[3][A] u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLK
9.064 -0.347 tSu 1 R3C9[3][A] u_la0_top/u_ao_mem_ctrl/capture_length_2_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 4.706
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.036, 87.279%; tC2Q: 0.442, 12.721%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path22

Path Summary:

Slack 0.880
Data Arrival Time 8.184
Data Required Time 9.064
From u_la0_top/rst_ao_s0
To u_la0_top/capture_end_dly_s0
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.706 4.706 active clock edge time
4.706 0.000 byte_clk
4.706 0.000 tCL FF 755 PLL_B u_pll/PLLA_inst/CLKOUT2
4.706 0.000 tNET FF 1 R5C3[1][A] u_la0_top/rst_ao_s0/CLK
5.148 0.442 tC2Q FF 54 R5C3[1][A] u_la0_top/rst_ao_s0/Q
8.184 3.036 tNET FF 1 R3C9[1][A] u_la0_top/capture_end_dly_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9.412 9.412 active clock edge time
9.412 0.000 byte_clk
9.412 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
9.412 0.000 tNET RR 1 R3C9[1][A] u_la0_top/capture_end_dly_s0/CLK
9.064 -0.347 tSu 1 R3C9[1][A] u_la0_top/capture_end_dly_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 4.706
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.036, 87.279%; tC2Q: 0.442, 12.721%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path23

Path Summary:

Slack 0.882
Data Arrival Time 8.182
Data Required Time 9.064
From u_la0_top/rst_ao_s0
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.706 4.706 active clock edge time
4.706 0.000 byte_clk
4.706 0.000 tCL FF 755 PLL_B u_pll/PLLA_inst/CLKOUT2
4.706 0.000 tNET FF 1 R5C3[1][A] u_la0_top/rst_ao_s0/CLK
5.148 0.442 tC2Q FF 54 R5C3[1][A] u_la0_top/rst_ao_s0/Q
8.182 3.033 tNET FF 1 R5C8[0][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9.412 9.412 active clock edge time
9.412 0.000 byte_clk
9.412 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
9.412 0.000 tNET RR 1 R5C8[0][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLK
9.064 -0.347 tSu 1 R5C8[0][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 4.706
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.033, 87.270%; tC2Q: 0.442, 12.730%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path24

Path Summary:

Slack 0.882
Data Arrival Time 8.182
Data Required Time 9.064
From u_la0_top/rst_ao_s0
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.706 4.706 active clock edge time
4.706 0.000 byte_clk
4.706 0.000 tCL FF 755 PLL_B u_pll/PLLA_inst/CLKOUT2
4.706 0.000 tNET FF 1 R5C3[1][A] u_la0_top/rst_ao_s0/CLK
5.148 0.442 tC2Q FF 54 R5C3[1][A] u_la0_top/rst_ao_s0/Q
8.182 3.033 tNET FF 1 R5C8[0][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9.412 9.412 active clock edge time
9.412 0.000 byte_clk
9.412 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
9.412 0.000 tNET RR 1 R5C8[0][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
9.064 -0.347 tSu 1 R5C8[0][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 4.706
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.033, 87.270%; tC2Q: 0.442, 12.730%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path25

Path Summary:

Slack 0.882
Data Arrival Time 8.182
Data Required Time 9.064
From u_la0_top/rst_ao_s0
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.706 4.706 active clock edge time
4.706 0.000 byte_clk
4.706 0.000 tCL FF 755 PLL_B u_pll/PLLA_inst/CLKOUT2
4.706 0.000 tNET FF 1 R5C3[1][A] u_la0_top/rst_ao_s0/CLK
5.148 0.442 tC2Q FF 54 R5C3[1][A] u_la0_top/rst_ao_s0/Q
8.182 3.033 tNET FF 1 R5C8[1][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9.412 9.412 active clock edge time
9.412 0.000 byte_clk
9.412 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
9.412 0.000 tNET RR 1 R5C8[1][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK
9.064 -0.347 tSu 1 R5C8[1][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 4.706
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.033, 87.270%; tC2Q: 0.442, 12.730%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 6.482
Data Arrival Time 6.293
Data Required Time -0.189
From u_la0_top/rst_ao_s0
To u_la0_top/u_ao_mem_ctrl/capture_length_0_s1
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.706 4.706 active clock edge time
4.706 0.000 byte_clk
4.706 0.000 tCL FF 755 PLL_B u_pll/PLLA_inst/CLKOUT2
4.706 0.000 tNET FF 1 R5C3[1][A] u_la0_top/rst_ao_s0/CLK
4.903 0.198 tC2Q FR 54 R5C3[1][A] u_la0_top/rst_ao_s0/Q
6.293 1.390 tNET RR 1 R12C2[0][A] u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.000 0.000 tNET RR 1 R12C2[0][A] u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLK
-0.189 -0.189 tHld 1 R12C2[0][A] u_la0_top/u_ao_mem_ctrl/capture_length_0_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship -4.706
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.390, 87.559%; tC2Q: 0.198, 12.441%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path2

Path Summary:

Slack 6.506
Data Arrival Time 6.317
Data Required Time -0.189
From u_la0_top/rst_ao_s0
To u_la0_top/u_ao_mem_ctrl/capture_length_9_s1
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.706 4.706 active clock edge time
4.706 0.000 byte_clk
4.706 0.000 tCL FF 755 PLL_B u_pll/PLLA_inst/CLKOUT2
4.706 0.000 tNET FF 1 R5C3[1][A] u_la0_top/rst_ao_s0/CLK
4.903 0.198 tC2Q FR 54 R5C3[1][A] u_la0_top/rst_ao_s0/Q
6.317 1.414 tNET RR 1 R8C3[0][A] u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.000 0.000 tNET RR 1 R8C3[0][A] u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLK
-0.189 -0.189 tHld 1 R8C3[0][A] u_la0_top/u_ao_mem_ctrl/capture_length_9_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship -4.706
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.414, 87.742%; tC2Q: 0.198, 12.258%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path3

Path Summary:

Slack 6.506
Data Arrival Time 6.317
Data Required Time -0.189
From u_la0_top/rst_ao_s0
To u_la0_top/trigger_seq_start_s1
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.706 4.706 active clock edge time
4.706 0.000 byte_clk
4.706 0.000 tCL FF 755 PLL_B u_pll/PLLA_inst/CLKOUT2
4.706 0.000 tNET FF 1 R5C3[1][A] u_la0_top/rst_ao_s0/CLK
4.903 0.198 tC2Q FR 54 R5C3[1][A] u_la0_top/rst_ao_s0/Q
6.317 1.414 tNET RR 1 R8C4[1][A] u_la0_top/trigger_seq_start_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.000 0.000 tNET RR 1 R8C4[1][A] u_la0_top/trigger_seq_start_s1/CLK
-0.189 -0.189 tHld 1 R8C4[1][A] u_la0_top/trigger_seq_start_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship -4.706
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.414, 87.742%; tC2Q: 0.198, 12.258%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path4

Path Summary:

Slack 6.506
Data Arrival Time 6.317
Data Required Time -0.189
From u_la0_top/rst_ao_s0
To u_la0_top/internal_reg_start_dly_1_s0
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.706 4.706 active clock edge time
4.706 0.000 byte_clk
4.706 0.000 tCL FF 755 PLL_B u_pll/PLLA_inst/CLKOUT2
4.706 0.000 tNET FF 1 R5C3[1][A] u_la0_top/rst_ao_s0/CLK
4.903 0.198 tC2Q FR 54 R5C3[1][A] u_la0_top/rst_ao_s0/Q
6.317 1.414 tNET RR 1 R8C4[0][B] u_la0_top/internal_reg_start_dly_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.000 0.000 tNET RR 1 R8C4[0][B] u_la0_top/internal_reg_start_dly_1_s0/CLK
-0.189 -0.189 tHld 1 R8C4[0][B] u_la0_top/internal_reg_start_dly_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship -4.706
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.414, 87.742%; tC2Q: 0.198, 12.258%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path5

Path Summary:

Slack 6.506
Data Arrival Time 6.317
Data Required Time -0.189
From u_la0_top/rst_ao_s0
To u_la0_top/internal_reg_force_triger_syn_1_s0
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.706 4.706 active clock edge time
4.706 0.000 byte_clk
4.706 0.000 tCL FF 755 PLL_B u_pll/PLLA_inst/CLKOUT2
4.706 0.000 tNET FF 1 R5C3[1][A] u_la0_top/rst_ao_s0/CLK
4.903 0.198 tC2Q FR 54 R5C3[1][A] u_la0_top/rst_ao_s0/Q
6.317 1.414 tNET RR 1 R8C4[0][A] u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.000 0.000 tNET RR 1 R8C4[0][A] u_la0_top/internal_reg_force_triger_syn_1_s0/CLK
-0.189 -0.189 tHld 1 R8C4[0][A] u_la0_top/internal_reg_force_triger_syn_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship -4.706
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.414, 87.742%; tC2Q: 0.198, 12.258%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path6

Path Summary:

Slack 6.508
Data Arrival Time 6.320
Data Required Time -0.189
From u_la0_top/rst_ao_s0
To u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.706 4.706 active clock edge time
4.706 0.000 byte_clk
4.706 0.000 tCL FF 755 PLL_B u_pll/PLLA_inst/CLKOUT2
4.706 0.000 tNET FF 1 R5C3[1][A] u_la0_top/rst_ao_s0/CLK
4.903 0.198 tC2Q FR 54 R5C3[1][A] u_la0_top/rst_ao_s0/Q
6.320 1.416 tNET RR 1 R8C5[2][A] u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.000 0.000 tNET RR 1 R8C5[2][A] u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLK
-0.189 -0.189 tHld 1 R8C5[2][A] u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship -4.706
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.416, 87.761%; tC2Q: 0.198, 12.239%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path7

Path Summary:

Slack 6.508
Data Arrival Time 6.320
Data Required Time -0.189
From u_la0_top/rst_ao_s0
To u_la0_top/internal_reg_start_syn_1_s0
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.706 4.706 active clock edge time
4.706 0.000 byte_clk
4.706 0.000 tCL FF 755 PLL_B u_pll/PLLA_inst/CLKOUT2
4.706 0.000 tNET FF 1 R5C3[1][A] u_la0_top/rst_ao_s0/CLK
4.903 0.198 tC2Q FR 54 R5C3[1][A] u_la0_top/rst_ao_s0/Q
6.320 1.416 tNET RR 1 R8C6[2][A] u_la0_top/internal_reg_start_syn_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.000 0.000 tNET RR 1 R8C6[2][A] u_la0_top/internal_reg_start_syn_1_s0/CLK
-0.189 -0.189 tHld 1 R8C6[2][A] u_la0_top/internal_reg_start_syn_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship -4.706
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.416, 87.761%; tC2Q: 0.198, 12.239%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path8

Path Summary:

Slack 6.517
Data Arrival Time 6.328
Data Required Time -0.189
From u_la0_top/rst_ao_s0
To u_la0_top/u_ao_mem_ctrl/capture_length_8_s1
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.706 4.706 active clock edge time
4.706 0.000 byte_clk
4.706 0.000 tCL FF 755 PLL_B u_pll/PLLA_inst/CLKOUT2
4.706 0.000 tNET FF 1 R5C3[1][A] u_la0_top/rst_ao_s0/CLK
4.903 0.198 tC2Q FR 54 R5C3[1][A] u_la0_top/rst_ao_s0/Q
6.328 1.425 tNET RR 1 R4C8[0][A] u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.000 0.000 tNET RR 1 R4C8[0][A] u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLK
-0.189 -0.189 tHld 1 R4C8[0][A] u_la0_top/u_ao_mem_ctrl/capture_length_8_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship -4.706
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.425, 87.827%; tC2Q: 0.198, 12.173%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path9

Path Summary:

Slack 6.517
Data Arrival Time 6.329
Data Required Time -0.189
From u_la0_top/rst_ao_s0
To u_la0_top/u_ao_match_0/match_sep_s0
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.706 4.706 active clock edge time
4.706 0.000 byte_clk
4.706 0.000 tCL FF 755 PLL_B u_pll/PLLA_inst/CLKOUT2
4.706 0.000 tNET FF 1 R5C3[1][A] u_la0_top/rst_ao_s0/CLK
4.903 0.198 tC2Q FR 54 R5C3[1][A] u_la0_top/rst_ao_s0/Q
6.329 1.425 tNET RR 1 R3C8[0][A] u_la0_top/u_ao_match_0/match_sep_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.000 0.000 tNET RR 1 R3C8[0][A] u_la0_top/u_ao_match_0/match_sep_s0/CLK
-0.189 -0.189 tHld 1 R3C8[0][A] u_la0_top/u_ao_match_0/match_sep_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship -4.706
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.425, 87.830%; tC2Q: 0.198, 12.170%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path10

Path Summary:

Slack 6.517
Data Arrival Time 6.329
Data Required Time -0.189
From u_la0_top/rst_ao_s0
To u_la0_top/u_ao_match_0/trig_dly_0_s0
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.706 4.706 active clock edge time
4.706 0.000 byte_clk
4.706 0.000 tCL FF 755 PLL_B u_pll/PLLA_inst/CLKOUT2
4.706 0.000 tNET FF 1 R5C3[1][A] u_la0_top/rst_ao_s0/CLK
4.903 0.198 tC2Q FR 54 R5C3[1][A] u_la0_top/rst_ao_s0/Q
6.329 1.425 tNET RR 1 R3C8[0][B] u_la0_top/u_ao_match_0/trig_dly_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.000 0.000 tNET RR 1 R3C8[0][B] u_la0_top/u_ao_match_0/trig_dly_0_s0/CLK
-0.189 -0.189 tHld 1 R3C8[0][B] u_la0_top/u_ao_match_0/trig_dly_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship -4.706
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.425, 87.830%; tC2Q: 0.198, 12.170%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path11

Path Summary:

Slack 6.517
Data Arrival Time 6.329
Data Required Time -0.189
From u_la0_top/rst_ao_s0
To u_la0_top/u_ao_mem_ctrl/capture_loop_s1
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.706 4.706 active clock edge time
4.706 0.000 byte_clk
4.706 0.000 tCL FF 755 PLL_B u_pll/PLLA_inst/CLKOUT2
4.706 0.000 tNET FF 1 R5C3[1][A] u_la0_top/rst_ao_s0/CLK
4.903 0.198 tC2Q FR 54 R5C3[1][A] u_la0_top/rst_ao_s0/Q
6.329 1.425 tNET RR 1 R3C8[1][A] u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.000 0.000 tNET RR 1 R3C8[1][A] u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK
-0.189 -0.189 tHld 1 R3C8[1][A] u_la0_top/u_ao_mem_ctrl/capture_loop_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship -4.706
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.425, 87.830%; tC2Q: 0.198, 12.170%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path12

Path Summary:

Slack 6.518
Data Arrival Time 6.329
Data Required Time -0.189
From u_la0_top/rst_ao_s0
To u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.706 4.706 active clock edge time
4.706 0.000 byte_clk
4.706 0.000 tCL FF 755 PLL_B u_pll/PLLA_inst/CLKOUT2
4.706 0.000 tNET FF 1 R5C3[1][A] u_la0_top/rst_ao_s0/CLK
4.903 0.198 tC2Q FR 54 R5C3[1][A] u_la0_top/rst_ao_s0/Q
6.329 1.426 tNET RR 1 R5C3[2][A] u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.000 0.000 tNET RR 1 R5C3[2][A] u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
-0.189 -0.189 tHld 1 R5C3[2][A] u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship -4.706
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.426, 87.834%; tC2Q: 0.198, 12.166%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path13

Path Summary:

Slack 6.520
Data Arrival Time 6.331
Data Required Time -0.189
From u_la0_top/rst_ao_s0
To u_la0_top/triger_level_cnt_0_s3
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.706 4.706 active clock edge time
4.706 0.000 byte_clk
4.706 0.000 tCL FF 755 PLL_B u_pll/PLLA_inst/CLKOUT2
4.706 0.000 tNET FF 1 R5C3[1][A] u_la0_top/rst_ao_s0/CLK
4.903 0.198 tC2Q FR 54 R5C3[1][A] u_la0_top/rst_ao_s0/Q
6.331 1.428 tNET RR 1 R3C3[2][B] u_la0_top/triger_level_cnt_0_s3/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.000 0.000 tNET RR 1 R3C3[2][B] u_la0_top/triger_level_cnt_0_s3/CLK
-0.189 -0.189 tHld 1 R3C3[2][B] u_la0_top/triger_level_cnt_0_s3

Path Statistics:

Clock Skew 0.000
Hold Relationship -4.706
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.428, 87.848%; tC2Q: 0.198, 12.152%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path14

Path Summary:

Slack 6.520
Data Arrival Time 6.331
Data Required Time -0.189
From u_la0_top/rst_ao_s0
To u_la0_top/capture_window_sel_9_s1
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.706 4.706 active clock edge time
4.706 0.000 byte_clk
4.706 0.000 tCL FF 755 PLL_B u_pll/PLLA_inst/CLKOUT2
4.706 0.000 tNET FF 1 R5C3[1][A] u_la0_top/rst_ao_s0/CLK
4.903 0.198 tC2Q FR 54 R5C3[1][A] u_la0_top/rst_ao_s0/Q
6.331 1.428 tNET RR 1 R3C7[2][A] u_la0_top/capture_window_sel_9_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.000 0.000 tNET RR 1 R3C7[2][A] u_la0_top/capture_window_sel_9_s1/CLK
-0.189 -0.189 tHld 1 R3C7[2][A] u_la0_top/capture_window_sel_9_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship -4.706
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.428, 87.848%; tC2Q: 0.198, 12.152%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path15

Path Summary:

Slack 6.520
Data Arrival Time 6.331
Data Required Time -0.189
From u_la0_top/rst_ao_s0
To u_la0_top/triger_level_cnt_1_s1
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.706 4.706 active clock edge time
4.706 0.000 byte_clk
4.706 0.000 tCL FF 755 PLL_B u_pll/PLLA_inst/CLKOUT2
4.706 0.000 tNET FF 1 R5C3[1][A] u_la0_top/rst_ao_s0/CLK
4.903 0.198 tC2Q FR 54 R5C3[1][A] u_la0_top/rst_ao_s0/Q
6.331 1.428 tNET RR 1 R3C2[3][B] u_la0_top/triger_level_cnt_1_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.000 0.000 tNET RR 1 R3C2[3][B] u_la0_top/triger_level_cnt_1_s1/CLK
-0.189 -0.189 tHld 1 R3C2[3][B] u_la0_top/triger_level_cnt_1_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship -4.706
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.428, 87.848%; tC2Q: 0.198, 12.152%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path16

Path Summary:

Slack 6.520
Data Arrival Time 6.331
Data Required Time -0.189
From u_la0_top/rst_ao_s0
To u_la0_top/triger_level_cnt_2_s1
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.706 4.706 active clock edge time
4.706 0.000 byte_clk
4.706 0.000 tCL FF 755 PLL_B u_pll/PLLA_inst/CLKOUT2
4.706 0.000 tNET FF 1 R5C3[1][A] u_la0_top/rst_ao_s0/CLK
4.903 0.198 tC2Q FR 54 R5C3[1][A] u_la0_top/rst_ao_s0/Q
6.331 1.428 tNET RR 1 R3C2[3][A] u_la0_top/triger_level_cnt_2_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.000 0.000 tNET RR 1 R3C2[3][A] u_la0_top/triger_level_cnt_2_s1/CLK
-0.189 -0.189 tHld 1 R3C2[3][A] u_la0_top/triger_level_cnt_2_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship -4.706
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.428, 87.848%; tC2Q: 0.198, 12.152%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path17

Path Summary:

Slack 6.520
Data Arrival Time 6.331
Data Required Time -0.189
From u_la0_top/rst_ao_s0
To u_la0_top/triger_level_cnt_3_s1
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.706 4.706 active clock edge time
4.706 0.000 byte_clk
4.706 0.000 tCL FF 755 PLL_B u_pll/PLLA_inst/CLKOUT2
4.706 0.000 tNET FF 1 R5C3[1][A] u_la0_top/rst_ao_s0/CLK
4.903 0.198 tC2Q FR 54 R5C3[1][A] u_la0_top/rst_ao_s0/Q
6.331 1.428 tNET RR 1 R3C2[2][B] u_la0_top/triger_level_cnt_3_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.000 0.000 tNET RR 1 R3C2[2][B] u_la0_top/triger_level_cnt_3_s1/CLK
-0.189 -0.189 tHld 1 R3C2[2][B] u_la0_top/triger_level_cnt_3_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship -4.706
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.428, 87.848%; tC2Q: 0.198, 12.152%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path18

Path Summary:

Slack 6.520
Data Arrival Time 6.331
Data Required Time -0.189
From u_la0_top/rst_ao_s0
To u_la0_top/triger_s0
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.706 4.706 active clock edge time
4.706 0.000 byte_clk
4.706 0.000 tCL FF 755 PLL_B u_pll/PLLA_inst/CLKOUT2
4.706 0.000 tNET FF 1 R5C3[1][A] u_la0_top/rst_ao_s0/CLK
4.903 0.198 tC2Q FR 54 R5C3[1][A] u_la0_top/rst_ao_s0/Q
6.331 1.428 tNET RR 1 R3C3[2][A] u_la0_top/triger_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.000 0.000 tNET RR 1 R3C3[2][A] u_la0_top/triger_s0/CLK
-0.189 -0.189 tHld 1 R3C3[2][A] u_la0_top/triger_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship -4.706
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.428, 87.848%; tC2Q: 0.198, 12.152%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path19

Path Summary:

Slack 6.521
Data Arrival Time 6.332
Data Required Time -0.189
From u_la0_top/rst_ao_s0
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.706 4.706 active clock edge time
4.706 0.000 byte_clk
4.706 0.000 tCL FF 755 PLL_B u_pll/PLLA_inst/CLKOUT2
4.706 0.000 tNET FF 1 R5C3[1][A] u_la0_top/rst_ao_s0/CLK
4.903 0.198 tC2Q FR 54 R5C3[1][A] u_la0_top/rst_ao_s0/Q
6.332 1.428 tNET RR 1 R5C8[0][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.000 0.000 tNET RR 1 R5C8[0][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLK
-0.189 -0.189 tHld 1 R5C8[0][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship -4.706
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.428, 87.853%; tC2Q: 0.198, 12.147%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path20

Path Summary:

Slack 6.521
Data Arrival Time 6.332
Data Required Time -0.189
From u_la0_top/rst_ao_s0
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.706 4.706 active clock edge time
4.706 0.000 byte_clk
4.706 0.000 tCL FF 755 PLL_B u_pll/PLLA_inst/CLKOUT2
4.706 0.000 tNET FF 1 R5C3[1][A] u_la0_top/rst_ao_s0/CLK
4.903 0.198 tC2Q FR 54 R5C3[1][A] u_la0_top/rst_ao_s0/Q
6.332 1.428 tNET RR 1 R5C8[0][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.000 0.000 tNET RR 1 R5C8[0][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
-0.189 -0.189 tHld 1 R5C8[0][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship -4.706
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.428, 87.853%; tC2Q: 0.198, 12.147%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path21

Path Summary:

Slack 6.521
Data Arrival Time 6.332
Data Required Time -0.189
From u_la0_top/rst_ao_s0
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.706 4.706 active clock edge time
4.706 0.000 byte_clk
4.706 0.000 tCL FF 755 PLL_B u_pll/PLLA_inst/CLKOUT2
4.706 0.000 tNET FF 1 R5C3[1][A] u_la0_top/rst_ao_s0/CLK
4.903 0.198 tC2Q FR 54 R5C3[1][A] u_la0_top/rst_ao_s0/Q
6.332 1.428 tNET RR 1 R5C8[1][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.000 0.000 tNET RR 1 R5C8[1][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK
-0.189 -0.189 tHld 1 R5C8[1][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship -4.706
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.428, 87.853%; tC2Q: 0.198, 12.147%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path22

Path Summary:

Slack 6.521
Data Arrival Time 6.332
Data Required Time -0.189
From u_la0_top/rst_ao_s0
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.706 4.706 active clock edge time
4.706 0.000 byte_clk
4.706 0.000 tCL FF 755 PLL_B u_pll/PLLA_inst/CLKOUT2
4.706 0.000 tNET FF 1 R5C3[1][A] u_la0_top/rst_ao_s0/CLK
4.903 0.198 tC2Q FR 54 R5C3[1][A] u_la0_top/rst_ao_s0/Q
6.332 1.428 tNET RR 1 R5C8[1][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.000 0.000 tNET RR 1 R5C8[1][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK
-0.189 -0.189 tHld 1 R5C8[1][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship -4.706
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.428, 87.853%; tC2Q: 0.198, 12.147%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path23

Path Summary:

Slack 6.521
Data Arrival Time 6.332
Data Required Time -0.189
From u_la0_top/rst_ao_s0
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.706 4.706 active clock edge time
4.706 0.000 byte_clk
4.706 0.000 tCL FF 755 PLL_B u_pll/PLLA_inst/CLKOUT2
4.706 0.000 tNET FF 1 R5C3[1][A] u_la0_top/rst_ao_s0/CLK
4.903 0.198 tC2Q FR 54 R5C3[1][A] u_la0_top/rst_ao_s0/Q
6.332 1.428 tNET RR 1 R5C8[2][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.000 0.000 tNET RR 1 R5C8[2][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
-0.189 -0.189 tHld 1 R5C8[2][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship -4.706
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.428, 87.853%; tC2Q: 0.198, 12.147%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path24

Path Summary:

Slack 6.522
Data Arrival Time 6.333
Data Required Time -0.189
From u_la0_top/rst_ao_s0
To u_la0_top/capture_window_sel_0_s3
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.706 4.706 active clock edge time
4.706 0.000 byte_clk
4.706 0.000 tCL FF 755 PLL_B u_pll/PLLA_inst/CLKOUT2
4.706 0.000 tNET FF 1 R5C3[1][A] u_la0_top/rst_ao_s0/CLK
4.903 0.198 tC2Q FR 54 R5C3[1][A] u_la0_top/rst_ao_s0/Q
6.333 1.430 tNET RR 1 R2C2[3][A] u_la0_top/capture_window_sel_0_s3/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.000 0.000 tNET RR 1 R2C2[3][A] u_la0_top/capture_window_sel_0_s3/CLK
-0.189 -0.189 tHld 1 R2C2[3][A] u_la0_top/capture_window_sel_0_s3

Path Statistics:

Clock Skew 0.000
Hold Relationship -4.706
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.430, 87.865%; tC2Q: 0.198, 12.135%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path25

Path Summary:

Slack 6.522
Data Arrival Time 6.333
Data Required Time -0.189
From u_la0_top/rst_ao_s0
To u_la0_top/internal_reg_force_triger_syn_0_s0
Launch Clk byte_clk:[F]
Latch Clk byte_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.706 4.706 active clock edge time
4.706 0.000 byte_clk
4.706 0.000 tCL FF 755 PLL_B u_pll/PLLA_inst/CLKOUT2
4.706 0.000 tNET FF 1 R5C3[1][A] u_la0_top/rst_ao_s0/CLK
4.903 0.198 tC2Q FR 54 R5C3[1][A] u_la0_top/rst_ao_s0/Q
6.333 1.430 tNET RR 1 R4C2[2][A] u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 byte_clk
0.000 0.000 tCL RR 755 PLL_B u_pll/PLLA_inst/CLKOUT2
0.000 0.000 tNET RR 1 R4C2[2][A] u_la0_top/internal_reg_force_triger_syn_0_s0/CLK
-0.189 -0.189 tHld 1 R4C2[2][A] u_la0_top/internal_reg_force_triger_syn_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship -4.706
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.430, 87.865%; tC2Q: 0.198, 12.135%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack: 2.033
Actual Width: 3.033
Required Width: 1.000
Type: Low Pulse Width
Clock: pixel_clk
Objects: u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s

Late clock Path:

AT DELAY TYPE RF NODE
3.529 0.000 active clock edge time
3.529 0.000 pixel_clk
3.529 0.000 tCL FF u_pll/PLLA_inst/CLKOUT3
4.395 0.865 tNET FF u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s/CLKA

Early clock Path:

AT DELAY TYPE RF NODE
7.059 0.000 active clock edge time
7.059 0.000 pixel_clk
7.059 0.000 tCL RR u_pll/PLLA_inst/CLKOUT3
7.428 0.369 tNET RR u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s/CLKA

MPW2

MPW Summary:

Slack: 2.035
Actual Width: 3.035
Required Width: 1.000
Type: High Pulse Width
Clock: pixel_clk
Objects: u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 pixel_clk
0.000 0.000 tCL RR u_pll/PLLA_inst/CLKOUT3
0.869 0.869 tNET RR u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s/CLKA

Early clock Path:

AT DELAY TYPE RF NODE
3.529 0.000 active clock edge time
3.529 0.000 pixel_clk
3.529 0.000 tCL FF u_pll/PLLA_inst/CLKOUT3
3.904 0.375 tNET FF u_p2b/u_p2b_0/u_mid_buf/u_dpram/mBsram_mBsram_0_0_s/CLKA

MPW3

MPW Summary:

Slack: 2.773
Actual Width: 3.023
Required Width: 0.250
Type: Low Pulse Width
Clock: pixel_clk
Objects: u_p2b/u_p2b_0/shift_data_117_s0

Late clock Path:

AT DELAY TYPE RF NODE
3.529 0.000 active clock edge time
3.529 0.000 pixel_clk
3.529 0.000 tCL FF u_pll/PLLA_inst/CLKOUT3
4.440 0.910 tNET FF u_p2b/u_p2b_0/shift_data_117_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
7.059 0.000 active clock edge time
7.059 0.000 pixel_clk
7.059 0.000 tCL RR u_pll/PLLA_inst/CLKOUT3
7.462 0.403 tNET RR u_p2b/u_p2b_0/shift_data_117_s0/CLK

MPW4

MPW Summary:

Slack: 2.773
Actual Width: 3.023
Required Width: 0.250
Type: Low Pulse Width
Clock: pixel_clk
Objects: vs_cnt_6_s0

Late clock Path:

AT DELAY TYPE RF NODE
3.529 0.000 active clock edge time
3.529 0.000 pixel_clk
3.529 0.000 tCL FF u_pll/PLLA_inst/CLKOUT3
4.437 0.907 tNET FF vs_cnt_6_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
7.059 0.000 active clock edge time
7.059 0.000 pixel_clk
7.059 0.000 tCL RR u_pll/PLLA_inst/CLKOUT3
7.460 0.401 tNET RR vs_cnt_6_s0/CLK

MPW5

MPW Summary:

Slack: 2.773
Actual Width: 3.023
Required Width: 0.250
Type: Low Pulse Width
Clock: pixel_clk
Objects: vs_cnt_5_s0

Late clock Path:

AT DELAY TYPE RF NODE
3.529 0.000 active clock edge time
3.529 0.000 pixel_clk
3.529 0.000 tCL FF u_pll/PLLA_inst/CLKOUT3
4.437 0.907 tNET FF vs_cnt_5_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
7.059 0.000 active clock edge time
7.059 0.000 pixel_clk
7.059 0.000 tCL RR u_pll/PLLA_inst/CLKOUT3
7.460 0.401 tNET RR vs_cnt_5_s0/CLK

MPW6

MPW Summary:

Slack: 2.773
Actual Width: 3.023
Required Width: 0.250
Type: Low Pulse Width
Clock: pixel_clk
Objects: vs_cnt_4_s0

Late clock Path:

AT DELAY TYPE RF NODE
3.529 0.000 active clock edge time
3.529 0.000 pixel_clk
3.529 0.000 tCL FF u_pll/PLLA_inst/CLKOUT3
4.437 0.907 tNET FF vs_cnt_4_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
7.059 0.000 active clock edge time
7.059 0.000 pixel_clk
7.059 0.000 tCL RR u_pll/PLLA_inst/CLKOUT3
7.460 0.401 tNET RR vs_cnt_4_s0/CLK

MPW7

MPW Summary:

Slack: 2.773
Actual Width: 3.023
Required Width: 0.250
Type: Low Pulse Width
Clock: pixel_clk
Objects: vs_cnt_3_s0

Late clock Path:

AT DELAY TYPE RF NODE
3.529 0.000 active clock edge time
3.529 0.000 pixel_clk
3.529 0.000 tCL FF u_pll/PLLA_inst/CLKOUT3
4.437 0.907 tNET FF vs_cnt_3_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
7.059 0.000 active clock edge time
7.059 0.000 pixel_clk
7.059 0.000 tCL RR u_pll/PLLA_inst/CLKOUT3
7.460 0.401 tNET RR vs_cnt_3_s0/CLK

MPW8

MPW Summary:

Slack: 2.773
Actual Width: 3.023
Required Width: 0.250
Type: Low Pulse Width
Clock: pixel_clk
Objects: vs_cnt_2_s0

Late clock Path:

AT DELAY TYPE RF NODE
3.529 0.000 active clock edge time
3.529 0.000 pixel_clk
3.529 0.000 tCL FF u_pll/PLLA_inst/CLKOUT3
4.437 0.907 tNET FF vs_cnt_2_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
7.059 0.000 active clock edge time
7.059 0.000 pixel_clk
7.059 0.000 tCL RR u_pll/PLLA_inst/CLKOUT3
7.460 0.401 tNET RR vs_cnt_2_s0/CLK

MPW9

MPW Summary:

Slack: 2.773
Actual Width: 3.023
Required Width: 0.250
Type: Low Pulse Width
Clock: pixel_clk
Objects: vs_cnt_1_s0

Late clock Path:

AT DELAY TYPE RF NODE
3.529 0.000 active clock edge time
3.529 0.000 pixel_clk
3.529 0.000 tCL FF u_pll/PLLA_inst/CLKOUT3
4.437 0.907 tNET FF vs_cnt_1_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
7.059 0.000 active clock edge time
7.059 0.000 pixel_clk
7.059 0.000 tCL RR u_pll/PLLA_inst/CLKOUT3
7.460 0.401 tNET RR vs_cnt_1_s0/CLK

MPW10

MPW Summary:

Slack: 2.773
Actual Width: 3.023
Required Width: 0.250
Type: Low Pulse Width
Clock: pixel_clk
Objects: vs_cnt_0_s0

Late clock Path:

AT DELAY TYPE RF NODE
3.529 0.000 active clock edge time
3.529 0.000 pixel_clk
3.529 0.000 tCL FF u_pll/PLLA_inst/CLKOUT3
4.437 0.907 tNET FF vs_cnt_0_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
7.059 0.000 active clock edge time
7.059 0.000 pixel_clk
7.059 0.000 tCL RR u_pll/PLLA_inst/CLKOUT3
7.460 0.401 tNET RR vs_cnt_0_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT NET NAME WORST SLACK MAX DELAY
755 byte_clk 1.386 0.915
278 pixel_clk 2.209 0.913
99 n3126_11 2.456 1.867
99 n3380_6 3.042 2.119
96 n2870_6 3.818 1.884
94 rRegData_125_8 3.042 2.183
94 n3219_9 2.456 2.107
75 rOffset[1] 4.642 0.979
66 rOffset[0] 4.919 1.501
65 mid_sel[0] 4.741 0.774

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC ROUTE CONGESTIONS
R24C24 73.61%
R25C22 72.22%
R12C36 66.67%
R21C25 62.50%
R14C29 61.11%
R11C31 61.11%
R12C31 61.11%
R20C28 61.11%
R23C21 59.72%
R22C23 59.72%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type State Detail Command
TC_CLOCK Actived create_clock -name clk_50 -period 20 -waveform {0 10} [get_ports {OSC_50M}]
TC_GENERATED_CLOCK Actived create_generated_clock -name pixel_clk -source [get_ports {OSC_50M}] -master_clock clk_50 -divide_by 6 -multiply_by 17 [get_nets {pixel_clk}]
TC_GENERATED_CLOCK Actived create_generated_clock -name byte_clk -source [get_ports {OSC_50M}] -master_clock clk_50 -divide_by 8 -multiply_by 17 [get_nets {byte_clk}]
TC_CLOCK_GROUP Actived set_clock_groups -exclusive -group [get_clocks {pixel_clk}] -group [get_clocks {byte_clk}]
TC_REPORT_TIMING Actived report_timing -setup -from_clock [get_clocks {pixel_clk}] -max_paths 20 -max_common_paths 1
TC_REPORT_TIMING Actived report_timing -setup -from_clock [get_clocks {byte_clk}] -max_paths 20 -max_common_paths 1
TC_REPORT_TIMING Actived report_timing -hold -from_clock [get_clocks {pixel_clk}] -max_paths 20 -max_common_paths 1
TC_REPORT_TIMING Actived report_timing -hold -from_clock [get_clocks {byte_clk}] -max_paths 20 -max_common_paths 1