Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | D:\Programs\Gowin\Gowin_V1.9.9.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v D:\Programs\Gowin\Gowin_V1.9.9.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v D:\Programs\Gowin\Gowin_V1.9.9.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v D:\Programs\Gowin\Gowin_V1.9.9.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v D:\Programs\Gowin\Gowin_V1.9.9.01_x64\IDE\data\ipcores\GAO\GW_CON\gw_con_top.v D:\Programs\Gowin\Gowin_V1.9.9.01_x64\IDE\data\ipcores\gw_jtag.v F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\DSI_Test_Pattern_1nr9\fpga_proj\impl\gao\gw_gao_top.v |
GowinSynthesis Constraints File | --- |
Tool Version | V1.9.9.01 (64-bit) |
Part Number | GW1NR-LV9MG100PC7/I6 |
Device | GW1NR-9 |
Device Version | C |
Created Time | Wed Mar 6 09:53:59 2024 |
Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | gw_gao |
Synthesis Process | Running parser: CPU time = 0h 0m 0.25s, Elapsed time = 0h 0m 0.259s, Peak memory usage = 105.562MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 105.562MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.028s, Peak memory usage = 105.562MB Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 105.562MB Optimizing Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.029s, Peak memory usage = 105.562MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 105.562MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 105.562MB Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 105.562MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 105.562MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.023s, Peak memory usage = 105.562MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 105.562MB Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 105.562MB Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 134.480MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.04s, Peak memory usage = 134.480MB Generate output files: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.06s, Peak memory usage = 134.480MB |
Total Time and Memory Usage | CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 134.480MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 77 |
I/O Buf | 77 |
    IBUF | 76 |
    OBUF | 1 |
Register | 523 |
    DFF | 149 |
    DFFR | 1 |
    DFFP | 3 |
    DFFPE | 33 |
    DFFC | 27 |
    DFFCE | 310 |
LUT | 457 |
    LUT2 | 38 |
    LUT3 | 105 |
    LUT4 | 314 |
MUX | 1 |
    MUX16 | 1 |
ALU | 13 |
    ALU | 13 |
INV | 4 |
    INV | 4 |
BSRAM | 4 |
    SDPX9B | 4 |
Black Box | 1 |
    GW_JTAG | 1 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 482(469 LUT, 13 ALU) / 8640 | 6% |
Register | 523 / 6741 | 8% |
  --Register as Latch | 0 / 6741 | 0% |
  --Register as FF | 523 / 6741 | 8% |
BSRAM | 4 / 26 | 16% |
Timing
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|
byte_clk | Base | 20.000 | 50.0 | 0.000 | 10.000 | byte_clk_ibuf/I | ||
u_icon_top/n19_6 | Base | 20.000 | 50.0 | 0.000 | 10.000 | u_icon_top/n19_s2/O | ||
u_la0_top/n15_6 | Base | 20.000 | 50.0 | 0.000 | 10.000 | u_la0_top/n15_s2/O |
Max Frequency Summary:
No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | byte_clk | 50.000(MHz) | 138.979(MHz) | 5 | TOP |
2 | u_icon_top/n19_6 | 50.000(MHz) | 742.178(MHz) | 1 | TOP |
3 | u_la0_top/n15_6 | 50.000(MHz) | 742.178(MHz) | 1 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | 12.805 |
Data Arrival Time | 8.164 |
Data Required Time | 20.969 |
From | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1 |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5 |
Launch Clk | byte_clk[R] |
Latch Clk | byte_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | byte_clk | |||
0.000 | 0.000 | tCL | RR | 1 | byte_clk_ibuf/I |
0.728 | 0.728 | tINS | RR | 206 | byte_clk_ibuf/O |
1.266 | 0.538 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK |
1.605 | 0.340 | tC2Q | RF | 6 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/Q |
2.317 | 0.711 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/n560_s9/I0 |
3.081 | 0.765 | tINS | FF | 1 | u_la0_top/u_ao_mem_ctrl/n560_s9/F |
3.793 | 0.711 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/n560_s6/I1 |
4.607 | 0.814 | tINS | FF | 1 | u_la0_top/u_ao_mem_ctrl/n560_s6/F |
5.318 | 0.711 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/n560_s4/I1 |
6.133 | 0.814 | tINS | FF | 11 | u_la0_top/u_ao_mem_ctrl/n560_s4/F |
6.844 | 0.711 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/n569_s3/I2 |
7.453 | 0.609 | tINS | FF | 1 | u_la0_top/u_ao_mem_ctrl/n569_s3/F |
8.164 | 0.711 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
20.000 | 0.000 | byte_clk | |||
20.000 | 0.000 | tCL | RR | 1 | byte_clk_ibuf/I |
20.728 | 0.728 | tINS | RR | 206 | byte_clk_ibuf/O |
21.266 | 0.538 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/CLK |
20.969 | -0.296 | tSu | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5 |
Clock Skew: | 0.000 |
Setup Relationship: | 20.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.728, 57.491%; route: 0.538, 42.509% |
Arrival Data Path Delay: | cell: 3.003, 43.522%; route: 3.557, 51.555%; tC2Q: 0.340, 4.923% |
Required Clock Path Delay: | cell: 0.728, 57.491%; route: 0.538, 42.509% |
Path 2
Path Summary:Slack | 12.805 |
Data Arrival Time | 8.164 |
Data Required Time | 20.969 |
From | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1 |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1 |
Launch Clk | byte_clk[R] |
Latch Clk | byte_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | byte_clk | |||
0.000 | 0.000 | tCL | RR | 1 | byte_clk_ibuf/I |
0.728 | 0.728 | tINS | RR | 206 | byte_clk_ibuf/O |
1.266 | 0.538 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK |
1.605 | 0.340 | tC2Q | RF | 6 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/Q |
2.317 | 0.711 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/n560_s9/I0 |
3.081 | 0.765 | tINS | FF | 1 | u_la0_top/u_ao_mem_ctrl/n560_s9/F |
3.793 | 0.711 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/n560_s6/I1 |
4.607 | 0.814 | tINS | FF | 1 | u_la0_top/u_ao_mem_ctrl/n560_s6/F |
5.318 | 0.711 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/n560_s4/I1 |
6.133 | 0.814 | tINS | FF | 11 | u_la0_top/u_ao_mem_ctrl/n560_s4/F |
6.844 | 0.711 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/n568_s1/I2 |
7.453 | 0.609 | tINS | FF | 1 | u_la0_top/u_ao_mem_ctrl/n568_s1/F |
8.164 | 0.711 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
20.000 | 0.000 | byte_clk | |||
20.000 | 0.000 | tCL | RR | 1 | byte_clk_ibuf/I |
20.728 | 0.728 | tINS | RR | 206 | byte_clk_ibuf/O |
21.266 | 0.538 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK |
20.969 | -0.296 | tSu | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 20.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.728, 57.491%; route: 0.538, 42.509% |
Arrival Data Path Delay: | cell: 3.003, 43.522%; route: 3.557, 51.555%; tC2Q: 0.340, 4.923% |
Required Clock Path Delay: | cell: 0.728, 57.491%; route: 0.538, 42.509% |
Path 3
Path Summary:Slack | 12.805 |
Data Arrival Time | 8.164 |
Data Required Time | 20.969 |
From | u_la0_top/capture_window_sel_0_s3 |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_9_s0 |
Launch Clk | byte_clk[R] |
Latch Clk | byte_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | byte_clk | |||
0.000 | 0.000 | tCL | RR | 1 | byte_clk_ibuf/I |
0.728 | 0.728 | tINS | RR | 206 | byte_clk_ibuf/O |
1.266 | 0.538 | tNET | RR | 1 | u_la0_top/capture_window_sel_0_s3/CLK |
1.605 | 0.340 | tC2Q | RF | 14 | u_la0_top/capture_window_sel_0_s3/Q |
2.317 | 0.711 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s18/I1 |
3.131 | 0.814 | tINS | FF | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s18/F |
3.842 | 0.711 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s15/I1 |
4.657 | 0.814 | tINS | FF | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s15/F |
5.368 | 0.711 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s12/I0 |
6.133 | 0.765 | tINS | FF | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s12/F |
6.844 | 0.711 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s10/I2 |
7.453 | 0.609 | tINS | FF | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s10/F |
8.164 | 0.711 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_9_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
20.000 | 0.000 | byte_clk | |||
20.000 | 0.000 | tCL | RR | 1 | byte_clk_ibuf/I |
20.728 | 0.728 | tINS | RR | 206 | byte_clk_ibuf/O |
21.266 | 0.538 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_9_s0/CLK |
20.969 | -0.296 | tSu | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_9_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 20.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.728, 57.491%; route: 0.538, 42.509% |
Arrival Data Path Delay: | cell: 3.003, 43.522%; route: 3.557, 51.555%; tC2Q: 0.340, 4.923% |
Required Clock Path Delay: | cell: 0.728, 57.491%; route: 0.538, 42.509% |
Path 4
Path Summary:Slack | 12.950 |
Data Arrival Time | 8.019 |
Data Required Time | 20.969 |
From | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1 |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1 |
Launch Clk | byte_clk[R] |
Latch Clk | byte_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | byte_clk | |||
0.000 | 0.000 | tCL | RR | 1 | byte_clk_ibuf/I |
0.728 | 0.728 | tINS | RR | 206 | byte_clk_ibuf/O |
1.266 | 0.538 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK |
1.605 | 0.340 | tC2Q | RF | 6 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/Q |
2.317 | 0.711 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/n560_s9/I0 |
3.081 | 0.765 | tINS | FF | 1 | u_la0_top/u_ao_mem_ctrl/n560_s9/F |
3.793 | 0.711 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/n560_s6/I1 |
4.607 | 0.814 | tINS | FF | 1 | u_la0_top/u_ao_mem_ctrl/n560_s6/F |
5.318 | 0.711 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/n560_s4/I1 |
6.133 | 0.814 | tINS | FF | 11 | u_la0_top/u_ao_mem_ctrl/n560_s4/F |
6.844 | 0.711 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/n567_s1/I3 |
7.308 | 0.464 | tINS | FF | 1 | u_la0_top/u_ao_mem_ctrl/n567_s1/F |
8.019 | 0.711 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
20.000 | 0.000 | byte_clk | |||
20.000 | 0.000 | tCL | RR | 1 | byte_clk_ibuf/I |
20.728 | 0.728 | tINS | RR | 206 | byte_clk_ibuf/O |
21.266 | 0.538 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK |
20.969 | -0.296 | tSu | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 20.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.728, 57.491%; route: 0.538, 42.509% |
Arrival Data Path Delay: | cell: 2.857, 42.307%; route: 3.557, 52.664%; tC2Q: 0.340, 5.029% |
Required Clock Path Delay: | cell: 0.728, 57.491%; route: 0.538, 42.509% |
Path 5
Path Summary:Slack | 12.950 |
Data Arrival Time | 8.019 |
Data Required Time | 20.969 |
From | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1 |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1 |
Launch Clk | byte_clk[R] |
Latch Clk | byte_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | byte_clk | |||
0.000 | 0.000 | tCL | RR | 1 | byte_clk_ibuf/I |
0.728 | 0.728 | tINS | RR | 206 | byte_clk_ibuf/O |
1.266 | 0.538 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK |
1.605 | 0.340 | tC2Q | RF | 6 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/Q |
2.317 | 0.711 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/n560_s9/I0 |
3.081 | 0.765 | tINS | FF | 1 | u_la0_top/u_ao_mem_ctrl/n560_s9/F |
3.793 | 0.711 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/n560_s6/I1 |
4.607 | 0.814 | tINS | FF | 1 | u_la0_top/u_ao_mem_ctrl/n560_s6/F |
5.318 | 0.711 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/n560_s4/I1 |
6.133 | 0.814 | tINS | FF | 11 | u_la0_top/u_ao_mem_ctrl/n560_s4/F |
6.844 | 0.711 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/n566_s1/I3 |
7.308 | 0.464 | tINS | FF | 1 | u_la0_top/u_ao_mem_ctrl/n566_s1/F |
8.019 | 0.711 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
20.000 | 0.000 | byte_clk | |||
20.000 | 0.000 | tCL | RR | 1 | byte_clk_ibuf/I |
20.728 | 0.728 | tINS | RR | 206 | byte_clk_ibuf/O |
21.266 | 0.538 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK |
20.969 | -0.296 | tSu | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 20.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.728, 57.491%; route: 0.538, 42.509% |
Arrival Data Path Delay: | cell: 2.857, 42.307%; route: 3.557, 52.664%; tC2Q: 0.340, 5.029% |
Required Clock Path Delay: | cell: 0.728, 57.491%; route: 0.538, 42.509% |