Timing Messages

Report Title Timing Analysis Report
Design File E:\myWork\IP\releaseVerify\version\1.9.11.02\Gowin_PWM_RefDesign\project\impl\gwsynthesis\fpga_project.vg
Physical Constraints File E:\myWork\IP\releaseVerify\version\1.9.11.02\Gowin_PWM_RefDesign\project\src\fpga_project.cst
Timing Constraint File E:\myWork\IP\releaseVerify\version\1.9.11.02\Gowin_PWM_RefDesign\project\src\fpga_project.sdc
Tool Version V1.9.11.02 (64-bit)
Part Number GW1N-LV9QN88C6/I5
Device GW1N-9
Device Version C
Created Time Tue Apr 15 15:23:05 2025
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model Slow 1.14V 85C C6/I5
Hold Delay Model Fast 1.26V 0C C6/I5
Numbers of Paths Analyzed 464
Numbers of Endpoints Analyzed 562
Numbers of Falling Endpoints 2
Numbers of Setup Violated Endpoints 0
Numbers of Hold Violated Endpoints 0

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Objects
1 tck_pad_i Base 50.000 20.000 0.000 25.000 tck_pad_i
2 pclk Base 10.000 100.000 0.000 5.000 u_CLKDIV/CLKOUT
3 clk Base 20.000 50.000 0.000 10.000 clk_ibuf/I
4 Gowin_PLL/rpll_inst/CLKOUT.default_gen_clk Generated 2.500 400.000 0.000 1.250 clk_ibuf/I clk Gowin_PLL/rpll_inst/CLKOUT
5 Gowin_PLL/rpll_inst/CLKOUTP.default_gen_clk Generated 2.500 400.000 0.000 1.250 clk_ibuf/I clk Gowin_PLL/rpll_inst/CLKOUTP
6 Gowin_PLL/rpll_inst/CLKOUTD.default_gen_clk Generated 5.000 200.000 0.000 2.500 clk_ibuf/I clk Gowin_PLL/rpll_inst/CLKOUTD
7 Gowin_PLL/rpll_inst/CLKOUTD3.default_gen_clk Generated 7.500 133.333 0.000 3.750 clk_ibuf/I clk Gowin_PLL/rpll_inst/CLKOUTD3

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 tck_pad_i 20.000(MHz) 67.683(MHz) 2 TOP
2 pclk 100.000(MHz) 101.889(MHz) 7 TOP

No timing paths to get frequency of clk!

No timing paths to get frequency of Gowin_PLL/rpll_inst/CLKOUT.default_gen_clk!

No timing paths to get frequency of Gowin_PLL/rpll_inst/CLKOUTP.default_gen_clk!

No timing paths to get frequency of Gowin_PLL/rpll_inst/CLKOUTD.default_gen_clk!

No timing paths to get frequency of Gowin_PLL/rpll_inst/CLKOUTD3.default_gen_clk!

Total Negative Slack Summary:

Clock Name Analysis Type Endpoints TNS Number of Endpoints
tck_pad_i Setup 0.000 0
tck_pad_i Hold 0.000 0
pclk Setup 0.000 0
pclk Hold 0.000 0
clk Setup 0.000 0
clk Hold 0.000 0
Gowin_PLL/rpll_inst/CLKOUT.default_gen_clk Setup 0.000 0
Gowin_PLL/rpll_inst/CLKOUT.default_gen_clk Hold 0.000 0
Gowin_PLL/rpll_inst/CLKOUTP.default_gen_clk Setup 0.000 0
Gowin_PLL/rpll_inst/CLKOUTP.default_gen_clk Hold 0.000 0
Gowin_PLL/rpll_inst/CLKOUTD.default_gen_clk Setup 0.000 0
Gowin_PLL/rpll_inst/CLKOUTD.default_gen_clk Hold 0.000 0
Gowin_PLL/rpll_inst/CLKOUTD3.default_gen_clk Setup 0.000 0
Gowin_PLL/rpll_inst/CLKOUTD3.default_gen_clk Hold 0.000 0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.185 dut/u_pwm/oserx8_duty_cycle_all_one_0_s0/Q dut/u_pwm/d_0_s0/D pclk:[R] pclk:[R] 10.000 0.000 9.415
2 0.261 dut/u_pwm/oserx8_duty_cycle_all_one_0_s0/Q dut/u_pwm/d_1_s0/D pclk:[R] pclk:[R] 10.000 0.000 9.339
3 1.209 dut/u_pwm/oserx8_duty_cycle_all_one_0_s0/Q dut/u_pwm/d_2_s0/D pclk:[R] pclk:[R] 10.000 0.000 8.391
4 1.284 dut/u_pwm/oserx8_duty_cycle_all_one_0_s0/Q dut/u_pwm/d_3_s0/D pclk:[R] pclk:[R] 10.000 0.000 8.316
5 1.491 dut/u_pwm/oserx8_duty_cycle_all_one_0_s0/Q dut/u_pwm/d_5_s0/D pclk:[R] pclk:[R] 10.000 0.000 8.109
6 1.625 dut/u_pwm/oserx8_duty_cycle_all_one_0_s0/Q dut/u_pwm/d_6_s0/D pclk:[R] pclk:[R] 10.000 0.000 7.975
7 1.625 dut/u_pwm/oserx8_duty_cycle_all_one_0_s0/Q dut/u_pwm/d_4_s0/D pclk:[R] pclk:[R] 10.000 0.000 7.975
8 1.728 dut/u_pwm/up_d0_s0/Q dut/u_pwm/duty_cycle_int_8_s1/D pclk:[R] pclk:[R] 10.000 0.000 7.872
9 1.865 dut/u_pwm/oserx8_cycle_1_s0/Q dut/u_pwm/oserx8_duty_cycle_all_one_1_s0/CE pclk:[R] pclk:[R] 10.000 0.000 8.092
10 1.869 dut/u_pwm/oserx8_cycle_1_s0/Q dut/u_pwm/oserx8_duty_cycle_all_one_4_s0/CE pclk:[R] pclk:[R] 10.000 0.000 8.088
11 1.869 dut/u_pwm/oserx8_cycle_1_s0/Q dut/u_pwm/oserx8_duty_cycle_all_one_3_s0/CE pclk:[R] pclk:[R] 10.000 0.000 8.088
12 2.232 dut/u_pwm/oserx8_cycle_1_s0/Q dut/u_pwm/oserx8_duty_cycle_remainder_0_s0/CE pclk:[R] pclk:[R] 10.000 0.000 7.725
13 2.232 dut/u_pwm/oserx8_cycle_1_s0/Q dut/u_pwm/oserx8_duty_cycle_remainder_1_s0/CE pclk:[R] pclk:[R] 10.000 0.000 7.725
14 2.232 dut/u_pwm/oserx8_cycle_1_s0/Q dut/u_pwm/oserx8_duty_cycle_remainder_2_s0/CE pclk:[R] pclk:[R] 10.000 0.000 7.725
15 2.232 dut/u_pwm/oserx8_cycle_1_s0/Q dut/u_pwm/oserx8_cycle_2_s0/CE pclk:[R] pclk:[R] 10.000 0.000 7.725
16 2.236 dut/u_pwm/oserx8_cycle_1_s0/Q dut/u_pwm/oserx8_duty_cycle_all_one_2_s0/CE pclk:[R] pclk:[R] 10.000 0.000 7.721
17 2.236 dut/u_pwm/oserx8_cycle_1_s0/Q dut/u_pwm/oserx8_duty_cycle_all_one_5_s0/CE pclk:[R] pclk:[R] 10.000 0.000 7.721
18 2.311 dut/u_pwm/oserx8_cycle_1_s0/Q dut/u_pwm/oserx8_cycle_1_s0/CE pclk:[R] pclk:[R] 10.000 0.000 7.645
19 2.311 dut/u_pwm/oserx8_cycle_1_s0/Q dut/u_pwm/oserx8_cycle_4_s0/CE pclk:[R] pclk:[R] 10.000 0.000 7.645
20 2.311 dut/u_pwm/oserx8_cycle_1_s0/Q dut/u_pwm/oserx8_cycle_5_s0/CE pclk:[R] pclk:[R] 10.000 0.000 7.645
21 2.319 dut/u_pwm/oserx8_cycle_1_s0/Q dut/u_pwm/oserx8_cycle_6_s0/CE pclk:[R] pclk:[R] 10.000 0.000 7.638
22 2.319 dut/u_pwm/oserx8_cycle_1_s0/Q dut/u_pwm/oserx8_duty_cycle_all_one_6_s0/CE pclk:[R] pclk:[R] 10.000 0.000 7.638
23 2.319 dut/u_pwm/oserx8_cycle_1_s0/Q dut/u_pwm/oserx8_duty_cycle_all_one_0_s0/CE pclk:[R] pclk:[R] 10.000 0.000 7.638
24 2.453 dut/u_pwm/oserx8_duty_cycle_all_one_0_s0/Q dut/u_pwm/d_7_s0/D pclk:[R] pclk:[R] 10.000 0.000 7.147
25 2.573 dut/u_pwm/duty_cycle_int_2_s1/Q dut/u_pwm/duty_cycle_int_5_s1/CE pclk:[R] pclk:[R] 10.000 0.000 7.384

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.582 gw_gvio_inst_0/u_gvio0_top/probe_out6_reg1_0_s2/Q gw_gvio_inst_0/u_gvio0_top/probe_out6_reg1_0_s6/AD[0] pclk:[R] pclk:[R] 0.000 0.000 0.595
2 0.708 gw_gvio_inst_0/u_gvio0_top/addr_all_7_s1/Q gw_gvio_inst_0/u_gvio0_top/addr_all_7_s1/D tck_pad_i:[R] tck_pad_i:[R] 0.000 0.000 0.708
3 0.708 gw_gvio_inst_0/u_gvio0_top/word_count_3_s0/Q gw_gvio_inst_0/u_gvio0_top/word_count_3_s0/D tck_pad_i:[R] tck_pad_i:[R] 0.000 0.000 0.708
4 0.708 gw_gvio_inst_0/u_gvio0_top/word_count_5_s0/Q gw_gvio_inst_0/u_gvio0_top/word_count_5_s0/D tck_pad_i:[R] tck_pad_i:[R] 0.000 0.000 0.708
5 0.708 gw_gvio_inst_0/u_gvio0_top/word_count_6_s0/Q gw_gvio_inst_0/u_gvio0_top/word_count_6_s0/D tck_pad_i:[R] tck_pad_i:[R] 0.000 0.000 0.708
6 0.708 gw_gvio_inst_0/u_gvio0_top/word_count_11_s0/Q gw_gvio_inst_0/u_gvio0_top/word_count_11_s0/D tck_pad_i:[R] tck_pad_i:[R] 0.000 0.000 0.708
7 0.709 gw_gvio_inst_0/u_gvio0_top/bit_count_3_s1/Q gw_gvio_inst_0/u_gvio0_top/bit_count_3_s1/D tck_pad_i:[R] tck_pad_i:[R] 0.000 0.000 0.709
8 0.709 gw_gvio_inst_0/u_gvio0_top/bit_count_6_s1/Q gw_gvio_inst_0/u_gvio0_top/bit_count_6_s1/D tck_pad_i:[R] tck_pad_i:[R] 0.000 0.000 0.709
9 0.709 gw_gvio_inst_0/u_gvio0_top/word_count_0_s0/Q gw_gvio_inst_0/u_gvio0_top/word_count_0_s0/D tck_pad_i:[R] tck_pad_i:[R] 0.000 0.000 0.709
10 0.709 gw_gvio_inst_0/u_gvio0_top/word_count_8_s0/Q gw_gvio_inst_0/u_gvio0_top/word_count_8_s0/D tck_pad_i:[R] tck_pad_i:[R] 0.000 0.000 0.709
11 0.709 gw_gvio_inst_0/u_gvio0_top/word_count_13_s0/Q gw_gvio_inst_0/u_gvio0_top/word_count_13_s0/D tck_pad_i:[R] tck_pad_i:[R] 0.000 0.000 0.709
12 0.710 gw_gvio_inst_0/u_gvio0_top/addr_all_5_s1/Q gw_gvio_inst_0/u_gvio0_top/addr_all_5_s1/D tck_pad_i:[R] tck_pad_i:[R] 0.000 0.000 0.710
13 0.711 gw_gvio_inst_0/u_gvio0_top/addr_all_3_s1/Q gw_gvio_inst_0/u_gvio0_top/addr_all_3_s1/D tck_pad_i:[R] tck_pad_i:[R] 0.000 0.000 0.711
14 0.711 gw_gvio_inst_0/u_gvio0_top/module_state_0_s0/Q gw_gvio_inst_0/u_gvio0_top/module_state_0_s0/D tck_pad_i:[R] tck_pad_i:[R] 0.000 0.000 0.711
15 0.711 gw_gvio_inst_0/u_gvio0_top/module_state_1_s0/Q gw_gvio_inst_0/u_gvio0_top/module_state_1_s0/D tck_pad_i:[R] tck_pad_i:[R] 0.000 0.000 0.711
16 0.711 dut/u_pwm/cnt_0_s0/Q dut/u_pwm/cnt_0_s0/D pclk:[R] pclk:[R] 0.000 0.000 0.711
17 0.712 gw_gvio_inst_0/u_gvio0_top/probe_out6_reg1_0_s2/Q gw_gvio_inst_0/u_gvio0_top/probe_out6_reg1_0_s2/D pclk:[R] pclk:[R] 0.000 0.000 0.712
18 0.731 dut/u_pwm/cnt_6_s0/Q dut/u_pwm/cnt_6_s0/D pclk:[R] pclk:[R] 0.000 0.000 0.731
19 0.733 dut/u_pwm/cnt_4_s0/Q dut/u_pwm/cnt_4_s0/D pclk:[R] pclk:[R] 0.000 0.000 0.733
20 0.837 gw_gvio_inst_0/u_gvio0_top/probe_out6_reg1_0_s2/Q gw_gvio_inst_0/u_gvio0_top/probe_out6_reg1_0_s8/AD[0] pclk:[R] pclk:[R] 0.000 0.000 0.849
21 0.854 dut/u_pwm/cnt_1_s0/Q dut/u_pwm/cnt_1_s0/D pclk:[R] pclk:[R] 0.000 0.000 0.854
22 0.869 dut/u_pwm/d_5_s0/Q dut/u_pwm/u_OSER8/D5 pclk:[R] pclk:[R] 0.000 0.000 0.881
23 0.869 dut/u_pwm/d_3_s0/Q dut/u_pwm/u_OSER8/D3 pclk:[R] pclk:[R] 0.000 0.000 0.881
24 0.892 gw_gvio_inst_0/u_gvio0_top/bit_count_4_s1/Q gw_gvio_inst_0/u_gvio0_top/bit_count_4_s1/D tck_pad_i:[R] tck_pad_i:[R] 0.000 0.000 0.892
25 0.894 gw_gvio_inst_0/u_gvio0_top/bit_count_2_s1/Q gw_gvio_inst_0/u_gvio0_top/bit_count_2_s1/D tck_pad_i:[R] tck_pad_i:[R] 0.000 0.000 0.894

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Nothing to report!

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Nothing to report!

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number Slack Actual Width Required Width Type Clock Objects
1 3.676 4.926 1.250 Low Pulse Width pclk gw_gvio_inst_0/u_gvio0_top/probe_out0_reg1_0_s0
2 3.676 4.926 1.250 Low Pulse Width pclk gw_gvio_inst_0/u_gvio0_top/probe_out1_reg1_1_s0
3 3.676 4.926 1.250 Low Pulse Width pclk gw_gvio_inst_0/u_gvio0_top/probe_out2_reg1_9_s0
4 3.676 4.926 1.250 Low Pulse Width pclk gw_gvio_inst_0/u_gvio0_top/probe_out2_reg2_8_s0
5 3.676 4.926 1.250 Low Pulse Width pclk dut/u_pwm/down_d1_s0
6 3.676 4.926 1.250 Low Pulse Width pclk dut/u_pwm/d_3_s0
7 3.676 4.926 1.250 Low Pulse Width pclk dut/u_pwm/d_4_s0
8 3.676 4.926 1.250 Low Pulse Width pclk dut/u_pwm/down_d0_s0
9 3.676 4.926 1.250 Low Pulse Width pclk dut/u_pwm/d_5_s0
10 3.676 4.926 1.250 Low Pulse Width pclk dut/u_pwm/d_6_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 0.185
Data Arrival Time 9.657
Data Required Time 9.842
From dut/u_pwm/oserx8_duty_cycle_all_one_0_s0
To dut/u_pwm/d_0_s0
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 92 BOTTOMSIDE[0] u_CLKDIV/CLKOUT
0.242 0.242 tNET RR 1 R21C6[1][B] dut/u_pwm/oserx8_duty_cycle_all_one_0_s0/CLK
0.700 0.458 tC2Q RF 2 R21C6[1][B] dut/u_pwm/oserx8_duty_cycle_all_one_0_s0/Q
3.284 2.583 tNET FF 2 R18C6[0][B] dut/u_pwm/n278_s14/CIN
3.341 0.057 tINS FF 1 R18C6[0][B] dut/u_pwm/n278_s14/COUT
3.341 0.000 tNET FF 2 R18C6[1][A] dut/u_pwm/n278_s15/CIN
3.398 0.057 tINS FF 1 R18C6[1][A] dut/u_pwm/n278_s15/COUT
3.398 0.000 tNET FF 2 R18C6[1][B] dut/u_pwm/n278_s16/CIN
3.455 0.057 tINS FF 1 R18C6[1][B] dut/u_pwm/n278_s16/COUT
3.455 0.000 tNET FF 2 R18C6[2][A] dut/u_pwm/n278_s17/CIN
3.512 0.057 tINS FF 1 R18C6[2][A] dut/u_pwm/n278_s17/COUT
3.512 0.000 tNET FF 2 R18C6[2][B] dut/u_pwm/n278_s18/CIN
3.569 0.057 tINS FF 1 R18C6[2][B] dut/u_pwm/n278_s18/COUT
3.569 0.000 tNET FF 2 R18C7[0][A] dut/u_pwm/n278_s19/CIN
3.626 0.057 tINS FF 1 R18C7[0][A] dut/u_pwm/n278_s19/COUT
4.194 0.568 tNET FF 1 R18C7[3][B] dut/u_pwm/n278_s20/I2
5.293 1.099 tINS FF 4 R18C7[3][B] dut/u_pwm/n278_s20/F
6.763 1.470 tNET FF 1 R24C8[3][B] dut/u_pwm/n335_s1/I2
7.565 0.802 tINS FR 3 R24C8[3][B] dut/u_pwm/n335_s1/F
7.988 0.423 tNET RR 1 R24C7[3][B] dut/u_pwm/n337_s1/I2
8.614 0.626 tINS RF 2 R24C7[3][B] dut/u_pwm/n337_s1/F
8.625 0.011 tNET FF 1 R24C7[0][A] dut/u_pwm/n338_s1/I2
9.657 1.032 tINS FF 1 R24C7[0][A] dut/u_pwm/n338_s1/F
9.657 0.000 tNET FF 1 R24C7[0][A] dut/u_pwm/d_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 pclk
10.000 0.000 tCL RR 92 BOTTOMSIDE[0] u_CLKDIV/CLKOUT
10.242 0.242 tNET RR 1 R24C7[0][A] dut/u_pwm/d_0_s0/CLK
9.842 -0.400 tSu 1 R24C7[0][A] dut/u_pwm/d_0_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay cell: 3.901, 41.436%; route: 5.055, 53.696%; tC2Q: 0.458, 4.868%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path2

Path Summary:

Slack 0.261
Data Arrival Time 9.581
Data Required Time 9.842
From dut/u_pwm/oserx8_duty_cycle_all_one_0_s0
To dut/u_pwm/d_1_s0
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 92 BOTTOMSIDE[0] u_CLKDIV/CLKOUT
0.242 0.242 tNET RR 1 R21C6[1][B] dut/u_pwm/oserx8_duty_cycle_all_one_0_s0/CLK
0.700 0.458 tC2Q RF 2 R21C6[1][B] dut/u_pwm/oserx8_duty_cycle_all_one_0_s0/Q
3.284 2.583 tNET FF 2 R18C6[0][B] dut/u_pwm/n278_s14/CIN
3.341 0.057 tINS FF 1 R18C6[0][B] dut/u_pwm/n278_s14/COUT
3.341 0.000 tNET FF 2 R18C6[1][A] dut/u_pwm/n278_s15/CIN
3.398 0.057 tINS FF 1 R18C6[1][A] dut/u_pwm/n278_s15/COUT
3.398 0.000 tNET FF 2 R18C6[1][B] dut/u_pwm/n278_s16/CIN
3.455 0.057 tINS FF 1 R18C6[1][B] dut/u_pwm/n278_s16/COUT
3.455 0.000 tNET FF 2 R18C6[2][A] dut/u_pwm/n278_s17/CIN
3.512 0.057 tINS FF 1 R18C6[2][A] dut/u_pwm/n278_s17/COUT
3.512 0.000 tNET FF 2 R18C6[2][B] dut/u_pwm/n278_s18/CIN
3.569 0.057 tINS FF 1 R18C6[2][B] dut/u_pwm/n278_s18/COUT
3.569 0.000 tNET FF 2 R18C7[0][A] dut/u_pwm/n278_s19/CIN
3.626 0.057 tINS FF 1 R18C7[0][A] dut/u_pwm/n278_s19/COUT
4.194 0.568 tNET FF 1 R18C7[3][B] dut/u_pwm/n278_s20/I2
5.293 1.099 tINS FF 4 R18C7[3][B] dut/u_pwm/n278_s20/F
6.763 1.470 tNET FF 1 R24C8[3][B] dut/u_pwm/n335_s1/I2
7.565 0.802 tINS FR 3 R24C8[3][B] dut/u_pwm/n335_s1/F
7.988 0.423 tNET RR 1 R24C7[3][B] dut/u_pwm/n337_s1/I2
8.614 0.626 tINS RF 2 R24C7[3][B] dut/u_pwm/n337_s1/F
9.581 0.968 tNET FF 1 R24C7[0][B] dut/u_pwm/d_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 pclk
10.000 0.000 tCL RR 92 BOTTOMSIDE[0] u_CLKDIV/CLKOUT
10.242 0.242 tNET RR 1 R24C7[0][B] dut/u_pwm/d_1_s0/CLK
9.842 -0.400 tSu 1 R24C7[0][B] dut/u_pwm/d_1_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay cell: 2.869, 30.719%; route: 6.012, 64.373%; tC2Q: 0.458, 4.908%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path3

Path Summary:

Slack 1.209
Data Arrival Time 8.633
Data Required Time 9.842
From dut/u_pwm/oserx8_duty_cycle_all_one_0_s0
To dut/u_pwm/d_2_s0
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 92 BOTTOMSIDE[0] u_CLKDIV/CLKOUT
0.242 0.242 tNET RR 1 R21C6[1][B] dut/u_pwm/oserx8_duty_cycle_all_one_0_s0/CLK
0.700 0.458 tC2Q RF 2 R21C6[1][B] dut/u_pwm/oserx8_duty_cycle_all_one_0_s0/Q
3.284 2.583 tNET FF 2 R18C6[0][B] dut/u_pwm/n278_s14/CIN
3.341 0.057 tINS FF 1 R18C6[0][B] dut/u_pwm/n278_s14/COUT
3.341 0.000 tNET FF 2 R18C6[1][A] dut/u_pwm/n278_s15/CIN
3.398 0.057 tINS FF 1 R18C6[1][A] dut/u_pwm/n278_s15/COUT
3.398 0.000 tNET FF 2 R18C6[1][B] dut/u_pwm/n278_s16/CIN
3.455 0.057 tINS FF 1 R18C6[1][B] dut/u_pwm/n278_s16/COUT
3.455 0.000 tNET FF 2 R18C6[2][A] dut/u_pwm/n278_s17/CIN
3.512 0.057 tINS FF 1 R18C6[2][A] dut/u_pwm/n278_s17/COUT
3.512 0.000 tNET FF 2 R18C6[2][B] dut/u_pwm/n278_s18/CIN
3.569 0.057 tINS FF 1 R18C6[2][B] dut/u_pwm/n278_s18/COUT
3.569 0.000 tNET FF 2 R18C7[0][A] dut/u_pwm/n278_s19/CIN
3.626 0.057 tINS FF 1 R18C7[0][A] dut/u_pwm/n278_s19/COUT
4.194 0.568 tNET FF 1 R18C7[3][B] dut/u_pwm/n278_s20/I2
5.293 1.099 tINS FF 4 R18C7[3][B] dut/u_pwm/n278_s20/F
6.763 1.470 tNET FF 1 R24C8[3][B] dut/u_pwm/n335_s1/I2
7.585 0.822 tINS FF 3 R24C8[3][B] dut/u_pwm/n335_s1/F
7.601 0.016 tNET FF 1 R24C8[1][A] dut/u_pwm/n336_s1/I3
8.633 1.032 tINS FF 1 R24C8[1][A] dut/u_pwm/n336_s1/F
8.633 0.000 tNET FF 1 R24C8[1][A] dut/u_pwm/d_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 pclk
10.000 0.000 tCL RR 92 BOTTOMSIDE[0] u_CLKDIV/CLKOUT
10.242 0.242 tNET RR 1 R24C8[1][A] dut/u_pwm/d_2_s0/CLK
9.842 -0.400 tSu 1 R24C8[1][A] dut/u_pwm/d_2_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay cell: 3.295, 39.267%; route: 4.638, 55.271%; tC2Q: 0.458, 5.462%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path4

Path Summary:

Slack 1.284
Data Arrival Time 8.558
Data Required Time 9.842
From dut/u_pwm/oserx8_duty_cycle_all_one_0_s0
To dut/u_pwm/d_3_s0
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 92 BOTTOMSIDE[0] u_CLKDIV/CLKOUT
0.242 0.242 tNET RR 1 R21C6[1][B] dut/u_pwm/oserx8_duty_cycle_all_one_0_s0/CLK
0.700 0.458 tC2Q RF 2 R21C6[1][B] dut/u_pwm/oserx8_duty_cycle_all_one_0_s0/Q
3.284 2.583 tNET FF 2 R18C6[0][B] dut/u_pwm/n278_s14/CIN
3.341 0.057 tINS FF 1 R18C6[0][B] dut/u_pwm/n278_s14/COUT
3.341 0.000 tNET FF 2 R18C6[1][A] dut/u_pwm/n278_s15/CIN
3.398 0.057 tINS FF 1 R18C6[1][A] dut/u_pwm/n278_s15/COUT
3.398 0.000 tNET FF 2 R18C6[1][B] dut/u_pwm/n278_s16/CIN
3.455 0.057 tINS FF 1 R18C6[1][B] dut/u_pwm/n278_s16/COUT
3.455 0.000 tNET FF 2 R18C6[2][A] dut/u_pwm/n278_s17/CIN
3.512 0.057 tINS FF 1 R18C6[2][A] dut/u_pwm/n278_s17/COUT
3.512 0.000 tNET FF 2 R18C6[2][B] dut/u_pwm/n278_s18/CIN
3.569 0.057 tINS FF 1 R18C6[2][B] dut/u_pwm/n278_s18/COUT
3.569 0.000 tNET FF 2 R18C7[0][A] dut/u_pwm/n278_s19/CIN
3.626 0.057 tINS FF 1 R18C7[0][A] dut/u_pwm/n278_s19/COUT
4.194 0.568 tNET FF 1 R18C7[3][B] dut/u_pwm/n278_s20/I2
5.293 1.099 tINS FF 4 R18C7[3][B] dut/u_pwm/n278_s20/F
6.763 1.470 tNET FF 1 R24C8[3][B] dut/u_pwm/n335_s1/I2
7.585 0.822 tINS FF 3 R24C8[3][B] dut/u_pwm/n335_s1/F
8.558 0.973 tNET FF 1 R24C8[2][B] dut/u_pwm/d_3_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 pclk
10.000 0.000 tCL RR 92 BOTTOMSIDE[0] u_CLKDIV/CLKOUT
10.242 0.242 tNET RR 1 R24C8[2][B] dut/u_pwm/d_3_s0/CLK
9.842 -0.400 tSu 1 R24C8[2][B] dut/u_pwm/d_3_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay cell: 2.263, 27.212%; route: 5.595, 67.276%; tC2Q: 0.458, 5.511%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path5

Path Summary:

Slack 1.491
Data Arrival Time 8.351
Data Required Time 9.842
From dut/u_pwm/oserx8_duty_cycle_all_one_0_s0
To dut/u_pwm/d_5_s0
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 92 BOTTOMSIDE[0] u_CLKDIV/CLKOUT
0.242 0.242 tNET RR 1 R21C6[1][B] dut/u_pwm/oserx8_duty_cycle_all_one_0_s0/CLK
0.700 0.458 tC2Q RF 2 R21C6[1][B] dut/u_pwm/oserx8_duty_cycle_all_one_0_s0/Q
3.284 2.583 tNET FF 2 R18C6[0][B] dut/u_pwm/n278_s14/CIN
3.341 0.057 tINS FF 1 R18C6[0][B] dut/u_pwm/n278_s14/COUT
3.341 0.000 tNET FF 2 R18C6[1][A] dut/u_pwm/n278_s15/CIN
3.398 0.057 tINS FF 1 R18C6[1][A] dut/u_pwm/n278_s15/COUT
3.398 0.000 tNET FF 2 R18C6[1][B] dut/u_pwm/n278_s16/CIN
3.455 0.057 tINS FF 1 R18C6[1][B] dut/u_pwm/n278_s16/COUT
3.455 0.000 tNET FF 2 R18C6[2][A] dut/u_pwm/n278_s17/CIN
3.512 0.057 tINS FF 1 R18C6[2][A] dut/u_pwm/n278_s17/COUT
3.512 0.000 tNET FF 2 R18C6[2][B] dut/u_pwm/n278_s18/CIN
3.569 0.057 tINS FF 1 R18C6[2][B] dut/u_pwm/n278_s18/COUT
3.569 0.000 tNET FF 2 R18C7[0][A] dut/u_pwm/n278_s19/CIN
3.626 0.057 tINS FF 1 R18C7[0][A] dut/u_pwm/n278_s19/COUT
4.194 0.568 tNET FF 1 R18C7[3][B] dut/u_pwm/n278_s20/I2
5.293 1.099 tINS FF 4 R18C7[3][B] dut/u_pwm/n278_s20/F
6.752 1.459 tNET FF 1 R24C8[3][A] dut/u_pwm/n333_s1/I3
7.378 0.626 tINS FF 3 R24C8[3][A] dut/u_pwm/n333_s1/F
8.351 0.973 tNET FF 1 R24C8[2][A] dut/u_pwm/d_5_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 pclk
10.000 0.000 tCL RR 92 BOTTOMSIDE[0] u_CLKDIV/CLKOUT
10.242 0.242 tNET RR 1 R24C8[2][A] dut/u_pwm/d_5_s0/CLK
9.842 -0.400 tSu 1 R24C8[2][A] dut/u_pwm/d_5_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay cell: 2.067, 25.489%; route: 5.584, 68.859%; tC2Q: 0.458, 5.652%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path6

Path Summary:

Slack 1.625
Data Arrival Time 8.217
Data Required Time 9.842
From dut/u_pwm/oserx8_duty_cycle_all_one_0_s0
To dut/u_pwm/d_6_s0
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 92 BOTTOMSIDE[0] u_CLKDIV/CLKOUT
0.242 0.242 tNET RR 1 R21C6[1][B] dut/u_pwm/oserx8_duty_cycle_all_one_0_s0/CLK
0.700 0.458 tC2Q RF 2 R21C6[1][B] dut/u_pwm/oserx8_duty_cycle_all_one_0_s0/Q
3.284 2.583 tNET FF 2 R18C6[0][B] dut/u_pwm/n278_s14/CIN
3.341 0.057 tINS FF 1 R18C6[0][B] dut/u_pwm/n278_s14/COUT
3.341 0.000 tNET FF 2 R18C6[1][A] dut/u_pwm/n278_s15/CIN
3.398 0.057 tINS FF 1 R18C6[1][A] dut/u_pwm/n278_s15/COUT
3.398 0.000 tNET FF 2 R18C6[1][B] dut/u_pwm/n278_s16/CIN
3.455 0.057 tINS FF 1 R18C6[1][B] dut/u_pwm/n278_s16/COUT
3.455 0.000 tNET FF 2 R18C6[2][A] dut/u_pwm/n278_s17/CIN
3.512 0.057 tINS FF 1 R18C6[2][A] dut/u_pwm/n278_s17/COUT
3.512 0.000 tNET FF 2 R18C6[2][B] dut/u_pwm/n278_s18/CIN
3.569 0.057 tINS FF 1 R18C6[2][B] dut/u_pwm/n278_s18/COUT
3.569 0.000 tNET FF 2 R18C7[0][A] dut/u_pwm/n278_s19/CIN
3.626 0.057 tINS FF 1 R18C7[0][A] dut/u_pwm/n278_s19/COUT
4.194 0.568 tNET FF 1 R18C7[3][B] dut/u_pwm/n278_s20/I2
5.293 1.099 tINS FF 4 R18C7[3][B] dut/u_pwm/n278_s20/F
6.752 1.459 tNET FF 1 R24C8[3][A] dut/u_pwm/n333_s1/I3
7.378 0.626 tINS FF 3 R24C8[3][A] dut/u_pwm/n333_s1/F
7.395 0.016 tNET FF 1 R24C8[0][B] dut/u_pwm/n332_s1/I2
8.217 0.822 tINS FF 1 R24C8[0][B] dut/u_pwm/n332_s1/F
8.217 0.000 tNET FF 1 R24C8[0][B] dut/u_pwm/d_6_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 pclk
10.000 0.000 tCL RR 92 BOTTOMSIDE[0] u_CLKDIV/CLKOUT
10.242 0.242 tNET RR 1 R24C8[0][B] dut/u_pwm/d_6_s0/CLK
9.842 -0.400 tSu 1 R24C8[0][B] dut/u_pwm/d_6_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay cell: 2.889, 36.227%; route: 4.627, 58.025%; tC2Q: 0.458, 5.747%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path7

Path Summary:

Slack 1.625
Data Arrival Time 8.217
Data Required Time 9.842
From dut/u_pwm/oserx8_duty_cycle_all_one_0_s0
To dut/u_pwm/d_4_s0
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 92 BOTTOMSIDE[0] u_CLKDIV/CLKOUT
0.242 0.242 tNET RR 1 R21C6[1][B] dut/u_pwm/oserx8_duty_cycle_all_one_0_s0/CLK
0.700 0.458 tC2Q RF 2 R21C6[1][B] dut/u_pwm/oserx8_duty_cycle_all_one_0_s0/Q
3.284 2.583 tNET FF 2 R18C6[0][B] dut/u_pwm/n278_s14/CIN
3.341 0.057 tINS FF 1 R18C6[0][B] dut/u_pwm/n278_s14/COUT
3.341 0.000 tNET FF 2 R18C6[1][A] dut/u_pwm/n278_s15/CIN
3.398 0.057 tINS FF 1 R18C6[1][A] dut/u_pwm/n278_s15/COUT
3.398 0.000 tNET FF 2 R18C6[1][B] dut/u_pwm/n278_s16/CIN
3.455 0.057 tINS FF 1 R18C6[1][B] dut/u_pwm/n278_s16/COUT
3.455 0.000 tNET FF 2 R18C6[2][A] dut/u_pwm/n278_s17/CIN
3.512 0.057 tINS FF 1 R18C6[2][A] dut/u_pwm/n278_s17/COUT
3.512 0.000 tNET FF 2 R18C6[2][B] dut/u_pwm/n278_s18/CIN
3.569 0.057 tINS FF 1 R18C6[2][B] dut/u_pwm/n278_s18/COUT
3.569 0.000 tNET FF 2 R18C7[0][A] dut/u_pwm/n278_s19/CIN
3.626 0.057 tINS FF 1 R18C7[0][A] dut/u_pwm/n278_s19/COUT
4.194 0.568 tNET FF 1 R18C7[3][B] dut/u_pwm/n278_s20/I2
5.293 1.099 tINS FF 4 R18C7[3][B] dut/u_pwm/n278_s20/F
6.752 1.459 tNET FF 1 R24C8[3][A] dut/u_pwm/n333_s1/I3
7.378 0.626 tINS FF 3 R24C8[3][A] dut/u_pwm/n333_s1/F
7.395 0.016 tNET FF 1 R24C8[0][A] dut/u_pwm/n334_s1/I3
8.217 0.822 tINS FF 1 R24C8[0][A] dut/u_pwm/n334_s1/F
8.217 0.000 tNET FF 1 R24C8[0][A] dut/u_pwm/d_4_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 pclk
10.000 0.000 tCL RR 92 BOTTOMSIDE[0] u_CLKDIV/CLKOUT
10.242 0.242 tNET RR 1 R24C8[0][A] dut/u_pwm/d_4_s0/CLK
9.842 -0.400 tSu 1 R24C8[0][A] dut/u_pwm/d_4_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay cell: 2.889, 36.227%; route: 4.627, 58.025%; tC2Q: 0.458, 5.747%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path8

Path Summary:

Slack 1.728
Data Arrival Time 8.114
Data Required Time 9.842
From dut/u_pwm/up_d0_s0
To dut/u_pwm/duty_cycle_int_8_s1
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 92 BOTTOMSIDE[0] u_CLKDIV/CLKOUT
0.242 0.242 tNET RR 1 R18C11[0][B] dut/u_pwm/up_d0_s0/CLK
0.700 0.458 tC2Q RF 8 R18C11[0][B] dut/u_pwm/up_d0_s0/Q
2.342 1.641 tNET FF 1 R22C10[3][A] dut/u_pwm/duty_cycle_int_9_s6/I1
2.968 0.626 tINS FF 10 R22C10[3][A] dut/u_pwm/duty_cycle_int_9_s6/F
4.293 1.325 tNET FF 1 R18C10[0][A] dut/u_pwm/n66_s2/I3
5.325 1.032 tINS FF 1 R18C10[0][A] dut/u_pwm/n66_s2/F
6.464 1.139 tNET FF 1 R22C10[2][A] dut/u_pwm/n66_s1/I2
7.286 0.822 tINS FF 1 R22C10[2][A] dut/u_pwm/n66_s1/F
7.292 0.005 tNET FF 1 R22C10[1][A] dut/u_pwm/n66_s6/I1
8.114 0.822 tINS FF 1 R22C10[1][A] dut/u_pwm/n66_s6/F
8.114 0.000 tNET FF 1 R22C10[1][A] dut/u_pwm/duty_cycle_int_8_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 pclk
10.000 0.000 tCL RR 92 BOTTOMSIDE[0] u_CLKDIV/CLKOUT
10.242 0.242 tNET RR 1 R22C10[1][A] dut/u_pwm/duty_cycle_int_8_s1/CLK
9.842 -0.400 tSu 1 R22C10[1][A] dut/u_pwm/duty_cycle_int_8_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay cell: 3.302, 41.947%; route: 4.111, 52.230%; tC2Q: 0.458, 5.822%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path9

Path Summary:

Slack 1.865
Data Arrival Time 8.334
Data Required Time 10.199
From dut/u_pwm/oserx8_cycle_1_s0
To dut/u_pwm/oserx8_duty_cycle_all_one_1_s0
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 92 BOTTOMSIDE[0] u_CLKDIV/CLKOUT
0.242 0.242 tNET RR 1 R21C8[0][A] dut/u_pwm/oserx8_cycle_1_s0/CLK
0.700 0.458 tC2Q RF 5 R21C8[0][A] dut/u_pwm/oserx8_cycle_1_s0/Q
1.528 0.828 tNET FF 1 R21C7[3][A] dut/u_pwm/n156_s4/I1
2.554 1.026 tINS FR 5 R21C7[3][A] dut/u_pwm/n156_s4/F
2.987 0.433 tNET RR 1 R21C8[3][B] dut/u_pwm/n156_s8/I2
4.019 1.032 tINS RF 3 R21C8[3][B] dut/u_pwm/n156_s8/F
5.319 1.300 tNET FF 1 R20C7[2][B] dut/u_pwm/n156_s3/I1
5.944 0.625 tINS FR 1 R20C7[2][B] dut/u_pwm/n156_s3/F
6.362 0.419 tNET RR 1 R21C7[0][A] dut/u_pwm/n156_s0/I2
7.164 0.802 tINS RR 17 R21C7[0][A] dut/u_pwm/n156_s0/F
8.334 1.170 tNET RR 1 R18C9[1][A] dut/u_pwm/oserx8_duty_cycle_all_one_1_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 pclk
10.000 0.000 tCL RR 92 BOTTOMSIDE[0] u_CLKDIV/CLKOUT
10.242 0.242 tNET RR 1 R18C9[1][A] dut/u_pwm/oserx8_duty_cycle_all_one_1_s0/CLK
10.199 -0.043 tSu 1 R18C9[1][A] dut/u_pwm/oserx8_duty_cycle_all_one_1_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay cell: 3.485, 43.067%; route: 4.149, 51.269%; tC2Q: 0.458, 5.664%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path10

Path Summary:

Slack 1.869
Data Arrival Time 8.330
Data Required Time 10.199
From dut/u_pwm/oserx8_cycle_1_s0
To dut/u_pwm/oserx8_duty_cycle_all_one_4_s0
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 92 BOTTOMSIDE[0] u_CLKDIV/CLKOUT
0.242 0.242 tNET RR 1 R21C8[0][A] dut/u_pwm/oserx8_cycle_1_s0/CLK
0.700 0.458 tC2Q RF 5 R21C8[0][A] dut/u_pwm/oserx8_cycle_1_s0/Q
1.528 0.828 tNET FF 1 R21C7[3][A] dut/u_pwm/n156_s4/I1
2.554 1.026 tINS FR 5 R21C7[3][A] dut/u_pwm/n156_s4/F
2.987 0.433 tNET RR 1 R21C8[3][B] dut/u_pwm/n156_s8/I2
4.019 1.032 tINS RF 3 R21C8[3][B] dut/u_pwm/n156_s8/F
5.319 1.300 tNET FF 1 R20C7[2][B] dut/u_pwm/n156_s3/I1
5.944 0.625 tINS FR 1 R20C7[2][B] dut/u_pwm/n156_s3/F
6.362 0.419 tNET RR 1 R21C7[0][A] dut/u_pwm/n156_s0/I2
7.164 0.802 tINS RR 17 R21C7[0][A] dut/u_pwm/n156_s0/F
8.330 1.166 tNET RR 1 R18C8[2][A] dut/u_pwm/oserx8_duty_cycle_all_one_4_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 pclk
10.000 0.000 tCL RR 92 BOTTOMSIDE[0] u_CLKDIV/CLKOUT
10.242 0.242 tNET RR 1 R18C8[2][A] dut/u_pwm/oserx8_duty_cycle_all_one_4_s0/CLK
10.199 -0.043 tSu 1 R18C8[2][A] dut/u_pwm/oserx8_duty_cycle_all_one_4_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay cell: 3.485, 43.088%; route: 4.145, 51.245%; tC2Q: 0.458, 5.667%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path11

Path Summary:

Slack 1.869
Data Arrival Time 8.330
Data Required Time 10.199
From dut/u_pwm/oserx8_cycle_1_s0
To dut/u_pwm/oserx8_duty_cycle_all_one_3_s0
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 92 BOTTOMSIDE[0] u_CLKDIV/CLKOUT
0.242 0.242 tNET RR 1 R21C8[0][A] dut/u_pwm/oserx8_cycle_1_s0/CLK
0.700 0.458 tC2Q RF 5 R21C8[0][A] dut/u_pwm/oserx8_cycle_1_s0/Q
1.528 0.828 tNET FF 1 R21C7[3][A] dut/u_pwm/n156_s4/I1
2.554 1.026 tINS FR 5 R21C7[3][A] dut/u_pwm/n156_s4/F
2.987 0.433 tNET RR 1 R21C8[3][B] dut/u_pwm/n156_s8/I2
4.019 1.032 tINS RF 3 R21C8[3][B] dut/u_pwm/n156_s8/F
5.319 1.300 tNET FF 1 R20C7[2][B] dut/u_pwm/n156_s3/I1
5.944 0.625 tINS FR 1 R20C7[2][B] dut/u_pwm/n156_s3/F
6.362 0.419 tNET RR 1 R21C7[0][A] dut/u_pwm/n156_s0/I2
7.164 0.802 tINS RR 17 R21C7[0][A] dut/u_pwm/n156_s0/F
8.330 1.166 tNET RR 1 R18C8[2][B] dut/u_pwm/oserx8_duty_cycle_all_one_3_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 pclk
10.000 0.000 tCL RR 92 BOTTOMSIDE[0] u_CLKDIV/CLKOUT
10.242 0.242 tNET RR 1 R18C8[2][B] dut/u_pwm/oserx8_duty_cycle_all_one_3_s0/CLK
10.199 -0.043 tSu 1 R18C8[2][B] dut/u_pwm/oserx8_duty_cycle_all_one_3_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay cell: 3.485, 43.088%; route: 4.145, 51.245%; tC2Q: 0.458, 5.667%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path12

Path Summary:

Slack 2.232
Data Arrival Time 7.967
Data Required Time 10.199
From dut/u_pwm/oserx8_cycle_1_s0
To dut/u_pwm/oserx8_duty_cycle_remainder_0_s0
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 92 BOTTOMSIDE[0] u_CLKDIV/CLKOUT
0.242 0.242 tNET RR 1 R21C8[0][A] dut/u_pwm/oserx8_cycle_1_s0/CLK
0.700 0.458 tC2Q RF 5 R21C8[0][A] dut/u_pwm/oserx8_cycle_1_s0/Q
1.528 0.828 tNET FF 1 R21C7[3][A] dut/u_pwm/n156_s4/I1
2.554 1.026 tINS FR 5 R21C7[3][A] dut/u_pwm/n156_s4/F
2.987 0.433 tNET RR 1 R21C8[3][B] dut/u_pwm/n156_s8/I2
4.019 1.032 tINS RF 3 R21C8[3][B] dut/u_pwm/n156_s8/F
5.319 1.300 tNET FF 1 R20C7[2][B] dut/u_pwm/n156_s3/I1
5.944 0.625 tINS FR 1 R20C7[2][B] dut/u_pwm/n156_s3/F
6.362 0.419 tNET RR 1 R21C7[0][A] dut/u_pwm/n156_s0/I2
7.164 0.802 tINS RR 17 R21C7[0][A] dut/u_pwm/n156_s0/F
7.967 0.803 tNET RR 1 R22C8[1][A] dut/u_pwm/oserx8_duty_cycle_remainder_0_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 pclk
10.000 0.000 tCL RR 92 BOTTOMSIDE[0] u_CLKDIV/CLKOUT
10.242 0.242 tNET RR 1 R22C8[1][A] dut/u_pwm/oserx8_duty_cycle_remainder_0_s0/CLK
10.199 -0.043 tSu 1 R22C8[1][A] dut/u_pwm/oserx8_duty_cycle_remainder_0_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay cell: 3.485, 45.112%; route: 3.782, 48.955%; tC2Q: 0.458, 5.933%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path13

Path Summary:

Slack 2.232
Data Arrival Time 7.967
Data Required Time 10.199
From dut/u_pwm/oserx8_cycle_1_s0
To dut/u_pwm/oserx8_duty_cycle_remainder_1_s0
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 92 BOTTOMSIDE[0] u_CLKDIV/CLKOUT
0.242 0.242 tNET RR 1 R21C8[0][A] dut/u_pwm/oserx8_cycle_1_s0/CLK
0.700 0.458 tC2Q RF 5 R21C8[0][A] dut/u_pwm/oserx8_cycle_1_s0/Q
1.528 0.828 tNET FF 1 R21C7[3][A] dut/u_pwm/n156_s4/I1
2.554 1.026 tINS FR 5 R21C7[3][A] dut/u_pwm/n156_s4/F
2.987 0.433 tNET RR 1 R21C8[3][B] dut/u_pwm/n156_s8/I2
4.019 1.032 tINS RF 3 R21C8[3][B] dut/u_pwm/n156_s8/F
5.319 1.300 tNET FF 1 R20C7[2][B] dut/u_pwm/n156_s3/I1
5.944 0.625 tINS FR 1 R20C7[2][B] dut/u_pwm/n156_s3/F
6.362 0.419 tNET RR 1 R21C7[0][A] dut/u_pwm/n156_s0/I2
7.164 0.802 tINS RR 17 R21C7[0][A] dut/u_pwm/n156_s0/F
7.967 0.803 tNET RR 1 R22C8[0][B] dut/u_pwm/oserx8_duty_cycle_remainder_1_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 pclk
10.000 0.000 tCL RR 92 BOTTOMSIDE[0] u_CLKDIV/CLKOUT
10.242 0.242 tNET RR 1 R22C8[0][B] dut/u_pwm/oserx8_duty_cycle_remainder_1_s0/CLK
10.199 -0.043 tSu 1 R22C8[0][B] dut/u_pwm/oserx8_duty_cycle_remainder_1_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay cell: 3.485, 45.112%; route: 3.782, 48.955%; tC2Q: 0.458, 5.933%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path14

Path Summary:

Slack 2.232
Data Arrival Time 7.967
Data Required Time 10.199
From dut/u_pwm/oserx8_cycle_1_s0
To dut/u_pwm/oserx8_duty_cycle_remainder_2_s0
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 92 BOTTOMSIDE[0] u_CLKDIV/CLKOUT
0.242 0.242 tNET RR 1 R21C8[0][A] dut/u_pwm/oserx8_cycle_1_s0/CLK
0.700 0.458 tC2Q RF 5 R21C8[0][A] dut/u_pwm/oserx8_cycle_1_s0/Q
1.528 0.828 tNET FF 1 R21C7[3][A] dut/u_pwm/n156_s4/I1
2.554 1.026 tINS FR 5 R21C7[3][A] dut/u_pwm/n156_s4/F
2.987 0.433 tNET RR 1 R21C8[3][B] dut/u_pwm/n156_s8/I2
4.019 1.032 tINS RF 3 R21C8[3][B] dut/u_pwm/n156_s8/F
5.319 1.300 tNET FF 1 R20C7[2][B] dut/u_pwm/n156_s3/I1
5.944 0.625 tINS FR 1 R20C7[2][B] dut/u_pwm/n156_s3/F
6.362 0.419 tNET RR 1 R21C7[0][A] dut/u_pwm/n156_s0/I2
7.164 0.802 tINS RR 17 R21C7[0][A] dut/u_pwm/n156_s0/F
7.967 0.803 tNET RR 1 R22C8[0][A] dut/u_pwm/oserx8_duty_cycle_remainder_2_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 pclk
10.000 0.000 tCL RR 92 BOTTOMSIDE[0] u_CLKDIV/CLKOUT
10.242 0.242 tNET RR 1 R22C8[0][A] dut/u_pwm/oserx8_duty_cycle_remainder_2_s0/CLK
10.199 -0.043 tSu 1 R22C8[0][A] dut/u_pwm/oserx8_duty_cycle_remainder_2_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay cell: 3.485, 45.112%; route: 3.782, 48.955%; tC2Q: 0.458, 5.933%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path15

Path Summary:

Slack 2.232
Data Arrival Time 7.967
Data Required Time 10.199
From dut/u_pwm/oserx8_cycle_1_s0
To dut/u_pwm/oserx8_cycle_2_s0
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 92 BOTTOMSIDE[0] u_CLKDIV/CLKOUT
0.242 0.242 tNET RR 1 R21C8[0][A] dut/u_pwm/oserx8_cycle_1_s0/CLK
0.700 0.458 tC2Q RF 5 R21C8[0][A] dut/u_pwm/oserx8_cycle_1_s0/Q
1.528 0.828 tNET FF 1 R21C7[3][A] dut/u_pwm/n156_s4/I1
2.554 1.026 tINS FR 5 R21C7[3][A] dut/u_pwm/n156_s4/F
2.987 0.433 tNET RR 1 R21C8[3][B] dut/u_pwm/n156_s8/I2
4.019 1.032 tINS RF 3 R21C8[3][B] dut/u_pwm/n156_s8/F
5.319 1.300 tNET FF 1 R20C7[2][B] dut/u_pwm/n156_s3/I1
5.944 0.625 tINS FR 1 R20C7[2][B] dut/u_pwm/n156_s3/F
6.362 0.419 tNET RR 1 R21C7[0][A] dut/u_pwm/n156_s0/I2
7.164 0.802 tINS RR 17 R21C7[0][A] dut/u_pwm/n156_s0/F
7.967 0.802 tNET RR 1 R20C5[0][A] dut/u_pwm/oserx8_cycle_2_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 pclk
10.000 0.000 tCL RR 92 BOTTOMSIDE[0] u_CLKDIV/CLKOUT
10.242 0.242 tNET RR 1 R20C5[0][A] dut/u_pwm/oserx8_cycle_2_s0/CLK
10.199 -0.043 tSu 1 R20C5[0][A] dut/u_pwm/oserx8_cycle_2_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay cell: 3.485, 45.116%; route: 3.781, 48.950%; tC2Q: 0.458, 5.933%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path16

Path Summary:

Slack 2.236
Data Arrival Time 7.963
Data Required Time 10.199
From dut/u_pwm/oserx8_cycle_1_s0
To dut/u_pwm/oserx8_duty_cycle_all_one_2_s0
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 92 BOTTOMSIDE[0] u_CLKDIV/CLKOUT
0.242 0.242 tNET RR 1 R21C8[0][A] dut/u_pwm/oserx8_cycle_1_s0/CLK
0.700 0.458 tC2Q RF 5 R21C8[0][A] dut/u_pwm/oserx8_cycle_1_s0/Q
1.528 0.828 tNET FF 1 R21C7[3][A] dut/u_pwm/n156_s4/I1
2.554 1.026 tINS FR 5 R21C7[3][A] dut/u_pwm/n156_s4/F
2.987 0.433 tNET RR 1 R21C8[3][B] dut/u_pwm/n156_s8/I2
4.019 1.032 tINS RF 3 R21C8[3][B] dut/u_pwm/n156_s8/F
5.319 1.300 tNET FF 1 R20C7[2][B] dut/u_pwm/n156_s3/I1
5.944 0.625 tINS FR 1 R20C7[2][B] dut/u_pwm/n156_s3/F
6.362 0.419 tNET RR 1 R21C7[0][A] dut/u_pwm/n156_s0/I2
7.164 0.802 tINS RR 17 R21C7[0][A] dut/u_pwm/n156_s0/F
7.963 0.798 tNET RR 1 R20C8[1][B] dut/u_pwm/oserx8_duty_cycle_all_one_2_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 pclk
10.000 0.000 tCL RR 92 BOTTOMSIDE[0] u_CLKDIV/CLKOUT
10.242 0.242 tNET RR 1 R20C8[1][B] dut/u_pwm/oserx8_duty_cycle_all_one_2_s0/CLK
10.199 -0.043 tSu 1 R20C8[1][B] dut/u_pwm/oserx8_duty_cycle_all_one_2_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay cell: 3.485, 45.139%; route: 3.777, 48.924%; tC2Q: 0.458, 5.937%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path17

Path Summary:

Slack 2.236
Data Arrival Time 7.963
Data Required Time 10.199
From dut/u_pwm/oserx8_cycle_1_s0
To dut/u_pwm/oserx8_duty_cycle_all_one_5_s0
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 92 BOTTOMSIDE[0] u_CLKDIV/CLKOUT
0.242 0.242 tNET RR 1 R21C8[0][A] dut/u_pwm/oserx8_cycle_1_s0/CLK
0.700 0.458 tC2Q RF 5 R21C8[0][A] dut/u_pwm/oserx8_cycle_1_s0/Q
1.528 0.828 tNET FF 1 R21C7[3][A] dut/u_pwm/n156_s4/I1
2.554 1.026 tINS FR 5 R21C7[3][A] dut/u_pwm/n156_s4/F
2.987 0.433 tNET RR 1 R21C8[3][B] dut/u_pwm/n156_s8/I2
4.019 1.032 tINS RF 3 R21C8[3][B] dut/u_pwm/n156_s8/F
5.319 1.300 tNET FF 1 R20C7[2][B] dut/u_pwm/n156_s3/I1
5.944 0.625 tINS FR 1 R20C7[2][B] dut/u_pwm/n156_s3/F
6.362 0.419 tNET RR 1 R21C7[0][A] dut/u_pwm/n156_s0/I2
7.164 0.802 tINS RR 17 R21C7[0][A] dut/u_pwm/n156_s0/F
7.963 0.798 tNET RR 1 R20C8[1][A] dut/u_pwm/oserx8_duty_cycle_all_one_5_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 pclk
10.000 0.000 tCL RR 92 BOTTOMSIDE[0] u_CLKDIV/CLKOUT
10.242 0.242 tNET RR 1 R20C8[1][A] dut/u_pwm/oserx8_duty_cycle_all_one_5_s0/CLK
10.199 -0.043 tSu 1 R20C8[1][A] dut/u_pwm/oserx8_duty_cycle_all_one_5_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay cell: 3.485, 45.139%; route: 3.777, 48.924%; tC2Q: 0.458, 5.937%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path18

Path Summary:

Slack 2.311
Data Arrival Time 7.887
Data Required Time 10.199
From dut/u_pwm/oserx8_cycle_1_s0
To dut/u_pwm/oserx8_cycle_1_s0
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 92 BOTTOMSIDE[0] u_CLKDIV/CLKOUT
0.242 0.242 tNET RR 1 R21C8[0][A] dut/u_pwm/oserx8_cycle_1_s0/CLK
0.700 0.458 tC2Q RF 5 R21C8[0][A] dut/u_pwm/oserx8_cycle_1_s0/Q
1.528 0.828 tNET FF 1 R21C7[3][A] dut/u_pwm/n156_s4/I1
2.554 1.026 tINS FR 5 R21C7[3][A] dut/u_pwm/n156_s4/F
2.987 0.433 tNET RR 1 R21C8[3][B] dut/u_pwm/n156_s8/I2
4.019 1.032 tINS RF 3 R21C8[3][B] dut/u_pwm/n156_s8/F
5.319 1.300 tNET FF 1 R20C7[2][B] dut/u_pwm/n156_s3/I1
5.944 0.625 tINS FR 1 R20C7[2][B] dut/u_pwm/n156_s3/F
6.362 0.419 tNET RR 1 R21C7[0][A] dut/u_pwm/n156_s0/I2
7.164 0.802 tINS RR 17 R21C7[0][A] dut/u_pwm/n156_s0/F
7.887 0.723 tNET RR 1 R21C8[0][A] dut/u_pwm/oserx8_cycle_1_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 pclk
10.000 0.000 tCL RR 92 BOTTOMSIDE[0] u_CLKDIV/CLKOUT
10.242 0.242 tNET RR 1 R21C8[0][A] dut/u_pwm/oserx8_cycle_1_s0/CLK
10.199 -0.043 tSu 1 R21C8[0][A] dut/u_pwm/oserx8_cycle_1_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay cell: 3.485, 45.584%; route: 3.702, 48.421%; tC2Q: 0.458, 5.995%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path19

Path Summary:

Slack 2.311
Data Arrival Time 7.887
Data Required Time 10.199
From dut/u_pwm/oserx8_cycle_1_s0
To dut/u_pwm/oserx8_cycle_4_s0
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 92 BOTTOMSIDE[0] u_CLKDIV/CLKOUT
0.242 0.242 tNET RR 1 R21C8[0][A] dut/u_pwm/oserx8_cycle_1_s0/CLK
0.700 0.458 tC2Q RF 5 R21C8[0][A] dut/u_pwm/oserx8_cycle_1_s0/Q
1.528 0.828 tNET FF 1 R21C7[3][A] dut/u_pwm/n156_s4/I1
2.554 1.026 tINS FR 5 R21C7[3][A] dut/u_pwm/n156_s4/F
2.987 0.433 tNET RR 1 R21C8[3][B] dut/u_pwm/n156_s8/I2
4.019 1.032 tINS RF 3 R21C8[3][B] dut/u_pwm/n156_s8/F
5.319 1.300 tNET FF 1 R20C7[2][B] dut/u_pwm/n156_s3/I1
5.944 0.625 tINS FR 1 R20C7[2][B] dut/u_pwm/n156_s3/F
6.362 0.419 tNET RR 1 R21C7[0][A] dut/u_pwm/n156_s0/I2
7.164 0.802 tINS RR 17 R21C7[0][A] dut/u_pwm/n156_s0/F
7.887 0.723 tNET RR 1 R21C8[1][B] dut/u_pwm/oserx8_cycle_4_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 pclk
10.000 0.000 tCL RR 92 BOTTOMSIDE[0] u_CLKDIV/CLKOUT
10.242 0.242 tNET RR 1 R21C8[1][B] dut/u_pwm/oserx8_cycle_4_s0/CLK
10.199 -0.043 tSu 1 R21C8[1][B] dut/u_pwm/oserx8_cycle_4_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay cell: 3.485, 45.584%; route: 3.702, 48.421%; tC2Q: 0.458, 5.995%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path20

Path Summary:

Slack 2.311
Data Arrival Time 7.887
Data Required Time 10.199
From dut/u_pwm/oserx8_cycle_1_s0
To dut/u_pwm/oserx8_cycle_5_s0
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 92 BOTTOMSIDE[0] u_CLKDIV/CLKOUT
0.242 0.242 tNET RR 1 R21C8[0][A] dut/u_pwm/oserx8_cycle_1_s0/CLK
0.700 0.458 tC2Q RF 5 R21C8[0][A] dut/u_pwm/oserx8_cycle_1_s0/Q
1.528 0.828 tNET FF 1 R21C7[3][A] dut/u_pwm/n156_s4/I1
2.554 1.026 tINS FR 5 R21C7[3][A] dut/u_pwm/n156_s4/F
2.987 0.433 tNET RR 1 R21C8[3][B] dut/u_pwm/n156_s8/I2
4.019 1.032 tINS RF 3 R21C8[3][B] dut/u_pwm/n156_s8/F
5.319 1.300 tNET FF 1 R20C7[2][B] dut/u_pwm/n156_s3/I1
5.944 0.625 tINS FR 1 R20C7[2][B] dut/u_pwm/n156_s3/F
6.362 0.419 tNET RR 1 R21C7[0][A] dut/u_pwm/n156_s0/I2
7.164 0.802 tINS RR 17 R21C7[0][A] dut/u_pwm/n156_s0/F
7.887 0.723 tNET RR 1 R21C8[0][B] dut/u_pwm/oserx8_cycle_5_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 pclk
10.000 0.000 tCL RR 92 BOTTOMSIDE[0] u_CLKDIV/CLKOUT
10.242 0.242 tNET RR 1 R21C8[0][B] dut/u_pwm/oserx8_cycle_5_s0/CLK
10.199 -0.043 tSu 1 R21C8[0][B] dut/u_pwm/oserx8_cycle_5_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay cell: 3.485, 45.584%; route: 3.702, 48.421%; tC2Q: 0.458, 5.995%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path21

Path Summary:

Slack 2.319
Data Arrival Time 7.880
Data Required Time 10.199
From dut/u_pwm/oserx8_cycle_1_s0
To dut/u_pwm/oserx8_cycle_6_s0
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 92 BOTTOMSIDE[0] u_CLKDIV/CLKOUT
0.242 0.242 tNET RR 1 R21C8[0][A] dut/u_pwm/oserx8_cycle_1_s0/CLK
0.700 0.458 tC2Q RF 5 R21C8[0][A] dut/u_pwm/oserx8_cycle_1_s0/Q
1.528 0.828 tNET FF 1 R21C7[3][A] dut/u_pwm/n156_s4/I1
2.554 1.026 tINS FR 5 R21C7[3][A] dut/u_pwm/n156_s4/F
2.987 0.433 tNET RR 1 R21C8[3][B] dut/u_pwm/n156_s8/I2
4.019 1.032 tINS RF 3 R21C8[3][B] dut/u_pwm/n156_s8/F
5.319 1.300 tNET FF 1 R20C7[2][B] dut/u_pwm/n156_s3/I1
5.944 0.625 tINS FR 1 R20C7[2][B] dut/u_pwm/n156_s3/F
6.362 0.419 tNET RR 1 R21C7[0][A] dut/u_pwm/n156_s0/I2
7.164 0.802 tINS RR 17 R21C7[0][A] dut/u_pwm/n156_s0/F
7.880 0.715 tNET RR 1 R21C6[1][A] dut/u_pwm/oserx8_cycle_6_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 pclk
10.000 0.000 tCL RR 92 BOTTOMSIDE[0] u_CLKDIV/CLKOUT
10.242 0.242 tNET RR 1 R21C6[1][A] dut/u_pwm/oserx8_cycle_6_s0/CLK
10.199 -0.043 tSu 1 R21C6[1][A] dut/u_pwm/oserx8_cycle_6_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay cell: 3.485, 45.627%; route: 3.695, 48.372%; tC2Q: 0.458, 6.001%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path22

Path Summary:

Slack 2.319
Data Arrival Time 7.880
Data Required Time 10.199
From dut/u_pwm/oserx8_cycle_1_s0
To dut/u_pwm/oserx8_duty_cycle_all_one_6_s0
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 92 BOTTOMSIDE[0] u_CLKDIV/CLKOUT
0.242 0.242 tNET RR 1 R21C8[0][A] dut/u_pwm/oserx8_cycle_1_s0/CLK
0.700 0.458 tC2Q RF 5 R21C8[0][A] dut/u_pwm/oserx8_cycle_1_s0/Q
1.528 0.828 tNET FF 1 R21C7[3][A] dut/u_pwm/n156_s4/I1
2.554 1.026 tINS FR 5 R21C7[3][A] dut/u_pwm/n156_s4/F
2.987 0.433 tNET RR 1 R21C8[3][B] dut/u_pwm/n156_s8/I2
4.019 1.032 tINS RF 3 R21C8[3][B] dut/u_pwm/n156_s8/F
5.319 1.300 tNET FF 1 R20C7[2][B] dut/u_pwm/n156_s3/I1
5.944 0.625 tINS FR 1 R20C7[2][B] dut/u_pwm/n156_s3/F
6.362 0.419 tNET RR 1 R21C7[0][A] dut/u_pwm/n156_s0/I2
7.164 0.802 tINS RR 17 R21C7[0][A] dut/u_pwm/n156_s0/F
7.880 0.715 tNET RR 1 R20C7[1][A] dut/u_pwm/oserx8_duty_cycle_all_one_6_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 pclk
10.000 0.000 tCL RR 92 BOTTOMSIDE[0] u_CLKDIV/CLKOUT
10.242 0.242 tNET RR 1 R20C7[1][A] dut/u_pwm/oserx8_duty_cycle_all_one_6_s0/CLK
10.199 -0.043 tSu 1 R20C7[1][A] dut/u_pwm/oserx8_duty_cycle_all_one_6_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay cell: 3.485, 45.627%; route: 3.695, 48.372%; tC2Q: 0.458, 6.001%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path23

Path Summary:

Slack 2.319
Data Arrival Time 7.880
Data Required Time 10.199
From dut/u_pwm/oserx8_cycle_1_s0
To dut/u_pwm/oserx8_duty_cycle_all_one_0_s0
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 92 BOTTOMSIDE[0] u_CLKDIV/CLKOUT
0.242 0.242 tNET RR 1 R21C8[0][A] dut/u_pwm/oserx8_cycle_1_s0/CLK
0.700 0.458 tC2Q RF 5 R21C8[0][A] dut/u_pwm/oserx8_cycle_1_s0/Q
1.528 0.828 tNET FF 1 R21C7[3][A] dut/u_pwm/n156_s4/I1
2.554 1.026 tINS FR 5 R21C7[3][A] dut/u_pwm/n156_s4/F
2.987 0.433 tNET RR 1 R21C8[3][B] dut/u_pwm/n156_s8/I2
4.019 1.032 tINS RF 3 R21C8[3][B] dut/u_pwm/n156_s8/F
5.319 1.300 tNET FF 1 R20C7[2][B] dut/u_pwm/n156_s3/I1
5.944 0.625 tINS FR 1 R20C7[2][B] dut/u_pwm/n156_s3/F
6.362 0.419 tNET RR 1 R21C7[0][A] dut/u_pwm/n156_s0/I2
7.164 0.802 tINS RR 17 R21C7[0][A] dut/u_pwm/n156_s0/F
7.880 0.715 tNET RR 1 R21C6[1][B] dut/u_pwm/oserx8_duty_cycle_all_one_0_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 pclk
10.000 0.000 tCL RR 92 BOTTOMSIDE[0] u_CLKDIV/CLKOUT
10.242 0.242 tNET RR 1 R21C6[1][B] dut/u_pwm/oserx8_duty_cycle_all_one_0_s0/CLK
10.199 -0.043 tSu 1 R21C6[1][B] dut/u_pwm/oserx8_duty_cycle_all_one_0_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay cell: 3.485, 45.627%; route: 3.695, 48.372%; tC2Q: 0.458, 6.001%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path24

Path Summary:

Slack 2.453
Data Arrival Time 7.389
Data Required Time 9.842
From dut/u_pwm/oserx8_duty_cycle_all_one_0_s0
To dut/u_pwm/d_7_s0
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 92 BOTTOMSIDE[0] u_CLKDIV/CLKOUT
0.242 0.242 tNET RR 1 R21C6[1][B] dut/u_pwm/oserx8_duty_cycle_all_one_0_s0/CLK
0.700 0.458 tC2Q RF 2 R21C6[1][B] dut/u_pwm/oserx8_duty_cycle_all_one_0_s0/Q
3.284 2.583 tNET FF 2 R18C6[0][B] dut/u_pwm/n278_s14/CIN
3.341 0.057 tINS FF 1 R18C6[0][B] dut/u_pwm/n278_s14/COUT
3.341 0.000 tNET FF 2 R18C6[1][A] dut/u_pwm/n278_s15/CIN
3.398 0.057 tINS FF 1 R18C6[1][A] dut/u_pwm/n278_s15/COUT
3.398 0.000 tNET FF 2 R18C6[1][B] dut/u_pwm/n278_s16/CIN
3.455 0.057 tINS FF 1 R18C6[1][B] dut/u_pwm/n278_s16/COUT
3.455 0.000 tNET FF 2 R18C6[2][A] dut/u_pwm/n278_s17/CIN
3.512 0.057 tINS FF 1 R18C6[2][A] dut/u_pwm/n278_s17/COUT
3.512 0.000 tNET FF 2 R18C6[2][B] dut/u_pwm/n278_s18/CIN
3.569 0.057 tINS FF 1 R18C6[2][B] dut/u_pwm/n278_s18/COUT
3.569 0.000 tNET FF 2 R18C7[0][A] dut/u_pwm/n278_s19/CIN
3.626 0.057 tINS FF 1 R18C7[0][A] dut/u_pwm/n278_s19/COUT
4.194 0.568 tNET FF 1 R18C7[3][B] dut/u_pwm/n278_s20/I2
5.293 1.099 tINS FF 4 R18C7[3][B] dut/u_pwm/n278_s20/F
7.389 2.096 tNET FF 1 R24C8[1][B] dut/u_pwm/d_7_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 pclk
10.000 0.000 tCL RR 92 BOTTOMSIDE[0] u_CLKDIV/CLKOUT
10.242 0.242 tNET RR 1 R24C8[1][B] dut/u_pwm/d_7_s0/CLK
9.842 -0.400 tSu 1 R24C8[1][B] dut/u_pwm/d_7_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay cell: 1.441, 20.163%; route: 5.248, 73.424%; tC2Q: 0.458, 6.413%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path25

Path Summary:

Slack 2.573
Data Arrival Time 7.626
Data Required Time 10.199
From dut/u_pwm/duty_cycle_int_2_s1
To dut/u_pwm/duty_cycle_int_5_s1
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 92 BOTTOMSIDE[0] u_CLKDIV/CLKOUT
0.242 0.242 tNET RR 1 R22C10[0][A] dut/u_pwm/duty_cycle_int_2_s1/CLK
0.700 0.458 tC2Q RF 6 R22C10[0][A] dut/u_pwm/duty_cycle_int_2_s1/Q
1.523 0.822 tNET FF 1 R21C9[0][B] dut/u_pwm/n69_s3/I2
2.555 1.032 tINS FF 6 R21C9[0][B] dut/u_pwm/n69_s3/F
3.398 0.843 tNET FF 1 R20C10[3][A] dut/u_pwm/n65_s3/I3
4.430 1.032 tINS FF 2 R20C10[3][A] dut/u_pwm/n65_s3/F
4.441 0.011 tNET FF 1 R20C10[2][B] dut/u_pwm/duty_cycle_int_9_s5/I1
5.243 0.802 tINS FR 1 R20C10[2][B] dut/u_pwm/duty_cycle_int_9_s5/F
5.662 0.419 tNET RR 1 R21C10[2][B] dut/u_pwm/duty_cycle_int_9_s3/I1
6.464 0.802 tINS RR 10 R21C10[2][B] dut/u_pwm/duty_cycle_int_9_s3/F
7.626 1.162 tNET RR 1 R18C9[0][A] dut/u_pwm/duty_cycle_int_5_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 pclk
10.000 0.000 tCL RR 92 BOTTOMSIDE[0] u_CLKDIV/CLKOUT
10.242 0.242 tNET RR 1 R18C9[0][A] dut/u_pwm/duty_cycle_int_5_s1/CLK
10.199 -0.043 tSu 1 R18C9[0][A] dut/u_pwm/duty_cycle_int_5_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay cell: 3.668, 49.676%; route: 3.258, 44.117%; tC2Q: 0.458, 6.207%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 0.582
Data Arrival Time 0.778
Data Required Time 0.196
From gw_gvio_inst_0/u_gvio0_top/probe_out6_reg1_0_s2
To gw_gvio_inst_0/u_gvio0_top/probe_out6_reg1_0_s6
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 92 BOTTOMSIDE[0] u_CLKDIV/CLKOUT
0.183 0.183 tNET RR 1 R22C11[0][A] gw_gvio_inst_0/u_gvio0_top/probe_out6_reg1_0_s2/CLK
0.516 0.333 tC2Q RF 13 R22C11[0][A] gw_gvio_inst_0/u_gvio0_top/probe_out6_reg1_0_s2/Q
0.778 0.261 tNET FF 1 R23C11 gw_gvio_inst_0/u_gvio0_top/probe_out6_reg1_0_s6/AD[0]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 92 BOTTOMSIDE[0] u_CLKDIV/CLKOUT
0.183 0.183 tNET RR 1 R23C11 gw_gvio_inst_0/u_gvio0_top/probe_out6_reg1_0_s6/CLK
0.196 0.012 tHld 1 R23C11 gw_gvio_inst_0/u_gvio0_top/probe_out6_reg1_0_s6

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.261, 43.957%; tC2Q: 0.333, 56.043%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%

Path2

Path Summary:

Slack 0.708
Data Arrival Time 3.910
Data Required Time 3.202
From gw_gvio_inst_0/u_gvio0_top/addr_all_7_s1
To gw_gvio_inst_0/u_gvio0_top/addr_all_7_s1
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOL11[B] tck_pad_i_ibuf/I
1.392 1.392 tINS RR 1 IOL11[B] tck_pad_i_ibuf/O
1.392 0.000 tNET RR 1 R1C1 gw_gvio_inst_0/u_gw_jtag/tck_pad_i
2.236 0.844 tINS RR 139 R1C1 gw_gvio_inst_0/u_gw_jtag/tck_o
3.202 0.966 tNET RR 1 R20C14[0][A] gw_gvio_inst_0/u_gvio0_top/addr_all_7_s1/CLK
3.536 0.333 tC2Q RR 4 R20C14[0][A] gw_gvio_inst_0/u_gvio0_top/addr_all_7_s1/Q
3.538 0.002 tNET RR 1 R20C14[0][A] gw_gvio_inst_0/u_gvio0_top/n289_s2/I3
3.910 0.372 tINS RF 1 R20C14[0][A] gw_gvio_inst_0/u_gvio0_top/n289_s2/F
3.910 0.000 tNET FF 1 R20C14[0][A] gw_gvio_inst_0/u_gvio0_top/addr_all_7_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOL11[B] tck_pad_i_ibuf/I
1.392 1.392 tINS RR 1 IOL11[B] tck_pad_i_ibuf/O
1.392 0.000 tNET RR 1 R1C1 gw_gvio_inst_0/u_gw_jtag/tck_pad_i
2.236 0.844 tINS RR 139 R1C1 gw_gvio_inst_0/u_gw_jtag/tck_o
3.202 0.966 tNET RR 1 R20C14[0][A] gw_gvio_inst_0/u_gvio0_top/addr_all_7_s1/CLK
3.202 0.000 tHld 1 R20C14[0][A] gw_gvio_inst_0/u_gvio0_top/addr_all_7_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 2.236, 69.836%; route: 0.966, 30.164%
Arrival Data Path Delay cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay cell: 2.236, 69.836%; route: 0.966, 30.164%

Path3

Path Summary:

Slack 0.708
Data Arrival Time 3.910
Data Required Time 3.202
From gw_gvio_inst_0/u_gvio0_top/word_count_3_s0
To gw_gvio_inst_0/u_gvio0_top/word_count_3_s0
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOL11[B] tck_pad_i_ibuf/I
1.392 1.392 tINS RR 1 IOL11[B] tck_pad_i_ibuf/O
1.392 0.000 tNET RR 1 R1C1 gw_gvio_inst_0/u_gw_jtag/tck_pad_i
2.236 0.844 tINS RR 139 R1C1 gw_gvio_inst_0/u_gw_jtag/tck_o
3.202 0.966 tNET RR 1 R21C19[0][A] gw_gvio_inst_0/u_gvio0_top/word_count_3_s0/CLK
3.536 0.333 tC2Q RR 2 R21C19[0][A] gw_gvio_inst_0/u_gvio0_top/word_count_3_s0/Q
3.538 0.002 tNET RR 1 R21C19[0][A] gw_gvio_inst_0/u_gvio0_top/data_to_word_counter_3_s2/I1
3.910 0.372 tINS RF 1 R21C19[0][A] gw_gvio_inst_0/u_gvio0_top/data_to_word_counter_3_s2/F
3.910 0.000 tNET FF 1 R21C19[0][A] gw_gvio_inst_0/u_gvio0_top/word_count_3_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOL11[B] tck_pad_i_ibuf/I
1.392 1.392 tINS RR 1 IOL11[B] tck_pad_i_ibuf/O
1.392 0.000 tNET RR 1 R1C1 gw_gvio_inst_0/u_gw_jtag/tck_pad_i
2.236 0.844 tINS RR 139 R1C1 gw_gvio_inst_0/u_gw_jtag/tck_o
3.202 0.966 tNET RR 1 R21C19[0][A] gw_gvio_inst_0/u_gvio0_top/word_count_3_s0/CLK
3.202 0.000 tHld 1 R21C19[0][A] gw_gvio_inst_0/u_gvio0_top/word_count_3_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 2.236, 69.836%; route: 0.966, 30.164%
Arrival Data Path Delay cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay cell: 2.236, 69.836%; route: 0.966, 30.164%

Path4

Path Summary:

Slack 0.708
Data Arrival Time 3.910
Data Required Time 3.202
From gw_gvio_inst_0/u_gvio0_top/word_count_5_s0
To gw_gvio_inst_0/u_gvio0_top/word_count_5_s0
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOL11[B] tck_pad_i_ibuf/I
1.392 1.392 tINS RR 1 IOL11[B] tck_pad_i_ibuf/O
1.392 0.000 tNET RR 1 R1C1 gw_gvio_inst_0/u_gw_jtag/tck_pad_i
2.236 0.844 tINS RR 139 R1C1 gw_gvio_inst_0/u_gw_jtag/tck_o
3.202 0.966 tNET RR 1 R22C21[1][A] gw_gvio_inst_0/u_gvio0_top/word_count_5_s0/CLK
3.536 0.333 tC2Q RR 3 R22C21[1][A] gw_gvio_inst_0/u_gvio0_top/word_count_5_s0/Q
3.538 0.002 tNET RR 1 R22C21[1][A] gw_gvio_inst_0/u_gvio0_top/data_to_word_counter_5_s2/I3
3.910 0.372 tINS RF 1 R22C21[1][A] gw_gvio_inst_0/u_gvio0_top/data_to_word_counter_5_s2/F
3.910 0.000 tNET FF 1 R22C21[1][A] gw_gvio_inst_0/u_gvio0_top/word_count_5_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOL11[B] tck_pad_i_ibuf/I
1.392 1.392 tINS RR 1 IOL11[B] tck_pad_i_ibuf/O
1.392 0.000 tNET RR 1 R1C1 gw_gvio_inst_0/u_gw_jtag/tck_pad_i
2.236 0.844 tINS RR 139 R1C1 gw_gvio_inst_0/u_gw_jtag/tck_o
3.202 0.966 tNET RR 1 R22C21[1][A] gw_gvio_inst_0/u_gvio0_top/word_count_5_s0/CLK
3.202 0.000 tHld 1 R22C21[1][A] gw_gvio_inst_0/u_gvio0_top/word_count_5_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 2.236, 69.836%; route: 0.966, 30.164%
Arrival Data Path Delay cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay cell: 2.236, 69.836%; route: 0.966, 30.164%

Path5

Path Summary:

Slack 0.708
Data Arrival Time 3.910
Data Required Time 3.202
From gw_gvio_inst_0/u_gvio0_top/word_count_6_s0
To gw_gvio_inst_0/u_gvio0_top/word_count_6_s0
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOL11[B] tck_pad_i_ibuf/I
1.392 1.392 tINS RR 1 IOL11[B] tck_pad_i_ibuf/O
1.392 0.000 tNET RR 1 R1C1 gw_gvio_inst_0/u_gw_jtag/tck_pad_i
2.236 0.844 tINS RR 139 R1C1 gw_gvio_inst_0/u_gw_jtag/tck_o
3.202 0.966 tNET RR 1 R21C20[0][A] gw_gvio_inst_0/u_gvio0_top/word_count_6_s0/CLK
3.536 0.333 tC2Q RR 3 R21C20[0][A] gw_gvio_inst_0/u_gvio0_top/word_count_6_s0/Q
3.538 0.002 tNET RR 1 R21C20[0][A] gw_gvio_inst_0/u_gvio0_top/data_to_word_counter_6_s2/I3
3.910 0.372 tINS RF 1 R21C20[0][A] gw_gvio_inst_0/u_gvio0_top/data_to_word_counter_6_s2/F
3.910 0.000 tNET FF 1 R21C20[0][A] gw_gvio_inst_0/u_gvio0_top/word_count_6_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOL11[B] tck_pad_i_ibuf/I
1.392 1.392 tINS RR 1 IOL11[B] tck_pad_i_ibuf/O
1.392 0.000 tNET RR 1 R1C1 gw_gvio_inst_0/u_gw_jtag/tck_pad_i
2.236 0.844 tINS RR 139 R1C1 gw_gvio_inst_0/u_gw_jtag/tck_o
3.202 0.966 tNET RR 1 R21C20[0][A] gw_gvio_inst_0/u_gvio0_top/word_count_6_s0/CLK
3.202 0.000 tHld 1 R21C20[0][A] gw_gvio_inst_0/u_gvio0_top/word_count_6_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 2.236, 69.836%; route: 0.966, 30.164%
Arrival Data Path Delay cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay cell: 2.236, 69.836%; route: 0.966, 30.164%

Path6

Path Summary:

Slack 0.708
Data Arrival Time 3.910
Data Required Time 3.202
From gw_gvio_inst_0/u_gvio0_top/word_count_11_s0
To gw_gvio_inst_0/u_gvio0_top/word_count_11_s0
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOL11[B] tck_pad_i_ibuf/I
1.392 1.392 tINS RR 1 IOL11[B] tck_pad_i_ibuf/O
1.392 0.000 tNET RR 1 R1C1 gw_gvio_inst_0/u_gw_jtag/tck_pad_i
2.236 0.844 tINS RR 139 R1C1 gw_gvio_inst_0/u_gw_jtag/tck_o
3.202 0.966 tNET RR 1 R23C21[0][A] gw_gvio_inst_0/u_gvio0_top/word_count_11_s0/CLK
3.536 0.333 tC2Q RR 2 R23C21[0][A] gw_gvio_inst_0/u_gvio0_top/word_count_11_s0/Q
3.538 0.002 tNET RR 1 R23C21[0][A] gw_gvio_inst_0/u_gvio0_top/data_to_word_counter_11_s2/I3
3.910 0.372 tINS RF 1 R23C21[0][A] gw_gvio_inst_0/u_gvio0_top/data_to_word_counter_11_s2/F
3.910 0.000 tNET FF 1 R23C21[0][A] gw_gvio_inst_0/u_gvio0_top/word_count_11_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOL11[B] tck_pad_i_ibuf/I
1.392 1.392 tINS RR 1 IOL11[B] tck_pad_i_ibuf/O
1.392 0.000 tNET RR 1 R1C1 gw_gvio_inst_0/u_gw_jtag/tck_pad_i
2.236 0.844 tINS RR 139 R1C1 gw_gvio_inst_0/u_gw_jtag/tck_o
3.202 0.966 tNET RR 1 R23C21[0][A] gw_gvio_inst_0/u_gvio0_top/word_count_11_s0/CLK
3.202 0.000 tHld 1 R23C21[0][A] gw_gvio_inst_0/u_gvio0_top/word_count_11_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 2.236, 69.836%; route: 0.966, 30.164%
Arrival Data Path Delay cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay cell: 2.236, 69.836%; route: 0.966, 30.164%

Path7

Path Summary:

Slack 0.709
Data Arrival Time 3.911
Data Required Time 3.202
From gw_gvio_inst_0/u_gvio0_top/bit_count_3_s1
To gw_gvio_inst_0/u_gvio0_top/bit_count_3_s1
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOL11[B] tck_pad_i_ibuf/I
1.392 1.392 tINS RR 1 IOL11[B] tck_pad_i_ibuf/O
1.392 0.000 tNET RR 1 R1C1 gw_gvio_inst_0/u_gw_jtag/tck_pad_i
2.236 0.844 tINS RR 139 R1C1 gw_gvio_inst_0/u_gw_jtag/tck_o
3.202 0.966 tNET RR 1 R21C20[1][A] gw_gvio_inst_0/u_gvio0_top/bit_count_3_s1/CLK
3.536 0.333 tC2Q RR 3 R21C20[1][A] gw_gvio_inst_0/u_gvio0_top/bit_count_3_s1/Q
3.539 0.004 tNET RR 1 R21C20[1][A] gw_gvio_inst_0/u_gvio0_top/n873_s2/I1
3.911 0.372 tINS RF 1 R21C20[1][A] gw_gvio_inst_0/u_gvio0_top/n873_s2/F
3.911 0.000 tNET FF 1 R21C20[1][A] gw_gvio_inst_0/u_gvio0_top/bit_count_3_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOL11[B] tck_pad_i_ibuf/I
1.392 1.392 tINS RR 1 IOL11[B] tck_pad_i_ibuf/O
1.392 0.000 tNET RR 1 R1C1 gw_gvio_inst_0/u_gw_jtag/tck_pad_i
2.236 0.844 tINS RR 139 R1C1 gw_gvio_inst_0/u_gw_jtag/tck_o
3.202 0.966 tNET RR 1 R21C20[1][A] gw_gvio_inst_0/u_gvio0_top/bit_count_3_s1/CLK
3.202 0.000 tHld 1 R21C20[1][A] gw_gvio_inst_0/u_gvio0_top/bit_count_3_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 2.236, 69.836%; route: 0.966, 30.164%
Arrival Data Path Delay cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay cell: 2.236, 69.836%; route: 0.966, 30.164%

Path8

Path Summary:

Slack 0.709
Data Arrival Time 3.911
Data Required Time 3.202
From gw_gvio_inst_0/u_gvio0_top/bit_count_6_s1
To gw_gvio_inst_0/u_gvio0_top/bit_count_6_s1
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOL11[B] tck_pad_i_ibuf/I
1.392 1.392 tINS RR 1 IOL11[B] tck_pad_i_ibuf/O
1.392 0.000 tNET RR 1 R1C1 gw_gvio_inst_0/u_gw_jtag/tck_pad_i
2.236 0.844 tINS RR 139 R1C1 gw_gvio_inst_0/u_gw_jtag/tck_o
3.202 0.966 tNET RR 1 R20C20[1][A] gw_gvio_inst_0/u_gvio0_top/bit_count_6_s1/CLK
3.536 0.333 tC2Q RR 3 R20C20[1][A] gw_gvio_inst_0/u_gvio0_top/bit_count_6_s1/Q
3.539 0.004 tNET RR 1 R20C20[1][A] gw_gvio_inst_0/u_gvio0_top/n870_s5/I0
3.911 0.372 tINS RF 1 R20C20[1][A] gw_gvio_inst_0/u_gvio0_top/n870_s5/F
3.911 0.000 tNET FF 1 R20C20[1][A] gw_gvio_inst_0/u_gvio0_top/bit_count_6_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOL11[B] tck_pad_i_ibuf/I
1.392 1.392 tINS RR 1 IOL11[B] tck_pad_i_ibuf/O
1.392 0.000 tNET RR 1 R1C1 gw_gvio_inst_0/u_gw_jtag/tck_pad_i
2.236 0.844 tINS RR 139 R1C1 gw_gvio_inst_0/u_gw_jtag/tck_o
3.202 0.966 tNET RR 1 R20C20[1][A] gw_gvio_inst_0/u_gvio0_top/bit_count_6_s1/CLK
3.202 0.000 tHld 1 R20C20[1][A] gw_gvio_inst_0/u_gvio0_top/bit_count_6_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 2.236, 69.836%; route: 0.966, 30.164%
Arrival Data Path Delay cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay cell: 2.236, 69.836%; route: 0.966, 30.164%

Path9

Path Summary:

Slack 0.709
Data Arrival Time 3.911
Data Required Time 3.202
From gw_gvio_inst_0/u_gvio0_top/word_count_0_s0
To gw_gvio_inst_0/u_gvio0_top/word_count_0_s0
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOL11[B] tck_pad_i_ibuf/I
1.392 1.392 tINS RR 1 IOL11[B] tck_pad_i_ibuf/O
1.392 0.000 tNET RR 1 R1C1 gw_gvio_inst_0/u_gw_jtag/tck_pad_i
2.236 0.844 tINS RR 139 R1C1 gw_gvio_inst_0/u_gw_jtag/tck_o
3.202 0.966 tNET RR 1 R21C21[1][A] gw_gvio_inst_0/u_gvio0_top/word_count_0_s0/CLK
3.536 0.333 tC2Q RR 5 R21C21[1][A] gw_gvio_inst_0/u_gvio0_top/word_count_0_s0/Q
3.539 0.004 tNET RR 1 R21C21[1][A] gw_gvio_inst_0/u_gvio0_top/data_to_word_counter_0_s2/I3
3.911 0.372 tINS RF 1 R21C21[1][A] gw_gvio_inst_0/u_gvio0_top/data_to_word_counter_0_s2/F
3.911 0.000 tNET FF 1 R21C21[1][A] gw_gvio_inst_0/u_gvio0_top/word_count_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOL11[B] tck_pad_i_ibuf/I
1.392 1.392 tINS RR 1 IOL11[B] tck_pad_i_ibuf/O
1.392 0.000 tNET RR 1 R1C1 gw_gvio_inst_0/u_gw_jtag/tck_pad_i
2.236 0.844 tINS RR 139 R1C1 gw_gvio_inst_0/u_gw_jtag/tck_o
3.202 0.966 tNET RR 1 R21C21[1][A] gw_gvio_inst_0/u_gvio0_top/word_count_0_s0/CLK
3.202 0.000 tHld 1 R21C21[1][A] gw_gvio_inst_0/u_gvio0_top/word_count_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 2.236, 69.836%; route: 0.966, 30.164%
Arrival Data Path Delay cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay cell: 2.236, 69.836%; route: 0.966, 30.164%

Path10

Path Summary:

Slack 0.709
Data Arrival Time 3.911
Data Required Time 3.202
From gw_gvio_inst_0/u_gvio0_top/word_count_8_s0
To gw_gvio_inst_0/u_gvio0_top/word_count_8_s0
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOL11[B] tck_pad_i_ibuf/I
1.392 1.392 tINS RR 1 IOL11[B] tck_pad_i_ibuf/O
1.392 0.000 tNET RR 1 R1C1 gw_gvio_inst_0/u_gw_jtag/tck_pad_i
2.236 0.844 tINS RR 139 R1C1 gw_gvio_inst_0/u_gw_jtag/tck_o
3.202 0.966 tNET RR 1 R20C21[1][A] gw_gvio_inst_0/u_gvio0_top/word_count_8_s0/CLK
3.536 0.333 tC2Q RR 4 R20C21[1][A] gw_gvio_inst_0/u_gvio0_top/word_count_8_s0/Q
3.539 0.004 tNET RR 1 R20C21[1][A] gw_gvio_inst_0/u_gvio0_top/data_to_word_counter_8_s2/I1
3.911 0.372 tINS RF 1 R20C21[1][A] gw_gvio_inst_0/u_gvio0_top/data_to_word_counter_8_s2/F
3.911 0.000 tNET FF 1 R20C21[1][A] gw_gvio_inst_0/u_gvio0_top/word_count_8_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOL11[B] tck_pad_i_ibuf/I
1.392 1.392 tINS RR 1 IOL11[B] tck_pad_i_ibuf/O
1.392 0.000 tNET RR 1 R1C1 gw_gvio_inst_0/u_gw_jtag/tck_pad_i
2.236 0.844 tINS RR 139 R1C1 gw_gvio_inst_0/u_gw_jtag/tck_o
3.202 0.966 tNET RR 1 R20C21[1][A] gw_gvio_inst_0/u_gvio0_top/word_count_8_s0/CLK
3.202 0.000 tHld 1 R20C21[1][A] gw_gvio_inst_0/u_gvio0_top/word_count_8_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 2.236, 69.836%; route: 0.966, 30.164%
Arrival Data Path Delay cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay cell: 2.236, 69.836%; route: 0.966, 30.164%

Path11

Path Summary:

Slack 0.709
Data Arrival Time 3.911
Data Required Time 3.202
From gw_gvio_inst_0/u_gvio0_top/word_count_13_s0
To gw_gvio_inst_0/u_gvio0_top/word_count_13_s0
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOL11[B] tck_pad_i_ibuf/I
1.392 1.392 tINS RR 1 IOL11[B] tck_pad_i_ibuf/O
1.392 0.000 tNET RR 1 R1C1 gw_gvio_inst_0/u_gw_jtag/tck_pad_i
2.236 0.844 tINS RR 139 R1C1 gw_gvio_inst_0/u_gw_jtag/tck_o
3.202 0.966 tNET RR 1 R22C21[0][A] gw_gvio_inst_0/u_gvio0_top/word_count_13_s0/CLK
3.536 0.333 tC2Q RR 3 R22C21[0][A] gw_gvio_inst_0/u_gvio0_top/word_count_13_s0/Q
3.539 0.004 tNET RR 1 R22C21[0][A] gw_gvio_inst_0/u_gvio0_top/data_to_word_counter_13_s4/I1
3.911 0.372 tINS RF 1 R22C21[0][A] gw_gvio_inst_0/u_gvio0_top/data_to_word_counter_13_s4/F
3.911 0.000 tNET FF 1 R22C21[0][A] gw_gvio_inst_0/u_gvio0_top/word_count_13_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOL11[B] tck_pad_i_ibuf/I
1.392 1.392 tINS RR 1 IOL11[B] tck_pad_i_ibuf/O
1.392 0.000 tNET RR 1 R1C1 gw_gvio_inst_0/u_gw_jtag/tck_pad_i
2.236 0.844 tINS RR 139 R1C1 gw_gvio_inst_0/u_gw_jtag/tck_o
3.202 0.966 tNET RR 1 R22C21[0][A] gw_gvio_inst_0/u_gvio0_top/word_count_13_s0/CLK
3.202 0.000 tHld 1 R22C21[0][A] gw_gvio_inst_0/u_gvio0_top/word_count_13_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 2.236, 69.836%; route: 0.966, 30.164%
Arrival Data Path Delay cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay cell: 2.236, 69.836%; route: 0.966, 30.164%

Path12

Path Summary:

Slack 0.710
Data Arrival Time 3.912
Data Required Time 3.202
From gw_gvio_inst_0/u_gvio0_top/addr_all_5_s1
To gw_gvio_inst_0/u_gvio0_top/addr_all_5_s1
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOL11[B] tck_pad_i_ibuf/I
1.392 1.392 tINS RR 1 IOL11[B] tck_pad_i_ibuf/O
1.392 0.000 tNET RR 1 R1C1 gw_gvio_inst_0/u_gw_jtag/tck_pad_i
2.236 0.844 tINS RR 139 R1C1 gw_gvio_inst_0/u_gw_jtag/tck_o
3.202 0.966 tNET RR 1 R20C15[0][A] gw_gvio_inst_0/u_gvio0_top/addr_all_5_s1/CLK
3.536 0.333 tC2Q RR 5 R20C15[0][A] gw_gvio_inst_0/u_gvio0_top/addr_all_5_s1/Q
3.540 0.005 tNET RR 1 R20C15[0][A] gw_gvio_inst_0/u_gvio0_top/n291_s2/I1
3.912 0.372 tINS RF 1 R20C15[0][A] gw_gvio_inst_0/u_gvio0_top/n291_s2/F
3.912 0.000 tNET FF 1 R20C15[0][A] gw_gvio_inst_0/u_gvio0_top/addr_all_5_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOL11[B] tck_pad_i_ibuf/I
1.392 1.392 tINS RR 1 IOL11[B] tck_pad_i_ibuf/O
1.392 0.000 tNET RR 1 R1C1 gw_gvio_inst_0/u_gw_jtag/tck_pad_i
2.236 0.844 tINS RR 139 R1C1 gw_gvio_inst_0/u_gw_jtag/tck_o
3.202 0.966 tNET RR 1 R20C15[0][A] gw_gvio_inst_0/u_gvio0_top/addr_all_5_s1/CLK
3.202 0.000 tHld 1 R20C15[0][A] gw_gvio_inst_0/u_gvio0_top/addr_all_5_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 2.236, 69.836%; route: 0.966, 30.164%
Arrival Data Path Delay cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945%
Required Clock Path Delay cell: 2.236, 69.836%; route: 0.966, 30.164%

Path13

Path Summary:

Slack 0.711
Data Arrival Time 3.914
Data Required Time 3.202
From gw_gvio_inst_0/u_gvio0_top/addr_all_3_s1
To gw_gvio_inst_0/u_gvio0_top/addr_all_3_s1
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOL11[B] tck_pad_i_ibuf/I
1.392 1.392 tINS RR 1 IOL11[B] tck_pad_i_ibuf/O
1.392 0.000 tNET RR 1 R1C1 gw_gvio_inst_0/u_gw_jtag/tck_pad_i
2.236 0.844 tINS RR 139 R1C1 gw_gvio_inst_0/u_gw_jtag/tck_o
3.202 0.966 tNET RR 1 R20C14[1][A] gw_gvio_inst_0/u_gvio0_top/addr_all_3_s1/CLK
3.536 0.333 tC2Q RR 8 R20C14[1][A] gw_gvio_inst_0/u_gvio0_top/addr_all_3_s1/Q
3.542 0.006 tNET RR 1 R20C14[1][A] gw_gvio_inst_0/u_gvio0_top/n293_s2/I3
3.914 0.372 tINS RF 1 R20C14[1][A] gw_gvio_inst_0/u_gvio0_top/n293_s2/F
3.914 0.000 tNET FF 1 R20C14[1][A] gw_gvio_inst_0/u_gvio0_top/addr_all_3_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOL11[B] tck_pad_i_ibuf/I
1.392 1.392 tINS RR 1 IOL11[B] tck_pad_i_ibuf/O
1.392 0.000 tNET RR 1 R1C1 gw_gvio_inst_0/u_gw_jtag/tck_pad_i
2.236 0.844 tINS RR 139 R1C1 gw_gvio_inst_0/u_gw_jtag/tck_o
3.202 0.966 tNET RR 1 R20C14[1][A] gw_gvio_inst_0/u_gvio0_top/addr_all_3_s1/CLK
3.202 0.000 tHld 1 R20C14[1][A] gw_gvio_inst_0/u_gvio0_top/addr_all_3_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 2.236, 69.836%; route: 0.966, 30.164%
Arrival Data Path Delay cell: 0.372, 52.303%; route: 0.006, 0.830%; tC2Q: 0.333, 46.867%
Required Clock Path Delay cell: 2.236, 69.836%; route: 0.966, 30.164%

Path14

Path Summary:

Slack 0.711
Data Arrival Time 3.914
Data Required Time 3.202
From gw_gvio_inst_0/u_gvio0_top/module_state_0_s0
To gw_gvio_inst_0/u_gvio0_top/module_state_0_s0
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOL11[B] tck_pad_i_ibuf/I
1.392 1.392 tINS RR 1 IOL11[B] tck_pad_i_ibuf/O
1.392 0.000 tNET RR 1 R1C1 gw_gvio_inst_0/u_gw_jtag/tck_pad_i
2.236 0.844 tINS RR 139 R1C1 gw_gvio_inst_0/u_gw_jtag/tck_o
3.202 0.966 tNET RR 1 R20C21[0][A] gw_gvio_inst_0/u_gvio0_top/module_state_0_s0/CLK
3.536 0.333 tC2Q RR 9 R20C21[0][A] gw_gvio_inst_0/u_gvio0_top/module_state_0_s0/Q
3.542 0.006 tNET RR 1 R20C21[0][A] gw_gvio_inst_0/u_gvio0_top/module_next_state_0_s7/I0
3.914 0.372 tINS RF 1 R20C21[0][A] gw_gvio_inst_0/u_gvio0_top/module_next_state_0_s7/F
3.914 0.000 tNET FF 1 R20C21[0][A] gw_gvio_inst_0/u_gvio0_top/module_state_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOL11[B] tck_pad_i_ibuf/I
1.392 1.392 tINS RR 1 IOL11[B] tck_pad_i_ibuf/O
1.392 0.000 tNET RR 1 R1C1 gw_gvio_inst_0/u_gw_jtag/tck_pad_i
2.236 0.844 tINS RR 139 R1C1 gw_gvio_inst_0/u_gw_jtag/tck_o
3.202 0.966 tNET RR 1 R20C21[0][A] gw_gvio_inst_0/u_gvio0_top/module_state_0_s0/CLK
3.202 0.000 tHld 1 R20C21[0][A] gw_gvio_inst_0/u_gvio0_top/module_state_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 2.236, 69.836%; route: 0.966, 30.164%
Arrival Data Path Delay cell: 0.372, 52.303%; route: 0.006, 0.830%; tC2Q: 0.333, 46.867%
Required Clock Path Delay cell: 2.236, 69.836%; route: 0.966, 30.164%

Path15

Path Summary:

Slack 0.711
Data Arrival Time 3.914
Data Required Time 3.202
From gw_gvio_inst_0/u_gvio0_top/module_state_1_s0
To gw_gvio_inst_0/u_gvio0_top/module_state_1_s0
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOL11[B] tck_pad_i_ibuf/I
1.392 1.392 tINS RR 1 IOL11[B] tck_pad_i_ibuf/O
1.392 0.000 tNET RR 1 R1C1 gw_gvio_inst_0/u_gw_jtag/tck_pad_i
2.236 0.844 tINS RR 139 R1C1 gw_gvio_inst_0/u_gw_jtag/tck_o
3.202 0.966 tNET RR 1 R21C21[0][A] gw_gvio_inst_0/u_gvio0_top/module_state_1_s0/CLK
3.536 0.333 tC2Q RR 9 R21C21[0][A] gw_gvio_inst_0/u_gvio0_top/module_state_1_s0/Q
3.542 0.006 tNET RR 1 R21C21[0][A] gw_gvio_inst_0/u_gvio0_top/module_next_state_1_s5/I2
3.914 0.372 tINS RF 1 R21C21[0][A] gw_gvio_inst_0/u_gvio0_top/module_next_state_1_s5/F
3.914 0.000 tNET FF 1 R21C21[0][A] gw_gvio_inst_0/u_gvio0_top/module_state_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOL11[B] tck_pad_i_ibuf/I
1.392 1.392 tINS RR 1 IOL11[B] tck_pad_i_ibuf/O
1.392 0.000 tNET RR 1 R1C1 gw_gvio_inst_0/u_gw_jtag/tck_pad_i
2.236 0.844 tINS RR 139 R1C1 gw_gvio_inst_0/u_gw_jtag/tck_o
3.202 0.966 tNET RR 1 R21C21[0][A] gw_gvio_inst_0/u_gvio0_top/module_state_1_s0/CLK
3.202 0.000 tHld 1 R21C21[0][A] gw_gvio_inst_0/u_gvio0_top/module_state_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 2.236, 69.836%; route: 0.966, 30.164%
Arrival Data Path Delay cell: 0.372, 52.303%; route: 0.006, 0.830%; tC2Q: 0.333, 46.867%
Required Clock Path Delay cell: 2.236, 69.836%; route: 0.966, 30.164%

Path16

Path Summary:

Slack 0.711
Data Arrival Time 0.894
Data Required Time 0.183
From dut/u_pwm/cnt_0_s0
To dut/u_pwm/cnt_0_s0
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 92 BOTTOMSIDE[0] u_CLKDIV/CLKOUT
0.183 0.183 tNET RR 1 R20C8[0][A] dut/u_pwm/cnt_0_s0/CLK
0.516 0.333 tC2Q RR 6 R20C8[0][A] dut/u_pwm/cnt_0_s0/Q
0.522 0.006 tNET RR 1 R20C8[0][A] dut/u_pwm/n270_s2/I0
0.894 0.372 tINS RF 1 R20C8[0][A] dut/u_pwm/n270_s2/F
0.894 0.000 tNET FF 1 R20C8[0][A] dut/u_pwm/cnt_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 92 BOTTOMSIDE[0] u_CLKDIV/CLKOUT
0.183 0.183 tNET RR 1 R20C8[0][A] dut/u_pwm/cnt_0_s0/CLK
0.183 0.000 tHld 1 R20C8[0][A] dut/u_pwm/cnt_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay cell: 0.372, 52.303%; route: 0.006, 0.830%; tC2Q: 0.333, 46.867%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%

Path17

Path Summary:

Slack 0.712
Data Arrival Time 0.895
Data Required Time 0.183
From gw_gvio_inst_0/u_gvio0_top/probe_out6_reg1_0_s2
To gw_gvio_inst_0/u_gvio0_top/probe_out6_reg1_0_s2
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 92 BOTTOMSIDE[0] u_CLKDIV/CLKOUT
0.183 0.183 tNET RR 1 R22C11[0][A] gw_gvio_inst_0/u_gvio0_top/probe_out6_reg1_0_s2/CLK
0.516 0.333 tC2Q RR 13 R22C11[0][A] gw_gvio_inst_0/u_gvio0_top/probe_out6_reg1_0_s2/Q
0.523 0.007 tNET RR 1 R22C11[0][A] gw_gvio_inst_0/u_gvio0_top/probe_out6_reg1_0_s14/I0
0.895 0.372 tINS RF 1 R22C11[0][A] gw_gvio_inst_0/u_gvio0_top/probe_out6_reg1_0_s14/F
0.895 0.000 tNET FF 1 R22C11[0][A] gw_gvio_inst_0/u_gvio0_top/probe_out6_reg1_0_s2/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 92 BOTTOMSIDE[0] u_CLKDIV/CLKOUT
0.183 0.183 tNET RR 1 R22C11[0][A] gw_gvio_inst_0/u_gvio0_top/probe_out6_reg1_0_s2/CLK
0.183 0.000 tHld 1 R22C11[0][A] gw_gvio_inst_0/u_gvio0_top/probe_out6_reg1_0_s2

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay cell: 0.372, 52.217%; route: 0.007, 0.994%; tC2Q: 0.333, 46.789%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%

Path18

Path Summary:

Slack 0.731
Data Arrival Time 0.914
Data Required Time 0.183
From dut/u_pwm/cnt_6_s0
To dut/u_pwm/cnt_6_s0
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 92 BOTTOMSIDE[0] u_CLKDIV/CLKOUT
0.183 0.183 tNET RR 1 R18C8[1][A] dut/u_pwm/cnt_6_s0/CLK
0.516 0.333 tC2Q RR 5 R18C8[1][A] dut/u_pwm/cnt_6_s0/Q
0.520 0.004 tNET RR 2 R18C8[1][A] dut/u_pwm/n264_s/I1
0.914 0.394 tINS RF 1 R18C8[1][A] dut/u_pwm/n264_s/SUM
0.914 0.000 tNET FF 1 R18C8[1][A] dut/u_pwm/cnt_6_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 92 BOTTOMSIDE[0] u_CLKDIV/CLKOUT
0.183 0.183 tNET RR 1 R18C8[1][A] dut/u_pwm/cnt_6_s0/CLK
0.183 0.000 tHld 1 R18C8[1][A] dut/u_pwm/cnt_6_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay cell: 0.394, 53.908%; route: 0.004, 0.485%; tC2Q: 0.333, 45.607%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%

Path19

Path Summary:

Slack 0.733
Data Arrival Time 0.916
Data Required Time 0.183
From dut/u_pwm/cnt_4_s0
To dut/u_pwm/cnt_4_s0
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 92 BOTTOMSIDE[0] u_CLKDIV/CLKOUT
0.183 0.183 tNET RR 1 R18C8[0][A] dut/u_pwm/cnt_4_s0/CLK
0.516 0.333 tC2Q RR 7 R18C8[0][A] dut/u_pwm/cnt_4_s0/Q
0.522 0.006 tNET RR 2 R18C8[0][A] dut/u_pwm/n266_s/I1
0.916 0.394 tINS RF 1 R18C8[0][A] dut/u_pwm/n266_s/SUM
0.916 0.000 tNET FF 1 R18C8[0][A] dut/u_pwm/cnt_4_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 92 BOTTOMSIDE[0] u_CLKDIV/CLKOUT
0.183 0.183 tNET RR 1 R18C8[0][A] dut/u_pwm/cnt_4_s0/CLK
0.183 0.000 tHld 1 R18C8[0][A] dut/u_pwm/cnt_4_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay cell: 0.394, 53.734%; route: 0.006, 0.805%; tC2Q: 0.333, 45.461%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%

Path20

Path Summary:

Slack 0.837
Data Arrival Time 1.032
Data Required Time 0.196
From gw_gvio_inst_0/u_gvio0_top/probe_out6_reg1_0_s2
To gw_gvio_inst_0/u_gvio0_top/probe_out6_reg1_0_s8
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 92 BOTTOMSIDE[0] u_CLKDIV/CLKOUT
0.183 0.183 tNET RR 1 R22C11[0][A] gw_gvio_inst_0/u_gvio0_top/probe_out6_reg1_0_s2/CLK
0.516 0.333 tC2Q RR 13 R22C11[0][A] gw_gvio_inst_0/u_gvio0_top/probe_out6_reg1_0_s2/Q
1.032 0.516 tNET RR 1 R24C11 gw_gvio_inst_0/u_gvio0_top/probe_out6_reg1_0_s8/AD[0]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 92 BOTTOMSIDE[0] u_CLKDIV/CLKOUT
0.183 0.183 tNET RR 1 R24C11 gw_gvio_inst_0/u_gvio0_top/probe_out6_reg1_0_s8/CLK
0.196 0.012 tHld 1 R24C11 gw_gvio_inst_0/u_gvio0_top/probe_out6_reg1_0_s8

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.516, 60.754%; tC2Q: 0.333, 39.246%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%

Path21

Path Summary:

Slack 0.854
Data Arrival Time 1.037
Data Required Time 0.183
From dut/u_pwm/cnt_1_s0
To dut/u_pwm/cnt_1_s0
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 92 BOTTOMSIDE[0] u_CLKDIV/CLKOUT
0.183 0.183 tNET RR 1 R18C7[1][B] dut/u_pwm/cnt_1_s0/CLK
0.516 0.333 tC2Q RR 5 R18C7[1][B] dut/u_pwm/cnt_1_s0/Q
0.520 0.004 tNET RR 2 R18C7[1][B] dut/u_pwm/n269_s/I0
1.037 0.517 tINS RF 1 R18C7[1][B] dut/u_pwm/n269_s/SUM
1.037 0.000 tNET FF 1 R18C7[1][B] dut/u_pwm/cnt_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 92 BOTTOMSIDE[0] u_CLKDIV/CLKOUT
0.183 0.183 tNET RR 1 R18C7[1][B] dut/u_pwm/cnt_1_s0/CLK
0.183 0.000 tHld 1 R18C7[1][B] dut/u_pwm/cnt_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay cell: 0.517, 60.548%; route: 0.004, 0.415%; tC2Q: 0.333, 39.038%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%

Path22

Path Summary:

Slack 0.869
Data Arrival Time 1.064
Data Required Time 0.196
From dut/u_pwm/d_5_s0
To dut/u_pwm/u_OSER8
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 92 BOTTOMSIDE[0] u_CLKDIV/CLKOUT
0.183 0.183 tNET RR 1 R24C8[2][A] dut/u_pwm/d_5_s0/CLK
0.516 0.333 tC2Q RR 1 R24C8[2][A] dut/u_pwm/d_5_s0/Q
1.064 0.548 tNET RR 1 IOB8[B] dut/u_pwm/u_OSER8/D5

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 92 BOTTOMSIDE[0] u_CLKDIV/CLKOUT
0.183 0.183 tNET RR 1 IOB8[B] dut/u_pwm/u_OSER8/PCLK
0.196 0.012 tHld 1 IOB8[B] dut/u_pwm/u_OSER8

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.548, 62.168%; tC2Q: 0.333, 37.832%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%

Path23

Path Summary:

Slack 0.869
Data Arrival Time 1.064
Data Required Time 0.196
From dut/u_pwm/d_3_s0
To dut/u_pwm/u_OSER8
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 92 BOTTOMSIDE[0] u_CLKDIV/CLKOUT
0.183 0.183 tNET RR 1 R24C8[2][B] dut/u_pwm/d_3_s0/CLK
0.516 0.333 tC2Q RR 1 R24C8[2][B] dut/u_pwm/d_3_s0/Q
1.064 0.548 tNET RR 1 IOB8[B] dut/u_pwm/u_OSER8/D3

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 92 BOTTOMSIDE[0] u_CLKDIV/CLKOUT
0.183 0.183 tNET RR 1 IOB8[B] dut/u_pwm/u_OSER8/PCLK
0.196 0.012 tHld 1 IOB8[B] dut/u_pwm/u_OSER8

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.548, 62.168%; tC2Q: 0.333, 37.832%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%

Path24

Path Summary:

Slack 0.892
Data Arrival Time 4.094
Data Required Time 3.202
From gw_gvio_inst_0/u_gvio0_top/bit_count_4_s1
To gw_gvio_inst_0/u_gvio0_top/bit_count_4_s1
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOL11[B] tck_pad_i_ibuf/I
1.392 1.392 tINS RR 1 IOL11[B] tck_pad_i_ibuf/O
1.392 0.000 tNET RR 1 R1C1 gw_gvio_inst_0/u_gw_jtag/tck_pad_i
2.236 0.844 tINS RR 139 R1C1 gw_gvio_inst_0/u_gw_jtag/tck_o
3.202 0.966 tNET RR 1 R18C21[2][A] gw_gvio_inst_0/u_gvio0_top/bit_count_4_s1/CLK
3.536 0.333 tC2Q RR 4 R18C21[2][A] gw_gvio_inst_0/u_gvio0_top/bit_count_4_s1/Q
3.538 0.002 tNET RR 1 R18C21[2][A] gw_gvio_inst_0/u_gvio0_top/n872_s4/I0
4.094 0.556 tINS RR 1 R18C21[2][A] gw_gvio_inst_0/u_gvio0_top/n872_s4/F
4.094 0.000 tNET RR 1 R18C21[2][A] gw_gvio_inst_0/u_gvio0_top/bit_count_4_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOL11[B] tck_pad_i_ibuf/I
1.392 1.392 tINS RR 1 IOL11[B] tck_pad_i_ibuf/O
1.392 0.000 tNET RR 1 R1C1 gw_gvio_inst_0/u_gw_jtag/tck_pad_i
2.236 0.844 tINS RR 139 R1C1 gw_gvio_inst_0/u_gw_jtag/tck_o
3.202 0.966 tNET RR 1 R18C21[2][A] gw_gvio_inst_0/u_gvio0_top/bit_count_4_s1/CLK
3.202 0.000 tHld 1 R18C21[2][A] gw_gvio_inst_0/u_gvio0_top/bit_count_4_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 2.236, 69.836%; route: 0.966, 30.164%
Arrival Data Path Delay cell: 0.556, 62.353%; route: 0.002, 0.265%; tC2Q: 0.333, 37.382%
Required Clock Path Delay cell: 2.236, 69.836%; route: 0.966, 30.164%

Path25

Path Summary:

Slack 0.894
Data Arrival Time 4.096
Data Required Time 3.202
From gw_gvio_inst_0/u_gvio0_top/bit_count_2_s1
To gw_gvio_inst_0/u_gvio0_top/bit_count_2_s1
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOL11[B] tck_pad_i_ibuf/I
1.392 1.392 tINS RR 1 IOL11[B] tck_pad_i_ibuf/O
1.392 0.000 tNET RR 1 R1C1 gw_gvio_inst_0/u_gw_jtag/tck_pad_i
2.236 0.844 tINS RR 139 R1C1 gw_gvio_inst_0/u_gw_jtag/tck_o
3.202 0.966 tNET RR 1 R20C20[2][A] gw_gvio_inst_0/u_gvio0_top/bit_count_2_s1/CLK
3.536 0.333 tC2Q RR 4 R20C20[2][A] gw_gvio_inst_0/u_gvio0_top/bit_count_2_s1/Q
3.540 0.005 tNET RR 1 R20C20[2][A] gw_gvio_inst_0/u_gvio0_top/n874_s2/I2
4.096 0.556 tINS RR 1 R20C20[2][A] gw_gvio_inst_0/u_gvio0_top/n874_s2/F
4.096 0.000 tNET RR 1 R20C20[2][A] gw_gvio_inst_0/u_gvio0_top/bit_count_2_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOL11[B] tck_pad_i_ibuf/I
1.392 1.392 tINS RR 1 IOL11[B] tck_pad_i_ibuf/O
1.392 0.000 tNET RR 1 R1C1 gw_gvio_inst_0/u_gw_jtag/tck_pad_i
2.236 0.844 tINS RR 139 R1C1 gw_gvio_inst_0/u_gw_jtag/tck_o
3.202 0.966 tNET RR 1 R20C20[2][A] gw_gvio_inst_0/u_gvio0_top/bit_count_2_s1/CLK
3.202 0.000 tHld 1 R20C20[2][A] gw_gvio_inst_0/u_gvio0_top/bit_count_2_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 2.236, 69.836%; route: 0.966, 30.164%
Arrival Data Path Delay cell: 0.556, 62.189%; route: 0.005, 0.528%; tC2Q: 0.333, 37.283%
Required Clock Path Delay cell: 2.236, 69.836%; route: 0.966, 30.164%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

No recovery paths to report!

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

No removal paths to report!

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack: 3.676
Actual Width: 4.926
Required Width: 1.250
Type: Low Pulse Width
Clock: pclk
Objects: gw_gvio_inst_0/u_gvio0_top/probe_out0_reg1_0_s0

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 pclk
5.000 0.000 tCL FF u_CLKDIV/CLKOUT
5.257 0.257 tNET FF gw_gvio_inst_0/u_gvio0_top/probe_out0_reg1_0_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 pclk
10.000 0.000 tCL RR u_CLKDIV/CLKOUT
10.183 0.183 tNET RR gw_gvio_inst_0/u_gvio0_top/probe_out0_reg1_0_s0/CLK

MPW2

MPW Summary:

Slack: 3.676
Actual Width: 4.926
Required Width: 1.250
Type: Low Pulse Width
Clock: pclk
Objects: gw_gvio_inst_0/u_gvio0_top/probe_out1_reg1_1_s0

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 pclk
5.000 0.000 tCL FF u_CLKDIV/CLKOUT
5.257 0.257 tNET FF gw_gvio_inst_0/u_gvio0_top/probe_out1_reg1_1_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 pclk
10.000 0.000 tCL RR u_CLKDIV/CLKOUT
10.183 0.183 tNET RR gw_gvio_inst_0/u_gvio0_top/probe_out1_reg1_1_s0/CLK

MPW3

MPW Summary:

Slack: 3.676
Actual Width: 4.926
Required Width: 1.250
Type: Low Pulse Width
Clock: pclk
Objects: gw_gvio_inst_0/u_gvio0_top/probe_out2_reg1_9_s0

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 pclk
5.000 0.000 tCL FF u_CLKDIV/CLKOUT
5.257 0.257 tNET FF gw_gvio_inst_0/u_gvio0_top/probe_out2_reg1_9_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 pclk
10.000 0.000 tCL RR u_CLKDIV/CLKOUT
10.183 0.183 tNET RR gw_gvio_inst_0/u_gvio0_top/probe_out2_reg1_9_s0/CLK

MPW4

MPW Summary:

Slack: 3.676
Actual Width: 4.926
Required Width: 1.250
Type: Low Pulse Width
Clock: pclk
Objects: gw_gvio_inst_0/u_gvio0_top/probe_out2_reg2_8_s0

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 pclk
5.000 0.000 tCL FF u_CLKDIV/CLKOUT
5.257 0.257 tNET FF gw_gvio_inst_0/u_gvio0_top/probe_out2_reg2_8_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 pclk
10.000 0.000 tCL RR u_CLKDIV/CLKOUT
10.183 0.183 tNET RR gw_gvio_inst_0/u_gvio0_top/probe_out2_reg2_8_s0/CLK

MPW5

MPW Summary:

Slack: 3.676
Actual Width: 4.926
Required Width: 1.250
Type: Low Pulse Width
Clock: pclk
Objects: dut/u_pwm/down_d1_s0

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 pclk
5.000 0.000 tCL FF u_CLKDIV/CLKOUT
5.257 0.257 tNET FF dut/u_pwm/down_d1_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 pclk
10.000 0.000 tCL RR u_CLKDIV/CLKOUT
10.183 0.183 tNET RR dut/u_pwm/down_d1_s0/CLK

MPW6

MPW Summary:

Slack: 3.676
Actual Width: 4.926
Required Width: 1.250
Type: Low Pulse Width
Clock: pclk
Objects: dut/u_pwm/d_3_s0

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 pclk
5.000 0.000 tCL FF u_CLKDIV/CLKOUT
5.257 0.257 tNET FF dut/u_pwm/d_3_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 pclk
10.000 0.000 tCL RR u_CLKDIV/CLKOUT
10.183 0.183 tNET RR dut/u_pwm/d_3_s0/CLK

MPW7

MPW Summary:

Slack: 3.676
Actual Width: 4.926
Required Width: 1.250
Type: Low Pulse Width
Clock: pclk
Objects: dut/u_pwm/d_4_s0

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 pclk
5.000 0.000 tCL FF u_CLKDIV/CLKOUT
5.257 0.257 tNET FF dut/u_pwm/d_4_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 pclk
10.000 0.000 tCL RR u_CLKDIV/CLKOUT
10.183 0.183 tNET RR dut/u_pwm/d_4_s0/CLK

MPW8

MPW Summary:

Slack: 3.676
Actual Width: 4.926
Required Width: 1.250
Type: Low Pulse Width
Clock: pclk
Objects: dut/u_pwm/down_d0_s0

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 pclk
5.000 0.000 tCL FF u_CLKDIV/CLKOUT
5.257 0.257 tNET FF dut/u_pwm/down_d0_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 pclk
10.000 0.000 tCL RR u_CLKDIV/CLKOUT
10.183 0.183 tNET RR dut/u_pwm/down_d0_s0/CLK

MPW9

MPW Summary:

Slack: 3.676
Actual Width: 4.926
Required Width: 1.250
Type: Low Pulse Width
Clock: pclk
Objects: dut/u_pwm/d_5_s0

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 pclk
5.000 0.000 tCL FF u_CLKDIV/CLKOUT
5.257 0.257 tNET FF dut/u_pwm/d_5_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 pclk
10.000 0.000 tCL RR u_CLKDIV/CLKOUT
10.183 0.183 tNET RR dut/u_pwm/d_5_s0/CLK

MPW10

MPW Summary:

Slack: 3.676
Actual Width: 4.926
Required Width: 1.250
Type: Low Pulse Width
Clock: pclk
Objects: dut/u_pwm/d_6_s0

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 pclk
5.000 0.000 tCL FF u_CLKDIV/CLKOUT
5.257 0.257 tNET FF dut/u_pwm/d_6_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 pclk
10.000 0.000 tCL RR u_CLKDIV/CLKOUT
10.183 0.183 tNET RR dut/u_pwm/d_6_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT NET NAME WORST SLACK MAX DELAY
139 gw_gvio_inst_0/control0[0] 3.163 1.726
92 pclk_d 0.185 0.659
37 gw_gvio_inst_0/u_gvio0_top/n16_3 43.601 2.295
32 gw_gvio_inst_0/u_gvio0_top/tdi_i_d 46.519 2.623
29 gw_gvio_inst_0/u_gvio0_top/addr_all[0] 41.658 1.822
28 gw_gvio_inst_0/u_gvio0_top/addr_all[1] 41.859 1.686
22 gw_gvio_inst_0/u_gvio0_top/probe_num[2] 44.741 1.503
18 gw_gvio_inst_0/u_gvio0_top/data_out_shift_reg_8_9 41.886 1.513
18 gw_gvio_inst_0/u_gvio0_top/bit_ct_rst 42.138 1.318
17 dut/u_pwm/n156_3 1.865 1.333

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC ROUTE CONGESTIONS
R2C2 100.00%
R2C7 100.00%
R2C9 100.00%
R2C10 100.00%
R2C26 100.00%
R3C13 100.00%
R4C32 100.00%
R7C25 100.00%
R13C43 100.00%
R25C41 100.00%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type State Detail Command
TC_CLOCK Actived create_clock -name tck_pad_i -period 50 -waveform {0 25} [get_ports {tck_pad_i}]
TC_CLOCK Actived create_clock -name pclk -period 10 -waveform {0 5} [get_pins {u_CLKDIV/CLKOUT}]