Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | E:\myWork\IP\releaseVerify\version\1.9.11.02\Gowin_PWM_RefDesign\project\src\gowin_rpll\gowin_rpll.v E:\myWork\IP\releaseVerify\version\1.9.11.02\Gowin_PWM_RefDesign\project\src\pwm\pwm.v E:\myWork\IP\releaseVerify\version\1.9.11.02\Gowin_PWM_RefDesign\project\src\top.v C:\Gowin\Gowin_V1.9.11.02_x64\IDE\data\ipcores\GVIO\GW_GVIO_0\gw_gvio_ao_top.v C:\Gowin\Gowin_V1.9.11.02_x64\IDE\data\ipcores\GVIO\GW_GVIO_CON\gw_gvio_con_top.v C:\Gowin\Gowin_V1.9.11.02_x64\IDE\data\ipcores\gw_jtag.v E:\myWork\IP\releaseVerify\version\1.9.11.02\Gowin_PWM_RefDesign\project\impl\gwsynthesis\GVIO\gw_gvio_top.v |
GowinSynthesis Constraints File | --- |
Tool Version | V1.9.11.02 (64-bit) |
Part Number | GW1N-LV9QN88C6/I5 |
Device | GW1N-9 |
Device Version | C |
Created Time | Tue Apr 15 15:18:41 2025 |
Legal Announcement | Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | top |
Synthesis Process | Running parser: CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.166s, Peak memory usage = 491.770MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 491.770MB Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 491.770MB Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.02s, Peak memory usage = 491.770MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 491.770MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 491.770MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 491.770MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 491.770MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 491.770MB Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 491.770MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 491.770MB Tech-Mapping Phase 3: CPU time = 0h 0m 0.468s, Elapsed time = 0h 0m 0.52s, Peak memory usage = 491.770MB Tech-Mapping Phase 4: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.081s, Peak memory usage = 491.770MB Generate output files: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.02s, Peak memory usage = 491.770MB |
Total Time and Memory Usage | CPU time = 0h 0m 0.762s, Elapsed time = 0h 0m 0.849s, Peak memory usage = 491.770MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 7 |
I/O Buf | 7 |
    IBUF | 4 |
    OBUF | 3 |
Register | 223 |
    DFF | 36 |
    DFFE | 82 |
    DFFR | 16 |
    DFFRE | 2 |
    DFFC | 9 |
    DFFCE | 78 |
LUT | 240 |
    LUT2 | 28 |
    LUT3 | 63 |
    LUT4 | 149 |
MUX | 1 |
    MUX16 | 1 |
ALU | 19 |
    ALU | 19 |
SSRAM | 6 |
    RAM16S4 | 6 |
INV | 7 |
    INV | 7 |
IOLOGIC | 1 |
    OSER8 | 1 |
CLOCK | 2 |
    CLKDIV | 1 |
    rPLL | 1 |
Black Box | 1 |
    GW_JTAG | 1 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 310(255 LUT, 19 ALU, 6 RAM16) / 8640 | 4% |
Register | 223 / 6693 | 4% |
  --Register as Latch | 0 / 6693 | 0% |
  --Register as FF | 223 / 6693 | 4% |
BSRAM | 0 / 26 | 0% |
Timing
Clock Summary:
NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|---|
1 | clk | Base | 20.000 | 50.000 | 0.000 | 10.000 | clk_ibuf/I | ||
2 | Gowin_PLL/rpll_inst/CLKOUT.default_gen_clk | Generated | 2.500 | 400.000 | 0.000 | 1.250 | clk_ibuf/I | clk | Gowin_PLL/rpll_inst/CLKOUT |
3 | Gowin_PLL/rpll_inst/CLKOUTP.default_gen_clk | Generated | 2.500 | 400.000 | 0.000 | 1.250 | clk_ibuf/I | clk | Gowin_PLL/rpll_inst/CLKOUTP |
4 | Gowin_PLL/rpll_inst/CLKOUTD.default_gen_clk | Generated | 5.000 | 200.000 | 0.000 | 2.500 | clk_ibuf/I | clk | Gowin_PLL/rpll_inst/CLKOUTD |
5 | Gowin_PLL/rpll_inst/CLKOUTD3.default_gen_clk | Generated | 7.500 | 133.333 | 0.000 | 3.750 | clk_ibuf/I | clk | Gowin_PLL/rpll_inst/CLKOUTD3 |
6 | u_CLKDIV/CLKOUT.default_gen_clk | Generated | 10.000 | 100.000 | 0.000 | 5.000 | Gowin_PLL/rpll_inst/CLKOUT | Gowin_PLL/rpll_inst/CLKOUT.default_gen_clk | u_CLKDIV/CLKOUT |
Max Frequency Summary:
NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | u_CLKDIV/CLKOUT.default_gen_clk | 100.000(MHz) | 88.997(MHz) | 7 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | -1.236 |
Data Arrival Time | 12.289 |
Data Required Time | 11.053 |
From | dut/u_pwm/cnt_0_s0 |
To | dut/u_pwm/d_0_s0 |
Launch Clk | u_CLKDIV/CLKOUT.default_gen_clk[R] |
Latch Clk | u_CLKDIV/CLKOUT.default_gen_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | u_CLKDIV/CLKOUT.default_gen_clk | |||
0.727 | 0.727 | tCL | RR | 92 | u_CLKDIV/CLKOUT |
1.453 | 0.726 | tNET | RR | 1 | dut/u_pwm/cnt_0_s0/CLK |
1.911 | 0.458 | tC2Q | RF | 6 | dut/u_pwm/cnt_0_s0/Q |
2.871 | 0.960 | tNET | FF | 2 | dut/u_pwm/n278_s14/I1 |
3.916 | 1.045 | tINS | FF | 1 | dut/u_pwm/n278_s14/COUT |
3.916 | 0.000 | tNET | FF | 2 | dut/u_pwm/n278_s15/CIN |
3.973 | 0.057 | tINS | FF | 1 | dut/u_pwm/n278_s15/COUT |
3.973 | 0.000 | tNET | FF | 2 | dut/u_pwm/n278_s16/CIN |
4.030 | 0.057 | tINS | FF | 1 | dut/u_pwm/n278_s16/COUT |
4.030 | 0.000 | tNET | FF | 2 | dut/u_pwm/n278_s17/CIN |
4.087 | 0.057 | tINS | FF | 1 | dut/u_pwm/n278_s17/COUT |
4.087 | 0.000 | tNET | FF | 2 | dut/u_pwm/n278_s18/CIN |
4.144 | 0.057 | tINS | FF | 1 | dut/u_pwm/n278_s18/COUT |
4.144 | 0.000 | tNET | FF | 2 | dut/u_pwm/n278_s19/CIN |
4.201 | 0.057 | tINS | FF | 1 | dut/u_pwm/n278_s19/COUT |
5.161 | 0.960 | tNET | FF | 1 | dut/u_pwm/n278_s20/I2 |
5.983 | 0.822 | tINS | FF | 4 | dut/u_pwm/n278_s20/F |
6.943 | 0.960 | tNET | FF | 1 | dut/u_pwm/n335_s1/I2 |
7.765 | 0.822 | tINS | FF | 3 | dut/u_pwm/n335_s1/F |
8.725 | 0.960 | tNET | FF | 1 | dut/u_pwm/n337_s1/I2 |
9.547 | 0.822 | tINS | FF | 2 | dut/u_pwm/n337_s1/F |
10.507 | 0.960 | tNET | FF | 1 | dut/u_pwm/n338_s1/I2 |
11.329 | 0.822 | tINS | FF | 1 | dut/u_pwm/n338_s1/F |
12.289 | 0.960 | tNET | FF | 1 | dut/u_pwm/d_0_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | u_CLKDIV/CLKOUT.default_gen_clk | |||
10.727 | 0.727 | tCL | RR | 92 | u_CLKDIV/CLKOUT |
11.453 | 0.726 | tNET | RR | 1 | dut/u_pwm/d_0_s0/CLK |
11.053 | -0.400 | tSu | 1 | dut/u_pwm/d_0_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 7 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Arrival Data Path Delay: | cell: 4.618, 42.616%; route: 5.760, 53.154%; tC2Q: 0.458, 4.230% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Path 2
Path Summary:Slack | -0.054 |
Data Arrival Time | 11.107 |
Data Required Time | 11.053 |
From | dut/u_pwm/duty_cycle_int_1_s1 |
To | dut/u_pwm/duty_cycle_int_5_s1 |
Launch Clk | u_CLKDIV/CLKOUT.default_gen_clk[R] |
Latch Clk | u_CLKDIV/CLKOUT.default_gen_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | u_CLKDIV/CLKOUT.default_gen_clk | |||
0.727 | 0.727 | tCL | RR | 92 | u_CLKDIV/CLKOUT |
1.453 | 0.726 | tNET | RR | 1 | dut/u_pwm/duty_cycle_int_1_s1/CLK |
1.911 | 0.458 | tC2Q | RF | 7 | dut/u_pwm/duty_cycle_int_1_s1/Q |
2.871 | 0.960 | tNET | FF | 1 | dut/u_pwm/n65_s8/I1 |
3.970 | 1.099 | tINS | FF | 7 | dut/u_pwm/n65_s8/F |
4.930 | 0.960 | tNET | FF | 1 | dut/u_pwm/n69_s4/I1 |
6.029 | 1.099 | tINS | FF | 1 | dut/u_pwm/n69_s4/F |
6.989 | 0.960 | tNET | FF | 1 | dut/u_pwm/n69_s2/I1 |
8.088 | 1.099 | tINS | FF | 1 | dut/u_pwm/n69_s2/F |
9.048 | 0.960 | tNET | FF | 1 | dut/u_pwm/n69_s0/I1 |
10.147 | 1.099 | tINS | FF | 1 | dut/u_pwm/n69_s0/F |
11.107 | 0.960 | tNET | FF | 1 | dut/u_pwm/duty_cycle_int_5_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | u_CLKDIV/CLKOUT.default_gen_clk | |||
10.727 | 0.727 | tCL | RR | 92 | u_CLKDIV/CLKOUT |
11.453 | 0.726 | tNET | RR | 1 | dut/u_pwm/duty_cycle_int_5_s1/CLK |
11.053 | -0.400 | tSu | 1 | dut/u_pwm/duty_cycle_int_5_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Arrival Data Path Delay: | cell: 4.396, 45.534%; route: 4.800, 49.719%; tC2Q: 0.458, 4.747% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Path 3
Path Summary:Slack | -0.054 |
Data Arrival Time | 11.107 |
Data Required Time | 11.053 |
From | dut/u_pwm/duty_cycle_int_1_s1 |
To | dut/u_pwm/duty_cycle_int_7_s1 |
Launch Clk | u_CLKDIV/CLKOUT.default_gen_clk[R] |
Latch Clk | u_CLKDIV/CLKOUT.default_gen_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | u_CLKDIV/CLKOUT.default_gen_clk | |||
0.727 | 0.727 | tCL | RR | 92 | u_CLKDIV/CLKOUT |
1.453 | 0.726 | tNET | RR | 1 | dut/u_pwm/duty_cycle_int_1_s1/CLK |
1.911 | 0.458 | tC2Q | RF | 7 | dut/u_pwm/duty_cycle_int_1_s1/Q |
2.871 | 0.960 | tNET | FF | 1 | dut/u_pwm/n65_s8/I1 |
3.970 | 1.099 | tINS | FF | 7 | dut/u_pwm/n65_s8/F |
4.930 | 0.960 | tNET | FF | 1 | dut/u_pwm/n67_s4/I1 |
6.029 | 1.099 | tINS | FF | 1 | dut/u_pwm/n67_s4/F |
6.989 | 0.960 | tNET | FF | 1 | dut/u_pwm/n67_s2/I1 |
8.088 | 1.099 | tINS | FF | 1 | dut/u_pwm/n67_s2/F |
9.048 | 0.960 | tNET | FF | 1 | dut/u_pwm/n67_s0/I1 |
10.147 | 1.099 | tINS | FF | 1 | dut/u_pwm/n67_s0/F |
11.107 | 0.960 | tNET | FF | 1 | dut/u_pwm/duty_cycle_int_7_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | u_CLKDIV/CLKOUT.default_gen_clk | |||
10.727 | 0.727 | tCL | RR | 92 | u_CLKDIV/CLKOUT |
11.453 | 0.726 | tNET | RR | 1 | dut/u_pwm/duty_cycle_int_7_s1/CLK |
11.053 | -0.400 | tSu | 1 | dut/u_pwm/duty_cycle_int_7_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Arrival Data Path Delay: | cell: 4.396, 45.534%; route: 4.800, 49.719%; tC2Q: 0.458, 4.747% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Path 4
Path Summary:Slack | 0.013 |
Data Arrival Time | 11.040 |
Data Required Time | 11.053 |
From | dut/u_pwm/duty_cycle_int_1_s1 |
To | dut/u_pwm/duty_cycle_int_4_s1 |
Launch Clk | u_CLKDIV/CLKOUT.default_gen_clk[R] |
Latch Clk | u_CLKDIV/CLKOUT.default_gen_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | u_CLKDIV/CLKOUT.default_gen_clk | |||
0.727 | 0.727 | tCL | RR | 92 | u_CLKDIV/CLKOUT |
1.453 | 0.726 | tNET | RR | 1 | dut/u_pwm/duty_cycle_int_1_s1/CLK |
1.911 | 0.458 | tC2Q | RF | 7 | dut/u_pwm/duty_cycle_int_1_s1/Q |
2.871 | 0.960 | tNET | FF | 1 | dut/u_pwm/n69_s3/I1 |
3.970 | 1.099 | tINS | FF | 6 | dut/u_pwm/n69_s3/F |
4.930 | 0.960 | tNET | FF | 1 | dut/u_pwm/n70_s6/I1 |
6.029 | 1.099 | tINS | FF | 1 | dut/u_pwm/n70_s6/F |
6.989 | 0.960 | tNET | FF | 1 | dut/u_pwm/n70_s1/I1 |
8.088 | 1.099 | tINS | FF | 1 | dut/u_pwm/n70_s1/F |
9.048 | 0.960 | tNET | FF | 1 | dut/u_pwm/n70_s7/I0 |
10.080 | 1.032 | tINS | FF | 1 | dut/u_pwm/n70_s7/F |
11.040 | 0.960 | tNET | FF | 1 | dut/u_pwm/duty_cycle_int_4_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | u_CLKDIV/CLKOUT.default_gen_clk | |||
10.727 | 0.727 | tCL | RR | 92 | u_CLKDIV/CLKOUT |
11.453 | 0.726 | tNET | RR | 1 | dut/u_pwm/duty_cycle_int_4_s1/CLK |
11.053 | -0.400 | tSu | 1 | dut/u_pwm/duty_cycle_int_4_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Arrival Data Path Delay: | cell: 4.329, 45.153%; route: 4.800, 50.066%; tC2Q: 0.458, 4.781% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Path 5
Path Summary:Slack | 0.013 |
Data Arrival Time | 11.040 |
Data Required Time | 11.053 |
From | dut/u_pwm/duty_cycle_int_1_s1 |
To | dut/u_pwm/duty_cycle_int_9_s1 |
Launch Clk | u_CLKDIV/CLKOUT.default_gen_clk[R] |
Latch Clk | u_CLKDIV/CLKOUT.default_gen_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | u_CLKDIV/CLKOUT.default_gen_clk | |||
0.727 | 0.727 | tCL | RR | 92 | u_CLKDIV/CLKOUT |
1.453 | 0.726 | tNET | RR | 1 | dut/u_pwm/duty_cycle_int_1_s1/CLK |
1.911 | 0.458 | tC2Q | RF | 7 | dut/u_pwm/duty_cycle_int_1_s1/Q |
2.871 | 0.960 | tNET | FF | 1 | dut/u_pwm/n65_s8/I1 |
3.970 | 1.099 | tINS | FF | 7 | dut/u_pwm/n65_s8/F |
4.930 | 0.960 | tNET | FF | 1 | dut/u_pwm/n65_s4/I1 |
6.029 | 1.099 | tINS | FF | 1 | dut/u_pwm/n65_s4/F |
6.989 | 0.960 | tNET | FF | 1 | dut/u_pwm/n65_s2/I0 |
8.021 | 1.032 | tINS | FF | 1 | dut/u_pwm/n65_s2/F |
8.981 | 0.960 | tNET | FF | 1 | dut/u_pwm/n65_s0/I1 |
10.080 | 1.099 | tINS | FF | 1 | dut/u_pwm/n65_s0/F |
11.040 | 0.960 | tNET | FF | 1 | dut/u_pwm/duty_cycle_int_9_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | u_CLKDIV/CLKOUT.default_gen_clk | |||
10.727 | 0.727 | tCL | RR | 92 | u_CLKDIV/CLKOUT |
11.453 | 0.726 | tNET | RR | 1 | dut/u_pwm/duty_cycle_int_9_s1/CLK |
11.053 | -0.400 | tSu | 1 | dut/u_pwm/duty_cycle_int_9_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Arrival Data Path Delay: | cell: 4.329, 45.153%; route: 4.800, 50.066%; tC2Q: 0.458, 4.781% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |