Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\picorv32.v
D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\picosoc.v
D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\advspi.v
D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\ahb_bus.v
D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\picosoc_dtcm.v
D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\picosoc_itcm.v
D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wb_bus.v
D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wb_brancher.v
D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wbgpio.v
D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wbi2c.v
D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wbspi.v
D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wbuart.v
D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\simpleuart.v
D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\dm.v
GowinSynthesis Constraints File ---
Tool Version V1.9.9.03 (64-bit)
Part Number GW2A-LV55PG484C8/I7
Device GW2A-55
Device Version C
Created Time Thu May 23 11:05:50 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module Gowin_PicoRV32_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 160.848MB
Running netlist conversion:
    CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.102s, Peak memory usage = 160.848MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.703s, Elapsed time = 0h 0m 0.709s, Peak memory usage = 160.848MB
    Optimizing Phase 1: CPU time = 0h 0m 0.296s, Elapsed time = 0h 0m 0.3s, Peak memory usage = 160.848MB
    Optimizing Phase 2: CPU time = 0h 0m 0.984s, Elapsed time = 0h 0m 0.974s, Peak memory usage = 160.848MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.296s, Elapsed time = 0h 0m 0.306s, Peak memory usage = 160.848MB
    Inferring Phase 1: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.06s, Peak memory usage = 160.848MB
    Inferring Phase 2: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.054s, Peak memory usage = 160.848MB
    Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.025s, Peak memory usage = 160.848MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 160.848MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.234s, Elapsed time = 0h 0m 0.234s, Peak memory usage = 160.848MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.39s, Elapsed time = 0h 0m 0.408s, Peak memory usage = 160.848MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 26s, Elapsed time = 0h 0m 26s, Peak memory usage = 178.520MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.625s, Elapsed time = 0h 0m 0.664s, Peak memory usage = 178.520MB
Generate output files:
    CPU time = 0h 0m 0.656s, Elapsed time = 0h 0m 0.658s, Peak memory usage = 206.254MB
Total Time and Memory Usage CPU time = 0h 0m 32s, Elapsed time = 0h 0m 32s, Peak memory usage = 206.254MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 241
I/O Buf 239
    IBUF 84
    OBUF 147
    TBUF 2
    IOBUF 6
Register 4011
    DFF 215
    DFFE 1842
    DFFS 20
    DFFSE 78
    DFFR 167
    DFFRE 570
    DFFP 6
    DFFPE 11
    DFFC 155
    DFFCE 947
LUT 6231
    LUT2 460
    LUT3 1991
    LUT4 3780
ALU 592
    ALU 592
SSRAM 24
    RAM16SDP4 24
INV 29
    INV 29
DSP
    MULT36X36 1
BSRAM 32
    SDPB 32

Resource Utilization Summary

Resource Usage Utilization
Logic 6996(6260 LUT, 592 ALU, 24 RAM16) / 54720 13%
Register 4011 / 41997 10%
  --Register as Latch 0 / 41997 0%
  --Register as FF 4011 / 41997 10%
BSRAM 32 / 140 23%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
clk_in Base 10.000 100.0 0.000 5.000 clk_in_ibuf/I
jtag_TCK Base 10.000 100.0 0.000 5.000 jtag_TCK_ibuf/I
u_dualportspi/u_atcspi/u_spi_spiif/n316_3 Base 10.000 100.0 0.000 5.000 u_dualportspi/u_atcspi/u_spi_spiif/n316_s0/F

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk_in 100.000(MHz) 50.408(MHz) 11 TOP
2 jtag_TCK 100.000(MHz) 102.690(MHz) 5 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack -8.314
Data Arrival Time 18.639
Data Required Time 10.325
From core/mem_addr_27_s0
To core/mem_rdata_q_27_s0
Launch Clk clk_in[R]
Latch Clk clk_in[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_in
0.000 0.000 tCL RR 1 clk_in_ibuf/I
0.000 0.000 tINS RR 3914 clk_in_ibuf/O
0.360 0.360 tNET RR 1 core/mem_addr_27_s0/CLK
0.592 0.232 tC2Q RF 3 core/mem_addr_27_s0/Q
1.066 0.474 tNET FF 1 itcm_valid_s3/I1
1.621 0.555 tINS FF 9 itcm_valid_s3/F
2.095 0.474 tNET FF 1 itcm_valid_s4/I3
2.466 0.371 tINS FF 9 itcm_valid_s4/F
2.940 0.474 tNET FF 1 u_dm/u_dm2dtm_cdc_tx/vld_set_s1/I0
3.457 0.517 tINS FF 5 u_dm/u_dm2dtm_cdc_tx/vld_set_s1/F
3.931 0.474 tNET FF 1 u_dm/u_dm2dtm_cdc_tx/vld_set_s0/I0
4.448 0.517 tINS FF 38 u_dm/u_dm2dtm_cdc_tx/vld_set_s0/F
4.922 0.474 tNET FF 1 u_dm/ram_addr_2_s2/I3
5.293 0.371 tINS FF 70 u_dm/ram_addr_2_s2/F
5.767 0.474 tNET FF 1 u_dm/ram_addr_0_s0/I2
6.220 0.453 tINS FF 103 u_dm/ram_addr_0_s0/F
6.694 0.474 tNET FF 1 u_dm/u_s_debug_ram/ram_dout_Z_12_s2/I2
7.147 0.453 tINS FF 1 u_dm/u_s_debug_ram/ram_dout_Z_12_s2/F
7.621 0.474 tNET FF 1 u_dm/u_s_debug_ram/ram_dout_Z_12_s0/I0
7.724 0.103 tINS FF 1 u_dm/u_s_debug_ram/ram_dout_Z_12_s0/O
8.198 0.474 tNET FF 1 u_dm/u_s_debug_ram/ram_dout_Z_12_s/I0
8.301 0.103 tINS FF 2 u_dm/u_s_debug_ram/ram_dout_Z_12_s/O
8.775 0.474 tNET FF 1 core/mem_rdata_latched_28_s11/I3
9.146 0.371 tINS FF 1 core/mem_rdata_latched_28_s11/F
9.620 0.474 tNET FF 1 core/mem_rdata_latched_28_s8/I0
10.137 0.517 tINS FF 1 core/mem_rdata_latched_28_s8/F
10.611 0.474 tNET FF 1 core/mem_rdata_latched_28_s4/I2
11.064 0.453 tINS FF 2 core/mem_rdata_latched_28_s4/F
11.538 0.474 tNET FF 1 core/mem_rdata_latched_12_s5/I1
12.093 0.555 tINS FF 4 core/mem_rdata_latched_12_s5/F
12.567 0.474 tNET FF 1 core/mem_rdata_latched_12_s3/I1
13.122 0.555 tINS FF 22 core/mem_rdata_latched_12_s3/F
13.596 0.474 tNET FF 1 core/mem_rdata_latched_12_s1/I1
14.151 0.555 tINS FF 26 core/mem_rdata_latched_12_s1/F
14.625 0.474 tNET FF 1 core/n2207_s18/I1
15.180 0.555 tINS FF 3 core/n2207_s18/F
15.654 0.474 tNET FF 1 core/n2207_s11/I1
16.209 0.555 tINS FF 1 core/n2207_s11/F
16.683 0.474 tNET FF 1 core/n2207_s3/I1
17.238 0.555 tINS FF 1 core/n2207_s3/F
17.712 0.474 tNET FF 1 core/n2207_s0/I2
18.165 0.453 tINS FF 1 core/n2207_s0/F
18.639 0.474 tNET FF 1 core/mem_rdata_q_27_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_in
10.000 0.000 tCL RR 1 clk_in_ibuf/I
10.000 0.000 tINS RR 3914 clk_in_ibuf/O
10.360 0.360 tNET RR 1 core/mem_rdata_q_27_s0/CLK
10.325 -0.035 tSu 1 core/mem_rdata_q_27_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 18
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%
Arrival Data Path Delay: cell: 8.567, 46.868%; route: 9.480, 51.863%; tC2Q: 0.232, 1.269%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%

Path 2

Path Summary:
Slack -8.314
Data Arrival Time 18.639
Data Required Time 10.325
From core/mem_addr_27_s0
To core/mem_rdata_q_30_s0
Launch Clk clk_in[R]
Latch Clk clk_in[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_in
0.000 0.000 tCL RR 1 clk_in_ibuf/I
0.000 0.000 tINS RR 3914 clk_in_ibuf/O
0.360 0.360 tNET RR 1 core/mem_addr_27_s0/CLK
0.592 0.232 tC2Q RF 3 core/mem_addr_27_s0/Q
1.066 0.474 tNET FF 1 itcm_valid_s3/I1
1.621 0.555 tINS FF 9 itcm_valid_s3/F
2.095 0.474 tNET FF 1 itcm_valid_s4/I3
2.466 0.371 tINS FF 9 itcm_valid_s4/F
2.940 0.474 tNET FF 1 u_dm/u_dm2dtm_cdc_tx/vld_set_s1/I0
3.457 0.517 tINS FF 5 u_dm/u_dm2dtm_cdc_tx/vld_set_s1/F
3.931 0.474 tNET FF 1 u_dm/u_dm2dtm_cdc_tx/vld_set_s0/I0
4.448 0.517 tINS FF 38 u_dm/u_dm2dtm_cdc_tx/vld_set_s0/F
4.922 0.474 tNET FF 1 u_dm/ram_addr_2_s2/I3
5.293 0.371 tINS FF 70 u_dm/ram_addr_2_s2/F
5.767 0.474 tNET FF 1 u_dm/ram_addr_0_s0/I2
6.220 0.453 tINS FF 103 u_dm/ram_addr_0_s0/F
6.694 0.474 tNET FF 1 u_dm/u_s_debug_ram/ram_dout_Z_12_s2/I2
7.147 0.453 tINS FF 1 u_dm/u_s_debug_ram/ram_dout_Z_12_s2/F
7.621 0.474 tNET FF 1 u_dm/u_s_debug_ram/ram_dout_Z_12_s0/I0
7.724 0.103 tINS FF 1 u_dm/u_s_debug_ram/ram_dout_Z_12_s0/O
8.198 0.474 tNET FF 1 u_dm/u_s_debug_ram/ram_dout_Z_12_s/I0
8.301 0.103 tINS FF 2 u_dm/u_s_debug_ram/ram_dout_Z_12_s/O
8.775 0.474 tNET FF 1 core/mem_rdata_latched_28_s11/I3
9.146 0.371 tINS FF 1 core/mem_rdata_latched_28_s11/F
9.620 0.474 tNET FF 1 core/mem_rdata_latched_28_s8/I0
10.137 0.517 tINS FF 1 core/mem_rdata_latched_28_s8/F
10.611 0.474 tNET FF 1 core/mem_rdata_latched_28_s4/I2
11.064 0.453 tINS FF 2 core/mem_rdata_latched_28_s4/F
11.538 0.474 tNET FF 1 core/mem_rdata_latched_12_s5/I1
12.093 0.555 tINS FF 4 core/mem_rdata_latched_12_s5/F
12.567 0.474 tNET FF 1 core/mem_rdata_latched_12_s3/I1
13.122 0.555 tINS FF 22 core/mem_rdata_latched_12_s3/F
13.596 0.474 tNET FF 1 core/mem_rdata_latched_12_s1/I1
14.151 0.555 tINS FF 26 core/mem_rdata_latched_12_s1/F
14.625 0.474 tNET FF 1 core/n2204_s9/I1
15.180 0.555 tINS FF 1 core/n2204_s9/F
15.654 0.474 tNET FF 1 core/n2204_s6/I2
16.107 0.453 tINS FF 1 core/n2204_s6/F
16.581 0.474 tNET FF 1 core/n2204_s2/I1
17.136 0.555 tINS FF 1 core/n2204_s2/F
17.610 0.474 tNET FF 1 core/n2204_s0/I1
18.165 0.555 tINS FF 1 core/n2204_s0/F
18.639 0.474 tNET FF 1 core/mem_rdata_q_30_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_in
10.000 0.000 tCL RR 1 clk_in_ibuf/I
10.000 0.000 tINS RR 3914 clk_in_ibuf/O
10.360 0.360 tNET RR 1 core/mem_rdata_q_30_s0/CLK
10.325 -0.035 tSu 1 core/mem_rdata_q_30_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 18
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%
Arrival Data Path Delay: cell: 8.567, 46.868%; route: 9.480, 51.863%; tC2Q: 0.232, 1.269%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%

Path 3

Path Summary:
Slack -8.276
Data Arrival Time 18.601
Data Required Time 10.325
From core/mem_addr_27_s0
To core/decoded_rs1_3_s0
Launch Clk clk_in[R]
Latch Clk clk_in[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_in
0.000 0.000 tCL RR 1 clk_in_ibuf/I
0.000 0.000 tINS RR 3914 clk_in_ibuf/O
0.360 0.360 tNET RR 1 core/mem_addr_27_s0/CLK
0.592 0.232 tC2Q RF 3 core/mem_addr_27_s0/Q
1.066 0.474 tNET FF 1 itcm_valid_s3/I1
1.621 0.555 tINS FF 9 itcm_valid_s3/F
2.095 0.474 tNET FF 1 itcm_valid_s4/I3
2.466 0.371 tINS FF 9 itcm_valid_s4/F
2.940 0.474 tNET FF 1 u_dm/u_dm2dtm_cdc_tx/vld_set_s1/I0
3.457 0.517 tINS FF 5 u_dm/u_dm2dtm_cdc_tx/vld_set_s1/F
3.931 0.474 tNET FF 1 u_dm/u_dm2dtm_cdc_tx/vld_set_s0/I0
4.448 0.517 tINS FF 38 u_dm/u_dm2dtm_cdc_tx/vld_set_s0/F
4.922 0.474 tNET FF 1 u_dm/ram_addr_2_s2/I3
5.293 0.371 tINS FF 70 u_dm/ram_addr_2_s2/F
5.767 0.474 tNET FF 1 u_dm/ram_addr_0_s0/I2
6.220 0.453 tINS FF 103 u_dm/ram_addr_0_s0/F
6.694 0.474 tNET FF 1 u_dm/u_s_debug_ram/ram_dout_Z_12_s2/I2
7.147 0.453 tINS FF 1 u_dm/u_s_debug_ram/ram_dout_Z_12_s2/F
7.621 0.474 tNET FF 1 u_dm/u_s_debug_ram/ram_dout_Z_12_s0/I0
7.724 0.103 tINS FF 1 u_dm/u_s_debug_ram/ram_dout_Z_12_s0/O
8.198 0.474 tNET FF 1 u_dm/u_s_debug_ram/ram_dout_Z_12_s/I0
8.301 0.103 tINS FF 2 u_dm/u_s_debug_ram/ram_dout_Z_12_s/O
8.775 0.474 tNET FF 1 core/mem_rdata_latched_28_s11/I3
9.146 0.371 tINS FF 1 core/mem_rdata_latched_28_s11/F
9.620 0.474 tNET FF 1 core/mem_rdata_latched_28_s8/I0
10.137 0.517 tINS FF 1 core/mem_rdata_latched_28_s8/F
10.611 0.474 tNET FF 1 core/mem_rdata_latched_28_s4/I2
11.064 0.453 tINS FF 2 core/mem_rdata_latched_28_s4/F
11.538 0.474 tNET FF 1 core/mem_rdata_latched_12_s5/I1
12.093 0.555 tINS FF 4 core/mem_rdata_latched_12_s5/F
12.567 0.474 tNET FF 1 core/mem_rdata_latched_12_s3/I1
13.122 0.555 tINS FF 22 core/mem_rdata_latched_12_s3/F
13.596 0.474 tNET FF 1 core/mem_rdata_latched_12_s1/I1
14.151 0.555 tINS FF 26 core/mem_rdata_latched_12_s1/F
14.625 0.474 tNET FF 1 core/n5710_s6/I1
15.180 0.555 tINS FF 4 core/n5710_s6/F
15.654 0.474 tNET FF 1 core/n5713_s5/I0
16.171 0.517 tINS FF 1 core/n5713_s5/F
16.645 0.474 tNET FF 1 core/n5713_s2/I1
17.200 0.555 tINS FF 1 core/n5713_s2/F
17.674 0.474 tNET FF 1 core/n5713_s0/I2
18.127 0.453 tINS FF 1 core/n5713_s0/F
18.601 0.474 tNET FF 1 core/decoded_rs1_3_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_in
10.000 0.000 tCL RR 1 clk_in_ibuf/I
10.000 0.000 tINS RR 3914 clk_in_ibuf/O
10.360 0.360 tNET RR 1 core/decoded_rs1_3_s0/CLK
10.325 -0.035 tSu 1 core/decoded_rs1_3_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 18
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%
Arrival Data Path Delay: cell: 8.529, 46.757%; route: 9.480, 51.971%; tC2Q: 0.232, 1.272%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%

Path 4

Path Summary:
Slack -8.238
Data Arrival Time 18.563
Data Required Time 10.325
From core/mem_addr_27_s0
To core/decoded_rs1_0_s0
Launch Clk clk_in[R]
Latch Clk clk_in[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_in
0.000 0.000 tCL RR 1 clk_in_ibuf/I
0.000 0.000 tINS RR 3914 clk_in_ibuf/O
0.360 0.360 tNET RR 1 core/mem_addr_27_s0/CLK
0.592 0.232 tC2Q RF 3 core/mem_addr_27_s0/Q
1.066 0.474 tNET FF 1 itcm_valid_s3/I1
1.621 0.555 tINS FF 9 itcm_valid_s3/F
2.095 0.474 tNET FF 1 itcm_valid_s4/I3
2.466 0.371 tINS FF 9 itcm_valid_s4/F
2.940 0.474 tNET FF 1 u_dm/u_dm2dtm_cdc_tx/vld_set_s1/I0
3.457 0.517 tINS FF 5 u_dm/u_dm2dtm_cdc_tx/vld_set_s1/F
3.931 0.474 tNET FF 1 u_dm/u_dm2dtm_cdc_tx/vld_set_s0/I0
4.448 0.517 tINS FF 38 u_dm/u_dm2dtm_cdc_tx/vld_set_s0/F
4.922 0.474 tNET FF 1 u_dm/ram_addr_2_s2/I3
5.293 0.371 tINS FF 70 u_dm/ram_addr_2_s2/F
5.767 0.474 tNET FF 1 u_dm/ram_addr_0_s0/I2
6.220 0.453 tINS FF 103 u_dm/ram_addr_0_s0/F
6.694 0.474 tNET FF 1 u_dm/u_s_debug_ram/ram_dout_Z_12_s2/I2
7.147 0.453 tINS FF 1 u_dm/u_s_debug_ram/ram_dout_Z_12_s2/F
7.621 0.474 tNET FF 1 u_dm/u_s_debug_ram/ram_dout_Z_12_s0/I0
7.724 0.103 tINS FF 1 u_dm/u_s_debug_ram/ram_dout_Z_12_s0/O
8.198 0.474 tNET FF 1 u_dm/u_s_debug_ram/ram_dout_Z_12_s/I0
8.301 0.103 tINS FF 2 u_dm/u_s_debug_ram/ram_dout_Z_12_s/O
8.775 0.474 tNET FF 1 core/mem_rdata_latched_28_s11/I3
9.146 0.371 tINS FF 1 core/mem_rdata_latched_28_s11/F
9.620 0.474 tNET FF 1 core/mem_rdata_latched_28_s8/I0
10.137 0.517 tINS FF 1 core/mem_rdata_latched_28_s8/F
10.611 0.474 tNET FF 1 core/mem_rdata_latched_28_s4/I2
11.064 0.453 tINS FF 2 core/mem_rdata_latched_28_s4/F
11.538 0.474 tNET FF 1 core/mem_rdata_latched_12_s5/I1
12.093 0.555 tINS FF 4 core/mem_rdata_latched_12_s5/F
12.567 0.474 tNET FF 1 core/mem_rdata_latched_12_s3/I1
13.122 0.555 tINS FF 22 core/mem_rdata_latched_12_s3/F
13.596 0.474 tNET FF 1 core/mem_rdata_latched_12_s1/I1
14.151 0.555 tINS FF 26 core/mem_rdata_latched_12_s1/F
14.625 0.474 tNET FF 1 core/n5710_s6/I1
15.180 0.555 tINS FF 4 core/n5710_s6/F
15.654 0.474 tNET FF 1 core/n5714_s4/I0
16.171 0.517 tINS FF 1 core/n5714_s4/F
16.645 0.474 tNET FF 1 core/n5714_s1/I2
17.098 0.453 tINS FF 2 core/n5714_s1/F
17.572 0.474 tNET FF 1 core/n5716_s0/I0
18.089 0.517 tINS FF 1 core/n5716_s0/F
18.563 0.474 tNET FF 1 core/decoded_rs1_0_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_in
10.000 0.000 tCL RR 1 clk_in_ibuf/I
10.000 0.000 tINS RR 3914 clk_in_ibuf/O
10.360 0.360 tNET RR 1 core/decoded_rs1_0_s0/CLK
10.325 -0.035 tSu 1 core/decoded_rs1_0_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 18
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%
Arrival Data Path Delay: cell: 8.491, 46.646%; route: 9.480, 52.079%; tC2Q: 0.232, 1.275%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%

Path 5

Path Summary:
Slack -8.238
Data Arrival Time 18.563
Data Required Time 10.325
From core/mem_addr_27_s0
To core/decoded_rs1_2_s0
Launch Clk clk_in[R]
Latch Clk clk_in[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_in
0.000 0.000 tCL RR 1 clk_in_ibuf/I
0.000 0.000 tINS RR 3914 clk_in_ibuf/O
0.360 0.360 tNET RR 1 core/mem_addr_27_s0/CLK
0.592 0.232 tC2Q RF 3 core/mem_addr_27_s0/Q
1.066 0.474 tNET FF 1 itcm_valid_s3/I1
1.621 0.555 tINS FF 9 itcm_valid_s3/F
2.095 0.474 tNET FF 1 itcm_valid_s4/I3
2.466 0.371 tINS FF 9 itcm_valid_s4/F
2.940 0.474 tNET FF 1 u_dm/u_dm2dtm_cdc_tx/vld_set_s1/I0
3.457 0.517 tINS FF 5 u_dm/u_dm2dtm_cdc_tx/vld_set_s1/F
3.931 0.474 tNET FF 1 u_dm/u_dm2dtm_cdc_tx/vld_set_s0/I0
4.448 0.517 tINS FF 38 u_dm/u_dm2dtm_cdc_tx/vld_set_s0/F
4.922 0.474 tNET FF 1 u_dm/ram_addr_2_s2/I3
5.293 0.371 tINS FF 70 u_dm/ram_addr_2_s2/F
5.767 0.474 tNET FF 1 u_dm/ram_addr_0_s0/I2
6.220 0.453 tINS FF 103 u_dm/ram_addr_0_s0/F
6.694 0.474 tNET FF 1 u_dm/u_s_debug_ram/ram_dout_Z_12_s2/I2
7.147 0.453 tINS FF 1 u_dm/u_s_debug_ram/ram_dout_Z_12_s2/F
7.621 0.474 tNET FF 1 u_dm/u_s_debug_ram/ram_dout_Z_12_s0/I0
7.724 0.103 tINS FF 1 u_dm/u_s_debug_ram/ram_dout_Z_12_s0/O
8.198 0.474 tNET FF 1 u_dm/u_s_debug_ram/ram_dout_Z_12_s/I0
8.301 0.103 tINS FF 2 u_dm/u_s_debug_ram/ram_dout_Z_12_s/O
8.775 0.474 tNET FF 1 core/mem_rdata_latched_28_s11/I3
9.146 0.371 tINS FF 1 core/mem_rdata_latched_28_s11/F
9.620 0.474 tNET FF 1 core/mem_rdata_latched_28_s8/I0
10.137 0.517 tINS FF 1 core/mem_rdata_latched_28_s8/F
10.611 0.474 tNET FF 1 core/mem_rdata_latched_28_s4/I2
11.064 0.453 tINS FF 2 core/mem_rdata_latched_28_s4/F
11.538 0.474 tNET FF 1 core/mem_rdata_latched_12_s5/I1
12.093 0.555 tINS FF 4 core/mem_rdata_latched_12_s5/F
12.567 0.474 tNET FF 1 core/mem_rdata_latched_12_s3/I1
13.122 0.555 tINS FF 22 core/mem_rdata_latched_12_s3/F
13.596 0.474 tNET FF 1 core/mem_rdata_latched_12_s1/I1
14.151 0.555 tINS FF 26 core/mem_rdata_latched_12_s1/F
14.625 0.474 tNET FF 1 core/n5710_s6/I1
15.180 0.555 tINS FF 4 core/n5710_s6/F
15.654 0.474 tNET FF 1 core/n5714_s4/I0
16.171 0.517 tINS FF 1 core/n5714_s4/F
16.645 0.474 tNET FF 1 core/n5714_s1/I2
17.098 0.453 tINS FF 2 core/n5714_s1/F
17.572 0.474 tNET FF 1 core/n5714_s0/I0
18.089 0.517 tINS FF 1 core/n5714_s0/F
18.563 0.474 tNET FF 1 core/decoded_rs1_2_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_in
10.000 0.000 tCL RR 1 clk_in_ibuf/I
10.000 0.000 tINS RR 3914 clk_in_ibuf/O
10.360 0.360 tNET RR 1 core/decoded_rs1_2_s0/CLK
10.325 -0.035 tSu 1 core/decoded_rs1_2_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 18
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%
Arrival Data Path Delay: cell: 8.491, 46.646%; route: 9.480, 52.079%; tC2Q: 0.232, 1.275%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%