Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\picorv32.v
D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\picosoc.v
D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\advspi.v
D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\ahb_bus.v
D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\picosoc_dtcm.v
D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\picosoc_itcm.v
D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wb_bus.v
D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wb_brancher.v
D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wbgpio.v
D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wbi2c.v
D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wbspi.v
D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wbuart.v
D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\simpleuart.v
D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\dm.v
GowinSynthesis Constraints File ---
Tool Version V1.9.9.03 (64-bit)
Part Number GW5A-LV25UG324ES
Device GW5A-25
Device Version A
Created Time Thu May 23 09:06:15 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module Gowin_PicoRV32_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 169.578MB
Running netlist conversion:
    CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.102s, Peak memory usage = 169.578MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.687s, Elapsed time = 0h 0m 0.699s, Peak memory usage = 169.578MB
    Optimizing Phase 1: CPU time = 0h 0m 0.312s, Elapsed time = 0h 0m 0.299s, Peak memory usage = 169.578MB
    Optimizing Phase 2: CPU time = 0h 0m 0.953s, Elapsed time = 0h 0m 0.977s, Peak memory usage = 169.578MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.343s, Elapsed time = 0h 0m 0.335s, Peak memory usage = 169.578MB
    Inferring Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.041s, Peak memory usage = 169.578MB
    Inferring Phase 2: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.059s, Peak memory usage = 169.578MB
    Inferring Phase 3: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.026s, Peak memory usage = 169.578MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 169.578MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.25s, Elapsed time = 0h 0m 0.26s, Peak memory usage = 169.578MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.453s, Elapsed time = 0h 0m 0.454s, Peak memory usage = 169.578MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 26s, Elapsed time = 0h 0m 26s, Peak memory usage = 183.688MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.718s, Elapsed time = 0h 0m 0.773s, Peak memory usage = 183.688MB
Generate output files:
    CPU time = 0h 0m 0.843s, Elapsed time = 0h 0m 2s, Peak memory usage = 224.313MB
Total Time and Memory Usage CPU time = 0h 0m 32s, Elapsed time = 0h 0m 34s, Peak memory usage = 224.313MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 241
I/O Buf 239
    IBUF 84
    OBUF 147
    TBUF 2
    IOBUF 6
Register 4561
    DFFSE 98
    DFFRE 3067
    DFFPE 17
    DFFCE 1379
LUT 6843
    LUT2 438
    LUT3 2248
    LUT4 4157
ALU 629
    ALU 629
INV 26
    INV 26
DSP
    MULT27X36 2
BSRAM 32
    SDPB 32

Resource Utilization Summary

Resource Usage Utilization
Logic 7498(6869 LUT, 629 ALU) / 23040 33%
Register 4561 / 23685 20%
  --Register as Latch 0 / 23685 0%
  --Register as FF 4561 / 23685 20%
BSRAM 32 / 56 58%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
clk_in Base 10.000 100.0 0.000 5.000 clk_in_ibuf/I
jtag_TCK Base 10.000 100.0 0.000 5.000 jtag_TCK_ibuf/I
u_dualportspi/u_atcspi/u_spi_spiif/n316_3 Base 10.000 100.0 0.000 5.000 u_dualportspi/u_atcspi/u_spi_spiif/n316_s0/F

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk_in 100.000(MHz) 56.125(MHz) 11 TOP
2 jtag_TCK 100.000(MHz) 110.988(MHz) 5 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack -6.287
Data Arrival Time 16.599
Data Required Time 10.311
From core/mem_addr_26_s0
To core/decoded_rs1_0_s0
Launch Clk clk_in[R]
Latch Clk clk_in[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_in
0.000 0.000 tCL RR 1 clk_in_ibuf/I
0.000 0.000 tINS RR 4441 clk_in_ibuf/O
0.375 0.375 tNET RR 1 core/mem_addr_26_s0/CLK
0.757 0.382 tC2Q RR 3 core/mem_addr_26_s0/Q
1.132 0.375 tNET RR 1 itcm_valid_s3/I0
1.659 0.526 tINS RR 9 itcm_valid_s3/F
2.034 0.375 tNET RR 1 itcm_valid_s4/I3
2.296 0.262 tINS RR 7 itcm_valid_s4/F
2.671 0.375 tNET RR 1 u_dm/u_dm2dtm_cdc_tx/vld_set_s4/I0
3.198 0.526 tINS RR 4 u_dm/u_dm2dtm_cdc_tx/vld_set_s4/F
3.573 0.375 tNET RR 1 u_dm/u_dm2dtm_cdc_tx/vld_set_s0/I0
4.099 0.526 tINS RR 40 u_dm/u_dm2dtm_cdc_tx/vld_set_s0/F
4.474 0.375 tNET RR 1 u_dm/ram_addr_2_s2/I3
4.736 0.262 tINS RR 70 u_dm/ram_addr_2_s2/F
5.111 0.375 tNET RR 1 u_dm/ram_addr_0_s0/I2
5.572 0.461 tINS RR 103 u_dm/ram_addr_0_s0/F
5.947 0.375 tNET RR 1 u_dm/u_s_debug_ram/ram_dout_Z_20_s2/I2
6.409 0.461 tINS RR 1 u_dm/u_s_debug_ram/ram_dout_Z_20_s2/F
6.784 0.375 tNET RR 1 u_dm/u_s_debug_ram/ram_dout_Z_20_s0/I0
6.920 0.136 tINS RR 1 u_dm/u_s_debug_ram/ram_dout_Z_20_s0/O
7.295 0.375 tNET RR 1 u_dm/u_s_debug_ram/ram_dout_Z_20_s/I0
7.381 0.086 tINS RR 2 u_dm/u_s_debug_ram/ram_dout_Z_20_s/O
7.756 0.375 tNET RR 1 mem_rdata_20_s6/I2
8.217 0.461 tINS RR 1 mem_rdata_20_s6/F
8.592 0.375 tNET RR 1 mem_rdata_20_s1/I1
9.109 0.516 tINS RR 1 mem_rdata_20_s1/F
9.484 0.375 tNET RR 1 mem_rdata_20_s0/I0
10.010 0.526 tINS RR 4 mem_rdata_20_s0/F
10.385 0.375 tNET RR 1 core/mem_rdata_latched_20_s0/I1
10.901 0.516 tINS RR 7 core/mem_rdata_latched_20_s0/F
11.276 0.375 tNET RR 1 core/mem_rdata_latched_4_s3/I2
11.737 0.461 tINS RR 8 core/mem_rdata_latched_4_s3/F
12.112 0.375 tNET RR 1 core/mem_rdata_latched_4_s1/I1
12.629 0.516 tINS RR 7 core/mem_rdata_latched_4_s1/F
13.004 0.375 tNET RR 1 core/n5706_s4/I0
13.530 0.526 tINS RR 2 core/n5706_s4/F
13.905 0.375 tNET RR 1 core/n5712_s3/I0
14.431 0.526 tINS RR 3 core/n5712_s3/F
14.806 0.375 tNET RR 1 core/n5713_s1/I1
15.322 0.516 tINS RR 3 core/n5713_s1/F
15.697 0.375 tNET RR 1 core/n5716_s0/I0
16.224 0.526 tINS RR 1 core/n5716_s0/F
16.599 0.375 tNET RR 1 core/decoded_rs1_0_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_in
10.000 0.000 tCL RR 1 clk_in_ibuf/I
10.000 0.000 tINS RR 4441 clk_in_ibuf/O
10.375 0.375 tNET RR 1 core/decoded_rs1_0_s0/CLK
10.311 -0.064 tSu 1 core/decoded_rs1_0_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 18
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 8.341, 51.413%; route: 7.500, 46.229%; tC2Q: 0.382, 2.358%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 2

Path Summary:
Slack -6.287
Data Arrival Time 16.599
Data Required Time 10.311
From core/mem_addr_26_s0
To core/decoded_rs1_3_s0
Launch Clk clk_in[R]
Latch Clk clk_in[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_in
0.000 0.000 tCL RR 1 clk_in_ibuf/I
0.000 0.000 tINS RR 4441 clk_in_ibuf/O
0.375 0.375 tNET RR 1 core/mem_addr_26_s0/CLK
0.757 0.382 tC2Q RR 3 core/mem_addr_26_s0/Q
1.132 0.375 tNET RR 1 itcm_valid_s3/I0
1.659 0.526 tINS RR 9 itcm_valid_s3/F
2.034 0.375 tNET RR 1 itcm_valid_s4/I3
2.296 0.262 tINS RR 7 itcm_valid_s4/F
2.671 0.375 tNET RR 1 u_dm/u_dm2dtm_cdc_tx/vld_set_s4/I0
3.198 0.526 tINS RR 4 u_dm/u_dm2dtm_cdc_tx/vld_set_s4/F
3.573 0.375 tNET RR 1 u_dm/u_dm2dtm_cdc_tx/vld_set_s0/I0
4.099 0.526 tINS RR 40 u_dm/u_dm2dtm_cdc_tx/vld_set_s0/F
4.474 0.375 tNET RR 1 u_dm/ram_addr_2_s2/I3
4.736 0.262 tINS RR 70 u_dm/ram_addr_2_s2/F
5.111 0.375 tNET RR 1 u_dm/ram_addr_0_s0/I2
5.572 0.461 tINS RR 103 u_dm/ram_addr_0_s0/F
5.947 0.375 tNET RR 1 u_dm/u_s_debug_ram/ram_dout_Z_20_s2/I2
6.409 0.461 tINS RR 1 u_dm/u_s_debug_ram/ram_dout_Z_20_s2/F
6.784 0.375 tNET RR 1 u_dm/u_s_debug_ram/ram_dout_Z_20_s0/I0
6.920 0.136 tINS RR 1 u_dm/u_s_debug_ram/ram_dout_Z_20_s0/O
7.295 0.375 tNET RR 1 u_dm/u_s_debug_ram/ram_dout_Z_20_s/I0
7.381 0.086 tINS RR 2 u_dm/u_s_debug_ram/ram_dout_Z_20_s/O
7.756 0.375 tNET RR 1 mem_rdata_20_s6/I2
8.217 0.461 tINS RR 1 mem_rdata_20_s6/F
8.592 0.375 tNET RR 1 mem_rdata_20_s1/I1
9.109 0.516 tINS RR 1 mem_rdata_20_s1/F
9.484 0.375 tNET RR 1 mem_rdata_20_s0/I0
10.010 0.526 tINS RR 4 mem_rdata_20_s0/F
10.385 0.375 tNET RR 1 core/mem_rdata_latched_20_s0/I1
10.901 0.516 tINS RR 7 core/mem_rdata_latched_20_s0/F
11.276 0.375 tNET RR 1 core/mem_rdata_latched_4_s3/I2
11.737 0.461 tINS RR 8 core/mem_rdata_latched_4_s3/F
12.112 0.375 tNET RR 1 core/mem_rdata_latched_4_s1/I1
12.629 0.516 tINS RR 7 core/mem_rdata_latched_4_s1/F
13.004 0.375 tNET RR 1 core/n5706_s4/I0
13.530 0.526 tINS RR 2 core/n5706_s4/F
13.905 0.375 tNET RR 1 core/n5712_s3/I0
14.431 0.526 tINS RR 3 core/n5712_s3/F
14.806 0.375 tNET RR 1 core/n5713_s1/I1
15.322 0.516 tINS RR 3 core/n5713_s1/F
15.697 0.375 tNET RR 1 core/n5713_s0/I0
16.224 0.526 tINS RR 1 core/n5713_s0/F
16.599 0.375 tNET RR 1 core/decoded_rs1_3_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_in
10.000 0.000 tCL RR 1 clk_in_ibuf/I
10.000 0.000 tINS RR 4441 clk_in_ibuf/O
10.375 0.375 tNET RR 1 core/decoded_rs1_3_s0/CLK
10.311 -0.064 tSu 1 core/decoded_rs1_3_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 18
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 8.341, 51.413%; route: 7.500, 46.229%; tC2Q: 0.382, 2.358%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 3

Path Summary:
Slack -6.287
Data Arrival Time 16.599
Data Required Time 10.311
From core/mem_addr_26_s0
To core/decoded_rs1_4_s0
Launch Clk clk_in[R]
Latch Clk clk_in[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_in
0.000 0.000 tCL RR 1 clk_in_ibuf/I
0.000 0.000 tINS RR 4441 clk_in_ibuf/O
0.375 0.375 tNET RR 1 core/mem_addr_26_s0/CLK
0.757 0.382 tC2Q RR 3 core/mem_addr_26_s0/Q
1.132 0.375 tNET RR 1 itcm_valid_s3/I0
1.659 0.526 tINS RR 9 itcm_valid_s3/F
2.034 0.375 tNET RR 1 itcm_valid_s4/I3
2.296 0.262 tINS RR 7 itcm_valid_s4/F
2.671 0.375 tNET RR 1 u_dm/u_dm2dtm_cdc_tx/vld_set_s4/I0
3.198 0.526 tINS RR 4 u_dm/u_dm2dtm_cdc_tx/vld_set_s4/F
3.573 0.375 tNET RR 1 u_dm/u_dm2dtm_cdc_tx/vld_set_s0/I0
4.099 0.526 tINS RR 40 u_dm/u_dm2dtm_cdc_tx/vld_set_s0/F
4.474 0.375 tNET RR 1 u_dm/ram_addr_2_s2/I3
4.736 0.262 tINS RR 70 u_dm/ram_addr_2_s2/F
5.111 0.375 tNET RR 1 u_dm/ram_addr_0_s0/I2
5.572 0.461 tINS RR 103 u_dm/ram_addr_0_s0/F
5.947 0.375 tNET RR 1 u_dm/u_s_debug_ram/ram_dout_Z_20_s2/I2
6.409 0.461 tINS RR 1 u_dm/u_s_debug_ram/ram_dout_Z_20_s2/F
6.784 0.375 tNET RR 1 u_dm/u_s_debug_ram/ram_dout_Z_20_s0/I0
6.920 0.136 tINS RR 1 u_dm/u_s_debug_ram/ram_dout_Z_20_s0/O
7.295 0.375 tNET RR 1 u_dm/u_s_debug_ram/ram_dout_Z_20_s/I0
7.381 0.086 tINS RR 2 u_dm/u_s_debug_ram/ram_dout_Z_20_s/O
7.756 0.375 tNET RR 1 mem_rdata_20_s6/I2
8.217 0.461 tINS RR 1 mem_rdata_20_s6/F
8.592 0.375 tNET RR 1 mem_rdata_20_s1/I1
9.109 0.516 tINS RR 1 mem_rdata_20_s1/F
9.484 0.375 tNET RR 1 mem_rdata_20_s0/I0
10.010 0.526 tINS RR 4 mem_rdata_20_s0/F
10.385 0.375 tNET RR 1 core/mem_rdata_latched_20_s0/I1
10.901 0.516 tINS RR 7 core/mem_rdata_latched_20_s0/F
11.276 0.375 tNET RR 1 core/mem_rdata_latched_4_s3/I2
11.737 0.461 tINS RR 8 core/mem_rdata_latched_4_s3/F
12.112 0.375 tNET RR 1 core/mem_rdata_latched_4_s1/I1
12.629 0.516 tINS RR 7 core/mem_rdata_latched_4_s1/F
13.004 0.375 tNET RR 1 core/n5706_s4/I0
13.530 0.526 tINS RR 2 core/n5706_s4/F
13.905 0.375 tNET RR 1 core/n5712_s3/I0
14.431 0.526 tINS RR 3 core/n5712_s3/F
14.806 0.375 tNET RR 1 core/n5712_s1/I1
15.322 0.516 tINS RR 1 core/n5712_s1/F
15.697 0.375 tNET RR 1 core/n5712_s0/I0
16.224 0.526 tINS RR 1 core/n5712_s0/F
16.599 0.375 tNET RR 1 core/decoded_rs1_4_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_in
10.000 0.000 tCL RR 1 clk_in_ibuf/I
10.000 0.000 tINS RR 4441 clk_in_ibuf/O
10.375 0.375 tNET RR 1 core/decoded_rs1_4_s0/CLK
10.311 -0.064 tSu 1 core/decoded_rs1_4_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 18
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 8.341, 51.413%; route: 7.500, 46.229%; tC2Q: 0.382, 2.358%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 4

Path Summary:
Slack -6.277
Data Arrival Time 16.589
Data Required Time 10.311
From core/mem_addr_26_s0
To core/decoded_rs1_2_s0
Launch Clk clk_in[R]
Latch Clk clk_in[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_in
0.000 0.000 tCL RR 1 clk_in_ibuf/I
0.000 0.000 tINS RR 4441 clk_in_ibuf/O
0.375 0.375 tNET RR 1 core/mem_addr_26_s0/CLK
0.757 0.382 tC2Q RR 3 core/mem_addr_26_s0/Q
1.132 0.375 tNET RR 1 itcm_valid_s3/I0
1.659 0.526 tINS RR 9 itcm_valid_s3/F
2.034 0.375 tNET RR 1 itcm_valid_s4/I3
2.296 0.262 tINS RR 7 itcm_valid_s4/F
2.671 0.375 tNET RR 1 u_dm/u_dm2dtm_cdc_tx/vld_set_s4/I0
3.198 0.526 tINS RR 4 u_dm/u_dm2dtm_cdc_tx/vld_set_s4/F
3.573 0.375 tNET RR 1 u_dm/u_dm2dtm_cdc_tx/vld_set_s0/I0
4.099 0.526 tINS RR 40 u_dm/u_dm2dtm_cdc_tx/vld_set_s0/F
4.474 0.375 tNET RR 1 u_dm/ram_addr_2_s2/I3
4.736 0.262 tINS RR 70 u_dm/ram_addr_2_s2/F
5.111 0.375 tNET RR 1 u_dm/ram_addr_0_s0/I2
5.572 0.461 tINS RR 103 u_dm/ram_addr_0_s0/F
5.947 0.375 tNET RR 1 u_dm/u_s_debug_ram/ram_dout_Z_20_s2/I2
6.409 0.461 tINS RR 1 u_dm/u_s_debug_ram/ram_dout_Z_20_s2/F
6.784 0.375 tNET RR 1 u_dm/u_s_debug_ram/ram_dout_Z_20_s0/I0
6.920 0.136 tINS RR 1 u_dm/u_s_debug_ram/ram_dout_Z_20_s0/O
7.295 0.375 tNET RR 1 u_dm/u_s_debug_ram/ram_dout_Z_20_s/I0
7.381 0.086 tINS RR 2 u_dm/u_s_debug_ram/ram_dout_Z_20_s/O
7.756 0.375 tNET RR 1 mem_rdata_20_s6/I2
8.217 0.461 tINS RR 1 mem_rdata_20_s6/F
8.592 0.375 tNET RR 1 mem_rdata_20_s1/I1
9.109 0.516 tINS RR 1 mem_rdata_20_s1/F
9.484 0.375 tNET RR 1 mem_rdata_20_s0/I0
10.010 0.526 tINS RR 4 mem_rdata_20_s0/F
10.385 0.375 tNET RR 1 core/mem_rdata_latched_20_s0/I1
10.901 0.516 tINS RR 7 core/mem_rdata_latched_20_s0/F
11.276 0.375 tNET RR 1 core/mem_rdata_latched_4_s3/I2
11.737 0.461 tINS RR 8 core/mem_rdata_latched_4_s3/F
12.112 0.375 tNET RR 1 core/mem_rdata_latched_4_s1/I1
12.629 0.516 tINS RR 7 core/mem_rdata_latched_4_s1/F
13.004 0.375 tNET RR 1 core/n5706_s4/I0
13.530 0.526 tINS RR 2 core/n5706_s4/F
13.905 0.375 tNET RR 1 core/n5712_s3/I0
14.431 0.526 tINS RR 3 core/n5712_s3/F
14.806 0.375 tNET RR 1 core/n5713_s1/I1
15.322 0.516 tINS RR 3 core/n5713_s1/F
15.697 0.375 tNET RR 1 core/n5714_s0/I1
16.214 0.516 tINS RR 1 core/n5714_s0/F
16.589 0.375 tNET RR 1 core/decoded_rs1_2_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_in
10.000 0.000 tCL RR 1 clk_in_ibuf/I
10.000 0.000 tINS RR 4441 clk_in_ibuf/O
10.375 0.375 tNET RR 1 core/decoded_rs1_2_s0/CLK
10.311 -0.064 tSu 1 core/decoded_rs1_2_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 18
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 8.331, 51.384%; route: 7.500, 46.257%; tC2Q: 0.382, 2.359%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 5

Path Summary:
Slack -6.232
Data Arrival Time 16.544
Data Required Time 10.311
From core/mem_addr_26_s0
To core/decoded_rd_1_s0
Launch Clk clk_in[R]
Latch Clk clk_in[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_in
0.000 0.000 tCL RR 1 clk_in_ibuf/I
0.000 0.000 tINS RR 4441 clk_in_ibuf/O
0.375 0.375 tNET RR 1 core/mem_addr_26_s0/CLK
0.757 0.382 tC2Q RR 3 core/mem_addr_26_s0/Q
1.132 0.375 tNET RR 1 itcm_valid_s3/I0
1.659 0.526 tINS RR 9 itcm_valid_s3/F
2.034 0.375 tNET RR 1 itcm_valid_s4/I3
2.296 0.262 tINS RR 7 itcm_valid_s4/F
2.671 0.375 tNET RR 1 u_dm/u_dm2dtm_cdc_tx/vld_set_s4/I0
3.198 0.526 tINS RR 4 u_dm/u_dm2dtm_cdc_tx/vld_set_s4/F
3.573 0.375 tNET RR 1 u_dm/u_dm2dtm_cdc_tx/vld_set_s0/I0
4.099 0.526 tINS RR 40 u_dm/u_dm2dtm_cdc_tx/vld_set_s0/F
4.474 0.375 tNET RR 1 u_dm/ram_addr_2_s2/I3
4.736 0.262 tINS RR 70 u_dm/ram_addr_2_s2/F
5.111 0.375 tNET RR 1 u_dm/ram_addr_0_s0/I2
5.572 0.461 tINS RR 103 u_dm/ram_addr_0_s0/F
5.947 0.375 tNET RR 1 u_dm/u_s_debug_ram/ram_dout_Z_20_s2/I2
6.409 0.461 tINS RR 1 u_dm/u_s_debug_ram/ram_dout_Z_20_s2/F
6.784 0.375 tNET RR 1 u_dm/u_s_debug_ram/ram_dout_Z_20_s0/I0
6.920 0.136 tINS RR 1 u_dm/u_s_debug_ram/ram_dout_Z_20_s0/O
7.295 0.375 tNET RR 1 u_dm/u_s_debug_ram/ram_dout_Z_20_s/I0
7.381 0.086 tINS RR 2 u_dm/u_s_debug_ram/ram_dout_Z_20_s/O
7.756 0.375 tNET RR 1 mem_rdata_20_s6/I2
8.217 0.461 tINS RR 1 mem_rdata_20_s6/F
8.592 0.375 tNET RR 1 mem_rdata_20_s1/I1
9.109 0.516 tINS RR 1 mem_rdata_20_s1/F
9.484 0.375 tNET RR 1 mem_rdata_20_s0/I0
10.010 0.526 tINS RR 4 mem_rdata_20_s0/F
10.385 0.375 tNET RR 1 core/mem_rdata_latched_20_s0/I1
10.901 0.516 tINS RR 7 core/mem_rdata_latched_20_s0/F
11.276 0.375 tNET RR 1 core/mem_rdata_latched_4_s3/I2
11.737 0.461 tINS RR 8 core/mem_rdata_latched_4_s3/F
12.112 0.375 tNET RR 1 core/n5376_s5/I1
12.629 0.516 tINS RR 6 core/n5376_s5/F
13.004 0.375 tNET RR 1 core/n5772_s3/I2
13.465 0.461 tINS RR 4 core/n5772_s3/F
13.840 0.375 tNET RR 1 core/n5708_s3/I0
14.366 0.526 tINS RR 1 core/n5708_s3/F
14.741 0.375 tNET RR 1 core/n5708_s5/I0
15.267 0.526 tINS RR 2 core/n5708_s5/F
15.642 0.375 tNET RR 1 core/n5709_s0/I0
16.169 0.526 tINS RR 1 core/n5709_s0/F
16.544 0.375 tNET RR 1 core/decoded_rd_1_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_in
10.000 0.000 tCL RR 1 clk_in_ibuf/I
10.000 0.000 tINS RR 4441 clk_in_ibuf/O
10.375 0.375 tNET RR 1 core/decoded_rd_1_s0/CLK
10.311 -0.064 tSu 1 core/decoded_rd_1_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 18
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 8.286, 51.248%; route: 7.500, 46.386%; tC2Q: 0.382, 2.366%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%