Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\picorv32.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\picosoc.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\advspi.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\ahb_bus.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\picosoc_dtcm.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\picosoc_itcm.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wb_bus.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wb_brancher.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wbgpio.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wbi2c.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wbspi.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wbuart.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\simpleuart.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\dm.v |
GowinSynthesis Constraints File | --- |
Tool Version | V1.9.9.03 (64-bit) |
Part Number | GW5AST-LV138FPG676AES |
Device | GW5AST-138 |
Device Version | B |
Created Time | Thu May 23 09:50:44 2024 |
Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | Gowin_PicoRV32_Top |
Synthesis Process | Running parser: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 168.781MB Running netlist conversion: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.102s, Peak memory usage = 168.781MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.718s, Elapsed time = 0h 0m 0.719s, Peak memory usage = 168.781MB Optimizing Phase 1: CPU time = 0h 0m 0.312s, Elapsed time = 0h 0m 0.304s, Peak memory usage = 168.781MB Optimizing Phase 2: CPU time = 0h 0m 0.953s, Elapsed time = 0h 0m 0.965s, Peak memory usage = 168.781MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.343s, Elapsed time = 0h 0m 0.333s, Peak memory usage = 168.781MB Inferring Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.042s, Peak memory usage = 168.781MB Inferring Phase 2: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.057s, Peak memory usage = 168.781MB Inferring Phase 3: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.026s, Peak memory usage = 168.781MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 168.781MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.25s, Elapsed time = 0h 0m 0.26s, Peak memory usage = 168.781MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.453s, Elapsed time = 0h 0m 0.447s, Peak memory usage = 168.781MB Tech-Mapping Phase 3: CPU time = 0h 0m 26s, Elapsed time = 0h 0m 26s, Peak memory usage = 185.113MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.671s, Elapsed time = 0h 0m 0.698s, Peak memory usage = 185.113MB Generate output files: CPU time = 0h 0m 0.796s, Elapsed time = 0h 0m 0.879s, Peak memory usage = 224.051MB |
Total Time and Memory Usage | CPU time = 0h 0m 32s, Elapsed time = 0h 0m 32s, Peak memory usage = 224.051MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 241 |
I/O Buf | 239 |
    IBUF | 84 |
    OBUF | 147 |
    TBUF | 2 |
    IOBUF | 6 |
Register | 4561 |
    DFFSE | 98 |
    DFFRE | 3067 |
    DFFPE | 17 |
    DFFCE | 1379 |
LUT | 6830 |
    LUT2 | 540 |
    LUT3 | 2320 |
    LUT4 | 3970 |
ALU | 630 |
    ALU | 630 |
INV | 26 |
    INV | 26 |
DSP | |
    MULT27X36 | 2 |
BSRAM | 32 |
    SDPB | 32 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 7486(6856 LUT, 630 ALU) / 138240 | 6% |
Register | 4561 / 139140 | 4% |
  --Register as Latch | 0 / 139140 | 0% |
  --Register as FF | 4561 / 139140 | 4% |
BSRAM | 32 / 340 | 10% |
Timing
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|
clk_in | Base | 10.000 | 100.0 | 0.000 | 5.000 | clk_in_ibuf/I | ||
jtag_TCK | Base | 10.000 | 100.0 | 0.000 | 5.000 | jtag_TCK_ibuf/I | ||
u_dualportspi/u_atcspi/u_spi_spiif/n316_3 | Base | 10.000 | 100.0 | 0.000 | 5.000 | u_dualportspi/u_atcspi/u_spi_spiif/n316_s0/F |
Max Frequency Summary:
No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | clk_in | 100.000(MHz) | 51.229(MHz) | 11 | TOP |
2 | jtag_TCK | 100.000(MHz) | 102.433(MHz) | 5 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | -7.129 |
Data Arrival Time | 17.230 |
Data Required Time | 10.101 |
From | core/mem_addr_26_s0 |
To | core/prefetched_high_word_s0 |
Launch Clk | clk_in[R] |
Latch Clk | clk_in[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk_in | |||
0.000 | 0.000 | tCL | RR | 1 | clk_in_ibuf/I |
0.000 | 0.000 | tINS | RR | 4441 | clk_in_ibuf/O |
0.413 | 0.413 | tNET | RR | 1 | core/mem_addr_26_s0/CLK |
0.795 | 0.382 | tC2Q | RR | 3 | core/mem_addr_26_s0/Q |
1.207 | 0.413 | tNET | RR | 1 | itcm_valid_s3/I0 |
1.786 | 0.579 | tINS | RR | 5 | itcm_valid_s3/F |
2.199 | 0.413 | tNET | RR | 1 | itcm_valid_s4/I3 |
2.487 | 0.289 | tINS | RR | 6 | itcm_valid_s4/F |
2.900 | 0.413 | tNET | RR | 1 | u_dm/u_dm2dtm_cdc_tx/vld_set_s2/I0 |
3.479 | 0.579 | tINS | RR | 2 | u_dm/u_dm2dtm_cdc_tx/vld_set_s2/F |
3.891 | 0.413 | tNET | RR | 1 | u_dm/u_dm2dtm_cdc_tx/vld_set_s0/I2 |
4.399 | 0.507 | tINS | RR | 41 | u_dm/u_dm2dtm_cdc_tx/vld_set_s0/F |
4.811 | 0.413 | tNET | RR | 1 | u_dm/ram_addr_2_s2/I3 |
5.100 | 0.289 | tINS | RR | 70 | u_dm/ram_addr_2_s2/F |
5.513 | 0.413 | tNET | RR | 1 | u_dm/ram_addr_0_s0/I2 |
6.020 | 0.507 | tINS | RR | 103 | u_dm/ram_addr_0_s0/F |
6.433 | 0.413 | tNET | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_1_s2/I2 |
6.940 | 0.507 | tINS | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_1_s2/F |
7.353 | 0.413 | tNET | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_1_s0/I0 |
7.503 | 0.150 | tINS | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_1_s0/O |
7.915 | 0.413 | tNET | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_1_s/I0 |
8.001 | 0.086 | tINS | RR | 2 | u_dm/u_s_debug_ram/ram_dout_Z_1_s/O |
8.414 | 0.413 | tNET | RR | 1 | core/n2421_s6/I0 |
8.993 | 0.579 | tINS | RR | 1 | core/n2421_s6/F |
9.405 | 0.413 | tNET | RR | 1 | core/n2421_s5/I1 |
9.973 | 0.567 | tINS | RR | 1 | core/n2421_s5/F |
10.385 | 0.413 | tNET | RR | 1 | core/n2421_s3/I0 |
10.964 | 0.579 | tINS | RR | 3 | core/n2421_s3/F |
11.376 | 0.413 | tNET | RR | 1 | core/mem_rdata_latched_1_s4/I0 |
11.955 | 0.579 | tINS | RR | 1 | core/mem_rdata_latched_1_s4/F |
12.368 | 0.413 | tNET | RR | 1 | core/mem_rdata_latched_1_s3/I0 |
12.946 | 0.579 | tINS | RR | 19 | core/mem_rdata_latched_1_s3/F |
13.359 | 0.413 | tNET | RR | 1 | core/n5416_s3/I1 |
13.926 | 0.567 | tINS | RR | 32 | core/n5416_s3/F |
14.339 | 0.413 | tNET | RR | 1 | core/mem_la_read_s1/I0 |
14.918 | 0.579 | tINS | RR | 4 | core/mem_la_read_s1/F |
15.330 | 0.413 | tNET | RR | 1 | core/mem_la_read_s3/I2 |
15.838 | 0.507 | tINS | RR | 3 | core/mem_la_read_s3/F |
16.250 | 0.413 | tNET | RR | 1 | core/prefetched_high_word_s2/I1 |
16.818 | 0.567 | tINS | RR | 1 | core/prefetched_high_word_s2/F |
17.230 | 0.413 | tNET | RR | 1 | core/prefetched_high_word_s0/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk_in | |||
10.000 | 0.000 | tCL | RR | 1 | clk_in_ibuf/I |
10.000 | 0.000 | tINS | RR | 4441 | clk_in_ibuf/O |
10.413 | 0.413 | tNET | RR | 1 | core/prefetched_high_word_s0/CLK |
10.101 | -0.311 | tSu | 1 | core/prefetched_high_word_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 17 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Arrival Data Path Delay: | cell: 8.598, 51.123%; route: 7.837, 46.603%; tC2Q: 0.382, 2.274% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 2
Path Summary:Slack | -7.069 |
Data Arrival Time | 17.170 |
Data Required Time | 10.101 |
From | core/mem_addr_26_s0 |
To | core/mem_16bit_buffer_0_s0 |
Launch Clk | clk_in[R] |
Latch Clk | clk_in[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk_in | |||
0.000 | 0.000 | tCL | RR | 1 | clk_in_ibuf/I |
0.000 | 0.000 | tINS | RR | 4441 | clk_in_ibuf/O |
0.413 | 0.413 | tNET | RR | 1 | core/mem_addr_26_s0/CLK |
0.795 | 0.382 | tC2Q | RR | 3 | core/mem_addr_26_s0/Q |
1.207 | 0.413 | tNET | RR | 1 | itcm_valid_s3/I0 |
1.786 | 0.579 | tINS | RR | 5 | itcm_valid_s3/F |
2.199 | 0.413 | tNET | RR | 1 | itcm_valid_s4/I3 |
2.487 | 0.289 | tINS | RR | 6 | itcm_valid_s4/F |
2.900 | 0.413 | tNET | RR | 1 | u_dm/u_dm2dtm_cdc_tx/vld_set_s2/I0 |
3.479 | 0.579 | tINS | RR | 2 | u_dm/u_dm2dtm_cdc_tx/vld_set_s2/F |
3.891 | 0.413 | tNET | RR | 1 | u_dm/u_dm2dtm_cdc_tx/vld_set_s0/I2 |
4.399 | 0.507 | tINS | RR | 41 | u_dm/u_dm2dtm_cdc_tx/vld_set_s0/F |
4.811 | 0.413 | tNET | RR | 1 | u_dm/ram_addr_2_s2/I3 |
5.100 | 0.289 | tINS | RR | 70 | u_dm/ram_addr_2_s2/F |
5.513 | 0.413 | tNET | RR | 1 | u_dm/ram_addr_0_s0/I2 |
6.020 | 0.507 | tINS | RR | 103 | u_dm/ram_addr_0_s0/F |
6.433 | 0.413 | tNET | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_1_s2/I2 |
6.940 | 0.507 | tINS | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_1_s2/F |
7.353 | 0.413 | tNET | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_1_s0/I0 |
7.503 | 0.150 | tINS | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_1_s0/O |
7.915 | 0.413 | tNET | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_1_s/I0 |
8.001 | 0.086 | tINS | RR | 2 | u_dm/u_s_debug_ram/ram_dout_Z_1_s/O |
8.414 | 0.413 | tNET | RR | 1 | core/n2421_s6/I0 |
8.993 | 0.579 | tINS | RR | 1 | core/n2421_s6/F |
9.405 | 0.413 | tNET | RR | 1 | core/n2421_s5/I1 |
9.973 | 0.567 | tINS | RR | 1 | core/n2421_s5/F |
10.385 | 0.413 | tNET | RR | 1 | core/n2421_s3/I0 |
10.964 | 0.579 | tINS | RR | 3 | core/n2421_s3/F |
11.376 | 0.413 | tNET | RR | 1 | core/mem_rdata_latched_1_s4/I0 |
11.955 | 0.579 | tINS | RR | 1 | core/mem_rdata_latched_1_s4/F |
12.368 | 0.413 | tNET | RR | 1 | core/mem_rdata_latched_1_s3/I0 |
12.946 | 0.579 | tINS | RR | 19 | core/mem_rdata_latched_1_s3/F |
13.359 | 0.413 | tNET | RR | 1 | core/n5416_s3/I1 |
13.926 | 0.567 | tINS | RR | 32 | core/n5416_s3/F |
14.339 | 0.413 | tNET | RR | 1 | core/mem_la_read_s1/I0 |
14.918 | 0.579 | tINS | RR | 4 | core/mem_la_read_s1/F |
15.330 | 0.413 | tNET | RR | 1 | core/mem_la_read_s3/I2 |
15.838 | 0.507 | tINS | RR | 3 | core/mem_la_read_s3/F |
16.250 | 0.413 | tNET | RR | 1 | core/mem_16bit_buffer_15_s3/I2 |
16.758 | 0.507 | tINS | RR | 16 | core/mem_16bit_buffer_15_s3/F |
17.170 | 0.413 | tNET | RR | 1 | core/mem_16bit_buffer_0_s0/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk_in | |||
10.000 | 0.000 | tCL | RR | 1 | clk_in_ibuf/I |
10.000 | 0.000 | tINS | RR | 4441 | clk_in_ibuf/O |
10.413 | 0.413 | tNET | RR | 1 | core/mem_16bit_buffer_0_s0/CLK |
10.101 | -0.311 | tSu | 1 | core/mem_16bit_buffer_0_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 17 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Arrival Data Path Delay: | cell: 8.538, 50.947%; route: 7.837, 46.770%; tC2Q: 0.382, 2.283% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 3
Path Summary:Slack | -7.069 |
Data Arrival Time | 17.170 |
Data Required Time | 10.101 |
From | core/mem_addr_26_s0 |
To | core/mem_16bit_buffer_1_s0 |
Launch Clk | clk_in[R] |
Latch Clk | clk_in[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk_in | |||
0.000 | 0.000 | tCL | RR | 1 | clk_in_ibuf/I |
0.000 | 0.000 | tINS | RR | 4441 | clk_in_ibuf/O |
0.413 | 0.413 | tNET | RR | 1 | core/mem_addr_26_s0/CLK |
0.795 | 0.382 | tC2Q | RR | 3 | core/mem_addr_26_s0/Q |
1.207 | 0.413 | tNET | RR | 1 | itcm_valid_s3/I0 |
1.786 | 0.579 | tINS | RR | 5 | itcm_valid_s3/F |
2.199 | 0.413 | tNET | RR | 1 | itcm_valid_s4/I3 |
2.487 | 0.289 | tINS | RR | 6 | itcm_valid_s4/F |
2.900 | 0.413 | tNET | RR | 1 | u_dm/u_dm2dtm_cdc_tx/vld_set_s2/I0 |
3.479 | 0.579 | tINS | RR | 2 | u_dm/u_dm2dtm_cdc_tx/vld_set_s2/F |
3.891 | 0.413 | tNET | RR | 1 | u_dm/u_dm2dtm_cdc_tx/vld_set_s0/I2 |
4.399 | 0.507 | tINS | RR | 41 | u_dm/u_dm2dtm_cdc_tx/vld_set_s0/F |
4.811 | 0.413 | tNET | RR | 1 | u_dm/ram_addr_2_s2/I3 |
5.100 | 0.289 | tINS | RR | 70 | u_dm/ram_addr_2_s2/F |
5.513 | 0.413 | tNET | RR | 1 | u_dm/ram_addr_0_s0/I2 |
6.020 | 0.507 | tINS | RR | 103 | u_dm/ram_addr_0_s0/F |
6.433 | 0.413 | tNET | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_1_s2/I2 |
6.940 | 0.507 | tINS | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_1_s2/F |
7.353 | 0.413 | tNET | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_1_s0/I0 |
7.503 | 0.150 | tINS | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_1_s0/O |
7.915 | 0.413 | tNET | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_1_s/I0 |
8.001 | 0.086 | tINS | RR | 2 | u_dm/u_s_debug_ram/ram_dout_Z_1_s/O |
8.414 | 0.413 | tNET | RR | 1 | core/n2421_s6/I0 |
8.993 | 0.579 | tINS | RR | 1 | core/n2421_s6/F |
9.405 | 0.413 | tNET | RR | 1 | core/n2421_s5/I1 |
9.973 | 0.567 | tINS | RR | 1 | core/n2421_s5/F |
10.385 | 0.413 | tNET | RR | 1 | core/n2421_s3/I0 |
10.964 | 0.579 | tINS | RR | 3 | core/n2421_s3/F |
11.376 | 0.413 | tNET | RR | 1 | core/mem_rdata_latched_1_s4/I0 |
11.955 | 0.579 | tINS | RR | 1 | core/mem_rdata_latched_1_s4/F |
12.368 | 0.413 | tNET | RR | 1 | core/mem_rdata_latched_1_s3/I0 |
12.946 | 0.579 | tINS | RR | 19 | core/mem_rdata_latched_1_s3/F |
13.359 | 0.413 | tNET | RR | 1 | core/n5416_s3/I1 |
13.926 | 0.567 | tINS | RR | 32 | core/n5416_s3/F |
14.339 | 0.413 | tNET | RR | 1 | core/mem_la_read_s1/I0 |
14.918 | 0.579 | tINS | RR | 4 | core/mem_la_read_s1/F |
15.330 | 0.413 | tNET | RR | 1 | core/mem_la_read_s3/I2 |
15.838 | 0.507 | tINS | RR | 3 | core/mem_la_read_s3/F |
16.250 | 0.413 | tNET | RR | 1 | core/mem_16bit_buffer_15_s3/I2 |
16.758 | 0.507 | tINS | RR | 16 | core/mem_16bit_buffer_15_s3/F |
17.170 | 0.413 | tNET | RR | 1 | core/mem_16bit_buffer_1_s0/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk_in | |||
10.000 | 0.000 | tCL | RR | 1 | clk_in_ibuf/I |
10.000 | 0.000 | tINS | RR | 4441 | clk_in_ibuf/O |
10.413 | 0.413 | tNET | RR | 1 | core/mem_16bit_buffer_1_s0/CLK |
10.101 | -0.311 | tSu | 1 | core/mem_16bit_buffer_1_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 17 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Arrival Data Path Delay: | cell: 8.538, 50.947%; route: 7.837, 46.770%; tC2Q: 0.382, 2.283% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 4
Path Summary:Slack | -7.069 |
Data Arrival Time | 17.170 |
Data Required Time | 10.101 |
From | core/mem_addr_26_s0 |
To | core/mem_16bit_buffer_2_s0 |
Launch Clk | clk_in[R] |
Latch Clk | clk_in[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk_in | |||
0.000 | 0.000 | tCL | RR | 1 | clk_in_ibuf/I |
0.000 | 0.000 | tINS | RR | 4441 | clk_in_ibuf/O |
0.413 | 0.413 | tNET | RR | 1 | core/mem_addr_26_s0/CLK |
0.795 | 0.382 | tC2Q | RR | 3 | core/mem_addr_26_s0/Q |
1.207 | 0.413 | tNET | RR | 1 | itcm_valid_s3/I0 |
1.786 | 0.579 | tINS | RR | 5 | itcm_valid_s3/F |
2.199 | 0.413 | tNET | RR | 1 | itcm_valid_s4/I3 |
2.487 | 0.289 | tINS | RR | 6 | itcm_valid_s4/F |
2.900 | 0.413 | tNET | RR | 1 | u_dm/u_dm2dtm_cdc_tx/vld_set_s2/I0 |
3.479 | 0.579 | tINS | RR | 2 | u_dm/u_dm2dtm_cdc_tx/vld_set_s2/F |
3.891 | 0.413 | tNET | RR | 1 | u_dm/u_dm2dtm_cdc_tx/vld_set_s0/I2 |
4.399 | 0.507 | tINS | RR | 41 | u_dm/u_dm2dtm_cdc_tx/vld_set_s0/F |
4.811 | 0.413 | tNET | RR | 1 | u_dm/ram_addr_2_s2/I3 |
5.100 | 0.289 | tINS | RR | 70 | u_dm/ram_addr_2_s2/F |
5.513 | 0.413 | tNET | RR | 1 | u_dm/ram_addr_0_s0/I2 |
6.020 | 0.507 | tINS | RR | 103 | u_dm/ram_addr_0_s0/F |
6.433 | 0.413 | tNET | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_1_s2/I2 |
6.940 | 0.507 | tINS | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_1_s2/F |
7.353 | 0.413 | tNET | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_1_s0/I0 |
7.503 | 0.150 | tINS | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_1_s0/O |
7.915 | 0.413 | tNET | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_1_s/I0 |
8.001 | 0.086 | tINS | RR | 2 | u_dm/u_s_debug_ram/ram_dout_Z_1_s/O |
8.414 | 0.413 | tNET | RR | 1 | core/n2421_s6/I0 |
8.993 | 0.579 | tINS | RR | 1 | core/n2421_s6/F |
9.405 | 0.413 | tNET | RR | 1 | core/n2421_s5/I1 |
9.973 | 0.567 | tINS | RR | 1 | core/n2421_s5/F |
10.385 | 0.413 | tNET | RR | 1 | core/n2421_s3/I0 |
10.964 | 0.579 | tINS | RR | 3 | core/n2421_s3/F |
11.376 | 0.413 | tNET | RR | 1 | core/mem_rdata_latched_1_s4/I0 |
11.955 | 0.579 | tINS | RR | 1 | core/mem_rdata_latched_1_s4/F |
12.368 | 0.413 | tNET | RR | 1 | core/mem_rdata_latched_1_s3/I0 |
12.946 | 0.579 | tINS | RR | 19 | core/mem_rdata_latched_1_s3/F |
13.359 | 0.413 | tNET | RR | 1 | core/n5416_s3/I1 |
13.926 | 0.567 | tINS | RR | 32 | core/n5416_s3/F |
14.339 | 0.413 | tNET | RR | 1 | core/mem_la_read_s1/I0 |
14.918 | 0.579 | tINS | RR | 4 | core/mem_la_read_s1/F |
15.330 | 0.413 | tNET | RR | 1 | core/mem_la_read_s3/I2 |
15.838 | 0.507 | tINS | RR | 3 | core/mem_la_read_s3/F |
16.250 | 0.413 | tNET | RR | 1 | core/mem_16bit_buffer_15_s3/I2 |
16.758 | 0.507 | tINS | RR | 16 | core/mem_16bit_buffer_15_s3/F |
17.170 | 0.413 | tNET | RR | 1 | core/mem_16bit_buffer_2_s0/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk_in | |||
10.000 | 0.000 | tCL | RR | 1 | clk_in_ibuf/I |
10.000 | 0.000 | tINS | RR | 4441 | clk_in_ibuf/O |
10.413 | 0.413 | tNET | RR | 1 | core/mem_16bit_buffer_2_s0/CLK |
10.101 | -0.311 | tSu | 1 | core/mem_16bit_buffer_2_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 17 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Arrival Data Path Delay: | cell: 8.538, 50.947%; route: 7.837, 46.770%; tC2Q: 0.382, 2.283% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 5
Path Summary:Slack | -7.069 |
Data Arrival Time | 17.170 |
Data Required Time | 10.101 |
From | core/mem_addr_26_s0 |
To | core/mem_16bit_buffer_3_s0 |
Launch Clk | clk_in[R] |
Latch Clk | clk_in[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk_in | |||
0.000 | 0.000 | tCL | RR | 1 | clk_in_ibuf/I |
0.000 | 0.000 | tINS | RR | 4441 | clk_in_ibuf/O |
0.413 | 0.413 | tNET | RR | 1 | core/mem_addr_26_s0/CLK |
0.795 | 0.382 | tC2Q | RR | 3 | core/mem_addr_26_s0/Q |
1.207 | 0.413 | tNET | RR | 1 | itcm_valid_s3/I0 |
1.786 | 0.579 | tINS | RR | 5 | itcm_valid_s3/F |
2.199 | 0.413 | tNET | RR | 1 | itcm_valid_s4/I3 |
2.487 | 0.289 | tINS | RR | 6 | itcm_valid_s4/F |
2.900 | 0.413 | tNET | RR | 1 | u_dm/u_dm2dtm_cdc_tx/vld_set_s2/I0 |
3.479 | 0.579 | tINS | RR | 2 | u_dm/u_dm2dtm_cdc_tx/vld_set_s2/F |
3.891 | 0.413 | tNET | RR | 1 | u_dm/u_dm2dtm_cdc_tx/vld_set_s0/I2 |
4.399 | 0.507 | tINS | RR | 41 | u_dm/u_dm2dtm_cdc_tx/vld_set_s0/F |
4.811 | 0.413 | tNET | RR | 1 | u_dm/ram_addr_2_s2/I3 |
5.100 | 0.289 | tINS | RR | 70 | u_dm/ram_addr_2_s2/F |
5.513 | 0.413 | tNET | RR | 1 | u_dm/ram_addr_0_s0/I2 |
6.020 | 0.507 | tINS | RR | 103 | u_dm/ram_addr_0_s0/F |
6.433 | 0.413 | tNET | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_1_s2/I2 |
6.940 | 0.507 | tINS | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_1_s2/F |
7.353 | 0.413 | tNET | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_1_s0/I0 |
7.503 | 0.150 | tINS | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_1_s0/O |
7.915 | 0.413 | tNET | RR | 1 | u_dm/u_s_debug_ram/ram_dout_Z_1_s/I0 |
8.001 | 0.086 | tINS | RR | 2 | u_dm/u_s_debug_ram/ram_dout_Z_1_s/O |
8.414 | 0.413 | tNET | RR | 1 | core/n2421_s6/I0 |
8.993 | 0.579 | tINS | RR | 1 | core/n2421_s6/F |
9.405 | 0.413 | tNET | RR | 1 | core/n2421_s5/I1 |
9.973 | 0.567 | tINS | RR | 1 | core/n2421_s5/F |
10.385 | 0.413 | tNET | RR | 1 | core/n2421_s3/I0 |
10.964 | 0.579 | tINS | RR | 3 | core/n2421_s3/F |
11.376 | 0.413 | tNET | RR | 1 | core/mem_rdata_latched_1_s4/I0 |
11.955 | 0.579 | tINS | RR | 1 | core/mem_rdata_latched_1_s4/F |
12.368 | 0.413 | tNET | RR | 1 | core/mem_rdata_latched_1_s3/I0 |
12.946 | 0.579 | tINS | RR | 19 | core/mem_rdata_latched_1_s3/F |
13.359 | 0.413 | tNET | RR | 1 | core/n5416_s3/I1 |
13.926 | 0.567 | tINS | RR | 32 | core/n5416_s3/F |
14.339 | 0.413 | tNET | RR | 1 | core/mem_la_read_s1/I0 |
14.918 | 0.579 | tINS | RR | 4 | core/mem_la_read_s1/F |
15.330 | 0.413 | tNET | RR | 1 | core/mem_la_read_s3/I2 |
15.838 | 0.507 | tINS | RR | 3 | core/mem_la_read_s3/F |
16.250 | 0.413 | tNET | RR | 1 | core/mem_16bit_buffer_15_s3/I2 |
16.758 | 0.507 | tINS | RR | 16 | core/mem_16bit_buffer_15_s3/F |
17.170 | 0.413 | tNET | RR | 1 | core/mem_16bit_buffer_3_s0/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk_in | |||
10.000 | 0.000 | tCL | RR | 1 | clk_in_ibuf/I |
10.000 | 0.000 | tINS | RR | 4441 | clk_in_ibuf/O |
10.413 | 0.413 | tNET | RR | 1 | core/mem_16bit_buffer_3_s0/CLK |
10.101 | -0.311 | tSu | 1 | core/mem_16bit_buffer_3_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 17 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Arrival Data Path Delay: | cell: 8.538, 50.947%; route: 7.837, 46.770%; tC2Q: 0.382, 2.283% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |