Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\picorv32.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\picosoc.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\advspi.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\ahb_bus.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\picosoc_dtcm.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\picosoc_itcm.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wb_bus.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wb_brancher.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wbgpio.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wbi2c.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wbspi.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wbuart.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\simpleuart.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\dm.v
GowinSynthesis Constraints File ---
Tool Version V1.9.11.02 (64-bit)
Part Number GW5AST-LV138FPG676AC1/I0
Device GW5AST-138
Device Version B
Created Time Tue May 20 16:08:46 2025
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module Gowin_PicoRV32_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 132.270MB
Running netlist conversion:
    CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.098s, Peak memory usage = 132.270MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.765s, Elapsed time = 0h 0m 0.755s, Peak memory usage = 132.270MB
    Optimizing Phase 1: CPU time = 0h 0m 0.312s, Elapsed time = 0h 0m 0.312s, Peak memory usage = 132.270MB
    Optimizing Phase 2: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 132.270MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.562s, Elapsed time = 0h 0m 0.617s, Peak memory usage = 132.270MB
    Inferring Phase 1: CPU time = 0h 0m 0.546s, Elapsed time = 0h 0m 0.536s, Peak memory usage = 132.270MB
    Inferring Phase 2: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.063s, Peak memory usage = 132.270MB
    Inferring Phase 3: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.035s, Peak memory usage = 132.270MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 132.270MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.5s, Elapsed time = 0h 0m 0.49s, Peak memory usage = 132.270MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.484s, Elapsed time = 0h 0m 0.493s, Peak memory usage = 132.270MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 28s, Elapsed time = 0h 0m 28s, Peak memory usage = 145.109MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.75s, Elapsed time = 0h 0m 0.835s, Peak memory usage = 145.109MB
Generate output files:
    CPU time = 0h 0m 0.812s, Elapsed time = 0h 0m 1s, Peak memory usage = 192.246MB
Total Time and Memory Usage CPU time = 0h 0m 35s, Elapsed time = 0h 0m 36s, Peak memory usage = 192.246MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 241
I/O Buf 239
    IBUF 84
    OBUF 147
    TBUF 2
    IOBUF 6
Register 4536
    DFFSE 98
    DFFRE 3067
    DFFPE 17
    DFFCE 1354
LUT 6732
    LUT2 531
    LUT3 2235
    LUT4 3966
ALU 629
    ALU 629
INV 24
    INV 24
DSP
    MULT27X36 2
BSRAM 32
    SDPB 32

Resource Utilization Summary

Resource Usage Utilization
Logic 7385(6756 LUT, 629 ALU) / 138240 6%
Register 4536 / 139140 4%
  --Register as Latch 0 / 139140 0%
  --Register as FF 4536 / 139140 4%
BSRAM 32 / 340 10%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 clk_in Base 10.000 100.000 0.000 5.000 clk_in_ibuf/I
2 jtag_TCK Base 10.000 100.000 0.000 5.000 jtag_TCK_ibuf/I
3 u_dualportspi/u_atcspi/u_spi_spiif/n316_3 Base 10.000 100.000 0.000 5.000 u_dualportspi/u_atcspi/u_spi_spiif/n316_s0/F

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk_in 100.000(MHz) 52.466(MHz) 11 TOP
2 jtag_TCK 100.000(MHz) 89.067(MHz) 6 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack -6.941
Data Arrival Time 17.290
Data Required Time 10.349
From core/mem_addr_26_s0
To core/mem_rdata_q_20_s0
Launch Clk clk_in[R]
Latch Clk clk_in[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_in
0.000 0.000 tCL RR 1 clk_in_ibuf/I
0.000 0.000 tINS RR 4416 clk_in_ibuf/O
0.413 0.413 tNET RR 1 core/mem_addr_26_s0/CLK
0.795 0.382 tC2Q RR 3 core/mem_addr_26_s0/Q
1.207 0.413 tNET RR 1 itcm_valid_s2/I0
1.786 0.579 tINS RR 3 itcm_valid_s2/F
2.199 0.413 tNET RR 1 itcm_valid_s3/I3
2.487 0.289 tINS RR 5 itcm_valid_s3/F
2.900 0.413 tNET RR 1 u_dm/u_dm2dtm_cdc_tx/vld_set_s4/I0
3.479 0.579 tINS RR 4 u_dm/u_dm2dtm_cdc_tx/vld_set_s4/F
3.891 0.413 tNET RR 1 u_dm/u_dm2dtm_cdc_tx/vld_set_s0/I2
4.399 0.507 tINS RR 41 u_dm/u_dm2dtm_cdc_tx/vld_set_s0/F
4.811 0.413 tNET RR 1 u_dm/ram_addr_2_s2/I3
5.100 0.289 tINS RR 70 u_dm/ram_addr_2_s2/F
5.513 0.413 tNET RR 1 u_dm/ram_addr_0_s0/I2
6.020 0.507 tINS RR 103 u_dm/ram_addr_0_s0/F
6.433 0.413 tNET RR 1 u_dm/u_s_debug_ram/ram_dout_Z_19_s4/I2
6.940 0.507 tINS RR 1 u_dm/u_s_debug_ram/ram_dout_Z_19_s4/F
7.353 0.413 tNET RR 1 u_dm/u_s_debug_ram/ram_dout_Z_19_s1/I0
7.503 0.150 tINS RR 1 u_dm/u_s_debug_ram/ram_dout_Z_19_s1/O
7.915 0.413 tNET RR 1 u_dm/u_s_debug_ram/ram_dout_Z_19_s/I1
8.001 0.086 tINS RR 2 u_dm/u_s_debug_ram/ram_dout_Z_19_s/O
8.414 0.413 tNET RR 1 mem_rdata_19_s5/I0
8.993 0.579 tINS RR 1 mem_rdata_19_s5/F
9.405 0.413 tNET RR 1 mem_rdata_19_s1/I1
9.973 0.567 tINS RR 2 mem_rdata_19_s1/F
10.385 0.413 tNET RR 1 core/mem_rdata_latched_3_s3/I0
10.964 0.579 tINS RR 1 core/mem_rdata_latched_3_s3/F
11.376 0.413 tNET RR 1 core/mem_rdata_latched_3_s1/I1
11.944 0.567 tINS RR 17 core/mem_rdata_latched_3_s1/F
12.356 0.413 tNET RR 1 core/n5248_s5/I1
12.924 0.567 tINS RR 7 core/n5248_s5/F
13.336 0.413 tNET RR 1 core/n5640_s6/I0
13.915 0.579 tINS RR 3 core/n5640_s6/F
14.328 0.413 tNET RR 1 core/n2082_s8/I1
14.895 0.567 tINS RR 4 core/n2082_s8/F
15.308 0.413 tNET RR 1 core/n2085_s5/I0
15.886 0.579 tINS RR 2 core/n2085_s5/F
16.299 0.413 tNET RR 1 core/n2086_s0/I0
16.878 0.579 tINS RR 1 core/n2086_s0/F
17.290 0.413 tNET RR 1 core/mem_rdata_q_20_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_in
10.000 0.000 tCL RR 1 clk_in_ibuf/I
10.000 0.000 tINS RR 4416 clk_in_ibuf/O
10.413 0.413 tNET RR 1 core/mem_rdata_q_20_s0/CLK
10.349 -0.064 tSu 1 core/mem_rdata_q_20_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 17
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 8.658, 51.296%; route: 7.837, 46.438%; tC2Q: 0.382, 2.266%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 2

Path Summary:
Slack -6.941
Data Arrival Time 17.290
Data Required Time 10.349
From core/mem_addr_26_s0
To core/mem_rdata_q_21_s0
Launch Clk clk_in[R]
Latch Clk clk_in[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_in
0.000 0.000 tCL RR 1 clk_in_ibuf/I
0.000 0.000 tINS RR 4416 clk_in_ibuf/O
0.413 0.413 tNET RR 1 core/mem_addr_26_s0/CLK
0.795 0.382 tC2Q RR 3 core/mem_addr_26_s0/Q
1.207 0.413 tNET RR 1 itcm_valid_s2/I0
1.786 0.579 tINS RR 3 itcm_valid_s2/F
2.199 0.413 tNET RR 1 itcm_valid_s3/I3
2.487 0.289 tINS RR 5 itcm_valid_s3/F
2.900 0.413 tNET RR 1 u_dm/u_dm2dtm_cdc_tx/vld_set_s4/I0
3.479 0.579 tINS RR 4 u_dm/u_dm2dtm_cdc_tx/vld_set_s4/F
3.891 0.413 tNET RR 1 u_dm/u_dm2dtm_cdc_tx/vld_set_s0/I2
4.399 0.507 tINS RR 41 u_dm/u_dm2dtm_cdc_tx/vld_set_s0/F
4.811 0.413 tNET RR 1 u_dm/ram_addr_2_s2/I3
5.100 0.289 tINS RR 70 u_dm/ram_addr_2_s2/F
5.513 0.413 tNET RR 1 u_dm/ram_addr_0_s0/I2
6.020 0.507 tINS RR 103 u_dm/ram_addr_0_s0/F
6.433 0.413 tNET RR 1 u_dm/u_s_debug_ram/ram_dout_Z_19_s4/I2
6.940 0.507 tINS RR 1 u_dm/u_s_debug_ram/ram_dout_Z_19_s4/F
7.353 0.413 tNET RR 1 u_dm/u_s_debug_ram/ram_dout_Z_19_s1/I0
7.503 0.150 tINS RR 1 u_dm/u_s_debug_ram/ram_dout_Z_19_s1/O
7.915 0.413 tNET RR 1 u_dm/u_s_debug_ram/ram_dout_Z_19_s/I1
8.001 0.086 tINS RR 2 u_dm/u_s_debug_ram/ram_dout_Z_19_s/O
8.414 0.413 tNET RR 1 mem_rdata_19_s5/I0
8.993 0.579 tINS RR 1 mem_rdata_19_s5/F
9.405 0.413 tNET RR 1 mem_rdata_19_s1/I1
9.973 0.567 tINS RR 2 mem_rdata_19_s1/F
10.385 0.413 tNET RR 1 core/mem_rdata_latched_3_s3/I0
10.964 0.579 tINS RR 1 core/mem_rdata_latched_3_s3/F
11.376 0.413 tNET RR 1 core/mem_rdata_latched_3_s1/I1
11.944 0.567 tINS RR 17 core/mem_rdata_latched_3_s1/F
12.356 0.413 tNET RR 1 core/n5248_s5/I1
12.924 0.567 tINS RR 7 core/n5248_s5/F
13.336 0.413 tNET RR 1 core/n5640_s6/I0
13.915 0.579 tINS RR 3 core/n5640_s6/F
14.328 0.413 tNET RR 1 core/n2082_s8/I1
14.895 0.567 tINS RR 4 core/n2082_s8/F
15.308 0.413 tNET RR 1 core/n2085_s5/I0
15.886 0.579 tINS RR 2 core/n2085_s5/F
16.299 0.413 tNET RR 1 core/n2085_s0/I0
16.878 0.579 tINS RR 1 core/n2085_s0/F
17.290 0.413 tNET RR 1 core/mem_rdata_q_21_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_in
10.000 0.000 tCL RR 1 clk_in_ibuf/I
10.000 0.000 tINS RR 4416 clk_in_ibuf/O
10.413 0.413 tNET RR 1 core/mem_rdata_q_21_s0/CLK
10.349 -0.064 tSu 1 core/mem_rdata_q_21_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 17
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 8.658, 51.296%; route: 7.837, 46.438%; tC2Q: 0.382, 2.266%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 3

Path Summary:
Slack -6.915
Data Arrival Time 17.264
Data Required Time 10.349
From core/mem_addr_26_s0
To core/mem_rdata_q_24_s0
Launch Clk clk_in[R]
Latch Clk clk_in[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_in
0.000 0.000 tCL RR 1 clk_in_ibuf/I
0.000 0.000 tINS RR 4416 clk_in_ibuf/O
0.413 0.413 tNET RR 1 core/mem_addr_26_s0/CLK
0.795 0.382 tC2Q RR 3 core/mem_addr_26_s0/Q
1.207 0.413 tNET RR 1 itcm_valid_s2/I0
1.786 0.579 tINS RR 3 itcm_valid_s2/F
2.199 0.413 tNET RR 1 itcm_valid_s3/I3
2.487 0.289 tINS RR 5 itcm_valid_s3/F
2.900 0.413 tNET RR 1 u_dm/u_dm2dtm_cdc_tx/vld_set_s4/I0
3.479 0.579 tINS RR 4 u_dm/u_dm2dtm_cdc_tx/vld_set_s4/F
3.891 0.413 tNET RR 1 u_dm/u_dm2dtm_cdc_tx/vld_set_s0/I2
4.399 0.507 tINS RR 41 u_dm/u_dm2dtm_cdc_tx/vld_set_s0/F
4.811 0.413 tNET RR 1 u_dm/ram_addr_2_s2/I3
5.100 0.289 tINS RR 70 u_dm/ram_addr_2_s2/F
5.513 0.413 tNET RR 1 u_dm/ram_addr_0_s0/I2
6.020 0.507 tINS RR 103 u_dm/ram_addr_0_s0/F
6.433 0.413 tNET RR 1 u_dm/u_s_debug_ram/ram_dout_Z_24_s4/I2
6.940 0.507 tINS RR 1 u_dm/u_s_debug_ram/ram_dout_Z_24_s4/F
7.353 0.413 tNET RR 1 u_dm/u_s_debug_ram/ram_dout_Z_24_s1/I0
7.503 0.150 tINS RR 1 u_dm/u_s_debug_ram/ram_dout_Z_24_s1/O
7.915 0.413 tNET RR 1 u_dm/u_s_debug_ram/ram_dout_Z_24_s/I1
8.001 0.086 tINS RR 2 u_dm/u_s_debug_ram/ram_dout_Z_24_s/O
8.414 0.413 tNET RR 1 mem_rdata_24_s5/I2
8.921 0.507 tINS RR 1 mem_rdata_24_s5/F
9.334 0.413 tNET RR 1 mem_rdata_24_s3/I0
9.913 0.579 tINS RR 1 mem_rdata_24_s3/F
10.325 0.413 tNET RR 1 mem_rdata_24_s1/I0
10.904 0.579 tINS RR 3 mem_rdata_24_s1/F
11.316 0.413 tNET RR 1 core/mem_rdata_latched_24_s1/I0
11.895 0.579 tINS RR 1 core/mem_rdata_latched_24_s1/F
12.308 0.413 tNET RR 1 core/mem_rdata_latched_24_s0/I0
12.886 0.579 tINS RR 5 core/mem_rdata_latched_24_s0/F
13.299 0.413 tNET RR 1 core/n2082_s9/I0
13.878 0.579 tINS RR 3 core/n2082_s9/F
14.290 0.413 tNET RR 1 core/n2082_s14/I0
14.869 0.579 tINS RR 1 core/n2082_s14/F
15.281 0.413 tNET RR 1 core/n2082_s1/I0
15.860 0.579 tINS RR 1 core/n2082_s1/F
16.273 0.413 tNET RR 1 core/n2082_s0/I0
16.851 0.579 tINS RR 1 core/n2082_s0/F
17.264 0.413 tNET RR 1 core/mem_rdata_q_24_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_in
10.000 0.000 tCL RR 1 clk_in_ibuf/I
10.000 0.000 tINS RR 4416 clk_in_ibuf/O
10.413 0.413 tNET RR 1 core/mem_rdata_q_24_s0/CLK
10.349 -0.064 tSu 1 core/mem_rdata_q_24_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 17
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 8.631, 51.220%; route: 7.837, 46.510%; tC2Q: 0.382, 2.270%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 4

Path Summary:
Slack -6.881
Data Arrival Time 17.230
Data Required Time 10.349
From core/mem_addr_26_s0
To core/csr_mcause_2_s0
Launch Clk clk_in[R]
Latch Clk clk_in[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_in
0.000 0.000 tCL RR 1 clk_in_ibuf/I
0.000 0.000 tINS RR 4416 clk_in_ibuf/O
0.413 0.413 tNET RR 1 core/mem_addr_26_s0/CLK
0.795 0.382 tC2Q RR 3 core/mem_addr_26_s0/Q
1.207 0.413 tNET RR 1 itcm_valid_s2/I0
1.786 0.579 tINS RR 3 itcm_valid_s2/F
2.199 0.413 tNET RR 1 itcm_valid_s3/I3
2.487 0.289 tINS RR 5 itcm_valid_s3/F
2.900 0.413 tNET RR 1 u_dm/u_dm2dtm_cdc_tx/vld_set_s4/I0
3.479 0.579 tINS RR 4 u_dm/u_dm2dtm_cdc_tx/vld_set_s4/F
3.891 0.413 tNET RR 1 u_dm/u_dm2dtm_cdc_tx/vld_set_s0/I2
4.399 0.507 tINS RR 41 u_dm/u_dm2dtm_cdc_tx/vld_set_s0/F
4.811 0.413 tNET RR 1 u_dm/ram_addr_2_s2/I3
5.100 0.289 tINS RR 70 u_dm/ram_addr_2_s2/F
5.513 0.413 tNET RR 1 u_dm/ram_addr_0_s0/I2
6.020 0.507 tINS RR 103 u_dm/ram_addr_0_s0/F
6.433 0.413 tNET RR 1 u_dm/u_s_debug_ram/ram_dout_Z_0_s4/I2
6.940 0.507 tINS RR 1 u_dm/u_s_debug_ram/ram_dout_Z_0_s4/F
7.353 0.413 tNET RR 1 u_dm/u_s_debug_ram/ram_dout_Z_0_s1/I0
7.503 0.150 tINS RR 1 u_dm/u_s_debug_ram/ram_dout_Z_0_s1/O
7.915 0.413 tNET RR 1 u_dm/u_s_debug_ram/ram_dout_Z_0_s/I1
8.001 0.086 tINS RR 2 u_dm/u_s_debug_ram/ram_dout_Z_0_s/O
8.414 0.413 tNET RR 1 core/n2293_s7/I0
8.993 0.579 tINS RR 1 core/n2293_s7/F
9.405 0.413 tNET RR 1 core/n2293_s3/I1
9.973 0.567 tINS RR 1 core/n2293_s3/F
10.385 0.413 tNET RR 1 core/n2293_s1/I0
10.964 0.579 tINS RR 4 core/n2293_s1/F
11.376 0.413 tNET RR 1 core/mem_rdata_latched_0_s2/I0
11.955 0.579 tINS RR 8 core/mem_rdata_latched_0_s2/F
12.368 0.413 tNET RR 1 core/n5288_s3/I1
12.935 0.567 tINS RR 55 core/n5288_s3/F
13.348 0.413 tNET RR 1 core/n5178_s1/I0
13.926 0.579 tINS RR 7 core/n5178_s1/F
14.339 0.413 tNET RR 1 core/csr_mcause_30_s3/I1
14.906 0.567 tINS RR 31 core/csr_mcause_30_s3/F
15.319 0.413 tNET RR 1 core/n11427_s2/I0
15.898 0.579 tINS RR 1 core/n11427_s2/F
16.310 0.413 tNET RR 1 core/n11427_s0/I2
16.818 0.507 tINS RR 1 core/n11427_s0/F
17.230 0.413 tNET RR 1 core/csr_mcause_2_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_in
10.000 0.000 tCL RR 1 clk_in_ibuf/I
10.000 0.000 tINS RR 4416 clk_in_ibuf/O
10.413 0.413 tNET RR 1 core/csr_mcause_2_s0/CLK
10.349 -0.064 tSu 1 core/csr_mcause_2_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 17
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 8.597, 51.123%; route: 7.837, 46.603%; tC2Q: 0.382, 2.274%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 5

Path Summary:
Slack -6.870
Data Arrival Time 17.219
Data Required Time 10.349
From core/mem_addr_26_s0
To core/decoded_rd_3_s0
Launch Clk clk_in[R]
Latch Clk clk_in[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_in
0.000 0.000 tCL RR 1 clk_in_ibuf/I
0.000 0.000 tINS RR 4416 clk_in_ibuf/O
0.413 0.413 tNET RR 1 core/mem_addr_26_s0/CLK
0.795 0.382 tC2Q RR 3 core/mem_addr_26_s0/Q
1.207 0.413 tNET RR 1 itcm_valid_s2/I0
1.786 0.579 tINS RR 3 itcm_valid_s2/F
2.199 0.413 tNET RR 1 itcm_valid_s3/I3
2.487 0.289 tINS RR 5 itcm_valid_s3/F
2.900 0.413 tNET RR 1 u_dm/u_dm2dtm_cdc_tx/vld_set_s4/I0
3.479 0.579 tINS RR 4 u_dm/u_dm2dtm_cdc_tx/vld_set_s4/F
3.891 0.413 tNET RR 1 u_dm/u_dm2dtm_cdc_tx/vld_set_s0/I2
4.399 0.507 tINS RR 41 u_dm/u_dm2dtm_cdc_tx/vld_set_s0/F
4.811 0.413 tNET RR 1 u_dm/ram_addr_2_s2/I3
5.100 0.289 tINS RR 70 u_dm/ram_addr_2_s2/F
5.513 0.413 tNET RR 1 u_dm/ram_addr_0_s0/I2
6.020 0.507 tINS RR 103 u_dm/ram_addr_0_s0/F
6.433 0.413 tNET RR 1 u_dm/u_s_debug_ram/ram_dout_Z_19_s4/I2
6.940 0.507 tINS RR 1 u_dm/u_s_debug_ram/ram_dout_Z_19_s4/F
7.353 0.413 tNET RR 1 u_dm/u_s_debug_ram/ram_dout_Z_19_s1/I0
7.503 0.150 tINS RR 1 u_dm/u_s_debug_ram/ram_dout_Z_19_s1/O
7.915 0.413 tNET RR 1 u_dm/u_s_debug_ram/ram_dout_Z_19_s/I1
8.001 0.086 tINS RR 2 u_dm/u_s_debug_ram/ram_dout_Z_19_s/O
8.414 0.413 tNET RR 1 mem_rdata_19_s5/I0
8.993 0.579 tINS RR 1 mem_rdata_19_s5/F
9.405 0.413 tNET RR 1 mem_rdata_19_s1/I1
9.973 0.567 tINS RR 2 mem_rdata_19_s1/F
10.385 0.413 tNET RR 1 core/mem_rdata_latched_3_s3/I0
10.964 0.579 tINS RR 1 core/mem_rdata_latched_3_s3/F
11.376 0.413 tNET RR 1 core/mem_rdata_latched_3_s1/I1
11.944 0.567 tINS RR 17 core/mem_rdata_latched_3_s1/F
12.356 0.413 tNET RR 1 core/n5248_s5/I1
12.924 0.567 tINS RR 7 core/n5248_s5/F
13.336 0.413 tNET RR 1 core/n5640_s6/I0
13.915 0.579 tINS RR 3 core/n5640_s6/F
14.328 0.413 tNET RR 1 core/n5578_s3/I1
14.895 0.567 tINS RR 3 core/n5578_s3/F
15.308 0.413 tNET RR 1 core/n5578_s1/I2
15.815 0.507 tINS RR 1 core/n5578_s1/F
16.228 0.413 tNET RR 1 core/n5579_s0/I0
16.806 0.579 tINS RR 1 core/n5579_s0/F
17.219 0.413 tNET RR 1 core/decoded_rd_3_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_in
10.000 0.000 tCL RR 1 clk_in_ibuf/I
10.000 0.000 tINS RR 4416 clk_in_ibuf/O
10.413 0.413 tNET RR 1 core/decoded_rd_3_s0/CLK
10.349 -0.064 tSu 1 core/decoded_rd_3_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 17
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 8.586, 51.090%; route: 7.837, 46.634%; tC2Q: 0.382, 2.276%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%