Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\picorv32.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\picosoc.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\advspi.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\ahb_bus.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\picosoc_dtcm.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\picosoc_itcm.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wb_bus.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wb_brancher.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wbgpio.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wbi2c.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wbspi.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wbuart.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\simpleuart.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\dm.v |
GowinSynthesis Constraints File | --- |
Tool Version | V1.9.11.02 (64-bit) |
Part Number | GW5A-LV25UG324C2/I1 |
Device | GW5A-25 |
Device Version | A |
Created Time | Tue May 20 09:50:29 2025 |
Legal Announcement | Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | Gowin_PicoRV32_Top |
Synthesis Process | Running parser: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 132.383MB Running netlist conversion: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.103s, Peak memory usage = 132.383MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.765s, Elapsed time = 0h 0m 0.771s, Peak memory usage = 132.383MB Optimizing Phase 1: CPU time = 0h 0m 0.312s, Elapsed time = 0h 0m 0.307s, Peak memory usage = 132.383MB Optimizing Phase 2: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 132.383MB Running inference: Inferring Phase 0: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 132.383MB Inferring Phase 1: CPU time = 0h 0m 0.562s, Elapsed time = 0h 0m 0.573s, Peak memory usage = 132.383MB Inferring Phase 2: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.064s, Peak memory usage = 132.383MB Inferring Phase 3: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.037s, Peak memory usage = 132.383MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 132.383MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.484s, Elapsed time = 0h 0m 0.49s, Peak memory usage = 132.383MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.515s, Elapsed time = 0h 0m 0.507s, Peak memory usage = 132.383MB Tech-Mapping Phase 3: CPU time = 0h 0m 28s, Elapsed time = 0h 0m 29s, Peak memory usage = 147.238MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.812s, Elapsed time = 0h 0m 0.872s, Peak memory usage = 147.238MB Generate output files: CPU time = 0h 0m 0.812s, Elapsed time = 0h 0m 1s, Peak memory usage = 192.004MB |
Total Time and Memory Usage | CPU time = 0h 0m 36s, Elapsed time = 0h 0m 37s, Peak memory usage = 192.004MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 241 |
I/O Buf | 239 |
    IBUF | 84 |
    OBUF | 147 |
    TBUF | 2 |
    IOBUF | 6 |
Register | 4536 |
    DFFSE | 96 |
    DFFRE | 3068 |
    DFFPE | 17 |
    DFFCE | 1355 |
LUT | 6755 |
    LUT2 | 503 |
    LUT3 | 2193 |
    LUT4 | 4059 |
ALU | 630 |
    ALU | 630 |
INV | 23 |
    INV | 23 |
DSP | |
    MULT27X36 | 2 |
BSRAM | 32 |
    SDPB | 32 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 7408(6778 LUT, 630 ALU) / 23040 | 33% |
Register | 4536 / 23685 | 20% |
  --Register as Latch | 0 / 23685 | 0% |
  --Register as FF | 4536 / 23685 | 20% |
BSRAM | 32 / 56 | 58% |
Timing
Clock Summary:
NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|---|
1 | clk_in | Base | 10.000 | 100.000 | 0.000 | 5.000 | clk_in_ibuf/I | ||
2 | jtag_TCK | Base | 10.000 | 100.000 | 0.000 | 5.000 | jtag_TCK_ibuf/I | ||
3 | u_dualportspi/u_atcspi/u_spi_spiif/n316_3 | Base | 10.000 | 100.000 | 0.000 | 5.000 | u_dualportspi/u_atcspi/u_spi_spiif/n316_s0/F |
Max Frequency Summary:
NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | clk_in | 100.000(MHz) | 65.608(MHz) | 11 | TOP |
2 | jtag_TCK | 100.000(MHz) | 119.875(MHz) | 6 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | -2.621 |
Data Arrival Time | 12.870 |
Data Required Time | 10.249 |
From | rstdly_15_s0 |
To | core/mem_rdata_q_24_s0 |
Launch Clk | clk_in[R] |
Latch Clk | clk_in[F] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
5.000 | 0.000 | clk_in | |||
5.000 | 0.000 | tCL | FF | 1 | clk_in_ibuf/I |
5.000 | 0.000 | tINS | FF | 4416 | clk_in_ibuf/O |
5.280 | 0.280 | tNET | FF | 1 | rstdly_15_s0/CLK |
5.627 | 0.347 | tC2Q | FR | 29 | rstdly_15_s0/Q |
5.927 | 0.300 | tNET | RR | 1 | core/n7234_s2/I3 |
6.137 | 0.210 | tINS | RR | 2 | core/n7234_s2/F |
6.437 | 0.300 | tNET | RR | 1 | core/mem_xfer_s1/I1 |
6.850 | 0.413 | tINS | RR | 27 | core/mem_xfer_s1/F |
7.150 | 0.300 | tNET | RR | 1 | core/mem_xfer_s0/I1 |
7.563 | 0.413 | tINS | RR | 85 | core/mem_xfer_s0/F |
7.863 | 0.300 | tNET | RR | 1 | core/mem_rdata_latched_10_s3/I1 |
8.276 | 0.413 | tINS | RR | 1 | core/mem_rdata_latched_10_s3/F |
8.576 | 0.300 | tNET | RR | 1 | core/mem_rdata_latched_10_s1/I1 |
8.989 | 0.413 | tINS | RR | 25 | core/mem_rdata_latched_10_s1/F |
9.289 | 0.300 | tNET | RR | 1 | core/n5231_s11/I1 |
9.702 | 0.413 | tINS | RR | 3 | core/n5231_s11/F |
10.002 | 0.300 | tNET | RR | 1 | core/n2082_s10/I0 |
10.423 | 0.421 | tINS | RR | 2 | core/n2082_s10/F |
10.723 | 0.300 | tNET | RR | 1 | core/n2082_s7/I1 |
11.136 | 0.413 | tINS | RR | 3 | core/n2082_s7/F |
11.436 | 0.300 | tNET | RR | 1 | core/n2082_s2/I0 |
11.857 | 0.421 | tINS | RR | 1 | core/n2082_s2/F |
12.157 | 0.300 | tNET | RR | 1 | core/n2082_s0/I1 |
12.570 | 0.413 | tINS | RR | 1 | core/n2082_s0/F |
12.870 | 0.300 | tNET | RR | 1 | core/mem_rdata_q_24_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk_in | |||
10.000 | 0.000 | tCL | RR | 1 | clk_in_ibuf/I |
10.000 | 0.000 | tINS | RR | 4416 | clk_in_ibuf/O |
10.300 | 0.300 | tNET | RR | 1 | core/mem_rdata_q_24_s0/CLK |
10.249 | -0.051 | tSu | 1 | core/mem_rdata_q_24_s0 |
Clock Skew: | 0.020 |
Setup Relationship: | 5.000 |
Logic Level: | 11 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.280, 100.000% |
Arrival Data Path Delay: | cell: 3.943, 51.950%; route: 3.300, 43.478%; tC2Q: 0.347, 4.572% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.280, 100.000% |
Path 2
Path Summary:Slack | -2.601 |
Data Arrival Time | 12.850 |
Data Required Time | 10.249 |
From | rstdly_15_s0 |
To | core/mem_rdata_q_28_s0 |
Launch Clk | clk_in[R] |
Latch Clk | clk_in[F] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
5.000 | 0.000 | clk_in | |||
5.000 | 0.000 | tCL | FF | 1 | clk_in_ibuf/I |
5.000 | 0.000 | tINS | FF | 4416 | clk_in_ibuf/O |
5.280 | 0.280 | tNET | FF | 1 | rstdly_15_s0/CLK |
5.627 | 0.347 | tC2Q | FR | 29 | rstdly_15_s0/Q |
5.927 | 0.300 | tNET | RR | 1 | core/n7234_s2/I3 |
6.137 | 0.210 | tINS | RR | 2 | core/n7234_s2/F |
6.437 | 0.300 | tNET | RR | 1 | core/mem_xfer_s1/I1 |
6.850 | 0.413 | tINS | RR | 27 | core/mem_xfer_s1/F |
7.150 | 0.300 | tNET | RR | 1 | core/mem_xfer_s0/I1 |
7.563 | 0.413 | tINS | RR | 85 | core/mem_xfer_s0/F |
7.863 | 0.300 | tNET | RR | 1 | core/mem_rdata_latched_12_s2/I1 |
8.276 | 0.413 | tINS | RR | 1 | core/mem_rdata_latched_12_s2/F |
8.576 | 0.300 | tNET | RR | 1 | core/mem_rdata_latched_12_s1/I0 |
8.997 | 0.421 | tINS | RR | 54 | core/mem_rdata_latched_12_s1/F |
9.297 | 0.300 | tNET | RR | 1 | core/n2078_s9/I0 |
9.718 | 0.421 | tINS | RR | 1 | core/n2078_s9/F |
10.018 | 0.300 | tNET | RR | 1 | core/n2078_s7/I2 |
10.387 | 0.369 | tINS | RR | 1 | core/n2078_s7/F |
10.687 | 0.300 | tNET | RR | 1 | core/n2078_s4/I0 |
11.108 | 0.421 | tINS | RR | 1 | core/n2078_s4/F |
11.408 | 0.300 | tNET | RR | 1 | core/n2078_s1/I0 |
11.829 | 0.421 | tINS | RR | 1 | core/n2078_s1/F |
12.129 | 0.300 | tNET | RR | 1 | core/n2078_s0/I0 |
12.550 | 0.421 | tINS | RR | 1 | core/n2078_s0/F |
12.850 | 0.300 | tNET | RR | 1 | core/mem_rdata_q_28_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk_in | |||
10.000 | 0.000 | tCL | RR | 1 | clk_in_ibuf/I |
10.000 | 0.000 | tINS | RR | 4416 | clk_in_ibuf/O |
10.300 | 0.300 | tNET | RR | 1 | core/mem_rdata_q_28_s0/CLK |
10.249 | -0.051 | tSu | 1 | core/mem_rdata_q_28_s0 |
Clock Skew: | 0.020 |
Setup Relationship: | 5.000 |
Logic Level: | 11 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.280, 100.000% |
Arrival Data Path Delay: | cell: 3.923, 51.823%; route: 3.300, 43.593%; tC2Q: 0.347, 4.584% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.280, 100.000% |
Path 3
Path Summary:Slack | -2.601 |
Data Arrival Time | 12.850 |
Data Required Time | 10.249 |
From | rstdly_15_s0 |
To | core/mem_rdata_q_20_s0 |
Launch Clk | clk_in[R] |
Latch Clk | clk_in[F] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
5.000 | 0.000 | clk_in | |||
5.000 | 0.000 | tCL | FF | 1 | clk_in_ibuf/I |
5.000 | 0.000 | tINS | FF | 4416 | clk_in_ibuf/O |
5.280 | 0.280 | tNET | FF | 1 | rstdly_15_s0/CLK |
5.627 | 0.347 | tC2Q | FR | 29 | rstdly_15_s0/Q |
5.927 | 0.300 | tNET | RR | 1 | core/n7234_s2/I3 |
6.137 | 0.210 | tINS | RR | 2 | core/n7234_s2/F |
6.437 | 0.300 | tNET | RR | 1 | core/mem_xfer_s1/I1 |
6.850 | 0.413 | tINS | RR | 27 | core/mem_xfer_s1/F |
7.150 | 0.300 | tNET | RR | 1 | core/mem_rdata_latched_30_s5/I0 |
7.571 | 0.421 | tINS | RR | 2 | core/mem_rdata_latched_30_s5/F |
7.871 | 0.300 | tNET | RR | 1 | core/n5624_s2/I1 |
8.284 | 0.413 | tINS | RR | 1 | core/n5624_s2/F |
8.584 | 0.300 | tNET | RR | 1 | core/n5624_s1/I0 |
9.005 | 0.421 | tINS | RR | 49 | core/n5624_s1/F |
9.305 | 0.300 | tNET | RR | 1 | core/n5204_s3/I0 |
9.726 | 0.421 | tINS | RR | 2 | core/n5204_s3/F |
10.026 | 0.300 | tNET | RR | 1 | core/n2084_s15/I2 |
10.395 | 0.369 | tINS | RR | 9 | core/n2084_s15/F |
10.695 | 0.300 | tNET | RR | 1 | core/n2085_s5/I1 |
11.108 | 0.413 | tINS | RR | 1 | core/n2085_s5/F |
11.408 | 0.300 | tNET | RR | 1 | core/n2085_s1/I0 |
11.829 | 0.421 | tINS | RR | 2 | core/n2085_s1/F |
12.129 | 0.300 | tNET | RR | 1 | core/n2086_s0/I0 |
12.550 | 0.421 | tINS | RR | 1 | core/n2086_s0/F |
12.850 | 0.300 | tNET | RR | 1 | core/mem_rdata_q_20_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk_in | |||
10.000 | 0.000 | tCL | RR | 1 | clk_in_ibuf/I |
10.000 | 0.000 | tINS | RR | 4416 | clk_in_ibuf/O |
10.300 | 0.300 | tNET | RR | 1 | core/mem_rdata_q_20_s0/CLK |
10.249 | -0.051 | tSu | 1 | core/mem_rdata_q_20_s0 |
Clock Skew: | 0.020 |
Setup Relationship: | 5.000 |
Logic Level: | 11 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.280, 100.000% |
Arrival Data Path Delay: | cell: 3.923, 51.823%; route: 3.300, 43.593%; tC2Q: 0.347, 4.584% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.280, 100.000% |
Path 4
Path Summary:Slack | -2.601 |
Data Arrival Time | 12.850 |
Data Required Time | 10.249 |
From | rstdly_15_s0 |
To | core/mem_rdata_q_21_s0 |
Launch Clk | clk_in[R] |
Latch Clk | clk_in[F] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
5.000 | 0.000 | clk_in | |||
5.000 | 0.000 | tCL | FF | 1 | clk_in_ibuf/I |
5.000 | 0.000 | tINS | FF | 4416 | clk_in_ibuf/O |
5.280 | 0.280 | tNET | FF | 1 | rstdly_15_s0/CLK |
5.627 | 0.347 | tC2Q | FR | 29 | rstdly_15_s0/Q |
5.927 | 0.300 | tNET | RR | 1 | core/n7234_s2/I3 |
6.137 | 0.210 | tINS | RR | 2 | core/n7234_s2/F |
6.437 | 0.300 | tNET | RR | 1 | core/mem_xfer_s1/I1 |
6.850 | 0.413 | tINS | RR | 27 | core/mem_xfer_s1/F |
7.150 | 0.300 | tNET | RR | 1 | core/mem_rdata_latched_30_s5/I0 |
7.571 | 0.421 | tINS | RR | 2 | core/mem_rdata_latched_30_s5/F |
7.871 | 0.300 | tNET | RR | 1 | core/n5624_s2/I1 |
8.284 | 0.413 | tINS | RR | 1 | core/n5624_s2/F |
8.584 | 0.300 | tNET | RR | 1 | core/n5624_s1/I0 |
9.005 | 0.421 | tINS | RR | 49 | core/n5624_s1/F |
9.305 | 0.300 | tNET | RR | 1 | core/n5204_s3/I0 |
9.726 | 0.421 | tINS | RR | 2 | core/n5204_s3/F |
10.026 | 0.300 | tNET | RR | 1 | core/n2084_s15/I2 |
10.395 | 0.369 | tINS | RR | 9 | core/n2084_s15/F |
10.695 | 0.300 | tNET | RR | 1 | core/n2085_s5/I1 |
11.108 | 0.413 | tINS | RR | 1 | core/n2085_s5/F |
11.408 | 0.300 | tNET | RR | 1 | core/n2085_s1/I0 |
11.829 | 0.421 | tINS | RR | 2 | core/n2085_s1/F |
12.129 | 0.300 | tNET | RR | 1 | core/n2085_s0/I0 |
12.550 | 0.421 | tINS | RR | 1 | core/n2085_s0/F |
12.850 | 0.300 | tNET | RR | 1 | core/mem_rdata_q_21_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk_in | |||
10.000 | 0.000 | tCL | RR | 1 | clk_in_ibuf/I |
10.000 | 0.000 | tINS | RR | 4416 | clk_in_ibuf/O |
10.300 | 0.300 | tNET | RR | 1 | core/mem_rdata_q_21_s0/CLK |
10.249 | -0.051 | tSu | 1 | core/mem_rdata_q_21_s0 |
Clock Skew: | 0.020 |
Setup Relationship: | 5.000 |
Logic Level: | 11 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.280, 100.000% |
Arrival Data Path Delay: | cell: 3.923, 51.823%; route: 3.300, 43.593%; tC2Q: 0.347, 4.584% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.280, 100.000% |
Path 5
Path Summary:Slack | -2.601 |
Data Arrival Time | 12.850 |
Data Required Time | 10.249 |
From | rstdly_15_s0 |
To | core/mem_rdata_q_23_s0 |
Launch Clk | clk_in[R] |
Latch Clk | clk_in[F] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
5.000 | 0.000 | clk_in | |||
5.000 | 0.000 | tCL | FF | 1 | clk_in_ibuf/I |
5.000 | 0.000 | tINS | FF | 4416 | clk_in_ibuf/O |
5.280 | 0.280 | tNET | FF | 1 | rstdly_15_s0/CLK |
5.627 | 0.347 | tC2Q | FR | 29 | rstdly_15_s0/Q |
5.927 | 0.300 | tNET | RR | 1 | core/n7234_s2/I3 |
6.137 | 0.210 | tINS | RR | 2 | core/n7234_s2/F |
6.437 | 0.300 | tNET | RR | 1 | core/mem_xfer_s1/I1 |
6.850 | 0.413 | tINS | RR | 27 | core/mem_xfer_s1/F |
7.150 | 0.300 | tNET | RR | 1 | core/mem_rdata_latched_29_s5/I0 |
7.571 | 0.421 | tINS | RR | 2 | core/mem_rdata_latched_29_s5/F |
7.871 | 0.300 | tNET | RR | 1 | core/n5625_s2/I1 |
8.284 | 0.413 | tINS | RR | 1 | core/n5625_s2/F |
8.584 | 0.300 | tNET | RR | 1 | core/n5625_s1/I0 |
9.005 | 0.421 | tINS | RR | 43 | core/n5625_s1/F |
9.305 | 0.300 | tNET | RR | 1 | core/n5579_s2/I1 |
9.718 | 0.413 | tINS | RR | 14 | core/n5579_s2/F |
10.018 | 0.300 | tNET | RR | 1 | core/n2083_s12/I0 |
10.439 | 0.421 | tINS | RR | 1 | core/n2083_s12/F |
10.739 | 0.300 | tNET | RR | 1 | core/n2083_s5/I0 |
11.160 | 0.421 | tINS | RR | 1 | core/n2083_s5/F |
11.460 | 0.300 | tNET | RR | 1 | core/n2083_s1/I2 |
11.829 | 0.369 | tINS | RR | 1 | core/n2083_s1/F |
12.129 | 0.300 | tNET | RR | 1 | core/n2083_s13/I0 |
12.550 | 0.421 | tINS | RR | 1 | core/n2083_s13/F |
12.850 | 0.300 | tNET | RR | 1 | core/mem_rdata_q_23_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk_in | |||
10.000 | 0.000 | tCL | RR | 1 | clk_in_ibuf/I |
10.000 | 0.000 | tINS | RR | 4416 | clk_in_ibuf/O |
10.300 | 0.300 | tNET | RR | 1 | core/mem_rdata_q_23_s0/CLK |
10.249 | -0.051 | tSu | 1 | core/mem_rdata_q_23_s0 |
Clock Skew: | 0.020 |
Setup Relationship: | 5.000 |
Logic Level: | 11 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.280, 100.000% |
Arrival Data Path Delay: | cell: 3.923, 51.823%; route: 3.300, 43.593%; tC2Q: 0.347, 4.584% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.280, 100.000% |