Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\picorv32.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\picosoc.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\advspi.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\ahb_bus.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\picosoc_dtcm.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\picosoc_itcm.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wb_bus.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wb_brancher.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wbgpio.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wbi2c.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wbspi.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wbuart.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\simpleuart.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\dm.v
GowinSynthesis Constraints File ---
Tool Version V1.9.11.02 (64-bit)
Part Number GW5AT-LV60UG225C2/I1
Device GW5AT-60
Device Version B
Created Time Tue May 20 13:57:42 2025
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module Gowin_PicoRV32_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 132.285MB
Running netlist conversion:
    CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.101s, Peak memory usage = 132.285MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.75s, Elapsed time = 0h 0m 0.75s, Peak memory usage = 132.285MB
    Optimizing Phase 1: CPU time = 0h 0m 0.296s, Elapsed time = 0h 0m 0.303s, Peak memory usage = 132.285MB
    Optimizing Phase 2: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 132.285MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.578s, Elapsed time = 0h 0m 0.576s, Peak memory usage = 132.285MB
    Inferring Phase 1: CPU time = 0h 0m 0.468s, Elapsed time = 0h 0m 0.455s, Peak memory usage = 132.285MB
    Inferring Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.057s, Peak memory usage = 132.285MB
    Inferring Phase 3: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.034s, Peak memory usage = 132.285MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 132.285MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.453s, Elapsed time = 0h 0m 0.461s, Peak memory usage = 132.285MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.468s, Elapsed time = 0h 0m 0.456s, Peak memory usage = 132.285MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 28s, Elapsed time = 0h 0m 28s, Peak memory usage = 146.781MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.734s, Elapsed time = 0h 0m 0.861s, Peak memory usage = 146.781MB
Generate output files:
    CPU time = 0h 0m 0.765s, Elapsed time = 0h 0m 0.83s, Peak memory usage = 191.063MB
Total Time and Memory Usage CPU time = 0h 0m 35s, Elapsed time = 0h 0m 35s, Peak memory usage = 191.063MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 239
I/O Buf 237
    IBUF 84
    OBUF 147
    TBUF 2
    IOBUF 4
Register 4012
    DFFSE 96
    DFFRE 2547
    DFFPE 17
    DFFCE 1352
LUT 6291
    LUT2 504
    LUT3 2003
    LUT4 3784
ALU 630
    ALU 630
SSRAM 24
    RAM16SDP4 24
INV 23
    INV 23
DSP
    MULT27X36 2
BSRAM 64
    SDPB 64

Resource Utilization Summary

Resource Usage Utilization
Logic 7088(6314 LUT, 630 ALU, 24 RAM16) / 59904 12%
Register 4012 / 60228 7%
  --Register as Latch 0 / 60228 0%
  --Register as FF 4012 / 60228 7%
BSRAM 64 / 118 55%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 clk_in Base 10.000 100.000 0.000 5.000 clk_in_ibuf/I
2 jtag_TCK Base 10.000 100.000 0.000 5.000 jtag_TCK_ibuf/I
3 u_dualportspi/u_atcspi/u_spi_spiif/n316_3 Base 10.000 100.000 0.000 5.000 u_dualportspi/u_atcspi/u_spi_spiif/n316_s0/F

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk_in 100.000(MHz) 65.989(MHz) 11 TOP
2 jtag_TCK 100.000(MHz) 118.624(MHz) 6 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack -2.577
Data Arrival Time 12.826
Data Required Time 10.249
From rstdly_15_s0
To core/decoded_rs1_1_s0
Launch Clk clk_in[R]
Latch Clk clk_in[F]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
5.000 0.000 clk_in
5.000 0.000 tCL FF 1 clk_in_ibuf/I
5.000 0.000 tINS FF 3980 clk_in_ibuf/O
5.280 0.280 tNET FF 1 rstdly_15_s0/CLK
5.627 0.347 tC2Q FR 30 rstdly_15_s0/Q
5.927 0.300 tNET RR 1 core/n7234_s2/I3
6.137 0.210 tINS RR 2 core/n7234_s2/F
6.437 0.300 tNET RR 1 core/mem_xfer_s1/I1
6.850 0.413 tINS RR 42 core/mem_xfer_s1/F
7.150 0.300 tNET RR 1 core/mem_xfer_s0/I1
7.563 0.413 tINS RR 89 core/mem_xfer_s0/F
7.863 0.300 tNET RR 1 core/mem_rdata_latched_6_s3/I2
8.232 0.369 tINS RR 1 core/mem_rdata_latched_6_s3/F
8.532 0.300 tNET RR 1 core/mem_rdata_latched_6_s2/I1
8.945 0.413 tINS RR 3 core/mem_rdata_latched_6_s2/F
9.245 0.300 tNET RR 1 core/n5189_s5/I1
9.658 0.413 tINS RR 9 core/n5189_s5/F
9.958 0.300 tNET RR 1 core/n5638_s6/I1
10.371 0.413 tINS RR 7 core/n5638_s6/F
10.671 0.300 tNET RR 1 core/n5584_s6/I0
11.092 0.421 tINS RR 5 core/n5584_s6/F
11.392 0.300 tNET RR 1 core/n5587_s1/I0
11.813 0.421 tINS RR 1 core/n5587_s1/F
12.113 0.300 tNET RR 1 core/n5587_s0/I1
12.526 0.413 tINS RR 1 core/n5587_s0/F
12.826 0.300 tNET RR 1 core/decoded_rs1_1_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_in
10.000 0.000 tCL RR 1 clk_in_ibuf/I
10.000 0.000 tINS RR 3980 clk_in_ibuf/O
10.300 0.300 tNET RR 1 core/decoded_rs1_1_s0/CLK
10.249 -0.051 tSu 1 core/decoded_rs1_1_s0
Path Statistics:
Clock Skew: 0.020
Setup Relationship: 5.000
Logic Level: 11
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.280, 100.000%
Arrival Data Path Delay: cell: 3.899, 51.670%; route: 3.300, 43.732%; tC2Q: 0.347, 4.598%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.280, 100.000%

Path 2

Path Summary:
Slack -2.569
Data Arrival Time 12.818
Data Required Time 10.249
From rstdly_15_s0
To core/decoded_rs1_0_s0
Launch Clk clk_in[R]
Latch Clk clk_in[F]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
5.000 0.000 clk_in
5.000 0.000 tCL FF 1 clk_in_ibuf/I
5.000 0.000 tINS FF 3980 clk_in_ibuf/O
5.280 0.280 tNET FF 1 rstdly_15_s0/CLK
5.627 0.347 tC2Q FR 30 rstdly_15_s0/Q
5.927 0.300 tNET RR 1 core/n7234_s2/I3
6.137 0.210 tINS RR 2 core/n7234_s2/F
6.437 0.300 tNET RR 1 core/mem_xfer_s1/I1
6.850 0.413 tINS RR 42 core/mem_xfer_s1/F
7.150 0.300 tNET RR 1 core/mem_xfer_s0/I1
7.563 0.413 tINS RR 89 core/mem_xfer_s0/F
7.863 0.300 tNET RR 1 core/mem_rdata_latched_6_s3/I2
8.232 0.369 tINS RR 1 core/mem_rdata_latched_6_s3/F
8.532 0.300 tNET RR 1 core/mem_rdata_latched_6_s2/I1
8.945 0.413 tINS RR 3 core/mem_rdata_latched_6_s2/F
9.245 0.300 tNET RR 1 core/n5189_s5/I1
9.658 0.413 tINS RR 9 core/n5189_s5/F
9.958 0.300 tNET RR 1 core/n5638_s6/I1
10.371 0.413 tINS RR 7 core/n5638_s6/F
10.671 0.300 tNET RR 1 core/n5584_s6/I0
11.092 0.421 tINS RR 5 core/n5584_s6/F
11.392 0.300 tNET RR 1 core/n5588_s1/I1
11.805 0.413 tINS RR 1 core/n5588_s1/F
12.105 0.300 tNET RR 1 core/n5588_s0/I1
12.518 0.413 tINS RR 1 core/n5588_s0/F
12.818 0.300 tNET RR 1 core/decoded_rs1_0_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_in
10.000 0.000 tCL RR 1 clk_in_ibuf/I
10.000 0.000 tINS RR 3980 clk_in_ibuf/O
10.300 0.300 tNET RR 1 core/decoded_rs1_0_s0/CLK
10.249 -0.051 tSu 1 core/decoded_rs1_0_s0
Path Statistics:
Clock Skew: 0.020
Setup Relationship: 5.000
Logic Level: 11
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.280, 100.000%
Arrival Data Path Delay: cell: 3.891, 51.619%; route: 3.300, 43.778%; tC2Q: 0.347, 4.603%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.280, 100.000%

Path 3

Path Summary:
Slack -2.541
Data Arrival Time 12.790
Data Required Time 10.249
From rstdly_15_s0
To core/decoded_rd_0_s0
Launch Clk clk_in[R]
Latch Clk clk_in[F]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
5.000 0.000 clk_in
5.000 0.000 tCL FF 1 clk_in_ibuf/I
5.000 0.000 tINS FF 3980 clk_in_ibuf/O
5.280 0.280 tNET FF 1 rstdly_15_s0/CLK
5.627 0.347 tC2Q FR 30 rstdly_15_s0/Q
5.927 0.300 tNET RR 1 core/n7234_s2/I3
6.137 0.210 tINS RR 2 core/n7234_s2/F
6.437 0.300 tNET RR 1 core/mem_xfer_s1/I1
6.850 0.413 tINS RR 42 core/mem_xfer_s1/F
7.150 0.300 tNET RR 1 core/mem_xfer_s0/I1
7.563 0.413 tINS RR 89 core/mem_xfer_s0/F
7.863 0.300 tNET RR 1 core/mem_rdata_latched_6_s3/I2
8.232 0.369 tINS RR 1 core/mem_rdata_latched_6_s3/F
8.532 0.300 tNET RR 1 core/mem_rdata_latched_6_s2/I1
8.945 0.413 tINS RR 3 core/mem_rdata_latched_6_s2/F
9.245 0.300 tNET RR 1 core/n5189_s5/I1
9.658 0.413 tINS RR 9 core/n5189_s5/F
9.958 0.300 tNET RR 1 core/n5644_s3/I2
10.327 0.369 tINS RR 5 core/n5644_s3/F
10.627 0.300 tNET RR 1 core/n5582_s4/I0
11.048 0.421 tINS RR 1 core/n5582_s4/F
11.348 0.300 tNET RR 1 core/n5582_s1/I0
11.769 0.421 tINS RR 1 core/n5582_s1/F
12.069 0.300 tNET RR 1 core/n5582_s0/I0
12.490 0.421 tINS RR 1 core/n5582_s0/F
12.790 0.300 tNET RR 1 core/decoded_rd_0_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_in
10.000 0.000 tCL RR 1 clk_in_ibuf/I
10.000 0.000 tINS RR 3980 clk_in_ibuf/O
10.300 0.300 tNET RR 1 core/decoded_rd_0_s0/CLK
10.249 -0.051 tSu 1 core/decoded_rd_0_s0
Path Statistics:
Clock Skew: 0.020
Setup Relationship: 5.000
Logic Level: 11
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.280, 100.000%
Arrival Data Path Delay: cell: 3.863, 51.438%; route: 3.300, 43.941%; tC2Q: 0.347, 4.621%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.280, 100.000%

Path 4

Path Summary:
Slack -2.541
Data Arrival Time 12.790
Data Required Time 10.249
From rstdly_15_s0
To core/decoded_rd_3_s0
Launch Clk clk_in[R]
Latch Clk clk_in[F]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
5.000 0.000 clk_in
5.000 0.000 tCL FF 1 clk_in_ibuf/I
5.000 0.000 tINS FF 3980 clk_in_ibuf/O
5.280 0.280 tNET FF 1 rstdly_15_s0/CLK
5.627 0.347 tC2Q FR 30 rstdly_15_s0/Q
5.927 0.300 tNET RR 1 core/n7234_s2/I3
6.137 0.210 tINS RR 2 core/n7234_s2/F
6.437 0.300 tNET RR 1 core/mem_xfer_s1/I1
6.850 0.413 tINS RR 42 core/mem_xfer_s1/F
7.150 0.300 tNET RR 1 core/mem_xfer_s0/I1
7.563 0.413 tINS RR 89 core/mem_xfer_s0/F
7.863 0.300 tNET RR 1 core/mem_rdata_latched_6_s3/I2
8.232 0.369 tINS RR 1 core/mem_rdata_latched_6_s3/F
8.532 0.300 tNET RR 1 core/mem_rdata_latched_6_s2/I1
8.945 0.413 tINS RR 3 core/mem_rdata_latched_6_s2/F
9.245 0.300 tNET RR 1 core/n5189_s5/I1
9.658 0.413 tINS RR 9 core/n5189_s5/F
9.958 0.300 tNET RR 1 core/n5644_s3/I2
10.327 0.369 tINS RR 5 core/n5644_s3/F
10.627 0.300 tNET RR 1 core/n5578_s2/I0
11.048 0.421 tINS RR 2 core/n5578_s2/F
11.348 0.300 tNET RR 1 core/n5578_s5/I0
11.769 0.421 tINS RR 2 core/n5578_s5/F
12.069 0.300 tNET RR 1 core/n5579_s0/I0
12.490 0.421 tINS RR 1 core/n5579_s0/F
12.790 0.300 tNET RR 1 core/decoded_rd_3_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_in
10.000 0.000 tCL RR 1 clk_in_ibuf/I
10.000 0.000 tINS RR 3980 clk_in_ibuf/O
10.300 0.300 tNET RR 1 core/decoded_rd_3_s0/CLK
10.249 -0.051 tSu 1 core/decoded_rd_3_s0
Path Statistics:
Clock Skew: 0.020
Setup Relationship: 5.000
Logic Level: 11
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.280, 100.000%
Arrival Data Path Delay: cell: 3.863, 51.438%; route: 3.300, 43.941%; tC2Q: 0.347, 4.621%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.280, 100.000%

Path 5

Path Summary:
Slack -2.541
Data Arrival Time 12.790
Data Required Time 10.249
From rstdly_15_s0
To core/decoded_rd_4_s0
Launch Clk clk_in[R]
Latch Clk clk_in[F]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
5.000 0.000 clk_in
5.000 0.000 tCL FF 1 clk_in_ibuf/I
5.000 0.000 tINS FF 3980 clk_in_ibuf/O
5.280 0.280 tNET FF 1 rstdly_15_s0/CLK
5.627 0.347 tC2Q FR 30 rstdly_15_s0/Q
5.927 0.300 tNET RR 1 core/n7234_s2/I3
6.137 0.210 tINS RR 2 core/n7234_s2/F
6.437 0.300 tNET RR 1 core/mem_xfer_s1/I1
6.850 0.413 tINS RR 42 core/mem_xfer_s1/F
7.150 0.300 tNET RR 1 core/mem_xfer_s0/I1
7.563 0.413 tINS RR 89 core/mem_xfer_s0/F
7.863 0.300 tNET RR 1 core/mem_rdata_latched_6_s3/I2
8.232 0.369 tINS RR 1 core/mem_rdata_latched_6_s3/F
8.532 0.300 tNET RR 1 core/mem_rdata_latched_6_s2/I1
8.945 0.413 tINS RR 3 core/mem_rdata_latched_6_s2/F
9.245 0.300 tNET RR 1 core/n5189_s5/I1
9.658 0.413 tINS RR 9 core/n5189_s5/F
9.958 0.300 tNET RR 1 core/n5644_s3/I2
10.327 0.369 tINS RR 5 core/n5644_s3/F
10.627 0.300 tNET RR 1 core/n5578_s2/I0
11.048 0.421 tINS RR 2 core/n5578_s2/F
11.348 0.300 tNET RR 1 core/n5578_s5/I0
11.769 0.421 tINS RR 2 core/n5578_s5/F
12.069 0.300 tNET RR 1 core/n5578_s0/I0
12.490 0.421 tINS RR 1 core/n5578_s0/F
12.790 0.300 tNET RR 1 core/decoded_rd_4_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_in
10.000 0.000 tCL RR 1 clk_in_ibuf/I
10.000 0.000 tINS RR 3980 clk_in_ibuf/O
10.300 0.300 tNET RR 1 core/decoded_rd_4_s0/CLK
10.249 -0.051 tSu 1 core/decoded_rd_4_s0
Path Statistics:
Clock Skew: 0.020
Setup Relationship: 5.000
Logic Level: 11
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.280, 100.000%
Arrival Data Path Delay: cell: 3.863, 51.438%; route: 3.300, 43.941%; tC2Q: 0.347, 4.621%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.280, 100.000%