Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\picorv32.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\picosoc.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\advspi.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\ahb_bus.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\picosoc_dtcm.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\picosoc_itcm.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wb_bus.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wb_brancher.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wbgpio.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wbi2c.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wbspi.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\wbuart.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\simpleuart.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GowinPicoRV32\Gowin_PicoRV32\dm.v
GowinSynthesis Constraints File ---
Tool Version V1.9.11.02 (64-bit)
Part Number GW2A-LV18PG256C8/I7
Device GW2A-18
Device Version C
Created Time Tue May 20 14:27:52 2025
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module Gowin_PicoRV32_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 123.676MB
Running netlist conversion:
    CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.101s, Peak memory usage = 123.676MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.781s, Elapsed time = 0h 0m 0.766s, Peak memory usage = 123.676MB
    Optimizing Phase 1: CPU time = 0h 0m 0.296s, Elapsed time = 0h 0m 0.304s, Peak memory usage = 123.676MB
    Optimizing Phase 2: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 123.676MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.546s, Elapsed time = 0h 0m 0.559s, Peak memory usage = 123.676MB
    Inferring Phase 1: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.149s, Peak memory usage = 123.676MB
    Inferring Phase 2: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.056s, Peak memory usage = 123.676MB
    Inferring Phase 3: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.033s, Peak memory usage = 123.676MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 123.676MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.281s, Elapsed time = 0h 0m 0.279s, Peak memory usage = 123.676MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.453s, Elapsed time = 0h 0m 0.449s, Peak memory usage = 123.676MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 28s, Elapsed time = 0h 0m 28s, Peak memory usage = 143.516MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.75s, Elapsed time = 0h 0m 0.865s, Peak memory usage = 143.516MB
Generate output files:
    CPU time = 0h 0m 0.671s, Elapsed time = 0h 0m 1s, Peak memory usage = 170.898MB
Total Time and Memory Usage CPU time = 0h 0m 35s, Elapsed time = 0h 0m 35s, Peak memory usage = 170.898MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 241
I/O Buf 239
    IBUF 84
    OBUF 147
    TBUF 2
    IOBUF 6
Register 4012
    DFF 215
    DFFE 1842
    DFFS 19
    DFFSE 79
    DFFR 170
    DFFRE 567
    DFFP 6
    DFFPE 11
    DFFC 163
    DFFCE 940
LUT 6269
    LUT2 523
    LUT3 2009
    LUT4 3737
ALU 592
    ALU 592
SSRAM 24
    RAM16SDP4 24
INV 24
    INV 24
DSP
    MULT36X36 1
BSRAM 32
    SDPB 32

Resource Utilization Summary

Resource Usage Utilization
Logic 7029(6293 LUT, 592 ALU, 24 RAM16) / 20736 34%
Register 4012 / 16173 25%
  --Register as Latch 0 / 16173 0%
  --Register as FF 4012 / 16173 25%
BSRAM 32 / 46 70%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 clk_in Base 10.000 100.000 0.000 5.000 clk_in_ibuf/I
2 jtag_TCK Base 10.000 100.000 0.000 5.000 jtag_TCK_ibuf/I
3 u_dualportspi/u_atcspi/u_spi_spiif/n316_3 Base 10.000 100.000 0.000 5.000 u_dualportspi/u_atcspi/u_spi_spiif/n316_s0/F

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk_in 100.000(MHz) 48.871(MHz) 11 TOP
2 jtag_TCK 100.000(MHz) 89.413(MHz) 6 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack -8.200
Data Arrival Time 18.525
Data Required Time 10.325
From core/mem_addr_27_s0
To core/mem_rdata_q_27_s0
Launch Clk clk_in[R]
Latch Clk clk_in[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_in
0.000 0.000 tCL RR 1 clk_in_ibuf/I
0.000 0.000 tINS RR 3915 clk_in_ibuf/O
0.360 0.360 tNET RR 1 core/mem_addr_27_s0/CLK
0.592 0.232 tC2Q RF 3 core/mem_addr_27_s0/Q
1.066 0.474 tNET FF 1 itcm_valid_s3/I1
1.621 0.555 tINS FF 6 itcm_valid_s3/F
2.095 0.474 tNET FF 1 itcm_valid_s4/I3
2.466 0.371 tINS FF 6 itcm_valid_s4/F
2.940 0.474 tNET FF 1 u_dm/u_dm2dtm_cdc_tx/vld_set_s4/I0
3.457 0.517 tINS FF 2 u_dm/u_dm2dtm_cdc_tx/vld_set_s4/F
3.931 0.474 tNET FF 1 u_dm/u_dm2dtm_cdc_tx/vld_set_s0/I0
4.448 0.517 tINS FF 41 u_dm/u_dm2dtm_cdc_tx/vld_set_s0/F
4.922 0.474 tNET FF 1 u_dm/ram_addr_2_s2/I3
5.293 0.371 tINS FF 70 u_dm/ram_addr_2_s2/F
5.767 0.474 tNET FF 1 u_dm/ram_addr_0_s0/I2
6.220 0.453 tINS FF 103 u_dm/ram_addr_0_s0/F
6.694 0.474 tNET FF 1 u_dm/u_s_debug_ram/ram_dout_Z_28_s4/I2
7.147 0.453 tINS FF 1 u_dm/u_s_debug_ram/ram_dout_Z_28_s4/F
7.621 0.474 tNET FF 1 u_dm/u_s_debug_ram/ram_dout_Z_28_s1/I0
7.724 0.103 tINS FF 1 u_dm/u_s_debug_ram/ram_dout_Z_28_s1/O
8.198 0.474 tNET FF 1 u_dm/u_s_debug_ram/ram_dout_Z_28_s/I1
8.301 0.103 tINS FF 2 u_dm/u_s_debug_ram/ram_dout_Z_28_s/O
8.775 0.474 tNET FF 1 mem_rdata_28_s3/I2
9.228 0.453 tINS FF 1 mem_rdata_28_s3/F
9.702 0.474 tNET FF 1 mem_rdata_28_s1/I0
10.219 0.517 tINS FF 1 mem_rdata_28_s1/F
10.693 0.474 tNET FF 1 mem_rdata_28_s0/I0
11.210 0.517 tINS FF 5 mem_rdata_28_s0/F
11.684 0.474 tNET FF 1 core/mem_rdata_latched_28_s0/I0
12.201 0.517 tINS FF 7 core/mem_rdata_latched_28_s0/F
12.675 0.474 tNET FF 1 core/mem_rdata_latched_12_s1/I3
13.046 0.371 tINS FF 44 core/mem_rdata_latched_12_s1/F
13.520 0.474 tNET FF 1 core/n2077_s12/I0
14.037 0.517 tINS FF 1 core/n2077_s12/F
14.511 0.474 tNET FF 1 core/n2077_s8/I1
15.066 0.555 tINS FF 2 core/n2077_s8/F
15.540 0.474 tNET FF 1 core/n2077_s4/I1
16.095 0.555 tINS FF 7 core/n2077_s4/F
16.569 0.474 tNET FF 1 core/n2079_s3/I1
17.124 0.555 tINS FF 1 core/n2079_s3/F
17.598 0.474 tNET FF 1 core/n2079_s0/I2
18.051 0.453 tINS FF 1 core/n2079_s0/F
18.525 0.474 tNET FF 1 core/mem_rdata_q_27_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_in
10.000 0.000 tCL RR 1 clk_in_ibuf/I
10.000 0.000 tINS RR 3915 clk_in_ibuf/O
10.360 0.360 tNET RR 1 core/mem_rdata_q_27_s0/CLK
10.325 -0.035 tSu 1 core/mem_rdata_q_27_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 18
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%
Arrival Data Path Delay: cell: 8.453, 46.535%; route: 9.480, 52.188%; tC2Q: 0.232, 1.277%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%

Path 2

Path Summary:
Slack -8.162
Data Arrival Time 18.487
Data Required Time 10.325
From core/mem_addr_27_s0
To core/mem_rdata_q_26_s0
Launch Clk clk_in[R]
Latch Clk clk_in[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_in
0.000 0.000 tCL RR 1 clk_in_ibuf/I
0.000 0.000 tINS RR 3915 clk_in_ibuf/O
0.360 0.360 tNET RR 1 core/mem_addr_27_s0/CLK
0.592 0.232 tC2Q RF 3 core/mem_addr_27_s0/Q
1.066 0.474 tNET FF 1 itcm_valid_s3/I1
1.621 0.555 tINS FF 6 itcm_valid_s3/F
2.095 0.474 tNET FF 1 itcm_valid_s4/I3
2.466 0.371 tINS FF 6 itcm_valid_s4/F
2.940 0.474 tNET FF 1 u_dm/u_dm2dtm_cdc_tx/vld_set_s4/I0
3.457 0.517 tINS FF 2 u_dm/u_dm2dtm_cdc_tx/vld_set_s4/F
3.931 0.474 tNET FF 1 u_dm/u_dm2dtm_cdc_tx/vld_set_s0/I0
4.448 0.517 tINS FF 41 u_dm/u_dm2dtm_cdc_tx/vld_set_s0/F
4.922 0.474 tNET FF 1 u_dm/ram_addr_2_s2/I3
5.293 0.371 tINS FF 70 u_dm/ram_addr_2_s2/F
5.767 0.474 tNET FF 1 u_dm/ram_addr_0_s0/I2
6.220 0.453 tINS FF 103 u_dm/ram_addr_0_s0/F
6.694 0.474 tNET FF 1 u_dm/u_s_debug_ram/ram_dout_Z_28_s4/I2
7.147 0.453 tINS FF 1 u_dm/u_s_debug_ram/ram_dout_Z_28_s4/F
7.621 0.474 tNET FF 1 u_dm/u_s_debug_ram/ram_dout_Z_28_s1/I0
7.724 0.103 tINS FF 1 u_dm/u_s_debug_ram/ram_dout_Z_28_s1/O
8.198 0.474 tNET FF 1 u_dm/u_s_debug_ram/ram_dout_Z_28_s/I1
8.301 0.103 tINS FF 2 u_dm/u_s_debug_ram/ram_dout_Z_28_s/O
8.775 0.474 tNET FF 1 mem_rdata_28_s3/I2
9.228 0.453 tINS FF 1 mem_rdata_28_s3/F
9.702 0.474 tNET FF 1 mem_rdata_28_s1/I0
10.219 0.517 tINS FF 1 mem_rdata_28_s1/F
10.693 0.474 tNET FF 1 mem_rdata_28_s0/I0
11.210 0.517 tINS FF 5 mem_rdata_28_s0/F
11.684 0.474 tNET FF 1 core/mem_rdata_latched_28_s0/I0
12.201 0.517 tINS FF 7 core/mem_rdata_latched_28_s0/F
12.675 0.474 tNET FF 1 core/mem_rdata_latched_12_s1/I3
13.046 0.371 tINS FF 44 core/mem_rdata_latched_12_s1/F
13.520 0.474 tNET FF 1 core/n2077_s12/I0
14.037 0.517 tINS FF 1 core/n2077_s12/F
14.511 0.474 tNET FF 1 core/n2077_s8/I1
15.066 0.555 tINS FF 2 core/n2077_s8/F
15.540 0.474 tNET FF 1 core/n2077_s4/I1
16.095 0.555 tINS FF 7 core/n2077_s4/F
16.569 0.474 tNET FF 1 core/n2080_s11/I0
17.086 0.517 tINS FF 1 core/n2080_s11/F
17.560 0.474 tNET FF 1 core/n2080_s0/I2
18.013 0.453 tINS FF 1 core/n2080_s0/F
18.487 0.474 tNET FF 1 core/mem_rdata_q_26_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_in
10.000 0.000 tCL RR 1 clk_in_ibuf/I
10.000 0.000 tINS RR 3915 clk_in_ibuf/O
10.360 0.360 tNET RR 1 core/mem_rdata_q_26_s0/CLK
10.325 -0.035 tSu 1 core/mem_rdata_q_26_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 18
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%
Arrival Data Path Delay: cell: 8.415, 46.422%; route: 9.480, 52.298%; tC2Q: 0.232, 1.280%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%

Path 3

Path Summary:
Slack -8.124
Data Arrival Time 18.449
Data Required Time 10.325
From core/mem_addr_27_s0
To core/mem_rdata_q_30_s0
Launch Clk clk_in[R]
Latch Clk clk_in[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_in
0.000 0.000 tCL RR 1 clk_in_ibuf/I
0.000 0.000 tINS RR 3915 clk_in_ibuf/O
0.360 0.360 tNET RR 1 core/mem_addr_27_s0/CLK
0.592 0.232 tC2Q RF 3 core/mem_addr_27_s0/Q
1.066 0.474 tNET FF 1 itcm_valid_s3/I1
1.621 0.555 tINS FF 6 itcm_valid_s3/F
2.095 0.474 tNET FF 1 itcm_valid_s4/I3
2.466 0.371 tINS FF 6 itcm_valid_s4/F
2.940 0.474 tNET FF 1 u_dm/u_dm2dtm_cdc_tx/vld_set_s4/I0
3.457 0.517 tINS FF 2 u_dm/u_dm2dtm_cdc_tx/vld_set_s4/F
3.931 0.474 tNET FF 1 u_dm/u_dm2dtm_cdc_tx/vld_set_s0/I0
4.448 0.517 tINS FF 41 u_dm/u_dm2dtm_cdc_tx/vld_set_s0/F
4.922 0.474 tNET FF 1 u_dm/ram_addr_2_s2/I3
5.293 0.371 tINS FF 70 u_dm/ram_addr_2_s2/F
5.767 0.474 tNET FF 1 u_dm/ram_addr_0_s0/I2
6.220 0.453 tINS FF 103 u_dm/ram_addr_0_s0/F
6.694 0.474 tNET FF 1 u_dm/u_s_debug_ram/ram_dout_Z_28_s4/I2
7.147 0.453 tINS FF 1 u_dm/u_s_debug_ram/ram_dout_Z_28_s4/F
7.621 0.474 tNET FF 1 u_dm/u_s_debug_ram/ram_dout_Z_28_s1/I0
7.724 0.103 tINS FF 1 u_dm/u_s_debug_ram/ram_dout_Z_28_s1/O
8.198 0.474 tNET FF 1 u_dm/u_s_debug_ram/ram_dout_Z_28_s/I1
8.301 0.103 tINS FF 2 u_dm/u_s_debug_ram/ram_dout_Z_28_s/O
8.775 0.474 tNET FF 1 mem_rdata_28_s3/I2
9.228 0.453 tINS FF 1 mem_rdata_28_s3/F
9.702 0.474 tNET FF 1 mem_rdata_28_s1/I0
10.219 0.517 tINS FF 1 mem_rdata_28_s1/F
10.693 0.474 tNET FF 1 mem_rdata_28_s0/I0
11.210 0.517 tINS FF 5 mem_rdata_28_s0/F
11.684 0.474 tNET FF 1 core/mem_rdata_latched_28_s0/I0
12.201 0.517 tINS FF 7 core/mem_rdata_latched_28_s0/F
12.675 0.474 tNET FF 1 core/mem_rdata_latched_12_s1/I3
13.046 0.371 tINS FF 44 core/mem_rdata_latched_12_s1/F
13.520 0.474 tNET FF 1 core/n2077_s12/I0
14.037 0.517 tINS FF 1 core/n2077_s12/F
14.511 0.474 tNET FF 1 core/n2077_s8/I1
15.066 0.555 tINS FF 2 core/n2077_s8/F
15.540 0.474 tNET FF 1 core/n2075_s5/I0
16.057 0.517 tINS FF 2 core/n2075_s5/F
16.531 0.474 tNET FF 1 core/n2075_s1/I2
16.984 0.453 tINS FF 2 core/n2075_s1/F
17.458 0.474 tNET FF 1 core/n2076_s0/I0
17.975 0.517 tINS FF 1 core/n2076_s0/F
18.449 0.474 tNET FF 1 core/mem_rdata_q_30_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_in
10.000 0.000 tCL RR 1 clk_in_ibuf/I
10.000 0.000 tINS RR 3915 clk_in_ibuf/O
10.360 0.360 tNET RR 1 core/mem_rdata_q_30_s0/CLK
10.325 -0.035 tSu 1 core/mem_rdata_q_30_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 18
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%
Arrival Data Path Delay: cell: 8.377, 46.310%; route: 9.480, 52.407%; tC2Q: 0.232, 1.283%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%

Path 4

Path Summary:
Slack -8.124
Data Arrival Time 18.449
Data Required Time 10.325
From core/mem_addr_27_s0
To core/mem_rdata_q_31_s0
Launch Clk clk_in[R]
Latch Clk clk_in[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_in
0.000 0.000 tCL RR 1 clk_in_ibuf/I
0.000 0.000 tINS RR 3915 clk_in_ibuf/O
0.360 0.360 tNET RR 1 core/mem_addr_27_s0/CLK
0.592 0.232 tC2Q RF 3 core/mem_addr_27_s0/Q
1.066 0.474 tNET FF 1 itcm_valid_s3/I1
1.621 0.555 tINS FF 6 itcm_valid_s3/F
2.095 0.474 tNET FF 1 itcm_valid_s4/I3
2.466 0.371 tINS FF 6 itcm_valid_s4/F
2.940 0.474 tNET FF 1 u_dm/u_dm2dtm_cdc_tx/vld_set_s4/I0
3.457 0.517 tINS FF 2 u_dm/u_dm2dtm_cdc_tx/vld_set_s4/F
3.931 0.474 tNET FF 1 u_dm/u_dm2dtm_cdc_tx/vld_set_s0/I0
4.448 0.517 tINS FF 41 u_dm/u_dm2dtm_cdc_tx/vld_set_s0/F
4.922 0.474 tNET FF 1 u_dm/ram_addr_2_s2/I3
5.293 0.371 tINS FF 70 u_dm/ram_addr_2_s2/F
5.767 0.474 tNET FF 1 u_dm/ram_addr_0_s0/I2
6.220 0.453 tINS FF 103 u_dm/ram_addr_0_s0/F
6.694 0.474 tNET FF 1 u_dm/u_s_debug_ram/ram_dout_Z_28_s4/I2
7.147 0.453 tINS FF 1 u_dm/u_s_debug_ram/ram_dout_Z_28_s4/F
7.621 0.474 tNET FF 1 u_dm/u_s_debug_ram/ram_dout_Z_28_s1/I0
7.724 0.103 tINS FF 1 u_dm/u_s_debug_ram/ram_dout_Z_28_s1/O
8.198 0.474 tNET FF 1 u_dm/u_s_debug_ram/ram_dout_Z_28_s/I1
8.301 0.103 tINS FF 2 u_dm/u_s_debug_ram/ram_dout_Z_28_s/O
8.775 0.474 tNET FF 1 mem_rdata_28_s3/I2
9.228 0.453 tINS FF 1 mem_rdata_28_s3/F
9.702 0.474 tNET FF 1 mem_rdata_28_s1/I0
10.219 0.517 tINS FF 1 mem_rdata_28_s1/F
10.693 0.474 tNET FF 1 mem_rdata_28_s0/I0
11.210 0.517 tINS FF 5 mem_rdata_28_s0/F
11.684 0.474 tNET FF 1 core/mem_rdata_latched_28_s0/I0
12.201 0.517 tINS FF 7 core/mem_rdata_latched_28_s0/F
12.675 0.474 tNET FF 1 core/mem_rdata_latched_12_s1/I3
13.046 0.371 tINS FF 44 core/mem_rdata_latched_12_s1/F
13.520 0.474 tNET FF 1 core/n2077_s12/I0
14.037 0.517 tINS FF 1 core/n2077_s12/F
14.511 0.474 tNET FF 1 core/n2077_s8/I1
15.066 0.555 tINS FF 2 core/n2077_s8/F
15.540 0.474 tNET FF 1 core/n2075_s5/I0
16.057 0.517 tINS FF 2 core/n2075_s5/F
16.531 0.474 tNET FF 1 core/n2075_s1/I2
16.984 0.453 tINS FF 2 core/n2075_s1/F
17.458 0.474 tNET FF 1 core/n2075_s0/I0
17.975 0.517 tINS FF 1 core/n2075_s0/F
18.449 0.474 tNET FF 1 core/mem_rdata_q_31_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_in
10.000 0.000 tCL RR 1 clk_in_ibuf/I
10.000 0.000 tINS RR 3915 clk_in_ibuf/O
10.360 0.360 tNET RR 1 core/mem_rdata_q_31_s0/CLK
10.325 -0.035 tSu 1 core/mem_rdata_q_31_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 18
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%
Arrival Data Path Delay: cell: 8.377, 46.310%; route: 9.480, 52.407%; tC2Q: 0.232, 1.283%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%

Path 5

Path Summary:
Slack -8.080
Data Arrival Time 18.405
Data Required Time 10.325
From core/mem_addr_27_s0
To core/mem_rdata_q_12_s0
Launch Clk clk_in[R]
Latch Clk clk_in[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_in
0.000 0.000 tCL RR 1 clk_in_ibuf/I
0.000 0.000 tINS RR 3915 clk_in_ibuf/O
0.360 0.360 tNET RR 1 core/mem_addr_27_s0/CLK
0.592 0.232 tC2Q RF 3 core/mem_addr_27_s0/Q
1.066 0.474 tNET FF 1 itcm_valid_s3/I1
1.621 0.555 tINS FF 6 itcm_valid_s3/F
2.095 0.474 tNET FF 1 itcm_valid_s4/I3
2.466 0.371 tINS FF 6 itcm_valid_s4/F
2.940 0.474 tNET FF 1 u_dm/u_dm2dtm_cdc_tx/vld_set_s4/I0
3.457 0.517 tINS FF 2 u_dm/u_dm2dtm_cdc_tx/vld_set_s4/F
3.931 0.474 tNET FF 1 u_dm/u_dm2dtm_cdc_tx/vld_set_s0/I0
4.448 0.517 tINS FF 41 u_dm/u_dm2dtm_cdc_tx/vld_set_s0/F
4.922 0.474 tNET FF 1 u_dm/ram_addr_2_s2/I3
5.293 0.371 tINS FF 70 u_dm/ram_addr_2_s2/F
5.767 0.474 tNET FF 1 u_dm/ram_addr_0_s0/I2
6.220 0.453 tINS FF 103 u_dm/ram_addr_0_s0/F
6.694 0.474 tNET FF 1 u_dm/u_s_debug_ram/ram_dout_Z_28_s4/I2
7.147 0.453 tINS FF 1 u_dm/u_s_debug_ram/ram_dout_Z_28_s4/F
7.621 0.474 tNET FF 1 u_dm/u_s_debug_ram/ram_dout_Z_28_s1/I0
7.724 0.103 tINS FF 1 u_dm/u_s_debug_ram/ram_dout_Z_28_s1/O
8.198 0.474 tNET FF 1 u_dm/u_s_debug_ram/ram_dout_Z_28_s/I1
8.301 0.103 tINS FF 2 u_dm/u_s_debug_ram/ram_dout_Z_28_s/O
8.775 0.474 tNET FF 1 mem_rdata_28_s3/I2
9.228 0.453 tINS FF 1 mem_rdata_28_s3/F
9.702 0.474 tNET FF 1 mem_rdata_28_s1/I0
10.219 0.517 tINS FF 1 mem_rdata_28_s1/F
10.693 0.474 tNET FF 1 mem_rdata_28_s0/I0
11.210 0.517 tINS FF 5 mem_rdata_28_s0/F
11.684 0.474 tNET FF 1 core/mem_rdata_latched_28_s0/I0
12.201 0.517 tINS FF 7 core/mem_rdata_latched_28_s0/F
12.675 0.474 tNET FF 1 core/mem_rdata_latched_12_s1/I3
13.046 0.371 tINS FF 44 core/mem_rdata_latched_12_s1/F
13.520 0.474 tNET FF 1 core/n2077_s12/I0
14.037 0.517 tINS FF 1 core/n2077_s12/F
14.511 0.474 tNET FF 1 core/n2077_s8/I1
15.066 0.555 tINS FF 2 core/n2077_s8/F
15.540 0.474 tNET FF 1 core/n2075_s5/I0
16.057 0.517 tINS FF 2 core/n2075_s5/F
16.531 0.474 tNET FF 1 core/n2094_s3/I1
17.086 0.555 tINS FF 1 core/n2094_s3/F
17.560 0.474 tNET FF 1 core/n2094_s0/I3
17.931 0.371 tINS FF 1 core/n2094_s0/F
18.405 0.474 tNET FF 1 core/mem_rdata_q_12_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_in
10.000 0.000 tCL RR 1 clk_in_ibuf/I
10.000 0.000 tINS RR 3915 clk_in_ibuf/O
10.360 0.360 tNET RR 1 core/mem_rdata_q_12_s0/CLK
10.325 -0.035 tSu 1 core/mem_rdata_q_12_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 18
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%
Arrival Data Path Delay: cell: 8.333, 46.179%; route: 9.480, 52.535%; tC2Q: 0.232, 1.286%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%