Power Messages

Report Title Power Analysis Report
Design File E:\IP_Release\QSGMII\1.1\ref_design\Gowin_QSGMII_IP_RefDesign\project\impl\gwsynthesis\fpga_project.vg
Physical Constraints File E:\IP_Release\QSGMII\1.1\ref_design\Gowin_QSGMII_IP_RefDesign\project\src\fpga_project.cst
Timing Constraints File E:\IP_Release\QSGMII\1.1\ref_design\Gowin_QSGMII_IP_RefDesign\project\src\fpga_project.sdc
Tool Version V1.9.10.03 (64-bit)
Part Number GW5AST-LV138FPG676AES
Device GW5AST-138
Device Version B
Created Time Sat Oct 12 09:56:42 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

Configure Information:

Grade Commercial
Process Typical
Ambient Temperature 25.000
Use Custom Theta JA false
Heat Sink None
Air Flow LFM_0
Use Custom Theta SA false
Board Thermal Model None
Use Custom Theta JB false
Related Vcd File
Related Saif File
Filter Glitches false
Default IO Toggle Rate 0.125
Default Remain Toggle Rate 0.125

Power Summary

Power Information:

Total Power (mW) 141.783
Quiescent Power (mW) 100.685
Dynamic Power (mW) 41.098

Thermal Information:

Junction Temperature 26.843
Theta JA 13.000
Max Allowed Ambient Temperature 83.157

Supply Information:

Voltage Source Voltage Dynamic Current(mA) Quiescent Current(mA) Power(mW)
VCC 0.900 19.908 80.009 89.926
VCCX 1.800 0.342 7.200 13.576
VCCIO33 3.300 0.346 3.017 11.098
VCC_LDO 1.200 17.853 4.800 27.184

Power Details

Power By Block Type:

Block Type Total Power(mW) Static Power(mW) Average Toggle Rate(millions of transitions/sec)
Logic 10.433 NA 13.248
IO 13.003 10.939 13.854
BSRAM 7.161 NA NA
PLL 21.424 NA NA

Power By Hierarchy:

Hierarchy Entity Total Power(mW) Block Dynamic Power(mW)
top 39.018 39.018(38.935)
top/gw_gao_inst_0/ 7.260 7.260(7.260)
top/gw_gao_inst_0/u_icon_top/ 0.002 0.002(0.000)
top/gw_gao_inst_0/u_la0_top/ 7.258 7.258(7.206)
top/gw_gao_inst_0/u_la0_top/u_ao_crc32/ 0.004 0.004(0.000)
top/gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/ 3.430 3.430(0.000)
top/gw_gao_inst_0/u_la0_top/u_ao_match_0/ 0.005 0.005(0.000)
top/gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/ 3.768 3.768(0.000)
top/sw1/ 0.002 0.002(0.000)
top/test[0].u_mac_rx_model/ 0.890 0.890(0.000)
top/test[0].u_mac_tx_model/ 0.626 0.626(0.000)
top/test[1].u_mac_rx_model/ 0.887 0.887(0.000)
top/test[1].u_mac_tx_model/ 0.623 0.623(0.000)
top/test[2].u_mac_rx_model/ 0.891 0.891(0.000)
top/test[2].u_mac_tx_model/ 0.624 0.624(0.000)
top/test[3].u_mac_rx_model/ 0.891 0.891(0.000)
top/test[3].u_mac_tx_model/ 0.623 0.623(0.000)
top/u_SerDes_Top/ 4.053 4.053(4.053)
top/u_SerDes_Top/QSGMII_Top_inst/ 4.053 4.053(4.053)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/ 4.053 4.053(3.975)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/ 0.992 0.992(0.975)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_ge_an/ 0.118 0.118(0.000)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_ge_rx/ 0.160 0.160(0.000)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_ge_sync/ 0.031 0.031(0.000)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_ge_tx/ 0.087 0.087(0.000)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_mac_rx_ctrl/ 0.249 0.249(0.036)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_mac_rx_ctrl/u_crc_chk/ 0.036 0.036(0.000)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_mac_tx_ctrl/ 0.331 0.331(0.063)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_mac_tx_ctrl/u_crc_gen/ 0.043 0.043(0.000)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_mac_tx_ctrl/u_lfsr/ 0.020 0.020(0.000)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/ 0.995 0.995(0.979)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_ge_an/ 0.118 0.118(0.000)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_ge_rx/ 0.160 0.160(0.000)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_ge_sync/ 0.031 0.031(0.000)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_ge_tx/ 0.087 0.087(0.000)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/ 0.250 0.250(0.037)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/u_crc_chk/ 0.037 0.037(0.000)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/ 0.333 0.333(0.065)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/u_crc_gen/ 0.044 0.044(0.000)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/u_lfsr/ 0.021 0.021(0.000)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/ 0.990 0.990(0.974)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_an/ 0.118 0.118(0.000)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_rx/ 0.160 0.160(0.000)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_sync/ 0.031 0.031(0.000)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_tx/ 0.087 0.087(0.000)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_rx_ctrl/ 0.250 0.250(0.036)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_rx_ctrl/u_crc_chk/ 0.036 0.036(0.000)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/ 0.329 0.329(0.064)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/u_crc_gen/ 0.042 0.042(0.000)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/u_lfsr/ 0.022 0.022(0.000)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/ 0.993 0.993(0.976)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_ge_an/ 0.118 0.118(0.000)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_ge_rx/ 0.160 0.160(0.000)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_ge_sync/ 0.031 0.031(0.000)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_ge_tx/ 0.087 0.087(0.000)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_rx_ctrl/ 0.250 0.250(0.036)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_rx_ctrl/u_crc_chk/ 0.036 0.036(0.000)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/ 0.331 0.331(0.063)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/u_crc_gen/ 0.043 0.043(0.000)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/u_lfsr/ 0.020 0.020(0.000)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_serdes_control/ 0.005 0.005(0.000)
top/u_Uart_to_Bus_Top/ 0.070 0.070(0.070)
top/u_Uart_to_Bus_Top/uart_bus_core/ 0.070 0.070(0.065)
top/u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/ 0.065 0.065(0.065)
top/u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/ 0.003 0.003(0.000)
top/u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_rx_md/ 0.031 0.031(0.031)
top/u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/ 0.028 0.028(0.022)
top/u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/ 0.022 0.022(0.000)
top/u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/ 0.002 0.002(0.000)
top/u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/ 0.031 0.031(0.031)
top/u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/ 0.028 0.028(0.023)
top/u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/ 0.023 0.023(0.000)
top/u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/ 0.003 0.003(0.000)
top/u_pll_uart/ 21.424 21.424(0.000)
top/u_sysreg/ 0.071 0.071(0.000)
top/uart1/ 0.002 0.002(0.000)

Power By Clock Domain:

Clock Domain Clock Frequency(Mhz) Total Dynamic Power(mW)
rx_mac_clk 125.000 12.242
clk_in 50.000 21.430
NO CLOCK DOMAIN 0.000 0.000
tx_mac_clk 125.000 4.232
clk_uart 10.000 0.111
tck_pad 20.000 1.019