Synthesis Messages

Report Title GowinSynthesis Report
Design File E:\IP_Release\QSGMII\1.1\ref_design\Gowin_QSGMII_IP_RefDesign\project\src\button.v
E:\IP_Release\QSGMII\1.1\ref_design\Gowin_QSGMII_IP_RefDesign\project\src\mac_rx_model.v
E:\IP_Release\QSGMII\1.1\ref_design\Gowin_QSGMII_IP_RefDesign\project\src\mac_tx_model.v
E:\IP_Release\QSGMII\1.1\ref_design\Gowin_QSGMII_IP_RefDesign\project\src\pll_uart\pll_uart.v
E:\IP_Release\QSGMII\1.1\ref_design\Gowin_QSGMII_IP_RefDesign\project\src\serdes\qsgmii\qsgmii.v
E:\IP_Release\QSGMII\1.1\ref_design\Gowin_QSGMII_IP_RefDesign\project\src\serdes\serdes.v
E:\IP_Release\QSGMII\1.1\ref_design\Gowin_QSGMII_IP_RefDesign\project\src\sysreg.v
E:\IP_Release\QSGMII\1.1\ref_design\Gowin_QSGMII_IP_RefDesign\project\src\top.v
E:\IP_Release\QSGMII\1.1\ref_design\Gowin_QSGMII_IP_RefDesign\project\src\uart_to_bus\uart_to_bus.v
D:\Gowin\Gowin_V1.9.10.03_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v
D:\Gowin\Gowin_V1.9.10.03_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v
D:\Gowin\Gowin_V1.9.10.03_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v
D:\Gowin\Gowin_V1.9.10.03_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v
D:\Gowin\Gowin_V1.9.10.03_x64\IDE\data\ipcores\GAO\GW_CON\gw_con_top_138.v
D:\Gowin\Gowin_V1.9.10.03_x64\IDE\data\ipcores\gw_jtag.v
E:\IP_Release\QSGMII\1.1\ref_design\Gowin_QSGMII_IP_RefDesign\project\impl\gwsynthesis\RTL_GAO\gw_gao_top.v
GowinSynthesis Constraints File ---
Tool Version V1.9.10.03 (64-bit)
Part Number GW5AST-LV138FPG676AES
Device GW5AST-138
Device Version B
Created Time Sat Oct 12 09:40:50 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module top
Synthesis Process Running parser:
    CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 1538.082MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 1538.082MB
    Optimizing Phase 1: CPU time = 0h 0m 0.734s, Elapsed time = 0h 0m 0.764s, Peak memory usage = 1538.082MB
    Optimizing Phase 2: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 1538.082MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.703s, Elapsed time = 0h 0m 0.703s, Peak memory usage = 1538.082MB
    Inferring Phase 1: CPU time = 0h 0m 0.375s, Elapsed time = 0h 0m 0.375s, Peak memory usage = 1538.082MB
    Inferring Phase 2: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.118s, Peak memory usage = 1538.082MB
    Inferring Phase 3: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.079s, Peak memory usage = 1538.082MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 1538.082MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.406s, Elapsed time = 0h 0m 0.394s, Peak memory usage = 1538.082MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.406s, Elapsed time = 0h 0m 0.41s, Peak memory usage = 1538.082MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 13s, Elapsed time = 0h 0m 13s, Peak memory usage = 1538.082MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 1538.082MB
Generate output files:
    CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 1538.082MB
Total Time and Memory Usage CPU time = 0h 0m 24s, Elapsed time = 0h 0m 24s, Peak memory usage = 1538.082MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 12
I/O Buf 12
    IBUF 6
    OBUF 6
Register 12335
    DFFRE 1017
    DFFPE 594
    DFFCE 10724
LUT 12163
    LUT2 1579
    LUT3 3513
    LUT4 7071
MUX 1
    MUX16 1
ALU 1312
    ALU 1312
INV 102
    INV 102
BSRAM 2
    SDPB 2
CLOCK 1
    PLL 1
Black Box 2
    GW_JTAG 1
GTR12_QUAD 1

Resource Utilization Summary

Resource Usage Utilization
Logic 13585(12273 LUT, 1312 ALU) / 138240 10%
Register 12335 / 139140 9%
  --Register as Latch 0 / 139140 0%
  --Register as FF 12335 / 139140 9%
BSRAM 2 / 340 <1%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 clk_in Base 20.000 50.0 0.000 10.000 clk_in_ibuf/I
2 u_pll_uart/PLL_inst/CLKOUT0.default_gen_clk Generated 100.000 10.0 0.000 50.000 clk_in_ibuf/I clk_in u_pll_uart/PLL_inst/CLKOUT0

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk_in 50.000(MHz) 361.011(MHz) 3 TOP
2 u_pll_uart/PLL_inst/CLKOUT0.default_gen_clk 10.000(MHz) 102.485(MHz) 10 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 16.455
Data Arrival Time 84.159
Data Required Time 100.614
From sw1/bout_s0
To u_sysreg/uart_rdata_2_s0
Launch Clk clk_in[R]
Latch Clk u_pll_uart/PLL_inst/CLKOUT0.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
80.000 0.000 clk_in
80.000 0.000 tCL RR 1 clk_in_ibuf/I
80.000 0.000 tINS RR 28 clk_in_ibuf/O
80.412 0.413 tNET RR 1 sw1/bout_s0/CLK
80.795 0.382 tC2Q RR 3 sw1/bout_s0/Q
81.207 0.413 tNET RR 1 u_sysreg/n1790_s58/I1
81.775 0.567 tINS RR 1 u_sysreg/n1790_s58/F
82.188 0.413 tNET RR 1 u_sysreg/n1790_s36/I1
82.755 0.567 tINS RR 1 u_sysreg/n1790_s36/F
83.167 0.413 tNET RR 1 u_sysreg/n1790_s35/I0
83.746 0.579 tINS RR 1 u_sysreg/n1790_s35/F
84.159 0.413 tNET RR 1 u_sysreg/uart_rdata_2_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
100.000 0.000 u_pll_uart/PLL_inst/CLKOUT0.default_gen_clk
100.300 0.300 tCL RR 2004 u_pll_uart/PLL_inst/CLKOUT0
100.713 0.413 tNET RR 1 u_sysreg/uart_rdata_2_s0/CLK
100.678 -0.035 tUnc u_sysreg/uart_rdata_2_s0
100.614 -0.064 tSu 1 u_sysreg/uart_rdata_2_s0
Path Statistics:
Clock Skew: 0.300
Setup Relationship: 20.000
Logic Level: 4
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 1.714, 45.746%; route: 1.650, 44.044%; tC2Q: 0.382, 10.210%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 2

Path Summary:
Slack 17.230
Data Arrival Time 3.119
Data Required Time 20.349
From uart1/temp_6_s0
To uart1/bout_s0
Launch Clk clk_in[R]
Latch Clk clk_in[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_in
0.000 0.000 tCL RR 1 clk_in_ibuf/I
0.000 0.000 tINS RR 28 clk_in_ibuf/O
0.413 0.413 tNET RR 1 uart1/temp_6_s0/CLK
0.795 0.382 tC2Q RR 2 uart1/temp_6_s0/Q
1.207 0.413 tNET RR 1 uart1/n5_s1/I0
1.786 0.579 tINS RR 1 uart1/n5_s1/F
2.199 0.413 tNET RR 1 uart1/n5_s0/I2
2.706 0.507 tINS RR 1 uart1/n5_s0/F
3.119 0.413 tNET RR 1 uart1/bout_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk_in
20.000 0.000 tCL RR 1 clk_in_ibuf/I
20.000 0.000 tINS RR 28 clk_in_ibuf/O
20.413 0.413 tNET RR 1 uart1/bout_s0/CLK
20.349 -0.064 tSu 1 uart1/bout_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 3
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 1.086, 40.139%; route: 1.238, 45.727%; tC2Q: 0.382, 14.134%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 3

Path Summary:
Slack 17.230
Data Arrival Time 3.119
Data Required Time 20.349
From sw1/temp_6_s0
To sw1/bout_s0
Launch Clk clk_in[R]
Latch Clk clk_in[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_in
0.000 0.000 tCL RR 1 clk_in_ibuf/I
0.000 0.000 tINS RR 28 clk_in_ibuf/O
0.413 0.413 tNET RR 1 sw1/temp_6_s0/CLK
0.795 0.382 tC2Q RR 2 sw1/temp_6_s0/Q
1.207 0.413 tNET RR 1 sw1/n5_s1/I0
1.786 0.579 tINS RR 1 sw1/n5_s1/F
2.199 0.413 tNET RR 1 sw1/n5_s0/I2
2.706 0.507 tINS RR 1 sw1/n5_s0/F
3.119 0.413 tNET RR 1 sw1/bout_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk_in
20.000 0.000 tCL RR 1 clk_in_ibuf/I
20.000 0.000 tINS RR 28 clk_in_ibuf/O
20.413 0.413 tNET RR 1 sw1/bout_s0/CLK
20.349 -0.064 tSu 1 sw1/bout_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 3
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 1.086, 40.139%; route: 1.238, 45.727%; tC2Q: 0.382, 14.134%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 4

Path Summary:
Slack 18.150
Data Arrival Time 2.199
Data Required Time 20.349
From u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_serdes_control/serdes_pll_ok_d3_s0
To u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_serdes_control/serdes_pcs_tx_rst_s0
Launch Clk clk_in[R]
Latch Clk clk_in[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_in
0.000 0.000 tCL RR 1 clk_in_ibuf/I
0.000 0.000 tINS RR 28 clk_in_ibuf/O
0.413 0.413 tNET RR 1 u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_serdes_control/serdes_pll_ok_d3_s0/CLK
0.795 0.382 tC2Q RR 2 u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_serdes_control/serdes_pll_ok_d3_s0/Q
1.207 0.413 tNET RR 1 u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_serdes_control/n97_s2/I0
1.786 0.579 tINS RR 1 u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_serdes_control/n97_s2/F
2.199 0.413 tNET RR 1 u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_serdes_control/serdes_pcs_tx_rst_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk_in
20.000 0.000 tCL RR 1 clk_in_ibuf/I
20.000 0.000 tINS RR 28 clk_in_ibuf/O
20.413 0.413 tNET RR 1 u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_serdes_control/serdes_pcs_tx_rst_s0/CLK
20.349 -0.064 tSu 1 u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_serdes_control/serdes_pcs_tx_rst_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 2
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 0.579, 32.400%; route: 0.825, 46.186%; tC2Q: 0.382, 21.414%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 5

Path Summary:
Slack 18.806
Data Arrival Time 1.508
Data Required Time 20.314
From u_sysreg/reg0x0030_0_s0
To uart1/temp_0_s0
Launch Clk u_pll_uart/PLL_inst/CLKOUT0.default_gen_clk[R]
Latch Clk clk_in[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 u_pll_uart/PLL_inst/CLKOUT0.default_gen_clk
0.300 0.300 tCL RR 2004 u_pll_uart/PLL_inst/CLKOUT0
0.713 0.413 tNET RR 1 u_sysreg/reg0x0030_0_s0/CLK
1.095 0.382 tC2Q RR 2 u_sysreg/reg0x0030_0_s0/Q
1.508 0.413 tNET RR 1 uart1/temp_0_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk_in
20.000 0.000 tCL RR 1 clk_in_ibuf/I
20.000 0.000 tINS RR 28 clk_in_ibuf/O
20.413 0.413 tNET RR 1 uart1/temp_0_s0/CLK
20.378 -0.035 tUnc uart1/temp_0_s0
20.314 -0.064 tSu 1 uart1/temp_0_s0
Path Statistics:
Clock Skew: -0.300
Setup Relationship: 20.000
Logic Level: 1
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 0.000, 0.000%; route: 0.413, 51.887%; tC2Q: 0.382, 48.113%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%