Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | D:\Gowin\Gowin_V1.9.10.03_x64\IDE\ipcore\SERDES_IP\IPlib\QSGMII\data\ge_pcs_qsgmii_wrap.v D:\Gowin\Gowin_V1.9.10.03_x64\IDE\ipcore\SERDES_IP\IPlib\QSGMII\data\ge_pcs_qsgmii.v |
GowinSynthesis Constraints File | --- |
Tool Version | V1.9.10.03 (64-bit) |
Part Number | GW5AST-LV138FPG676AES |
Device | GW5AST-138 |
Device Version | B |
Created Time | Sat Oct 12 09:40:04 2024 |
Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | QSGMII_Top |
Synthesis Process | Running parser: CPU time = 0h 0m 0.843s, Elapsed time = 0h 0m 0.847s, Peak memory usage = 133.379MB Running netlist conversion: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.151s, Peak memory usage = 133.379MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.734s, Elapsed time = 0h 0m 0.726s, Peak memory usage = 133.379MB Optimizing Phase 1: CPU time = 0h 0m 0.812s, Elapsed time = 0h 0m 0.812s, Peak memory usage = 133.379MB Optimizing Phase 2: CPU time = 0h 0m 0.921s, Elapsed time = 0h 0m 0.927s, Peak memory usage = 133.379MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.406s, Elapsed time = 0h 0m 0.409s, Peak memory usage = 133.379MB Inferring Phase 1: CPU time = 0h 0m 0.453s, Elapsed time = 0h 0m 0.472s, Peak memory usage = 133.379MB Inferring Phase 2: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.095s, Peak memory usage = 133.379MB Inferring Phase 3: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.04s, Peak memory usage = 133.379MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.703s, Elapsed time = 0h 0m 0.696s, Peak memory usage = 133.379MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.203s, Peak memory usage = 133.379MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.155s, Peak memory usage = 133.379MB Tech-Mapping Phase 3: CPU time = 0h 0m 13s, Elapsed time = 0h 0m 13s, Peak memory usage = 156.398MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.859s, Elapsed time = 0h 0m 0.882s, Peak memory usage = 156.398MB Generate output files: CPU time = 0h 0m 0.75s, Elapsed time = 0h 0m 0.773s, Peak memory usage = 200.926MB |
Total Time and Memory Usage | CPU time = 0h 0m 20s, Elapsed time = 0h 0m 20s, Peak memory usage = 200.926MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 1323 |
I/O Buf | 1309 |
    IBUF | 624 |
    OBUF | 685 |
Register | 6207 |
    DFFRE | 139 |
    DFFPE | 328 |
    DFFCE | 5740 |
LUT | 6482 |
    LUT2 | 898 |
    LUT3 | 1245 |
    LUT4 | 4339 |
ALU | 168 |
    ALU | 168 |
INV | 49 |
    INV | 49 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 6699(6531 LUT, 168 ALU) / 138240 | 5% |
Register | 6207 / 139140 | 5% |
  --Register as Latch | 0 / 139140 | 0% |
  --Register as FF | 6207 / 139140 | 5% |
BSRAM | 0 / 340 | 0% |
Timing
Clock Summary:
NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|---|
1 | serdes_pcs_rx_clk_i | Base | 10.000 | 100.0 | 0.000 | 5.000 | serdes_pcs_rx_clk_i_ibuf/I | ||
2 | serdes_pcs_tx_clk_i | Base | 10.000 | 100.0 | 0.000 | 5.000 | serdes_pcs_tx_clk_i_ibuf/I | ||
3 | clk_in_i | Base | 10.000 | 100.0 | 0.000 | 5.000 | clk_in_i_ibuf/I | ||
4 | miim_hs_clk_ch0_i | Base | 10.000 | 100.0 | 0.000 | 5.000 | miim_hs_clk_ch0_i_ibuf/I | ||
5 | miim_hs_clk_ch1_i | Base | 10.000 | 100.0 | 0.000 | 5.000 | miim_hs_clk_ch1_i_ibuf/I | ||
6 | miim_hs_clk_ch2_i | Base | 10.000 | 100.0 | 0.000 | 5.000 | miim_hs_clk_ch2_i_ibuf/I | ||
7 | miim_hs_clk_ch3_i | Base | 10.000 | 100.0 | 0.000 | 5.000 | miim_hs_clk_ch3_i_ibuf/I |
Max Frequency Summary:
NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | serdes_pcs_rx_clk_i | 100.000(MHz) | 172.973(MHz) | 6 | TOP |
2 | serdes_pcs_tx_clk_i | 100.000(MHz) | 163.066(MHz) | 7 | TOP |
3 | clk_in_i | 100.000(MHz) | 540.540(MHz) | 2 | TOP |
4 | miim_hs_clk_ch0_i | 100.000(MHz) | 179.897(MHz) | 6 | TOP |
5 | miim_hs_clk_ch1_i | 100.000(MHz) | 179.897(MHz) | 6 | TOP |
6 | miim_hs_clk_ch2_i | 100.000(MHz) | 179.897(MHz) | 6 | TOP |
7 | miim_hs_clk_ch3_i | 100.000(MHz) | 179.897(MHz) | 6 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | 3.867 |
Data Arrival Time | 6.481 |
Data Required Time | 10.349 |
From | u_ge_pcs_qsgmii/u_ge_pcs_port0/u_mac_tx_ctrl/back_cnt_0_s1 |
To | u_ge_pcs_qsgmii/u_ge_pcs_port0/u_mac_tx_ctrl/back_cnt_15_s1 |
Launch Clk | serdes_pcs_tx_clk_i[R] |
Latch Clk | serdes_pcs_tx_clk_i[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | serdes_pcs_tx_clk_i | |||
0.000 | 0.000 | tCL | RR | 1 | serdes_pcs_tx_clk_i_ibuf/I |
0.000 | 0.000 | tINS | RR | 2528 | serdes_pcs_tx_clk_i_ibuf/O |
0.413 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port0/u_mac_tx_ctrl/back_cnt_0_s1/CLK |
0.795 | 0.382 | tC2Q | RR | 5 | u_ge_pcs_qsgmii/u_ge_pcs_port0/u_mac_tx_ctrl/back_cnt_0_s1/Q |
1.207 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port0/u_mac_tx_ctrl/n1186_s2/I0 |
1.786 | 0.579 | tINS | RR | 4 | u_ge_pcs_qsgmii/u_ge_pcs_port0/u_mac_tx_ctrl/n1186_s2/F |
2.199 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port0/u_mac_tx_ctrl/n1183_s2/I3 |
2.487 | 0.289 | tINS | RR | 7 | u_ge_pcs_qsgmii/u_ge_pcs_port0/u_mac_tx_ctrl/n1183_s2/F |
2.900 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port0/u_mac_tx_ctrl/n1179_s2/I1 |
3.468 | 0.567 | tINS | RR | 2 | u_ge_pcs_qsgmii/u_ge_pcs_port0/u_mac_tx_ctrl/n1179_s2/F |
3.880 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port0/u_mac_tx_ctrl/n1176_s2/I3 |
4.169 | 0.289 | tINS | RR | 2 | u_ge_pcs_qsgmii/u_ge_pcs_port0/u_mac_tx_ctrl/n1176_s2/F |
4.581 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port0/u_mac_tx_ctrl/n1175_s2/I1 |
5.149 | 0.567 | tINS | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port0/u_mac_tx_ctrl/n1175_s2/F |
5.561 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port0/u_mac_tx_ctrl/n1175_s0/I2 |
6.069 | 0.507 | tINS | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port0/u_mac_tx_ctrl/n1175_s0/F |
6.481 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port0/u_mac_tx_ctrl/back_cnt_15_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | serdes_pcs_tx_clk_i | |||
10.000 | 0.000 | tCL | RR | 1 | serdes_pcs_tx_clk_i_ibuf/I |
10.000 | 0.000 | tINS | RR | 2528 | serdes_pcs_tx_clk_i_ibuf/O |
10.413 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port0/u_mac_tx_ctrl/back_cnt_15_s1/CLK |
10.349 | -0.064 | tSu | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port0/u_mac_tx_ctrl/back_cnt_15_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 7 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Arrival Data Path Delay: | cell: 2.799, 46.117%; route: 2.887, 47.580%; tC2Q: 0.382, 6.303% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 2
Path Summary:Slack | 3.960 |
Data Arrival Time | 6.141 |
Data Required Time | 10.101 |
From | u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/frm_byte_cnt_6_s3 |
To | u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_fcs_s6 |
Launch Clk | serdes_pcs_tx_clk_i[R] |
Latch Clk | serdes_pcs_tx_clk_i[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | serdes_pcs_tx_clk_i | |||
0.000 | 0.000 | tCL | RR | 1 | serdes_pcs_tx_clk_i_ibuf/I |
0.000 | 0.000 | tINS | RR | 2528 | serdes_pcs_tx_clk_i_ibuf/O |
0.413 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/frm_byte_cnt_6_s3/CLK |
0.795 | 0.382 | tC2Q | RR | 7 | u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/frm_byte_cnt_6_s3/Q |
1.207 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/late_col_s8/I0 |
1.786 | 0.579 | tINS | RR | 3 | u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/late_col_s8/F |
2.199 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/late_col_s5/I1 |
2.766 | 0.567 | tINS | RR | 4 | u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/late_col_s5/F |
3.179 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_ifg_s7/I0 |
3.758 | 0.579 | tINS | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_ifg_s7/F |
4.170 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_ifg_s6/I0 |
4.749 | 0.579 | tINS | RR | 2 | u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_ifg_s6/F |
5.161 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_ifg_s4/I1 |
5.729 | 0.567 | tINS | RR | 8 | u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_ifg_s4/F |
6.141 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_fcs_s6/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | serdes_pcs_tx_clk_i | |||
10.000 | 0.000 | tCL | RR | 1 | serdes_pcs_tx_clk_i_ibuf/I |
10.000 | 0.000 | tINS | RR | 2528 | serdes_pcs_tx_clk_i_ibuf/O |
10.413 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_fcs_s6/CLK |
10.101 | -0.311 | tSu | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_fcs_s6 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 6 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Arrival Data Path Delay: | cell: 2.871, 50.120%; route: 2.475, 43.203%; tC2Q: 0.382, 6.677% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 3
Path Summary:Slack | 3.960 |
Data Arrival Time | 6.141 |
Data Required Time | 10.101 |
From | u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/frm_byte_cnt_6_s3 |
To | u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_pad_s8 |
Launch Clk | serdes_pcs_tx_clk_i[R] |
Latch Clk | serdes_pcs_tx_clk_i[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | serdes_pcs_tx_clk_i | |||
0.000 | 0.000 | tCL | RR | 1 | serdes_pcs_tx_clk_i_ibuf/I |
0.000 | 0.000 | tINS | RR | 2528 | serdes_pcs_tx_clk_i_ibuf/O |
0.413 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/frm_byte_cnt_6_s3/CLK |
0.795 | 0.382 | tC2Q | RR | 7 | u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/frm_byte_cnt_6_s3/Q |
1.207 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/late_col_s8/I0 |
1.786 | 0.579 | tINS | RR | 3 | u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/late_col_s8/F |
2.199 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/late_col_s5/I1 |
2.766 | 0.567 | tINS | RR | 4 | u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/late_col_s5/F |
3.179 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_ifg_s7/I0 |
3.758 | 0.579 | tINS | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_ifg_s7/F |
4.170 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_ifg_s6/I0 |
4.749 | 0.579 | tINS | RR | 2 | u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_ifg_s6/F |
5.161 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_ifg_s4/I1 |
5.729 | 0.567 | tINS | RR | 8 | u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_ifg_s4/F |
6.141 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_pad_s8/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | serdes_pcs_tx_clk_i | |||
10.000 | 0.000 | tCL | RR | 1 | serdes_pcs_tx_clk_i_ibuf/I |
10.000 | 0.000 | tINS | RR | 2528 | serdes_pcs_tx_clk_i_ibuf/O |
10.413 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_pad_s8/CLK |
10.101 | -0.311 | tSu | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_pad_s8 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 6 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Arrival Data Path Delay: | cell: 2.871, 50.120%; route: 2.475, 43.203%; tC2Q: 0.382, 6.677% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 4
Path Summary:Slack | 3.960 |
Data Arrival Time | 6.141 |
Data Required Time | 10.101 |
From | u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/frm_byte_cnt_6_s3 |
To | u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_jam_s4 |
Launch Clk | serdes_pcs_tx_clk_i[R] |
Latch Clk | serdes_pcs_tx_clk_i[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | serdes_pcs_tx_clk_i | |||
0.000 | 0.000 | tCL | RR | 1 | serdes_pcs_tx_clk_i_ibuf/I |
0.000 | 0.000 | tINS | RR | 2528 | serdes_pcs_tx_clk_i_ibuf/O |
0.413 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/frm_byte_cnt_6_s3/CLK |
0.795 | 0.382 | tC2Q | RR | 7 | u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/frm_byte_cnt_6_s3/Q |
1.207 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/late_col_s8/I0 |
1.786 | 0.579 | tINS | RR | 3 | u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/late_col_s8/F |
2.199 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/late_col_s5/I1 |
2.766 | 0.567 | tINS | RR | 4 | u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/late_col_s5/F |
3.179 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_ifg_s7/I0 |
3.758 | 0.579 | tINS | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_ifg_s7/F |
4.170 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_ifg_s6/I0 |
4.749 | 0.579 | tINS | RR | 2 | u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_ifg_s6/F |
5.161 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_ifg_s4/I1 |
5.729 | 0.567 | tINS | RR | 8 | u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_ifg_s4/F |
6.141 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_jam_s4/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | serdes_pcs_tx_clk_i | |||
10.000 | 0.000 | tCL | RR | 1 | serdes_pcs_tx_clk_i_ibuf/I |
10.000 | 0.000 | tINS | RR | 2528 | serdes_pcs_tx_clk_i_ibuf/O |
10.413 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_jam_s4/CLK |
10.101 | -0.311 | tSu | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_jam_s4 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 6 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Arrival Data Path Delay: | cell: 2.871, 50.120%; route: 2.475, 43.203%; tC2Q: 0.382, 6.677% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 5
Path Summary:Slack | 3.960 |
Data Arrival Time | 6.141 |
Data Required Time | 10.101 |
From | u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/frm_byte_cnt_6_s3 |
To | u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_data_s12 |
Launch Clk | serdes_pcs_tx_clk_i[R] |
Latch Clk | serdes_pcs_tx_clk_i[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | serdes_pcs_tx_clk_i | |||
0.000 | 0.000 | tCL | RR | 1 | serdes_pcs_tx_clk_i_ibuf/I |
0.000 | 0.000 | tINS | RR | 2528 | serdes_pcs_tx_clk_i_ibuf/O |
0.413 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/frm_byte_cnt_6_s3/CLK |
0.795 | 0.382 | tC2Q | RR | 7 | u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/frm_byte_cnt_6_s3/Q |
1.207 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/late_col_s8/I0 |
1.786 | 0.579 | tINS | RR | 3 | u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/late_col_s8/F |
2.199 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/late_col_s5/I1 |
2.766 | 0.567 | tINS | RR | 4 | u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/late_col_s5/F |
3.179 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_ifg_s7/I0 |
3.758 | 0.579 | tINS | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_ifg_s7/F |
4.170 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_ifg_s6/I0 |
4.749 | 0.579 | tINS | RR | 2 | u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_ifg_s6/F |
5.161 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_ifg_s4/I1 |
5.729 | 0.567 | tINS | RR | 8 | u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_ifg_s4/F |
6.141 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_data_s12/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | serdes_pcs_tx_clk_i | |||
10.000 | 0.000 | tCL | RR | 1 | serdes_pcs_tx_clk_i_ibuf/I |
10.000 | 0.000 | tINS | RR | 2528 | serdes_pcs_tx_clk_i_ibuf/O |
10.413 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_data_s12/CLK |
10.101 | -0.311 | tSu | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_data_s12 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 6 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Arrival Data Path Delay: | cell: 2.871, 50.120%; route: 2.475, 43.203%; tC2Q: 0.382, 6.677% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |