Timing Messages

Report Title Timing Analysis Report
Design File E:\IP_Release\QSGMII\1.1\ref_design\Gowin_QSGMII_IP_RefDesign\project\impl\gwsynthesis\fpga_project.vg
Physical Constraints File E:\IP_Release\QSGMII\1.1\ref_design\Gowin_QSGMII_IP_RefDesign\project\src\fpga_project.cst
Timing Constraint File E:\IP_Release\QSGMII\1.1\ref_design\Gowin_QSGMII_IP_RefDesign\project\src\fpga_project.sdc
Tool Version V1.9.10.03 (64-bit)
Part Number GW5AST-LV138FPG676AES
Device GW5AST-138
Device Version B
Created Time Sat Oct 12 09:56:43 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model Slow 0.855V 0C ES
Hold Delay Model Fast 0.945V 85C ES
Numbers of Paths Analyzed 34842
Numbers of Endpoints Analyzed 37808
Numbers of Falling Endpoints 3
Numbers of Setup Violated Endpoints 0
Numbers of Hold Violated Endpoints 0

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Objects
1 tck_pad Base 50.000 20.000 0.000 25.000 gw_gao_inst_0/tck_ibuf/I
2 clk_in Base 20.000 50.000 0.000 10.000 clk_in_ibuf/I
3 tx_mac_clk Base 8.000 125.000 0.000 4.000 tx_mac_clk[3]
4 rx_mac_clk Base 8.000 125.000 0.000 4.000 rx_mac_clk[3]
5 clk_uart Generated 100.000 10.000 0.000 50.000 clk_in_ibuf/I clk_in u_pll_uart/PLL_inst/CLKOUT0

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 tck_pad 20.000(MHz) 134.918(MHz) 6 TOP
2 tx_mac_clk 125.000(MHz) 125.029(MHz) 5 TOP
3 rx_mac_clk 125.000(MHz) 129.607(MHz) 4 TOP
4 clk_uart 10.000(MHz) 50.837(MHz) 10 TOP

No timing paths to get frequency of clk_in!

Total Negative Slack Summary:

Clock Name Analysis Type Endpoints TNS Number of Endpoints
tck_pad Setup 0.000 0
tck_pad Hold 0.000 0
clk_in Setup 0.000 0
clk_in Hold 0.000 0
tx_mac_clk Setup 0.000 0
tx_mac_clk Hold 0.000 0
rx_mac_clk Setup 0.000 0
rx_mac_clk Hold 0.000 0
clk_uart Setup 0.000 0
clk_uart Hold 0.000 0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.002 u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/frm_byte_cnt_0_s3/Q u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_preamble_s14/CE tx_mac_clk:[R] tx_mac_clk:[R] 8.000 -0.027 7.714
2 0.006 u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_ge_tx/xmitCHANGE_to_config_s1/Q u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_ge_tx/encode_txd_6_s1/D tx_mac_clk:[R] tx_mac_clk:[R] 8.000 -0.062 7.993
3 0.052 u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/clk_ena_s0/Q u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_pause_s12/CE tx_mac_clk:[R] tx_mac_clk:[R] 8.000 -0.071 7.707
4 0.057 u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/clk_ena_s0/Q u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_data_s12/CE tx_mac_clk:[R] tx_mac_clk:[R] 8.000 -0.016 7.648
5 0.101 u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/tx_mac_ready_o_s0/Q test[2].u_mac_tx_model/tx_mac_data_6_s1/CE tx_mac_clk:[R] tx_mac_clk:[R] 8.000 -0.009 7.598
6 0.189 u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_tx/c_state_3_s0/Q u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_tx/encode_txd_2_s1/D tx_mac_clk:[R] tx_mac_clk:[R] 8.000 0.013 7.734
7 0.201 u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/frm_byte_cnt_0_s3/Q u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_pause_s12/CE tx_mac_clk:[R] tx_mac_clk:[R] 8.000 -0.018 7.505
8 0.227 u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_tx/c_state_3_s0/Q u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_tx/encode_txd_4_s1/D tx_mac_clk:[R] tx_mac_clk:[R] 8.000 0.009 7.700
9 0.235 u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_mac_tx_ctrl/tx_mac_ready_o_s0/Q test[0].u_mac_tx_model/tx_mac_data_7_s1/CE tx_mac_clk:[R] tx_mac_clk:[R] 8.000 -0.041 7.495
10 0.262 u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/back_cnt_1_s1/Q u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/back_cnt_15_s1/CE tx_mac_clk:[R] tx_mac_clk:[R] 8.000 -0.010 7.437
11 0.266 u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/clk_ena_s0/Q u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_fcs_s6/CE tx_mac_clk:[R] tx_mac_clk:[R] 8.000 -0.014 7.436
12 0.266 u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/clk_ena_s0/Q u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_pad_s8/CE tx_mac_clk:[R] tx_mac_clk:[R] 8.000 -0.014 7.436
13 0.266 u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/clk_ena_s0/Q u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_jam_s4/CE tx_mac_clk:[R] tx_mac_clk:[R] 8.000 -0.014 7.436
14 0.275 u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/clk_ena_s0/Q u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_preamble_s14/CE tx_mac_clk:[R] tx_mac_clk:[R] 8.000 -0.025 7.439
15 0.279 u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_ge_tx/c_state_2_s0/Q u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_ge_tx/encode_txd_7_s2/D tx_mac_clk:[R] tx_mac_clk:[R] 8.000 -0.094 7.587
16 0.284 u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_ge_rx/rudi_1_s3/Q u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_ge_an/mr_lp_adv_ability_10_s2/CE rx_mac_clk:[R] rx_mac_clk:[R] 8.000 -0.008 7.413
17 0.284 u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_ge_rx/rudi_1_s3/Q u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_ge_an/mr_lp_adv_ability_12_s2/CE rx_mac_clk:[R] rx_mac_clk:[R] 8.000 -0.008 7.413
18 0.296 u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_an/mr_an_enable_d3_s0/Q u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_an/link_timer_cnt_20_s1/CE rx_mac_clk:[R] rx_mac_clk:[R] 8.000 0.051 7.343
19 0.298 u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/frm_byte_cnt_0_s3/Q u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_idle_s16/CE tx_mac_clk:[R] tx_mac_clk:[R] 8.000 0.007 7.384
20 0.307 u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/frm_byte_cnt_0_s3/Q u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_jam_s4/CE tx_mac_clk:[R] tx_mac_clk:[R] 8.000 -0.002 7.384
21 0.401 u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/frm_byte_cnt_0_s3/Q u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_fcs_s6/CE tx_mac_clk:[R] tx_mac_clk:[R] 8.000 0.038 7.250
22 0.401 u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/frm_byte_cnt_0_s3/Q u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_pad_s8/CE tx_mac_clk:[R] tx_mac_clk:[R] 8.000 0.038 7.250
23 0.424 u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_tx/encoder_tx_even_s0/Q u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_tx/encode_k_s2/D tx_mac_clk:[R] tx_mac_clk:[R] 8.000 0.026 7.323
24 0.437 u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_mac_tx_ctrl/tx_mac_ready_o_s0/Q test[0].u_mac_tx_model/tx_mac_data_1_s1/CE tx_mac_clk:[R] tx_mac_clk:[R] 8.000 -0.034 7.286
25 0.452 u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_tx/encoder_tx_even_s0/Q u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_tx/encode_txd_1_s1/D tx_mac_clk:[R] tx_mac_clk:[R] 8.000 0.026 7.294

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.229 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_0_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[0] rx_mac_clk:[R] rx_mac_clk:[R] 0.000 0.021 0.245
2 0.275 test[3].u_mac_rx_model/rx_cnt_30_s1/Q test[3].u_mac_rx_model/rx_cnt_30_s1/D rx_mac_clk:[R] rx_mac_clk:[R] 0.000 0.000 0.300
3 0.275 test[3].u_mac_rx_model/rx_data_cnt_pause_0_s1/Q test[3].u_mac_rx_model/rx_data_cnt_pause_0_s1/D rx_mac_clk:[R] rx_mac_clk:[R] 0.000 0.000 0.300
4 0.275 test[3].u_mac_rx_model/rx_data_cnt_pause_15_s1/Q test[3].u_mac_rx_model/rx_data_cnt_pause_15_s1/D rx_mac_clk:[R] rx_mac_clk:[R] 0.000 0.000 0.300
5 0.275 test[3].u_mac_rx_model/shift_reg_pause_1_s1/Q test[3].u_mac_rx_model/shift_reg_pause_1_s1/D rx_mac_clk:[R] rx_mac_clk:[R] 0.000 0.000 0.300
6 0.275 test[3].u_mac_rx_model/shift_reg_pause_5_s1/Q test[3].u_mac_rx_model/shift_reg_pause_5_s1/D rx_mac_clk:[R] rx_mac_clk:[R] 0.000 0.000 0.300
7 0.275 test[3].u_mac_rx_model/pause_address_21_s1/Q test[3].u_mac_rx_model/pause_address_21_s1/D rx_mac_clk:[R] rx_mac_clk:[R] 0.000 0.000 0.300
8 0.275 test[3].u_mac_rx_model/pause_address_47_s1/Q test[3].u_mac_rx_model/pause_address_47_s1/D rx_mac_clk:[R] rx_mac_clk:[R] 0.000 0.000 0.300
9 0.275 test[3].u_mac_rx_model/pause_value_10_s1/Q test[3].u_mac_rx_model/pause_value_10_s1/D rx_mac_clk:[R] rx_mac_clk:[R] 0.000 0.000 0.300
10 0.275 test[3].u_mac_rx_model/shift_reg_4_s1/Q test[3].u_mac_rx_model/shift_reg_4_s1/D rx_mac_clk:[R] rx_mac_clk:[R] 0.000 0.000 0.300
11 0.275 test[3].u_mac_rx_model/shift_reg_7_s1/Q test[3].u_mac_rx_model/shift_reg_7_s1/D rx_mac_clk:[R] rx_mac_clk:[R] 0.000 0.000 0.300
12 0.275 test[3].u_mac_rx_model/shift_reg_8_s1/Q test[3].u_mac_rx_model/shift_reg_8_s1/D rx_mac_clk:[R] rx_mac_clk:[R] 0.000 0.000 0.300
13 0.275 test[3].u_mac_rx_model/shift_reg_10_s1/Q test[3].u_mac_rx_model/shift_reg_10_s1/D rx_mac_clk:[R] rx_mac_clk:[R] 0.000 0.000 0.300
14 0.275 test[3].u_mac_rx_model/shift_reg_13_s1/Q test[3].u_mac_rx_model/shift_reg_13_s1/D rx_mac_clk:[R] rx_mac_clk:[R] 0.000 0.000 0.300
15 0.275 test[3].u_mac_rx_model/shift_reg_20_s1/Q test[3].u_mac_rx_model/shift_reg_20_s1/D rx_mac_clk:[R] rx_mac_clk:[R] 0.000 0.000 0.300
16 0.275 test[3].u_mac_rx_model/shift_reg_21_s1/Q test[3].u_mac_rx_model/shift_reg_21_s1/D rx_mac_clk:[R] rx_mac_clk:[R] 0.000 0.000 0.300
17 0.275 test[3].u_mac_rx_model/shift_reg_25_s1/Q test[3].u_mac_rx_model/shift_reg_25_s1/D rx_mac_clk:[R] rx_mac_clk:[R] 0.000 0.000 0.300
18 0.275 test[3].u_mac_rx_model/shift_reg_33_s1/Q test[3].u_mac_rx_model/shift_reg_33_s1/D rx_mac_clk:[R] rx_mac_clk:[R] 0.000 0.000 0.300
19 0.275 test[3].u_mac_rx_model/shift_reg_39_s1/Q test[3].u_mac_rx_model/shift_reg_39_s1/D rx_mac_clk:[R] rx_mac_clk:[R] 0.000 0.000 0.300
20 0.275 test[3].u_mac_rx_model/shift_reg_40_s1/Q test[3].u_mac_rx_model/shift_reg_40_s1/D rx_mac_clk:[R] rx_mac_clk:[R] 0.000 0.000 0.300
21 0.275 test[3].u_mac_rx_model/shift_reg_45_s1/Q test[3].u_mac_rx_model/shift_reg_45_s1/D rx_mac_clk:[R] rx_mac_clk:[R] 0.000 0.000 0.300
22 0.275 test[3].u_mac_rx_model/shift_reg_46_s1/Q test[3].u_mac_rx_model/shift_reg_46_s1/D rx_mac_clk:[R] rx_mac_clk:[R] 0.000 0.000 0.300
23 0.275 test[3].u_mac_rx_model/shift_reg_49_s1/Q test[3].u_mac_rx_model/shift_reg_49_s1/D rx_mac_clk:[R] rx_mac_clk:[R] 0.000 0.000 0.300
24 0.275 test[3].u_mac_rx_model/shift_reg_51_s1/Q test[3].u_mac_rx_model/shift_reg_51_s1/D rx_mac_clk:[R] rx_mac_clk:[R] 0.000 0.000 0.300
25 0.275 test[3].u_mac_rx_model/shift_reg_57_s1/Q test[3].u_mac_rx_model/shift_reg_57_s1/D rx_mac_clk:[R] rx_mac_clk:[R] 0.000 0.000 0.300

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.117 rx_mac_rst_n_3_s0/Q test[3].u_mac_rx_model/rx_cnt_0_s3/CLEAR rx_mac_clk:[R] rx_mac_clk:[R] 8.000 0.094 7.441
2 0.117 rx_mac_rst_n_3_s0/Q test[3].u_mac_rx_model/rx_cnt_1_s3/CLEAR rx_mac_clk:[R] rx_mac_clk:[R] 8.000 0.094 7.441
3 0.117 rx_mac_rst_n_3_s0/Q test[3].u_mac_rx_model/rx_cnt_3_s1/CLEAR rx_mac_clk:[R] rx_mac_clk:[R] 8.000 0.094 7.441
4 0.117 rx_mac_rst_n_3_s0/Q test[3].u_mac_rx_model/rx_cnt_9_s1/CLEAR rx_mac_clk:[R] rx_mac_clk:[R] 8.000 0.094 7.441
5 0.339 rx_mac_rst_n_3_s0/Q test[3].u_mac_rx_model/rx_cnt_10_s3/CLEAR rx_mac_clk:[R] rx_mac_clk:[R] 8.000 0.091 7.223
6 0.339 rx_mac_rst_n_3_s0/Q test[3].u_mac_rx_model/rx_cnt_14_s1/CLEAR rx_mac_clk:[R] rx_mac_clk:[R] 8.000 0.091 7.223
7 0.339 rx_mac_rst_n_3_s0/Q test[3].u_mac_rx_model/rx_cnt_15_s1/CLEAR rx_mac_clk:[R] rx_mac_clk:[R] 8.000 0.091 7.223
8 0.339 rx_mac_rst_n_3_s0/Q test[3].u_mac_rx_model/rx_cnt_16_s1/CLEAR rx_mac_clk:[R] rx_mac_clk:[R] 8.000 0.091 7.223
9 0.341 rx_mac_rst_n_3_s0/Q test[3].u_mac_rx_model/rx_cnt_13_s3/CLEAR rx_mac_clk:[R] rx_mac_clk:[R] 8.000 0.089 7.223
10 0.341 rx_mac_rst_n_3_s0/Q test[3].u_mac_rx_model/rx_cnt_29_s3/CLEAR rx_mac_clk:[R] rx_mac_clk:[R] 8.000 0.089 7.223
11 0.341 rx_mac_rst_n_3_s0/Q test[3].u_mac_rx_model/rx_cnt_30_s1/CLEAR rx_mac_clk:[R] rx_mac_clk:[R] 8.000 0.089 7.223
12 0.341 rx_mac_rst_n_3_s0/Q test[3].u_mac_rx_model/data_length_0_s1/PRESET rx_mac_clk:[R] rx_mac_clk:[R] 8.000 0.089 7.223
13 0.382 rx_mac_rst_n_3_s0/Q test[3].u_mac_rx_model/rx_cnt_11_s1/CLEAR rx_mac_clk:[R] rx_mac_clk:[R] 8.000 0.082 7.188
14 0.382 rx_mac_rst_n_3_s0/Q test[3].u_mac_rx_model/rx_cnt_12_s1/CLEAR rx_mac_clk:[R] rx_mac_clk:[R] 8.000 0.082 7.188
15 0.382 rx_mac_rst_n_3_s0/Q test[3].u_mac_rx_model/rx_cnt_27_s1/CLEAR rx_mac_clk:[R] rx_mac_clk:[R] 8.000 0.082 7.188
16 0.385 rx_mac_rst_n_3_s0/Q test[3].u_mac_rx_model/rx_cnt_31_s4/CLEAR rx_mac_clk:[R] rx_mac_clk:[R] 8.000 0.079 7.188
17 0.385 rx_mac_rst_n_3_s0/Q test[3].u_mac_rx_model/rx_cnt_28_s1/CLEAR rx_mac_clk:[R] rx_mac_clk:[R] 8.000 0.079 7.188
18 0.389 rx_mac_rst_n_3_s0/Q test[3].u_mac_rx_model/data_length_1_s1/PRESET rx_mac_clk:[R] rx_mac_clk:[R] 8.000 0.074 7.189
19 0.389 rx_mac_rst_n_3_s0/Q test[3].u_mac_rx_model/data_length_13_s1/CLEAR rx_mac_clk:[R] rx_mac_clk:[R] 8.000 0.074 7.189
20 0.389 rx_mac_rst_n_3_s0/Q test[3].u_mac_rx_model/data_length_14_s1/CLEAR rx_mac_clk:[R] rx_mac_clk:[R] 8.000 0.074 7.189
21 0.389 rx_mac_rst_n_3_s0/Q test[3].u_mac_rx_model/data_length_15_s1/CLEAR rx_mac_clk:[R] rx_mac_clk:[R] 8.000 0.074 7.189
22 0.389 rx_mac_rst_n_3_s0/Q test[3].u_mac_rx_model/data_length_next_rea_1_s1/CLEAR rx_mac_clk:[R] rx_mac_clk:[R] 8.000 0.074 7.189
23 0.441 rx_mac_rst_n_3_s0/Q test[3].u_mac_rx_model/rx_cnt_17_s1/CLEAR rx_mac_clk:[R] rx_mac_clk:[R] 8.000 0.070 7.141
24 0.441 rx_mac_rst_n_3_s0/Q test[3].u_mac_rx_model/rx_cnt_23_s1/CLEAR rx_mac_clk:[R] rx_mac_clk:[R] 8.000 0.070 7.141
25 0.493 rx_mac_rst_n_3_s0/Q test[3].u_mac_rx_model/rx_cnt_7_s3/CLEAR rx_mac_clk:[R] rx_mac_clk:[R] 8.000 0.084 7.075

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.376 tx_mac_rst_n_2_s0/Q test[2].u_mac_tx_model/frm_length_last_0_s0/CLEAR tx_mac_clk:[R] tx_mac_clk:[R] 0.000 0.000 0.323
2 0.376 tx_mac_rst_n_2_s0/Q test[2].u_mac_tx_model/frm_length_0_s0/CLEAR tx_mac_clk:[R] tx_mac_clk:[R] 0.000 0.000 0.323
3 0.400 tx_mac_rst_n_2_s0/Q test[2].u_mac_tx_model/tx_data_cnt_10_s1/CLEAR tx_mac_clk:[R] tx_mac_clk:[R] 0.000 -0.004 0.351
4 0.404 tx_mac_rst_n_2_s0/Q test[2].u_mac_tx_model/tx_data_cnt_11_s1/CLEAR tx_mac_clk:[R] tx_mac_clk:[R] 0.000 0.000 0.351
5 0.503 tx_mac_rst_n_2_s0/Q test[2].u_mac_tx_model/data_start_byte_1_s0/PRESET tx_mac_clk:[R] tx_mac_clk:[R] 0.000 -0.009 0.459
6 0.503 tx_mac_rst_n_2_s0/Q test[2].u_mac_tx_model/data_start_byte_2_s0/CLEAR tx_mac_clk:[R] tx_mac_clk:[R] 0.000 -0.009 0.459
7 0.503 tx_mac_rst_n_2_s0/Q test[2].u_mac_tx_model/data_start_byte_3_s0/PRESET tx_mac_clk:[R] tx_mac_clk:[R] 0.000 -0.009 0.459
8 0.503 tx_mac_rst_n_2_s0/Q test[2].u_mac_tx_model/data_start_byte_4_s0/CLEAR tx_mac_clk:[R] tx_mac_clk:[R] 0.000 -0.009 0.459
9 0.503 tx_mac_rst_n_2_s0/Q test[2].u_mac_tx_model/data_start_byte_5_s0/PRESET tx_mac_clk:[R] tx_mac_clk:[R] 0.000 -0.009 0.459
10 0.503 tx_mac_rst_n_2_s0/Q test[2].u_mac_tx_model/data_start_byte_6_s0/CLEAR tx_mac_clk:[R] tx_mac_clk:[R] 0.000 -0.009 0.459
11 0.504 tx_mac_rst_n_2_s0/Q test[2].u_mac_tx_model/tx_data_cnt_12_s1/CLEAR tx_mac_clk:[R] tx_mac_clk:[R] 0.000 -0.008 0.459
12 0.504 tx_mac_rst_n_2_s0/Q test[2].u_mac_tx_model/tx_data_cnt_13_s1/CLEAR tx_mac_clk:[R] tx_mac_clk:[R] 0.000 -0.008 0.459
13 0.504 tx_mac_rst_n_2_s0/Q test[2].u_mac_tx_model/tx_data_cnt_14_s1/CLEAR tx_mac_clk:[R] tx_mac_clk:[R] 0.000 -0.008 0.459
14 0.504 tx_mac_rst_n_2_s0/Q test[2].u_mac_tx_model/tx_data_cnt_15_s1/CLEAR tx_mac_clk:[R] tx_mac_clk:[R] 0.000 -0.008 0.459
15 0.514 tx_mac_rst_n_2_s0/Q test[2].u_mac_tx_model/shift_reg_92_s1/CLEAR tx_mac_clk:[R] tx_mac_clk:[R] 0.000 0.000 0.461
16 0.514 tx_mac_rst_n_2_s0/Q test[2].u_mac_tx_model/shift_reg_93_s1/CLEAR tx_mac_clk:[R] tx_mac_clk:[R] 0.000 0.000 0.461
17 0.514 tx_mac_rst_n_2_s0/Q test[2].u_mac_tx_model/shift_reg_94_s1/CLEAR tx_mac_clk:[R] tx_mac_clk:[R] 0.000 0.000 0.461
18 0.514 tx_mac_rst_n_2_s0/Q test[2].u_mac_tx_model/shift_reg_96_s1/CLEAR tx_mac_clk:[R] tx_mac_clk:[R] 0.000 0.000 0.461
19 0.514 tx_mac_rst_n_2_s0/Q test[2].u_mac_tx_model/shift_reg_99_s1/CLEAR tx_mac_clk:[R] tx_mac_clk:[R] 0.000 0.000 0.461
20 0.516 tx_mac_rst_n_2_s0/Q test[2].u_mac_tx_model/shift_reg_55_s1/CLEAR tx_mac_clk:[R] tx_mac_clk:[R] 0.000 0.004 0.459
21 0.516 tx_mac_rst_n_2_s0/Q test[2].u_mac_tx_model/shift_reg_62_s1/CLEAR tx_mac_clk:[R] tx_mac_clk:[R] 0.000 0.004 0.459
22 0.516 tx_mac_rst_n_2_s0/Q test[2].u_mac_tx_model/shift_reg_70_s1/CLEAR tx_mac_clk:[R] tx_mac_clk:[R] 0.000 0.004 0.459
23 0.516 tx_mac_rst_n_2_s0/Q test[2].u_mac_tx_model/shift_reg_98_s1/CLEAR tx_mac_clk:[R] tx_mac_clk:[R] 0.000 0.004 0.459
24 0.516 tx_mac_rst_n_2_s0/Q test[2].u_mac_tx_model/shift_reg_100_s1/CLEAR tx_mac_clk:[R] tx_mac_clk:[R] 0.000 0.004 0.459
25 0.516 tx_mac_rst_n_2_s0/Q test[2].u_mac_tx_model/shift_reg_101_s1/CLEAR tx_mac_clk:[R] tx_mac_clk:[R] 0.000 0.004 0.459

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number Slack Actual Width Required Width Type Clock Objects
1 0.851 1.851 1.000 High Pulse Width rx_mac_clk gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s
2 0.861 1.861 1.000 High Pulse Width rx_mac_clk gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
3 0.962 1.962 1.000 Low Pulse Width rx_mac_clk gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s
4 0.973 1.973 1.000 Low Pulse Width rx_mac_clk gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
5 1.591 1.841 0.250 High Pulse Width rx_mac_clk u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_rx/rx_decode_rxd_d1_2_s0
6 1.591 1.841 0.250 High Pulse Width rx_mac_clk u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_rx/rx_decode_rxd_d3_4_s0
7 1.591 1.841 0.250 High Pulse Width rx_mac_clk u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_rx/rx_decode_rxd_d3_1_s0
8 1.591 1.841 0.250 High Pulse Width rx_mac_clk u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/gmii_rxd_int_6_s0
9 1.591 1.841 0.250 High Pulse Width rx_mac_clk u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_ge_sync/decode_k_d2_s0
10 1.591 1.841 0.250 High Pulse Width rx_mac_clk u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_frm_lgt_o_tmp_15_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 0.002
Data Arrival Time 11.546
Data Required Time 11.548
From u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/frm_byte_cnt_0_s3
To u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_preamble_s14
Launch Clk tx_mac_clk:[R]
Latch Clk tx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
3.832 3.832 tNET RR 1 R27C155[1][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/frm_byte_cnt_0_s3/CLK
4.215 0.382 tC2Q RR 35 R27C155[1][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/frm_byte_cnt_0_s3/Q
7.379 3.164 tNET RR 1 R36C158[2][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_ifg_s18/I2
7.958 0.579 tINS RR 1 R36C158[2][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_ifg_s18/F
8.130 0.172 tNET RR 1 R36C157[2][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_ifg_s7/I1
8.698 0.567 tINS RR 1 R36C157[2][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_ifg_s7/F
8.700 0.003 tNET RR 1 R36C157[3][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_ifg_s6/I0
9.247 0.548 tINS RR 2 R36C157[3][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_ifg_s6/F
9.840 0.593 tNET RR 1 R34C156[1][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_ifg_s4/I1
10.407 0.567 tINS RR 8 R34C156[1][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_ifg_s4/F
11.546 1.139 tNET RR 1 R38C157[2][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_preamble_s14/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 tx_mac_clk
8.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
11.859 3.859 tNET RR 1 R38C157[2][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_preamble_s14/CLK
11.548 -0.311 tSu 1 R38C157[2][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_preamble_s14

Path Statistics:

Clock Skew 0.027
Setup Relationship 8.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.832, 100.000%
Arrival Data Path Delay cell: 2.261, 29.315%; route: 5.070, 65.727%; tC2Q: 0.382, 4.959%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.859, 100.000%

Path2

Path Summary:

Slack 0.006
Data Arrival Time 11.812
Data Required Time 11.818
From u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_ge_tx/xmitCHANGE_to_config_s1
To u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_ge_tx/encode_txd_6_s1
Launch Clk tx_mac_clk:[R]
Latch Clk tx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
3.819 3.819 tNET RR 1 R51C159[0][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_ge_tx/xmitCHANGE_to_config_s1/CLK
4.202 0.382 tC2Q RR 4 R51C159[0][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_ge_tx/xmitCHANGE_to_config_s1/Q
4.586 0.384 tNET RR 1 R50C158[0][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_ge_tx/gmii_col_s7/I0
5.164 0.579 tINS RR 36 R50C158[0][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_ge_tx/gmii_col_s7/F
5.771 0.606 tNET RR 1 R51C156[3][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_ge_tx/n234_s4/I0
6.318 0.548 tINS RR 2 R51C156[3][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_ge_tx/n234_s4/F
6.727 0.409 tNET RR 1 R50C155[3][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_ge_tx/n231_s3/I3
7.301 0.574 tINS RR 1 R50C155[3][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_ge_tx/n231_s3/F
7.303 0.003 tNET RR 1 R50C155[0][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_ge_tx/n231_s1/I3
7.882 0.579 tINS RR 1 R50C155[0][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_ge_tx/n231_s1/F
11.812 3.930 tNET RR 1 R17C136[0][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_ge_tx/encode_txd_6_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 tx_mac_clk
8.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
11.881 3.881 tNET RR 1 R17C136[0][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_ge_tx/encode_txd_6_s1/CLK
11.818 -0.064 tSu 1 R17C136[0][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_ge_tx/encode_txd_6_s1

Path Statistics:

Clock Skew 0.062
Setup Relationship 8.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.819, 100.000%
Arrival Data Path Delay cell: 2.279, 28.511%; route: 5.331, 66.703%; tC2Q: 0.382, 4.786%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.881, 100.000%

Path3

Path Summary:

Slack 0.052
Data Arrival Time 11.506
Data Required Time 11.557
From u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/clk_ena_s0
To u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_pause_s12
Launch Clk tx_mac_clk:[R]
Latch Clk tx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
3.798 3.798 tNET RR 1 R31C156[0][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/clk_ena_s0/CLK
4.181 0.382 tC2Q RR 74 R31C156[0][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/clk_ena_s0/Q
5.199 1.019 tNET RR 1 R26C155[1][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/tx_unicast_frm_latch_s6/I3
5.767 0.567 tINS RR 1 R26C155[1][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/tx_unicast_frm_latch_s6/F
6.127 0.360 tNET RR 1 R24C155[3][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/tx_unicast_frm_latch_s5/I0
6.701 0.574 tINS RR 1 R24C155[3][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/tx_unicast_frm_latch_s5/F
7.082 0.381 tNET RR 1 R26C155[3][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/n_state.s_pad_s33/I2
7.656 0.574 tINS RR 2 R26C155[3][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/n_state.s_pad_s33/F
8.039 0.384 tNET RR 1 R27C156[3][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_ifg_s5/I0
8.613 0.574 tINS RR 2 R27C156[3][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_ifg_s5/F
9.231 0.618 tNET RR 1 R24C154[1][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_ifg_s4/I2
9.809 0.579 tINS RR 8 R24C154[1][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_ifg_s4/F
11.506 1.696 tNET RR 1 R38C154[1][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_pause_s12/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 tx_mac_clk
8.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
11.869 3.869 tNET RR 1 R38C154[1][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_pause_s12/CLK
11.557 -0.311 tSu 1 R38C154[1][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_pause_s12

Path Statistics:

Clock Skew 0.071
Setup Relationship 8.000
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.798, 100.000%
Arrival Data Path Delay cell: 2.868, 37.204%; route: 4.457, 57.833%; tC2Q: 0.382, 4.963%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.869, 100.000%

Path4

Path Summary:

Slack 0.057
Data Arrival Time 11.446
Data Required Time 11.503
From u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/clk_ena_s0
To u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_data_s12
Launch Clk tx_mac_clk:[R]
Latch Clk tx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
3.798 3.798 tNET RR 1 R31C156[0][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/clk_ena_s0/CLK
4.181 0.382 tC2Q RR 74 R31C156[0][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/clk_ena_s0/Q
5.199 1.019 tNET RR 1 R26C155[1][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/tx_unicast_frm_latch_s6/I3
5.767 0.567 tINS RR 1 R26C155[1][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/tx_unicast_frm_latch_s6/F
6.127 0.360 tNET RR 1 R24C155[3][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/tx_unicast_frm_latch_s5/I0
6.701 0.574 tINS RR 1 R24C155[3][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/tx_unicast_frm_latch_s5/F
7.082 0.381 tNET RR 1 R26C155[3][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/n_state.s_pad_s33/I2
7.656 0.574 tINS RR 2 R26C155[3][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/n_state.s_pad_s33/F
8.039 0.384 tNET RR 1 R27C156[3][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_ifg_s5/I0
8.613 0.574 tINS RR 2 R27C156[3][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_ifg_s5/F
9.231 0.618 tNET RR 1 R24C154[1][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_ifg_s4/I2
9.809 0.579 tINS RR 8 R24C154[1][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_ifg_s4/F
11.446 1.636 tNET RR 1 R35C156[3][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_data_s12/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 tx_mac_clk
8.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
11.814 3.814 tNET RR 1 R35C156[3][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_data_s12/CLK
11.503 -0.311 tSu 1 R35C156[3][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_data_s12

Path Statistics:

Clock Skew 0.016
Setup Relationship 8.000
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.798, 100.000%
Arrival Data Path Delay cell: 2.868, 37.496%; route: 4.398, 57.502%; tC2Q: 0.382, 5.002%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.814, 100.000%

Path5

Path Summary:

Slack 0.101
Data Arrival Time 11.390
Data Required Time 11.490
From u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/tx_mac_ready_o_s0
To test[2].u_mac_tx_model/tx_mac_data_6_s1
Launch Clk tx_mac_clk:[R]
Latch Clk tx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
3.792 3.792 tNET RR 1 R48C152[1][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/tx_mac_ready_o_s0/CLK
4.160 0.368 tC2Q RF 41 R48C152[1][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/tx_mac_ready_o_s0/Q
6.538 2.379 tNET FF 1 R32C143[3][A] test[2].u_mac_tx_model/tx_mac_data_7_s3/I0
7.112 0.574 tINS FR 8 R32C143[3][A] test[2].u_mac_tx_model/tx_mac_data_7_s3/F
11.390 4.278 tNET RR 1 R48C151[0][A] test[2].u_mac_tx_model/tx_mac_data_6_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 tx_mac_clk
8.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
11.802 3.802 tNET RR 1 R48C151[0][A] test[2].u_mac_tx_model/tx_mac_data_6_s1/CLK
11.490 -0.311 tSu 1 R48C151[0][A] test[2].u_mac_tx_model/tx_mac_data_6_s1

Path Statistics:

Clock Skew 0.009
Setup Relationship 8.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.792, 100.000%
Arrival Data Path Delay cell: 0.574, 7.552%; route: 6.656, 87.611%; tC2Q: 0.368, 4.837%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.802, 100.000%

Path6

Path Summary:

Slack 0.189
Data Arrival Time 11.643
Data Required Time 11.832
From u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_tx/c_state_3_s0
To u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_tx/encode_txd_2_s1
Launch Clk tx_mac_clk:[R]
Latch Clk tx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
3.909 3.909 tNET RR 1 R63C138[0][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_tx/c_state_3_s0/CLK
4.292 0.382 tC2Q RR 29 R63C138[0][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_tx/c_state_3_s0/Q
4.851 0.559 tNET RR 1 R61C139[1][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_tx/config_cnt_3_s4/I3
5.358 0.507 tINS RR 19 R61C139[1][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_tx/config_cnt_3_s4/F
6.336 0.978 tNET RR 1 R57C140[3][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_tx/n235_s7/I3
6.792 0.456 tINS RR 1 R57C140[3][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_tx/n235_s7/F
7.173 0.381 tNET RR 1 R60C140[0][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_tx/n235_s3/I3
7.681 0.507 tINS RR 1 R60C140[0][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_tx/n235_s3/F
7.853 0.172 tNET RR 1 R60C141[0][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_tx/n235_s1/I3
8.421 0.567 tINS RR 1 R60C141[0][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_tx/n235_s1/F
11.643 3.223 tNET RR 1 R33C126[3][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_tx/encode_txd_2_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 tx_mac_clk
8.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
11.896 3.896 tNET RR 1 R33C126[3][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_tx/encode_txd_2_s1/CLK
11.832 -0.064 tSu 1 R33C126[3][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_tx/encode_txd_2_s1

Path Statistics:

Clock Skew -0.013
Setup Relationship 8.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.909, 100.000%
Arrival Data Path Delay cell: 2.039, 26.362%; route: 5.312, 68.692%; tC2Q: 0.382, 4.946%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.896, 100.000%

Path7

Path Summary:

Slack 0.201
Data Arrival Time 11.337
Data Required Time 11.539
From u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/frm_byte_cnt_0_s3
To u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_pause_s12
Launch Clk tx_mac_clk:[R]
Latch Clk tx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
3.832 3.832 tNET RR 1 R27C155[1][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/frm_byte_cnt_0_s3/CLK
4.215 0.382 tC2Q RR 35 R27C155[1][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/frm_byte_cnt_0_s3/Q
7.379 3.164 tNET RR 1 R36C158[2][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_ifg_s18/I2
7.958 0.579 tINS RR 1 R36C158[2][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_ifg_s18/F
8.130 0.172 tNET RR 1 R36C157[2][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_ifg_s7/I1
8.698 0.567 tINS RR 1 R36C157[2][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_ifg_s7/F
8.700 0.003 tNET RR 1 R36C157[3][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_ifg_s6/I0
9.247 0.548 tINS RR 2 R36C157[3][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_ifg_s6/F
9.840 0.593 tNET RR 1 R34C156[1][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_ifg_s4/I1
10.407 0.567 tINS RR 8 R34C156[1][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_ifg_s4/F
11.337 0.930 tNET RR 1 R38C156[0][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_pause_s12/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 tx_mac_clk
8.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
11.850 3.850 tNET RR 1 R38C156[0][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_pause_s12/CLK
11.539 -0.311 tSu 1 R38C156[0][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_pause_s12

Path Statistics:

Clock Skew 0.018
Setup Relationship 8.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.832, 100.000%
Arrival Data Path Delay cell: 2.261, 30.130%; route: 4.861, 64.773%; tC2Q: 0.382, 5.097%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.850, 100.000%

Path8

Path Summary:

Slack 0.227
Data Arrival Time 11.609
Data Required Time 11.836
From u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_tx/c_state_3_s0
To u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_tx/encode_txd_4_s1
Launch Clk tx_mac_clk:[R]
Latch Clk tx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
3.909 3.909 tNET RR 1 R63C138[0][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_tx/c_state_3_s0/CLK
4.292 0.382 tC2Q RR 29 R63C138[0][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_tx/c_state_3_s0/Q
4.851 0.559 tNET RR 1 R61C139[1][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_tx/config_cnt_3_s4/I3
5.358 0.507 tINS RR 19 R61C139[1][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_tx/config_cnt_3_s4/F
6.184 0.826 tNET RR 1 R57C141[3][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_tx/n237_s5/I3
6.503 0.319 tINS RF 6 R57C141[3][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_tx/n237_s5/F
7.094 0.591 tNET FF 1 R59C140[0][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_tx/n233_s2/I0
7.673 0.579 tINS FR 1 R59C140[0][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_tx/n233_s2/F
8.054 0.381 tNET RR 1 R58C141[0][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_tx/n233_s1/I3
8.622 0.567 tINS RR 1 R58C141[0][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_tx/n233_s1/F
11.609 2.988 tNET RR 1 R45C109[0][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_tx/encode_txd_4_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 tx_mac_clk
8.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
11.900 3.900 tNET RR 1 R45C109[0][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_tx/encode_txd_4_s1/CLK
11.836 -0.064 tSu 1 R45C109[0][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_tx/encode_txd_4_s1

Path Statistics:

Clock Skew -0.009
Setup Relationship 8.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.909, 100.000%
Arrival Data Path Delay cell: 1.972, 25.617%; route: 5.345, 69.416%; tC2Q: 0.382, 4.968%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.900, 100.000%

Path9

Path Summary:

Slack 0.235
Data Arrival Time 11.306
Data Required Time 11.541
From u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_mac_tx_ctrl/tx_mac_ready_o_s0
To test[0].u_mac_tx_model/tx_mac_data_7_s1
Launch Clk tx_mac_clk:[R]
Latch Clk tx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
3.811 3.811 tNET RR 1 R48C150[0][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_mac_tx_ctrl/tx_mac_ready_o_s0/CLK
4.193 0.382 tC2Q RR 42 R48C150[0][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_mac_tx_ctrl/tx_mac_ready_o_s0/Q
7.926 3.733 tNET RR 1 R23C143[2][B] test[0].u_mac_tx_model/tx_mac_data_7_s3/I0
8.493 0.567 tINS RR 8 R23C143[2][B] test[0].u_mac_tx_model/tx_mac_data_7_s3/F
11.306 2.812 tNET RR 1 R41C147[2][A] test[0].u_mac_tx_model/tx_mac_data_7_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 tx_mac_clk
8.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
11.852 3.852 tNET RR 1 R41C147[2][A] test[0].u_mac_tx_model/tx_mac_data_7_s1/CLK
11.541 -0.311 tSu 1 R41C147[2][A] test[0].u_mac_tx_model/tx_mac_data_7_s1

Path Statistics:

Clock Skew 0.041
Setup Relationship 8.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.811, 100.000%
Arrival Data Path Delay cell: 0.567, 7.572%; route: 6.545, 87.325%; tC2Q: 0.382, 5.103%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.852, 100.000%

Path10

Path Summary:

Slack 0.262
Data Arrival Time 11.250
Data Required Time 11.512
From u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/back_cnt_1_s1
To u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/back_cnt_15_s1
Launch Clk tx_mac_clk:[R]
Latch Clk tx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
3.813 3.813 tNET RR 1 R32C155[0][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/back_cnt_1_s1/CLK
4.196 0.382 tC2Q RR 4 R32C155[0][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/back_cnt_1_s1/Q
4.373 0.177 tNET RR 1 R32C156[1][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/n1186_s2/I1
4.941 0.567 tINS RR 4 R32C156[1][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/n1186_s2/F
5.730 0.789 tNET RR 1 R24C156[0][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/n1183_s2/I3
6.308 0.579 tINS RR 6 R24C156[0][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/n1183_s2/F
6.486 0.178 tNET RR 1 R24C155[0][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/n1175_s2/I1
6.775 0.289 tINS RR 4 R24C155[0][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/n1175_s2/F
7.733 0.959 tNET RR 1 R33C156[2][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/n1088_s1/I1
8.312 0.579 tINS RR 1 R33C156[2][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/n1088_s1/F
8.315 0.003 tNET RR 1 R33C156[3][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/n1088_s0/I3
8.862 0.548 tINS RR 16 R33C156[3][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/n1088_s0/F
11.250 2.388 tNET RR 1 R27C156[2][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/back_cnt_15_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 tx_mac_clk
8.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
11.823 3.823 tNET RR 1 R27C156[2][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/back_cnt_15_s1/CLK
11.512 -0.311 tSu 1 R27C156[2][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/back_cnt_15_s1

Path Statistics:

Clock Skew 0.010
Setup Relationship 8.000
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.813, 100.000%
Arrival Data Path Delay cell: 2.561, 34.441%; route: 4.493, 60.415%; tC2Q: 0.382, 5.144%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.823, 100.000%

Path11

Path Summary:

Slack 0.266
Data Arrival Time 11.234
Data Required Time 11.501
From u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/clk_ena_s0
To u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_fcs_s6
Launch Clk tx_mac_clk:[R]
Latch Clk tx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
3.798 3.798 tNET RR 1 R31C156[0][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/clk_ena_s0/CLK
4.181 0.382 tC2Q RR 74 R31C156[0][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/clk_ena_s0/Q
5.199 1.019 tNET RR 1 R26C155[1][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/tx_unicast_frm_latch_s6/I3
5.767 0.567 tINS RR 1 R26C155[1][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/tx_unicast_frm_latch_s6/F
6.127 0.360 tNET RR 1 R24C155[3][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/tx_unicast_frm_latch_s5/I0
6.701 0.574 tINS RR 1 R24C155[3][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/tx_unicast_frm_latch_s5/F
7.082 0.381 tNET RR 1 R26C155[3][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/n_state.s_pad_s33/I2
7.656 0.574 tINS RR 2 R26C155[3][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/n_state.s_pad_s33/F
8.039 0.384 tNET RR 1 R27C156[3][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_ifg_s5/I0
8.613 0.574 tINS RR 2 R27C156[3][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_ifg_s5/F
9.231 0.618 tNET RR 1 R24C154[1][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_ifg_s4/I2
9.809 0.579 tINS RR 8 R24C154[1][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_ifg_s4/F
11.234 1.425 tNET RR 1 R34C156[0][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_fcs_s6/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 tx_mac_clk
8.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
11.812 3.812 tNET RR 1 R34C156[0][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_fcs_s6/CLK
11.501 -0.311 tSu 1 R34C156[0][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_fcs_s6

Path Statistics:

Clock Skew 0.014
Setup Relationship 8.000
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.798, 100.000%
Arrival Data Path Delay cell: 2.868, 38.561%; route: 4.186, 56.295%; tC2Q: 0.382, 5.144%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.812, 100.000%

Path12

Path Summary:

Slack 0.266
Data Arrival Time 11.234
Data Required Time 11.501
From u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/clk_ena_s0
To u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_pad_s8
Launch Clk tx_mac_clk:[R]
Latch Clk tx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
3.798 3.798 tNET RR 1 R31C156[0][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/clk_ena_s0/CLK
4.181 0.382 tC2Q RR 74 R31C156[0][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/clk_ena_s0/Q
5.199 1.019 tNET RR 1 R26C155[1][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/tx_unicast_frm_latch_s6/I3
5.767 0.567 tINS RR 1 R26C155[1][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/tx_unicast_frm_latch_s6/F
6.127 0.360 tNET RR 1 R24C155[3][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/tx_unicast_frm_latch_s5/I0
6.701 0.574 tINS RR 1 R24C155[3][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/tx_unicast_frm_latch_s5/F
7.082 0.381 tNET RR 1 R26C155[3][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/n_state.s_pad_s33/I2
7.656 0.574 tINS RR 2 R26C155[3][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/n_state.s_pad_s33/F
8.039 0.384 tNET RR 1 R27C156[3][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_ifg_s5/I0
8.613 0.574 tINS RR 2 R27C156[3][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_ifg_s5/F
9.231 0.618 tNET RR 1 R24C154[1][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_ifg_s4/I2
9.809 0.579 tINS RR 8 R24C154[1][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_ifg_s4/F
11.234 1.425 tNET RR 1 R34C156[1][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_pad_s8/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 tx_mac_clk
8.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
11.812 3.812 tNET RR 1 R34C156[1][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_pad_s8/CLK
11.501 -0.311 tSu 1 R34C156[1][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_pad_s8

Path Statistics:

Clock Skew 0.014
Setup Relationship 8.000
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.798, 100.000%
Arrival Data Path Delay cell: 2.868, 38.561%; route: 4.186, 56.295%; tC2Q: 0.382, 5.144%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.812, 100.000%

Path13

Path Summary:

Slack 0.266
Data Arrival Time 11.234
Data Required Time 11.501
From u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/clk_ena_s0
To u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_jam_s4
Launch Clk tx_mac_clk:[R]
Latch Clk tx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
3.798 3.798 tNET RR 1 R31C156[0][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/clk_ena_s0/CLK
4.181 0.382 tC2Q RR 74 R31C156[0][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/clk_ena_s0/Q
5.199 1.019 tNET RR 1 R26C155[1][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/tx_unicast_frm_latch_s6/I3
5.767 0.567 tINS RR 1 R26C155[1][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/tx_unicast_frm_latch_s6/F
6.127 0.360 tNET RR 1 R24C155[3][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/tx_unicast_frm_latch_s5/I0
6.701 0.574 tINS RR 1 R24C155[3][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/tx_unicast_frm_latch_s5/F
7.082 0.381 tNET RR 1 R26C155[3][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/n_state.s_pad_s33/I2
7.656 0.574 tINS RR 2 R26C155[3][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/n_state.s_pad_s33/F
8.039 0.384 tNET RR 1 R27C156[3][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_ifg_s5/I0
8.613 0.574 tINS RR 2 R27C156[3][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_ifg_s5/F
9.231 0.618 tNET RR 1 R24C154[1][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_ifg_s4/I2
9.809 0.579 tINS RR 8 R24C154[1][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_ifg_s4/F
11.234 1.425 tNET RR 1 R34C156[0][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_jam_s4/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 tx_mac_clk
8.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
11.812 3.812 tNET RR 1 R34C156[0][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_jam_s4/CLK
11.501 -0.311 tSu 1 R34C156[0][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_jam_s4

Path Statistics:

Clock Skew 0.014
Setup Relationship 8.000
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.798, 100.000%
Arrival Data Path Delay cell: 2.868, 38.561%; route: 4.186, 56.295%; tC2Q: 0.382, 5.144%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.812, 100.000%

Path14

Path Summary:

Slack 0.275
Data Arrival Time 11.237
Data Required Time 11.512
From u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/clk_ena_s0
To u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_preamble_s14
Launch Clk tx_mac_clk:[R]
Latch Clk tx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
3.798 3.798 tNET RR 1 R31C156[0][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/clk_ena_s0/CLK
4.181 0.382 tC2Q RR 74 R31C156[0][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/clk_ena_s0/Q
5.199 1.019 tNET RR 1 R26C155[1][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/tx_unicast_frm_latch_s6/I3
5.767 0.567 tINS RR 1 R26C155[1][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/tx_unicast_frm_latch_s6/F
6.127 0.360 tNET RR 1 R24C155[3][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/tx_unicast_frm_latch_s5/I0
6.701 0.574 tINS RR 1 R24C155[3][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/tx_unicast_frm_latch_s5/F
7.082 0.381 tNET RR 1 R26C155[3][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/n_state.s_pad_s33/I2
7.656 0.574 tINS RR 2 R26C155[3][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/n_state.s_pad_s33/F
8.039 0.384 tNET RR 1 R27C156[3][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_ifg_s5/I0
8.613 0.574 tINS RR 2 R27C156[3][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_ifg_s5/F
9.231 0.618 tNET RR 1 R24C154[1][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_ifg_s4/I2
9.809 0.579 tINS RR 8 R24C154[1][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_ifg_s4/F
11.237 1.428 tNET RR 1 R35C155[0][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_preamble_s14/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 tx_mac_clk
8.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
11.823 3.823 tNET RR 1 R35C155[0][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_preamble_s14/CLK
11.512 -0.311 tSu 1 R35C155[0][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_preamble_s14

Path Statistics:

Clock Skew 0.025
Setup Relationship 8.000
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.798, 100.000%
Arrival Data Path Delay cell: 2.868, 38.548%; route: 4.189, 56.310%; tC2Q: 0.382, 5.142%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.823, 100.000%

Path15

Path Summary:

Slack 0.279
Data Arrival Time 11.401
Data Required Time 11.680
From u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_ge_tx/c_state_2_s0
To u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_ge_tx/encode_txd_7_s2
Launch Clk tx_mac_clk:[R]
Latch Clk tx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
3.813 3.813 tNET RR 1 R50C159[2][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_ge_tx/c_state_2_s0/CLK
4.181 0.368 tC2Q RF 32 R50C159[2][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_ge_tx/c_state_2_s0/Q
4.991 0.810 tNET FF 1 R52C159[2][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_ge_tx/config_cnt_3_s4/I2
5.280 0.289 tINS FR 19 R52C159[2][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_ge_tx/config_cnt_3_s4/F
5.892 0.613 tNET RR 1 R53C156[0][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_ge_tx/n237_s6/I3
6.460 0.567 tINS RR 2 R53C156[0][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_ge_tx/n237_s6/F
6.822 0.363 tNET RR 1 R51C156[2][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_ge_tx/n230_s4/I0
7.390 0.567 tINS RR 1 R51C156[2][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_ge_tx/n230_s4/F
7.771 0.381 tNET RR 1 R50C155[0][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_ge_tx/n230_s1/I3
8.350 0.579 tINS RR 1 R50C155[0][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_ge_tx/n230_s1/F
11.401 3.051 tNET RR 1 R24C136[1][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_ge_tx/encode_txd_7_s2/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 tx_mac_clk
8.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
11.908 3.908 tNET RR 1 R24C136[1][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_ge_tx/encode_txd_7_s2/CLK
11.680 -0.227 tSu 1 R24C136[1][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_ge_tx/encode_txd_7_s2

Path Statistics:

Clock Skew 0.094
Setup Relationship 8.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.813, 100.000%
Arrival Data Path Delay cell: 2.003, 26.392%; route: 5.217, 68.764%; tC2Q: 0.368, 4.843%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.908, 100.000%

Path16

Path Summary:

Slack 0.284
Data Arrival Time 11.223
Data Required Time 11.507
From u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_ge_rx/rudi_1_s3
To u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_ge_an/mr_lp_adv_ability_10_s2
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.810 3.810 tNET RR 1 R51C146[1][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_ge_rx/rudi_1_s3/CLK
4.193 0.382 tC2Q RR 1 R51C146[1][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_ge_rx/rudi_1_s3/Q
4.783 0.590 tNET RR 1 R51C150[3][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_ge_an/mr_page_rx_s8/I1
5.239 0.456 tINS RR 1 R51C150[3][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_ge_an/mr_page_rx_s8/F
6.101 0.863 tNET RR 1 R49C155[2][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_ge_an/mr_page_rx_s7/I3
6.669 0.567 tINS RR 31 R49C155[2][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_ge_an/mr_page_rx_s7/F
8.535 1.866 tNET RR 1 R57C155[0][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_ge_an/mr_lp_adv_ability_15_s5/I3
9.114 0.579 tINS RR 3 R57C155[0][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_ge_an/mr_lp_adv_ability_15_s5/F
11.223 2.109 tNET RR 1 R47C155[1][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_ge_an/mr_lp_adv_ability_10_s2/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 rx_mac_clk
8.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
11.818 3.818 tNET RR 1 R47C155[1][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_ge_an/mr_lp_adv_ability_10_s2/CLK
11.507 -0.311 tSu 1 R47C155[1][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_ge_an/mr_lp_adv_ability_10_s2

Path Statistics:

Clock Skew 0.008
Setup Relationship 8.000
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.810, 100.000%
Arrival Data Path Delay cell: 1.603, 21.619%; route: 5.428, 73.221%; tC2Q: 0.382, 5.160%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.818, 100.000%

Path17

Path Summary:

Slack 0.284
Data Arrival Time 11.223
Data Required Time 11.507
From u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_ge_rx/rudi_1_s3
To u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_ge_an/mr_lp_adv_ability_12_s2
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.810 3.810 tNET RR 1 R51C146[1][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_ge_rx/rudi_1_s3/CLK
4.193 0.382 tC2Q RR 1 R51C146[1][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_ge_rx/rudi_1_s3/Q
4.783 0.590 tNET RR 1 R51C150[3][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_ge_an/mr_page_rx_s8/I1
5.239 0.456 tINS RR 1 R51C150[3][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_ge_an/mr_page_rx_s8/F
6.101 0.863 tNET RR 1 R49C155[2][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_ge_an/mr_page_rx_s7/I3
6.669 0.567 tINS RR 31 R49C155[2][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_ge_an/mr_page_rx_s7/F
8.535 1.866 tNET RR 1 R57C155[0][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_ge_an/mr_lp_adv_ability_15_s5/I3
9.114 0.579 tINS RR 3 R57C155[0][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_ge_an/mr_lp_adv_ability_15_s5/F
11.223 2.109 tNET RR 1 R47C155[1][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_ge_an/mr_lp_adv_ability_12_s2/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 rx_mac_clk
8.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
11.818 3.818 tNET RR 1 R47C155[1][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_ge_an/mr_lp_adv_ability_12_s2/CLK
11.507 -0.311 tSu 1 R47C155[1][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_ge_an/mr_lp_adv_ability_12_s2

Path Statistics:

Clock Skew 0.008
Setup Relationship 8.000
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.810, 100.000%
Arrival Data Path Delay cell: 1.603, 21.619%; route: 5.428, 73.221%; tC2Q: 0.382, 5.160%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.818, 100.000%

Path18

Path Summary:

Slack 0.296
Data Arrival Time 11.259
Data Required Time 11.555
From u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_an/mr_an_enable_d3_s0
To u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_an/link_timer_cnt_20_s1
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.917 3.917 tNET RR 1 R60C143[1][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_an/mr_an_enable_d3_s0/CLK
4.299 0.382 tC2Q RR 24 R60C143[1][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_an/mr_an_enable_d3_s0/Q
4.688 0.389 tNET RR 1 R61C142[3][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_an/mr_page_rx_s8/I2
5.236 0.548 tINS RR 1 R61C142[3][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_an/mr_page_rx_s8/F
6.564 1.329 tNET RR 1 R52C151[3][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_an/mr_page_rx_s7/I3
7.021 0.456 tINS RR 31 R52C151[3][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_an/mr_page_rx_s7/F
8.152 1.131 tNET RR 1 R60C150[3][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_an/n222_s2/I3
8.726 0.574 tINS RR 23 R60C150[3][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_an/n222_s2/F
9.833 1.108 tNET RR 1 R51C148[3][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_an/link_timer_cnt_20_s5/I0
10.124 0.291 tINS RR 20 R51C148[3][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_an/link_timer_cnt_20_s5/F
11.259 1.135 tNET RR 1 R57C148[0][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_an/link_timer_cnt_20_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 rx_mac_clk
8.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
11.866 3.866 tNET RR 1 R57C148[0][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_an/link_timer_cnt_20_s1/CLK
11.555 -0.311 tSu 1 R57C148[0][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_an/link_timer_cnt_20_s1

Path Statistics:

Clock Skew -0.051
Setup Relationship 8.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.917, 100.000%
Arrival Data Path Delay cell: 1.869, 25.451%; route: 5.091, 69.339%; tC2Q: 0.382, 5.209%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.866, 100.000%

Path19

Path Summary:

Slack 0.298
Data Arrival Time 11.216
Data Required Time 11.514
From u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/frm_byte_cnt_0_s3
To u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_idle_s16
Launch Clk tx_mac_clk:[R]
Latch Clk tx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
3.832 3.832 tNET RR 1 R27C155[1][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/frm_byte_cnt_0_s3/CLK
4.215 0.382 tC2Q RR 35 R27C155[1][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/frm_byte_cnt_0_s3/Q
7.379 3.164 tNET RR 1 R36C158[2][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_ifg_s18/I2
7.958 0.579 tINS RR 1 R36C158[2][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_ifg_s18/F
8.130 0.172 tNET RR 1 R36C157[2][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_ifg_s7/I1
8.698 0.567 tINS RR 1 R36C157[2][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_ifg_s7/F
8.700 0.003 tNET RR 1 R36C157[3][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_ifg_s6/I0
9.247 0.548 tINS RR 2 R36C157[3][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_ifg_s6/F
9.840 0.593 tNET RR 1 R34C156[1][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_ifg_s4/I1
10.407 0.567 tINS RR 8 R34C156[1][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_ifg_s4/F
11.216 0.809 tNET RR 1 R36C157[0][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_idle_s16/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 tx_mac_clk
8.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
11.825 3.825 tNET RR 1 R36C157[0][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_idle_s16/CLK
11.514 -0.311 tSu 1 R36C157[0][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_idle_s16

Path Statistics:

Clock Skew -0.007
Setup Relationship 8.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.832, 100.000%
Arrival Data Path Delay cell: 2.261, 30.625%; route: 4.740, 64.195%; tC2Q: 0.382, 5.180%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.825, 100.000%

Path20

Path Summary:

Slack 0.307
Data Arrival Time 11.216
Data Required Time 11.523
From u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/frm_byte_cnt_0_s3
To u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_jam_s4
Launch Clk tx_mac_clk:[R]
Latch Clk tx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
3.832 3.832 tNET RR 1 R27C155[1][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/frm_byte_cnt_0_s3/CLK
4.215 0.382 tC2Q RR 35 R27C155[1][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/frm_byte_cnt_0_s3/Q
7.379 3.164 tNET RR 1 R36C158[2][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_ifg_s18/I2
7.958 0.579 tINS RR 1 R36C158[2][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_ifg_s18/F
8.130 0.172 tNET RR 1 R36C157[2][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_ifg_s7/I1
8.698 0.567 tINS RR 1 R36C157[2][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_ifg_s7/F
8.700 0.003 tNET RR 1 R36C157[3][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_ifg_s6/I0
9.247 0.548 tINS RR 2 R36C157[3][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_ifg_s6/F
9.840 0.593 tNET RR 1 R34C156[1][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_ifg_s4/I1
10.407 0.567 tINS RR 8 R34C156[1][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_ifg_s4/F
11.216 0.809 tNET RR 1 R36C158[0][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_jam_s4/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 tx_mac_clk
8.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
11.834 3.834 tNET RR 1 R36C158[0][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_jam_s4/CLK
11.523 -0.311 tSu 1 R36C158[0][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_jam_s4

Path Statistics:

Clock Skew 0.002
Setup Relationship 8.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.832, 100.000%
Arrival Data Path Delay cell: 2.261, 30.625%; route: 4.740, 64.195%; tC2Q: 0.382, 5.180%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.834, 100.000%

Path21

Path Summary:

Slack 0.401
Data Arrival Time 11.119
Data Required Time 11.519
From u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/frm_byte_cnt_0_s3
To u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_fcs_s6
Launch Clk tx_mac_clk:[R]
Latch Clk tx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
3.869 3.869 tNET RR 1 R56C154[3][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/frm_byte_cnt_0_s3/CLK
4.251 0.382 tC2Q RR 37 R56C154[3][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/frm_byte_cnt_0_s3/Q
5.794 1.543 tNET RR 1 R58C156[1][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_ifg_s11/I2
6.301 0.507 tINS RR 2 R58C156[1][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_ifg_s11/F
7.265 0.964 tNET RR 1 R52C155[0][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_ifg_s7/I0
7.833 0.567 tINS RR 1 R52C155[0][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_ifg_s7/F
7.835 0.003 tNET RR 1 R52C155[3][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_ifg_s5/I2
8.409 0.574 tINS RR 2 R52C155[3][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_ifg_s5/F
9.176 0.767 tNET RR 1 R56C156[1][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_ifg_s4/I3
9.684 0.507 tINS RR 8 R56C156[1][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_ifg_s4/F
11.119 1.435 tNET RR 1 R52C154[2][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_fcs_s6/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 tx_mac_clk
8.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
11.831 3.831 tNET RR 1 R52C154[2][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_fcs_s6/CLK
11.519 -0.311 tSu 1 R52C154[2][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_fcs_s6

Path Statistics:

Clock Skew -0.038
Setup Relationship 8.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.869, 100.000%
Arrival Data Path Delay cell: 2.156, 29.741%; route: 4.711, 64.983%; tC2Q: 0.382, 5.276%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.831, 100.000%

Path22

Path Summary:

Slack 0.401
Data Arrival Time 11.119
Data Required Time 11.519
From u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/frm_byte_cnt_0_s3
To u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_pad_s8
Launch Clk tx_mac_clk:[R]
Latch Clk tx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
3.869 3.869 tNET RR 1 R56C154[3][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/frm_byte_cnt_0_s3/CLK
4.251 0.382 tC2Q RR 37 R56C154[3][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/frm_byte_cnt_0_s3/Q
5.794 1.543 tNET RR 1 R58C156[1][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_ifg_s11/I2
6.301 0.507 tINS RR 2 R58C156[1][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_ifg_s11/F
7.265 0.964 tNET RR 1 R52C155[0][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_ifg_s7/I0
7.833 0.567 tINS RR 1 R52C155[0][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_ifg_s7/F
7.835 0.003 tNET RR 1 R52C155[3][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_ifg_s5/I2
8.409 0.574 tINS RR 2 R52C155[3][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_ifg_s5/F
9.176 0.767 tNET RR 1 R56C156[1][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_ifg_s4/I3
9.684 0.507 tINS RR 8 R56C156[1][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_ifg_s4/F
11.119 1.435 tNET RR 1 R52C154[2][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_pad_s8/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 tx_mac_clk
8.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
11.831 3.831 tNET RR 1 R52C154[2][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_pad_s8/CLK
11.519 -0.311 tSu 1 R52C154[2][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_pad_s8

Path Statistics:

Clock Skew -0.038
Setup Relationship 8.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.869, 100.000%
Arrival Data Path Delay cell: 2.156, 29.741%; route: 4.711, 64.983%; tC2Q: 0.382, 5.276%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.831, 100.000%

Path23

Path Summary:

Slack 0.424
Data Arrival Time 11.249
Data Required Time 11.672
From u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_tx/encoder_tx_even_s0
To u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_tx/encode_k_s2
Launch Clk tx_mac_clk:[R]
Latch Clk tx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
3.926 3.926 tNET RR 1 R60C138[0][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_tx/encoder_tx_even_s0/CLK
4.309 0.382 tC2Q RR 11 R60C138[0][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_tx/encoder_tx_even_s0/Q
4.703 0.394 tNET RR 1 R58C139[3][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_tx/gmii_col_s7/I1
5.250 0.548 tINS RR 36 R58C139[3][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_tx/gmii_col_s7/F
6.024 0.774 tNET RR 1 R61C141[2][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_tx/n133_s11/I3
6.531 0.507 tINS RR 3 R61C141[2][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_tx/n133_s11/F
6.709 0.177 tNET RR 1 R60C141[1][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_tx/n133_s3/I2
7.276 0.567 tINS RR 5 R60C141[1][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_tx/n133_s3/F
7.915 0.639 tNET RR 1 R56C140[0][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_tx/n133_s0/I2
8.483 0.567 tINS RR 1 R56C140[0][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_tx/n133_s0/F
11.249 2.766 tNET RR 1 R45C113[1][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_tx/encode_k_s2/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 tx_mac_clk
8.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
11.900 3.900 tNET RR 1 R45C113[1][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_tx/encode_k_s2/CLK
11.672 -0.227 tSu 1 R45C113[1][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_tx/encode_k_s2

Path Statistics:

Clock Skew -0.026
Setup Relationship 8.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.926, 100.000%
Arrival Data Path Delay cell: 2.190, 29.908%; route: 4.750, 64.869%; tC2Q: 0.382, 5.224%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.900, 100.000%

Path24

Path Summary:

Slack 0.437
Data Arrival Time 11.097
Data Required Time 11.534
From u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_mac_tx_ctrl/tx_mac_ready_o_s0
To test[0].u_mac_tx_model/tx_mac_data_1_s1
Launch Clk tx_mac_clk:[R]
Latch Clk tx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
3.811 3.811 tNET RR 1 R48C150[0][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_mac_tx_ctrl/tx_mac_ready_o_s0/CLK
4.193 0.382 tC2Q RR 42 R48C150[0][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_mac_tx_ctrl/tx_mac_ready_o_s0/Q
7.926 3.733 tNET RR 1 R23C143[2][B] test[0].u_mac_tx_model/tx_mac_data_7_s3/I0
8.493 0.567 tINS RR 8 R23C143[2][B] test[0].u_mac_tx_model/tx_mac_data_7_s3/F
11.097 2.604 tNET RR 1 R40C148[0][A] test[0].u_mac_tx_model/tx_mac_data_1_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 tx_mac_clk
8.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
11.845 3.845 tNET RR 1 R40C148[0][A] test[0].u_mac_tx_model/tx_mac_data_1_s1/CLK
11.534 -0.311 tSu 1 R40C148[0][A] test[0].u_mac_tx_model/tx_mac_data_1_s1

Path Statistics:

Clock Skew 0.034
Setup Relationship 8.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.811, 100.000%
Arrival Data Path Delay cell: 0.567, 7.789%; route: 6.336, 86.962%; tC2Q: 0.382, 5.250%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.845, 100.000%

Path25

Path Summary:

Slack 0.452
Data Arrival Time 11.220
Data Required Time 11.672
From u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_tx/encoder_tx_even_s0
To u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_tx/encode_txd_1_s1
Launch Clk tx_mac_clk:[R]
Latch Clk tx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
3.926 3.926 tNET RR 1 R60C138[0][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_tx/encoder_tx_even_s0/CLK
4.309 0.382 tC2Q RR 11 R60C138[0][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_tx/encoder_tx_even_s0/Q
4.703 0.394 tNET RR 1 R58C139[3][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_tx/gmii_col_s7/I1
5.250 0.548 tINS RR 36 R58C139[3][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_tx/gmii_col_s7/F
5.875 0.625 tNET RR 1 R62C140[2][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_tx/n237_s13/I0
6.454 0.579 tINS RR 4 R62C140[2][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_tx/n237_s13/F
7.239 0.785 tNET RR 1 R59C141[1][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_tx/n236_s3/I1
7.818 0.579 tINS RR 1 R59C141[1][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_tx/n236_s3/F
7.990 0.172 tNET RR 1 R58C141[1][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_tx/n236_s1/I2
8.558 0.567 tINS RR 1 R58C141[1][A] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_tx/n236_s1/F
11.220 2.663 tNET RR 1 R45C113[0][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_tx/encode_txd_1_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 tx_mac_clk
8.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
11.900 3.900 tNET RR 1 R45C113[0][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_tx/encode_txd_1_s1/CLK
11.672 -0.227 tSu 1 R45C113[0][B] u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_tx/encode_txd_1_s1

Path Statistics:

Clock Skew -0.026
Setup Relationship 8.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.926, 100.000%
Arrival Data Path Delay cell: 2.273, 31.157%; route: 4.639, 63.599%; tC2Q: 0.382, 5.244%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.900, 100.000%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 0.229
Data Arrival Time 1.706
Data Required Time 1.477
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_0_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.461 1.461 tNET RR 1 R24C135[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_0_s0/CLK
1.605 0.144 tC2Q RR 1 R24C135[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_0_s0/Q
1.706 0.101 tNET RR 1 BSRAM_R28[26] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[0]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.440 1.440 tNET RR 1 BSRAM_R28[26] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
1.477 0.037 tHld 1 BSRAM_R28[26] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew -0.021
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.461, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.101, 41.224%; tC2Q: 0.144, 58.776%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.440, 100.000%

Path2

Path Summary:

Slack 0.275
Data Arrival Time 1.749
Data Required Time 1.474
From test[3].u_mac_rx_model/rx_cnt_30_s1
To test[3].u_mac_rx_model/rx_cnt_30_s1
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.449 1.449 tNET RR 1 R5C158[1][A] test[3].u_mac_rx_model/rx_cnt_30_s1/CLK
1.590 0.141 tC2Q RF 3 R5C158[1][A] test[3].u_mac_rx_model/rx_cnt_30_s1/Q
1.596 0.006 tNET FF 1 R5C158[1][A] test[3].u_mac_rx_model/n2381_s2/I3
1.749 0.153 tINS FF 1 R5C158[1][A] test[3].u_mac_rx_model/n2381_s2/F
1.749 0.000 tNET FF 1 R5C158[1][A] test[3].u_mac_rx_model/rx_cnt_30_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.449 1.449 tNET RR 1 R5C158[1][A] test[3].u_mac_rx_model/rx_cnt_30_s1/CLK
1.474 0.025 tHld 1 R5C158[1][A] test[3].u_mac_rx_model/rx_cnt_30_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.449, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.449, 100.000%

Path3

Path Summary:

Slack 0.275
Data Arrival Time 1.766
Data Required Time 1.491
From test[3].u_mac_rx_model/rx_data_cnt_pause_0_s1
To test[3].u_mac_rx_model/rx_data_cnt_pause_0_s1
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.466 1.466 tNET RR 1 R3C133[0][A] test[3].u_mac_rx_model/rx_data_cnt_pause_0_s1/CLK
1.607 0.141 tC2Q RF 6 R3C133[0][A] test[3].u_mac_rx_model/rx_data_cnt_pause_0_s1/Q
1.613 0.006 tNET FF 1 R3C133[0][A] test[3].u_mac_rx_model/n2154_s1/I1
1.766 0.153 tINS FF 1 R3C133[0][A] test[3].u_mac_rx_model/n2154_s1/F
1.766 0.000 tNET FF 1 R3C133[0][A] test[3].u_mac_rx_model/rx_data_cnt_pause_0_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.466 1.466 tNET RR 1 R3C133[0][A] test[3].u_mac_rx_model/rx_data_cnt_pause_0_s1/CLK
1.491 0.025 tHld 1 R3C133[0][A] test[3].u_mac_rx_model/rx_data_cnt_pause_0_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.466, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.466, 100.000%

Path4

Path Summary:

Slack 0.275
Data Arrival Time 1.763
Data Required Time 1.488
From test[3].u_mac_rx_model/rx_data_cnt_pause_15_s1
To test[3].u_mac_rx_model/rx_data_cnt_pause_15_s1
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.463 1.463 tNET RR 1 R7C136[0][A] test[3].u_mac_rx_model/rx_data_cnt_pause_15_s1/CLK
1.604 0.141 tC2Q RF 2 R7C136[0][A] test[3].u_mac_rx_model/rx_data_cnt_pause_15_s1/Q
1.610 0.006 tNET FF 1 R7C136[0][A] test[3].u_mac_rx_model/n2139_s1/I2
1.763 0.153 tINS FF 1 R7C136[0][A] test[3].u_mac_rx_model/n2139_s1/F
1.763 0.000 tNET FF 1 R7C136[0][A] test[3].u_mac_rx_model/rx_data_cnt_pause_15_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.463 1.463 tNET RR 1 R7C136[0][A] test[3].u_mac_rx_model/rx_data_cnt_pause_15_s1/CLK
1.488 0.025 tHld 1 R7C136[0][A] test[3].u_mac_rx_model/rx_data_cnt_pause_15_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.463, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.463, 100.000%

Path5

Path Summary:

Slack 0.275
Data Arrival Time 1.761
Data Required Time 1.486
From test[3].u_mac_rx_model/shift_reg_pause_1_s1
To test[3].u_mac_rx_model/shift_reg_pause_1_s1
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.461 1.461 tNET RR 1 R6C131[1][A] test[3].u_mac_rx_model/shift_reg_pause_1_s1/CLK
1.602 0.141 tC2Q RF 2 R6C131[1][A] test[3].u_mac_rx_model/shift_reg_pause_1_s1/Q
1.608 0.006 tNET FF 1 R6C131[1][A] test[3].u_mac_rx_model/n1948_s0/I1
1.761 0.153 tINS FF 1 R6C131[1][A] test[3].u_mac_rx_model/n1948_s0/F
1.761 0.000 tNET FF 1 R6C131[1][A] test[3].u_mac_rx_model/shift_reg_pause_1_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.461 1.461 tNET RR 1 R6C131[1][A] test[3].u_mac_rx_model/shift_reg_pause_1_s1/CLK
1.486 0.025 tHld 1 R6C131[1][A] test[3].u_mac_rx_model/shift_reg_pause_1_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.461, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.461, 100.000%

Path6

Path Summary:

Slack 0.275
Data Arrival Time 1.762
Data Required Time 1.487
From test[3].u_mac_rx_model/shift_reg_pause_5_s1
To test[3].u_mac_rx_model/shift_reg_pause_5_s1
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.462 1.462 tNET RR 1 R3C130[1][A] test[3].u_mac_rx_model/shift_reg_pause_5_s1/CLK
1.603 0.141 tC2Q RF 2 R3C130[1][A] test[3].u_mac_rx_model/shift_reg_pause_5_s1/Q
1.609 0.006 tNET FF 1 R3C130[1][A] test[3].u_mac_rx_model/n1944_s0/I1
1.762 0.153 tINS FF 1 R3C130[1][A] test[3].u_mac_rx_model/n1944_s0/F
1.762 0.000 tNET FF 1 R3C130[1][A] test[3].u_mac_rx_model/shift_reg_pause_5_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.462 1.462 tNET RR 1 R3C130[1][A] test[3].u_mac_rx_model/shift_reg_pause_5_s1/CLK
1.487 0.025 tHld 1 R3C130[1][A] test[3].u_mac_rx_model/shift_reg_pause_5_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.462, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.462, 100.000%

Path7

Path Summary:

Slack 0.275
Data Arrival Time 1.759
Data Required Time 1.484
From test[3].u_mac_rx_model/pause_address_21_s1
To test[3].u_mac_rx_model/pause_address_21_s1
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.459 1.459 tNET RR 1 R7C129[0][A] test[3].u_mac_rx_model/pause_address_21_s1/CLK
1.600 0.141 tC2Q RF 5 R7C129[0][A] test[3].u_mac_rx_model/pause_address_21_s1/Q
1.606 0.006 tNET FF 1 R7C129[0][A] test[3].u_mac_rx_model/n1436_s0/I2
1.759 0.153 tINS FF 1 R7C129[0][A] test[3].u_mac_rx_model/n1436_s0/F
1.759 0.000 tNET FF 1 R7C129[0][A] test[3].u_mac_rx_model/pause_address_21_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.459 1.459 tNET RR 1 R7C129[0][A] test[3].u_mac_rx_model/pause_address_21_s1/CLK
1.484 0.025 tHld 1 R7C129[0][A] test[3].u_mac_rx_model/pause_address_21_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.459, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.459, 100.000%

Path8

Path Summary:

Slack 0.275
Data Arrival Time 1.754
Data Required Time 1.479
From test[3].u_mac_rx_model/pause_address_47_s1
To test[3].u_mac_rx_model/pause_address_47_s1
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.454 1.454 tNET RR 1 R8C127[1][A] test[3].u_mac_rx_model/pause_address_47_s1/CLK
1.595 0.141 tC2Q RF 2 R8C127[1][A] test[3].u_mac_rx_model/pause_address_47_s1/Q
1.601 0.006 tNET FF 1 R8C127[1][A] test[3].u_mac_rx_model/n1410_s0/I3
1.754 0.153 tINS FF 1 R8C127[1][A] test[3].u_mac_rx_model/n1410_s0/F
1.754 0.000 tNET FF 1 R8C127[1][A] test[3].u_mac_rx_model/pause_address_47_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.454 1.454 tNET RR 1 R8C127[1][A] test[3].u_mac_rx_model/pause_address_47_s1/CLK
1.479 0.025 tHld 1 R8C127[1][A] test[3].u_mac_rx_model/pause_address_47_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.454, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.454, 100.000%

Path9

Path Summary:

Slack 0.275
Data Arrival Time 1.761
Data Required Time 1.486
From test[3].u_mac_rx_model/pause_value_10_s1
To test[3].u_mac_rx_model/pause_value_10_s1
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.461 1.461 tNET RR 1 R6C135[1][A] test[3].u_mac_rx_model/pause_value_10_s1/CLK
1.602 0.141 tC2Q RF 7 R6C135[1][A] test[3].u_mac_rx_model/pause_value_10_s1/Q
1.608 0.006 tNET FF 1 R6C135[1][A] test[3].u_mac_rx_model/n1328_s1/I0
1.761 0.153 tINS FF 1 R6C135[1][A] test[3].u_mac_rx_model/n1328_s1/F
1.761 0.000 tNET FF 1 R6C135[1][A] test[3].u_mac_rx_model/pause_value_10_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.461 1.461 tNET RR 1 R6C135[1][A] test[3].u_mac_rx_model/pause_value_10_s1/CLK
1.486 0.025 tHld 1 R6C135[1][A] test[3].u_mac_rx_model/pause_value_10_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.461, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.461, 100.000%

Path10

Path Summary:

Slack 0.275
Data Arrival Time 1.760
Data Required Time 1.485
From test[3].u_mac_rx_model/shift_reg_4_s1
To test[3].u_mac_rx_model/shift_reg_4_s1
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.460 1.460 tNET RR 1 R4C138[1][A] test[3].u_mac_rx_model/shift_reg_4_s1/CLK
1.601 0.141 tC2Q RF 2 R4C138[1][A] test[3].u_mac_rx_model/shift_reg_4_s1/Q
1.607 0.006 tNET FF 1 R4C138[1][A] test[3].u_mac_rx_model/n883_s3/I0
1.760 0.153 tINS FF 1 R4C138[1][A] test[3].u_mac_rx_model/n883_s3/F
1.760 0.000 tNET FF 1 R4C138[1][A] test[3].u_mac_rx_model/shift_reg_4_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.460 1.460 tNET RR 1 R4C138[1][A] test[3].u_mac_rx_model/shift_reg_4_s1/CLK
1.485 0.025 tHld 1 R4C138[1][A] test[3].u_mac_rx_model/shift_reg_4_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.460, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.460, 100.000%

Path11

Path Summary:

Slack 0.275
Data Arrival Time 1.768
Data Required Time 1.493
From test[3].u_mac_rx_model/shift_reg_7_s1
To test[3].u_mac_rx_model/shift_reg_7_s1
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.468 1.468 tNET RR 1 R4C140[0][A] test[3].u_mac_rx_model/shift_reg_7_s1/CLK
1.609 0.141 tC2Q RF 2 R4C140[0][A] test[3].u_mac_rx_model/shift_reg_7_s1/Q
1.615 0.006 tNET FF 1 R4C140[0][A] test[3].u_mac_rx_model/n880_s3/I0
1.768 0.153 tINS FF 1 R4C140[0][A] test[3].u_mac_rx_model/n880_s3/F
1.768 0.000 tNET FF 1 R4C140[0][A] test[3].u_mac_rx_model/shift_reg_7_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.468 1.468 tNET RR 1 R4C140[0][A] test[3].u_mac_rx_model/shift_reg_7_s1/CLK
1.493 0.025 tHld 1 R4C140[0][A] test[3].u_mac_rx_model/shift_reg_7_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.468, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.468, 100.000%

Path12

Path Summary:

Slack 0.275
Data Arrival Time 1.764
Data Required Time 1.489
From test[3].u_mac_rx_model/shift_reg_8_s1
To test[3].u_mac_rx_model/shift_reg_8_s1
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.464 1.464 tNET RR 1 R4C137[1][A] test[3].u_mac_rx_model/shift_reg_8_s1/CLK
1.605 0.141 tC2Q RF 2 R4C137[1][A] test[3].u_mac_rx_model/shift_reg_8_s1/Q
1.611 0.006 tNET FF 1 R4C137[1][A] test[3].u_mac_rx_model/n879_s2/I0
1.764 0.153 tINS FF 1 R4C137[1][A] test[3].u_mac_rx_model/n879_s2/F
1.764 0.000 tNET FF 1 R4C137[1][A] test[3].u_mac_rx_model/shift_reg_8_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.464 1.464 tNET RR 1 R4C137[1][A] test[3].u_mac_rx_model/shift_reg_8_s1/CLK
1.489 0.025 tHld 1 R4C137[1][A] test[3].u_mac_rx_model/shift_reg_8_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.464, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.464, 100.000%

Path13

Path Summary:

Slack 0.275
Data Arrival Time 1.766
Data Required Time 1.491
From test[3].u_mac_rx_model/shift_reg_10_s1
To test[3].u_mac_rx_model/shift_reg_10_s1
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.466 1.466 tNET RR 1 R3C139[0][A] test[3].u_mac_rx_model/shift_reg_10_s1/CLK
1.607 0.141 tC2Q RF 2 R3C139[0][A] test[3].u_mac_rx_model/shift_reg_10_s1/Q
1.613 0.006 tNET FF 1 R3C139[0][A] test[3].u_mac_rx_model/n877_s2/I0
1.766 0.153 tINS FF 1 R3C139[0][A] test[3].u_mac_rx_model/n877_s2/F
1.766 0.000 tNET FF 1 R3C139[0][A] test[3].u_mac_rx_model/shift_reg_10_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.466 1.466 tNET RR 1 R3C139[0][A] test[3].u_mac_rx_model/shift_reg_10_s1/CLK
1.491 0.025 tHld 1 R3C139[0][A] test[3].u_mac_rx_model/shift_reg_10_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.466, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.466, 100.000%

Path14

Path Summary:

Slack 0.275
Data Arrival Time 1.763
Data Required Time 1.488
From test[3].u_mac_rx_model/shift_reg_13_s1
To test[3].u_mac_rx_model/shift_reg_13_s1
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.463 1.463 tNET RR 1 R5C139[0][A] test[3].u_mac_rx_model/shift_reg_13_s1/CLK
1.604 0.141 tC2Q RF 2 R5C139[0][A] test[3].u_mac_rx_model/shift_reg_13_s1/Q
1.610 0.006 tNET FF 1 R5C139[0][A] test[3].u_mac_rx_model/n874_s2/I0
1.763 0.153 tINS FF 1 R5C139[0][A] test[3].u_mac_rx_model/n874_s2/F
1.763 0.000 tNET FF 1 R5C139[0][A] test[3].u_mac_rx_model/shift_reg_13_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.463 1.463 tNET RR 1 R5C139[0][A] test[3].u_mac_rx_model/shift_reg_13_s1/CLK
1.488 0.025 tHld 1 R5C139[0][A] test[3].u_mac_rx_model/shift_reg_13_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.463, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.463, 100.000%

Path15

Path Summary:

Slack 0.275
Data Arrival Time 1.760
Data Required Time 1.485
From test[3].u_mac_rx_model/shift_reg_20_s1
To test[3].u_mac_rx_model/shift_reg_20_s1
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.460 1.460 tNET RR 1 R4C138[0][A] test[3].u_mac_rx_model/shift_reg_20_s1/CLK
1.601 0.141 tC2Q RF 2 R4C138[0][A] test[3].u_mac_rx_model/shift_reg_20_s1/Q
1.607 0.006 tNET FF 1 R4C138[0][A] test[3].u_mac_rx_model/n867_s2/I0
1.760 0.153 tINS FF 1 R4C138[0][A] test[3].u_mac_rx_model/n867_s2/F
1.760 0.000 tNET FF 1 R4C138[0][A] test[3].u_mac_rx_model/shift_reg_20_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.460 1.460 tNET RR 1 R4C138[0][A] test[3].u_mac_rx_model/shift_reg_20_s1/CLK
1.485 0.025 tHld 1 R4C138[0][A] test[3].u_mac_rx_model/shift_reg_20_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.460, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.460, 100.000%

Path16

Path Summary:

Slack 0.275
Data Arrival Time 1.759
Data Required Time 1.484
From test[3].u_mac_rx_model/shift_reg_21_s1
To test[3].u_mac_rx_model/shift_reg_21_s1
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.459 1.459 tNET RR 1 R5C138[1][A] test[3].u_mac_rx_model/shift_reg_21_s1/CLK
1.600 0.141 tC2Q RF 2 R5C138[1][A] test[3].u_mac_rx_model/shift_reg_21_s1/Q
1.606 0.006 tNET FF 1 R5C138[1][A] test[3].u_mac_rx_model/n866_s1/I0
1.759 0.153 tINS FF 1 R5C138[1][A] test[3].u_mac_rx_model/n866_s1/F
1.759 0.000 tNET FF 1 R5C138[1][A] test[3].u_mac_rx_model/shift_reg_21_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.459 1.459 tNET RR 1 R5C138[1][A] test[3].u_mac_rx_model/shift_reg_21_s1/CLK
1.484 0.025 tHld 1 R5C138[1][A] test[3].u_mac_rx_model/shift_reg_21_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.459, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.459, 100.000%

Path17

Path Summary:

Slack 0.275
Data Arrival Time 1.764
Data Required Time 1.489
From test[3].u_mac_rx_model/shift_reg_25_s1
To test[3].u_mac_rx_model/shift_reg_25_s1
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.464 1.464 tNET RR 1 R4C139[0][A] test[3].u_mac_rx_model/shift_reg_25_s1/CLK
1.605 0.141 tC2Q RF 2 R4C139[0][A] test[3].u_mac_rx_model/shift_reg_25_s1/Q
1.611 0.006 tNET FF 1 R4C139[0][A] test[3].u_mac_rx_model/n862_s2/I0
1.764 0.153 tINS FF 1 R4C139[0][A] test[3].u_mac_rx_model/n862_s2/F
1.764 0.000 tNET FF 1 R4C139[0][A] test[3].u_mac_rx_model/shift_reg_25_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.464 1.464 tNET RR 1 R4C139[0][A] test[3].u_mac_rx_model/shift_reg_25_s1/CLK
1.489 0.025 tHld 1 R4C139[0][A] test[3].u_mac_rx_model/shift_reg_25_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.464, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.464, 100.000%

Path18

Path Summary:

Slack 0.275
Data Arrival Time 1.764
Data Required Time 1.489
From test[3].u_mac_rx_model/shift_reg_33_s1
To test[3].u_mac_rx_model/shift_reg_33_s1
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.464 1.464 tNET RR 1 R4C137[0][A] test[3].u_mac_rx_model/shift_reg_33_s1/CLK
1.605 0.141 tC2Q RF 2 R4C137[0][A] test[3].u_mac_rx_model/shift_reg_33_s1/Q
1.611 0.006 tNET FF 1 R4C137[0][A] test[3].u_mac_rx_model/n854_s2/I0
1.764 0.153 tINS FF 1 R4C137[0][A] test[3].u_mac_rx_model/n854_s2/F
1.764 0.000 tNET FF 1 R4C137[0][A] test[3].u_mac_rx_model/shift_reg_33_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.464 1.464 tNET RR 1 R4C137[0][A] test[3].u_mac_rx_model/shift_reg_33_s1/CLK
1.489 0.025 tHld 1 R4C137[0][A] test[3].u_mac_rx_model/shift_reg_33_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.464, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.464, 100.000%

Path19

Path Summary:

Slack 0.275
Data Arrival Time 1.759
Data Required Time 1.484
From test[3].u_mac_rx_model/shift_reg_39_s1
To test[3].u_mac_rx_model/shift_reg_39_s1
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.459 1.459 tNET RR 1 R5C138[0][A] test[3].u_mac_rx_model/shift_reg_39_s1/CLK
1.600 0.141 tC2Q RF 2 R5C138[0][A] test[3].u_mac_rx_model/shift_reg_39_s1/Q
1.606 0.006 tNET FF 1 R5C138[0][A] test[3].u_mac_rx_model/n848_s2/I0
1.759 0.153 tINS FF 1 R5C138[0][A] test[3].u_mac_rx_model/n848_s2/F
1.759 0.000 tNET FF 1 R5C138[0][A] test[3].u_mac_rx_model/shift_reg_39_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.459 1.459 tNET RR 1 R5C138[0][A] test[3].u_mac_rx_model/shift_reg_39_s1/CLK
1.484 0.025 tHld 1 R5C138[0][A] test[3].u_mac_rx_model/shift_reg_39_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.459, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.459, 100.000%

Path20

Path Summary:

Slack 0.275
Data Arrival Time 1.768
Data Required Time 1.493
From test[3].u_mac_rx_model/shift_reg_40_s1
To test[3].u_mac_rx_model/shift_reg_40_s1
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.468 1.468 tNET RR 1 R4C136[0][A] test[3].u_mac_rx_model/shift_reg_40_s1/CLK
1.609 0.141 tC2Q RF 2 R4C136[0][A] test[3].u_mac_rx_model/shift_reg_40_s1/Q
1.615 0.006 tNET FF 1 R4C136[0][A] test[3].u_mac_rx_model/n847_s1/I0
1.768 0.153 tINS FF 1 R4C136[0][A] test[3].u_mac_rx_model/n847_s1/F
1.768 0.000 tNET FF 1 R4C136[0][A] test[3].u_mac_rx_model/shift_reg_40_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.468 1.468 tNET RR 1 R4C136[0][A] test[3].u_mac_rx_model/shift_reg_40_s1/CLK
1.493 0.025 tHld 1 R4C136[0][A] test[3].u_mac_rx_model/shift_reg_40_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.468, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.468, 100.000%

Path21

Path Summary:

Slack 0.275
Data Arrival Time 1.768
Data Required Time 1.493
From test[3].u_mac_rx_model/shift_reg_45_s1
To test[3].u_mac_rx_model/shift_reg_45_s1
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.468 1.468 tNET RR 1 R4C136[1][A] test[3].u_mac_rx_model/shift_reg_45_s1/CLK
1.609 0.141 tC2Q RF 2 R4C136[1][A] test[3].u_mac_rx_model/shift_reg_45_s1/Q
1.615 0.006 tNET FF 1 R4C136[1][A] test[3].u_mac_rx_model/n842_s1/I0
1.768 0.153 tINS FF 1 R4C136[1][A] test[3].u_mac_rx_model/n842_s1/F
1.768 0.000 tNET FF 1 R4C136[1][A] test[3].u_mac_rx_model/shift_reg_45_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.468 1.468 tNET RR 1 R4C136[1][A] test[3].u_mac_rx_model/shift_reg_45_s1/CLK
1.493 0.025 tHld 1 R4C136[1][A] test[3].u_mac_rx_model/shift_reg_45_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.468, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.468, 100.000%

Path22

Path Summary:

Slack 0.275
Data Arrival Time 1.766
Data Required Time 1.491
From test[3].u_mac_rx_model/shift_reg_46_s1
To test[3].u_mac_rx_model/shift_reg_46_s1
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.466 1.466 tNET RR 1 R3C137[0][A] test[3].u_mac_rx_model/shift_reg_46_s1/CLK
1.607 0.141 tC2Q RF 2 R3C137[0][A] test[3].u_mac_rx_model/shift_reg_46_s1/Q
1.613 0.006 tNET FF 1 R3C137[0][A] test[3].u_mac_rx_model/n841_s2/I0
1.766 0.153 tINS FF 1 R3C137[0][A] test[3].u_mac_rx_model/n841_s2/F
1.766 0.000 tNET FF 1 R3C137[0][A] test[3].u_mac_rx_model/shift_reg_46_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.466 1.466 tNET RR 1 R3C137[0][A] test[3].u_mac_rx_model/shift_reg_46_s1/CLK
1.491 0.025 tHld 1 R3C137[0][A] test[3].u_mac_rx_model/shift_reg_46_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.466, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.466, 100.000%

Path23

Path Summary:

Slack 0.275
Data Arrival Time 1.766
Data Required Time 1.491
From test[3].u_mac_rx_model/shift_reg_49_s1
To test[3].u_mac_rx_model/shift_reg_49_s1
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.466 1.466 tNET RR 1 R3C137[1][A] test[3].u_mac_rx_model/shift_reg_49_s1/CLK
1.607 0.141 tC2Q RF 2 R3C137[1][A] test[3].u_mac_rx_model/shift_reg_49_s1/Q
1.613 0.006 tNET FF 1 R3C137[1][A] test[3].u_mac_rx_model/n838_s2/I0
1.766 0.153 tINS FF 1 R3C137[1][A] test[3].u_mac_rx_model/n838_s2/F
1.766 0.000 tNET FF 1 R3C137[1][A] test[3].u_mac_rx_model/shift_reg_49_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.466 1.466 tNET RR 1 R3C137[1][A] test[3].u_mac_rx_model/shift_reg_49_s1/CLK
1.491 0.025 tHld 1 R3C137[1][A] test[3].u_mac_rx_model/shift_reg_49_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.466, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.466, 100.000%

Path24

Path Summary:

Slack 0.275
Data Arrival Time 1.770
Data Required Time 1.495
From test[3].u_mac_rx_model/shift_reg_51_s1
To test[3].u_mac_rx_model/shift_reg_51_s1
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.470 1.470 tNET RR 1 R3C136[0][A] test[3].u_mac_rx_model/shift_reg_51_s1/CLK
1.611 0.141 tC2Q RF 2 R3C136[0][A] test[3].u_mac_rx_model/shift_reg_51_s1/Q
1.617 0.006 tNET FF 1 R3C136[0][A] test[3].u_mac_rx_model/n836_s1/I0
1.770 0.153 tINS FF 1 R3C136[0][A] test[3].u_mac_rx_model/n836_s1/F
1.770 0.000 tNET FF 1 R3C136[0][A] test[3].u_mac_rx_model/shift_reg_51_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.470 1.470 tNET RR 1 R3C136[0][A] test[3].u_mac_rx_model/shift_reg_51_s1/CLK
1.495 0.025 tHld 1 R3C136[0][A] test[3].u_mac_rx_model/shift_reg_51_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.470, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.470, 100.000%

Path25

Path Summary:

Slack 0.275
Data Arrival Time 1.767
Data Required Time 1.492
From test[3].u_mac_rx_model/shift_reg_57_s1
To test[3].u_mac_rx_model/shift_reg_57_s1
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.467 1.467 tNET RR 1 R5C136[0][A] test[3].u_mac_rx_model/shift_reg_57_s1/CLK
1.608 0.141 tC2Q RF 2 R5C136[0][A] test[3].u_mac_rx_model/shift_reg_57_s1/Q
1.614 0.006 tNET FF 1 R5C136[0][A] test[3].u_mac_rx_model/n830_s1/I0
1.767 0.153 tINS FF 1 R5C136[0][A] test[3].u_mac_rx_model/n830_s1/F
1.767 0.000 tNET FF 1 R5C136[0][A] test[3].u_mac_rx_model/shift_reg_57_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.467 1.467 tNET RR 1 R5C136[0][A] test[3].u_mac_rx_model/shift_reg_57_s1/CLK
1.492 0.025 tHld 1 R5C136[0][A] test[3].u_mac_rx_model/shift_reg_57_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.467, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.467, 100.000%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 0.117
Data Arrival Time 11.373
Data Required Time 11.490
From rx_mac_rst_n_3_s0
To test[3].u_mac_rx_model/rx_cnt_0_s3
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.931 3.931 tNET RR 1 R22C132[0][A] rx_mac_rst_n_3_s0/CLK
4.299 0.368 tC2Q RF 780 R22C132[0][A] rx_mac_rst_n_3_s0/Q
11.373 7.074 tNET FF 1 R7C158[0][A] test[3].u_mac_rx_model/rx_cnt_0_s3/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 rx_mac_clk
8.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
11.837 3.838 tNET RR 1 R7C158[0][A] test[3].u_mac_rx_model/rx_cnt_0_s3/CLK
11.490 -0.347 tSu 1 R7C158[0][A] test[3].u_mac_rx_model/rx_cnt_0_s3

Path Statistics:

Clock Skew -0.094
Setup Relationship 8.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.931, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 7.074, 95.061%; tC2Q: 0.368, 4.939%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.838, 100.000%

Path2

Path Summary:

Slack 0.117
Data Arrival Time 11.373
Data Required Time 11.490
From rx_mac_rst_n_3_s0
To test[3].u_mac_rx_model/rx_cnt_1_s3
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.931 3.931 tNET RR 1 R22C132[0][A] rx_mac_rst_n_3_s0/CLK
4.299 0.368 tC2Q RF 780 R22C132[0][A] rx_mac_rst_n_3_s0/Q
11.373 7.074 tNET FF 1 R7C158[1][A] test[3].u_mac_rx_model/rx_cnt_1_s3/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 rx_mac_clk
8.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
11.837 3.838 tNET RR 1 R7C158[1][A] test[3].u_mac_rx_model/rx_cnt_1_s3/CLK
11.490 -0.347 tSu 1 R7C158[1][A] test[3].u_mac_rx_model/rx_cnt_1_s3

Path Statistics:

Clock Skew -0.094
Setup Relationship 8.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.931, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 7.074, 95.061%; tC2Q: 0.368, 4.939%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.838, 100.000%

Path3

Path Summary:

Slack 0.117
Data Arrival Time 11.373
Data Required Time 11.490
From rx_mac_rst_n_3_s0
To test[3].u_mac_rx_model/rx_cnt_3_s1
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.931 3.931 tNET RR 1 R22C132[0][A] rx_mac_rst_n_3_s0/CLK
4.299 0.368 tC2Q RF 780 R22C132[0][A] rx_mac_rst_n_3_s0/Q
11.373 7.074 tNET FF 1 R7C158[2][B] test[3].u_mac_rx_model/rx_cnt_3_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 rx_mac_clk
8.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
11.837 3.838 tNET RR 1 R7C158[2][B] test[3].u_mac_rx_model/rx_cnt_3_s1/CLK
11.490 -0.347 tSu 1 R7C158[2][B] test[3].u_mac_rx_model/rx_cnt_3_s1

Path Statistics:

Clock Skew -0.094
Setup Relationship 8.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.931, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 7.074, 95.061%; tC2Q: 0.368, 4.939%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.838, 100.000%

Path4

Path Summary:

Slack 0.117
Data Arrival Time 11.373
Data Required Time 11.490
From rx_mac_rst_n_3_s0
To test[3].u_mac_rx_model/rx_cnt_9_s1
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.931 3.931 tNET RR 1 R22C132[0][A] rx_mac_rst_n_3_s0/CLK
4.299 0.368 tC2Q RF 780 R22C132[0][A] rx_mac_rst_n_3_s0/Q
11.373 7.074 tNET FF 1 R7C158[2][A] test[3].u_mac_rx_model/rx_cnt_9_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 rx_mac_clk
8.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
11.837 3.838 tNET RR 1 R7C158[2][A] test[3].u_mac_rx_model/rx_cnt_9_s1/CLK
11.490 -0.347 tSu 1 R7C158[2][A] test[3].u_mac_rx_model/rx_cnt_9_s1

Path Statistics:

Clock Skew -0.094
Setup Relationship 8.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.931, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 7.074, 95.061%; tC2Q: 0.368, 4.939%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.838, 100.000%

Path5

Path Summary:

Slack 0.339
Data Arrival Time 11.154
Data Required Time 11.493
From rx_mac_rst_n_3_s0
To test[3].u_mac_rx_model/rx_cnt_10_s3
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.931 3.931 tNET RR 1 R22C132[0][A] rx_mac_rst_n_3_s0/CLK
4.299 0.368 tC2Q RF 780 R22C132[0][A] rx_mac_rst_n_3_s0/Q
11.154 6.855 tNET FF 1 R6C158[0][B] test[3].u_mac_rx_model/rx_cnt_10_s3/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 rx_mac_clk
8.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
11.840 3.840 tNET RR 1 R6C158[0][B] test[3].u_mac_rx_model/rx_cnt_10_s3/CLK
11.493 -0.347 tSu 1 R6C158[0][B] test[3].u_mac_rx_model/rx_cnt_10_s3

Path Statistics:

Clock Skew -0.091
Setup Relationship 8.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.931, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 6.855, 94.912%; tC2Q: 0.368, 5.088%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.840, 100.000%

Path6

Path Summary:

Slack 0.339
Data Arrival Time 11.154
Data Required Time 11.493
From rx_mac_rst_n_3_s0
To test[3].u_mac_rx_model/rx_cnt_14_s1
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.931 3.931 tNET RR 1 R22C132[0][A] rx_mac_rst_n_3_s0/CLK
4.299 0.368 tC2Q RF 780 R22C132[0][A] rx_mac_rst_n_3_s0/Q
11.154 6.855 tNET FF 1 R6C158[2][A] test[3].u_mac_rx_model/rx_cnt_14_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 rx_mac_clk
8.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
11.840 3.840 tNET RR 1 R6C158[2][A] test[3].u_mac_rx_model/rx_cnt_14_s1/CLK
11.493 -0.347 tSu 1 R6C158[2][A] test[3].u_mac_rx_model/rx_cnt_14_s1

Path Statistics:

Clock Skew -0.091
Setup Relationship 8.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.931, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 6.855, 94.912%; tC2Q: 0.368, 5.088%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.840, 100.000%

Path7

Path Summary:

Slack 0.339
Data Arrival Time 11.154
Data Required Time 11.493
From rx_mac_rst_n_3_s0
To test[3].u_mac_rx_model/rx_cnt_15_s1
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.931 3.931 tNET RR 1 R22C132[0][A] rx_mac_rst_n_3_s0/CLK
4.299 0.368 tC2Q RF 780 R22C132[0][A] rx_mac_rst_n_3_s0/Q
11.154 6.855 tNET FF 1 R6C158[3][A] test[3].u_mac_rx_model/rx_cnt_15_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 rx_mac_clk
8.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
11.840 3.840 tNET RR 1 R6C158[3][A] test[3].u_mac_rx_model/rx_cnt_15_s1/CLK
11.493 -0.347 tSu 1 R6C158[3][A] test[3].u_mac_rx_model/rx_cnt_15_s1

Path Statistics:

Clock Skew -0.091
Setup Relationship 8.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.931, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 6.855, 94.912%; tC2Q: 0.368, 5.088%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.840, 100.000%

Path8

Path Summary:

Slack 0.339
Data Arrival Time 11.154
Data Required Time 11.493
From rx_mac_rst_n_3_s0
To test[3].u_mac_rx_model/rx_cnt_16_s1
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.931 3.931 tNET RR 1 R22C132[0][A] rx_mac_rst_n_3_s0/CLK
4.299 0.368 tC2Q RF 780 R22C132[0][A] rx_mac_rst_n_3_s0/Q
11.154 6.855 tNET FF 1 R6C158[2][B] test[3].u_mac_rx_model/rx_cnt_16_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 rx_mac_clk
8.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
11.840 3.840 tNET RR 1 R6C158[2][B] test[3].u_mac_rx_model/rx_cnt_16_s1/CLK
11.493 -0.347 tSu 1 R6C158[2][B] test[3].u_mac_rx_model/rx_cnt_16_s1

Path Statistics:

Clock Skew -0.091
Setup Relationship 8.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.931, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 6.855, 94.912%; tC2Q: 0.368, 5.088%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.840, 100.000%

Path9

Path Summary:

Slack 0.341
Data Arrival Time 11.154
Data Required Time 11.495
From rx_mac_rst_n_3_s0
To test[3].u_mac_rx_model/rx_cnt_13_s3
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.931 3.931 tNET RR 1 R22C132[0][A] rx_mac_rst_n_3_s0/CLK
4.299 0.368 tC2Q RF 780 R22C132[0][A] rx_mac_rst_n_3_s0/Q
11.154 6.855 tNET FF 1 R5C158[0][B] test[3].u_mac_rx_model/rx_cnt_13_s3/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 rx_mac_clk
8.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
11.843 3.843 tNET RR 1 R5C158[0][B] test[3].u_mac_rx_model/rx_cnt_13_s3/CLK
11.495 -0.347 tSu 1 R5C158[0][B] test[3].u_mac_rx_model/rx_cnt_13_s3

Path Statistics:

Clock Skew -0.089
Setup Relationship 8.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.931, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 6.855, 94.912%; tC2Q: 0.368, 5.088%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.843, 100.000%

Path10

Path Summary:

Slack 0.341
Data Arrival Time 11.154
Data Required Time 11.495
From rx_mac_rst_n_3_s0
To test[3].u_mac_rx_model/rx_cnt_29_s3
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.931 3.931 tNET RR 1 R22C132[0][A] rx_mac_rst_n_3_s0/CLK
4.299 0.368 tC2Q RF 780 R22C132[0][A] rx_mac_rst_n_3_s0/Q
11.154 6.855 tNET FF 1 R5C158[0][A] test[3].u_mac_rx_model/rx_cnt_29_s3/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 rx_mac_clk
8.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
11.843 3.843 tNET RR 1 R5C158[0][A] test[3].u_mac_rx_model/rx_cnt_29_s3/CLK
11.495 -0.347 tSu 1 R5C158[0][A] test[3].u_mac_rx_model/rx_cnt_29_s3

Path Statistics:

Clock Skew -0.089
Setup Relationship 8.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.931, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 6.855, 94.912%; tC2Q: 0.368, 5.088%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.843, 100.000%

Path11

Path Summary:

Slack 0.341
Data Arrival Time 11.154
Data Required Time 11.495
From rx_mac_rst_n_3_s0
To test[3].u_mac_rx_model/rx_cnt_30_s1
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.931 3.931 tNET RR 1 R22C132[0][A] rx_mac_rst_n_3_s0/CLK
4.299 0.368 tC2Q RF 780 R22C132[0][A] rx_mac_rst_n_3_s0/Q
11.154 6.855 tNET FF 1 R5C158[1][A] test[3].u_mac_rx_model/rx_cnt_30_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 rx_mac_clk
8.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
11.843 3.843 tNET RR 1 R5C158[1][A] test[3].u_mac_rx_model/rx_cnt_30_s1/CLK
11.495 -0.347 tSu 1 R5C158[1][A] test[3].u_mac_rx_model/rx_cnt_30_s1

Path Statistics:

Clock Skew -0.089
Setup Relationship 8.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.931, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 6.855, 94.912%; tC2Q: 0.368, 5.088%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.843, 100.000%

Path12

Path Summary:

Slack 0.341
Data Arrival Time 11.154
Data Required Time 11.495
From rx_mac_rst_n_3_s0
To test[3].u_mac_rx_model/data_length_0_s1
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.931 3.931 tNET RR 1 R22C132[0][A] rx_mac_rst_n_3_s0/CLK
4.299 0.368 tC2Q RF 780 R22C132[0][A] rx_mac_rst_n_3_s0/Q
11.154 6.855 tNET FF 1 R5C158[2][A] test[3].u_mac_rx_model/data_length_0_s1/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 rx_mac_clk
8.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
11.843 3.843 tNET RR 1 R5C158[2][A] test[3].u_mac_rx_model/data_length_0_s1/CLK
11.495 -0.347 tSu 1 R5C158[2][A] test[3].u_mac_rx_model/data_length_0_s1

Path Statistics:

Clock Skew -0.089
Setup Relationship 8.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.931, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 6.855, 94.912%; tC2Q: 0.368, 5.088%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.843, 100.000%

Path13

Path Summary:

Slack 0.382
Data Arrival Time 11.119
Data Required Time 11.502
From rx_mac_rst_n_3_s0
To test[3].u_mac_rx_model/rx_cnt_11_s1
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.931 3.931 tNET RR 1 R22C132[0][A] rx_mac_rst_n_3_s0/CLK
4.299 0.368 tC2Q RF 780 R22C132[0][A] rx_mac_rst_n_3_s0/Q
11.119 6.821 tNET FF 1 R6C157[0][A] test[3].u_mac_rx_model/rx_cnt_11_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 rx_mac_clk
8.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
11.849 3.849 tNET RR 1 R6C157[0][A] test[3].u_mac_rx_model/rx_cnt_11_s1/CLK
11.502 -0.347 tSu 1 R6C157[0][A] test[3].u_mac_rx_model/rx_cnt_11_s1

Path Statistics:

Clock Skew -0.082
Setup Relationship 8.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.931, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 6.821, 94.887%; tC2Q: 0.368, 5.113%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.849, 100.000%

Path14

Path Summary:

Slack 0.382
Data Arrival Time 11.119
Data Required Time 11.502
From rx_mac_rst_n_3_s0
To test[3].u_mac_rx_model/rx_cnt_12_s1
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.931 3.931 tNET RR 1 R22C132[0][A] rx_mac_rst_n_3_s0/CLK
4.299 0.368 tC2Q RF 780 R22C132[0][A] rx_mac_rst_n_3_s0/Q
11.119 6.821 tNET FF 1 R6C157[2][A] test[3].u_mac_rx_model/rx_cnt_12_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 rx_mac_clk
8.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
11.849 3.849 tNET RR 1 R6C157[2][A] test[3].u_mac_rx_model/rx_cnt_12_s1/CLK
11.502 -0.347 tSu 1 R6C157[2][A] test[3].u_mac_rx_model/rx_cnt_12_s1

Path Statistics:

Clock Skew -0.082
Setup Relationship 8.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.931, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 6.821, 94.887%; tC2Q: 0.368, 5.113%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.849, 100.000%

Path15

Path Summary:

Slack 0.382
Data Arrival Time 11.119
Data Required Time 11.502
From rx_mac_rst_n_3_s0
To test[3].u_mac_rx_model/rx_cnt_27_s1
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.931 3.931 tNET RR 1 R22C132[0][A] rx_mac_rst_n_3_s0/CLK
4.299 0.368 tC2Q RF 780 R22C132[0][A] rx_mac_rst_n_3_s0/Q
11.119 6.821 tNET FF 1 R6C157[0][B] test[3].u_mac_rx_model/rx_cnt_27_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 rx_mac_clk
8.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
11.849 3.849 tNET RR 1 R6C157[0][B] test[3].u_mac_rx_model/rx_cnt_27_s1/CLK
11.502 -0.347 tSu 1 R6C157[0][B] test[3].u_mac_rx_model/rx_cnt_27_s1

Path Statistics:

Clock Skew -0.082
Setup Relationship 8.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.931, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 6.821, 94.887%; tC2Q: 0.368, 5.113%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.849, 100.000%

Path16

Path Summary:

Slack 0.385
Data Arrival Time 11.119
Data Required Time 11.504
From rx_mac_rst_n_3_s0
To test[3].u_mac_rx_model/rx_cnt_31_s4
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.931 3.931 tNET RR 1 R22C132[0][A] rx_mac_rst_n_3_s0/CLK
4.299 0.368 tC2Q RF 780 R22C132[0][A] rx_mac_rst_n_3_s0/Q
11.119 6.821 tNET FF 1 R5C157[1][A] test[3].u_mac_rx_model/rx_cnt_31_s4/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 rx_mac_clk
8.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
11.852 3.852 tNET RR 1 R5C157[1][A] test[3].u_mac_rx_model/rx_cnt_31_s4/CLK
11.504 -0.347 tSu 1 R5C157[1][A] test[3].u_mac_rx_model/rx_cnt_31_s4

Path Statistics:

Clock Skew -0.079
Setup Relationship 8.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.931, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 6.821, 94.887%; tC2Q: 0.368, 5.113%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.852, 100.000%

Path17

Path Summary:

Slack 0.385
Data Arrival Time 11.119
Data Required Time 11.504
From rx_mac_rst_n_3_s0
To test[3].u_mac_rx_model/rx_cnt_28_s1
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.931 3.931 tNET RR 1 R22C132[0][A] rx_mac_rst_n_3_s0/CLK
4.299 0.368 tC2Q RF 780 R22C132[0][A] rx_mac_rst_n_3_s0/Q
11.119 6.821 tNET FF 1 R5C157[0][B] test[3].u_mac_rx_model/rx_cnt_28_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 rx_mac_clk
8.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
11.852 3.852 tNET RR 1 R5C157[0][B] test[3].u_mac_rx_model/rx_cnt_28_s1/CLK
11.504 -0.347 tSu 1 R5C157[0][B] test[3].u_mac_rx_model/rx_cnt_28_s1

Path Statistics:

Clock Skew -0.079
Setup Relationship 8.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.931, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 6.821, 94.887%; tC2Q: 0.368, 5.113%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.852, 100.000%

Path18

Path Summary:

Slack 0.389
Data Arrival Time 11.120
Data Required Time 11.509
From rx_mac_rst_n_3_s0
To test[3].u_mac_rx_model/data_length_1_s1
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.931 3.931 tNET RR 1 R22C132[0][A] rx_mac_rst_n_3_s0/CLK
4.299 0.368 tC2Q RF 780 R22C132[0][A] rx_mac_rst_n_3_s0/Q
11.120 6.821 tNET FF 1 R3C159[0][A] test[3].u_mac_rx_model/data_length_1_s1/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 rx_mac_clk
8.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
11.857 3.857 tNET RR 1 R3C159[0][A] test[3].u_mac_rx_model/data_length_1_s1/CLK
11.509 -0.347 tSu 1 R3C159[0][A] test[3].u_mac_rx_model/data_length_1_s1

Path Statistics:

Clock Skew -0.074
Setup Relationship 8.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.931, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 6.821, 94.888%; tC2Q: 0.368, 5.112%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.857, 100.000%

Path19

Path Summary:

Slack 0.389
Data Arrival Time 11.120
Data Required Time 11.509
From rx_mac_rst_n_3_s0
To test[3].u_mac_rx_model/data_length_13_s1
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.931 3.931 tNET RR 1 R22C132[0][A] rx_mac_rst_n_3_s0/CLK
4.299 0.368 tC2Q RF 780 R22C132[0][A] rx_mac_rst_n_3_s0/Q
11.120 6.821 tNET FF 1 R3C159[2][B] test[3].u_mac_rx_model/data_length_13_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 rx_mac_clk
8.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
11.857 3.857 tNET RR 1 R3C159[2][B] test[3].u_mac_rx_model/data_length_13_s1/CLK
11.509 -0.347 tSu 1 R3C159[2][B] test[3].u_mac_rx_model/data_length_13_s1

Path Statistics:

Clock Skew -0.074
Setup Relationship 8.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.931, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 6.821, 94.888%; tC2Q: 0.368, 5.112%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.857, 100.000%

Path20

Path Summary:

Slack 0.389
Data Arrival Time 11.120
Data Required Time 11.509
From rx_mac_rst_n_3_s0
To test[3].u_mac_rx_model/data_length_14_s1
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.931 3.931 tNET RR 1 R22C132[0][A] rx_mac_rst_n_3_s0/CLK
4.299 0.368 tC2Q RF 780 R22C132[0][A] rx_mac_rst_n_3_s0/Q
11.120 6.821 tNET FF 1 R3C159[2][A] test[3].u_mac_rx_model/data_length_14_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 rx_mac_clk
8.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
11.857 3.857 tNET RR 1 R3C159[2][A] test[3].u_mac_rx_model/data_length_14_s1/CLK
11.509 -0.347 tSu 1 R3C159[2][A] test[3].u_mac_rx_model/data_length_14_s1

Path Statistics:

Clock Skew -0.074
Setup Relationship 8.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.931, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 6.821, 94.888%; tC2Q: 0.368, 5.112%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.857, 100.000%

Path21

Path Summary:

Slack 0.389
Data Arrival Time 11.120
Data Required Time 11.509
From rx_mac_rst_n_3_s0
To test[3].u_mac_rx_model/data_length_15_s1
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.931 3.931 tNET RR 1 R22C132[0][A] rx_mac_rst_n_3_s0/CLK
4.299 0.368 tC2Q RF 780 R22C132[0][A] rx_mac_rst_n_3_s0/Q
11.120 6.821 tNET FF 1 R3C159[0][B] test[3].u_mac_rx_model/data_length_15_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 rx_mac_clk
8.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
11.857 3.857 tNET RR 1 R3C159[0][B] test[3].u_mac_rx_model/data_length_15_s1/CLK
11.509 -0.347 tSu 1 R3C159[0][B] test[3].u_mac_rx_model/data_length_15_s1

Path Statistics:

Clock Skew -0.074
Setup Relationship 8.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.931, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 6.821, 94.888%; tC2Q: 0.368, 5.112%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.857, 100.000%

Path22

Path Summary:

Slack 0.389
Data Arrival Time 11.120
Data Required Time 11.509
From rx_mac_rst_n_3_s0
To test[3].u_mac_rx_model/data_length_next_rea_1_s1
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.931 3.931 tNET RR 1 R22C132[0][A] rx_mac_rst_n_3_s0/CLK
4.299 0.368 tC2Q RF 780 R22C132[0][A] rx_mac_rst_n_3_s0/Q
11.120 6.821 tNET FF 1 R3C159[1][A] test[3].u_mac_rx_model/data_length_next_rea_1_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 rx_mac_clk
8.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
11.857 3.857 tNET RR 1 R3C159[1][A] test[3].u_mac_rx_model/data_length_next_rea_1_s1/CLK
11.509 -0.347 tSu 1 R3C159[1][A] test[3].u_mac_rx_model/data_length_next_rea_1_s1

Path Statistics:

Clock Skew -0.074
Setup Relationship 8.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.931, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 6.821, 94.888%; tC2Q: 0.368, 5.112%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.857, 100.000%

Path23

Path Summary:

Slack 0.441
Data Arrival Time 11.073
Data Required Time 11.514
From rx_mac_rst_n_3_s0
To test[3].u_mac_rx_model/rx_cnt_17_s1
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.931 3.931 tNET RR 1 R22C132[0][A] rx_mac_rst_n_3_s0/CLK
4.299 0.368 tC2Q RF 780 R22C132[0][A] rx_mac_rst_n_3_s0/Q
11.073 6.774 tNET FF 1 R5C156[2][A] test[3].u_mac_rx_model/rx_cnt_17_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 rx_mac_clk
8.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
11.861 3.861 tNET RR 1 R5C156[2][A] test[3].u_mac_rx_model/rx_cnt_17_s1/CLK
11.514 -0.347 tSu 1 R5C156[2][A] test[3].u_mac_rx_model/rx_cnt_17_s1

Path Statistics:

Clock Skew -0.070
Setup Relationship 8.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.931, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 6.774, 94.854%; tC2Q: 0.368, 5.146%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.861, 100.000%

Path24

Path Summary:

Slack 0.441
Data Arrival Time 11.073
Data Required Time 11.514
From rx_mac_rst_n_3_s0
To test[3].u_mac_rx_model/rx_cnt_23_s1
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.931 3.931 tNET RR 1 R22C132[0][A] rx_mac_rst_n_3_s0/CLK
4.299 0.368 tC2Q RF 780 R22C132[0][A] rx_mac_rst_n_3_s0/Q
11.073 6.774 tNET FF 1 R5C156[0][B] test[3].u_mac_rx_model/rx_cnt_23_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 rx_mac_clk
8.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
11.861 3.861 tNET RR 1 R5C156[0][B] test[3].u_mac_rx_model/rx_cnt_23_s1/CLK
11.514 -0.347 tSu 1 R5C156[0][B] test[3].u_mac_rx_model/rx_cnt_23_s1

Path Statistics:

Clock Skew -0.070
Setup Relationship 8.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.931, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 6.774, 94.854%; tC2Q: 0.368, 5.146%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.861, 100.000%

Path25

Path Summary:

Slack 0.493
Data Arrival Time 11.007
Data Required Time 11.499
From rx_mac_rst_n_3_s0
To test[3].u_mac_rx_model/rx_cnt_7_s3
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.931 3.931 tNET RR 1 R22C132[0][A] rx_mac_rst_n_3_s0/CLK
4.299 0.368 tC2Q RF 780 R22C132[0][A] rx_mac_rst_n_3_s0/Q
11.007 6.708 tNET FF 1 R7C157[1][B] test[3].u_mac_rx_model/rx_cnt_7_s3/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 rx_mac_clk
8.000 0.000 tCL RR 6471 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
11.847 3.847 tNET RR 1 R7C157[1][B] test[3].u_mac_rx_model/rx_cnt_7_s3/CLK
11.499 -0.347 tSu 1 R7C157[1][B] test[3].u_mac_rx_model/rx_cnt_7_s3

Path Statistics:

Clock Skew -0.084
Setup Relationship 8.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.931, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 6.708, 94.806%; tC2Q: 0.368, 5.194%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.847, 100.000%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 0.376
Data Arrival Time 1.761
Data Required Time 1.385
From tx_mac_rst_n_2_s0
To test[2].u_mac_tx_model/frm_length_last_0_s0
Launch Clk tx_mac_clk:[R]
Latch Clk tx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
1.438 1.438 tNET RR 1 R32C131[3][A] tx_mac_rst_n_2_s0/CLK
1.582 0.144 tC2Q RR 378 R32C131[3][A] tx_mac_rst_n_2_s0/Q
1.761 0.179 tNET RR 1 R32C133[1][B] test[2].u_mac_tx_model/frm_length_last_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
1.438 1.438 tNET RR 1 R32C133[1][B] test[2].u_mac_tx_model/frm_length_last_0_s0/CLK
1.385 -0.053 tHld 1 R32C133[1][B] test[2].u_mac_tx_model/frm_length_last_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.438, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.179, 55.418%; tC2Q: 0.144, 44.582%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.438, 100.000%

Path2

Path Summary:

Slack 0.376
Data Arrival Time 1.761
Data Required Time 1.385
From tx_mac_rst_n_2_s0
To test[2].u_mac_tx_model/frm_length_0_s0
Launch Clk tx_mac_clk:[R]
Latch Clk tx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
1.438 1.438 tNET RR 1 R32C131[3][A] tx_mac_rst_n_2_s0/CLK
1.582 0.144 tC2Q RR 378 R32C131[3][A] tx_mac_rst_n_2_s0/Q
1.761 0.179 tNET RR 1 R32C133[0][A] test[2].u_mac_tx_model/frm_length_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
1.438 1.438 tNET RR 1 R32C133[0][A] test[2].u_mac_tx_model/frm_length_0_s0/CLK
1.385 -0.053 tHld 1 R32C133[0][A] test[2].u_mac_tx_model/frm_length_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.438, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.179, 55.418%; tC2Q: 0.144, 44.582%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.438, 100.000%

Path3

Path Summary:

Slack 0.400
Data Arrival Time 1.789
Data Required Time 1.389
From tx_mac_rst_n_2_s0
To test[2].u_mac_tx_model/tx_data_cnt_10_s1
Launch Clk tx_mac_clk:[R]
Latch Clk tx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
1.438 1.438 tNET RR 1 R32C131[3][A] tx_mac_rst_n_2_s0/CLK
1.582 0.144 tC2Q RR 378 R32C131[3][A] tx_mac_rst_n_2_s0/Q
1.789 0.207 tNET RR 1 R32C134[3][A] test[2].u_mac_tx_model/tx_data_cnt_10_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
1.442 1.442 tNET RR 1 R32C134[3][A] test[2].u_mac_tx_model/tx_data_cnt_10_s1/CLK
1.389 -0.053 tHld 1 R32C134[3][A] test[2].u_mac_tx_model/tx_data_cnt_10_s1

Path Statistics:

Clock Skew 0.004
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.438, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.207, 58.974%; tC2Q: 0.144, 41.026%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.442, 100.000%

Path4

Path Summary:

Slack 0.404
Data Arrival Time 1.789
Data Required Time 1.385
From tx_mac_rst_n_2_s0
To test[2].u_mac_tx_model/tx_data_cnt_11_s1
Launch Clk tx_mac_clk:[R]
Latch Clk tx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
1.438 1.438 tNET RR 1 R32C131[3][A] tx_mac_rst_n_2_s0/CLK
1.582 0.144 tC2Q RR 378 R32C131[3][A] tx_mac_rst_n_2_s0/Q
1.789 0.207 tNET RR 1 R32C135[3][A] test[2].u_mac_tx_model/tx_data_cnt_11_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
1.438 1.438 tNET RR 1 R32C135[3][A] test[2].u_mac_tx_model/tx_data_cnt_11_s1/CLK
1.385 -0.053 tHld 1 R32C135[3][A] test[2].u_mac_tx_model/tx_data_cnt_11_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.438, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.207, 58.974%; tC2Q: 0.144, 41.026%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.438, 100.000%

Path5

Path Summary:

Slack 0.503
Data Arrival Time 1.897
Data Required Time 1.394
From tx_mac_rst_n_2_s0
To test[2].u_mac_tx_model/data_start_byte_1_s0
Launch Clk tx_mac_clk:[R]
Latch Clk tx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
1.438 1.438 tNET RR 1 R32C131[3][A] tx_mac_rst_n_2_s0/CLK
1.582 0.144 tC2Q RR 378 R32C131[3][A] tx_mac_rst_n_2_s0/Q
1.897 0.315 tNET RR 1 R34C134[0][A] test[2].u_mac_tx_model/data_start_byte_1_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
1.447 1.447 tNET RR 1 R34C134[0][A] test[2].u_mac_tx_model/data_start_byte_1_s0/CLK
1.394 -0.053 tHld 1 R34C134[0][A] test[2].u_mac_tx_model/data_start_byte_1_s0

Path Statistics:

Clock Skew 0.009
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.438, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.315, 68.627%; tC2Q: 0.144, 31.373%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.447, 100.000%

Path6

Path Summary:

Slack 0.503
Data Arrival Time 1.897
Data Required Time 1.394
From tx_mac_rst_n_2_s0
To test[2].u_mac_tx_model/data_start_byte_2_s0
Launch Clk tx_mac_clk:[R]
Latch Clk tx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
1.438 1.438 tNET RR 1 R32C131[3][A] tx_mac_rst_n_2_s0/CLK
1.582 0.144 tC2Q RR 378 R32C131[3][A] tx_mac_rst_n_2_s0/Q
1.897 0.315 tNET RR 1 R34C134[0][B] test[2].u_mac_tx_model/data_start_byte_2_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
1.447 1.447 tNET RR 1 R34C134[0][B] test[2].u_mac_tx_model/data_start_byte_2_s0/CLK
1.394 -0.053 tHld 1 R34C134[0][B] test[2].u_mac_tx_model/data_start_byte_2_s0

Path Statistics:

Clock Skew 0.009
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.438, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.315, 68.627%; tC2Q: 0.144, 31.373%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.447, 100.000%

Path7

Path Summary:

Slack 0.503
Data Arrival Time 1.897
Data Required Time 1.394
From tx_mac_rst_n_2_s0
To test[2].u_mac_tx_model/data_start_byte_3_s0
Launch Clk tx_mac_clk:[R]
Latch Clk tx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
1.438 1.438 tNET RR 1 R32C131[3][A] tx_mac_rst_n_2_s0/CLK
1.582 0.144 tC2Q RR 378 R32C131[3][A] tx_mac_rst_n_2_s0/Q
1.897 0.315 tNET RR 1 R34C134[1][A] test[2].u_mac_tx_model/data_start_byte_3_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
1.447 1.447 tNET RR 1 R34C134[1][A] test[2].u_mac_tx_model/data_start_byte_3_s0/CLK
1.394 -0.053 tHld 1 R34C134[1][A] test[2].u_mac_tx_model/data_start_byte_3_s0

Path Statistics:

Clock Skew 0.009
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.438, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.315, 68.627%; tC2Q: 0.144, 31.373%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.447, 100.000%

Path8

Path Summary:

Slack 0.503
Data Arrival Time 1.897
Data Required Time 1.394
From tx_mac_rst_n_2_s0
To test[2].u_mac_tx_model/data_start_byte_4_s0
Launch Clk tx_mac_clk:[R]
Latch Clk tx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
1.438 1.438 tNET RR 1 R32C131[3][A] tx_mac_rst_n_2_s0/CLK
1.582 0.144 tC2Q RR 378 R32C131[3][A] tx_mac_rst_n_2_s0/Q
1.897 0.315 tNET RR 1 R34C134[1][B] test[2].u_mac_tx_model/data_start_byte_4_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
1.447 1.447 tNET RR 1 R34C134[1][B] test[2].u_mac_tx_model/data_start_byte_4_s0/CLK
1.394 -0.053 tHld 1 R34C134[1][B] test[2].u_mac_tx_model/data_start_byte_4_s0

Path Statistics:

Clock Skew 0.009
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.438, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.315, 68.627%; tC2Q: 0.144, 31.373%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.447, 100.000%

Path9

Path Summary:

Slack 0.503
Data Arrival Time 1.897
Data Required Time 1.394
From tx_mac_rst_n_2_s0
To test[2].u_mac_tx_model/data_start_byte_5_s0
Launch Clk tx_mac_clk:[R]
Latch Clk tx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
1.438 1.438 tNET RR 1 R32C131[3][A] tx_mac_rst_n_2_s0/CLK
1.582 0.144 tC2Q RR 378 R32C131[3][A] tx_mac_rst_n_2_s0/Q
1.897 0.315 tNET RR 1 R34C134[2][A] test[2].u_mac_tx_model/data_start_byte_5_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
1.447 1.447 tNET RR 1 R34C134[2][A] test[2].u_mac_tx_model/data_start_byte_5_s0/CLK
1.394 -0.053 tHld 1 R34C134[2][A] test[2].u_mac_tx_model/data_start_byte_5_s0

Path Statistics:

Clock Skew 0.009
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.438, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.315, 68.627%; tC2Q: 0.144, 31.373%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.447, 100.000%

Path10

Path Summary:

Slack 0.503
Data Arrival Time 1.897
Data Required Time 1.394
From tx_mac_rst_n_2_s0
To test[2].u_mac_tx_model/data_start_byte_6_s0
Launch Clk tx_mac_clk:[R]
Latch Clk tx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
1.438 1.438 tNET RR 1 R32C131[3][A] tx_mac_rst_n_2_s0/CLK
1.582 0.144 tC2Q RR 378 R32C131[3][A] tx_mac_rst_n_2_s0/Q
1.897 0.315 tNET RR 1 R34C134[2][B] test[2].u_mac_tx_model/data_start_byte_6_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
1.447 1.447 tNET RR 1 R34C134[2][B] test[2].u_mac_tx_model/data_start_byte_6_s0/CLK
1.394 -0.053 tHld 1 R34C134[2][B] test[2].u_mac_tx_model/data_start_byte_6_s0

Path Statistics:

Clock Skew 0.009
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.438, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.315, 68.627%; tC2Q: 0.144, 31.373%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.447, 100.000%

Path11

Path Summary:

Slack 0.504
Data Arrival Time 1.897
Data Required Time 1.393
From tx_mac_rst_n_2_s0
To test[2].u_mac_tx_model/tx_data_cnt_12_s1
Launch Clk tx_mac_clk:[R]
Latch Clk tx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
1.438 1.438 tNET RR 1 R32C131[3][A] tx_mac_rst_n_2_s0/CLK
1.582 0.144 tC2Q RR 378 R32C131[3][A] tx_mac_rst_n_2_s0/Q
1.897 0.315 tNET RR 1 R33C134[0][B] test[2].u_mac_tx_model/tx_data_cnt_12_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
1.446 1.446 tNET RR 1 R33C134[0][B] test[2].u_mac_tx_model/tx_data_cnt_12_s1/CLK
1.393 -0.053 tHld 1 R33C134[0][B] test[2].u_mac_tx_model/tx_data_cnt_12_s1

Path Statistics:

Clock Skew 0.008
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.438, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.315, 68.627%; tC2Q: 0.144, 31.373%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.446, 100.000%

Path12

Path Summary:

Slack 0.504
Data Arrival Time 1.897
Data Required Time 1.393
From tx_mac_rst_n_2_s0
To test[2].u_mac_tx_model/tx_data_cnt_13_s1
Launch Clk tx_mac_clk:[R]
Latch Clk tx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
1.438 1.438 tNET RR 1 R32C131[3][A] tx_mac_rst_n_2_s0/CLK
1.582 0.144 tC2Q RR 378 R32C131[3][A] tx_mac_rst_n_2_s0/Q
1.897 0.315 tNET RR 1 R33C134[0][A] test[2].u_mac_tx_model/tx_data_cnt_13_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
1.446 1.446 tNET RR 1 R33C134[0][A] test[2].u_mac_tx_model/tx_data_cnt_13_s1/CLK
1.393 -0.053 tHld 1 R33C134[0][A] test[2].u_mac_tx_model/tx_data_cnt_13_s1

Path Statistics:

Clock Skew 0.008
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.438, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.315, 68.627%; tC2Q: 0.144, 31.373%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.446, 100.000%

Path13

Path Summary:

Slack 0.504
Data Arrival Time 1.897
Data Required Time 1.393
From tx_mac_rst_n_2_s0
To test[2].u_mac_tx_model/tx_data_cnt_14_s1
Launch Clk tx_mac_clk:[R]
Latch Clk tx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
1.438 1.438 tNET RR 1 R32C131[3][A] tx_mac_rst_n_2_s0/CLK
1.582 0.144 tC2Q RR 378 R32C131[3][A] tx_mac_rst_n_2_s0/Q
1.897 0.315 tNET RR 1 R33C134[1][B] test[2].u_mac_tx_model/tx_data_cnt_14_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
1.446 1.446 tNET RR 1 R33C134[1][B] test[2].u_mac_tx_model/tx_data_cnt_14_s1/CLK
1.393 -0.053 tHld 1 R33C134[1][B] test[2].u_mac_tx_model/tx_data_cnt_14_s1

Path Statistics:

Clock Skew 0.008
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.438, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.315, 68.627%; tC2Q: 0.144, 31.373%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.446, 100.000%

Path14

Path Summary:

Slack 0.504
Data Arrival Time 1.897
Data Required Time 1.393
From tx_mac_rst_n_2_s0
To test[2].u_mac_tx_model/tx_data_cnt_15_s1
Launch Clk tx_mac_clk:[R]
Latch Clk tx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
1.438 1.438 tNET RR 1 R32C131[3][A] tx_mac_rst_n_2_s0/CLK
1.582 0.144 tC2Q RR 378 R32C131[3][A] tx_mac_rst_n_2_s0/Q
1.897 0.315 tNET RR 1 R33C134[1][A] test[2].u_mac_tx_model/tx_data_cnt_15_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
1.446 1.446 tNET RR 1 R33C134[1][A] test[2].u_mac_tx_model/tx_data_cnt_15_s1/CLK
1.393 -0.053 tHld 1 R33C134[1][A] test[2].u_mac_tx_model/tx_data_cnt_15_s1

Path Statistics:

Clock Skew 0.008
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.438, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.315, 68.627%; tC2Q: 0.144, 31.373%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.446, 100.000%

Path15

Path Summary:

Slack 0.514
Data Arrival Time 1.899
Data Required Time 1.385
From tx_mac_rst_n_2_s0
To test[2].u_mac_tx_model/shift_reg_92_s1
Launch Clk tx_mac_clk:[R]
Latch Clk tx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
1.438 1.438 tNET RR 1 R32C131[3][A] tx_mac_rst_n_2_s0/CLK
1.582 0.144 tC2Q RR 378 R32C131[3][A] tx_mac_rst_n_2_s0/Q
1.899 0.317 tNET RR 1 R31C134[0][B] test[2].u_mac_tx_model/shift_reg_92_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
1.438 1.438 tNET RR 1 R31C134[0][B] test[2].u_mac_tx_model/shift_reg_92_s1/CLK
1.385 -0.053 tHld 1 R31C134[0][B] test[2].u_mac_tx_model/shift_reg_92_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.438, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.317, 68.764%; tC2Q: 0.144, 31.236%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.438, 100.000%

Path16

Path Summary:

Slack 0.514
Data Arrival Time 1.899
Data Required Time 1.385
From tx_mac_rst_n_2_s0
To test[2].u_mac_tx_model/shift_reg_93_s1
Launch Clk tx_mac_clk:[R]
Latch Clk tx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
1.438 1.438 tNET RR 1 R32C131[3][A] tx_mac_rst_n_2_s0/CLK
1.582 0.144 tC2Q RR 378 R32C131[3][A] tx_mac_rst_n_2_s0/Q
1.899 0.317 tNET RR 1 R31C134[2][A] test[2].u_mac_tx_model/shift_reg_93_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
1.438 1.438 tNET RR 1 R31C134[2][A] test[2].u_mac_tx_model/shift_reg_93_s1/CLK
1.385 -0.053 tHld 1 R31C134[2][A] test[2].u_mac_tx_model/shift_reg_93_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.438, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.317, 68.764%; tC2Q: 0.144, 31.236%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.438, 100.000%

Path17

Path Summary:

Slack 0.514
Data Arrival Time 1.899
Data Required Time 1.385
From tx_mac_rst_n_2_s0
To test[2].u_mac_tx_model/shift_reg_94_s1
Launch Clk tx_mac_clk:[R]
Latch Clk tx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
1.438 1.438 tNET RR 1 R32C131[3][A] tx_mac_rst_n_2_s0/CLK
1.582 0.144 tC2Q RR 378 R32C131[3][A] tx_mac_rst_n_2_s0/Q
1.899 0.317 tNET RR 1 R31C134[0][A] test[2].u_mac_tx_model/shift_reg_94_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
1.438 1.438 tNET RR 1 R31C134[0][A] test[2].u_mac_tx_model/shift_reg_94_s1/CLK
1.385 -0.053 tHld 1 R31C134[0][A] test[2].u_mac_tx_model/shift_reg_94_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.438, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.317, 68.764%; tC2Q: 0.144, 31.236%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.438, 100.000%

Path18

Path Summary:

Slack 0.514
Data Arrival Time 1.899
Data Required Time 1.385
From tx_mac_rst_n_2_s0
To test[2].u_mac_tx_model/shift_reg_96_s1
Launch Clk tx_mac_clk:[R]
Latch Clk tx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
1.438 1.438 tNET RR 1 R32C131[3][A] tx_mac_rst_n_2_s0/CLK
1.582 0.144 tC2Q RR 378 R32C131[3][A] tx_mac_rst_n_2_s0/Q
1.899 0.317 tNET RR 1 R31C134[1][B] test[2].u_mac_tx_model/shift_reg_96_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
1.438 1.438 tNET RR 1 R31C134[1][B] test[2].u_mac_tx_model/shift_reg_96_s1/CLK
1.385 -0.053 tHld 1 R31C134[1][B] test[2].u_mac_tx_model/shift_reg_96_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.438, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.317, 68.764%; tC2Q: 0.144, 31.236%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.438, 100.000%

Path19

Path Summary:

Slack 0.514
Data Arrival Time 1.899
Data Required Time 1.385
From tx_mac_rst_n_2_s0
To test[2].u_mac_tx_model/shift_reg_99_s1
Launch Clk tx_mac_clk:[R]
Latch Clk tx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
1.438 1.438 tNET RR 1 R32C131[3][A] tx_mac_rst_n_2_s0/CLK
1.582 0.144 tC2Q RR 378 R32C131[3][A] tx_mac_rst_n_2_s0/Q
1.899 0.317 tNET RR 1 R31C134[1][A] test[2].u_mac_tx_model/shift_reg_99_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
1.438 1.438 tNET RR 1 R31C134[1][A] test[2].u_mac_tx_model/shift_reg_99_s1/CLK
1.385 -0.053 tHld 1 R31C134[1][A] test[2].u_mac_tx_model/shift_reg_99_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.438, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.317, 68.764%; tC2Q: 0.144, 31.236%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.438, 100.000%

Path20

Path Summary:

Slack 0.516
Data Arrival Time 1.897
Data Required Time 1.381
From tx_mac_rst_n_2_s0
To test[2].u_mac_tx_model/shift_reg_55_s1
Launch Clk tx_mac_clk:[R]
Latch Clk tx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
1.438 1.438 tNET RR 1 R32C131[3][A] tx_mac_rst_n_2_s0/CLK
1.582 0.144 tC2Q RR 378 R32C131[3][A] tx_mac_rst_n_2_s0/Q
1.897 0.315 tNET RR 1 R31C135[3][B] test[2].u_mac_tx_model/shift_reg_55_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
1.434 1.434 tNET RR 1 R31C135[3][B] test[2].u_mac_tx_model/shift_reg_55_s1/CLK
1.381 -0.053 tHld 1 R31C135[3][B] test[2].u_mac_tx_model/shift_reg_55_s1

Path Statistics:

Clock Skew -0.004
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.438, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.315, 68.627%; tC2Q: 0.144, 31.373%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.434, 100.000%

Path21

Path Summary:

Slack 0.516
Data Arrival Time 1.897
Data Required Time 1.381
From tx_mac_rst_n_2_s0
To test[2].u_mac_tx_model/shift_reg_62_s1
Launch Clk tx_mac_clk:[R]
Latch Clk tx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
1.438 1.438 tNET RR 1 R32C131[3][A] tx_mac_rst_n_2_s0/CLK
1.582 0.144 tC2Q RR 378 R32C131[3][A] tx_mac_rst_n_2_s0/Q
1.897 0.315 tNET RR 1 R31C135[1][B] test[2].u_mac_tx_model/shift_reg_62_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
1.434 1.434 tNET RR 1 R31C135[1][B] test[2].u_mac_tx_model/shift_reg_62_s1/CLK
1.381 -0.053 tHld 1 R31C135[1][B] test[2].u_mac_tx_model/shift_reg_62_s1

Path Statistics:

Clock Skew -0.004
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.438, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.315, 68.627%; tC2Q: 0.144, 31.373%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.434, 100.000%

Path22

Path Summary:

Slack 0.516
Data Arrival Time 1.897
Data Required Time 1.381
From tx_mac_rst_n_2_s0
To test[2].u_mac_tx_model/shift_reg_70_s1
Launch Clk tx_mac_clk:[R]
Latch Clk tx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
1.438 1.438 tNET RR 1 R32C131[3][A] tx_mac_rst_n_2_s0/CLK
1.582 0.144 tC2Q RR 378 R32C131[3][A] tx_mac_rst_n_2_s0/Q
1.897 0.315 tNET RR 1 R31C135[1][A] test[2].u_mac_tx_model/shift_reg_70_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
1.434 1.434 tNET RR 1 R31C135[1][A] test[2].u_mac_tx_model/shift_reg_70_s1/CLK
1.381 -0.053 tHld 1 R31C135[1][A] test[2].u_mac_tx_model/shift_reg_70_s1

Path Statistics:

Clock Skew -0.004
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.438, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.315, 68.627%; tC2Q: 0.144, 31.373%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.434, 100.000%

Path23

Path Summary:

Slack 0.516
Data Arrival Time 1.897
Data Required Time 1.381
From tx_mac_rst_n_2_s0
To test[2].u_mac_tx_model/shift_reg_98_s1
Launch Clk tx_mac_clk:[R]
Latch Clk tx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
1.438 1.438 tNET RR 1 R32C131[3][A] tx_mac_rst_n_2_s0/CLK
1.582 0.144 tC2Q RR 378 R32C131[3][A] tx_mac_rst_n_2_s0/Q
1.897 0.315 tNET RR 1 R31C135[2][B] test[2].u_mac_tx_model/shift_reg_98_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
1.434 1.434 tNET RR 1 R31C135[2][B] test[2].u_mac_tx_model/shift_reg_98_s1/CLK
1.381 -0.053 tHld 1 R31C135[2][B] test[2].u_mac_tx_model/shift_reg_98_s1

Path Statistics:

Clock Skew -0.004
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.438, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.315, 68.627%; tC2Q: 0.144, 31.373%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.434, 100.000%

Path24

Path Summary:

Slack 0.516
Data Arrival Time 1.897
Data Required Time 1.381
From tx_mac_rst_n_2_s0
To test[2].u_mac_tx_model/shift_reg_100_s1
Launch Clk tx_mac_clk:[R]
Latch Clk tx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
1.438 1.438 tNET RR 1 R32C131[3][A] tx_mac_rst_n_2_s0/CLK
1.582 0.144 tC2Q RR 378 R32C131[3][A] tx_mac_rst_n_2_s0/Q
1.897 0.315 tNET RR 1 R31C135[0][B] test[2].u_mac_tx_model/shift_reg_100_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
1.434 1.434 tNET RR 1 R31C135[0][B] test[2].u_mac_tx_model/shift_reg_100_s1/CLK
1.381 -0.053 tHld 1 R31C135[0][B] test[2].u_mac_tx_model/shift_reg_100_s1

Path Statistics:

Clock Skew -0.004
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.438, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.315, 68.627%; tC2Q: 0.144, 31.373%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.434, 100.000%

Path25

Path Summary:

Slack 0.516
Data Arrival Time 1.897
Data Required Time 1.381
From tx_mac_rst_n_2_s0
To test[2].u_mac_tx_model/shift_reg_101_s1
Launch Clk tx_mac_clk:[R]
Latch Clk tx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
1.438 1.438 tNET RR 1 R32C131[3][A] tx_mac_rst_n_2_s0/CLK
1.582 0.144 tC2Q RR 378 R32C131[3][A] tx_mac_rst_n_2_s0/Q
1.897 0.315 tNET RR 1 R31C135[3][A] test[2].u_mac_tx_model/shift_reg_101_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 3625 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
1.434 1.434 tNET RR 1 R31C135[3][A] test[2].u_mac_tx_model/shift_reg_101_s1/CLK
1.381 -0.053 tHld 1 R31C135[3][A] test[2].u_mac_tx_model/shift_reg_101_s1

Path Statistics:

Clock Skew -0.004
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.438, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.315, 68.627%; tC2Q: 0.144, 31.373%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.434, 100.000%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack: 0.851
Actual Width: 1.851
Required Width: 1.000
Type: High Pulse Width
Clock: rx_mac_clk
Objects: gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.902 3.902 tNET RR gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s/CLKB

Early clock Path:

AT DELAY TYPE RF NODE
4.000 0.000 active clock edge time
4.000 0.000 rx_mac_clk
4.000 0.000 tCL FF u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
5.753 1.753 tNET FF gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s/CLKB

MPW2

MPW Summary:

Slack: 0.861
Actual Width: 1.861
Required Width: 1.000
Type: High Pulse Width
Clock: rx_mac_clk
Objects: gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.883 3.883 tNET RR gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA

Early clock Path:

AT DELAY TYPE RF NODE
4.000 0.000 active clock edge time
4.000 0.000 rx_mac_clk
4.000 0.000 tCL FF u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
5.745 1.745 tNET FF gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA

MPW3

MPW Summary:

Slack: 0.962
Actual Width: 1.962
Required Width: 1.000
Type: Low Pulse Width
Clock: rx_mac_clk
Objects: gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s

Late clock Path:

AT DELAY TYPE RF NODE
4.000 0.000 active clock edge time
4.000 0.000 rx_mac_clk
4.000 0.000 tCL FF u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
7.486 3.486 tNET FF gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s/CLKB

Early clock Path:

AT DELAY TYPE RF NODE
8.000 0.000 active clock edge time
8.000 0.000 rx_mac_clk
8.000 0.000 tCL RR u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
9.448 1.448 tNET RR gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s/CLKB

MPW4

MPW Summary:

Slack: 0.973
Actual Width: 1.973
Required Width: 1.000
Type: Low Pulse Width
Clock: rx_mac_clk
Objects: gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Late clock Path:

AT DELAY TYPE RF NODE
4.000 0.000 active clock edge time
4.000 0.000 rx_mac_clk
4.000 0.000 tCL FF u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
7.467 3.467 tNET FF gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA

Early clock Path:

AT DELAY TYPE RF NODE
8.000 0.000 active clock edge time
8.000 0.000 rx_mac_clk
8.000 0.000 tCL RR u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
9.440 1.440 tNET RR gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA

MPW5

MPW Summary:

Slack: 1.591
Actual Width: 1.841
Required Width: 0.250
Type: High Pulse Width
Clock: rx_mac_clk
Objects: u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_rx/rx_decode_rxd_d1_2_s0

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.936 3.936 tNET RR u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_rx/rx_decode_rxd_d1_2_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
4.000 0.000 active clock edge time
4.000 0.000 rx_mac_clk
4.000 0.000 tCL FF u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
5.777 1.777 tNET FF u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_rx/rx_decode_rxd_d1_2_s0/CLK

MPW6

MPW Summary:

Slack: 1.591
Actual Width: 1.841
Required Width: 0.250
Type: High Pulse Width
Clock: rx_mac_clk
Objects: u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_rx/rx_decode_rxd_d3_4_s0

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.936 3.936 tNET RR u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_rx/rx_decode_rxd_d3_4_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
4.000 0.000 active clock edge time
4.000 0.000 rx_mac_clk
4.000 0.000 tCL FF u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
5.777 1.777 tNET FF u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_rx/rx_decode_rxd_d3_4_s0/CLK

MPW7

MPW Summary:

Slack: 1.591
Actual Width: 1.841
Required Width: 0.250
Type: High Pulse Width
Clock: rx_mac_clk
Objects: u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_rx/rx_decode_rxd_d3_1_s0

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.936 3.936 tNET RR u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_rx/rx_decode_rxd_d3_1_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
4.000 0.000 active clock edge time
4.000 0.000 rx_mac_clk
4.000 0.000 tCL FF u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
5.777 1.777 tNET FF u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_rx/rx_decode_rxd_d3_1_s0/CLK

MPW8

MPW Summary:

Slack: 1.591
Actual Width: 1.841
Required Width: 0.250
Type: High Pulse Width
Clock: rx_mac_clk
Objects: u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/gmii_rxd_int_6_s0

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.936 3.936 tNET RR u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/gmii_rxd_int_6_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
4.000 0.000 active clock edge time
4.000 0.000 rx_mac_clk
4.000 0.000 tCL FF u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
5.777 1.777 tNET FF u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/gmii_rxd_int_6_s0/CLK

MPW9

MPW Summary:

Slack: 1.591
Actual Width: 1.841
Required Width: 0.250
Type: High Pulse Width
Clock: rx_mac_clk
Objects: u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_ge_sync/decode_k_d2_s0

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.936 3.936 tNET RR u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_ge_sync/decode_k_d2_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
4.000 0.000 active clock edge time
4.000 0.000 rx_mac_clk
4.000 0.000 tCL FF u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
5.777 1.777 tNET FF u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_ge_sync/decode_k_d2_s0/CLK

MPW10

MPW Summary:

Slack: 1.591
Actual Width: 1.841
Required Width: 0.250
Type: High Pulse Width
Clock: rx_mac_clk
Objects: u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_frm_lgt_o_tmp_15_s0

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.936 3.936 tNET RR u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_frm_lgt_o_tmp_15_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
4.000 0.000 active clock edge time
4.000 0.000 rx_mac_clk
4.000 0.000 tCL FF u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
5.777 1.777 tNET FF u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_frm_lgt_o_tmp_15_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT NET NAME WORST SLACK MAX DELAY
6471 rx_mac_clk[3] 0.117 3.936
3625 tx_mac_clk[3] 0.002 3.939
2004 clk_uart 80.329 3.895
955 rstn_uart 92.144 5.207
214 control0[0] 42.588 5.721
196 rd_ptr[2] 93.221 3.138
192 rd_ptr[2] 94.163 3.428
162 rx_pause_state 3.124 3.898
162 rx_pause_state 4.960 2.125
162 rx_pause_state 3.723 3.289

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC ROUTE CONGESTIONS
R16C162 77.78%
R18C167 77.78%
R49C151 76.39%
R15C161 75.00%
R12C126 75.00%
R12C166 73.61%
R11C126 73.61%
R34C155 73.61%
R56C155 72.22%
R57C155 72.22%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type State Detail Command
TC_CLOCK Actived create_clock -name tck_pad -period 50 -waveform {0 25} [get_pins {gw_gao_inst_0/tck_ibuf/I}]
TC_CLOCK Actived create_clock -name clk_in -period 20 -waveform {0 10} [get_pins {clk_in_ibuf/I}]
TC_CLOCK Actived create_clock -name tx_mac_clk -period 8 -waveform {0 4} [get_nets {tx_mac_clk[3]}]
TC_CLOCK Actived create_clock -name rx_mac_clk -period 8 -waveform {0 4} [get_nets {rx_mac_clk[3]}]
TC_GENERATED_CLOCK Actived create_generated_clock -name clk_uart -source [get_pins {clk_in_ibuf/I}] -master_clock clk_in -divide_by 80 -multiply_by 16 [get_pins {u_pll_uart/PLL_inst/CLKOUT0}]
TC_FALSE_PATH Actived set_false_path -from [get_clocks {clk_uart tck_pad clk_in}] -to [get_clocks {rx_mac_clk tx_mac_clk clk_in}]
TC_FALSE_PATH Actived set_false_path -from [get_clocks {rx_mac_clk tx_mac_clk}] -to [get_clocks {clk_uart tck_pad}]