Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\SERDES_IP\IPlib\QSGMII\data\ge_pcs_qsgmii_wrap.v
D:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\SERDES_IP\IPlib\QSGMII\data\ge_pcs_qsgmii.v
GowinSynthesis Constraints File ---
Tool Version V1.9.9.01 (64-bit)
Part Number GW5AST-LV138FPG676AES
Device GW5AST-138
Device Version B
Created Time Tue Dec 26 09:47:07 2023
Legal Announcement Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module QSGMII_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.828s, Elapsed time = 0h 0m 0.916s, Peak memory usage = 104.152MB
Running netlist conversion:
    CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.142s, Peak memory usage = 104.152MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.656s, Elapsed time = 0h 0m 0.672s, Peak memory usage = 104.152MB
    Optimizing Phase 1: CPU time = 0h 0m 0.734s, Elapsed time = 0h 0m 0.751s, Peak memory usage = 104.152MB
    Optimizing Phase 2: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 104.152MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.375s, Elapsed time = 0h 0m 0.405s, Peak memory usage = 104.152MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 104.152MB
    Inferring Phase 2: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.114s, Peak memory usage = 104.152MB
    Inferring Phase 3: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.027s, Peak memory usage = 104.152MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.718s, Elapsed time = 0h 0m 0.72s, Peak memory usage = 104.152MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.187s, Elapsed time = 0h 0m 0.179s, Peak memory usage = 104.152MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.144s, Peak memory usage = 104.152MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 13s, Elapsed time = 0h 0m 13s, Peak memory usage = 127.070MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.843s, Elapsed time = 0h 0m 0.849s, Peak memory usage = 127.070MB
Generate output files:
    CPU time = 0h 0m 0.812s, Elapsed time = 0h 0m 0.832s, Peak memory usage = 160.434MB
Total Time and Memory Usage CPU time = 0h 0m 19s, Elapsed time = 0h 0m 19s, Peak memory usage = 160.434MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 1319
I/O Buf 1304
    IBUF 619
    OBUF 685
Register 6190
    DFFRE 138
    DFFPE 328
    DFFCE 5724
LUT 6488
    LUT2 922
    LUT3 1225
    LUT4 4341
ALU 168
    ALU 168
INV 44
    INV 44

Resource Utilization Summary

Resource Usage Utilization
Logic 6700(6532 LUT, 168 ALU) / 138240 5%
Register 6190 / 139140 5%
  --Register as Latch 0 / 139140 0%
  --Register as FF 6190 / 139140 5%
BSRAM 0 / 340 0%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
serdes_pcs_rx_clk_i Base 10.000 100.0 0.000 5.000 serdes_pcs_rx_clk_i_ibuf/I
serdes_pcs_tx_clk_i Base 10.000 100.0 0.000 5.000 serdes_pcs_tx_clk_i_ibuf/I
clk_in_i Base 10.000 100.0 0.000 5.000 clk_in_i_ibuf/I
miim_hs_clk_ch0_i Base 10.000 100.0 0.000 5.000 miim_hs_clk_ch0_i_ibuf/I
miim_hs_clk_ch1_i Base 10.000 100.0 0.000 5.000 miim_hs_clk_ch1_i_ibuf/I
miim_hs_clk_ch2_i Base 10.000 100.0 0.000 5.000 miim_hs_clk_ch2_i_ibuf/I
miim_hs_clk_ch3_i Base 10.000 100.0 0.000 5.000 miim_hs_clk_ch3_i_ibuf/I

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 serdes_pcs_rx_clk_i 100.0(MHz) 219.5(MHz) 6 TOP
2 serdes_pcs_tx_clk_i 100.0(MHz) 210.9(MHz) 6 TOP
3 clk_in_i 100.0(MHz) 1532.6(MHz) 1 TOP
4 miim_hs_clk_ch0_i 100.0(MHz) 250.9(MHz) 6 TOP
5 miim_hs_clk_ch1_i 100.0(MHz) 241.3(MHz) 6 TOP
6 miim_hs_clk_ch2_i 100.0(MHz) 237.8(MHz) 6 TOP
7 miim_hs_clk_ch3_i 100.0(MHz) 237.8(MHz) 6 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 5.258
Data Arrival Time 5.320
Data Required Time 10.578
From u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/frm_byte_cnt_3_s3
To u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_fcs_s6
Launch Clk serdes_pcs_tx_clk_i[R]
Latch Clk serdes_pcs_tx_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 serdes_pcs_tx_clk_i
0.000 0.000 tCL RR 1 serdes_pcs_tx_clk_i_ibuf/I
0.683 0.683 tINS RR 2519 serdes_pcs_tx_clk_i_ibuf/O
0.889 0.206 tNET RR 1 u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/frm_byte_cnt_3_s3/CLK
1.271 0.382 tC2Q RR 26 u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/frm_byte_cnt_3_s3/Q
1.477 0.206 tNET RR 1 u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/late_col_s8/I0
2.056 0.579 tINS RR 4 u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/late_col_s8/F
2.263 0.206 tNET RR 1 u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_ifg_s18/I1
2.830 0.567 tINS RR 1 u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_ifg_s18/F
3.036 0.206 tNET RR 1 u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_ifg_s7/I0
3.615 0.579 tINS RR 1 u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_ifg_s7/F
3.821 0.206 tNET RR 1 u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_ifg_s6/I0
4.400 0.579 tINS RR 2 u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_ifg_s6/F
4.606 0.206 tNET RR 1 u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_ifg_s4/I2
5.114 0.507 tINS RR 8 u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_ifg_s4/F
5.320 0.206 tNET RR 1 u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_fcs_s6/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 serdes_pcs_tx_clk_i
10.000 0.000 tCL RR 1 serdes_pcs_tx_clk_i_ibuf/I
10.682 0.683 tINS RR 2519 serdes_pcs_tx_clk_i_ibuf/O
10.889 0.206 tNET RR 1 u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_fcs_s6/CLK
10.578 -0.311 tSu 1 u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_fcs_s6
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.683, 76.793%; route: 0.206, 23.207%
Arrival Data Path Delay: cell: 2.811, 63.441%; route: 1.237, 27.927%; tC2Q: 0.382, 8.632%
Required Clock Path Delay: cell: 0.683, 76.793%; route: 0.206, 23.207%

Path 2

Path Summary:
Slack 5.258
Data Arrival Time 5.320
Data Required Time 10.578
From u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/frm_byte_cnt_3_s3
To u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_pad_s8
Launch Clk serdes_pcs_tx_clk_i[R]
Latch Clk serdes_pcs_tx_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 serdes_pcs_tx_clk_i
0.000 0.000 tCL RR 1 serdes_pcs_tx_clk_i_ibuf/I
0.683 0.683 tINS RR 2519 serdes_pcs_tx_clk_i_ibuf/O
0.889 0.206 tNET RR 1 u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/frm_byte_cnt_3_s3/CLK
1.271 0.382 tC2Q RR 26 u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/frm_byte_cnt_3_s3/Q
1.477 0.206 tNET RR 1 u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/late_col_s8/I0
2.056 0.579 tINS RR 4 u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/late_col_s8/F
2.263 0.206 tNET RR 1 u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_ifg_s18/I1
2.830 0.567 tINS RR 1 u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_ifg_s18/F
3.036 0.206 tNET RR 1 u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_ifg_s7/I0
3.615 0.579 tINS RR 1 u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_ifg_s7/F
3.821 0.206 tNET RR 1 u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_ifg_s6/I0
4.400 0.579 tINS RR 2 u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_ifg_s6/F
4.606 0.206 tNET RR 1 u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_ifg_s4/I2
5.114 0.507 tINS RR 8 u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_ifg_s4/F
5.320 0.206 tNET RR 1 u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_pad_s8/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 serdes_pcs_tx_clk_i
10.000 0.000 tCL RR 1 serdes_pcs_tx_clk_i_ibuf/I
10.682 0.683 tINS RR 2519 serdes_pcs_tx_clk_i_ibuf/O
10.889 0.206 tNET RR 1 u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_pad_s8/CLK
10.578 -0.311 tSu 1 u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_pad_s8
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.683, 76.793%; route: 0.206, 23.207%
Arrival Data Path Delay: cell: 2.811, 63.441%; route: 1.237, 27.927%; tC2Q: 0.382, 8.632%
Required Clock Path Delay: cell: 0.683, 76.793%; route: 0.206, 23.207%

Path 3

Path Summary:
Slack 5.258
Data Arrival Time 5.320
Data Required Time 10.578
From u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/frm_byte_cnt_3_s3
To u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_jam_s4
Launch Clk serdes_pcs_tx_clk_i[R]
Latch Clk serdes_pcs_tx_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 serdes_pcs_tx_clk_i
0.000 0.000 tCL RR 1 serdes_pcs_tx_clk_i_ibuf/I
0.683 0.683 tINS RR 2519 serdes_pcs_tx_clk_i_ibuf/O
0.889 0.206 tNET RR 1 u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/frm_byte_cnt_3_s3/CLK
1.271 0.382 tC2Q RR 26 u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/frm_byte_cnt_3_s3/Q
1.477 0.206 tNET RR 1 u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/late_col_s8/I0
2.056 0.579 tINS RR 4 u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/late_col_s8/F
2.263 0.206 tNET RR 1 u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_ifg_s18/I1
2.830 0.567 tINS RR 1 u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_ifg_s18/F
3.036 0.206 tNET RR 1 u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_ifg_s7/I0
3.615 0.579 tINS RR 1 u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_ifg_s7/F
3.821 0.206 tNET RR 1 u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_ifg_s6/I0
4.400 0.579 tINS RR 2 u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_ifg_s6/F
4.606 0.206 tNET RR 1 u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_ifg_s4/I2
5.114 0.507 tINS RR 8 u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_ifg_s4/F
5.320 0.206 tNET RR 1 u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_jam_s4/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 serdes_pcs_tx_clk_i
10.000 0.000 tCL RR 1 serdes_pcs_tx_clk_i_ibuf/I
10.682 0.683 tINS RR 2519 serdes_pcs_tx_clk_i_ibuf/O
10.889 0.206 tNET RR 1 u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_jam_s4/CLK
10.578 -0.311 tSu 1 u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_jam_s4
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.683, 76.793%; route: 0.206, 23.207%
Arrival Data Path Delay: cell: 2.811, 63.441%; route: 1.237, 27.927%; tC2Q: 0.382, 8.632%
Required Clock Path Delay: cell: 0.683, 76.793%; route: 0.206, 23.207%

Path 4

Path Summary:
Slack 5.258
Data Arrival Time 5.320
Data Required Time 10.578
From u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/frm_byte_cnt_3_s3
To u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_data_s12
Launch Clk serdes_pcs_tx_clk_i[R]
Latch Clk serdes_pcs_tx_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 serdes_pcs_tx_clk_i
0.000 0.000 tCL RR 1 serdes_pcs_tx_clk_i_ibuf/I
0.683 0.683 tINS RR 2519 serdes_pcs_tx_clk_i_ibuf/O
0.889 0.206 tNET RR 1 u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/frm_byte_cnt_3_s3/CLK
1.271 0.382 tC2Q RR 26 u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/frm_byte_cnt_3_s3/Q
1.477 0.206 tNET RR 1 u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/late_col_s8/I0
2.056 0.579 tINS RR 4 u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/late_col_s8/F
2.263 0.206 tNET RR 1 u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_ifg_s18/I1
2.830 0.567 tINS RR 1 u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_ifg_s18/F
3.036 0.206 tNET RR 1 u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_ifg_s7/I0
3.615 0.579 tINS RR 1 u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_ifg_s7/F
3.821 0.206 tNET RR 1 u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_ifg_s6/I0
4.400 0.579 tINS RR 2 u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_ifg_s6/F
4.606 0.206 tNET RR 1 u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_ifg_s4/I2
5.114 0.507 tINS RR 8 u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_ifg_s4/F
5.320 0.206 tNET RR 1 u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_data_s12/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 serdes_pcs_tx_clk_i
10.000 0.000 tCL RR 1 serdes_pcs_tx_clk_i_ibuf/I
10.682 0.683 tINS RR 2519 serdes_pcs_tx_clk_i_ibuf/O
10.889 0.206 tNET RR 1 u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_data_s12/CLK
10.578 -0.311 tSu 1 u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_data_s12
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.683, 76.793%; route: 0.206, 23.207%
Arrival Data Path Delay: cell: 2.811, 63.441%; route: 1.237, 27.927%; tC2Q: 0.382, 8.632%
Required Clock Path Delay: cell: 0.683, 76.793%; route: 0.206, 23.207%

Path 5

Path Summary:
Slack 5.258
Data Arrival Time 5.320
Data Required Time 10.578
From u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/frm_byte_cnt_3_s3
To u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_preamble_s14
Launch Clk serdes_pcs_tx_clk_i[R]
Latch Clk serdes_pcs_tx_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 serdes_pcs_tx_clk_i
0.000 0.000 tCL RR 1 serdes_pcs_tx_clk_i_ibuf/I
0.683 0.683 tINS RR 2519 serdes_pcs_tx_clk_i_ibuf/O
0.889 0.206 tNET RR 1 u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/frm_byte_cnt_3_s3/CLK
1.271 0.382 tC2Q RR 26 u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/frm_byte_cnt_3_s3/Q
1.477 0.206 tNET RR 1 u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/late_col_s8/I0
2.056 0.579 tINS RR 4 u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/late_col_s8/F
2.263 0.206 tNET RR 1 u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_ifg_s18/I1
2.830 0.567 tINS RR 1 u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_ifg_s18/F
3.036 0.206 tNET RR 1 u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_ifg_s7/I0
3.615 0.579 tINS RR 1 u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_ifg_s7/F
3.821 0.206 tNET RR 1 u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_ifg_s6/I0
4.400 0.579 tINS RR 2 u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_ifg_s6/F
4.606 0.206 tNET RR 1 u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_ifg_s4/I2
5.114 0.507 tINS RR 8 u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_ifg_s4/F
5.320 0.206 tNET RR 1 u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_preamble_s14/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 serdes_pcs_tx_clk_i
10.000 0.000 tCL RR 1 serdes_pcs_tx_clk_i_ibuf/I
10.682 0.683 tINS RR 2519 serdes_pcs_tx_clk_i_ibuf/O
10.889 0.206 tNET RR 1 u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_preamble_s14/CLK
10.578 -0.311 tSu 1 u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_preamble_s14
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.683, 76.793%; route: 0.206, 23.207%
Arrival Data Path Delay: cell: 2.811, 63.441%; route: 1.237, 27.927%; tC2Q: 0.382, 8.632%
Required Clock Path Delay: cell: 0.683, 76.793%; route: 0.206, 23.207%