Timing Messages
Report Title | Timing Analysis Report |
Design File | E:\IP_Release\QSGMII\1.0\ref_design\Gowin_QSGMII_IP_RefDesign_1\project\impl\gwsynthesis\fpga_project.vg |
Physical Constraints File | E:\IP_Release\QSGMII\1.0\ref_design\Gowin_QSGMII_IP_RefDesign_1\project\src\fpga_project.cst |
Timing Constraint File | E:\IP_Release\QSGMII\1.0\ref_design\Gowin_QSGMII_IP_RefDesign_1\project\src\fpga_project.sdc |
Tool Version | V1.9.9.01 (64-bit) |
Part Number | GW5AST-LV138FPG676AES |
Device | GW5AST-138 |
Device Version | B |
Created Time | Tue Jan 2 14:17:46 2024 |
Legal Announcement | Copyright (C)2014-2023 Gowin Semiconductor Corporation. All rights reserved. |
Timing Summaries
STA Tool Run Summary:
Setup Delay Model | Slow 0.855V 0C ES |
Hold Delay Model | Fast 0.945V 85C ES |
Numbers of Paths Analyzed | 34785 |
Numbers of Endpoints Analyzed | 37018 |
Numbers of Falling Endpoints | 3 |
Numbers of Setup Violated Endpoints | 0 |
Numbers of Hold Violated Endpoints | 0 |
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Objects |
---|---|---|---|---|---|---|---|---|
rx_mac_clk | Base | 8.000 | 125.000 | 0.000 | 4.000 | rx_mac_clk[3] | ||
tx_mac_clk | Base | 8.000 | 125.000 | 0.000 | 4.000 | tx_mac_clk[3] | ||
clk_in | Base | 20.000 | 50.000 | 0.000 | 10.000 | gowin_ibuf_clk_in/I | ||
tck_pad | Base | 50.000 | 20.000 | 0.000 | 25.000 | gw_gao_inst_0/tck_ibuf/I | ||
clk_uart | Generated | 100.000 | 10.000 | 0.000 | 50.000 | gowin_ibuf_clk_in/I | clk_in | u_pll_uart/PLL_inst/CLKOUT0 |
Max Frequency Summary:
NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | rx_mac_clk | 125.000(MHz) | 1133.144(MHz) | 1 | TOP |
2 | tx_mac_clk | 125.000(MHz) | 128.031(MHz) | 6 | TOP |
3 | tck_pad | 20.000(MHz) | 130.314(MHz) | 6 | TOP |
4 | clk_uart | 10.000(MHz) | 51.792(MHz) | 9 | TOP |
No timing paths to get frequency of clk_in!
Total Negative Slack Summary:
Clock Name | Analysis Type | Endpoints TNS | Number of Endpoints |
---|---|---|---|
rx_mac_clk | Setup | 0.000 | 0 |
rx_mac_clk | Hold | 0.000 | 0 |
tx_mac_clk | Setup | 0.000 | 0 |
tx_mac_clk | Hold | 0.000 | 0 |
clk_in | Setup | 0.000 | 0 |
clk_in | Hold | 0.000 | 0 |
tck_pad | Setup | 0.000 | 0 |
tck_pad | Hold | 0.000 | 0 |
clk_uart | Setup | 0.000 | 0 |
clk_uart | Hold | 0.000 | 0 |
Timing Details
Path Slacks Table:
Setup Paths Table
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 0.069 | test[2].u_mac_rx_model/cur_state_1_s0/Q | test[2].u_mac_rx_model/pause_address_31_s1/D | rx_mac_clk:[R] | rx_mac_clk:[R] | 8.000 | -0.036 | 7.904 |
2 | 0.162 | test[0].u_mac_rx_model/pause_address_0_s1/Q | test[0].u_mac_rx_model/pause_address_25_s1/D | rx_mac_clk:[R] | rx_mac_clk:[R] | 8.000 | -0.048 | 7.821 |
3 | 0.189 | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_mac_tx_ctrl/frm_byte_cnt_6_s3/Q | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_mac_tx_ctrl/c_state.s_pause_s12/CE | tx_mac_clk:[R] | tx_mac_clk:[R] | 8.000 | 0.007 | 7.493 |
4 | 0.217 | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/tx_mac_ready_o_s0/Q | test[1].u_mac_tx_model/shift_reg_42_s1/CE | tx_mac_clk:[R] | tx_mac_clk:[R] | 8.000 | 0.012 | 7.460 |
5 | 0.217 | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/tx_mac_ready_o_s0/Q | test[1].u_mac_tx_model/shift_reg_50_s1/CE | tx_mac_clk:[R] | tx_mac_clk:[R] | 8.000 | 0.012 | 7.460 |
6 | 0.217 | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/tx_mac_ready_o_s0/Q | test[1].u_mac_tx_model/shift_reg_72_s1/CE | tx_mac_clk:[R] | tx_mac_clk:[R] | 8.000 | 0.012 | 7.460 |
7 | 0.217 | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/tx_mac_ready_o_s0/Q | test[1].u_mac_tx_model/shift_reg_80_s1/CE | tx_mac_clk:[R] | tx_mac_clk:[R] | 8.000 | 0.012 | 7.460 |
8 | 0.217 | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/tx_mac_ready_o_s0/Q | test[1].u_mac_tx_model/shift_reg_88_s1/CE | tx_mac_clk:[R] | tx_mac_clk:[R] | 8.000 | 0.012 | 7.460 |
9 | 0.217 | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/tx_mac_ready_o_s0/Q | test[1].u_mac_tx_model/shift_reg_96_s1/CE | tx_mac_clk:[R] | tx_mac_clk:[R] | 8.000 | 0.012 | 7.460 |
10 | 0.217 | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/tx_mac_ready_o_s0/Q | test[1].u_mac_tx_model/shift_reg_104_s1/CE | tx_mac_clk:[R] | tx_mac_clk:[R] | 8.000 | 0.012 | 7.460 |
11 | 0.325 | test[2].u_mac_rx_model/cur_state_1_s0/Q | test[2].u_mac_rx_model/pause_address_32_s1/D | rx_mac_clk:[R] | rx_mac_clk:[R] | 8.000 | -0.041 | 7.653 |
12 | 0.325 | test[2].u_mac_rx_model/cur_state_1_s0/Q | test[2].u_mac_rx_model/pause_address_33_s1/D | rx_mac_clk:[R] | rx_mac_clk:[R] | 8.000 | -0.041 | 7.653 |
13 | 0.355 | test[2].u_mac_rx_model/cur_state_1_s0/Q | test[2].u_mac_rx_model/pause_address_34_s1/D | rx_mac_clk:[R] | rx_mac_clk:[R] | 8.000 | -0.041 | 7.623 |
14 | 0.374 | test[0].u_mac_rx_model/pause_address_0_s1/Q | test[0].u_mac_rx_model/pause_address_31_s1/D | rx_mac_clk:[R] | rx_mac_clk:[R] | 8.000 | -0.024 | 7.586 |
15 | 0.377 | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_frm_lgt_reg_14_s1/Q | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_pause_val_reg_0_s1/CE | rx_mac_clk:[R] | rx_mac_clk:[R] | 8.000 | 0.007 | 7.304 |
16 | 0.377 | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_frm_lgt_reg_14_s1/Q | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_pause_val_reg_1_s1/CE | rx_mac_clk:[R] | rx_mac_clk:[R] | 8.000 | 0.004 | 7.307 |
17 | 0.377 | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_frm_lgt_reg_14_s1/Q | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_pause_val_reg_2_s1/CE | rx_mac_clk:[R] | rx_mac_clk:[R] | 8.000 | 0.004 | 7.307 |
18 | 0.377 | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_frm_lgt_reg_14_s1/Q | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_pause_val_reg_3_s1/CE | rx_mac_clk:[R] | rx_mac_clk:[R] | 8.000 | 0.007 | 7.304 |
19 | 0.377 | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_frm_lgt_reg_14_s1/Q | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_pause_val_reg_4_s1/CE | rx_mac_clk:[R] | rx_mac_clk:[R] | 8.000 | 0.004 | 7.307 |
20 | 0.377 | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_frm_lgt_reg_14_s1/Q | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_pause_val_reg_5_s1/CE | rx_mac_clk:[R] | rx_mac_clk:[R] | 8.000 | 0.004 | 7.307 |
21 | 0.377 | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_frm_lgt_reg_14_s1/Q | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_pause_val_reg_6_s1/CE | rx_mac_clk:[R] | rx_mac_clk:[R] | 8.000 | 0.007 | 7.304 |
22 | 0.377 | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_frm_lgt_reg_14_s1/Q | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_pause_val_reg_8_s1/CE | rx_mac_clk:[R] | rx_mac_clk:[R] | 8.000 | 0.007 | 7.304 |
23 | 0.377 | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_frm_lgt_reg_14_s1/Q | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_pause_val_reg_9_s1/CE | rx_mac_clk:[R] | rx_mac_clk:[R] | 8.000 | 0.004 | 7.307 |
24 | 0.377 | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_frm_lgt_reg_14_s1/Q | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_pause_val_reg_10_s1/CE | rx_mac_clk:[R] | rx_mac_clk:[R] | 8.000 | 0.007 | 7.304 |
25 | 0.377 | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_frm_lgt_reg_14_s1/Q | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_pause_val_reg_11_s1/CE | rx_mac_clk:[R] | rx_mac_clk:[R] | 8.000 | 0.007 | 7.304 |
Hold Paths Table
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 0.263 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_1_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[1] | rx_mac_clk:[R] | rx_mac_clk:[R] | 0.000 | -0.006 | 0.519 |
2 | 0.358 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_3_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[3] | rx_mac_clk:[R] | rx_mac_clk:[R] | 0.000 | -0.006 | 0.614 |
3 | 0.358 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_2_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[2] | rx_mac_clk:[R] | rx_mac_clk:[R] | 0.000 | -0.006 | 0.614 |
4 | 0.374 | test[3].u_mac_rx_model/rx_error_all_pause_check_s4/Q | test[3].u_mac_rx_model/rx_error_all_pause_check_s4/D | rx_mac_clk:[R] | rx_mac_clk:[R] | 0.000 | 0.000 | 0.375 |
5 | 0.374 | test[3].u_mac_rx_model/rx_data_cnt_pause_4_s1/Q | test[3].u_mac_rx_model/rx_data_cnt_pause_4_s1/D | rx_mac_clk:[R] | rx_mac_clk:[R] | 0.000 | 0.000 | 0.375 |
6 | 0.374 | test[3].u_mac_rx_model/rx_data_cnt_pause_5_s1/Q | test[3].u_mac_rx_model/rx_data_cnt_pause_5_s1/D | rx_mac_clk:[R] | rx_mac_clk:[R] | 0.000 | 0.000 | 0.375 |
7 | 0.374 | test[3].u_mac_rx_model/rx_data_cnt_pause_7_s1/Q | test[3].u_mac_rx_model/rx_data_cnt_pause_7_s1/D | rx_mac_clk:[R] | rx_mac_clk:[R] | 0.000 | 0.000 | 0.375 |
8 | 0.374 | test[3].u_mac_rx_model/shift_reg_pause_1_s1/Q | test[3].u_mac_rx_model/shift_reg_pause_1_s1/D | rx_mac_clk:[R] | rx_mac_clk:[R] | 0.000 | 0.000 | 0.375 |
9 | 0.374 | test[3].u_mac_rx_model/shift_reg_pause_2_s1/Q | test[3].u_mac_rx_model/shift_reg_pause_2_s1/D | rx_mac_clk:[R] | rx_mac_clk:[R] | 0.000 | 0.000 | 0.375 |
10 | 0.374 | test[3].u_mac_rx_model/shift_reg_pause_4_s1/Q | test[3].u_mac_rx_model/shift_reg_pause_4_s1/D | rx_mac_clk:[R] | rx_mac_clk:[R] | 0.000 | 0.000 | 0.375 |
11 | 0.374 | test[3].u_mac_rx_model/pause_address_47_s1/Q | test[3].u_mac_rx_model/pause_address_47_s1/D | rx_mac_clk:[R] | rx_mac_clk:[R] | 0.000 | 0.000 | 0.375 |
12 | 0.374 | test[3].u_mac_rx_model/pause_value_4_s1/Q | test[3].u_mac_rx_model/pause_value_4_s1/D | rx_mac_clk:[R] | rx_mac_clk:[R] | 0.000 | 0.000 | 0.375 |
13 | 0.374 | test[3].u_mac_rx_model/rx_data_cnt_0_s1/Q | test[3].u_mac_rx_model/rx_data_cnt_0_s1/D | rx_mac_clk:[R] | rx_mac_clk:[R] | 0.000 | 0.000 | 0.375 |
14 | 0.374 | test[3].u_mac_rx_model/rx_data_cnt_2_s1/Q | test[3].u_mac_rx_model/rx_data_cnt_2_s1/D | rx_mac_clk:[R] | rx_mac_clk:[R] | 0.000 | 0.000 | 0.375 |
15 | 0.374 | test[3].u_mac_rx_model/shift_reg_0_s1/Q | test[3].u_mac_rx_model/shift_reg_0_s1/D | rx_mac_clk:[R] | rx_mac_clk:[R] | 0.000 | 0.000 | 0.375 |
16 | 0.374 | test[3].u_mac_rx_model/shift_reg_2_s1/Q | test[3].u_mac_rx_model/shift_reg_2_s1/D | rx_mac_clk:[R] | rx_mac_clk:[R] | 0.000 | 0.000 | 0.375 |
17 | 0.374 | test[3].u_mac_rx_model/shift_reg_3_s1/Q | test[3].u_mac_rx_model/shift_reg_3_s1/D | rx_mac_clk:[R] | rx_mac_clk:[R] | 0.000 | 0.000 | 0.375 |
18 | 0.374 | test[3].u_mac_rx_model/shift_reg_4_s1/Q | test[3].u_mac_rx_model/shift_reg_4_s1/D | rx_mac_clk:[R] | rx_mac_clk:[R] | 0.000 | 0.000 | 0.375 |
19 | 0.374 | test[3].u_mac_rx_model/shift_reg_12_s1/Q | test[3].u_mac_rx_model/shift_reg_12_s1/D | rx_mac_clk:[R] | rx_mac_clk:[R] | 0.000 | 0.000 | 0.375 |
20 | 0.374 | test[3].u_mac_rx_model/shift_reg_16_s1/Q | test[3].u_mac_rx_model/shift_reg_16_s1/D | rx_mac_clk:[R] | rx_mac_clk:[R] | 0.000 | 0.000 | 0.375 |
21 | 0.374 | test[3].u_mac_rx_model/shift_reg_22_s1/Q | test[3].u_mac_rx_model/shift_reg_22_s1/D | rx_mac_clk:[R] | rx_mac_clk:[R] | 0.000 | 0.000 | 0.375 |
22 | 0.374 | test[3].u_mac_rx_model/shift_reg_27_s1/Q | test[3].u_mac_rx_model/shift_reg_27_s1/D | rx_mac_clk:[R] | rx_mac_clk:[R] | 0.000 | 0.000 | 0.375 |
23 | 0.374 | test[3].u_mac_rx_model/shift_reg_30_s1/Q | test[3].u_mac_rx_model/shift_reg_30_s1/D | rx_mac_clk:[R] | rx_mac_clk:[R] | 0.000 | 0.000 | 0.375 |
24 | 0.374 | test[3].u_mac_rx_model/shift_reg_35_s1/Q | test[3].u_mac_rx_model/shift_reg_35_s1/D | rx_mac_clk:[R] | rx_mac_clk:[R] | 0.000 | 0.000 | 0.375 |
25 | 0.374 | test[3].u_mac_rx_model/shift_reg_37_s1/Q | test[3].u_mac_rx_model/shift_reg_37_s1/D | rx_mac_clk:[R] | rx_mac_clk:[R] | 0.000 | 0.000 | 0.375 |
Recovery Paths Table
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 0.025 | rx_mac_rst_n_3_s0/Q | test[3].u_mac_rx_model/rx_cnt_error_0_s0/CLEAR | rx_mac_clk:[R] | rx_mac_clk:[R] | 8.000 | -0.021 | 7.649 |
2 | 0.025 | rx_mac_rst_n_3_s0/Q | test[3].u_mac_rx_model/rx_data_state_d1_s0/CLEAR | rx_mac_clk:[R] | rx_mac_clk:[R] | 8.000 | -0.021 | 7.649 |
3 | 0.034 | rx_mac_rst_n_3_s0/Q | test[3].u_mac_rx_model/rx_data_cnt_data_s1/CLEAR | rx_mac_clk:[R] | rx_mac_clk:[R] | 8.000 | -0.031 | 7.649 |
4 | 0.034 | rx_mac_rst_n_3_s0/Q | test[3].u_mac_rx_model/rx_data_cnt_1_s1/CLEAR | rx_mac_clk:[R] | rx_mac_clk:[R] | 8.000 | -0.031 | 7.649 |
5 | 0.034 | rx_mac_rst_n_3_s0/Q | test[3].u_mac_rx_model/rx_data_cnt_3_s1/CLEAR | rx_mac_clk:[R] | rx_mac_clk:[R] | 8.000 | -0.031 | 7.649 |
6 | 0.034 | rx_mac_rst_n_3_s0/Q | test[3].u_mac_rx_model/rx_data_cnt_4_s1/CLEAR | rx_mac_clk:[R] | rx_mac_clk:[R] | 8.000 | -0.031 | 7.649 |
7 | 0.071 | rx_mac_rst_n_3_s0/Q | test[3].u_mac_rx_model/rx_statistics_vector_d3_6_s1/CLEAR | rx_mac_clk:[R] | rx_mac_clk:[R] | 8.000 | -0.033 | 7.615 |
8 | 0.071 | rx_mac_rst_n_3_s0/Q | test[3].u_mac_rx_model/rx_statistics_vector_d3_7_s1/CLEAR | rx_mac_clk:[R] | rx_mac_clk:[R] | 8.000 | -0.033 | 7.615 |
9 | 0.071 | rx_mac_rst_n_3_s0/Q | test[3].u_mac_rx_model/rx_statistics_vector_d3_18_s1/CLEAR | rx_mac_clk:[R] | rx_mac_clk:[R] | 8.000 | -0.033 | 7.615 |
10 | 0.071 | rx_mac_rst_n_3_s0/Q | test[3].u_mac_rx_model/rx_statistics_vector_d2_6_s1/CLEAR | rx_mac_clk:[R] | rx_mac_clk:[R] | 8.000 | -0.033 | 7.615 |
11 | 0.071 | rx_mac_rst_n_3_s0/Q | test[3].u_mac_rx_model/rx_statistics_vector_d2_7_s1/CLEAR | rx_mac_clk:[R] | rx_mac_clk:[R] | 8.000 | -0.033 | 7.615 |
12 | 0.071 | rx_mac_rst_n_3_s0/Q | test[3].u_mac_rx_model/rx_statistics_vector_d2_18_s1/CLEAR | rx_mac_clk:[R] | rx_mac_clk:[R] | 8.000 | -0.033 | 7.615 |
13 | 0.176 | rx_mac_rst_n_2_s0/Q | test[2].u_mac_rx_model/shift_reg_pause_94_s1/CLEAR | rx_mac_clk:[R] | rx_mac_clk:[R] | 8.000 | -0.033 | 7.510 |
14 | 0.176 | rx_mac_rst_n_2_s0/Q | test[2].u_mac_rx_model/pause_data_2_46_s1/CLEAR | rx_mac_clk:[R] | rx_mac_clk:[R] | 8.000 | -0.033 | 7.510 |
15 | 0.176 | rx_mac_rst_n_2_s0/Q | test[2].u_mac_rx_model/pause_address_11_s1/PRESET | rx_mac_clk:[R] | rx_mac_clk:[R] | 8.000 | -0.033 | 7.510 |
16 | 0.176 | rx_mac_rst_n_2_s0/Q | test[2].u_mac_rx_model/pause_address_14_s1/CLEAR | rx_mac_clk:[R] | rx_mac_clk:[R] | 8.000 | -0.033 | 7.510 |
17 | 0.176 | rx_mac_rst_n_2_s0/Q | test[2].u_mac_rx_model/pause_address_15_s1/PRESET | rx_mac_clk:[R] | rx_mac_clk:[R] | 8.000 | -0.033 | 7.510 |
18 | 0.185 | rx_mac_rst_n_2_s0/Q | test[2].u_mac_rx_model/pause_data_2_24_s1/CLEAR | rx_mac_clk:[R] | rx_mac_clk:[R] | 8.000 | -0.043 | 7.510 |
19 | 0.185 | rx_mac_rst_n_2_s0/Q | test[2].u_mac_rx_model/pause_data_2_26_s1/CLEAR | rx_mac_clk:[R] | rx_mac_clk:[R] | 8.000 | -0.043 | 7.510 |
20 | 0.185 | rx_mac_rst_n_2_s0/Q | test[2].u_mac_rx_model/pause_address_16_s1/CLEAR | rx_mac_clk:[R] | rx_mac_clk:[R] | 8.000 | -0.043 | 7.510 |
21 | 0.185 | rx_mac_rst_n_2_s0/Q | test[2].u_mac_rx_model/pause_address_17_s1/PRESET | rx_mac_clk:[R] | rx_mac_clk:[R] | 8.000 | -0.043 | 7.510 |
22 | 0.205 | rx_mac_rst_n_2_s0/Q | test[2].u_mac_rx_model/shift_reg_pause_91_s1/CLEAR | rx_mac_clk:[R] | rx_mac_clk:[R] | 8.000 | -0.026 | 7.474 |
23 | 0.205 | rx_mac_rst_n_2_s0/Q | test[2].u_mac_rx_model/pause_data_2_42_s1/CLEAR | rx_mac_clk:[R] | rx_mac_clk:[R] | 8.000 | -0.026 | 7.474 |
24 | 0.205 | rx_mac_rst_n_2_s0/Q | test[2].u_mac_rx_model/pause_data_2_43_s1/CLEAR | rx_mac_clk:[R] | rx_mac_clk:[R] | 8.000 | -0.026 | 7.474 |
25 | 0.205 | rx_mac_rst_n_2_s0/Q | test[2].u_mac_rx_model/pause_data_2_44_s1/CLEAR | rx_mac_clk:[R] | rx_mac_clk:[R] | 8.000 | -0.026 | 7.474 |
Removal Paths Table
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 0.629 | tx_mac_rst_n_3_s0/Q | test[3].u_mac_tx_model/shift_reg_78_s1/CLEAR | tx_mac_clk:[R] | tx_mac_clk:[R] | 0.000 | 0.015 | 0.425 |
2 | 0.629 | tx_mac_rst_n_3_s0/Q | test[3].u_mac_tx_model/shift_reg_86_s1/CLEAR | tx_mac_clk:[R] | tx_mac_clk:[R] | 0.000 | 0.015 | 0.425 |
3 | 0.629 | tx_mac_rst_n_3_s0/Q | test[3].u_mac_tx_model/shift_reg_94_s1/CLEAR | tx_mac_clk:[R] | tx_mac_clk:[R] | 0.000 | 0.015 | 0.425 |
4 | 0.629 | tx_mac_rst_n_3_s0/Q | test[3].u_mac_tx_model/shift_reg_102_s1/CLEAR | tx_mac_clk:[R] | tx_mac_clk:[R] | 0.000 | 0.015 | 0.425 |
5 | 0.629 | tx_mac_rst_n_3_s0/Q | test[3].u_mac_tx_model/shift_reg_110_s1/CLEAR | tx_mac_clk:[R] | tx_mac_clk:[R] | 0.000 | 0.015 | 0.425 |
6 | 0.751 | tx_mac_rst_n_3_s0/Q | test[3].u_mac_tx_model/shift_reg_46_s1/CLEAR | tx_mac_clk:[R] | tx_mac_clk:[R] | 0.000 | 0.005 | 0.558 |
7 | 0.751 | tx_mac_rst_n_3_s0/Q | test[3].u_mac_tx_model/shift_reg_54_s1/CLEAR | tx_mac_clk:[R] | tx_mac_clk:[R] | 0.000 | 0.005 | 0.558 |
8 | 0.751 | tx_mac_rst_n_3_s0/Q | test[3].u_mac_tx_model/shift_reg_62_s1/CLEAR | tx_mac_clk:[R] | tx_mac_clk:[R] | 0.000 | 0.005 | 0.558 |
9 | 0.751 | tx_mac_rst_n_3_s0/Q | test[3].u_mac_tx_model/shift_reg_70_s1/CLEAR | tx_mac_clk:[R] | tx_mac_clk:[R] | 0.000 | 0.005 | 0.558 |
10 | 0.751 | tx_mac_rst_n_3_s0/Q | test[3].u_mac_tx_model/shift_reg_98_s1/CLEAR | tx_mac_clk:[R] | tx_mac_clk:[R] | 0.000 | 0.005 | 0.558 |
11 | 0.751 | tx_mac_rst_n_3_s0/Q | test[3].u_mac_tx_model/shift_reg_106_s1/CLEAR | tx_mac_clk:[R] | tx_mac_clk:[R] | 0.000 | 0.005 | 0.558 |
12 | 0.756 | tx_mac_rst_n_3_s0/Q | test[3].u_mac_tx_model/shift_reg_42_s1/CLEAR | tx_mac_clk:[R] | tx_mac_clk:[R] | 0.000 | 0.010 | 0.558 |
13 | 0.756 | tx_mac_rst_n_3_s0/Q | test[3].u_mac_tx_model/shift_reg_50_s1/CLEAR | tx_mac_clk:[R] | tx_mac_clk:[R] | 0.000 | 0.010 | 0.558 |
14 | 0.756 | tx_mac_rst_n_3_s0/Q | test[3].u_mac_tx_model/shift_reg_58_s1/CLEAR | tx_mac_clk:[R] | tx_mac_clk:[R] | 0.000 | 0.010 | 0.558 |
15 | 0.756 | tx_mac_rst_n_3_s0/Q | test[3].u_mac_tx_model/shift_reg_66_s1/CLEAR | tx_mac_clk:[R] | tx_mac_clk:[R] | 0.000 | 0.010 | 0.558 |
16 | 0.756 | tx_mac_rst_n_3_s0/Q | test[3].u_mac_tx_model/shift_reg_74_s1/CLEAR | tx_mac_clk:[R] | tx_mac_clk:[R] | 0.000 | 0.010 | 0.558 |
17 | 0.756 | tx_mac_rst_n_3_s0/Q | test[3].u_mac_tx_model/shift_reg_82_s1/CLEAR | tx_mac_clk:[R] | tx_mac_clk:[R] | 0.000 | 0.010 | 0.558 |
18 | 0.756 | tx_mac_rst_n_3_s0/Q | test[3].u_mac_tx_model/shift_reg_90_s1/CLEAR | tx_mac_clk:[R] | tx_mac_clk:[R] | 0.000 | 0.010 | 0.558 |
19 | 0.832 | rx_mac_rst_n_2_s0/Q | test[2].u_mac_rx_model/rx_error_all_pause_check_s4/CLEAR | rx_mac_clk:[R] | rx_mac_clk:[R] | 0.000 | -0.007 | 0.650 |
20 | 0.832 | rx_mac_rst_n_2_s0/Q | test[2].u_mac_rx_model/rx_error_all_data_check_s4/CLEAR | rx_mac_clk:[R] | rx_mac_clk:[R] | 0.000 | -0.007 | 0.650 |
21 | 0.833 | tx_mac_rst_n_3_s0/Q | test[3].u_mac_tx_model/pause_value_1_s0/PRESET | tx_mac_clk:[R] | tx_mac_clk:[R] | 0.000 | -0.021 | 0.665 |
22 | 0.833 | tx_mac_rst_n_3_s0/Q | test[3].u_mac_tx_model/pause_value_2_s0/CLEAR | tx_mac_clk:[R] | tx_mac_clk:[R] | 0.000 | -0.021 | 0.665 |
23 | 0.833 | tx_mac_rst_n_3_s0/Q | test[3].u_mac_tx_model/pause_value_3_s0/CLEAR | tx_mac_clk:[R] | tx_mac_clk:[R] | 0.000 | -0.021 | 0.665 |
24 | 0.833 | tx_mac_rst_n_3_s0/Q | test[3].u_mac_tx_model/pause_value_4_s0/PRESET | tx_mac_clk:[R] | tx_mac_clk:[R] | 0.000 | -0.021 | 0.665 |
25 | 0.833 | tx_mac_rst_n_3_s0/Q | test[3].u_mac_tx_model/pause_value_5_s0/CLEAR | tx_mac_clk:[R] | tx_mac_clk:[R] | 0.000 | -0.021 | 0.665 |
Minimum Pulse Width Table:
Number | Slack | Actual Width | Required Width | Type | Clock | Objects |
---|---|---|---|---|---|---|
1 | 1.729 | 2.729 | 1.000 | High Pulse Width | rx_mac_clk | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s |
2 | 1.852 | 2.852 | 1.000 | Low Pulse Width | rx_mac_clk | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s |
3 | 2.419 | 2.669 | 0.250 | High Pulse Width | rx_mac_clk | rx_running_d1_2_s0 |
4 | 2.419 | 2.669 | 0.250 | High Pulse Width | rx_mac_clk | test[3].u_mac_rx_model/rx_mac_data_d1_0_s1 |
5 | 2.419 | 2.669 | 0.250 | High Pulse Width | rx_mac_clk | test[3].u_mac_rx_model/shift_reg_7_s1 |
6 | 2.419 | 2.669 | 0.250 | High Pulse Width | rx_mac_clk | test[3].u_mac_rx_model/pause_value_15_s1 |
7 | 2.419 | 2.669 | 0.250 | High Pulse Width | rx_mac_clk | test[3].u_mac_rx_model/pause_data_2_39_s1 |
8 | 2.419 | 2.669 | 0.250 | High Pulse Width | rx_mac_clk | test[3].u_mac_rx_model/pause_value_14_s1 |
9 | 2.419 | 2.669 | 0.250 | High Pulse Width | rx_mac_clk | test[3].u_mac_rx_model/rx_statistics_vector_d1_23_s1 |
10 | 2.419 | 2.669 | 0.250 | High Pulse Width | rx_mac_clk | test[3].u_mac_rx_model/rx_mac_valid_d4_s0 |
Timing Report By Analysis Type:
Setup Analysis Report
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 0.069 |
Data Arrival Time | 10.774 |
Data Required Time | 10.842 |
From | test[2].u_mac_rx_model/cur_state_1_s0 |
To | test[2].u_mac_rx_model/pause_address_31_s1 |
Launch Clk | rx_mac_clk:[R] |
Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
2.870 | 2.870 | tNET | RR | 1 | R47C116[1][A] | test[2].u_mac_rx_model/cur_state_1_s0/CLK |
3.253 | 0.382 | tC2Q | RR | 13 | R47C116[1][A] | test[2].u_mac_rx_model/cur_state_1_s0/Q |
4.901 | 1.649 | tNET | RR | 1 | R60C112[3][B] | test[2].u_mac_rx_model/n1327_s2/I1 |
5.475 | 0.574 | tINS | RR | 38 | R60C112[3][B] | test[2].u_mac_rx_model/n1327_s2/F |
7.598 | 2.123 | tNET | RR | 1 | R59C121[1][A] | test[2].u_mac_rx_model/n1432_s1/I3 |
8.165 | 0.567 | tINS | RR | 3 | R59C121[1][A] | test[2].u_mac_rx_model/n1432_s1/F |
8.760 | 0.595 | tNET | RR | 1 | R57C119[0][A] | test[2].u_mac_rx_model/n1428_s4/I2 |
9.267 | 0.507 | tINS | RR | 7 | R57C119[0][A] | test[2].u_mac_rx_model/n1428_s4/F |
9.807 | 0.540 | tNET | RR | 1 | R58C120[3][A] | test[2].u_mac_rx_model/n1426_s1/I3 |
10.264 | 0.456 | tINS | RR | 1 | R58C120[3][A] | test[2].u_mac_rx_model/n1426_s1/F |
10.266 | 0.003 | tNET | RR | 1 | R58C120[0][A] | test[2].u_mac_rx_model/n1426_s0/I1 |
10.774 | 0.507 | tINS | RR | 1 | R58C120[0][A] | test[2].u_mac_rx_model/n1426_s0/F |
10.774 | 0.000 | tNET | RR | 1 | R58C120[0][A] | test[2].u_mac_rx_model/pause_address_31_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
8.000 | 8.000 | active clock edge time | ||||
8.000 | 0.000 | rx_mac_clk | ||||
8.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
10.906 | 2.906 | tNET | RR | 1 | R58C120[0][A] | test[2].u_mac_rx_model/pause_address_31_s1/CLK |
10.842 | -0.064 | tSu | 1 | R58C120[0][A] | test[2].u_mac_rx_model/pause_address_31_s1 |
Path Statistics:
Clock Skew | 0.036 |
Setup Relationship | 8.000 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.870, 100.000% |
Arrival Data Path Delay | cell: 2.612, 33.054%; route: 4.909, 62.107%; tC2Q: 0.382, 4.839% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.906, 100.000% |
Path2
Path Summary:
Slack | 0.162 |
Data Arrival Time | 10.691 |
Data Required Time | 10.854 |
From | test[0].u_mac_rx_model/pause_address_0_s1 |
To | test[0].u_mac_rx_model/pause_address_25_s1 |
Launch Clk | rx_mac_clk:[R] |
Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
2.870 | 2.870 | tNET | RR | 1 | R11C116[0][A] | test[0].u_mac_rx_model/pause_address_0_s1/CLK |
3.253 | 0.382 | tC2Q | RR | 7 | R11C116[0][A] | test[0].u_mac_rx_model/pause_address_0_s1/Q |
4.134 | 0.881 | tNET | RR | 1 | R18C119[3][B] | test[0].u_mac_rx_model/n1448_s2/I0 |
4.590 | 0.456 | tINS | RR | 3 | R18C119[3][B] | test[0].u_mac_rx_model/n1448_s2/F |
5.332 | 0.743 | tNET | RR | 1 | R20C118[2][B] | test[0].u_mac_rx_model/n1437_s3/I1 |
5.840 | 0.507 | tINS | RR | 4 | R20C118[2][B] | test[0].u_mac_rx_model/n1437_s3/F |
6.224 | 0.384 | tNET | RR | 1 | R20C115[3][B] | test[0].u_mac_rx_model/n1437_s1/I0 |
6.771 | 0.548 | tINS | RR | 5 | R20C115[3][B] | test[0].u_mac_rx_model/n1437_s1/F |
7.828 | 1.056 | tNET | RR | 1 | R15C116[1][A] | test[0].u_mac_rx_model/n1410_s1/I0 |
8.395 | 0.567 | tINS | RR | 27 | R15C116[1][A] | test[0].u_mac_rx_model/n1410_s1/F |
10.235 | 1.840 | tNET | RR | 1 | R7C114[3][A] | test[0].u_mac_rx_model/n1432_s0/I0 |
10.691 | 0.456 | tINS | RR | 1 | R7C114[3][A] | test[0].u_mac_rx_model/n1432_s0/F |
10.691 | 0.000 | tNET | RR | 1 | R7C114[3][A] | test[0].u_mac_rx_model/pause_address_25_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
8.000 | 8.000 | active clock edge time | ||||
8.000 | 0.000 | rx_mac_clk | ||||
8.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
10.918 | 2.918 | tNET | RR | 1 | R7C114[3][A] | test[0].u_mac_rx_model/pause_address_25_s1/CLK |
10.854 | -0.064 | tSu | 1 | R7C114[3][A] | test[0].u_mac_rx_model/pause_address_25_s1 |
Path Statistics:
Clock Skew | 0.048 |
Setup Relationship | 8.000 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.870, 100.000% |
Arrival Data Path Delay | cell: 2.535, 32.412%; route: 4.904, 62.698%; tC2Q: 0.382, 4.891% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.918, 100.000% |
Path3
Path Summary:
Slack | 0.189 |
Data Arrival Time | 10.127 |
Data Required Time | 10.317 |
From | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_mac_tx_ctrl/frm_byte_cnt_6_s3 |
To | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_mac_tx_ctrl/c_state.s_pause_s12 |
Launch Clk | tx_mac_clk:[R] |
Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 3615 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
2.635 | 2.635 | tNET | RR | 1 | R39C149[2][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_mac_tx_ctrl/frm_byte_cnt_6_s3/CLK |
3.017 | 0.382 | tC2Q | RR | 7 | R39C149[2][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_mac_tx_ctrl/frm_byte_cnt_6_s3/Q |
4.155 | 1.138 | tNET | RR | 1 | R36C150[2][B] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_mac_tx_ctrl/tx_unicast_frm_latch_s7/I1 |
4.734 | 0.579 | tINS | RR | 1 | R36C150[2][B] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_mac_tx_ctrl/tx_unicast_frm_latch_s7/F |
4.736 | 0.003 | tNET | RR | 1 | R36C150[3][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_mac_tx_ctrl/tx_unicast_frm_latch_s6/I0 |
5.284 | 0.548 | tINS | RR | 1 | R36C150[3][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_mac_tx_ctrl/tx_unicast_frm_latch_s6/F |
6.200 | 0.916 | tNET | RR | 1 | R39C149[1][B] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_mac_tx_ctrl/n_state.s_pad_s35/I3 |
6.707 | 0.507 | tINS | RR | 2 | R39C149[1][B] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_mac_tx_ctrl/n_state.s_pad_s35/F |
7.794 | 1.086 | tNET | RR | 1 | R36C148[0][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_mac_tx_ctrl/c_state.s_ifg_s5/I0 |
8.372 | 0.579 | tINS | RR | 2 | R36C148[0][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_mac_tx_ctrl/c_state.s_ifg_s5/F |
8.547 | 0.175 | tNET | RR | 1 | R36C147[1][B] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_mac_tx_ctrl/c_state.s_ifg_s4/I2 |
8.836 | 0.289 | tINS | RR | 8 | R36C147[1][B] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_mac_tx_ctrl/c_state.s_ifg_s4/F |
10.127 | 1.291 | tNET | RR | 1 | R38C150[2][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_mac_tx_ctrl/c_state.s_pause_s12/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
8.000 | 8.000 | active clock edge time | ||||
8.000 | 0.000 | tx_mac_clk | ||||
8.000 | 0.000 | tCL | RR | 3615 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
10.628 | 2.628 | tNET | RR | 1 | R38C150[2][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_mac_tx_ctrl/c_state.s_pause_s12/CLK |
10.317 | -0.311 | tSu | 1 | R38C150[2][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_mac_tx_ctrl/c_state.s_pause_s12 |
Path Statistics:
Clock Skew | -0.007 |
Setup Relationship | 8.000 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.635, 100.000% |
Arrival Data Path Delay | cell: 2.501, 33.383%; route: 4.609, 61.512%; tC2Q: 0.382, 5.105% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.628, 100.000% |
Path4
Path Summary:
Slack | 0.217 |
Data Arrival Time | 10.039 |
Data Required Time | 10.256 |
From | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/tx_mac_ready_o_s0 |
To | test[1].u_mac_tx_model/shift_reg_42_s1 |
Launch Clk | tx_mac_clk:[R] |
Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 3615 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
2.579 | 2.579 | tNET | RR | 1 | R51C159[1][B] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/tx_mac_ready_o_s0/CLK |
2.946 | 0.368 | tC2Q | RF | 40 | R51C159[1][B] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/tx_mac_ready_o_s0/Q |
7.089 | 4.142 | tNET | FF | 1 | R15C149[2][B] | test[1].u_mac_tx_model/shift_reg_111_s4/I1 |
7.656 | 0.567 | tINS | FR | 65 | R15C149[2][B] | test[1].u_mac_tx_model/shift_reg_111_s4/F |
10.039 | 2.383 | tNET | RR | 1 | R13C147[2][B] | test[1].u_mac_tx_model/shift_reg_42_s1/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
8.000 | 8.000 | active clock edge time | ||||
8.000 | 0.000 | tx_mac_clk | ||||
8.000 | 0.000 | tCL | RR | 3615 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
10.567 | 2.567 | tNET | RR | 1 | R13C147[2][B] | test[1].u_mac_tx_model/shift_reg_42_s1/CLK |
10.256 | -0.311 | tSu | 1 | R13C147[2][B] | test[1].u_mac_tx_model/shift_reg_42_s1 |
Path Statistics:
Clock Skew | -0.012 |
Setup Relationship | 8.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.579, 100.000% |
Arrival Data Path Delay | cell: 0.567, 7.607%; route: 6.525, 87.466%; tC2Q: 0.368, 4.926% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.567, 100.000% |
Path5
Path Summary:
Slack | 0.217 |
Data Arrival Time | 10.039 |
Data Required Time | 10.256 |
From | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/tx_mac_ready_o_s0 |
To | test[1].u_mac_tx_model/shift_reg_50_s1 |
Launch Clk | tx_mac_clk:[R] |
Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 3615 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
2.579 | 2.579 | tNET | RR | 1 | R51C159[1][B] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/tx_mac_ready_o_s0/CLK |
2.946 | 0.368 | tC2Q | RF | 40 | R51C159[1][B] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/tx_mac_ready_o_s0/Q |
7.089 | 4.142 | tNET | FF | 1 | R15C149[2][B] | test[1].u_mac_tx_model/shift_reg_111_s4/I1 |
7.656 | 0.567 | tINS | FR | 65 | R15C149[2][B] | test[1].u_mac_tx_model/shift_reg_111_s4/F |
10.039 | 2.383 | tNET | RR | 1 | R13C147[3][A] | test[1].u_mac_tx_model/shift_reg_50_s1/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
8.000 | 8.000 | active clock edge time | ||||
8.000 | 0.000 | tx_mac_clk | ||||
8.000 | 0.000 | tCL | RR | 3615 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
10.567 | 2.567 | tNET | RR | 1 | R13C147[3][A] | test[1].u_mac_tx_model/shift_reg_50_s1/CLK |
10.256 | -0.311 | tSu | 1 | R13C147[3][A] | test[1].u_mac_tx_model/shift_reg_50_s1 |
Path Statistics:
Clock Skew | -0.012 |
Setup Relationship | 8.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.579, 100.000% |
Arrival Data Path Delay | cell: 0.567, 7.607%; route: 6.525, 87.466%; tC2Q: 0.368, 4.926% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.567, 100.000% |
Path6
Path Summary:
Slack | 0.217 |
Data Arrival Time | 10.039 |
Data Required Time | 10.256 |
From | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/tx_mac_ready_o_s0 |
To | test[1].u_mac_tx_model/shift_reg_72_s1 |
Launch Clk | tx_mac_clk:[R] |
Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 3615 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
2.579 | 2.579 | tNET | RR | 1 | R51C159[1][B] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/tx_mac_ready_o_s0/CLK |
2.946 | 0.368 | tC2Q | RF | 40 | R51C159[1][B] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/tx_mac_ready_o_s0/Q |
7.089 | 4.142 | tNET | FF | 1 | R15C149[2][B] | test[1].u_mac_tx_model/shift_reg_111_s4/I1 |
7.656 | 0.567 | tINS | FR | 65 | R15C149[2][B] | test[1].u_mac_tx_model/shift_reg_111_s4/F |
10.039 | 2.383 | tNET | RR | 1 | R13C147[0][A] | test[1].u_mac_tx_model/shift_reg_72_s1/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
8.000 | 8.000 | active clock edge time | ||||
8.000 | 0.000 | tx_mac_clk | ||||
8.000 | 0.000 | tCL | RR | 3615 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
10.567 | 2.567 | tNET | RR | 1 | R13C147[0][A] | test[1].u_mac_tx_model/shift_reg_72_s1/CLK |
10.256 | -0.311 | tSu | 1 | R13C147[0][A] | test[1].u_mac_tx_model/shift_reg_72_s1 |
Path Statistics:
Clock Skew | -0.012 |
Setup Relationship | 8.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.579, 100.000% |
Arrival Data Path Delay | cell: 0.567, 7.607%; route: 6.525, 87.466%; tC2Q: 0.368, 4.926% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.567, 100.000% |
Path7
Path Summary:
Slack | 0.217 |
Data Arrival Time | 10.039 |
Data Required Time | 10.256 |
From | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/tx_mac_ready_o_s0 |
To | test[1].u_mac_tx_model/shift_reg_80_s1 |
Launch Clk | tx_mac_clk:[R] |
Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 3615 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
2.579 | 2.579 | tNET | RR | 1 | R51C159[1][B] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/tx_mac_ready_o_s0/CLK |
2.946 | 0.368 | tC2Q | RF | 40 | R51C159[1][B] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/tx_mac_ready_o_s0/Q |
7.089 | 4.142 | tNET | FF | 1 | R15C149[2][B] | test[1].u_mac_tx_model/shift_reg_111_s4/I1 |
7.656 | 0.567 | tINS | FR | 65 | R15C149[2][B] | test[1].u_mac_tx_model/shift_reg_111_s4/F |
10.039 | 2.383 | tNET | RR | 1 | R13C147[0][B] | test[1].u_mac_tx_model/shift_reg_80_s1/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
8.000 | 8.000 | active clock edge time | ||||
8.000 | 0.000 | tx_mac_clk | ||||
8.000 | 0.000 | tCL | RR | 3615 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
10.567 | 2.567 | tNET | RR | 1 | R13C147[0][B] | test[1].u_mac_tx_model/shift_reg_80_s1/CLK |
10.256 | -0.311 | tSu | 1 | R13C147[0][B] | test[1].u_mac_tx_model/shift_reg_80_s1 |
Path Statistics:
Clock Skew | -0.012 |
Setup Relationship | 8.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.579, 100.000% |
Arrival Data Path Delay | cell: 0.567, 7.607%; route: 6.525, 87.466%; tC2Q: 0.368, 4.926% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.567, 100.000% |
Path8
Path Summary:
Slack | 0.217 |
Data Arrival Time | 10.039 |
Data Required Time | 10.256 |
From | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/tx_mac_ready_o_s0 |
To | test[1].u_mac_tx_model/shift_reg_88_s1 |
Launch Clk | tx_mac_clk:[R] |
Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 3615 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
2.579 | 2.579 | tNET | RR | 1 | R51C159[1][B] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/tx_mac_ready_o_s0/CLK |
2.946 | 0.368 | tC2Q | RF | 40 | R51C159[1][B] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/tx_mac_ready_o_s0/Q |
7.089 | 4.142 | tNET | FF | 1 | R15C149[2][B] | test[1].u_mac_tx_model/shift_reg_111_s4/I1 |
7.656 | 0.567 | tINS | FR | 65 | R15C149[2][B] | test[1].u_mac_tx_model/shift_reg_111_s4/F |
10.039 | 2.383 | tNET | RR | 1 | R13C147[1][A] | test[1].u_mac_tx_model/shift_reg_88_s1/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
8.000 | 8.000 | active clock edge time | ||||
8.000 | 0.000 | tx_mac_clk | ||||
8.000 | 0.000 | tCL | RR | 3615 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
10.567 | 2.567 | tNET | RR | 1 | R13C147[1][A] | test[1].u_mac_tx_model/shift_reg_88_s1/CLK |
10.256 | -0.311 | tSu | 1 | R13C147[1][A] | test[1].u_mac_tx_model/shift_reg_88_s1 |
Path Statistics:
Clock Skew | -0.012 |
Setup Relationship | 8.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.579, 100.000% |
Arrival Data Path Delay | cell: 0.567, 7.607%; route: 6.525, 87.466%; tC2Q: 0.368, 4.926% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.567, 100.000% |
Path9
Path Summary:
Slack | 0.217 |
Data Arrival Time | 10.039 |
Data Required Time | 10.256 |
From | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/tx_mac_ready_o_s0 |
To | test[1].u_mac_tx_model/shift_reg_96_s1 |
Launch Clk | tx_mac_clk:[R] |
Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 3615 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
2.579 | 2.579 | tNET | RR | 1 | R51C159[1][B] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/tx_mac_ready_o_s0/CLK |
2.946 | 0.368 | tC2Q | RF | 40 | R51C159[1][B] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/tx_mac_ready_o_s0/Q |
7.089 | 4.142 | tNET | FF | 1 | R15C149[2][B] | test[1].u_mac_tx_model/shift_reg_111_s4/I1 |
7.656 | 0.567 | tINS | FR | 65 | R15C149[2][B] | test[1].u_mac_tx_model/shift_reg_111_s4/F |
10.039 | 2.383 | tNET | RR | 1 | R13C147[1][B] | test[1].u_mac_tx_model/shift_reg_96_s1/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
8.000 | 8.000 | active clock edge time | ||||
8.000 | 0.000 | tx_mac_clk | ||||
8.000 | 0.000 | tCL | RR | 3615 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
10.567 | 2.567 | tNET | RR | 1 | R13C147[1][B] | test[1].u_mac_tx_model/shift_reg_96_s1/CLK |
10.256 | -0.311 | tSu | 1 | R13C147[1][B] | test[1].u_mac_tx_model/shift_reg_96_s1 |
Path Statistics:
Clock Skew | -0.012 |
Setup Relationship | 8.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.579, 100.000% |
Arrival Data Path Delay | cell: 0.567, 7.607%; route: 6.525, 87.466%; tC2Q: 0.368, 4.926% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.567, 100.000% |
Path10
Path Summary:
Slack | 0.217 |
Data Arrival Time | 10.039 |
Data Required Time | 10.256 |
From | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/tx_mac_ready_o_s0 |
To | test[1].u_mac_tx_model/shift_reg_104_s1 |
Launch Clk | tx_mac_clk:[R] |
Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 3615 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
2.579 | 2.579 | tNET | RR | 1 | R51C159[1][B] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/tx_mac_ready_o_s0/CLK |
2.946 | 0.368 | tC2Q | RF | 40 | R51C159[1][B] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/tx_mac_ready_o_s0/Q |
7.089 | 4.142 | tNET | FF | 1 | R15C149[2][B] | test[1].u_mac_tx_model/shift_reg_111_s4/I1 |
7.656 | 0.567 | tINS | FR | 65 | R15C149[2][B] | test[1].u_mac_tx_model/shift_reg_111_s4/F |
10.039 | 2.383 | tNET | RR | 1 | R13C147[2][A] | test[1].u_mac_tx_model/shift_reg_104_s1/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
8.000 | 8.000 | active clock edge time | ||||
8.000 | 0.000 | tx_mac_clk | ||||
8.000 | 0.000 | tCL | RR | 3615 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
10.567 | 2.567 | tNET | RR | 1 | R13C147[2][A] | test[1].u_mac_tx_model/shift_reg_104_s1/CLK |
10.256 | -0.311 | tSu | 1 | R13C147[2][A] | test[1].u_mac_tx_model/shift_reg_104_s1 |
Path Statistics:
Clock Skew | -0.012 |
Setup Relationship | 8.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.579, 100.000% |
Arrival Data Path Delay | cell: 0.567, 7.607%; route: 6.525, 87.466%; tC2Q: 0.368, 4.926% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.567, 100.000% |
Path11
Path Summary:
Slack | 0.325 |
Data Arrival Time | 10.523 |
Data Required Time | 10.847 |
From | test[2].u_mac_rx_model/cur_state_1_s0 |
To | test[2].u_mac_rx_model/pause_address_32_s1 |
Launch Clk | rx_mac_clk:[R] |
Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
2.870 | 2.870 | tNET | RR | 1 | R47C116[1][A] | test[2].u_mac_rx_model/cur_state_1_s0/CLK |
3.253 | 0.382 | tC2Q | RR | 13 | R47C116[1][A] | test[2].u_mac_rx_model/cur_state_1_s0/Q |
4.901 | 1.649 | tNET | RR | 1 | R60C112[3][B] | test[2].u_mac_rx_model/n1327_s2/I1 |
5.475 | 0.574 | tINS | RR | 38 | R60C112[3][B] | test[2].u_mac_rx_model/n1327_s2/F |
7.598 | 2.123 | tNET | RR | 1 | R59C121[1][A] | test[2].u_mac_rx_model/n1432_s1/I3 |
8.165 | 0.567 | tINS | RR | 3 | R59C121[1][A] | test[2].u_mac_rx_model/n1432_s1/F |
8.760 | 0.595 | tNET | RR | 1 | R57C119[0][A] | test[2].u_mac_rx_model/n1428_s4/I2 |
9.267 | 0.507 | tINS | RR | 7 | R57C119[0][A] | test[2].u_mac_rx_model/n1428_s4/F |
9.445 | 0.178 | tNET | RR | 1 | R57C120[3][A] | test[2].u_mac_rx_model/n1423_s2/I2 |
9.736 | 0.291 | tINS | RR | 3 | R57C120[3][A] | test[2].u_mac_rx_model/n1423_s2/F |
10.015 | 0.279 | tNET | RR | 1 | R56C120[1][B] | test[2].u_mac_rx_model/n1425_s0/I1 |
10.523 | 0.507 | tINS | RR | 1 | R56C120[1][B] | test[2].u_mac_rx_model/n1425_s0/F |
10.523 | 0.000 | tNET | RR | 1 | R56C120[1][B] | test[2].u_mac_rx_model/pause_address_32_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
8.000 | 8.000 | active clock edge time | ||||
8.000 | 0.000 | rx_mac_clk | ||||
8.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
10.911 | 2.911 | tNET | RR | 1 | R56C120[1][B] | test[2].u_mac_rx_model/pause_address_32_s1/CLK |
10.847 | -0.064 | tSu | 1 | R56C120[1][B] | test[2].u_mac_rx_model/pause_address_32_s1 |
Path Statistics:
Clock Skew | 0.041 |
Setup Relationship | 8.000 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.870, 100.000% |
Arrival Data Path Delay | cell: 2.447, 31.983%; route: 4.822, 63.019%; tC2Q: 0.382, 4.998% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.911, 100.000% |
Path12
Path Summary:
Slack | 0.325 |
Data Arrival Time | 10.523 |
Data Required Time | 10.847 |
From | test[2].u_mac_rx_model/cur_state_1_s0 |
To | test[2].u_mac_rx_model/pause_address_33_s1 |
Launch Clk | rx_mac_clk:[R] |
Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
2.870 | 2.870 | tNET | RR | 1 | R47C116[1][A] | test[2].u_mac_rx_model/cur_state_1_s0/CLK |
3.253 | 0.382 | tC2Q | RR | 13 | R47C116[1][A] | test[2].u_mac_rx_model/cur_state_1_s0/Q |
4.901 | 1.649 | tNET | RR | 1 | R60C112[3][B] | test[2].u_mac_rx_model/n1327_s2/I1 |
5.475 | 0.574 | tINS | RR | 38 | R60C112[3][B] | test[2].u_mac_rx_model/n1327_s2/F |
7.598 | 2.123 | tNET | RR | 1 | R59C121[1][A] | test[2].u_mac_rx_model/n1432_s1/I3 |
8.165 | 0.567 | tINS | RR | 3 | R59C121[1][A] | test[2].u_mac_rx_model/n1432_s1/F |
8.760 | 0.595 | tNET | RR | 1 | R57C119[0][A] | test[2].u_mac_rx_model/n1428_s4/I2 |
9.267 | 0.507 | tINS | RR | 7 | R57C119[0][A] | test[2].u_mac_rx_model/n1428_s4/F |
9.445 | 0.178 | tNET | RR | 1 | R57C120[3][A] | test[2].u_mac_rx_model/n1423_s2/I2 |
9.736 | 0.291 | tINS | RR | 3 | R57C120[3][A] | test[2].u_mac_rx_model/n1423_s2/F |
10.015 | 0.279 | tNET | RR | 1 | R56C120[0][B] | test[2].u_mac_rx_model/n1424_s0/I2 |
10.523 | 0.507 | tINS | RR | 1 | R56C120[0][B] | test[2].u_mac_rx_model/n1424_s0/F |
10.523 | 0.000 | tNET | RR | 1 | R56C120[0][B] | test[2].u_mac_rx_model/pause_address_33_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
8.000 | 8.000 | active clock edge time | ||||
8.000 | 0.000 | rx_mac_clk | ||||
8.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
10.911 | 2.911 | tNET | RR | 1 | R56C120[0][B] | test[2].u_mac_rx_model/pause_address_33_s1/CLK |
10.847 | -0.064 | tSu | 1 | R56C120[0][B] | test[2].u_mac_rx_model/pause_address_33_s1 |
Path Statistics:
Clock Skew | 0.041 |
Setup Relationship | 8.000 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.870, 100.000% |
Arrival Data Path Delay | cell: 2.447, 31.983%; route: 4.822, 63.019%; tC2Q: 0.382, 4.998% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.911, 100.000% |
Path13
Path Summary:
Slack | 0.355 |
Data Arrival Time | 10.493 |
Data Required Time | 10.847 |
From | test[2].u_mac_rx_model/cur_state_1_s0 |
To | test[2].u_mac_rx_model/pause_address_34_s1 |
Launch Clk | rx_mac_clk:[R] |
Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
2.870 | 2.870 | tNET | RR | 1 | R47C116[1][A] | test[2].u_mac_rx_model/cur_state_1_s0/CLK |
3.253 | 0.382 | tC2Q | RR | 13 | R47C116[1][A] | test[2].u_mac_rx_model/cur_state_1_s0/Q |
4.901 | 1.649 | tNET | RR | 1 | R60C112[3][B] | test[2].u_mac_rx_model/n1327_s2/I1 |
5.475 | 0.574 | tINS | RR | 38 | R60C112[3][B] | test[2].u_mac_rx_model/n1327_s2/F |
7.598 | 2.123 | tNET | RR | 1 | R59C121[1][A] | test[2].u_mac_rx_model/n1432_s1/I3 |
8.165 | 0.567 | tINS | RR | 3 | R59C121[1][A] | test[2].u_mac_rx_model/n1432_s1/F |
8.760 | 0.595 | tNET | RR | 1 | R57C119[0][A] | test[2].u_mac_rx_model/n1428_s4/I2 |
9.267 | 0.507 | tINS | RR | 7 | R57C119[0][A] | test[2].u_mac_rx_model/n1428_s4/F |
9.445 | 0.178 | tNET | RR | 1 | R57C120[3][A] | test[2].u_mac_rx_model/n1423_s2/I2 |
9.764 | 0.319 | tINS | RF | 3 | R57C120[3][A] | test[2].u_mac_rx_model/n1423_s2/F |
9.925 | 0.161 | tNET | FF | 1 | R56C120[0][A] | test[2].u_mac_rx_model/n1423_s0/I2 |
10.493 | 0.567 | tINS | FR | 1 | R56C120[0][A] | test[2].u_mac_rx_model/n1423_s0/F |
10.493 | 0.000 | tNET | RR | 1 | R56C120[0][A] | test[2].u_mac_rx_model/pause_address_34_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
8.000 | 8.000 | active clock edge time | ||||
8.000 | 0.000 | rx_mac_clk | ||||
8.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
10.911 | 2.911 | tNET | RR | 1 | R56C120[0][A] | test[2].u_mac_rx_model/pause_address_34_s1/CLK |
10.847 | -0.064 | tSu | 1 | R56C120[0][A] | test[2].u_mac_rx_model/pause_address_34_s1 |
Path Statistics:
Clock Skew | 0.041 |
Setup Relationship | 8.000 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.870, 100.000% |
Arrival Data Path Delay | cell: 2.535, 33.257%; route: 4.705, 61.725%; tC2Q: 0.382, 5.018% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.911, 100.000% |
Path14
Path Summary:
Slack | 0.374 |
Data Arrival Time | 10.456 |
Data Required Time | 10.830 |
From | test[0].u_mac_rx_model/pause_address_0_s1 |
To | test[0].u_mac_rx_model/pause_address_31_s1 |
Launch Clk | rx_mac_clk:[R] |
Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
2.870 | 2.870 | tNET | RR | 1 | R11C116[0][A] | test[0].u_mac_rx_model/pause_address_0_s1/CLK |
3.253 | 0.382 | tC2Q | RR | 7 | R11C116[0][A] | test[0].u_mac_rx_model/pause_address_0_s1/Q |
4.134 | 0.881 | tNET | RR | 1 | R18C119[3][B] | test[0].u_mac_rx_model/n1448_s2/I0 |
4.590 | 0.456 | tINS | RR | 3 | R18C119[3][B] | test[0].u_mac_rx_model/n1448_s2/F |
5.332 | 0.743 | tNET | RR | 1 | R20C118[2][B] | test[0].u_mac_rx_model/n1437_s3/I1 |
5.840 | 0.507 | tINS | RR | 4 | R20C118[2][B] | test[0].u_mac_rx_model/n1437_s3/F |
6.224 | 0.384 | tNET | RR | 1 | R20C115[3][B] | test[0].u_mac_rx_model/n1437_s1/I0 |
6.771 | 0.548 | tINS | RR | 5 | R20C115[3][B] | test[0].u_mac_rx_model/n1437_s1/F |
7.828 | 1.056 | tNET | RR | 1 | R15C116[1][A] | test[0].u_mac_rx_model/n1410_s1/I0 |
8.395 | 0.567 | tINS | RR | 27 | R15C116[1][A] | test[0].u_mac_rx_model/n1410_s1/F |
9.878 | 1.482 | tNET | RR | 1 | R9C115[1][B] | test[0].u_mac_rx_model/n1426_s0/I0 |
10.456 | 0.579 | tINS | RR | 1 | R9C115[1][B] | test[0].u_mac_rx_model/n1426_s0/F |
10.456 | 0.000 | tNET | RR | 1 | R9C115[1][B] | test[0].u_mac_rx_model/pause_address_31_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
8.000 | 8.000 | active clock edge time | ||||
8.000 | 0.000 | rx_mac_clk | ||||
8.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
10.894 | 2.894 | tNET | RR | 1 | R9C115[1][B] | test[0].u_mac_rx_model/pause_address_31_s1/CLK |
10.830 | -0.064 | tSu | 1 | R9C115[1][B] | test[0].u_mac_rx_model/pause_address_31_s1 |
Path Statistics:
Clock Skew | 0.024 |
Setup Relationship | 8.000 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.870, 100.000% |
Arrival Data Path Delay | cell: 2.658, 35.030%; route: 4.546, 59.927%; tC2Q: 0.382, 5.042% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.894, 100.000% |
Path15
Path Summary:
Slack | 0.377 |
Data Arrival Time | 10.154 |
Data Required Time | 10.532 |
From | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_frm_lgt_reg_14_s1 |
To | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_pause_val_reg_0_s1 |
Launch Clk | rx_mac_clk:[R] |
Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
2.850 | 2.850 | tNET | RR | 1 | R61C150[0][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_frm_lgt_reg_14_s1/CLK |
3.233 | 0.382 | tC2Q | RR | 4 | R61C150[0][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_frm_lgt_reg_14_s1/Q |
3.621 | 0.389 | tNET | RR | 1 | R62C149[1][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/vlan_reg_15_s9/I0 |
4.189 | 0.567 | tINS | RR | 1 | R62C149[1][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/vlan_reg_15_s9/F |
4.361 | 0.172 | tNET | RR | 1 | R62C150[3][B] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/vlan_reg_15_s8/I3 |
4.818 | 0.456 | tINS | RR | 2 | R62C150[3][B] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/vlan_reg_15_s8/F |
4.971 | 0.154 | tNET | RR | 1 | R62C150[3][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/vlan_reg_15_s5/I3 |
5.290 | 0.319 | tINS | RF | 4 | R62C150[3][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/vlan_reg_15_s5/F |
5.891 | 0.601 | tNET | FF | 1 | R62C154[3][B] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/dest_addr_reg_47_s5/I2 |
6.465 | 0.574 | tINS | FR | 5 | R62C154[3][B] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/dest_addr_reg_47_s5/F |
7.005 | 0.540 | tNET | RR | 1 | R59C154[0][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_pause_val_reg_15_s3/I2 |
7.513 | 0.507 | tINS | RR | 16 | R59C154[0][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_pause_val_reg_15_s3/F |
10.154 | 2.642 | tNET | RR | 1 | R60C149[2][B] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_pause_val_reg_0_s1/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
8.000 | 8.000 | active clock edge time | ||||
8.000 | 0.000 | rx_mac_clk | ||||
8.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
10.843 | 2.843 | tNET | RR | 1 | R60C149[2][B] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_pause_val_reg_0_s1/CLK |
10.532 | -0.311 | tSu | 1 | R60C149[2][B] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_pause_val_reg_0_s1 |
Path Statistics:
Clock Skew | -0.007 |
Setup Relationship | 8.000 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.850, 100.000% |
Arrival Data Path Delay | cell: 2.424, 33.182%; route: 4.498, 61.581%; tC2Q: 0.382, 5.237% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.843, 100.000% |
Path16
Path Summary:
Slack | 0.377 |
Data Arrival Time | 10.157 |
Data Required Time | 10.534 |
From | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_frm_lgt_reg_14_s1 |
To | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_pause_val_reg_1_s1 |
Launch Clk | rx_mac_clk:[R] |
Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
2.850 | 2.850 | tNET | RR | 1 | R61C150[0][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_frm_lgt_reg_14_s1/CLK |
3.233 | 0.382 | tC2Q | RR | 4 | R61C150[0][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_frm_lgt_reg_14_s1/Q |
3.621 | 0.389 | tNET | RR | 1 | R62C149[1][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/vlan_reg_15_s9/I0 |
4.189 | 0.567 | tINS | RR | 1 | R62C149[1][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/vlan_reg_15_s9/F |
4.361 | 0.172 | tNET | RR | 1 | R62C150[3][B] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/vlan_reg_15_s8/I3 |
4.818 | 0.456 | tINS | RR | 2 | R62C150[3][B] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/vlan_reg_15_s8/F |
4.971 | 0.154 | tNET | RR | 1 | R62C150[3][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/vlan_reg_15_s5/I3 |
5.290 | 0.319 | tINS | RF | 4 | R62C150[3][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/vlan_reg_15_s5/F |
5.891 | 0.601 | tNET | FF | 1 | R62C154[3][B] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/dest_addr_reg_47_s5/I2 |
6.465 | 0.574 | tINS | FR | 5 | R62C154[3][B] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/dest_addr_reg_47_s5/F |
7.005 | 0.540 | tNET | RR | 1 | R59C154[0][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_pause_val_reg_15_s3/I2 |
7.513 | 0.507 | tINS | RR | 16 | R59C154[0][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_pause_val_reg_15_s3/F |
10.157 | 2.644 | tNET | RR | 1 | R59C149[1][B] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_pause_val_reg_1_s1/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
8.000 | 8.000 | active clock edge time | ||||
8.000 | 0.000 | rx_mac_clk | ||||
8.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
10.846 | 2.846 | tNET | RR | 1 | R59C149[1][B] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_pause_val_reg_1_s1/CLK |
10.534 | -0.311 | tSu | 1 | R59C149[1][B] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_pause_val_reg_1_s1 |
Path Statistics:
Clock Skew | -0.004 |
Setup Relationship | 8.000 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.850, 100.000% |
Arrival Data Path Delay | cell: 2.424, 33.171%; route: 4.501, 61.594%; tC2Q: 0.382, 5.235% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.846, 100.000% |
Path17
Path Summary:
Slack | 0.377 |
Data Arrival Time | 10.157 |
Data Required Time | 10.534 |
From | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_frm_lgt_reg_14_s1 |
To | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_pause_val_reg_2_s1 |
Launch Clk | rx_mac_clk:[R] |
Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
2.850 | 2.850 | tNET | RR | 1 | R61C150[0][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_frm_lgt_reg_14_s1/CLK |
3.233 | 0.382 | tC2Q | RR | 4 | R61C150[0][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_frm_lgt_reg_14_s1/Q |
3.621 | 0.389 | tNET | RR | 1 | R62C149[1][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/vlan_reg_15_s9/I0 |
4.189 | 0.567 | tINS | RR | 1 | R62C149[1][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/vlan_reg_15_s9/F |
4.361 | 0.172 | tNET | RR | 1 | R62C150[3][B] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/vlan_reg_15_s8/I3 |
4.818 | 0.456 | tINS | RR | 2 | R62C150[3][B] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/vlan_reg_15_s8/F |
4.971 | 0.154 | tNET | RR | 1 | R62C150[3][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/vlan_reg_15_s5/I3 |
5.290 | 0.319 | tINS | RF | 4 | R62C150[3][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/vlan_reg_15_s5/F |
5.891 | 0.601 | tNET | FF | 1 | R62C154[3][B] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/dest_addr_reg_47_s5/I2 |
6.465 | 0.574 | tINS | FR | 5 | R62C154[3][B] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/dest_addr_reg_47_s5/F |
7.005 | 0.540 | tNET | RR | 1 | R59C154[0][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_pause_val_reg_15_s3/I2 |
7.513 | 0.507 | tINS | RR | 16 | R59C154[0][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_pause_val_reg_15_s3/F |
10.157 | 2.644 | tNET | RR | 1 | R59C149[1][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_pause_val_reg_2_s1/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
8.000 | 8.000 | active clock edge time | ||||
8.000 | 0.000 | rx_mac_clk | ||||
8.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
10.846 | 2.846 | tNET | RR | 1 | R59C149[1][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_pause_val_reg_2_s1/CLK |
10.534 | -0.311 | tSu | 1 | R59C149[1][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_pause_val_reg_2_s1 |
Path Statistics:
Clock Skew | -0.004 |
Setup Relationship | 8.000 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.850, 100.000% |
Arrival Data Path Delay | cell: 2.424, 33.171%; route: 4.501, 61.594%; tC2Q: 0.382, 5.235% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.846, 100.000% |
Path18
Path Summary:
Slack | 0.377 |
Data Arrival Time | 10.154 |
Data Required Time | 10.532 |
From | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_frm_lgt_reg_14_s1 |
To | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_pause_val_reg_3_s1 |
Launch Clk | rx_mac_clk:[R] |
Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
2.850 | 2.850 | tNET | RR | 1 | R61C150[0][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_frm_lgt_reg_14_s1/CLK |
3.233 | 0.382 | tC2Q | RR | 4 | R61C150[0][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_frm_lgt_reg_14_s1/Q |
3.621 | 0.389 | tNET | RR | 1 | R62C149[1][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/vlan_reg_15_s9/I0 |
4.189 | 0.567 | tINS | RR | 1 | R62C149[1][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/vlan_reg_15_s9/F |
4.361 | 0.172 | tNET | RR | 1 | R62C150[3][B] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/vlan_reg_15_s8/I3 |
4.818 | 0.456 | tINS | RR | 2 | R62C150[3][B] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/vlan_reg_15_s8/F |
4.971 | 0.154 | tNET | RR | 1 | R62C150[3][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/vlan_reg_15_s5/I3 |
5.290 | 0.319 | tINS | RF | 4 | R62C150[3][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/vlan_reg_15_s5/F |
5.891 | 0.601 | tNET | FF | 1 | R62C154[3][B] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/dest_addr_reg_47_s5/I2 |
6.465 | 0.574 | tINS | FR | 5 | R62C154[3][B] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/dest_addr_reg_47_s5/F |
7.005 | 0.540 | tNET | RR | 1 | R59C154[0][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_pause_val_reg_15_s3/I2 |
7.513 | 0.507 | tINS | RR | 16 | R59C154[0][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_pause_val_reg_15_s3/F |
10.154 | 2.642 | tNET | RR | 1 | R60C149[3][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_pause_val_reg_3_s1/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
8.000 | 8.000 | active clock edge time | ||||
8.000 | 0.000 | rx_mac_clk | ||||
8.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
10.843 | 2.843 | tNET | RR | 1 | R60C149[3][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_pause_val_reg_3_s1/CLK |
10.532 | -0.311 | tSu | 1 | R60C149[3][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_pause_val_reg_3_s1 |
Path Statistics:
Clock Skew | -0.007 |
Setup Relationship | 8.000 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.850, 100.000% |
Arrival Data Path Delay | cell: 2.424, 33.182%; route: 4.498, 61.581%; tC2Q: 0.382, 5.237% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.843, 100.000% |
Path19
Path Summary:
Slack | 0.377 |
Data Arrival Time | 10.157 |
Data Required Time | 10.534 |
From | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_frm_lgt_reg_14_s1 |
To | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_pause_val_reg_4_s1 |
Launch Clk | rx_mac_clk:[R] |
Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
2.850 | 2.850 | tNET | RR | 1 | R61C150[0][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_frm_lgt_reg_14_s1/CLK |
3.233 | 0.382 | tC2Q | RR | 4 | R61C150[0][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_frm_lgt_reg_14_s1/Q |
3.621 | 0.389 | tNET | RR | 1 | R62C149[1][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/vlan_reg_15_s9/I0 |
4.189 | 0.567 | tINS | RR | 1 | R62C149[1][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/vlan_reg_15_s9/F |
4.361 | 0.172 | tNET | RR | 1 | R62C150[3][B] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/vlan_reg_15_s8/I3 |
4.818 | 0.456 | tINS | RR | 2 | R62C150[3][B] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/vlan_reg_15_s8/F |
4.971 | 0.154 | tNET | RR | 1 | R62C150[3][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/vlan_reg_15_s5/I3 |
5.290 | 0.319 | tINS | RF | 4 | R62C150[3][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/vlan_reg_15_s5/F |
5.891 | 0.601 | tNET | FF | 1 | R62C154[3][B] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/dest_addr_reg_47_s5/I2 |
6.465 | 0.574 | tINS | FR | 5 | R62C154[3][B] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/dest_addr_reg_47_s5/F |
7.005 | 0.540 | tNET | RR | 1 | R59C154[0][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_pause_val_reg_15_s3/I2 |
7.513 | 0.507 | tINS | RR | 16 | R59C154[0][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_pause_val_reg_15_s3/F |
10.157 | 2.644 | tNET | RR | 1 | R59C149[2][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_pause_val_reg_4_s1/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
8.000 | 8.000 | active clock edge time | ||||
8.000 | 0.000 | rx_mac_clk | ||||
8.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
10.846 | 2.846 | tNET | RR | 1 | R59C149[2][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_pause_val_reg_4_s1/CLK |
10.534 | -0.311 | tSu | 1 | R59C149[2][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_pause_val_reg_4_s1 |
Path Statistics:
Clock Skew | -0.004 |
Setup Relationship | 8.000 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.850, 100.000% |
Arrival Data Path Delay | cell: 2.424, 33.171%; route: 4.501, 61.594%; tC2Q: 0.382, 5.235% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.846, 100.000% |
Path20
Path Summary:
Slack | 0.377 |
Data Arrival Time | 10.157 |
Data Required Time | 10.534 |
From | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_frm_lgt_reg_14_s1 |
To | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_pause_val_reg_5_s1 |
Launch Clk | rx_mac_clk:[R] |
Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
2.850 | 2.850 | tNET | RR | 1 | R61C150[0][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_frm_lgt_reg_14_s1/CLK |
3.233 | 0.382 | tC2Q | RR | 4 | R61C150[0][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_frm_lgt_reg_14_s1/Q |
3.621 | 0.389 | tNET | RR | 1 | R62C149[1][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/vlan_reg_15_s9/I0 |
4.189 | 0.567 | tINS | RR | 1 | R62C149[1][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/vlan_reg_15_s9/F |
4.361 | 0.172 | tNET | RR | 1 | R62C150[3][B] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/vlan_reg_15_s8/I3 |
4.818 | 0.456 | tINS | RR | 2 | R62C150[3][B] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/vlan_reg_15_s8/F |
4.971 | 0.154 | tNET | RR | 1 | R62C150[3][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/vlan_reg_15_s5/I3 |
5.290 | 0.319 | tINS | RF | 4 | R62C150[3][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/vlan_reg_15_s5/F |
5.891 | 0.601 | tNET | FF | 1 | R62C154[3][B] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/dest_addr_reg_47_s5/I2 |
6.465 | 0.574 | tINS | FR | 5 | R62C154[3][B] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/dest_addr_reg_47_s5/F |
7.005 | 0.540 | tNET | RR | 1 | R59C154[0][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_pause_val_reg_15_s3/I2 |
7.513 | 0.507 | tINS | RR | 16 | R59C154[0][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_pause_val_reg_15_s3/F |
10.157 | 2.644 | tNET | RR | 1 | R59C149[2][B] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_pause_val_reg_5_s1/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
8.000 | 8.000 | active clock edge time | ||||
8.000 | 0.000 | rx_mac_clk | ||||
8.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
10.846 | 2.846 | tNET | RR | 1 | R59C149[2][B] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_pause_val_reg_5_s1/CLK |
10.534 | -0.311 | tSu | 1 | R59C149[2][B] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_pause_val_reg_5_s1 |
Path Statistics:
Clock Skew | -0.004 |
Setup Relationship | 8.000 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.850, 100.000% |
Arrival Data Path Delay | cell: 2.424, 33.171%; route: 4.501, 61.594%; tC2Q: 0.382, 5.235% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.846, 100.000% |
Path21
Path Summary:
Slack | 0.377 |
Data Arrival Time | 10.154 |
Data Required Time | 10.532 |
From | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_frm_lgt_reg_14_s1 |
To | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_pause_val_reg_6_s1 |
Launch Clk | rx_mac_clk:[R] |
Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
2.850 | 2.850 | tNET | RR | 1 | R61C150[0][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_frm_lgt_reg_14_s1/CLK |
3.233 | 0.382 | tC2Q | RR | 4 | R61C150[0][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_frm_lgt_reg_14_s1/Q |
3.621 | 0.389 | tNET | RR | 1 | R62C149[1][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/vlan_reg_15_s9/I0 |
4.189 | 0.567 | tINS | RR | 1 | R62C149[1][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/vlan_reg_15_s9/F |
4.361 | 0.172 | tNET | RR | 1 | R62C150[3][B] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/vlan_reg_15_s8/I3 |
4.818 | 0.456 | tINS | RR | 2 | R62C150[3][B] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/vlan_reg_15_s8/F |
4.971 | 0.154 | tNET | RR | 1 | R62C150[3][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/vlan_reg_15_s5/I3 |
5.290 | 0.319 | tINS | RF | 4 | R62C150[3][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/vlan_reg_15_s5/F |
5.891 | 0.601 | tNET | FF | 1 | R62C154[3][B] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/dest_addr_reg_47_s5/I2 |
6.465 | 0.574 | tINS | FR | 5 | R62C154[3][B] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/dest_addr_reg_47_s5/F |
7.005 | 0.540 | tNET | RR | 1 | R59C154[0][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_pause_val_reg_15_s3/I2 |
7.513 | 0.507 | tINS | RR | 16 | R59C154[0][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_pause_val_reg_15_s3/F |
10.154 | 2.642 | tNET | RR | 1 | R60C149[1][B] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_pause_val_reg_6_s1/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
8.000 | 8.000 | active clock edge time | ||||
8.000 | 0.000 | rx_mac_clk | ||||
8.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
10.843 | 2.843 | tNET | RR | 1 | R60C149[1][B] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_pause_val_reg_6_s1/CLK |
10.532 | -0.311 | tSu | 1 | R60C149[1][B] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_pause_val_reg_6_s1 |
Path Statistics:
Clock Skew | -0.007 |
Setup Relationship | 8.000 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.850, 100.000% |
Arrival Data Path Delay | cell: 2.424, 33.182%; route: 4.498, 61.581%; tC2Q: 0.382, 5.237% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.843, 100.000% |
Path22
Path Summary:
Slack | 0.377 |
Data Arrival Time | 10.154 |
Data Required Time | 10.532 |
From | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_frm_lgt_reg_14_s1 |
To | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_pause_val_reg_8_s1 |
Launch Clk | rx_mac_clk:[R] |
Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
2.850 | 2.850 | tNET | RR | 1 | R61C150[0][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_frm_lgt_reg_14_s1/CLK |
3.233 | 0.382 | tC2Q | RR | 4 | R61C150[0][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_frm_lgt_reg_14_s1/Q |
3.621 | 0.389 | tNET | RR | 1 | R62C149[1][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/vlan_reg_15_s9/I0 |
4.189 | 0.567 | tINS | RR | 1 | R62C149[1][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/vlan_reg_15_s9/F |
4.361 | 0.172 | tNET | RR | 1 | R62C150[3][B] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/vlan_reg_15_s8/I3 |
4.818 | 0.456 | tINS | RR | 2 | R62C150[3][B] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/vlan_reg_15_s8/F |
4.971 | 0.154 | tNET | RR | 1 | R62C150[3][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/vlan_reg_15_s5/I3 |
5.290 | 0.319 | tINS | RF | 4 | R62C150[3][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/vlan_reg_15_s5/F |
5.891 | 0.601 | tNET | FF | 1 | R62C154[3][B] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/dest_addr_reg_47_s5/I2 |
6.465 | 0.574 | tINS | FR | 5 | R62C154[3][B] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/dest_addr_reg_47_s5/F |
7.005 | 0.540 | tNET | RR | 1 | R59C154[0][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_pause_val_reg_15_s3/I2 |
7.513 | 0.507 | tINS | RR | 16 | R59C154[0][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_pause_val_reg_15_s3/F |
10.154 | 2.642 | tNET | RR | 1 | R60C149[2][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_pause_val_reg_8_s1/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
8.000 | 8.000 | active clock edge time | ||||
8.000 | 0.000 | rx_mac_clk | ||||
8.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
10.843 | 2.843 | tNET | RR | 1 | R60C149[2][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_pause_val_reg_8_s1/CLK |
10.532 | -0.311 | tSu | 1 | R60C149[2][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_pause_val_reg_8_s1 |
Path Statistics:
Clock Skew | -0.007 |
Setup Relationship | 8.000 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.850, 100.000% |
Arrival Data Path Delay | cell: 2.424, 33.182%; route: 4.498, 61.581%; tC2Q: 0.382, 5.237% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.843, 100.000% |
Path23
Path Summary:
Slack | 0.377 |
Data Arrival Time | 10.157 |
Data Required Time | 10.534 |
From | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_frm_lgt_reg_14_s1 |
To | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_pause_val_reg_9_s1 |
Launch Clk | rx_mac_clk:[R] |
Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
2.850 | 2.850 | tNET | RR | 1 | R61C150[0][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_frm_lgt_reg_14_s1/CLK |
3.233 | 0.382 | tC2Q | RR | 4 | R61C150[0][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_frm_lgt_reg_14_s1/Q |
3.621 | 0.389 | tNET | RR | 1 | R62C149[1][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/vlan_reg_15_s9/I0 |
4.189 | 0.567 | tINS | RR | 1 | R62C149[1][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/vlan_reg_15_s9/F |
4.361 | 0.172 | tNET | RR | 1 | R62C150[3][B] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/vlan_reg_15_s8/I3 |
4.818 | 0.456 | tINS | RR | 2 | R62C150[3][B] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/vlan_reg_15_s8/F |
4.971 | 0.154 | tNET | RR | 1 | R62C150[3][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/vlan_reg_15_s5/I3 |
5.290 | 0.319 | tINS | RF | 4 | R62C150[3][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/vlan_reg_15_s5/F |
5.891 | 0.601 | tNET | FF | 1 | R62C154[3][B] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/dest_addr_reg_47_s5/I2 |
6.465 | 0.574 | tINS | FR | 5 | R62C154[3][B] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/dest_addr_reg_47_s5/F |
7.005 | 0.540 | tNET | RR | 1 | R59C154[0][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_pause_val_reg_15_s3/I2 |
7.513 | 0.507 | tINS | RR | 16 | R59C154[0][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_pause_val_reg_15_s3/F |
10.157 | 2.644 | tNET | RR | 1 | R59C149[3][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_pause_val_reg_9_s1/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
8.000 | 8.000 | active clock edge time | ||||
8.000 | 0.000 | rx_mac_clk | ||||
8.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
10.846 | 2.846 | tNET | RR | 1 | R59C149[3][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_pause_val_reg_9_s1/CLK |
10.534 | -0.311 | tSu | 1 | R59C149[3][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_pause_val_reg_9_s1 |
Path Statistics:
Clock Skew | -0.004 |
Setup Relationship | 8.000 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.850, 100.000% |
Arrival Data Path Delay | cell: 2.424, 33.171%; route: 4.501, 61.594%; tC2Q: 0.382, 5.235% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.846, 100.000% |
Path24
Path Summary:
Slack | 0.377 |
Data Arrival Time | 10.154 |
Data Required Time | 10.532 |
From | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_frm_lgt_reg_14_s1 |
To | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_pause_val_reg_10_s1 |
Launch Clk | rx_mac_clk:[R] |
Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
2.850 | 2.850 | tNET | RR | 1 | R61C150[0][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_frm_lgt_reg_14_s1/CLK |
3.233 | 0.382 | tC2Q | RR | 4 | R61C150[0][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_frm_lgt_reg_14_s1/Q |
3.621 | 0.389 | tNET | RR | 1 | R62C149[1][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/vlan_reg_15_s9/I0 |
4.189 | 0.567 | tINS | RR | 1 | R62C149[1][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/vlan_reg_15_s9/F |
4.361 | 0.172 | tNET | RR | 1 | R62C150[3][B] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/vlan_reg_15_s8/I3 |
4.818 | 0.456 | tINS | RR | 2 | R62C150[3][B] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/vlan_reg_15_s8/F |
4.971 | 0.154 | tNET | RR | 1 | R62C150[3][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/vlan_reg_15_s5/I3 |
5.290 | 0.319 | tINS | RF | 4 | R62C150[3][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/vlan_reg_15_s5/F |
5.891 | 0.601 | tNET | FF | 1 | R62C154[3][B] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/dest_addr_reg_47_s5/I2 |
6.465 | 0.574 | tINS | FR | 5 | R62C154[3][B] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/dest_addr_reg_47_s5/F |
7.005 | 0.540 | tNET | RR | 1 | R59C154[0][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_pause_val_reg_15_s3/I2 |
7.513 | 0.507 | tINS | RR | 16 | R59C154[0][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_pause_val_reg_15_s3/F |
10.154 | 2.642 | tNET | RR | 1 | R60C149[1][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_pause_val_reg_10_s1/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
8.000 | 8.000 | active clock edge time | ||||
8.000 | 0.000 | rx_mac_clk | ||||
8.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
10.843 | 2.843 | tNET | RR | 1 | R60C149[1][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_pause_val_reg_10_s1/CLK |
10.532 | -0.311 | tSu | 1 | R60C149[1][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_pause_val_reg_10_s1 |
Path Statistics:
Clock Skew | -0.007 |
Setup Relationship | 8.000 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.850, 100.000% |
Arrival Data Path Delay | cell: 2.424, 33.182%; route: 4.498, 61.581%; tC2Q: 0.382, 5.237% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.843, 100.000% |
Path25
Path Summary:
Slack | 0.377 |
Data Arrival Time | 10.154 |
Data Required Time | 10.532 |
From | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_frm_lgt_reg_14_s1 |
To | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_pause_val_reg_11_s1 |
Launch Clk | rx_mac_clk:[R] |
Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
2.850 | 2.850 | tNET | RR | 1 | R61C150[0][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_frm_lgt_reg_14_s1/CLK |
3.233 | 0.382 | tC2Q | RR | 4 | R61C150[0][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_frm_lgt_reg_14_s1/Q |
3.621 | 0.389 | tNET | RR | 1 | R62C149[1][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/vlan_reg_15_s9/I0 |
4.189 | 0.567 | tINS | RR | 1 | R62C149[1][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/vlan_reg_15_s9/F |
4.361 | 0.172 | tNET | RR | 1 | R62C150[3][B] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/vlan_reg_15_s8/I3 |
4.818 | 0.456 | tINS | RR | 2 | R62C150[3][B] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/vlan_reg_15_s8/F |
4.971 | 0.154 | tNET | RR | 1 | R62C150[3][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/vlan_reg_15_s5/I3 |
5.290 | 0.319 | tINS | RF | 4 | R62C150[3][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/vlan_reg_15_s5/F |
5.891 | 0.601 | tNET | FF | 1 | R62C154[3][B] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/dest_addr_reg_47_s5/I2 |
6.465 | 0.574 | tINS | FR | 5 | R62C154[3][B] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/dest_addr_reg_47_s5/F |
7.005 | 0.540 | tNET | RR | 1 | R59C154[0][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_pause_val_reg_15_s3/I2 |
7.513 | 0.507 | tINS | RR | 16 | R59C154[0][A] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_pause_val_reg_15_s3/F |
10.154 | 2.642 | tNET | RR | 1 | R60C149[0][B] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_pause_val_reg_11_s1/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
8.000 | 8.000 | active clock edge time | ||||
8.000 | 0.000 | rx_mac_clk | ||||
8.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
10.843 | 2.843 | tNET | RR | 1 | R60C149[0][B] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_pause_val_reg_11_s1/CLK |
10.532 | -0.311 | tSu | 1 | R60C149[0][B] | u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/rx_pause_val_reg_11_s1 |
Path Statistics:
Clock Skew | -0.007 |
Setup Relationship | 8.000 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.850, 100.000% |
Arrival Data Path Delay | cell: 2.424, 33.182%; route: 4.498, 61.581%; tC2Q: 0.382, 5.237% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.843, 100.000% |
Hold Analysis Report
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 0.263 |
Data Arrival Time | 1.774 |
Data Required Time | 1.510 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_1_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s |
Launch Clk | rx_mac_clk:[R] |
Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
1.255 | 1.255 | tNET | RR | 1 | R11C152[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_1_s0/CLK |
1.435 | 0.180 | tC2Q | RR | 1 | R11C152[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_1_s0/Q |
1.774 | 0.339 | tNET | RR | 1 | BSRAM_R10[33] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[1] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
1.261 | 1.261 | tNET | RR | 1 | BSRAM_R10[33] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA |
1.510 | 0.249 | tHld | 1 | BSRAM_R10[33] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s |
Path Statistics:
Clock Skew | 0.006 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.255, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.339, 65.301%; tC2Q: 0.180, 34.699% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.261, 100.000% |
Path2
Path Summary:
Slack | 0.358 |
Data Arrival Time | 1.869 |
Data Required Time | 1.510 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_3_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s |
Launch Clk | rx_mac_clk:[R] |
Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
1.255 | 1.255 | tNET | RR | 1 | R11C152[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_3_s0/CLK |
1.435 | 0.180 | tC2Q | RR | 1 | R11C152[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_3_s0/Q |
1.869 | 0.434 | tNET | RR | 1 | BSRAM_R10[33] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[3] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
1.261 | 1.261 | tNET | RR | 1 | BSRAM_R10[33] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA |
1.510 | 0.249 | tHld | 1 | BSRAM_R10[33] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s |
Path Statistics:
Clock Skew | 0.006 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.255, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.434, 70.672%; tC2Q: 0.180, 29.328% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.261, 100.000% |
Path3
Path Summary:
Slack | 0.358 |
Data Arrival Time | 1.869 |
Data Required Time | 1.510 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_2_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s |
Launch Clk | rx_mac_clk:[R] |
Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
1.255 | 1.255 | tNET | RR | 1 | R11C152[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_2_s0/CLK |
1.435 | 0.180 | tC2Q | RR | 1 | R11C152[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_2_s0/Q |
1.869 | 0.434 | tNET | RR | 1 | BSRAM_R10[33] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[2] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
1.261 | 1.261 | tNET | RR | 1 | BSRAM_R10[33] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA |
1.510 | 0.249 | tHld | 1 | BSRAM_R10[33] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s |
Path Statistics:
Clock Skew | 0.006 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.255, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.434, 70.672%; tC2Q: 0.180, 29.328% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.261, 100.000% |
Path4
Path Summary:
Slack | 0.374 |
Data Arrival Time | 1.659 |
Data Required Time | 1.286 |
From | test[3].u_mac_rx_model/rx_error_all_pause_check_s4 |
To | test[3].u_mac_rx_model/rx_error_all_pause_check_s4 |
Launch Clk | rx_mac_clk:[R] |
Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
1.284 | 1.284 | tNET | RR | 1 | R5C156[0][A] | test[3].u_mac_rx_model/rx_error_all_pause_check_s4/CLK |
1.461 | 0.176 | tC2Q | RF | 3 | R5C156[0][A] | test[3].u_mac_rx_model/rx_error_all_pause_check_s4/Q |
1.468 | 0.008 | tNET | FF | 1 | R5C156[0][A] | test[3].u_mac_tx_model/n974_s11/I1 |
1.659 | 0.191 | tINS | FF | 1 | R5C156[0][A] | test[3].u_mac_tx_model/n974_s11/F |
1.659 | 0.000 | tNET | FF | 1 | R5C156[0][A] | test[3].u_mac_rx_model/rx_error_all_pause_check_s4/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
1.284 | 1.284 | tNET | RR | 1 | R5C156[0][A] | test[3].u_mac_rx_model/rx_error_all_pause_check_s4/CLK |
1.286 | 0.001 | tHld | 1 | R5C156[0][A] | test[3].u_mac_rx_model/rx_error_all_pause_check_s4 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.284, 100.000% |
Arrival Data Path Delay | cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.284, 100.000% |
Path5
Path Summary:
Slack | 0.374 |
Data Arrival Time | 1.666 |
Data Required Time | 1.293 |
From | test[3].u_mac_rx_model/rx_data_cnt_pause_4_s1 |
To | test[3].u_mac_rx_model/rx_data_cnt_pause_4_s1 |
Launch Clk | rx_mac_clk:[R] |
Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
1.291 | 1.291 | tNET | RR | 1 | R8C137[0][A] | test[3].u_mac_rx_model/rx_data_cnt_pause_4_s1/CLK |
1.467 | 0.176 | tC2Q | RF | 3 | R8C137[0][A] | test[3].u_mac_rx_model/rx_data_cnt_pause_4_s1/Q |
1.475 | 0.008 | tNET | FF | 1 | R8C137[0][A] | test[3].u_mac_rx_model/n2150_s1/I2 |
1.666 | 0.191 | tINS | FF | 1 | R8C137[0][A] | test[3].u_mac_rx_model/n2150_s1/F |
1.666 | 0.000 | tNET | FF | 1 | R8C137[0][A] | test[3].u_mac_rx_model/rx_data_cnt_pause_4_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
1.291 | 1.291 | tNET | RR | 1 | R8C137[0][A] | test[3].u_mac_rx_model/rx_data_cnt_pause_4_s1/CLK |
1.293 | 0.001 | tHld | 1 | R8C137[0][A] | test[3].u_mac_rx_model/rx_data_cnt_pause_4_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.291, 100.000% |
Arrival Data Path Delay | cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.291, 100.000% |
Path6
Path Summary:
Slack | 0.374 |
Data Arrival Time | 1.666 |
Data Required Time | 1.293 |
From | test[3].u_mac_rx_model/rx_data_cnt_pause_5_s1 |
To | test[3].u_mac_rx_model/rx_data_cnt_pause_5_s1 |
Launch Clk | rx_mac_clk:[R] |
Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
1.291 | 1.291 | tNET | RR | 1 | R8C137[1][A] | test[3].u_mac_rx_model/rx_data_cnt_pause_5_s1/CLK |
1.467 | 0.176 | tC2Q | RF | 2 | R8C137[1][A] | test[3].u_mac_rx_model/rx_data_cnt_pause_5_s1/Q |
1.475 | 0.008 | tNET | FF | 1 | R8C137[1][A] | test[3].u_mac_rx_model/n2149_s1/I2 |
1.666 | 0.191 | tINS | FF | 1 | R8C137[1][A] | test[3].u_mac_rx_model/n2149_s1/F |
1.666 | 0.000 | tNET | FF | 1 | R8C137[1][A] | test[3].u_mac_rx_model/rx_data_cnt_pause_5_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
1.291 | 1.291 | tNET | RR | 1 | R8C137[1][A] | test[3].u_mac_rx_model/rx_data_cnt_pause_5_s1/CLK |
1.293 | 0.001 | tHld | 1 | R8C137[1][A] | test[3].u_mac_rx_model/rx_data_cnt_pause_5_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.291, 100.000% |
Arrival Data Path Delay | cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.291, 100.000% |
Path7
Path Summary:
Slack | 0.374 |
Data Arrival Time | 1.672 |
Data Required Time | 1.299 |
From | test[3].u_mac_rx_model/rx_data_cnt_pause_7_s1 |
To | test[3].u_mac_rx_model/rx_data_cnt_pause_7_s1 |
Launch Clk | rx_mac_clk:[R] |
Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
1.297 | 1.297 | tNET | RR | 1 | R7C137[1][A] | test[3].u_mac_rx_model/rx_data_cnt_pause_7_s1/CLK |
1.474 | 0.176 | tC2Q | RF | 5 | R7C137[1][A] | test[3].u_mac_rx_model/rx_data_cnt_pause_7_s1/Q |
1.481 | 0.008 | tNET | FF | 1 | R7C137[1][A] | test[3].u_mac_rx_model/n2147_s3/I0 |
1.672 | 0.191 | tINS | FF | 1 | R7C137[1][A] | test[3].u_mac_rx_model/n2147_s3/F |
1.672 | 0.000 | tNET | FF | 1 | R7C137[1][A] | test[3].u_mac_rx_model/rx_data_cnt_pause_7_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
1.297 | 1.297 | tNET | RR | 1 | R7C137[1][A] | test[3].u_mac_rx_model/rx_data_cnt_pause_7_s1/CLK |
1.299 | 0.001 | tHld | 1 | R7C137[1][A] | test[3].u_mac_rx_model/rx_data_cnt_pause_7_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.297, 100.000% |
Arrival Data Path Delay | cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.297, 100.000% |
Path8
Path Summary:
Slack | 0.374 |
Data Arrival Time | 1.681 |
Data Required Time | 1.307 |
From | test[3].u_mac_rx_model/shift_reg_pause_1_s1 |
To | test[3].u_mac_rx_model/shift_reg_pause_1_s1 |
Launch Clk | rx_mac_clk:[R] |
Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
1.306 | 1.306 | tNET | RR | 1 | R3C135[0][A] | test[3].u_mac_rx_model/shift_reg_pause_1_s1/CLK |
1.482 | 0.176 | tC2Q | RF | 2 | R3C135[0][A] | test[3].u_mac_rx_model/shift_reg_pause_1_s1/Q |
1.490 | 0.008 | tNET | FF | 1 | R3C135[0][A] | test[3].u_mac_rx_model/n1948_s0/I1 |
1.681 | 0.191 | tINS | FF | 1 | R3C135[0][A] | test[3].u_mac_rx_model/n1948_s0/F |
1.681 | 0.000 | tNET | FF | 1 | R3C135[0][A] | test[3].u_mac_rx_model/shift_reg_pause_1_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
1.306 | 1.306 | tNET | RR | 1 | R3C135[0][A] | test[3].u_mac_rx_model/shift_reg_pause_1_s1/CLK |
1.307 | 0.001 | tHld | 1 | R3C135[0][A] | test[3].u_mac_rx_model/shift_reg_pause_1_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.306, 100.000% |
Arrival Data Path Delay | cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.306, 100.000% |
Path9
Path Summary:
Slack | 0.374 |
Data Arrival Time | 1.670 |
Data Required Time | 1.296 |
From | test[3].u_mac_rx_model/shift_reg_pause_2_s1 |
To | test[3].u_mac_rx_model/shift_reg_pause_2_s1 |
Launch Clk | rx_mac_clk:[R] |
Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
1.295 | 1.295 | tNET | RR | 1 | R6C128[1][A] | test[3].u_mac_rx_model/shift_reg_pause_2_s1/CLK |
1.471 | 0.176 | tC2Q | RF | 2 | R6C128[1][A] | test[3].u_mac_rx_model/shift_reg_pause_2_s1/Q |
1.478 | 0.008 | tNET | FF | 1 | R6C128[1][A] | test[3].u_mac_rx_model/n1947_s0/I1 |
1.670 | 0.191 | tINS | FF | 1 | R6C128[1][A] | test[3].u_mac_rx_model/n1947_s0/F |
1.670 | 0.000 | tNET | FF | 1 | R6C128[1][A] | test[3].u_mac_rx_model/shift_reg_pause_2_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
1.295 | 1.295 | tNET | RR | 1 | R6C128[1][A] | test[3].u_mac_rx_model/shift_reg_pause_2_s1/CLK |
1.296 | 0.001 | tHld | 1 | R6C128[1][A] | test[3].u_mac_rx_model/shift_reg_pause_2_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.295, 100.000% |
Arrival Data Path Delay | cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.295, 100.000% |
Path10
Path Summary:
Slack | 0.374 |
Data Arrival Time | 1.682 |
Data Required Time | 1.308 |
From | test[3].u_mac_rx_model/shift_reg_pause_4_s1 |
To | test[3].u_mac_rx_model/shift_reg_pause_4_s1 |
Launch Clk | rx_mac_clk:[R] |
Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
1.307 | 1.307 | tNET | RR | 1 | R5C134[1][A] | test[3].u_mac_rx_model/shift_reg_pause_4_s1/CLK |
1.483 | 0.176 | tC2Q | RF | 2 | R5C134[1][A] | test[3].u_mac_rx_model/shift_reg_pause_4_s1/Q |
1.491 | 0.008 | tNET | FF | 1 | R5C134[1][A] | test[3].u_mac_rx_model/n1945_s0/I1 |
1.682 | 0.191 | tINS | FF | 1 | R5C134[1][A] | test[3].u_mac_rx_model/n1945_s0/F |
1.682 | 0.000 | tNET | FF | 1 | R5C134[1][A] | test[3].u_mac_rx_model/shift_reg_pause_4_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
1.307 | 1.307 | tNET | RR | 1 | R5C134[1][A] | test[3].u_mac_rx_model/shift_reg_pause_4_s1/CLK |
1.308 | 0.001 | tHld | 1 | R5C134[1][A] | test[3].u_mac_rx_model/shift_reg_pause_4_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.307, 100.000% |
Arrival Data Path Delay | cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.307, 100.000% |
Path11
Path Summary:
Slack | 0.374 |
Data Arrival Time | 1.672 |
Data Required Time | 1.299 |
From | test[3].u_mac_rx_model/pause_address_47_s1 |
To | test[3].u_mac_rx_model/pause_address_47_s1 |
Launch Clk | rx_mac_clk:[R] |
Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
1.297 | 1.297 | tNET | RR | 1 | R7C129[1][A] | test[3].u_mac_rx_model/pause_address_47_s1/CLK |
1.474 | 0.176 | tC2Q | RF | 2 | R7C129[1][A] | test[3].u_mac_rx_model/pause_address_47_s1/Q |
1.481 | 0.008 | tNET | FF | 1 | R7C129[1][A] | test[3].u_mac_rx_model/n1410_s0/I3 |
1.672 | 0.191 | tINS | FF | 1 | R7C129[1][A] | test[3].u_mac_rx_model/n1410_s0/F |
1.672 | 0.000 | tNET | FF | 1 | R7C129[1][A] | test[3].u_mac_rx_model/pause_address_47_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
1.297 | 1.297 | tNET | RR | 1 | R7C129[1][A] | test[3].u_mac_rx_model/pause_address_47_s1/CLK |
1.299 | 0.001 | tHld | 1 | R7C129[1][A] | test[3].u_mac_rx_model/pause_address_47_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.297, 100.000% |
Arrival Data Path Delay | cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.297, 100.000% |
Path12
Path Summary:
Slack | 0.374 |
Data Arrival Time | 1.682 |
Data Required Time | 1.308 |
From | test[3].u_mac_rx_model/pause_value_4_s1 |
To | test[3].u_mac_rx_model/pause_value_4_s1 |
Launch Clk | rx_mac_clk:[R] |
Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
1.307 | 1.307 | tNET | RR | 1 | R5C130[0][A] | test[3].u_mac_rx_model/pause_value_4_s1/CLK |
1.483 | 0.176 | tC2Q | RF | 6 | R5C130[0][A] | test[3].u_mac_rx_model/pause_value_4_s1/Q |
1.491 | 0.008 | tNET | FF | 1 | R5C130[0][A] | test[3].u_mac_rx_model/n1334_s0/I3 |
1.682 | 0.191 | tINS | FF | 1 | R5C130[0][A] | test[3].u_mac_rx_model/n1334_s0/F |
1.682 | 0.000 | tNET | FF | 1 | R5C130[0][A] | test[3].u_mac_rx_model/pause_value_4_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
1.307 | 1.307 | tNET | RR | 1 | R5C130[0][A] | test[3].u_mac_rx_model/pause_value_4_s1/CLK |
1.308 | 0.001 | tHld | 1 | R5C130[0][A] | test[3].u_mac_rx_model/pause_value_4_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.307, 100.000% |
Arrival Data Path Delay | cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.307, 100.000% |
Path13
Path Summary:
Slack | 0.374 |
Data Arrival Time | 1.664 |
Data Required Time | 1.290 |
From | test[3].u_mac_rx_model/rx_data_cnt_0_s1 |
To | test[3].u_mac_rx_model/rx_data_cnt_0_s1 |
Launch Clk | rx_mac_clk:[R] |
Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
1.289 | 1.289 | tNET | RR | 1 | R3C152[0][A] | test[3].u_mac_rx_model/rx_data_cnt_0_s1/CLK |
1.465 | 0.176 | tC2Q | RF | 8 | R3C152[0][A] | test[3].u_mac_rx_model/rx_data_cnt_0_s1/Q |
1.472 | 0.008 | tNET | FF | 1 | R3C152[0][A] | test[3].u_mac_rx_model/n1103_s1/I1 |
1.664 | 0.191 | tINS | FF | 1 | R3C152[0][A] | test[3].u_mac_rx_model/n1103_s1/F |
1.664 | 0.000 | tNET | FF | 1 | R3C152[0][A] | test[3].u_mac_rx_model/rx_data_cnt_0_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
1.289 | 1.289 | tNET | RR | 1 | R3C152[0][A] | test[3].u_mac_rx_model/rx_data_cnt_0_s1/CLK |
1.290 | 0.001 | tHld | 1 | R3C152[0][A] | test[3].u_mac_rx_model/rx_data_cnt_0_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.289, 100.000% |
Arrival Data Path Delay | cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.289, 100.000% |
Path14
Path Summary:
Slack | 0.374 |
Data Arrival Time | 1.672 |
Data Required Time | 1.298 |
From | test[3].u_mac_rx_model/rx_data_cnt_2_s1 |
To | test[3].u_mac_rx_model/rx_data_cnt_2_s1 |
Launch Clk | rx_mac_clk:[R] |
Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
1.297 | 1.297 | tNET | RR | 1 | R4C154[0][A] | test[3].u_mac_rx_model/rx_data_cnt_2_s1/CLK |
1.473 | 0.176 | tC2Q | RF | 5 | R4C154[0][A] | test[3].u_mac_rx_model/rx_data_cnt_2_s1/Q |
1.480 | 0.008 | tNET | FF | 1 | R4C154[0][A] | test[3].u_mac_rx_model/n1101_s1/I2 |
1.672 | 0.191 | tINS | FF | 1 | R4C154[0][A] | test[3].u_mac_rx_model/n1101_s1/F |
1.672 | 0.000 | tNET | FF | 1 | R4C154[0][A] | test[3].u_mac_rx_model/rx_data_cnt_2_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
1.297 | 1.297 | tNET | RR | 1 | R4C154[0][A] | test[3].u_mac_rx_model/rx_data_cnt_2_s1/CLK |
1.298 | 0.001 | tHld | 1 | R4C154[0][A] | test[3].u_mac_rx_model/rx_data_cnt_2_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.297, 100.000% |
Arrival Data Path Delay | cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.297, 100.000% |
Path15
Path Summary:
Slack | 0.374 |
Data Arrival Time | 1.682 |
Data Required Time | 1.308 |
From | test[3].u_mac_rx_model/shift_reg_0_s1 |
To | test[3].u_mac_rx_model/shift_reg_0_s1 |
Launch Clk | rx_mac_clk:[R] |
Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
1.307 | 1.307 | tNET | RR | 1 | R5C142[0][A] | test[3].u_mac_rx_model/shift_reg_0_s1/CLK |
1.483 | 0.176 | tC2Q | RF | 2 | R5C142[0][A] | test[3].u_mac_rx_model/shift_reg_0_s1/Q |
1.491 | 0.008 | tNET | FF | 1 | R5C142[0][A] | test[3].u_mac_rx_model/n887_s4/I0 |
1.682 | 0.191 | tINS | FF | 1 | R5C142[0][A] | test[3].u_mac_rx_model/n887_s4/F |
1.682 | 0.000 | tNET | FF | 1 | R5C142[0][A] | test[3].u_mac_rx_model/shift_reg_0_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
1.307 | 1.307 | tNET | RR | 1 | R5C142[0][A] | test[3].u_mac_rx_model/shift_reg_0_s1/CLK |
1.308 | 0.001 | tHld | 1 | R5C142[0][A] | test[3].u_mac_rx_model/shift_reg_0_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.307, 100.000% |
Arrival Data Path Delay | cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.307, 100.000% |
Path16
Path Summary:
Slack | 0.374 |
Data Arrival Time | 1.682 |
Data Required Time | 1.308 |
From | test[3].u_mac_rx_model/shift_reg_2_s1 |
To | test[3].u_mac_rx_model/shift_reg_2_s1 |
Launch Clk | rx_mac_clk:[R] |
Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
1.307 | 1.307 | tNET | RR | 1 | R5C142[1][A] | test[3].u_mac_rx_model/shift_reg_2_s1/CLK |
1.483 | 0.176 | tC2Q | RF | 2 | R5C142[1][A] | test[3].u_mac_rx_model/shift_reg_2_s1/Q |
1.491 | 0.008 | tNET | FF | 1 | R5C142[1][A] | test[3].u_mac_rx_model/n885_s3/I0 |
1.682 | 0.191 | tINS | FF | 1 | R5C142[1][A] | test[3].u_mac_rx_model/n885_s3/F |
1.682 | 0.000 | tNET | FF | 1 | R5C142[1][A] | test[3].u_mac_rx_model/shift_reg_2_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
1.307 | 1.307 | tNET | RR | 1 | R5C142[1][A] | test[3].u_mac_rx_model/shift_reg_2_s1/CLK |
1.308 | 0.001 | tHld | 1 | R5C142[1][A] | test[3].u_mac_rx_model/shift_reg_2_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.307, 100.000% |
Arrival Data Path Delay | cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.307, 100.000% |
Path17
Path Summary:
Slack | 0.374 |
Data Arrival Time | 1.681 |
Data Required Time | 1.307 |
From | test[3].u_mac_rx_model/shift_reg_3_s1 |
To | test[3].u_mac_rx_model/shift_reg_3_s1 |
Launch Clk | rx_mac_clk:[R] |
Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
1.306 | 1.306 | tNET | RR | 1 | R3C141[1][A] | test[3].u_mac_rx_model/shift_reg_3_s1/CLK |
1.482 | 0.176 | tC2Q | RF | 2 | R3C141[1][A] | test[3].u_mac_rx_model/shift_reg_3_s1/Q |
1.490 | 0.008 | tNET | FF | 1 | R3C141[1][A] | test[3].u_mac_rx_model/n884_s3/I0 |
1.681 | 0.191 | tINS | FF | 1 | R3C141[1][A] | test[3].u_mac_rx_model/n884_s3/F |
1.681 | 0.000 | tNET | FF | 1 | R3C141[1][A] | test[3].u_mac_rx_model/shift_reg_3_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
1.306 | 1.306 | tNET | RR | 1 | R3C141[1][A] | test[3].u_mac_rx_model/shift_reg_3_s1/CLK |
1.307 | 0.001 | tHld | 1 | R3C141[1][A] | test[3].u_mac_rx_model/shift_reg_3_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.306, 100.000% |
Arrival Data Path Delay | cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.306, 100.000% |
Path18
Path Summary:
Slack | 0.374 |
Data Arrival Time | 1.672 |
Data Required Time | 1.298 |
From | test[3].u_mac_rx_model/shift_reg_4_s1 |
To | test[3].u_mac_rx_model/shift_reg_4_s1 |
Launch Clk | rx_mac_clk:[R] |
Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
1.297 | 1.297 | tNET | RR | 1 | R5C140[0][A] | test[3].u_mac_rx_model/shift_reg_4_s1/CLK |
1.473 | 0.176 | tC2Q | RF | 2 | R5C140[0][A] | test[3].u_mac_rx_model/shift_reg_4_s1/Q |
1.481 | 0.008 | tNET | FF | 1 | R5C140[0][A] | test[3].u_mac_rx_model/n883_s3/I0 |
1.672 | 0.191 | tINS | FF | 1 | R5C140[0][A] | test[3].u_mac_rx_model/n883_s3/F |
1.672 | 0.000 | tNET | FF | 1 | R5C140[0][A] | test[3].u_mac_rx_model/shift_reg_4_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
1.297 | 1.297 | tNET | RR | 1 | R5C140[0][A] | test[3].u_mac_rx_model/shift_reg_4_s1/CLK |
1.298 | 0.001 | tHld | 1 | R5C140[0][A] | test[3].u_mac_rx_model/shift_reg_4_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.297, 100.000% |
Arrival Data Path Delay | cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.297, 100.000% |
Path19
Path Summary:
Slack | 0.374 |
Data Arrival Time | 1.677 |
Data Required Time | 1.303 |
From | test[3].u_mac_rx_model/shift_reg_12_s1 |
To | test[3].u_mac_rx_model/shift_reg_12_s1 |
Launch Clk | rx_mac_clk:[R] |
Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
1.302 | 1.302 | tNET | RR | 1 | R5C141[1][A] | test[3].u_mac_rx_model/shift_reg_12_s1/CLK |
1.478 | 0.176 | tC2Q | RF | 2 | R5C141[1][A] | test[3].u_mac_rx_model/shift_reg_12_s1/Q |
1.486 | 0.008 | tNET | FF | 1 | R5C141[1][A] | test[3].u_mac_rx_model/n875_s2/I0 |
1.677 | 0.191 | tINS | FF | 1 | R5C141[1][A] | test[3].u_mac_rx_model/n875_s2/F |
1.677 | 0.000 | tNET | FF | 1 | R5C141[1][A] | test[3].u_mac_rx_model/shift_reg_12_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
1.302 | 1.302 | tNET | RR | 1 | R5C141[1][A] | test[3].u_mac_rx_model/shift_reg_12_s1/CLK |
1.303 | 0.001 | tHld | 1 | R5C141[1][A] | test[3].u_mac_rx_model/shift_reg_12_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.302, 100.000% |
Arrival Data Path Delay | cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.302, 100.000% |
Path20
Path Summary:
Slack | 0.374 |
Data Arrival Time | 1.677 |
Data Required Time | 1.303 |
From | test[3].u_mac_rx_model/shift_reg_16_s1 |
To | test[3].u_mac_rx_model/shift_reg_16_s1 |
Launch Clk | rx_mac_clk:[R] |
Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
1.302 | 1.302 | tNET | RR | 1 | R5C141[0][A] | test[3].u_mac_rx_model/shift_reg_16_s1/CLK |
1.478 | 0.176 | tC2Q | RF | 2 | R5C141[0][A] | test[3].u_mac_rx_model/shift_reg_16_s1/Q |
1.486 | 0.008 | tNET | FF | 1 | R5C141[0][A] | test[3].u_mac_rx_model/n871_s2/I0 |
1.677 | 0.191 | tINS | FF | 1 | R5C141[0][A] | test[3].u_mac_rx_model/n871_s2/F |
1.677 | 0.000 | tNET | FF | 1 | R5C141[0][A] | test[3].u_mac_rx_model/shift_reg_16_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
1.302 | 1.302 | tNET | RR | 1 | R5C141[0][A] | test[3].u_mac_rx_model/shift_reg_16_s1/CLK |
1.303 | 0.001 | tHld | 1 | R5C141[0][A] | test[3].u_mac_rx_model/shift_reg_16_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.302, 100.000% |
Arrival Data Path Delay | cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.302, 100.000% |
Path21
Path Summary:
Slack | 0.374 |
Data Arrival Time | 1.674 |
Data Required Time | 1.300 |
From | test[3].u_mac_rx_model/shift_reg_22_s1 |
To | test[3].u_mac_rx_model/shift_reg_22_s1 |
Launch Clk | rx_mac_clk:[R] |
Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
1.299 | 1.299 | tNET | RR | 1 | R4C140[1][A] | test[3].u_mac_rx_model/shift_reg_22_s1/CLK |
1.475 | 0.176 | tC2Q | RF | 2 | R4C140[1][A] | test[3].u_mac_rx_model/shift_reg_22_s1/Q |
1.483 | 0.008 | tNET | FF | 1 | R4C140[1][A] | test[3].u_mac_rx_model/n865_s1/I0 |
1.674 | 0.191 | tINS | FF | 1 | R4C140[1][A] | test[3].u_mac_rx_model/n865_s1/F |
1.674 | 0.000 | tNET | FF | 1 | R4C140[1][A] | test[3].u_mac_rx_model/shift_reg_22_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
1.299 | 1.299 | tNET | RR | 1 | R4C140[1][A] | test[3].u_mac_rx_model/shift_reg_22_s1/CLK |
1.300 | 0.001 | tHld | 1 | R4C140[1][A] | test[3].u_mac_rx_model/shift_reg_22_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.299, 100.000% |
Arrival Data Path Delay | cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.299, 100.000% |
Path22
Path Summary:
Slack | 0.374 |
Data Arrival Time | 1.681 |
Data Required Time | 1.307 |
From | test[3].u_mac_rx_model/shift_reg_27_s1 |
To | test[3].u_mac_rx_model/shift_reg_27_s1 |
Launch Clk | rx_mac_clk:[R] |
Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
1.306 | 1.306 | tNET | RR | 1 | R3C141[0][A] | test[3].u_mac_rx_model/shift_reg_27_s1/CLK |
1.482 | 0.176 | tC2Q | RF | 2 | R3C141[0][A] | test[3].u_mac_rx_model/shift_reg_27_s1/Q |
1.490 | 0.008 | tNET | FF | 1 | R3C141[0][A] | test[3].u_mac_rx_model/n860_s2/I0 |
1.681 | 0.191 | tINS | FF | 1 | R3C141[0][A] | test[3].u_mac_rx_model/n860_s2/F |
1.681 | 0.000 | tNET | FF | 1 | R3C141[0][A] | test[3].u_mac_rx_model/shift_reg_27_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
1.306 | 1.306 | tNET | RR | 1 | R3C141[0][A] | test[3].u_mac_rx_model/shift_reg_27_s1/CLK |
1.307 | 0.001 | tHld | 1 | R3C141[0][A] | test[3].u_mac_rx_model/shift_reg_27_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.306, 100.000% |
Arrival Data Path Delay | cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.306, 100.000% |
Path23
Path Summary:
Slack | 0.374 |
Data Arrival Time | 1.674 |
Data Required Time | 1.300 |
From | test[3].u_mac_rx_model/shift_reg_30_s1 |
To | test[3].u_mac_rx_model/shift_reg_30_s1 |
Launch Clk | rx_mac_clk:[R] |
Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
1.299 | 1.299 | tNET | RR | 1 | R4C140[0][A] | test[3].u_mac_rx_model/shift_reg_30_s1/CLK |
1.475 | 0.176 | tC2Q | RF | 2 | R4C140[0][A] | test[3].u_mac_rx_model/shift_reg_30_s1/Q |
1.483 | 0.008 | tNET | FF | 1 | R4C140[0][A] | test[3].u_mac_rx_model/n857_s1/I0 |
1.674 | 0.191 | tINS | FF | 1 | R4C140[0][A] | test[3].u_mac_rx_model/n857_s1/F |
1.674 | 0.000 | tNET | FF | 1 | R4C140[0][A] | test[3].u_mac_rx_model/shift_reg_30_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
1.299 | 1.299 | tNET | RR | 1 | R4C140[0][A] | test[3].u_mac_rx_model/shift_reg_30_s1/CLK |
1.300 | 0.001 | tHld | 1 | R4C140[0][A] | test[3].u_mac_rx_model/shift_reg_30_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.299, 100.000% |
Arrival Data Path Delay | cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.299, 100.000% |
Path24
Path Summary:
Slack | 0.374 |
Data Arrival Time | 1.676 |
Data Required Time | 1.303 |
From | test[3].u_mac_rx_model/shift_reg_35_s1 |
To | test[3].u_mac_rx_model/shift_reg_35_s1 |
Launch Clk | rx_mac_clk:[R] |
Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
1.301 | 1.301 | tNET | RR | 1 | R3C140[0][A] | test[3].u_mac_rx_model/shift_reg_35_s1/CLK |
1.477 | 0.176 | tC2Q | RF | 2 | R3C140[0][A] | test[3].u_mac_rx_model/shift_reg_35_s1/Q |
1.485 | 0.008 | tNET | FF | 1 | R3C140[0][A] | test[3].u_mac_rx_model/n852_s2/I0 |
1.676 | 0.191 | tINS | FF | 1 | R3C140[0][A] | test[3].u_mac_rx_model/n852_s2/F |
1.676 | 0.000 | tNET | FF | 1 | R3C140[0][A] | test[3].u_mac_rx_model/shift_reg_35_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
1.301 | 1.301 | tNET | RR | 1 | R3C140[0][A] | test[3].u_mac_rx_model/shift_reg_35_s1/CLK |
1.303 | 0.001 | tHld | 1 | R3C140[0][A] | test[3].u_mac_rx_model/shift_reg_35_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.301, 100.000% |
Arrival Data Path Delay | cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.301, 100.000% |
Path25
Path Summary:
Slack | 0.374 |
Data Arrival Time | 1.679 |
Data Required Time | 1.305 |
From | test[3].u_mac_rx_model/shift_reg_37_s1 |
To | test[3].u_mac_rx_model/shift_reg_37_s1 |
Launch Clk | rx_mac_clk:[R] |
Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
1.304 | 1.304 | tNET | RR | 1 | R4C141[0][A] | test[3].u_mac_rx_model/shift_reg_37_s1/CLK |
1.480 | 0.176 | tC2Q | RF | 2 | R4C141[0][A] | test[3].u_mac_rx_model/shift_reg_37_s1/Q |
1.488 | 0.008 | tNET | FF | 1 | R4C141[0][A] | test[3].u_mac_rx_model/n850_s2/I0 |
1.679 | 0.191 | tINS | FF | 1 | R4C141[0][A] | test[3].u_mac_rx_model/n850_s2/F |
1.679 | 0.000 | tNET | FF | 1 | R4C141[0][A] | test[3].u_mac_rx_model/shift_reg_37_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
1.304 | 1.304 | tNET | RR | 1 | R4C141[0][A] | test[3].u_mac_rx_model/shift_reg_37_s1/CLK |
1.305 | 0.001 | tHld | 1 | R4C141[0][A] | test[3].u_mac_rx_model/shift_reg_37_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.304, 100.000% |
Arrival Data Path Delay | cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.304, 100.000% |
Recovery Analysis Report
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 0.025 |
Data Arrival Time | 10.464 |
Data Required Time | 10.489 |
From | rx_mac_rst_n_3_s0 |
To | test[3].u_mac_rx_model/rx_cnt_error_0_s0 |
Launch Clk | rx_mac_clk:[R] |
Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
2.815 | 2.815 | tNET | RR | 1 | R16C147[1][A] | rx_mac_rst_n_3_s0/CLK |
3.183 | 0.368 | tC2Q | RF | 780 | R16C147[1][A] | rx_mac_rst_n_3_s0/Q |
10.464 | 7.281 | tNET | FF | 1 | R5C152[1][A] | test[3].u_mac_rx_model/rx_cnt_error_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
8.000 | 8.000 | active clock edge time | ||||
8.000 | 0.000 | rx_mac_clk | ||||
8.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
10.836 | 2.836 | tNET | RR | 1 | R5C152[1][A] | test[3].u_mac_rx_model/rx_cnt_error_0_s0/CLK |
10.489 | -0.347 | tSu | 1 | R5C152[1][A] | test[3].u_mac_rx_model/rx_cnt_error_0_s0 |
Path Statistics:
Clock Skew | 0.021 |
Setup Relationship | 8.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.815, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 7.281, 95.195%; tC2Q: 0.368, 4.805% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.836, 100.000% |
Path2
Path Summary:
Slack | 0.025 |
Data Arrival Time | 10.464 |
Data Required Time | 10.489 |
From | rx_mac_rst_n_3_s0 |
To | test[3].u_mac_rx_model/rx_data_state_d1_s0 |
Launch Clk | rx_mac_clk:[R] |
Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
2.815 | 2.815 | tNET | RR | 1 | R16C147[1][A] | rx_mac_rst_n_3_s0/CLK |
3.183 | 0.368 | tC2Q | RF | 780 | R16C147[1][A] | rx_mac_rst_n_3_s0/Q |
10.464 | 7.281 | tNET | FF | 1 | R5C152[1][B] | test[3].u_mac_rx_model/rx_data_state_d1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
8.000 | 8.000 | active clock edge time | ||||
8.000 | 0.000 | rx_mac_clk | ||||
8.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
10.836 | 2.836 | tNET | RR | 1 | R5C152[1][B] | test[3].u_mac_rx_model/rx_data_state_d1_s0/CLK |
10.489 | -0.347 | tSu | 1 | R5C152[1][B] | test[3].u_mac_rx_model/rx_data_state_d1_s0 |
Path Statistics:
Clock Skew | 0.021 |
Setup Relationship | 8.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.815, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 7.281, 95.195%; tC2Q: 0.368, 4.805% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.836, 100.000% |
Path3
Path Summary:
Slack | 0.034 |
Data Arrival Time | 10.464 |
Data Required Time | 10.498 |
From | rx_mac_rst_n_3_s0 |
To | test[3].u_mac_rx_model/rx_data_cnt_data_s1 |
Launch Clk | rx_mac_clk:[R] |
Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
2.815 | 2.815 | tNET | RR | 1 | R16C147[1][A] | rx_mac_rst_n_3_s0/CLK |
3.183 | 0.368 | tC2Q | RF | 780 | R16C147[1][A] | rx_mac_rst_n_3_s0/Q |
10.464 | 7.281 | tNET | FF | 1 | R5C153[1][A] | test[3].u_mac_rx_model/rx_data_cnt_data_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
8.000 | 8.000 | active clock edge time | ||||
8.000 | 0.000 | rx_mac_clk | ||||
8.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
10.846 | 2.846 | tNET | RR | 1 | R5C153[1][A] | test[3].u_mac_rx_model/rx_data_cnt_data_s1/CLK |
10.498 | -0.347 | tSu | 1 | R5C153[1][A] | test[3].u_mac_rx_model/rx_data_cnt_data_s1 |
Path Statistics:
Clock Skew | 0.031 |
Setup Relationship | 8.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.815, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 7.281, 95.195%; tC2Q: 0.368, 4.805% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.846, 100.000% |
Path4
Path Summary:
Slack | 0.034 |
Data Arrival Time | 10.464 |
Data Required Time | 10.498 |
From | rx_mac_rst_n_3_s0 |
To | test[3].u_mac_rx_model/rx_data_cnt_1_s1 |
Launch Clk | rx_mac_clk:[R] |
Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
2.815 | 2.815 | tNET | RR | 1 | R16C147[1][A] | rx_mac_rst_n_3_s0/CLK |
3.183 | 0.368 | tC2Q | RF | 780 | R16C147[1][A] | rx_mac_rst_n_3_s0/Q |
10.464 | 7.281 | tNET | FF | 1 | R5C153[2][A] | test[3].u_mac_rx_model/rx_data_cnt_1_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
8.000 | 8.000 | active clock edge time | ||||
8.000 | 0.000 | rx_mac_clk | ||||
8.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
10.846 | 2.846 | tNET | RR | 1 | R5C153[2][A] | test[3].u_mac_rx_model/rx_data_cnt_1_s1/CLK |
10.498 | -0.347 | tSu | 1 | R5C153[2][A] | test[3].u_mac_rx_model/rx_data_cnt_1_s1 |
Path Statistics:
Clock Skew | 0.031 |
Setup Relationship | 8.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.815, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 7.281, 95.195%; tC2Q: 0.368, 4.805% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.846, 100.000% |
Path5
Path Summary:
Slack | 0.034 |
Data Arrival Time | 10.464 |
Data Required Time | 10.498 |
From | rx_mac_rst_n_3_s0 |
To | test[3].u_mac_rx_model/rx_data_cnt_3_s1 |
Launch Clk | rx_mac_clk:[R] |
Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
2.815 | 2.815 | tNET | RR | 1 | R16C147[1][A] | rx_mac_rst_n_3_s0/CLK |
3.183 | 0.368 | tC2Q | RF | 780 | R16C147[1][A] | rx_mac_rst_n_3_s0/Q |
10.464 | 7.281 | tNET | FF | 1 | R5C153[0][A] | test[3].u_mac_rx_model/rx_data_cnt_3_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
8.000 | 8.000 | active clock edge time | ||||
8.000 | 0.000 | rx_mac_clk | ||||
8.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
10.846 | 2.846 | tNET | RR | 1 | R5C153[0][A] | test[3].u_mac_rx_model/rx_data_cnt_3_s1/CLK |
10.498 | -0.347 | tSu | 1 | R5C153[0][A] | test[3].u_mac_rx_model/rx_data_cnt_3_s1 |
Path Statistics:
Clock Skew | 0.031 |
Setup Relationship | 8.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.815, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 7.281, 95.195%; tC2Q: 0.368, 4.805% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.846, 100.000% |
Path6
Path Summary:
Slack | 0.034 |
Data Arrival Time | 10.464 |
Data Required Time | 10.498 |
From | rx_mac_rst_n_3_s0 |
To | test[3].u_mac_rx_model/rx_data_cnt_4_s1 |
Launch Clk | rx_mac_clk:[R] |
Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
2.815 | 2.815 | tNET | RR | 1 | R16C147[1][A] | rx_mac_rst_n_3_s0/CLK |
3.183 | 0.368 | tC2Q | RF | 780 | R16C147[1][A] | rx_mac_rst_n_3_s0/Q |
10.464 | 7.281 | tNET | FF | 1 | R5C153[0][B] | test[3].u_mac_rx_model/rx_data_cnt_4_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
8.000 | 8.000 | active clock edge time | ||||
8.000 | 0.000 | rx_mac_clk | ||||
8.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
10.846 | 2.846 | tNET | RR | 1 | R5C153[0][B] | test[3].u_mac_rx_model/rx_data_cnt_4_s1/CLK |
10.498 | -0.347 | tSu | 1 | R5C153[0][B] | test[3].u_mac_rx_model/rx_data_cnt_4_s1 |
Path Statistics:
Clock Skew | 0.031 |
Setup Relationship | 8.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.815, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 7.281, 95.195%; tC2Q: 0.368, 4.805% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.846, 100.000% |
Path7
Path Summary:
Slack | 0.071 |
Data Arrival Time | 10.430 |
Data Required Time | 10.501 |
From | rx_mac_rst_n_3_s0 |
To | test[3].u_mac_rx_model/rx_statistics_vector_d3_6_s1 |
Launch Clk | rx_mac_clk:[R] |
Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
2.815 | 2.815 | tNET | RR | 1 | R16C147[1][A] | rx_mac_rst_n_3_s0/CLK |
3.183 | 0.368 | tC2Q | RF | 780 | R16C147[1][A] | rx_mac_rst_n_3_s0/Q |
10.430 | 7.247 | tNET | FF | 1 | R4C149[2][B] | test[3].u_mac_rx_model/rx_statistics_vector_d3_6_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
8.000 | 8.000 | active clock edge time | ||||
8.000 | 0.000 | rx_mac_clk | ||||
8.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
10.848 | 2.848 | tNET | RR | 1 | R4C149[2][B] | test[3].u_mac_rx_model/rx_statistics_vector_d3_6_s1/CLK |
10.501 | -0.347 | tSu | 1 | R4C149[2][B] | test[3].u_mac_rx_model/rx_statistics_vector_d3_6_s1 |
Path Statistics:
Clock Skew | 0.033 |
Setup Relationship | 8.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.815, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 7.247, 95.174%; tC2Q: 0.368, 4.826% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.848, 100.000% |
Path8
Path Summary:
Slack | 0.071 |
Data Arrival Time | 10.430 |
Data Required Time | 10.501 |
From | rx_mac_rst_n_3_s0 |
To | test[3].u_mac_rx_model/rx_statistics_vector_d3_7_s1 |
Launch Clk | rx_mac_clk:[R] |
Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
2.815 | 2.815 | tNET | RR | 1 | R16C147[1][A] | rx_mac_rst_n_3_s0/CLK |
3.183 | 0.368 | tC2Q | RF | 780 | R16C147[1][A] | rx_mac_rst_n_3_s0/Q |
10.430 | 7.247 | tNET | FF | 1 | R4C149[1][A] | test[3].u_mac_rx_model/rx_statistics_vector_d3_7_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
8.000 | 8.000 | active clock edge time | ||||
8.000 | 0.000 | rx_mac_clk | ||||
8.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
10.848 | 2.848 | tNET | RR | 1 | R4C149[1][A] | test[3].u_mac_rx_model/rx_statistics_vector_d3_7_s1/CLK |
10.501 | -0.347 | tSu | 1 | R4C149[1][A] | test[3].u_mac_rx_model/rx_statistics_vector_d3_7_s1 |
Path Statistics:
Clock Skew | 0.033 |
Setup Relationship | 8.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.815, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 7.247, 95.174%; tC2Q: 0.368, 4.826% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.848, 100.000% |
Path9
Path Summary:
Slack | 0.071 |
Data Arrival Time | 10.430 |
Data Required Time | 10.501 |
From | rx_mac_rst_n_3_s0 |
To | test[3].u_mac_rx_model/rx_statistics_vector_d3_18_s1 |
Launch Clk | rx_mac_clk:[R] |
Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
2.815 | 2.815 | tNET | RR | 1 | R16C147[1][A] | rx_mac_rst_n_3_s0/CLK |
3.183 | 0.368 | tC2Q | RF | 780 | R16C147[1][A] | rx_mac_rst_n_3_s0/Q |
10.430 | 7.247 | tNET | FF | 1 | R4C149[0][A] | test[3].u_mac_rx_model/rx_statistics_vector_d3_18_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
8.000 | 8.000 | active clock edge time | ||||
8.000 | 0.000 | rx_mac_clk | ||||
8.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
10.848 | 2.848 | tNET | RR | 1 | R4C149[0][A] | test[3].u_mac_rx_model/rx_statistics_vector_d3_18_s1/CLK |
10.501 | -0.347 | tSu | 1 | R4C149[0][A] | test[3].u_mac_rx_model/rx_statistics_vector_d3_18_s1 |
Path Statistics:
Clock Skew | 0.033 |
Setup Relationship | 8.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.815, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 7.247, 95.174%; tC2Q: 0.368, 4.826% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.848, 100.000% |
Path10
Path Summary:
Slack | 0.071 |
Data Arrival Time | 10.430 |
Data Required Time | 10.501 |
From | rx_mac_rst_n_3_s0 |
To | test[3].u_mac_rx_model/rx_statistics_vector_d2_6_s1 |
Launch Clk | rx_mac_clk:[R] |
Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
2.815 | 2.815 | tNET | RR | 1 | R16C147[1][A] | rx_mac_rst_n_3_s0/CLK |
3.183 | 0.368 | tC2Q | RF | 780 | R16C147[1][A] | rx_mac_rst_n_3_s0/Q |
10.430 | 7.247 | tNET | FF | 1 | R4C149[3][A] | test[3].u_mac_rx_model/rx_statistics_vector_d2_6_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
8.000 | 8.000 | active clock edge time | ||||
8.000 | 0.000 | rx_mac_clk | ||||
8.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
10.848 | 2.848 | tNET | RR | 1 | R4C149[3][A] | test[3].u_mac_rx_model/rx_statistics_vector_d2_6_s1/CLK |
10.501 | -0.347 | tSu | 1 | R4C149[3][A] | test[3].u_mac_rx_model/rx_statistics_vector_d2_6_s1 |
Path Statistics:
Clock Skew | 0.033 |
Setup Relationship | 8.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.815, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 7.247, 95.174%; tC2Q: 0.368, 4.826% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.848, 100.000% |
Path11
Path Summary:
Slack | 0.071 |
Data Arrival Time | 10.430 |
Data Required Time | 10.501 |
From | rx_mac_rst_n_3_s0 |
To | test[3].u_mac_rx_model/rx_statistics_vector_d2_7_s1 |
Launch Clk | rx_mac_clk:[R] |
Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
2.815 | 2.815 | tNET | RR | 1 | R16C147[1][A] | rx_mac_rst_n_3_s0/CLK |
3.183 | 0.368 | tC2Q | RF | 780 | R16C147[1][A] | rx_mac_rst_n_3_s0/Q |
10.430 | 7.247 | tNET | FF | 1 | R4C149[1][B] | test[3].u_mac_rx_model/rx_statistics_vector_d2_7_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
8.000 | 8.000 | active clock edge time | ||||
8.000 | 0.000 | rx_mac_clk | ||||
8.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
10.848 | 2.848 | tNET | RR | 1 | R4C149[1][B] | test[3].u_mac_rx_model/rx_statistics_vector_d2_7_s1/CLK |
10.501 | -0.347 | tSu | 1 | R4C149[1][B] | test[3].u_mac_rx_model/rx_statistics_vector_d2_7_s1 |
Path Statistics:
Clock Skew | 0.033 |
Setup Relationship | 8.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.815, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 7.247, 95.174%; tC2Q: 0.368, 4.826% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.848, 100.000% |
Path12
Path Summary:
Slack | 0.071 |
Data Arrival Time | 10.430 |
Data Required Time | 10.501 |
From | rx_mac_rst_n_3_s0 |
To | test[3].u_mac_rx_model/rx_statistics_vector_d2_18_s1 |
Launch Clk | rx_mac_clk:[R] |
Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
2.815 | 2.815 | tNET | RR | 1 | R16C147[1][A] | rx_mac_rst_n_3_s0/CLK |
3.183 | 0.368 | tC2Q | RF | 780 | R16C147[1][A] | rx_mac_rst_n_3_s0/Q |
10.430 | 7.247 | tNET | FF | 1 | R4C149[0][B] | test[3].u_mac_rx_model/rx_statistics_vector_d2_18_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
8.000 | 8.000 | active clock edge time | ||||
8.000 | 0.000 | rx_mac_clk | ||||
8.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
10.848 | 2.848 | tNET | RR | 1 | R4C149[0][B] | test[3].u_mac_rx_model/rx_statistics_vector_d2_18_s1/CLK |
10.501 | -0.347 | tSu | 1 | R4C149[0][B] | test[3].u_mac_rx_model/rx_statistics_vector_d2_18_s1 |
Path Statistics:
Clock Skew | 0.033 |
Setup Relationship | 8.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.815, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 7.247, 95.174%; tC2Q: 0.368, 4.826% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.848, 100.000% |
Path13
Path Summary:
Slack | 0.176 |
Data Arrival Time | 10.385 |
Data Required Time | 10.561 |
From | rx_mac_rst_n_2_s0 |
To | test[2].u_mac_rx_model/shift_reg_pause_94_s1 |
Launch Clk | rx_mac_clk:[R] |
Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
2.875 | 2.875 | tNET | RR | 1 | R17C128[2][A] | rx_mac_rst_n_2_s0/CLK |
3.243 | 0.368 | tC2Q | RF | 780 | R17C128[2][A] | rx_mac_rst_n_2_s0/Q |
10.385 | 7.143 | tNET | FF | 1 | R61C121[1][A] | test[2].u_mac_rx_model/shift_reg_pause_94_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
8.000 | 8.000 | active clock edge time | ||||
8.000 | 0.000 | rx_mac_clk | ||||
8.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
10.908 | 2.908 | tNET | RR | 1 | R61C121[1][A] | test[2].u_mac_rx_model/shift_reg_pause_94_s1/CLK |
10.561 | -0.347 | tSu | 1 | R61C121[1][A] | test[2].u_mac_rx_model/shift_reg_pause_94_s1 |
Path Statistics:
Clock Skew | 0.033 |
Setup Relationship | 8.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.875, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 7.143, 95.107%; tC2Q: 0.368, 4.893% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.908, 100.000% |
Path14
Path Summary:
Slack | 0.176 |
Data Arrival Time | 10.385 |
Data Required Time | 10.561 |
From | rx_mac_rst_n_2_s0 |
To | test[2].u_mac_rx_model/pause_data_2_46_s1 |
Launch Clk | rx_mac_clk:[R] |
Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
2.875 | 2.875 | tNET | RR | 1 | R17C128[2][A] | rx_mac_rst_n_2_s0/CLK |
3.243 | 0.368 | tC2Q | RF | 780 | R17C128[2][A] | rx_mac_rst_n_2_s0/Q |
10.385 | 7.143 | tNET | FF | 1 | R61C121[2][B] | test[2].u_mac_rx_model/pause_data_2_46_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
8.000 | 8.000 | active clock edge time | ||||
8.000 | 0.000 | rx_mac_clk | ||||
8.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
10.908 | 2.908 | tNET | RR | 1 | R61C121[2][B] | test[2].u_mac_rx_model/pause_data_2_46_s1/CLK |
10.561 | -0.347 | tSu | 1 | R61C121[2][B] | test[2].u_mac_rx_model/pause_data_2_46_s1 |
Path Statistics:
Clock Skew | 0.033 |
Setup Relationship | 8.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.875, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 7.143, 95.107%; tC2Q: 0.368, 4.893% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.908, 100.000% |
Path15
Path Summary:
Slack | 0.176 |
Data Arrival Time | 10.385 |
Data Required Time | 10.561 |
From | rx_mac_rst_n_2_s0 |
To | test[2].u_mac_rx_model/pause_address_11_s1 |
Launch Clk | rx_mac_clk:[R] |
Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
2.875 | 2.875 | tNET | RR | 1 | R17C128[2][A] | rx_mac_rst_n_2_s0/CLK |
3.243 | 0.368 | tC2Q | RF | 780 | R17C128[2][A] | rx_mac_rst_n_2_s0/Q |
10.385 | 7.143 | tNET | FF | 1 | R61C121[2][A] | test[2].u_mac_rx_model/pause_address_11_s1/PRESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
8.000 | 8.000 | active clock edge time | ||||
8.000 | 0.000 | rx_mac_clk | ||||
8.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
10.908 | 2.908 | tNET | RR | 1 | R61C121[2][A] | test[2].u_mac_rx_model/pause_address_11_s1/CLK |
10.561 | -0.347 | tSu | 1 | R61C121[2][A] | test[2].u_mac_rx_model/pause_address_11_s1 |
Path Statistics:
Clock Skew | 0.033 |
Setup Relationship | 8.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.875, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 7.143, 95.107%; tC2Q: 0.368, 4.893% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.908, 100.000% |
Path16
Path Summary:
Slack | 0.176 |
Data Arrival Time | 10.385 |
Data Required Time | 10.561 |
From | rx_mac_rst_n_2_s0 |
To | test[2].u_mac_rx_model/pause_address_14_s1 |
Launch Clk | rx_mac_clk:[R] |
Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
2.875 | 2.875 | tNET | RR | 1 | R17C128[2][A] | rx_mac_rst_n_2_s0/CLK |
3.243 | 0.368 | tC2Q | RF | 780 | R17C128[2][A] | rx_mac_rst_n_2_s0/Q |
10.385 | 7.143 | tNET | FF | 1 | R61C121[0][B] | test[2].u_mac_rx_model/pause_address_14_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
8.000 | 8.000 | active clock edge time | ||||
8.000 | 0.000 | rx_mac_clk | ||||
8.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
10.908 | 2.908 | tNET | RR | 1 | R61C121[0][B] | test[2].u_mac_rx_model/pause_address_14_s1/CLK |
10.561 | -0.347 | tSu | 1 | R61C121[0][B] | test[2].u_mac_rx_model/pause_address_14_s1 |
Path Statistics:
Clock Skew | 0.033 |
Setup Relationship | 8.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.875, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 7.143, 95.107%; tC2Q: 0.368, 4.893% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.908, 100.000% |
Path17
Path Summary:
Slack | 0.176 |
Data Arrival Time | 10.385 |
Data Required Time | 10.561 |
From | rx_mac_rst_n_2_s0 |
To | test[2].u_mac_rx_model/pause_address_15_s1 |
Launch Clk | rx_mac_clk:[R] |
Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
2.875 | 2.875 | tNET | RR | 1 | R17C128[2][A] | rx_mac_rst_n_2_s0/CLK |
3.243 | 0.368 | tC2Q | RF | 780 | R17C128[2][A] | rx_mac_rst_n_2_s0/Q |
10.385 | 7.143 | tNET | FF | 1 | R61C121[1][B] | test[2].u_mac_rx_model/pause_address_15_s1/PRESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
8.000 | 8.000 | active clock edge time | ||||
8.000 | 0.000 | rx_mac_clk | ||||
8.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
10.908 | 2.908 | tNET | RR | 1 | R61C121[1][B] | test[2].u_mac_rx_model/pause_address_15_s1/CLK |
10.561 | -0.347 | tSu | 1 | R61C121[1][B] | test[2].u_mac_rx_model/pause_address_15_s1 |
Path Statistics:
Clock Skew | 0.033 |
Setup Relationship | 8.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.875, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 7.143, 95.107%; tC2Q: 0.368, 4.893% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.908, 100.000% |
Path18
Path Summary:
Slack | 0.185 |
Data Arrival Time | 10.385 |
Data Required Time | 10.570 |
From | rx_mac_rst_n_2_s0 |
To | test[2].u_mac_rx_model/pause_data_2_24_s1 |
Launch Clk | rx_mac_clk:[R] |
Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
2.875 | 2.875 | tNET | RR | 1 | R17C128[2][A] | rx_mac_rst_n_2_s0/CLK |
3.243 | 0.368 | tC2Q | RF | 780 | R17C128[2][A] | rx_mac_rst_n_2_s0/Q |
10.385 | 7.143 | tNET | FF | 1 | R61C122[2][A] | test[2].u_mac_rx_model/pause_data_2_24_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
8.000 | 8.000 | active clock edge time | ||||
8.000 | 0.000 | rx_mac_clk | ||||
8.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
10.918 | 2.918 | tNET | RR | 1 | R61C122[2][A] | test[2].u_mac_rx_model/pause_data_2_24_s1/CLK |
10.570 | -0.347 | tSu | 1 | R61C122[2][A] | test[2].u_mac_rx_model/pause_data_2_24_s1 |
Path Statistics:
Clock Skew | 0.043 |
Setup Relationship | 8.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.875, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 7.143, 95.107%; tC2Q: 0.368, 4.893% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.918, 100.000% |
Path19
Path Summary:
Slack | 0.185 |
Data Arrival Time | 10.385 |
Data Required Time | 10.570 |
From | rx_mac_rst_n_2_s0 |
To | test[2].u_mac_rx_model/pause_data_2_26_s1 |
Launch Clk | rx_mac_clk:[R] |
Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
2.875 | 2.875 | tNET | RR | 1 | R17C128[2][A] | rx_mac_rst_n_2_s0/CLK |
3.243 | 0.368 | tC2Q | RF | 780 | R17C128[2][A] | rx_mac_rst_n_2_s0/Q |
10.385 | 7.143 | tNET | FF | 1 | R61C122[3][A] | test[2].u_mac_rx_model/pause_data_2_26_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
8.000 | 8.000 | active clock edge time | ||||
8.000 | 0.000 | rx_mac_clk | ||||
8.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
10.918 | 2.918 | tNET | RR | 1 | R61C122[3][A] | test[2].u_mac_rx_model/pause_data_2_26_s1/CLK |
10.570 | -0.347 | tSu | 1 | R61C122[3][A] | test[2].u_mac_rx_model/pause_data_2_26_s1 |
Path Statistics:
Clock Skew | 0.043 |
Setup Relationship | 8.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.875, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 7.143, 95.107%; tC2Q: 0.368, 4.893% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.918, 100.000% |
Path20
Path Summary:
Slack | 0.185 |
Data Arrival Time | 10.385 |
Data Required Time | 10.570 |
From | rx_mac_rst_n_2_s0 |
To | test[2].u_mac_rx_model/pause_address_16_s1 |
Launch Clk | rx_mac_clk:[R] |
Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
2.875 | 2.875 | tNET | RR | 1 | R17C128[2][A] | rx_mac_rst_n_2_s0/CLK |
3.243 | 0.368 | tC2Q | RF | 780 | R17C128[2][A] | rx_mac_rst_n_2_s0/Q |
10.385 | 7.143 | tNET | FF | 1 | R61C122[0][A] | test[2].u_mac_rx_model/pause_address_16_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
8.000 | 8.000 | active clock edge time | ||||
8.000 | 0.000 | rx_mac_clk | ||||
8.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
10.918 | 2.918 | tNET | RR | 1 | R61C122[0][A] | test[2].u_mac_rx_model/pause_address_16_s1/CLK |
10.570 | -0.347 | tSu | 1 | R61C122[0][A] | test[2].u_mac_rx_model/pause_address_16_s1 |
Path Statistics:
Clock Skew | 0.043 |
Setup Relationship | 8.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.875, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 7.143, 95.107%; tC2Q: 0.368, 4.893% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.918, 100.000% |
Path21
Path Summary:
Slack | 0.185 |
Data Arrival Time | 10.385 |
Data Required Time | 10.570 |
From | rx_mac_rst_n_2_s0 |
To | test[2].u_mac_rx_model/pause_address_17_s1 |
Launch Clk | rx_mac_clk:[R] |
Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
2.875 | 2.875 | tNET | RR | 1 | R17C128[2][A] | rx_mac_rst_n_2_s0/CLK |
3.243 | 0.368 | tC2Q | RF | 780 | R17C128[2][A] | rx_mac_rst_n_2_s0/Q |
10.385 | 7.143 | tNET | FF | 1 | R61C122[1][A] | test[2].u_mac_rx_model/pause_address_17_s1/PRESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
8.000 | 8.000 | active clock edge time | ||||
8.000 | 0.000 | rx_mac_clk | ||||
8.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
10.918 | 2.918 | tNET | RR | 1 | R61C122[1][A] | test[2].u_mac_rx_model/pause_address_17_s1/CLK |
10.570 | -0.347 | tSu | 1 | R61C122[1][A] | test[2].u_mac_rx_model/pause_address_17_s1 |
Path Statistics:
Clock Skew | 0.043 |
Setup Relationship | 8.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.875, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 7.143, 95.107%; tC2Q: 0.368, 4.893% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.918, 100.000% |
Path22
Path Summary:
Slack | 0.205 |
Data Arrival Time | 10.349 |
Data Required Time | 10.553 |
From | rx_mac_rst_n_2_s0 |
To | test[2].u_mac_rx_model/shift_reg_pause_91_s1 |
Launch Clk | rx_mac_clk:[R] |
Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
2.875 | 2.875 | tNET | RR | 1 | R17C128[2][A] | rx_mac_rst_n_2_s0/CLK |
3.243 | 0.368 | tC2Q | RF | 780 | R17C128[2][A] | rx_mac_rst_n_2_s0/Q |
10.349 | 7.106 | tNET | FF | 1 | R62C119[1][B] | test[2].u_mac_rx_model/shift_reg_pause_91_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
8.000 | 8.000 | active clock edge time | ||||
8.000 | 0.000 | rx_mac_clk | ||||
8.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
10.901 | 2.901 | tNET | RR | 1 | R62C119[1][B] | test[2].u_mac_rx_model/shift_reg_pause_91_s1/CLK |
10.553 | -0.347 | tSu | 1 | R62C119[1][B] | test[2].u_mac_rx_model/shift_reg_pause_91_s1 |
Path Statistics:
Clock Skew | 0.026 |
Setup Relationship | 8.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.875, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 7.106, 95.083%; tC2Q: 0.368, 4.917% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.901, 100.000% |
Path23
Path Summary:
Slack | 0.205 |
Data Arrival Time | 10.349 |
Data Required Time | 10.553 |
From | rx_mac_rst_n_2_s0 |
To | test[2].u_mac_rx_model/pause_data_2_42_s1 |
Launch Clk | rx_mac_clk:[R] |
Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
2.875 | 2.875 | tNET | RR | 1 | R17C128[2][A] | rx_mac_rst_n_2_s0/CLK |
3.243 | 0.368 | tC2Q | RF | 780 | R17C128[2][A] | rx_mac_rst_n_2_s0/Q |
10.349 | 7.106 | tNET | FF | 1 | R62C119[2][A] | test[2].u_mac_rx_model/pause_data_2_42_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
8.000 | 8.000 | active clock edge time | ||||
8.000 | 0.000 | rx_mac_clk | ||||
8.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
10.901 | 2.901 | tNET | RR | 1 | R62C119[2][A] | test[2].u_mac_rx_model/pause_data_2_42_s1/CLK |
10.553 | -0.347 | tSu | 1 | R62C119[2][A] | test[2].u_mac_rx_model/pause_data_2_42_s1 |
Path Statistics:
Clock Skew | 0.026 |
Setup Relationship | 8.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.875, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 7.106, 95.083%; tC2Q: 0.368, 4.917% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.901, 100.000% |
Path24
Path Summary:
Slack | 0.205 |
Data Arrival Time | 10.349 |
Data Required Time | 10.553 |
From | rx_mac_rst_n_2_s0 |
To | test[2].u_mac_rx_model/pause_data_2_43_s1 |
Launch Clk | rx_mac_clk:[R] |
Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
2.875 | 2.875 | tNET | RR | 1 | R17C128[2][A] | rx_mac_rst_n_2_s0/CLK |
3.243 | 0.368 | tC2Q | RF | 780 | R17C128[2][A] | rx_mac_rst_n_2_s0/Q |
10.349 | 7.106 | tNET | FF | 1 | R62C119[2][B] | test[2].u_mac_rx_model/pause_data_2_43_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
8.000 | 8.000 | active clock edge time | ||||
8.000 | 0.000 | rx_mac_clk | ||||
8.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
10.901 | 2.901 | tNET | RR | 1 | R62C119[2][B] | test[2].u_mac_rx_model/pause_data_2_43_s1/CLK |
10.553 | -0.347 | tSu | 1 | R62C119[2][B] | test[2].u_mac_rx_model/pause_data_2_43_s1 |
Path Statistics:
Clock Skew | 0.026 |
Setup Relationship | 8.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.875, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 7.106, 95.083%; tC2Q: 0.368, 4.917% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.901, 100.000% |
Path25
Path Summary:
Slack | 0.205 |
Data Arrival Time | 10.349 |
Data Required Time | 10.553 |
From | rx_mac_rst_n_2_s0 |
To | test[2].u_mac_rx_model/pause_data_2_44_s1 |
Launch Clk | rx_mac_clk:[R] |
Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
2.875 | 2.875 | tNET | RR | 1 | R17C128[2][A] | rx_mac_rst_n_2_s0/CLK |
3.243 | 0.368 | tC2Q | RF | 780 | R17C128[2][A] | rx_mac_rst_n_2_s0/Q |
10.349 | 7.106 | tNET | FF | 1 | R62C119[1][A] | test[2].u_mac_rx_model/pause_data_2_44_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
8.000 | 8.000 | active clock edge time | ||||
8.000 | 0.000 | rx_mac_clk | ||||
8.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
10.901 | 2.901 | tNET | RR | 1 | R62C119[1][A] | test[2].u_mac_rx_model/pause_data_2_44_s1/CLK |
10.553 | -0.347 | tSu | 1 | R62C119[1][A] | test[2].u_mac_rx_model/pause_data_2_44_s1 |
Path Statistics:
Clock Skew | 0.026 |
Setup Relationship | 8.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.875, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 7.106, 95.083%; tC2Q: 0.368, 4.917% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.901, 100.000% |
Removal Analysis Report
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 0.629 |
Data Arrival Time | 1.675 |
Data Required Time | 1.046 |
From | tx_mac_rst_n_3_s0 |
To | test[3].u_mac_tx_model/shift_reg_78_s1 |
Launch Clk | tx_mac_clk:[R] |
Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 3615 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
1.250 | 1.250 | tNET | RR | 1 | R15C129[0][A] | tx_mac_rst_n_3_s0/CLK |
1.430 | 0.180 | tC2Q | RR | 378 | R15C129[0][A] | tx_mac_rst_n_3_s0/Q |
1.675 | 0.245 | tNET | RR | 1 | R14C131[1][A] | test[3].u_mac_tx_model/shift_reg_78_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 3615 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
1.235 | 1.235 | tNET | RR | 1 | R14C131[1][A] | test[3].u_mac_tx_model/shift_reg_78_s1/CLK |
1.046 | -0.189 | tHld | 1 | R14C131[1][A] | test[3].u_mac_tx_model/shift_reg_78_s1 |
Path Statistics:
Clock Skew | -0.015 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.250, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.245, 57.647%; tC2Q: 0.180, 42.353% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.235, 100.000% |
Path2
Path Summary:
Slack | 0.629 |
Data Arrival Time | 1.675 |
Data Required Time | 1.046 |
From | tx_mac_rst_n_3_s0 |
To | test[3].u_mac_tx_model/shift_reg_86_s1 |
Launch Clk | tx_mac_clk:[R] |
Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 3615 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
1.250 | 1.250 | tNET | RR | 1 | R15C129[0][A] | tx_mac_rst_n_3_s0/CLK |
1.430 | 0.180 | tC2Q | RR | 378 | R15C129[0][A] | tx_mac_rst_n_3_s0/Q |
1.675 | 0.245 | tNET | RR | 1 | R14C131[1][B] | test[3].u_mac_tx_model/shift_reg_86_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 3615 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
1.235 | 1.235 | tNET | RR | 1 | R14C131[1][B] | test[3].u_mac_tx_model/shift_reg_86_s1/CLK |
1.046 | -0.189 | tHld | 1 | R14C131[1][B] | test[3].u_mac_tx_model/shift_reg_86_s1 |
Path Statistics:
Clock Skew | -0.015 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.250, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.245, 57.647%; tC2Q: 0.180, 42.353% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.235, 100.000% |
Path3
Path Summary:
Slack | 0.629 |
Data Arrival Time | 1.675 |
Data Required Time | 1.046 |
From | tx_mac_rst_n_3_s0 |
To | test[3].u_mac_tx_model/shift_reg_94_s1 |
Launch Clk | tx_mac_clk:[R] |
Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 3615 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
1.250 | 1.250 | tNET | RR | 1 | R15C129[0][A] | tx_mac_rst_n_3_s0/CLK |
1.430 | 0.180 | tC2Q | RR | 378 | R15C129[0][A] | tx_mac_rst_n_3_s0/Q |
1.675 | 0.245 | tNET | RR | 1 | R14C131[2][A] | test[3].u_mac_tx_model/shift_reg_94_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 3615 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
1.235 | 1.235 | tNET | RR | 1 | R14C131[2][A] | test[3].u_mac_tx_model/shift_reg_94_s1/CLK |
1.046 | -0.189 | tHld | 1 | R14C131[2][A] | test[3].u_mac_tx_model/shift_reg_94_s1 |
Path Statistics:
Clock Skew | -0.015 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.250, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.245, 57.647%; tC2Q: 0.180, 42.353% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.235, 100.000% |
Path4
Path Summary:
Slack | 0.629 |
Data Arrival Time | 1.675 |
Data Required Time | 1.046 |
From | tx_mac_rst_n_3_s0 |
To | test[3].u_mac_tx_model/shift_reg_102_s1 |
Launch Clk | tx_mac_clk:[R] |
Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 3615 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
1.250 | 1.250 | tNET | RR | 1 | R15C129[0][A] | tx_mac_rst_n_3_s0/CLK |
1.430 | 0.180 | tC2Q | RR | 378 | R15C129[0][A] | tx_mac_rst_n_3_s0/Q |
1.675 | 0.245 | tNET | RR | 1 | R14C131[2][B] | test[3].u_mac_tx_model/shift_reg_102_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 3615 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
1.235 | 1.235 | tNET | RR | 1 | R14C131[2][B] | test[3].u_mac_tx_model/shift_reg_102_s1/CLK |
1.046 | -0.189 | tHld | 1 | R14C131[2][B] | test[3].u_mac_tx_model/shift_reg_102_s1 |
Path Statistics:
Clock Skew | -0.015 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.250, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.245, 57.647%; tC2Q: 0.180, 42.353% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.235, 100.000% |
Path5
Path Summary:
Slack | 0.629 |
Data Arrival Time | 1.675 |
Data Required Time | 1.046 |
From | tx_mac_rst_n_3_s0 |
To | test[3].u_mac_tx_model/shift_reg_110_s1 |
Launch Clk | tx_mac_clk:[R] |
Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 3615 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
1.250 | 1.250 | tNET | RR | 1 | R15C129[0][A] | tx_mac_rst_n_3_s0/CLK |
1.430 | 0.180 | tC2Q | RR | 378 | R15C129[0][A] | tx_mac_rst_n_3_s0/Q |
1.675 | 0.245 | tNET | RR | 1 | R14C131[3][A] | test[3].u_mac_tx_model/shift_reg_110_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 3615 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
1.235 | 1.235 | tNET | RR | 1 | R14C131[3][A] | test[3].u_mac_tx_model/shift_reg_110_s1/CLK |
1.046 | -0.189 | tHld | 1 | R14C131[3][A] | test[3].u_mac_tx_model/shift_reg_110_s1 |
Path Statistics:
Clock Skew | -0.015 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.250, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.245, 57.647%; tC2Q: 0.180, 42.353% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.235, 100.000% |
Path6
Path Summary:
Slack | 0.751 |
Data Arrival Time | 1.808 |
Data Required Time | 1.056 |
From | tx_mac_rst_n_3_s0 |
To | test[3].u_mac_tx_model/shift_reg_46_s1 |
Launch Clk | tx_mac_clk:[R] |
Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 3615 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
1.250 | 1.250 | tNET | RR | 1 | R15C129[0][A] | tx_mac_rst_n_3_s0/CLK |
1.430 | 0.180 | tC2Q | RR | 378 | R15C129[0][A] | tx_mac_rst_n_3_s0/Q |
1.807 | 0.377 | tNET | RR | 1 | R14C133[2][A] | test[3].u_mac_tx_model/shift_reg_46_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 3615 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
1.245 | 1.245 | tNET | RR | 1 | R14C133[2][A] | test[3].u_mac_tx_model/shift_reg_46_s1/CLK |
1.056 | -0.189 | tHld | 1 | R14C133[2][A] | test[3].u_mac_tx_model/shift_reg_46_s1 |
Path Statistics:
Clock Skew | -0.005 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.250, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.377, 67.713%; tC2Q: 0.180, 32.287% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.245, 100.000% |
Path7
Path Summary:
Slack | 0.751 |
Data Arrival Time | 1.808 |
Data Required Time | 1.056 |
From | tx_mac_rst_n_3_s0 |
To | test[3].u_mac_tx_model/shift_reg_54_s1 |
Launch Clk | tx_mac_clk:[R] |
Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 3615 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
1.250 | 1.250 | tNET | RR | 1 | R15C129[0][A] | tx_mac_rst_n_3_s0/CLK |
1.430 | 0.180 | tC2Q | RR | 378 | R15C129[0][A] | tx_mac_rst_n_3_s0/Q |
1.807 | 0.377 | tNET | RR | 1 | R14C133[2][B] | test[3].u_mac_tx_model/shift_reg_54_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 3615 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
1.245 | 1.245 | tNET | RR | 1 | R14C133[2][B] | test[3].u_mac_tx_model/shift_reg_54_s1/CLK |
1.056 | -0.189 | tHld | 1 | R14C133[2][B] | test[3].u_mac_tx_model/shift_reg_54_s1 |
Path Statistics:
Clock Skew | -0.005 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.250, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.377, 67.713%; tC2Q: 0.180, 32.287% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.245, 100.000% |
Path8
Path Summary:
Slack | 0.751 |
Data Arrival Time | 1.808 |
Data Required Time | 1.056 |
From | tx_mac_rst_n_3_s0 |
To | test[3].u_mac_tx_model/shift_reg_62_s1 |
Launch Clk | tx_mac_clk:[R] |
Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 3615 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
1.250 | 1.250 | tNET | RR | 1 | R15C129[0][A] | tx_mac_rst_n_3_s0/CLK |
1.430 | 0.180 | tC2Q | RR | 378 | R15C129[0][A] | tx_mac_rst_n_3_s0/Q |
1.807 | 0.377 | tNET | RR | 1 | R14C133[1][A] | test[3].u_mac_tx_model/shift_reg_62_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 3615 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
1.245 | 1.245 | tNET | RR | 1 | R14C133[1][A] | test[3].u_mac_tx_model/shift_reg_62_s1/CLK |
1.056 | -0.189 | tHld | 1 | R14C133[1][A] | test[3].u_mac_tx_model/shift_reg_62_s1 |
Path Statistics:
Clock Skew | -0.005 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.250, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.377, 67.713%; tC2Q: 0.180, 32.287% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.245, 100.000% |
Path9
Path Summary:
Slack | 0.751 |
Data Arrival Time | 1.808 |
Data Required Time | 1.056 |
From | tx_mac_rst_n_3_s0 |
To | test[3].u_mac_tx_model/shift_reg_70_s1 |
Launch Clk | tx_mac_clk:[R] |
Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 3615 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
1.250 | 1.250 | tNET | RR | 1 | R15C129[0][A] | tx_mac_rst_n_3_s0/CLK |
1.430 | 0.180 | tC2Q | RR | 378 | R15C129[0][A] | tx_mac_rst_n_3_s0/Q |
1.807 | 0.377 | tNET | RR | 1 | R14C133[1][B] | test[3].u_mac_tx_model/shift_reg_70_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 3615 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
1.245 | 1.245 | tNET | RR | 1 | R14C133[1][B] | test[3].u_mac_tx_model/shift_reg_70_s1/CLK |
1.056 | -0.189 | tHld | 1 | R14C133[1][B] | test[3].u_mac_tx_model/shift_reg_70_s1 |
Path Statistics:
Clock Skew | -0.005 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.250, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.377, 67.713%; tC2Q: 0.180, 32.287% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.245, 100.000% |
Path10
Path Summary:
Slack | 0.751 |
Data Arrival Time | 1.808 |
Data Required Time | 1.056 |
From | tx_mac_rst_n_3_s0 |
To | test[3].u_mac_tx_model/shift_reg_98_s1 |
Launch Clk | tx_mac_clk:[R] |
Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 3615 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
1.250 | 1.250 | tNET | RR | 1 | R15C129[0][A] | tx_mac_rst_n_3_s0/CLK |
1.430 | 0.180 | tC2Q | RR | 378 | R15C129[0][A] | tx_mac_rst_n_3_s0/Q |
1.807 | 0.377 | tNET | RR | 1 | R14C133[0][A] | test[3].u_mac_tx_model/shift_reg_98_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 3615 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
1.245 | 1.245 | tNET | RR | 1 | R14C133[0][A] | test[3].u_mac_tx_model/shift_reg_98_s1/CLK |
1.056 | -0.189 | tHld | 1 | R14C133[0][A] | test[3].u_mac_tx_model/shift_reg_98_s1 |
Path Statistics:
Clock Skew | -0.005 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.250, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.377, 67.713%; tC2Q: 0.180, 32.287% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.245, 100.000% |
Path11
Path Summary:
Slack | 0.751 |
Data Arrival Time | 1.808 |
Data Required Time | 1.056 |
From | tx_mac_rst_n_3_s0 |
To | test[3].u_mac_tx_model/shift_reg_106_s1 |
Launch Clk | tx_mac_clk:[R] |
Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 3615 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
1.250 | 1.250 | tNET | RR | 1 | R15C129[0][A] | tx_mac_rst_n_3_s0/CLK |
1.430 | 0.180 | tC2Q | RR | 378 | R15C129[0][A] | tx_mac_rst_n_3_s0/Q |
1.807 | 0.377 | tNET | RR | 1 | R14C133[0][B] | test[3].u_mac_tx_model/shift_reg_106_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 3615 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
1.245 | 1.245 | tNET | RR | 1 | R14C133[0][B] | test[3].u_mac_tx_model/shift_reg_106_s1/CLK |
1.056 | -0.189 | tHld | 1 | R14C133[0][B] | test[3].u_mac_tx_model/shift_reg_106_s1 |
Path Statistics:
Clock Skew | -0.005 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.250, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.377, 67.713%; tC2Q: 0.180, 32.287% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.245, 100.000% |
Path12
Path Summary:
Slack | 0.756 |
Data Arrival Time | 1.808 |
Data Required Time | 1.051 |
From | tx_mac_rst_n_3_s0 |
To | test[3].u_mac_tx_model/shift_reg_42_s1 |
Launch Clk | tx_mac_clk:[R] |
Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 3615 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
1.250 | 1.250 | tNET | RR | 1 | R15C129[0][A] | tx_mac_rst_n_3_s0/CLK |
1.430 | 0.180 | tC2Q | RR | 378 | R15C129[0][A] | tx_mac_rst_n_3_s0/Q |
1.807 | 0.377 | tNET | RR | 1 | R14C132[0][A] | test[3].u_mac_tx_model/shift_reg_42_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 3615 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
1.240 | 1.240 | tNET | RR | 1 | R14C132[0][A] | test[3].u_mac_tx_model/shift_reg_42_s1/CLK |
1.051 | -0.189 | tHld | 1 | R14C132[0][A] | test[3].u_mac_tx_model/shift_reg_42_s1 |
Path Statistics:
Clock Skew | -0.010 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.250, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.377, 67.713%; tC2Q: 0.180, 32.287% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.240, 100.000% |
Path13
Path Summary:
Slack | 0.756 |
Data Arrival Time | 1.808 |
Data Required Time | 1.051 |
From | tx_mac_rst_n_3_s0 |
To | test[3].u_mac_tx_model/shift_reg_50_s1 |
Launch Clk | tx_mac_clk:[R] |
Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 3615 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
1.250 | 1.250 | tNET | RR | 1 | R15C129[0][A] | tx_mac_rst_n_3_s0/CLK |
1.430 | 0.180 | tC2Q | RR | 378 | R15C129[0][A] | tx_mac_rst_n_3_s0/Q |
1.807 | 0.377 | tNET | RR | 1 | R14C132[0][B] | test[3].u_mac_tx_model/shift_reg_50_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 3615 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
1.240 | 1.240 | tNET | RR | 1 | R14C132[0][B] | test[3].u_mac_tx_model/shift_reg_50_s1/CLK |
1.051 | -0.189 | tHld | 1 | R14C132[0][B] | test[3].u_mac_tx_model/shift_reg_50_s1 |
Path Statistics:
Clock Skew | -0.010 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.250, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.377, 67.713%; tC2Q: 0.180, 32.287% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.240, 100.000% |
Path14
Path Summary:
Slack | 0.756 |
Data Arrival Time | 1.808 |
Data Required Time | 1.051 |
From | tx_mac_rst_n_3_s0 |
To | test[3].u_mac_tx_model/shift_reg_58_s1 |
Launch Clk | tx_mac_clk:[R] |
Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 3615 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
1.250 | 1.250 | tNET | RR | 1 | R15C129[0][A] | tx_mac_rst_n_3_s0/CLK |
1.430 | 0.180 | tC2Q | RR | 378 | R15C129[0][A] | tx_mac_rst_n_3_s0/Q |
1.807 | 0.377 | tNET | RR | 1 | R14C132[1][A] | test[3].u_mac_tx_model/shift_reg_58_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 3615 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
1.240 | 1.240 | tNET | RR | 1 | R14C132[1][A] | test[3].u_mac_tx_model/shift_reg_58_s1/CLK |
1.051 | -0.189 | tHld | 1 | R14C132[1][A] | test[3].u_mac_tx_model/shift_reg_58_s1 |
Path Statistics:
Clock Skew | -0.010 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.250, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.377, 67.713%; tC2Q: 0.180, 32.287% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.240, 100.000% |
Path15
Path Summary:
Slack | 0.756 |
Data Arrival Time | 1.808 |
Data Required Time | 1.051 |
From | tx_mac_rst_n_3_s0 |
To | test[3].u_mac_tx_model/shift_reg_66_s1 |
Launch Clk | tx_mac_clk:[R] |
Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 3615 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
1.250 | 1.250 | tNET | RR | 1 | R15C129[0][A] | tx_mac_rst_n_3_s0/CLK |
1.430 | 0.180 | tC2Q | RR | 378 | R15C129[0][A] | tx_mac_rst_n_3_s0/Q |
1.807 | 0.377 | tNET | RR | 1 | R14C132[1][B] | test[3].u_mac_tx_model/shift_reg_66_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 3615 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
1.240 | 1.240 | tNET | RR | 1 | R14C132[1][B] | test[3].u_mac_tx_model/shift_reg_66_s1/CLK |
1.051 | -0.189 | tHld | 1 | R14C132[1][B] | test[3].u_mac_tx_model/shift_reg_66_s1 |
Path Statistics:
Clock Skew | -0.010 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.250, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.377, 67.713%; tC2Q: 0.180, 32.287% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.240, 100.000% |
Path16
Path Summary:
Slack | 0.756 |
Data Arrival Time | 1.808 |
Data Required Time | 1.051 |
From | tx_mac_rst_n_3_s0 |
To | test[3].u_mac_tx_model/shift_reg_74_s1 |
Launch Clk | tx_mac_clk:[R] |
Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 3615 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
1.250 | 1.250 | tNET | RR | 1 | R15C129[0][A] | tx_mac_rst_n_3_s0/CLK |
1.430 | 0.180 | tC2Q | RR | 378 | R15C129[0][A] | tx_mac_rst_n_3_s0/Q |
1.807 | 0.377 | tNET | RR | 1 | R14C132[2][A] | test[3].u_mac_tx_model/shift_reg_74_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 3615 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
1.240 | 1.240 | tNET | RR | 1 | R14C132[2][A] | test[3].u_mac_tx_model/shift_reg_74_s1/CLK |
1.051 | -0.189 | tHld | 1 | R14C132[2][A] | test[3].u_mac_tx_model/shift_reg_74_s1 |
Path Statistics:
Clock Skew | -0.010 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.250, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.377, 67.713%; tC2Q: 0.180, 32.287% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.240, 100.000% |
Path17
Path Summary:
Slack | 0.756 |
Data Arrival Time | 1.808 |
Data Required Time | 1.051 |
From | tx_mac_rst_n_3_s0 |
To | test[3].u_mac_tx_model/shift_reg_82_s1 |
Launch Clk | tx_mac_clk:[R] |
Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 3615 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
1.250 | 1.250 | tNET | RR | 1 | R15C129[0][A] | tx_mac_rst_n_3_s0/CLK |
1.430 | 0.180 | tC2Q | RR | 378 | R15C129[0][A] | tx_mac_rst_n_3_s0/Q |
1.807 | 0.377 | tNET | RR | 1 | R14C132[2][B] | test[3].u_mac_tx_model/shift_reg_82_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 3615 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
1.240 | 1.240 | tNET | RR | 1 | R14C132[2][B] | test[3].u_mac_tx_model/shift_reg_82_s1/CLK |
1.051 | -0.189 | tHld | 1 | R14C132[2][B] | test[3].u_mac_tx_model/shift_reg_82_s1 |
Path Statistics:
Clock Skew | -0.010 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.250, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.377, 67.713%; tC2Q: 0.180, 32.287% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.240, 100.000% |
Path18
Path Summary:
Slack | 0.756 |
Data Arrival Time | 1.808 |
Data Required Time | 1.051 |
From | tx_mac_rst_n_3_s0 |
To | test[3].u_mac_tx_model/shift_reg_90_s1 |
Launch Clk | tx_mac_clk:[R] |
Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 3615 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
1.250 | 1.250 | tNET | RR | 1 | R15C129[0][A] | tx_mac_rst_n_3_s0/CLK |
1.430 | 0.180 | tC2Q | RR | 378 | R15C129[0][A] | tx_mac_rst_n_3_s0/Q |
1.807 | 0.377 | tNET | RR | 1 | R14C132[3][A] | test[3].u_mac_tx_model/shift_reg_90_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 3615 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
1.240 | 1.240 | tNET | RR | 1 | R14C132[3][A] | test[3].u_mac_tx_model/shift_reg_90_s1/CLK |
1.051 | -0.189 | tHld | 1 | R14C132[3][A] | test[3].u_mac_tx_model/shift_reg_90_s1 |
Path Statistics:
Clock Skew | -0.010 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.250, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.377, 67.713%; tC2Q: 0.180, 32.287% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.240, 100.000% |
Path19
Path Summary:
Slack | 0.832 |
Data Arrival Time | 1.924 |
Data Required Time | 1.092 |
From | rx_mac_rst_n_2_s0 |
To | test[2].u_mac_rx_model/rx_error_all_pause_check_s4 |
Launch Clk | rx_mac_clk:[R] |
Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
1.274 | 1.274 | tNET | RR | 1 | R17C128[2][A] | rx_mac_rst_n_2_s0/CLK |
1.454 | 0.180 | tC2Q | RR | 780 | R17C128[2][A] | rx_mac_rst_n_2_s0/Q |
1.924 | 0.470 | tNET | RR | 1 | R15C122[1][A] | test[2].u_mac_rx_model/rx_error_all_pause_check_s4/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
1.281 | 1.281 | tNET | RR | 1 | R15C122[1][A] | test[2].u_mac_rx_model/rx_error_all_pause_check_s4/CLK |
1.092 | -0.189 | tHld | 1 | R15C122[1][A] | test[2].u_mac_rx_model/rx_error_all_pause_check_s4 |
Path Statistics:
Clock Skew | 0.007 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.274, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.470, 72.308%; tC2Q: 0.180, 27.692% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.281, 100.000% |
Path20
Path Summary:
Slack | 0.832 |
Data Arrival Time | 1.924 |
Data Required Time | 1.092 |
From | rx_mac_rst_n_2_s0 |
To | test[2].u_mac_rx_model/rx_error_all_data_check_s4 |
Launch Clk | rx_mac_clk:[R] |
Latch Clk | rx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
1.274 | 1.274 | tNET | RR | 1 | R17C128[2][A] | rx_mac_rst_n_2_s0/CLK |
1.454 | 0.180 | tC2Q | RR | 780 | R17C128[2][A] | rx_mac_rst_n_2_s0/Q |
1.924 | 0.470 | tNET | RR | 1 | R15C122[1][B] | test[2].u_mac_rx_model/rx_error_all_data_check_s4/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 6461 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
1.281 | 1.281 | tNET | RR | 1 | R15C122[1][B] | test[2].u_mac_rx_model/rx_error_all_data_check_s4/CLK |
1.092 | -0.189 | tHld | 1 | R15C122[1][B] | test[2].u_mac_rx_model/rx_error_all_data_check_s4 |
Path Statistics:
Clock Skew | 0.007 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.274, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.470, 72.308%; tC2Q: 0.180, 27.692% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.281, 100.000% |
Path21
Path Summary:
Slack | 0.833 |
Data Arrival Time | 1.915 |
Data Required Time | 1.082 |
From | tx_mac_rst_n_3_s0 |
To | test[3].u_mac_tx_model/pause_value_1_s0 |
Launch Clk | tx_mac_clk:[R] |
Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 3615 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
1.250 | 1.250 | tNET | RR | 1 | R15C129[0][A] | tx_mac_rst_n_3_s0/CLK |
1.430 | 0.180 | tC2Q | RR | 378 | R15C129[0][A] | tx_mac_rst_n_3_s0/Q |
1.915 | 0.485 | tNET | RR | 1 | R25C129[0][A] | test[3].u_mac_tx_model/pause_value_1_s0/PRESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 3615 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
1.271 | 1.271 | tNET | RR | 1 | R25C129[0][A] | test[3].u_mac_tx_model/pause_value_1_s0/CLK |
1.082 | -0.189 | tHld | 1 | R25C129[0][A] | test[3].u_mac_tx_model/pause_value_1_s0 |
Path Statistics:
Clock Skew | 0.021 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.250, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.485, 72.932%; tC2Q: 0.180, 27.068% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.271, 100.000% |
Path22
Path Summary:
Slack | 0.833 |
Data Arrival Time | 1.915 |
Data Required Time | 1.082 |
From | tx_mac_rst_n_3_s0 |
To | test[3].u_mac_tx_model/pause_value_2_s0 |
Launch Clk | tx_mac_clk:[R] |
Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 3615 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
1.250 | 1.250 | tNET | RR | 1 | R15C129[0][A] | tx_mac_rst_n_3_s0/CLK |
1.430 | 0.180 | tC2Q | RR | 378 | R15C129[0][A] | tx_mac_rst_n_3_s0/Q |
1.915 | 0.485 | tNET | RR | 1 | R25C129[0][B] | test[3].u_mac_tx_model/pause_value_2_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 3615 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
1.271 | 1.271 | tNET | RR | 1 | R25C129[0][B] | test[3].u_mac_tx_model/pause_value_2_s0/CLK |
1.082 | -0.189 | tHld | 1 | R25C129[0][B] | test[3].u_mac_tx_model/pause_value_2_s0 |
Path Statistics:
Clock Skew | 0.021 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.250, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.485, 72.932%; tC2Q: 0.180, 27.068% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.271, 100.000% |
Path23
Path Summary:
Slack | 0.833 |
Data Arrival Time | 1.915 |
Data Required Time | 1.082 |
From | tx_mac_rst_n_3_s0 |
To | test[3].u_mac_tx_model/pause_value_3_s0 |
Launch Clk | tx_mac_clk:[R] |
Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 3615 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
1.250 | 1.250 | tNET | RR | 1 | R15C129[0][A] | tx_mac_rst_n_3_s0/CLK |
1.430 | 0.180 | tC2Q | RR | 378 | R15C129[0][A] | tx_mac_rst_n_3_s0/Q |
1.915 | 0.485 | tNET | RR | 1 | R25C129[1][A] | test[3].u_mac_tx_model/pause_value_3_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 3615 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
1.271 | 1.271 | tNET | RR | 1 | R25C129[1][A] | test[3].u_mac_tx_model/pause_value_3_s0/CLK |
1.082 | -0.189 | tHld | 1 | R25C129[1][A] | test[3].u_mac_tx_model/pause_value_3_s0 |
Path Statistics:
Clock Skew | 0.021 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.250, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.485, 72.932%; tC2Q: 0.180, 27.068% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.271, 100.000% |
Path24
Path Summary:
Slack | 0.833 |
Data Arrival Time | 1.915 |
Data Required Time | 1.082 |
From | tx_mac_rst_n_3_s0 |
To | test[3].u_mac_tx_model/pause_value_4_s0 |
Launch Clk | tx_mac_clk:[R] |
Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 3615 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
1.250 | 1.250 | tNET | RR | 1 | R15C129[0][A] | tx_mac_rst_n_3_s0/CLK |
1.430 | 0.180 | tC2Q | RR | 378 | R15C129[0][A] | tx_mac_rst_n_3_s0/Q |
1.915 | 0.485 | tNET | RR | 1 | R25C129[1][B] | test[3].u_mac_tx_model/pause_value_4_s0/PRESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 3615 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
1.271 | 1.271 | tNET | RR | 1 | R25C129[1][B] | test[3].u_mac_tx_model/pause_value_4_s0/CLK |
1.082 | -0.189 | tHld | 1 | R25C129[1][B] | test[3].u_mac_tx_model/pause_value_4_s0 |
Path Statistics:
Clock Skew | 0.021 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.250, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.485, 72.932%; tC2Q: 0.180, 27.068% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.271, 100.000% |
Path25
Path Summary:
Slack | 0.833 |
Data Arrival Time | 1.915 |
Data Required Time | 1.082 |
From | tx_mac_rst_n_3_s0 |
To | test[3].u_mac_tx_model/pause_value_5_s0 |
Launch Clk | tx_mac_clk:[R] |
Latch Clk | tx_mac_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 3615 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
1.250 | 1.250 | tNET | RR | 1 | R15C129[0][A] | tx_mac_rst_n_3_s0/CLK |
1.430 | 0.180 | tC2Q | RR | 378 | R15C129[0][A] | tx_mac_rst_n_3_s0/Q |
1.915 | 0.485 | tNET | RR | 1 | R25C129[2][A] | test[3].u_mac_tx_model/pause_value_5_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tx_mac_clk | ||||
0.000 | 0.000 | tCL | RR | 3615 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK |
1.271 | 1.271 | tNET | RR | 1 | R25C129[2][A] | test[3].u_mac_tx_model/pause_value_5_s0/CLK |
1.082 | -0.189 | tHld | 1 | R25C129[2][A] | test[3].u_mac_tx_model/pause_value_5_s0 |
Path Statistics:
Clock Skew | 0.021 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.250, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.485, 72.932%; tC2Q: 0.180, 27.068% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.271, 100.000% |
Minimum Pulse Width Report:
Report Command:report_min_pulse_width -nworst 10 -detail
MPW1
MPW Summary:
Slack: | 1.729 |
Actual Width: | 2.729 |
Required Width: | 1.000 |
Type: | High Pulse Width |
Clock: | rx_mac_clk |
Objects: | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||
0.000 | 0.000 | rx_mac_clk | ||
0.000 | 0.000 | tCL | RR | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
2.810 | 2.810 | tNET | RR | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
4.000 | 0.000 | active clock edge time | ||
4.000 | 0.000 | rx_mac_clk | ||
4.000 | 0.000 | tCL | FF | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
5.538 | 1.538 | tNET | FF | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA |
MPW2
MPW Summary:
Slack: | 1.852 |
Actual Width: | 2.852 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | rx_mac_clk |
Objects: | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
4.000 | 0.000 | active clock edge time | ||
4.000 | 0.000 | rx_mac_clk | ||
4.000 | 0.000 | tCL | FF | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
6.410 | 2.410 | tNET | FF | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
8.000 | 0.000 | active clock edge time | ||
8.000 | 0.000 | rx_mac_clk | ||
8.000 | 0.000 | tCL | RR | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
9.261 | 1.261 | tNET | RR | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA |
MPW3
MPW Summary:
Slack: | 2.419 |
Actual Width: | 2.669 |
Required Width: | 0.250 |
Type: | High Pulse Width |
Clock: | rx_mac_clk |
Objects: | rx_running_d1_2_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||
0.000 | 0.000 | rx_mac_clk | ||
0.000 | 0.000 | tCL | RR | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
2.918 | 2.918 | tNET | RR | rx_running_d1_2_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
4.000 | 0.000 | active clock edge time | ||
4.000 | 0.000 | rx_mac_clk | ||
4.000 | 0.000 | tCL | FF | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
5.586 | 1.586 | tNET | FF | rx_running_d1_2_s0/CLK |
MPW4
MPW Summary:
Slack: | 2.419 |
Actual Width: | 2.669 |
Required Width: | 0.250 |
Type: | High Pulse Width |
Clock: | rx_mac_clk |
Objects: | test[3].u_mac_rx_model/rx_mac_data_d1_0_s1 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||
0.000 | 0.000 | rx_mac_clk | ||
0.000 | 0.000 | tCL | RR | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
2.918 | 2.918 | tNET | RR | test[3].u_mac_rx_model/rx_mac_data_d1_0_s1/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
4.000 | 0.000 | active clock edge time | ||
4.000 | 0.000 | rx_mac_clk | ||
4.000 | 0.000 | tCL | FF | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
5.586 | 1.586 | tNET | FF | test[3].u_mac_rx_model/rx_mac_data_d1_0_s1/CLK |
MPW5
MPW Summary:
Slack: | 2.419 |
Actual Width: | 2.669 |
Required Width: | 0.250 |
Type: | High Pulse Width |
Clock: | rx_mac_clk |
Objects: | test[3].u_mac_rx_model/shift_reg_7_s1 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||
0.000 | 0.000 | rx_mac_clk | ||
0.000 | 0.000 | tCL | RR | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
2.918 | 2.918 | tNET | RR | test[3].u_mac_rx_model/shift_reg_7_s1/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
4.000 | 0.000 | active clock edge time | ||
4.000 | 0.000 | rx_mac_clk | ||
4.000 | 0.000 | tCL | FF | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
5.586 | 1.586 | tNET | FF | test[3].u_mac_rx_model/shift_reg_7_s1/CLK |
MPW6
MPW Summary:
Slack: | 2.419 |
Actual Width: | 2.669 |
Required Width: | 0.250 |
Type: | High Pulse Width |
Clock: | rx_mac_clk |
Objects: | test[3].u_mac_rx_model/pause_value_15_s1 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||
0.000 | 0.000 | rx_mac_clk | ||
0.000 | 0.000 | tCL | RR | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
2.918 | 2.918 | tNET | RR | test[3].u_mac_rx_model/pause_value_15_s1/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
4.000 | 0.000 | active clock edge time | ||
4.000 | 0.000 | rx_mac_clk | ||
4.000 | 0.000 | tCL | FF | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
5.586 | 1.586 | tNET | FF | test[3].u_mac_rx_model/pause_value_15_s1/CLK |
MPW7
MPW Summary:
Slack: | 2.419 |
Actual Width: | 2.669 |
Required Width: | 0.250 |
Type: | High Pulse Width |
Clock: | rx_mac_clk |
Objects: | test[3].u_mac_rx_model/pause_data_2_39_s1 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||
0.000 | 0.000 | rx_mac_clk | ||
0.000 | 0.000 | tCL | RR | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
2.918 | 2.918 | tNET | RR | test[3].u_mac_rx_model/pause_data_2_39_s1/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
4.000 | 0.000 | active clock edge time | ||
4.000 | 0.000 | rx_mac_clk | ||
4.000 | 0.000 | tCL | FF | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
5.586 | 1.586 | tNET | FF | test[3].u_mac_rx_model/pause_data_2_39_s1/CLK |
MPW8
MPW Summary:
Slack: | 2.419 |
Actual Width: | 2.669 |
Required Width: | 0.250 |
Type: | High Pulse Width |
Clock: | rx_mac_clk |
Objects: | test[3].u_mac_rx_model/pause_value_14_s1 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||
0.000 | 0.000 | rx_mac_clk | ||
0.000 | 0.000 | tCL | RR | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
2.918 | 2.918 | tNET | RR | test[3].u_mac_rx_model/pause_value_14_s1/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
4.000 | 0.000 | active clock edge time | ||
4.000 | 0.000 | rx_mac_clk | ||
4.000 | 0.000 | tCL | FF | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
5.586 | 1.586 | tNET | FF | test[3].u_mac_rx_model/pause_value_14_s1/CLK |
MPW9
MPW Summary:
Slack: | 2.419 |
Actual Width: | 2.669 |
Required Width: | 0.250 |
Type: | High Pulse Width |
Clock: | rx_mac_clk |
Objects: | test[3].u_mac_rx_model/rx_statistics_vector_d1_23_s1 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||
0.000 | 0.000 | rx_mac_clk | ||
0.000 | 0.000 | tCL | RR | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
2.918 | 2.918 | tNET | RR | test[3].u_mac_rx_model/rx_statistics_vector_d1_23_s1/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
4.000 | 0.000 | active clock edge time | ||
4.000 | 0.000 | rx_mac_clk | ||
4.000 | 0.000 | tCL | FF | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
5.586 | 1.586 | tNET | FF | test[3].u_mac_rx_model/rx_statistics_vector_d1_23_s1/CLK |
MPW10
MPW Summary:
Slack: | 2.419 |
Actual Width: | 2.669 |
Required Width: | 0.250 |
Type: | High Pulse Width |
Clock: | rx_mac_clk |
Objects: | test[3].u_mac_rx_model/rx_mac_valid_d4_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||
0.000 | 0.000 | rx_mac_clk | ||
0.000 | 0.000 | tCL | RR | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
2.918 | 2.918 | tNET | RR | test[3].u_mac_rx_model/rx_mac_valid_d4_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
4.000 | 0.000 | active clock edge time | ||
4.000 | 0.000 | rx_mac_clk | ||
4.000 | 0.000 | tCL | FF | u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK |
5.586 | 1.586 | tNET | FF | test[3].u_mac_rx_model/rx_mac_valid_d4_s0/CLK |
High Fanout Nets Report:
Report Command:report_high_fanout_nets -max_nets 10
FANOUT | NET NAME | WORST SLACK | MAX DELAY |
---|---|---|---|
6461 | rx_mac_clk[3] | 0.025 | 2.930 |
3615 | tx_mac_clk[3] | 0.189 | 2.705 |
2004 | clk_uart | 80.692 | 2.655 |
955 | rstn_uart | 91.580 | 5.351 |
215 | control0[0] | 42.326 | 5.654 |
196 | rd_ptr[2] | 94.138 | 3.077 |
192 | rd_ptr[2] | 95.422 | 2.568 |
162 | rx_pause_state | 2.500 | 4.550 |
162 | rx_pause_state | 3.108 | 3.924 |
162 | rx_pause_state | 3.942 | 3.346 |
Route Congestions Report:
Report Command:report_route_congestion -max_grids 10
GRID LOC | ROUTE CONGESTIONS |
---|---|
R15C151 | 72.22% |
R8C166 | 70.83% |
R8C167 | 70.83% |
R35C128 | 70.83% |
R7C165 | 69.44% |
R24C139 | 69.44% |
R16C160 | 68.06% |
R14C159 | 68.06% |
R15C159 | 68.06% |
R21C146 | 68.06% |
Timing Exceptions Report:
Setup Analysis Report
Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Hold Analysis Report
Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Recovery Analysis Report
Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Removal Analysis Report
Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Timing Constraints Report:
SDC Command Type | State | Detail Command |
---|---|---|
TC_CLOCK | Actived | create_clock -name rx_mac_clk -period 8 -waveform {0 4} [get_nets {rx_mac_clk[3]}] |
TC_CLOCK | Actived | create_clock -name tx_mac_clk -period 8 -waveform {0 4} [get_nets {tx_mac_clk[3]}] |
TC_CLOCK | Actived | create_clock -name clk_in -period 20 -waveform {0 10} [get_pins {gowin_ibuf_clk_in/I}] |
TC_CLOCK | Actived | create_clock -name tck_pad -period 50 -waveform {0 25} [get_pins {gw_gao_inst_0/tck_ibuf/I}] |
TC_GENERATED_CLOCK | Actived | create_generated_clock -name clk_uart -source [get_pins {gowin_ibuf_clk_in/I}] -master_clock clk_in -divide_by 80 -multiply_by 16 [get_pins {u_pll_uart/PLL_inst/CLKOUT0}] |
TC_FALSE_PATH | Actived | set_false_path -from [get_clocks {clk_uart tck_pad clk_in}] -to [get_clocks {rx_mac_clk tx_mac_clk clk_in}] |
TC_FALSE_PATH | Actived | set_false_path -from [get_clocks {rx_mac_clk tx_mac_clk}] -to [get_clocks {clk_uart tck_pad}] |