Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | E:\IP_Release\QSGMII\1.0\ref_design\Gowin_QSGMII_IP_RefDesign_1\project\src\button.v E:\IP_Release\QSGMII\1.0\ref_design\Gowin_QSGMII_IP_RefDesign_1\project\src\mac_rx_model.v E:\IP_Release\QSGMII\1.0\ref_design\Gowin_QSGMII_IP_RefDesign_1\project\src\mac_tx_model.v E:\IP_Release\QSGMII\1.0\ref_design\Gowin_QSGMII_IP_RefDesign_1\project\src\pll_uart\pll_uart.v E:\IP_Release\QSGMII\1.0\ref_design\Gowin_QSGMII_IP_RefDesign_1\project\src\serdes\qsgmii\qsgmii.v E:\IP_Release\QSGMII\1.0\ref_design\Gowin_QSGMII_IP_RefDesign_1\project\src\serdes\serdes.v E:\IP_Release\QSGMII\1.0\ref_design\Gowin_QSGMII_IP_RefDesign_1\project\src\sysreg.v E:\IP_Release\QSGMII\1.0\ref_design\Gowin_QSGMII_IP_RefDesign_1\project\src\top.v E:\IP_Release\QSGMII\1.0\ref_design\Gowin_QSGMII_IP_RefDesign_1\project\src\uart_to_bus\uart_to_bus.v D:\Gowin\Gowin_V1.9.9.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v D:\Gowin\Gowin_V1.9.9.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v D:\Gowin\Gowin_V1.9.9.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v D:\Gowin\Gowin_V1.9.9.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v D:\Gowin\Gowin_V1.9.9.01_x64\IDE\data\ipcores\GAO\GW_CON\gw_con_top_138.v D:\Gowin\Gowin_V1.9.9.01_x64\IDE\data\ipcores\gw_jtag.v E:\IP_Release\QSGMII\1.0\ref_design\Gowin_QSGMII_IP_RefDesign_1\project\impl\gwsynthesis\RTL_GAO\gw_gao_top.v |
GowinSynthesis Constraints File | --- |
Tool Version | V1.9.9.01 (64-bit) |
Part Number | GW5AST-LV138FPG676AES |
Device | GW5AST-138 |
Device Version | B |
Created Time | Tue Jan 2 14:13:14 2024 |
Legal Announcement | Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | top |
Synthesis Process | Running parser: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 2s, Peak memory usage = 1886.629MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 0.998s, Peak memory usage = 1886.629MB Optimizing Phase 1: CPU time = 0h 0m 0.734s, Elapsed time = 0h 0m 0.735s, Peak memory usage = 1886.629MB Optimizing Phase 2: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 1886.629MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.5s, Elapsed time = 0h 0m 0.5s, Peak memory usage = 1886.629MB Inferring Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.014s, Peak memory usage = 1886.629MB Inferring Phase 2: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.156s, Peak memory usage = 1886.629MB Inferring Phase 3: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.061s, Peak memory usage = 1886.629MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 1886.629MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.484s, Elapsed time = 0h 0m 0.425s, Peak memory usage = 1886.629MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.453s, Elapsed time = 0h 0m 0.449s, Peak memory usage = 1886.629MB Tech-Mapping Phase 3: CPU time = 0h 0m 13s, Elapsed time = 0h 0m 13s, Peak memory usage = 1886.629MB Tech-Mapping Phase 4: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 1886.629MB Generate output files: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 1886.629MB |
Total Time and Memory Usage | CPU time = 0h 0m 25s, Elapsed time = 0h 0m 24s, Peak memory usage = 1886.629MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 12 |
I/O Buf | 12 |
    IBUF | 6 |
    OBUF | 6 |
Register | 12321 |
    DFFRE | 1018 |
    DFFPE | 594 |
    DFFCE | 10709 |
LUT | 12079 |
    LUT2 | 1565 |
    LUT3 | 3472 |
    LUT4 | 7042 |
MUX | 1 |
    MUX16 | 1 |
ALU | 1312 |
    ALU | 1312 |
INV | 101 |
    INV | 101 |
BSRAM | 1 |
    SDPB | 1 |
CLOCK | 1 |
    PLL | 1 |
Black Box | 2 |
    GW_JTAG | 1 |
GTR12_QUAD | 1 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 13500(12188 LUT, 1312 ALU) / 138240 | 10% |
Register | 12321 / 139140 | 9% |
  --Register as Latch | 0 / 139140 | 0% |
  --Register as FF | 12321 / 139140 | 9% |
BSRAM | 1 / 340 | <1% |
Timing
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|
clk_in | Base | 20.000 | 50.0 | 0.000 | 10.000 | clk_in_ibuf/I | ||
gw_gao_inst_0/u_icon_top/n31_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 | gw_gao_inst_0/u_icon_top/n31_s2/O | ||
gw_gao_inst_0/u_la0_top/n15_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 | gw_gao_inst_0/u_la0_top/n15_s2/O | ||
u_pll_uart/PLL_inst/CLKOUT0.default_gen_clk | Generated | 100.000 | 10.0 | 0.000 | 50.000 | clk_in_ibuf/I | clk_in | u_pll_uart/PLL_inst/CLKOUT0 |
Max Frequency Summary:
No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | clk_in | 50.0(MHz) | 464.8(MHz) | 3 | TOP |
2 | gw_gao_inst_0/u_icon_top/n31_6 | 100.0(MHz) | 1532.6(MHz) | 1 | TOP |
3 | gw_gao_inst_0/u_la0_top/n15_6 | 100.0(MHz) | 1532.6(MHz) | 1 | TOP |
4 | u_pll_uart/PLL_inst/CLKOUT0.default_gen_clk | 10.0(MHz) | 130.0(MHz) | 10 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | 9.347 |
Data Arrival Time | 0.795 |
Data Required Time | 10.142 |
From | gw_gao_inst_0/u_la0_top/rst_ao_syn_s0 |
To | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
Launch Clk | gw_gao_inst_0/u_la0_top/n15_6[R] |
Latch Clk | gw_gao_inst_0/u_la0_top/n15_6[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | gw_gao_inst_0/u_la0_top/n15_6 | |||
0.000 | 0.000 | tCL | RR | 2 | gw_gao_inst_0/u_la0_top/n15_s2/O |
0.206 | 0.206 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/rst_ao_syn_s0/CLK |
0.589 | 0.382 | tC2Q | RR | 1 | gw_gao_inst_0/u_la0_top/rst_ao_syn_s0/Q |
0.795 | 0.206 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/rst_ao_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | gw_gao_inst_0/u_la0_top/n15_6 | |||
10.000 | 0.000 | tCL | RR | 2 | gw_gao_inst_0/u_la0_top/n15_s2/O |
10.206 | 0.206 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
10.142 | -0.064 | tSu | 1 | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 1 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.206, 100.000% |
Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.206, 35.032%; tC2Q: 0.382, 64.968% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.206, 100.000% |
Path 2
Path Summary:Slack | 9.347 |
Data Arrival Time | 0.795 |
Data Required Time | 10.142 |
From | gw_gao_inst_0/u_icon_top/enable_reg_1_s0 |
To | gw_gao_inst_0/u_icon_top/enable_reg_0_s0 |
Launch Clk | gw_gao_inst_0/u_icon_top/n31_6[R] |
Latch Clk | gw_gao_inst_0/u_icon_top/n31_6[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | gw_gao_inst_0/u_icon_top/n31_6 | |||
0.000 | 0.000 | tCL | RR | 4 | gw_gao_inst_0/u_icon_top/n31_s2/O |
0.206 | 0.206 | tNET | RR | 1 | gw_gao_inst_0/u_icon_top/enable_reg_1_s0/CLK |
0.589 | 0.382 | tC2Q | RR | 3 | gw_gao_inst_0/u_icon_top/enable_reg_1_s0/Q |
0.795 | 0.206 | tNET | RR | 1 | gw_gao_inst_0/u_icon_top/enable_reg_0_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | gw_gao_inst_0/u_icon_top/n31_6 | |||
10.000 | 0.000 | tCL | RR | 4 | gw_gao_inst_0/u_icon_top/n31_s2/O |
10.206 | 0.206 | tNET | RR | 1 | gw_gao_inst_0/u_icon_top/enable_reg_0_s0/CLK |
10.142 | -0.064 | tSu | 1 | gw_gao_inst_0/u_icon_top/enable_reg_0_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 1 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.206, 100.000% |
Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.206, 35.032%; tC2Q: 0.382, 64.968% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.206, 100.000% |
Path 3
Path Summary:Slack | 9.347 |
Data Arrival Time | 0.795 |
Data Required Time | 10.142 |
From | gw_gao_inst_0/u_icon_top/enable_reg_2_s0 |
To | gw_gao_inst_0/u_icon_top/enable_reg_1_s0 |
Launch Clk | gw_gao_inst_0/u_icon_top/n31_6[R] |
Latch Clk | gw_gao_inst_0/u_icon_top/n31_6[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | gw_gao_inst_0/u_icon_top/n31_6 | |||
0.000 | 0.000 | tCL | RR | 4 | gw_gao_inst_0/u_icon_top/n31_s2/O |
0.206 | 0.206 | tNET | RR | 1 | gw_gao_inst_0/u_icon_top/enable_reg_2_s0/CLK |
0.589 | 0.382 | tC2Q | RR | 3 | gw_gao_inst_0/u_icon_top/enable_reg_2_s0/Q |
0.795 | 0.206 | tNET | RR | 1 | gw_gao_inst_0/u_icon_top/enable_reg_1_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | gw_gao_inst_0/u_icon_top/n31_6 | |||
10.000 | 0.000 | tCL | RR | 4 | gw_gao_inst_0/u_icon_top/n31_s2/O |
10.206 | 0.206 | tNET | RR | 1 | gw_gao_inst_0/u_icon_top/enable_reg_1_s0/CLK |
10.142 | -0.064 | tSu | 1 | gw_gao_inst_0/u_icon_top/enable_reg_1_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 1 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.206, 100.000% |
Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.206, 35.032%; tC2Q: 0.382, 64.968% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.206, 100.000% |
Path 4
Path Summary:Slack | 16.911 |
Data Arrival Time | 84.037 |
Data Required Time | 100.948 |
From | sw1/bout_s0 |
To | u_sysreg/uart_rdata_2_s0 |
Launch Clk | clk_in[R] |
Latch Clk | u_pll_uart/PLL_inst/CLKOUT0.default_gen_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
80.000 | 0.000 | clk_in | |||
80.000 | 0.000 | tCL | RR | 1 | clk_in_ibuf/I |
80.683 | 0.683 | tINS | RR | 29 | clk_in_ibuf/O |
80.889 | 0.206 | tNET | RR | 1 | sw1/bout_s0/CLK |
81.271 | 0.382 | tC2Q | RR | 2 | sw1/bout_s0/Q |
81.478 | 0.206 | tNET | RR | 1 | rstn_ip_s0/I0 |
82.056 | 0.579 | tINS | RR | 2 | rstn_ip_s0/F |
82.263 | 0.206 | tNET | RR | 1 | u_sysreg/n1790_s53/I0 |
82.841 | 0.579 | tINS | RR | 1 | u_sysreg/n1790_s53/F |
83.048 | 0.206 | tNET | RR | 1 | u_sysreg/n1790_s39/I3 |
83.336 | 0.289 | tINS | RR | 1 | u_sysreg/n1790_s39/F |
83.543 | 0.206 | tNET | RR | 1 | u_sysreg/n1790_s35/I3 |
83.831 | 0.289 | tINS | RR | 1 | u_sysreg/n1790_s35/F |
84.038 | 0.206 | tNET | RR | 1 | u_sysreg/uart_rdata_2_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
100.000 | 0.000 | u_pll_uart/PLL_inst/CLKOUT0.default_gen_clk | |||
100.841 | 0.841 | tCL | RR | 2004 | u_pll_uart/PLL_inst/CLKOUT0 |
101.047 | 0.206 | tNET | RR | 1 | u_sysreg/uart_rdata_2_s0/CLK |
101.012 | -0.035 | tUnc | u_sysreg/uart_rdata_2_s0 | ||
100.948 | -0.064 | tSu | 1 | u_sysreg/uart_rdata_2_s0 |
Clock Skew: | 0.158 |
Setup Relationship: | 20.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.683, 76.793%; route: 0.206, 23.207% |
Arrival Data Path Delay: | cell: 1.735, 55.101%; route: 1.031, 32.751%; tC2Q: 0.382, 12.148% |
Required Clock Path Delay: | cell: 0.683, 76.793%; route: 0.206, 23.207% |
Path 5
Path Summary:Slack | 17.849 |
Data Arrival Time | 2.976 |
Data Required Time | 20.825 |
From | uart1/temp_6_s0 |
To | uart1/bout_s0 |
Launch Clk | clk_in[R] |
Latch Clk | clk_in[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk_in | |||
0.000 | 0.000 | tCL | RR | 1 | clk_in_ibuf/I |
0.683 | 0.683 | tINS | RR | 29 | clk_in_ibuf/O |
0.889 | 0.206 | tNET | RR | 1 | uart1/temp_6_s0/CLK |
1.271 | 0.382 | tC2Q | RR | 2 | uart1/temp_6_s0/Q |
1.477 | 0.206 | tNET | RR | 1 | uart1/n5_s1/I0 |
2.056 | 0.579 | tINS | RR | 1 | uart1/n5_s1/F |
2.263 | 0.206 | tNET | RR | 1 | uart1/n5_s0/I2 |
2.770 | 0.507 | tINS | RR | 1 | uart1/n5_s0/F |
2.976 | 0.206 | tNET | RR | 1 | uart1/bout_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
20.000 | 0.000 | clk_in | |||
20.000 | 0.000 | tCL | RR | 1 | clk_in_ibuf/I |
20.683 | 0.683 | tINS | RR | 29 | clk_in_ibuf/O |
20.889 | 0.206 | tNET | RR | 1 | uart1/bout_s0/CLK |
20.825 | -0.064 | tSu | 1 | uart1/bout_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 20.000 |
Logic Level: | 3 |
Arrival Clock Path Delay: | cell: 0.683, 76.793%; route: 0.206, 23.207% |
Arrival Data Path Delay: | cell: 1.086, 52.036%; route: 0.619, 29.641%; tC2Q: 0.382, 18.323% |
Required Clock Path Delay: | cell: 0.683, 76.793%; route: 0.206, 23.207% |