Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | D:\Gowin\Gowin_V1.9.9Beta-6\IDE\ipcore\UARTTOBUS\data\uart_bus_core_encryption.v D:\Gowin\Gowin_V1.9.9Beta-6\IDE\ipcore\UARTTOBUS\data\uart_to_bus_top.v |
GowinSynthesis Constraints File | --- |
Version | V1.9.9 Beta-6 |
Part Number | GW5AST-LV138FPG676AES |
Device | GW5AST-138 |
Device Version | B |
Created Time | Mon Nov 20 15:12:42 2023 |
Legal Announcement | Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | Uart_to_Bus_Top |
Synthesis Process | Running parser: CPU time = 0h 0m 0.484s, Elapsed time = 0h 0m 0.638s, Peak memory usage = 49.668MB Running netlist conversion: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.017s, Peak memory usage = 49.668MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.054s, Peak memory usage = 49.668MB Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.021s, Peak memory usage = 49.668MB Optimizing Phase 2: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.049s, Peak memory usage = 49.668MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.036s, Peak memory usage = 49.668MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 49.668MB Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.019s, Peak memory usage = 49.668MB Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 49.668MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.13s, Peak memory usage = 49.668MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.039s, Peak memory usage = 49.668MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.039s, Peak memory usage = 49.668MB Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 62.766MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.145s, Peak memory usage = 62.766MB Generate output files: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.198s, Peak memory usage = 62.766MB |
Total Time and Memory Usage | CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 62.766MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 90 |
I/O Buf | 90 |
    IBUF | 37 |
    OBUF | 53 |
Register | 1437 |
    DFFRE | 838 |
    DFFPE | 9 |
    DFFCE | 590 |
LUT | 933 |
    LUT2 | 131 |
    LUT3 | 549 |
    LUT4 | 253 |
ALU | 39 |
    ALU | 39 |
INV | 12 |
    INV | 12 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 984(945 LUT, 39 ALU) / 138240 | <1% |
Register | 1437 / 139140 | 2% |
  --Register as Latch | 0 / 139140 | 0% |
  --Register as FF | 1437 / 139140 | 2% |
BSRAM | 0 / 340 | 0% |
Timing
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|
clk_i | Base | 10.000 | 100.0 | 0.000 | 5.000 | clk_i_ibuf/I |
Max Frequency Summary:
No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | clk_i | 100.0(MHz) | 168.7(MHz) | 7 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | 4.071 |
Data Arrival Time | 6.754 |
Data Required Time | 10.825 |
From | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_3_s0 |
To | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_2_s0 |
Launch Clk | clk_i[R] |
Latch Clk | clk_i[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk_i | |||
0.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
0.683 | 0.683 | tINS | RR | 1437 | clk_i_ibuf/O |
0.889 | 0.206 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_3_s0/CLK |
1.271 | 0.382 | tC2Q | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_3_s0/Q |
1.477 | 0.206 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n196_s3/I0 |
2.056 | 0.579 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n196_s3/F |
2.263 | 0.206 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n196_s1/I0 |
2.412 | 0.150 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n196_s1/O |
2.619 | 0.206 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n196_s0/I0 |
2.705 | 0.086 | tINS | RR | 2 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n196_s0/O |
2.911 | 0.206 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n740_s45/I2 |
3.419 | 0.507 | tINS | RR | 3 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n740_s45/F |
3.625 | 0.206 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n742_s46/I0 |
4.204 | 0.579 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n742_s46/F |
4.410 | 0.206 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n742_s42/I0 |
4.989 | 0.579 | tINS | RR | 2 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n742_s42/F |
5.195 | 0.206 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n742_s40/I1 |
5.763 | 0.567 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n742_s40/F |
5.969 | 0.206 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n742_s39/I0 |
6.548 | 0.579 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n742_s39/F |
6.754 | 0.206 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_2_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk_i | |||
10.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
10.682 | 0.683 | tINS | RR | 1437 | clk_i_ibuf/O |
10.889 | 0.206 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_2_s0/CLK |
10.825 | -0.064 | tSu | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_2_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 7 |
Arrival Clock Path Delay: | cell: 0.683, 76.793%; route: 0.206, 23.207% |
Arrival Data Path Delay: | cell: 3.626, 61.828%; route: 1.856, 31.650%; tC2Q: 0.382, 6.522% |
Required Clock Path Delay: | cell: 0.683, 76.793%; route: 0.206, 23.207% |
Path 2
Path Summary:Slack | 4.154 |
Data Arrival Time | 6.671 |
Data Required Time | 10.825 |
From | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_1_s0 |
To | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_6_s0 |
Launch Clk | clk_i[R] |
Latch Clk | clk_i[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk_i | |||
0.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
0.683 | 0.683 | tINS | RR | 1437 | clk_i_ibuf/O |
0.889 | 0.206 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_1_s0/CLK |
1.271 | 0.382 | tC2Q | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_1_s0/Q |
1.477 | 0.206 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s3/I0 |
2.056 | 0.579 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s3/F |
2.263 | 0.206 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s1/I0 |
2.412 | 0.150 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s1/O |
2.619 | 0.206 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s0/I0 |
2.705 | 0.086 | tINS | RR | 2 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s0/O |
2.911 | 0.206 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n740_s46/I1 |
3.479 | 0.567 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n740_s46/F |
3.685 | 0.206 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n740_s41/I2 |
4.192 | 0.507 | tINS | RR | 8 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n740_s41/F |
4.399 | 0.206 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s43/I0 |
4.977 | 0.579 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s43/F |
5.184 | 0.206 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s40/I2 |
5.691 | 0.507 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s40/F |
5.898 | 0.206 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s39/I1 |
6.465 | 0.567 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s39/F |
6.671 | 0.206 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_6_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk_i | |||
10.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
10.682 | 0.683 | tINS | RR | 1437 | clk_i_ibuf/O |
10.889 | 0.206 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_6_s0/CLK |
10.825 | -0.064 | tSu | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_6_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 7 |
Arrival Clock Path Delay: | cell: 0.683, 76.793%; route: 0.206, 23.207% |
Arrival Data Path Delay: | cell: 3.544, 61.284%; route: 1.856, 32.101%; tC2Q: 0.382, 6.615% |
Required Clock Path Delay: | cell: 0.683, 76.793%; route: 0.206, 23.207% |
Path 3
Path Summary:Slack | 4.372 |
Data Arrival Time | 6.453 |
Data Required Time | 10.825 |
From | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_3_s0 |
To | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_0_s0 |
Launch Clk | clk_i[R] |
Latch Clk | clk_i[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk_i | |||
0.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
0.683 | 0.683 | tINS | RR | 1437 | clk_i_ibuf/O |
0.889 | 0.206 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_3_s0/CLK |
1.271 | 0.382 | tC2Q | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_3_s0/Q |
1.477 | 0.206 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n196_s3/I0 |
2.056 | 0.579 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n196_s3/F |
2.263 | 0.206 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n196_s1/I0 |
2.412 | 0.150 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n196_s1/O |
2.619 | 0.206 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n196_s0/I0 |
2.705 | 0.086 | tINS | RR | 2 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n196_s0/O |
2.911 | 0.206 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n740_s45/I2 |
3.419 | 0.507 | tINS | RR | 3 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n740_s45/F |
3.625 | 0.206 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n740_s41/I1 |
4.192 | 0.567 | tINS | RR | 8 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n740_s41/F |
4.399 | 0.206 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n744_s43/I3 |
4.688 | 0.289 | tINS | RR | 2 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n744_s43/F |
4.894 | 0.206 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n744_s40/I0 |
5.473 | 0.579 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n744_s40/F |
5.679 | 0.206 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n744_s39/I1 |
6.246 | 0.567 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n744_s39/F |
6.453 | 0.206 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_0_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk_i | |||
10.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
10.682 | 0.683 | tINS | RR | 1437 | clk_i_ibuf/O |
10.889 | 0.206 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_0_s0/CLK |
10.825 | -0.064 | tSu | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_0_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 7 |
Arrival Clock Path Delay: | cell: 0.683, 76.793%; route: 0.206, 23.207% |
Arrival Data Path Delay: | cell: 3.325, 59.762%; route: 1.856, 33.363%; tC2Q: 0.382, 6.875% |
Required Clock Path Delay: | cell: 0.683, 76.793%; route: 0.206, 23.207% |
Path 4
Path Summary:Slack | 4.432 |
Data Arrival Time | 6.393 |
Data Required Time | 10.825 |
From | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_3_s0 |
To | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_3_s0 |
Launch Clk | clk_i[R] |
Latch Clk | clk_i[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk_i | |||
0.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
0.683 | 0.683 | tINS | RR | 1437 | clk_i_ibuf/O |
0.889 | 0.206 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_3_s0/CLK |
1.271 | 0.382 | tC2Q | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_3_s0/Q |
1.477 | 0.206 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n196_s3/I0 |
2.056 | 0.579 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n196_s3/F |
2.263 | 0.206 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n196_s1/I0 |
2.412 | 0.150 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n196_s1/O |
2.619 | 0.206 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n196_s0/I0 |
2.705 | 0.086 | tINS | RR | 2 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n196_s0/O |
2.911 | 0.206 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n740_s45/I2 |
3.419 | 0.507 | tINS | RR | 3 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n740_s45/F |
3.625 | 0.206 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n740_s41/I1 |
4.192 | 0.567 | tINS | RR | 8 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n740_s41/F |
4.399 | 0.206 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n741_s44/I3 |
4.688 | 0.289 | tINS | RR | 2 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n741_s44/F |
4.894 | 0.206 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n741_s42/I0 |
5.473 | 0.579 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n741_s42/F |
5.679 | 0.206 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n741_s40/I2 |
6.186 | 0.507 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n741_s40/F |
6.393 | 0.206 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_3_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk_i | |||
10.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
10.682 | 0.683 | tINS | RR | 1437 | clk_i_ibuf/O |
10.889 | 0.206 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_3_s0/CLK |
10.825 | -0.064 | tSu | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_3_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 7 |
Arrival Clock Path Delay: | cell: 0.683, 76.793%; route: 0.206, 23.207% |
Arrival Data Path Delay: | cell: 3.265, 59.323%; route: 1.856, 33.727%; tC2Q: 0.382, 6.950% |
Required Clock Path Delay: | cell: 0.683, 76.793%; route: 0.206, 23.207% |
Path 5
Path Summary:Slack | 4.446 |
Data Arrival Time | 6.379 |
Data Required Time | 10.825 |
From | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_32_s0 |
To | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_1_s0 |
Launch Clk | clk_i[R] |
Latch Clk | clk_i[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk_i | |||
0.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
0.683 | 0.683 | tINS | RR | 1437 | clk_i_ibuf/O |
0.889 | 0.206 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_32_s0/CLK |
1.271 | 0.382 | tC2Q | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_32_s0/Q |
1.477 | 0.206 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n177_s1/I0 |
2.056 | 0.579 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n177_s1/F |
2.263 | 0.206 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n177_s0/I0 |
2.412 | 0.150 | tINS | RR | 2 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n177_s0/O |
2.619 | 0.206 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n743_s47/I0 |
3.197 | 0.579 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n743_s47/F |
3.404 | 0.206 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n743_s46/I2 |
3.911 | 0.507 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n743_s46/F |
4.117 | 0.206 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n743_s43/I2 |
4.625 | 0.507 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n743_s43/F |
4.831 | 0.206 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n743_s41/I1 |
5.399 | 0.567 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n743_s41/F |
5.605 | 0.206 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n743_s40/I1 |
6.173 | 0.567 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n743_s40/F |
6.379 | 0.206 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_1_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk_i | |||
10.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
10.682 | 0.683 | tINS | RR | 1437 | clk_i_ibuf/O |
10.889 | 0.206 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_1_s0/CLK |
10.825 | -0.064 | tSu | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_1_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 7 |
Arrival Clock Path Delay: | cell: 0.683, 76.793%; route: 0.206, 23.207% |
Arrival Data Path Delay: | cell: 3.457, 62.978%; route: 1.650, 30.055%; tC2Q: 0.382, 6.967% |
Required Clock Path Delay: | cell: 0.683, 76.793%; route: 0.206, 23.207% |