Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\RiscVN25\data\AE250.v
D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\RiscVN25\data\ae250_chip_wrap.v
GowinSynthesis Constraints File ---
Tool Version V1.9.9.03 (64-bit)
Part Number GW2A-LV55PG484C8/I7
Device GW2A-55
Device Version C
Created Time Wed May 15 18:05:44 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module RiscV_AE250_Top
Synthesis Process Running parser:
    CPU time = 0h 1m 20s, Elapsed time = 0h 1m 22s, Peak memory usage = 1859.652MB
Running netlist conversion:
    CPU time = 0h 0m 0.781s, Elapsed time = 0h 0m 0.991s, Peak memory usage = 1859.652MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 6s, Elapsed time = 0h 0m 7s, Peak memory usage = 1859.652MB
    Optimizing Phase 1: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 1859.652MB
    Optimizing Phase 2: CPU time = 0h 0m 5s, Elapsed time = 0h 0m 5s, Peak memory usage = 1859.652MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 1859.652MB
    Inferring Phase 1: CPU time = 0h 0m 0.265s, Elapsed time = 0h 0m 0.296s, Peak memory usage = 1859.652MB
    Inferring Phase 2: CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.237s, Peak memory usage = 1859.652MB
    Inferring Phase 3: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.126s, Peak memory usage = 1859.652MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 5s, Elapsed time = 0h 0m 5s, Peak memory usage = 1859.652MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 1859.652MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 1859.652MB
    Tech-Mapping Phase 3: CPU time = 0h 1m 18s, Elapsed time = 0h 1m 19s, Peak memory usage = 1859.652MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 1859.652MB
Generate output files:
    CPU time = 0h 0m 1s, Elapsed time = 0h 0m 3s, Peak memory usage = 1859.652MB
Total Time and Memory Usage CPU time = 0h 3m 2s, Elapsed time = 0h 3m 8s, Peak memory usage = 1859.652MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 141
I/O Buf 129
    IBUF 10
    OBUF 73
    TBUF 35
    IOBUF 11
Register 6777
    DFF 4
    DFFE 1882
    DFFSE 10
    DFFRE 500
    DFFP 60
    DFFPE 138
    DFFC 398
    DFFCE 3783
    DL 1
    DLN 1
LUT 17571
    LUT2 1332
    LUT3 6192
    LUT4 10047
ALU 1336
    ALU 1336
SSRAM 44
    RAM16SDP4 44
INV 39
    INV 39
DSP
    MULTALU36X18 1
BSRAM 64
    SP 64

Resource Utilization Summary

Resource Usage Utilization
Logic 19210(17610 LUT, 1336 ALU, 44 RAM16) / 54720 36%
Register 6777 / 41997 17%
  --Register as Latch 2 / 41997 <1%
  --Register as FF 6775 / 41997 17%
BSRAM 64 / 140 46%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
X_oschin Base 10.000 100.0 0.000 5.000 X_oschin_ibuf/I
X_osclin Base 10.000 100.0 0.000 5.000 X_osclin_ibuf/I
X_tck Base 10.000 100.0 0.000 5.000 X_tck_ibuf/I
ae250_chip/gen_SPI1_SUPPORT.u_spi1/u_spi_spiif/spi_r_clk Base 10.000 100.0 0.000 5.000 ae250_chip/gen_SPI1_SUPPORT.u_spi1/u_spi_spiif/n314_s0/F

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 X_oschin 100.000(MHz) 52.813(MHz) 23 TOP
2 X_osclin 100.000(MHz) 1349.527(MHz) 1 TOP
3 X_tck 100.000(MHz) 111.086(MHz) 5 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack -8.935
Data Arrival Time 19.260
Data Required Time 10.325
From ae250_chip/ahb2apb/u_cmd_fifo/rd_ptr_0_s2
To ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/spi_addr_r_2_s1
Launch Clk X_oschin[R]
Latch Clk X_oschin[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 X_oschin
0.000 0.000 tCL RR 1 X_oschin_ibuf/I
0.000 0.000 tINS RR 6781 X_oschin_ibuf/O
0.360 0.360 tNET RR 1 ae250_chip/ahb2apb/u_cmd_fifo/rd_ptr_0_s2/CLK
0.592 0.232 tC2Q RF 9 ae250_chip/ahb2apb/u_cmd_fifo/rd_ptr_0_s2/Q
1.066 0.474 tNET FF 4 ae250_chip/ahb2apb/u_cmd_fifo/mem_mem_0_3_s/RAD[0]
1.583 0.517 tINS FF 22 ae250_chip/ahb2apb/u_cmd_fifo/mem_mem_0_3_s/DO[3]
2.057 0.474 tNET FF 1 ae250_chip/ahb2apb/paddr_miss_s5/I3
2.428 0.371 tINS FF 2 ae250_chip/ahb2apb/paddr_miss_s5/F
2.902 0.474 tNET FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/u_spi_regif/reg_rd_a_Z_s5/I3
3.273 0.371 tINS FF 5 ae250_chip/gen_SPI1_SUPPORT.u_spi1/u_spi_regif/reg_rd_a_Z_s5/F
3.747 0.474 tNET FF 1 ae250_chip/ahb2apb/n2673_s1/I1
4.302 0.555 tINS FF 3 ae250_chip/ahb2apb/n2673_s1/F
4.776 0.474 tNET FF 1 ae250_chip/ahb2apb/u_cmd_fifo/n38_s2/I2
5.229 0.453 tINS FF 4 ae250_chip/ahb2apb/u_cmd_fifo/n38_s2/F
5.703 0.474 tNET FF 1 ae250_chip/Matrix/gen_slv1_commander.u_slv_commander1/bmc_hs1_hready_s1/I0
6.220 0.517 tINS FF 4 ae250_chip/Matrix/gen_slv1_commander.u_slv_commander1/bmc_hs1_hready_s1/F
6.694 0.474 tNET FF 1 ae250_chip/Matrix/gen_slv1_commander.u_slv_commander1/bmc_hs1_hready_s0/I0
7.211 0.517 tINS FF 1 ae250_chip/Matrix/gen_slv1_commander.u_slv_commander1/bmc_hs1_hready_s0/F
7.685 0.474 tNET FF 1 ae250_chip/Matrix/gen_mst0_commander.u_mst_commander0/u_mst_decoder/gen_addrdec0.u_ahb_addrdec0/mst0_slv0_req_s7/I1
8.240 0.555 tINS FF 1 ae250_chip/Matrix/gen_mst0_commander.u_mst_commander0/u_mst_decoder/gen_addrdec0.u_ahb_addrdec0/mst0_slv0_req_s7/F
8.714 0.474 tNET FF 1 ae250_chip/Matrix/gen_mst0_commander.u_mst_commander0/u_mst_decoder/gen_addrdec0.u_ahb_addrdec0/mst0_slv0_req_s4/I3
9.085 0.371 tINS FF 1 ae250_chip/Matrix/gen_mst0_commander.u_mst_commander0/u_mst_decoder/gen_addrdec0.u_ahb_addrdec0/mst0_slv0_req_s4/F
9.559 0.474 tNET FF 1 ae250_chip/Matrix/gen_mst0_commander.u_mst_commander0/u_mst_decoder/gen_addrdec0.u_ahb_addrdec0/mst0_slv0_req_s0/I0
10.076 0.517 tINS FF 15 ae250_chip/Matrix/gen_mst0_commander.u_mst_commander0/u_mst_decoder/gen_addrdec0.u_ahb_addrdec0/mst0_slv0_req_s0/F
10.550 0.474 tNET FF 1 ae250_chip/Matrix/gen_mst0_commander.u_mst_commander0/u_mst_decoder/gen_addrdec15.u_ahb_addrdec15/mst0_slv15_req_s/I0
11.067 0.517 tINS FF 5 ae250_chip/Matrix/gen_mst0_commander.u_mst_commander0/u_mst_decoder/gen_addrdec15.u_ahb_addrdec15/mst0_slv15_req_s/F
11.541 0.474 tNET FF 1 ae250_chip/Matrix/gen_slv15_commander.u_slv_commander15/n215_s0/I3
11.912 0.371 tINS FF 37 ae250_chip/Matrix/gen_slv15_commander.u_slv_commander15/n215_s0/F
12.386 0.474 tNET FF 1 ae250_chip/Matrix/gen_slv15_commander.u_slv_commander15/hs_haddr_2_s20/I0
12.903 0.517 tINS FF 3 ae250_chip/Matrix/gen_slv15_commander.u_slv_commander15/hs_haddr_2_s20/F
13.377 0.474 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n21_s0/I0
13.926 0.549 tINS FR 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n21_s0/COUT
13.926 0.000 tNET RR 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n22_s0/CIN
13.961 0.035 tINS RF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n22_s0/COUT
13.961 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n23_s0/CIN
13.996 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n23_s0/COUT
13.996 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n24_s0/CIN
14.032 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n24_s0/COUT
14.032 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n25_s0/CIN
14.067 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n25_s0/COUT
14.067 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n26_s0/CIN
14.102 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n26_s0/COUT
14.102 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n27_s0/CIN
14.137 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n27_s0/COUT
14.137 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n28_s0/CIN
14.172 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n28_s0/COUT
14.172 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n29_s0/CIN
14.208 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n29_s0/COUT
14.208 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n30_s0/CIN
14.243 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n30_s0/COUT
14.243 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n31_s0/CIN
14.278 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n31_s0/COUT
14.278 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n32_s0/CIN
14.313 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n32_s0/COUT
14.313 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n33_s0/CIN
14.348 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n33_s0/COUT
14.348 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n34_s0/CIN
14.384 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n34_s0/COUT
14.384 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n35_s0/CIN
14.419 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n35_s0/COUT
14.419 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n36_s0/CIN
14.454 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n36_s0/COUT
14.454 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n37_s0/CIN
14.489 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n37_s0/COUT
14.489 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n38_s0/CIN
14.524 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n38_s0/COUT
14.524 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n39_s0/CIN
14.560 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n39_s0/COUT
14.560 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n40_s0/CIN
14.595 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n40_s0/COUT
14.595 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n41_s0/CIN
14.630 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n41_s0/COUT
14.630 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n42_s0/CIN
14.665 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n42_s0/COUT
14.665 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n43_s0/CIN
14.700 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n43_s0/COUT
14.700 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n44_s0/CIN
14.736 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n44_s0/COUT
14.736 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n45_s0/CIN
14.771 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n45_s0/COUT
14.771 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n46_s0/CIN
14.806 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n46_s0/COUT
14.806 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n47_s0/CIN
14.841 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n47_s0/COUT
14.841 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n48_s0/CIN
14.876 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n48_s0/COUT
14.876 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n49_s0/CIN
14.912 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n49_s0/COUT
14.912 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n50_s0/CIN
14.947 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n50_s0/COUT
15.421 0.474 tNET FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n483_s8/I0
15.938 0.517 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n483_s8/F
16.412 0.474 tNET FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n483_s6/I2
16.865 0.453 tINS FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n483_s6/F
17.339 0.474 tNET FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n483_s4/I0
17.856 0.517 tINS FF 31 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n483_s4/F
18.330 0.474 tNET FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/spi_addr_r_31_s3/I1
18.900 0.570 tINS FR 30 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/spi_addr_r_31_s3/F
19.260 0.360 tNET RR 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/spi_addr_r_2_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 X_oschin
10.000 0.000 tCL RR 1 X_oschin_ibuf/I
10.000 0.000 tINS RR 6781 X_oschin_ibuf/O
10.360 0.360 tNET RR 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/spi_addr_r_2_s1/CLK
10.325 -0.035 tSu 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/spi_addr_r_2_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 23
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%
Arrival Data Path Delay: cell: 9.776, 51.724%; route: 8.892, 47.048%; tC2Q: 0.232, 1.228%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%

Path 2

Path Summary:
Slack -8.935
Data Arrival Time 19.260
Data Required Time 10.325
From ae250_chip/ahb2apb/u_cmd_fifo/rd_ptr_0_s2
To ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/spi_addr_r_3_s1
Launch Clk X_oschin[R]
Latch Clk X_oschin[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 X_oschin
0.000 0.000 tCL RR 1 X_oschin_ibuf/I
0.000 0.000 tINS RR 6781 X_oschin_ibuf/O
0.360 0.360 tNET RR 1 ae250_chip/ahb2apb/u_cmd_fifo/rd_ptr_0_s2/CLK
0.592 0.232 tC2Q RF 9 ae250_chip/ahb2apb/u_cmd_fifo/rd_ptr_0_s2/Q
1.066 0.474 tNET FF 4 ae250_chip/ahb2apb/u_cmd_fifo/mem_mem_0_3_s/RAD[0]
1.583 0.517 tINS FF 22 ae250_chip/ahb2apb/u_cmd_fifo/mem_mem_0_3_s/DO[3]
2.057 0.474 tNET FF 1 ae250_chip/ahb2apb/paddr_miss_s5/I3
2.428 0.371 tINS FF 2 ae250_chip/ahb2apb/paddr_miss_s5/F
2.902 0.474 tNET FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/u_spi_regif/reg_rd_a_Z_s5/I3
3.273 0.371 tINS FF 5 ae250_chip/gen_SPI1_SUPPORT.u_spi1/u_spi_regif/reg_rd_a_Z_s5/F
3.747 0.474 tNET FF 1 ae250_chip/ahb2apb/n2673_s1/I1
4.302 0.555 tINS FF 3 ae250_chip/ahb2apb/n2673_s1/F
4.776 0.474 tNET FF 1 ae250_chip/ahb2apb/u_cmd_fifo/n38_s2/I2
5.229 0.453 tINS FF 4 ae250_chip/ahb2apb/u_cmd_fifo/n38_s2/F
5.703 0.474 tNET FF 1 ae250_chip/Matrix/gen_slv1_commander.u_slv_commander1/bmc_hs1_hready_s1/I0
6.220 0.517 tINS FF 4 ae250_chip/Matrix/gen_slv1_commander.u_slv_commander1/bmc_hs1_hready_s1/F
6.694 0.474 tNET FF 1 ae250_chip/Matrix/gen_slv1_commander.u_slv_commander1/bmc_hs1_hready_s0/I0
7.211 0.517 tINS FF 1 ae250_chip/Matrix/gen_slv1_commander.u_slv_commander1/bmc_hs1_hready_s0/F
7.685 0.474 tNET FF 1 ae250_chip/Matrix/gen_mst0_commander.u_mst_commander0/u_mst_decoder/gen_addrdec0.u_ahb_addrdec0/mst0_slv0_req_s7/I1
8.240 0.555 tINS FF 1 ae250_chip/Matrix/gen_mst0_commander.u_mst_commander0/u_mst_decoder/gen_addrdec0.u_ahb_addrdec0/mst0_slv0_req_s7/F
8.714 0.474 tNET FF 1 ae250_chip/Matrix/gen_mst0_commander.u_mst_commander0/u_mst_decoder/gen_addrdec0.u_ahb_addrdec0/mst0_slv0_req_s4/I3
9.085 0.371 tINS FF 1 ae250_chip/Matrix/gen_mst0_commander.u_mst_commander0/u_mst_decoder/gen_addrdec0.u_ahb_addrdec0/mst0_slv0_req_s4/F
9.559 0.474 tNET FF 1 ae250_chip/Matrix/gen_mst0_commander.u_mst_commander0/u_mst_decoder/gen_addrdec0.u_ahb_addrdec0/mst0_slv0_req_s0/I0
10.076 0.517 tINS FF 15 ae250_chip/Matrix/gen_mst0_commander.u_mst_commander0/u_mst_decoder/gen_addrdec0.u_ahb_addrdec0/mst0_slv0_req_s0/F
10.550 0.474 tNET FF 1 ae250_chip/Matrix/gen_mst0_commander.u_mst_commander0/u_mst_decoder/gen_addrdec15.u_ahb_addrdec15/mst0_slv15_req_s/I0
11.067 0.517 tINS FF 5 ae250_chip/Matrix/gen_mst0_commander.u_mst_commander0/u_mst_decoder/gen_addrdec15.u_ahb_addrdec15/mst0_slv15_req_s/F
11.541 0.474 tNET FF 1 ae250_chip/Matrix/gen_slv15_commander.u_slv_commander15/n215_s0/I3
11.912 0.371 tINS FF 37 ae250_chip/Matrix/gen_slv15_commander.u_slv_commander15/n215_s0/F
12.386 0.474 tNET FF 1 ae250_chip/Matrix/gen_slv15_commander.u_slv_commander15/hs_haddr_2_s20/I0
12.903 0.517 tINS FF 3 ae250_chip/Matrix/gen_slv15_commander.u_slv_commander15/hs_haddr_2_s20/F
13.377 0.474 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n21_s0/I0
13.926 0.549 tINS FR 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n21_s0/COUT
13.926 0.000 tNET RR 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n22_s0/CIN
13.961 0.035 tINS RF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n22_s0/COUT
13.961 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n23_s0/CIN
13.996 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n23_s0/COUT
13.996 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n24_s0/CIN
14.032 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n24_s0/COUT
14.032 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n25_s0/CIN
14.067 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n25_s0/COUT
14.067 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n26_s0/CIN
14.102 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n26_s0/COUT
14.102 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n27_s0/CIN
14.137 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n27_s0/COUT
14.137 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n28_s0/CIN
14.172 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n28_s0/COUT
14.172 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n29_s0/CIN
14.208 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n29_s0/COUT
14.208 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n30_s0/CIN
14.243 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n30_s0/COUT
14.243 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n31_s0/CIN
14.278 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n31_s0/COUT
14.278 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n32_s0/CIN
14.313 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n32_s0/COUT
14.313 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n33_s0/CIN
14.348 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n33_s0/COUT
14.348 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n34_s0/CIN
14.384 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n34_s0/COUT
14.384 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n35_s0/CIN
14.419 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n35_s0/COUT
14.419 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n36_s0/CIN
14.454 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n36_s0/COUT
14.454 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n37_s0/CIN
14.489 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n37_s0/COUT
14.489 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n38_s0/CIN
14.524 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n38_s0/COUT
14.524 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n39_s0/CIN
14.560 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n39_s0/COUT
14.560 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n40_s0/CIN
14.595 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n40_s0/COUT
14.595 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n41_s0/CIN
14.630 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n41_s0/COUT
14.630 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n42_s0/CIN
14.665 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n42_s0/COUT
14.665 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n43_s0/CIN
14.700 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n43_s0/COUT
14.700 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n44_s0/CIN
14.736 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n44_s0/COUT
14.736 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n45_s0/CIN
14.771 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n45_s0/COUT
14.771 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n46_s0/CIN
14.806 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n46_s0/COUT
14.806 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n47_s0/CIN
14.841 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n47_s0/COUT
14.841 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n48_s0/CIN
14.876 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n48_s0/COUT
14.876 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n49_s0/CIN
14.912 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n49_s0/COUT
14.912 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n50_s0/CIN
14.947 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n50_s0/COUT
15.421 0.474 tNET FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n483_s8/I0
15.938 0.517 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n483_s8/F
16.412 0.474 tNET FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n483_s6/I2
16.865 0.453 tINS FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n483_s6/F
17.339 0.474 tNET FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n483_s4/I0
17.856 0.517 tINS FF 31 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n483_s4/F
18.330 0.474 tNET FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/spi_addr_r_31_s3/I1
18.900 0.570 tINS FR 30 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/spi_addr_r_31_s3/F
19.260 0.360 tNET RR 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/spi_addr_r_3_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 X_oschin
10.000 0.000 tCL RR 1 X_oschin_ibuf/I
10.000 0.000 tINS RR 6781 X_oschin_ibuf/O
10.360 0.360 tNET RR 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/spi_addr_r_3_s1/CLK
10.325 -0.035 tSu 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/spi_addr_r_3_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 23
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%
Arrival Data Path Delay: cell: 9.776, 51.724%; route: 8.892, 47.048%; tC2Q: 0.232, 1.228%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%

Path 3

Path Summary:
Slack -8.935
Data Arrival Time 19.260
Data Required Time 10.325
From ae250_chip/ahb2apb/u_cmd_fifo/rd_ptr_0_s2
To ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/spi_addr_r_4_s1
Launch Clk X_oschin[R]
Latch Clk X_oschin[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 X_oschin
0.000 0.000 tCL RR 1 X_oschin_ibuf/I
0.000 0.000 tINS RR 6781 X_oschin_ibuf/O
0.360 0.360 tNET RR 1 ae250_chip/ahb2apb/u_cmd_fifo/rd_ptr_0_s2/CLK
0.592 0.232 tC2Q RF 9 ae250_chip/ahb2apb/u_cmd_fifo/rd_ptr_0_s2/Q
1.066 0.474 tNET FF 4 ae250_chip/ahb2apb/u_cmd_fifo/mem_mem_0_3_s/RAD[0]
1.583 0.517 tINS FF 22 ae250_chip/ahb2apb/u_cmd_fifo/mem_mem_0_3_s/DO[3]
2.057 0.474 tNET FF 1 ae250_chip/ahb2apb/paddr_miss_s5/I3
2.428 0.371 tINS FF 2 ae250_chip/ahb2apb/paddr_miss_s5/F
2.902 0.474 tNET FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/u_spi_regif/reg_rd_a_Z_s5/I3
3.273 0.371 tINS FF 5 ae250_chip/gen_SPI1_SUPPORT.u_spi1/u_spi_regif/reg_rd_a_Z_s5/F
3.747 0.474 tNET FF 1 ae250_chip/ahb2apb/n2673_s1/I1
4.302 0.555 tINS FF 3 ae250_chip/ahb2apb/n2673_s1/F
4.776 0.474 tNET FF 1 ae250_chip/ahb2apb/u_cmd_fifo/n38_s2/I2
5.229 0.453 tINS FF 4 ae250_chip/ahb2apb/u_cmd_fifo/n38_s2/F
5.703 0.474 tNET FF 1 ae250_chip/Matrix/gen_slv1_commander.u_slv_commander1/bmc_hs1_hready_s1/I0
6.220 0.517 tINS FF 4 ae250_chip/Matrix/gen_slv1_commander.u_slv_commander1/bmc_hs1_hready_s1/F
6.694 0.474 tNET FF 1 ae250_chip/Matrix/gen_slv1_commander.u_slv_commander1/bmc_hs1_hready_s0/I0
7.211 0.517 tINS FF 1 ae250_chip/Matrix/gen_slv1_commander.u_slv_commander1/bmc_hs1_hready_s0/F
7.685 0.474 tNET FF 1 ae250_chip/Matrix/gen_mst0_commander.u_mst_commander0/u_mst_decoder/gen_addrdec0.u_ahb_addrdec0/mst0_slv0_req_s7/I1
8.240 0.555 tINS FF 1 ae250_chip/Matrix/gen_mst0_commander.u_mst_commander0/u_mst_decoder/gen_addrdec0.u_ahb_addrdec0/mst0_slv0_req_s7/F
8.714 0.474 tNET FF 1 ae250_chip/Matrix/gen_mst0_commander.u_mst_commander0/u_mst_decoder/gen_addrdec0.u_ahb_addrdec0/mst0_slv0_req_s4/I3
9.085 0.371 tINS FF 1 ae250_chip/Matrix/gen_mst0_commander.u_mst_commander0/u_mst_decoder/gen_addrdec0.u_ahb_addrdec0/mst0_slv0_req_s4/F
9.559 0.474 tNET FF 1 ae250_chip/Matrix/gen_mst0_commander.u_mst_commander0/u_mst_decoder/gen_addrdec0.u_ahb_addrdec0/mst0_slv0_req_s0/I0
10.076 0.517 tINS FF 15 ae250_chip/Matrix/gen_mst0_commander.u_mst_commander0/u_mst_decoder/gen_addrdec0.u_ahb_addrdec0/mst0_slv0_req_s0/F
10.550 0.474 tNET FF 1 ae250_chip/Matrix/gen_mst0_commander.u_mst_commander0/u_mst_decoder/gen_addrdec15.u_ahb_addrdec15/mst0_slv15_req_s/I0
11.067 0.517 tINS FF 5 ae250_chip/Matrix/gen_mst0_commander.u_mst_commander0/u_mst_decoder/gen_addrdec15.u_ahb_addrdec15/mst0_slv15_req_s/F
11.541 0.474 tNET FF 1 ae250_chip/Matrix/gen_slv15_commander.u_slv_commander15/n215_s0/I3
11.912 0.371 tINS FF 37 ae250_chip/Matrix/gen_slv15_commander.u_slv_commander15/n215_s0/F
12.386 0.474 tNET FF 1 ae250_chip/Matrix/gen_slv15_commander.u_slv_commander15/hs_haddr_2_s20/I0
12.903 0.517 tINS FF 3 ae250_chip/Matrix/gen_slv15_commander.u_slv_commander15/hs_haddr_2_s20/F
13.377 0.474 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n21_s0/I0
13.926 0.549 tINS FR 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n21_s0/COUT
13.926 0.000 tNET RR 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n22_s0/CIN
13.961 0.035 tINS RF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n22_s0/COUT
13.961 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n23_s0/CIN
13.996 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n23_s0/COUT
13.996 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n24_s0/CIN
14.032 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n24_s0/COUT
14.032 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n25_s0/CIN
14.067 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n25_s0/COUT
14.067 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n26_s0/CIN
14.102 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n26_s0/COUT
14.102 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n27_s0/CIN
14.137 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n27_s0/COUT
14.137 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n28_s0/CIN
14.172 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n28_s0/COUT
14.172 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n29_s0/CIN
14.208 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n29_s0/COUT
14.208 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n30_s0/CIN
14.243 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n30_s0/COUT
14.243 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n31_s0/CIN
14.278 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n31_s0/COUT
14.278 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n32_s0/CIN
14.313 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n32_s0/COUT
14.313 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n33_s0/CIN
14.348 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n33_s0/COUT
14.348 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n34_s0/CIN
14.384 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n34_s0/COUT
14.384 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n35_s0/CIN
14.419 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n35_s0/COUT
14.419 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n36_s0/CIN
14.454 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n36_s0/COUT
14.454 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n37_s0/CIN
14.489 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n37_s0/COUT
14.489 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n38_s0/CIN
14.524 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n38_s0/COUT
14.524 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n39_s0/CIN
14.560 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n39_s0/COUT
14.560 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n40_s0/CIN
14.595 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n40_s0/COUT
14.595 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n41_s0/CIN
14.630 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n41_s0/COUT
14.630 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n42_s0/CIN
14.665 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n42_s0/COUT
14.665 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n43_s0/CIN
14.700 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n43_s0/COUT
14.700 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n44_s0/CIN
14.736 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n44_s0/COUT
14.736 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n45_s0/CIN
14.771 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n45_s0/COUT
14.771 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n46_s0/CIN
14.806 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n46_s0/COUT
14.806 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n47_s0/CIN
14.841 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n47_s0/COUT
14.841 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n48_s0/CIN
14.876 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n48_s0/COUT
14.876 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n49_s0/CIN
14.912 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n49_s0/COUT
14.912 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n50_s0/CIN
14.947 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n50_s0/COUT
15.421 0.474 tNET FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n483_s8/I0
15.938 0.517 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n483_s8/F
16.412 0.474 tNET FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n483_s6/I2
16.865 0.453 tINS FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n483_s6/F
17.339 0.474 tNET FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n483_s4/I0
17.856 0.517 tINS FF 31 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n483_s4/F
18.330 0.474 tNET FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/spi_addr_r_31_s3/I1
18.900 0.570 tINS FR 30 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/spi_addr_r_31_s3/F
19.260 0.360 tNET RR 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/spi_addr_r_4_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 X_oschin
10.000 0.000 tCL RR 1 X_oschin_ibuf/I
10.000 0.000 tINS RR 6781 X_oschin_ibuf/O
10.360 0.360 tNET RR 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/spi_addr_r_4_s1/CLK
10.325 -0.035 tSu 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/spi_addr_r_4_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 23
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%
Arrival Data Path Delay: cell: 9.776, 51.724%; route: 8.892, 47.048%; tC2Q: 0.232, 1.228%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%

Path 4

Path Summary:
Slack -8.935
Data Arrival Time 19.260
Data Required Time 10.325
From ae250_chip/ahb2apb/u_cmd_fifo/rd_ptr_0_s2
To ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/spi_addr_r_5_s1
Launch Clk X_oschin[R]
Latch Clk X_oschin[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 X_oschin
0.000 0.000 tCL RR 1 X_oschin_ibuf/I
0.000 0.000 tINS RR 6781 X_oschin_ibuf/O
0.360 0.360 tNET RR 1 ae250_chip/ahb2apb/u_cmd_fifo/rd_ptr_0_s2/CLK
0.592 0.232 tC2Q RF 9 ae250_chip/ahb2apb/u_cmd_fifo/rd_ptr_0_s2/Q
1.066 0.474 tNET FF 4 ae250_chip/ahb2apb/u_cmd_fifo/mem_mem_0_3_s/RAD[0]
1.583 0.517 tINS FF 22 ae250_chip/ahb2apb/u_cmd_fifo/mem_mem_0_3_s/DO[3]
2.057 0.474 tNET FF 1 ae250_chip/ahb2apb/paddr_miss_s5/I3
2.428 0.371 tINS FF 2 ae250_chip/ahb2apb/paddr_miss_s5/F
2.902 0.474 tNET FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/u_spi_regif/reg_rd_a_Z_s5/I3
3.273 0.371 tINS FF 5 ae250_chip/gen_SPI1_SUPPORT.u_spi1/u_spi_regif/reg_rd_a_Z_s5/F
3.747 0.474 tNET FF 1 ae250_chip/ahb2apb/n2673_s1/I1
4.302 0.555 tINS FF 3 ae250_chip/ahb2apb/n2673_s1/F
4.776 0.474 tNET FF 1 ae250_chip/ahb2apb/u_cmd_fifo/n38_s2/I2
5.229 0.453 tINS FF 4 ae250_chip/ahb2apb/u_cmd_fifo/n38_s2/F
5.703 0.474 tNET FF 1 ae250_chip/Matrix/gen_slv1_commander.u_slv_commander1/bmc_hs1_hready_s1/I0
6.220 0.517 tINS FF 4 ae250_chip/Matrix/gen_slv1_commander.u_slv_commander1/bmc_hs1_hready_s1/F
6.694 0.474 tNET FF 1 ae250_chip/Matrix/gen_slv1_commander.u_slv_commander1/bmc_hs1_hready_s0/I0
7.211 0.517 tINS FF 1 ae250_chip/Matrix/gen_slv1_commander.u_slv_commander1/bmc_hs1_hready_s0/F
7.685 0.474 tNET FF 1 ae250_chip/Matrix/gen_mst0_commander.u_mst_commander0/u_mst_decoder/gen_addrdec0.u_ahb_addrdec0/mst0_slv0_req_s7/I1
8.240 0.555 tINS FF 1 ae250_chip/Matrix/gen_mst0_commander.u_mst_commander0/u_mst_decoder/gen_addrdec0.u_ahb_addrdec0/mst0_slv0_req_s7/F
8.714 0.474 tNET FF 1 ae250_chip/Matrix/gen_mst0_commander.u_mst_commander0/u_mst_decoder/gen_addrdec0.u_ahb_addrdec0/mst0_slv0_req_s4/I3
9.085 0.371 tINS FF 1 ae250_chip/Matrix/gen_mst0_commander.u_mst_commander0/u_mst_decoder/gen_addrdec0.u_ahb_addrdec0/mst0_slv0_req_s4/F
9.559 0.474 tNET FF 1 ae250_chip/Matrix/gen_mst0_commander.u_mst_commander0/u_mst_decoder/gen_addrdec0.u_ahb_addrdec0/mst0_slv0_req_s0/I0
10.076 0.517 tINS FF 15 ae250_chip/Matrix/gen_mst0_commander.u_mst_commander0/u_mst_decoder/gen_addrdec0.u_ahb_addrdec0/mst0_slv0_req_s0/F
10.550 0.474 tNET FF 1 ae250_chip/Matrix/gen_mst0_commander.u_mst_commander0/u_mst_decoder/gen_addrdec15.u_ahb_addrdec15/mst0_slv15_req_s/I0
11.067 0.517 tINS FF 5 ae250_chip/Matrix/gen_mst0_commander.u_mst_commander0/u_mst_decoder/gen_addrdec15.u_ahb_addrdec15/mst0_slv15_req_s/F
11.541 0.474 tNET FF 1 ae250_chip/Matrix/gen_slv15_commander.u_slv_commander15/n215_s0/I3
11.912 0.371 tINS FF 37 ae250_chip/Matrix/gen_slv15_commander.u_slv_commander15/n215_s0/F
12.386 0.474 tNET FF 1 ae250_chip/Matrix/gen_slv15_commander.u_slv_commander15/hs_haddr_2_s20/I0
12.903 0.517 tINS FF 3 ae250_chip/Matrix/gen_slv15_commander.u_slv_commander15/hs_haddr_2_s20/F
13.377 0.474 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n21_s0/I0
13.926 0.549 tINS FR 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n21_s0/COUT
13.926 0.000 tNET RR 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n22_s0/CIN
13.961 0.035 tINS RF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n22_s0/COUT
13.961 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n23_s0/CIN
13.996 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n23_s0/COUT
13.996 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n24_s0/CIN
14.032 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n24_s0/COUT
14.032 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n25_s0/CIN
14.067 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n25_s0/COUT
14.067 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n26_s0/CIN
14.102 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n26_s0/COUT
14.102 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n27_s0/CIN
14.137 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n27_s0/COUT
14.137 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n28_s0/CIN
14.172 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n28_s0/COUT
14.172 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n29_s0/CIN
14.208 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n29_s0/COUT
14.208 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n30_s0/CIN
14.243 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n30_s0/COUT
14.243 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n31_s0/CIN
14.278 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n31_s0/COUT
14.278 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n32_s0/CIN
14.313 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n32_s0/COUT
14.313 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n33_s0/CIN
14.348 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n33_s0/COUT
14.348 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n34_s0/CIN
14.384 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n34_s0/COUT
14.384 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n35_s0/CIN
14.419 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n35_s0/COUT
14.419 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n36_s0/CIN
14.454 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n36_s0/COUT
14.454 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n37_s0/CIN
14.489 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n37_s0/COUT
14.489 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n38_s0/CIN
14.524 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n38_s0/COUT
14.524 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n39_s0/CIN
14.560 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n39_s0/COUT
14.560 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n40_s0/CIN
14.595 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n40_s0/COUT
14.595 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n41_s0/CIN
14.630 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n41_s0/COUT
14.630 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n42_s0/CIN
14.665 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n42_s0/COUT
14.665 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n43_s0/CIN
14.700 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n43_s0/COUT
14.700 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n44_s0/CIN
14.736 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n44_s0/COUT
14.736 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n45_s0/CIN
14.771 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n45_s0/COUT
14.771 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n46_s0/CIN
14.806 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n46_s0/COUT
14.806 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n47_s0/CIN
14.841 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n47_s0/COUT
14.841 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n48_s0/CIN
14.876 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n48_s0/COUT
14.876 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n49_s0/CIN
14.912 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n49_s0/COUT
14.912 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n50_s0/CIN
14.947 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n50_s0/COUT
15.421 0.474 tNET FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n483_s8/I0
15.938 0.517 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n483_s8/F
16.412 0.474 tNET FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n483_s6/I2
16.865 0.453 tINS FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n483_s6/F
17.339 0.474 tNET FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n483_s4/I0
17.856 0.517 tINS FF 31 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n483_s4/F
18.330 0.474 tNET FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/spi_addr_r_31_s3/I1
18.900 0.570 tINS FR 30 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/spi_addr_r_31_s3/F
19.260 0.360 tNET RR 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/spi_addr_r_5_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 X_oschin
10.000 0.000 tCL RR 1 X_oschin_ibuf/I
10.000 0.000 tINS RR 6781 X_oschin_ibuf/O
10.360 0.360 tNET RR 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/spi_addr_r_5_s1/CLK
10.325 -0.035 tSu 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/spi_addr_r_5_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 23
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%
Arrival Data Path Delay: cell: 9.776, 51.724%; route: 8.892, 47.048%; tC2Q: 0.232, 1.228%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%

Path 5

Path Summary:
Slack -8.935
Data Arrival Time 19.260
Data Required Time 10.325
From ae250_chip/ahb2apb/u_cmd_fifo/rd_ptr_0_s2
To ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/spi_addr_r_6_s1
Launch Clk X_oschin[R]
Latch Clk X_oschin[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 X_oschin
0.000 0.000 tCL RR 1 X_oschin_ibuf/I
0.000 0.000 tINS RR 6781 X_oschin_ibuf/O
0.360 0.360 tNET RR 1 ae250_chip/ahb2apb/u_cmd_fifo/rd_ptr_0_s2/CLK
0.592 0.232 tC2Q RF 9 ae250_chip/ahb2apb/u_cmd_fifo/rd_ptr_0_s2/Q
1.066 0.474 tNET FF 4 ae250_chip/ahb2apb/u_cmd_fifo/mem_mem_0_3_s/RAD[0]
1.583 0.517 tINS FF 22 ae250_chip/ahb2apb/u_cmd_fifo/mem_mem_0_3_s/DO[3]
2.057 0.474 tNET FF 1 ae250_chip/ahb2apb/paddr_miss_s5/I3
2.428 0.371 tINS FF 2 ae250_chip/ahb2apb/paddr_miss_s5/F
2.902 0.474 tNET FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/u_spi_regif/reg_rd_a_Z_s5/I3
3.273 0.371 tINS FF 5 ae250_chip/gen_SPI1_SUPPORT.u_spi1/u_spi_regif/reg_rd_a_Z_s5/F
3.747 0.474 tNET FF 1 ae250_chip/ahb2apb/n2673_s1/I1
4.302 0.555 tINS FF 3 ae250_chip/ahb2apb/n2673_s1/F
4.776 0.474 tNET FF 1 ae250_chip/ahb2apb/u_cmd_fifo/n38_s2/I2
5.229 0.453 tINS FF 4 ae250_chip/ahb2apb/u_cmd_fifo/n38_s2/F
5.703 0.474 tNET FF 1 ae250_chip/Matrix/gen_slv1_commander.u_slv_commander1/bmc_hs1_hready_s1/I0
6.220 0.517 tINS FF 4 ae250_chip/Matrix/gen_slv1_commander.u_slv_commander1/bmc_hs1_hready_s1/F
6.694 0.474 tNET FF 1 ae250_chip/Matrix/gen_slv1_commander.u_slv_commander1/bmc_hs1_hready_s0/I0
7.211 0.517 tINS FF 1 ae250_chip/Matrix/gen_slv1_commander.u_slv_commander1/bmc_hs1_hready_s0/F
7.685 0.474 tNET FF 1 ae250_chip/Matrix/gen_mst0_commander.u_mst_commander0/u_mst_decoder/gen_addrdec0.u_ahb_addrdec0/mst0_slv0_req_s7/I1
8.240 0.555 tINS FF 1 ae250_chip/Matrix/gen_mst0_commander.u_mst_commander0/u_mst_decoder/gen_addrdec0.u_ahb_addrdec0/mst0_slv0_req_s7/F
8.714 0.474 tNET FF 1 ae250_chip/Matrix/gen_mst0_commander.u_mst_commander0/u_mst_decoder/gen_addrdec0.u_ahb_addrdec0/mst0_slv0_req_s4/I3
9.085 0.371 tINS FF 1 ae250_chip/Matrix/gen_mst0_commander.u_mst_commander0/u_mst_decoder/gen_addrdec0.u_ahb_addrdec0/mst0_slv0_req_s4/F
9.559 0.474 tNET FF 1 ae250_chip/Matrix/gen_mst0_commander.u_mst_commander0/u_mst_decoder/gen_addrdec0.u_ahb_addrdec0/mst0_slv0_req_s0/I0
10.076 0.517 tINS FF 15 ae250_chip/Matrix/gen_mst0_commander.u_mst_commander0/u_mst_decoder/gen_addrdec0.u_ahb_addrdec0/mst0_slv0_req_s0/F
10.550 0.474 tNET FF 1 ae250_chip/Matrix/gen_mst0_commander.u_mst_commander0/u_mst_decoder/gen_addrdec15.u_ahb_addrdec15/mst0_slv15_req_s/I0
11.067 0.517 tINS FF 5 ae250_chip/Matrix/gen_mst0_commander.u_mst_commander0/u_mst_decoder/gen_addrdec15.u_ahb_addrdec15/mst0_slv15_req_s/F
11.541 0.474 tNET FF 1 ae250_chip/Matrix/gen_slv15_commander.u_slv_commander15/n215_s0/I3
11.912 0.371 tINS FF 37 ae250_chip/Matrix/gen_slv15_commander.u_slv_commander15/n215_s0/F
12.386 0.474 tNET FF 1 ae250_chip/Matrix/gen_slv15_commander.u_slv_commander15/hs_haddr_2_s20/I0
12.903 0.517 tINS FF 3 ae250_chip/Matrix/gen_slv15_commander.u_slv_commander15/hs_haddr_2_s20/F
13.377 0.474 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n21_s0/I0
13.926 0.549 tINS FR 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n21_s0/COUT
13.926 0.000 tNET RR 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n22_s0/CIN
13.961 0.035 tINS RF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n22_s0/COUT
13.961 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n23_s0/CIN
13.996 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n23_s0/COUT
13.996 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n24_s0/CIN
14.032 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n24_s0/COUT
14.032 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n25_s0/CIN
14.067 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n25_s0/COUT
14.067 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n26_s0/CIN
14.102 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n26_s0/COUT
14.102 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n27_s0/CIN
14.137 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n27_s0/COUT
14.137 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n28_s0/CIN
14.172 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n28_s0/COUT
14.172 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n29_s0/CIN
14.208 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n29_s0/COUT
14.208 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n30_s0/CIN
14.243 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n30_s0/COUT
14.243 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n31_s0/CIN
14.278 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n31_s0/COUT
14.278 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n32_s0/CIN
14.313 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n32_s0/COUT
14.313 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n33_s0/CIN
14.348 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n33_s0/COUT
14.348 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n34_s0/CIN
14.384 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n34_s0/COUT
14.384 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n35_s0/CIN
14.419 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n35_s0/COUT
14.419 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n36_s0/CIN
14.454 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n36_s0/COUT
14.454 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n37_s0/CIN
14.489 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n37_s0/COUT
14.489 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n38_s0/CIN
14.524 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n38_s0/COUT
14.524 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n39_s0/CIN
14.560 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n39_s0/COUT
14.560 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n40_s0/CIN
14.595 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n40_s0/COUT
14.595 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n41_s0/CIN
14.630 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n41_s0/COUT
14.630 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n42_s0/CIN
14.665 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n42_s0/COUT
14.665 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n43_s0/CIN
14.700 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n43_s0/COUT
14.700 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n44_s0/CIN
14.736 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n44_s0/COUT
14.736 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n45_s0/CIN
14.771 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n45_s0/COUT
14.771 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n46_s0/CIN
14.806 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n46_s0/COUT
14.806 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n47_s0/CIN
14.841 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n47_s0/COUT
14.841 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n48_s0/CIN
14.876 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n48_s0/COUT
14.876 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n49_s0/CIN
14.912 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n49_s0/COUT
14.912 0.000 tNET FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n50_s0/CIN
14.947 0.035 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n50_s0/COUT
15.421 0.474 tNET FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n483_s8/I0
15.938 0.517 tINS FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n483_s8/F
16.412 0.474 tNET FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n483_s6/I2
16.865 0.453 tINS FF 2 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n483_s6/F
17.339 0.474 tNET FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n483_s4/I0
17.856 0.517 tINS FF 31 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/n483_s4/F
18.330 0.474 tNET FF 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/spi_addr_r_31_s3/I1
18.900 0.570 tINS FR 30 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/spi_addr_r_31_s3/F
19.260 0.360 tNET RR 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/spi_addr_r_6_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 X_oschin
10.000 0.000 tCL RR 1 X_oschin_ibuf/I
10.000 0.000 tINS RR 6781 X_oschin_ibuf/O
10.360 0.360 tNET RR 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/spi_addr_r_6_s1/CLK
10.325 -0.035 tSu 1 ae250_chip/gen_SPI1_SUPPORT.u_spi1/gen_ATCSPI200_AHB_MEM_SUPPORT.u_spi_ahbif_ctrl/spi_addr_r_6_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 23
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%
Arrival Data Path Delay: cell: 9.776, 51.724%; route: 8.892, 47.048%; tC2Q: 0.232, 1.228%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%