Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\gowin_empu_gw1ns4\data\gowin_empu.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\gowin_empu_gw1ns4\data\gowin_empu_top.v |
GowinSynthesis Constraints File | --- |
Tool Version | V1.9.9.03 (64-bit) |
Part Number | GW1NSR-LV4CQN48PC7/I6 |
Device | GW1NSR-4C |
Created Time | Wed May 15 15:13:30 2024 |
Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | Gowin_EMPU_Top |
Synthesis Process | Running parser: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.247s, Peak memory usage = 99.445MB Running netlist conversion: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 99.445MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 99.445MB Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 99.445MB Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 99.445MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 99.445MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 99.445MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 99.445MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 99.445MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 99.445MB Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 99.445MB Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 99.445MB Tech-Mapping Phase 3: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.141s, Peak memory usage = 126.980MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.027s, Peak memory usage = 126.980MB Generate output files: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.074s, Peak memory usage = 126.980MB |
Total Time and Memory Usage | CPU time = 0h 0m 0.326s, Elapsed time = 0h 0m 0.509s, Peak memory usage = 126.980MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 21 |
I/O Buf | 21 |
    IBUF | 4 |
    OBUF | 1 |
    IOBUF | 16 |
Register | 15 |
    DFFR | 1 |
    DFFRE | 14 |
LUT | 21 |
    LUT2 | 17 |
    LUT3 | 1 |
    LUT4 | 3 |
INV | 21 |
    INV | 21 |
BSRAM | 4 |
    SDPB | 4 |
User Flash | 1 |
    FLASH256K | 1 |
EMCU | 1 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 42(42 LUT, 0 ALU) / 4608 | <1% |
Register | 15 / 3570 | <1% |
  --Register as Latch | 0 / 3570 | 0% |
  --Register as FF | 15 / 3570 | <1% |
BSRAM | 4 / 10 | 40% |
Timing
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|
sys_clk | Base | 20.000 | 50.0 | 0.000 | 10.000 | sys_clk_ibuf/I |
Max Frequency Summary:
No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | sys_clk | 50.000(MHz) | 229.929(MHz) | 3 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | 15.651 |
Data Arrival Time | 4.591 |
Data Required Time | 20.242 |
From | Gowin_EMPU_inst/builder_resetinserter_state_1_s7 |
To | Gowin_EMPU_inst/main_gowinemcu_ahbflash_addr_12_s0 |
Launch Clk | sys_clk[R] |
Latch Clk | sys_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | sys_clk | |||
0.000 | 0.000 | tCL | RR | 1 | sys_clk_ibuf/I |
0.000 | 0.000 | tINS | RR | 23 | sys_clk_ibuf/O |
0.538 | 0.538 | tNET | RR | 1 | Gowin_EMPU_inst/builder_resetinserter_state_1_s7/CLK |
0.878 | 0.340 | tC2Q | RF | 5 | Gowin_EMPU_inst/builder_resetinserter_state_1_s7/Q |
1.589 | 0.711 | tNET | FF | 1 | Gowin_EMPU_inst/main_gowinemcu_ahbflash_addr_resetinserter_next_value_ce_s2/I1 |
2.403 | 0.814 | tINS | FF | 26 | Gowin_EMPU_inst/main_gowinemcu_ahbflash_addr_resetinserter_next_value_ce_s2/F |
3.115 | 0.711 | tNET | FF | 1 | Gowin_EMPU_inst/main_gowinemcu_ahbflash_addr_resetinserter_next_value_12_s2/I0 |
3.879 | 0.765 | tINS | FF | 1 | Gowin_EMPU_inst/main_gowinemcu_ahbflash_addr_resetinserter_next_value_12_s2/F |
4.591 | 0.711 | tNET | FF | 1 | Gowin_EMPU_inst/main_gowinemcu_ahbflash_addr_12_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
20.000 | 0.000 | sys_clk | |||
20.000 | 0.000 | tCL | RR | 1 | sys_clk_ibuf/I |
20.000 | 0.000 | tINS | RR | 23 | sys_clk_ibuf/O |
20.538 | 0.538 | tNET | RR | 1 | Gowin_EMPU_inst/main_gowinemcu_ahbflash_addr_12_s0/CLK |
20.242 | -0.296 | tSu | 1 | Gowin_EMPU_inst/main_gowinemcu_ahbflash_addr_12_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 20.000 |
Logic Level: | 3 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.538, 100.000% |
Arrival Data Path Delay: | cell: 1.579, 38.963%; route: 2.134, 52.657%; tC2Q: 0.340, 8.380% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.538, 100.000% |
Path 2
Path Summary:Slack | 15.651 |
Data Arrival Time | 4.591 |
Data Required Time | 20.242 |
From | Gowin_EMPU_inst/builder_resetinserter_state_1_s7 |
To | Gowin_EMPU_inst/main_gowinemcu_ahbflash_addr_0_s0 |
Launch Clk | sys_clk[R] |
Latch Clk | sys_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | sys_clk | |||
0.000 | 0.000 | tCL | RR | 1 | sys_clk_ibuf/I |
0.000 | 0.000 | tINS | RR | 23 | sys_clk_ibuf/O |
0.538 | 0.538 | tNET | RR | 1 | Gowin_EMPU_inst/builder_resetinserter_state_1_s7/CLK |
0.878 | 0.340 | tC2Q | RF | 5 | Gowin_EMPU_inst/builder_resetinserter_state_1_s7/Q |
1.589 | 0.711 | tNET | FF | 1 | Gowin_EMPU_inst/main_gowinemcu_ahbflash_addr_resetinserter_next_value_ce_s2/I1 |
2.403 | 0.814 | tINS | FF | 26 | Gowin_EMPU_inst/main_gowinemcu_ahbflash_addr_resetinserter_next_value_ce_s2/F |
3.115 | 0.711 | tNET | FF | 1 | Gowin_EMPU_inst/main_gowinemcu_ahbflash_addr_resetinserter_next_value_0_s2/I0 |
3.879 | 0.765 | tINS | FF | 1 | Gowin_EMPU_inst/main_gowinemcu_ahbflash_addr_resetinserter_next_value_0_s2/F |
4.591 | 0.711 | tNET | FF | 1 | Gowin_EMPU_inst/main_gowinemcu_ahbflash_addr_0_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
20.000 | 0.000 | sys_clk | |||
20.000 | 0.000 | tCL | RR | 1 | sys_clk_ibuf/I |
20.000 | 0.000 | tINS | RR | 23 | sys_clk_ibuf/O |
20.538 | 0.538 | tNET | RR | 1 | Gowin_EMPU_inst/main_gowinemcu_ahbflash_addr_0_s0/CLK |
20.242 | -0.296 | tSu | 1 | Gowin_EMPU_inst/main_gowinemcu_ahbflash_addr_0_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 20.000 |
Logic Level: | 3 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.538, 100.000% |
Arrival Data Path Delay: | cell: 1.579, 38.963%; route: 2.134, 52.657%; tC2Q: 0.340, 8.380% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.538, 100.000% |
Path 3
Path Summary:Slack | 15.651 |
Data Arrival Time | 4.591 |
Data Required Time | 20.242 |
From | Gowin_EMPU_inst/builder_resetinserter_state_1_s7 |
To | Gowin_EMPU_inst/main_gowinemcu_ahbflash_addr_1_s0 |
Launch Clk | sys_clk[R] |
Latch Clk | sys_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | sys_clk | |||
0.000 | 0.000 | tCL | RR | 1 | sys_clk_ibuf/I |
0.000 | 0.000 | tINS | RR | 23 | sys_clk_ibuf/O |
0.538 | 0.538 | tNET | RR | 1 | Gowin_EMPU_inst/builder_resetinserter_state_1_s7/CLK |
0.878 | 0.340 | tC2Q | RF | 5 | Gowin_EMPU_inst/builder_resetinserter_state_1_s7/Q |
1.589 | 0.711 | tNET | FF | 1 | Gowin_EMPU_inst/main_gowinemcu_ahbflash_addr_resetinserter_next_value_ce_s2/I1 |
2.403 | 0.814 | tINS | FF | 26 | Gowin_EMPU_inst/main_gowinemcu_ahbflash_addr_resetinserter_next_value_ce_s2/F |
3.115 | 0.711 | tNET | FF | 1 | Gowin_EMPU_inst/main_gowinemcu_ahbflash_addr_resetinserter_next_value_1_s2/I0 |
3.879 | 0.765 | tINS | FF | 1 | Gowin_EMPU_inst/main_gowinemcu_ahbflash_addr_resetinserter_next_value_1_s2/F |
4.591 | 0.711 | tNET | FF | 1 | Gowin_EMPU_inst/main_gowinemcu_ahbflash_addr_1_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
20.000 | 0.000 | sys_clk | |||
20.000 | 0.000 | tCL | RR | 1 | sys_clk_ibuf/I |
20.000 | 0.000 | tINS | RR | 23 | sys_clk_ibuf/O |
20.538 | 0.538 | tNET | RR | 1 | Gowin_EMPU_inst/main_gowinemcu_ahbflash_addr_1_s0/CLK |
20.242 | -0.296 | tSu | 1 | Gowin_EMPU_inst/main_gowinemcu_ahbflash_addr_1_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 20.000 |
Logic Level: | 3 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.538, 100.000% |
Arrival Data Path Delay: | cell: 1.579, 38.963%; route: 2.134, 52.657%; tC2Q: 0.340, 8.380% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.538, 100.000% |
Path 4
Path Summary:Slack | 15.651 |
Data Arrival Time | 4.591 |
Data Required Time | 20.242 |
From | Gowin_EMPU_inst/builder_resetinserter_state_1_s7 |
To | Gowin_EMPU_inst/main_gowinemcu_ahbflash_addr_2_s0 |
Launch Clk | sys_clk[R] |
Latch Clk | sys_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | sys_clk | |||
0.000 | 0.000 | tCL | RR | 1 | sys_clk_ibuf/I |
0.000 | 0.000 | tINS | RR | 23 | sys_clk_ibuf/O |
0.538 | 0.538 | tNET | RR | 1 | Gowin_EMPU_inst/builder_resetinserter_state_1_s7/CLK |
0.878 | 0.340 | tC2Q | RF | 5 | Gowin_EMPU_inst/builder_resetinserter_state_1_s7/Q |
1.589 | 0.711 | tNET | FF | 1 | Gowin_EMPU_inst/main_gowinemcu_ahbflash_addr_resetinserter_next_value_ce_s2/I1 |
2.403 | 0.814 | tINS | FF | 26 | Gowin_EMPU_inst/main_gowinemcu_ahbflash_addr_resetinserter_next_value_ce_s2/F |
3.115 | 0.711 | tNET | FF | 1 | Gowin_EMPU_inst/main_gowinemcu_ahbflash_addr_resetinserter_next_value_2_s2/I0 |
3.879 | 0.765 | tINS | FF | 1 | Gowin_EMPU_inst/main_gowinemcu_ahbflash_addr_resetinserter_next_value_2_s2/F |
4.591 | 0.711 | tNET | FF | 1 | Gowin_EMPU_inst/main_gowinemcu_ahbflash_addr_2_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
20.000 | 0.000 | sys_clk | |||
20.000 | 0.000 | tCL | RR | 1 | sys_clk_ibuf/I |
20.000 | 0.000 | tINS | RR | 23 | sys_clk_ibuf/O |
20.538 | 0.538 | tNET | RR | 1 | Gowin_EMPU_inst/main_gowinemcu_ahbflash_addr_2_s0/CLK |
20.242 | -0.296 | tSu | 1 | Gowin_EMPU_inst/main_gowinemcu_ahbflash_addr_2_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 20.000 |
Logic Level: | 3 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.538, 100.000% |
Arrival Data Path Delay: | cell: 1.579, 38.963%; route: 2.134, 52.657%; tC2Q: 0.340, 8.380% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.538, 100.000% |
Path 5
Path Summary:Slack | 15.651 |
Data Arrival Time | 4.591 |
Data Required Time | 20.242 |
From | Gowin_EMPU_inst/builder_resetinserter_state_1_s7 |
To | Gowin_EMPU_inst/main_gowinemcu_ahbflash_addr_3_s0 |
Launch Clk | sys_clk[R] |
Latch Clk | sys_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | sys_clk | |||
0.000 | 0.000 | tCL | RR | 1 | sys_clk_ibuf/I |
0.000 | 0.000 | tINS | RR | 23 | sys_clk_ibuf/O |
0.538 | 0.538 | tNET | RR | 1 | Gowin_EMPU_inst/builder_resetinserter_state_1_s7/CLK |
0.878 | 0.340 | tC2Q | RF | 5 | Gowin_EMPU_inst/builder_resetinserter_state_1_s7/Q |
1.589 | 0.711 | tNET | FF | 1 | Gowin_EMPU_inst/main_gowinemcu_ahbflash_addr_resetinserter_next_value_ce_s2/I1 |
2.403 | 0.814 | tINS | FF | 26 | Gowin_EMPU_inst/main_gowinemcu_ahbflash_addr_resetinserter_next_value_ce_s2/F |
3.115 | 0.711 | tNET | FF | 1 | Gowin_EMPU_inst/main_gowinemcu_ahbflash_addr_resetinserter_next_value_3_s2/I0 |
3.879 | 0.765 | tINS | FF | 1 | Gowin_EMPU_inst/main_gowinemcu_ahbflash_addr_resetinserter_next_value_3_s2/F |
4.591 | 0.711 | tNET | FF | 1 | Gowin_EMPU_inst/main_gowinemcu_ahbflash_addr_3_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
20.000 | 0.000 | sys_clk | |||
20.000 | 0.000 | tCL | RR | 1 | sys_clk_ibuf/I |
20.000 | 0.000 | tINS | RR | 23 | sys_clk_ibuf/O |
20.538 | 0.538 | tNET | RR | 1 | Gowin_EMPU_inst/main_gowinemcu_ahbflash_addr_3_s0/CLK |
20.242 | -0.296 | tSu | 1 | Gowin_EMPU_inst/main_gowinemcu_ahbflash_addr_3_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 20.000 |
Logic Level: | 3 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.538, 100.000% |
Arrival Data Path Delay: | cell: 1.579, 38.963%; route: 2.134, 52.657%; tC2Q: 0.340, 8.380% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.538, 100.000% |