Timing Messages
Report Title | Timing Analysis Report |
Design File | E:\myWork\IP\releaseVerify\version\1.9.9.01\RS\Gowin_RS_Decoder_RefDesign\project\impl\gwsynthesis\fpga_project.vg |
Physical Constraints File | E:\myWork\IP\releaseVerify\version\1.9.9.01\RS\Gowin_RS_Decoder_RefDesign\project\src\demo.cst |
Timing Constraint File | --- |
Tool Version | V1.9.9.01 (64-bit) |
Part Number | GW2A-LV55PG484C8/I7 |
Device | GW2A-55 |
Device Version | C |
Created Time | Wed Jan 10 14:52:44 2024 |
Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved. |
Timing Summaries
STA Tool Run Summary:
Setup Delay Model | Slow 0.95V 85C C8/I7 |
Hold Delay Model | Fast 1.05V 0C C8/I7 |
Numbers of Paths Analyzed | 2867 |
Numbers of Endpoints Analyzed | 3100 |
Numbers of Falling Endpoints | 0 |
Numbers of Setup Violated Endpoints | 0 |
Numbers of Hold Violated Endpoints | 0 |
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Objects |
---|---|---|---|---|---|---|---|---|
SYM_CLK | Base | 10.000 | 100.000 | 0.000 | 5.000 | SYM_CLK_ibuf/I | ||
tck_pad_i | Base | 50.000 | 20.000 | 0.000 | 25.000 | tck_ibuf/I |
Max Frequency Summary:
NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | SYM_CLK | 100.000(MHz) | 121.353(MHz) | 8 | TOP |
2 | tck_pad_i | 20.000(MHz) | 142.968(MHz) | 5 | TOP |
Total Negative Slack Summary:
Clock Name | Analysis Type | Endpoints TNS | Number of Endpoints |
---|---|---|---|
SYM_CLK | Setup | 0.000 | 0 |
SYM_CLK | Hold | 0.000 | 0 |
tck_pad_i | Setup | 0.000 | 0 |
tck_pad_i | Hold | 0.000 | 0 |
Timing Details
Path Slacks Table:
Setup Paths Table
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 1.760 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_d_3_s0/Q | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_0_1_s/DI[3] | SYM_CLK:[R] | SYM_CLK:[R] | 10.000 | 0.000 | 8.206 |
2 | 1.836 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_d_3_s0/Q | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_1_1_s/DI[3] | SYM_CLK:[R] | SYM_CLK:[R] | 10.000 | 0.000 | 8.129 |
3 | 1.852 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_d_3_s0/Q | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_0_1_s/DI[2] | SYM_CLK:[R] | SYM_CLK:[R] | 10.000 | 0.000 | 8.113 |
4 | 1.929 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_d_3_s0/Q | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_1_1_s/DI[2] | SYM_CLK:[R] | SYM_CLK:[R] | 10.000 | 0.000 | 8.036 |
5 | 2.123 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_d_3_s0/Q | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_0_0_s/DI[3] | SYM_CLK:[R] | SYM_CLK:[R] | 10.000 | 0.000 | 7.842 |
6 | 2.245 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_d_3_s0/Q | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_1_0_s/DI[3] | SYM_CLK:[R] | SYM_CLK:[R] | 10.000 | 0.000 | 7.721 |
7 | 2.443 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_Div_Lamda_vo_4_s0/Q | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_0_1_s/DI[1] | SYM_CLK:[R] | SYM_CLK:[R] | 10.000 | 0.000 | 7.523 |
8 | 2.583 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_Div_Lamda_vo_1_s0/Q | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_0_1_s/DI[0] | SYM_CLK:[R] | SYM_CLK:[R] | 10.000 | 0.000 | 7.382 |
9 | 2.660 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_Div_Lamda_vo_1_s0/Q | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_1_1_s/DI[0] | SYM_CLK:[R] | SYM_CLK:[R] | 10.000 | 0.000 | 7.305 |
10 | 2.660 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_Div_Lamda_vo_1_s0/Q | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_1_0_s/DI[0] | SYM_CLK:[R] | SYM_CLK:[R] | 10.000 | 0.000 | 7.305 |
11 | 2.688 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_Div_Lamda_vo_1_s0/Q | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_0_0_s/DI[0] | SYM_CLK:[R] | SYM_CLK:[R] | 10.000 | 0.000 | 7.277 |
12 | 2.697 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_Div_Lamda_vo_4_s0/Q | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_1_1_s/DI[1] | SYM_CLK:[R] | SYM_CLK:[R] | 10.000 | 0.000 | 7.268 |
13 | 2.746 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_Div_Lamda_vo_4_s0/Q | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_1_0_s/DI[2] | SYM_CLK:[R] | SYM_CLK:[R] | 10.000 | 0.000 | 7.220 |
14 | 2.746 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_Div_Lamda_vo_4_s0/Q | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_0_0_s/DI[2] | SYM_CLK:[R] | SYM_CLK:[R] | 10.000 | 0.000 | 7.220 |
15 | 3.109 | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/delta_7_s3/Q | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/lamda_shift_12_s1/D | SYM_CLK:[R] | SYM_CLK:[R] | 10.000 | 0.000 | 6.856 |
16 | 3.137 | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/delta_7_s3/Q | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Lamda_shift_12_s0/D | SYM_CLK:[R] | SYM_CLK:[R] | 10.000 | 0.000 | 6.828 |
17 | 3.197 | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/delta_7_s3/Q | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_reg_12_s3/D | SYM_CLK:[R] | SYM_CLK:[R] | 10.000 | 0.000 | 6.768 |
18 | 3.256 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Caculate_lamda_ov_test/tmpC_7_s0/Q | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_Div_Lamda_vo_0_s0/D | SYM_CLK:[R] | SYM_CLK:[R] | 10.000 | 0.000 | 6.709 |
19 | 3.619 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_d_3_s0/Q | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_1_0_s/DI[1] | SYM_CLK:[R] | SYM_CLK:[R] | 10.000 | 0.000 | 6.347 |
20 | 3.619 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_d_3_s0/Q | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_0_0_s/DI[1] | SYM_CLK:[R] | SYM_CLK:[R] | 10.000 | 0.000 | 6.347 |
21 | 3.645 | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/delta_7_s3/Q | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/lamda_shift_14_s1/D | SYM_CLK:[R] | SYM_CLK:[R] | 10.000 | 0.000 | 6.320 |
22 | 3.654 | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/delta_7_s3/Q | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Lamda_shift_14_s0/D | SYM_CLK:[R] | SYM_CLK:[R] | 10.000 | 0.000 | 6.311 |
23 | 3.822 | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/delta_7_s3/Q | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Lamda_shift_13_s0/D | SYM_CLK:[R] | SYM_CLK:[R] | 10.000 | 0.000 | 6.143 |
24 | 3.849 | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/delta_5_s3/Q | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/lamda_shift_15_s1/D | SYM_CLK:[R] | SYM_CLK:[R] | 10.000 | 0.000 | 6.116 |
25 | 3.870 | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/delta_7_s3/Q | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/lamda_shift_13_s1/D | SYM_CLK:[R] | SYM_CLK:[R] | 10.000 | 0.000 | 6.095 |
Hold Paths Table
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 0.213 | u_la0_top/u_ao_mem_ctrl/data_reg_46_s0/Q | u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[10] | SYM_CLK:[R] | SYM_CLK:[R] | 0.000 | 0.000 | 0.462 |
2 | 0.225 | u_la0_top/u_ao_mem_ctrl/data_reg_44_s0/Q | u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[8] | SYM_CLK:[R] | SYM_CLK:[R] | 0.000 | 0.000 | 0.474 |
3 | 0.225 | u_la0_top/u_ao_mem_ctrl/data_reg_43_s0/Q | u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[7] | SYM_CLK:[R] | SYM_CLK:[R] | 0.000 | 0.000 | 0.474 |
4 | 0.225 | u_la0_top/u_ao_mem_ctrl/data_reg_40_s0/Q | u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[4] | SYM_CLK:[R] | SYM_CLK:[R] | 0.000 | 0.000 | 0.474 |
5 | 0.225 | u_la0_top/u_ao_mem_ctrl/data_reg_39_s0/Q | u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[3] | SYM_CLK:[R] | SYM_CLK:[R] | 0.000 | 0.000 | 0.474 |
6 | 0.307 | u_la0_top/data_register_17_s0/Q | u_la0_top/data_register_16_s0/D | tck_pad_i:[R] | tck_pad_i:[R] | 0.000 | 0.000 | 0.318 |
7 | 0.307 | u_la0_top/data_register_18_s0/Q | u_la0_top/data_register_17_s0/D | tck_pad_i:[R] | tck_pad_i:[R] | 0.000 | 0.000 | 0.318 |
8 | 0.307 | u_la0_top/data_register_22_s0/Q | u_la0_top/data_register_21_s0/D | tck_pad_i:[R] | tck_pad_i:[R] | 0.000 | 0.000 | 0.318 |
9 | 0.307 | u_la0_top/data_register_24_s0/Q | u_la0_top/data_register_23_s0/D | tck_pad_i:[R] | tck_pad_i:[R] | 0.000 | 0.000 | 0.318 |
10 | 0.307 | u_la0_top/data_register_27_s0/Q | u_la0_top/data_register_26_s0/D | tck_pad_i:[R] | tck_pad_i:[R] | 0.000 | 0.000 | 0.318 |
11 | 0.307 | u_la0_top/data_register_28_s0/Q | u_la0_top/data_register_27_s0/D | tck_pad_i:[R] | tck_pad_i:[R] | 0.000 | 0.000 | 0.318 |
12 | 0.307 | u_la0_top/data_register_30_s0/Q | u_la0_top/data_register_29_s0/D | tck_pad_i:[R] | tck_pad_i:[R] | 0.000 | 0.000 | 0.318 |
13 | 0.307 | u_la0_top/u_ao_mem_ctrl/data_reg_dly_47_s0/Q | u_la0_top/u_ao_mem_ctrl/data_reg_47_s0/D | SYM_CLK:[R] | SYM_CLK:[R] | 0.000 | 0.000 | 0.318 |
14 | 0.310 | u_la0_top/capture_end_tck_1_s0/Q | u_la0_top/capture_end_tck_2_s0/D | tck_pad_i:[R] | tck_pad_i:[R] | 0.000 | 0.000 | 0.321 |
15 | 0.310 | u_la0_top/data_register_60_s0/Q | u_la0_top/internal_register_select_11_s0/D | tck_pad_i:[R] | tck_pad_i:[R] | 0.000 | 0.000 | 0.321 |
16 | 0.310 | u_la0_top/data_register_63_s0/Q | u_la0_top/internal_register_select_14_s0/D | tck_pad_i:[R] | tck_pad_i:[R] | 0.000 | 0.000 | 0.321 |
17 | 0.310 | u_la0_top/data_register_13_s0/Q | u_la0_top/data_register_12_s0/D | tck_pad_i:[R] | tck_pad_i:[R] | 0.000 | 0.000 | 0.321 |
18 | 0.310 | u_la0_top/data_register_15_s0/Q | u_la0_top/data_register_14_s0/D | tck_pad_i:[R] | tck_pad_i:[R] | 0.000 | 0.000 | 0.321 |
19 | 0.310 | u_la0_top/data_register_35_s0/Q | u_la0_top/data_register_34_s0/D | tck_pad_i:[R] | tck_pad_i:[R] | 0.000 | 0.000 | 0.321 |
20 | 0.310 | u_la0_top/data_register_39_s0/Q | u_la0_top/data_register_38_s0/D | tck_pad_i:[R] | tck_pad_i:[R] | 0.000 | 0.000 | 0.321 |
21 | 0.310 | u_la0_top/data_register_42_s0/Q | u_la0_top/data_register_41_s0/D | tck_pad_i:[R] | tck_pad_i:[R] | 0.000 | 0.000 | 0.321 |
22 | 0.310 | u_icon_top/input_shift_reg_3_s0/Q | u_icon_top/input_shift_reg_2_s0/D | tck_pad_i:[R] | tck_pad_i:[R] | 0.000 | 0.000 | 0.321 |
23 | 0.310 | u_icon_top/input_shift_reg_1_s0/Q | u_icon_top/module_id_reg_1_s0/D | tck_pad_i:[R] | tck_pad_i:[R] | 0.000 | 0.000 | 0.321 |
24 | 0.314 | u_la0_top/data_register_56_s0/Q | u_la0_top/internal_register_select_7_s0/D | tck_pad_i:[R] | tck_pad_i:[R] | 0.000 | 0.000 | 0.325 |
25 | 0.314 | u_la0_top/data_register_58_s0/Q | u_la0_top/internal_register_select_9_s0/D | tck_pad_i:[R] | tck_pad_i:[R] | 0.000 | 0.000 | 0.325 |
Recovery Paths Table
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 8.506 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR | SYM_CLK:[R] | SYM_CLK:[R] | 10.000 | 0.000 | 1.459 |
2 | 8.589 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLEAR | SYM_CLK:[R] | SYM_CLK:[R] | 10.000 | 0.000 | 1.376 |
3 | 8.589 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR | SYM_CLK:[R] | SYM_CLK:[R] | 10.000 | 0.000 | 1.376 |
4 | 8.589 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR | SYM_CLK:[R] | SYM_CLK:[R] | 10.000 | 0.000 | 1.376 |
5 | 8.589 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR | SYM_CLK:[R] | SYM_CLK:[R] | 10.000 | 0.000 | 1.376 |
6 | 8.670 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR | SYM_CLK:[R] | SYM_CLK:[R] | 10.000 | 0.000 | 1.295 |
7 | 8.670 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR | SYM_CLK:[R] | SYM_CLK:[R] | 10.000 | 0.000 | 1.295 |
8 | 8.670 | u_la0_top/rst_ao_s0/Q | u_la0_top/capture_window_sel_1_s1/CLEAR | SYM_CLK:[R] | SYM_CLK:[R] | 10.000 | 0.000 | 1.295 |
9 | 8.702 | u_la0_top/rst_ao_s0/Q | u_la0_top/capture_window_sel_9_s1/CLEAR | SYM_CLK:[R] | SYM_CLK:[R] | 10.000 | 0.000 | 1.263 |
10 | 8.789 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR | SYM_CLK:[R] | SYM_CLK:[R] | 10.000 | 0.000 | 1.176 |
11 | 8.801 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR | SYM_CLK:[R] | SYM_CLK:[R] | 10.000 | 0.000 | 1.164 |
12 | 8.801 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR | SYM_CLK:[R] | SYM_CLK:[R] | 10.000 | 0.000 | 1.164 |
13 | 8.907 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR | SYM_CLK:[R] | SYM_CLK:[R] | 10.000 | 0.000 | 1.058 |
14 | 8.907 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR | SYM_CLK:[R] | SYM_CLK:[R] | 10.000 | 0.000 | 1.058 |
15 | 8.907 | u_la0_top/rst_ao_s0/Q | u_la0_top/triger_level_cnt_0_s3/CLEAR | SYM_CLK:[R] | SYM_CLK:[R] | 10.000 | 0.000 | 1.058 |
16 | 8.939 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR | SYM_CLK:[R] | SYM_CLK:[R] | 10.000 | 0.000 | 1.026 |
17 | 8.939 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR | SYM_CLK:[R] | SYM_CLK:[R] | 10.000 | 0.000 | 1.026 |
18 | 8.939 | u_la0_top/rst_ao_s0/Q | u_la0_top/internal_reg_start_dly_1_s0/CLEAR | SYM_CLK:[R] | SYM_CLK:[R] | 10.000 | 0.000 | 1.026 |
19 | 8.945 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR | SYM_CLK:[R] | SYM_CLK:[R] | 10.000 | 0.000 | 1.020 |
20 | 8.950 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR | SYM_CLK:[R] | SYM_CLK:[R] | 10.000 | 0.000 | 1.015 |
21 | 9.020 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR | SYM_CLK:[R] | SYM_CLK:[R] | 10.000 | 0.000 | 0.945 |
22 | 9.020 | u_la0_top/rst_ao_s0/Q | u_la0_top/triger_level_cnt_1_s1/CLEAR | SYM_CLK:[R] | SYM_CLK:[R] | 10.000 | 0.000 | 0.945 |
23 | 9.050 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_match_0/match_sep_s0/CLEAR | SYM_CLK:[R] | SYM_CLK:[R] | 10.000 | 0.000 | 0.915 |
24 | 9.050 | u_la0_top/rst_ao_s0/Q | u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR | SYM_CLK:[R] | SYM_CLK:[R] | 10.000 | 0.000 | 0.915 |
25 | 9.056 | u_la0_top/rst_ao_s0/Q | u_la0_top/capture_window_sel_2_s1/CLEAR | SYM_CLK:[R] | SYM_CLK:[R] | 10.000 | 0.000 | 0.909 |
Removal Paths Table
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 0.332 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR | SYM_CLK:[R] | SYM_CLK:[R] | 0.000 | 0.000 | 0.343 |
2 | 0.332 | u_la0_top/rst_ao_s0/Q | u_la0_top/capture_end_dly_s0/PRESET | SYM_CLK:[R] | SYM_CLK:[R] | 0.000 | 0.000 | 0.343 |
3 | 0.332 | u_la0_top/rst_ao_s0/Q | u_la0_top/internal_reg_start_dly_0_s0/CLEAR | SYM_CLK:[R] | SYM_CLK:[R] | 0.000 | 0.000 | 0.343 |
4 | 0.332 | u_la0_top/rst_ao_s0/Q | u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR | SYM_CLK:[R] | SYM_CLK:[R] | 0.000 | 0.000 | 0.343 |
5 | 0.459 | u_la0_top/rst_ao_s0/Q | u_la0_top/capture_window_sel_0_s3/CLEAR | SYM_CLK:[R] | SYM_CLK:[R] | 0.000 | 0.000 | 0.470 |
6 | 0.459 | u_la0_top/rst_ao_s0/Q | u_la0_top/capture_window_sel_5_s1/CLEAR | SYM_CLK:[R] | SYM_CLK:[R] | 0.000 | 0.000 | 0.470 |
7 | 0.459 | u_la0_top/rst_ao_s0/Q | u_la0_top/capture_window_sel_6_s1/CLEAR | SYM_CLK:[R] | SYM_CLK:[R] | 0.000 | 0.000 | 0.470 |
8 | 0.459 | u_la0_top/rst_ao_s0/Q | u_la0_top/capture_window_sel_7_s1/CLEAR | SYM_CLK:[R] | SYM_CLK:[R] | 0.000 | 0.000 | 0.470 |
9 | 0.459 | u_la0_top/rst_ao_s0/Q | u_la0_top/capture_window_sel_8_s1/CLEAR | SYM_CLK:[R] | SYM_CLK:[R] | 0.000 | 0.000 | 0.470 |
10 | 0.459 | u_la0_top/rst_ao_s0/Q | u_la0_top/internal_reg_start_syn_1_s0/CLEAR | SYM_CLK:[R] | SYM_CLK:[R] | 0.000 | 0.000 | 0.470 |
11 | 0.460 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR | SYM_CLK:[R] | SYM_CLK:[R] | 0.000 | 0.000 | 0.471 |
12 | 0.463 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET | SYM_CLK:[R] | SYM_CLK:[R] | 0.000 | 0.000 | 0.474 |
13 | 0.463 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR | SYM_CLK:[R] | SYM_CLK:[R] | 0.000 | 0.000 | 0.474 |
14 | 0.463 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR | SYM_CLK:[R] | SYM_CLK:[R] | 0.000 | 0.000 | 0.474 |
15 | 0.465 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR | SYM_CLK:[R] | SYM_CLK:[R] | 0.000 | 0.000 | 0.476 |
16 | 0.465 | u_la0_top/rst_ao_s0/Q | u_la0_top/capture_window_sel_3_s1/CLEAR | SYM_CLK:[R] | SYM_CLK:[R] | 0.000 | 0.000 | 0.476 |
17 | 0.465 | u_la0_top/rst_ao_s0/Q | u_la0_top/capture_window_sel_4_s1/CLEAR | SYM_CLK:[R] | SYM_CLK:[R] | 0.000 | 0.000 | 0.476 |
18 | 0.465 | u_la0_top/rst_ao_s0/Q | u_la0_top/start_reg_s0/CLEAR | SYM_CLK:[R] | SYM_CLK:[R] | 0.000 | 0.000 | 0.476 |
19 | 0.581 | u_la0_top/rst_ao_s0/Q | u_la0_top/capture_window_sel_2_s1/CLEAR | SYM_CLK:[R] | SYM_CLK:[R] | 0.000 | 0.000 | 0.592 |
20 | 0.581 | u_la0_top/rst_ao_s0/Q | u_la0_top/triger_level_cnt_2_s1/CLEAR | SYM_CLK:[R] | SYM_CLK:[R] | 0.000 | 0.000 | 0.592 |
21 | 0.581 | u_la0_top/rst_ao_s0/Q | u_la0_top/triger_level_cnt_3_s1/CLEAR | SYM_CLK:[R] | SYM_CLK:[R] | 0.000 | 0.000 | 0.592 |
22 | 0.581 | u_la0_top/rst_ao_s0/Q | u_la0_top/triger_s0/CLEAR | SYM_CLK:[R] | SYM_CLK:[R] | 0.000 | 0.000 | 0.592 |
23 | 0.581 | u_la0_top/rst_ao_s0/Q | u_la0_top/internal_reg_start_syn_0_s0/CLEAR | SYM_CLK:[R] | SYM_CLK:[R] | 0.000 | 0.000 | 0.592 |
24 | 0.585 | u_la0_top/rst_ao_s0/Q | u_la0_top/u_ao_match_0/match_sep_s0/CLEAR | SYM_CLK:[R] | SYM_CLK:[R] | 0.000 | 0.000 | 0.596 |
25 | 0.585 | u_la0_top/rst_ao_s0/Q | u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR | SYM_CLK:[R] | SYM_CLK:[R] | 0.000 | 0.000 | 0.596 |
Minimum Pulse Width Table:
Number | Slack | Actual Width | Required Width | Type | Clock | Objects |
---|---|---|---|---|---|---|
1 | 3.911 | 4.911 | 1.000 | Low Pulse Width | SYM_CLK | cycle_cnt_5_s0 |
2 | 3.911 | 4.911 | 1.000 | Low Pulse Width | SYM_CLK | cycle_cnt_3_s0 |
3 | 3.911 | 4.911 | 1.000 | Low Pulse Width | SYM_CLK | din_7_s0 |
4 | 3.911 | 4.911 | 1.000 | Low Pulse Width | SYM_CLK | noise_7_s0 |
5 | 3.911 | 4.911 | 1.000 | Low Pulse Width | SYM_CLK | RS_Encoder_Top/RS_Encoder/data_in_shift_40_s0 |
6 | 3.911 | 4.911 | 1.000 | Low Pulse Width | SYM_CLK | RS_Encoder_Top/RS_Encoder/data_in_shift_8_s0 |
7 | 3.911 | 4.911 | 1.000 | Low Pulse Width | SYM_CLK | RS_Encoder_Top/RS_Encoder/R_out_10_s0 |
8 | 3.911 | 4.911 | 1.000 | Low Pulse Width | SYM_CLK | RS_Decoder_Top/RS_Decoder/RS_Syndrome/syndrome_reg_17_s0 |
9 | 3.911 | 4.911 | 1.000 | Low Pulse Width | SYM_CLK | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_reg_14_s3 |
10 | 3.911 | 4.911 | 1.000 | Low Pulse Width | SYM_CLK | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_reg_15_s3 |
Timing Report By Analysis Type:
Setup Analysis Report
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 1.760 |
Data Arrival Time | 9.132 |
Data Required Time | 10.891 |
From | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_d_3_s0 |
To | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_0_1_s |
Launch Clk | SYM_CLK:[R] |
Latch Clk | SYM_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.926 | 0.243 | tNET | RR | 1 | R44C36[2][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_d_3_s0/CLK |
1.158 | 0.232 | tC2Q | RF | 8 | R44C36[2][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_d_3_s0/Q |
1.859 | 0.701 | tNET | FF | 1 | R39C35[0][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s19/I1 |
2.414 | 0.555 | tINS | FF | 1 | R39C35[0][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s19/F |
2.827 | 0.413 | tNET | FF | 1 | R38C36[2][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s12/I2 |
3.382 | 0.555 | tINS | FF | 4 | R38C36[2][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s12/F |
3.804 | 0.422 | tNET | FF | 1 | R39C37[3][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s5/I2 |
4.175 | 0.371 | tINS | FF | 5 | R39C37[3][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s5/F |
4.946 | 0.771 | tNET | FF | 1 | R37C40[3][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_5_s6/I1 |
5.408 | 0.462 | tINS | FR | 1 | R37C40[3][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_5_s6/F |
5.409 | 0.001 | tNET | RR | 1 | R37C40[3][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_5_s2/I3 |
5.926 | 0.517 | tINS | RF | 3 | R37C40[3][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_5_s2/F |
6.736 | 0.810 | tNET | FF | 1 | R37C36[1][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s24/I3 |
7.189 | 0.453 | tINS | FF | 2 | R37C36[1][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s24/F |
7.849 | 0.660 | tNET | FF | 1 | R37C40[1][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s1/I1 |
8.366 | 0.517 | tINS | FF | 2 | R37C40[1][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s1/F |
9.132 | 0.765 | tNET | FF | 1 | R31C38 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_0_1_s/DI[3] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | SYM_CLK | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
10.926 | 0.243 | tNET | RR | 1 | R31C38 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_0_1_s/CLK |
10.891 | -0.035 | tSu | 1 | R31C38 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_0_1_s |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 8 |
Arrival Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Arrival Data Path Delay | cell: 3.430, 41.800%; route: 4.544, 55.373%; tC2Q: 0.232, 2.827% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path2
Path Summary:
Slack | 1.836 |
Data Arrival Time | 9.055 |
Data Required Time | 10.891 |
From | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_d_3_s0 |
To | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_1_1_s |
Launch Clk | SYM_CLK:[R] |
Latch Clk | SYM_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.926 | 0.243 | tNET | RR | 1 | R44C36[2][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_d_3_s0/CLK |
1.158 | 0.232 | tC2Q | RF | 8 | R44C36[2][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_d_3_s0/Q |
1.859 | 0.701 | tNET | FF | 1 | R39C35[0][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s19/I1 |
2.414 | 0.555 | tINS | FF | 1 | R39C35[0][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s19/F |
2.827 | 0.413 | tNET | FF | 1 | R38C36[2][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s12/I2 |
3.382 | 0.555 | tINS | FF | 4 | R38C36[2][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s12/F |
3.804 | 0.422 | tNET | FF | 1 | R39C37[3][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s5/I2 |
4.175 | 0.371 | tINS | FF | 5 | R39C37[3][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s5/F |
4.946 | 0.771 | tNET | FF | 1 | R37C40[3][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_5_s6/I1 |
5.408 | 0.462 | tINS | FR | 1 | R37C40[3][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_5_s6/F |
5.409 | 0.001 | tNET | RR | 1 | R37C40[3][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_5_s2/I3 |
5.926 | 0.517 | tINS | RF | 3 | R37C40[3][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_5_s2/F |
6.736 | 0.810 | tNET | FF | 1 | R37C36[1][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s24/I3 |
7.189 | 0.453 | tINS | FF | 2 | R37C36[1][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s24/F |
7.849 | 0.660 | tNET | FF | 1 | R37C40[1][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s1/I1 |
8.366 | 0.517 | tINS | FF | 2 | R37C40[1][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s1/F |
9.055 | 0.688 | tNET | FF | 1 | R32C39 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_1_1_s/DI[3] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | SYM_CLK | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
10.926 | 0.243 | tNET | RR | 1 | R32C39 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_1_1_s/CLK |
10.891 | -0.035 | tSu | 1 | R32C39 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_1_1_s |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 8 |
Arrival Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Arrival Data Path Delay | cell: 3.430, 42.194%; route: 4.467, 54.952%; tC2Q: 0.232, 2.854% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path3
Path Summary:
Slack | 1.852 |
Data Arrival Time | 9.039 |
Data Required Time | 10.891 |
From | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_d_3_s0 |
To | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_0_1_s |
Launch Clk | SYM_CLK:[R] |
Latch Clk | SYM_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.926 | 0.243 | tNET | RR | 1 | R44C36[2][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_d_3_s0/CLK |
1.158 | 0.232 | tC2Q | RF | 8 | R44C36[2][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_d_3_s0/Q |
1.859 | 0.701 | tNET | FF | 1 | R39C35[0][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s19/I1 |
2.414 | 0.555 | tINS | FF | 1 | R39C35[0][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s19/F |
2.827 | 0.413 | tNET | FF | 1 | R38C36[2][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s12/I2 |
3.382 | 0.555 | tINS | FF | 4 | R38C36[2][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s12/F |
3.804 | 0.422 | tNET | FF | 1 | R39C37[3][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s5/I2 |
4.175 | 0.371 | tINS | FF | 5 | R39C37[3][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s5/F |
4.946 | 0.771 | tNET | FF | 1 | R37C40[3][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_5_s6/I1 |
5.408 | 0.462 | tINS | FR | 1 | R37C40[3][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_5_s6/F |
5.409 | 0.001 | tNET | RR | 1 | R37C40[3][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_5_s2/I3 |
5.926 | 0.517 | tINS | RF | 3 | R37C40[3][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_5_s2/F |
6.736 | 0.810 | tNET | FF | 1 | R37C36[1][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s24/I3 |
7.189 | 0.453 | tINS | FF | 2 | R37C36[1][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s24/F |
7.607 | 0.418 | tNET | FF | 1 | R37C39[2][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_6_s1/I1 |
8.124 | 0.517 | tINS | FF | 2 | R37C39[2][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_6_s1/F |
9.039 | 0.915 | tNET | FF | 1 | R31C38 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_0_1_s/DI[2] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | SYM_CLK | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
10.926 | 0.243 | tNET | RR | 1 | R31C38 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_0_1_s/CLK |
10.891 | -0.035 | tSu | 1 | R31C38 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_0_1_s |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 8 |
Arrival Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Arrival Data Path Delay | cell: 3.430, 42.278%; route: 4.451, 54.862%; tC2Q: 0.232, 2.860% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path4
Path Summary:
Slack | 1.929 |
Data Arrival Time | 8.962 |
Data Required Time | 10.891 |
From | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_d_3_s0 |
To | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_1_1_s |
Launch Clk | SYM_CLK:[R] |
Latch Clk | SYM_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.926 | 0.243 | tNET | RR | 1 | R44C36[2][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_d_3_s0/CLK |
1.158 | 0.232 | tC2Q | RF | 8 | R44C36[2][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_d_3_s0/Q |
1.859 | 0.701 | tNET | FF | 1 | R39C35[0][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s19/I1 |
2.414 | 0.555 | tINS | FF | 1 | R39C35[0][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s19/F |
2.827 | 0.413 | tNET | FF | 1 | R38C36[2][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s12/I2 |
3.382 | 0.555 | tINS | FF | 4 | R38C36[2][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s12/F |
3.804 | 0.422 | tNET | FF | 1 | R39C37[3][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s5/I2 |
4.175 | 0.371 | tINS | FF | 5 | R39C37[3][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s5/F |
4.946 | 0.771 | tNET | FF | 1 | R37C40[3][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_5_s6/I1 |
5.408 | 0.462 | tINS | FR | 1 | R37C40[3][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_5_s6/F |
5.409 | 0.001 | tNET | RR | 1 | R37C40[3][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_5_s2/I3 |
5.926 | 0.517 | tINS | RF | 3 | R37C40[3][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_5_s2/F |
6.736 | 0.810 | tNET | FF | 1 | R37C36[1][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s24/I3 |
7.189 | 0.453 | tINS | FF | 2 | R37C36[1][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s24/F |
7.607 | 0.418 | tNET | FF | 1 | R37C39[2][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_6_s1/I1 |
8.124 | 0.517 | tINS | FF | 2 | R37C39[2][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_6_s1/F |
8.962 | 0.838 | tNET | FF | 1 | R32C39 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_1_1_s/DI[2] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | SYM_CLK | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
10.926 | 0.243 | tNET | RR | 1 | R32C39 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_1_1_s/CLK |
10.891 | -0.035 | tSu | 1 | R32C39 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_1_1_s |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 8 |
Arrival Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Arrival Data Path Delay | cell: 3.430, 42.682%; route: 4.374, 54.431%; tC2Q: 0.232, 2.887% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path5
Path Summary:
Slack | 2.123 |
Data Arrival Time | 8.768 |
Data Required Time | 10.891 |
From | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_d_3_s0 |
To | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_0_0_s |
Launch Clk | SYM_CLK:[R] |
Latch Clk | SYM_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.926 | 0.243 | tNET | RR | 1 | R44C36[2][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_d_3_s0/CLK |
1.158 | 0.232 | tC2Q | RF | 8 | R44C36[2][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_d_3_s0/Q |
1.859 | 0.701 | tNET | FF | 1 | R39C35[0][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s19/I1 |
2.414 | 0.555 | tINS | FF | 1 | R39C35[0][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s19/F |
2.827 | 0.413 | tNET | FF | 1 | R38C36[2][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s12/I2 |
3.382 | 0.555 | tINS | FF | 4 | R38C36[2][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s12/F |
3.804 | 0.422 | tNET | FF | 1 | R39C37[3][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s5/I2 |
4.175 | 0.371 | tINS | FF | 5 | R39C37[3][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s5/F |
4.946 | 0.771 | tNET | FF | 1 | R37C40[3][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_5_s6/I1 |
5.408 | 0.462 | tINS | FR | 1 | R37C40[3][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_5_s6/F |
5.409 | 0.001 | tNET | RR | 1 | R37C40[3][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_5_s2/I3 |
5.926 | 0.517 | tINS | RF | 3 | R37C40[3][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_5_s2/F |
6.586 | 0.660 | tNET | FF | 1 | R37C35[3][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_3_s2/I2 |
7.103 | 0.517 | tINS | FF | 1 | R37C35[3][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_3_s2/F |
7.500 | 0.397 | tNET | FF | 1 | R37C37[3][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_3_s1/I2 |
7.953 | 0.453 | tINS | FF | 2 | R37C37[3][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_3_s1/F |
8.768 | 0.815 | tNET | FF | 1 | R32C37 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_0_0_s/DI[3] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | SYM_CLK | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
10.926 | 0.243 | tNET | RR | 1 | R32C37 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_0_0_s/CLK |
10.891 | -0.035 | tSu | 1 | R32C37 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_0_0_s |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 8 |
Arrival Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Arrival Data Path Delay | cell: 3.430, 43.737%; route: 4.180, 53.304%; tC2Q: 0.232, 2.958% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path6
Path Summary:
Slack | 2.245 |
Data Arrival Time | 8.646 |
Data Required Time | 10.891 |
From | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_d_3_s0 |
To | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_1_0_s |
Launch Clk | SYM_CLK:[R] |
Latch Clk | SYM_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.926 | 0.243 | tNET | RR | 1 | R44C36[2][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_d_3_s0/CLK |
1.158 | 0.232 | tC2Q | RF | 8 | R44C36[2][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_d_3_s0/Q |
1.859 | 0.701 | tNET | FF | 1 | R39C35[0][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s19/I1 |
2.414 | 0.555 | tINS | FF | 1 | R39C35[0][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s19/F |
2.827 | 0.413 | tNET | FF | 1 | R38C36[2][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s12/I2 |
3.382 | 0.555 | tINS | FF | 4 | R38C36[2][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s12/F |
3.804 | 0.422 | tNET | FF | 1 | R39C37[3][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s5/I2 |
4.175 | 0.371 | tINS | FF | 5 | R39C37[3][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s5/F |
4.946 | 0.771 | tNET | FF | 1 | R37C40[3][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_5_s6/I1 |
5.408 | 0.462 | tINS | FR | 1 | R37C40[3][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_5_s6/F |
5.409 | 0.001 | tNET | RR | 1 | R37C40[3][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_5_s2/I3 |
5.926 | 0.517 | tINS | RF | 3 | R37C40[3][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_5_s2/F |
6.586 | 0.660 | tNET | FF | 1 | R37C35[3][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_3_s2/I2 |
7.103 | 0.517 | tINS | FF | 1 | R37C35[3][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_3_s2/F |
7.500 | 0.397 | tNET | FF | 1 | R37C37[3][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_3_s1/I2 |
7.953 | 0.453 | tINS | FF | 2 | R37C37[3][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_3_s1/F |
8.646 | 0.693 | tNET | FF | 1 | R32C38 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_1_0_s/DI[3] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | SYM_CLK | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
10.926 | 0.243 | tNET | RR | 1 | R32C38 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_1_0_s/CLK |
10.891 | -0.035 | tSu | 1 | R32C38 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_1_0_s |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 8 |
Arrival Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Arrival Data Path Delay | cell: 3.430, 44.427%; route: 4.059, 52.568%; tC2Q: 0.232, 3.005% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path7
Path Summary:
Slack | 2.443 |
Data Arrival Time | 8.449 |
Data Required Time | 10.891 |
From | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_Div_Lamda_vo_4_s0 |
To | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_0_1_s |
Launch Clk | SYM_CLK:[R] |
Latch Clk | SYM_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.926 | 0.243 | tNET | RR | 1 | R46C37[0][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_Div_Lamda_vo_4_s0/CLK |
1.158 | 0.232 | tC2Q | RF | 8 | R46C37[0][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_Div_Lamda_vo_4_s0/Q |
2.013 | 0.855 | tNET | FF | 1 | R40C36[3][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s16/I1 |
2.562 | 0.549 | tINS | FR | 3 | R40C36[3][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s16/F |
2.737 | 0.175 | tNET | RR | 1 | R40C37[1][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s11/I3 |
3.254 | 0.517 | tINS | RF | 7 | R40C37[1][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s11/F |
3.928 | 0.674 | tNET | FF | 1 | R39C40[0][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_0_s19/I0 |
4.299 | 0.371 | tINS | FF | 11 | R39C40[0][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_0_s19/F |
4.731 | 0.432 | tNET | FF | 1 | R39C39[2][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_6_s6/I0 |
5.193 | 0.462 | tINS | FR | 1 | R39C39[2][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_6_s6/F |
5.194 | 0.001 | tNET | RR | 1 | R39C39[3][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_6_s2/I3 |
5.711 | 0.517 | tINS | RF | 3 | R39C39[3][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_6_s2/F |
6.210 | 0.499 | tNET | FF | 1 | R37C37[3][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_5_s3/I1 |
6.765 | 0.555 | tINS | FF | 2 | R37C37[3][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_5_s3/F |
7.017 | 0.252 | tNET | FF | 1 | R37C39[3][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_5_s1/I1 |
7.534 | 0.517 | tINS | FF | 2 | R37C39[3][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_5_s1/F |
8.449 | 0.915 | tNET | FF | 1 | R31C38 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_0_1_s/DI[1] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | SYM_CLK | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
10.926 | 0.243 | tNET | RR | 1 | R31C38 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_0_1_s/CLK |
10.891 | -0.035 | tSu | 1 | R31C38 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_0_1_s |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 8 |
Arrival Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Arrival Data Path Delay | cell: 3.488, 46.366%; route: 3.803, 50.550%; tC2Q: 0.232, 3.084% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path8
Path Summary:
Slack | 2.583 |
Data Arrival Time | 8.308 |
Data Required Time | 10.891 |
From | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_Div_Lamda_vo_1_s0 |
To | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_0_1_s |
Launch Clk | SYM_CLK:[R] |
Latch Clk | SYM_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.926 | 0.243 | tNET | RR | 1 | R46C39[0][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_Div_Lamda_vo_1_s0/CLK |
1.158 | 0.232 | tC2Q | RF | 8 | R46C39[0][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_Div_Lamda_vo_1_s0/Q |
2.108 | 0.950 | tNET | FF | 1 | R40C36[0][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_0_s13/I0 |
2.570 | 0.462 | tINS | FR | 1 | R40C36[0][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_0_s13/F |
2.571 | 0.001 | tNET | RR | 1 | R40C36[2][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_0_s4/I3 |
3.126 | 0.555 | tINS | RF | 4 | R40C36[2][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_0_s4/F |
3.550 | 0.423 | tNET | FF | 1 | R39C36[2][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_1_s14/I0 |
4.105 | 0.555 | tINS | FF | 8 | R39C36[2][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_1_s14/F |
4.924 | 0.819 | tNET | FF | 1 | R38C36[1][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_0_s21/I3 |
5.494 | 0.570 | tINS | FR | 1 | R38C36[1][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_0_s21/F |
5.495 | 0.001 | tNET | RR | 1 | R38C36[3][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_0_s9/I3 |
6.065 | 0.570 | tINS | RR | 1 | R38C36[3][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_0_s9/F |
6.237 | 0.172 | tNET | RR | 1 | R37C36[3][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_0_s3/I3 |
6.807 | 0.570 | tINS | RR | 4 | R37C36[3][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_0_s3/F |
6.988 | 0.180 | tNET | RR | 1 | R37C37[2][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_4_s1/I0 |
7.543 | 0.555 | tINS | RF | 2 | R37C37[2][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_4_s1/F |
8.308 | 0.765 | tNET | FF | 1 | R31C38 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_0_1_s/DI[0] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | SYM_CLK | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
10.926 | 0.243 | tNET | RR | 1 | R31C38 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_0_1_s/CLK |
10.891 | -0.035 | tSu | 1 | R31C38 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_0_1_s |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 8 |
Arrival Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Arrival Data Path Delay | cell: 3.837, 51.978%; route: 3.313, 44.879%; tC2Q: 0.232, 3.143% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path9
Path Summary:
Slack | 2.660 |
Data Arrival Time | 8.231 |
Data Required Time | 10.891 |
From | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_Div_Lamda_vo_1_s0 |
To | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_1_1_s |
Launch Clk | SYM_CLK:[R] |
Latch Clk | SYM_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.926 | 0.243 | tNET | RR | 1 | R46C39[0][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_Div_Lamda_vo_1_s0/CLK |
1.158 | 0.232 | tC2Q | RF | 8 | R46C39[0][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_Div_Lamda_vo_1_s0/Q |
2.108 | 0.950 | tNET | FF | 1 | R40C36[0][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_0_s13/I0 |
2.570 | 0.462 | tINS | FR | 1 | R40C36[0][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_0_s13/F |
2.571 | 0.001 | tNET | RR | 1 | R40C36[2][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_0_s4/I3 |
3.126 | 0.555 | tINS | RF | 4 | R40C36[2][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_0_s4/F |
3.550 | 0.423 | tNET | FF | 1 | R39C36[2][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_1_s14/I0 |
4.105 | 0.555 | tINS | FF | 8 | R39C36[2][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_1_s14/F |
4.924 | 0.819 | tNET | FF | 1 | R38C36[1][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_0_s21/I3 |
5.494 | 0.570 | tINS | FR | 1 | R38C36[1][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_0_s21/F |
5.495 | 0.001 | tNET | RR | 1 | R38C36[3][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_0_s9/I3 |
6.065 | 0.570 | tINS | RR | 1 | R38C36[3][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_0_s9/F |
6.237 | 0.172 | tNET | RR | 1 | R37C36[3][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_0_s3/I3 |
6.807 | 0.570 | tINS | RR | 4 | R37C36[3][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_0_s3/F |
6.988 | 0.180 | tNET | RR | 1 | R37C37[2][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_4_s1/I0 |
7.543 | 0.555 | tINS | RF | 2 | R37C37[2][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_4_s1/F |
8.231 | 0.688 | tNET | FF | 1 | R32C39 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_1_1_s/DI[0] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | SYM_CLK | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
10.926 | 0.243 | tNET | RR | 1 | R32C39 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_1_1_s/CLK |
10.891 | -0.035 | tSu | 1 | R32C39 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_1_1_s |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 8 |
Arrival Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Arrival Data Path Delay | cell: 3.837, 52.524%; route: 3.236, 44.300%; tC2Q: 0.232, 3.176% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path10
Path Summary:
Slack | 2.660 |
Data Arrival Time | 8.231 |
Data Required Time | 10.891 |
From | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_Div_Lamda_vo_1_s0 |
To | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_1_0_s |
Launch Clk | SYM_CLK:[R] |
Latch Clk | SYM_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.926 | 0.243 | tNET | RR | 1 | R46C39[0][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_Div_Lamda_vo_1_s0/CLK |
1.158 | 0.232 | tC2Q | RF | 8 | R46C39[0][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_Div_Lamda_vo_1_s0/Q |
2.108 | 0.950 | tNET | FF | 1 | R40C36[0][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_0_s13/I0 |
2.570 | 0.462 | tINS | FR | 1 | R40C36[0][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_0_s13/F |
2.571 | 0.001 | tNET | RR | 1 | R40C36[2][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_0_s4/I3 |
3.126 | 0.555 | tINS | RF | 4 | R40C36[2][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_0_s4/F |
3.550 | 0.423 | tNET | FF | 1 | R39C36[2][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_1_s14/I0 |
4.105 | 0.555 | tINS | FF | 8 | R39C36[2][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_1_s14/F |
4.924 | 0.819 | tNET | FF | 1 | R38C36[1][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_0_s21/I3 |
5.494 | 0.570 | tINS | FR | 1 | R38C36[1][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_0_s21/F |
5.495 | 0.001 | tNET | RR | 1 | R38C36[3][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_0_s9/I3 |
6.065 | 0.570 | tINS | RR | 1 | R38C36[3][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_0_s9/F |
6.237 | 0.172 | tNET | RR | 1 | R37C36[3][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_0_s3/I3 |
6.807 | 0.570 | tINS | RR | 4 | R37C36[3][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_0_s3/F |
6.988 | 0.180 | tNET | RR | 1 | R37C37[1][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_0_s1/I2 |
7.543 | 0.555 | tINS | RF | 2 | R37C37[1][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_0_s1/F |
8.231 | 0.688 | tNET | FF | 1 | R32C38 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_1_0_s/DI[0] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | SYM_CLK | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
10.926 | 0.243 | tNET | RR | 1 | R32C38 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_1_0_s/CLK |
10.891 | -0.035 | tSu | 1 | R32C38 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_1_0_s |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 8 |
Arrival Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Arrival Data Path Delay | cell: 3.837, 52.524%; route: 3.236, 44.300%; tC2Q: 0.232, 3.176% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path11
Path Summary:
Slack | 2.688 |
Data Arrival Time | 8.203 |
Data Required Time | 10.891 |
From | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_Div_Lamda_vo_1_s0 |
To | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_0_0_s |
Launch Clk | SYM_CLK:[R] |
Latch Clk | SYM_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.926 | 0.243 | tNET | RR | 1 | R46C39[0][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_Div_Lamda_vo_1_s0/CLK |
1.158 | 0.232 | tC2Q | RF | 8 | R46C39[0][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_Div_Lamda_vo_1_s0/Q |
2.108 | 0.950 | tNET | FF | 1 | R40C36[0][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_0_s13/I0 |
2.570 | 0.462 | tINS | FR | 1 | R40C36[0][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_0_s13/F |
2.571 | 0.001 | tNET | RR | 1 | R40C36[2][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_0_s4/I3 |
3.126 | 0.555 | tINS | RF | 4 | R40C36[2][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_0_s4/F |
3.550 | 0.423 | tNET | FF | 1 | R39C36[2][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_1_s14/I0 |
4.105 | 0.555 | tINS | FF | 8 | R39C36[2][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_1_s14/F |
4.924 | 0.819 | tNET | FF | 1 | R38C36[1][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_0_s21/I3 |
5.494 | 0.570 | tINS | FR | 1 | R38C36[1][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_0_s21/F |
5.495 | 0.001 | tNET | RR | 1 | R38C36[3][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_0_s9/I3 |
6.065 | 0.570 | tINS | RR | 1 | R38C36[3][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_0_s9/F |
6.237 | 0.172 | tNET | RR | 1 | R37C36[3][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_0_s3/I3 |
6.807 | 0.570 | tINS | RR | 4 | R37C36[3][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_0_s3/F |
6.988 | 0.180 | tNET | RR | 1 | R37C37[1][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_0_s1/I2 |
7.543 | 0.555 | tINS | RF | 2 | R37C37[1][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_0_s1/F |
8.203 | 0.660 | tNET | FF | 1 | R32C37 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_0_0_s/DI[0] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | SYM_CLK | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
10.926 | 0.243 | tNET | RR | 1 | R32C37 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_0_0_s/CLK |
10.891 | -0.035 | tSu | 1 | R32C37 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_0_0_s |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 8 |
Arrival Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Arrival Data Path Delay | cell: 3.837, 52.727%; route: 3.208, 44.085%; tC2Q: 0.232, 3.188% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path12
Path Summary:
Slack | 2.697 |
Data Arrival Time | 8.194 |
Data Required Time | 10.891 |
From | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_Div_Lamda_vo_4_s0 |
To | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_1_1_s |
Launch Clk | SYM_CLK:[R] |
Latch Clk | SYM_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.926 | 0.243 | tNET | RR | 1 | R46C37[0][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_Div_Lamda_vo_4_s0/CLK |
1.158 | 0.232 | tC2Q | RF | 8 | R46C37[0][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_Div_Lamda_vo_4_s0/Q |
2.013 | 0.855 | tNET | FF | 1 | R40C36[3][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s16/I1 |
2.562 | 0.549 | tINS | FR | 3 | R40C36[3][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s16/F |
2.737 | 0.175 | tNET | RR | 1 | R40C37[1][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s11/I3 |
3.254 | 0.517 | tINS | RF | 7 | R40C37[1][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s11/F |
3.928 | 0.674 | tNET | FF | 1 | R39C40[0][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_0_s19/I0 |
4.299 | 0.371 | tINS | FF | 11 | R39C40[0][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_0_s19/F |
4.731 | 0.432 | tNET | FF | 1 | R39C39[2][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_6_s6/I0 |
5.193 | 0.462 | tINS | FR | 1 | R39C39[2][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_6_s6/F |
5.194 | 0.001 | tNET | RR | 1 | R39C39[3][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_6_s2/I3 |
5.711 | 0.517 | tINS | RF | 3 | R39C39[3][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_6_s2/F |
6.210 | 0.499 | tNET | FF | 1 | R37C37[3][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_5_s3/I1 |
6.765 | 0.555 | tINS | FF | 2 | R37C37[3][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_5_s3/F |
7.017 | 0.252 | tNET | FF | 1 | R37C39[3][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_5_s1/I1 |
7.534 | 0.517 | tINS | FF | 2 | R37C39[3][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_5_s1/F |
8.194 | 0.660 | tNET | FF | 1 | R32C39 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_1_1_s/DI[1] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | SYM_CLK | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
10.926 | 0.243 | tNET | RR | 1 | R32C39 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_1_1_s/CLK |
10.891 | -0.035 | tSu | 1 | R32C39 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_1_1_s |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 8 |
Arrival Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Arrival Data Path Delay | cell: 3.488, 47.991%; route: 3.548, 48.817%; tC2Q: 0.232, 3.192% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path13
Path Summary:
Slack | 2.746 |
Data Arrival Time | 8.145 |
Data Required Time | 10.891 |
From | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_Div_Lamda_vo_4_s0 |
To | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_1_0_s |
Launch Clk | SYM_CLK:[R] |
Latch Clk | SYM_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.926 | 0.243 | tNET | RR | 1 | R46C37[0][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_Div_Lamda_vo_4_s0/CLK |
1.158 | 0.232 | tC2Q | RF | 8 | R46C37[0][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_Div_Lamda_vo_4_s0/Q |
2.013 | 0.855 | tNET | FF | 1 | R40C36[3][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s16/I1 |
2.562 | 0.549 | tINS | FR | 3 | R40C36[3][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s16/F |
2.737 | 0.175 | tNET | RR | 1 | R40C37[1][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s11/I3 |
3.254 | 0.517 | tINS | RF | 7 | R40C37[1][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s11/F |
3.928 | 0.674 | tNET | FF | 1 | R39C40[0][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_0_s19/I0 |
4.299 | 0.371 | tINS | FF | 11 | R39C40[0][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_0_s19/F |
4.731 | 0.432 | tNET | FF | 1 | R39C39[2][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_6_s6/I0 |
5.193 | 0.462 | tINS | FR | 1 | R39C39[2][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_6_s6/F |
5.194 | 0.001 | tNET | RR | 1 | R39C39[3][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_6_s2/I3 |
5.711 | 0.517 | tINS | RF | 3 | R39C39[3][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_6_s2/F |
6.376 | 0.665 | tNET | FF | 1 | R37C36[2][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_2_s2/I2 |
6.946 | 0.570 | tINS | FR | 1 | R37C36[2][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_2_s2/F |
7.090 | 0.144 | tNET | RR | 1 | R37C36[2][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_2_s1/I1 |
7.461 | 0.371 | tINS | RF | 2 | R37C36[2][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_2_s1/F |
8.145 | 0.684 | tNET | FF | 1 | R32C38 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_1_0_s/DI[2] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | SYM_CLK | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
10.926 | 0.243 | tNET | RR | 1 | R32C38 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_1_0_s/CLK |
10.891 | -0.035 | tSu | 1 | R32C38 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_1_0_s |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 8 |
Arrival Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Arrival Data Path Delay | cell: 3.357, 46.499%; route: 3.631, 50.288%; tC2Q: 0.232, 3.213% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path14
Path Summary:
Slack | 2.746 |
Data Arrival Time | 8.145 |
Data Required Time | 10.891 |
From | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_Div_Lamda_vo_4_s0 |
To | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_0_0_s |
Launch Clk | SYM_CLK:[R] |
Latch Clk | SYM_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.926 | 0.243 | tNET | RR | 1 | R46C37[0][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_Div_Lamda_vo_4_s0/CLK |
1.158 | 0.232 | tC2Q | RF | 8 | R46C37[0][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_Div_Lamda_vo_4_s0/Q |
2.013 | 0.855 | tNET | FF | 1 | R40C36[3][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s16/I1 |
2.562 | 0.549 | tINS | FR | 3 | R40C36[3][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s16/F |
2.737 | 0.175 | tNET | RR | 1 | R40C37[1][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s11/I3 |
3.254 | 0.517 | tINS | RF | 7 | R40C37[1][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s11/F |
3.928 | 0.674 | tNET | FF | 1 | R39C40[0][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_0_s19/I0 |
4.299 | 0.371 | tINS | FF | 11 | R39C40[0][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_0_s19/F |
4.731 | 0.432 | tNET | FF | 1 | R39C39[2][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_6_s6/I0 |
5.193 | 0.462 | tINS | FR | 1 | R39C39[2][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_6_s6/F |
5.194 | 0.001 | tNET | RR | 1 | R39C39[3][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_6_s2/I3 |
5.711 | 0.517 | tINS | RF | 3 | R39C39[3][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_6_s2/F |
6.376 | 0.665 | tNET | FF | 1 | R37C36[2][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_2_s2/I2 |
6.946 | 0.570 | tINS | FR | 1 | R37C36[2][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_2_s2/F |
7.090 | 0.144 | tNET | RR | 1 | R37C36[2][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_2_s1/I1 |
7.461 | 0.371 | tINS | RF | 2 | R37C36[2][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_2_s1/F |
8.145 | 0.684 | tNET | FF | 1 | R32C37 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_0_0_s/DI[2] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | SYM_CLK | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
10.926 | 0.243 | tNET | RR | 1 | R32C37 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_0_0_s/CLK |
10.891 | -0.035 | tSu | 1 | R32C37 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_0_0_s |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 8 |
Arrival Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Arrival Data Path Delay | cell: 3.357, 46.499%; route: 3.631, 50.288%; tC2Q: 0.232, 3.213% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path15
Path Summary:
Slack | 3.109 |
Data Arrival Time | 7.782 |
Data Required Time | 10.891 |
From | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/delta_7_s3 |
To | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/lamda_shift_12_s1 |
Launch Clk | SYM_CLK:[R] |
Latch Clk | SYM_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.926 | 0.243 | tNET | RR | 1 | R49C50[0][B] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/delta_7_s3/CLK |
1.158 | 0.232 | tC2Q | RF | 21 | R49C50[0][B] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/delta_7_s3/Q |
1.981 | 0.823 | tNET | FF | 1 | R43C54[3][B] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_Z_2_s2/I1 |
2.434 | 0.453 | tINS | FF | 2 | R43C54[3][B] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_Z_2_s2/F |
3.001 | 0.567 | tNET | FF | 1 | R40C54[2][A] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_Z_10_s3/I1 |
3.550 | 0.549 | tINS | FR | 1 | R40C54[2][A] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_Z_10_s3/F |
3.552 | 0.001 | tNET | RR | 1 | R40C54[2][B] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_Z_10_s0/I3 |
4.005 | 0.453 | tINS | RF | 4 | R40C54[2][B] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_Z_10_s0/F |
5.123 | 1.118 | tNET | FF | 1 | R46C47[3][B] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_Z_12_s0/I3 |
5.678 | 0.555 | tINS | FF | 2 | R46C47[3][B] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_Z_12_s0/F |
6.340 | 0.662 | tNET | FF | 1 | R46C48[3][A] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_Z_12_s/I1 |
6.711 | 0.371 | tINS | FF | 2 | R46C48[3][A] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_Z_12_s/F |
7.233 | 0.522 | tNET | FF | 1 | R42C46[2][A] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/n855_s3/I0 |
7.782 | 0.549 | tINS | FR | 1 | R42C46[2][A] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/n855_s3/F |
7.782 | 0.000 | tNET | RR | 1 | R42C46[2][A] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/lamda_shift_12_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | SYM_CLK | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
10.926 | 0.243 | tNET | RR | 1 | R42C46[2][A] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/lamda_shift_12_s1/CLK |
10.891 | -0.035 | tSu | 1 | R42C46[2][A] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/lamda_shift_12_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Arrival Data Path Delay | cell: 2.930, 42.735%; route: 3.694, 53.881%; tC2Q: 0.232, 3.384% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path16
Path Summary:
Slack | 3.137 |
Data Arrival Time | 7.754 |
Data Required Time | 10.891 |
From | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/delta_7_s3 |
To | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Lamda_shift_12_s0 |
Launch Clk | SYM_CLK:[R] |
Latch Clk | SYM_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.926 | 0.243 | tNET | RR | 1 | R49C50[0][B] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/delta_7_s3/CLK |
1.158 | 0.232 | tC2Q | RF | 21 | R49C50[0][B] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/delta_7_s3/Q |
1.981 | 0.823 | tNET | FF | 1 | R43C54[3][B] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_Z_2_s2/I1 |
2.434 | 0.453 | tINS | FF | 2 | R43C54[3][B] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_Z_2_s2/F |
3.001 | 0.567 | tNET | FF | 1 | R40C54[2][A] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_Z_10_s3/I1 |
3.550 | 0.549 | tINS | FR | 1 | R40C54[2][A] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_Z_10_s3/F |
3.552 | 0.001 | tNET | RR | 1 | R40C54[2][B] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_Z_10_s0/I3 |
4.005 | 0.453 | tINS | RF | 4 | R40C54[2][B] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_Z_10_s0/F |
5.123 | 1.118 | tNET | FF | 1 | R46C47[3][B] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_Z_12_s0/I3 |
5.678 | 0.555 | tINS | FF | 2 | R46C47[3][B] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_Z_12_s0/F |
6.340 | 0.662 | tNET | FF | 1 | R46C48[3][A] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_Z_12_s/I1 |
6.711 | 0.371 | tINS | FF | 2 | R46C48[3][A] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_Z_12_s/F |
7.754 | 1.043 | tNET | FF | 1 | R46C41[0][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Lamda_shift_12_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | SYM_CLK | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
10.926 | 0.243 | tNET | RR | 1 | R46C41[0][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Lamda_shift_12_s0/CLK |
10.891 | -0.035 | tSu | 1 | R46C41[0][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Lamda_shift_12_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Arrival Data Path Delay | cell: 2.381, 34.871%; route: 4.215, 61.731%; tC2Q: 0.232, 3.398% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path17
Path Summary:
Slack | 3.197 |
Data Arrival Time | 7.694 |
Data Required Time | 10.891 |
From | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/delta_7_s3 |
To | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_reg_12_s3 |
Launch Clk | SYM_CLK:[R] |
Latch Clk | SYM_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.926 | 0.243 | tNET | RR | 1 | R49C50[0][B] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/delta_7_s3/CLK |
1.158 | 0.232 | tC2Q | RF | 21 | R49C50[0][B] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/delta_7_s3/Q |
1.981 | 0.823 | tNET | FF | 1 | R43C54[3][B] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_Z_2_s2/I1 |
2.434 | 0.453 | tINS | FF | 2 | R43C54[3][B] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_Z_2_s2/F |
3.001 | 0.567 | tNET | FF | 1 | R40C54[2][A] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_Z_10_s3/I1 |
3.550 | 0.549 | tINS | FR | 1 | R40C54[2][A] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_Z_10_s3/F |
3.552 | 0.001 | tNET | RR | 1 | R40C54[2][B] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_Z_10_s0/I3 |
4.005 | 0.453 | tINS | RF | 4 | R40C54[2][B] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_Z_10_s0/F |
5.123 | 1.118 | tNET | FF | 1 | R46C47[3][B] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_Z_12_s0/I3 |
5.678 | 0.555 | tINS | FF | 2 | R46C47[3][B] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_Z_12_s0/F |
6.340 | 0.662 | tNET | FF | 1 | R46C48[3][B] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/n732_s6/I2 |
6.711 | 0.371 | tINS | FF | 1 | R46C48[3][B] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/n732_s6/F |
7.124 | 0.413 | tNET | FF | 1 | R46C46[0][A] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/n732_s7/I2 |
7.694 | 0.570 | tINS | FR | 1 | R46C46[0][A] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/n732_s7/F |
7.694 | 0.000 | tNET | RR | 1 | R46C46[0][A] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_reg_12_s3/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | SYM_CLK | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
10.926 | 0.243 | tNET | RR | 1 | R46C46[0][A] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_reg_12_s3/CLK |
10.891 | -0.035 | tSu | 1 | R46C46[0][A] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_reg_12_s3 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Arrival Data Path Delay | cell: 2.951, 43.602%; route: 3.585, 52.970%; tC2Q: 0.232, 3.428% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path18
Path Summary:
Slack | 3.256 |
Data Arrival Time | 7.635 |
Data Required Time | 10.891 |
From | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Caculate_lamda_ov_test/tmpC_7_s0 |
To | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_Div_Lamda_vo_0_s0 |
Launch Clk | SYM_CLK:[R] |
Latch Clk | SYM_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.926 | 0.243 | tNET | RR | 1 | R46C40[2][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Caculate_lamda_ov_test/tmpC_7_s0/CLK |
1.158 | 0.232 | tC2Q | RF | 111 | R46C40[2][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Caculate_lamda_ov_test/tmpC_7_s0/Q |
2.427 | 1.269 | tNET | FF | 1 | R46C36[3][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/n727_s3973/I0 |
2.880 | 0.453 | tINS | FF | 4 | R46C36[3][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/n727_s3973/F |
3.312 | 0.432 | tNET | FF | 1 | R47C34[0][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/n727_s3971/I3 |
3.867 | 0.555 | tINS | FF | 3 | R47C34[0][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/n727_s3971/F |
4.528 | 0.660 | tNET | FF | 1 | R46C37[3][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/n727_s4035/I3 |
4.981 | 0.453 | tINS | FF | 1 | R46C37[3][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/n727_s4035/F |
4.981 | 0.000 | tNET | FF | 1 | R46C37[3][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/n727_s3622/I1 |
5.084 | 0.103 | tINS | FF | 1 | R46C37[3][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/n727_s3622/O |
5.988 | 0.904 | tNET | FF | 1 | R46C37[2][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/n727_s3958/I1 |
6.537 | 0.549 | tINS | FR | 1 | R46C37[2][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/n727_s3958/F |
6.538 | 0.001 | tNET | RR | 1 | R46C37[2][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/n727_s3946/I1 |
7.000 | 0.462 | tINS | RR | 1 | R46C37[2][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/n727_s3946/F |
7.173 | 0.172 | tNET | RR | 1 | R46C36[2][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/n735_s2/I1 |
7.635 | 0.462 | tINS | RR | 1 | R46C36[2][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/n735_s2/F |
7.635 | 0.000 | tNET | RR | 1 | R46C36[2][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_Div_Lamda_vo_0_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | SYM_CLK | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
10.926 | 0.243 | tNET | RR | 1 | R46C36[2][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_Div_Lamda_vo_0_s0/CLK |
10.891 | -0.035 | tSu | 1 | R46C36[2][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_Div_Lamda_vo_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Arrival Data Path Delay | cell: 3.037, 45.267%; route: 3.440, 51.275%; tC2Q: 0.232, 3.458% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path19
Path Summary:
Slack | 3.619 |
Data Arrival Time | 7.273 |
Data Required Time | 10.891 |
From | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_d_3_s0 |
To | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_1_0_s |
Launch Clk | SYM_CLK:[R] |
Latch Clk | SYM_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.926 | 0.243 | tNET | RR | 1 | R44C36[2][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_d_3_s0/CLK |
1.158 | 0.232 | tC2Q | RF | 8 | R44C36[2][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_d_3_s0/Q |
1.859 | 0.701 | tNET | FF | 1 | R39C35[0][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s19/I1 |
2.414 | 0.555 | tINS | FF | 1 | R39C35[0][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s19/F |
2.827 | 0.413 | tNET | FF | 1 | R38C36[2][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s12/I2 |
3.382 | 0.555 | tINS | FF | 4 | R38C36[2][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s12/F |
4.052 | 0.670 | tNET | FF | 1 | R39C39[0][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_1_s15/I2 |
4.622 | 0.570 | tINS | FR | 3 | R39C39[0][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_1_s15/F |
4.799 | 0.177 | tNET | RR | 1 | R39C38[1][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_1_s7/I3 |
5.252 | 0.453 | tINS | RF | 1 | R39C38[1][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_1_s7/F |
5.407 | 0.154 | tNET | FF | 1 | R39C38[3][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_1_s2/I3 |
5.778 | 0.371 | tINS | FF | 3 | R39C38[3][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_1_s2/F |
6.029 | 0.252 | tNET | FF | 1 | R37C38[3][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_1_s1/I0 |
6.584 | 0.555 | tINS | FF | 2 | R37C38[3][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_1_s1/F |
7.273 | 0.688 | tNET | FF | 1 | R32C38 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_1_0_s/DI[1] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | SYM_CLK | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
10.926 | 0.243 | tNET | RR | 1 | R32C38 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_1_0_s/CLK |
10.891 | -0.035 | tSu | 1 | R32C38 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_1_0_s |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Arrival Data Path Delay | cell: 3.059, 48.198%; route: 3.056, 48.146%; tC2Q: 0.232, 3.655% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path20
Path Summary:
Slack | 3.619 |
Data Arrival Time | 7.273 |
Data Required Time | 10.891 |
From | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_d_3_s0 |
To | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_0_0_s |
Launch Clk | SYM_CLK:[R] |
Latch Clk | SYM_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.926 | 0.243 | tNET | RR | 1 | R44C36[2][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_d_3_s0/CLK |
1.158 | 0.232 | tC2Q | RF | 8 | R44C36[2][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_d_3_s0/Q |
1.859 | 0.701 | tNET | FF | 1 | R39C35[0][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s19/I1 |
2.414 | 0.555 | tINS | FF | 1 | R39C35[0][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s19/F |
2.827 | 0.413 | tNET | FF | 1 | R38C36[2][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s12/I2 |
3.382 | 0.555 | tINS | FF | 4 | R38C36[2][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s12/F |
4.052 | 0.670 | tNET | FF | 1 | R39C39[0][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_1_s15/I2 |
4.622 | 0.570 | tINS | FR | 3 | R39C39[0][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_1_s15/F |
4.799 | 0.177 | tNET | RR | 1 | R39C38[1][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_1_s7/I3 |
5.252 | 0.453 | tINS | RF | 1 | R39C38[1][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_1_s7/F |
5.407 | 0.154 | tNET | FF | 1 | R39C38[3][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_1_s2/I3 |
5.778 | 0.371 | tINS | FF | 3 | R39C38[3][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_1_s2/F |
6.029 | 0.252 | tNET | FF | 1 | R37C38[3][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_1_s1/I0 |
6.584 | 0.555 | tINS | FF | 2 | R37C38[3][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_1_s1/F |
7.273 | 0.688 | tNET | FF | 1 | R32C37 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_0_0_s/DI[1] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | SYM_CLK | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
10.926 | 0.243 | tNET | RR | 1 | R32C37 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_0_0_s/CLK |
10.891 | -0.035 | tSu | 1 | R32C37 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_0_0_s |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Arrival Data Path Delay | cell: 3.059, 48.198%; route: 3.056, 48.146%; tC2Q: 0.232, 3.655% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path21
Path Summary:
Slack | 3.645 |
Data Arrival Time | 7.246 |
Data Required Time | 10.891 |
From | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/delta_7_s3 |
To | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/lamda_shift_14_s1 |
Launch Clk | SYM_CLK:[R] |
Latch Clk | SYM_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.926 | 0.243 | tNET | RR | 1 | R49C50[0][B] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/delta_7_s3/CLK |
1.158 | 0.232 | tC2Q | RF | 21 | R49C50[0][B] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/delta_7_s3/Q |
1.981 | 0.823 | tNET | FF | 1 | R43C54[3][B] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_Z_2_s2/I1 |
2.434 | 0.453 | tINS | FF | 2 | R43C54[3][B] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_Z_2_s2/F |
3.001 | 0.567 | tNET | FF | 1 | R40C54[2][A] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_Z_10_s3/I1 |
3.550 | 0.549 | tINS | FR | 1 | R40C54[2][A] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_Z_10_s3/F |
3.552 | 0.001 | tNET | RR | 1 | R40C54[2][B] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_Z_10_s0/I3 |
4.005 | 0.453 | tINS | RF | 4 | R40C54[2][B] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_Z_10_s0/F |
4.018 | 0.013 | tNET | FF | 1 | R40C54[3][A] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_Z_13_s5/I0 |
4.535 | 0.517 | tINS | FF | 2 | R40C54[3][A] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_Z_13_s5/F |
5.495 | 0.960 | tNET | FF | 1 | R50C49[3][A] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_Z_14_s/I2 |
6.012 | 0.517 | tINS | FF | 3 | R50C49[3][A] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_Z_14_s/F |
6.875 | 0.864 | tNET | FF | 1 | R41C46[1][A] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/n853_s3/I0 |
7.246 | 0.371 | tINS | FF | 1 | R41C46[1][A] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/n853_s3/F |
7.246 | 0.000 | tNET | FF | 1 | R41C46[1][A] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/lamda_shift_14_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | SYM_CLK | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
10.926 | 0.243 | tNET | RR | 1 | R41C46[1][A] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/lamda_shift_14_s1/CLK |
10.891 | -0.035 | tSu | 1 | R41C46[1][A] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/lamda_shift_14_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Arrival Data Path Delay | cell: 2.860, 45.251%; route: 3.228, 51.078%; tC2Q: 0.232, 3.671% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path22
Path Summary:
Slack | 3.654 |
Data Arrival Time | 7.237 |
Data Required Time | 10.891 |
From | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/delta_7_s3 |
To | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Lamda_shift_14_s0 |
Launch Clk | SYM_CLK:[R] |
Latch Clk | SYM_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.926 | 0.243 | tNET | RR | 1 | R49C50[0][B] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/delta_7_s3/CLK |
1.158 | 0.232 | tC2Q | RF | 21 | R49C50[0][B] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/delta_7_s3/Q |
1.981 | 0.823 | tNET | FF | 1 | R43C54[3][B] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_Z_2_s2/I1 |
2.434 | 0.453 | tINS | FF | 2 | R43C54[3][B] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_Z_2_s2/F |
3.001 | 0.567 | tNET | FF | 1 | R40C54[2][A] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_Z_10_s3/I1 |
3.550 | 0.549 | tINS | FR | 1 | R40C54[2][A] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_Z_10_s3/F |
3.552 | 0.001 | tNET | RR | 1 | R40C54[2][B] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_Z_10_s0/I3 |
4.005 | 0.453 | tINS | RF | 4 | R40C54[2][B] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_Z_10_s0/F |
4.018 | 0.013 | tNET | FF | 1 | R40C54[3][A] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_Z_13_s5/I0 |
4.535 | 0.517 | tINS | FF | 2 | R40C54[3][A] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_Z_13_s5/F |
5.495 | 0.960 | tNET | FF | 1 | R50C49[3][A] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_Z_14_s/I2 |
6.012 | 0.517 | tINS | FF | 3 | R50C49[3][A] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_Z_14_s/F |
7.237 | 1.225 | tNET | FF | 1 | R47C42[0][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Lamda_shift_14_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | SYM_CLK | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
10.926 | 0.243 | tNET | RR | 1 | R47C42[0][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Lamda_shift_14_s0/CLK |
10.891 | -0.035 | tSu | 1 | R47C42[0][B] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Lamda_shift_14_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Arrival Data Path Delay | cell: 2.489, 39.438%; route: 3.590, 56.886%; tC2Q: 0.232, 3.676% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path23
Path Summary:
Slack | 3.822 |
Data Arrival Time | 7.069 |
Data Required Time | 10.891 |
From | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/delta_7_s3 |
To | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Lamda_shift_13_s0 |
Launch Clk | SYM_CLK:[R] |
Latch Clk | SYM_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.926 | 0.243 | tNET | RR | 1 | R49C50[0][B] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/delta_7_s3/CLK |
1.158 | 0.232 | tC2Q | RF | 21 | R49C50[0][B] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/delta_7_s3/Q |
1.981 | 0.823 | tNET | FF | 1 | R43C54[3][B] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_Z_2_s2/I1 |
2.434 | 0.453 | tINS | FF | 2 | R43C54[3][B] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_Z_2_s2/F |
3.001 | 0.567 | tNET | FF | 1 | R40C54[2][A] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_Z_10_s3/I1 |
3.550 | 0.549 | tINS | FR | 1 | R40C54[2][A] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_Z_10_s3/F |
3.552 | 0.001 | tNET | RR | 1 | R40C54[2][B] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_Z_10_s0/I3 |
4.005 | 0.453 | tINS | RF | 4 | R40C54[2][B] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_Z_10_s0/F |
4.018 | 0.013 | tNET | FF | 1 | R40C54[3][A] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_Z_13_s5/I0 |
4.535 | 0.517 | tINS | FF | 2 | R40C54[3][A] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_Z_13_s5/F |
5.374 | 0.839 | tNET | FF | 1 | R46C53[0][A] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_Z_13_s/I3 |
5.929 | 0.555 | tINS | FF | 3 | R46C53[0][A] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_Z_13_s/F |
7.069 | 1.141 | tNET | FF | 1 | R46C41[1][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Lamda_shift_13_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | SYM_CLK | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
10.926 | 0.243 | tNET | RR | 1 | R46C41[1][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Lamda_shift_13_s0/CLK |
10.891 | -0.035 | tSu | 1 | R46C41[1][A] | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Lamda_shift_13_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Arrival Data Path Delay | cell: 2.527, 41.135%; route: 3.384, 55.089%; tC2Q: 0.232, 3.777% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path24
Path Summary:
Slack | 3.849 |
Data Arrival Time | 7.042 |
Data Required Time | 10.891 |
From | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/delta_5_s3 |
To | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/lamda_shift_15_s1 |
Launch Clk | SYM_CLK:[R] |
Latch Clk | SYM_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.926 | 0.243 | tNET | RR | 1 | R50C51[1][A] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/delta_5_s3/CLK |
1.158 | 0.232 | tC2Q | RF | 17 | R50C51[1][A] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/delta_5_s3/Q |
2.131 | 0.973 | tNET | FF | 1 | R40C54[1][B] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_Z_11_s5/I0 |
2.701 | 0.570 | tINS | FR | 2 | R40C54[1][B] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_Z_11_s5/F |
2.851 | 0.150 | tNET | RR | 1 | R40C54[1][A] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_Z_11_s2/I1 |
3.222 | 0.371 | tINS | RF | 2 | R40C54[1][A] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_Z_11_s2/F |
3.911 | 0.688 | tNET | FF | 1 | R46C53[2][B] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_Z_15_s2/I3 |
4.466 | 0.555 | tINS | FF | 1 | R46C53[2][B] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_Z_15_s2/F |
5.254 | 0.789 | tNET | FF | 1 | R50C48[3][A] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_Z_15_s/I3 |
5.707 | 0.453 | tINS | FF | 3 | R50C48[3][A] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_Z_15_s/F |
6.671 | 0.964 | tNET | FF | 1 | R39C46[2][B] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/n852_s3/I0 |
7.042 | 0.371 | tINS | FF | 1 | R39C46[2][B] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/n852_s3/F |
7.042 | 0.000 | tNET | FF | 1 | R39C46[2][B] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/lamda_shift_15_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | SYM_CLK | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
10.926 | 0.243 | tNET | RR | 1 | R39C46[2][B] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/lamda_shift_15_s1/CLK |
10.891 | -0.035 | tSu | 1 | R39C46[2][B] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/lamda_shift_15_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Arrival Data Path Delay | cell: 2.320, 37.931%; route: 3.564, 58.276%; tC2Q: 0.232, 3.793% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Path25
Path Summary:
Slack | 3.870 |
Data Arrival Time | 7.021 |
Data Required Time | 10.891 |
From | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/delta_7_s3 |
To | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/lamda_shift_13_s1 |
Launch Clk | SYM_CLK:[R] |
Latch Clk | SYM_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.926 | 0.243 | tNET | RR | 1 | R49C50[0][B] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/delta_7_s3/CLK |
1.158 | 0.232 | tC2Q | RF | 21 | R49C50[0][B] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/delta_7_s3/Q |
1.981 | 0.823 | tNET | FF | 1 | R43C54[3][B] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_Z_2_s2/I1 |
2.434 | 0.453 | tINS | FF | 2 | R43C54[3][B] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_Z_2_s2/F |
3.001 | 0.567 | tNET | FF | 1 | R40C54[2][A] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_Z_10_s3/I1 |
3.550 | 0.549 | tINS | FR | 1 | R40C54[2][A] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_Z_10_s3/F |
3.552 | 0.001 | tNET | RR | 1 | R40C54[2][B] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_Z_10_s0/I3 |
4.005 | 0.453 | tINS | RF | 4 | R40C54[2][B] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_Z_10_s0/F |
4.018 | 0.013 | tNET | FF | 1 | R40C54[3][A] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_Z_13_s5/I0 |
4.535 | 0.517 | tINS | FF | 2 | R40C54[3][A] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_Z_13_s5/F |
5.374 | 0.839 | tNET | FF | 1 | R46C53[0][A] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_Z_13_s/I3 |
5.929 | 0.555 | tINS | FF | 3 | R46C53[0][A] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_Z_13_s/F |
6.650 | 0.721 | tNET | FF | 1 | R42C46[1][B] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/n854_s3/I0 |
7.021 | 0.371 | tINS | FF | 1 | R42C46[1][B] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/n854_s3/F |
7.021 | 0.000 | tNET | FF | 1 | R42C46[1][B] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/lamda_shift_13_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | SYM_CLK | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
10.926 | 0.243 | tNET | RR | 1 | R42C46[1][B] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/lamda_shift_13_s1/CLK |
10.891 | -0.035 | tSu | 1 | R42C46[1][B] | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/lamda_shift_13_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Arrival Data Path Delay | cell: 2.898, 47.550%; route: 2.965, 48.644%; tC2Q: 0.232, 3.807% |
Required Clock Path Delay | cell: 0.683, 73.717%; route: 0.243, 26.283% |
Hold Analysis Report
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 0.213 |
Data Arrival Time | 1.138 |
Data Required Time | 0.924 |
From | u_la0_top/u_ao_mem_ctrl/data_reg_46_s0 |
To | u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s |
Launch Clk | SYM_CLK:[R] |
Latch Clk | SYM_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.675 | 0.675 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | R11C8[2][B] | u_la0_top/u_ao_mem_ctrl/data_reg_46_s0/CLK |
0.877 | 0.202 | tC2Q | RR | 1 | R11C8[2][B] | u_la0_top/u_ao_mem_ctrl/data_reg_46_s0/Q |
1.138 | 0.260 | tNET | RR | 1 | BSRAM_R10[0] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[10] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.675 | 0.675 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | BSRAM_R10[0] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA |
0.924 | 0.249 | tHld | 1 | BSRAM_R10[0] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 100.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686% |
Required Clock Path Delay | cell: 0.675, 100.000%; route: 0.000, 0.000% |
Path2
Path Summary:
Slack | 0.225 |
Data Arrival Time | 1.150 |
Data Required Time | 0.924 |
From | u_la0_top/u_ao_mem_ctrl/data_reg_44_s0 |
To | u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s |
Launch Clk | SYM_CLK:[R] |
Latch Clk | SYM_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.675 | 0.675 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | R6C6[0][B] | u_la0_top/u_ao_mem_ctrl/data_reg_44_s0/CLK |
0.877 | 0.202 | tC2Q | RR | 1 | R6C6[0][B] | u_la0_top/u_ao_mem_ctrl/data_reg_44_s0/Q |
1.150 | 0.272 | tNET | RR | 1 | BSRAM_R10[0] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[8] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.675 | 0.675 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | BSRAM_R10[0] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA |
0.924 | 0.249 | tHld | 1 | BSRAM_R10[0] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 100.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.272, 57.427%; tC2Q: 0.202, 42.573% |
Required Clock Path Delay | cell: 0.675, 100.000%; route: 0.000, 0.000% |
Path3
Path Summary:
Slack | 0.225 |
Data Arrival Time | 1.150 |
Data Required Time | 0.924 |
From | u_la0_top/u_ao_mem_ctrl/data_reg_43_s0 |
To | u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s |
Launch Clk | SYM_CLK:[R] |
Latch Clk | SYM_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.675 | 0.675 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | R6C6[0][A] | u_la0_top/u_ao_mem_ctrl/data_reg_43_s0/CLK |
0.877 | 0.202 | tC2Q | RR | 1 | R6C6[0][A] | u_la0_top/u_ao_mem_ctrl/data_reg_43_s0/Q |
1.150 | 0.272 | tNET | RR | 1 | BSRAM_R10[0] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[7] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.675 | 0.675 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | BSRAM_R10[0] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA |
0.924 | 0.249 | tHld | 1 | BSRAM_R10[0] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 100.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.272, 57.427%; tC2Q: 0.202, 42.573% |
Required Clock Path Delay | cell: 0.675, 100.000%; route: 0.000, 0.000% |
Path4
Path Summary:
Slack | 0.225 |
Data Arrival Time | 1.150 |
Data Required Time | 0.924 |
From | u_la0_top/u_ao_mem_ctrl/data_reg_40_s0 |
To | u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s |
Launch Clk | SYM_CLK:[R] |
Latch Clk | SYM_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.675 | 0.675 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | R6C7[1][B] | u_la0_top/u_ao_mem_ctrl/data_reg_40_s0/CLK |
0.877 | 0.202 | tC2Q | RR | 1 | R6C7[1][B] | u_la0_top/u_ao_mem_ctrl/data_reg_40_s0/Q |
1.150 | 0.272 | tNET | RR | 1 | BSRAM_R10[0] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[4] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.675 | 0.675 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | BSRAM_R10[0] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA |
0.924 | 0.249 | tHld | 1 | BSRAM_R10[0] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 100.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.272, 57.427%; tC2Q: 0.202, 42.573% |
Required Clock Path Delay | cell: 0.675, 100.000%; route: 0.000, 0.000% |
Path5
Path Summary:
Slack | 0.225 |
Data Arrival Time | 1.150 |
Data Required Time | 0.924 |
From | u_la0_top/u_ao_mem_ctrl/data_reg_39_s0 |
To | u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s |
Launch Clk | SYM_CLK:[R] |
Latch Clk | SYM_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.675 | 0.675 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | R6C7[1][A] | u_la0_top/u_ao_mem_ctrl/data_reg_39_s0/CLK |
0.877 | 0.202 | tC2Q | RR | 1 | R6C7[1][A] | u_la0_top/u_ao_mem_ctrl/data_reg_39_s0/Q |
1.150 | 0.272 | tNET | RR | 1 | BSRAM_R10[0] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[3] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.675 | 0.675 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | BSRAM_R10[0] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA |
0.924 | 0.249 | tHld | 1 | BSRAM_R10[0] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 100.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.272, 57.427%; tC2Q: 0.202, 42.573% |
Required Clock Path Delay | cell: 0.675, 100.000%; route: 0.000, 0.000% |
Path6
Path Summary:
Slack | 0.307 |
Data Arrival Time | 2.234 |
Data Required Time | 1.927 |
From | u_la0_top/data_register_17_s0 |
To | u_la0_top/data_register_16_s0 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | tck_pad_i:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | tck_ibuf/I | |
0.675 | 0.675 | tINS | RR | 1 | tck_ibuf/O | |
0.675 | 0.000 | tNET | RR | 1 | u_gw_jtag/tck_pad_i | |
1.351 | 0.675 | tINS | RR | 275 | u_gw_jtag/tck_o | |
1.916 | 0.565 | tNET | RR | 1 | u_la0_top/data_register_17_s0/CLK | |
2.117 | 0.201 | tC2Q | RF | 1 | u_la0_top/data_register_17_s0/Q | |
2.234 | 0.117 | tNET | FF | 1 | u_la0_top/data_register_16_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | tck_ibuf/I | |
0.675 | 0.675 | tINS | RR | 1 | tck_ibuf/O | |
0.675 | 0.000 | tNET | RR | 1 | u_gw_jtag/tck_pad_i | |
1.351 | 0.675 | tINS | RR | 275 | u_gw_jtag/tck_o | |
1.916 | 0.565 | tNET | RR | 1 | u_la0_top/data_register_16_s0/CLK | |
1.927 | 0.011 | tHld | 1 | u_la0_top/data_register_16_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 1.351, 70.497%; route: 0.565, 29.503% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.117, 36.787%; tC2Q: 0.201, 63.213% |
Required Clock Path Delay | cell: 1.351, 70.497%; route: 0.565, 29.503% |
Path7
Path Summary:
Slack | 0.307 |
Data Arrival Time | 2.234 |
Data Required Time | 1.927 |
From | u_la0_top/data_register_18_s0 |
To | u_la0_top/data_register_17_s0 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | tck_pad_i:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | tck_ibuf/I | |
0.675 | 0.675 | tINS | RR | 1 | tck_ibuf/O | |
0.675 | 0.000 | tNET | RR | 1 | u_gw_jtag/tck_pad_i | |
1.351 | 0.675 | tINS | RR | 275 | u_gw_jtag/tck_o | |
1.916 | 0.565 | tNET | RR | 1 | u_la0_top/data_register_18_s0/CLK | |
2.117 | 0.201 | tC2Q | RF | 1 | u_la0_top/data_register_18_s0/Q | |
2.234 | 0.117 | tNET | FF | 1 | u_la0_top/data_register_17_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | tck_ibuf/I | |
0.675 | 0.675 | tINS | RR | 1 | tck_ibuf/O | |
0.675 | 0.000 | tNET | RR | 1 | u_gw_jtag/tck_pad_i | |
1.351 | 0.675 | tINS | RR | 275 | u_gw_jtag/tck_o | |
1.916 | 0.565 | tNET | RR | 1 | u_la0_top/data_register_17_s0/CLK | |
1.927 | 0.011 | tHld | 1 | u_la0_top/data_register_17_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 1.351, 70.497%; route: 0.565, 29.503% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.117, 36.787%; tC2Q: 0.201, 63.213% |
Required Clock Path Delay | cell: 1.351, 70.497%; route: 0.565, 29.503% |
Path8
Path Summary:
Slack | 0.307 |
Data Arrival Time | 2.234 |
Data Required Time | 1.927 |
From | u_la0_top/data_register_22_s0 |
To | u_la0_top/data_register_21_s0 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | tck_pad_i:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | tck_ibuf/I | |
0.675 | 0.675 | tINS | RR | 1 | tck_ibuf/O | |
0.675 | 0.000 | tNET | RR | 1 | u_gw_jtag/tck_pad_i | |
1.351 | 0.675 | tINS | RR | 275 | u_gw_jtag/tck_o | |
1.916 | 0.565 | tNET | RR | 1 | u_la0_top/data_register_22_s0/CLK | |
2.117 | 0.201 | tC2Q | RF | 1 | u_la0_top/data_register_22_s0/Q | |
2.234 | 0.117 | tNET | FF | 1 | u_la0_top/data_register_21_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | tck_ibuf/I | |
0.675 | 0.675 | tINS | RR | 1 | tck_ibuf/O | |
0.675 | 0.000 | tNET | RR | 1 | u_gw_jtag/tck_pad_i | |
1.351 | 0.675 | tINS | RR | 275 | u_gw_jtag/tck_o | |
1.916 | 0.565 | tNET | RR | 1 | u_la0_top/data_register_21_s0/CLK | |
1.927 | 0.011 | tHld | 1 | u_la0_top/data_register_21_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 1.351, 70.497%; route: 0.565, 29.503% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.117, 36.787%; tC2Q: 0.201, 63.213% |
Required Clock Path Delay | cell: 1.351, 70.497%; route: 0.565, 29.503% |
Path9
Path Summary:
Slack | 0.307 |
Data Arrival Time | 2.234 |
Data Required Time | 1.927 |
From | u_la0_top/data_register_24_s0 |
To | u_la0_top/data_register_23_s0 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | tck_pad_i:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | tck_ibuf/I | |
0.675 | 0.675 | tINS | RR | 1 | tck_ibuf/O | |
0.675 | 0.000 | tNET | RR | 1 | u_gw_jtag/tck_pad_i | |
1.351 | 0.675 | tINS | RR | 275 | u_gw_jtag/tck_o | |
1.916 | 0.565 | tNET | RR | 1 | u_la0_top/data_register_24_s0/CLK | |
2.117 | 0.201 | tC2Q | RF | 1 | u_la0_top/data_register_24_s0/Q | |
2.234 | 0.117 | tNET | FF | 1 | u_la0_top/data_register_23_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | tck_ibuf/I | |
0.675 | 0.675 | tINS | RR | 1 | tck_ibuf/O | |
0.675 | 0.000 | tNET | RR | 1 | u_gw_jtag/tck_pad_i | |
1.351 | 0.675 | tINS | RR | 275 | u_gw_jtag/tck_o | |
1.916 | 0.565 | tNET | RR | 1 | u_la0_top/data_register_23_s0/CLK | |
1.927 | 0.011 | tHld | 1 | u_la0_top/data_register_23_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 1.351, 70.497%; route: 0.565, 29.503% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.117, 36.787%; tC2Q: 0.201, 63.213% |
Required Clock Path Delay | cell: 1.351, 70.497%; route: 0.565, 29.503% |
Path10
Path Summary:
Slack | 0.307 |
Data Arrival Time | 2.234 |
Data Required Time | 1.927 |
From | u_la0_top/data_register_27_s0 |
To | u_la0_top/data_register_26_s0 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | tck_pad_i:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | tck_ibuf/I | |
0.675 | 0.675 | tINS | RR | 1 | tck_ibuf/O | |
0.675 | 0.000 | tNET | RR | 1 | u_gw_jtag/tck_pad_i | |
1.351 | 0.675 | tINS | RR | 275 | u_gw_jtag/tck_o | |
1.916 | 0.565 | tNET | RR | 1 | u_la0_top/data_register_27_s0/CLK | |
2.117 | 0.201 | tC2Q | RF | 1 | u_la0_top/data_register_27_s0/Q | |
2.234 | 0.117 | tNET | FF | 1 | u_la0_top/data_register_26_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | tck_ibuf/I | |
0.675 | 0.675 | tINS | RR | 1 | tck_ibuf/O | |
0.675 | 0.000 | tNET | RR | 1 | u_gw_jtag/tck_pad_i | |
1.351 | 0.675 | tINS | RR | 275 | u_gw_jtag/tck_o | |
1.916 | 0.565 | tNET | RR | 1 | u_la0_top/data_register_26_s0/CLK | |
1.927 | 0.011 | tHld | 1 | u_la0_top/data_register_26_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 1.351, 70.497%; route: 0.565, 29.503% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.117, 36.787%; tC2Q: 0.201, 63.213% |
Required Clock Path Delay | cell: 1.351, 70.497%; route: 0.565, 29.503% |
Path11
Path Summary:
Slack | 0.307 |
Data Arrival Time | 2.234 |
Data Required Time | 1.927 |
From | u_la0_top/data_register_28_s0 |
To | u_la0_top/data_register_27_s0 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | tck_pad_i:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | tck_ibuf/I | |
0.675 | 0.675 | tINS | RR | 1 | tck_ibuf/O | |
0.675 | 0.000 | tNET | RR | 1 | u_gw_jtag/tck_pad_i | |
1.351 | 0.675 | tINS | RR | 275 | u_gw_jtag/tck_o | |
1.916 | 0.565 | tNET | RR | 1 | u_la0_top/data_register_28_s0/CLK | |
2.117 | 0.201 | tC2Q | RF | 1 | u_la0_top/data_register_28_s0/Q | |
2.234 | 0.117 | tNET | FF | 1 | u_la0_top/data_register_27_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | tck_ibuf/I | |
0.675 | 0.675 | tINS | RR | 1 | tck_ibuf/O | |
0.675 | 0.000 | tNET | RR | 1 | u_gw_jtag/tck_pad_i | |
1.351 | 0.675 | tINS | RR | 275 | u_gw_jtag/tck_o | |
1.916 | 0.565 | tNET | RR | 1 | u_la0_top/data_register_27_s0/CLK | |
1.927 | 0.011 | tHld | 1 | u_la0_top/data_register_27_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 1.351, 70.497%; route: 0.565, 29.503% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.117, 36.787%; tC2Q: 0.201, 63.213% |
Required Clock Path Delay | cell: 1.351, 70.497%; route: 0.565, 29.503% |
Path12
Path Summary:
Slack | 0.307 |
Data Arrival Time | 2.234 |
Data Required Time | 1.927 |
From | u_la0_top/data_register_30_s0 |
To | u_la0_top/data_register_29_s0 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | tck_pad_i:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | tck_ibuf/I | |
0.675 | 0.675 | tINS | RR | 1 | tck_ibuf/O | |
0.675 | 0.000 | tNET | RR | 1 | u_gw_jtag/tck_pad_i | |
1.351 | 0.675 | tINS | RR | 275 | u_gw_jtag/tck_o | |
1.916 | 0.565 | tNET | RR | 1 | u_la0_top/data_register_30_s0/CLK | |
2.117 | 0.201 | tC2Q | RF | 1 | u_la0_top/data_register_30_s0/Q | |
2.234 | 0.117 | tNET | FF | 1 | u_la0_top/data_register_29_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | tck_ibuf/I | |
0.675 | 0.675 | tINS | RR | 1 | tck_ibuf/O | |
0.675 | 0.000 | tNET | RR | 1 | u_gw_jtag/tck_pad_i | |
1.351 | 0.675 | tINS | RR | 275 | u_gw_jtag/tck_o | |
1.916 | 0.565 | tNET | RR | 1 | u_la0_top/data_register_29_s0/CLK | |
1.927 | 0.011 | tHld | 1 | u_la0_top/data_register_29_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 1.351, 70.497%; route: 0.565, 29.503% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.117, 36.787%; tC2Q: 0.201, 63.213% |
Required Clock Path Delay | cell: 1.351, 70.497%; route: 0.565, 29.503% |
Path13
Path Summary:
Slack | 0.307 |
Data Arrival Time | 0.993 |
Data Required Time | 0.686 |
From | u_la0_top/u_ao_mem_ctrl/data_reg_dly_47_s0 |
To | u_la0_top/u_ao_mem_ctrl/data_reg_47_s0 |
Launch Clk | SYM_CLK:[R] |
Latch Clk | SYM_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.675 | 0.675 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | R3C4[0][B] | u_la0_top/u_ao_mem_ctrl/data_reg_dly_47_s0/CLK |
0.877 | 0.201 | tC2Q | RF | 1 | R3C4[0][B] | u_la0_top/u_ao_mem_ctrl/data_reg_dly_47_s0/Q |
0.993 | 0.117 | tNET | FF | 1 | R3C4[0][A] | u_la0_top/u_ao_mem_ctrl/data_reg_47_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.675 | 0.675 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | R3C4[0][A] | u_la0_top/u_ao_mem_ctrl/data_reg_47_s0/CLK |
0.686 | 0.011 | tHld | 1 | R3C4[0][A] | u_la0_top/u_ao_mem_ctrl/data_reg_47_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 100.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.117, 36.787%; tC2Q: 0.201, 63.213% |
Required Clock Path Delay | cell: 0.675, 100.000%; route: 0.000, 0.000% |
Path14
Path Summary:
Slack | 0.310 |
Data Arrival Time | 2.238 |
Data Required Time | 1.927 |
From | u_la0_top/capture_end_tck_1_s0 |
To | u_la0_top/capture_end_tck_2_s0 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | tck_pad_i:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | tck_ibuf/I | |
0.675 | 0.675 | tINS | RR | 1 | tck_ibuf/O | |
0.675 | 0.000 | tNET | RR | 1 | u_gw_jtag/tck_pad_i | |
1.351 | 0.675 | tINS | RR | 275 | u_gw_jtag/tck_o | |
1.916 | 0.565 | tNET | RR | 1 | u_la0_top/capture_end_tck_1_s0/CLK | |
2.117 | 0.201 | tC2Q | RF | 2 | u_la0_top/capture_end_tck_1_s0/Q | |
2.238 | 0.120 | tNET | FF | 1 | u_la0_top/capture_end_tck_2_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | tck_ibuf/I | |
0.675 | 0.675 | tINS | RR | 1 | tck_ibuf/O | |
0.675 | 0.000 | tNET | RR | 1 | u_gw_jtag/tck_pad_i | |
1.351 | 0.675 | tINS | RR | 275 | u_gw_jtag/tck_o | |
1.916 | 0.565 | tNET | RR | 1 | u_la0_top/capture_end_tck_2_s0/CLK | |
1.927 | 0.011 | tHld | 1 | u_la0_top/capture_end_tck_2_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 1.351, 70.497%; route: 0.565, 29.503% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.120, 37.432%; tC2Q: 0.201, 62.568% |
Required Clock Path Delay | cell: 1.351, 70.497%; route: 0.565, 29.503% |
Path15
Path Summary:
Slack | 0.310 |
Data Arrival Time | 2.238 |
Data Required Time | 1.927 |
From | u_la0_top/data_register_60_s0 |
To | u_la0_top/internal_register_select_11_s0 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | tck_pad_i:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | tck_ibuf/I | |
0.675 | 0.675 | tINS | RR | 1 | tck_ibuf/O | |
0.675 | 0.000 | tNET | RR | 1 | u_gw_jtag/tck_pad_i | |
1.351 | 0.675 | tINS | RR | 275 | u_gw_jtag/tck_o | |
1.916 | 0.565 | tNET | RR | 1 | u_la0_top/data_register_60_s0/CLK | |
2.117 | 0.201 | tC2Q | RF | 3 | u_la0_top/data_register_60_s0/Q | |
2.238 | 0.120 | tNET | FF | 1 | u_la0_top/internal_register_select_11_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | tck_ibuf/I | |
0.675 | 0.675 | tINS | RR | 1 | tck_ibuf/O | |
0.675 | 0.000 | tNET | RR | 1 | u_gw_jtag/tck_pad_i | |
1.351 | 0.675 | tINS | RR | 275 | u_gw_jtag/tck_o | |
1.916 | 0.565 | tNET | RR | 1 | u_la0_top/internal_register_select_11_s0/CLK | |
1.927 | 0.011 | tHld | 1 | u_la0_top/internal_register_select_11_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 1.351, 70.497%; route: 0.565, 29.503% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.120, 37.432%; tC2Q: 0.201, 62.568% |
Required Clock Path Delay | cell: 1.351, 70.497%; route: 0.565, 29.503% |
Path16
Path Summary:
Slack | 0.310 |
Data Arrival Time | 2.238 |
Data Required Time | 1.927 |
From | u_la0_top/data_register_63_s0 |
To | u_la0_top/internal_register_select_14_s0 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | tck_pad_i:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | tck_ibuf/I | |
0.675 | 0.675 | tINS | RR | 1 | tck_ibuf/O | |
0.675 | 0.000 | tNET | RR | 1 | u_gw_jtag/tck_pad_i | |
1.351 | 0.675 | tINS | RR | 275 | u_gw_jtag/tck_o | |
1.916 | 0.565 | tNET | RR | 1 | u_la0_top/data_register_63_s0/CLK | |
2.117 | 0.201 | tC2Q | RF | 3 | u_la0_top/data_register_63_s0/Q | |
2.238 | 0.120 | tNET | FF | 1 | u_la0_top/internal_register_select_14_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | tck_ibuf/I | |
0.675 | 0.675 | tINS | RR | 1 | tck_ibuf/O | |
0.675 | 0.000 | tNET | RR | 1 | u_gw_jtag/tck_pad_i | |
1.351 | 0.675 | tINS | RR | 275 | u_gw_jtag/tck_o | |
1.916 | 0.565 | tNET | RR | 1 | u_la0_top/internal_register_select_14_s0/CLK | |
1.927 | 0.011 | tHld | 1 | u_la0_top/internal_register_select_14_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 1.351, 70.497%; route: 0.565, 29.503% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.120, 37.432%; tC2Q: 0.201, 62.568% |
Required Clock Path Delay | cell: 1.351, 70.497%; route: 0.565, 29.503% |
Path17
Path Summary:
Slack | 0.310 |
Data Arrival Time | 2.238 |
Data Required Time | 1.927 |
From | u_la0_top/data_register_13_s0 |
To | u_la0_top/data_register_12_s0 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | tck_pad_i:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | tck_ibuf/I | |
0.675 | 0.675 | tINS | RR | 1 | tck_ibuf/O | |
0.675 | 0.000 | tNET | RR | 1 | u_gw_jtag/tck_pad_i | |
1.351 | 0.675 | tINS | RR | 275 | u_gw_jtag/tck_o | |
1.916 | 0.565 | tNET | RR | 1 | u_la0_top/data_register_13_s0/CLK | |
2.117 | 0.201 | tC2Q | RF | 3 | u_la0_top/data_register_13_s0/Q | |
2.238 | 0.120 | tNET | FF | 1 | u_la0_top/data_register_12_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | tck_ibuf/I | |
0.675 | 0.675 | tINS | RR | 1 | tck_ibuf/O | |
0.675 | 0.000 | tNET | RR | 1 | u_gw_jtag/tck_pad_i | |
1.351 | 0.675 | tINS | RR | 275 | u_gw_jtag/tck_o | |
1.916 | 0.565 | tNET | RR | 1 | u_la0_top/data_register_12_s0/CLK | |
1.927 | 0.011 | tHld | 1 | u_la0_top/data_register_12_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 1.351, 70.497%; route: 0.565, 29.503% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.120, 37.432%; tC2Q: 0.201, 62.568% |
Required Clock Path Delay | cell: 1.351, 70.497%; route: 0.565, 29.503% |
Path18
Path Summary:
Slack | 0.310 |
Data Arrival Time | 2.238 |
Data Required Time | 1.927 |
From | u_la0_top/data_register_15_s0 |
To | u_la0_top/data_register_14_s0 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | tck_pad_i:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | tck_ibuf/I | |
0.675 | 0.675 | tINS | RR | 1 | tck_ibuf/O | |
0.675 | 0.000 | tNET | RR | 1 | u_gw_jtag/tck_pad_i | |
1.351 | 0.675 | tINS | RR | 275 | u_gw_jtag/tck_o | |
1.916 | 0.565 | tNET | RR | 1 | u_la0_top/data_register_15_s0/CLK | |
2.117 | 0.201 | tC2Q | RF | 3 | u_la0_top/data_register_15_s0/Q | |
2.238 | 0.120 | tNET | FF | 1 | u_la0_top/data_register_14_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | tck_ibuf/I | |
0.675 | 0.675 | tINS | RR | 1 | tck_ibuf/O | |
0.675 | 0.000 | tNET | RR | 1 | u_gw_jtag/tck_pad_i | |
1.351 | 0.675 | tINS | RR | 275 | u_gw_jtag/tck_o | |
1.916 | 0.565 | tNET | RR | 1 | u_la0_top/data_register_14_s0/CLK | |
1.927 | 0.011 | tHld | 1 | u_la0_top/data_register_14_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 1.351, 70.497%; route: 0.565, 29.503% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.120, 37.432%; tC2Q: 0.201, 62.568% |
Required Clock Path Delay | cell: 1.351, 70.497%; route: 0.565, 29.503% |
Path19
Path Summary:
Slack | 0.310 |
Data Arrival Time | 2.238 |
Data Required Time | 1.927 |
From | u_la0_top/data_register_35_s0 |
To | u_la0_top/data_register_34_s0 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | tck_pad_i:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | tck_ibuf/I | |
0.675 | 0.675 | tINS | RR | 1 | tck_ibuf/O | |
0.675 | 0.000 | tNET | RR | 1 | u_gw_jtag/tck_pad_i | |
1.351 | 0.675 | tINS | RR | 275 | u_gw_jtag/tck_o | |
1.916 | 0.565 | tNET | RR | 1 | u_la0_top/data_register_35_s0/CLK | |
2.117 | 0.201 | tC2Q | RF | 2 | u_la0_top/data_register_35_s0/Q | |
2.238 | 0.120 | tNET | FF | 1 | u_la0_top/data_register_34_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | tck_ibuf/I | |
0.675 | 0.675 | tINS | RR | 1 | tck_ibuf/O | |
0.675 | 0.000 | tNET | RR | 1 | u_gw_jtag/tck_pad_i | |
1.351 | 0.675 | tINS | RR | 275 | u_gw_jtag/tck_o | |
1.916 | 0.565 | tNET | RR | 1 | u_la0_top/data_register_34_s0/CLK | |
1.927 | 0.011 | tHld | 1 | u_la0_top/data_register_34_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 1.351, 70.497%; route: 0.565, 29.503% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.120, 37.432%; tC2Q: 0.201, 62.568% |
Required Clock Path Delay | cell: 1.351, 70.497%; route: 0.565, 29.503% |
Path20
Path Summary:
Slack | 0.310 |
Data Arrival Time | 2.238 |
Data Required Time | 1.927 |
From | u_la0_top/data_register_39_s0 |
To | u_la0_top/data_register_38_s0 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | tck_pad_i:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | tck_ibuf/I | |
0.675 | 0.675 | tINS | RR | 1 | tck_ibuf/O | |
0.675 | 0.000 | tNET | RR | 1 | u_gw_jtag/tck_pad_i | |
1.351 | 0.675 | tINS | RR | 275 | u_gw_jtag/tck_o | |
1.916 | 0.565 | tNET | RR | 1 | u_la0_top/data_register_39_s0/CLK | |
2.117 | 0.201 | tC2Q | RF | 2 | u_la0_top/data_register_39_s0/Q | |
2.238 | 0.120 | tNET | FF | 1 | u_la0_top/data_register_38_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | tck_ibuf/I | |
0.675 | 0.675 | tINS | RR | 1 | tck_ibuf/O | |
0.675 | 0.000 | tNET | RR | 1 | u_gw_jtag/tck_pad_i | |
1.351 | 0.675 | tINS | RR | 275 | u_gw_jtag/tck_o | |
1.916 | 0.565 | tNET | RR | 1 | u_la0_top/data_register_38_s0/CLK | |
1.927 | 0.011 | tHld | 1 | u_la0_top/data_register_38_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 1.351, 70.497%; route: 0.565, 29.503% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.120, 37.432%; tC2Q: 0.201, 62.568% |
Required Clock Path Delay | cell: 1.351, 70.497%; route: 0.565, 29.503% |
Path21
Path Summary:
Slack | 0.310 |
Data Arrival Time | 2.238 |
Data Required Time | 1.927 |
From | u_la0_top/data_register_42_s0 |
To | u_la0_top/data_register_41_s0 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | tck_pad_i:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | tck_ibuf/I | |
0.675 | 0.675 | tINS | RR | 1 | tck_ibuf/O | |
0.675 | 0.000 | tNET | RR | 1 | u_gw_jtag/tck_pad_i | |
1.351 | 0.675 | tINS | RR | 275 | u_gw_jtag/tck_o | |
1.916 | 0.565 | tNET | RR | 1 | u_la0_top/data_register_42_s0/CLK | |
2.117 | 0.201 | tC2Q | RF | 2 | u_la0_top/data_register_42_s0/Q | |
2.238 | 0.120 | tNET | FF | 1 | u_la0_top/data_register_41_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | tck_ibuf/I | |
0.675 | 0.675 | tINS | RR | 1 | tck_ibuf/O | |
0.675 | 0.000 | tNET | RR | 1 | u_gw_jtag/tck_pad_i | |
1.351 | 0.675 | tINS | RR | 275 | u_gw_jtag/tck_o | |
1.916 | 0.565 | tNET | RR | 1 | u_la0_top/data_register_41_s0/CLK | |
1.927 | 0.011 | tHld | 1 | u_la0_top/data_register_41_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 1.351, 70.497%; route: 0.565, 29.503% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.120, 37.432%; tC2Q: 0.201, 62.568% |
Required Clock Path Delay | cell: 1.351, 70.497%; route: 0.565, 29.503% |
Path22
Path Summary:
Slack | 0.310 |
Data Arrival Time | 2.238 |
Data Required Time | 1.927 |
From | u_icon_top/input_shift_reg_3_s0 |
To | u_icon_top/input_shift_reg_2_s0 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | tck_pad_i:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | tck_ibuf/I | |
0.675 | 0.675 | tINS | RR | 1 | tck_ibuf/O | |
0.675 | 0.000 | tNET | RR | 1 | u_gw_jtag/tck_pad_i | |
1.351 | 0.675 | tINS | RR | 275 | u_gw_jtag/tck_o | |
1.916 | 0.565 | tNET | RR | 1 | u_icon_top/input_shift_reg_3_s0/CLK | |
2.117 | 0.201 | tC2Q | RF | 2 | u_icon_top/input_shift_reg_3_s0/Q | |
2.238 | 0.120 | tNET | FF | 1 | u_icon_top/input_shift_reg_2_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | tck_ibuf/I | |
0.675 | 0.675 | tINS | RR | 1 | tck_ibuf/O | |
0.675 | 0.000 | tNET | RR | 1 | u_gw_jtag/tck_pad_i | |
1.351 | 0.675 | tINS | RR | 275 | u_gw_jtag/tck_o | |
1.916 | 0.565 | tNET | RR | 1 | u_icon_top/input_shift_reg_2_s0/CLK | |
1.927 | 0.011 | tHld | 1 | u_icon_top/input_shift_reg_2_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 1.351, 70.497%; route: 0.565, 29.503% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.120, 37.432%; tC2Q: 0.201, 62.568% |
Required Clock Path Delay | cell: 1.351, 70.497%; route: 0.565, 29.503% |
Path23
Path Summary:
Slack | 0.310 |
Data Arrival Time | 2.238 |
Data Required Time | 1.927 |
From | u_icon_top/input_shift_reg_1_s0 |
To | u_icon_top/module_id_reg_1_s0 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | tck_pad_i:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | tck_ibuf/I | |
0.675 | 0.675 | tINS | RR | 1 | tck_ibuf/O | |
0.675 | 0.000 | tNET | RR | 1 | u_gw_jtag/tck_pad_i | |
1.351 | 0.675 | tINS | RR | 275 | u_gw_jtag/tck_o | |
1.916 | 0.565 | tNET | RR | 1 | u_icon_top/input_shift_reg_1_s0/CLK | |
2.117 | 0.201 | tC2Q | RF | 2 | u_icon_top/input_shift_reg_1_s0/Q | |
2.238 | 0.120 | tNET | FF | 1 | u_icon_top/module_id_reg_1_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | tck_ibuf/I | |
0.675 | 0.675 | tINS | RR | 1 | tck_ibuf/O | |
0.675 | 0.000 | tNET | RR | 1 | u_gw_jtag/tck_pad_i | |
1.351 | 0.675 | tINS | RR | 275 | u_gw_jtag/tck_o | |
1.916 | 0.565 | tNET | RR | 1 | u_icon_top/module_id_reg_1_s0/CLK | |
1.927 | 0.011 | tHld | 1 | u_icon_top/module_id_reg_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 1.351, 70.497%; route: 0.565, 29.503% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.120, 37.432%; tC2Q: 0.201, 62.568% |
Required Clock Path Delay | cell: 1.351, 70.497%; route: 0.565, 29.503% |
Path24
Path Summary:
Slack | 0.314 |
Data Arrival Time | 2.241 |
Data Required Time | 1.927 |
From | u_la0_top/data_register_56_s0 |
To | u_la0_top/internal_register_select_7_s0 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | tck_pad_i:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | tck_ibuf/I | |
0.675 | 0.675 | tINS | RR | 1 | tck_ibuf/O | |
0.675 | 0.000 | tNET | RR | 1 | u_gw_jtag/tck_pad_i | |
1.351 | 0.675 | tINS | RR | 275 | u_gw_jtag/tck_o | |
1.916 | 0.565 | tNET | RR | 1 | u_la0_top/data_register_56_s0/CLK | |
2.117 | 0.201 | tC2Q | RF | 4 | u_la0_top/data_register_56_s0/Q | |
2.241 | 0.124 | tNET | FF | 1 | u_la0_top/internal_register_select_7_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | tck_ibuf/I | |
0.675 | 0.675 | tINS | RR | 1 | tck_ibuf/O | |
0.675 | 0.000 | tNET | RR | 1 | u_gw_jtag/tck_pad_i | |
1.351 | 0.675 | tINS | RR | 275 | u_gw_jtag/tck_o | |
1.916 | 0.565 | tNET | RR | 1 | u_la0_top/internal_register_select_7_s0/CLK | |
1.927 | 0.011 | tHld | 1 | u_la0_top/internal_register_select_7_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 1.351, 70.497%; route: 0.565, 29.503% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.124, 38.064%; tC2Q: 0.201, 61.936% |
Required Clock Path Delay | cell: 1.351, 70.497%; route: 0.565, 29.503% |
Path25
Path Summary:
Slack | 0.314 |
Data Arrival Time | 2.241 |
Data Required Time | 1.927 |
From | u_la0_top/data_register_58_s0 |
To | u_la0_top/internal_register_select_9_s0 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | tck_pad_i:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | tck_ibuf/I | |
0.675 | 0.675 | tINS | RR | 1 | tck_ibuf/O | |
0.675 | 0.000 | tNET | RR | 1 | u_gw_jtag/tck_pad_i | |
1.351 | 0.675 | tINS | RR | 275 | u_gw_jtag/tck_o | |
1.916 | 0.565 | tNET | RR | 1 | u_la0_top/data_register_58_s0/CLK | |
2.117 | 0.201 | tC2Q | RF | 4 | u_la0_top/data_register_58_s0/Q | |
2.241 | 0.124 | tNET | FF | 1 | u_la0_top/internal_register_select_9_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | tck_ibuf/I | |
0.675 | 0.675 | tINS | RR | 1 | tck_ibuf/O | |
0.675 | 0.000 | tNET | RR | 1 | u_gw_jtag/tck_pad_i | |
1.351 | 0.675 | tINS | RR | 275 | u_gw_jtag/tck_o | |
1.916 | 0.565 | tNET | RR | 1 | u_la0_top/internal_register_select_9_s0/CLK | |
1.927 | 0.011 | tHld | 1 | u_la0_top/internal_register_select_9_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 1.351, 70.497%; route: 0.565, 29.503% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.124, 38.064%; tC2Q: 0.201, 61.936% |
Required Clock Path Delay | cell: 1.351, 70.497%; route: 0.565, 29.503% |
Recovery Analysis Report
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 8.506 |
Data Arrival Time | 2.141 |
Data Required Time | 10.648 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1 |
Launch Clk | SYM_CLK:[R] |
Latch Clk | SYM_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.683 | 0.000 | tNET | RR | 1 | R2C5[2][A] | u_la0_top/rst_ao_s0/CLK |
0.914 | 0.232 | tC2Q | RF | 53 | R2C5[2][A] | u_la0_top/rst_ao_s0/Q |
2.141 | 1.227 | tNET | FF | 1 | R13C2[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | SYM_CLK | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
10.682 | 0.000 | tNET | RR | 1 | R13C2[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK |
10.648 | -0.035 | tSu | 1 | R13C2[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.683, 100.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.227, 84.095%; tC2Q: 0.232, 15.905% |
Required Clock Path Delay | cell: 0.683, 100.000%; route: 0.000, 0.000% |
Path2
Path Summary:
Slack | 8.589 |
Data Arrival Time | 2.059 |
Data Required Time | 10.648 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1 |
Launch Clk | SYM_CLK:[R] |
Latch Clk | SYM_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.683 | 0.000 | tNET | RR | 1 | R2C5[2][A] | u_la0_top/rst_ao_s0/CLK |
0.914 | 0.232 | tC2Q | RF | 53 | R2C5[2][A] | u_la0_top/rst_ao_s0/Q |
2.059 | 1.144 | tNET | FF | 1 | R11C2[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | SYM_CLK | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
10.682 | 0.000 | tNET | RR | 1 | R11C2[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLK |
10.648 | -0.035 | tSu | 1 | R11C2[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.683, 100.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.144, 83.143%; tC2Q: 0.232, 16.857% |
Required Clock Path Delay | cell: 0.683, 100.000%; route: 0.000, 0.000% |
Path3
Path Summary:
Slack | 8.589 |
Data Arrival Time | 2.059 |
Data Required Time | 10.648 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1 |
Launch Clk | SYM_CLK:[R] |
Latch Clk | SYM_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.683 | 0.000 | tNET | RR | 1 | R2C5[2][A] | u_la0_top/rst_ao_s0/CLK |
0.914 | 0.232 | tC2Q | RF | 53 | R2C5[2][A] | u_la0_top/rst_ao_s0/Q |
2.059 | 1.144 | tNET | FF | 1 | R11C2[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | SYM_CLK | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
10.682 | 0.000 | tNET | RR | 1 | R11C2[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK |
10.648 | -0.035 | tSu | 1 | R11C2[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.683, 100.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.144, 83.143%; tC2Q: 0.232, 16.857% |
Required Clock Path Delay | cell: 0.683, 100.000%; route: 0.000, 0.000% |
Path4
Path Summary:
Slack | 8.589 |
Data Arrival Time | 2.059 |
Data Required Time | 10.648 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1 |
Launch Clk | SYM_CLK:[R] |
Latch Clk | SYM_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.683 | 0.000 | tNET | RR | 1 | R2C5[2][A] | u_la0_top/rst_ao_s0/CLK |
0.914 | 0.232 | tC2Q | RF | 53 | R2C5[2][A] | u_la0_top/rst_ao_s0/Q |
2.059 | 1.144 | tNET | FF | 1 | R11C2[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | SYM_CLK | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
10.682 | 0.000 | tNET | RR | 1 | R11C2[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK |
10.648 | -0.035 | tSu | 1 | R11C2[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.683, 100.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.144, 83.143%; tC2Q: 0.232, 16.857% |
Required Clock Path Delay | cell: 0.683, 100.000%; route: 0.000, 0.000% |
Path5
Path Summary:
Slack | 8.589 |
Data Arrival Time | 2.059 |
Data Required Time | 10.648 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1 |
Launch Clk | SYM_CLK:[R] |
Latch Clk | SYM_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.683 | 0.000 | tNET | RR | 1 | R2C5[2][A] | u_la0_top/rst_ao_s0/CLK |
0.914 | 0.232 | tC2Q | RF | 53 | R2C5[2][A] | u_la0_top/rst_ao_s0/Q |
2.059 | 1.144 | tNET | FF | 1 | R11C2[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | SYM_CLK | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
10.682 | 0.000 | tNET | RR | 1 | R11C2[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK |
10.648 | -0.035 | tSu | 1 | R11C2[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.683, 100.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.144, 83.143%; tC2Q: 0.232, 16.857% |
Required Clock Path Delay | cell: 0.683, 100.000%; route: 0.000, 0.000% |
Path6
Path Summary:
Slack | 8.670 |
Data Arrival Time | 1.978 |
Data Required Time | 10.648 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1 |
Launch Clk | SYM_CLK:[R] |
Latch Clk | SYM_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.683 | 0.000 | tNET | RR | 1 | R2C5[2][A] | u_la0_top/rst_ao_s0/CLK |
0.914 | 0.232 | tC2Q | RF | 53 | R2C5[2][A] | u_la0_top/rst_ao_s0/Q |
1.978 | 1.063 | tNET | FF | 1 | R12C2[2][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | SYM_CLK | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
10.682 | 0.000 | tNET | RR | 1 | R12C2[2][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK |
10.648 | -0.035 | tSu | 1 | R12C2[2][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.683, 100.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.063, 82.088%; tC2Q: 0.232, 17.912% |
Required Clock Path Delay | cell: 0.683, 100.000%; route: 0.000, 0.000% |
Path7
Path Summary:
Slack | 8.670 |
Data Arrival Time | 1.978 |
Data Required Time | 10.648 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1 |
Launch Clk | SYM_CLK:[R] |
Latch Clk | SYM_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.683 | 0.000 | tNET | RR | 1 | R2C5[2][A] | u_la0_top/rst_ao_s0/CLK |
0.914 | 0.232 | tC2Q | RF | 53 | R2C5[2][A] | u_la0_top/rst_ao_s0/Q |
1.978 | 1.063 | tNET | FF | 1 | R12C2[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | SYM_CLK | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
10.682 | 0.000 | tNET | RR | 1 | R12C2[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK |
10.648 | -0.035 | tSu | 1 | R12C2[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.683, 100.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.063, 82.088%; tC2Q: 0.232, 17.912% |
Required Clock Path Delay | cell: 0.683, 100.000%; route: 0.000, 0.000% |
Path8
Path Summary:
Slack | 8.670 |
Data Arrival Time | 1.978 |
Data Required Time | 10.648 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/capture_window_sel_1_s1 |
Launch Clk | SYM_CLK:[R] |
Latch Clk | SYM_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.683 | 0.000 | tNET | RR | 1 | R2C5[2][A] | u_la0_top/rst_ao_s0/CLK |
0.914 | 0.232 | tC2Q | RF | 53 | R2C5[2][A] | u_la0_top/rst_ao_s0/Q |
1.978 | 1.063 | tNET | FF | 1 | R5C2[2][A] | u_la0_top/capture_window_sel_1_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | SYM_CLK | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
10.682 | 0.000 | tNET | RR | 1 | R5C2[2][A] | u_la0_top/capture_window_sel_1_s1/CLK |
10.648 | -0.035 | tSu | 1 | R5C2[2][A] | u_la0_top/capture_window_sel_1_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.683, 100.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.063, 82.088%; tC2Q: 0.232, 17.912% |
Required Clock Path Delay | cell: 0.683, 100.000%; route: 0.000, 0.000% |
Path9
Path Summary:
Slack | 8.702 |
Data Arrival Time | 1.946 |
Data Required Time | 10.648 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/capture_window_sel_9_s1 |
Launch Clk | SYM_CLK:[R] |
Latch Clk | SYM_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.683 | 0.000 | tNET | RR | 1 | R2C5[2][A] | u_la0_top/rst_ao_s0/CLK |
0.914 | 0.232 | tC2Q | RF | 53 | R2C5[2][A] | u_la0_top/rst_ao_s0/Q |
1.946 | 1.031 | tNET | FF | 1 | R7C3[2][A] | u_la0_top/capture_window_sel_9_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | SYM_CLK | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
10.682 | 0.000 | tNET | RR | 1 | R7C3[2][A] | u_la0_top/capture_window_sel_9_s1/CLK |
10.648 | -0.035 | tSu | 1 | R7C3[2][A] | u_la0_top/capture_window_sel_9_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.683, 100.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.031, 81.631%; tC2Q: 0.232, 18.369% |
Required Clock Path Delay | cell: 0.683, 100.000%; route: 0.000, 0.000% |
Path10
Path Summary:
Slack | 8.789 |
Data Arrival Time | 1.859 |
Data Required Time | 10.648 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1 |
Launch Clk | SYM_CLK:[R] |
Latch Clk | SYM_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.683 | 0.000 | tNET | RR | 1 | R2C5[2][A] | u_la0_top/rst_ao_s0/CLK |
0.914 | 0.232 | tC2Q | RF | 53 | R2C5[2][A] | u_la0_top/rst_ao_s0/Q |
1.859 | 0.944 | tNET | FF | 1 | R2C2[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | SYM_CLK | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
10.682 | 0.000 | tNET | RR | 1 | R2C2[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK |
10.648 | -0.035 | tSu | 1 | R2C2[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.683, 100.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.944, 80.277%; tC2Q: 0.232, 19.723% |
Required Clock Path Delay | cell: 0.683, 100.000%; route: 0.000, 0.000% |
Path11
Path Summary:
Slack | 8.801 |
Data Arrival Time | 1.847 |
Data Required Time | 10.648 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_mem_ctrl/capture_length_4_s1 |
Launch Clk | SYM_CLK:[R] |
Latch Clk | SYM_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.683 | 0.000 | tNET | RR | 1 | R2C5[2][A] | u_la0_top/rst_ao_s0/CLK |
0.914 | 0.232 | tC2Q | RF | 53 | R2C5[2][A] | u_la0_top/rst_ao_s0/Q |
1.847 | 0.932 | tNET | FF | 1 | R7C2[0][A] | u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | SYM_CLK | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
10.682 | 0.000 | tNET | RR | 1 | R7C2[0][A] | u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLK |
10.648 | -0.035 | tSu | 1 | R7C2[0][A] | u_la0_top/u_ao_mem_ctrl/capture_length_4_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.683, 100.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.932, 80.076%; tC2Q: 0.232, 19.924% |
Required Clock Path Delay | cell: 0.683, 100.000%; route: 0.000, 0.000% |
Path12
Path Summary:
Slack | 8.801 |
Data Arrival Time | 1.847 |
Data Required Time | 10.648 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_mem_ctrl/capture_length_5_s1 |
Launch Clk | SYM_CLK:[R] |
Latch Clk | SYM_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.683 | 0.000 | tNET | RR | 1 | R2C5[2][A] | u_la0_top/rst_ao_s0/CLK |
0.914 | 0.232 | tC2Q | RF | 53 | R2C5[2][A] | u_la0_top/rst_ao_s0/Q |
1.847 | 0.932 | tNET | FF | 1 | R7C2[0][B] | u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | SYM_CLK | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
10.682 | 0.000 | tNET | RR | 1 | R7C2[0][B] | u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLK |
10.648 | -0.035 | tSu | 1 | R7C2[0][B] | u_la0_top/u_ao_mem_ctrl/capture_length_5_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.683, 100.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.932, 80.076%; tC2Q: 0.232, 19.924% |
Required Clock Path Delay | cell: 0.683, 100.000%; route: 0.000, 0.000% |
Path13
Path Summary:
Slack | 8.907 |
Data Arrival Time | 1.741 |
Data Required Time | 10.648 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_mem_ctrl/capture_length_6_s1 |
Launch Clk | SYM_CLK:[R] |
Latch Clk | SYM_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.683 | 0.000 | tNET | RR | 1 | R2C5[2][A] | u_la0_top/rst_ao_s0/CLK |
0.914 | 0.232 | tC2Q | RF | 53 | R2C5[2][A] | u_la0_top/rst_ao_s0/Q |
1.741 | 0.826 | tNET | FF | 1 | R6C2[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | SYM_CLK | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
10.682 | 0.000 | tNET | RR | 1 | R6C2[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLK |
10.648 | -0.035 | tSu | 1 | R6C2[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_6_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.683, 100.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.826, 78.077%; tC2Q: 0.232, 21.923% |
Required Clock Path Delay | cell: 0.683, 100.000%; route: 0.000, 0.000% |
Path14
Path Summary:
Slack | 8.907 |
Data Arrival Time | 1.741 |
Data Required Time | 10.648 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_mem_ctrl/capture_length_7_s1 |
Launch Clk | SYM_CLK:[R] |
Latch Clk | SYM_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.683 | 0.000 | tNET | RR | 1 | R2C5[2][A] | u_la0_top/rst_ao_s0/CLK |
0.914 | 0.232 | tC2Q | RF | 53 | R2C5[2][A] | u_la0_top/rst_ao_s0/Q |
1.741 | 0.826 | tNET | FF | 1 | R6C2[2][A] | u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | SYM_CLK | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
10.682 | 0.000 | tNET | RR | 1 | R6C2[2][A] | u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLK |
10.648 | -0.035 | tSu | 1 | R6C2[2][A] | u_la0_top/u_ao_mem_ctrl/capture_length_7_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.683, 100.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.826, 78.077%; tC2Q: 0.232, 21.923% |
Required Clock Path Delay | cell: 0.683, 100.000%; route: 0.000, 0.000% |
Path15
Path Summary:
Slack | 8.907 |
Data Arrival Time | 1.741 |
Data Required Time | 10.648 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/triger_level_cnt_0_s3 |
Launch Clk | SYM_CLK:[R] |
Latch Clk | SYM_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.683 | 0.000 | tNET | RR | 1 | R2C5[2][A] | u_la0_top/rst_ao_s0/CLK |
0.914 | 0.232 | tC2Q | RF | 53 | R2C5[2][A] | u_la0_top/rst_ao_s0/Q |
1.741 | 0.826 | tNET | FF | 1 | R6C2[0][A] | u_la0_top/triger_level_cnt_0_s3/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | SYM_CLK | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
10.682 | 0.000 | tNET | RR | 1 | R6C2[0][A] | u_la0_top/triger_level_cnt_0_s3/CLK |
10.648 | -0.035 | tSu | 1 | R6C2[0][A] | u_la0_top/triger_level_cnt_0_s3 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.683, 100.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.826, 78.077%; tC2Q: 0.232, 21.923% |
Required Clock Path Delay | cell: 0.683, 100.000%; route: 0.000, 0.000% |
Path16
Path Summary:
Slack | 8.939 |
Data Arrival Time | 1.709 |
Data Required Time | 10.648 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1 |
Launch Clk | SYM_CLK:[R] |
Latch Clk | SYM_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.683 | 0.000 | tNET | RR | 1 | R2C5[2][A] | u_la0_top/rst_ao_s0/CLK |
0.914 | 0.232 | tC2Q | RF | 53 | R2C5[2][A] | u_la0_top/rst_ao_s0/Q |
1.709 | 0.794 | tNET | FF | 1 | R12C3[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | SYM_CLK | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
10.682 | 0.000 | tNET | RR | 1 | R12C3[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK |
10.648 | -0.035 | tSu | 1 | R12C3[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.683, 100.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.794, 77.389%; tC2Q: 0.232, 22.611% |
Required Clock Path Delay | cell: 0.683, 100.000%; route: 0.000, 0.000% |
Path17
Path Summary:
Slack | 8.939 |
Data Arrival Time | 1.709 |
Data Required Time | 10.648 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1 |
Launch Clk | SYM_CLK:[R] |
Latch Clk | SYM_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.683 | 0.000 | tNET | RR | 1 | R2C5[2][A] | u_la0_top/rst_ao_s0/CLK |
0.914 | 0.232 | tC2Q | RF | 53 | R2C5[2][A] | u_la0_top/rst_ao_s0/Q |
1.709 | 0.794 | tNET | FF | 1 | R12C3[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | SYM_CLK | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
10.682 | 0.000 | tNET | RR | 1 | R12C3[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK |
10.648 | -0.035 | tSu | 1 | R12C3[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.683, 100.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.794, 77.389%; tC2Q: 0.232, 22.611% |
Required Clock Path Delay | cell: 0.683, 100.000%; route: 0.000, 0.000% |
Path18
Path Summary:
Slack | 8.939 |
Data Arrival Time | 1.709 |
Data Required Time | 10.648 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/internal_reg_start_dly_1_s0 |
Launch Clk | SYM_CLK:[R] |
Latch Clk | SYM_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.683 | 0.000 | tNET | RR | 1 | R2C5[2][A] | u_la0_top/rst_ao_s0/CLK |
0.914 | 0.232 | tC2Q | RF | 53 | R2C5[2][A] | u_la0_top/rst_ao_s0/Q |
1.709 | 0.794 | tNET | FF | 1 | R12C3[0][A] | u_la0_top/internal_reg_start_dly_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | SYM_CLK | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
10.682 | 0.000 | tNET | RR | 1 | R12C3[0][A] | u_la0_top/internal_reg_start_dly_1_s0/CLK |
10.648 | -0.035 | tSu | 1 | R12C3[0][A] | u_la0_top/internal_reg_start_dly_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.683, 100.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.794, 77.389%; tC2Q: 0.232, 22.611% |
Required Clock Path Delay | cell: 0.683, 100.000%; route: 0.000, 0.000% |
Path19
Path Summary:
Slack | 8.945 |
Data Arrival Time | 1.703 |
Data Required Time | 10.648 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1 |
Launch Clk | SYM_CLK:[R] |
Latch Clk | SYM_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.683 | 0.000 | tNET | RR | 1 | R2C5[2][A] | u_la0_top/rst_ao_s0/CLK |
0.914 | 0.232 | tC2Q | RF | 53 | R2C5[2][A] | u_la0_top/rst_ao_s0/Q |
1.703 | 0.788 | tNET | FF | 1 | R11C3[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | SYM_CLK | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
10.682 | 0.000 | tNET | RR | 1 | R11C3[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK |
10.648 | -0.035 | tSu | 1 | R11C3[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.683, 100.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.788, 77.262%; tC2Q: 0.232, 22.738% |
Required Clock Path Delay | cell: 0.683, 100.000%; route: 0.000, 0.000% |
Path20
Path Summary:
Slack | 8.950 |
Data Arrival Time | 1.697 |
Data Required Time | 10.648 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_mem_ctrl/capture_loop_s1 |
Launch Clk | SYM_CLK:[R] |
Latch Clk | SYM_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.683 | 0.000 | tNET | RR | 1 | R2C5[2][A] | u_la0_top/rst_ao_s0/CLK |
0.914 | 0.232 | tC2Q | RF | 53 | R2C5[2][A] | u_la0_top/rst_ao_s0/Q |
1.697 | 0.783 | tNET | FF | 1 | R12C4[1][A] | u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | SYM_CLK | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
10.682 | 0.000 | tNET | RR | 1 | R12C4[1][A] | u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK |
10.648 | -0.035 | tSu | 1 | R12C4[1][A] | u_la0_top/u_ao_mem_ctrl/capture_loop_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.683, 100.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.783, 77.133%; tC2Q: 0.232, 22.867% |
Required Clock Path Delay | cell: 0.683, 100.000%; route: 0.000, 0.000% |
Path21
Path Summary:
Slack | 9.020 |
Data Arrival Time | 1.628 |
Data Required Time | 10.648 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1 |
Launch Clk | SYM_CLK:[R] |
Latch Clk | SYM_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.683 | 0.000 | tNET | RR | 1 | R2C5[2][A] | u_la0_top/rst_ao_s0/CLK |
0.914 | 0.232 | tC2Q | RF | 53 | R2C5[2][A] | u_la0_top/rst_ao_s0/Q |
1.628 | 0.713 | tNET | FF | 1 | R4C2[1][A] | u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | SYM_CLK | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
10.682 | 0.000 | tNET | RR | 1 | R4C2[1][A] | u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLK |
10.648 | -0.035 | tSu | 1 | R4C2[1][A] | u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.683, 100.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.713, 75.450%; tC2Q: 0.232, 24.550% |
Required Clock Path Delay | cell: 0.683, 100.000%; route: 0.000, 0.000% |
Path22
Path Summary:
Slack | 9.020 |
Data Arrival Time | 1.628 |
Data Required Time | 10.648 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/triger_level_cnt_1_s1 |
Launch Clk | SYM_CLK:[R] |
Latch Clk | SYM_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.683 | 0.000 | tNET | RR | 1 | R2C5[2][A] | u_la0_top/rst_ao_s0/CLK |
0.914 | 0.232 | tC2Q | RF | 53 | R2C5[2][A] | u_la0_top/rst_ao_s0/Q |
1.628 | 0.713 | tNET | FF | 1 | R4C2[0][A] | u_la0_top/triger_level_cnt_1_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | SYM_CLK | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
10.682 | 0.000 | tNET | RR | 1 | R4C2[0][A] | u_la0_top/triger_level_cnt_1_s1/CLK |
10.648 | -0.035 | tSu | 1 | R4C2[0][A] | u_la0_top/triger_level_cnt_1_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.683, 100.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.713, 75.450%; tC2Q: 0.232, 24.550% |
Required Clock Path Delay | cell: 0.683, 100.000%; route: 0.000, 0.000% |
Path23
Path Summary:
Slack | 9.050 |
Data Arrival Time | 1.598 |
Data Required Time | 10.648 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_match_0/match_sep_s0 |
Launch Clk | SYM_CLK:[R] |
Latch Clk | SYM_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.683 | 0.000 | tNET | RR | 1 | R2C5[2][A] | u_la0_top/rst_ao_s0/CLK |
0.914 | 0.232 | tC2Q | RF | 53 | R2C5[2][A] | u_la0_top/rst_ao_s0/Q |
1.598 | 0.683 | tNET | FF | 1 | R5C3[1][B] | u_la0_top/u_ao_match_0/match_sep_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | SYM_CLK | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
10.682 | 0.000 | tNET | RR | 1 | R5C3[1][B] | u_la0_top/u_ao_match_0/match_sep_s0/CLK |
10.648 | -0.035 | tSu | 1 | R5C3[1][B] | u_la0_top/u_ao_match_0/match_sep_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.683, 100.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.683, 74.657%; tC2Q: 0.232, 25.343% |
Required Clock Path Delay | cell: 0.683, 100.000%; route: 0.000, 0.000% |
Path24
Path Summary:
Slack | 9.050 |
Data Arrival Time | 1.598 |
Data Required Time | 10.648 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/internal_reg_force_triger_syn_1_s0 |
Launch Clk | SYM_CLK:[R] |
Latch Clk | SYM_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.683 | 0.000 | tNET | RR | 1 | R2C5[2][A] | u_la0_top/rst_ao_s0/CLK |
0.914 | 0.232 | tC2Q | RF | 53 | R2C5[2][A] | u_la0_top/rst_ao_s0/Q |
1.598 | 0.683 | tNET | FF | 1 | R5C3[1][A] | u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | SYM_CLK | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
10.682 | 0.000 | tNET | RR | 1 | R5C3[1][A] | u_la0_top/internal_reg_force_triger_syn_1_s0/CLK |
10.648 | -0.035 | tSu | 1 | R5C3[1][A] | u_la0_top/internal_reg_force_triger_syn_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.683, 100.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.683, 74.657%; tC2Q: 0.232, 25.343% |
Required Clock Path Delay | cell: 0.683, 100.000%; route: 0.000, 0.000% |
Path25
Path Summary:
Slack | 9.056 |
Data Arrival Time | 1.592 |
Data Required Time | 10.648 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/capture_window_sel_2_s1 |
Launch Clk | SYM_CLK:[R] |
Latch Clk | SYM_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.683 | 0.000 | tNET | RR | 1 | R2C5[2][A] | u_la0_top/rst_ao_s0/CLK |
0.914 | 0.232 | tC2Q | RF | 53 | R2C5[2][A] | u_la0_top/rst_ao_s0/Q |
1.592 | 0.677 | tNET | FF | 1 | R4C3[0][A] | u_la0_top/capture_window_sel_2_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | SYM_CLK | ||||
10.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
10.682 | 0.000 | tNET | RR | 1 | R4C3[0][A] | u_la0_top/capture_window_sel_2_s1/CLK |
10.648 | -0.035 | tSu | 1 | R4C3[0][A] | u_la0_top/capture_window_sel_2_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.683, 100.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.677, 74.484%; tC2Q: 0.232, 25.516% |
Required Clock Path Delay | cell: 0.683, 100.000%; route: 0.000, 0.000% |
Removal Analysis Report
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 0.332 |
Data Arrival Time | 1.018 |
Data Required Time | 0.686 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0 |
Launch Clk | SYM_CLK:[R] |
Latch Clk | SYM_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.675 | 0.675 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | R2C5[2][A] | u_la0_top/rst_ao_s0/CLK |
0.877 | 0.202 | tC2Q | RR | 53 | R2C5[2][A] | u_la0_top/rst_ao_s0/Q |
1.018 | 0.141 | tNET | RR | 1 | R2C5[0][A] | u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.675 | 0.675 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | R2C5[0][A] | u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLK |
0.686 | 0.011 | tHld | 1 | R2C5[0][A] | u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 100.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.141, 41.059%; tC2Q: 0.202, 58.941% |
Required Clock Path Delay | cell: 0.675, 100.000%; route: 0.000, 0.000% |
Path2
Path Summary:
Slack | 0.332 |
Data Arrival Time | 1.018 |
Data Required Time | 0.686 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/capture_end_dly_s0 |
Launch Clk | SYM_CLK:[R] |
Latch Clk | SYM_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.675 | 0.675 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | R2C5[2][A] | u_la0_top/rst_ao_s0/CLK |
0.877 | 0.202 | tC2Q | RR | 53 | R2C5[2][A] | u_la0_top/rst_ao_s0/Q |
1.018 | 0.141 | tNET | RR | 1 | R2C5[1][A] | u_la0_top/capture_end_dly_s0/PRESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.675 | 0.675 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | R2C5[1][A] | u_la0_top/capture_end_dly_s0/CLK |
0.686 | 0.011 | tHld | 1 | R2C5[1][A] | u_la0_top/capture_end_dly_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 100.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.141, 41.059%; tC2Q: 0.202, 58.941% |
Required Clock Path Delay | cell: 0.675, 100.000%; route: 0.000, 0.000% |
Path3
Path Summary:
Slack | 0.332 |
Data Arrival Time | 1.018 |
Data Required Time | 0.686 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/internal_reg_start_dly_0_s0 |
Launch Clk | SYM_CLK:[R] |
Latch Clk | SYM_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.675 | 0.675 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | R2C5[2][A] | u_la0_top/rst_ao_s0/CLK |
0.877 | 0.202 | tC2Q | RR | 53 | R2C5[2][A] | u_la0_top/rst_ao_s0/Q |
1.018 | 0.141 | tNET | RR | 1 | R2C5[0][B] | u_la0_top/internal_reg_start_dly_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.675 | 0.675 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | R2C5[0][B] | u_la0_top/internal_reg_start_dly_0_s0/CLK |
0.686 | 0.011 | tHld | 1 | R2C5[0][B] | u_la0_top/internal_reg_start_dly_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 100.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.141, 41.059%; tC2Q: 0.202, 58.941% |
Required Clock Path Delay | cell: 0.675, 100.000%; route: 0.000, 0.000% |
Path4
Path Summary:
Slack | 0.332 |
Data Arrival Time | 1.018 |
Data Required Time | 0.686 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/internal_reg_force_triger_syn_0_s0 |
Launch Clk | SYM_CLK:[R] |
Latch Clk | SYM_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.675 | 0.675 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | R2C5[2][A] | u_la0_top/rst_ao_s0/CLK |
0.877 | 0.202 | tC2Q | RR | 53 | R2C5[2][A] | u_la0_top/rst_ao_s0/Q |
1.018 | 0.141 | tNET | RR | 1 | R2C5[1][B] | u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.675 | 0.675 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | R2C5[1][B] | u_la0_top/internal_reg_force_triger_syn_0_s0/CLK |
0.686 | 0.011 | tHld | 1 | R2C5[1][B] | u_la0_top/internal_reg_force_triger_syn_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 100.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.141, 41.059%; tC2Q: 0.202, 58.941% |
Required Clock Path Delay | cell: 0.675, 100.000%; route: 0.000, 0.000% |
Path5
Path Summary:
Slack | 0.459 |
Data Arrival Time | 1.145 |
Data Required Time | 0.686 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/capture_window_sel_0_s3 |
Launch Clk | SYM_CLK:[R] |
Latch Clk | SYM_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.675 | 0.675 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | R2C5[2][A] | u_la0_top/rst_ao_s0/CLK |
0.877 | 0.202 | tC2Q | RR | 53 | R2C5[2][A] | u_la0_top/rst_ao_s0/Q |
1.145 | 0.268 | tNET | RR | 1 | R2C4[0][B] | u_la0_top/capture_window_sel_0_s3/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.675 | 0.675 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | R2C4[0][B] | u_la0_top/capture_window_sel_0_s3/CLK |
0.686 | 0.011 | tHld | 1 | R2C4[0][B] | u_la0_top/capture_window_sel_0_s3 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 100.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.268, 56.993%; tC2Q: 0.202, 43.007% |
Required Clock Path Delay | cell: 0.675, 100.000%; route: 0.000, 0.000% |
Path6
Path Summary:
Slack | 0.459 |
Data Arrival Time | 1.145 |
Data Required Time | 0.686 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/capture_window_sel_5_s1 |
Launch Clk | SYM_CLK:[R] |
Latch Clk | SYM_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.675 | 0.675 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | R2C5[2][A] | u_la0_top/rst_ao_s0/CLK |
0.877 | 0.202 | tC2Q | RR | 53 | R2C5[2][A] | u_la0_top/rst_ao_s0/Q |
1.145 | 0.268 | tNET | RR | 1 | R2C4[2][B] | u_la0_top/capture_window_sel_5_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.675 | 0.675 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | R2C4[2][B] | u_la0_top/capture_window_sel_5_s1/CLK |
0.686 | 0.011 | tHld | 1 | R2C4[2][B] | u_la0_top/capture_window_sel_5_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 100.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.268, 56.993%; tC2Q: 0.202, 43.007% |
Required Clock Path Delay | cell: 0.675, 100.000%; route: 0.000, 0.000% |
Path7
Path Summary:
Slack | 0.459 |
Data Arrival Time | 1.145 |
Data Required Time | 0.686 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/capture_window_sel_6_s1 |
Launch Clk | SYM_CLK:[R] |
Latch Clk | SYM_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.675 | 0.675 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | R2C5[2][A] | u_la0_top/rst_ao_s0/CLK |
0.877 | 0.202 | tC2Q | RR | 53 | R2C5[2][A] | u_la0_top/rst_ao_s0/Q |
1.145 | 0.268 | tNET | RR | 1 | R2C4[2][A] | u_la0_top/capture_window_sel_6_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.675 | 0.675 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | R2C4[2][A] | u_la0_top/capture_window_sel_6_s1/CLK |
0.686 | 0.011 | tHld | 1 | R2C4[2][A] | u_la0_top/capture_window_sel_6_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 100.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.268, 56.993%; tC2Q: 0.202, 43.007% |
Required Clock Path Delay | cell: 0.675, 100.000%; route: 0.000, 0.000% |
Path8
Path Summary:
Slack | 0.459 |
Data Arrival Time | 1.145 |
Data Required Time | 0.686 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/capture_window_sel_7_s1 |
Launch Clk | SYM_CLK:[R] |
Latch Clk | SYM_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.675 | 0.675 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | R2C5[2][A] | u_la0_top/rst_ao_s0/CLK |
0.877 | 0.202 | tC2Q | RR | 53 | R2C5[2][A] | u_la0_top/rst_ao_s0/Q |
1.145 | 0.268 | tNET | RR | 1 | R2C4[1][B] | u_la0_top/capture_window_sel_7_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.675 | 0.675 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | R2C4[1][B] | u_la0_top/capture_window_sel_7_s1/CLK |
0.686 | 0.011 | tHld | 1 | R2C4[1][B] | u_la0_top/capture_window_sel_7_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 100.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.268, 56.993%; tC2Q: 0.202, 43.007% |
Required Clock Path Delay | cell: 0.675, 100.000%; route: 0.000, 0.000% |
Path9
Path Summary:
Slack | 0.459 |
Data Arrival Time | 1.145 |
Data Required Time | 0.686 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/capture_window_sel_8_s1 |
Launch Clk | SYM_CLK:[R] |
Latch Clk | SYM_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.675 | 0.675 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | R2C5[2][A] | u_la0_top/rst_ao_s0/CLK |
0.877 | 0.202 | tC2Q | RR | 53 | R2C5[2][A] | u_la0_top/rst_ao_s0/Q |
1.145 | 0.268 | tNET | RR | 1 | R2C4[1][A] | u_la0_top/capture_window_sel_8_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.675 | 0.675 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | R2C4[1][A] | u_la0_top/capture_window_sel_8_s1/CLK |
0.686 | 0.011 | tHld | 1 | R2C4[1][A] | u_la0_top/capture_window_sel_8_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 100.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.268, 56.993%; tC2Q: 0.202, 43.007% |
Required Clock Path Delay | cell: 0.675, 100.000%; route: 0.000, 0.000% |
Path10
Path Summary:
Slack | 0.459 |
Data Arrival Time | 1.145 |
Data Required Time | 0.686 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/internal_reg_start_syn_1_s0 |
Launch Clk | SYM_CLK:[R] |
Latch Clk | SYM_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.675 | 0.675 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | R2C5[2][A] | u_la0_top/rst_ao_s0/CLK |
0.877 | 0.202 | tC2Q | RR | 53 | R2C5[2][A] | u_la0_top/rst_ao_s0/Q |
1.145 | 0.268 | tNET | RR | 1 | R2C4[0][A] | u_la0_top/internal_reg_start_syn_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.675 | 0.675 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | R2C4[0][A] | u_la0_top/internal_reg_start_syn_1_s0/CLK |
0.686 | 0.011 | tHld | 1 | R2C4[0][A] | u_la0_top/internal_reg_start_syn_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 100.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.268, 56.993%; tC2Q: 0.202, 43.007% |
Required Clock Path Delay | cell: 0.675, 100.000%; route: 0.000, 0.000% |
Path11
Path Summary:
Slack | 0.460 |
Data Arrival Time | 1.146 |
Data Required Time | 0.686 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_mem_ctrl/capture_length_2_s1 |
Launch Clk | SYM_CLK:[R] |
Latch Clk | SYM_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.675 | 0.675 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | R2C5[2][A] | u_la0_top/rst_ao_s0/CLK |
0.877 | 0.202 | tC2Q | RR | 53 | R2C5[2][A] | u_la0_top/rst_ao_s0/Q |
1.146 | 0.269 | tNET | RR | 1 | R3C6[0][A] | u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.675 | 0.675 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | R3C6[0][A] | u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLK |
0.686 | 0.011 | tHld | 1 | R3C6[0][A] | u_la0_top/u_ao_mem_ctrl/capture_length_2_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 100.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.269, 57.107%; tC2Q: 0.202, 42.893% |
Required Clock Path Delay | cell: 0.675, 100.000%; route: 0.000, 0.000% |
Path12
Path Summary:
Slack | 0.463 |
Data Arrival Time | 1.149 |
Data Required Time | 0.686 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_mem_ctrl/capture_length_3_s1 |
Launch Clk | SYM_CLK:[R] |
Latch Clk | SYM_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.675 | 0.675 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | R2C5[2][A] | u_la0_top/rst_ao_s0/CLK |
0.877 | 0.202 | tC2Q | RR | 53 | R2C5[2][A] | u_la0_top/rst_ao_s0/Q |
1.149 | 0.272 | tNET | RR | 1 | R3C5[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.675 | 0.675 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | R3C5[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/CLK |
0.686 | 0.011 | tHld | 1 | R3C5[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_3_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 100.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.272, 57.379%; tC2Q: 0.202, 42.621% |
Required Clock Path Delay | cell: 0.675, 100.000%; route: 0.000, 0.000% |
Path13
Path Summary:
Slack | 0.463 |
Data Arrival Time | 1.149 |
Data Required Time | 0.686 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_mem_ctrl/capture_length_0_s1 |
Launch Clk | SYM_CLK:[R] |
Latch Clk | SYM_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.675 | 0.675 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | R2C5[2][A] | u_la0_top/rst_ao_s0/CLK |
0.877 | 0.202 | tC2Q | RR | 53 | R2C5[2][A] | u_la0_top/rst_ao_s0/Q |
1.149 | 0.272 | tNET | RR | 1 | R3C5[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.675 | 0.675 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | R3C5[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLK |
0.686 | 0.011 | tHld | 1 | R3C5[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_0_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 100.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.272, 57.379%; tC2Q: 0.202, 42.621% |
Required Clock Path Delay | cell: 0.675, 100.000%; route: 0.000, 0.000% |
Path14
Path Summary:
Slack | 0.463 |
Data Arrival Time | 1.149 |
Data Required Time | 0.686 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_mem_ctrl/capture_length_9_s1 |
Launch Clk | SYM_CLK:[R] |
Latch Clk | SYM_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.675 | 0.675 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | R2C5[2][A] | u_la0_top/rst_ao_s0/CLK |
0.877 | 0.202 | tC2Q | RR | 53 | R2C5[2][A] | u_la0_top/rst_ao_s0/Q |
1.149 | 0.272 | tNET | RR | 1 | R3C5[2][A] | u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.675 | 0.675 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | R3C5[2][A] | u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLK |
0.686 | 0.011 | tHld | 1 | R3C5[2][A] | u_la0_top/u_ao_mem_ctrl/capture_length_9_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 100.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.272, 57.379%; tC2Q: 0.202, 42.621% |
Required Clock Path Delay | cell: 0.675, 100.000%; route: 0.000, 0.000% |
Path15
Path Summary:
Slack | 0.465 |
Data Arrival Time | 1.152 |
Data Required Time | 0.686 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_match_0/trig_dly_in_0_s0 |
Launch Clk | SYM_CLK:[R] |
Latch Clk | SYM_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.675 | 0.675 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | R2C5[2][A] | u_la0_top/rst_ao_s0/CLK |
0.877 | 0.202 | tC2Q | RR | 53 | R2C5[2][A] | u_la0_top/rst_ao_s0/Q |
1.152 | 0.274 | tNET | RR | 1 | R3C4[1][A] | u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.675 | 0.675 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | R3C4[1][A] | u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLK |
0.686 | 0.011 | tHld | 1 | R3C4[1][A] | u_la0_top/u_ao_match_0/trig_dly_in_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 100.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.274, 57.588%; tC2Q: 0.202, 42.412% |
Required Clock Path Delay | cell: 0.675, 100.000%; route: 0.000, 0.000% |
Path16
Path Summary:
Slack | 0.465 |
Data Arrival Time | 1.152 |
Data Required Time | 0.686 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/capture_window_sel_3_s1 |
Launch Clk | SYM_CLK:[R] |
Latch Clk | SYM_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.675 | 0.675 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | R2C5[2][A] | u_la0_top/rst_ao_s0/CLK |
0.877 | 0.202 | tC2Q | RR | 53 | R2C5[2][A] | u_la0_top/rst_ao_s0/Q |
1.152 | 0.274 | tNET | RR | 1 | R3C4[2][B] | u_la0_top/capture_window_sel_3_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.675 | 0.675 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | R3C4[2][B] | u_la0_top/capture_window_sel_3_s1/CLK |
0.686 | 0.011 | tHld | 1 | R3C4[2][B] | u_la0_top/capture_window_sel_3_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 100.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.274, 57.588%; tC2Q: 0.202, 42.412% |
Required Clock Path Delay | cell: 0.675, 100.000%; route: 0.000, 0.000% |
Path17
Path Summary:
Slack | 0.465 |
Data Arrival Time | 1.152 |
Data Required Time | 0.686 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/capture_window_sel_4_s1 |
Launch Clk | SYM_CLK:[R] |
Latch Clk | SYM_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.675 | 0.675 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | R2C5[2][A] | u_la0_top/rst_ao_s0/CLK |
0.877 | 0.202 | tC2Q | RR | 53 | R2C5[2][A] | u_la0_top/rst_ao_s0/Q |
1.152 | 0.274 | tNET | RR | 1 | R3C4[2][A] | u_la0_top/capture_window_sel_4_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.675 | 0.675 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | R3C4[2][A] | u_la0_top/capture_window_sel_4_s1/CLK |
0.686 | 0.011 | tHld | 1 | R3C4[2][A] | u_la0_top/capture_window_sel_4_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 100.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.274, 57.588%; tC2Q: 0.202, 42.412% |
Required Clock Path Delay | cell: 0.675, 100.000%; route: 0.000, 0.000% |
Path18
Path Summary:
Slack | 0.465 |
Data Arrival Time | 1.152 |
Data Required Time | 0.686 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/start_reg_s0 |
Launch Clk | SYM_CLK:[R] |
Latch Clk | SYM_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.675 | 0.675 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | R2C5[2][A] | u_la0_top/rst_ao_s0/CLK |
0.877 | 0.202 | tC2Q | RR | 53 | R2C5[2][A] | u_la0_top/rst_ao_s0/Q |
1.152 | 0.274 | tNET | RR | 1 | R3C4[1][B] | u_la0_top/start_reg_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.675 | 0.675 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | R3C4[1][B] | u_la0_top/start_reg_s0/CLK |
0.686 | 0.011 | tHld | 1 | R3C4[1][B] | u_la0_top/start_reg_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 100.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.274, 57.588%; tC2Q: 0.202, 42.412% |
Required Clock Path Delay | cell: 0.675, 100.000%; route: 0.000, 0.000% |
Path19
Path Summary:
Slack | 0.581 |
Data Arrival Time | 1.267 |
Data Required Time | 0.686 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/capture_window_sel_2_s1 |
Launch Clk | SYM_CLK:[R] |
Latch Clk | SYM_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.675 | 0.675 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | R2C5[2][A] | u_la0_top/rst_ao_s0/CLK |
0.877 | 0.202 | tC2Q | RR | 53 | R2C5[2][A] | u_la0_top/rst_ao_s0/Q |
1.267 | 0.390 | tNET | RR | 1 | R4C3[0][A] | u_la0_top/capture_window_sel_2_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.675 | 0.675 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | R4C3[0][A] | u_la0_top/capture_window_sel_2_s1/CLK |
0.686 | 0.011 | tHld | 1 | R4C3[0][A] | u_la0_top/capture_window_sel_2_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 100.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.390, 65.860%; tC2Q: 0.202, 34.140% |
Required Clock Path Delay | cell: 0.675, 100.000%; route: 0.000, 0.000% |
Path20
Path Summary:
Slack | 0.581 |
Data Arrival Time | 1.267 |
Data Required Time | 0.686 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/triger_level_cnt_2_s1 |
Launch Clk | SYM_CLK:[R] |
Latch Clk | SYM_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.675 | 0.675 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | R2C5[2][A] | u_la0_top/rst_ao_s0/CLK |
0.877 | 0.202 | tC2Q | RR | 53 | R2C5[2][A] | u_la0_top/rst_ao_s0/Q |
1.267 | 0.390 | tNET | RR | 1 | R4C3[2][B] | u_la0_top/triger_level_cnt_2_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.675 | 0.675 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | R4C3[2][B] | u_la0_top/triger_level_cnt_2_s1/CLK |
0.686 | 0.011 | tHld | 1 | R4C3[2][B] | u_la0_top/triger_level_cnt_2_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 100.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.390, 65.860%; tC2Q: 0.202, 34.140% |
Required Clock Path Delay | cell: 0.675, 100.000%; route: 0.000, 0.000% |
Path21
Path Summary:
Slack | 0.581 |
Data Arrival Time | 1.267 |
Data Required Time | 0.686 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/triger_level_cnt_3_s1 |
Launch Clk | SYM_CLK:[R] |
Latch Clk | SYM_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.675 | 0.675 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | R2C5[2][A] | u_la0_top/rst_ao_s0/CLK |
0.877 | 0.202 | tC2Q | RR | 53 | R2C5[2][A] | u_la0_top/rst_ao_s0/Q |
1.267 | 0.390 | tNET | RR | 1 | R4C3[2][A] | u_la0_top/triger_level_cnt_3_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.675 | 0.675 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | R4C3[2][A] | u_la0_top/triger_level_cnt_3_s1/CLK |
0.686 | 0.011 | tHld | 1 | R4C3[2][A] | u_la0_top/triger_level_cnt_3_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 100.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.390, 65.860%; tC2Q: 0.202, 34.140% |
Required Clock Path Delay | cell: 0.675, 100.000%; route: 0.000, 0.000% |
Path22
Path Summary:
Slack | 0.581 |
Data Arrival Time | 1.267 |
Data Required Time | 0.686 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/triger_s0 |
Launch Clk | SYM_CLK:[R] |
Latch Clk | SYM_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.675 | 0.675 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | R2C5[2][A] | u_la0_top/rst_ao_s0/CLK |
0.877 | 0.202 | tC2Q | RR | 53 | R2C5[2][A] | u_la0_top/rst_ao_s0/Q |
1.267 | 0.390 | tNET | RR | 1 | R4C3[1][A] | u_la0_top/triger_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.675 | 0.675 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | R4C3[1][A] | u_la0_top/triger_s0/CLK |
0.686 | 0.011 | tHld | 1 | R4C3[1][A] | u_la0_top/triger_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 100.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.390, 65.860%; tC2Q: 0.202, 34.140% |
Required Clock Path Delay | cell: 0.675, 100.000%; route: 0.000, 0.000% |
Path23
Path Summary:
Slack | 0.581 |
Data Arrival Time | 1.267 |
Data Required Time | 0.686 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/internal_reg_start_syn_0_s0 |
Launch Clk | SYM_CLK:[R] |
Latch Clk | SYM_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.675 | 0.675 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | R2C5[2][A] | u_la0_top/rst_ao_s0/CLK |
0.877 | 0.202 | tC2Q | RR | 53 | R2C5[2][A] | u_la0_top/rst_ao_s0/Q |
1.267 | 0.390 | tNET | RR | 1 | R4C3[1][B] | u_la0_top/internal_reg_start_syn_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.675 | 0.675 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | R4C3[1][B] | u_la0_top/internal_reg_start_syn_0_s0/CLK |
0.686 | 0.011 | tHld | 1 | R4C3[1][B] | u_la0_top/internal_reg_start_syn_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 100.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.390, 65.860%; tC2Q: 0.202, 34.140% |
Required Clock Path Delay | cell: 0.675, 100.000%; route: 0.000, 0.000% |
Path24
Path Summary:
Slack | 0.585 |
Data Arrival Time | 1.271 |
Data Required Time | 0.686 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/u_ao_match_0/match_sep_s0 |
Launch Clk | SYM_CLK:[R] |
Latch Clk | SYM_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.675 | 0.675 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | R2C5[2][A] | u_la0_top/rst_ao_s0/CLK |
0.877 | 0.202 | tC2Q | RR | 53 | R2C5[2][A] | u_la0_top/rst_ao_s0/Q |
1.271 | 0.394 | tNET | RR | 1 | R5C3[1][B] | u_la0_top/u_ao_match_0/match_sep_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.675 | 0.675 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | R5C3[1][B] | u_la0_top/u_ao_match_0/match_sep_s0/CLK |
0.686 | 0.011 | tHld | 1 | R5C3[1][B] | u_la0_top/u_ao_match_0/match_sep_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 100.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.394, 66.104%; tC2Q: 0.202, 33.896% |
Required Clock Path Delay | cell: 0.675, 100.000%; route: 0.000, 0.000% |
Path25
Path Summary:
Slack | 0.585 |
Data Arrival Time | 1.271 |
Data Required Time | 0.686 |
From | u_la0_top/rst_ao_s0 |
To | u_la0_top/internal_reg_force_triger_syn_1_s0 |
Launch Clk | SYM_CLK:[R] |
Latch Clk | SYM_CLK:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.675 | 0.675 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | R2C5[2][A] | u_la0_top/rst_ao_s0/CLK |
0.877 | 0.202 | tC2Q | RR | 53 | R2C5[2][A] | u_la0_top/rst_ao_s0/Q |
1.271 | 0.394 | tNET | RR | 1 | R5C3[1][A] | u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | SYM_CLK | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR44[A] | SYM_CLK_ibuf/I |
0.675 | 0.675 | tINS | RR | 932 | IOR44[A] | SYM_CLK_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | R5C3[1][A] | u_la0_top/internal_reg_force_triger_syn_1_s0/CLK |
0.686 | 0.011 | tHld | 1 | R5C3[1][A] | u_la0_top/internal_reg_force_triger_syn_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 100.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.394, 66.104%; tC2Q: 0.202, 33.896% |
Required Clock Path Delay | cell: 0.675, 100.000%; route: 0.000, 0.000% |
Minimum Pulse Width Report:
Report Command:report_min_pulse_width -nworst 10 -detail
MPW1
MPW Summary:
Slack: | 3.911 |
Actual Width: | 4.911 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | SYM_CLK |
Objects: | cycle_cnt_5_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | SYM_CLK | ||
5.000 | 0.000 | tCL | FF | SYM_CLK_ibuf/I |
5.688 | 0.688 | tINS | FF | SYM_CLK_ibuf/O |
5.949 | 0.261 | tNET | FF | cycle_cnt_5_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | SYM_CLK | ||
10.000 | 0.000 | tCL | RR | SYM_CLK_ibuf/I |
10.675 | 0.675 | tINS | RR | SYM_CLK_ibuf/O |
10.860 | 0.184 | tNET | RR | cycle_cnt_5_s0/CLK |
MPW2
MPW Summary:
Slack: | 3.911 |
Actual Width: | 4.911 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | SYM_CLK |
Objects: | cycle_cnt_3_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | SYM_CLK | ||
5.000 | 0.000 | tCL | FF | SYM_CLK_ibuf/I |
5.688 | 0.688 | tINS | FF | SYM_CLK_ibuf/O |
5.949 | 0.261 | tNET | FF | cycle_cnt_3_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | SYM_CLK | ||
10.000 | 0.000 | tCL | RR | SYM_CLK_ibuf/I |
10.675 | 0.675 | tINS | RR | SYM_CLK_ibuf/O |
10.860 | 0.184 | tNET | RR | cycle_cnt_3_s0/CLK |
MPW3
MPW Summary:
Slack: | 3.911 |
Actual Width: | 4.911 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | SYM_CLK |
Objects: | din_7_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | SYM_CLK | ||
5.000 | 0.000 | tCL | FF | SYM_CLK_ibuf/I |
5.688 | 0.688 | tINS | FF | SYM_CLK_ibuf/O |
5.949 | 0.261 | tNET | FF | din_7_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | SYM_CLK | ||
10.000 | 0.000 | tCL | RR | SYM_CLK_ibuf/I |
10.675 | 0.675 | tINS | RR | SYM_CLK_ibuf/O |
10.860 | 0.184 | tNET | RR | din_7_s0/CLK |
MPW4
MPW Summary:
Slack: | 3.911 |
Actual Width: | 4.911 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | SYM_CLK |
Objects: | noise_7_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | SYM_CLK | ||
5.000 | 0.000 | tCL | FF | SYM_CLK_ibuf/I |
5.688 | 0.688 | tINS | FF | SYM_CLK_ibuf/O |
5.949 | 0.261 | tNET | FF | noise_7_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | SYM_CLK | ||
10.000 | 0.000 | tCL | RR | SYM_CLK_ibuf/I |
10.675 | 0.675 | tINS | RR | SYM_CLK_ibuf/O |
10.860 | 0.184 | tNET | RR | noise_7_s0/CLK |
MPW5
MPW Summary:
Slack: | 3.911 |
Actual Width: | 4.911 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | SYM_CLK |
Objects: | RS_Encoder_Top/RS_Encoder/data_in_shift_40_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | SYM_CLK | ||
5.000 | 0.000 | tCL | FF | SYM_CLK_ibuf/I |
5.688 | 0.688 | tINS | FF | SYM_CLK_ibuf/O |
5.949 | 0.261 | tNET | FF | RS_Encoder_Top/RS_Encoder/data_in_shift_40_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | SYM_CLK | ||
10.000 | 0.000 | tCL | RR | SYM_CLK_ibuf/I |
10.675 | 0.675 | tINS | RR | SYM_CLK_ibuf/O |
10.860 | 0.184 | tNET | RR | RS_Encoder_Top/RS_Encoder/data_in_shift_40_s0/CLK |
MPW6
MPW Summary:
Slack: | 3.911 |
Actual Width: | 4.911 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | SYM_CLK |
Objects: | RS_Encoder_Top/RS_Encoder/data_in_shift_8_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | SYM_CLK | ||
5.000 | 0.000 | tCL | FF | SYM_CLK_ibuf/I |
5.688 | 0.688 | tINS | FF | SYM_CLK_ibuf/O |
5.949 | 0.261 | tNET | FF | RS_Encoder_Top/RS_Encoder/data_in_shift_8_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | SYM_CLK | ||
10.000 | 0.000 | tCL | RR | SYM_CLK_ibuf/I |
10.675 | 0.675 | tINS | RR | SYM_CLK_ibuf/O |
10.860 | 0.184 | tNET | RR | RS_Encoder_Top/RS_Encoder/data_in_shift_8_s0/CLK |
MPW7
MPW Summary:
Slack: | 3.911 |
Actual Width: | 4.911 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | SYM_CLK |
Objects: | RS_Encoder_Top/RS_Encoder/R_out_10_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | SYM_CLK | ||
5.000 | 0.000 | tCL | FF | SYM_CLK_ibuf/I |
5.688 | 0.688 | tINS | FF | SYM_CLK_ibuf/O |
5.949 | 0.261 | tNET | FF | RS_Encoder_Top/RS_Encoder/R_out_10_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | SYM_CLK | ||
10.000 | 0.000 | tCL | RR | SYM_CLK_ibuf/I |
10.675 | 0.675 | tINS | RR | SYM_CLK_ibuf/O |
10.860 | 0.184 | tNET | RR | RS_Encoder_Top/RS_Encoder/R_out_10_s0/CLK |
MPW8
MPW Summary:
Slack: | 3.911 |
Actual Width: | 4.911 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | SYM_CLK |
Objects: | RS_Decoder_Top/RS_Decoder/RS_Syndrome/syndrome_reg_17_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | SYM_CLK | ||
5.000 | 0.000 | tCL | FF | SYM_CLK_ibuf/I |
5.688 | 0.688 | tINS | FF | SYM_CLK_ibuf/O |
5.949 | 0.261 | tNET | FF | RS_Decoder_Top/RS_Decoder/RS_Syndrome/syndrome_reg_17_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | SYM_CLK | ||
10.000 | 0.000 | tCL | RR | SYM_CLK_ibuf/I |
10.675 | 0.675 | tINS | RR | SYM_CLK_ibuf/O |
10.860 | 0.184 | tNET | RR | RS_Decoder_Top/RS_Decoder/RS_Syndrome/syndrome_reg_17_s0/CLK |
MPW9
MPW Summary:
Slack: | 3.911 |
Actual Width: | 4.911 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | SYM_CLK |
Objects: | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_reg_14_s3 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | SYM_CLK | ||
5.000 | 0.000 | tCL | FF | SYM_CLK_ibuf/I |
5.688 | 0.688 | tINS | FF | SYM_CLK_ibuf/O |
5.949 | 0.261 | tNET | FF | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_reg_14_s3/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | SYM_CLK | ||
10.000 | 0.000 | tCL | RR | SYM_CLK_ibuf/I |
10.675 | 0.675 | tINS | RR | SYM_CLK_ibuf/O |
10.860 | 0.184 | tNET | RR | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_reg_14_s3/CLK |
MPW10
MPW Summary:
Slack: | 3.911 |
Actual Width: | 4.911 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | SYM_CLK |
Objects: | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_reg_15_s3 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | SYM_CLK | ||
5.000 | 0.000 | tCL | FF | SYM_CLK_ibuf/I |
5.688 | 0.688 | tINS | FF | SYM_CLK_ibuf/O |
5.949 | 0.261 | tNET | FF | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_reg_15_s3/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | SYM_CLK | ||
10.000 | 0.000 | tCL | RR | SYM_CLK_ibuf/I |
10.675 | 0.675 | tINS | RR | SYM_CLK_ibuf/O |
10.860 | 0.184 | tNET | RR | RS_Decoder_Top/RS_Decoder/RS_Key_Equation/Lamda_reg_15_s3/CLK |
High Fanout Nets Report:
Report Command:report_high_fanout_nets -max_nets 10
FANOUT | NET NAME | WORST SLACK | MAX DELAY |
---|---|---|---|
932 | SYM_CLK_d | 1.760 | 0.261 |
247 | syndrome_valid_Z | 6.259 | 1.523 |
125 | Lamda_ov[4] | 3.280 | 1.596 |
124 | Lamda_ov[5] | 3.367 | 1.263 |
112 | Lamda_ov[6] | 3.349 | 1.341 |
111 | Lamda_ov[7] | 3.256 | 1.972 |
95 | syndrome_reg_47_45 | 5.742 | 1.468 |
77 | Lamda_valid | 6.481 | 1.848 |
64 | Lamda_ov[3] | 4.599 | 2.682 |
40 | B_tmp_39_7 | 6.750 | 1.915 |
Route Congestions Report:
Report Command:report_route_congestion -max_grids 10
GRID LOC | ROUTE CONGESTIONS |
---|---|
R46C47 | 69.44% |
R41C47 | 61.11% |
R46C48 | 61.11% |
R41C36 | 56.94% |
R43C49 | 56.94% |
R47C49 | 55.56% |
R43C47 | 55.56% |
R43C48 | 55.56% |
R42C38 | 55.56% |
R46C46 | 54.17% |
Timing Exceptions Report:
Setup Analysis Report
Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Hold Analysis Report
Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Recovery Analysis Report
Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Removal Analysis Report
Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Timing Constraints Report:
SDC Command Type | State | Detail Command |
---|