Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\RS_EN_DE_CODER\data\enc\RS_Encoder_top.v C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\RS_EN_DE_CODER\data\enc\RS_Encoder_top_wrap.v |
GowinSynthesis Constraints File | --- |
Tool Version | V1.9.9.01 (64-bit) |
Part Number | GW2A-LV55PG484C8/I7 |
Device | GW2A-55 |
Device Version | C |
Created Time | Tue Dec 26 10:15:35 2023 |
Legal Announcement | Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | RS_Encoder_Top |
Synthesis Process | Running parser: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.122s, Peak memory usage = 42.652MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 42.652MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 42.652MB Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 42.652MB Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 42.652MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 42.652MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 42.652MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 42.652MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 42.652MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 42.652MB Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 42.652MB Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 42.652MB Tech-Mapping Phase 3: CPU time = 0h 0m 0.437s, Elapsed time = 0h 0m 0.487s, Peak memory usage = 71.547MB Tech-Mapping Phase 4: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 71.547MB Generate output files: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 71.547MB |
Total Time and Memory Usage | CPU time = 0h 0m 0.576s, Elapsed time = 0h 0m 0.662s, Peak memory usage = 71.547MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 25 |
I/O Buf | 25 |
    IBUF | 13 |
    OBUF | 12 |
Register | 157 |
    DFFC | 117 |
    DFFCE | 40 |
LUT | 124 |
    LUT2 | 18 |
    LUT3 | 49 |
    LUT4 | 57 |
INV | 1 |
    INV | 1 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 125(125 LUT, 0 ALU) / 54720 | <1% |
Register | 157 / 41997 | <1% |
  --Register as Latch | 0 / 41997 | 0% |
  --Register as FF | 157 / 41997 | <1% |
BSRAM | 0 / 140 | 0% |
Timing
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|
clk | Base | 10.000 | 100.0 | 0.000 | 5.000 | clk_ibuf/I |
Max Frequency Summary:
No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | clk | 100.0(MHz) | 347.2(MHz) | 4 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | 7.120 |
Data Arrival Time | 3.708 |
Data Required Time | 10.828 |
From | RS_Encoder/B_tmp_33_s1 |
To | RS_Encoder/B_tmp_17_s1 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 157 | clk_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | RS_Encoder/B_tmp_33_s1/CLK |
1.095 | 0.232 | tC2Q | RF | 15 | RS_Encoder/B_tmp_33_s1/Q |
1.332 | 0.237 | tNET | FF | 1 | RS_Encoder/n243_s2/I1 |
1.887 | 0.555 | tINS | FF | 2 | RS_Encoder/n243_s2/F |
2.124 | 0.237 | tNET | FF | 1 | RS_Encoder/n248_s1/I1 |
2.679 | 0.555 | tINS | FF | 2 | RS_Encoder/n248_s1/F |
2.916 | 0.237 | tNET | FF | 1 | RS_Encoder/n248_s0/I1 |
3.471 | 0.555 | tINS | FF | 1 | RS_Encoder/n248_s0/F |
3.708 | 0.237 | tNET | FF | 1 | RS_Encoder/B_tmp_17_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk | |||
10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 157 | clk_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | RS_Encoder/B_tmp_17_s1/CLK |
10.828 | -0.035 | tSu | 1 | RS_Encoder/B_tmp_17_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 4 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 1.665, 58.523%; route: 0.948, 33.322%; tC2Q: 0.232, 8.155% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 2
Path Summary:Slack | 7.120 |
Data Arrival Time | 3.708 |
Data Required Time | 10.828 |
From | RS_Encoder/B_tmp_33_s1 |
To | RS_Encoder/B_tmp_20_s1 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 157 | clk_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | RS_Encoder/B_tmp_33_s1/CLK |
1.095 | 0.232 | tC2Q | RF | 15 | RS_Encoder/B_tmp_33_s1/Q |
1.332 | 0.237 | tNET | FF | 1 | RS_Encoder/n241_s1/I1 |
1.887 | 0.555 | tINS | FF | 3 | RS_Encoder/n241_s1/F |
2.124 | 0.237 | tNET | FF | 1 | RS_Encoder/n245_s1/I1 |
2.679 | 0.555 | tINS | FF | 2 | RS_Encoder/n245_s1/F |
2.916 | 0.237 | tNET | FF | 1 | RS_Encoder/n245_s0/I1 |
3.471 | 0.555 | tINS | FF | 1 | RS_Encoder/n245_s0/F |
3.708 | 0.237 | tNET | FF | 1 | RS_Encoder/B_tmp_20_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk | |||
10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 157 | clk_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | RS_Encoder/B_tmp_20_s1/CLK |
10.828 | -0.035 | tSu | 1 | RS_Encoder/B_tmp_20_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 4 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 1.665, 58.523%; route: 0.948, 33.322%; tC2Q: 0.232, 8.155% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 3
Path Summary:Slack | 7.120 |
Data Arrival Time | 3.708 |
Data Required Time | 10.828 |
From | RS_Encoder/B_tmp_35_s1 |
To | RS_Encoder/B_tmp_21_s1 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 157 | clk_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | RS_Encoder/B_tmp_35_s1/CLK |
1.095 | 0.232 | tC2Q | RF | 11 | RS_Encoder/B_tmp_35_s1/Q |
1.332 | 0.237 | tNET | FF | 1 | RS_Encoder/n228_s1/I1 |
1.887 | 0.555 | tINS | FF | 6 | RS_Encoder/n228_s1/F |
2.124 | 0.237 | tNET | FF | 1 | RS_Encoder/n244_s1/I1 |
2.679 | 0.555 | tINS | FF | 2 | RS_Encoder/n244_s1/F |
2.916 | 0.237 | tNET | FF | 1 | RS_Encoder/n244_s0/I1 |
3.471 | 0.555 | tINS | FF | 1 | RS_Encoder/n244_s0/F |
3.708 | 0.237 | tNET | FF | 1 | RS_Encoder/B_tmp_21_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk | |||
10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 157 | clk_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | RS_Encoder/B_tmp_21_s1/CLK |
10.828 | -0.035 | tSu | 1 | RS_Encoder/B_tmp_21_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 4 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 1.665, 58.523%; route: 0.948, 33.322%; tC2Q: 0.232, 8.155% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 4
Path Summary:Slack | 7.120 |
Data Arrival Time | 3.708 |
Data Required Time | 10.828 |
From | RS_Encoder/B_tmp_32_s1 |
To | RS_Encoder/B_tmp_23_s1 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 157 | clk_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | RS_Encoder/B_tmp_32_s1/CLK |
1.095 | 0.232 | tC2Q | RF | 16 | RS_Encoder/B_tmp_32_s1/Q |
1.332 | 0.237 | tNET | FF | 1 | RS_Encoder/n230_s2/I1 |
1.887 | 0.555 | tINS | FF | 4 | RS_Encoder/n230_s2/F |
2.124 | 0.237 | tNET | FF | 1 | RS_Encoder/n242_s1/I1 |
2.679 | 0.555 | tINS | FF | 2 | RS_Encoder/n242_s1/F |
2.916 | 0.237 | tNET | FF | 1 | RS_Encoder/n242_s0/I1 |
3.471 | 0.555 | tINS | FF | 1 | RS_Encoder/n242_s0/F |
3.708 | 0.237 | tNET | FF | 1 | RS_Encoder/B_tmp_23_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk | |||
10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 157 | clk_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | RS_Encoder/B_tmp_23_s1/CLK |
10.828 | -0.035 | tSu | 1 | RS_Encoder/B_tmp_23_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 4 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 1.665, 58.523%; route: 0.948, 33.322%; tC2Q: 0.232, 8.155% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 5
Path Summary:Slack | 7.120 |
Data Arrival Time | 3.708 |
Data Required Time | 10.828 |
From | RS_Encoder/B_tmp_36_s1 |
To | RS_Encoder/B_tmp_36_s1 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 157 | clk_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | RS_Encoder/B_tmp_36_s1/CLK |
1.095 | 0.232 | tC2Q | RF | 11 | RS_Encoder/B_tmp_36_s1/Q |
1.332 | 0.237 | tNET | FF | 1 | RS_Encoder/n247_s1/I1 |
1.887 | 0.555 | tINS | FF | 3 | RS_Encoder/n247_s1/F |
2.124 | 0.237 | tNET | FF | 1 | RS_Encoder/n229_s1/I1 |
2.679 | 0.555 | tINS | FF | 2 | RS_Encoder/n229_s1/F |
2.916 | 0.237 | tNET | FF | 1 | RS_Encoder/n229_s0/I1 |
3.471 | 0.555 | tINS | FF | 1 | RS_Encoder/n229_s0/F |
3.708 | 0.237 | tNET | FF | 1 | RS_Encoder/B_tmp_36_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk | |||
10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 157 | clk_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | RS_Encoder/B_tmp_36_s1/CLK |
10.828 | -0.035 | tSu | 1 | RS_Encoder/B_tmp_36_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 4 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 1.665, 58.523%; route: 0.948, 33.322%; tC2Q: 0.232, 8.155% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |