Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | C:\Gowin\Gowin_V1.9.9.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v C:\Gowin\Gowin_V1.9.9.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v C:\Gowin\Gowin_V1.9.9.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v C:\Gowin\Gowin_V1.9.9.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v C:\Gowin\Gowin_V1.9.9.01_x64\IDE\data\ipcores\GAO\GW_CON\gw_con_top.v C:\Gowin\Gowin_V1.9.9.01_x64\IDE\data\ipcores\gw_jtag.v E:\W_File\RS_Code\Onboard\RS_Code_Ref_Design\fpga_project\impl\gao\gw_gao_top.v |
GowinSynthesis Constraints File | --- |
Tool Version | V1.9.9.01 (64-bit) |
Part Number | GW2A-LV55PG484C8/I7 |
Device | GW2A-55 |
Device Version | C |
Created Time | Tue Dec 26 10:16:25 2023 |
Legal Announcement | Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | gw_gao |
Synthesis Process | Running parser: CPU time = 0h 0m 0.265s, Elapsed time = 0h 0m 0.265s, Peak memory usage = 42.988MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 42.988MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.027s, Peak memory usage = 42.988MB Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 42.988MB Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.03s, Peak memory usage = 42.988MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 42.988MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 42.988MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 42.988MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 42.988MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.024s, Peak memory usage = 42.988MB Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 42.988MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 42.988MB Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 72.246MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.048s, Peak memory usage = 72.246MB Generate output files: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.029s, Peak memory usage = 72.246MB |
Total Time and Memory Usage | CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 72.246MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 53 |
I/O Buf | 53 |
    IBUF | 52 |
    OBUF | 1 |
Register | 428 |
    DFF | 103 |
    DFFR | 1 |
    DFFP | 3 |
    DFFPE | 33 |
    DFFC | 25 |
    DFFCE | 263 |
LUT | 442 |
    LUT2 | 68 |
    LUT3 | 108 |
    LUT4 | 266 |
MUX | 1 |
    MUX16 | 1 |
ALU | 13 |
    ALU | 13 |
INV | 4 |
    INV | 4 |
BSRAM | 3 |
    SDPX9B | 3 |
Black Box | 1 |
    GW_JTAG | 1 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 467(454 LUT, 13 ALU) / 54720 | <1% |
Register | 428 / 41997 | 2% |
  --Register as Latch | 0 / 41997 | 0% |
  --Register as FF | 428 / 41997 | 2% |
BSRAM | 3 / 140 | 3% |
Timing
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|
SYM_CLK | Base | 10.000 | 100.0 | 0.000 | 5.000 | SYM_CLK_ibuf/I | ||
u_icon_top/n19_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 | u_icon_top/n19_s2/O | ||
u_la0_top/n15_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 | u_la0_top/n15_s2/O |
Max Frequency Summary:
No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | SYM_CLK | 100.0(MHz) | 275.2(MHz) | 5 | TOP |
2 | u_icon_top/n19_6 | 100.0(MHz) | 1984.1(MHz) | 1 | TOP |
3 | u_la0_top/n15_6 | 100.0(MHz) | 1984.1(MHz) | 1 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | 6.366 |
Data Arrival Time | 4.462 |
Data Required Time | 10.828 |
From | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1 |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1 |
Launch Clk | SYM_CLK[R] |
Latch Clk | SYM_CLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | SYM_CLK | |||
0.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 158 | SYM_CLK_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK |
1.095 | 0.232 | tC2Q | RF | 8 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/Q |
1.332 | 0.237 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/n450_s2/I1 |
1.887 | 0.555 | tINS | FF | 4 | u_la0_top/u_ao_mem_ctrl/n450_s2/F |
2.124 | 0.237 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/n446_s2/I1 |
2.679 | 0.555 | tINS | FF | 2 | u_la0_top/u_ao_mem_ctrl/n446_s2/F |
2.916 | 0.237 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/n445_s3/I1 |
3.471 | 0.555 | tINS | FF | 1 | u_la0_top/u_ao_mem_ctrl/n445_s3/F |
3.708 | 0.237 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/n445_s2/I0 |
4.225 | 0.517 | tINS | FF | 1 | u_la0_top/u_ao_mem_ctrl/n445_s2/F |
4.462 | 0.237 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | SYM_CLK | |||
10.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 158 | SYM_CLK_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK |
10.828 | -0.035 | tSu | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 2.182, 60.628%; route: 1.185, 32.926%; tC2Q: 0.232, 6.446% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 2
Path Summary:Slack | 6.467 |
Data Arrival Time | 4.360 |
Data Required Time | 10.828 |
From | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1 |
To | u_la0_top/u_ao_mem_ctrl/capture_loop_s1 |
Launch Clk | SYM_CLK[R] |
Latch Clk | SYM_CLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | SYM_CLK | |||
0.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 158 | SYM_CLK_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK |
1.095 | 0.232 | tC2Q | RF | 5 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/Q |
1.332 | 0.237 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/n445_s8/I0 |
1.849 | 0.517 | tINS | FF | 1 | u_la0_top/u_ao_mem_ctrl/n445_s8/F |
2.086 | 0.237 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/n445_s5/I1 |
2.641 | 0.555 | tINS | FF | 2 | u_la0_top/u_ao_mem_ctrl/n445_s5/F |
2.878 | 0.237 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/n445_s4/I0 |
3.395 | 0.517 | tINS | FF | 10 | u_la0_top/u_ao_mem_ctrl/n445_s4/F |
3.632 | 0.237 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/capture_loop_s4/I0 |
4.181 | 0.549 | tINS | FR | 1 | u_la0_top/u_ao_mem_ctrl/capture_loop_s4/F |
4.360 | 0.180 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | SYM_CLK | |||
10.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 158 | SYM_CLK_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK |
10.828 | -0.035 | tSu | 1 | u_la0_top/u_ao_mem_ctrl/capture_loop_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 2.138, 61.121%; route: 1.128, 32.247%; tC2Q: 0.232, 6.632% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 3
Path Summary:Slack | 6.468 |
Data Arrival Time | 4.360 |
Data Required Time | 10.828 |
From | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1 |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1 |
Launch Clk | SYM_CLK[R] |
Latch Clk | SYM_CLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | SYM_CLK | |||
0.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 158 | SYM_CLK_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK |
1.095 | 0.232 | tC2Q | RF | 8 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/Q |
1.332 | 0.237 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/n450_s2/I1 |
1.887 | 0.555 | tINS | FF | 4 | u_la0_top/u_ao_mem_ctrl/n450_s2/F |
2.124 | 0.237 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/n449_s2/I1 |
2.679 | 0.555 | tINS | FF | 2 | u_la0_top/u_ao_mem_ctrl/n449_s2/F |
2.916 | 0.237 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/n447_s2/I2 |
3.369 | 0.453 | tINS | FF | 1 | u_la0_top/u_ao_mem_ctrl/n447_s2/F |
3.606 | 0.237 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/n447_s1/I0 |
4.123 | 0.517 | tINS | FF | 1 | u_la0_top/u_ao_mem_ctrl/n447_s1/F |
4.360 | 0.237 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | SYM_CLK | |||
10.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 158 | SYM_CLK_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK |
10.828 | -0.035 | tSu | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 2.080, 59.480%; route: 1.185, 33.886%; tC2Q: 0.232, 6.634% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 4
Path Summary:Slack | 6.468 |
Data Arrival Time | 4.359 |
Data Required Time | 10.828 |
From | u_la0_top/capture_window_sel_0_s3 |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_9_s0 |
Launch Clk | SYM_CLK[R] |
Latch Clk | SYM_CLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | SYM_CLK | |||
0.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 158 | SYM_CLK_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | u_la0_top/capture_window_sel_0_s3/CLK |
1.095 | 0.232 | tC2Q | RF | 14 | u_la0_top/capture_window_sel_0_s3/Q |
1.332 | 0.237 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s17/I1 |
1.887 | 0.555 | tINS | FF | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s17/F |
2.124 | 0.237 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s15/I1 |
2.679 | 0.555 | tINS | FF | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s15/F |
2.916 | 0.237 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s12/I0 |
3.433 | 0.517 | tINS | FF | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s12/F |
3.670 | 0.237 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s10/I2 |
4.122 | 0.453 | tINS | FF | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s10/F |
4.359 | 0.237 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_9_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | SYM_CLK | |||
10.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 158 | SYM_CLK_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_9_s0/CLK |
10.828 | -0.035 | tSu | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_9_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 2.080, 59.480%; route: 1.185, 33.886%; tC2Q: 0.232, 6.634% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 5
Path Summary:Slack | 6.506 |
Data Arrival Time | 4.321 |
Data Required Time | 10.828 |
From | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1 |
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1 |
Launch Clk | SYM_CLK[R] |
Latch Clk | SYM_CLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | SYM_CLK | |||
0.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 158 | SYM_CLK_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK |
1.095 | 0.232 | tC2Q | RF | 5 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/Q |
1.332 | 0.237 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/n445_s8/I0 |
1.849 | 0.517 | tINS | FF | 1 | u_la0_top/u_ao_mem_ctrl/n445_s8/F |
2.086 | 0.237 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/n445_s5/I1 |
2.641 | 0.555 | tINS | FF | 2 | u_la0_top/u_ao_mem_ctrl/n445_s5/F |
2.878 | 0.237 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/n445_s4/I0 |
3.395 | 0.517 | tINS | FF | 10 | u_la0_top/u_ao_mem_ctrl/n445_s4/F |
3.632 | 0.237 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/n453_s1/I2 |
4.084 | 0.453 | tINS | FF | 1 | u_la0_top/u_ao_mem_ctrl/n453_s1/F |
4.321 | 0.237 | tNET | FF | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | SYM_CLK | |||
10.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 158 | SYM_CLK_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK |
10.828 | -0.035 | tSu | 1 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 2.042, 59.035%; route: 1.185, 34.258%; tC2Q: 0.232, 6.707% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |