Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\SERDES_IP\IPlib\RORALINK\data\RoraLink_64B66B_Top.v
C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\SERDES_IP\IPlib\RORALINK\data\RoraLink_64B66B_Core_encryption.v
GowinSynthesis Constraints File ---
Tool Version V1.9.9.01 (64-bit)
Part Number GW5AST-LV138FPG676AC2/I1
Device GW5AST-138
Device Version B
Created Time Fri Jan 12 16:15:06 2024
Legal Announcement Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module RoraLink_64B66B_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.875s, Elapsed time = 0h 0m 0.95s, Peak memory usage = 108.727MB
Running netlist conversion:
    CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.064s, Peak memory usage = 108.727MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.213s, Peak memory usage = 108.727MB
    Optimizing Phase 1: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.118s, Peak memory usage = 108.727MB
    Optimizing Phase 2: CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.21s, Peak memory usage = 108.727MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.081s, Peak memory usage = 108.727MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 108.727MB
    Inferring Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.037s, Peak memory usage = 108.727MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 108.727MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.222s, Peak memory usage = 108.727MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.06s, Peak memory usage = 108.727MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.034s, Peak memory usage = 108.727MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 118.531MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.226s, Peak memory usage = 118.531MB
Generate output files:
    CPU time = 0h 0m 0.296s, Elapsed time = 0h 0m 0.346s, Peak memory usage = 136.375MB
Total Time and Memory Usage CPU time = 0h 0m 5s, Elapsed time = 0h 0m 5s, Peak memory usage = 136.375MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 659
I/O Buf 625
    IBUF 296
    OBUF 329
Register 5032
    DFFSE 258
    DFFRE 3746
    DFFPE 9
    DFFCE 1019
LUT 4757
    LUT1 64
    LUT2 428
    LUT3 1789
    LUT4 1856
    LUT5 172
    LUT6 448
ALU 292
    ALU 292
INV 50
    INV 50
BSRAM 2
    SDPX9B 2

Resource Utilization Summary

Resource Usage Utilization
Logic 6615(6323 LUT, 292 ALU) / 138240 5%
Register 5032 / 139140 4%
  --Register as Latch 0 / 139140 0%
  --Register as FF 5032 / 139140 4%
BSRAM 2 / 340 <1%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
sys_clk_i Base 10.000 100.0 0.000 5.000 sys_clk_i_ibuf/I
serdes_lanex_pcs_rx_fabric_clk_i[0] Base 10.000 100.0 0.000 5.000 serdes_lanex_pcs_rx_fabric_clk_i_0_ibuf/I
init_clk_i Base 10.000 100.0 0.000 5.000 init_clk_i_ibuf/I

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 sys_clk_i 100.0(MHz) 186.7(MHz) 7 TOP
2 serdes_lanex_pcs_rx_fabric_clk_i[0] 100.0(MHz) 358.0(MHz) 5 TOP
3 init_clk_i 100.0(MHz) 393.9(MHz) 4 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 4.645
Data Arrival Time 6.056
Data Required Time 10.701
From u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/crc_data_i_reg[42]
To u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/crcreg_reg[3]
Launch Clk sys_clk_i[R]
Latch Clk sys_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 sys_clk_i
0.000 0.000 tCL RR 1 sys_clk_i_ibuf/I
0.587 0.587 tINS RR 2861 sys_clk_i_ibuf/O
0.752 0.165 tNET RR 1 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/crc_data_i_reg[42]/CLK
1.058 0.306 tC2Q RR 5 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/crc_data_i_reg[42]/Q
1.223 0.165 tNET RR 1 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_340/I0
1.806 0.583 tINS RR 10 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_340/F
1.971 0.165 tNET RR 1 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_326/I0
2.623 0.652 tINS RR 1 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_326/F
2.788 0.165 tNET RR 1 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_172/I1
3.440 0.652 tINS RR 30 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_172/F
3.605 0.165 tNET RR 1 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_313/I0
4.257 0.652 tINS RR 1 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_313/F
4.422 0.165 tNET RR 1 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_157/I0
5.074 0.652 tINS RR 1 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_157/F
5.239 0.165 tNET RR 1 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_30/I0
5.891 0.652 tINS RR 1 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_30/F
6.056 0.165 tNET RR 1 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/crcreg_reg[3]/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 sys_clk_i
10.000 0.000 tCL RR 1 sys_clk_i_ibuf/I
10.587 0.587 tINS RR 2861 sys_clk_i_ibuf/O
10.752 0.165 tNET RR 1 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/crcreg_reg[3]/CLK
10.701 -0.051 tSu 1 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/crcreg_reg[3]
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.587, 78.057%; route: 0.165, 21.943%
Arrival Data Path Delay: cell: 3.843, 72.455%; route: 1.155, 21.776%; tC2Q: 0.306, 5.769%
Required Clock Path Delay: cell: 0.587, 78.057%; route: 0.165, 21.943%

Path 2

Path Summary:
Slack 4.645
Data Arrival Time 6.056
Data Required Time 10.701
From u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/crc_data_i_reg[59]
To u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/crcreg_reg[26]
Launch Clk sys_clk_i[R]
Latch Clk sys_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 sys_clk_i
0.000 0.000 tCL RR 1 sys_clk_i_ibuf/I
0.587 0.587 tINS RR 2861 sys_clk_i_ibuf/O
0.752 0.165 tNET RR 1 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/crc_data_i_reg[59]/CLK
1.058 0.306 tC2Q RR 4 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/crc_data_i_reg[59]/Q
1.223 0.165 tNET RR 1 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_450/I0
1.806 0.583 tINS RR 1 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_450/F
1.971 0.165 tNET RR 1 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_357/I1
2.623 0.652 tINS RR 1 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_357/F
2.788 0.165 tNET RR 1 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_197/I1
3.440 0.652 tINS RR 31 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_197/F
3.605 0.165 tNET RR 1 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_244/I0
4.257 0.652 tINS RR 1 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_244/F
4.422 0.165 tNET RR 1 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_59/I0
5.074 0.652 tINS RR 1 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_59/F
5.239 0.165 tNET RR 1 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_7/I0
5.891 0.652 tINS RR 1 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_7/F
6.056 0.165 tNET RR 1 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/crcreg_reg[26]/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 sys_clk_i
10.000 0.000 tCL RR 1 sys_clk_i_ibuf/I
10.587 0.587 tINS RR 2861 sys_clk_i_ibuf/O
10.752 0.165 tNET RR 1 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/crcreg_reg[26]/CLK
10.701 -0.051 tSu 1 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/crcreg_reg[26]
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.587, 78.057%; route: 0.165, 21.943%
Arrival Data Path Delay: cell: 3.843, 72.455%; route: 1.155, 21.776%; tC2Q: 0.306, 5.769%
Required Clock Path Delay: cell: 0.587, 78.057%; route: 0.165, 21.943%

Path 3

Path Summary:
Slack 4.645
Data Arrival Time 6.056
Data Required Time 10.701
From u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/crc_data_i_reg[53]
To u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/crcreg_reg[15]
Launch Clk sys_clk_i[R]
Latch Clk sys_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 sys_clk_i
0.000 0.000 tCL RR 1 sys_clk_i_ibuf/I
0.587 0.587 tINS RR 2861 sys_clk_i_ibuf/O
0.752 0.165 tNET RR 1 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/crc_data_i_reg[53]/CLK
1.058 0.306 tC2Q RR 8 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/crc_data_i_reg[53]/Q
1.223 0.165 tNET RR 1 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_337/I0
1.806 0.583 tINS RR 3 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_337/F
1.971 0.165 tNET RR 1 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_321/I0
2.623 0.652 tINS RR 1 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_321/F
2.788 0.165 tNET RR 1 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_171/I0
3.440 0.652 tINS RR 31 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_171/F
3.605 0.165 tNET RR 1 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_287/I0
4.257 0.652 tINS RR 1 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_287/F
4.422 0.165 tNET RR 1 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_104/I0
5.074 0.652 tINS RR 1 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_104/F
5.239 0.165 tNET RR 1 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_18/I0
5.891 0.652 tINS RR 1 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_18/F
6.056 0.165 tNET RR 1 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/crcreg_reg[15]/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 sys_clk_i
10.000 0.000 tCL RR 1 sys_clk_i_ibuf/I
10.587 0.587 tINS RR 2861 sys_clk_i_ibuf/O
10.752 0.165 tNET RR 1 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/crcreg_reg[15]/CLK
10.701 -0.051 tSu 1 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/crcreg_reg[15]
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.587, 78.057%; route: 0.165, 21.943%
Arrival Data Path Delay: cell: 3.843, 72.455%; route: 1.155, 21.776%; tC2Q: 0.306, 5.769%
Required Clock Path Delay: cell: 0.587, 78.057%; route: 0.165, 21.943%

Path 4

Path Summary:
Slack 4.645
Data Arrival Time 6.056
Data Required Time 10.701
From u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/crc_data_i_reg[38]
To u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/crcreg_reg[14]
Launch Clk sys_clk_i[R]
Latch Clk sys_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 sys_clk_i
0.000 0.000 tCL RR 1 sys_clk_i_ibuf/I
0.587 0.587 tINS RR 2861 sys_clk_i_ibuf/O
0.752 0.165 tNET RR 1 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/crc_data_i_reg[38]/CLK
1.058 0.306 tC2Q RR 6 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/crc_data_i_reg[38]/Q
1.223 0.165 tNET RR 1 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_430/I0
1.806 0.583 tINS RR 3 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_430/F
1.971 0.165 tNET RR 1 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_326/I1
2.623 0.652 tINS RR 1 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_326/F
2.788 0.165 tNET RR 1 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_172/I1
3.440 0.652 tINS RR 30 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_172/F
3.605 0.165 tNET RR 1 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_264/I0
4.257 0.652 tINS RR 2 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_264/F
4.422 0.165 tNET RR 1 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_109/I0
5.074 0.652 tINS RR 1 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_109/F
5.239 0.165 tNET RR 1 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_19/I0
5.891 0.652 tINS RR 1 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_19/F
6.056 0.165 tNET RR 1 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/crcreg_reg[14]/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 sys_clk_i
10.000 0.000 tCL RR 1 sys_clk_i_ibuf/I
10.587 0.587 tINS RR 2861 sys_clk_i_ibuf/O
10.752 0.165 tNET RR 1 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/crcreg_reg[14]/CLK
10.701 -0.051 tSu 1 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/crcreg_reg[14]
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.587, 78.057%; route: 0.165, 21.943%
Arrival Data Path Delay: cell: 3.843, 72.455%; route: 1.155, 21.776%; tC2Q: 0.306, 5.769%
Required Clock Path Delay: cell: 0.587, 78.057%; route: 0.165, 21.943%

Path 5

Path Summary:
Slack 4.645
Data Arrival Time 6.056
Data Required Time 10.701
From u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_txcrc/tx_crc_gen_inst[0].tx_crc_gen/crc_data_i_reg[42]
To u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_txcrc/tx_crc_gen_inst[0].tx_crc_gen/crcreg_reg[3]
Launch Clk sys_clk_i[R]
Latch Clk sys_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 sys_clk_i
0.000 0.000 tCL RR 1 sys_clk_i_ibuf/I
0.587 0.587 tINS RR 2861 sys_clk_i_ibuf/O
0.752 0.165 tNET RR 1 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_txcrc/tx_crc_gen_inst[0].tx_crc_gen/crc_data_i_reg[42]/CLK
1.058 0.306 tC2Q RR 5 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_txcrc/tx_crc_gen_inst[0].tx_crc_gen/crc_data_i_reg[42]/Q
1.223 0.165 tNET RR 1 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_txcrc/tx_crc_gen_inst[0].tx_crc_gen/msg_inferred_i_340/I0
1.806 0.583 tINS RR 10 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_txcrc/tx_crc_gen_inst[0].tx_crc_gen/msg_inferred_i_340/F
1.971 0.165 tNET RR 1 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_txcrc/tx_crc_gen_inst[0].tx_crc_gen/msg_inferred_i_326/I0
2.623 0.652 tINS RR 1 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_txcrc/tx_crc_gen_inst[0].tx_crc_gen/msg_inferred_i_326/F
2.788 0.165 tNET RR 1 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_txcrc/tx_crc_gen_inst[0].tx_crc_gen/msg_inferred_i_172/I1
3.440 0.652 tINS RR 30 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_txcrc/tx_crc_gen_inst[0].tx_crc_gen/msg_inferred_i_172/F
3.605 0.165 tNET RR 1 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_txcrc/tx_crc_gen_inst[0].tx_crc_gen/msg_inferred_i_313/I0
4.257 0.652 tINS RR 1 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_txcrc/tx_crc_gen_inst[0].tx_crc_gen/msg_inferred_i_313/F
4.422 0.165 tNET RR 1 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_txcrc/tx_crc_gen_inst[0].tx_crc_gen/msg_inferred_i_157/I0
5.074 0.652 tINS RR 1 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_txcrc/tx_crc_gen_inst[0].tx_crc_gen/msg_inferred_i_157/F
5.239 0.165 tNET RR 1 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_txcrc/tx_crc_gen_inst[0].tx_crc_gen/msg_inferred_i_30/I0
5.891 0.652 tINS RR 1 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_txcrc/tx_crc_gen_inst[0].tx_crc_gen/msg_inferred_i_30/F
6.056 0.165 tNET RR 1 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_txcrc/tx_crc_gen_inst[0].tx_crc_gen/crcreg_reg[3]/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 sys_clk_i
10.000 0.000 tCL RR 1 sys_clk_i_ibuf/I
10.587 0.587 tINS RR 2861 sys_clk_i_ibuf/O
10.752 0.165 tNET RR 1 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_txcrc/tx_crc_gen_inst[0].tx_crc_gen/crcreg_reg[3]/CLK
10.701 -0.051 tSu 1 u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_txcrc/tx_crc_gen_inst[0].tx_crc_gen/crcreg_reg[3]
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.587, 78.057%; route: 0.165, 21.943%
Arrival Data Path Delay: cell: 3.843, 72.455%; route: 1.155, 21.776%; tC2Q: 0.306, 5.769%
Required Clock Path Delay: cell: 0.587, 78.057%; route: 0.165, 21.943%