Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Gowin\Gowin_V1.9.9.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v
C:\Gowin\Gowin_V1.9.9.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v
C:\Gowin\Gowin_V1.9.9.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v
C:\Gowin\Gowin_V1.9.9.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v
C:\Gowin\Gowin_V1.9.9.01_x64\IDE\data\ipcores\GAO\GW_CON\gw_con_top_138.v
C:\Gowin\Gowin_V1.9.9.01_x64\IDE\data\ipcores\gw_jtag.v
E:\gowin_prj\RoraLink_64b66b\Gowin RoraLink 64B66B IP RefDesign\project\impl\gao\gw_gao_top.v
GowinSynthesis Constraints File ---
Tool Version V1.9.9.01 (64-bit)
Part Number GW5AST-LV138FPG676AC2/I1
Device GW5AST-138
Device Version B
Created Time Fri Jan 12 16:03:23 2024
Legal Announcement Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module gw_gao
Synthesis Process Running parser:
    CPU time = 0h 0m 0.296s, Elapsed time = 0h 0m 0.298s, Peak memory usage = 52.801MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 52.801MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.023s, Peak memory usage = 52.801MB
    Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 52.801MB
    Optimizing Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.028s, Peak memory usage = 52.801MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 52.801MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 52.801MB
    Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 52.801MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 52.801MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.021s, Peak memory usage = 52.801MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 52.801MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 52.801MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 79.527MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.034s, Peak memory usage = 79.527MB
Generate output files:
    CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.038s, Peak memory usage = 79.527MB
Total Time and Memory Usage CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 79.527MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 87
I/O Buf 87
    IBUF 86
    OBUF 1
Register 565
    DFFRE 1
    DFFPE 36
    DFFCE 528
LUT 472
    LUT2 46
    LUT3 141
    LUT4 285
MUX 1
    MUX16 1
ALU 13
    ALU 13
INV 4
    INV 4
BSRAM 5
    SDPX9B 5
Black Box 1
    GW_JTAG 1

Resource Utilization Summary

Resource Usage Utilization
Logic 497(484 LUT, 13 ALU) / 138240 <1%
Register 565 / 139140 <1%
  --Register as Latch 0 / 139140 0%
  --Register as FF 565 / 139140 <1%
BSRAM 5 / 340 2%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
sys_clk Base 10.000 100.0 0.000 5.000 sys_clk_ibuf/I
u_icon_top/n31_6 Base 10.000 100.0 0.000 5.000 u_icon_top/n31_s2/O
u_la0_top/n15_6 Base 10.000 100.0 0.000 5.000 u_la0_top/n15_s2/O

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 sys_clk 100.0(MHz) 282.6(MHz) 6 TOP
2 u_icon_top/n31_6 100.0(MHz) 1915.7(MHz) 1 TOP
3 u_la0_top/n15_6 100.0(MHz) 1915.7(MHz) 1 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 6.461
Data Arrival Time 4.240
Data Required Time 10.701
From u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
Launch Clk sys_clk[R]
Latch Clk sys_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 sys_clk_ibuf/I
0.587 0.587 tINS RR 228 sys_clk_ibuf/O
0.752 0.165 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLK
1.058 0.306 tC2Q RR 11 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/Q
1.223 0.165 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n620_s2/I0
1.686 0.463 tINS RR 3 u_la0_top/u_ao_mem_ctrl/n620_s2/F
1.851 0.165 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n618_s2/I2
2.257 0.406 tINS RR 3 u_la0_top/u_ao_mem_ctrl/n618_s2/F
2.422 0.165 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n616_s2/I2
2.828 0.406 tINS RR 2 u_la0_top/u_ao_mem_ctrl/n616_s2/F
2.993 0.165 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n615_s3/I1
3.447 0.454 tINS RR 1 u_la0_top/u_ao_mem_ctrl/n615_s3/F
3.612 0.165 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n615_s2/I0
4.075 0.463 tINS RR 1 u_la0_top/u_ao_mem_ctrl/n615_s2/F
4.240 0.165 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 sys_clk
10.000 0.000 tCL RR 1 sys_clk_ibuf/I
10.587 0.587 tINS RR 228 sys_clk_ibuf/O
10.752 0.165 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK
10.701 -0.051 tSu 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.587, 78.057%; route: 0.165, 21.943%
Arrival Data Path Delay: cell: 2.192, 62.844%; route: 0.990, 28.383%; tC2Q: 0.306, 8.773%
Required Clock Path Delay: cell: 0.587, 78.057%; route: 0.165, 21.943%

Path 2

Path Summary:
Slack 6.777
Data Arrival Time 3.726
Data Required Time 10.503
From u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
To u_la0_top/u_ao_mem_ctrl/capture_loop_s1
Launch Clk sys_clk[R]
Latch Clk sys_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 sys_clk_ibuf/I
0.587 0.587 tINS RR 228 sys_clk_ibuf/O
0.752 0.165 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
1.058 0.306 tC2Q RR 9 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/Q
1.223 0.165 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n615_s8/I0
1.686 0.463 tINS RR 1 u_la0_top/u_ao_mem_ctrl/n615_s8/F
1.851 0.165 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n615_s5/I1
2.305 0.454 tINS RR 2 u_la0_top/u_ao_mem_ctrl/n615_s5/F
2.470 0.165 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n615_s4/I0
2.933 0.463 tINS RR 10 u_la0_top/u_ao_mem_ctrl/n615_s4/F
3.098 0.165 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_loop_s4/I0
3.561 0.463 tINS RR 1 u_la0_top/u_ao_mem_ctrl/capture_loop_s4/F
3.726 0.165 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 sys_clk
10.000 0.000 tCL RR 1 sys_clk_ibuf/I
10.587 0.587 tINS RR 228 sys_clk_ibuf/O
10.752 0.165 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK
10.503 -0.249 tSu 1 u_la0_top/u_ao_mem_ctrl/capture_loop_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.587, 78.057%; route: 0.165, 21.943%
Arrival Data Path Delay: cell: 1.843, 61.971%; route: 0.825, 27.740%; tC2Q: 0.306, 10.289%
Required Clock Path Delay: cell: 0.587, 78.057%; route: 0.165, 21.943%

Path 3

Path Summary:
Slack 6.882
Data Arrival Time 3.621
Data Required Time 10.503
From u_la0_top/u_ao_mem_ctrl/capture_length_4_s1
To u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
Launch Clk sys_clk[R]
Latch Clk sys_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 sys_clk_ibuf/I
0.587 0.587 tINS RR 228 sys_clk_ibuf/O
0.752 0.165 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLK
1.058 0.306 tC2Q RR 4 u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/Q
1.223 0.165 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n521_s2/I0
1.686 0.463 tINS RR 3 u_la0_top/u_ao_mem_ctrl/n521_s2/F
1.851 0.165 tNET RR 1 u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s4/I2
2.257 0.406 tINS RR 2 u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s4/F
2.422 0.165 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s5/I0
2.885 0.463 tINS RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s5/F
3.050 0.165 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s3/I2
3.456 0.406 tINS RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s3/F
3.621 0.165 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 sys_clk
10.000 0.000 tCL RR 1 sys_clk_ibuf/I
10.587 0.587 tINS RR 228 sys_clk_ibuf/O
10.752 0.165 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
10.503 -0.249 tSu 1 u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.587, 78.057%; route: 0.165, 21.943%
Arrival Data Path Delay: cell: 1.738, 60.578%; route: 0.825, 28.756%; tC2Q: 0.306, 10.666%
Required Clock Path Delay: cell: 0.587, 78.057%; route: 0.165, 21.943%

Path 4

Path Summary:
Slack 7.032
Data Arrival Time 3.669
Data Required Time 10.701
From u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Launch Clk sys_clk[R]
Latch Clk sys_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 sys_clk_ibuf/I
0.587 0.587 tINS RR 228 sys_clk_ibuf/O
0.752 0.165 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
1.058 0.306 tC2Q RR 9 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/Q
1.223 0.165 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n615_s8/I0
1.686 0.463 tINS RR 1 u_la0_top/u_ao_mem_ctrl/n615_s8/F
1.851 0.165 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n615_s5/I1
2.305 0.454 tINS RR 2 u_la0_top/u_ao_mem_ctrl/n615_s5/F
2.470 0.165 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n615_s4/I0
2.933 0.463 tINS RR 10 u_la0_top/u_ao_mem_ctrl/n615_s4/F
3.098 0.165 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n623_s1/I2
3.504 0.406 tINS RR 1 u_la0_top/u_ao_mem_ctrl/n623_s1/F
3.669 0.165 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 sys_clk
10.000 0.000 tCL RR 1 sys_clk_ibuf/I
10.587 0.587 tINS RR 228 sys_clk_ibuf/O
10.752 0.165 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
10.701 -0.051 tSu 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.587, 78.057%; route: 0.165, 21.943%
Arrival Data Path Delay: cell: 1.786, 61.228%; route: 0.825, 28.282%; tC2Q: 0.306, 10.490%
Required Clock Path Delay: cell: 0.587, 78.057%; route: 0.165, 21.943%

Path 5

Path Summary:
Slack 7.032
Data Arrival Time 3.669
Data Required Time 10.701
From u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
Launch Clk sys_clk[R]
Latch Clk sys_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 sys_clk_ibuf/I
0.587 0.587 tINS RR 228 sys_clk_ibuf/O
0.752 0.165 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
1.058 0.306 tC2Q RR 9 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/Q
1.223 0.165 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n615_s8/I0
1.686 0.463 tINS RR 1 u_la0_top/u_ao_mem_ctrl/n615_s8/F
1.851 0.165 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n615_s5/I1
2.305 0.454 tINS RR 2 u_la0_top/u_ao_mem_ctrl/n615_s5/F
2.470 0.165 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n615_s4/I0
2.933 0.463 tINS RR 10 u_la0_top/u_ao_mem_ctrl/n615_s4/F
3.098 0.165 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n621_s1/I2
3.504 0.406 tINS RR 1 u_la0_top/u_ao_mem_ctrl/n621_s1/F
3.669 0.165 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 sys_clk
10.000 0.000 tCL RR 1 sys_clk_ibuf/I
10.587 0.587 tINS RR 228 sys_clk_ibuf/O
10.752 0.165 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK
10.701 -0.051 tSu 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.587, 78.057%; route: 0.165, 21.943%
Arrival Data Path Delay: cell: 1.786, 61.228%; route: 0.825, 28.282%; tC2Q: 0.306, 10.490%
Required Clock Path Delay: cell: 0.587, 78.057%; route: 0.165, 21.943%