Timing Messages

Report Title Timing Analysis Report
Design File E:\gowin_prj\RoraLink_64b66b\Gowin RoraLink 64B66B IP RefDesign\project\impl\gwsynthesis\serial_64b66b.vg
Physical Constraints File E:\gowin_prj\RoraLink_64b66b\Gowin RoraLink 64B66B IP RefDesign\project\src\top.cst
Timing Constraint File E:\gowin_prj\RoraLink_64b66b\Gowin RoraLink 64B66B IP RefDesign\project\src\top.sdc
Tool Version V1.9.9.01 (64-bit)
Part Number GW5AST-LV138FPG676AC2/I1
Device GW5AST-138
Device Version B
Created Time Fri Jan 12 16:17:25 2024
Legal Announcement Copyright (C)2014-2023 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model Slow 0.855V 0C C2/I1
Hold Delay Model Fast 0.945V 85C C2/I1
Numbers of Paths Analyzed 16461
Numbers of Endpoints Analyzed 25849
Numbers of Falling Endpoints 0
Numbers of Setup Violated Endpoints 0
Numbers of Hold Violated Endpoints 0

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Objects
osc_clk_i Base 20.000 50.000 0.000 10.000 osc_clk_i
cfg_clk Base 20.000 50.000 0.000 10.000 cfg_clk
sys_clk Base 20.480 48.828 0.000 10.240 sys_clk
u_SerDes_Top/q1_lane1_fabric_rx_clk Base 10.000 100.000 0.000 5.000 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 cfg_clk 50.000(MHz) 80.652(MHz) 10 TOP
2 sys_clk 48.828(MHz) 72.368(MHz) 7 TOP
3 u_SerDes_Top/q1_lane1_fabric_rx_clk 100.000(MHz) 169.671(MHz) 3 TOP

No timing paths to get frequency of osc_clk_i!

Total Negative Slack Summary:

Clock Name Analysis Type Endpoints TNS Number of Endpoints
osc_clk_i Setup 0.000 0
osc_clk_i Hold 0.000 0
cfg_clk Setup 0.000 0
cfg_clk Hold 0.000 0
sys_clk Setup 0.000 0
sys_clk Hold 0.000 0
u_SerDes_Top/q1_lane1_fabric_rx_clk Setup 0.000 0
u_SerDes_Top/q1_lane1_fabric_rx_clk Hold 0.000 0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 4.106 u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/u_gtr12_common_logic_cbcc/all_start_cb_writes_out_s0/Q u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_3_s0/CE u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] 10.000 -0.036 5.681
2 4.106 u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/u_gtr12_common_logic_cbcc/all_start_cb_writes_out_s0/Q u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_4_s0/CE u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] 10.000 -0.036 5.681
3 4.243 u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/serdes_rx_dat_slip_2d_51_s0/Q u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx1_66b_data_29_s0/D u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] 10.000 0.015 5.691
4 4.452 u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/u_gtr12_common_logic_cbcc/all_start_cb_writes_out_s0/Q u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_0_s0/CE u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] 10.000 -0.048 5.347
5 4.452 u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/u_gtr12_common_logic_cbcc/all_start_cb_writes_out_s0/Q u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_1_s0/CE u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] 10.000 -0.048 5.347
6 4.452 u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/u_gtr12_common_logic_cbcc/all_start_cb_writes_out_s0/Q u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_2_s0/CE u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] 10.000 -0.048 5.347
7 4.498 u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/u_gtr12_common_logic_cbcc/all_start_cb_writes_out_s0/Q u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_5_s0/CE u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] 10.000 0.016 5.237
8 4.582 u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx_sequence1_1d_1_s0/Q u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx1_66b_data_55_s0/D u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] 10.000 0.011 5.356
9 4.586 u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/u_gtr12_common_reset_cbcc/cbcc_fifo_reset_wr_clk_s0/Q u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/do_wr_en_s0/RESET u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] 10.000 0.004 5.113
10 4.627 u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/u_gtr12_common_logic_cbcc/all_start_cb_writes_out_s0/Q u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_6_s0/CE u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] 10.000 -0.001 5.125
11 4.627 u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/u_gtr12_common_logic_cbcc/all_start_cb_writes_out_s0/Q u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_30_s0/CE u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] 10.000 -0.001 5.125
12 4.723 u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/u_gtr12_common_logic_cbcc/all_start_cb_writes_out_s0/Q u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_7_s0/CE u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] 10.000 0.010 5.018
13 4.723 u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/u_gtr12_common_logic_cbcc/all_start_cb_writes_out_s0/Q u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_13_s0/CE u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] 10.000 0.010 5.018
14 4.774 u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/serdes_rx_dat_slip_2d_51_s0/Q u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx2_66b_data_9_s0/D u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] 10.000 0.024 5.151
15 4.791 u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/serdes_rx_dat_slip_1d_10_s0/Q u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx1_66b_data_46_s0/D u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] 10.000 -0.004 5.162
16 4.842 u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/u_gtr12_common_logic_cbcc/all_start_cb_writes_out_s0/Q u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_32_s0/CE u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] 10.000 0.006 4.903
17 4.842 u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/u_gtr12_common_logic_cbcc/all_start_cb_writes_out_s0/Q u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_33_s0/CE u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] 10.000 0.006 4.903
18 4.859 u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/serdes_rx_dat_slip_2d_51_s0/Q u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx1_66b_data_33_s0/D u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] 10.000 0.022 5.068
19 4.894 u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/u_gtr12_common_logic_cbcc/all_start_cb_writes_out_s0/Q u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_8_s0/CE u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] 10.000 0.006 4.851
20 4.917 u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/u_gtr12_common_reset_cbcc/cbcc_fifo_reset_wr_clk_s0/Q u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_29_s0/RESET u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] 10.000 0.012 4.774
21 4.922 u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/u_gtr12_common_reset_cbcc/cbcc_fifo_reset_wr_clk_s0/Q u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_29_s0/RESET u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] 10.000 0.006 4.774
22 4.949 u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/serdes_rx_dat_slip_2d_51_s0/Q u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx1_66b_data_37_s0/D u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] 10.000 0.013 4.987
23 4.962 u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/u_gtr12_common_reset_cbcc/cbcc_fifo_reset_wr_clk_s0/Q u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_40_s0/RESET u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] 10.000 -0.006 4.746
24 4.962 u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/u_gtr12_common_reset_cbcc/cbcc_fifo_reset_wr_clk_s0/Q u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_40_s0/RESET u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] 10.000 -0.006 4.746
25 4.974 u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx_sequence1_1d_1_s0/Q u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx1_66b_data_64_s0/D u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] 10.000 0.006 4.969

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.026 u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_53_s0/Q u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/DI[17] u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] 0.000 0.001 0.240
2 0.030 u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_68_s0/Q u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/DI[31] u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] 0.000 0.005 0.240
3 0.030 u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_63_s0/Q u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/DI[27] u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] 0.000 0.005 0.240
4 0.038 u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_64_s0/Q u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/DI[28] u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] 0.000 0.010 0.243
5 0.113 u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_66_s0/Q u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/DI[30] u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] 0.000 0.010 0.318
6 0.113 u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_65_s0/Q u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/DI[29] u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] 0.000 0.010 0.318
7 0.126 u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_61_s0/Q u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/DI[25] u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] 0.000 0.005 0.336
8 0.147 u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_45_s0/Q u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/DI[9] u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] 0.000 0.020 0.341
9 0.147 u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_60_s0/Q u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/DI[24] u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] 0.000 0.001 0.361
10 0.181 u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_62_s0/Q u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/DI[26] u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] 0.000 0.015 0.381
11 0.198 u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_5_s0/Q u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s/DI[5] u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] 0.000 0.010 0.403
12 0.205 u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_59_s0/Q u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/DI[23] u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] 0.000 0.010 0.410
13 0.206 u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_52_s0/Q u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/DI[16] u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] 0.000 0.011 0.410
14 0.206 u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_50_s0/Q u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/DI[14] u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] 0.000 0.010 0.411
15 0.229 u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_21_s0/Q u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s/DI[21] u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] 0.000 0.015 0.429
16 0.232 u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_58_s0/Q u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/DI[22] u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] 0.000 0.015 0.432
17 0.243 u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_46_s0/Q u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/DI[10] u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] 0.000 0.020 0.437
18 0.252 u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_54_s0/Q u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/DI[18] u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] 0.000 0.011 0.456
19 0.259 u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_47_s0/Q u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/DI[11] u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] 0.000 0.020 0.453
20 0.267 u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_51_s0/Q u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/DI[15] u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] 0.000 0.010 0.472
21 0.269 u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_22_s0/Q u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s/DI[22] u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] 0.000 0.015 0.469
22 0.277 u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_25_s0/Q u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s/DI[25] u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] 0.000 0.014 0.478
23 0.277 u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_23_s0/Q u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s/DI[23] u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] 0.000 0.014 0.478
24 0.288 u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_24_s0/Q u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s/DI[24] u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] 0.000 0.010 0.493
25 0.294 u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_28_s0/Q u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s/DI[28] u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] 0.000 0.010 0.499

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 4.781 u1_reset_gen/o_rst1_s1/Q u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/rx_rst_srl_0_s0/PRESET cfg_clk:[R] u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] 10.000 -0.029 4.935
2 4.781 u1_reset_gen/o_rst1_s1/Q u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/rx_rst_srl_1_s0/PRESET cfg_clk:[R] u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] 10.000 -0.029 4.935
3 4.781 u1_reset_gen/o_rst1_s1/Q u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/rx_rst_srl_2_s0/PRESET cfg_clk:[R] u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] 10.000 -0.029 4.935
4 7.643 u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s1/Q u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/hpcnt_reset_srl_2_s0/PRESET u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] cfg_clk:[R] 10.000 -0.019 2.063
5 7.643 u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s1/Q u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/hpcnt_reset_srl_0_s0/PRESET u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] cfg_clk:[R] 10.000 -0.019 2.063
6 7.643 u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s1/Q u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/hpcnt_reset_srl_1_s0/PRESET u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] cfg_clk:[R] 10.000 -0.019 2.063
7 7.959 u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s1/Q u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_headsync/fsm_st_curr_0_s0/CLEAR u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] 10.000 -0.019 1.782
8 7.961 u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s1/Q u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_headsync/fsm_st_curr_1_s0/CLEAR u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] 10.000 -0.021 1.782
9 8.145 u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s1/Q u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_headsync/fsm_st_curr_2_s0/CLEAR u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] u_SerDes_Top/q1_lane1_fabric_rx_clk:[R] 10.000 -0.008 1.585
10 14.188 u_SerDes_Top/RoraLink_64B66B_Top_inst/gt_pll_ok_o_s2/Q u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/tx_rst_srl_2_s0/PRESET sys_clk:[R] sys_clk:[R] 20.480 0.008 6.006
11 14.188 u_SerDes_Top/RoraLink_64B66B_Top_inst/gt_pll_ok_o_s2/Q u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/tx_rst_srl_0_s0/PRESET sys_clk:[R] sys_clk:[R] 20.480 0.008 6.006
12 14.188 u_SerDes_Top/RoraLink_64B66B_Top_inst/gt_pll_ok_o_s2/Q u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/tx_rst_srl_1_s0/PRESET sys_clk:[R] sys_clk:[R] 20.480 0.008 6.006
13 16.352 u1_reset_gen/o_rst1_s1/Q u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/tb_delay_0_s1/CLEAR cfg_clk:[R] cfg_clk:[R] 20.000 -0.020 3.390
14 16.352 u1_reset_gen/o_rst1_s1/Q u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/divclk_cnt_2_s0/CLEAR cfg_clk:[R] cfg_clk:[R] 20.000 -0.020 3.390
15 16.352 u1_reset_gen/o_rst1_s1/Q u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/divclk_cnt_4_s0/CLEAR cfg_clk:[R] cfg_clk:[R] 20.000 -0.020 3.390
16 16.352 u1_reset_gen/o_rst1_s1/Q u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/divclk_cnt_15_s0/CLEAR cfg_clk:[R] cfg_clk:[R] 20.000 -0.020 3.390
17 16.352 u1_reset_gen/o_rst1_s1/Q u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/tb_delay_2_s0/CLEAR cfg_clk:[R] cfg_clk:[R] 20.000 -0.020 3.390
18 16.352 u1_reset_gen/o_rst1_s1/Q u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/tb_delay_3_s0/CLEAR cfg_clk:[R] cfg_clk:[R] 20.000 -0.020 3.390
19 16.360 u1_reset_gen/o_rst1_s1/Q u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/divclk_cnt_0_s0/CLEAR cfg_clk:[R] cfg_clk:[R] 20.000 -0.028 3.390
20 16.360 u1_reset_gen/o_rst1_s1/Q u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/fsm_st_curr_0_s0/CLEAR cfg_clk:[R] cfg_clk:[R] 20.000 -0.028 3.390
21 16.360 u1_reset_gen/o_rst1_s1/Q u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/fsm_st_curr_1_s0/CLEAR cfg_clk:[R] cfg_clk:[R] 20.000 -0.028 3.390
22 16.429 u1_reset_gen/o_rst1_s1/Q u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/fsm_st_curr_1_s1/CLEAR cfg_clk:[R] cfg_clk:[R] 20.000 -0.018 3.311
23 16.429 u1_reset_gen/o_rst1_s1/Q u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/fsm_st_curr_2_s1/CLEAR cfg_clk:[R] cfg_clk:[R] 20.000 -0.018 3.311
24 16.429 u1_reset_gen/o_rst1_s1/Q u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_0_s0/CLEAR cfg_clk:[R] cfg_clk:[R] 20.000 -0.018 3.311
25 16.437 u1_reset_gen/o_rst1_s1/Q u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_5_s0/CLEAR cfg_clk:[R] cfg_clk:[R] 20.000 -0.026 3.311

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.496 u1_reset_gen/o_rst1_s1/Q u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_14_s0/CLEAR cfg_clk:[R] cfg_clk:[R] 0.000 -0.004 0.349
2 0.496 u1_reset_gen/o_rst1_s1/Q u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_15_s0/CLEAR cfg_clk:[R] cfg_clk:[R] 0.000 -0.004 0.349
3 0.496 u1_reset_gen/o_rst1_s1/Q u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_18_s0/CLEAR cfg_clk:[R] cfg_clk:[R] 0.000 -0.004 0.349
4 0.496 u1_reset_gen/o_rst1_s1/Q u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_19_s0/CLEAR cfg_clk:[R] cfg_clk:[R] 0.000 -0.004 0.349
5 0.504 u1_reset_gen/o_rst1_s1/Q u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_17_s0/CLEAR cfg_clk:[R] cfg_clk:[R] 0.000 0.007 0.347
6 0.600 u1_reset_gen/o_rst1_s1/Q u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_2_s0/CLEAR cfg_clk:[R] cfg_clk:[R] 0.000 -0.002 0.451
7 0.600 u1_reset_gen/o_rst1_s1/Q u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_20_s0/CLEAR cfg_clk:[R] cfg_clk:[R] 0.000 -0.002 0.451
8 0.600 u1_reset_gen/o_rst1_s1/Q u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_21_s0/CLEAR cfg_clk:[R] cfg_clk:[R] 0.000 -0.002 0.451
9 0.600 u1_reset_gen/o_rst1_s1/Q u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_22_s0/CLEAR cfg_clk:[R] cfg_clk:[R] 0.000 -0.002 0.451
10 0.600 u1_reset_gen/o_rst1_s1/Q u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_23_s0/CLEAR cfg_clk:[R] cfg_clk:[R] 0.000 -0.002 0.451
11 0.600 u1_reset_gen/o_rst1_s1/Q u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_24_s0/CLEAR cfg_clk:[R] cfg_clk:[R] 0.000 -0.002 0.451
12 0.600 u1_reset_gen/o_rst1_s1/Q u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_25_s0/CLEAR cfg_clk:[R] cfg_clk:[R] 0.000 -0.002 0.451
13 0.604 u1_reset_gen/o_rst1_s1/Q u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/wp_rd_g2b_ptr_0_s0/CLEAR cfg_clk:[R] cfg_clk:[R] 0.000 0.000 0.453
14 0.604 u1_reset_gen/o_rst1_s1/Q u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/wp_rd_g2b_ptr_1_s0/CLEAR cfg_clk:[R] cfg_clk:[R] 0.000 0.000 0.453
15 0.604 u1_reset_gen/o_rst1_s1/Q u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/wp_rd_g2b_ptr_2_s0/CLEAR cfg_clk:[R] cfg_clk:[R] 0.000 0.000 0.453
16 0.604 u1_reset_gen/o_rst1_s1/Q u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/wp_rd_gray_ptr_0_s0/CLEAR cfg_clk:[R] cfg_clk:[R] 0.000 0.000 0.453
17 0.604 u1_reset_gen/o_rst1_s1/Q u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/wp_rd_gray_ptr_2_s0/CLEAR cfg_clk:[R] cfg_clk:[R] 0.000 0.000 0.453
18 0.604 u1_reset_gen/o_rst1_s1/Q u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/wp_rd_gray_ptr1_0_s0/CLEAR cfg_clk:[R] cfg_clk:[R] 0.000 0.000 0.453
19 0.604 u1_reset_gen/o_rst1_s1/Q u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/wp_rd_gray_ptr1_2_s0/CLEAR cfg_clk:[R] cfg_clk:[R] 0.000 0.000 0.453
20 0.604 u1_reset_gen/o_rst1_s1/Q u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/rd_gray_ptr_0_s0/CLEAR cfg_clk:[R] cfg_clk:[R] 0.000 0.000 0.453
21 0.604 u1_reset_gen/o_rst1_s1/Q u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_16_s0/CLEAR cfg_clk:[R] cfg_clk:[R] 0.000 0.003 0.451
22 0.604 u1_reset_gen/o_rst1_s1/Q u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wen_s0/CLEAR cfg_clk:[R] cfg_clk:[R] 0.000 0.003 0.451
23 0.606 u1_reset_gen/o_rst1_s1/Q u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_0_s0/CLEAR cfg_clk:[R] cfg_clk:[R] 0.000 0.012 0.443
24 0.606 u1_reset_gen/o_rst1_s1/Q u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_1_s0/CLEAR cfg_clk:[R] cfg_clk:[R] 0.000 0.012 0.443
25 0.708 u1_reset_gen/o_rst1_s1/Q u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_8_s0/CLEAR cfg_clk:[R] cfg_clk:[R] 0.000 0.004 0.553

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number Slack Actual Width Required Width Type Clock Objects
1 3.204 4.066 0.862 High Pulse Width u_SerDes_Top/q1_lane1_fabric_rx_clk u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s
2 3.208 4.070 0.862 High Pulse Width u_SerDes_Top/q1_lane1_fabric_rx_clk u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s
3 3.244 4.106 0.862 Low Pulse Width u_SerDes_Top/q1_lane1_fabric_rx_clk u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s
4 3.247 4.109 0.862 Low Pulse Width u_SerDes_Top/q1_lane1_fabric_rx_clk u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s
5 3.822 4.022 0.200 High Pulse Width u_SerDes_Top/q1_lane1_fabric_rx_clk u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/raw_data_c_srl[0]_4_s0
6 3.822 4.022 0.200 High Pulse Width u_SerDes_Top/q1_lane1_fabric_rx_clk u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/raw_data_c_srl[0]_3_s0
7 3.822 4.022 0.200 High Pulse Width u_SerDes_Top/q1_lane1_fabric_rx_clk u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/raw_data_c_srl[0]_2_s0
8 3.822 4.022 0.200 High Pulse Width u_SerDes_Top/q1_lane1_fabric_rx_clk u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/raw_data_r_3_s0
9 3.822 4.022 0.200 High Pulse Width u_SerDes_Top/q1_lane1_fabric_rx_clk u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/raw_data_r_2_s0
10 3.822 4.022 0.200 High Pulse Width u_SerDes_Top/q1_lane1_fabric_rx_clk u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/raw_data_r_1_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 4.106
Data Arrival Time 7.819
Data Required Time 11.925
From u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/u_gtr12_common_logic_cbcc/all_start_cb_writes_out_s0
To u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_3_s0
Launch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
2.138 2.138 tNET RR 1 R12C90[0][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/u_gtr12_common_logic_cbcc/all_start_cb_writes_out_s0/CLK
2.444 0.306 tC2Q RR 3 R12C90[0][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/u_gtr12_common_logic_cbcc/all_start_cb_writes_out_s0/Q
4.334 1.890 tNET RR 1 R23C109[2][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/n1416_s0/I2
4.797 0.463 tINS RR 2 R23C109[2][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/n1416_s0/F
4.920 0.123 tNET RR 1 R23C109[3][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/mod_do_wr_en_s1/I2
5.285 0.365 tINS RR 71 R23C109[3][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/mod_do_wr_en_s1/F
7.819 2.534 tNET RR 1 R25C90[0][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_3_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
10.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
12.174 2.174 tNET RR 1 R25C90[0][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_3_s0/CLK
11.925 -0.249 tSu 1 R25C90[0][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_3_s0

Path Statistics:

Clock Skew 0.036
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.138, 100.000%
Arrival Data Path Delay cell: 0.828, 14.575%; route: 4.547, 80.039%; tC2Q: 0.306, 5.386%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.174, 100.000%

Path2

Path Summary:

Slack 4.106
Data Arrival Time 7.819
Data Required Time 11.925
From u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/u_gtr12_common_logic_cbcc/all_start_cb_writes_out_s0
To u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_4_s0
Launch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
2.138 2.138 tNET RR 1 R12C90[0][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/u_gtr12_common_logic_cbcc/all_start_cb_writes_out_s0/CLK
2.444 0.306 tC2Q RR 3 R12C90[0][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/u_gtr12_common_logic_cbcc/all_start_cb_writes_out_s0/Q
4.334 1.890 tNET RR 1 R23C109[2][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/n1416_s0/I2
4.797 0.463 tINS RR 2 R23C109[2][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/n1416_s0/F
4.920 0.123 tNET RR 1 R23C109[3][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/mod_do_wr_en_s1/I2
5.285 0.365 tINS RR 71 R23C109[3][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/mod_do_wr_en_s1/F
7.819 2.534 tNET RR 1 R25C90[0][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_4_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
10.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
12.174 2.174 tNET RR 1 R25C90[0][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_4_s0/CLK
11.925 -0.249 tSu 1 R25C90[0][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_4_s0

Path Statistics:

Clock Skew 0.036
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.138, 100.000%
Arrival Data Path Delay cell: 0.828, 14.575%; route: 4.547, 80.039%; tC2Q: 0.306, 5.386%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.174, 100.000%

Path3

Path Summary:

Slack 4.243
Data Arrival Time 7.821
Data Required Time 12.064
From u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/serdes_rx_dat_slip_2d_51_s0
To u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx1_66b_data_29_s0
Launch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
2.130 2.130 tNET RR 1 R8C114[2][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/serdes_rx_dat_slip_2d_51_s0/CLK
2.436 0.306 tC2Q RR 9 R8C114[2][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/serdes_rx_dat_slip_2d_51_s0/Q
5.149 2.713 tNET RR 1 R12C125[2][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/n707_s9/I0
5.603 0.454 tINS RR 4 R12C125[2][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/n707_s9/F
6.911 1.308 tNET RR 1 R16C126[1][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/n703_s9/I0
7.365 0.454 tINS RR 1 R16C126[1][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/n703_s9/F
7.367 0.002 tNET RR 1 R16C126[1][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/n703_s7/I3
7.821 0.454 tINS RR 1 R16C126[1][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/n703_s7/F
7.821 0.000 tNET RR 1 R16C126[1][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx1_66b_data_29_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
10.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
12.115 2.115 tNET RR 1 R16C126[1][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx1_66b_data_29_s0/CLK
12.064 -0.051 tSu 1 R16C126[1][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx1_66b_data_29_s0

Path Statistics:

Clock Skew -0.015
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.130, 100.000%
Arrival Data Path Delay cell: 1.362, 23.933%; route: 4.023, 70.691%; tC2Q: 0.306, 5.377%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.115, 100.000%

Path4

Path Summary:

Slack 4.452
Data Arrival Time 7.485
Data Required Time 11.937
From u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/u_gtr12_common_logic_cbcc/all_start_cb_writes_out_s0
To u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_0_s0
Launch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
2.138 2.138 tNET RR 1 R12C90[0][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/u_gtr12_common_logic_cbcc/all_start_cb_writes_out_s0/CLK
2.444 0.306 tC2Q RR 3 R12C90[0][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/u_gtr12_common_logic_cbcc/all_start_cb_writes_out_s0/Q
4.334 1.890 tNET RR 1 R23C109[2][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/n1416_s0/I2
4.797 0.463 tINS RR 2 R23C109[2][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/n1416_s0/F
4.920 0.123 tNET RR 1 R23C109[3][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/mod_do_wr_en_s1/I2
5.285 0.365 tINS RR 71 R23C109[3][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/mod_do_wr_en_s1/F
7.485 2.200 tNET RR 1 R23C91[3][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_0_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
10.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
12.186 2.186 tNET RR 1 R23C91[3][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_0_s0/CLK
11.937 -0.249 tSu 1 R23C91[3][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_0_s0

Path Statistics:

Clock Skew 0.048
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.138, 100.000%
Arrival Data Path Delay cell: 0.828, 15.485%; route: 4.213, 78.792%; tC2Q: 0.306, 5.723%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.186, 100.000%

Path5

Path Summary:

Slack 4.452
Data Arrival Time 7.485
Data Required Time 11.937
From u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/u_gtr12_common_logic_cbcc/all_start_cb_writes_out_s0
To u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_1_s0
Launch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
2.138 2.138 tNET RR 1 R12C90[0][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/u_gtr12_common_logic_cbcc/all_start_cb_writes_out_s0/CLK
2.444 0.306 tC2Q RR 3 R12C90[0][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/u_gtr12_common_logic_cbcc/all_start_cb_writes_out_s0/Q
4.334 1.890 tNET RR 1 R23C109[2][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/n1416_s0/I2
4.797 0.463 tINS RR 2 R23C109[2][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/n1416_s0/F
4.920 0.123 tNET RR 1 R23C109[3][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/mod_do_wr_en_s1/I2
5.285 0.365 tINS RR 71 R23C109[3][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/mod_do_wr_en_s1/F
7.485 2.200 tNET RR 1 R23C91[2][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_1_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
10.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
12.186 2.186 tNET RR 1 R23C91[2][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_1_s0/CLK
11.937 -0.249 tSu 1 R23C91[2][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_1_s0

Path Statistics:

Clock Skew 0.048
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.138, 100.000%
Arrival Data Path Delay cell: 0.828, 15.485%; route: 4.213, 78.792%; tC2Q: 0.306, 5.723%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.186, 100.000%

Path6

Path Summary:

Slack 4.452
Data Arrival Time 7.485
Data Required Time 11.937
From u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/u_gtr12_common_logic_cbcc/all_start_cb_writes_out_s0
To u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_2_s0
Launch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
2.138 2.138 tNET RR 1 R12C90[0][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/u_gtr12_common_logic_cbcc/all_start_cb_writes_out_s0/CLK
2.444 0.306 tC2Q RR 3 R12C90[0][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/u_gtr12_common_logic_cbcc/all_start_cb_writes_out_s0/Q
4.334 1.890 tNET RR 1 R23C109[2][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/n1416_s0/I2
4.797 0.463 tINS RR 2 R23C109[2][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/n1416_s0/F
4.920 0.123 tNET RR 1 R23C109[3][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/mod_do_wr_en_s1/I2
5.285 0.365 tINS RR 71 R23C109[3][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/mod_do_wr_en_s1/F
7.485 2.200 tNET RR 1 R23C91[2][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_2_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
10.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
12.186 2.186 tNET RR 1 R23C91[2][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_2_s0/CLK
11.937 -0.249 tSu 1 R23C91[2][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_2_s0

Path Statistics:

Clock Skew 0.048
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.138, 100.000%
Arrival Data Path Delay cell: 0.828, 15.485%; route: 4.213, 78.792%; tC2Q: 0.306, 5.723%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.186, 100.000%

Path7

Path Summary:

Slack 4.498
Data Arrival Time 7.375
Data Required Time 11.873
From u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/u_gtr12_common_logic_cbcc/all_start_cb_writes_out_s0
To u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_5_s0
Launch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
2.138 2.138 tNET RR 1 R12C90[0][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/u_gtr12_common_logic_cbcc/all_start_cb_writes_out_s0/CLK
2.444 0.306 tC2Q RR 3 R12C90[0][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/u_gtr12_common_logic_cbcc/all_start_cb_writes_out_s0/Q
4.334 1.890 tNET RR 1 R23C109[2][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/n1416_s0/I2
4.797 0.463 tINS RR 2 R23C109[2][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/n1416_s0/F
4.920 0.123 tNET RR 1 R23C109[3][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/mod_do_wr_en_s1/I2
5.285 0.365 tINS RR 71 R23C109[3][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/mod_do_wr_en_s1/F
7.375 2.090 tNET RR 1 R26C93[0][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_5_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
10.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
12.122 2.122 tNET RR 1 R26C93[0][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_5_s0/CLK
11.873 -0.249 tSu 1 R26C93[0][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_5_s0

Path Statistics:

Clock Skew -0.016
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.138, 100.000%
Arrival Data Path Delay cell: 0.828, 15.811%; route: 4.103, 78.346%; tC2Q: 0.306, 5.843%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.122, 100.000%

Path8

Path Summary:

Slack 4.582
Data Arrival Time 7.479
Data Required Time 12.061
From u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx_sequence1_1d_1_s0
To u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx1_66b_data_55_s0
Launch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
2.123 2.123 tNET RR 1 R16C119[3][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx_sequence1_1d_1_s0/CLK
2.429 0.306 tC2Q RR 127 R16C119[3][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx_sequence1_1d_1_s0/Q
6.062 3.633 tNET RR 1 R9C115[3][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/n677_s9/I3
6.295 0.233 tINS RR 1 R9C115[3][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/n677_s9/F
7.016 0.721 tNET RR 1 R13C115[1][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/n677_s7/I3
7.479 0.463 tINS RR 1 R13C115[1][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/n677_s7/F
7.479 0.000 tNET RR 1 R13C115[1][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx1_66b_data_55_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
10.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
12.111 2.112 tNET RR 1 R13C115[1][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx1_66b_data_55_s0/CLK
12.061 -0.051 tSu 1 R13C115[1][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx1_66b_data_55_s0

Path Statistics:

Clock Skew -0.011
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.123, 100.000%
Arrival Data Path Delay cell: 0.696, 12.994%; route: 4.354, 81.293%; tC2Q: 0.306, 5.713%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.112, 100.000%

Path9

Path Summary:

Slack 4.586
Data Arrival Time 7.248
Data Required Time 11.834
From u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/u_gtr12_common_reset_cbcc/cbcc_fifo_reset_wr_clk_s0
To u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/do_wr_en_s0
Launch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
2.136 2.136 tNET RR 1 R25C126[0][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/u_gtr12_common_reset_cbcc/cbcc_fifo_reset_wr_clk_s0/CLK
2.430 0.294 tC2Q RF 163 R25C126[0][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/u_gtr12_common_reset_cbcc/cbcc_fifo_reset_wr_clk_s0/Q
5.907 3.478 tNET FF 1 R23C116[3][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/n3449_s0/I0
6.273 0.365 tINS FR 4 R23C116[3][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/n3449_s0/F
6.279 0.006 tNET RR 1 R23C116[3][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/n1431_s1/I1
6.644 0.365 tINS RR 1 R23C116[3][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/n1431_s1/F
7.249 0.605 tNET RR 1 R23C109[2][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/do_wr_en_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
10.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
12.132 2.132 tNET RR 1 R23C109[2][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/do_wr_en_s0/CLK
11.834 -0.298 tSu 1 R23C109[2][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/do_wr_en_s0

Path Statistics:

Clock Skew -0.004
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.136, 100.000%
Arrival Data Path Delay cell: 0.730, 14.277%; route: 4.089, 79.973%; tC2Q: 0.294, 5.750%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.132, 100.000%

Path10

Path Summary:

Slack 4.627
Data Arrival Time 7.263
Data Required Time 11.891
From u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/u_gtr12_common_logic_cbcc/all_start_cb_writes_out_s0
To u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_6_s0
Launch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
2.138 2.138 tNET RR 1 R12C90[0][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/u_gtr12_common_logic_cbcc/all_start_cb_writes_out_s0/CLK
2.444 0.306 tC2Q RR 3 R12C90[0][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/u_gtr12_common_logic_cbcc/all_start_cb_writes_out_s0/Q
4.334 1.890 tNET RR 1 R23C109[2][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/n1416_s0/I2
4.797 0.463 tINS RR 2 R23C109[2][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/n1416_s0/F
4.920 0.123 tNET RR 1 R23C109[3][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/mod_do_wr_en_s1/I2
5.285 0.365 tINS RR 71 R23C109[3][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/mod_do_wr_en_s1/F
7.263 1.978 tNET RR 1 R23C92[2][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_6_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
10.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
12.139 2.140 tNET RR 1 R23C92[2][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_6_s0/CLK
11.891 -0.249 tSu 1 R23C92[2][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_6_s0

Path Statistics:

Clock Skew 0.001
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.138, 100.000%
Arrival Data Path Delay cell: 0.828, 16.156%; route: 3.991, 77.873%; tC2Q: 0.306, 5.971%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.140, 100.000%

Path11

Path Summary:

Slack 4.627
Data Arrival Time 7.263
Data Required Time 11.891
From u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/u_gtr12_common_logic_cbcc/all_start_cb_writes_out_s0
To u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_30_s0
Launch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
2.138 2.138 tNET RR 1 R12C90[0][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/u_gtr12_common_logic_cbcc/all_start_cb_writes_out_s0/CLK
2.444 0.306 tC2Q RR 3 R12C90[0][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/u_gtr12_common_logic_cbcc/all_start_cb_writes_out_s0/Q
4.334 1.890 tNET RR 1 R23C109[2][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/n1416_s0/I2
4.797 0.463 tINS RR 2 R23C109[2][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/n1416_s0/F
4.920 0.123 tNET RR 1 R23C109[3][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/mod_do_wr_en_s1/I2
5.285 0.365 tINS RR 71 R23C109[3][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/mod_do_wr_en_s1/F
7.263 1.978 tNET RR 1 R23C92[3][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_30_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
10.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
12.139 2.140 tNET RR 1 R23C92[3][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_30_s0/CLK
11.891 -0.249 tSu 1 R23C92[3][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_30_s0

Path Statistics:

Clock Skew 0.001
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.138, 100.000%
Arrival Data Path Delay cell: 0.828, 16.156%; route: 3.991, 77.873%; tC2Q: 0.306, 5.971%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.140, 100.000%

Path12

Path Summary:

Slack 4.723
Data Arrival Time 7.156
Data Required Time 11.879
From u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/u_gtr12_common_logic_cbcc/all_start_cb_writes_out_s0
To u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_7_s0
Launch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
2.138 2.138 tNET RR 1 R12C90[0][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/u_gtr12_common_logic_cbcc/all_start_cb_writes_out_s0/CLK
2.444 0.306 tC2Q RR 3 R12C90[0][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/u_gtr12_common_logic_cbcc/all_start_cb_writes_out_s0/Q
4.334 1.890 tNET RR 1 R23C109[2][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/n1416_s0/I2
4.797 0.463 tINS RR 2 R23C109[2][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/n1416_s0/F
4.920 0.123 tNET RR 1 R23C109[3][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/mod_do_wr_en_s1/I2
5.285 0.365 tINS RR 71 R23C109[3][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/mod_do_wr_en_s1/F
7.156 1.871 tNET RR 1 R25C101[0][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_7_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
10.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
12.128 2.128 tNET RR 1 R25C101[0][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_7_s0/CLK
11.879 -0.249 tSu 1 R25C101[0][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_7_s0

Path Statistics:

Clock Skew -0.010
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.138, 100.000%
Arrival Data Path Delay cell: 0.828, 16.501%; route: 3.884, 77.401%; tC2Q: 0.306, 6.098%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.128, 100.000%

Path13

Path Summary:

Slack 4.723
Data Arrival Time 7.156
Data Required Time 11.879
From u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/u_gtr12_common_logic_cbcc/all_start_cb_writes_out_s0
To u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_13_s0
Launch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
2.138 2.138 tNET RR 1 R12C90[0][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/u_gtr12_common_logic_cbcc/all_start_cb_writes_out_s0/CLK
2.444 0.306 tC2Q RR 3 R12C90[0][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/u_gtr12_common_logic_cbcc/all_start_cb_writes_out_s0/Q
4.334 1.890 tNET RR 1 R23C109[2][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/n1416_s0/I2
4.797 0.463 tINS RR 2 R23C109[2][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/n1416_s0/F
4.920 0.123 tNET RR 1 R23C109[3][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/mod_do_wr_en_s1/I2
5.285 0.365 tINS RR 71 R23C109[3][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/mod_do_wr_en_s1/F
7.156 1.871 tNET RR 1 R25C101[0][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_13_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
10.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
12.128 2.128 tNET RR 1 R25C101[0][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_13_s0/CLK
11.879 -0.249 tSu 1 R25C101[0][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_13_s0

Path Statistics:

Clock Skew -0.010
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.138, 100.000%
Arrival Data Path Delay cell: 0.828, 16.501%; route: 3.884, 77.401%; tC2Q: 0.306, 6.098%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.128, 100.000%

Path14

Path Summary:

Slack 4.774
Data Arrival Time 7.281
Data Required Time 12.055
From u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/serdes_rx_dat_slip_2d_51_s0
To u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx2_66b_data_9_s0
Launch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
2.130 2.130 tNET RR 1 R8C114[2][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/serdes_rx_dat_slip_2d_51_s0/CLK
2.436 0.306 tC2Q RR 9 R8C114[2][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/serdes_rx_dat_slip_2d_51_s0/Q
4.982 2.546 tNET RR 1 R12C124[1][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/n912_s10/I0
5.436 0.454 tINS RR 3 R12C124[1][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/n912_s10/F
5.745 0.309 tNET RR 1 R14C125[3][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/n920_s8/I1
6.204 0.459 tINS RR 2 R14C125[3][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/n920_s8/F
6.875 0.671 tNET RR 1 R15C129[1][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/n924_s7/I1
7.281 0.406 tINS RR 1 R15C129[1][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/n924_s7/F
7.281 0.000 tNET RR 1 R15C129[1][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx2_66b_data_9_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
10.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
12.106 2.106 tNET RR 1 R15C129[1][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx2_66b_data_9_s0/CLK
12.055 -0.051 tSu 1 R15C129[1][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx2_66b_data_9_s0

Path Statistics:

Clock Skew -0.024
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.130, 100.000%
Arrival Data Path Delay cell: 1.319, 25.607%; route: 3.526, 68.453%; tC2Q: 0.306, 5.941%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.106, 100.000%

Path15

Path Summary:

Slack 4.791
Data Arrival Time 7.274
Data Required Time 12.066
From u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/serdes_rx_dat_slip_1d_10_s0
To u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx1_66b_data_46_s0
Launch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
2.113 2.113 tNET RR 1 R11C118[2][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/serdes_rx_dat_slip_1d_10_s0/CLK
2.419 0.306 tC2Q RR 10 R11C118[2][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/serdes_rx_dat_slip_1d_10_s0/Q
4.793 2.375 tNET RR 1 R11C111[0][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/n678_s8/I0
5.256 0.463 tINS RR 4 R11C111[0][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/n678_s8/F
6.820 1.564 tNET RR 1 R9C121[2][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/n686_s15/I0
7.274 0.454 tINS RR 1 R9C121[2][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/n686_s15/F
7.274 0.000 tNET RR 1 R9C121[2][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx1_66b_data_46_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
10.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
12.116 2.117 tNET RR 1 R9C121[2][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx1_66b_data_46_s0/CLK
12.066 -0.051 tSu 1 R9C121[2][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx1_66b_data_46_s0

Path Statistics:

Clock Skew 0.004
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.113, 100.000%
Arrival Data Path Delay cell: 0.917, 17.764%; route: 3.939, 76.308%; tC2Q: 0.306, 5.928%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.117, 100.000%

Path16

Path Summary:

Slack 4.842
Data Arrival Time 7.041
Data Required Time 11.883
From u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/u_gtr12_common_logic_cbcc/all_start_cb_writes_out_s0
To u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_32_s0
Launch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
2.138 2.138 tNET RR 1 R12C90[0][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/u_gtr12_common_logic_cbcc/all_start_cb_writes_out_s0/CLK
2.444 0.306 tC2Q RR 3 R12C90[0][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/u_gtr12_common_logic_cbcc/all_start_cb_writes_out_s0/Q
4.334 1.890 tNET RR 1 R23C109[2][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/n1416_s0/I2
4.797 0.463 tINS RR 2 R23C109[2][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/n1416_s0/F
4.920 0.123 tNET RR 1 R23C109[3][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/mod_do_wr_en_s1/I2
5.285 0.365 tINS RR 71 R23C109[3][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/mod_do_wr_en_s1/F
7.041 1.756 tNET RR 1 R23C93[1][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_32_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
10.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
12.132 2.132 tNET RR 1 R23C93[1][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_32_s0/CLK
11.883 -0.249 tSu 1 R23C93[1][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_32_s0

Path Statistics:

Clock Skew -0.006
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.138, 100.000%
Arrival Data Path Delay cell: 0.828, 16.888%; route: 3.769, 76.871%; tC2Q: 0.306, 6.241%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.132, 100.000%

Path17

Path Summary:

Slack 4.842
Data Arrival Time 7.041
Data Required Time 11.883
From u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/u_gtr12_common_logic_cbcc/all_start_cb_writes_out_s0
To u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_33_s0
Launch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
2.138 2.138 tNET RR 1 R12C90[0][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/u_gtr12_common_logic_cbcc/all_start_cb_writes_out_s0/CLK
2.444 0.306 tC2Q RR 3 R12C90[0][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/u_gtr12_common_logic_cbcc/all_start_cb_writes_out_s0/Q
4.334 1.890 tNET RR 1 R23C109[2][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/n1416_s0/I2
4.797 0.463 tINS RR 2 R23C109[2][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/n1416_s0/F
4.920 0.123 tNET RR 1 R23C109[3][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/mod_do_wr_en_s1/I2
5.285 0.365 tINS RR 71 R23C109[3][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/mod_do_wr_en_s1/F
7.041 1.756 tNET RR 1 R23C93[1][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_33_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
10.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
12.132 2.132 tNET RR 1 R23C93[1][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_33_s0/CLK
11.883 -0.249 tSu 1 R23C93[1][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_33_s0

Path Statistics:

Clock Skew -0.006
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.138, 100.000%
Arrival Data Path Delay cell: 0.828, 16.888%; route: 3.769, 76.871%; tC2Q: 0.306, 6.241%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.132, 100.000%

Path18

Path Summary:

Slack 4.859
Data Arrival Time 7.198
Data Required Time 12.057
From u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/serdes_rx_dat_slip_2d_51_s0
To u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx1_66b_data_33_s0
Launch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
2.130 2.130 tNET RR 1 R8C114[2][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/serdes_rx_dat_slip_2d_51_s0/CLK
2.436 0.306 tC2Q RR 9 R8C114[2][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/serdes_rx_dat_slip_2d_51_s0/Q
5.149 2.713 tNET RR 1 R12C125[2][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/n707_s9/I0
5.603 0.454 tINS RR 4 R12C125[2][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/n707_s9/F
6.744 1.141 tNET RR 1 R16C125[0][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/n699_s15/I1
7.198 0.454 tINS RR 1 R16C125[0][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/n699_s15/F
7.198 0.000 tNET RR 1 R16C125[0][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx1_66b_data_33_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
10.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
12.108 2.108 tNET RR 1 R16C125[0][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx1_66b_data_33_s0/CLK
12.057 -0.051 tSu 1 R16C125[0][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx1_66b_data_33_s0

Path Statistics:

Clock Skew -0.022
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.130, 100.000%
Arrival Data Path Delay cell: 0.908, 17.916%; route: 3.854, 76.046%; tC2Q: 0.306, 6.038%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.108, 100.000%

Path19

Path Summary:

Slack 4.894
Data Arrival Time 6.989
Data Required Time 11.883
From u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/u_gtr12_common_logic_cbcc/all_start_cb_writes_out_s0
To u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_8_s0
Launch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
2.138 2.138 tNET RR 1 R12C90[0][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/u_gtr12_common_logic_cbcc/all_start_cb_writes_out_s0/CLK
2.444 0.306 tC2Q RR 3 R12C90[0][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/u_gtr12_common_logic_cbcc/all_start_cb_writes_out_s0/Q
4.334 1.890 tNET RR 1 R23C109[2][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/n1416_s0/I2
4.797 0.463 tINS RR 2 R23C109[2][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/n1416_s0/F
4.920 0.123 tNET RR 1 R23C109[3][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/mod_do_wr_en_s1/I2
5.285 0.365 tINS RR 71 R23C109[3][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/mod_do_wr_en_s1/F
6.989 1.704 tNET RR 1 R23C101[0][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_8_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
10.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
12.132 2.132 tNET RR 1 R23C101[0][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_8_s0/CLK
11.883 -0.249 tSu 1 R23C101[0][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_8_s0

Path Statistics:

Clock Skew -0.006
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.138, 100.000%
Arrival Data Path Delay cell: 0.828, 17.069%; route: 3.717, 76.623%; tC2Q: 0.306, 6.308%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.132, 100.000%

Path20

Path Summary:

Slack 4.917
Data Arrival Time 6.910
Data Required Time 11.826
From u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/u_gtr12_common_reset_cbcc/cbcc_fifo_reset_wr_clk_s0
To u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_29_s0
Launch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
2.136 2.136 tNET RR 1 R25C126[0][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/u_gtr12_common_reset_cbcc/cbcc_fifo_reset_wr_clk_s0/CLK
2.442 0.306 tC2Q RR 163 R25C126[0][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/u_gtr12_common_reset_cbcc/cbcc_fifo_reset_wr_clk_s0/Q
6.910 4.468 tNET RR 1 R27C110[1][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_29_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
10.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
12.124 2.124 tNET RR 1 R27C110[1][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_29_s0/CLK
11.826 -0.298 tSu 1 R27C110[1][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_29_s0

Path Statistics:

Clock Skew -0.012
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.136, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 4.468, 93.590%; tC2Q: 0.306, 6.410%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.124, 100.000%

Path21

Path Summary:

Slack 4.922
Data Arrival Time 6.910
Data Required Time 11.832
From u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/u_gtr12_common_reset_cbcc/cbcc_fifo_reset_wr_clk_s0
To u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_29_s0
Launch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
2.136 2.136 tNET RR 1 R25C126[0][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/u_gtr12_common_reset_cbcc/cbcc_fifo_reset_wr_clk_s0/CLK
2.442 0.306 tC2Q RR 163 R25C126[0][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/u_gtr12_common_reset_cbcc/cbcc_fifo_reset_wr_clk_s0/Q
6.910 4.468 tNET RR 1 R26C110[1][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_29_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
10.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
12.130 2.130 tNET RR 1 R26C110[1][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_29_s0/CLK
11.832 -0.298 tSu 1 R26C110[1][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_29_s0

Path Statistics:

Clock Skew -0.006
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.136, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 4.468, 93.590%; tC2Q: 0.306, 6.410%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.130, 100.000%

Path22

Path Summary:

Slack 4.949
Data Arrival Time 7.117
Data Required Time 12.066
From u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/serdes_rx_dat_slip_2d_51_s0
To u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx1_66b_data_37_s0
Launch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
2.130 2.130 tNET RR 1 R8C114[2][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/serdes_rx_dat_slip_2d_51_s0/CLK
2.436 0.306 tC2Q RR 9 R8C114[2][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/serdes_rx_dat_slip_2d_51_s0/Q
5.149 2.713 tNET RR 1 R12C125[2][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/n707_s9/I0
5.603 0.454 tINS RR 4 R12C125[2][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/n707_s9/F
6.344 0.741 tNET RR 1 R9C125[3][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/n695_s9/I1
6.709 0.365 tINS RR 1 R9C125[3][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/n695_s9/F
6.711 0.002 tNET RR 1 R9C125[2][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/n695_s7/I3
7.117 0.406 tINS RR 1 R9C125[2][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/n695_s7/F
7.117 0.000 tNET RR 1 R9C125[2][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx1_66b_data_37_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
10.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
12.116 2.117 tNET RR 1 R9C125[2][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx1_66b_data_37_s0/CLK
12.066 -0.051 tSu 1 R9C125[2][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx1_66b_data_37_s0

Path Statistics:

Clock Skew -0.013
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.130, 100.000%
Arrival Data Path Delay cell: 1.225, 24.564%; route: 3.456, 69.300%; tC2Q: 0.306, 6.136%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.117, 100.000%

Path23

Path Summary:

Slack 4.962
Data Arrival Time 6.882
Data Required Time 11.844
From u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/u_gtr12_common_reset_cbcc/cbcc_fifo_reset_wr_clk_s0
To u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_40_s0
Launch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
2.136 2.136 tNET RR 1 R25C126[0][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/u_gtr12_common_reset_cbcc/cbcc_fifo_reset_wr_clk_s0/CLK
2.442 0.306 tC2Q RR 163 R25C126[0][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/u_gtr12_common_reset_cbcc/cbcc_fifo_reset_wr_clk_s0/Q
6.882 4.440 tNET RR 1 R22C112[0][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_40_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
10.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
12.142 2.141 tNET RR 1 R22C112[0][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_40_s0/CLK
11.844 -0.298 tSu 1 R22C112[0][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_40_s0

Path Statistics:

Clock Skew 0.006
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.136, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 4.440, 93.552%; tC2Q: 0.306, 6.448%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.141, 100.000%

Path24

Path Summary:

Slack 4.962
Data Arrival Time 6.882
Data Required Time 11.844
From u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/u_gtr12_common_reset_cbcc/cbcc_fifo_reset_wr_clk_s0
To u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_40_s0
Launch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
2.136 2.136 tNET RR 1 R25C126[0][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/u_gtr12_common_reset_cbcc/cbcc_fifo_reset_wr_clk_s0/CLK
2.442 0.306 tC2Q RR 163 R25C126[0][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/u_gtr12_common_reset_cbcc/cbcc_fifo_reset_wr_clk_s0/Q
6.882 4.440 tNET RR 1 R22C112[1][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_40_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
10.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
12.142 2.141 tNET RR 1 R22C112[1][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_40_s0/CLK
11.844 -0.298 tSu 1 R22C112[1][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_40_s0

Path Statistics:

Clock Skew 0.006
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.136, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 4.440, 93.552%; tC2Q: 0.306, 6.448%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.141, 100.000%

Path25

Path Summary:

Slack 4.974
Data Arrival Time 7.092
Data Required Time 12.066
From u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx_sequence1_1d_1_s0
To u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx1_66b_data_64_s0
Launch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
2.123 2.123 tNET RR 1 R16C119[3][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx_sequence1_1d_1_s0/CLK
2.429 0.306 tC2Q RR 127 R16C119[3][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx_sequence1_1d_1_s0/Q
5.629 3.200 tNET RR 1 R12C113[3][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/n668_s18/I3
6.067 0.438 tINS RR 1 R12C113[3][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/n668_s18/F
6.638 0.571 tNET RR 1 R9C113[1][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/n668_s16/I3
7.092 0.454 tINS RR 1 R9C113[1][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/n668_s16/F
7.092 0.000 tNET RR 1 R9C113[1][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx1_66b_data_64_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
10.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
12.116 2.117 tNET RR 1 R9C113[1][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx1_66b_data_64_s0/CLK
12.066 -0.051 tSu 1 R9C113[1][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx1_66b_data_64_s0

Path Statistics:

Clock Skew -0.006
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.123, 100.000%
Arrival Data Path Delay cell: 0.892, 17.950%; route: 3.771, 75.892%; tC2Q: 0.306, 6.158%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.117, 100.000%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 0.026
Data Arrival Time 1.232
Data Required Time 1.206
From u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_53_s0
To u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s
Launch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
0.992 0.992 tNET RR 1 R27C117[2][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_53_s0/CLK
1.136 0.144 tC2Q RR 2 R27C117[2][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_53_s0/Q
1.232 0.096 tNET RR 1 BSRAM_R28[22] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/DI[17]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
0.991 0.991 tNET RR 1 BSRAM_R28[22] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/CLKA
1.206 0.215 tHld 1 BSRAM_R28[22] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s

Path Statistics:

Clock Skew -0.001
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.992, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.096, 40.000%; tC2Q: 0.144, 60.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.991, 100.000%

Path2

Path Summary:

Slack 0.030
Data Arrival Time 1.236
Data Required Time 1.206
From u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_68_s0
To u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s
Launch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
0.996 0.996 tNET RR 1 R27C118[1][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_68_s0/CLK
1.140 0.144 tC2Q RR 2 R27C118[1][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_68_s0/Q
1.236 0.096 tNET RR 1 BSRAM_R28[22] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/DI[31]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
0.991 0.991 tNET RR 1 BSRAM_R28[22] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/CLKA
1.206 0.215 tHld 1 BSRAM_R28[22] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s

Path Statistics:

Clock Skew -0.005
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.996, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.096, 40.000%; tC2Q: 0.144, 60.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.991, 100.000%

Path3

Path Summary:

Slack 0.030
Data Arrival Time 1.236
Data Required Time 1.206
From u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_63_s0
To u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s
Launch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
0.996 0.996 tNET RR 1 R27C118[2][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_63_s0/CLK
1.140 0.144 tC2Q RR 2 R27C118[2][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_63_s0/Q
1.236 0.096 tNET RR 1 BSRAM_R28[22] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/DI[27]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
0.991 0.991 tNET RR 1 BSRAM_R28[22] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/CLKA
1.206 0.215 tHld 1 BSRAM_R28[22] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s

Path Statistics:

Clock Skew -0.005
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.996, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.096, 40.000%; tC2Q: 0.144, 60.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.991, 100.000%

Path4

Path Summary:

Slack 0.038
Data Arrival Time 1.244
Data Required Time 1.206
From u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_64_s0
To u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s
Launch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
1.001 1.001 tNET RR 1 R26C118[1][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_64_s0/CLK
1.145 0.144 tC2Q RR 1 R26C118[1][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_64_s0/Q
1.244 0.099 tNET RR 1 BSRAM_R28[22] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/DI[28]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
0.991 0.991 tNET RR 1 BSRAM_R28[22] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/CLKA
1.206 0.215 tHld 1 BSRAM_R28[22] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s

Path Statistics:

Clock Skew -0.010
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.001, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.099, 40.741%; tC2Q: 0.144, 59.259%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.991, 100.000%

Path5

Path Summary:

Slack 0.113
Data Arrival Time 1.319
Data Required Time 1.206
From u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_66_s0
To u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s
Launch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
1.001 1.001 tNET RR 1 R26C118[3][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_66_s0/CLK
1.145 0.144 tC2Q RR 1 R26C118[3][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_66_s0/Q
1.319 0.174 tNET RR 1 BSRAM_R28[22] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/DI[30]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
0.991 0.991 tNET RR 1 BSRAM_R28[22] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/CLKA
1.206 0.215 tHld 1 BSRAM_R28[22] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s

Path Statistics:

Clock Skew -0.010
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.001, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.174, 54.717%; tC2Q: 0.144, 45.283%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.991, 100.000%

Path6

Path Summary:

Slack 0.113
Data Arrival Time 1.319
Data Required Time 1.206
From u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_65_s0
To u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s
Launch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
1.001 1.001 tNET RR 1 R26C118[3][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_65_s0/CLK
1.145 0.144 tC2Q RR 1 R26C118[3][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_65_s0/Q
1.319 0.174 tNET RR 1 BSRAM_R28[22] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/DI[29]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
0.991 0.991 tNET RR 1 BSRAM_R28[22] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/CLKA
1.206 0.215 tHld 1 BSRAM_R28[22] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s

Path Statistics:

Clock Skew -0.010
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.001, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.174, 54.717%; tC2Q: 0.144, 45.283%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.991, 100.000%

Path7

Path Summary:

Slack 0.126
Data Arrival Time 1.332
Data Required Time 1.206
From u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_61_s0
To u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s
Launch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
0.996 0.996 tNET RR 1 R27C118[1][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_61_s0/CLK
1.140 0.144 tC2Q RR 2 R27C118[1][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_61_s0/Q
1.332 0.192 tNET RR 1 BSRAM_R28[22] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/DI[25]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
0.991 0.991 tNET RR 1 BSRAM_R28[22] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/CLKA
1.206 0.215 tHld 1 BSRAM_R28[22] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s

Path Statistics:

Clock Skew -0.005
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.996, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.192, 57.143%; tC2Q: 0.144, 42.857%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.991, 100.000%

Path8

Path Summary:

Slack 0.147
Data Arrival Time 1.352
Data Required Time 1.206
From u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_45_s0
To u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s
Launch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
1.011 1.011 tNET RR 1 R22C114[1][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_45_s0/CLK
1.155 0.144 tC2Q RR 1 R22C114[1][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_45_s0/Q
1.352 0.197 tNET RR 1 BSRAM_R28[22] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/DI[9]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
0.991 0.991 tNET RR 1 BSRAM_R28[22] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/CLKA
1.206 0.215 tHld 1 BSRAM_R28[22] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s

Path Statistics:

Clock Skew -0.020
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.011, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.197, 57.771%; tC2Q: 0.144, 42.229%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.991, 100.000%

Path9

Path Summary:

Slack 0.147
Data Arrival Time 1.353
Data Required Time 1.206
From u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_60_s0
To u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s
Launch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
0.992 0.992 tNET RR 1 R27C117[3][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_60_s0/CLK
1.136 0.144 tC2Q RR 2 R27C117[3][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_60_s0/Q
1.353 0.217 tNET RR 1 BSRAM_R28[22] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/DI[24]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
0.991 0.991 tNET RR 1 BSRAM_R28[22] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/CLKA
1.206 0.215 tHld 1 BSRAM_R28[22] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s

Path Statistics:

Clock Skew -0.001
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.992, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.217, 60.111%; tC2Q: 0.144, 39.889%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.991, 100.000%

Path10

Path Summary:

Slack 0.181
Data Arrival Time 1.387
Data Required Time 1.206
From u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_62_s0
To u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s
Launch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
1.006 1.006 tNET RR 1 R25C118[0][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_62_s0/CLK
1.150 0.144 tC2Q RR 2 R25C118[0][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_62_s0/Q
1.387 0.237 tNET RR 1 BSRAM_R28[22] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/DI[26]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
0.991 0.991 tNET RR 1 BSRAM_R28[22] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/CLKA
1.206 0.215 tHld 1 BSRAM_R28[22] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s

Path Statistics:

Clock Skew -0.015
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.006, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.237, 62.205%; tC2Q: 0.144, 37.795%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.991, 100.000%

Path11

Path Summary:

Slack 0.198
Data Arrival Time 1.400
Data Required Time 1.202
From u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_5_s0
To u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s
Launch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
0.997 0.997 tNET RR 1 R26C105[2][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_5_s0/CLK
1.141 0.144 tC2Q RR 1 R26C105[2][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_5_s0/Q
1.400 0.259 tNET RR 1 BSRAM_R28[21][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s/DI[5]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
0.987 0.987 tNET RR 1 BSRAM_R28[21][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s/CLKA
1.202 0.215 tHld 1 BSRAM_R28[21][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s

Path Statistics:

Clock Skew -0.010
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.997, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.259, 64.268%; tC2Q: 0.144, 35.732%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.987, 100.000%

Path12

Path Summary:

Slack 0.205
Data Arrival Time 1.411
Data Required Time 1.206
From u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_59_s0
To u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s
Launch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
1.001 1.001 tNET RR 1 R26C118[0][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_59_s0/CLK
1.145 0.144 tC2Q RR 2 R26C118[0][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_59_s0/Q
1.411 0.266 tNET RR 1 BSRAM_R28[22] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/DI[23]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
0.991 0.991 tNET RR 1 BSRAM_R28[22] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/CLKA
1.206 0.215 tHld 1 BSRAM_R28[22] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s

Path Statistics:

Clock Skew -0.010
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.001, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.266, 64.878%; tC2Q: 0.144, 35.122%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.991, 100.000%

Path13

Path Summary:

Slack 0.206
Data Arrival Time 1.412
Data Required Time 1.206
From u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_52_s0
To u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s
Launch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
1.002 1.002 tNET RR 1 R25C117[0][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_52_s0/CLK
1.146 0.144 tC2Q RR 2 R25C117[0][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_52_s0/Q
1.412 0.266 tNET RR 1 BSRAM_R28[22] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/DI[16]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
0.991 0.991 tNET RR 1 BSRAM_R28[22] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/CLKA
1.206 0.215 tHld 1 BSRAM_R28[22] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s

Path Statistics:

Clock Skew -0.011
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.002, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.266, 64.878%; tC2Q: 0.144, 35.122%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.991, 100.000%

Path14

Path Summary:

Slack 0.206
Data Arrival Time 1.412
Data Required Time 1.206
From u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_50_s0
To u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s
Launch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
1.001 1.001 tNET RR 1 R26C118[2][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_50_s0/CLK
1.145 0.144 tC2Q RR 2 R26C118[2][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_50_s0/Q
1.412 0.267 tNET RR 1 BSRAM_R28[22] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/DI[14]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
0.991 0.991 tNET RR 1 BSRAM_R28[22] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/CLKA
1.206 0.215 tHld 1 BSRAM_R28[22] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s

Path Statistics:

Clock Skew -0.010
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.001, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.267, 64.964%; tC2Q: 0.144, 35.036%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.991, 100.000%

Path15

Path Summary:

Slack 0.229
Data Arrival Time 1.431
Data Required Time 1.202
From u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_21_s0
To u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s
Launch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
1.002 1.002 tNET RR 1 R25C113[2][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_21_s0/CLK
1.146 0.144 tC2Q RR 1 R25C113[2][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_21_s0/Q
1.431 0.285 tNET RR 1 BSRAM_R28[21][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s/DI[21]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
0.987 0.987 tNET RR 1 BSRAM_R28[21][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s/CLKA
1.202 0.215 tHld 1 BSRAM_R28[21][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s

Path Statistics:

Clock Skew -0.015
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.002, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.285, 66.434%; tC2Q: 0.144, 33.566%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.987, 100.000%

Path16

Path Summary:

Slack 0.232
Data Arrival Time 1.438
Data Required Time 1.206
From u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_58_s0
To u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s
Launch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
1.006 1.006 tNET RR 1 R25C116[1][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_58_s0/CLK
1.150 0.144 tC2Q RR 2 R25C116[1][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_58_s0/Q
1.438 0.288 tNET RR 1 BSRAM_R28[22] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/DI[22]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
0.991 0.991 tNET RR 1 BSRAM_R28[22] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/CLKA
1.206 0.215 tHld 1 BSRAM_R28[22] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s

Path Statistics:

Clock Skew -0.015
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.006, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.288, 66.667%; tC2Q: 0.144, 33.333%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.991, 100.000%

Path17

Path Summary:

Slack 0.243
Data Arrival Time 1.448
Data Required Time 1.206
From u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_46_s0
To u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s
Launch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
1.011 1.011 tNET RR 1 R22C114[1][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_46_s0/CLK
1.155 0.144 tC2Q RR 1 R22C114[1][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_46_s0/Q
1.448 0.293 tNET RR 1 BSRAM_R28[22] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/DI[10]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
0.991 0.991 tNET RR 1 BSRAM_R28[22] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/CLKA
1.206 0.215 tHld 1 BSRAM_R28[22] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s

Path Statistics:

Clock Skew -0.020
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.011, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.293, 67.048%; tC2Q: 0.144, 32.952%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.991, 100.000%

Path18

Path Summary:

Slack 0.252
Data Arrival Time 1.458
Data Required Time 1.206
From u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_54_s0
To u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s
Launch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
1.002 1.002 tNET RR 1 R25C117[0][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_54_s0/CLK
1.146 0.144 tC2Q RR 2 R25C117[0][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_54_s0/Q
1.458 0.312 tNET RR 1 BSRAM_R28[22] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/DI[18]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
0.991 0.991 tNET RR 1 BSRAM_R28[22] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/CLKA
1.206 0.215 tHld 1 BSRAM_R28[22] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s

Path Statistics:

Clock Skew -0.011
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.002, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.312, 68.421%; tC2Q: 0.144, 31.579%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.991, 100.000%

Path19

Path Summary:

Slack 0.259
Data Arrival Time 1.464
Data Required Time 1.206
From u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_47_s0
To u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s
Launch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
1.011 1.011 tNET RR 1 R22C114[0][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_47_s0/CLK
1.155 0.144 tC2Q RR 1 R22C114[0][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_47_s0/Q
1.464 0.309 tNET RR 1 BSRAM_R28[22] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/DI[11]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
0.991 0.991 tNET RR 1 BSRAM_R28[22] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/CLKA
1.206 0.215 tHld 1 BSRAM_R28[22] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s

Path Statistics:

Clock Skew -0.020
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.011, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.309, 68.212%; tC2Q: 0.144, 31.788%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.991, 100.000%

Path20

Path Summary:

Slack 0.267
Data Arrival Time 1.473
Data Required Time 1.206
From u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_51_s0
To u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s
Launch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
1.001 1.001 tNET RR 1 R26C118[2][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_51_s0/CLK
1.145 0.144 tC2Q RR 2 R26C118[2][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_51_s0/Q
1.473 0.328 tNET RR 1 BSRAM_R28[22] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/DI[15]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
0.991 0.991 tNET RR 1 BSRAM_R28[22] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/CLKA
1.206 0.215 tHld 1 BSRAM_R28[22] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s

Path Statistics:

Clock Skew -0.010
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.001, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.328, 69.492%; tC2Q: 0.144, 30.508%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.991, 100.000%

Path21

Path Summary:

Slack 0.269
Data Arrival Time 1.471
Data Required Time 1.202
From u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_22_s0
To u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s
Launch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
1.002 1.002 tNET RR 1 R25C113[1][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_22_s0/CLK
1.146 0.144 tC2Q RR 1 R25C113[1][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_22_s0/Q
1.471 0.325 tNET RR 1 BSRAM_R28[21][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s/DI[22]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
0.987 0.987 tNET RR 1 BSRAM_R28[21][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s/CLKA
1.202 0.215 tHld 1 BSRAM_R28[21][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s

Path Statistics:

Clock Skew -0.015
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.002, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.325, 69.296%; tC2Q: 0.144, 30.704%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.987, 100.000%

Path22

Path Summary:

Slack 0.277
Data Arrival Time 1.479
Data Required Time 1.202
From u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_25_s0
To u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s
Launch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
1.001 1.001 tNET RR 1 R26C106[0][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_25_s0/CLK
1.145 0.144 tC2Q RR 1 R26C106[0][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_25_s0/Q
1.479 0.334 tNET RR 1 BSRAM_R28[21][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s/DI[25]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
0.987 0.987 tNET RR 1 BSRAM_R28[21][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s/CLKA
1.202 0.215 tHld 1 BSRAM_R28[21][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s

Path Statistics:

Clock Skew -0.014
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.001, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.334, 69.874%; tC2Q: 0.144, 30.126%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.987, 100.000%

Path23

Path Summary:

Slack 0.277
Data Arrival Time 1.479
Data Required Time 1.202
From u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_23_s0
To u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s
Launch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
1.001 1.001 tNET RR 1 R26C106[0][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_23_s0/CLK
1.145 0.144 tC2Q RR 1 R26C106[0][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_23_s0/Q
1.479 0.334 tNET RR 1 BSRAM_R28[21][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s/DI[23]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
0.987 0.987 tNET RR 1 BSRAM_R28[21][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s/CLKA
1.202 0.215 tHld 1 BSRAM_R28[21][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s

Path Statistics:

Clock Skew -0.014
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.001, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.334, 69.874%; tC2Q: 0.144, 30.126%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.987, 100.000%

Path24

Path Summary:

Slack 0.288
Data Arrival Time 1.490
Data Required Time 1.202
From u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_24_s0
To u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s
Launch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
0.997 0.997 tNET RR 1 R26C105[2][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_24_s0/CLK
1.141 0.144 tC2Q RR 1 R26C105[2][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_24_s0/Q
1.490 0.349 tNET RR 1 BSRAM_R28[21][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s/DI[24]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
0.987 0.987 tNET RR 1 BSRAM_R28[21][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s/CLKA
1.202 0.215 tHld 1 BSRAM_R28[21][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s

Path Statistics:

Clock Skew -0.010
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.997, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.349, 70.791%; tC2Q: 0.144, 29.209%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.987, 100.000%

Path25

Path Summary:

Slack 0.294
Data Arrival Time 1.496
Data Required Time 1.202
From u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_28_s0
To u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s
Launch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
0.997 0.997 tNET RR 1 R26C105[0][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_28_s0/CLK
1.141 0.144 tC2Q RR 1 R26C105[0][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_2stage_28_s0/Q
1.496 0.355 tNET RR 1 BSRAM_R28[21][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s/DI[28]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
0.987 0.987 tNET RR 1 BSRAM_R28[21][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s/CLKA
1.202 0.215 tHld 1 BSRAM_R28[21][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s

Path Statistics:

Clock Skew -0.010
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.997, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.355, 71.142%; tC2Q: 0.144, 28.858%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.987, 100.000%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 4.781
Data Arrival Time 7.053
Data Required Time 11.834
From u1_reset_gen/o_rst1_s1
To u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/rx_rst_srl_0_s0
Launch Clk cfg_clk:[R]
Latch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 cfg_clk
0.000 0.000 tCL RR 2032 PLL_R[3] u_Gowin_PLL/PLL_inst/CLKOUT0
2.118 2.118 tNET RR 1 R18C129[1][A] u1_reset_gen/o_rst1_s1/CLK
2.424 0.306 tC2Q RR 444 R18C129[1][A] u1_reset_gen/o_rst1_s1/Q
4.191 1.767 tNET RR 1 R27C121[0][B] gt_pma_rstn_s0/I1
4.645 0.454 tINS RR 3 R27C121[0][B] gt_pma_rstn_s0/F
6.417 1.772 tNET RR 1 R6C115[0][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/rx_arst_s1/I3
6.760 0.343 tINS RF 3 R6C115[0][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/rx_arst_s1/F
7.053 0.293 tNET FF 1 R5C115[1][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/rx_rst_srl_0_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
10.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
12.147 2.147 tNET RR 1 R5C115[1][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/rx_rst_srl_0_s0/CLK
12.112 -0.035 tUnc u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/rx_rst_srl_0_s0
11.834 -0.278 tSu 1 R5C115[1][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/rx_rst_srl_0_s0

Path Statistics:

Clock Skew 0.029
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.118, 100.000%
Arrival Data Path Delay cell: 0.797, 16.150%; route: 3.832, 77.649%; tC2Q: 0.306, 6.201%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.147, 100.000%

Path2

Path Summary:

Slack 4.781
Data Arrival Time 7.053
Data Required Time 11.834
From u1_reset_gen/o_rst1_s1
To u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/rx_rst_srl_1_s0
Launch Clk cfg_clk:[R]
Latch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 cfg_clk
0.000 0.000 tCL RR 2032 PLL_R[3] u_Gowin_PLL/PLL_inst/CLKOUT0
2.118 2.118 tNET RR 1 R18C129[1][A] u1_reset_gen/o_rst1_s1/CLK
2.424 0.306 tC2Q RR 444 R18C129[1][A] u1_reset_gen/o_rst1_s1/Q
4.191 1.767 tNET RR 1 R27C121[0][B] gt_pma_rstn_s0/I1
4.645 0.454 tINS RR 3 R27C121[0][B] gt_pma_rstn_s0/F
6.417 1.772 tNET RR 1 R6C115[0][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/rx_arst_s1/I3
6.760 0.343 tINS RF 3 R6C115[0][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/rx_arst_s1/F
7.053 0.293 tNET FF 1 R5C115[0][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/rx_rst_srl_1_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
10.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
12.147 2.147 tNET RR 1 R5C115[0][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/rx_rst_srl_1_s0/CLK
12.112 -0.035 tUnc u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/rx_rst_srl_1_s0
11.834 -0.278 tSu 1 R5C115[0][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/rx_rst_srl_1_s0

Path Statistics:

Clock Skew 0.029
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.118, 100.000%
Arrival Data Path Delay cell: 0.797, 16.150%; route: 3.832, 77.649%; tC2Q: 0.306, 6.201%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.147, 100.000%

Path3

Path Summary:

Slack 4.781
Data Arrival Time 7.053
Data Required Time 11.834
From u1_reset_gen/o_rst1_s1
To u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/rx_rst_srl_2_s0
Launch Clk cfg_clk:[R]
Latch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 cfg_clk
0.000 0.000 tCL RR 2032 PLL_R[3] u_Gowin_PLL/PLL_inst/CLKOUT0
2.118 2.118 tNET RR 1 R18C129[1][A] u1_reset_gen/o_rst1_s1/CLK
2.424 0.306 tC2Q RR 444 R18C129[1][A] u1_reset_gen/o_rst1_s1/Q
4.191 1.767 tNET RR 1 R27C121[0][B] gt_pma_rstn_s0/I1
4.645 0.454 tINS RR 3 R27C121[0][B] gt_pma_rstn_s0/F
6.417 1.772 tNET RR 1 R6C115[0][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/rx_arst_s1/I3
6.760 0.343 tINS RF 3 R6C115[0][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/rx_arst_s1/F
7.053 0.293 tNET FF 1 R5C115[0][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/rx_rst_srl_2_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
10.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
12.147 2.147 tNET RR 1 R5C115[0][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/rx_rst_srl_2_s0/CLK
12.112 -0.035 tUnc u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/rx_rst_srl_2_s0
11.834 -0.278 tSu 1 R5C115[0][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/rx_rst_srl_2_s0

Path Statistics:

Clock Skew 0.029
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.118, 100.000%
Arrival Data Path Delay cell: 0.797, 16.150%; route: 3.832, 77.649%; tC2Q: 0.306, 6.201%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.147, 100.000%

Path4

Path Summary:

Slack 7.643
Data Arrival Time 14.193
Data Required Time 21.836
From u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s1
To u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/hpcnt_reset_srl_2_s0
Launch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk cfg_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
10.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
12.130 2.130 tNET RR 1 R26C112[0][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s1/CLK
12.424 0.294 tC2Q RF 17 R26C112[0][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s1/Q
13.583 1.159 tNET FF 1 R23C124[1][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/hpcnt_reset_async_s1/I1
13.926 0.343 tINS FF 7 R23C124[1][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/hpcnt_reset_async_s1/F
14.193 0.267 tNET FF 1 R22C124[0][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/hpcnt_reset_srl_2_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 cfg_clk
20.000 0.000 tCL RR 2032 PLL_R[3] u_Gowin_PLL/PLL_inst/CLKOUT0
22.149 2.149 tNET RR 1 R22C124[0][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/hpcnt_reset_srl_2_s0/CLK
22.114 -0.035 tUnc u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/hpcnt_reset_srl_2_s0
21.836 -0.278 tSu 1 R22C124[0][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/hpcnt_reset_srl_2_s0

Path Statistics:

Clock Skew 0.019
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.130, 100.000%
Arrival Data Path Delay cell: 0.343, 16.626%; route: 1.426, 69.123%; tC2Q: 0.294, 14.251%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.149, 100.000%

Path5

Path Summary:

Slack 7.643
Data Arrival Time 14.193
Data Required Time 21.836
From u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s1
To u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/hpcnt_reset_srl_0_s0
Launch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk cfg_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
10.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
12.130 2.130 tNET RR 1 R26C112[0][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s1/CLK
12.424 0.294 tC2Q RF 17 R26C112[0][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s1/Q
13.583 1.159 tNET FF 1 R23C124[1][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/hpcnt_reset_async_s1/I1
13.926 0.343 tINS FF 7 R23C124[1][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/hpcnt_reset_async_s1/F
14.193 0.267 tNET FF 1 R22C124[1][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/hpcnt_reset_srl_0_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 cfg_clk
20.000 0.000 tCL RR 2032 PLL_R[3] u_Gowin_PLL/PLL_inst/CLKOUT0
22.149 2.149 tNET RR 1 R22C124[1][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/hpcnt_reset_srl_0_s0/CLK
22.114 -0.035 tUnc u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/hpcnt_reset_srl_0_s0
21.836 -0.278 tSu 1 R22C124[1][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/hpcnt_reset_srl_0_s0

Path Statistics:

Clock Skew 0.019
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.130, 100.000%
Arrival Data Path Delay cell: 0.343, 16.626%; route: 1.426, 69.123%; tC2Q: 0.294, 14.251%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.149, 100.000%

Path6

Path Summary:

Slack 7.643
Data Arrival Time 14.193
Data Required Time 21.836
From u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s1
To u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/hpcnt_reset_srl_1_s0
Launch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk cfg_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
10.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
12.130 2.130 tNET RR 1 R26C112[0][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s1/CLK
12.424 0.294 tC2Q RF 17 R26C112[0][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s1/Q
13.583 1.159 tNET FF 1 R23C124[1][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/hpcnt_reset_async_s1/I1
13.926 0.343 tINS FF 7 R23C124[1][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/hpcnt_reset_async_s1/F
14.193 0.267 tNET FF 1 R22C124[0][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/hpcnt_reset_srl_1_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 cfg_clk
20.000 0.000 tCL RR 2032 PLL_R[3] u_Gowin_PLL/PLL_inst/CLKOUT0
22.149 2.149 tNET RR 1 R22C124[0][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/hpcnt_reset_srl_1_s0/CLK
22.114 -0.035 tUnc u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/hpcnt_reset_srl_1_s0
21.836 -0.278 tSu 1 R22C124[0][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/hpcnt_reset_srl_1_s0

Path Statistics:

Clock Skew 0.019
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.130, 100.000%
Arrival Data Path Delay cell: 0.343, 16.626%; route: 1.426, 69.123%; tC2Q: 0.294, 14.251%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.149, 100.000%

Path7

Path Summary:

Slack 7.959
Data Arrival Time 3.912
Data Required Time 11.871
From u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s1
To u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_headsync/fsm_st_curr_0_s0
Launch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
2.130 2.130 tNET RR 1 R26C112[0][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s1/CLK
2.424 0.294 tC2Q RF 17 R26C112[0][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s1/Q
3.912 1.488 tNET FF 1 R22C123[1][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_headsync/fsm_st_curr_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
10.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
12.149 2.149 tNET RR 1 R22C123[1][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_headsync/fsm_st_curr_0_s0/CLK
11.871 -0.278 tSu 1 R22C123[1][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_headsync/fsm_st_curr_0_s0

Path Statistics:

Clock Skew 0.019
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.130, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.488, 83.502%; tC2Q: 0.294, 16.498%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.149, 100.000%

Path8

Path Summary:

Slack 7.961
Data Arrival Time 3.912
Data Required Time 11.873
From u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s1
To u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_headsync/fsm_st_curr_1_s0
Launch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
2.130 2.130 tNET RR 1 R26C112[0][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s1/CLK
2.424 0.294 tC2Q RF 17 R26C112[0][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s1/Q
3.912 1.488 tNET FF 1 R21C123[1][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_headsync/fsm_st_curr_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
10.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
12.151 2.151 tNET RR 1 R21C123[1][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_headsync/fsm_st_curr_1_s0/CLK
11.873 -0.278 tSu 1 R21C123[1][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_headsync/fsm_st_curr_1_s0

Path Statistics:

Clock Skew 0.021
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.130, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.488, 83.502%; tC2Q: 0.294, 16.498%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.151, 100.000%

Path9

Path Summary:

Slack 8.145
Data Arrival Time 3.715
Data Required Time 11.860
From u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s1
To u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_headsync/fsm_st_curr_2_s0
Launch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
2.130 2.130 tNET RR 1 R26C112[0][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s1/CLK
2.424 0.294 tC2Q RF 17 R26C112[0][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s1/Q
3.715 1.291 tNET FF 1 R20C125[0][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_headsync/fsm_st_curr_2_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
10.000 0.000 tCL RR 2141 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
12.138 2.138 tNET RR 1 R20C125[0][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_headsync/fsm_st_curr_2_s0/CLK
11.860 -0.278 tSu 1 R20C125[0][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_headsync/fsm_st_curr_2_s0

Path Statistics:

Clock Skew 0.008
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.130, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.291, 81.451%; tC2Q: 0.294, 18.549%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.138, 100.000%

Path10

Path Summary:

Slack 14.188
Data Arrival Time 8.336
Data Required Time 22.524
From u_SerDes_Top/RoraLink_64B66B_Top_inst/gt_pll_ok_o_s2
To u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/tx_rst_srl_2_s0
Launch Clk sys_clk:[R]
Latch Clk sys_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sys_clk
0.000 0.000 tCL RR 4394 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
2.331 2.331 tNET RR 1 R5C99[1][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/gt_pll_ok_o_s2/CLK
2.637 0.306 tC2Q RR 9 R5C99[1][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/gt_pll_ok_o_s2/Q
6.183 3.546 tNET RR 1 R33C121[0][A] gt_pcs_tx_rst_s1/I2
6.646 0.463 tINS RR 2 R33C121[0][A] gt_pcs_tx_rst_s1/F
7.687 1.041 tNET RR 1 R27C112[1][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/tx_arst_s1/I1
8.021 0.334 tINS RF 3 R27C112[1][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/tx_arst_s1/F
8.337 0.316 tNET FF 1 R27C110[2][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/tx_rst_srl_2_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.480 20.480 active clock edge time
20.480 0.000 sys_clk
20.480 0.000 tCL RR 4394 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
22.802 2.322 tNET RR 1 R27C110[2][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/tx_rst_srl_2_s0/CLK
22.524 -0.278 tSu 1 R27C110[2][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/tx_rst_srl_2_s0

Path Statistics:

Clock Skew -0.008
Setup Relationship 20.480
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.331, 100.000%
Arrival Data Path Delay cell: 0.797, 13.270%; route: 4.903, 81.635%; tC2Q: 0.306, 5.095%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.322, 100.000%

Path11

Path Summary:

Slack 14.188
Data Arrival Time 8.336
Data Required Time 22.524
From u_SerDes_Top/RoraLink_64B66B_Top_inst/gt_pll_ok_o_s2
To u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/tx_rst_srl_0_s0
Launch Clk sys_clk:[R]
Latch Clk sys_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sys_clk
0.000 0.000 tCL RR 4394 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
2.331 2.331 tNET RR 1 R5C99[1][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/gt_pll_ok_o_s2/CLK
2.637 0.306 tC2Q RR 9 R5C99[1][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/gt_pll_ok_o_s2/Q
6.183 3.546 tNET RR 1 R33C121[0][A] gt_pcs_tx_rst_s1/I2
6.646 0.463 tINS RR 2 R33C121[0][A] gt_pcs_tx_rst_s1/F
7.687 1.041 tNET RR 1 R27C112[1][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/tx_arst_s1/I1
8.021 0.334 tINS RF 3 R27C112[1][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/tx_arst_s1/F
8.337 0.316 tNET FF 1 R27C110[3][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/tx_rst_srl_0_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.480 20.480 active clock edge time
20.480 0.000 sys_clk
20.480 0.000 tCL RR 4394 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
22.802 2.322 tNET RR 1 R27C110[3][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/tx_rst_srl_0_s0/CLK
22.524 -0.278 tSu 1 R27C110[3][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/tx_rst_srl_0_s0

Path Statistics:

Clock Skew -0.008
Setup Relationship 20.480
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.331, 100.000%
Arrival Data Path Delay cell: 0.797, 13.270%; route: 4.903, 81.635%; tC2Q: 0.306, 5.095%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.322, 100.000%

Path12

Path Summary:

Slack 14.188
Data Arrival Time 8.336
Data Required Time 22.524
From u_SerDes_Top/RoraLink_64B66B_Top_inst/gt_pll_ok_o_s2
To u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/tx_rst_srl_1_s0
Launch Clk sys_clk:[R]
Latch Clk sys_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sys_clk
0.000 0.000 tCL RR 4394 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
2.331 2.331 tNET RR 1 R5C99[1][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/gt_pll_ok_o_s2/CLK
2.637 0.306 tC2Q RR 9 R5C99[1][A] u_SerDes_Top/RoraLink_64B66B_Top_inst/gt_pll_ok_o_s2/Q
6.183 3.546 tNET RR 1 R33C121[0][A] gt_pcs_tx_rst_s1/I2
6.646 0.463 tINS RR 2 R33C121[0][A] gt_pcs_tx_rst_s1/F
7.687 1.041 tNET RR 1 R27C112[1][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/tx_arst_s1/I1
8.021 0.334 tINS RF 3 R27C112[1][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/tx_arst_s1/F
8.337 0.316 tNET FF 1 R27C110[2][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/tx_rst_srl_1_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.480 20.480 active clock edge time
20.480 0.000 sys_clk
20.480 0.000 tCL RR 4394 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
22.802 2.322 tNET RR 1 R27C110[2][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/tx_rst_srl_1_s0/CLK
22.524 -0.278 tSu 1 R27C110[2][B] u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/tx_rst_srl_1_s0

Path Statistics:

Clock Skew -0.008
Setup Relationship 20.480
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.331, 100.000%
Arrival Data Path Delay cell: 0.797, 13.270%; route: 4.903, 81.635%; tC2Q: 0.306, 5.095%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.322, 100.000%

Path13

Path Summary:

Slack 16.352
Data Arrival Time 5.508
Data Required Time 21.860
From u1_reset_gen/o_rst1_s1
To u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/tb_delay_0_s1
Launch Clk cfg_clk:[R]
Latch Clk cfg_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 cfg_clk
0.000 0.000 tCL RR 2032 PLL_R[3] u_Gowin_PLL/PLL_inst/CLKOUT0
2.118 2.118 tNET RR 1 R18C129[1][A] u1_reset_gen/o_rst1_s1/CLK
2.412 0.294 tC2Q RF 444 R18C129[1][A] u1_reset_gen/o_rst1_s1/Q
5.508 3.096 tNET FF 1 R2C142[3][A] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/tb_delay_0_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 cfg_clk
20.000 0.000 tCL RR 2032 PLL_R[3] u_Gowin_PLL/PLL_inst/CLKOUT0
22.138 2.138 tNET RR 1 R2C142[3][A] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/tb_delay_0_s1/CLK
21.860 -0.278 tSu 1 R2C142[3][A] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/tb_delay_0_s1

Path Statistics:

Clock Skew 0.020
Setup Relationship 20.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.118, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.096, 91.327%; tC2Q: 0.294, 8.673%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.138, 100.000%

Path14

Path Summary:

Slack 16.352
Data Arrival Time 5.508
Data Required Time 21.860
From u1_reset_gen/o_rst1_s1
To u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/divclk_cnt_2_s0
Launch Clk cfg_clk:[R]
Latch Clk cfg_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 cfg_clk
0.000 0.000 tCL RR 2032 PLL_R[3] u_Gowin_PLL/PLL_inst/CLKOUT0
2.118 2.118 tNET RR 1 R18C129[1][A] u1_reset_gen/o_rst1_s1/CLK
2.412 0.294 tC2Q RF 444 R18C129[1][A] u1_reset_gen/o_rst1_s1/Q
5.508 3.096 tNET FF 1 R2C142[2][A] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/divclk_cnt_2_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 cfg_clk
20.000 0.000 tCL RR 2032 PLL_R[3] u_Gowin_PLL/PLL_inst/CLKOUT0
22.138 2.138 tNET RR 1 R2C142[2][A] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/divclk_cnt_2_s0/CLK
21.860 -0.278 tSu 1 R2C142[2][A] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/divclk_cnt_2_s0

Path Statistics:

Clock Skew 0.020
Setup Relationship 20.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.118, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.096, 91.327%; tC2Q: 0.294, 8.673%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.138, 100.000%

Path15

Path Summary:

Slack 16.352
Data Arrival Time 5.508
Data Required Time 21.860
From u1_reset_gen/o_rst1_s1
To u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/divclk_cnt_4_s0
Launch Clk cfg_clk:[R]
Latch Clk cfg_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 cfg_clk
0.000 0.000 tCL RR 2032 PLL_R[3] u_Gowin_PLL/PLL_inst/CLKOUT0
2.118 2.118 tNET RR 1 R18C129[1][A] u1_reset_gen/o_rst1_s1/CLK
2.412 0.294 tC2Q RF 444 R18C129[1][A] u1_reset_gen/o_rst1_s1/Q
5.508 3.096 tNET FF 1 R2C142[1][A] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/divclk_cnt_4_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 cfg_clk
20.000 0.000 tCL RR 2032 PLL_R[3] u_Gowin_PLL/PLL_inst/CLKOUT0
22.138 2.138 tNET RR 1 R2C142[1][A] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/divclk_cnt_4_s0/CLK
21.860 -0.278 tSu 1 R2C142[1][A] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/divclk_cnt_4_s0

Path Statistics:

Clock Skew 0.020
Setup Relationship 20.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.118, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.096, 91.327%; tC2Q: 0.294, 8.673%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.138, 100.000%

Path16

Path Summary:

Slack 16.352
Data Arrival Time 5.508
Data Required Time 21.860
From u1_reset_gen/o_rst1_s1
To u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/divclk_cnt_15_s0
Launch Clk cfg_clk:[R]
Latch Clk cfg_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 cfg_clk
0.000 0.000 tCL RR 2032 PLL_R[3] u_Gowin_PLL/PLL_inst/CLKOUT0
2.118 2.118 tNET RR 1 R18C129[1][A] u1_reset_gen/o_rst1_s1/CLK
2.412 0.294 tC2Q RF 444 R18C129[1][A] u1_reset_gen/o_rst1_s1/Q
5.508 3.096 tNET FF 1 R2C142[1][B] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/divclk_cnt_15_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 cfg_clk
20.000 0.000 tCL RR 2032 PLL_R[3] u_Gowin_PLL/PLL_inst/CLKOUT0
22.138 2.138 tNET RR 1 R2C142[1][B] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/divclk_cnt_15_s0/CLK
21.860 -0.278 tSu 1 R2C142[1][B] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/divclk_cnt_15_s0

Path Statistics:

Clock Skew 0.020
Setup Relationship 20.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.118, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.096, 91.327%; tC2Q: 0.294, 8.673%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.138, 100.000%

Path17

Path Summary:

Slack 16.352
Data Arrival Time 5.508
Data Required Time 21.860
From u1_reset_gen/o_rst1_s1
To u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/tb_delay_2_s0
Launch Clk cfg_clk:[R]
Latch Clk cfg_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 cfg_clk
0.000 0.000 tCL RR 2032 PLL_R[3] u_Gowin_PLL/PLL_inst/CLKOUT0
2.118 2.118 tNET RR 1 R18C129[1][A] u1_reset_gen/o_rst1_s1/CLK
2.412 0.294 tC2Q RF 444 R18C129[1][A] u1_reset_gen/o_rst1_s1/Q
5.508 3.096 tNET FF 1 R2C142[0][B] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/tb_delay_2_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 cfg_clk
20.000 0.000 tCL RR 2032 PLL_R[3] u_Gowin_PLL/PLL_inst/CLKOUT0
22.138 2.138 tNET RR 1 R2C142[0][B] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/tb_delay_2_s0/CLK
21.860 -0.278 tSu 1 R2C142[0][B] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/tb_delay_2_s0

Path Statistics:

Clock Skew 0.020
Setup Relationship 20.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.118, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.096, 91.327%; tC2Q: 0.294, 8.673%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.138, 100.000%

Path18

Path Summary:

Slack 16.352
Data Arrival Time 5.508
Data Required Time 21.860
From u1_reset_gen/o_rst1_s1
To u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/tb_delay_3_s0
Launch Clk cfg_clk:[R]
Latch Clk cfg_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 cfg_clk
0.000 0.000 tCL RR 2032 PLL_R[3] u_Gowin_PLL/PLL_inst/CLKOUT0
2.118 2.118 tNET RR 1 R18C129[1][A] u1_reset_gen/o_rst1_s1/CLK
2.412 0.294 tC2Q RF 444 R18C129[1][A] u1_reset_gen/o_rst1_s1/Q
5.508 3.096 tNET FF 1 R2C142[0][A] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/tb_delay_3_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 cfg_clk
20.000 0.000 tCL RR 2032 PLL_R[3] u_Gowin_PLL/PLL_inst/CLKOUT0
22.138 2.138 tNET RR 1 R2C142[0][A] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/tb_delay_3_s0/CLK
21.860 -0.278 tSu 1 R2C142[0][A] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/tb_delay_3_s0

Path Statistics:

Clock Skew 0.020
Setup Relationship 20.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.118, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.096, 91.327%; tC2Q: 0.294, 8.673%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.138, 100.000%

Path19

Path Summary:

Slack 16.360
Data Arrival Time 5.508
Data Required Time 21.868
From u1_reset_gen/o_rst1_s1
To u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/divclk_cnt_0_s0
Launch Clk cfg_clk:[R]
Latch Clk cfg_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 cfg_clk
0.000 0.000 tCL RR 2032 PLL_R[3] u_Gowin_PLL/PLL_inst/CLKOUT0
2.118 2.118 tNET RR 1 R18C129[1][A] u1_reset_gen/o_rst1_s1/CLK
2.412 0.294 tC2Q RF 444 R18C129[1][A] u1_reset_gen/o_rst1_s1/Q
5.508 3.096 tNET FF 1 R2C143[2][A] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/divclk_cnt_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 cfg_clk
20.000 0.000 tCL RR 2032 PLL_R[3] u_Gowin_PLL/PLL_inst/CLKOUT0
22.146 2.146 tNET RR 1 R2C143[2][A] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/divclk_cnt_0_s0/CLK
21.868 -0.278 tSu 1 R2C143[2][A] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/divclk_cnt_0_s0

Path Statistics:

Clock Skew 0.028
Setup Relationship 20.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.118, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.096, 91.327%; tC2Q: 0.294, 8.673%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.146, 100.000%

Path20

Path Summary:

Slack 16.360
Data Arrival Time 5.508
Data Required Time 21.868
From u1_reset_gen/o_rst1_s1
To u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/fsm_st_curr_0_s0
Launch Clk cfg_clk:[R]
Latch Clk cfg_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 cfg_clk
0.000 0.000 tCL RR 2032 PLL_R[3] u_Gowin_PLL/PLL_inst/CLKOUT0
2.118 2.118 tNET RR 1 R18C129[1][A] u1_reset_gen/o_rst1_s1/CLK
2.412 0.294 tC2Q RF 444 R18C129[1][A] u1_reset_gen/o_rst1_s1/Q
5.508 3.096 tNET FF 1 R2C143[1][B] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/fsm_st_curr_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 cfg_clk
20.000 0.000 tCL RR 2032 PLL_R[3] u_Gowin_PLL/PLL_inst/CLKOUT0
22.146 2.146 tNET RR 1 R2C143[1][B] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/fsm_st_curr_0_s0/CLK
21.868 -0.278 tSu 1 R2C143[1][B] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/fsm_st_curr_0_s0

Path Statistics:

Clock Skew 0.028
Setup Relationship 20.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.118, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.096, 91.327%; tC2Q: 0.294, 8.673%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.146, 100.000%

Path21

Path Summary:

Slack 16.360
Data Arrival Time 5.508
Data Required Time 21.868
From u1_reset_gen/o_rst1_s1
To u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/fsm_st_curr_1_s0
Launch Clk cfg_clk:[R]
Latch Clk cfg_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 cfg_clk
0.000 0.000 tCL RR 2032 PLL_R[3] u_Gowin_PLL/PLL_inst/CLKOUT0
2.118 2.118 tNET RR 1 R18C129[1][A] u1_reset_gen/o_rst1_s1/CLK
2.412 0.294 tC2Q RF 444 R18C129[1][A] u1_reset_gen/o_rst1_s1/Q
5.508 3.096 tNET FF 1 R2C143[1][A] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/fsm_st_curr_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 cfg_clk
20.000 0.000 tCL RR 2032 PLL_R[3] u_Gowin_PLL/PLL_inst/CLKOUT0
22.146 2.146 tNET RR 1 R2C143[1][A] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/fsm_st_curr_1_s0/CLK
21.868 -0.278 tSu 1 R2C143[1][A] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/fsm_st_curr_1_s0

Path Statistics:

Clock Skew 0.028
Setup Relationship 20.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.118, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.096, 91.327%; tC2Q: 0.294, 8.673%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.146, 100.000%

Path22

Path Summary:

Slack 16.429
Data Arrival Time 5.429
Data Required Time 21.858
From u1_reset_gen/o_rst1_s1
To u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/fsm_st_curr_1_s1
Launch Clk cfg_clk:[R]
Latch Clk cfg_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 cfg_clk
0.000 0.000 tCL RR 2032 PLL_R[3] u_Gowin_PLL/PLL_inst/CLKOUT0
2.118 2.118 tNET RR 1 R18C129[1][A] u1_reset_gen/o_rst1_s1/CLK
2.412 0.294 tC2Q RF 444 R18C129[1][A] u1_reset_gen/o_rst1_s1/Q
5.429 3.017 tNET FF 1 R3C142[0][B] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/fsm_st_curr_1_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 cfg_clk
20.000 0.000 tCL RR 2032 PLL_R[3] u_Gowin_PLL/PLL_inst/CLKOUT0
22.136 2.136 tNET RR 1 R3C142[0][B] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/fsm_st_curr_1_s1/CLK
21.858 -0.278 tSu 1 R3C142[0][B] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/fsm_st_curr_1_s1

Path Statistics:

Clock Skew 0.018
Setup Relationship 20.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.118, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.017, 91.121%; tC2Q: 0.294, 8.879%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.136, 100.000%

Path23

Path Summary:

Slack 16.429
Data Arrival Time 5.429
Data Required Time 21.858
From u1_reset_gen/o_rst1_s1
To u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/fsm_st_curr_2_s1
Launch Clk cfg_clk:[R]
Latch Clk cfg_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 cfg_clk
0.000 0.000 tCL RR 2032 PLL_R[3] u_Gowin_PLL/PLL_inst/CLKOUT0
2.118 2.118 tNET RR 1 R18C129[1][A] u1_reset_gen/o_rst1_s1/CLK
2.412 0.294 tC2Q RF 444 R18C129[1][A] u1_reset_gen/o_rst1_s1/Q
5.429 3.017 tNET FF 1 R3C142[0][A] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/fsm_st_curr_2_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 cfg_clk
20.000 0.000 tCL RR 2032 PLL_R[3] u_Gowin_PLL/PLL_inst/CLKOUT0
22.136 2.136 tNET RR 1 R3C142[0][A] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/fsm_st_curr_2_s1/CLK
21.858 -0.278 tSu 1 R3C142[0][A] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/fsm_st_curr_2_s1

Path Statistics:

Clock Skew 0.018
Setup Relationship 20.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.118, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.017, 91.121%; tC2Q: 0.294, 8.879%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.136, 100.000%

Path24

Path Summary:

Slack 16.429
Data Arrival Time 5.429
Data Required Time 21.858
From u1_reset_gen/o_rst1_s1
To u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_0_s0
Launch Clk cfg_clk:[R]
Latch Clk cfg_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 cfg_clk
0.000 0.000 tCL RR 2032 PLL_R[3] u_Gowin_PLL/PLL_inst/CLKOUT0
2.118 2.118 tNET RR 1 R18C129[1][A] u1_reset_gen/o_rst1_s1/CLK
2.412 0.294 tC2Q RF 444 R18C129[1][A] u1_reset_gen/o_rst1_s1/Q
5.429 3.017 tNET FF 1 R3C142[2][B] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 cfg_clk
20.000 0.000 tCL RR 2032 PLL_R[3] u_Gowin_PLL/PLL_inst/CLKOUT0
22.136 2.136 tNET RR 1 R3C142[2][B] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_0_s0/CLK
21.858 -0.278 tSu 1 R3C142[2][B] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_0_s0

Path Statistics:

Clock Skew 0.018
Setup Relationship 20.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.118, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.017, 91.121%; tC2Q: 0.294, 8.879%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.136, 100.000%

Path25

Path Summary:

Slack 16.437
Data Arrival Time 5.429
Data Required Time 21.865
From u1_reset_gen/o_rst1_s1
To u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_5_s0
Launch Clk cfg_clk:[R]
Latch Clk cfg_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 cfg_clk
0.000 0.000 tCL RR 2032 PLL_R[3] u_Gowin_PLL/PLL_inst/CLKOUT0
2.118 2.118 tNET RR 1 R18C129[1][A] u1_reset_gen/o_rst1_s1/CLK
2.412 0.294 tC2Q RF 444 R18C129[1][A] u1_reset_gen/o_rst1_s1/Q
5.429 3.017 tNET FF 1 R3C143[0][A] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_5_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 cfg_clk
20.000 0.000 tCL RR 2032 PLL_R[3] u_Gowin_PLL/PLL_inst/CLKOUT0
22.143 2.144 tNET RR 1 R3C143[0][A] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_5_s0/CLK
21.865 -0.278 tSu 1 R3C143[0][A] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_5_s0

Path Statistics:

Clock Skew 0.026
Setup Relationship 20.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.118, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 3.017, 91.121%; tC2Q: 0.294, 8.879%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.144, 100.000%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 0.496
Data Arrival Time 1.342
Data Required Time 0.846
From u1_reset_gen/o_rst1_s1
To u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_14_s0
Launch Clk cfg_clk:[R]
Latch Clk cfg_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 cfg_clk
0.000 0.000 tCL RR 2032 PLL_R[3] u_Gowin_PLL/PLL_inst/CLKOUT0
0.993 0.993 tNET RR 1 R18C129[1][A] u1_reset_gen/o_rst1_s1/CLK
1.137 0.144 tC2Q RR 444 R18C129[1][A] u1_reset_gen/o_rst1_s1/Q
1.342 0.205 tNET RR 1 R18C132[0][A] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_14_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 cfg_clk
0.000 0.000 tCL RR 2032 PLL_R[3] u_Gowin_PLL/PLL_inst/CLKOUT0
0.997 0.997 tNET RR 1 R18C132[0][A] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_14_s0/CLK
0.846 -0.151 tHld 1 R18C132[0][A] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_14_s0

Path Statistics:

Clock Skew 0.004
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.993, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.205, 58.739%; tC2Q: 0.144, 41.261%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.997, 100.000%

Path2

Path Summary:

Slack 0.496
Data Arrival Time 1.342
Data Required Time 0.846
From u1_reset_gen/o_rst1_s1
To u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_15_s0
Launch Clk cfg_clk:[R]
Latch Clk cfg_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 cfg_clk
0.000 0.000 tCL RR 2032 PLL_R[3] u_Gowin_PLL/PLL_inst/CLKOUT0
0.993 0.993 tNET RR 1 R18C129[1][A] u1_reset_gen/o_rst1_s1/CLK
1.137 0.144 tC2Q RR 444 R18C129[1][A] u1_reset_gen/o_rst1_s1/Q
1.342 0.205 tNET RR 1 R18C132[0][B] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_15_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 cfg_clk
0.000 0.000 tCL RR 2032 PLL_R[3] u_Gowin_PLL/PLL_inst/CLKOUT0
0.997 0.997 tNET RR 1 R18C132[0][B] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_15_s0/CLK
0.846 -0.151 tHld 1 R18C132[0][B] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_15_s0

Path Statistics:

Clock Skew 0.004
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.993, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.205, 58.739%; tC2Q: 0.144, 41.261%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.997, 100.000%

Path3

Path Summary:

Slack 0.496
Data Arrival Time 1.342
Data Required Time 0.846
From u1_reset_gen/o_rst1_s1
To u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_18_s0
Launch Clk cfg_clk:[R]
Latch Clk cfg_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 cfg_clk
0.000 0.000 tCL RR 2032 PLL_R[3] u_Gowin_PLL/PLL_inst/CLKOUT0
0.993 0.993 tNET RR 1 R18C129[1][A] u1_reset_gen/o_rst1_s1/CLK
1.137 0.144 tC2Q RR 444 R18C129[1][A] u1_reset_gen/o_rst1_s1/Q
1.342 0.205 tNET RR 1 R18C132[2][A] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_18_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 cfg_clk
0.000 0.000 tCL RR 2032 PLL_R[3] u_Gowin_PLL/PLL_inst/CLKOUT0
0.997 0.997 tNET RR 1 R18C132[2][A] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_18_s0/CLK
0.846 -0.151 tHld 1 R18C132[2][A] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_18_s0

Path Statistics:

Clock Skew 0.004
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.993, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.205, 58.739%; tC2Q: 0.144, 41.261%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.997, 100.000%

Path4

Path Summary:

Slack 0.496
Data Arrival Time 1.342
Data Required Time 0.846
From u1_reset_gen/o_rst1_s1
To u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_19_s0
Launch Clk cfg_clk:[R]
Latch Clk cfg_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 cfg_clk
0.000 0.000 tCL RR 2032 PLL_R[3] u_Gowin_PLL/PLL_inst/CLKOUT0
0.993 0.993 tNET RR 1 R18C129[1][A] u1_reset_gen/o_rst1_s1/CLK
1.137 0.144 tC2Q RR 444 R18C129[1][A] u1_reset_gen/o_rst1_s1/Q
1.342 0.205 tNET RR 1 R18C132[2][B] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_19_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 cfg_clk
0.000 0.000 tCL RR 2032 PLL_R[3] u_Gowin_PLL/PLL_inst/CLKOUT0
0.997 0.997 tNET RR 1 R18C132[2][B] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_19_s0/CLK
0.846 -0.151 tHld 1 R18C132[2][B] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_19_s0

Path Statistics:

Clock Skew 0.004
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.993, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.205, 58.739%; tC2Q: 0.144, 41.261%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.997, 100.000%

Path5

Path Summary:

Slack 0.504
Data Arrival Time 1.340
Data Required Time 0.835
From u1_reset_gen/o_rst1_s1
To u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_17_s0
Launch Clk cfg_clk:[R]
Latch Clk cfg_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 cfg_clk
0.000 0.000 tCL RR 2032 PLL_R[3] u_Gowin_PLL/PLL_inst/CLKOUT0
0.993 0.993 tNET RR 1 R18C129[1][A] u1_reset_gen/o_rst1_s1/CLK
1.137 0.144 tC2Q RR 444 R18C129[1][A] u1_reset_gen/o_rst1_s1/Q
1.340 0.203 tNET RR 1 R16C130[0][A] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_17_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 cfg_clk
0.000 0.000 tCL RR 2032 PLL_R[3] u_Gowin_PLL/PLL_inst/CLKOUT0
0.986 0.986 tNET RR 1 R16C130[0][A] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_17_s0/CLK
0.835 -0.151 tHld 1 R16C130[0][A] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_17_s0

Path Statistics:

Clock Skew -0.007
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.993, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.203, 58.501%; tC2Q: 0.144, 41.499%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.986, 100.000%

Path6

Path Summary:

Slack 0.600
Data Arrival Time 1.444
Data Required Time 0.843
From u1_reset_gen/o_rst1_s1
To u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_2_s0
Launch Clk cfg_clk:[R]
Latch Clk cfg_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 cfg_clk
0.000 0.000 tCL RR 2032 PLL_R[3] u_Gowin_PLL/PLL_inst/CLKOUT0
0.993 0.993 tNET RR 1 R18C129[1][A] u1_reset_gen/o_rst1_s1/CLK
1.137 0.144 tC2Q RR 444 R18C129[1][A] u1_reset_gen/o_rst1_s1/Q
1.444 0.307 tNET RR 1 R16C132[3][A] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_2_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 cfg_clk
0.000 0.000 tCL RR 2032 PLL_R[3] u_Gowin_PLL/PLL_inst/CLKOUT0
0.994 0.994 tNET RR 1 R16C132[3][A] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_2_s0/CLK
0.843 -0.151 tHld 1 R16C132[3][A] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_2_s0

Path Statistics:

Clock Skew 0.002
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.993, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.307, 68.071%; tC2Q: 0.144, 31.929%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.994, 100.000%

Path7

Path Summary:

Slack 0.600
Data Arrival Time 1.444
Data Required Time 0.843
From u1_reset_gen/o_rst1_s1
To u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_20_s0
Launch Clk cfg_clk:[R]
Latch Clk cfg_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 cfg_clk
0.000 0.000 tCL RR 2032 PLL_R[3] u_Gowin_PLL/PLL_inst/CLKOUT0
0.993 0.993 tNET RR 1 R18C129[1][A] u1_reset_gen/o_rst1_s1/CLK
1.137 0.144 tC2Q RR 444 R18C129[1][A] u1_reset_gen/o_rst1_s1/Q
1.444 0.307 tNET RR 1 R16C132[0][A] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_20_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 cfg_clk
0.000 0.000 tCL RR 2032 PLL_R[3] u_Gowin_PLL/PLL_inst/CLKOUT0
0.994 0.994 tNET RR 1 R16C132[0][A] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_20_s0/CLK
0.843 -0.151 tHld 1 R16C132[0][A] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_20_s0

Path Statistics:

Clock Skew 0.002
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.993, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.307, 68.071%; tC2Q: 0.144, 31.929%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.994, 100.000%

Path8

Path Summary:

Slack 0.600
Data Arrival Time 1.444
Data Required Time 0.843
From u1_reset_gen/o_rst1_s1
To u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_21_s0
Launch Clk cfg_clk:[R]
Latch Clk cfg_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 cfg_clk
0.000 0.000 tCL RR 2032 PLL_R[3] u_Gowin_PLL/PLL_inst/CLKOUT0
0.993 0.993 tNET RR 1 R18C129[1][A] u1_reset_gen/o_rst1_s1/CLK
1.137 0.144 tC2Q RR 444 R18C129[1][A] u1_reset_gen/o_rst1_s1/Q
1.444 0.307 tNET RR 1 R16C132[0][B] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_21_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 cfg_clk
0.000 0.000 tCL RR 2032 PLL_R[3] u_Gowin_PLL/PLL_inst/CLKOUT0
0.994 0.994 tNET RR 1 R16C132[0][B] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_21_s0/CLK
0.843 -0.151 tHld 1 R16C132[0][B] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_21_s0

Path Statistics:

Clock Skew 0.002
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.993, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.307, 68.071%; tC2Q: 0.144, 31.929%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.994, 100.000%

Path9

Path Summary:

Slack 0.600
Data Arrival Time 1.444
Data Required Time 0.843
From u1_reset_gen/o_rst1_s1
To u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_22_s0
Launch Clk cfg_clk:[R]
Latch Clk cfg_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 cfg_clk
0.000 0.000 tCL RR 2032 PLL_R[3] u_Gowin_PLL/PLL_inst/CLKOUT0
0.993 0.993 tNET RR 1 R18C129[1][A] u1_reset_gen/o_rst1_s1/CLK
1.137 0.144 tC2Q RR 444 R18C129[1][A] u1_reset_gen/o_rst1_s1/Q
1.444 0.307 tNET RR 1 R16C132[1][A] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_22_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 cfg_clk
0.000 0.000 tCL RR 2032 PLL_R[3] u_Gowin_PLL/PLL_inst/CLKOUT0
0.994 0.994 tNET RR 1 R16C132[1][A] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_22_s0/CLK
0.843 -0.151 tHld 1 R16C132[1][A] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_22_s0

Path Statistics:

Clock Skew 0.002
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.993, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.307, 68.071%; tC2Q: 0.144, 31.929%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.994, 100.000%

Path10

Path Summary:

Slack 0.600
Data Arrival Time 1.444
Data Required Time 0.843
From u1_reset_gen/o_rst1_s1
To u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_23_s0
Launch Clk cfg_clk:[R]
Latch Clk cfg_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 cfg_clk
0.000 0.000 tCL RR 2032 PLL_R[3] u_Gowin_PLL/PLL_inst/CLKOUT0
0.993 0.993 tNET RR 1 R18C129[1][A] u1_reset_gen/o_rst1_s1/CLK
1.137 0.144 tC2Q RR 444 R18C129[1][A] u1_reset_gen/o_rst1_s1/Q
1.444 0.307 tNET RR 1 R16C132[1][B] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_23_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 cfg_clk
0.000 0.000 tCL RR 2032 PLL_R[3] u_Gowin_PLL/PLL_inst/CLKOUT0
0.994 0.994 tNET RR 1 R16C132[1][B] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_23_s0/CLK
0.843 -0.151 tHld 1 R16C132[1][B] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_23_s0

Path Statistics:

Clock Skew 0.002
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.993, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.307, 68.071%; tC2Q: 0.144, 31.929%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.994, 100.000%

Path11

Path Summary:

Slack 0.600
Data Arrival Time 1.444
Data Required Time 0.843
From u1_reset_gen/o_rst1_s1
To u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_24_s0
Launch Clk cfg_clk:[R]
Latch Clk cfg_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 cfg_clk
0.000 0.000 tCL RR 2032 PLL_R[3] u_Gowin_PLL/PLL_inst/CLKOUT0
0.993 0.993 tNET RR 1 R18C129[1][A] u1_reset_gen/o_rst1_s1/CLK
1.137 0.144 tC2Q RR 444 R18C129[1][A] u1_reset_gen/o_rst1_s1/Q
1.444 0.307 tNET RR 1 R16C132[2][A] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_24_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 cfg_clk
0.000 0.000 tCL RR 2032 PLL_R[3] u_Gowin_PLL/PLL_inst/CLKOUT0
0.994 0.994 tNET RR 1 R16C132[2][A] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_24_s0/CLK
0.843 -0.151 tHld 1 R16C132[2][A] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_24_s0

Path Statistics:

Clock Skew 0.002
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.993, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.307, 68.071%; tC2Q: 0.144, 31.929%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.994, 100.000%

Path12

Path Summary:

Slack 0.600
Data Arrival Time 1.444
Data Required Time 0.843
From u1_reset_gen/o_rst1_s1
To u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_25_s0
Launch Clk cfg_clk:[R]
Latch Clk cfg_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 cfg_clk
0.000 0.000 tCL RR 2032 PLL_R[3] u_Gowin_PLL/PLL_inst/CLKOUT0
0.993 0.993 tNET RR 1 R18C129[1][A] u1_reset_gen/o_rst1_s1/CLK
1.137 0.144 tC2Q RR 444 R18C129[1][A] u1_reset_gen/o_rst1_s1/Q
1.444 0.307 tNET RR 1 R16C132[2][B] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_25_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 cfg_clk
0.000 0.000 tCL RR 2032 PLL_R[3] u_Gowin_PLL/PLL_inst/CLKOUT0
0.994 0.994 tNET RR 1 R16C132[2][B] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_25_s0/CLK
0.843 -0.151 tHld 1 R16C132[2][B] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_25_s0

Path Statistics:

Clock Skew 0.002
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.993, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.307, 68.071%; tC2Q: 0.144, 31.929%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.994, 100.000%

Path13

Path Summary:

Slack 0.604
Data Arrival Time 1.446
Data Required Time 0.842
From u1_reset_gen/o_rst1_s1
To u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/wp_rd_g2b_ptr_0_s0
Launch Clk cfg_clk:[R]
Latch Clk cfg_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 cfg_clk
0.000 0.000 tCL RR 2032 PLL_R[3] u_Gowin_PLL/PLL_inst/CLKOUT0
0.993 0.993 tNET RR 1 R18C129[1][A] u1_reset_gen/o_rst1_s1/CLK
1.137 0.144 tC2Q RR 444 R18C129[1][A] u1_reset_gen/o_rst1_s1/Q
1.446 0.309 tNET RR 1 R18C133[1][A] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/wp_rd_g2b_ptr_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 cfg_clk
0.000 0.000 tCL RR 2032 PLL_R[3] u_Gowin_PLL/PLL_inst/CLKOUT0
0.993 0.993 tNET RR 1 R18C133[1][A] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/wp_rd_g2b_ptr_0_s0/CLK
0.842 -0.151 tHld 1 R18C133[1][A] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/wp_rd_g2b_ptr_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.993, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.309, 68.212%; tC2Q: 0.144, 31.788%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.993, 100.000%

Path14

Path Summary:

Slack 0.604
Data Arrival Time 1.446
Data Required Time 0.842
From u1_reset_gen/o_rst1_s1
To u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/wp_rd_g2b_ptr_1_s0
Launch Clk cfg_clk:[R]
Latch Clk cfg_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 cfg_clk
0.000 0.000 tCL RR 2032 PLL_R[3] u_Gowin_PLL/PLL_inst/CLKOUT0
0.993 0.993 tNET RR 1 R18C129[1][A] u1_reset_gen/o_rst1_s1/CLK
1.137 0.144 tC2Q RR 444 R18C129[1][A] u1_reset_gen/o_rst1_s1/Q
1.446 0.309 tNET RR 1 R18C133[0][B] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/wp_rd_g2b_ptr_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 cfg_clk
0.000 0.000 tCL RR 2032 PLL_R[3] u_Gowin_PLL/PLL_inst/CLKOUT0
0.993 0.993 tNET RR 1 R18C133[0][B] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/wp_rd_g2b_ptr_1_s0/CLK
0.842 -0.151 tHld 1 R18C133[0][B] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/wp_rd_g2b_ptr_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.993, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.309, 68.212%; tC2Q: 0.144, 31.788%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.993, 100.000%

Path15

Path Summary:

Slack 0.604
Data Arrival Time 1.446
Data Required Time 0.842
From u1_reset_gen/o_rst1_s1
To u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/wp_rd_g2b_ptr_2_s0
Launch Clk cfg_clk:[R]
Latch Clk cfg_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 cfg_clk
0.000 0.000 tCL RR 2032 PLL_R[3] u_Gowin_PLL/PLL_inst/CLKOUT0
0.993 0.993 tNET RR 1 R18C129[1][A] u1_reset_gen/o_rst1_s1/CLK
1.137 0.144 tC2Q RR 444 R18C129[1][A] u1_reset_gen/o_rst1_s1/Q
1.446 0.309 tNET RR 1 R18C133[0][A] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/wp_rd_g2b_ptr_2_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 cfg_clk
0.000 0.000 tCL RR 2032 PLL_R[3] u_Gowin_PLL/PLL_inst/CLKOUT0
0.993 0.993 tNET RR 1 R18C133[0][A] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/wp_rd_g2b_ptr_2_s0/CLK
0.842 -0.151 tHld 1 R18C133[0][A] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/wp_rd_g2b_ptr_2_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.993, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.309, 68.212%; tC2Q: 0.144, 31.788%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.993, 100.000%

Path16

Path Summary:

Slack 0.604
Data Arrival Time 1.446
Data Required Time 0.842
From u1_reset_gen/o_rst1_s1
To u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/wp_rd_gray_ptr_0_s0
Launch Clk cfg_clk:[R]
Latch Clk cfg_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 cfg_clk
0.000 0.000 tCL RR 2032 PLL_R[3] u_Gowin_PLL/PLL_inst/CLKOUT0
0.993 0.993 tNET RR 1 R18C129[1][A] u1_reset_gen/o_rst1_s1/CLK
1.137 0.144 tC2Q RR 444 R18C129[1][A] u1_reset_gen/o_rst1_s1/Q
1.446 0.309 tNET RR 1 R18C133[2][A] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/wp_rd_gray_ptr_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 cfg_clk
0.000 0.000 tCL RR 2032 PLL_R[3] u_Gowin_PLL/PLL_inst/CLKOUT0
0.993 0.993 tNET RR 1 R18C133[2][A] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/wp_rd_gray_ptr_0_s0/CLK
0.842 -0.151 tHld 1 R18C133[2][A] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/wp_rd_gray_ptr_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.993, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.309, 68.212%; tC2Q: 0.144, 31.788%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.993, 100.000%

Path17

Path Summary:

Slack 0.604
Data Arrival Time 1.446
Data Required Time 0.842
From u1_reset_gen/o_rst1_s1
To u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/wp_rd_gray_ptr_2_s0
Launch Clk cfg_clk:[R]
Latch Clk cfg_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 cfg_clk
0.000 0.000 tCL RR 2032 PLL_R[3] u_Gowin_PLL/PLL_inst/CLKOUT0
0.993 0.993 tNET RR 1 R18C129[1][A] u1_reset_gen/o_rst1_s1/CLK
1.137 0.144 tC2Q RR 444 R18C129[1][A] u1_reset_gen/o_rst1_s1/Q
1.446 0.309 tNET RR 1 R18C133[3][A] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/wp_rd_gray_ptr_2_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 cfg_clk
0.000 0.000 tCL RR 2032 PLL_R[3] u_Gowin_PLL/PLL_inst/CLKOUT0
0.993 0.993 tNET RR 1 R18C133[3][A] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/wp_rd_gray_ptr_2_s0/CLK
0.842 -0.151 tHld 1 R18C133[3][A] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/wp_rd_gray_ptr_2_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.993, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.309, 68.212%; tC2Q: 0.144, 31.788%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.993, 100.000%

Path18

Path Summary:

Slack 0.604
Data Arrival Time 1.446
Data Required Time 0.842
From u1_reset_gen/o_rst1_s1
To u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/wp_rd_gray_ptr1_0_s0
Launch Clk cfg_clk:[R]
Latch Clk cfg_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 cfg_clk
0.000 0.000 tCL RR 2032 PLL_R[3] u_Gowin_PLL/PLL_inst/CLKOUT0
0.993 0.993 tNET RR 1 R18C129[1][A] u1_reset_gen/o_rst1_s1/CLK
1.137 0.144 tC2Q RR 444 R18C129[1][A] u1_reset_gen/o_rst1_s1/Q
1.446 0.309 tNET RR 1 R18C133[3][B] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/wp_rd_gray_ptr1_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 cfg_clk
0.000 0.000 tCL RR 2032 PLL_R[3] u_Gowin_PLL/PLL_inst/CLKOUT0
0.993 0.993 tNET RR 1 R18C133[3][B] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/wp_rd_gray_ptr1_0_s0/CLK
0.842 -0.151 tHld 1 R18C133[3][B] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/wp_rd_gray_ptr1_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.993, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.309, 68.212%; tC2Q: 0.144, 31.788%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.993, 100.000%

Path19

Path Summary:

Slack 0.604
Data Arrival Time 1.446
Data Required Time 0.842
From u1_reset_gen/o_rst1_s1
To u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/wp_rd_gray_ptr1_2_s0
Launch Clk cfg_clk:[R]
Latch Clk cfg_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 cfg_clk
0.000 0.000 tCL RR 2032 PLL_R[3] u_Gowin_PLL/PLL_inst/CLKOUT0
0.993 0.993 tNET RR 1 R18C129[1][A] u1_reset_gen/o_rst1_s1/CLK
1.137 0.144 tC2Q RR 444 R18C129[1][A] u1_reset_gen/o_rst1_s1/Q
1.446 0.309 tNET RR 1 R18C133[2][B] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/wp_rd_gray_ptr1_2_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 cfg_clk
0.000 0.000 tCL RR 2032 PLL_R[3] u_Gowin_PLL/PLL_inst/CLKOUT0
0.993 0.993 tNET RR 1 R18C133[2][B] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/wp_rd_gray_ptr1_2_s0/CLK
0.842 -0.151 tHld 1 R18C133[2][B] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/wp_rd_gray_ptr1_2_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.993, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.309, 68.212%; tC2Q: 0.144, 31.788%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.993, 100.000%

Path20

Path Summary:

Slack 0.604
Data Arrival Time 1.446
Data Required Time 0.842
From u1_reset_gen/o_rst1_s1
To u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/rd_gray_ptr_0_s0
Launch Clk cfg_clk:[R]
Latch Clk cfg_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 cfg_clk
0.000 0.000 tCL RR 2032 PLL_R[3] u_Gowin_PLL/PLL_inst/CLKOUT0
0.993 0.993 tNET RR 1 R18C129[1][A] u1_reset_gen/o_rst1_s1/CLK
1.137 0.144 tC2Q RR 444 R18C129[1][A] u1_reset_gen/o_rst1_s1/Q
1.446 0.309 tNET RR 1 R18C133[1][B] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/rd_gray_ptr_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 cfg_clk
0.000 0.000 tCL RR 2032 PLL_R[3] u_Gowin_PLL/PLL_inst/CLKOUT0
0.993 0.993 tNET RR 1 R18C133[1][B] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/rd_gray_ptr_0_s0/CLK
0.842 -0.151 tHld 1 R18C133[1][B] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/rd_gray_ptr_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.993, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.309, 68.212%; tC2Q: 0.144, 31.788%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.993, 100.000%

Path21

Path Summary:

Slack 0.604
Data Arrival Time 1.444
Data Required Time 0.839
From u1_reset_gen/o_rst1_s1
To u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_16_s0
Launch Clk cfg_clk:[R]
Latch Clk cfg_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 cfg_clk
0.000 0.000 tCL RR 2032 PLL_R[3] u_Gowin_PLL/PLL_inst/CLKOUT0
0.993 0.993 tNET RR 1 R18C129[1][A] u1_reset_gen/o_rst1_s1/CLK
1.137 0.144 tC2Q RR 444 R18C129[1][A] u1_reset_gen/o_rst1_s1/Q
1.444 0.307 tNET RR 1 R16C131[1][A] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_16_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 cfg_clk
0.000 0.000 tCL RR 2032 PLL_R[3] u_Gowin_PLL/PLL_inst/CLKOUT0
0.990 0.990 tNET RR 1 R16C131[1][A] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_16_s0/CLK
0.839 -0.151 tHld 1 R16C131[1][A] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_16_s0

Path Statistics:

Clock Skew -0.003
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.993, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.307, 68.071%; tC2Q: 0.144, 31.929%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.990, 100.000%

Path22

Path Summary:

Slack 0.604
Data Arrival Time 1.444
Data Required Time 0.839
From u1_reset_gen/o_rst1_s1
To u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wen_s0
Launch Clk cfg_clk:[R]
Latch Clk cfg_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 cfg_clk
0.000 0.000 tCL RR 2032 PLL_R[3] u_Gowin_PLL/PLL_inst/CLKOUT0
0.993 0.993 tNET RR 1 R18C129[1][A] u1_reset_gen/o_rst1_s1/CLK
1.137 0.144 tC2Q RR 444 R18C129[1][A] u1_reset_gen/o_rst1_s1/Q
1.444 0.307 tNET RR 1 R16C131[1][B] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wen_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 cfg_clk
0.000 0.000 tCL RR 2032 PLL_R[3] u_Gowin_PLL/PLL_inst/CLKOUT0
0.990 0.990 tNET RR 1 R16C131[1][B] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wen_s0/CLK
0.839 -0.151 tHld 1 R16C131[1][B] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wen_s0

Path Statistics:

Clock Skew -0.003
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.993, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.307, 68.071%; tC2Q: 0.144, 31.929%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.990, 100.000%

Path23

Path Summary:

Slack 0.606
Data Arrival Time 1.436
Data Required Time 0.830
From u1_reset_gen/o_rst1_s1
To u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_0_s0
Launch Clk cfg_clk:[R]
Latch Clk cfg_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 cfg_clk
0.000 0.000 tCL RR 2032 PLL_R[3] u_Gowin_PLL/PLL_inst/CLKOUT0
0.993 0.993 tNET RR 1 R18C129[1][A] u1_reset_gen/o_rst1_s1/CLK
1.137 0.144 tC2Q RR 444 R18C129[1][A] u1_reset_gen/o_rst1_s1/Q
1.436 0.299 tNET RR 1 R14C130[1][A] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 cfg_clk
0.000 0.000 tCL RR 2032 PLL_R[3] u_Gowin_PLL/PLL_inst/CLKOUT0
0.981 0.981 tNET RR 1 R14C130[1][A] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_0_s0/CLK
0.830 -0.151 tHld 1 R14C130[1][A] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_0_s0

Path Statistics:

Clock Skew -0.012
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.993, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.299, 67.494%; tC2Q: 0.144, 32.506%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.981, 100.000%

Path24

Path Summary:

Slack 0.606
Data Arrival Time 1.436
Data Required Time 0.830
From u1_reset_gen/o_rst1_s1
To u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_1_s0
Launch Clk cfg_clk:[R]
Latch Clk cfg_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 cfg_clk
0.000 0.000 tCL RR 2032 PLL_R[3] u_Gowin_PLL/PLL_inst/CLKOUT0
0.993 0.993 tNET RR 1 R18C129[1][A] u1_reset_gen/o_rst1_s1/CLK
1.137 0.144 tC2Q RR 444 R18C129[1][A] u1_reset_gen/o_rst1_s1/Q
1.436 0.299 tNET RR 1 R14C130[1][B] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 cfg_clk
0.000 0.000 tCL RR 2032 PLL_R[3] u_Gowin_PLL/PLL_inst/CLKOUT0
0.981 0.981 tNET RR 1 R14C130[1][B] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_1_s0/CLK
0.830 -0.151 tHld 1 R14C130[1][B] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_1_s0

Path Statistics:

Clock Skew -0.012
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.993, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.299, 67.494%; tC2Q: 0.144, 32.506%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.981, 100.000%

Path25

Path Summary:

Slack 0.708
Data Arrival Time 1.546
Data Required Time 0.838
From u1_reset_gen/o_rst1_s1
To u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_8_s0
Launch Clk cfg_clk:[R]
Latch Clk cfg_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 cfg_clk
0.000 0.000 tCL RR 2032 PLL_R[3] u_Gowin_PLL/PLL_inst/CLKOUT0
0.993 0.993 tNET RR 1 R18C129[1][A] u1_reset_gen/o_rst1_s1/CLK
1.137 0.144 tC2Q RR 444 R18C129[1][A] u1_reset_gen/o_rst1_s1/Q
1.546 0.409 tNET RR 1 R15C131[0][A] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_8_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 cfg_clk
0.000 0.000 tCL RR 2032 PLL_R[3] u_Gowin_PLL/PLL_inst/CLKOUT0
0.989 0.989 tNET RR 1 R15C131[0][A] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_8_s0/CLK
0.838 -0.151 tHld 1 R15C131[0][A] u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_8_s0

Path Statistics:

Clock Skew -0.004
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.993, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.409, 73.960%; tC2Q: 0.144, 26.040%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.989, 100.000%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack: 3.204
Actual Width: 4.066
Required Width: 0.862
Type: High Pulse Width
Clock: u_SerDes_Top/q1_lane1_fabric_rx_clk
Objects: u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
2.118 2.118 tNET RR u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/CLKA

Early clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
5.000 0.000 tCL FF u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
6.185 1.185 tNET FF u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/CLKA

MPW2

MPW Summary:

Slack: 3.208
Actual Width: 4.070
Required Width: 0.862
Type: High Pulse Width
Clock: u_SerDes_Top/q1_lane1_fabric_rx_clk
Objects: u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
2.111 2.111 tNET RR u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s/CLKA

Early clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
5.000 0.000 tCL FF u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
6.181 1.181 tNET FF u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s/CLKA

MPW3

MPW Summary:

Slack: 3.244
Actual Width: 4.106
Required Width: 0.862
Type: Low Pulse Width
Clock: u_SerDes_Top/q1_lane1_fabric_rx_clk
Objects: u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
5.000 0.000 tCL FF u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
6.885 1.885 tNET FF u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/CLKA

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
10.000 0.000 tCL RR u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
10.991 0.991 tNET RR u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/CLKA

MPW4

MPW Summary:

Slack: 3.247
Actual Width: 4.109
Required Width: 0.862
Type: Low Pulse Width
Clock: u_SerDes_Top/q1_lane1_fabric_rx_clk
Objects: u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
5.000 0.000 tCL FF u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
6.878 1.878 tNET FF u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s/CLKA

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
10.000 0.000 tCL RR u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
10.987 0.987 tNET RR u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s/CLKA

MPW5

MPW Summary:

Slack: 3.822
Actual Width: 4.022
Required Width: 0.200
Type: High Pulse Width
Clock: u_SerDes_Top/q1_lane1_fabric_rx_clk
Objects: u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/raw_data_c_srl[0]_4_s0

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
2.184 2.184 tNET RR u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/raw_data_c_srl[0]_4_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
5.000 0.000 tCL FF u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
6.206 1.206 tNET FF u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/raw_data_c_srl[0]_4_s0/CLK

MPW6

MPW Summary:

Slack: 3.822
Actual Width: 4.022
Required Width: 0.200
Type: High Pulse Width
Clock: u_SerDes_Top/q1_lane1_fabric_rx_clk
Objects: u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/raw_data_c_srl[0]_3_s0

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
2.184 2.184 tNET RR u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/raw_data_c_srl[0]_3_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
5.000 0.000 tCL FF u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
6.206 1.206 tNET FF u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/raw_data_c_srl[0]_3_s0/CLK

MPW7

MPW Summary:

Slack: 3.822
Actual Width: 4.022
Required Width: 0.200
Type: High Pulse Width
Clock: u_SerDes_Top/q1_lane1_fabric_rx_clk
Objects: u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/raw_data_c_srl[0]_2_s0

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
2.184 2.184 tNET RR u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/raw_data_c_srl[0]_2_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
5.000 0.000 tCL FF u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
6.206 1.206 tNET FF u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/raw_data_c_srl[0]_2_s0/CLK

MPW8

MPW Summary:

Slack: 3.822
Actual Width: 4.022
Required Width: 0.200
Type: High Pulse Width
Clock: u_SerDes_Top/q1_lane1_fabric_rx_clk
Objects: u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/raw_data_r_3_s0

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
2.182 2.182 tNET RR u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/raw_data_r_3_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
5.000 0.000 tCL FF u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
6.204 1.204 tNET FF u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/raw_data_r_3_s0/CLK

MPW9

MPW Summary:

Slack: 3.822
Actual Width: 4.022
Required Width: 0.200
Type: High Pulse Width
Clock: u_SerDes_Top/q1_lane1_fabric_rx_clk
Objects: u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/raw_data_r_2_s0

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
2.182 2.182 tNET RR u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/raw_data_r_2_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
5.000 0.000 tCL FF u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
6.204 1.204 tNET FF u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/raw_data_r_2_s0/CLK

MPW10

MPW Summary:

Slack: 3.822
Actual Width: 4.022
Required Width: 0.200
Type: High Pulse Width
Clock: u_SerDes_Top/q1_lane1_fabric_rx_clk
Objects: u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/raw_data_r_1_s0

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000 0.000 tCL RR u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
2.184 2.184 tNET RR u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/raw_data_r_1_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 u_SerDes_Top/q1_lane1_fabric_rx_clk
5.000 0.000 tCL FF u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
6.206 1.206 tNET FF u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/raw_data_r_1_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT NET NAME WORST SLACK MAX DELAY
4394 sys_clk 6.662 2.391
2141 q1_lane1_fabric_rx_clk 4.106 2.186
2032 cfg_clk 4.781 2.153
444 cfg_rst 4.781 4.761
196 rd_ptr[2] 15.526 2.126
194 p_0_in__0 6.974 3.842
194 p_0_in__0 6.662 3.889
192 rd_ptr[2] 14.981 2.367
186 tx_reset_comb 14.974 3.285
163 cbcc_fifo_reset_wr_clk_Z 4.586 4.542

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC ROUTE CONGESTIONS
R14C117 77.78%
R31C100 76.39%
R13C97 72.22%
R14C119 72.22%
R14C114 70.83%
R14C118 70.83%
R15C117 69.44%
R13C116 69.44%
R34C114 68.06%
R8C121 68.06%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type State Detail Command
TC_CLOCK Actived create_clock -name osc_clk_i -period 20 -waveform {0 10} [get_ports {osc_clk_i}]
TC_CLOCK Actived create_clock -name cfg_clk -period 20 -waveform {0 10} [get_nets {cfg_clk}]
TC_CLOCK Actived create_clock -name sys_clk -period 20.48 -waveform {0 10.24} [get_nets {sys_clk}]
TC_FALSE_PATH Actived set_false_path -from [get_clocks {cfg_clk}] -to [get_clocks {sys_clk}]
TC_FALSE_PATH Actived set_false_path -from [get_clocks {sys_clk}] -to [get_clocks {cfg_clk}]