Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | E:\gowin_prj\RoraLink_64b66b\Gowin RoraLink 64B66B IP RefDesign\project\src\apb2local.v E:\gowin_prj\RoraLink_64b66b\Gowin RoraLink 64B66B IP RefDesign\project\src\axi_register_slice.v E:\gowin_prj\RoraLink_64b66b\Gowin RoraLink 64B66B IP RefDesign\project\src\axi_to_ll_reg.v E:\gowin_prj\RoraLink_64b66b\Gowin RoraLink 64B66B IP RefDesign\project\src\frame_check.v E:\gowin_prj\RoraLink_64b66b\Gowin RoraLink 64B66B IP RefDesign\project\src\frame_gen.v E:\gowin_prj\RoraLink_64b66b\Gowin RoraLink 64B66B IP RefDesign\project\src\gowin_pll\gowin_pll.v E:\gowin_prj\RoraLink_64b66b\Gowin RoraLink 64B66B IP RefDesign\project\src\ll_to_axi_reg.v E:\gowin_prj\RoraLink_64b66b\Gowin RoraLink 64B66B IP RefDesign\project\src\local2reg.v E:\gowin_prj\RoraLink_64b66b\Gowin RoraLink 64B66B IP RefDesign\project\src\reset_gen.v E:\gowin_prj\RoraLink_64b66b\Gowin RoraLink 64B66B IP RefDesign\project\src\serdes\roralink_64b66b\roralink_64b66b.v E:\gowin_prj\RoraLink_64b66b\Gowin RoraLink 64B66B IP RefDesign\project\src\serdes\serdes.v E:\gowin_prj\RoraLink_64b66b\Gowin RoraLink 64B66B IP RefDesign\project\src\top.v E:\gowin_prj\RoraLink_64b66b\Gowin RoraLink 64B66B IP RefDesign\project\src\uart_to_bus\uart_to_bus.v |
GowinSynthesis Constraints File | E:\gowin_prj\RoraLink_64b66b\Gowin RoraLink 64B66B IP RefDesign\project\src\top.gsc |
Tool Version | V1.9.9.01 (64-bit) |
Part Number | GW5AST-LV138FPG676AC2/I1 |
Device | GW5AST-138 |
Device Version | B |
Created Time | Fri Jan 12 16:16:50 2024 |
Legal Announcement | Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | top |
Synthesis Process | Running parser: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 2125.766MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.359s, Elapsed time = 0h 0m 0.365s, Peak memory usage = 2125.766MB Optimizing Phase 1: CPU time = 0h 0m 0.25s, Elapsed time = 0h 0m 0.23s, Peak memory usage = 2125.766MB Optimizing Phase 2: CPU time = 0h 0m 0.406s, Elapsed time = 0h 0m 0.373s, Peak memory usage = 2125.766MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.187s, Elapsed time = 0h 0m 0.193s, Peak memory usage = 2125.766MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 2125.766MB Inferring Phase 2: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.058s, Peak memory usage = 2125.766MB Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.014s, Peak memory usage = 2125.766MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.421s, Elapsed time = 0h 0m 0.424s, Peak memory usage = 2125.766MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.097s, Peak memory usage = 2125.766MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.05s, Peak memory usage = 2125.766MB Tech-Mapping Phase 3: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 2125.766MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.359s, Elapsed time = 0h 0m 0.353s, Peak memory usage = 2125.766MB Generate output files: CPU time = 0h 0m 0.453s, Elapsed time = 0h 0m 0.443s, Peak memory usage = 2125.766MB |
Total Time and Memory Usage | CPU time = 0h 0m 6s, Elapsed time = 0h 0m 6s, Peak memory usage = 2125.766MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 18 |
I/O Buf | 17 |
    IBUF | 3 |
    OBUF | 11 |
    TBUF | 3 |
Register | 8563 |
    DFFSE | 432 |
    DFFRE | 6373 |
    DFFPE | 18 |
    DFFCE | 1740 |
LUT | 7176 |
    LUT1 | 64 |
    LUT2 | 625 |
    LUT3 | 2929 |
    LUT4 | 2938 |
    LUT5 | 172 |
    LUT6 | 448 |
ALU | 558 |
    ALU | 558 |
INV | 79 |
    INV | 79 |
BSRAM | 2 |
    SDPX9B | 2 |
CLOCK | 1 |
    PLL | 1 |
GTR12_QUAD | 1 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 9329(8771 LUT, 558 ALU) / 138240 | 7% |
Register | 8563 / 139140 | 7% |
  --Register as Latch | 0 / 139140 | 0% |
  --Register as FF | 8563 / 139140 | 7% |
BSRAM | 2 / 340 | <1% |
Timing
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|
osc_clk_i | Base | 20.000 | 50.0 | 0.000 | 10.000 | osc_clk_i_ibuf/I | ||
u_Gowin_PLL/PLL_inst/CLKOUT0.default_gen_clk | Generated | 20.000 | 50.0 | 0.000 | 10.000 | osc_clk_i_ibuf/I | osc_clk_i | u_Gowin_PLL/PLL_inst/CLKOUT0 |
Max Frequency Summary:
No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | u_Gowin_PLL/PLL_inst/CLKOUT0.default_gen_clk | 50.0(MHz) | 164.0(MHz) | 10 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | 13.901 |
Data Arrival Time | 6.926 |
Data Required Time | 20.827 |
From | u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_0_s0 |
To | u_local2reg/local_rdat_o_3_s0 |
Launch Clk | u_Gowin_PLL/PLL_inst/CLKOUT0.default_gen_clk[R] |
Latch Clk | u_Gowin_PLL/PLL_inst/CLKOUT0.default_gen_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | u_Gowin_PLL/PLL_inst/CLKOUT0.default_gen_clk | |||
0.713 | 0.713 | tCL | RR | 2032 | u_Gowin_PLL/PLL_inst/CLKOUT0 |
0.878 | 0.165 | tNET | RR | 1 | u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_0_s0/CLK |
1.184 | 0.306 | tC2Q | RR | 3 | u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_0_s0/Q |
1.349 | 0.165 | tNET | RR | 1 | u_uart_bus_top/uart_bus_core/apb0_sel_o_d_s2/I0 |
1.812 | 0.463 | tINS | RR | 1 | u_uart_bus_top/uart_bus_core/apb0_sel_o_d_s2/F |
1.977 | 0.165 | tNET | RR | 1 | u_uart_bus_top/uart_bus_core/apb0_sel_o_d_s0/I0 |
2.440 | 0.463 | tINS | RR | 76 | u_uart_bus_top/uart_bus_core/apb0_sel_o_d_s0/F |
2.605 | 0.165 | tNET | RR | 1 | u_uart_bus_top/uart_bus_core/apb0_addr_o_d_7_s0/I1 |
3.059 | 0.454 | tINS | RR | 1 | u_uart_bus_top/uart_bus_core/apb0_addr_o_d_7_s0/F |
3.224 | 0.165 | tNET | RR | 1 | u_local2reg/n2418_s5/I0 |
3.687 | 0.463 | tINS | RR | 2 | u_local2reg/n2418_s5/F |
3.852 | 0.165 | tNET | RR | 1 | u_local2reg/n1788_s47/I2 |
4.258 | 0.406 | tINS | RR | 23 | u_local2reg/n1788_s47/F |
4.423 | 0.165 | tNET | RR | 1 | u_local2reg/n1765_s65/I1 |
4.877 | 0.454 | tINS | RR | 32 | u_local2reg/n1765_s65/F |
5.042 | 0.165 | tNET | RR | 1 | u_local2reg/n1793_s40/I0 |
5.505 | 0.463 | tINS | RR | 1 | u_local2reg/n1793_s40/F |
5.670 | 0.165 | tNET | RR | 1 | u_local2reg/n1793_s36/I0 |
6.133 | 0.463 | tINS | RR | 1 | u_local2reg/n1793_s36/F |
6.298 | 0.165 | tNET | RR | 1 | u_local2reg/n1793_s35/I0 |
6.761 | 0.463 | tINS | RR | 1 | u_local2reg/n1793_s35/F |
6.926 | 0.165 | tNET | RR | 1 | u_local2reg/local_rdat_o_3_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
20.000 | 0.000 | u_Gowin_PLL/PLL_inst/CLKOUT0.default_gen_clk | |||
20.713 | 0.713 | tCL | RR | 2032 | u_Gowin_PLL/PLL_inst/CLKOUT0 |
20.878 | 0.165 | tNET | RR | 1 | u_local2reg/local_rdat_o_3_s0/CLK |
20.827 | -0.051 | tSu | 1 | u_local2reg/local_rdat_o_3_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 20.000 |
Logic Level: | 10 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.165, 100.000% |
Arrival Data Path Delay: | cell: 4.092, 67.658%; route: 1.650, 27.282%; tC2Q: 0.306, 5.060% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.165, 100.000% |
Path 2
Path Summary:Slack | 13.910 |
Data Arrival Time | 6.917 |
Data Required Time | 20.827 |
From | u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_0_s0 |
To | u_local2reg/local_rdat_o_0_s0 |
Launch Clk | u_Gowin_PLL/PLL_inst/CLKOUT0.default_gen_clk[R] |
Latch Clk | u_Gowin_PLL/PLL_inst/CLKOUT0.default_gen_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | u_Gowin_PLL/PLL_inst/CLKOUT0.default_gen_clk | |||
0.713 | 0.713 | tCL | RR | 2032 | u_Gowin_PLL/PLL_inst/CLKOUT0 |
0.878 | 0.165 | tNET | RR | 1 | u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_0_s0/CLK |
1.184 | 0.306 | tC2Q | RR | 3 | u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_0_s0/Q |
1.349 | 0.165 | tNET | RR | 1 | u_uart_bus_top/uart_bus_core/apb0_sel_o_d_s2/I0 |
1.812 | 0.463 | tINS | RR | 1 | u_uart_bus_top/uart_bus_core/apb0_sel_o_d_s2/F |
1.977 | 0.165 | tNET | RR | 1 | u_uart_bus_top/uart_bus_core/apb0_sel_o_d_s0/I0 |
2.440 | 0.463 | tINS | RR | 76 | u_uart_bus_top/uart_bus_core/apb0_sel_o_d_s0/F |
2.605 | 0.165 | tNET | RR | 1 | u_uart_bus_top/uart_bus_core/apb0_addr_o_d_7_s0/I1 |
3.059 | 0.454 | tINS | RR | 1 | u_uart_bus_top/uart_bus_core/apb0_addr_o_d_7_s0/F |
3.224 | 0.165 | tNET | RR | 1 | u_local2reg/n2418_s5/I0 |
3.687 | 0.463 | tINS | RR | 2 | u_local2reg/n2418_s5/F |
3.852 | 0.165 | tNET | RR | 1 | u_local2reg/n1788_s47/I2 |
4.258 | 0.406 | tINS | RR | 23 | u_local2reg/n1788_s47/F |
4.423 | 0.165 | tNET | RR | 1 | u_local2reg/n1765_s64/I1 |
4.877 | 0.454 | tINS | RR | 32 | u_local2reg/n1765_s64/F |
5.042 | 0.165 | tNET | RR | 1 | u_local2reg/n1796_s41/I0 |
5.505 | 0.463 | tINS | RR | 1 | u_local2reg/n1796_s41/F |
5.670 | 0.165 | tNET | RR | 1 | u_local2reg/n1796_s37/I0 |
6.133 | 0.463 | tINS | RR | 1 | u_local2reg/n1796_s37/F |
6.298 | 0.165 | tNET | RR | 1 | u_local2reg/n1796_s35/I1 |
6.752 | 0.454 | tINS | RR | 1 | u_local2reg/n1796_s35/F |
6.917 | 0.165 | tNET | RR | 1 | u_local2reg/local_rdat_o_0_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
20.000 | 0.000 | u_Gowin_PLL/PLL_inst/CLKOUT0.default_gen_clk | |||
20.713 | 0.713 | tCL | RR | 2032 | u_Gowin_PLL/PLL_inst/CLKOUT0 |
20.878 | 0.165 | tNET | RR | 1 | u_local2reg/local_rdat_o_0_s0/CLK |
20.827 | -0.051 | tSu | 1 | u_local2reg/local_rdat_o_0_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 20.000 |
Logic Level: | 10 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.165, 100.000% |
Arrival Data Path Delay: | cell: 4.083, 67.611%; route: 1.650, 27.322%; tC2Q: 0.306, 5.067% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.165, 100.000% |
Path 3
Path Summary:Slack | 13.910 |
Data Arrival Time | 6.917 |
Data Required Time | 20.827 |
From | u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_0_s0 |
To | u_local2reg/local_rdat_o_2_s0 |
Launch Clk | u_Gowin_PLL/PLL_inst/CLKOUT0.default_gen_clk[R] |
Latch Clk | u_Gowin_PLL/PLL_inst/CLKOUT0.default_gen_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | u_Gowin_PLL/PLL_inst/CLKOUT0.default_gen_clk | |||
0.713 | 0.713 | tCL | RR | 2032 | u_Gowin_PLL/PLL_inst/CLKOUT0 |
0.878 | 0.165 | tNET | RR | 1 | u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_0_s0/CLK |
1.184 | 0.306 | tC2Q | RR | 3 | u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_0_s0/Q |
1.349 | 0.165 | tNET | RR | 1 | u_uart_bus_top/uart_bus_core/apb0_sel_o_d_s2/I0 |
1.812 | 0.463 | tINS | RR | 1 | u_uart_bus_top/uart_bus_core/apb0_sel_o_d_s2/F |
1.977 | 0.165 | tNET | RR | 1 | u_uart_bus_top/uart_bus_core/apb0_sel_o_d_s0/I0 |
2.440 | 0.463 | tINS | RR | 76 | u_uart_bus_top/uart_bus_core/apb0_sel_o_d_s0/F |
2.605 | 0.165 | tNET | RR | 1 | u_uart_bus_top/uart_bus_core/apb0_addr_o_d_7_s0/I1 |
3.059 | 0.454 | tINS | RR | 1 | u_uart_bus_top/uart_bus_core/apb0_addr_o_d_7_s0/F |
3.224 | 0.165 | tNET | RR | 1 | u_local2reg/n2418_s5/I0 |
3.687 | 0.463 | tINS | RR | 2 | u_local2reg/n2418_s5/F |
3.852 | 0.165 | tNET | RR | 1 | u_local2reg/n1788_s47/I2 |
4.258 | 0.406 | tINS | RR | 23 | u_local2reg/n1788_s47/F |
4.423 | 0.165 | tNET | RR | 1 | u_local2reg/n1765_s68/I1 |
4.877 | 0.454 | tINS | RR | 32 | u_local2reg/n1765_s68/F |
5.042 | 0.165 | tNET | RR | 1 | u_local2reg/n1794_s42/I0 |
5.505 | 0.463 | tINS | RR | 1 | u_local2reg/n1794_s42/F |
5.670 | 0.165 | tNET | RR | 1 | u_local2reg/n1794_s37/I0 |
6.133 | 0.463 | tINS | RR | 1 | u_local2reg/n1794_s37/F |
6.298 | 0.165 | tNET | RR | 1 | u_local2reg/n1794_s35/I1 |
6.752 | 0.454 | tINS | RR | 1 | u_local2reg/n1794_s35/F |
6.917 | 0.165 | tNET | RR | 1 | u_local2reg/local_rdat_o_2_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
20.000 | 0.000 | u_Gowin_PLL/PLL_inst/CLKOUT0.default_gen_clk | |||
20.713 | 0.713 | tCL | RR | 2032 | u_Gowin_PLL/PLL_inst/CLKOUT0 |
20.878 | 0.165 | tNET | RR | 1 | u_local2reg/local_rdat_o_2_s0/CLK |
20.827 | -0.051 | tSu | 1 | u_local2reg/local_rdat_o_2_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 20.000 |
Logic Level: | 10 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.165, 100.000% |
Arrival Data Path Delay: | cell: 4.083, 67.611%; route: 1.650, 27.322%; tC2Q: 0.306, 5.067% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.165, 100.000% |
Path 4
Path Summary:Slack | 13.910 |
Data Arrival Time | 6.917 |
Data Required Time | 20.827 |
From | u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_0_s0 |
To | u_local2reg/local_rdat_o_4_s0 |
Launch Clk | u_Gowin_PLL/PLL_inst/CLKOUT0.default_gen_clk[R] |
Latch Clk | u_Gowin_PLL/PLL_inst/CLKOUT0.default_gen_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | u_Gowin_PLL/PLL_inst/CLKOUT0.default_gen_clk | |||
0.713 | 0.713 | tCL | RR | 2032 | u_Gowin_PLL/PLL_inst/CLKOUT0 |
0.878 | 0.165 | tNET | RR | 1 | u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_0_s0/CLK |
1.184 | 0.306 | tC2Q | RR | 3 | u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_0_s0/Q |
1.349 | 0.165 | tNET | RR | 1 | u_uart_bus_top/uart_bus_core/apb0_sel_o_d_s2/I0 |
1.812 | 0.463 | tINS | RR | 1 | u_uart_bus_top/uart_bus_core/apb0_sel_o_d_s2/F |
1.977 | 0.165 | tNET | RR | 1 | u_uart_bus_top/uart_bus_core/apb0_sel_o_d_s0/I0 |
2.440 | 0.463 | tINS | RR | 76 | u_uart_bus_top/uart_bus_core/apb0_sel_o_d_s0/F |
2.605 | 0.165 | tNET | RR | 1 | u_uart_bus_top/uart_bus_core/apb0_addr_o_d_7_s0/I1 |
3.059 | 0.454 | tINS | RR | 1 | u_uart_bus_top/uart_bus_core/apb0_addr_o_d_7_s0/F |
3.224 | 0.165 | tNET | RR | 1 | u_local2reg/n2418_s5/I0 |
3.687 | 0.463 | tINS | RR | 2 | u_local2reg/n2418_s5/F |
3.852 | 0.165 | tNET | RR | 1 | u_local2reg/n1788_s47/I2 |
4.258 | 0.406 | tINS | RR | 23 | u_local2reg/n1788_s47/F |
4.423 | 0.165 | tNET | RR | 1 | u_local2reg/n1765_s69/I1 |
4.877 | 0.454 | tINS | RR | 32 | u_local2reg/n1765_s69/F |
5.042 | 0.165 | tNET | RR | 1 | u_local2reg/n1792_s42/I0 |
5.505 | 0.463 | tINS | RR | 1 | u_local2reg/n1792_s42/F |
5.670 | 0.165 | tNET | RR | 1 | u_local2reg/n1792_s37/I0 |
6.133 | 0.463 | tINS | RR | 1 | u_local2reg/n1792_s37/F |
6.298 | 0.165 | tNET | RR | 1 | u_local2reg/n1792_s35/I1 |
6.752 | 0.454 | tINS | RR | 1 | u_local2reg/n1792_s35/F |
6.917 | 0.165 | tNET | RR | 1 | u_local2reg/local_rdat_o_4_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
20.000 | 0.000 | u_Gowin_PLL/PLL_inst/CLKOUT0.default_gen_clk | |||
20.713 | 0.713 | tCL | RR | 2032 | u_Gowin_PLL/PLL_inst/CLKOUT0 |
20.878 | 0.165 | tNET | RR | 1 | u_local2reg/local_rdat_o_4_s0/CLK |
20.827 | -0.051 | tSu | 1 | u_local2reg/local_rdat_o_4_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 20.000 |
Logic Level: | 10 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.165, 100.000% |
Arrival Data Path Delay: | cell: 4.083, 67.611%; route: 1.650, 27.322%; tC2Q: 0.306, 5.067% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.165, 100.000% |
Path 5
Path Summary:Slack | 13.910 |
Data Arrival Time | 6.917 |
Data Required Time | 20.827 |
From | u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_0_s0 |
To | u_local2reg/local_rdat_o_8_s0 |
Launch Clk | u_Gowin_PLL/PLL_inst/CLKOUT0.default_gen_clk[R] |
Latch Clk | u_Gowin_PLL/PLL_inst/CLKOUT0.default_gen_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | u_Gowin_PLL/PLL_inst/CLKOUT0.default_gen_clk | |||
0.713 | 0.713 | tCL | RR | 2032 | u_Gowin_PLL/PLL_inst/CLKOUT0 |
0.878 | 0.165 | tNET | RR | 1 | u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_0_s0/CLK |
1.184 | 0.306 | tC2Q | RR | 3 | u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_0_s0/Q |
1.349 | 0.165 | tNET | RR | 1 | u_uart_bus_top/uart_bus_core/apb0_sel_o_d_s2/I0 |
1.812 | 0.463 | tINS | RR | 1 | u_uart_bus_top/uart_bus_core/apb0_sel_o_d_s2/F |
1.977 | 0.165 | tNET | RR | 1 | u_uart_bus_top/uart_bus_core/apb0_sel_o_d_s0/I0 |
2.440 | 0.463 | tINS | RR | 76 | u_uart_bus_top/uart_bus_core/apb0_sel_o_d_s0/F |
2.605 | 0.165 | tNET | RR | 1 | u_uart_bus_top/uart_bus_core/apb0_addr_o_d_7_s0/I1 |
3.059 | 0.454 | tINS | RR | 1 | u_uart_bus_top/uart_bus_core/apb0_addr_o_d_7_s0/F |
3.224 | 0.165 | tNET | RR | 1 | u_local2reg/n2418_s5/I0 |
3.687 | 0.463 | tINS | RR | 2 | u_local2reg/n2418_s5/F |
3.852 | 0.165 | tNET | RR | 1 | u_local2reg/n1788_s47/I2 |
4.258 | 0.406 | tINS | RR | 23 | u_local2reg/n1788_s47/F |
4.423 | 0.165 | tNET | RR | 1 | u_local2reg/n1765_s65/I1 |
4.877 | 0.454 | tINS | RR | 32 | u_local2reg/n1765_s65/F |
5.042 | 0.165 | tNET | RR | 1 | u_local2reg/n1788_s42/I0 |
5.505 | 0.463 | tINS | RR | 1 | u_local2reg/n1788_s42/F |
5.670 | 0.165 | tNET | RR | 1 | u_local2reg/n1788_s37/I0 |
6.133 | 0.463 | tINS | RR | 1 | u_local2reg/n1788_s37/F |
6.298 | 0.165 | tNET | RR | 1 | u_local2reg/n1788_s35/I1 |
6.752 | 0.454 | tINS | RR | 1 | u_local2reg/n1788_s35/F |
6.917 | 0.165 | tNET | RR | 1 | u_local2reg/local_rdat_o_8_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
20.000 | 0.000 | u_Gowin_PLL/PLL_inst/CLKOUT0.default_gen_clk | |||
20.713 | 0.713 | tCL | RR | 2032 | u_Gowin_PLL/PLL_inst/CLKOUT0 |
20.878 | 0.165 | tNET | RR | 1 | u_local2reg/local_rdat_o_8_s0/CLK |
20.827 | -0.051 | tSu | 1 | u_local2reg/local_rdat_o_8_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 20.000 |
Logic Level: | 10 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.165, 100.000% |
Arrival Data Path Delay: | cell: 4.083, 67.611%; route: 1.650, 27.322%; tC2Q: 0.306, 5.067% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.165, 100.000% |