Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Gowin\Gowin_V1.9.9_x64\IDE\ipcore\UARTTOBUS\data\uart_bus_core_encryption.v
C:\Gowin\Gowin_V1.9.9_x64\IDE\ipcore\UARTTOBUS\data\uart_to_bus_top.v
GowinSynthesis Constraints File ---
Tool Version V1.9.9 (64-bit)
Part Number GW5AST-LV138FPG676AES
Device GW5AST-138
Device Version B
Created Time Fri Dec 8 16:59:10 2023
Legal Announcement Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module Uart_to_Bus_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.25s, Elapsed time = 0h 0m 0.299s, Peak memory usage = 64.812MB
Running netlist conversion:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 64.812MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.033s, Peak memory usage = 64.812MB
    Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 64.812MB
    Optimizing Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.029s, Peak memory usage = 64.812MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.019s, Peak memory usage = 64.812MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 64.812MB
    Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 64.812MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 64.812MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.077s, Peak memory usage = 64.812MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.023s, Peak memory usage = 64.812MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.023s, Peak memory usage = 64.812MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 83.207MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.073s, Peak memory usage = 83.207MB
Generate output files:
    CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.101s, Peak memory usage = 83.207MB
Total Time and Memory Usage CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 83.207MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 96
I/O Buf 96
    IBUF 36
    OBUF 60
Register 1438
    DFFRE 839
    DFFPE 9
    DFFCE 590
LUT 951
    LUT2 95
    LUT3 602
    LUT4 254
ALU 39
    ALU 39
INV 11
    INV 11

Resource Utilization Summary

Resource Usage Utilization
Logic 1001(962 LUT, 39 ALU) / 138240 <1%
Register 1438 / 139140 2%
  --Register as Latch 0 / 139140 0%
  --Register as FF 1438 / 139140 2%
BSRAM 0 / 340 0%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
clk_i Base 10.000 100.0 0.000 5.000 clk_i_ibuf/I

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk_i 100.0(MHz) 191.3(MHz) 6 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 4.774
Data Arrival Time 6.051
Data Required Time 10.825
From uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_1_s0
To uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_0_s0
Launch Clk clk_i[R]
Latch Clk clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_i
0.000 0.000 tCL RR 1 clk_i_ibuf/I
0.683 0.683 tINS RR 1438 clk_i_ibuf/O
0.889 0.206 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_1_s0/CLK
1.271 0.382 tC2Q RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_1_s0/Q
1.477 0.206 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s3/I0
2.056 0.579 tINS RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s3/F
2.263 0.206 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s1/I0
2.412 0.150 tINS RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s1/O
2.619 0.206 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s0/I0
2.705 0.086 tINS RR 2 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s0/O
2.911 0.206 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s51/I0
3.490 0.579 tINS RR 2 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s51/F
3.696 0.206 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s43/I0
4.275 0.579 tINS RR 9 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s43/F
4.481 0.206 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n744_s40/I0
5.060 0.579 tINS RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n744_s40/F
5.266 0.206 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n744_s39/I0
5.845 0.579 tINS RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n744_s39/F
6.051 0.206 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_0_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_i
10.000 0.000 tCL RR 1 clk_i_ibuf/I
10.682 0.683 tINS RR 1438 clk_i_ibuf/O
10.889 0.206 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_0_s0/CLK
10.825 -0.064 tSu 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_0_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.683, 76.793%; route: 0.206, 23.207%
Arrival Data Path Delay: cell: 3.130, 60.630%; route: 1.650, 31.961%; tC2Q: 0.382, 7.409%
Required Clock Path Delay: cell: 0.683, 76.793%; route: 0.206, 23.207%

Path 2

Path Summary:
Slack 4.774
Data Arrival Time 6.051
Data Required Time 10.825
From uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_1_s0
To uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_4_s0
Launch Clk clk_i[R]
Latch Clk clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_i
0.000 0.000 tCL RR 1 clk_i_ibuf/I
0.683 0.683 tINS RR 1438 clk_i_ibuf/O
0.889 0.206 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_1_s0/CLK
1.271 0.382 tC2Q RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_1_s0/Q
1.477 0.206 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s3/I0
2.056 0.579 tINS RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s3/F
2.263 0.206 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s1/I0
2.412 0.150 tINS RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s1/O
2.619 0.206 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s0/I0
2.705 0.086 tINS RR 2 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s0/O
2.911 0.206 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s51/I0
3.490 0.579 tINS RR 2 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s51/F
3.696 0.206 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s43/I0
4.275 0.579 tINS RR 9 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s43/F
4.481 0.206 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n740_s40/I0
5.060 0.579 tINS RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n740_s40/F
5.266 0.206 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n740_s39/I0
5.845 0.579 tINS RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n740_s39/F
6.051 0.206 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_4_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_i
10.000 0.000 tCL RR 1 clk_i_ibuf/I
10.682 0.683 tINS RR 1438 clk_i_ibuf/O
10.889 0.206 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_4_s0/CLK
10.825 -0.064 tSu 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_4_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.683, 76.793%; route: 0.206, 23.207%
Arrival Data Path Delay: cell: 3.130, 60.630%; route: 1.650, 31.961%; tC2Q: 0.382, 7.409%
Required Clock Path Delay: cell: 0.683, 76.793%; route: 0.206, 23.207%

Path 3

Path Summary:
Slack 4.774
Data Arrival Time 6.051
Data Required Time 10.825
From uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_1_s0
To uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_5_s0
Launch Clk clk_i[R]
Latch Clk clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_i
0.000 0.000 tCL RR 1 clk_i_ibuf/I
0.683 0.683 tINS RR 1438 clk_i_ibuf/O
0.889 0.206 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_1_s0/CLK
1.271 0.382 tC2Q RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_1_s0/Q
1.477 0.206 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s3/I0
2.056 0.579 tINS RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s3/F
2.263 0.206 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s1/I0
2.412 0.150 tINS RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s1/O
2.619 0.206 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s0/I0
2.705 0.086 tINS RR 2 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s0/O
2.911 0.206 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s51/I0
3.490 0.579 tINS RR 2 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s51/F
3.696 0.206 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s43/I0
4.275 0.579 tINS RR 9 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s43/F
4.481 0.206 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n739_s40/I0
5.060 0.579 tINS RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n739_s40/F
5.266 0.206 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n739_s39/I0
5.845 0.579 tINS RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n739_s39/F
6.051 0.206 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_5_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_i
10.000 0.000 tCL RR 1 clk_i_ibuf/I
10.682 0.683 tINS RR 1438 clk_i_ibuf/O
10.889 0.206 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_5_s0/CLK
10.825 -0.064 tSu 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_5_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.683, 76.793%; route: 0.206, 23.207%
Arrival Data Path Delay: cell: 3.130, 60.630%; route: 1.650, 31.961%; tC2Q: 0.382, 7.409%
Required Clock Path Delay: cell: 0.683, 76.793%; route: 0.206, 23.207%

Path 4

Path Summary:
Slack 4.774
Data Arrival Time 6.051
Data Required Time 10.825
From uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_1_s0
To uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_6_s0
Launch Clk clk_i[R]
Latch Clk clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_i
0.000 0.000 tCL RR 1 clk_i_ibuf/I
0.683 0.683 tINS RR 1438 clk_i_ibuf/O
0.889 0.206 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_1_s0/CLK
1.271 0.382 tC2Q RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_1_s0/Q
1.477 0.206 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s3/I0
2.056 0.579 tINS RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s3/F
2.263 0.206 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s1/I0
2.412 0.150 tINS RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s1/O
2.619 0.206 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s0/I0
2.705 0.086 tINS RR 2 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s0/O
2.911 0.206 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s51/I0
3.490 0.579 tINS RR 2 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s51/F
3.696 0.206 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s43/I0
4.275 0.579 tINS RR 9 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s43/F
4.481 0.206 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s40/I0
5.060 0.579 tINS RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s40/F
5.266 0.206 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s39/I0
5.845 0.579 tINS RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s39/F
6.051 0.206 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_6_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_i
10.000 0.000 tCL RR 1 clk_i_ibuf/I
10.682 0.683 tINS RR 1438 clk_i_ibuf/O
10.889 0.206 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_6_s0/CLK
10.825 -0.064 tSu 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_6_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.683, 76.793%; route: 0.206, 23.207%
Arrival Data Path Delay: cell: 3.130, 60.630%; route: 1.650, 31.961%; tC2Q: 0.382, 7.409%
Required Clock Path Delay: cell: 0.683, 76.793%; route: 0.206, 23.207%

Path 5

Path Summary:
Slack 4.785
Data Arrival Time 6.040
Data Required Time 10.825
From uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_1_s0
To uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_3_s0
Launch Clk clk_i[R]
Latch Clk clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_i
0.000 0.000 tCL RR 1 clk_i_ibuf/I
0.683 0.683 tINS RR 1438 clk_i_ibuf/O
0.889 0.206 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_1_s0/CLK
1.271 0.382 tC2Q RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_1_s0/Q
1.477 0.206 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s3/I0
2.056 0.579 tINS RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s3/F
2.263 0.206 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s1/I0
2.412 0.150 tINS RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s1/O
2.619 0.206 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s0/I0
2.705 0.086 tINS RR 2 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s0/O
2.911 0.206 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s51/I0
3.490 0.579 tINS RR 2 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s51/F
3.696 0.206 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s43/I0
4.275 0.579 tINS RR 9 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s43/F
4.481 0.206 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n741_s46/I0
5.060 0.579 tINS RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n741_s46/F
5.266 0.206 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n741_s40/I1
5.834 0.567 tINS RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n741_s40/F
6.040 0.206 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_3_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_i
10.000 0.000 tCL RR 1 clk_i_ibuf/I
10.682 0.683 tINS RR 1438 clk_i_ibuf/O
10.889 0.206 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_3_s0/CLK
10.825 -0.064 tSu 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_3_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.683, 76.793%; route: 0.206, 23.207%
Arrival Data Path Delay: cell: 3.119, 60.544%; route: 1.650, 32.031%; tC2Q: 0.382, 7.425%
Required Clock Path Delay: cell: 0.683, 76.793%; route: 0.206, 23.207%