Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | C:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\I2CMASTER\data\I2C_MASTER_TOP.v C:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\I2CMASTER\data\I2C_MASTER.vp |
GowinSynthesis Constraints File | --- |
Tool Version | V1.9.11.01 (64-bit) |
Part Number | GW5AT-LV60PG484AES |
Device | GW5AT-60 |
Device Version | B |
Created Time | Mon Mar 10 11:26:44 2025 |
Legal Announcement | Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | I2C_MASTER_Top |
Synthesis Process | Running parser: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.186s, Peak memory usage = 107.301MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 107.301MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 107.301MB Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 107.301MB Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 107.301MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 107.301MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 107.301MB Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0s, Peak memory usage = 107.301MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 107.301MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 107.301MB Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 107.301MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 107.301MB Tech-Mapping Phase 3: CPU time = 0h 0m 0.656s, Elapsed time = 0h 0m 0.691s, Peak memory usage = 129.887MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.086s, Peak memory usage = 129.887MB Generate output files: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.017s, Peak memory usage = 129.887MB |
Total Time and Memory Usage | CPU time = 0h 0m 0.919s, Elapsed time = 0h 0m 1s, Peak memory usage = 129.887MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 29 |
I/O Buf | 29 |
    IBUF | 18 |
    OBUF | 9 |
    IOBUF | 2 |
Register | 124 |
    DFFPE | 7 |
    DFFCE | 117 |
LUT | 216 |
    LUT2 | 27 |
    LUT3 | 75 |
    LUT4 | 114 |
INV | 1 |
    INV | 1 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 217(217 LUT, 0 ALU) / 59904 | <1% |
Register | 124 / 60783 | <1% |
  --Register as Latch | 0 / 60783 | 0% |
  --Register as FF | 124 / 60783 | <1% |
BSRAM | 0 / 118 | 0% |
Timing
Clock Summary:
NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|---|
1 | I_CLK | Base | 10.000 | 100.000 | 0.000 | 5.000 | I_CLK_ibuf/I |
Max Frequency Summary:
NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | I_CLK | 100.000(MHz) | 214.420(MHz) | 5 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | 5.336 |
Data Arrival Time | 4.727 |
Data Required Time | 10.064 |
From | u_i2c_master/bit_controller/c_state_8_s1 |
To | u_i2c_master/bit_controller/SCL_OEN_s1 |
Launch Clk | I_CLK[R] |
Latch Clk | I_CLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | I_CLK | |||
0.000 | 0.000 | tCL | RR | 1 | I_CLK_ibuf/I |
0.000 | 0.000 | tINS | RR | 124 | I_CLK_ibuf/O |
0.375 | 0.375 | tNET | RR | 1 | u_i2c_master/bit_controller/c_state_8_s1/CLK |
0.757 | 0.382 | tC2Q | RR | 9 | u_i2c_master/bit_controller/c_state_8_s1/Q |
1.132 | 0.375 | tNET | RR | 1 | u_i2c_master/bit_controller/n214_s5/I0 |
1.659 | 0.526 | tINS | RR | 1 | u_i2c_master/bit_controller/n214_s5/F |
2.034 | 0.375 | tNET | RR | 1 | u_i2c_master/bit_controller/n214_s4/I0 |
2.560 | 0.526 | tINS | RR | 7 | u_i2c_master/bit_controller/n214_s4/F |
2.935 | 0.375 | tNET | RR | 1 | u_i2c_master/bit_controller/n228_s4/I1 |
3.451 | 0.516 | tINS | RR | 4 | u_i2c_master/bit_controller/n228_s4/F |
3.826 | 0.375 | tNET | RR | 1 | u_i2c_master/bit_controller/SCL_OEN_s5/I0 |
4.352 | 0.526 | tINS | RR | 1 | u_i2c_master/bit_controller/SCL_OEN_s5/F |
4.727 | 0.375 | tNET | RR | 1 | u_i2c_master/bit_controller/SCL_OEN_s1/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | I_CLK | |||
10.000 | 0.000 | tCL | RR | 1 | I_CLK_ibuf/I |
10.000 | 0.000 | tINS | RR | 124 | I_CLK_ibuf/O |
10.375 | 0.375 | tNET | RR | 1 | u_i2c_master/bit_controller/SCL_OEN_s1/CLK |
10.064 | -0.311 | tSu | 1 | u_i2c_master/bit_controller/SCL_OEN_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Arrival Data Path Delay: | cell: 2.095, 48.133%; route: 1.875, 43.079%; tC2Q: 0.382, 8.788% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 2
Path Summary:Slack | 5.346 |
Data Arrival Time | 4.718 |
Data Required Time | 10.064 |
From | u_i2c_master/bit_controller/cnt_9_s1 |
To | u_i2c_master/bit_controller/cnt_15_s1 |
Launch Clk | I_CLK[R] |
Latch Clk | I_CLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | I_CLK | |||
0.000 | 0.000 | tCL | RR | 1 | I_CLK_ibuf/I |
0.000 | 0.000 | tINS | RR | 124 | I_CLK_ibuf/O |
0.375 | 0.375 | tNET | RR | 1 | u_i2c_master/bit_controller/cnt_9_s1/CLK |
0.757 | 0.382 | tC2Q | RR | 5 | u_i2c_master/bit_controller/cnt_9_s1/Q |
1.132 | 0.375 | tNET | RR | 1 | u_i2c_master/bit_controller/n13_s3/I0 |
1.659 | 0.526 | tINS | RR | 1 | u_i2c_master/bit_controller/n13_s3/F |
2.034 | 0.375 | tNET | RR | 1 | u_i2c_master/bit_controller/n13_s1/I1 |
2.550 | 0.516 | tINS | RR | 4 | u_i2c_master/bit_controller/n13_s1/F |
2.925 | 0.375 | tNET | RR | 1 | u_i2c_master/bit_controller/n13_s0/I0 |
3.451 | 0.526 | tINS | RR | 17 | u_i2c_master/bit_controller/n13_s0/F |
3.826 | 0.375 | tNET | RR | 1 | u_i2c_master/bit_controller/cnt_15_s3/I1 |
4.343 | 0.516 | tINS | RR | 16 | u_i2c_master/bit_controller/cnt_15_s3/F |
4.718 | 0.375 | tNET | RR | 1 | u_i2c_master/bit_controller/cnt_15_s1/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | I_CLK | |||
10.000 | 0.000 | tCL | RR | 1 | I_CLK_ibuf/I |
10.000 | 0.000 | tINS | RR | 124 | I_CLK_ibuf/O |
10.375 | 0.375 | tNET | RR | 1 | u_i2c_master/bit_controller/cnt_15_s1/CLK |
10.064 | -0.311 | tSu | 1 | u_i2c_master/bit_controller/cnt_15_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Arrival Data Path Delay: | cell: 2.085, 48.014%; route: 1.875, 43.178%; tC2Q: 0.382, 8.808% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 3
Path Summary:Slack | 5.346 |
Data Arrival Time | 4.718 |
Data Required Time | 10.064 |
From | u_i2c_master/bit_controller/cnt_9_s1 |
To | u_i2c_master/bit_controller/cnt_14_s1 |
Launch Clk | I_CLK[R] |
Latch Clk | I_CLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | I_CLK | |||
0.000 | 0.000 | tCL | RR | 1 | I_CLK_ibuf/I |
0.000 | 0.000 | tINS | RR | 124 | I_CLK_ibuf/O |
0.375 | 0.375 | tNET | RR | 1 | u_i2c_master/bit_controller/cnt_9_s1/CLK |
0.757 | 0.382 | tC2Q | RR | 5 | u_i2c_master/bit_controller/cnt_9_s1/Q |
1.132 | 0.375 | tNET | RR | 1 | u_i2c_master/bit_controller/n13_s3/I0 |
1.659 | 0.526 | tINS | RR | 1 | u_i2c_master/bit_controller/n13_s3/F |
2.034 | 0.375 | tNET | RR | 1 | u_i2c_master/bit_controller/n13_s1/I1 |
2.550 | 0.516 | tINS | RR | 4 | u_i2c_master/bit_controller/n13_s1/F |
2.925 | 0.375 | tNET | RR | 1 | u_i2c_master/bit_controller/n13_s0/I0 |
3.451 | 0.526 | tINS | RR | 17 | u_i2c_master/bit_controller/n13_s0/F |
3.826 | 0.375 | tNET | RR | 1 | u_i2c_master/bit_controller/cnt_15_s3/I1 |
4.343 | 0.516 | tINS | RR | 16 | u_i2c_master/bit_controller/cnt_15_s3/F |
4.718 | 0.375 | tNET | RR | 1 | u_i2c_master/bit_controller/cnt_14_s1/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | I_CLK | |||
10.000 | 0.000 | tCL | RR | 1 | I_CLK_ibuf/I |
10.000 | 0.000 | tINS | RR | 124 | I_CLK_ibuf/O |
10.375 | 0.375 | tNET | RR | 1 | u_i2c_master/bit_controller/cnt_14_s1/CLK |
10.064 | -0.311 | tSu | 1 | u_i2c_master/bit_controller/cnt_14_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Arrival Data Path Delay: | cell: 2.085, 48.014%; route: 1.875, 43.178%; tC2Q: 0.382, 8.808% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 4
Path Summary:Slack | 5.346 |
Data Arrival Time | 4.718 |
Data Required Time | 10.064 |
From | u_i2c_master/bit_controller/cnt_9_s1 |
To | u_i2c_master/bit_controller/cnt_13_s1 |
Launch Clk | I_CLK[R] |
Latch Clk | I_CLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | I_CLK | |||
0.000 | 0.000 | tCL | RR | 1 | I_CLK_ibuf/I |
0.000 | 0.000 | tINS | RR | 124 | I_CLK_ibuf/O |
0.375 | 0.375 | tNET | RR | 1 | u_i2c_master/bit_controller/cnt_9_s1/CLK |
0.757 | 0.382 | tC2Q | RR | 5 | u_i2c_master/bit_controller/cnt_9_s1/Q |
1.132 | 0.375 | tNET | RR | 1 | u_i2c_master/bit_controller/n13_s3/I0 |
1.659 | 0.526 | tINS | RR | 1 | u_i2c_master/bit_controller/n13_s3/F |
2.034 | 0.375 | tNET | RR | 1 | u_i2c_master/bit_controller/n13_s1/I1 |
2.550 | 0.516 | tINS | RR | 4 | u_i2c_master/bit_controller/n13_s1/F |
2.925 | 0.375 | tNET | RR | 1 | u_i2c_master/bit_controller/n13_s0/I0 |
3.451 | 0.526 | tINS | RR | 17 | u_i2c_master/bit_controller/n13_s0/F |
3.826 | 0.375 | tNET | RR | 1 | u_i2c_master/bit_controller/cnt_15_s3/I1 |
4.343 | 0.516 | tINS | RR | 16 | u_i2c_master/bit_controller/cnt_15_s3/F |
4.718 | 0.375 | tNET | RR | 1 | u_i2c_master/bit_controller/cnt_13_s1/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | I_CLK | |||
10.000 | 0.000 | tCL | RR | 1 | I_CLK_ibuf/I |
10.000 | 0.000 | tINS | RR | 124 | I_CLK_ibuf/O |
10.375 | 0.375 | tNET | RR | 1 | u_i2c_master/bit_controller/cnt_13_s1/CLK |
10.064 | -0.311 | tSu | 1 | u_i2c_master/bit_controller/cnt_13_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Arrival Data Path Delay: | cell: 2.085, 48.014%; route: 1.875, 43.178%; tC2Q: 0.382, 8.808% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 5
Path Summary:Slack | 5.346 |
Data Arrival Time | 4.718 |
Data Required Time | 10.064 |
From | u_i2c_master/bit_controller/cnt_9_s1 |
To | u_i2c_master/bit_controller/cnt_12_s1 |
Launch Clk | I_CLK[R] |
Latch Clk | I_CLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | I_CLK | |||
0.000 | 0.000 | tCL | RR | 1 | I_CLK_ibuf/I |
0.000 | 0.000 | tINS | RR | 124 | I_CLK_ibuf/O |
0.375 | 0.375 | tNET | RR | 1 | u_i2c_master/bit_controller/cnt_9_s1/CLK |
0.757 | 0.382 | tC2Q | RR | 5 | u_i2c_master/bit_controller/cnt_9_s1/Q |
1.132 | 0.375 | tNET | RR | 1 | u_i2c_master/bit_controller/n13_s3/I0 |
1.659 | 0.526 | tINS | RR | 1 | u_i2c_master/bit_controller/n13_s3/F |
2.034 | 0.375 | tNET | RR | 1 | u_i2c_master/bit_controller/n13_s1/I1 |
2.550 | 0.516 | tINS | RR | 4 | u_i2c_master/bit_controller/n13_s1/F |
2.925 | 0.375 | tNET | RR | 1 | u_i2c_master/bit_controller/n13_s0/I0 |
3.451 | 0.526 | tINS | RR | 17 | u_i2c_master/bit_controller/n13_s0/F |
3.826 | 0.375 | tNET | RR | 1 | u_i2c_master/bit_controller/cnt_15_s3/I1 |
4.343 | 0.516 | tINS | RR | 16 | u_i2c_master/bit_controller/cnt_15_s3/F |
4.718 | 0.375 | tNET | RR | 1 | u_i2c_master/bit_controller/cnt_12_s1/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | I_CLK | |||
10.000 | 0.000 | tCL | RR | 1 | I_CLK_ibuf/I |
10.000 | 0.000 | tINS | RR | 124 | I_CLK_ibuf/O |
10.375 | 0.375 | tNET | RR | 1 | u_i2c_master/bit_controller/cnt_12_s1/CLK |
10.064 | -0.311 | tSu | 1 | u_i2c_master/bit_controller/cnt_12_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Arrival Data Path Delay: | cell: 2.085, 48.014%; route: 1.875, 43.178%; tC2Q: 0.382, 8.808% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |