Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\SDIDecoder\data\sdi_decoder_top.v
C:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\SDIDecoder\data\sdi_decoder_wrapper.v
GowinSynthesis Constraints File ---
Tool Version V1.9.11.01 (64-bit)
Part Number GW5AT-LV60PG484AES
Device GW5AT-60
Device Version B
Created Time Mon Mar 10 11:26:00 2025
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module SDI_Decoder_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.234s, Elapsed time = 0h 0m 0.23s, Peak memory usage = 109.699MB
Running netlist conversion:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 109.699MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.052s, Peak memory usage = 109.699MB
    Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.014s, Peak memory usage = 109.699MB
    Optimizing Phase 2: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.056s, Peak memory usage = 109.699MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 109.699MB
    Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 109.699MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 109.699MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 109.699MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.042s, Peak memory usage = 109.699MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.065s, Peak memory usage = 109.699MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 109.699MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 134.945MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.112s, Peak memory usage = 134.945MB
Generate output files:
    CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.053s, Peak memory usage = 134.945MB
Total Time and Memory Usage CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 134.945MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 192
I/O Buf 124
    IBUF 28
    OBUF 96
Register 465
    DFFPE 2
    DFFCE 463
LUT 698
    LUT2 58
    LUT3 234
    LUT4 406
ALU 10
    ALU 10
INV 1
    INV 1

Resource Utilization Summary

Resource Usage Utilization
Logic 709(699 LUT, 10 ALU) / 59904 2%
Register 465 / 60783 <1%
  --Register as Latch 0 / 60783 0%
  --Register as FF 465 / 60783 <1%
BSRAM 0 / 118 0%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 I_clk Base 10.000 100.000 0.000 5.000 I_clk_ibuf/I
2 I_drp_clk Base 10.000 100.000 0.000 5.000 I_drp_clk_ibuf/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 I_clk 100.000(MHz) 154.410(MHz) 7 TOP
2 I_drp_clk 100.000(MHz) 162.503(MHz) 7 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 3.524
Data Arrival Time 6.540
Data Required Time 10.064
From sdi_decoder_wrapper_inst/rx_hd_nrzi_des_inst/des_7_s0
To sdi_decoder_wrapper_inst/rx_data_align_inst/hd_align_phase_4_s0
Launch Clk I_clk[R]
Latch Clk I_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 I_clk_ibuf/I
0.000 0.000 tINS RR 387 I_clk_ibuf/O
0.375 0.375 tNET RR 1 sdi_decoder_wrapper_inst/rx_hd_nrzi_des_inst/des_7_s0/CLK
0.757 0.382 tC2Q RR 5 sdi_decoder_wrapper_inst/rx_hd_nrzi_des_inst/des_7_s0/Q
1.132 0.375 tNET RR 1 sdi_decoder_wrapper_inst/rx_data_align_inst/n1113_s42/I0
1.659 0.526 tINS RR 1 sdi_decoder_wrapper_inst/rx_data_align_inst/n1113_s42/F
2.034 0.375 tNET RR 1 sdi_decoder_wrapper_inst/rx_data_align_inst/n1113_s20/I0
2.560 0.526 tINS RR 3 sdi_decoder_wrapper_inst/rx_data_align_inst/n1113_s20/F
2.935 0.375 tNET RR 1 sdi_decoder_wrapper_inst/rx_data_align_inst/n1113_s11/I0
3.461 0.526 tINS RR 4 sdi_decoder_wrapper_inst/rx_data_align_inst/n1113_s11/F
3.836 0.375 tNET RR 1 sdi_decoder_wrapper_inst/rx_data_align_inst/n1111_s7/I0
4.362 0.526 tINS RR 2 sdi_decoder_wrapper_inst/rx_data_align_inst/n1111_s7/F
4.737 0.375 tNET RR 1 sdi_decoder_wrapper_inst/rx_data_align_inst/n1265_s23/I0
5.264 0.526 tINS RR 4 sdi_decoder_wrapper_inst/rx_data_align_inst/n1265_s23/F
5.639 0.375 tNET RR 1 sdi_decoder_wrapper_inst/rx_data_align_inst/hd_align_phase_4_s5/I0
6.165 0.526 tINS RR 5 sdi_decoder_wrapper_inst/rx_data_align_inst/hd_align_phase_4_s5/F
6.540 0.375 tNET RR 1 sdi_decoder_wrapper_inst/rx_data_align_inst/hd_align_phase_4_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_clk
10.000 0.000 tCL RR 1 I_clk_ibuf/I
10.000 0.000 tINS RR 387 I_clk_ibuf/O
10.375 0.375 tNET RR 1 sdi_decoder_wrapper_inst/rx_data_align_inst/hd_align_phase_4_s0/CLK
10.064 -0.311 tSu 1 sdi_decoder_wrapper_inst/rx_data_align_inst/hd_align_phase_4_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 3.157, 51.217%; route: 2.625, 42.579%; tC2Q: 0.382, 6.204%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 2

Path Summary:
Slack 3.524
Data Arrival Time 6.540
Data Required Time 10.064
From sdi_decoder_wrapper_inst/rx_hd_nrzi_des_inst/des_7_s0
To sdi_decoder_wrapper_inst/rx_data_align_inst/hd_align_phase_3_s0
Launch Clk I_clk[R]
Latch Clk I_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 I_clk_ibuf/I
0.000 0.000 tINS RR 387 I_clk_ibuf/O
0.375 0.375 tNET RR 1 sdi_decoder_wrapper_inst/rx_hd_nrzi_des_inst/des_7_s0/CLK
0.757 0.382 tC2Q RR 5 sdi_decoder_wrapper_inst/rx_hd_nrzi_des_inst/des_7_s0/Q
1.132 0.375 tNET RR 1 sdi_decoder_wrapper_inst/rx_data_align_inst/n1113_s42/I0
1.659 0.526 tINS RR 1 sdi_decoder_wrapper_inst/rx_data_align_inst/n1113_s42/F
2.034 0.375 tNET RR 1 sdi_decoder_wrapper_inst/rx_data_align_inst/n1113_s20/I0
2.560 0.526 tINS RR 3 sdi_decoder_wrapper_inst/rx_data_align_inst/n1113_s20/F
2.935 0.375 tNET RR 1 sdi_decoder_wrapper_inst/rx_data_align_inst/n1113_s11/I0
3.461 0.526 tINS RR 4 sdi_decoder_wrapper_inst/rx_data_align_inst/n1113_s11/F
3.836 0.375 tNET RR 1 sdi_decoder_wrapper_inst/rx_data_align_inst/n1111_s7/I0
4.362 0.526 tINS RR 2 sdi_decoder_wrapper_inst/rx_data_align_inst/n1111_s7/F
4.737 0.375 tNET RR 1 sdi_decoder_wrapper_inst/rx_data_align_inst/n1265_s23/I0
5.264 0.526 tINS RR 4 sdi_decoder_wrapper_inst/rx_data_align_inst/n1265_s23/F
5.639 0.375 tNET RR 1 sdi_decoder_wrapper_inst/rx_data_align_inst/hd_align_phase_4_s5/I0
6.165 0.526 tINS RR 5 sdi_decoder_wrapper_inst/rx_data_align_inst/hd_align_phase_4_s5/F
6.540 0.375 tNET RR 1 sdi_decoder_wrapper_inst/rx_data_align_inst/hd_align_phase_3_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_clk
10.000 0.000 tCL RR 1 I_clk_ibuf/I
10.000 0.000 tINS RR 387 I_clk_ibuf/O
10.375 0.375 tNET RR 1 sdi_decoder_wrapper_inst/rx_data_align_inst/hd_align_phase_3_s0/CLK
10.064 -0.311 tSu 1 sdi_decoder_wrapper_inst/rx_data_align_inst/hd_align_phase_3_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 3.157, 51.217%; route: 2.625, 42.579%; tC2Q: 0.382, 6.204%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 3

Path Summary:
Slack 3.524
Data Arrival Time 6.540
Data Required Time 10.064
From sdi_decoder_wrapper_inst/rx_hd_nrzi_des_inst/des_7_s0
To sdi_decoder_wrapper_inst/rx_data_align_inst/hd_align_phase_2_s0
Launch Clk I_clk[R]
Latch Clk I_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 I_clk_ibuf/I
0.000 0.000 tINS RR 387 I_clk_ibuf/O
0.375 0.375 tNET RR 1 sdi_decoder_wrapper_inst/rx_hd_nrzi_des_inst/des_7_s0/CLK
0.757 0.382 tC2Q RR 5 sdi_decoder_wrapper_inst/rx_hd_nrzi_des_inst/des_7_s0/Q
1.132 0.375 tNET RR 1 sdi_decoder_wrapper_inst/rx_data_align_inst/n1113_s42/I0
1.659 0.526 tINS RR 1 sdi_decoder_wrapper_inst/rx_data_align_inst/n1113_s42/F
2.034 0.375 tNET RR 1 sdi_decoder_wrapper_inst/rx_data_align_inst/n1113_s20/I0
2.560 0.526 tINS RR 3 sdi_decoder_wrapper_inst/rx_data_align_inst/n1113_s20/F
2.935 0.375 tNET RR 1 sdi_decoder_wrapper_inst/rx_data_align_inst/n1113_s11/I0
3.461 0.526 tINS RR 4 sdi_decoder_wrapper_inst/rx_data_align_inst/n1113_s11/F
3.836 0.375 tNET RR 1 sdi_decoder_wrapper_inst/rx_data_align_inst/n1111_s7/I0
4.362 0.526 tINS RR 2 sdi_decoder_wrapper_inst/rx_data_align_inst/n1111_s7/F
4.737 0.375 tNET RR 1 sdi_decoder_wrapper_inst/rx_data_align_inst/n1265_s23/I0
5.264 0.526 tINS RR 4 sdi_decoder_wrapper_inst/rx_data_align_inst/n1265_s23/F
5.639 0.375 tNET RR 1 sdi_decoder_wrapper_inst/rx_data_align_inst/hd_align_phase_4_s5/I0
6.165 0.526 tINS RR 5 sdi_decoder_wrapper_inst/rx_data_align_inst/hd_align_phase_4_s5/F
6.540 0.375 tNET RR 1 sdi_decoder_wrapper_inst/rx_data_align_inst/hd_align_phase_2_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_clk
10.000 0.000 tCL RR 1 I_clk_ibuf/I
10.000 0.000 tINS RR 387 I_clk_ibuf/O
10.375 0.375 tNET RR 1 sdi_decoder_wrapper_inst/rx_data_align_inst/hd_align_phase_2_s0/CLK
10.064 -0.311 tSu 1 sdi_decoder_wrapper_inst/rx_data_align_inst/hd_align_phase_2_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 3.157, 51.217%; route: 2.625, 42.579%; tC2Q: 0.382, 6.204%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 4

Path Summary:
Slack 3.524
Data Arrival Time 6.540
Data Required Time 10.064
From sdi_decoder_wrapper_inst/rx_hd_nrzi_des_inst/des_7_s0
To sdi_decoder_wrapper_inst/rx_data_align_inst/hd_align_phase_1_s0
Launch Clk I_clk[R]
Latch Clk I_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 I_clk_ibuf/I
0.000 0.000 tINS RR 387 I_clk_ibuf/O
0.375 0.375 tNET RR 1 sdi_decoder_wrapper_inst/rx_hd_nrzi_des_inst/des_7_s0/CLK
0.757 0.382 tC2Q RR 5 sdi_decoder_wrapper_inst/rx_hd_nrzi_des_inst/des_7_s0/Q
1.132 0.375 tNET RR 1 sdi_decoder_wrapper_inst/rx_data_align_inst/n1113_s42/I0
1.659 0.526 tINS RR 1 sdi_decoder_wrapper_inst/rx_data_align_inst/n1113_s42/F
2.034 0.375 tNET RR 1 sdi_decoder_wrapper_inst/rx_data_align_inst/n1113_s20/I0
2.560 0.526 tINS RR 3 sdi_decoder_wrapper_inst/rx_data_align_inst/n1113_s20/F
2.935 0.375 tNET RR 1 sdi_decoder_wrapper_inst/rx_data_align_inst/n1113_s11/I0
3.461 0.526 tINS RR 4 sdi_decoder_wrapper_inst/rx_data_align_inst/n1113_s11/F
3.836 0.375 tNET RR 1 sdi_decoder_wrapper_inst/rx_data_align_inst/n1111_s7/I0
4.362 0.526 tINS RR 2 sdi_decoder_wrapper_inst/rx_data_align_inst/n1111_s7/F
4.737 0.375 tNET RR 1 sdi_decoder_wrapper_inst/rx_data_align_inst/n1265_s23/I0
5.264 0.526 tINS RR 4 sdi_decoder_wrapper_inst/rx_data_align_inst/n1265_s23/F
5.639 0.375 tNET RR 1 sdi_decoder_wrapper_inst/rx_data_align_inst/hd_align_phase_4_s5/I0
6.165 0.526 tINS RR 5 sdi_decoder_wrapper_inst/rx_data_align_inst/hd_align_phase_4_s5/F
6.540 0.375 tNET RR 1 sdi_decoder_wrapper_inst/rx_data_align_inst/hd_align_phase_1_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_clk
10.000 0.000 tCL RR 1 I_clk_ibuf/I
10.000 0.000 tINS RR 387 I_clk_ibuf/O
10.375 0.375 tNET RR 1 sdi_decoder_wrapper_inst/rx_data_align_inst/hd_align_phase_1_s0/CLK
10.064 -0.311 tSu 1 sdi_decoder_wrapper_inst/rx_data_align_inst/hd_align_phase_1_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 3.157, 51.217%; route: 2.625, 42.579%; tC2Q: 0.382, 6.204%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 5

Path Summary:
Slack 3.524
Data Arrival Time 6.540
Data Required Time 10.064
From sdi_decoder_wrapper_inst/rx_hd_nrzi_des_inst/des_7_s0
To sdi_decoder_wrapper_inst/rx_data_align_inst/hd_align_phase_0_s0
Launch Clk I_clk[R]
Latch Clk I_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 I_clk_ibuf/I
0.000 0.000 tINS RR 387 I_clk_ibuf/O
0.375 0.375 tNET RR 1 sdi_decoder_wrapper_inst/rx_hd_nrzi_des_inst/des_7_s0/CLK
0.757 0.382 tC2Q RR 5 sdi_decoder_wrapper_inst/rx_hd_nrzi_des_inst/des_7_s0/Q
1.132 0.375 tNET RR 1 sdi_decoder_wrapper_inst/rx_data_align_inst/n1113_s42/I0
1.659 0.526 tINS RR 1 sdi_decoder_wrapper_inst/rx_data_align_inst/n1113_s42/F
2.034 0.375 tNET RR 1 sdi_decoder_wrapper_inst/rx_data_align_inst/n1113_s20/I0
2.560 0.526 tINS RR 3 sdi_decoder_wrapper_inst/rx_data_align_inst/n1113_s20/F
2.935 0.375 tNET RR 1 sdi_decoder_wrapper_inst/rx_data_align_inst/n1113_s11/I0
3.461 0.526 tINS RR 4 sdi_decoder_wrapper_inst/rx_data_align_inst/n1113_s11/F
3.836 0.375 tNET RR 1 sdi_decoder_wrapper_inst/rx_data_align_inst/n1111_s7/I0
4.362 0.526 tINS RR 2 sdi_decoder_wrapper_inst/rx_data_align_inst/n1111_s7/F
4.737 0.375 tNET RR 1 sdi_decoder_wrapper_inst/rx_data_align_inst/n1265_s23/I0
5.264 0.526 tINS RR 4 sdi_decoder_wrapper_inst/rx_data_align_inst/n1265_s23/F
5.639 0.375 tNET RR 1 sdi_decoder_wrapper_inst/rx_data_align_inst/hd_align_phase_4_s5/I0
6.165 0.526 tINS RR 5 sdi_decoder_wrapper_inst/rx_data_align_inst/hd_align_phase_4_s5/F
6.540 0.375 tNET RR 1 sdi_decoder_wrapper_inst/rx_data_align_inst/hd_align_phase_0_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_clk
10.000 0.000 tCL RR 1 I_clk_ibuf/I
10.000 0.000 tINS RR 387 I_clk_ibuf/O
10.375 0.375 tNET RR 1 sdi_decoder_wrapper_inst/rx_data_align_inst/hd_align_phase_0_s0/CLK
10.064 -0.311 tSu 1 sdi_decoder_wrapper_inst/rx_data_align_inst/hd_align_phase_0_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 3.157, 51.217%; route: 2.625, 42.579%; tC2Q: 0.382, 6.204%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%