Timing Messages

Report Title Timing Analysis Report
Design File E:\myWork\IP\releaseVerify\verifyCase\Serdes\Gowin_SDI_PHY_RefDesign\project\impl\gwsynthesis\dk_video.vg
Physical Constraints File E:\myWork\IP\releaseVerify\verifyCase\Serdes\Gowin_SDI_PHY_RefDesign\project\src\dk_video.cst
Timing Constraint File E:\myWork\IP\releaseVerify\verifyCase\Serdes\Gowin_SDI_PHY_RefDesign\project\src\dk_video.sdc
Tool Version V1.9.11.01 (64-bit)
Part Number GW5AT-LV60PG484AES
Device GW5AT-60
Device Version B
Created Time Mon Mar 10 15:48:42 2025
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model Slow 0.855V 0C ES
Hold Delay Model Fast 0.945V 85C ES
Numbers of Paths Analyzed 4170
Numbers of Endpoints Analyzed 6336
Numbers of Falling Endpoints 0
Numbers of Setup Violated Endpoints 0
Numbers of Hold Violated Endpoints 0

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Objects
1 sclk Base 20.000 50.000 0.000 10.000 sclk
2 sdi_phy_tx_clk Base 13.468 74.250 0.000 6.734 sdi_phy_tx_clk
3 sdi_phy_rx_clk Base 13.468 74.250 0.000 6.734 sdi_phy_rx_clk
4 I_clk_p Base 5.000 200.000 0.000 2.500 IB_clk_inst/I
5 Gowin_PLL_inst/PLLA_inst/CLKOUT0.default_gen_clk Generated 13.468 74.250 0.000 6.734 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_RX_O_FABRIC_CLK sdi_phy_rx_clk Gowin_PLL_inst/PLLA_inst/CLKOUT0

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 sclk 50.000(MHz) 179.694(MHz) 5 TOP
2 sdi_phy_tx_clk 74.250(MHz) 115.665(MHz) 8 TOP
3 sdi_phy_rx_clk 74.250(MHz) 121.102(MHz) 7 TOP

No timing paths to get frequency of I_clk_p!

No timing paths to get frequency of Gowin_PLL_inst/PLLA_inst/CLKOUT0.default_gen_clk!

Total Negative Slack Summary:

Clock Name Analysis Type Endpoints TNS Number of Endpoints
sclk Setup 0.000 0
sclk Hold 0.000 0
sdi_phy_tx_clk Setup 0.000 0
sdi_phy_tx_clk Hold 0.000 0
sdi_phy_rx_clk Setup 0.000 0
sdi_phy_rx_clk Hold 0.000 0
I_clk_p Setup 0.000 0
I_clk_p Hold 0.000 0
Gowin_PLL_inst/PLLA_inst/CLKOUT0.default_gen_clk Setup 0.000 0
Gowin_PLL_inst/PLLA_inst/CLKOUT0.default_gen_clk Hold 0.000 0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 4.822 SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_12_s0/Q SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_13_s0/D sdi_phy_tx_clk:[R] sdi_phy_tx_clk:[R] 13.468 -0.009 8.591
2 5.211 SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/rx_data_d3_13_s0/Q SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/hd_align_phase_4_s0/CE sdi_phy_rx_clk:[R] sdi_phy_rx_clk:[R] 13.468 0.000 7.946
3 5.211 SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/rx_data_d3_13_s0/Q SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/hd_align_phase_3_s0/CE sdi_phy_rx_clk:[R] sdi_phy_rx_clk:[R] 13.468 0.000 7.946
4 5.211 SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/rx_data_d3_13_s0/Q SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/hd_align_phase_2_s0/CE sdi_phy_rx_clk:[R] sdi_phy_rx_clk:[R] 13.468 0.000 7.946
5 5.213 SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/rx_data_d3_13_s0/Q SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/hd_align_phase_0_s0/CE sdi_phy_rx_clk:[R] sdi_phy_rx_clk:[R] 13.468 0.000 7.944
6 5.319 SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_12_s0/Q SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_15_s0/D sdi_phy_tx_clk:[R] sdi_phy_tx_clk:[R] 13.468 0.000 8.085
7 5.403 SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/rx_data_d3_13_s0/Q SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/hd_align_phase_1_s0/CE sdi_phy_rx_clk:[R] sdi_phy_rx_clk:[R] 13.468 0.000 7.754
8 5.432 SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_12_s0/Q SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_11_s0/D sdi_phy_tx_clk:[R] sdi_phy_tx_clk:[R] 13.468 0.009 7.962
9 5.461 SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_12_s0/Q SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_18_s0/D sdi_phy_tx_clk:[R] sdi_phy_tx_clk:[R] 13.468 0.000 7.944
10 5.514 SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_1_s0/Q SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_5_s0/D sdi_phy_tx_clk:[R] sdi_phy_tx_clk:[R] 13.468 0.000 7.890
11 5.628 SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_12_s0/Q SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_0_s0/D sdi_phy_tx_clk:[R] sdi_phy_tx_clk:[R] 13.468 0.000 7.776
12 5.650 SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_12_s0/Q SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_1_s0/D sdi_phy_tx_clk:[R] sdi_phy_tx_clk:[R] 13.468 -0.009 7.764
13 5.677 SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_12_s0/Q SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_12_s0/D sdi_phy_tx_clk:[R] sdi_phy_tx_clk:[R] 13.468 0.000 7.727
14 5.690 SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0/Q SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_10_s0/D sdi_phy_tx_clk:[R] sdi_phy_tx_clk:[R] 13.468 -0.009 7.724
15 5.719 SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/rx_data_d3_13_s0/Q SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/hd_match_flag_s0/D sdi_phy_rx_clk:[R] sdi_phy_rx_clk:[R] 13.468 0.000 7.685
16 5.731 SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_12_s0/Q SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_14_s0/D sdi_phy_tx_clk:[R] sdi_phy_tx_clk:[R] 13.468 -0.009 7.682
17 5.758 SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_12_s0/Q SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_7_s0/D sdi_phy_tx_clk:[R] sdi_phy_tx_clk:[R] 13.468 0.000 7.646
18 5.762 SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_1_s0/Q SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_3_s0/D sdi_phy_tx_clk:[R] sdi_phy_tx_clk:[R] 13.468 -0.009 7.651
19 5.763 SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0/Q SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_6_s0/D sdi_phy_tx_clk:[R] sdi_phy_tx_clk:[R] 13.468 0.000 7.641
20 5.774 SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0/Q SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_16_s0/D sdi_phy_tx_clk:[R] sdi_phy_tx_clk:[R] 13.468 0.000 7.630
21 5.825 SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_12_s0/Q SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_19_s0/D sdi_phy_tx_clk:[R] sdi_phy_tx_clk:[R] 13.468 -0.009 7.589
22 5.837 SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_12_s0/Q SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_2_s0/D sdi_phy_tx_clk:[R] sdi_phy_tx_clk:[R] 13.468 0.009 7.558
23 5.907 SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_12_s0/Q SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_8_s0/D sdi_phy_tx_clk:[R] sdi_phy_tx_clk:[R] 13.468 0.000 7.497
24 5.947 SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_1_s0/Q SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_4_s0/D sdi_phy_tx_clk:[R] sdi_phy_tx_clk:[R] 13.468 -0.019 7.476
25 5.950 SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_1_s0/Q SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_17_s0/D sdi_phy_tx_clk:[R] sdi_phy_tx_clk:[R] 13.468 -0.009 7.464

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.193 SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/I_data_d1_0_s2/Q SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/I_data_d1_0_s14/AD[0] sdi_phy_tx_clk:[R] sdi_phy_tx_clk:[R] 0.000 0.000 0.243
2 0.275 SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_data_extract_inst/dot_cnt_2_s0/Q SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_data_extract_inst/dot_cnt_2_s0/D sdi_phy_rx_clk:[R] sdi_phy_rx_clk:[R] 0.000 0.000 0.300
3 0.275 SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/hd_check_phase_0_s1/Q SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/hd_check_phase_0_s1/D sdi_phy_rx_clk:[R] sdi_phy_rx_clk:[R] 0.000 0.000 0.300
4 0.275 SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/hd_check_phase_3_s1/Q SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/hd_check_phase_3_s1/D sdi_phy_rx_clk:[R] sdi_phy_rx_clk:[R] 0.000 0.000 0.300
5 0.275 SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/match_cnt_4_s1/Q SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/match_cnt_4_s1/D sdi_phy_rx_clk:[R] sdi_phy_rx_clk:[R] 0.000 0.000 0.300
6 0.275 SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/match_cnt_6_s1/Q SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/match_cnt_6_s1/D sdi_phy_rx_clk:[R] sdi_phy_rx_clk:[R] 0.000 0.000 0.300
7 0.275 SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/drp_cnt_1_s0/Q SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/drp_cnt_1_s0/D sclk:[R] sclk:[R] 0.000 0.000 0.300
8 0.275 SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/sd_time_cnt_0_s0/Q SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/sd_time_cnt_0_s0/D sclk:[R] sclk:[R] 0.000 0.000 0.300
9 0.275 SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/sd_time_cnt_3_s0/Q SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/sd_time_cnt_3_s0/D sclk:[R] sclk:[R] 0.000 0.000 0.300
10 0.275 SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/sd_time_cnt_8_s0/Q SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/sd_time_cnt_8_s0/D sclk:[R] sclk:[R] 0.000 0.000 0.300
11 0.275 SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/sd_time_cnt_13_s0/Q SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/sd_time_cnt_13_s0/D sclk:[R] sclk:[R] 0.000 0.000 0.300
12 0.275 SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/sd_time_cnt_31_s0/Q SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/sd_time_cnt_31_s0/D sclk:[R] sclk:[R] 0.000 0.000 0.300
13 0.275 SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/hd_time_cnt_6_s0/Q SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/hd_time_cnt_6_s0/D sclk:[R] sclk:[R] 0.000 0.000 0.300
14 0.275 I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/sda_chk_s3/Q I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/sda_chk_s3/D sclk:[R] sclk:[R] 0.000 0.000 0.300
15 0.275 I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_3_s1/Q I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_3_s1/D sclk:[R] sclk:[R] 0.000 0.000 0.300
16 0.275 I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_2_s1/Q I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_2_s1/D sclk:[R] sclk:[R] 0.000 0.000 0.300
17 0.275 I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_5_s1/Q I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_5_s1/D sclk:[R] sclk:[R] 0.000 0.000 0.300
18 0.275 I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_9_s1/Q I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_9_s1/D sclk:[R] sclk:[R] 0.000 0.000 0.300
19 0.275 I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_11_s1/Q I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_11_s1/D sclk:[R] sclk:[R] 0.000 0.000 0.300
20 0.275 I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_15_s1/Q I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_15_s1/D sclk:[R] sclk:[R] 0.000 0.000 0.300
21 0.275 I2C_MASTER_Top_inst0/u_i2c_master/byte_controller/CORE_CMD_3_s0/Q I2C_MASTER_Top_inst0/u_i2c_master/byte_controller/CORE_CMD_3_s0/D sclk:[R] sclk:[R] 0.000 0.000 0.300
22 0.275 adv7513_iic_init_inst0/mem_cnt_4_s3/Q adv7513_iic_init_inst0/mem_cnt_4_s3/D sclk:[R] sclk:[R] 0.000 0.000 0.300
23 0.275 adv7513_iic_init_inst0/O_RADDR_2_s2/Q adv7513_iic_init_inst0/O_RADDR_2_s2/D sclk:[R] sclk:[R] 0.000 0.000 0.300
24 0.275 adv7513_iic_init_inst0/O_WDATA_1_s1/Q adv7513_iic_init_inst0/O_WDATA_1_s1/D sclk:[R] sclk:[R] 0.000 0.000 0.300
25 0.275 adv7513_iic_init_inst0/O_WDATA_4_s1/Q adv7513_iic_init_inst0/O_WDATA_4_s1/D sclk:[R] sclk:[R] 0.000 0.000 0.300

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 11.743 SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_6_s0/CLEAR sdi_phy_tx_clk:[R] sdi_phy_tx_clk:[R] 13.468 0.000 1.377
2 11.743 SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_2_s0/CLEAR sdi_phy_tx_clk:[R] sdi_phy_tx_clk:[R] 13.468 0.000 1.377
3 11.743 SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_13_s0/CLEAR sdi_phy_tx_clk:[R] sdi_phy_tx_clk:[R] 13.468 0.000 1.377
4 11.743 SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_9_s0/CLEAR sdi_phy_tx_clk:[R] sdi_phy_tx_clk:[R] 13.468 0.000 1.377
5 11.743 SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_8_s0/CLEAR sdi_phy_tx_clk:[R] sdi_phy_tx_clk:[R] 13.468 0.000 1.377
6 11.743 SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_5_s0/CLEAR sdi_phy_tx_clk:[R] sdi_phy_tx_clk:[R] 13.468 0.000 1.377
7 11.743 SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_4_s0/CLEAR sdi_phy_tx_clk:[R] sdi_phy_tx_clk:[R] 13.468 0.000 1.377
8 11.743 SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_1_s0/CLEAR sdi_phy_tx_clk:[R] sdi_phy_tx_clk:[R] 13.468 0.000 1.377
9 11.769 SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_0_s0/CLEAR sdi_phy_tx_clk:[R] sdi_phy_tx_clk:[R] 13.468 0.000 1.351
10 11.769 SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_0_s0/CLEAR sdi_phy_tx_clk:[R] sdi_phy_tx_clk:[R] 13.468 0.000 1.351
11 11.779 SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_3_s0/CLEAR sdi_phy_tx_clk:[R] sdi_phy_tx_clk:[R] 13.468 -0.009 1.351
12 11.779 SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_17_s0/CLEAR sdi_phy_tx_clk:[R] sdi_phy_tx_clk:[R] 13.468 -0.009 1.351
13 11.779 SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/ready_r_s0/CLEAR sdi_phy_tx_clk:[R] sdi_phy_tx_clk:[R] 13.468 -0.009 1.351
14 11.779 SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_14_s0/CLEAR sdi_phy_tx_clk:[R] sdi_phy_tx_clk:[R] 13.468 -0.009 1.351
15 11.855 SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_12_s0/CLEAR sdi_phy_tx_clk:[R] sdi_phy_tx_clk:[R] 13.468 -0.009 1.275
16 11.855 SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_15_s0/CLEAR sdi_phy_tx_clk:[R] sdi_phy_tx_clk:[R] 13.468 -0.009 1.275
17 11.855 SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_16_s0/CLEAR sdi_phy_tx_clk:[R] sdi_phy_tx_clk:[R] 13.468 -0.009 1.275
18 11.953 SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_3_s0/CLEAR sdi_phy_tx_clk:[R] sdi_phy_tx_clk:[R] 13.468 0.000 1.168
19 11.953 SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_4_s0/CLEAR sdi_phy_tx_clk:[R] sdi_phy_tx_clk:[R] 13.468 0.000 1.168
20 11.953 SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_7_s0/CLEAR sdi_phy_tx_clk:[R] sdi_phy_tx_clk:[R] 13.468 0.000 1.168
21 11.953 SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_8_s0/CLEAR sdi_phy_tx_clk:[R] sdi_phy_tx_clk:[R] 13.468 0.000 1.168
22 11.953 SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_11_s0/CLEAR sdi_phy_tx_clk:[R] sdi_phy_tx_clk:[R] 13.468 0.000 1.168
23 11.953 SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_13_s0/CLEAR sdi_phy_tx_clk:[R] sdi_phy_tx_clk:[R] 13.468 0.000 1.168
24 11.953 SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_16_s0/CLEAR sdi_phy_tx_clk:[R] sdi_phy_tx_clk:[R] 13.468 0.000 1.168
25 11.985 SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_17_s0/CLEAR sdi_phy_tx_clk:[R] sdi_phy_tx_clk:[R] 13.468 0.009 1.126

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.493 SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_1_s0/CLEAR sdi_phy_tx_clk:[R] sdi_phy_tx_clk:[R] 0.000 0.000 0.440
2 0.493 SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_5_s0/CLEAR sdi_phy_tx_clk:[R] sdi_phy_tx_clk:[R] 0.000 0.000 0.440
3 0.493 SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_9_s0/CLEAR sdi_phy_tx_clk:[R] sdi_phy_tx_clk:[R] 0.000 0.000 0.440
4 0.602 SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_12_s0/CLEAR sdi_phy_tx_clk:[R] sdi_phy_tx_clk:[R] 0.000 0.004 0.545
5 0.602 SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_15_s0/CLEAR sdi_phy_tx_clk:[R] sdi_phy_tx_clk:[R] 0.000 0.004 0.545
6 0.604 SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_10_s0/CLEAR sdi_phy_tx_clk:[R] sdi_phy_tx_clk:[R] 0.000 0.000 0.551
7 0.604 SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_11_s0/CLEAR sdi_phy_tx_clk:[R] sdi_phy_tx_clk:[R] 0.000 0.000 0.551
8 0.604 SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_10_s0/CLEAR sdi_phy_tx_clk:[R] sdi_phy_tx_clk:[R] 0.000 0.000 0.551
9 0.604 SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_7_s0/CLEAR sdi_phy_tx_clk:[R] sdi_phy_tx_clk:[R] 0.000 0.000 0.551
10 0.604 SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_6_s0/CLEAR sdi_phy_tx_clk:[R] sdi_phy_tx_clk:[R] 0.000 0.000 0.551
11 0.604 SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_2_s0/CLEAR sdi_phy_tx_clk:[R] sdi_phy_tx_clk:[R] 0.000 0.000 0.551
12 0.619 SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_17_s0/CLEAR sdi_phy_tx_clk:[R] sdi_phy_tx_clk:[R] 0.000 0.004 0.562
13 0.619 SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_14_s0/CLEAR sdi_phy_tx_clk:[R] sdi_phy_tx_clk:[R] 0.000 0.004 0.562
14 0.623 SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_3_s0/CLEAR sdi_phy_tx_clk:[R] sdi_phy_tx_clk:[R] 0.000 0.000 0.570
15 0.623 SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_4_s0/CLEAR sdi_phy_tx_clk:[R] sdi_phy_tx_clk:[R] 0.000 0.000 0.570
16 0.623 SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_7_s0/CLEAR sdi_phy_tx_clk:[R] sdi_phy_tx_clk:[R] 0.000 0.000 0.570
17 0.623 SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_8_s0/CLEAR sdi_phy_tx_clk:[R] sdi_phy_tx_clk:[R] 0.000 0.000 0.570
18 0.623 SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_11_s0/CLEAR sdi_phy_tx_clk:[R] sdi_phy_tx_clk:[R] 0.000 0.000 0.570
19 0.623 SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_13_s0/CLEAR sdi_phy_tx_clk:[R] sdi_phy_tx_clk:[R] 0.000 0.000 0.570
20 0.623 SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_16_s0/CLEAR sdi_phy_tx_clk:[R] sdi_phy_tx_clk:[R] 0.000 0.000 0.570
21 0.694 SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_16_s0/CLEAR sdi_phy_tx_clk:[R] sdi_phy_tx_clk:[R] 0.000 -0.004 0.645
22 0.694 SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_15_s0/CLEAR sdi_phy_tx_clk:[R] sdi_phy_tx_clk:[R] 0.000 -0.004 0.645
23 0.694 SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_12_s0/CLEAR sdi_phy_tx_clk:[R] sdi_phy_tx_clk:[R] 0.000 -0.004 0.645
24 0.715 SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_3_s0/CLEAR sdi_phy_tx_clk:[R] sdi_phy_tx_clk:[R] 0.000 -0.004 0.666
25 0.715 SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_17_s0/CLEAR sdi_phy_tx_clk:[R] sdi_phy_tx_clk:[R] 0.000 -0.004 0.666

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number Slack Actual Width Required Width Type Clock Objects
1 4.250 4.500 0.250 Low Pulse Width sdi_phy_tx_clk testpattern_inst/H_cnt_10_s0
2 4.250 4.500 0.250 Low Pulse Width sdi_phy_tx_clk testpattern_inst/H_cnt_9_s0
3 4.250 4.500 0.250 Low Pulse Width sdi_phy_tx_clk testpattern_inst/H_cnt_7_s0
4 4.250 4.500 0.250 Low Pulse Width sdi_phy_tx_clk testpattern_inst/V_cnt_12_s1
5 4.250 4.500 0.250 Low Pulse Width sdi_phy_tx_clk testpattern_inst/De_vcnt_12_s1
6 4.250 4.500 0.250 Low Pulse Width sdi_phy_tx_clk testpattern_inst/De_hcnt_7_s3
7 4.250 4.500 0.250 Low Pulse Width sdi_phy_tx_clk testpattern_inst/De_hcnt_6_s3
8 4.250 4.500 0.250 Low Pulse Width sdi_phy_tx_clk testpattern_inst/De_hcnt_4_s3
9 4.250 4.500 0.250 Low Pulse Width sdi_phy_tx_clk testpattern_inst/De_hcnt_3_s3
10 4.250 4.500 0.250 Low Pulse Width sdi_phy_tx_clk testpattern_inst/De_vcnt_11_s1

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 4.822
Data Arrival Time 12.047
Data Required Time 16.869
From SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_12_s0
To SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_13_s0
Launch Clk sdi_phy_tx_clk:[R]
Latch Clk sdi_phy_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
3.456 3.456 tNET RR 1 R33C49[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_12_s0/CLK
3.838 0.382 tC2Q RR 12 R33C49[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_12_s0/Q
5.136 1.297 tNET RR 1 R31C39[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1906_s34/I3
5.597 0.461 tINS RR 8 R31C39[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1906_s34/F
5.957 0.360 tNET RR 1 R32C40[3][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1906_s19/I1
6.454 0.498 tINS RR 37 R32C40[3][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1906_s19/F
7.639 1.185 tNET RR 1 R30C35[3][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1911_s14/I3
8.137 0.498 tINS RR 16 R30C35[3][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1911_s14/F
9.639 1.502 tNET RR 1 R35C37[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1911_s20/I3
10.166 0.526 tINS RR 1 R35C37[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1911_s20/F
10.168 0.003 tNET RR 1 R35C37[2][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1911_s9/I1
10.684 0.516 tINS RR 1 R35C37[2][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1911_s9/F
10.842 0.157 tNET RR 1 R35C36[3][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1911_s2/I1
11.363 0.521 tINS RR 1 R35C36[3][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1911_s2/F
11.521 0.157 tNET RR 1 R34C36[0][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1911_s0/I1
12.047 0.526 tINS RR 1 R34C36[0][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1911_s0/F
12.047 0.000 tNET RR 1 R34C36[0][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_13_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 sdi_phy_tx_clk
13.468 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
16.933 3.465 tNET RR 1 R34C36[0][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_13_s0/CLK
16.869 -0.064 tSu 1 R34C36[0][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_13_s0

Path Statistics:

Clock Skew 0.009
Setup Relationship 13.468
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.456, 100.000%
Arrival Data Path Delay cell: 3.546, 41.277%; route: 4.662, 54.270%; tC2Q: 0.382, 4.452%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.465, 100.000%

Path2

Path Summary:

Slack 5.211
Data Arrival Time 10.048
Data Required Time 15.259
From SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/rx_data_d3_13_s0
To SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/hd_align_phase_4_s0
Launch Clk sdi_phy_rx_clk:[R]
Latch Clk sdi_phy_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_rx_clk
0.000 0.000 tCL RR 607 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_RX_O_FABRIC_CLK
2.102 2.102 tNET RR 1 R46C34[1][B] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/rx_data_d3_13_s0/CLK
2.484 0.382 tC2Q RR 6 R46C34[1][B] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/rx_data_d3_13_s0/Q
3.394 0.910 tNET RR 1 R41C36[3][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n1265_s58/I2
3.916 0.521 tINS RR 5 R41C36[3][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n1265_s58/F
4.786 0.870 tNET RR 1 R44C33[3][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n1112_s18/I2
5.283 0.498 tINS RR 4 R44C33[3][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n1112_s18/F
5.828 0.545 tNET RR 1 R42C34[2][B] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n1265_s44/I0
6.354 0.526 tINS RR 1 R42C34[2][B] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n1265_s44/F
6.512 0.157 tNET RR 1 R42C33[2][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n1265_s30/I0
7.028 0.516 tINS RR 3 R42C33[2][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n1265_s30/F
7.513 0.485 tNET RR 1 R43C35[3][B] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n1265_s24/I1
8.011 0.498 tINS RR 2 R43C35[3][B] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n1265_s24/F
8.861 0.850 tNET RR 1 R40C40[3][B] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/hd_align_phase_4_s5/I1
9.276 0.415 tINS RR 5 R40C40[3][B] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/hd_align_phase_4_s5/F
10.048 0.772 tNET RR 1 R40C36[2][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/hd_align_phase_4_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 sdi_phy_rx_clk
13.468 0.000 tCL RR 607 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_RX_O_FABRIC_CLK
15.570 2.102 tNET RR 1 R40C36[2][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/hd_align_phase_4_s0/CLK
15.259 -0.311 tSu 1 R40C36[2][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/hd_align_phase_4_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 13.468
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.102, 100.000%
Arrival Data Path Delay cell: 2.974, 37.423%; route: 4.590, 57.763%; tC2Q: 0.382, 4.814%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.102, 100.000%

Path3

Path Summary:

Slack 5.211
Data Arrival Time 10.048
Data Required Time 15.259
From SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/rx_data_d3_13_s0
To SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/hd_align_phase_3_s0
Launch Clk sdi_phy_rx_clk:[R]
Latch Clk sdi_phy_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_rx_clk
0.000 0.000 tCL RR 607 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_RX_O_FABRIC_CLK
2.102 2.102 tNET RR 1 R46C34[1][B] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/rx_data_d3_13_s0/CLK
2.484 0.382 tC2Q RR 6 R46C34[1][B] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/rx_data_d3_13_s0/Q
3.394 0.910 tNET RR 1 R41C36[3][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n1265_s58/I2
3.916 0.521 tINS RR 5 R41C36[3][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n1265_s58/F
4.786 0.870 tNET RR 1 R44C33[3][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n1112_s18/I2
5.283 0.498 tINS RR 4 R44C33[3][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n1112_s18/F
5.828 0.545 tNET RR 1 R42C34[2][B] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n1265_s44/I0
6.354 0.526 tINS RR 1 R42C34[2][B] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n1265_s44/F
6.512 0.157 tNET RR 1 R42C33[2][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n1265_s30/I0
7.028 0.516 tINS RR 3 R42C33[2][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n1265_s30/F
7.513 0.485 tNET RR 1 R43C35[3][B] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n1265_s24/I1
8.011 0.498 tINS RR 2 R43C35[3][B] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n1265_s24/F
8.861 0.850 tNET RR 1 R40C40[3][B] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/hd_align_phase_4_s5/I1
9.276 0.415 tINS RR 5 R40C40[3][B] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/hd_align_phase_4_s5/F
10.048 0.772 tNET RR 1 R39C36[3][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/hd_align_phase_3_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 sdi_phy_rx_clk
13.468 0.000 tCL RR 607 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_RX_O_FABRIC_CLK
15.570 2.102 tNET RR 1 R39C36[3][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/hd_align_phase_3_s0/CLK
15.259 -0.311 tSu 1 R39C36[3][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/hd_align_phase_3_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 13.468
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.102, 100.000%
Arrival Data Path Delay cell: 2.974, 37.423%; route: 4.590, 57.763%; tC2Q: 0.382, 4.814%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.102, 100.000%

Path4

Path Summary:

Slack 5.211
Data Arrival Time 10.048
Data Required Time 15.259
From SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/rx_data_d3_13_s0
To SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/hd_align_phase_2_s0
Launch Clk sdi_phy_rx_clk:[R]
Latch Clk sdi_phy_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_rx_clk
0.000 0.000 tCL RR 607 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_RX_O_FABRIC_CLK
2.102 2.102 tNET RR 1 R46C34[1][B] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/rx_data_d3_13_s0/CLK
2.484 0.382 tC2Q RR 6 R46C34[1][B] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/rx_data_d3_13_s0/Q
3.394 0.910 tNET RR 1 R41C36[3][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n1265_s58/I2
3.916 0.521 tINS RR 5 R41C36[3][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n1265_s58/F
4.786 0.870 tNET RR 1 R44C33[3][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n1112_s18/I2
5.283 0.498 tINS RR 4 R44C33[3][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n1112_s18/F
5.828 0.545 tNET RR 1 R42C34[2][B] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n1265_s44/I0
6.354 0.526 tINS RR 1 R42C34[2][B] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n1265_s44/F
6.512 0.157 tNET RR 1 R42C33[2][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n1265_s30/I0
7.028 0.516 tINS RR 3 R42C33[2][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n1265_s30/F
7.513 0.485 tNET RR 1 R43C35[3][B] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n1265_s24/I1
8.011 0.498 tINS RR 2 R43C35[3][B] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n1265_s24/F
8.861 0.850 tNET RR 1 R40C40[3][B] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/hd_align_phase_4_s5/I1
9.276 0.415 tINS RR 5 R40C40[3][B] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/hd_align_phase_4_s5/F
10.048 0.772 tNET RR 1 R40C36[2][B] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/hd_align_phase_2_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 sdi_phy_rx_clk
13.468 0.000 tCL RR 607 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_RX_O_FABRIC_CLK
15.570 2.102 tNET RR 1 R40C36[2][B] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/hd_align_phase_2_s0/CLK
15.259 -0.311 tSu 1 R40C36[2][B] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/hd_align_phase_2_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 13.468
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.102, 100.000%
Arrival Data Path Delay cell: 2.974, 37.423%; route: 4.590, 57.763%; tC2Q: 0.382, 4.814%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.102, 100.000%

Path5

Path Summary:

Slack 5.213
Data Arrival Time 10.046
Data Required Time 15.259
From SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/rx_data_d3_13_s0
To SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/hd_align_phase_0_s0
Launch Clk sdi_phy_rx_clk:[R]
Latch Clk sdi_phy_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_rx_clk
0.000 0.000 tCL RR 607 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_RX_O_FABRIC_CLK
2.102 2.102 tNET RR 1 R46C34[1][B] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/rx_data_d3_13_s0/CLK
2.484 0.382 tC2Q RR 6 R46C34[1][B] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/rx_data_d3_13_s0/Q
3.394 0.910 tNET RR 1 R41C36[3][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n1265_s58/I2
3.916 0.521 tINS RR 5 R41C36[3][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n1265_s58/F
4.786 0.870 tNET RR 1 R44C33[3][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n1112_s18/I2
5.283 0.498 tINS RR 4 R44C33[3][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n1112_s18/F
5.828 0.545 tNET RR 1 R42C34[2][B] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n1265_s44/I0
6.354 0.526 tINS RR 1 R42C34[2][B] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n1265_s44/F
6.512 0.157 tNET RR 1 R42C33[2][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n1265_s30/I0
7.028 0.516 tINS RR 3 R42C33[2][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n1265_s30/F
7.513 0.485 tNET RR 1 R43C35[3][B] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n1265_s24/I1
8.011 0.498 tINS RR 2 R43C35[3][B] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n1265_s24/F
8.861 0.850 tNET RR 1 R40C40[3][B] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/hd_align_phase_4_s5/I1
9.276 0.415 tINS RR 5 R40C40[3][B] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/hd_align_phase_4_s5/F
10.046 0.770 tNET RR 1 R43C36[2][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/hd_align_phase_0_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 sdi_phy_rx_clk
13.468 0.000 tCL RR 607 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_RX_O_FABRIC_CLK
15.570 2.102 tNET RR 1 R43C36[2][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/hd_align_phase_0_s0/CLK
15.259 -0.311 tSu 1 R43C36[2][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/hd_align_phase_0_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 13.468
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.102, 100.000%
Arrival Data Path Delay cell: 2.974, 37.435%; route: 4.587, 57.750%; tC2Q: 0.382, 4.815%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.102, 100.000%

Path6

Path Summary:

Slack 5.319
Data Arrival Time 11.541
Data Required Time 16.860
From SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_12_s0
To SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_15_s0
Launch Clk sdi_phy_tx_clk:[R]
Latch Clk sdi_phy_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
3.456 3.456 tNET RR 1 R33C49[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_12_s0/CLK
3.838 0.382 tC2Q RR 12 R33C49[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_12_s0/Q
5.136 1.297 tNET RR 1 R31C39[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1906_s34/I3
5.597 0.461 tINS RR 8 R31C39[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1906_s34/F
5.957 0.360 tNET RR 1 R32C40[3][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1906_s19/I1
6.454 0.498 tINS RR 37 R32C40[3][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1906_s19/F
7.634 1.180 tNET RR 1 R30C34[3][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1909_s16/I3
8.132 0.498 tINS RR 16 R30C34[3][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1909_s16/F
9.462 1.330 tNET RR 1 R36C32[3][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1909_s20/I2
9.983 0.521 tINS RR 1 R36C32[3][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1909_s20/F
10.141 0.157 tNET RR 1 R37C32[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1909_s6/I1
10.657 0.516 tINS RR 1 R37C32[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1909_s6/F
10.814 0.157 tNET RR 1 R37C33[0][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1909_s1/I2
11.276 0.461 tINS RR 1 R37C33[0][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1909_s1/F
11.278 0.003 tNET RR 1 R37C33[2][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1909_s0/I0
11.541 0.262 tINS RR 1 R37C33[2][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1909_s0/F
11.541 0.000 tNET RR 1 R37C33[2][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_15_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 sdi_phy_tx_clk
13.468 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
16.924 3.456 tNET RR 1 R37C33[2][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_15_s0/CLK
16.860 -0.064 tSu 1 R37C33[2][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_15_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 13.468
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.456, 100.000%
Arrival Data Path Delay cell: 3.218, 39.796%; route: 4.485, 55.473%; tC2Q: 0.382, 4.731%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.456, 100.000%

Path7

Path Summary:

Slack 5.403
Data Arrival Time 9.856
Data Required Time 15.259
From SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/rx_data_d3_13_s0
To SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/hd_align_phase_1_s0
Launch Clk sdi_phy_rx_clk:[R]
Latch Clk sdi_phy_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_rx_clk
0.000 0.000 tCL RR 607 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_RX_O_FABRIC_CLK
2.102 2.102 tNET RR 1 R46C34[1][B] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/rx_data_d3_13_s0/CLK
2.484 0.382 tC2Q RR 6 R46C34[1][B] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/rx_data_d3_13_s0/Q
3.394 0.910 tNET RR 1 R41C36[3][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n1265_s58/I2
3.916 0.521 tINS RR 5 R41C36[3][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n1265_s58/F
4.786 0.870 tNET RR 1 R44C33[3][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n1112_s18/I2
5.283 0.498 tINS RR 4 R44C33[3][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n1112_s18/F
5.828 0.545 tNET RR 1 R42C34[2][B] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n1265_s44/I0
6.354 0.526 tINS RR 1 R42C34[2][B] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n1265_s44/F
6.512 0.157 tNET RR 1 R42C33[2][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n1265_s30/I0
7.028 0.516 tINS RR 3 R42C33[2][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n1265_s30/F
7.513 0.485 tNET RR 1 R43C35[3][B] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n1265_s24/I1
8.011 0.498 tINS RR 2 R43C35[3][B] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n1265_s24/F
8.861 0.850 tNET RR 1 R40C40[3][B] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/hd_align_phase_4_s5/I1
9.276 0.415 tINS RR 5 R40C40[3][B] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/hd_align_phase_4_s5/F
9.856 0.580 tNET RR 1 R41C36[0][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/hd_align_phase_1_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 sdi_phy_rx_clk
13.468 0.000 tCL RR 607 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_RX_O_FABRIC_CLK
15.570 2.102 tNET RR 1 R41C36[0][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/hd_align_phase_1_s0/CLK
15.259 -0.311 tSu 1 R41C36[0][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/hd_align_phase_1_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 13.468
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.102, 100.000%
Arrival Data Path Delay cell: 2.974, 38.352%; route: 4.398, 56.714%; tC2Q: 0.382, 4.933%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.102, 100.000%

Path8

Path Summary:

Slack 5.432
Data Arrival Time 11.418
Data Required Time 16.851
From SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_12_s0
To SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_11_s0
Launch Clk sdi_phy_tx_clk:[R]
Latch Clk sdi_phy_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
3.456 3.456 tNET RR 1 R33C49[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_12_s0/CLK
3.838 0.382 tC2Q RR 12 R33C49[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_12_s0/Q
5.136 1.297 tNET RR 1 R31C39[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1906_s34/I3
5.597 0.461 tINS RR 8 R31C39[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1906_s34/F
5.957 0.360 tNET RR 1 R32C40[3][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1906_s19/I1
6.454 0.498 tINS RR 37 R32C40[3][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1906_s19/F
7.254 0.800 tNET RR 1 R31C37[3][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1905_s96/I0
7.776 0.521 tINS RR 38 R31C37[3][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1905_s96/F
8.176 0.400 tNET RR 1 R32C35[2][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1908_s14/I0
8.637 0.461 tINS RR 1 R32C35[2][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1908_s14/F
8.794 0.157 tNET RR 1 R33C35[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1908_s5/I1
9.311 0.516 tINS RR 6 R33C35[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1908_s5/F
10.492 1.181 tNET RR 1 R36C42[2][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1913_s4/I2
11.018 0.526 tINS RR 1 R36C42[2][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1913_s4/F
11.156 0.137 tNET RR 1 R36C42[0][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1913_s0/I3
11.418 0.262 tINS RR 1 R36C42[0][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1913_s0/F
11.418 0.000 tNET RR 1 R36C42[0][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_11_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 sdi_phy_tx_clk
13.468 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
16.914 3.446 tNET RR 1 R36C42[0][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_11_s0/CLK
16.851 -0.064 tSu 1 R36C42[0][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_11_s0

Path Statistics:

Clock Skew -0.009
Setup Relationship 13.468
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.456, 100.000%
Arrival Data Path Delay cell: 3.246, 40.769%; route: 4.334, 54.427%; tC2Q: 0.382, 4.804%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.446, 100.000%

Path9

Path Summary:

Slack 5.461
Data Arrival Time 11.399
Data Required Time 16.860
From SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_12_s0
To SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_18_s0
Launch Clk sdi_phy_tx_clk:[R]
Latch Clk sdi_phy_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
3.456 3.456 tNET RR 1 R33C49[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_12_s0/CLK
3.838 0.382 tC2Q RR 12 R33C49[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_12_s0/Q
5.136 1.297 tNET RR 1 R31C39[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1906_s34/I3
5.597 0.461 tINS RR 8 R31C39[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1906_s34/F
5.957 0.360 tNET RR 1 R32C40[3][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1906_s19/I1
6.454 0.498 tINS RR 37 R32C40[3][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1906_s19/F
7.254 0.800 tNET RR 1 R31C37[3][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1905_s96/I0
7.776 0.521 tINS RR 38 R31C37[3][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1905_s96/F
8.841 1.065 tNET RR 1 R36C37[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1905_s36/I2
9.302 0.461 tINS RR 3 R36C37[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1905_s36/F
9.654 0.352 tNET RR 1 R36C35[2][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1906_s5/I3
10.181 0.526 tINS RR 1 R36C35[2][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1906_s5/F
10.373 0.192 tNET RR 1 R36C33[3][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1906_s61/I0
10.871 0.498 tINS RR 1 R36C33[3][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1906_s61/F
10.873 0.003 tNET RR 1 R36C33[2][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1906_s0/I0
11.399 0.526 tINS RR 1 R36C33[2][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1906_s0/F
11.399 0.000 tNET RR 1 R36C33[2][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_18_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 sdi_phy_tx_clk
13.468 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
16.924 3.456 tNET RR 1 R36C33[2][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_18_s0/CLK
16.860 -0.064 tSu 1 R36C33[2][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_18_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 13.468
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.456, 100.000%
Arrival Data Path Delay cell: 3.491, 43.950%; route: 4.070, 51.235%; tC2Q: 0.382, 4.815%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.456, 100.000%

Path10

Path Summary:

Slack 5.514
Data Arrival Time 11.336
Data Required Time 16.851
From SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_1_s0
To SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_5_s0
Launch Clk sdi_phy_tx_clk:[R]
Latch Clk sdi_phy_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
3.446 3.446 tNET RR 1 R31C50[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_1_s0/CLK
3.814 0.368 tC2Q RF 54 R31C50[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_1_s0/Q
5.175 1.361 tNET FF 1 R32C39[2][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1908_s12/I1
5.691 0.516 tINS FR 7 R32C39[2][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1908_s12/F
6.051 0.360 tNET RR 1 R33C41[2][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1905_s88/I3
6.578 0.526 tINS RR 6 R33C41[2][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1905_s88/F
6.913 0.335 tNET RR 1 R31C41[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1906_s27/I3
7.175 0.262 tINS RR 1 R31C41[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1906_s27/F
7.313 0.137 tNET RR 1 R31C41[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1906_s11/I3
7.839 0.526 tINS RR 9 R31C41[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1906_s11/F
8.841 1.002 tNET RR 1 R35C38[3][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1909_s10/I0
9.339 0.498 tINS RR 8 R35C38[3][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1909_s10/F
10.286 0.947 tNET RR 1 R31C34[3][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1919_s2/I3
10.807 0.521 tINS RR 1 R31C34[3][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1919_s2/F
10.810 0.003 tNET RR 1 R31C34[0][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1919_s0/I1
11.336 0.526 tINS RR 1 R31C34[0][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1919_s0/F
11.336 0.000 tNET RR 1 R31C34[0][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_5_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 sdi_phy_tx_clk
13.468 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
16.914 3.446 tNET RR 1 R31C34[0][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_5_s0/CLK
16.851 -0.064 tSu 1 R31C34[0][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_5_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 13.468
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.446, 100.000%
Arrival Data Path Delay cell: 3.376, 42.792%; route: 4.146, 52.551%; tC2Q: 0.368, 4.658%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.446, 100.000%

Path11

Path Summary:

Slack 5.628
Data Arrival Time 11.232
Data Required Time 16.860
From SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_12_s0
To SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_0_s0
Launch Clk sdi_phy_tx_clk:[R]
Latch Clk sdi_phy_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
3.456 3.456 tNET RR 1 R33C49[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_12_s0/CLK
3.838 0.382 tC2Q RR 12 R33C49[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_12_s0/Q
5.136 1.297 tNET RR 1 R31C39[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1906_s34/I3
5.597 0.461 tINS RR 8 R31C39[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1906_s34/F
5.957 0.360 tNET RR 1 R32C40[3][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1906_s19/I1
6.454 0.498 tINS RR 37 R32C40[3][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1906_s19/F
7.254 0.800 tNET RR 1 R32C37[3][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1923_s14/I2
7.776 0.521 tINS RR 2 R32C37[3][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1923_s14/F
8.436 0.660 tNET RR 1 R32C42[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1923_s5/I0
8.897 0.461 tINS RR 2 R32C42[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1923_s5/F
9.247 0.350 tNET RR 1 R35C42[2][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1913_s19/I0
9.763 0.516 tINS RR 3 R35C42[2][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1913_s19/F
10.116 0.352 tNET RR 1 R36C41[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1924_s2/I1
10.642 0.526 tINS RR 1 R36C41[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1924_s2/F
10.969 0.327 tNET RR 1 R36C39[0][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1924_s0/I1
11.232 0.262 tINS RR 1 R36C39[0][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1924_s0/F
11.232 0.000 tNET RR 1 R36C39[0][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 sdi_phy_tx_clk
13.468 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
16.924 3.456 tNET RR 1 R36C39[0][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_0_s0/CLK
16.860 -0.064 tSu 1 R36C39[0][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_0_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 13.468
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.456, 100.000%
Arrival Data Path Delay cell: 3.246, 41.746%; route: 4.147, 53.335%; tC2Q: 0.382, 4.919%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.456, 100.000%

Path12

Path Summary:

Slack 5.650
Data Arrival Time 11.219
Data Required Time 16.869
From SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_12_s0
To SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_1_s0
Launch Clk sdi_phy_tx_clk:[R]
Latch Clk sdi_phy_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
3.456 3.456 tNET RR 1 R33C49[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_12_s0/CLK
3.838 0.382 tC2Q RR 12 R33C49[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_12_s0/Q
5.136 1.297 tNET RR 1 R31C39[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1906_s34/I3
5.597 0.461 tINS RR 8 R31C39[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1906_s34/F
5.957 0.360 tNET RR 1 R32C40[3][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1906_s19/I1
6.454 0.498 tINS RR 37 R32C40[3][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1906_s19/F
7.254 0.800 tNET RR 1 R32C37[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1924_s9/I2
7.781 0.526 tINS RR 13 R32C37[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1924_s9/F
8.938 1.157 tNET RR 1 R34C42[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1913_s14/I2
9.399 0.461 tINS RR 2 R34C42[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1913_s14/F
9.729 0.330 tNET RR 1 R34C44[2][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1923_s8/I0
10.256 0.526 tINS RR 1 R34C44[2][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1923_s8/F
10.258 0.003 tNET RR 1 R34C44[3][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1923_s13/I2
10.756 0.498 tINS RR 1 R34C44[3][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1923_s13/F
10.758 0.003 tNET RR 1 R34C44[0][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1923_s0/I3
11.219 0.461 tINS RR 1 R34C44[0][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1923_s0/F
11.219 0.000 tNET RR 1 R34C44[0][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 sdi_phy_tx_clk
13.468 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
16.933 3.465 tNET RR 1 R34C44[0][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_1_s0/CLK
16.869 -0.064 tSu 1 R34C44[0][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_1_s0

Path Statistics:

Clock Skew 0.009
Setup Relationship 13.468
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.456, 100.000%
Arrival Data Path Delay cell: 3.431, 44.196%; route: 3.950, 50.877%; tC2Q: 0.382, 4.927%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.465, 100.000%

Path13

Path Summary:

Slack 5.677
Data Arrival Time 11.183
Data Required Time 16.860
From SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_12_s0
To SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_12_s0
Launch Clk sdi_phy_tx_clk:[R]
Latch Clk sdi_phy_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
3.456 3.456 tNET RR 1 R33C49[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_12_s0/CLK
3.838 0.382 tC2Q RR 12 R33C49[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_12_s0/Q
5.136 1.297 tNET RR 1 R31C39[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1906_s34/I3
5.597 0.461 tINS RR 8 R31C39[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1906_s34/F
5.957 0.360 tNET RR 1 R32C40[3][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1906_s19/I1
6.454 0.498 tINS RR 37 R32C40[3][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1906_s19/F
7.254 0.800 tNET RR 1 R32C37[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1924_s9/I2
7.781 0.526 tINS RR 13 R32C37[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1924_s9/F
9.073 1.292 tNET RR 1 R35C42[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1912_s21/I1
9.599 0.526 tINS RR 1 R35C42[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1912_s21/F
9.757 0.157 tNET RR 1 R35C41[2][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1912_s11/I0
10.019 0.262 tINS RR 1 R35C41[2][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1912_s11/F
10.022 0.003 tNET RR 1 R35C41[3][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1912_s3/I2
10.519 0.498 tINS RR 1 R35C41[3][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1912_s3/F
10.657 0.137 tNET RR 1 R35C41[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1912_s0/I3
11.183 0.526 tINS RR 1 R35C41[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1912_s0/F
11.183 0.000 tNET RR 1 R35C41[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_12_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 sdi_phy_tx_clk
13.468 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
16.924 3.456 tNET RR 1 R35C41[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_12_s0/CLK
16.860 -0.064 tSu 1 R35C41[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_12_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 13.468
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.456, 100.000%
Arrival Data Path Delay cell: 3.298, 42.672%; route: 4.048, 52.378%; tC2Q: 0.382, 4.950%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.456, 100.000%

Path14

Path Summary:

Slack 5.690
Data Arrival Time 11.179
Data Required Time 16.869
From SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0
To SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_10_s0
Launch Clk sdi_phy_tx_clk:[R]
Latch Clk sdi_phy_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
3.456 3.456 tNET RR 1 R33C49[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0/CLK
3.838 0.382 tC2Q RR 7 R33C49[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0/Q
4.461 0.623 tNET RR 1 R33C43[2][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1906_s26/I1
4.977 0.516 tINS RR 12 R33C43[2][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1906_s26/F
5.529 0.553 tNET RR 1 R31C41[2][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1905_s26/I0
6.056 0.526 tINS RR 36 R31C41[2][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1905_s26/F
6.751 0.695 tNET RR 1 R30C38[3][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1905_s60/I1
7.272 0.521 tINS RR 5 R30C38[3][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1905_s60/F
8.548 1.276 tNET RR 1 R33C41[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1905_s34/I1
9.009 0.461 tINS RR 3 R33C41[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1905_s34/F
9.014 0.005 tNET RR 1 R33C41[3][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1914_s5/I1
9.536 0.521 tINS RR 2 R33C41[3][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1914_s5/F
10.301 0.765 tNET RR 1 R36C44[3][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1914_s1/I1
10.716 0.415 tINS RR 1 R36C44[3][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1914_s1/F
10.718 0.003 tNET RR 1 R36C44[0][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1914_s0/I0
11.179 0.461 tINS RR 1 R36C44[0][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1914_s0/F
11.179 0.000 tNET RR 1 R36C44[0][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_10_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 sdi_phy_tx_clk
13.468 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
16.933 3.465 tNET RR 1 R36C44[0][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_10_s0/CLK
16.869 -0.064 tSu 1 R36C44[0][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_10_s0

Path Statistics:

Clock Skew 0.009
Setup Relationship 13.468
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.456, 100.000%
Arrival Data Path Delay cell: 3.423, 44.311%; route: 3.919, 50.736%; tC2Q: 0.382, 4.952%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.465, 100.000%

Path15

Path Summary:

Slack 5.719
Data Arrival Time 9.787
Data Required Time 15.506
From SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/rx_data_d3_13_s0
To SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/hd_match_flag_s0
Launch Clk sdi_phy_rx_clk:[R]
Latch Clk sdi_phy_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_rx_clk
0.000 0.000 tCL RR 607 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_RX_O_FABRIC_CLK
2.102 2.102 tNET RR 1 R46C34[1][B] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/rx_data_d3_13_s0/CLK
2.484 0.382 tC2Q RR 6 R46C34[1][B] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/rx_data_d3_13_s0/Q
3.394 0.910 tNET RR 1 R41C36[3][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n1265_s58/I2
3.916 0.521 tINS RR 5 R41C36[3][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n1265_s58/F
4.786 0.870 tNET RR 1 R44C33[3][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n1112_s18/I2
5.283 0.498 tINS RR 4 R44C33[3][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n1112_s18/F
5.828 0.545 tNET RR 1 R42C34[2][B] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n1265_s44/I0
6.354 0.526 tINS RR 1 R42C34[2][B] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n1265_s44/F
6.512 0.157 tNET RR 1 R42C33[2][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n1265_s30/I0
7.028 0.516 tINS RR 3 R42C33[2][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n1265_s30/F
7.513 0.485 tNET RR 1 R43C35[3][B] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n1265_s24/I1
8.011 0.498 tINS RR 2 R43C35[3][B] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n1265_s24/F
9.271 1.260 tNET RR 1 R39C40[0][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n1265_s22/I1
9.787 0.516 tINS RR 1 R39C40[0][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n1265_s22/F
9.787 0.000 tNET RR 1 R39C40[0][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/hd_match_flag_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 sdi_phy_rx_clk
13.468 0.000 tCL RR 607 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_RX_O_FABRIC_CLK
15.570 2.102 tNET RR 1 R39C40[0][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/hd_match_flag_s0/CLK
15.506 -0.064 tSu 1 R39C40[0][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/hd_match_flag_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 13.468
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.102, 100.000%
Arrival Data Path Delay cell: 3.075, 40.013%; route: 4.227, 55.010%; tC2Q: 0.382, 4.977%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.102, 100.000%

Path16

Path Summary:

Slack 5.731
Data Arrival Time 11.138
Data Required Time 16.869
From SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_12_s0
To SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_14_s0
Launch Clk sdi_phy_tx_clk:[R]
Latch Clk sdi_phy_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
3.456 3.456 tNET RR 1 R33C49[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_12_s0/CLK
3.838 0.382 tC2Q RR 12 R33C49[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_12_s0/Q
5.136 1.297 tNET RR 1 R31C39[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1906_s34/I3
5.597 0.461 tINS RR 8 R31C39[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1906_s34/F
5.957 0.360 tNET RR 1 R32C40[3][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1906_s19/I1
6.454 0.498 tINS RR 37 R32C40[3][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1906_s19/F
7.254 0.800 tNET RR 1 R31C37[3][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1905_s96/I0
7.776 0.521 tINS RR 38 R31C37[3][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1905_s96/F
8.841 1.065 tNET RR 1 R35C34[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1910_s20/I1
9.302 0.461 tINS RR 1 R35C34[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1910_s20/F
9.304 0.003 tNET RR 1 R35C34[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1910_s9/I1
9.821 0.516 tINS RR 1 R35C34[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1910_s9/F
10.148 0.327 tNET RR 1 R35C32[2][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1910_s2/I1
10.674 0.526 tINS RR 1 R35C32[2][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1910_s2/F
10.677 0.003 tNET RR 1 R35C32[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1910_s0/I1
11.138 0.461 tINS RR 1 R35C32[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1910_s0/F
11.138 0.000 tNET RR 1 R35C32[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_14_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 sdi_phy_tx_clk
13.468 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
16.933 3.465 tNET RR 1 R35C32[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_14_s0/CLK
16.869 -0.064 tSu 1 R35C32[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_14_s0

Path Statistics:

Clock Skew 0.009
Setup Relationship 13.468
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.456, 100.000%
Arrival Data Path Delay cell: 3.445, 44.842%; route: 3.855, 50.179%; tC2Q: 0.382, 4.979%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.465, 100.000%

Path17

Path Summary:

Slack 5.758
Data Arrival Time 11.102
Data Required Time 16.860
From SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_12_s0
To SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_7_s0
Launch Clk sdi_phy_tx_clk:[R]
Latch Clk sdi_phy_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
3.456 3.456 tNET RR 1 R33C49[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_12_s0/CLK
3.838 0.382 tC2Q RR 12 R33C49[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_12_s0/Q
5.136 1.297 tNET RR 1 R31C39[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1906_s34/I3
5.597 0.461 tINS RR 8 R31C39[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1906_s34/F
5.957 0.360 tNET RR 1 R32C40[3][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1906_s19/I1
6.454 0.498 tINS RR 37 R32C40[3][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1906_s19/F
7.447 0.992 tNET RR 1 R30C37[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1907_s26/I2
7.973 0.526 tINS RR 3 R30C37[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1907_s26/F
8.741 0.767 tNET RR 1 R32C32[2][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1917_s16/I2
9.267 0.526 tINS RR 1 R32C32[2][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1917_s16/F
9.424 0.157 tNET RR 1 R32C33[3][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1917_s9/I1
9.839 0.415 tINS RR 1 R32C33[3][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1917_s9/F
10.032 0.192 tNET RR 1 R32C31[3][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1917_s3/I3
10.529 0.498 tINS RR 1 R32C31[3][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1917_s3/F
10.687 0.157 tNET RR 1 R31C31[3][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1917_s0/I3
11.102 0.415 tINS RR 1 R31C31[3][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1917_s0/F
11.102 0.000 tNET RR 1 R31C31[3][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_7_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 sdi_phy_tx_clk
13.468 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
16.924 3.456 tNET RR 1 R31C31[3][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_7_s0/CLK
16.860 -0.064 tSu 1 R31C31[3][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_7_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 13.468
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.456, 100.000%
Arrival Data Path Delay cell: 3.339, 43.665%; route: 3.925, 51.332%; tC2Q: 0.382, 5.002%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.456, 100.000%

Path18

Path Summary:

Slack 5.762
Data Arrival Time 11.097
Data Required Time 16.860
From SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_1_s0
To SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_3_s0
Launch Clk sdi_phy_tx_clk:[R]
Latch Clk sdi_phy_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
3.446 3.446 tNET RR 1 R31C50[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_1_s0/CLK
3.814 0.368 tC2Q RF 54 R31C50[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_1_s0/Q
5.175 1.361 tNET FF 1 R32C39[2][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1908_s12/I1
5.691 0.516 tINS FR 7 R32C39[2][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1908_s12/F
6.051 0.360 tNET RR 1 R33C41[2][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1905_s88/I3
6.578 0.526 tINS RR 6 R33C41[2][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1905_s88/F
6.913 0.335 tNET RR 1 R31C41[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1906_s27/I3
7.175 0.262 tINS RR 1 R31C41[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1906_s27/F
7.313 0.137 tNET RR 1 R31C41[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1906_s11/I3
7.839 0.526 tINS RR 9 R31C41[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1906_s11/F
8.841 1.002 tNET RR 1 R35C38[3][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1909_s10/I0
9.339 0.498 tINS RR 8 R35C38[3][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1909_s10/F
10.151 0.812 tNET RR 1 R33C33[2][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1921_s2/I3
10.414 0.262 tINS RR 1 R33C33[2][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1921_s2/F
10.571 0.157 tNET RR 1 R32C33[0][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1921_s0/I1
11.097 0.526 tINS RR 1 R32C33[0][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1921_s0/F
11.097 0.000 tNET RR 1 R32C33[0][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_3_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 sdi_phy_tx_clk
13.468 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
16.924 3.456 tNET RR 1 R32C33[0][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_3_s0/CLK
16.860 -0.064 tSu 1 R32C33[0][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_3_s0

Path Statistics:

Clock Skew 0.009
Setup Relationship 13.468
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.446, 100.000%
Arrival Data Path Delay cell: 3.118, 40.745%; route: 4.166, 54.452%; tC2Q: 0.368, 4.803%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.456, 100.000%

Path19

Path Summary:

Slack 5.763
Data Arrival Time 11.097
Data Required Time 16.860
From SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0
To SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_6_s0
Launch Clk sdi_phy_tx_clk:[R]
Latch Clk sdi_phy_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
3.456 3.456 tNET RR 1 R33C49[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0/CLK
3.838 0.382 tC2Q RR 7 R33C49[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0/Q
4.461 0.623 tNET RR 1 R33C43[2][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1906_s26/I1
4.977 0.516 tINS RR 12 R33C43[2][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1906_s26/F
5.529 0.553 tNET RR 1 R31C41[2][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1905_s26/I0
6.056 0.526 tINS RR 36 R31C41[2][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1905_s26/F
6.751 0.695 tNET RR 1 R30C38[3][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1905_s60/I1
7.272 0.521 tINS RR 5 R30C38[3][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1905_s60/F
8.548 1.276 tNET RR 1 R33C41[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1905_s34/I1
9.009 0.461 tINS RR 3 R33C41[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1905_s34/F
9.397 0.387 tNET RR 1 R35C39[2][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1918_s10/I0
9.923 0.526 tINS RR 1 R35C39[2][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1918_s10/F
9.926 0.003 tNET RR 1 R35C39[3][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1918_s3/I3
10.423 0.498 tINS RR 1 R35C39[3][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1918_s3/F
10.581 0.157 tNET RR 1 R34C39[0][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1918_s0/I2
11.097 0.516 tINS RR 1 R34C39[0][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1918_s0/F
11.097 0.000 tNET RR 1 R34C39[0][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_6_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 sdi_phy_tx_clk
13.468 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
16.924 3.456 tNET RR 1 R34C39[0][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_6_s0/CLK
16.860 -0.064 tSu 1 R34C39[0][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_6_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 13.468
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.456, 100.000%
Arrival Data Path Delay cell: 3.565, 46.655%; route: 3.694, 48.340%; tC2Q: 0.382, 5.006%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.456, 100.000%

Path20

Path Summary:

Slack 5.774
Data Arrival Time 11.086
Data Required Time 16.860
From SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0
To SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_16_s0
Launch Clk sdi_phy_tx_clk:[R]
Latch Clk sdi_phy_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
3.456 3.456 tNET RR 1 R33C49[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0/CLK
3.838 0.382 tC2Q RR 7 R33C49[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0/Q
4.461 0.623 tNET RR 1 R33C43[2][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1906_s26/I1
4.977 0.516 tINS RR 12 R33C43[2][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1906_s26/F
5.529 0.553 tNET RR 1 R31C41[2][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1905_s26/I0
6.056 0.526 tINS RR 36 R31C41[2][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1905_s26/F
6.751 0.695 tNET RR 1 R30C38[3][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1905_s60/I1
7.272 0.521 tINS RR 5 R30C38[3][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1905_s60/F
8.548 1.276 tNET RR 1 R33C41[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1905_s34/I1
9.009 0.461 tINS RR 3 R33C41[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1905_s34/F
9.397 0.387 tNET RR 1 R34C39[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1908_s9/I2
9.913 0.516 tINS RR 1 R34C39[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1908_s9/F
9.916 0.003 tNET RR 1 R34C39[2][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1908_s2/I2
10.432 0.516 tINS RR 1 R34C39[2][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1908_s2/F
10.569 0.137 tNET RR 1 R34C39[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1908_s0/I1
11.086 0.516 tINS RR 1 R34C39[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1908_s0/F
11.086 0.000 tNET RR 1 R34C39[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_16_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 sdi_phy_tx_clk
13.468 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
16.924 3.456 tNET RR 1 R34C39[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_16_s0/CLK
16.860 -0.064 tSu 1 R34C39[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_16_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 13.468
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.456, 100.000%
Arrival Data Path Delay cell: 3.574, 46.838%; route: 3.674, 48.149%; tC2Q: 0.382, 5.013%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.456, 100.000%

Path21

Path Summary:

Slack 5.825
Data Arrival Time 11.044
Data Required Time 16.869
From SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_12_s0
To SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_19_s0
Launch Clk sdi_phy_tx_clk:[R]
Latch Clk sdi_phy_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
3.456 3.456 tNET RR 1 R33C49[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_12_s0/CLK
3.838 0.382 tC2Q RR 12 R33C49[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_12_s0/Q
5.136 1.297 tNET RR 1 R31C39[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1906_s34/I3
5.597 0.461 tINS RR 8 R31C39[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1906_s34/F
5.957 0.360 tNET RR 1 R32C40[3][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1906_s19/I1
6.454 0.498 tINS RR 37 R32C40[3][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1906_s19/F
7.254 0.800 tNET RR 1 R31C37[3][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1905_s96/I0
7.776 0.521 tINS RR 38 R31C37[3][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1905_s96/F
8.841 1.065 tNET RR 1 R36C37[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1905_s36/I2
9.302 0.461 tINS RR 3 R36C37[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1905_s36/F
9.464 0.162 tNET RR 1 R36C36[2][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1905_s13/I2
9.991 0.526 tINS RR 1 R36C36[2][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1905_s13/F
10.318 0.327 tNET RR 1 R34C36[2][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1905_s3/I0
10.581 0.262 tINS RR 1 R34C36[2][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1905_s3/F
10.583 0.003 tNET RR 1 R34C36[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1905_s0/I2
11.044 0.461 tINS RR 1 R34C36[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1905_s0/F
11.044 0.000 tNET RR 1 R34C36[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_19_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 sdi_phy_tx_clk
13.468 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
16.933 3.465 tNET RR 1 R34C36[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_19_s0/CLK
16.869 -0.064 tSu 1 R34C36[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_19_s0

Path Statistics:

Clock Skew 0.009
Setup Relationship 13.468
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.456, 100.000%
Arrival Data Path Delay cell: 3.191, 42.052%; route: 4.015, 52.907%; tC2Q: 0.382, 5.040%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.465, 100.000%

Path22

Path Summary:

Slack 5.837
Data Arrival Time 11.013
Data Required Time 16.851
From SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_12_s0
To SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_2_s0
Launch Clk sdi_phy_tx_clk:[R]
Latch Clk sdi_phy_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
3.456 3.456 tNET RR 1 R33C49[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_12_s0/CLK
3.838 0.382 tC2Q RR 12 R33C49[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_12_s0/Q
5.136 1.297 tNET RR 1 R31C39[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1906_s34/I3
5.597 0.461 tINS RR 8 R31C39[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1906_s34/F
5.957 0.360 tNET RR 1 R32C40[3][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1906_s19/I1
6.454 0.498 tINS RR 37 R32C40[3][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1906_s19/F
6.787 0.332 tNET RR 1 R32C42[0][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1905_s22/I2
7.303 0.516 tINS RR 14 R32C42[0][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1905_s22/F
8.603 1.300 tNET RR 1 R33C37[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1922_s18/I1
9.064 0.461 tINS RR 1 R33C37[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1922_s18/F
9.067 0.003 tNET RR 1 R33C37[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1922_s11/I0
9.583 0.516 tINS RR 1 R33C37[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1922_s11/F
9.586 0.003 tNET RR 1 R33C37[2][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1922_s3/I3
10.102 0.516 tINS RR 1 R33C37[2][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1922_s3/F
10.487 0.385 tNET RR 1 R32C38[0][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1922_s0/I3
11.013 0.526 tINS RR 1 R32C38[0][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1922_s0/F
11.013 0.000 tNET RR 1 R32C38[0][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 sdi_phy_tx_clk
13.468 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
16.914 3.446 tNET RR 1 R32C38[0][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_2_s0/CLK
16.851 -0.064 tSu 1 R32C38[0][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_2_s0

Path Statistics:

Clock Skew -0.009
Setup Relationship 13.468
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.456, 100.000%
Arrival Data Path Delay cell: 3.495, 46.245%; route: 3.680, 48.693%; tC2Q: 0.382, 5.061%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.446, 100.000%

Path23

Path Summary:

Slack 5.907
Data Arrival Time 10.953
Data Required Time 16.860
From SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_12_s0
To SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_8_s0
Launch Clk sdi_phy_tx_clk:[R]
Latch Clk sdi_phy_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
3.456 3.456 tNET RR 1 R33C49[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_12_s0/CLK
3.838 0.382 tC2Q RR 12 R33C49[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_12_s0/Q
5.136 1.297 tNET RR 1 R31C39[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1906_s34/I3
5.597 0.461 tINS RR 8 R31C39[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1906_s34/F
5.957 0.360 tNET RR 1 R32C40[3][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1906_s19/I1
6.454 0.498 tINS RR 37 R32C40[3][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1906_s19/F
8.022 1.567 tNET RR 1 R34C35[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1916_s26/I0
8.538 0.516 tINS RR 2 R34C35[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1916_s26/F
8.698 0.160 tNET RR 1 R33C35[3][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1916_s14/I0
9.196 0.498 tINS RR 1 R33C35[3][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1916_s14/F
9.198 0.003 tNET RR 1 R33C35[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1916_s5/I0
9.724 0.526 tINS RR 2 R33C35[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1916_s5/F
10.074 0.350 tNET RR 1 R34C33[3][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1916_s1/I0
10.489 0.415 tINS RR 1 R34C33[3][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1916_s1/F
10.492 0.003 tNET RR 1 R34C33[0][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1916_s0/I0
10.953 0.461 tINS RR 1 R34C33[0][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1916_s0/F
10.953 0.000 tNET RR 1 R34C33[0][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_8_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 sdi_phy_tx_clk
13.468 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
16.924 3.456 tNET RR 1 R34C33[0][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_8_s0/CLK
16.860 -0.064 tSu 1 R34C33[0][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_8_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 13.468
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.456, 100.000%
Arrival Data Path Delay cell: 3.375, 45.015%; route: 3.740, 49.883%; tC2Q: 0.382, 5.102%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.456, 100.000%

Path24

Path Summary:

Slack 5.947
Data Arrival Time 10.922
Data Required Time 16.869
From SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_1_s0
To SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_4_s0
Launch Clk sdi_phy_tx_clk:[R]
Latch Clk sdi_phy_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
3.446 3.446 tNET RR 1 R31C50[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_1_s0/CLK
3.814 0.368 tC2Q RF 54 R31C50[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_1_s0/Q
5.175 1.361 tNET FF 1 R32C39[2][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1908_s12/I1
5.691 0.516 tINS FR 7 R32C39[2][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1908_s12/F
6.051 0.360 tNET RR 1 R33C41[2][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1905_s88/I3
6.578 0.526 tINS RR 6 R33C41[2][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1905_s88/F
6.968 0.390 tNET RR 1 R31C42[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1905_s7/I0
7.494 0.526 tINS RR 10 R31C42[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1905_s7/F
8.034 0.540 tNET RR 1 R31C38[3][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1909_s29/I0
8.449 0.415 tINS RR 8 R31C38[3][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1909_s29/F
9.204 0.755 tNET RR 1 R32C35[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1920_s11/I2
9.720 0.516 tINS RR 1 R32C35[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1920_s11/F
9.878 0.157 tNET RR 1 R32C36[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1920_s3/I3
10.404 0.526 tINS RR 1 R32C36[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1920_s3/F
10.406 0.003 tNET RR 1 R32C36[2][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1920_s0/I3
10.922 0.516 tINS RR 1 R32C36[2][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1920_s0/F
10.922 0.000 tNET RR 1 R32C36[2][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_4_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 sdi_phy_tx_clk
13.468 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
16.933 3.465 tNET RR 1 R32C36[2][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_4_s0/CLK
16.869 -0.064 tSu 1 R32C36[2][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_4_s0

Path Statistics:

Clock Skew 0.019
Setup Relationship 13.468
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.446, 100.000%
Arrival Data Path Delay cell: 3.543, 47.383%; route: 3.566, 47.701%; tC2Q: 0.368, 4.916%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.465, 100.000%

Path25

Path Summary:

Slack 5.950
Data Arrival Time 10.910
Data Required Time 16.860
From SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_1_s0
To SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_17_s0
Launch Clk sdi_phy_tx_clk:[R]
Latch Clk sdi_phy_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
3.446 3.446 tNET RR 1 R31C50[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_1_s0/CLK
3.814 0.368 tC2Q RF 54 R31C50[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_1_s0/Q
5.175 1.361 tNET FF 1 R32C39[2][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1908_s12/I1
5.691 0.516 tINS FR 7 R32C39[2][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1908_s12/F
6.051 0.360 tNET RR 1 R33C41[2][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1905_s88/I3
6.578 0.526 tINS RR 6 R33C41[2][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1905_s88/F
6.933 0.355 tNET RR 1 R32C40[0][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1916_s10/I3
7.394 0.461 tINS RR 18 R32C40[0][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1916_s10/F
8.734 1.340 tNET RR 1 R32C33[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1907_s31/I2
9.260 0.526 tINS RR 2 R32C33[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1907_s31/F
9.455 0.195 tNET RR 1 R32C31[2][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1907_s15/I2
9.717 0.262 tINS RR 1 R32C31[2][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1907_s15/F
9.855 0.137 tNET RR 1 R32C31[2][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1907_s4/I3
10.381 0.526 tINS RR 1 R32C31[2][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1907_s4/F
10.384 0.003 tNET RR 1 R32C31[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1907_s0/I3
10.910 0.526 tINS RR 1 R32C31[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1907_s0/F
10.910 0.000 tNET RR 1 R32C31[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_17_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 sdi_phy_tx_clk
13.468 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
16.924 3.456 tNET RR 1 R32C31[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_17_s0/CLK
16.860 -0.064 tSu 1 R32C31[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_17_s0

Path Statistics:

Clock Skew 0.009
Setup Relationship 13.468
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.446, 100.000%
Arrival Data Path Delay cell: 3.345, 44.817%; route: 3.751, 50.260%; tC2Q: 0.368, 4.924%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.456, 100.000%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 0.193
Data Arrival Time 1.469
Data Required Time 1.276
From SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/I_data_d1_0_s2
To SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/I_data_d1_0_s14
Launch Clk sdi_phy_tx_clk:[R]
Latch Clk sdi_phy_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
1.226 1.226 tNET RR 1 R31C47[0][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/I_data_d1_0_s2/CLK
1.370 0.144 tC2Q RR 13 R31C47[0][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/I_data_d1_0_s2/Q
1.469 0.099 tNET RR 1 R30C47 SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/I_data_d1_0_s14/AD[0]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
1.226 1.226 tNET RR 1 R30C47 SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/I_data_d1_0_s14/CLK
1.276 0.050 tHld 1 R30C47 SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/I_data_d1_0_s14

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.226, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.099, 40.741%; tC2Q: 0.144, 59.259%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.226, 100.000%

Path2

Path Summary:

Slack 0.275
Data Arrival Time 0.972
Data Required Time 0.697
From SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_data_extract_inst/dot_cnt_2_s0
To SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_data_extract_inst/dot_cnt_2_s0
Launch Clk sdi_phy_rx_clk:[R]
Latch Clk sdi_phy_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_rx_clk
0.000 0.000 tCL RR 607 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_RX_O_FABRIC_CLK
0.672 0.672 tNET RR 1 R40C49[0][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_data_extract_inst/dot_cnt_2_s0/CLK
0.813 0.141 tC2Q RF 5 R40C49[0][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_data_extract_inst/dot_cnt_2_s0/Q
0.819 0.006 tNET FF 1 R40C49[0][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_data_extract_inst/n247_s2/I3
0.972 0.153 tINS FF 1 R40C49[0][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_data_extract_inst/n247_s2/F
0.972 0.000 tNET FF 1 R40C49[0][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_data_extract_inst/dot_cnt_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_rx_clk
0.000 0.000 tCL RR 607 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_RX_O_FABRIC_CLK
0.672 0.672 tNET RR 1 R40C49[0][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_data_extract_inst/dot_cnt_2_s0/CLK
0.697 0.025 tHld 1 R40C49[0][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_hd_data_extract_inst/dot_cnt_2_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.672, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.672, 100.000%

Path3

Path Summary:

Slack 0.275
Data Arrival Time 0.980
Data Required Time 0.705
From SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/hd_check_phase_0_s1
To SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/hd_check_phase_0_s1
Launch Clk sdi_phy_rx_clk:[R]
Latch Clk sdi_phy_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_rx_clk
0.000 0.000 tCL RR 607 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_RX_O_FABRIC_CLK
0.680 0.680 tNET RR 1 R39C39[0][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/hd_check_phase_0_s1/CLK
0.821 0.141 tC2Q RF 2 R39C39[0][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/hd_check_phase_0_s1/Q
0.827 0.006 tNET FF 1 R39C39[0][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n1283_s21/I2
0.980 0.153 tINS FF 1 R39C39[0][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n1283_s21/F
0.980 0.000 tNET FF 1 R39C39[0][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/hd_check_phase_0_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_rx_clk
0.000 0.000 tCL RR 607 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_RX_O_FABRIC_CLK
0.680 0.680 tNET RR 1 R39C39[0][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/hd_check_phase_0_s1/CLK
0.705 0.025 tHld 1 R39C39[0][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/hd_check_phase_0_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.680, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.680, 100.000%

Path4

Path Summary:

Slack 0.275
Data Arrival Time 0.972
Data Required Time 0.697
From SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/hd_check_phase_3_s1
To SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/hd_check_phase_3_s1
Launch Clk sdi_phy_rx_clk:[R]
Latch Clk sdi_phy_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_rx_clk
0.000 0.000 tCL RR 607 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_RX_O_FABRIC_CLK
0.672 0.672 tNET RR 1 R39C37[1][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/hd_check_phase_3_s1/CLK
0.813 0.141 tC2Q RF 2 R39C37[1][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/hd_check_phase_3_s1/Q
0.819 0.006 tNET FF 1 R39C37[1][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n1280_s21/I2
0.972 0.153 tINS FF 1 R39C37[1][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n1280_s21/F
0.972 0.000 tNET FF 1 R39C37[1][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/hd_check_phase_3_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_rx_clk
0.000 0.000 tCL RR 607 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_RX_O_FABRIC_CLK
0.672 0.672 tNET RR 1 R39C37[1][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/hd_check_phase_3_s1/CLK
0.697 0.025 tHld 1 R39C37[1][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/hd_check_phase_3_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.672, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.672, 100.000%

Path5

Path Summary:

Slack 0.275
Data Arrival Time 0.976
Data Required Time 0.701
From SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/match_cnt_4_s1
To SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/match_cnt_4_s1
Launch Clk sdi_phy_rx_clk:[R]
Latch Clk sdi_phy_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_rx_clk
0.000 0.000 tCL RR 607 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_RX_O_FABRIC_CLK
0.676 0.676 tNET RR 1 R41C38[0][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/match_cnt_4_s1/CLK
0.817 0.141 tC2Q RF 4 R41C38[0][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/match_cnt_4_s1/Q
0.823 0.006 tNET FF 1 R41C38[0][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n1274_s30/I3
0.976 0.153 tINS FF 1 R41C38[0][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n1274_s30/F
0.976 0.000 tNET FF 1 R41C38[0][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/match_cnt_4_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_rx_clk
0.000 0.000 tCL RR 607 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_RX_O_FABRIC_CLK
0.676 0.676 tNET RR 1 R41C38[0][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/match_cnt_4_s1/CLK
0.701 0.025 tHld 1 R41C38[0][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/match_cnt_4_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.676, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.676, 100.000%

Path6

Path Summary:

Slack 0.275
Data Arrival Time 0.976
Data Required Time 0.701
From SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/match_cnt_6_s1
To SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/match_cnt_6_s1
Launch Clk sdi_phy_rx_clk:[R]
Latch Clk sdi_phy_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_rx_clk
0.000 0.000 tCL RR 607 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_RX_O_FABRIC_CLK
0.676 0.676 tNET RR 1 R40C38[1][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/match_cnt_6_s1/CLK
0.817 0.141 tC2Q RF 2 R40C38[1][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/match_cnt_6_s1/Q
0.823 0.006 tNET FF 1 R40C38[1][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n1272_s30/I3
0.976 0.153 tINS FF 1 R40C38[1][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n1272_s30/F
0.976 0.000 tNET FF 1 R40C38[1][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/match_cnt_6_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_rx_clk
0.000 0.000 tCL RR 607 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_RX_O_FABRIC_CLK
0.676 0.676 tNET RR 1 R40C38[1][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/match_cnt_6_s1/CLK
0.701 0.025 tHld 1 R40C38[1][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/match_cnt_6_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.676, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.676, 100.000%

Path7

Path Summary:

Slack 0.275
Data Arrival Time 0.977
Data Required Time 0.702
From SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/drp_cnt_1_s0
To SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/drp_cnt_1_s0
Launch Clk sclk:[R]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 288 PLL_T[0] sys_pll_inst/PLLA_inst/CLKOUT0
0.677 0.677 tNET RR 1 R44C45[1][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/drp_cnt_1_s0/CLK
0.818 0.141 tC2Q RF 5 R44C45[1][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/drp_cnt_1_s0/Q
0.824 0.006 tNET FF 1 R44C45[1][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n325_s1/I1
0.977 0.153 tINS FF 1 R44C45[1][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n325_s1/F
0.977 0.000 tNET FF 1 R44C45[1][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/drp_cnt_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 288 PLL_T[0] sys_pll_inst/PLLA_inst/CLKOUT0
0.677 0.677 tNET RR 1 R44C45[1][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/drp_cnt_1_s0/CLK
0.702 0.025 tHld 1 R44C45[1][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/drp_cnt_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.677, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.677, 100.000%

Path8

Path Summary:

Slack 0.275
Data Arrival Time 0.969
Data Required Time 0.694
From SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/sd_time_cnt_0_s0
To SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/sd_time_cnt_0_s0
Launch Clk sclk:[R]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 288 PLL_T[0] sys_pll_inst/PLLA_inst/CLKOUT0
0.669 0.669 tNET RR 1 R42C43[0][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/sd_time_cnt_0_s0/CLK
0.810 0.141 tC2Q RF 5 R42C43[0][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/sd_time_cnt_0_s0/Q
0.816 0.006 tNET FF 1 R42C43[0][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n235_s3/I0
0.969 0.153 tINS FF 1 R42C43[0][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n235_s3/F
0.969 0.000 tNET FF 1 R42C43[0][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/sd_time_cnt_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 288 PLL_T[0] sys_pll_inst/PLLA_inst/CLKOUT0
0.669 0.669 tNET RR 1 R42C43[0][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/sd_time_cnt_0_s0/CLK
0.694 0.025 tHld 1 R42C43[0][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/sd_time_cnt_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.669, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.669, 100.000%

Path9

Path Summary:

Slack 0.275
Data Arrival Time 0.969
Data Required Time 0.694
From SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/sd_time_cnt_3_s0
To SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/sd_time_cnt_3_s0
Launch Clk sclk:[R]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 288 PLL_T[0] sys_pll_inst/PLLA_inst/CLKOUT0
0.669 0.669 tNET RR 1 R48C43[0][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/sd_time_cnt_3_s0/CLK
0.810 0.141 tC2Q RF 2 R48C43[0][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/sd_time_cnt_3_s0/Q
0.816 0.006 tNET FF 1 R48C43[0][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n232_s1/I1
0.969 0.153 tINS FF 1 R48C43[0][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n232_s1/F
0.969 0.000 tNET FF 1 R48C43[0][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/sd_time_cnt_3_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 288 PLL_T[0] sys_pll_inst/PLLA_inst/CLKOUT0
0.669 0.669 tNET RR 1 R48C43[0][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/sd_time_cnt_3_s0/CLK
0.694 0.025 tHld 1 R48C43[0][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/sd_time_cnt_3_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.669, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.669, 100.000%

Path10

Path Summary:

Slack 0.275
Data Arrival Time 0.969
Data Required Time 0.694
From SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/sd_time_cnt_8_s0
To SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/sd_time_cnt_8_s0
Launch Clk sclk:[R]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 288 PLL_T[0] sys_pll_inst/PLLA_inst/CLKOUT0
0.669 0.669 tNET RR 1 R46C43[0][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/sd_time_cnt_8_s0/CLK
0.810 0.141 tC2Q RF 4 R46C43[0][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/sd_time_cnt_8_s0/Q
0.816 0.006 tNET FF 1 R46C43[0][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n227_s1/I0
0.969 0.153 tINS FF 1 R46C43[0][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n227_s1/F
0.969 0.000 tNET FF 1 R46C43[0][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/sd_time_cnt_8_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 288 PLL_T[0] sys_pll_inst/PLLA_inst/CLKOUT0
0.669 0.669 tNET RR 1 R46C43[0][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/sd_time_cnt_8_s0/CLK
0.694 0.025 tHld 1 R46C43[0][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/sd_time_cnt_8_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.669, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.669, 100.000%

Path11

Path Summary:

Slack 0.275
Data Arrival Time 0.977
Data Required Time 0.702
From SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/sd_time_cnt_13_s0
To SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/sd_time_cnt_13_s0
Launch Clk sclk:[R]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 288 PLL_T[0] sys_pll_inst/PLLA_inst/CLKOUT0
0.677 0.677 tNET RR 1 R48C45[1][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/sd_time_cnt_13_s0/CLK
0.818 0.141 tC2Q RF 7 R48C45[1][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/sd_time_cnt_13_s0/Q
0.824 0.006 tNET FF 1 R48C45[1][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n222_s1/I0
0.977 0.153 tINS FF 1 R48C45[1][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n222_s1/F
0.977 0.000 tNET FF 1 R48C45[1][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/sd_time_cnt_13_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 288 PLL_T[0] sys_pll_inst/PLLA_inst/CLKOUT0
0.677 0.677 tNET RR 1 R48C45[1][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/sd_time_cnt_13_s0/CLK
0.702 0.025 tHld 1 R48C45[1][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/sd_time_cnt_13_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.677, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.677, 100.000%

Path12

Path Summary:

Slack 0.275
Data Arrival Time 0.969
Data Required Time 0.694
From SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/sd_time_cnt_31_s0
To SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/sd_time_cnt_31_s0
Launch Clk sclk:[R]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 288 PLL_T[0] sys_pll_inst/PLLA_inst/CLKOUT0
0.669 0.669 tNET RR 1 R43C43[1][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/sd_time_cnt_31_s0/CLK
0.810 0.141 tC2Q RF 2 R43C43[1][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/sd_time_cnt_31_s0/Q
0.816 0.006 tNET FF 1 R43C43[1][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n204_s1/I2
0.969 0.153 tINS FF 1 R43C43[1][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n204_s1/F
0.969 0.000 tNET FF 1 R43C43[1][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/sd_time_cnt_31_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 288 PLL_T[0] sys_pll_inst/PLLA_inst/CLKOUT0
0.669 0.669 tNET RR 1 R43C43[1][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/sd_time_cnt_31_s0/CLK
0.694 0.025 tHld 1 R43C43[1][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/sd_time_cnt_31_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.669, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.669, 100.000%

Path13

Path Summary:

Slack 0.275
Data Arrival Time 0.973
Data Required Time 0.698
From SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/hd_time_cnt_6_s0
To SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/hd_time_cnt_6_s0
Launch Clk sclk:[R]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 288 PLL_T[0] sys_pll_inst/PLLA_inst/CLKOUT0
0.673 0.673 tNET RR 1 R39C44[1][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/hd_time_cnt_6_s0/CLK
0.814 0.141 tC2Q RF 3 R39C44[1][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/hd_time_cnt_6_s0/Q
0.820 0.006 tNET FF 1 R39C44[1][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n121_s1/I1
0.973 0.153 tINS FF 1 R39C44[1][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n121_s1/F
0.973 0.000 tNET FF 1 R39C44[1][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/hd_time_cnt_6_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 288 PLL_T[0] sys_pll_inst/PLLA_inst/CLKOUT0
0.673 0.673 tNET RR 1 R39C44[1][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/hd_time_cnt_6_s0/CLK
0.698 0.025 tHld 1 R39C44[1][A] SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/hd_time_cnt_6_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.673, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.673, 100.000%

Path14

Path Summary:

Slack 0.275
Data Arrival Time 0.969
Data Required Time 0.694
From I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/sda_chk_s3
To I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/sda_chk_s3
Launch Clk sclk:[R]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 288 PLL_T[0] sys_pll_inst/PLLA_inst/CLKOUT0
0.669 0.669 tNET RR 1 R42C67[0][A] I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/sda_chk_s3/CLK
0.810 0.141 tC2Q RF 2 R42C67[0][A] I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/sda_chk_s3/Q
0.816 0.006 tNET FF 1 R42C67[0][A] I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/n231_s5/I1
0.969 0.153 tINS FF 1 R42C67[0][A] I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/n231_s5/F
0.969 0.000 tNET FF 1 R42C67[0][A] I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/sda_chk_s3/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 288 PLL_T[0] sys_pll_inst/PLLA_inst/CLKOUT0
0.669 0.669 tNET RR 1 R42C67[0][A] I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/sda_chk_s3/CLK
0.694 0.025 tHld 1 R42C67[0][A] I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/sda_chk_s3

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.669, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.669, 100.000%

Path15

Path Summary:

Slack 0.275
Data Arrival Time 0.977
Data Required Time 0.702
From I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_3_s1
To I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_3_s1
Launch Clk sclk:[R]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 288 PLL_T[0] sys_pll_inst/PLLA_inst/CLKOUT0
0.677 0.677 tNET RR 1 R40C69[0][A] I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_3_s1/CLK
0.818 0.141 tC2Q RF 6 R40C69[0][A] I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_3_s1/Q
0.824 0.006 tNET FF 1 R40C69[0][A] I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/n225_s2/I0
0.977 0.153 tINS FF 1 R40C69[0][A] I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/n225_s2/F
0.977 0.000 tNET FF 1 R40C69[0][A] I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_3_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 288 PLL_T[0] sys_pll_inst/PLLA_inst/CLKOUT0
0.677 0.677 tNET RR 1 R40C69[0][A] I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_3_s1/CLK
0.702 0.025 tHld 1 R40C69[0][A] I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_3_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.677, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.677, 100.000%

Path16

Path Summary:

Slack 0.275
Data Arrival Time 0.973
Data Required Time 0.698
From I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_2_s1
To I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_2_s1
Launch Clk sclk:[R]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 288 PLL_T[0] sys_pll_inst/PLLA_inst/CLKOUT0
0.673 0.673 tNET RR 1 R41C66[1][A] I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_2_s1/CLK
0.814 0.141 tC2Q RF 3 R41C66[1][A] I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_2_s1/Q
0.820 0.006 tNET FF 1 R41C66[1][A] I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/n44_s0/I2
0.973 0.153 tINS FF 1 R41C66[1][A] I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/n44_s0/F
0.973 0.000 tNET FF 1 R41C66[1][A] I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_2_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 288 PLL_T[0] sys_pll_inst/PLLA_inst/CLKOUT0
0.673 0.673 tNET RR 1 R41C66[1][A] I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_2_s1/CLK
0.698 0.025 tHld 1 R41C66[1][A] I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_2_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.673, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.673, 100.000%

Path17

Path Summary:

Slack 0.275
Data Arrival Time 0.973
Data Required Time 0.698
From I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_5_s1
To I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_5_s1
Launch Clk sclk:[R]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 288 PLL_T[0] sys_pll_inst/PLLA_inst/CLKOUT0
0.673 0.673 tNET RR 1 R42C66[0][A] I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_5_s1/CLK
0.814 0.141 tC2Q RF 4 R42C66[0][A] I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_5_s1/Q
0.820 0.006 tNET FF 1 R42C66[0][A] I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/n41_s0/I2
0.973 0.153 tINS FF 1 R42C66[0][A] I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/n41_s0/F
0.973 0.000 tNET FF 1 R42C66[0][A] I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_5_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 288 PLL_T[0] sys_pll_inst/PLLA_inst/CLKOUT0
0.673 0.673 tNET RR 1 R42C66[0][A] I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_5_s1/CLK
0.698 0.025 tHld 1 R42C66[0][A] I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_5_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.673, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.673, 100.000%

Path18

Path Summary:

Slack 0.275
Data Arrival Time 0.969
Data Required Time 0.694
From I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_9_s1
To I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_9_s1
Launch Clk sclk:[R]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 288 PLL_T[0] sys_pll_inst/PLLA_inst/CLKOUT0
0.669 0.669 tNET RR 1 R42C67[1][A] I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_9_s1/CLK
0.810 0.141 tC2Q RF 5 R42C67[1][A] I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_9_s1/Q
0.816 0.006 tNET FF 1 R42C67[1][A] I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/n37_s0/I1
0.969 0.153 tINS FF 1 R42C67[1][A] I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/n37_s0/F
0.969 0.000 tNET FF 1 R42C67[1][A] I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_9_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 288 PLL_T[0] sys_pll_inst/PLLA_inst/CLKOUT0
0.669 0.669 tNET RR 1 R42C67[1][A] I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_9_s1/CLK
0.694 0.025 tHld 1 R42C67[1][A] I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_9_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.669, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.669, 100.000%

Path19

Path Summary:

Slack 0.275
Data Arrival Time 0.977
Data Required Time 0.702
From I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_11_s1
To I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_11_s1
Launch Clk sclk:[R]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 288 PLL_T[0] sys_pll_inst/PLLA_inst/CLKOUT0
0.677 0.677 tNET RR 1 R42C69[1][A] I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_11_s1/CLK
0.818 0.141 tC2Q RF 3 R42C69[1][A] I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_11_s1/Q
0.824 0.006 tNET FF 1 R42C69[1][A] I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/n35_s0/I2
0.977 0.153 tINS FF 1 R42C69[1][A] I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/n35_s0/F
0.977 0.000 tNET FF 1 R42C69[1][A] I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_11_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 288 PLL_T[0] sys_pll_inst/PLLA_inst/CLKOUT0
0.677 0.677 tNET RR 1 R42C69[1][A] I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_11_s1/CLK
0.702 0.025 tHld 1 R42C69[1][A] I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_11_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.677, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.677, 100.000%

Path20

Path Summary:

Slack 0.275
Data Arrival Time 0.973
Data Required Time 0.698
From I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_15_s1
To I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_15_s1
Launch Clk sclk:[R]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 288 PLL_T[0] sys_pll_inst/PLLA_inst/CLKOUT0
0.673 0.673 tNET RR 1 R41C66[0][A] I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_15_s1/CLK
0.814 0.141 tC2Q RF 2 R41C66[0][A] I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_15_s1/Q
0.820 0.006 tNET FF 1 R41C66[0][A] I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/n31_s0/I3
0.973 0.153 tINS FF 1 R41C66[0][A] I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/n31_s0/F
0.973 0.000 tNET FF 1 R41C66[0][A] I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_15_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 288 PLL_T[0] sys_pll_inst/PLLA_inst/CLKOUT0
0.673 0.673 tNET RR 1 R41C66[0][A] I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_15_s1/CLK
0.698 0.025 tHld 1 R41C66[0][A] I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/cnt_15_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.673, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.673, 100.000%

Path21

Path Summary:

Slack 0.275
Data Arrival Time 0.977
Data Required Time 0.702
From I2C_MASTER_Top_inst0/u_i2c_master/byte_controller/CORE_CMD_3_s0
To I2C_MASTER_Top_inst0/u_i2c_master/byte_controller/CORE_CMD_3_s0
Launch Clk sclk:[R]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 288 PLL_T[0] sys_pll_inst/PLLA_inst/CLKOUT0
0.677 0.677 tNET RR 1 R43C69[1][A] I2C_MASTER_Top_inst0/u_i2c_master/byte_controller/CORE_CMD_3_s0/CLK
0.818 0.141 tC2Q RF 5 R43C69[1][A] I2C_MASTER_Top_inst0/u_i2c_master/byte_controller/CORE_CMD_3_s0/Q
0.824 0.006 tNET FF 1 R43C69[1][A] I2C_MASTER_Top_inst0/u_i2c_master/byte_controller/n199_s2/I0
0.977 0.153 tINS FF 1 R43C69[1][A] I2C_MASTER_Top_inst0/u_i2c_master/byte_controller/n199_s2/F
0.977 0.000 tNET FF 1 R43C69[1][A] I2C_MASTER_Top_inst0/u_i2c_master/byte_controller/CORE_CMD_3_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 288 PLL_T[0] sys_pll_inst/PLLA_inst/CLKOUT0
0.677 0.677 tNET RR 1 R43C69[1][A] I2C_MASTER_Top_inst0/u_i2c_master/byte_controller/CORE_CMD_3_s0/CLK
0.702 0.025 tHld 1 R43C69[1][A] I2C_MASTER_Top_inst0/u_i2c_master/byte_controller/CORE_CMD_3_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.677, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.677, 100.000%

Path22

Path Summary:

Slack 0.275
Data Arrival Time 0.973
Data Required Time 0.698
From adv7513_iic_init_inst0/mem_cnt_4_s3
To adv7513_iic_init_inst0/mem_cnt_4_s3
Launch Clk sclk:[R]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 288 PLL_T[0] sys_pll_inst/PLLA_inst/CLKOUT0
0.673 0.673 tNET RR 1 R44C64[1][A] adv7513_iic_init_inst0/mem_cnt_4_s3/CLK
0.814 0.141 tC2Q RF 3 R44C64[1][A] adv7513_iic_init_inst0/mem_cnt_4_s3/Q
0.820 0.006 tNET FF 1 R44C64[1][A] adv7513_iic_init_inst0/n268_s5/I3
0.973 0.153 tINS FF 1 R44C64[1][A] adv7513_iic_init_inst0/n268_s5/F
0.973 0.000 tNET FF 1 R44C64[1][A] adv7513_iic_init_inst0/mem_cnt_4_s3/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 288 PLL_T[0] sys_pll_inst/PLLA_inst/CLKOUT0
0.673 0.673 tNET RR 1 R44C64[1][A] adv7513_iic_init_inst0/mem_cnt_4_s3/CLK
0.698 0.025 tHld 1 R44C64[1][A] adv7513_iic_init_inst0/mem_cnt_4_s3

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.673, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.673, 100.000%

Path23

Path Summary:

Slack 0.275
Data Arrival Time 0.973
Data Required Time 0.698
From adv7513_iic_init_inst0/O_RADDR_2_s2
To adv7513_iic_init_inst0/O_RADDR_2_s2
Launch Clk sclk:[R]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 288 PLL_T[0] sys_pll_inst/PLLA_inst/CLKOUT0
0.673 0.673 tNET RR 1 R45C64[1][A] adv7513_iic_init_inst0/O_RADDR_2_s2/CLK
0.814 0.141 tC2Q RF 3 R45C64[1][A] adv7513_iic_init_inst0/O_RADDR_2_s2/Q
0.820 0.006 tNET FF 1 R45C64[1][A] adv7513_iic_init_inst0/n1051_s10/I0
0.973 0.153 tINS FF 1 R45C64[1][A] adv7513_iic_init_inst0/n1051_s10/F
0.973 0.000 tNET FF 1 R45C64[1][A] adv7513_iic_init_inst0/O_RADDR_2_s2/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 288 PLL_T[0] sys_pll_inst/PLLA_inst/CLKOUT0
0.673 0.673 tNET RR 1 R45C64[1][A] adv7513_iic_init_inst0/O_RADDR_2_s2/CLK
0.698 0.025 tHld 1 R45C64[1][A] adv7513_iic_init_inst0/O_RADDR_2_s2

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.673, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.673, 100.000%

Path24

Path Summary:

Slack 0.275
Data Arrival Time 0.969
Data Required Time 0.694
From adv7513_iic_init_inst0/O_WDATA_1_s1
To adv7513_iic_init_inst0/O_WDATA_1_s1
Launch Clk sclk:[R]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 288 PLL_T[0] sys_pll_inst/PLLA_inst/CLKOUT0
0.669 0.669 tNET RR 1 R41C63[1][A] adv7513_iic_init_inst0/O_WDATA_1_s1/CLK
0.810 0.141 tC2Q RF 5 R41C63[1][A] adv7513_iic_init_inst0/O_WDATA_1_s1/Q
0.816 0.006 tNET FF 1 R41C63[1][A] adv7513_iic_init_inst0/n1038_s14/I2
0.969 0.153 tINS FF 1 R41C63[1][A] adv7513_iic_init_inst0/n1038_s14/F
0.969 0.000 tNET FF 1 R41C63[1][A] adv7513_iic_init_inst0/O_WDATA_1_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 288 PLL_T[0] sys_pll_inst/PLLA_inst/CLKOUT0
0.669 0.669 tNET RR 1 R41C63[1][A] adv7513_iic_init_inst0/O_WDATA_1_s1/CLK
0.694 0.025 tHld 1 R41C63[1][A] adv7513_iic_init_inst0/O_WDATA_1_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.669, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.669, 100.000%

Path25

Path Summary:

Slack 0.275
Data Arrival Time 0.973
Data Required Time 0.698
From adv7513_iic_init_inst0/O_WDATA_4_s1
To adv7513_iic_init_inst0/O_WDATA_4_s1
Launch Clk sclk:[R]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 288 PLL_T[0] sys_pll_inst/PLLA_inst/CLKOUT0
0.673 0.673 tNET RR 1 R42C64[1][A] adv7513_iic_init_inst0/O_WDATA_4_s1/CLK
0.814 0.141 tC2Q RF 5 R42C64[1][A] adv7513_iic_init_inst0/O_WDATA_4_s1/Q
0.820 0.006 tNET FF 1 R42C64[1][A] adv7513_iic_init_inst0/n1025_s14/I2
0.973 0.153 tINS FF 1 R42C64[1][A] adv7513_iic_init_inst0/n1025_s14/F
0.973 0.000 tNET FF 1 R42C64[1][A] adv7513_iic_init_inst0/O_WDATA_4_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 288 PLL_T[0] sys_pll_inst/PLLA_inst/CLKOUT0
0.673 0.673 tNET RR 1 R42C64[1][A] adv7513_iic_init_inst0/O_WDATA_4_s1/CLK
0.698 0.025 tHld 1 R42C64[1][A] adv7513_iic_init_inst0/O_WDATA_4_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.673, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.673, 100.000%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 11.743
Data Arrival Time 4.833
Data Required Time 16.576
From SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1
To SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_6_s0
Launch Clk sdi_phy_tx_clk:[R]
Latch Clk sdi_phy_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
3.456 3.456 tNET RR 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/CLK
3.838 0.382 tC2Q RR 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q
3.976 0.137 tNET RR 1 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/I1
4.211 0.235 tINS RF 37 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/F
4.833 0.622 tNET FF 1 R36C45[2][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_6_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 sdi_phy_tx_clk
13.468 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
16.924 3.456 tNET RR 1 R36C45[2][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_6_s0/CLK
16.576 -0.347 tSu 1 R36C45[2][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_6_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 13.468
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.456, 100.000%
Arrival Data Path Delay cell: 0.235, 17.060%; route: 0.760, 55.172%; tC2Q: 0.382, 27.768%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.456, 100.000%

Path2

Path Summary:

Slack 11.743
Data Arrival Time 4.833
Data Required Time 16.576
From SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1
To SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_2_s0
Launch Clk sdi_phy_tx_clk:[R]
Latch Clk sdi_phy_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
3.456 3.456 tNET RR 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/CLK
3.838 0.382 tC2Q RR 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q
3.976 0.137 tNET RR 1 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/I1
4.211 0.235 tINS RF 37 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/F
4.833 0.622 tNET FF 1 R36C45[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_2_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 sdi_phy_tx_clk
13.468 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
16.924 3.456 tNET RR 1 R36C45[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_2_s0/CLK
16.576 -0.347 tSu 1 R36C45[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_2_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 13.468
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.456, 100.000%
Arrival Data Path Delay cell: 0.235, 17.060%; route: 0.760, 55.172%; tC2Q: 0.382, 27.768%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.456, 100.000%

Path3

Path Summary:

Slack 11.743
Data Arrival Time 4.833
Data Required Time 16.576
From SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1
To SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_13_s0
Launch Clk sdi_phy_tx_clk:[R]
Latch Clk sdi_phy_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
3.456 3.456 tNET RR 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/CLK
3.838 0.382 tC2Q RR 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q
3.976 0.137 tNET RR 1 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/I1
4.211 0.235 tINS RF 37 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/F
4.833 0.622 tNET FF 1 R37C45[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_13_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 sdi_phy_tx_clk
13.468 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
16.924 3.456 tNET RR 1 R37C45[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_13_s0/CLK
16.576 -0.347 tSu 1 R37C45[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_13_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 13.468
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.456, 100.000%
Arrival Data Path Delay cell: 0.235, 17.060%; route: 0.760, 55.172%; tC2Q: 0.382, 27.768%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.456, 100.000%

Path4

Path Summary:

Slack 11.743
Data Arrival Time 4.833
Data Required Time 16.576
From SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1
To SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_9_s0
Launch Clk sdi_phy_tx_clk:[R]
Latch Clk sdi_phy_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
3.456 3.456 tNET RR 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/CLK
3.838 0.382 tC2Q RR 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q
3.976 0.137 tNET RR 1 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/I1
4.211 0.235 tINS RF 37 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/F
4.833 0.622 tNET FF 1 R37C45[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_9_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 sdi_phy_tx_clk
13.468 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
16.924 3.456 tNET RR 1 R37C45[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_9_s0/CLK
16.576 -0.347 tSu 1 R37C45[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_9_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 13.468
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.456, 100.000%
Arrival Data Path Delay cell: 0.235, 17.060%; route: 0.760, 55.172%; tC2Q: 0.382, 27.768%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.456, 100.000%

Path5

Path Summary:

Slack 11.743
Data Arrival Time 4.833
Data Required Time 16.576
From SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1
To SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_8_s0
Launch Clk sdi_phy_tx_clk:[R]
Latch Clk sdi_phy_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
3.456 3.456 tNET RR 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/CLK
3.838 0.382 tC2Q RR 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q
3.976 0.137 tNET RR 1 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/I1
4.211 0.235 tINS RF 37 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/F
4.833 0.622 tNET FF 1 R36C45[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_8_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 sdi_phy_tx_clk
13.468 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
16.924 3.456 tNET RR 1 R36C45[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_8_s0/CLK
16.576 -0.347 tSu 1 R36C45[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_8_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 13.468
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.456, 100.000%
Arrival Data Path Delay cell: 0.235, 17.060%; route: 0.760, 55.172%; tC2Q: 0.382, 27.768%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.456, 100.000%

Path6

Path Summary:

Slack 11.743
Data Arrival Time 4.833
Data Required Time 16.576
From SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1
To SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_5_s0
Launch Clk sdi_phy_tx_clk:[R]
Latch Clk sdi_phy_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
3.456 3.456 tNET RR 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/CLK
3.838 0.382 tC2Q RR 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q
3.976 0.137 tNET RR 1 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/I1
4.211 0.235 tINS RF 37 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/F
4.833 0.622 tNET FF 1 R36C45[0][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_5_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 sdi_phy_tx_clk
13.468 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
16.924 3.456 tNET RR 1 R36C45[0][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_5_s0/CLK
16.576 -0.347 tSu 1 R36C45[0][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_5_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 13.468
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.456, 100.000%
Arrival Data Path Delay cell: 0.235, 17.060%; route: 0.760, 55.172%; tC2Q: 0.382, 27.768%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.456, 100.000%

Path7

Path Summary:

Slack 11.743
Data Arrival Time 4.833
Data Required Time 16.576
From SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1
To SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_4_s0
Launch Clk sdi_phy_tx_clk:[R]
Latch Clk sdi_phy_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
3.456 3.456 tNET RR 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/CLK
3.838 0.382 tC2Q RR 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q
3.976 0.137 tNET RR 1 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/I1
4.211 0.235 tINS RF 37 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/F
4.833 0.622 tNET FF 1 R36C45[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_4_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 sdi_phy_tx_clk
13.468 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
16.924 3.456 tNET RR 1 R36C45[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_4_s0/CLK
16.576 -0.347 tSu 1 R36C45[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_4_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 13.468
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.456, 100.000%
Arrival Data Path Delay cell: 0.235, 17.060%; route: 0.760, 55.172%; tC2Q: 0.382, 27.768%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.456, 100.000%

Path8

Path Summary:

Slack 11.743
Data Arrival Time 4.833
Data Required Time 16.576
From SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1
To SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_1_s0
Launch Clk sdi_phy_tx_clk:[R]
Latch Clk sdi_phy_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
3.456 3.456 tNET RR 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/CLK
3.838 0.382 tC2Q RR 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q
3.976 0.137 tNET RR 1 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/I1
4.211 0.235 tINS RF 37 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/F
4.833 0.622 tNET FF 1 R36C45[3][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 sdi_phy_tx_clk
13.468 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
16.924 3.456 tNET RR 1 R36C45[3][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_1_s0/CLK
16.576 -0.347 tSu 1 R36C45[3][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_1_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 13.468
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.456, 100.000%
Arrival Data Path Delay cell: 0.235, 17.060%; route: 0.760, 55.172%; tC2Q: 0.382, 27.768%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.456, 100.000%

Path9

Path Summary:

Slack 11.769
Data Arrival Time 4.807
Data Required Time 16.576
From SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1
To SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_0_s0
Launch Clk sdi_phy_tx_clk:[R]
Latch Clk sdi_phy_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
3.456 3.456 tNET RR 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/CLK
3.838 0.382 tC2Q RR 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q
3.976 0.137 tNET RR 1 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/I1
4.211 0.235 tINS RF 37 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/F
4.807 0.596 tNET FF 1 R34C45[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 sdi_phy_tx_clk
13.468 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
16.924 3.456 tNET RR 1 R34C45[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_0_s0/CLK
16.576 -0.347 tSu 1 R34C45[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_0_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 13.468
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.456, 100.000%
Arrival Data Path Delay cell: 0.235, 17.391%; route: 0.734, 54.302%; tC2Q: 0.382, 28.307%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.456, 100.000%

Path10

Path Summary:

Slack 11.769
Data Arrival Time 4.807
Data Required Time 16.576
From SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1
To SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_0_s0
Launch Clk sdi_phy_tx_clk:[R]
Latch Clk sdi_phy_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
3.456 3.456 tNET RR 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/CLK
3.838 0.382 tC2Q RR 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q
3.976 0.137 tNET RR 1 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/I1
4.211 0.235 tINS RF 37 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/F
4.807 0.596 tNET FF 1 R34C45[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 sdi_phy_tx_clk
13.468 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
16.924 3.456 tNET RR 1 R34C45[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_0_s0/CLK
16.576 -0.347 tSu 1 R34C45[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_0_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 13.468
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.456, 100.000%
Arrival Data Path Delay cell: 0.235, 17.391%; route: 0.734, 54.302%; tC2Q: 0.382, 28.307%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.456, 100.000%

Path11

Path Summary:

Slack 11.779
Data Arrival Time 4.807
Data Required Time 16.586
From SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1
To SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_3_s0
Launch Clk sdi_phy_tx_clk:[R]
Latch Clk sdi_phy_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
3.456 3.456 tNET RR 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/CLK
3.838 0.382 tC2Q RR 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q
3.976 0.137 tNET RR 1 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/I1
4.211 0.235 tINS RF 37 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/F
4.807 0.596 tNET FF 1 R36C44[2][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_3_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 sdi_phy_tx_clk
13.468 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
16.933 3.465 tNET RR 1 R36C44[2][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_3_s0/CLK
16.586 -0.347 tSu 1 R36C44[2][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_3_s0

Path Statistics:

Clock Skew 0.009
Setup Relationship 13.468
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.456, 100.000%
Arrival Data Path Delay cell: 0.235, 17.391%; route: 0.734, 54.302%; tC2Q: 0.382, 28.307%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.465, 100.000%

Path12

Path Summary:

Slack 11.779
Data Arrival Time 4.807
Data Required Time 16.586
From SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1
To SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_17_s0
Launch Clk sdi_phy_tx_clk:[R]
Latch Clk sdi_phy_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
3.456 3.456 tNET RR 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/CLK
3.838 0.382 tC2Q RR 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q
3.976 0.137 tNET RR 1 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/I1
4.211 0.235 tINS RF 37 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/F
4.807 0.596 tNET FF 1 R37C48[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_17_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 sdi_phy_tx_clk
13.468 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
16.933 3.465 tNET RR 1 R37C48[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_17_s0/CLK
16.586 -0.347 tSu 1 R37C48[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_17_s0

Path Statistics:

Clock Skew 0.009
Setup Relationship 13.468
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.456, 100.000%
Arrival Data Path Delay cell: 0.235, 17.391%; route: 0.734, 54.302%; tC2Q: 0.382, 28.307%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.465, 100.000%

Path13

Path Summary:

Slack 11.779
Data Arrival Time 4.807
Data Required Time 16.586
From SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1
To SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/ready_r_s0
Launch Clk sdi_phy_tx_clk:[R]
Latch Clk sdi_phy_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
3.456 3.456 tNET RR 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/CLK
3.838 0.382 tC2Q RR 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q
3.976 0.137 tNET RR 1 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/I1
4.211 0.235 tINS RF 37 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/F
4.807 0.596 tNET FF 1 R34C44[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/ready_r_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 sdi_phy_tx_clk
13.468 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
16.933 3.465 tNET RR 1 R34C44[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/ready_r_s0/CLK
16.586 -0.347 tSu 1 R34C44[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/ready_r_s0

Path Statistics:

Clock Skew 0.009
Setup Relationship 13.468
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.456, 100.000%
Arrival Data Path Delay cell: 0.235, 17.391%; route: 0.734, 54.302%; tC2Q: 0.382, 28.307%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.465, 100.000%

Path14

Path Summary:

Slack 11.779
Data Arrival Time 4.807
Data Required Time 16.586
From SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1
To SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_14_s0
Launch Clk sdi_phy_tx_clk:[R]
Latch Clk sdi_phy_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
3.456 3.456 tNET RR 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/CLK
3.838 0.382 tC2Q RR 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q
3.976 0.137 tNET RR 1 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/I1
4.211 0.235 tINS RF 37 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/F
4.807 0.596 tNET FF 1 R37C48[0][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_14_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 sdi_phy_tx_clk
13.468 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
16.933 3.465 tNET RR 1 R37C48[0][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_14_s0/CLK
16.586 -0.347 tSu 1 R37C48[0][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_14_s0

Path Statistics:

Clock Skew 0.009
Setup Relationship 13.468
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.456, 100.000%
Arrival Data Path Delay cell: 0.235, 17.391%; route: 0.734, 54.302%; tC2Q: 0.382, 28.307%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.465, 100.000%

Path15

Path Summary:

Slack 11.855
Data Arrival Time 4.731
Data Required Time 16.586
From SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1
To SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_12_s0
Launch Clk sdi_phy_tx_clk:[R]
Latch Clk sdi_phy_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
3.456 3.456 tNET RR 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/CLK
3.838 0.382 tC2Q RR 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q
3.976 0.137 tNET RR 1 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/I1
4.211 0.235 tINS RF 37 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/F
4.731 0.520 tNET FF 1 R35C44[3][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_12_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 sdi_phy_tx_clk
13.468 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
16.933 3.465 tNET RR 1 R35C44[3][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_12_s0/CLK
16.586 -0.347 tSu 1 R35C44[3][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_12_s0

Path Statistics:

Clock Skew 0.009
Setup Relationship 13.468
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.456, 100.000%
Arrival Data Path Delay cell: 0.235, 18.431%; route: 0.657, 51.569%; tC2Q: 0.382, 30.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.465, 100.000%

Path16

Path Summary:

Slack 11.855
Data Arrival Time 4.731
Data Required Time 16.586
From SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1
To SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_15_s0
Launch Clk sdi_phy_tx_clk:[R]
Latch Clk sdi_phy_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
3.456 3.456 tNET RR 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/CLK
3.838 0.382 tC2Q RR 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q
3.976 0.137 tNET RR 1 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/I1
4.211 0.235 tINS RF 37 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/F
4.731 0.520 tNET FF 1 R35C44[2][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_15_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 sdi_phy_tx_clk
13.468 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
16.933 3.465 tNET RR 1 R35C44[2][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_15_s0/CLK
16.586 -0.347 tSu 1 R35C44[2][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_15_s0

Path Statistics:

Clock Skew 0.009
Setup Relationship 13.468
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.456, 100.000%
Arrival Data Path Delay cell: 0.235, 18.431%; route: 0.657, 51.569%; tC2Q: 0.382, 30.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.465, 100.000%

Path17

Path Summary:

Slack 11.855
Data Arrival Time 4.731
Data Required Time 16.586
From SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1
To SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_16_s0
Launch Clk sdi_phy_tx_clk:[R]
Latch Clk sdi_phy_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
3.456 3.456 tNET RR 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/CLK
3.838 0.382 tC2Q RR 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q
3.976 0.137 tNET RR 1 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/I1
4.211 0.235 tINS RF 37 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/F
4.731 0.520 tNET FF 1 R35C44[2][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_16_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 sdi_phy_tx_clk
13.468 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
16.933 3.465 tNET RR 1 R35C44[2][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_16_s0/CLK
16.586 -0.347 tSu 1 R35C44[2][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_16_s0

Path Statistics:

Clock Skew 0.009
Setup Relationship 13.468
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.456, 100.000%
Arrival Data Path Delay cell: 0.235, 18.431%; route: 0.657, 51.569%; tC2Q: 0.382, 30.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.465, 100.000%

Path18

Path Summary:

Slack 11.953
Data Arrival Time 4.623
Data Required Time 16.576
From SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1
To SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_3_s0
Launch Clk sdi_phy_tx_clk:[R]
Latch Clk sdi_phy_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
3.456 3.456 tNET RR 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/CLK
3.838 0.382 tC2Q RR 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q
3.976 0.137 tNET RR 1 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/I1
4.211 0.235 tINS RF 37 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/F
4.623 0.412 tNET FF 1 R37C47[2][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_3_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 sdi_phy_tx_clk
13.468 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
16.924 3.456 tNET RR 1 R37C47[2][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_3_s0/CLK
16.576 -0.347 tSu 1 R37C47[2][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_3_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 13.468
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.456, 100.000%
Arrival Data Path Delay cell: 0.235, 20.128%; route: 0.550, 47.109%; tC2Q: 0.382, 32.762%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.456, 100.000%

Path19

Path Summary:

Slack 11.953
Data Arrival Time 4.623
Data Required Time 16.576
From SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1
To SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_4_s0
Launch Clk sdi_phy_tx_clk:[R]
Latch Clk sdi_phy_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
3.456 3.456 tNET RR 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/CLK
3.838 0.382 tC2Q RR 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q
3.976 0.137 tNET RR 1 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/I1
4.211 0.235 tINS RF 37 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/F
4.623 0.412 tNET FF 1 R36C47[3][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_4_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 sdi_phy_tx_clk
13.468 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
16.924 3.456 tNET RR 1 R36C47[3][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_4_s0/CLK
16.576 -0.347 tSu 1 R36C47[3][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_4_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 13.468
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.456, 100.000%
Arrival Data Path Delay cell: 0.235, 20.128%; route: 0.550, 47.109%; tC2Q: 0.382, 32.762%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.456, 100.000%

Path20

Path Summary:

Slack 11.953
Data Arrival Time 4.623
Data Required Time 16.576
From SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1
To SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_7_s0
Launch Clk sdi_phy_tx_clk:[R]
Latch Clk sdi_phy_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
3.456 3.456 tNET RR 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/CLK
3.838 0.382 tC2Q RR 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q
3.976 0.137 tNET RR 1 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/I1
4.211 0.235 tINS RF 37 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/F
4.623 0.412 tNET FF 1 R36C47[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_7_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 sdi_phy_tx_clk
13.468 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
16.924 3.456 tNET RR 1 R36C47[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_7_s0/CLK
16.576 -0.347 tSu 1 R36C47[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_7_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 13.468
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.456, 100.000%
Arrival Data Path Delay cell: 0.235, 20.128%; route: 0.550, 47.109%; tC2Q: 0.382, 32.762%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.456, 100.000%

Path21

Path Summary:

Slack 11.953
Data Arrival Time 4.623
Data Required Time 16.576
From SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1
To SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_8_s0
Launch Clk sdi_phy_tx_clk:[R]
Latch Clk sdi_phy_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
3.456 3.456 tNET RR 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/CLK
3.838 0.382 tC2Q RR 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q
3.976 0.137 tNET RR 1 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/I1
4.211 0.235 tINS RF 37 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/F
4.623 0.412 tNET FF 1 R36C47[2][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_8_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 sdi_phy_tx_clk
13.468 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
16.924 3.456 tNET RR 1 R36C47[2][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_8_s0/CLK
16.576 -0.347 tSu 1 R36C47[2][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_8_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 13.468
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.456, 100.000%
Arrival Data Path Delay cell: 0.235, 20.128%; route: 0.550, 47.109%; tC2Q: 0.382, 32.762%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.456, 100.000%

Path22

Path Summary:

Slack 11.953
Data Arrival Time 4.623
Data Required Time 16.576
From SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1
To SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_11_s0
Launch Clk sdi_phy_tx_clk:[R]
Latch Clk sdi_phy_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
3.456 3.456 tNET RR 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/CLK
3.838 0.382 tC2Q RR 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q
3.976 0.137 tNET RR 1 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/I1
4.211 0.235 tINS RF 37 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/F
4.623 0.412 tNET FF 1 R36C47[0][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_11_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 sdi_phy_tx_clk
13.468 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
16.924 3.456 tNET RR 1 R36C47[0][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_11_s0/CLK
16.576 -0.347 tSu 1 R36C47[0][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_11_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 13.468
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.456, 100.000%
Arrival Data Path Delay cell: 0.235, 20.128%; route: 0.550, 47.109%; tC2Q: 0.382, 32.762%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.456, 100.000%

Path23

Path Summary:

Slack 11.953
Data Arrival Time 4.623
Data Required Time 16.576
From SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1
To SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_13_s0
Launch Clk sdi_phy_tx_clk:[R]
Latch Clk sdi_phy_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
3.456 3.456 tNET RR 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/CLK
3.838 0.382 tC2Q RR 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q
3.976 0.137 tNET RR 1 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/I1
4.211 0.235 tINS RF 37 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/F
4.623 0.412 tNET FF 1 R37C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_13_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 sdi_phy_tx_clk
13.468 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
16.924 3.456 tNET RR 1 R37C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_13_s0/CLK
16.576 -0.347 tSu 1 R37C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_13_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 13.468
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.456, 100.000%
Arrival Data Path Delay cell: 0.235, 20.128%; route: 0.550, 47.109%; tC2Q: 0.382, 32.762%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.456, 100.000%

Path24

Path Summary:

Slack 11.953
Data Arrival Time 4.623
Data Required Time 16.576
From SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1
To SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_16_s0
Launch Clk sdi_phy_tx_clk:[R]
Latch Clk sdi_phy_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
3.456 3.456 tNET RR 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/CLK
3.838 0.382 tC2Q RR 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q
3.976 0.137 tNET RR 1 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/I1
4.211 0.235 tINS RF 37 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/F
4.623 0.412 tNET FF 1 R37C47[2][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_16_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 sdi_phy_tx_clk
13.468 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
16.924 3.456 tNET RR 1 R37C47[2][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_16_s0/CLK
16.576 -0.347 tSu 1 R37C47[2][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_16_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 13.468
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.456, 100.000%
Arrival Data Path Delay cell: 0.235, 20.128%; route: 0.550, 47.109%; tC2Q: 0.382, 32.762%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.456, 100.000%

Path25

Path Summary:

Slack 11.985
Data Arrival Time 4.582
Data Required Time 16.567
From SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1
To SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_17_s0
Launch Clk sdi_phy_tx_clk:[R]
Latch Clk sdi_phy_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
3.456 3.456 tNET RR 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/CLK
3.838 0.382 tC2Q RR 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q
3.976 0.137 tNET RR 1 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/I1
4.211 0.235 tINS RF 37 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/F
4.582 0.371 tNET FF 1 R37C46[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_17_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 sdi_phy_tx_clk
13.468 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
16.914 3.446 tNET RR 1 R37C46[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_17_s0/CLK
16.567 -0.347 tSu 1 R37C46[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_17_s0

Path Statistics:

Clock Skew -0.009
Setup Relationship 13.468
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.456, 100.000%
Arrival Data Path Delay cell: 0.235, 20.866%; route: 0.509, 45.172%; tC2Q: 0.382, 33.962%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.446, 100.000%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 0.493
Data Arrival Time 1.666
Data Required Time 1.173
From SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1
To SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_1_s0
Launch Clk sdi_phy_tx_clk:[R]
Latch Clk sdi_phy_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
1.226 1.226 tNET RR 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/CLK
1.367 0.141 tC2Q RF 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q
1.433 0.066 tNET FF 1 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/I1
1.579 0.146 tINS FR 37 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/F
1.666 0.087 tNET RR 1 R35C47[2][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
1.226 1.226 tNET RR 1 R35C47[2][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_1_s0/CLK
1.173 -0.053 tHld 1 R35C47[2][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.226, 100.000%
Arrival Data Path Delay cell: 0.146, 33.182%; route: 0.153, 34.773%; tC2Q: 0.141, 32.045%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.226, 100.000%

Path2

Path Summary:

Slack 0.493
Data Arrival Time 1.666
Data Required Time 1.173
From SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1
To SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_5_s0
Launch Clk sdi_phy_tx_clk:[R]
Latch Clk sdi_phy_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
1.226 1.226 tNET RR 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/CLK
1.367 0.141 tC2Q RF 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q
1.433 0.066 tNET FF 1 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/I1
1.579 0.146 tINS FR 37 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/F
1.666 0.087 tNET RR 1 R35C47[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_5_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
1.226 1.226 tNET RR 1 R35C47[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_5_s0/CLK
1.173 -0.053 tHld 1 R35C47[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_5_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.226, 100.000%
Arrival Data Path Delay cell: 0.146, 33.182%; route: 0.153, 34.773%; tC2Q: 0.141, 32.045%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.226, 100.000%

Path3

Path Summary:

Slack 0.493
Data Arrival Time 1.666
Data Required Time 1.173
From SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1
To SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_9_s0
Launch Clk sdi_phy_tx_clk:[R]
Latch Clk sdi_phy_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
1.226 1.226 tNET RR 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/CLK
1.367 0.141 tC2Q RF 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q
1.433 0.066 tNET FF 1 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/I1
1.579 0.146 tINS FR 37 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/F
1.666 0.087 tNET RR 1 R35C47[3][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_9_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
1.226 1.226 tNET RR 1 R35C47[3][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_9_s0/CLK
1.173 -0.053 tHld 1 R35C47[3][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_9_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.226, 100.000%
Arrival Data Path Delay cell: 0.146, 33.182%; route: 0.153, 34.773%; tC2Q: 0.141, 32.045%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.226, 100.000%

Path4

Path Summary:

Slack 0.602
Data Arrival Time 1.771
Data Required Time 1.169
From SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1
To SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_12_s0
Launch Clk sdi_phy_tx_clk:[R]
Latch Clk sdi_phy_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
1.226 1.226 tNET RR 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/CLK
1.367 0.141 tC2Q RF 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q
1.433 0.066 tNET FF 1 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/I1
1.579 0.146 tINS FR 37 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/F
1.771 0.192 tNET RR 1 R35C46[0][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_12_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
1.222 1.222 tNET RR 1 R35C46[0][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_12_s0/CLK
1.169 -0.053 tHld 1 R35C46[0][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_12_s0

Path Statistics:

Clock Skew -0.004
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.226, 100.000%
Arrival Data Path Delay cell: 0.146, 26.789%; route: 0.258, 47.339%; tC2Q: 0.141, 25.872%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.222, 100.000%

Path5

Path Summary:

Slack 0.602
Data Arrival Time 1.771
Data Required Time 1.169
From SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1
To SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_15_s0
Launch Clk sdi_phy_tx_clk:[R]
Latch Clk sdi_phy_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
1.226 1.226 tNET RR 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/CLK
1.367 0.141 tC2Q RF 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q
1.433 0.066 tNET FF 1 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/I1
1.579 0.146 tINS FR 37 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/F
1.771 0.192 tNET RR 1 R35C46[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_15_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
1.222 1.222 tNET RR 1 R35C46[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_15_s0/CLK
1.169 -0.053 tHld 1 R35C46[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_15_s0

Path Statistics:

Clock Skew -0.004
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.226, 100.000%
Arrival Data Path Delay cell: 0.146, 26.789%; route: 0.258, 47.339%; tC2Q: 0.141, 25.872%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.222, 100.000%

Path6

Path Summary:

Slack 0.604
Data Arrival Time 1.777
Data Required Time 1.173
From SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1
To SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_10_s0
Launch Clk sdi_phy_tx_clk:[R]
Latch Clk sdi_phy_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
1.226 1.226 tNET RR 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/CLK
1.367 0.141 tC2Q RF 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q
1.433 0.066 tNET FF 1 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/I1
1.579 0.146 tINS FR 37 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/F
1.777 0.198 tNET RR 1 R35C45[3][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_10_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
1.226 1.226 tNET RR 1 R35C45[3][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_10_s0/CLK
1.173 -0.053 tHld 1 R35C45[3][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_10_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.226, 100.000%
Arrival Data Path Delay cell: 0.146, 26.497%; route: 0.264, 47.913%; tC2Q: 0.141, 25.590%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.226, 100.000%

Path7

Path Summary:

Slack 0.604
Data Arrival Time 1.777
Data Required Time 1.173
From SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1
To SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_11_s0
Launch Clk sdi_phy_tx_clk:[R]
Latch Clk sdi_phy_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
1.226 1.226 tNET RR 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/CLK
1.367 0.141 tC2Q RF 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q
1.433 0.066 tNET FF 1 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/I1
1.579 0.146 tINS FR 37 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/F
1.777 0.198 tNET RR 1 R35C45[2][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_11_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
1.226 1.226 tNET RR 1 R35C45[2][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_11_s0/CLK
1.173 -0.053 tHld 1 R35C45[2][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_11_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.226, 100.000%
Arrival Data Path Delay cell: 0.146, 26.497%; route: 0.264, 47.913%; tC2Q: 0.141, 25.590%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.226, 100.000%

Path8

Path Summary:

Slack 0.604
Data Arrival Time 1.777
Data Required Time 1.173
From SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1
To SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_10_s0
Launch Clk sdi_phy_tx_clk:[R]
Latch Clk sdi_phy_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
1.226 1.226 tNET RR 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/CLK
1.367 0.141 tC2Q RF 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q
1.433 0.066 tNET FF 1 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/I1
1.579 0.146 tINS FR 37 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/F
1.777 0.198 tNET RR 1 R35C45[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_10_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
1.226 1.226 tNET RR 1 R35C45[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_10_s0/CLK
1.173 -0.053 tHld 1 R35C45[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_10_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.226, 100.000%
Arrival Data Path Delay cell: 0.146, 26.497%; route: 0.264, 47.913%; tC2Q: 0.141, 25.590%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.226, 100.000%

Path9

Path Summary:

Slack 0.604
Data Arrival Time 1.777
Data Required Time 1.173
From SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1
To SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_7_s0
Launch Clk sdi_phy_tx_clk:[R]
Latch Clk sdi_phy_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
1.226 1.226 tNET RR 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/CLK
1.367 0.141 tC2Q RF 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q
1.433 0.066 tNET FF 1 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/I1
1.579 0.146 tINS FR 37 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/F
1.777 0.198 tNET RR 1 R35C45[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_7_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
1.226 1.226 tNET RR 1 R35C45[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_7_s0/CLK
1.173 -0.053 tHld 1 R35C45[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_7_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.226, 100.000%
Arrival Data Path Delay cell: 0.146, 26.497%; route: 0.264, 47.913%; tC2Q: 0.141, 25.590%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.226, 100.000%

Path10

Path Summary:

Slack 0.604
Data Arrival Time 1.777
Data Required Time 1.173
From SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1
To SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_6_s0
Launch Clk sdi_phy_tx_clk:[R]
Latch Clk sdi_phy_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
1.226 1.226 tNET RR 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/CLK
1.367 0.141 tC2Q RF 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q
1.433 0.066 tNET FF 1 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/I1
1.579 0.146 tINS FR 37 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/F
1.777 0.198 tNET RR 1 R35C45[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_6_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
1.226 1.226 tNET RR 1 R35C45[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_6_s0/CLK
1.173 -0.053 tHld 1 R35C45[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_6_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.226, 100.000%
Arrival Data Path Delay cell: 0.146, 26.497%; route: 0.264, 47.913%; tC2Q: 0.141, 25.590%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.226, 100.000%

Path11

Path Summary:

Slack 0.604
Data Arrival Time 1.777
Data Required Time 1.173
From SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1
To SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_2_s0
Launch Clk sdi_phy_tx_clk:[R]
Latch Clk sdi_phy_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
1.226 1.226 tNET RR 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/CLK
1.367 0.141 tC2Q RF 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q
1.433 0.066 tNET FF 1 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/I1
1.579 0.146 tINS FR 37 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/F
1.777 0.198 tNET RR 1 R35C45[0][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_2_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
1.226 1.226 tNET RR 1 R35C45[0][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_2_s0/CLK
1.173 -0.053 tHld 1 R35C45[0][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_2_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.226, 100.000%
Arrival Data Path Delay cell: 0.146, 26.497%; route: 0.264, 47.913%; tC2Q: 0.141, 25.590%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.226, 100.000%

Path12

Path Summary:

Slack 0.619
Data Arrival Time 1.788
Data Required Time 1.169
From SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1
To SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_17_s0
Launch Clk sdi_phy_tx_clk:[R]
Latch Clk sdi_phy_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
1.226 1.226 tNET RR 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/CLK
1.367 0.141 tC2Q RF 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q
1.433 0.066 tNET FF 1 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/I1
1.579 0.146 tINS FR 37 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/F
1.788 0.209 tNET RR 1 R37C46[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_17_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
1.222 1.222 tNET RR 1 R37C46[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_17_s0/CLK
1.169 -0.053 tHld 1 R37C46[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_17_s0

Path Statistics:

Clock Skew -0.004
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.226, 100.000%
Arrival Data Path Delay cell: 0.146, 25.979%; route: 0.275, 48.932%; tC2Q: 0.141, 25.089%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.222, 100.000%

Path13

Path Summary:

Slack 0.619
Data Arrival Time 1.788
Data Required Time 1.169
From SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1
To SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_14_s0
Launch Clk sdi_phy_tx_clk:[R]
Latch Clk sdi_phy_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
1.226 1.226 tNET RR 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/CLK
1.367 0.141 tC2Q RF 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q
1.433 0.066 tNET FF 1 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/I1
1.579 0.146 tINS FR 37 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/F
1.788 0.209 tNET RR 1 R37C46[0][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_14_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
1.222 1.222 tNET RR 1 R37C46[0][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_14_s0/CLK
1.169 -0.053 tHld 1 R37C46[0][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_14_s0

Path Statistics:

Clock Skew -0.004
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.226, 100.000%
Arrival Data Path Delay cell: 0.146, 25.979%; route: 0.275, 48.932%; tC2Q: 0.141, 25.089%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.222, 100.000%

Path14

Path Summary:

Slack 0.623
Data Arrival Time 1.796
Data Required Time 1.173
From SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1
To SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_3_s0
Launch Clk sdi_phy_tx_clk:[R]
Latch Clk sdi_phy_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
1.226 1.226 tNET RR 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/CLK
1.367 0.141 tC2Q RF 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q
1.433 0.066 tNET FF 1 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/I1
1.579 0.146 tINS FR 37 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/F
1.796 0.217 tNET RR 1 R37C47[2][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_3_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
1.226 1.226 tNET RR 1 R37C47[2][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_3_s0/CLK
1.173 -0.053 tHld 1 R37C47[2][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_3_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.226, 100.000%
Arrival Data Path Delay cell: 0.146, 25.614%; route: 0.283, 49.649%; tC2Q: 0.141, 24.737%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.226, 100.000%

Path15

Path Summary:

Slack 0.623
Data Arrival Time 1.796
Data Required Time 1.173
From SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1
To SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_4_s0
Launch Clk sdi_phy_tx_clk:[R]
Latch Clk sdi_phy_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
1.226 1.226 tNET RR 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/CLK
1.367 0.141 tC2Q RF 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q
1.433 0.066 tNET FF 1 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/I1
1.579 0.146 tINS FR 37 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/F
1.796 0.217 tNET RR 1 R36C47[3][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_4_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
1.226 1.226 tNET RR 1 R36C47[3][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_4_s0/CLK
1.173 -0.053 tHld 1 R36C47[3][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_4_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.226, 100.000%
Arrival Data Path Delay cell: 0.146, 25.614%; route: 0.283, 49.649%; tC2Q: 0.141, 24.737%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.226, 100.000%

Path16

Path Summary:

Slack 0.623
Data Arrival Time 1.796
Data Required Time 1.173
From SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1
To SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_7_s0
Launch Clk sdi_phy_tx_clk:[R]
Latch Clk sdi_phy_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
1.226 1.226 tNET RR 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/CLK
1.367 0.141 tC2Q RF 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q
1.433 0.066 tNET FF 1 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/I1
1.579 0.146 tINS FR 37 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/F
1.796 0.217 tNET RR 1 R36C47[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_7_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
1.226 1.226 tNET RR 1 R36C47[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_7_s0/CLK
1.173 -0.053 tHld 1 R36C47[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_7_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.226, 100.000%
Arrival Data Path Delay cell: 0.146, 25.614%; route: 0.283, 49.649%; tC2Q: 0.141, 24.737%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.226, 100.000%

Path17

Path Summary:

Slack 0.623
Data Arrival Time 1.796
Data Required Time 1.173
From SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1
To SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_8_s0
Launch Clk sdi_phy_tx_clk:[R]
Latch Clk sdi_phy_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
1.226 1.226 tNET RR 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/CLK
1.367 0.141 tC2Q RF 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q
1.433 0.066 tNET FF 1 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/I1
1.579 0.146 tINS FR 37 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/F
1.796 0.217 tNET RR 1 R36C47[2][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_8_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
1.226 1.226 tNET RR 1 R36C47[2][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_8_s0/CLK
1.173 -0.053 tHld 1 R36C47[2][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_8_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.226, 100.000%
Arrival Data Path Delay cell: 0.146, 25.614%; route: 0.283, 49.649%; tC2Q: 0.141, 24.737%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.226, 100.000%

Path18

Path Summary:

Slack 0.623
Data Arrival Time 1.796
Data Required Time 1.173
From SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1
To SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_11_s0
Launch Clk sdi_phy_tx_clk:[R]
Latch Clk sdi_phy_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
1.226 1.226 tNET RR 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/CLK
1.367 0.141 tC2Q RF 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q
1.433 0.066 tNET FF 1 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/I1
1.579 0.146 tINS FR 37 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/F
1.796 0.217 tNET RR 1 R36C47[0][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_11_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
1.226 1.226 tNET RR 1 R36C47[0][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_11_s0/CLK
1.173 -0.053 tHld 1 R36C47[0][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_11_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.226, 100.000%
Arrival Data Path Delay cell: 0.146, 25.614%; route: 0.283, 49.649%; tC2Q: 0.141, 24.737%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.226, 100.000%

Path19

Path Summary:

Slack 0.623
Data Arrival Time 1.796
Data Required Time 1.173
From SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1
To SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_13_s0
Launch Clk sdi_phy_tx_clk:[R]
Latch Clk sdi_phy_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
1.226 1.226 tNET RR 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/CLK
1.367 0.141 tC2Q RF 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q
1.433 0.066 tNET FF 1 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/I1
1.579 0.146 tINS FR 37 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/F
1.796 0.217 tNET RR 1 R37C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_13_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
1.226 1.226 tNET RR 1 R37C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_13_s0/CLK
1.173 -0.053 tHld 1 R37C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_13_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.226, 100.000%
Arrival Data Path Delay cell: 0.146, 25.614%; route: 0.283, 49.649%; tC2Q: 0.141, 24.737%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.226, 100.000%

Path20

Path Summary:

Slack 0.623
Data Arrival Time 1.796
Data Required Time 1.173
From SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1
To SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_16_s0
Launch Clk sdi_phy_tx_clk:[R]
Latch Clk sdi_phy_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
1.226 1.226 tNET RR 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/CLK
1.367 0.141 tC2Q RF 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q
1.433 0.066 tNET FF 1 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/I1
1.579 0.146 tINS FR 37 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/F
1.796 0.217 tNET RR 1 R37C47[2][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_16_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
1.226 1.226 tNET RR 1 R37C47[2][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_16_s0/CLK
1.173 -0.053 tHld 1 R37C47[2][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_16_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.226, 100.000%
Arrival Data Path Delay cell: 0.146, 25.614%; route: 0.283, 49.649%; tC2Q: 0.141, 24.737%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.226, 100.000%

Path21

Path Summary:

Slack 0.694
Data Arrival Time 1.871
Data Required Time 1.177
From SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1
To SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_16_s0
Launch Clk sdi_phy_tx_clk:[R]
Latch Clk sdi_phy_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
1.226 1.226 tNET RR 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/CLK
1.367 0.141 tC2Q RF 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q
1.433 0.066 tNET FF 1 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/I1
1.579 0.146 tINS FR 37 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/F
1.871 0.292 tNET RR 1 R35C44[2][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_16_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
1.230 1.230 tNET RR 1 R35C44[2][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_16_s0/CLK
1.177 -0.053 tHld 1 R35C44[2][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_16_s0

Path Statistics:

Clock Skew 0.004
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.226, 100.000%
Arrival Data Path Delay cell: 0.146, 22.636%; route: 0.358, 55.504%; tC2Q: 0.141, 21.860%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.230, 100.000%

Path22

Path Summary:

Slack 0.694
Data Arrival Time 1.871
Data Required Time 1.177
From SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1
To SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_15_s0
Launch Clk sdi_phy_tx_clk:[R]
Latch Clk sdi_phy_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
1.226 1.226 tNET RR 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/CLK
1.367 0.141 tC2Q RF 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q
1.433 0.066 tNET FF 1 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/I1
1.579 0.146 tINS FR 37 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/F
1.871 0.292 tNET RR 1 R35C44[2][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_15_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
1.230 1.230 tNET RR 1 R35C44[2][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_15_s0/CLK
1.177 -0.053 tHld 1 R35C44[2][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_15_s0

Path Statistics:

Clock Skew 0.004
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.226, 100.000%
Arrival Data Path Delay cell: 0.146, 22.636%; route: 0.358, 55.504%; tC2Q: 0.141, 21.860%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.230, 100.000%

Path23

Path Summary:

Slack 0.694
Data Arrival Time 1.871
Data Required Time 1.177
From SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1
To SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_12_s0
Launch Clk sdi_phy_tx_clk:[R]
Latch Clk sdi_phy_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
1.226 1.226 tNET RR 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/CLK
1.367 0.141 tC2Q RF 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q
1.433 0.066 tNET FF 1 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/I1
1.579 0.146 tINS FR 37 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/F
1.871 0.292 tNET RR 1 R35C44[3][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_12_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
1.230 1.230 tNET RR 1 R35C44[3][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_12_s0/CLK
1.177 -0.053 tHld 1 R35C44[3][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_12_s0

Path Statistics:

Clock Skew 0.004
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.226, 100.000%
Arrival Data Path Delay cell: 0.146, 22.636%; route: 0.358, 55.504%; tC2Q: 0.141, 21.860%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.230, 100.000%

Path24

Path Summary:

Slack 0.715
Data Arrival Time 1.892
Data Required Time 1.177
From SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1
To SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_3_s0
Launch Clk sdi_phy_tx_clk:[R]
Latch Clk sdi_phy_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
1.226 1.226 tNET RR 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/CLK
1.367 0.141 tC2Q RF 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q
1.433 0.066 tNET FF 1 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/I1
1.579 0.146 tINS FR 37 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/F
1.892 0.313 tNET RR 1 R36C44[2][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_3_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
1.230 1.230 tNET RR 1 R36C44[2][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_3_s0/CLK
1.177 -0.053 tHld 1 R36C44[2][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst1/crc_r_3_s0

Path Statistics:

Clock Skew 0.004
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.226, 100.000%
Arrival Data Path Delay cell: 0.146, 21.922%; route: 0.379, 56.907%; tC2Q: 0.141, 21.171%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.230, 100.000%

Path25

Path Summary:

Slack 0.715
Data Arrival Time 1.892
Data Required Time 1.177
From SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1
To SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_17_s0
Launch Clk sdi_phy_tx_clk:[R]
Latch Clk sdi_phy_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
1.226 1.226 tNET RR 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/CLK
1.367 0.141 tC2Q RF 1 R35C47[1][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/crc_rstn_s1/Q
1.433 0.066 tNET FF 1 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/I1
1.579 0.146 tINS FR 37 R35C47[1][A] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/n34_s1/F
1.892 0.313 tNET RR 1 R37C48[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_17_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sdi_phy_tx_clk
0.000 0.000 tCL RR 941 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
1.230 1.230 tNET RR 1 R37C48[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_17_s0/CLK
1.177 -0.053 tHld 1 R37C48[0][B] SDI_Encoder_Top_inst/sdi_encoder_wrapper_inst/tx_hd_crc_inst/tx_crc18_d10_inst0/crc_r_17_s0

Path Statistics:

Clock Skew 0.004
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.226, 100.000%
Arrival Data Path Delay cell: 0.146, 21.922%; route: 0.379, 56.907%; tC2Q: 0.141, 21.171%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.230, 100.000%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack: 4.250
Actual Width: 4.500
Required Width: 0.250
Type: Low Pulse Width
Clock: sdi_phy_tx_clk
Objects: testpattern_inst/H_cnt_10_s0

Late clock Path:

AT DELAY TYPE RF NODE
6.734 0.000 active clock edge time
6.734 0.000 sdi_phy_tx_clk
6.734 0.000 tCL FF SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
10.198 3.464 tNET FF testpattern_inst/H_cnt_10_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
13.468 0.000 active clock edge time
13.468 0.000 sdi_phy_tx_clk
13.468 0.000 tCL RR SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
14.698 1.230 tNET RR testpattern_inst/H_cnt_10_s0/CLK

MPW2

MPW Summary:

Slack: 4.250
Actual Width: 4.500
Required Width: 0.250
Type: Low Pulse Width
Clock: sdi_phy_tx_clk
Objects: testpattern_inst/H_cnt_9_s0

Late clock Path:

AT DELAY TYPE RF NODE
6.734 0.000 active clock edge time
6.734 0.000 sdi_phy_tx_clk
6.734 0.000 tCL FF SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
10.198 3.464 tNET FF testpattern_inst/H_cnt_9_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
13.468 0.000 active clock edge time
13.468 0.000 sdi_phy_tx_clk
13.468 0.000 tCL RR SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
14.698 1.230 tNET RR testpattern_inst/H_cnt_9_s0/CLK

MPW3

MPW Summary:

Slack: 4.250
Actual Width: 4.500
Required Width: 0.250
Type: Low Pulse Width
Clock: sdi_phy_tx_clk
Objects: testpattern_inst/H_cnt_7_s0

Late clock Path:

AT DELAY TYPE RF NODE
6.734 0.000 active clock edge time
6.734 0.000 sdi_phy_tx_clk
6.734 0.000 tCL FF SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
10.198 3.464 tNET FF testpattern_inst/H_cnt_7_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
13.468 0.000 active clock edge time
13.468 0.000 sdi_phy_tx_clk
13.468 0.000 tCL RR SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
14.698 1.230 tNET RR testpattern_inst/H_cnt_7_s0/CLK

MPW4

MPW Summary:

Slack: 4.250
Actual Width: 4.500
Required Width: 0.250
Type: Low Pulse Width
Clock: sdi_phy_tx_clk
Objects: testpattern_inst/V_cnt_12_s1

Late clock Path:

AT DELAY TYPE RF NODE
6.734 0.000 active clock edge time
6.734 0.000 sdi_phy_tx_clk
6.734 0.000 tCL FF SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
10.198 3.464 tNET FF testpattern_inst/V_cnt_12_s1/CLK

Early clock Path:

AT DELAY TYPE RF NODE
13.468 0.000 active clock edge time
13.468 0.000 sdi_phy_tx_clk
13.468 0.000 tCL RR SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
14.698 1.230 tNET RR testpattern_inst/V_cnt_12_s1/CLK

MPW5

MPW Summary:

Slack: 4.250
Actual Width: 4.500
Required Width: 0.250
Type: Low Pulse Width
Clock: sdi_phy_tx_clk
Objects: testpattern_inst/De_vcnt_12_s1

Late clock Path:

AT DELAY TYPE RF NODE
6.734 0.000 active clock edge time
6.734 0.000 sdi_phy_tx_clk
6.734 0.000 tCL FF SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
10.198 3.464 tNET FF testpattern_inst/De_vcnt_12_s1/CLK

Early clock Path:

AT DELAY TYPE RF NODE
13.468 0.000 active clock edge time
13.468 0.000 sdi_phy_tx_clk
13.468 0.000 tCL RR SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
14.698 1.230 tNET RR testpattern_inst/De_vcnt_12_s1/CLK

MPW6

MPW Summary:

Slack: 4.250
Actual Width: 4.500
Required Width: 0.250
Type: Low Pulse Width
Clock: sdi_phy_tx_clk
Objects: testpattern_inst/De_hcnt_7_s3

Late clock Path:

AT DELAY TYPE RF NODE
6.734 0.000 active clock edge time
6.734 0.000 sdi_phy_tx_clk
6.734 0.000 tCL FF SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
10.198 3.464 tNET FF testpattern_inst/De_hcnt_7_s3/CLK

Early clock Path:

AT DELAY TYPE RF NODE
13.468 0.000 active clock edge time
13.468 0.000 sdi_phy_tx_clk
13.468 0.000 tCL RR SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
14.698 1.230 tNET RR testpattern_inst/De_hcnt_7_s3/CLK

MPW7

MPW Summary:

Slack: 4.250
Actual Width: 4.500
Required Width: 0.250
Type: Low Pulse Width
Clock: sdi_phy_tx_clk
Objects: testpattern_inst/De_hcnt_6_s3

Late clock Path:

AT DELAY TYPE RF NODE
6.734 0.000 active clock edge time
6.734 0.000 sdi_phy_tx_clk
6.734 0.000 tCL FF SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
10.198 3.464 tNET FF testpattern_inst/De_hcnt_6_s3/CLK

Early clock Path:

AT DELAY TYPE RF NODE
13.468 0.000 active clock edge time
13.468 0.000 sdi_phy_tx_clk
13.468 0.000 tCL RR SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
14.698 1.230 tNET RR testpattern_inst/De_hcnt_6_s3/CLK

MPW8

MPW Summary:

Slack: 4.250
Actual Width: 4.500
Required Width: 0.250
Type: Low Pulse Width
Clock: sdi_phy_tx_clk
Objects: testpattern_inst/De_hcnt_4_s3

Late clock Path:

AT DELAY TYPE RF NODE
6.734 0.000 active clock edge time
6.734 0.000 sdi_phy_tx_clk
6.734 0.000 tCL FF SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
10.198 3.464 tNET FF testpattern_inst/De_hcnt_4_s3/CLK

Early clock Path:

AT DELAY TYPE RF NODE
13.468 0.000 active clock edge time
13.468 0.000 sdi_phy_tx_clk
13.468 0.000 tCL RR SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
14.698 1.230 tNET RR testpattern_inst/De_hcnt_4_s3/CLK

MPW9

MPW Summary:

Slack: 4.250
Actual Width: 4.500
Required Width: 0.250
Type: Low Pulse Width
Clock: sdi_phy_tx_clk
Objects: testpattern_inst/De_hcnt_3_s3

Late clock Path:

AT DELAY TYPE RF NODE
6.734 0.000 active clock edge time
6.734 0.000 sdi_phy_tx_clk
6.734 0.000 tCL FF SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
10.198 3.464 tNET FF testpattern_inst/De_hcnt_3_s3/CLK

Early clock Path:

AT DELAY TYPE RF NODE
13.468 0.000 active clock edge time
13.468 0.000 sdi_phy_tx_clk
13.468 0.000 tCL RR SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
14.698 1.230 tNET RR testpattern_inst/De_hcnt_3_s3/CLK

MPW10

MPW Summary:

Slack: 4.250
Actual Width: 4.500
Required Width: 0.250
Type: Low Pulse Width
Clock: sdi_phy_tx_clk
Objects: testpattern_inst/De_vcnt_11_s1

Late clock Path:

AT DELAY TYPE RF NODE
6.734 0.000 active clock edge time
6.734 0.000 sdi_phy_tx_clk
6.734 0.000 tCL FF SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
10.198 3.464 tNET FF testpattern_inst/De_vcnt_11_s1/CLK

Early clock Path:

AT DELAY TYPE RF NODE
13.468 0.000 active clock edge time
13.468 0.000 sdi_phy_tx_clk
13.468 0.000 tCL RR SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
14.698 1.230 tNET RR testpattern_inst/De_vcnt_11_s1/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT NET NAME WORST SLACK MAX DELAY
1457 rst_n1 15.441 2.378
941 sdi_phy_tx_clk 4.822 3.465
607 sdi_phy_rx_clk 5.211 2.597
288 sclk 14.435 2.118
105 rst_n2 16.211 2.668
54 hd_dot_cnt[1] 5.500 2.394
49 hd_match_phase[2] 9.472 2.175
43 V_cnt_14_16 9.702 0.799
43 hd_dot_cnt[0] 5.846 2.516
41 crc_ready_d2 9.997 2.126

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC ROUTE CONGESTIONS
R32C38 63.89%
R43C34 63.89%
R41C58 62.50%
R43C35 62.50%
R44C34 61.11%
R35C53 61.11%
R40C48 59.72%
R31C34 58.33%
R32C34 58.33%
R44C32 58.33%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type State Detail Command
TC_CLOCK Actived create_clock -name sclk -period 20 -waveform {0 10} [get_nets {sclk}] -add
TC_CLOCK Actived create_clock -name sdi_phy_tx_clk -period 13.468 -waveform {0 6.734} [get_nets {sdi_phy_tx_clk}] -add
TC_CLOCK Actived create_clock -name sdi_phy_rx_clk -period 13.468 -waveform {0 6.734} [get_nets {sdi_phy_rx_clk}] -add
TC_FALSE_PATH Actived set_false_path -from [get_clocks {sclk}] -to [get_clocks {sdi_phy_tx_clk}]
TC_FALSE_PATH Actived set_false_path -from [get_clocks {sdi_phy_tx_clk}] -to [get_clocks {sclk}]
TC_FALSE_PATH Actived set_false_path -from [get_clocks {sclk}] -to [get_clocks {sdi_phy_rx_clk}]
TC_FALSE_PATH Actived set_false_path -from [get_clocks {sdi_phy_rx_clk}] -to [get_clocks {sclk}]