Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | C:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\SDIEncoder\data\sdi_encoder_top.v C:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\SDIEncoder\data\sdi_encoder_wrapper.v |
GowinSynthesis Constraints File | --- |
Tool Version | V1.9.11.01 (64-bit) |
Part Number | GW5AT-LV60PG484AES |
Device | GW5AT-60 |
Device Version | B |
Created Time | Mon Mar 10 11:25:41 2025 |
Legal Announcement | Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | SDI_Encoder_Top |
Synthesis Process | Running parser: CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.253s, Peak memory usage = 110.238MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 110.238MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.046s, Peak memory usage = 110.238MB Optimizing Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.032s, Peak memory usage = 110.238MB Optimizing Phase 2: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.05s, Peak memory usage = 110.238MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.015s, Peak memory usage = 110.238MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 110.238MB Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 110.238MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 110.238MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.057s, Peak memory usage = 110.238MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.017s, Peak memory usage = 110.238MB Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 110.238MB Tech-Mapping Phase 3: CPU time = 0h 0m 5s, Elapsed time = 0h 0m 5s, Peak memory usage = 136.121MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.148s, Peak memory usage = 136.121MB Generate output files: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.08s, Peak memory usage = 136.121MB |
Total Time and Memory Usage | CPU time = 0h 0m 5s, Elapsed time = 0h 0m 5s, Peak memory usage = 136.121MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 150 |
I/O Buf | 133 |
    IBUF | 53 |
    OBUF | 80 |
Register | 629 |
    DFFSE | 1 |
    DFFPE | 1 |
    DFFCE | 627 |
LUT | 1008 |
    LUT2 | 127 |
    LUT3 | 215 |
    LUT4 | 666 |
ALU | 53 |
    ALU | 53 |
SSRAM | 5 |
    RAM16S4 | 5 |
INV | 7 |
    INV | 7 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 1098(1015 LUT, 53 ALU, 5 RAM16) / 59904 | 2% |
Register | 629 / 60783 | 2% |
  --Register as Latch | 0 / 60783 | 0% |
  --Register as FF | 629 / 60783 | 2% |
BSRAM | 0 / 118 | 0% |
Timing
Clock Summary:
NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|---|
1 | I_clk | Base | 10.000 | 100.000 | 0.000 | 5.000 | I_clk_ibuf/I |
Max Frequency Summary:
NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | I_clk | 100.000(MHz) | 140.252(MHz) | 8 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | 2.870 |
Data Arrival Time | 7.441 |
Data Required Time | 10.311 |
From | sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_5_s0 |
To | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_8_s0 |
Launch Clk | I_clk[R] |
Latch Clk | I_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | I_clk | |||
0.000 | 0.000 | tCL | RR | 1 | I_clk_ibuf/I |
0.000 | 0.000 | tINS | RR | 634 | I_clk_ibuf/O |
0.375 | 0.375 | tNET | RR | 1 | sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_5_s0/CLK |
0.757 | 0.382 | tC2Q | RR | 15 | sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_5_s0/Q |
1.132 | 0.375 | tNET | RR | 1 | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1905_s50/I0 |
1.659 | 0.526 | tINS | RR | 4 | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1905_s50/F |
2.034 | 0.375 | tNET | RR | 1 | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1906_s19/I0 |
2.560 | 0.526 | tINS | RR | 37 | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1906_s19/F |
2.935 | 0.375 | tNET | RR | 1 | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1916_s26/I0 |
3.461 | 0.526 | tINS | RR | 2 | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1916_s26/F |
3.836 | 0.375 | tNET | RR | 1 | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1916_s14/I0 |
4.362 | 0.526 | tINS | RR | 1 | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1916_s14/F |
4.737 | 0.375 | tNET | RR | 1 | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1916_s5/I0 |
5.264 | 0.526 | tINS | RR | 2 | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1916_s5/F |
5.639 | 0.375 | tNET | RR | 1 | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1916_s1/I0 |
6.165 | 0.526 | tINS | RR | 1 | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1916_s1/F |
6.540 | 0.375 | tNET | RR | 1 | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1916_s0/I0 |
7.066 | 0.526 | tINS | RR | 1 | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1916_s0/F |
7.441 | 0.375 | tNET | RR | 1 | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_8_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | I_clk | |||
10.000 | 0.000 | tCL | RR | 1 | I_clk_ibuf/I |
10.000 | 0.000 | tINS | RR | 634 | I_clk_ibuf/O |
10.375 | 0.375 | tNET | RR | 1 | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_8_s0/CLK |
10.311 | -0.064 | tSu | 1 | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_8_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 8 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Arrival Data Path Delay: | cell: 3.684, 52.132%; route: 3.000, 42.455%; tC2Q: 0.382, 5.413% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 2
Path Summary:Slack | 2.880 |
Data Arrival Time | 7.431 |
Data Required Time | 10.311 |
From | sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_5_s0 |
To | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_16_s0 |
Launch Clk | I_clk[R] |
Latch Clk | I_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | I_clk | |||
0.000 | 0.000 | tCL | RR | 1 | I_clk_ibuf/I |
0.000 | 0.000 | tINS | RR | 634 | I_clk_ibuf/O |
0.375 | 0.375 | tNET | RR | 1 | sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_5_s0/CLK |
0.757 | 0.382 | tC2Q | RR | 15 | sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_5_s0/Q |
1.132 | 0.375 | tNET | RR | 1 | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1905_s50/I0 |
1.659 | 0.526 | tINS | RR | 4 | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1905_s50/F |
2.034 | 0.375 | tNET | RR | 1 | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1906_s19/I0 |
2.560 | 0.526 | tINS | RR | 37 | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1906_s19/F |
2.935 | 0.375 | tNET | RR | 1 | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1905_s96/I0 |
3.461 | 0.526 | tINS | RR | 38 | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1905_s96/F |
3.836 | 0.375 | tNET | RR | 1 | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1908_s13/I0 |
4.362 | 0.526 | tINS | RR | 1 | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1908_s13/F |
4.737 | 0.375 | tNET | RR | 1 | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1908_s5/I0 |
5.264 | 0.526 | tINS | RR | 6 | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1908_s5/F |
5.639 | 0.375 | tNET | RR | 1 | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1908_s1/I1 |
6.155 | 0.516 | tINS | RR | 1 | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1908_s1/F |
6.530 | 0.375 | tNET | RR | 1 | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1908_s0/I0 |
7.056 | 0.526 | tINS | RR | 1 | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1908_s0/F |
7.431 | 0.375 | tNET | RR | 1 | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_16_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | I_clk | |||
10.000 | 0.000 | tCL | RR | 1 | I_clk_ibuf/I |
10.000 | 0.000 | tINS | RR | 634 | I_clk_ibuf/O |
10.375 | 0.375 | tNET | RR | 1 | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_16_s0/CLK |
10.311 | -0.064 | tSu | 1 | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_16_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 8 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Arrival Data Path Delay: | cell: 3.674, 52.063%; route: 3.000, 42.516%; tC2Q: 0.382, 5.421% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 3
Path Summary:Slack | 2.880 |
Data Arrival Time | 7.431 |
Data Required Time | 10.311 |
From | sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/I_data_d1_0_s2 |
To | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_7_s0 |
Launch Clk | I_clk[R] |
Latch Clk | I_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | I_clk | |||
0.000 | 0.000 | tCL | RR | 1 | I_clk_ibuf/I |
0.000 | 0.000 | tINS | RR | 634 | I_clk_ibuf/O |
0.375 | 0.375 | tNET | RR | 1 | sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/I_data_d1_0_s2/CLK |
0.757 | 0.382 | tC2Q | RR | 13 | sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/I_data_d1_0_s2/Q |
1.132 | 0.375 | tNET | RR | 4 | sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/I_data_d1_0_s10/AD[0] |
1.659 | 0.526 | tINS | RR | 1 | sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/I_data_d1_0_s10/DO[3] |
2.034 | 0.375 | tNET | RR | 1 | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1917_s21/I0 |
2.560 | 0.526 | tINS | RR | 8 | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1917_s21/F |
2.935 | 0.375 | tNET | RR | 1 | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1917_s18/I0 |
3.461 | 0.526 | tINS | RR | 1 | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1917_s18/F |
3.836 | 0.375 | tNET | RR | 1 | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1917_s20/I0 |
4.362 | 0.526 | tINS | RR | 1 | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1917_s20/F |
4.737 | 0.375 | tNET | RR | 1 | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1917_s5/I0 |
5.264 | 0.526 | tINS | RR | 1 | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1917_s5/F |
5.639 | 0.375 | tNET | RR | 1 | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1917_s1/I1 |
6.155 | 0.516 | tINS | RR | 1 | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1917_s1/F |
6.530 | 0.375 | tNET | RR | 1 | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1917_s0/I0 |
7.056 | 0.526 | tINS | RR | 1 | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1917_s0/F |
7.431 | 0.375 | tNET | RR | 1 | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_7_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | I_clk | |||
10.000 | 0.000 | tCL | RR | 1 | I_clk_ibuf/I |
10.000 | 0.000 | tINS | RR | 634 | I_clk_ibuf/O |
10.375 | 0.375 | tNET | RR | 1 | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_7_s0/CLK |
10.311 | -0.064 | tSu | 1 | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_7_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 8 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Arrival Data Path Delay: | cell: 3.674, 52.063%; route: 3.000, 42.516%; tC2Q: 0.382, 5.421% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 4
Path Summary:Slack | 2.890 |
Data Arrival Time | 7.421 |
Data Required Time | 10.311 |
From | sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_2_s0 |
To | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_15_s0 |
Launch Clk | I_clk[R] |
Latch Clk | I_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | I_clk | |||
0.000 | 0.000 | tCL | RR | 1 | I_clk_ibuf/I |
0.000 | 0.000 | tINS | RR | 634 | I_clk_ibuf/O |
0.375 | 0.375 | tNET | RR | 1 | sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_2_s0/CLK |
0.757 | 0.382 | tC2Q | RR | 26 | sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_2_s0/Q |
1.132 | 0.375 | tNET | RR | 1 | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1905_s42/I0 |
1.659 | 0.526 | tINS | RR | 2 | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1905_s42/F |
2.034 | 0.375 | tNET | RR | 1 | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1905_s81/I0 |
2.560 | 0.526 | tINS | RR | 1 | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1905_s81/F |
2.935 | 0.375 | tNET | RR | 1 | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1905_s67/I0 |
3.461 | 0.526 | tINS | RR | 7 | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1905_s67/F |
3.836 | 0.375 | tNET | RR | 1 | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1909_s42/I0 |
4.362 | 0.526 | tINS | RR | 8 | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1909_s42/F |
4.737 | 0.375 | tNET | RR | 1 | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1909_s5/I1 |
5.254 | 0.516 | tINS | RR | 1 | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1909_s5/F |
5.629 | 0.375 | tNET | RR | 1 | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1909_s1/I1 |
6.145 | 0.516 | tINS | RR | 1 | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1909_s1/F |
6.520 | 0.375 | tNET | RR | 1 | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1909_s0/I0 |
7.046 | 0.526 | tINS | RR | 1 | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1909_s0/F |
7.421 | 0.375 | tNET | RR | 1 | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_15_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | I_clk | |||
10.000 | 0.000 | tCL | RR | 1 | I_clk_ibuf/I |
10.000 | 0.000 | tINS | RR | 634 | I_clk_ibuf/O |
10.375 | 0.375 | tNET | RR | 1 | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_15_s0/CLK |
10.311 | -0.064 | tSu | 1 | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_15_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 8 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Arrival Data Path Delay: | cell: 3.664, 51.996%; route: 3.000, 42.576%; tC2Q: 0.382, 5.428% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 5
Path Summary:Slack | 2.890 |
Data Arrival Time | 7.421 |
Data Required Time | 10.311 |
From | sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_2_s0 |
To | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_14_s0 |
Launch Clk | I_clk[R] |
Latch Clk | I_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | I_clk | |||
0.000 | 0.000 | tCL | RR | 1 | I_clk_ibuf/I |
0.000 | 0.000 | tINS | RR | 634 | I_clk_ibuf/O |
0.375 | 0.375 | tNET | RR | 1 | sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_2_s0/CLK |
0.757 | 0.382 | tC2Q | RR | 26 | sdi_encoder_wrapper_inst/tx_hd_cnt_gen_inst/dot_cnt_2_s0/Q |
1.132 | 0.375 | tNET | RR | 1 | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1905_s42/I0 |
1.659 | 0.526 | tINS | RR | 2 | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1905_s42/F |
2.034 | 0.375 | tNET | RR | 1 | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1905_s81/I0 |
2.560 | 0.526 | tINS | RR | 1 | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1905_s81/F |
2.935 | 0.375 | tNET | RR | 1 | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1905_s67/I0 |
3.461 | 0.526 | tINS | RR | 7 | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1905_s67/F |
3.836 | 0.375 | tNET | RR | 1 | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1909_s42/I0 |
4.362 | 0.526 | tINS | RR | 8 | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1909_s42/F |
4.737 | 0.375 | tNET | RR | 1 | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1910_s5/I1 |
5.254 | 0.516 | tINS | RR | 1 | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1910_s5/F |
5.629 | 0.375 | tNET | RR | 1 | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1910_s1/I1 |
6.145 | 0.516 | tINS | RR | 1 | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1910_s1/F |
6.520 | 0.375 | tNET | RR | 1 | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1910_s0/I0 |
7.046 | 0.526 | tINS | RR | 1 | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/n1910_s0/F |
7.421 | 0.375 | tNET | RR | 1 | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_14_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | I_clk | |||
10.000 | 0.000 | tCL | RR | 1 | I_clk_ibuf/I |
10.000 | 0.000 | tINS | RR | 634 | I_clk_ibuf/O |
10.375 | 0.375 | tNET | RR | 1 | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_14_s0/CLK |
10.311 | -0.064 | tSu | 1 | sdi_encoder_wrapper_inst/tx_hd_esl_insert_inst/data_ins_14_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 8 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Arrival Data Path Delay: | cell: 3.664, 51.996%; route: 3.000, 42.576%; tC2Q: 0.382, 5.428% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |