Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | C:\Users\itadmin\Desktop\Gowin_SDI_PHY_RefDesign\project\src\adv7513_iic_init.v C:\Users\itadmin\Desktop\Gowin_SDI_PHY_RefDesign\project\src\gowin_pll\gowin_pll.v C:\Users\itadmin\Desktop\Gowin_SDI_PHY_RefDesign\project\src\gowin_pll\sys_pll.v C:\Users\itadmin\Desktop\Gowin_SDI_PHY_RefDesign\project\src\i2c_master\i2c_master.v C:\Users\itadmin\Desktop\Gowin_SDI_PHY_RefDesign\project\src\key_debounceN.v C:\Users\itadmin\Desktop\Gowin_SDI_PHY_RefDesign\project\src\rgb_to_yc\rgb_yc422.v C:\Users\itadmin\Desktop\Gowin_SDI_PHY_RefDesign\project\src\sdi_decoder\sdi_decoder.v C:\Users\itadmin\Desktop\Gowin_SDI_PHY_RefDesign\project\src\sdi_encoder\sdi_encoder.v C:\Users\itadmin\Desktop\Gowin_SDI_PHY_RefDesign\project\src\serdes\sdi_phy\sdi_phy.v C:\Users\itadmin\Desktop\Gowin_SDI_PHY_RefDesign\project\src\serdes\serdes.v C:\Users\itadmin\Desktop\Gowin_SDI_PHY_RefDesign\project\src\testpattern.v C:\Users\itadmin\Desktop\Gowin_SDI_PHY_RefDesign\project\src\video_top.v C:\Users\itadmin\Desktop\Gowin_SDI_PHY_RefDesign\project\src\yc_to_rgb\yc422_rgb.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.11.01 (64-bit) |
| Part Number | GW5AT-LV60PG484AES |
| Device | GW5AT-60 |
| Device Version | B |
| Created Time | Mon Mar 10 15:13:21 2025 |
| Legal Announcement | Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | video_top |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.734s, Elapsed time = 0h 0m 0.765s, Peak memory usage = 224.973MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.145s, Peak memory usage = 224.973MB Optimizing Phase 1: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.076s, Peak memory usage = 224.973MB Optimizing Phase 2: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.153s, Peak memory usage = 224.973MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.053s, Peak memory usage = 224.973MB Inferring Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.026s, Peak memory usage = 224.973MB Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.014s, Peak memory usage = 224.973MB Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.019s, Peak memory usage = 224.973MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.213s, Peak memory usage = 224.973MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.056s, Peak memory usage = 224.973MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.021s, Peak memory usage = 224.973MB Tech-Mapping Phase 3: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 244.355MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.296s, Elapsed time = 0h 0m 0.375s, Peak memory usage = 244.355MB Generate output files: CPU time = 0h 0m 0.187s, Elapsed time = 0h 0m 0.196s, Peak memory usage = 244.355MB |
| Total Time and Memory Usage | CPU time = 0h 0m 4s, Elapsed time = 0h 0m 5s, Peak memory usage = 244.355MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 37 |
| I/O Buf | 36 |
| IBUF | 1 |
| OBUF | 32 |
| IOBUF | 2 |
| TLVDS_IBUF | 1 |
| Register | 1827 |
| DFFSE | 2 |
| DFFRE | 98 |
| DFFPE | 19 |
| DFFCE | 1708 |
| LUT | 2640 |
| LUT2 | 333 |
| LUT3 | 716 |
| LUT4 | 1591 |
| ALU | 412 |
| ALU | 412 |
| SSRAM | 6 |
| RAM16S4 | 5 |
| RAM16SDP2 | 1 |
| INV | 23 |
| INV | 23 |
| CLOCK | 2 |
| PLLA | 2 |
| GTR12_QUADA | 1 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 3111(2663 LUT, 412 ALU, 6 RAM16) / 59904 | 6% |
| Register | 1827 / 60783 | 4% |
| --Register as Latch | 0 / 60783 | 0% |
| --Register as FF | 1827 / 60783 | 4% |
| BSRAM | 0 / 118 | 0% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | I_clk_p | Base | 5.000 | 200.000 | 0.000 | 2.500 | IB_clk_inst/I | ||
| 2 | sys_pll_inst/PLLA_inst/CLKOUT0.default_gen_clk | Generated | 20.000 | 50.000 | 0.000 | 10.000 | IB_clk_inst/I | I_clk_p | sys_pll_inst/PLLA_inst/CLKOUT0 |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | sys_pll_inst/PLLA_inst/CLKOUT0.default_gen_clk | 50.000(MHz) | 162.503(MHz) | 7 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 13.846 |
| Data Arrival Time | 6.747 |
| Data Required Time | 20.593 |
| From | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/sd_time_cnt_7_s0 |
| To | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/current_state_0_s0 |
| Launch Clk | sys_pll_inst/PLLA_inst/CLKOUT0.default_gen_clk[R] |
| Latch Clk | sys_pll_inst/PLLA_inst/CLKOUT0.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | sys_pll_inst/PLLA_inst/CLKOUT0.default_gen_clk | |||
| 0.281 | 0.281 | tCL | RR | 288 | sys_pll_inst/PLLA_inst/CLKOUT0 |
| 0.656 | 0.375 | tNET | RR | 1 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/sd_time_cnt_7_s0/CLK |
| 1.039 | 0.382 | tC2Q | RR | 4 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/sd_time_cnt_7_s0/Q |
| 1.414 | 0.375 | tNET | RR | 1 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/next_state_0_s22/I0 |
| 1.940 | 0.526 | tINS | RR | 1 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/next_state_0_s22/F |
| 2.315 | 0.375 | tNET | RR | 1 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/next_state_0_s17/I1 |
| 2.832 | 0.516 | tINS | RR | 1 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/next_state_0_s17/F |
| 3.207 | 0.375 | tNET | RR | 1 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/next_state_0_s9/I2 |
| 3.668 | 0.461 | tINS | RR | 1 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/next_state_0_s9/F |
| 4.043 | 0.375 | tNET | RR | 1 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/next_state_0_s5/I0 |
| 4.569 | 0.526 | tINS | RR | 2 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/next_state_0_s5/F |
| 4.944 | 0.375 | tNET | RR | 1 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/next_state_0_s2/I0 |
| 5.470 | 0.526 | tINS | RR | 2 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/next_state_0_s2/F |
| 5.845 | 0.375 | tNET | RR | 1 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/next_state_0_s1/I0 |
| 6.372 | 0.526 | tINS | RR | 1 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/next_state_0_s1/F |
| 6.747 | 0.375 | tNET | RR | 1 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/current_state_0_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | sys_pll_inst/PLLA_inst/CLKOUT0.default_gen_clk | |||
| 20.281 | 0.281 | tCL | RR | 288 | sys_pll_inst/PLLA_inst/CLKOUT0 |
| 20.656 | 0.375 | tNET | RR | 1 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/current_state_0_s0/CLK |
| 20.593 | -0.064 | tSu | 1 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/current_state_0_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 7 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
| Arrival Data Path Delay: | cell: 3.082, 50.616%; route: 2.625, 43.103%; tC2Q: 0.382, 6.281% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 2
Path Summary:| Slack | 13.846 |
| Data Arrival Time | 6.747 |
| Data Required Time | 20.593 |
| From | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/sd_time_cnt_7_s0 |
| To | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/current_state_2_s0 |
| Launch Clk | sys_pll_inst/PLLA_inst/CLKOUT0.default_gen_clk[R] |
| Latch Clk | sys_pll_inst/PLLA_inst/CLKOUT0.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | sys_pll_inst/PLLA_inst/CLKOUT0.default_gen_clk | |||
| 0.281 | 0.281 | tCL | RR | 288 | sys_pll_inst/PLLA_inst/CLKOUT0 |
| 0.656 | 0.375 | tNET | RR | 1 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/sd_time_cnt_7_s0/CLK |
| 1.039 | 0.382 | tC2Q | RR | 4 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/sd_time_cnt_7_s0/Q |
| 1.414 | 0.375 | tNET | RR | 1 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/next_state_0_s22/I0 |
| 1.940 | 0.526 | tINS | RR | 1 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/next_state_0_s22/F |
| 2.315 | 0.375 | tNET | RR | 1 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/next_state_0_s17/I1 |
| 2.832 | 0.516 | tINS | RR | 1 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/next_state_0_s17/F |
| 3.207 | 0.375 | tNET | RR | 1 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/next_state_0_s9/I2 |
| 3.668 | 0.461 | tINS | RR | 1 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/next_state_0_s9/F |
| 4.043 | 0.375 | tNET | RR | 1 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/next_state_0_s5/I0 |
| 4.569 | 0.526 | tINS | RR | 2 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/next_state_0_s5/F |
| 4.944 | 0.375 | tNET | RR | 1 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/next_state_0_s2/I0 |
| 5.470 | 0.526 | tINS | RR | 2 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/next_state_0_s2/F |
| 5.845 | 0.375 | tNET | RR | 1 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/next_state_2_s1/I0 |
| 6.372 | 0.526 | tINS | RR | 1 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/next_state_2_s1/F |
| 6.747 | 0.375 | tNET | RR | 1 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/current_state_2_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | sys_pll_inst/PLLA_inst/CLKOUT0.default_gen_clk | |||
| 20.281 | 0.281 | tCL | RR | 288 | sys_pll_inst/PLLA_inst/CLKOUT0 |
| 20.656 | 0.375 | tNET | RR | 1 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/current_state_2_s0/CLK |
| 20.593 | -0.064 | tSu | 1 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/current_state_2_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 7 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
| Arrival Data Path Delay: | cell: 3.082, 50.616%; route: 2.625, 43.103%; tC2Q: 0.382, 6.281% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 3
Path Summary:| Slack | 13.911 |
| Data Arrival Time | 6.681 |
| Data Required Time | 20.593 |
| From | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/sd_time_cnt_7_s0 |
| To | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/current_state_1_s0 |
| Launch Clk | sys_pll_inst/PLLA_inst/CLKOUT0.default_gen_clk[R] |
| Latch Clk | sys_pll_inst/PLLA_inst/CLKOUT0.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | sys_pll_inst/PLLA_inst/CLKOUT0.default_gen_clk | |||
| 0.281 | 0.281 | tCL | RR | 288 | sys_pll_inst/PLLA_inst/CLKOUT0 |
| 0.656 | 0.375 | tNET | RR | 1 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/sd_time_cnt_7_s0/CLK |
| 1.039 | 0.382 | tC2Q | RR | 4 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/sd_time_cnt_7_s0/Q |
| 1.414 | 0.375 | tNET | RR | 1 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/next_state_0_s22/I0 |
| 1.940 | 0.526 | tINS | RR | 1 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/next_state_0_s22/F |
| 2.315 | 0.375 | tNET | RR | 1 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/next_state_0_s17/I1 |
| 2.832 | 0.516 | tINS | RR | 1 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/next_state_0_s17/F |
| 3.207 | 0.375 | tNET | RR | 1 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/next_state_0_s9/I2 |
| 3.668 | 0.461 | tINS | RR | 1 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/next_state_0_s9/F |
| 4.043 | 0.375 | tNET | RR | 1 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/next_state_0_s5/I0 |
| 4.569 | 0.526 | tINS | RR | 2 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/next_state_0_s5/F |
| 4.944 | 0.375 | tNET | RR | 1 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/next_state_1_s3/I0 |
| 5.470 | 0.526 | tINS | RR | 1 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/next_state_1_s3/F |
| 5.845 | 0.375 | tNET | RR | 1 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/next_state_1_s1/I2 |
| 6.306 | 0.461 | tINS | RR | 1 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/next_state_1_s1/F |
| 6.681 | 0.375 | tNET | RR | 1 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/current_state_1_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | sys_pll_inst/PLLA_inst/CLKOUT0.default_gen_clk | |||
| 20.281 | 0.281 | tCL | RR | 288 | sys_pll_inst/PLLA_inst/CLKOUT0 |
| 20.656 | 0.375 | tNET | RR | 1 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/current_state_1_s0/CLK |
| 20.593 | -0.064 | tSu | 1 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/current_state_1_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 7 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
| Arrival Data Path Delay: | cell: 3.018, 50.083%; route: 2.625, 43.568%; tC2Q: 0.382, 6.349% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 4
Path Summary:| Slack | 14.175 |
| Data Arrival Time | 6.418 |
| Data Required Time | 20.593 |
| From | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/sd_time_cnt_1_s0 |
| To | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/sd_time_cnt_26_s0 |
| Launch Clk | sys_pll_inst/PLLA_inst/CLKOUT0.default_gen_clk[R] |
| Latch Clk | sys_pll_inst/PLLA_inst/CLKOUT0.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | sys_pll_inst/PLLA_inst/CLKOUT0.default_gen_clk | |||
| 0.281 | 0.281 | tCL | RR | 288 | sys_pll_inst/PLLA_inst/CLKOUT0 |
| 0.656 | 0.375 | tNET | RR | 1 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/sd_time_cnt_1_s0/CLK |
| 1.039 | 0.382 | tC2Q | RR | 4 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/sd_time_cnt_1_s0/Q |
| 1.414 | 0.375 | tNET | RR | 1 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n231_s2/I0 |
| 1.940 | 0.526 | tINS | RR | 3 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n231_s2/F |
| 2.315 | 0.375 | tNET | RR | 1 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n229_s2/I2 |
| 2.776 | 0.461 | tINS | RR | 4 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n229_s2/F |
| 3.151 | 0.375 | tNET | RR | 1 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n227_s2/I2 |
| 3.613 | 0.461 | tINS | RR | 2 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n227_s2/F |
| 3.988 | 0.375 | tNET | RR | 1 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n222_s2/I3 |
| 4.250 | 0.262 | tINS | RR | 7 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n222_s2/F |
| 4.625 | 0.375 | tNET | RR | 1 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n211_s2/I1 |
| 5.141 | 0.516 | tINS | RR | 3 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n211_s2/F |
| 5.516 | 0.375 | tNET | RR | 1 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n209_s1/I0 |
| 6.043 | 0.526 | tINS | RR | 1 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n209_s1/F |
| 6.418 | 0.375 | tNET | RR | 1 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/sd_time_cnt_26_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | sys_pll_inst/PLLA_inst/CLKOUT0.default_gen_clk | |||
| 20.281 | 0.281 | tCL | RR | 288 | sys_pll_inst/PLLA_inst/CLKOUT0 |
| 20.656 | 0.375 | tNET | RR | 1 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/sd_time_cnt_26_s0/CLK |
| 20.593 | -0.064 | tSu | 1 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/sd_time_cnt_26_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 7 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
| Arrival Data Path Delay: | cell: 2.754, 47.798%; route: 2.625, 45.563%; tC2Q: 0.382, 6.639% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 5
Path Summary:| Slack | 14.185 |
| Data Arrival Time | 6.408 |
| Data Required Time | 20.593 |
| From | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/sd_time_cnt_1_s0 |
| To | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/sd_time_cnt_24_s0 |
| Launch Clk | sys_pll_inst/PLLA_inst/CLKOUT0.default_gen_clk[R] |
| Latch Clk | sys_pll_inst/PLLA_inst/CLKOUT0.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | sys_pll_inst/PLLA_inst/CLKOUT0.default_gen_clk | |||
| 0.281 | 0.281 | tCL | RR | 288 | sys_pll_inst/PLLA_inst/CLKOUT0 |
| 0.656 | 0.375 | tNET | RR | 1 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/sd_time_cnt_1_s0/CLK |
| 1.039 | 0.382 | tC2Q | RR | 4 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/sd_time_cnt_1_s0/Q |
| 1.414 | 0.375 | tNET | RR | 1 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n231_s2/I0 |
| 1.940 | 0.526 | tINS | RR | 3 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n231_s2/F |
| 2.315 | 0.375 | tNET | RR | 1 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n229_s2/I2 |
| 2.776 | 0.461 | tINS | RR | 4 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n229_s2/F |
| 3.151 | 0.375 | tNET | RR | 1 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n227_s2/I2 |
| 3.613 | 0.461 | tINS | RR | 2 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n227_s2/F |
| 3.988 | 0.375 | tNET | RR | 1 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n222_s2/I3 |
| 4.250 | 0.262 | tINS | RR | 7 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n222_s2/F |
| 4.625 | 0.375 | tNET | RR | 1 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n211_s2/I1 |
| 5.141 | 0.516 | tINS | RR | 3 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n211_s2/F |
| 5.516 | 0.375 | tNET | RR | 1 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n211_s1/I1 |
| 6.033 | 0.516 | tINS | RR | 1 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/n211_s1/F |
| 6.408 | 0.375 | tNET | RR | 1 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/sd_time_cnt_24_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | sys_pll_inst/PLLA_inst/CLKOUT0.default_gen_clk | |||
| 20.281 | 0.281 | tCL | RR | 288 | sys_pll_inst/PLLA_inst/CLKOUT0 |
| 20.656 | 0.375 | tNET | RR | 1 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/sd_time_cnt_24_s0/CLK |
| 20.593 | -0.064 | tSu | 1 | SDI_Decoder_Top_inst/sdi_decoder_wrapper_inst/rx_data_align_inst/sd_time_cnt_24_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 7 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
| Arrival Data Path Delay: | cell: 2.744, 47.707%; route: 2.625, 45.642%; tC2Q: 0.382, 6.651% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |