Timing Messages

Report Title Timing Analysis Report
Design File E:\myWork\IP\releaseVerify\RefDesign\1.9.9Beta-6\refDesign\Gowin_SDI_RefDesign_231025_t1_720_60p\project\impl\gwsynthesis\dk_video.vg
Physical Constraints File E:\myWork\IP\releaseVerify\RefDesign\1.9.9Beta-6\refDesign\Gowin_SDI_RefDesign_231025_t1_720_60p\project\src\dk_video.cst
Timing Constraint File E:\myWork\IP\releaseVerify\RefDesign\1.9.9Beta-6\refDesign\Gowin_SDI_RefDesign_231025_t1_720_60p\project\src\dk_video.sdc
Version V1.9.9 Beta-6
Part Number GW5AST-LV138FPG676AES
Device GW5AST-138B
Device Version B
Created Time Fri Oct 27 10:50:37 2023
Legal Announcement Copyright (C)2014-2023 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model Slow 0.85V -40C ES
Hold Delay Model Fast 0.95V 100C ES
Numbers of Paths Analyzed 4045
Numbers of Endpoints Analyzed 5624
Numbers of Falling Endpoints 0
Numbers of Setup Violated Endpoints 0
Numbers of Hold Violated Endpoints 0

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Objects
O_led Base 10.000 100.000 0.000 5.000 O_led_d_0[2]
lane3_pcs_tx_o_fabric_clk Base 13.468 74.250 0.000 6.734 lane3_pcs_tx_o_fabric_clk
O_adv7513_clk Base 13.468 74.250 0.000 6.734 O_adv7513_clk O_adv7513_clk_d
sclk Base 20.000 50.000 0.000 10.000 sclk
I_clk Base 20.000 50.000 0.000 10.000 I_clk

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 O_led 100.000(MHz) 1084.378(MHz) 2 TOP
2 lane3_pcs_tx_o_fabric_clk 74.250(MHz) 76.216(MHz) 8 TOP
3 O_adv7513_clk 74.250(MHz) 108.792(MHz) 8 TOP
4 sclk 50.000(MHz) 122.012(MHz) 2 TOP

No timing paths to get frequency of I_clk!

Total Negative Slack Summary:

Clock Name Analysis Type Endpoints TNS Number of Endpoints
O_led Setup 0.000 0
O_led Hold 0.000 0
lane3_pcs_tx_o_fabric_clk Setup 0.000 0
lane3_pcs_tx_o_fabric_clk Hold 0.000 0
O_adv7513_clk Setup 0.000 0
O_adv7513_clk Hold 0.000 0
sclk Setup 0.000 0
sclk Hold 0.000 0
I_clk Setup 0.000 0
I_clk Hold 0.000 0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.347 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0/Q Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_0_s0/D lane3_pcs_tx_o_fabric_clk:[R] lane3_pcs_tx_o_fabric_clk:[R] 13.468 -0.038 13.095
2 0.783 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0/Q Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_17_s0/D lane3_pcs_tx_o_fabric_clk:[R] lane3_pcs_tx_o_fabric_clk:[R] 13.468 -0.023 12.645
3 1.202 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0/Q Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_1_s0/D lane3_pcs_tx_o_fabric_clk:[R] lane3_pcs_tx_o_fabric_clk:[R] 13.468 -0.038 12.240
4 1.202 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0/Q Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_10_s0/D lane3_pcs_tx_o_fabric_clk:[R] lane3_pcs_tx_o_fabric_clk:[R] 13.468 -0.038 12.240
5 1.327 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0/Q Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_18_s0/D lane3_pcs_tx_o_fabric_clk:[R] lane3_pcs_tx_o_fabric_clk:[R] 13.468 -0.055 12.132
6 1.363 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0/Q Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_13_s0/D lane3_pcs_tx_o_fabric_clk:[R] lane3_pcs_tx_o_fabric_clk:[R] 13.468 -0.048 12.089
7 1.417 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0/Q Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_12_s0/D lane3_pcs_tx_o_fabric_clk:[R] lane3_pcs_tx_o_fabric_clk:[R] 13.468 -0.045 12.032
8 1.423 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0/Q Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_11_s0/D lane3_pcs_tx_o_fabric_clk:[R] lane3_pcs_tx_o_fabric_clk:[R] 13.468 -0.048 12.029
9 1.454 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0/Q Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_16_s0/D lane3_pcs_tx_o_fabric_clk:[R] lane3_pcs_tx_o_fabric_clk:[R] 13.468 -0.047 11.997
10 1.492 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0/Q Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_8_s0/D lane3_pcs_tx_o_fabric_clk:[R] lane3_pcs_tx_o_fabric_clk:[R] 13.468 -0.033 11.945
11 1.614 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0/Q Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_9_s0/D lane3_pcs_tx_o_fabric_clk:[R] lane3_pcs_tx_o_fabric_clk:[R] 13.468 -0.029 11.819
12 1.780 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0/Q Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_7_s0/D lane3_pcs_tx_o_fabric_clk:[R] lane3_pcs_tx_o_fabric_clk:[R] 13.468 -0.053 11.677
13 1.899 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/next_state_0_s3/I3 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/current_state_0_s0/D O_led:[F] sclk:[R] 5.000 -2.636 5.639
14 1.940 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0/Q Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_4_s0/D lane3_pcs_tx_o_fabric_clk:[R] lane3_pcs_tx_o_fabric_clk:[R] 13.468 -0.040 11.505
15 1.966 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0/Q Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_19_s0/D lane3_pcs_tx_o_fabric_clk:[R] lane3_pcs_tx_o_fabric_clk:[R] 13.468 -0.057 11.495
16 1.982 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0/Q Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_3_s0/D lane3_pcs_tx_o_fabric_clk:[R] lane3_pcs_tx_o_fabric_clk:[R] 13.468 -0.029 11.458
17 2.080 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0/Q Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_14_s0/D lane3_pcs_tx_o_fabric_clk:[R] lane3_pcs_tx_o_fabric_clk:[R] 13.468 -0.031 11.355
18 2.285 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0/Q Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_6_s0/D lane3_pcs_tx_o_fabric_clk:[R] lane3_pcs_tx_o_fabric_clk:[R] 13.468 -0.048 11.167
19 2.420 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0/Q Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_2_s0/D lane3_pcs_tx_o_fabric_clk:[R] lane3_pcs_tx_o_fabric_clk:[R] 13.468 -0.057 11.041
20 2.472 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/next_state_1_s1/I3 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/current_state_1_s0/D O_led:[F] sclk:[R] 5.000 -2.655 5.084
21 2.472 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/next_state_2_s1/I3 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/current_state_2_s0/D O_led:[F] sclk:[R] 5.000 -2.655 5.084
22 2.595 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/next_state_3_s1/I1 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/current_state_3_s0/D O_led:[F] sclk:[R] 5.000 -2.655 4.961
23 2.799 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0/Q Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_5_s0/D lane3_pcs_tx_o_fabric_clk:[R] lane3_pcs_tx_o_fabric_clk:[R] 13.468 -0.038 10.644
24 3.160 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0/Q Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_15_s0/D lane3_pcs_tx_o_fabric_clk:[R] lane3_pcs_tx_o_fabric_clk:[R] 13.468 -0.048 10.292
25 4.276 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/rx_data_d2_15_s0/Q Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_align_phase_1_s0/CE O_adv7513_clk:[R] O_adv7513_clk:[R] 13.468 -0.031 8.911

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.321 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_hd_data_extract_inst/I_data20_d1_10_s10/DO[1] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_hd_data_extract_inst/I_data20_d3_15_s0/D O_adv7513_clk:[R] O_adv7513_clk:[R] 0.000 -0.005 0.733
2 0.374 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_hd_data_extract_inst/I_data20_d1_10_s2/Q Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_hd_data_extract_inst/I_data20_d1_10_s2/D O_adv7513_clk:[R] O_adv7513_clk:[R] 0.000 0.000 0.375
3 0.374 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_hd_data_extract_inst/dot_cnt_9_s0/Q Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_hd_data_extract_inst/dot_cnt_9_s0/D O_adv7513_clk:[R] O_adv7513_clk:[R] 0.000 0.000 0.375
4 0.374 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/drp_cnt_0_s2/Q Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/drp_cnt_0_s2/D sclk:[R] sclk:[R] 0.000 0.000 0.375
5 0.374 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/drp_cnt_3_s4/Q Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/drp_cnt_3_s4/D sclk:[R] sclk:[R] 0.000 0.000 0.375
6 0.374 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_check_phase_0_s1/Q Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_check_phase_0_s1/D O_adv7513_clk:[R] O_adv7513_clk:[R] 0.000 0.000 0.375
7 0.374 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_check_phase_3_s1/Q Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_check_phase_3_s1/D O_adv7513_clk:[R] O_adv7513_clk:[R] 0.000 0.000 0.375
8 0.374 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/match_cnt_1_s1/Q Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/match_cnt_1_s1/D O_adv7513_clk:[R] O_adv7513_clk:[R] 0.000 0.000 0.375
9 0.374 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/mod_cnt_0_s1/Q Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/mod_cnt_0_s1/D sclk:[R] sclk:[R] 0.000 0.000 0.375
10 0.374 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/drp_cnt_1_s0/Q Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/drp_cnt_1_s0/D sclk:[R] sclk:[R] 0.000 0.000 0.375
11 0.374 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_2_s0/Q Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_2_s0/D sclk:[R] sclk:[R] 0.000 0.000 0.375
12 0.374 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_5_s0/Q Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_5_s0/D sclk:[R] sclk:[R] 0.000 0.000 0.375
13 0.374 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_15_s0/Q Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_15_s0/D sclk:[R] sclk:[R] 0.000 0.000 0.375
14 0.374 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_23_s0/Q Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_23_s0/D sclk:[R] sclk:[R] 0.000 0.000 0.375
15 0.374 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_26_s0/Q Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_26_s0/D sclk:[R] sclk:[R] 0.000 0.000 0.375
16 0.374 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_29_s0/Q Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_29_s0/D sclk:[R] sclk:[R] 0.000 0.000 0.375
17 0.374 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_0_s0/Q Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_0_s0/D sclk:[R] sclk:[R] 0.000 0.000 0.375
18 0.374 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_5_s0/Q Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_5_s0/D sclk:[R] sclk:[R] 0.000 0.000 0.375
19 0.374 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_10_s0/Q Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_10_s0/D sclk:[R] sclk:[R] 0.000 0.000 0.375
20 0.374 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_28_s0/Q Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_28_s0/D sclk:[R] sclk:[R] 0.000 0.000 0.375
21 0.374 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_29_s0/Q Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_29_s0/D sclk:[R] sclk:[R] 0.000 0.000 0.375
22 0.374 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_crc_inst/ycr1_9_s1/Q Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_crc_inst/ycr1_9_s1/D lane3_pcs_tx_o_fabric_clk:[R] lane3_pcs_tx_o_fabric_clk:[R] 0.000 0.000 0.375
23 0.374 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/de_cnt_0_s1/Q Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/de_cnt_0_s1/D lane3_pcs_tx_o_fabric_clk:[R] lane3_pcs_tx_o_fabric_clk:[R] 0.000 0.000 0.375
24 0.374 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/line_cnt_7_s1/Q Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/line_cnt_7_s1/D lane3_pcs_tx_o_fabric_clk:[R] lane3_pcs_tx_o_fabric_clk:[R] 0.000 0.000 0.375
25 0.374 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/vcnt_13_s1/Q Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/vcnt_13_s1/D lane3_pcs_tx_o_fabric_clk:[R] lane3_pcs_tx_o_fabric_clk:[R] 0.000 0.000 0.375

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 2.244 adv7513_iic_init_inst0/state_4_s0/CLEAR adv7513_iic_init_inst0/state_4_s0/CLEAR O_led:[F] sclk:[R] 5.000 -2.631 5.005
2 2.244 adv7513_iic_init_inst0/start_d2_s0/CLEAR adv7513_iic_init_inst0/start_d2_s0/CLEAR O_led:[F] sclk:[R] 5.000 -2.631 5.005
3 2.499 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_4_s0/CLEAR Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_4_s0/CLEAR O_led:[F] sclk:[R] 5.000 -2.668 4.786
4 2.499 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_7_s0/CLEAR Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_7_s0/CLEAR O_led:[F] sclk:[R] 5.000 -2.668 4.786
5 2.499 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_10_s0/CLEAR Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_10_s0/CLEAR O_led:[F] sclk:[R] 5.000 -2.668 4.786
6 2.511 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_1_s0/CLEAR Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_1_s0/CLEAR O_led:[F] sclk:[R] 5.000 -2.674 4.781
7 2.511 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_2_s0/CLEAR Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_2_s0/CLEAR O_led:[F] sclk:[R] 5.000 -2.674 4.781
8 2.511 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_3_s0/CLEAR Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_3_s0/CLEAR O_led:[F] sclk:[R] 5.000 -2.674 4.781
9 2.520 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_24_s0/CLEAR Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_24_s0/CLEAR O_led:[F] sclk:[R] 5.000 -2.684 4.781
10 2.520 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_25_s0/CLEAR Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_25_s0/CLEAR O_led:[F] sclk:[R] 5.000 -2.684 4.781
11 2.520 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_27_s0/CLEAR Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_27_s0/CLEAR O_led:[F] sclk:[R] 5.000 -2.684 4.781
12 2.522 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_0_s0/CLEAR Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_0_s0/CLEAR O_led:[F] sclk:[R] 5.000 -2.674 4.770
13 2.522 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_1_s0/CLEAR Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_1_s0/CLEAR O_led:[F] sclk:[R] 5.000 -2.674 4.770
14 2.522 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_2_s0/CLEAR Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_2_s0/CLEAR O_led:[F] sclk:[R] 5.000 -2.674 4.770
15 2.522 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_30_s0/CLEAR Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_30_s0/CLEAR O_led:[F] sclk:[R] 5.000 -2.674 4.770
16 2.522 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_31_s0/CLEAR Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_31_s0/CLEAR O_led:[F] sclk:[R] 5.000 -2.674 4.770
17 2.522 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_18_s0/CLEAR Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_18_s0/CLEAR O_led:[F] sclk:[R] 5.000 -2.674 4.770
18 2.522 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_19_s0/CLEAR Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_19_s0/CLEAR O_led:[F] sclk:[R] 5.000 -2.674 4.770
19 2.523 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_6_s0/CLEAR Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_6_s0/CLEAR O_led:[F] sclk:[R] 5.000 -2.677 4.772
20 2.523 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_8_s0/CLEAR Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_8_s0/CLEAR O_led:[F] sclk:[R] 5.000 -2.677 4.772
21 2.523 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_9_s0/CLEAR Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_9_s0/CLEAR O_led:[F] sclk:[R] 5.000 -2.677 4.772
22 2.528 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_24_s0/CLEAR Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_24_s0/CLEAR O_led:[F] sclk:[R] 5.000 -2.665 4.755
23 2.528 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_5_s0/CLEAR Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_5_s0/CLEAR O_led:[F] sclk:[R] 5.000 -2.665 4.755
24 2.529 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/current_state_3_s0/CLEAR Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/current_state_3_s0/CLEAR O_led:[F] sclk:[R] 5.000 -2.655 4.743
25 2.529 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/current_state_1_s0/CLEAR Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/current_state_1_s0/CLEAR O_led:[F] sclk:[R] 5.000 -2.655 4.743

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.539 rgb_yc422_inst/yc444_yc422_inst/n251_s1/I1 rgb_yc422_inst/yc444_yc422_inst/count_s6/CLEAR O_led:[R] O_led:[R] 0.000 -2.226 2.631
2 0.614 key_debounceN_inst0/key_n_out2_s1/Q I2C_MASTER_Top_inst0/u_i2c_master/byte_controller/c_state_2_s0/CLEAR sclk:[R] sclk:[R] 0.000 -0.008 0.434
3 0.614 key_debounceN_inst0/key_n_out2_s1/Q I2C_MASTER_Top_inst0/u_i2c_master/byte_controller/CORE_CMD_2_s0/CLEAR sclk:[R] sclk:[R] 0.000 -0.008 0.434
4 0.614 key_debounceN_inst0/key_n_out2_s1/Q I2C_MASTER_Top_inst0/u_i2c_master/byte_controller/CORE_CMD_3_s0/CLEAR sclk:[R] sclk:[R] 0.000 -0.008 0.434
5 0.618 key_debounceN_inst0/key_n_out2_s1/Q I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_15_s1/CLEAR sclk:[R] sclk:[R] 0.000 -0.010 0.439
6 0.618 key_debounceN_inst0/key_n_out2_s1/Q I2C_MASTER_Top_inst0/u_i2c_master/control_reg_7_s0/CLEAR sclk:[R] sclk:[R] 0.000 -0.010 0.439
7 0.618 key_debounceN_inst0/key_n_out2_s1/Q I2C_MASTER_Top_inst0/u_i2c_master/byte_controller/CORE_CMD_0_s1/CLEAR sclk:[R] sclk:[R] 0.000 -0.012 0.441
8 0.620 key_debounceN_inst0/key_n_out2_s1/Q I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_16_s1/CLEAR sclk:[R] sclk:[R] 0.000 -0.010 0.441
9 0.620 key_debounceN_inst0/key_n_out2_s1/Q I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/CMD_ACK_s0/CLEAR sclk:[R] sclk:[R] 0.000 -0.010 0.441
10 0.623 key_debounceN_inst0/key_n_out2_s1/Q I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_0_s1/CLEAR sclk:[R] sclk:[R] 0.000 -0.005 0.439
11 0.623 key_debounceN_inst0/key_n_out2_s1/Q I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_5_s1/CLEAR sclk:[R] sclk:[R] 0.000 -0.005 0.439
12 0.623 key_debounceN_inst0/key_n_out2_s1/Q I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_9_s1/CLEAR sclk:[R] sclk:[R] 0.000 -0.005 0.439
13 0.623 key_debounceN_inst0/key_n_out2_s1/Q I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_13_s1/CLEAR sclk:[R] sclk:[R] 0.000 -0.005 0.439
14 0.623 key_debounceN_inst0/key_n_out2_s1/Q I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_14_s1/CLEAR sclk:[R] sclk:[R] 0.000 -0.005 0.439
15 0.636 key_debounceN_inst0/key_n_out2_s1/Q I2C_MASTER_Top_inst0/u_i2c_master/prescale_reg0_7_s0/CLEAR sclk:[R] sclk:[R] 0.000 -0.001 0.449
16 0.636 key_debounceN_inst0/key_n_out2_s1/Q I2C_MASTER_Top_inst0/u_i2c_master/prescale_reg1_0_s0/CLEAR sclk:[R] sclk:[R] 0.000 -0.001 0.449
17 0.636 key_debounceN_inst0/key_n_out2_s1/Q I2C_MASTER_Top_inst0/u_i2c_master/prescale_reg1_7_s0/CLEAR sclk:[R] sclk:[R] 0.000 -0.001 0.449
18 0.636 key_debounceN_inst0/key_n_out2_s1/Q I2C_MASTER_Top_inst0/u_i2c_master/prescale_reg0_0_s0/CLEAR sclk:[R] sclk:[R] 0.000 -0.001 0.449
19 0.638 key_debounceN_inst0/key_n_out2_s1/Q I2C_MASTER_Top_inst0/u_i2c_master/prescale_reg1_2_s0/CLEAR sclk:[R] sclk:[R] 0.000 0.005 0.444
20 0.638 key_debounceN_inst0/key_n_out2_s1/Q I2C_MASTER_Top_inst0/u_i2c_master/prescale_reg1_3_s0/CLEAR sclk:[R] sclk:[R] 0.000 0.005 0.444
21 0.638 key_debounceN_inst0/key_n_out2_s1/Q I2C_MASTER_Top_inst0/u_i2c_master/prescale_reg1_4_s0/CLEAR sclk:[R] sclk:[R] 0.000 0.005 0.444
22 0.638 key_debounceN_inst0/key_n_out2_s1/Q I2C_MASTER_Top_inst0/u_i2c_master/prescale_reg1_5_s0/CLEAR sclk:[R] sclk:[R] 0.000 0.005 0.444
23 0.638 key_debounceN_inst0/key_n_out2_s1/Q I2C_MASTER_Top_inst0/u_i2c_master/prescale_reg1_6_s0/CLEAR sclk:[R] sclk:[R] 0.000 0.005 0.444
24 0.638 key_debounceN_inst0/key_n_out2_s1/Q I2C_MASTER_Top_inst0/u_i2c_master/prescale_reg0_5_s0/CLEAR sclk:[R] sclk:[R] 0.000 0.005 0.444
25 0.647 key_debounceN_inst0/key_n_out2_s1/Q I2C_MASTER_Top_inst0/u_i2c_master/prescale_reg0_1_s0/CLEAR sclk:[R] sclk:[R] 0.000 0.010 0.449

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number Slack Actual Width Required Width Type Clock Objects
1 5.110 5.360 0.250 High Pulse Width O_adv7513_clk yc422_rgb_inst/yc444_rgb_inst/r_o_6_s0
2 5.110 5.360 0.250 High Pulse Width O_adv7513_clk yc422_rgb_inst/yc444_rgb_inst/r_o_3_s0
3 5.110 5.360 0.250 High Pulse Width O_adv7513_clk yc422_rgb_inst/yc444_rgb_inst/g_o_0_s0
4 5.110 5.360 0.250 High Pulse Width O_adv7513_clk yc422_rgb_inst/yc444_rgb_inst/b_o_7_s0
5 5.110 5.360 0.250 High Pulse Width O_adv7513_clk yc422_rgb_inst/yc444_rgb_inst/vs_o_3_s0
6 5.115 5.365 0.250 High Pulse Width O_adv7513_clk yc422_rgb_inst/yc444_rgb_inst/dout_valid_s0
7 5.115 5.365 0.250 High Pulse Width O_adv7513_clk yc422_rgb_inst/yc444_rgb_inst/r_o_7_s0
8 5.115 5.365 0.250 High Pulse Width O_adv7513_clk yc422_rgb_inst/yc444_rgb_inst/hs_o_3_s0
9 5.115 5.365 0.250 High Pulse Width O_adv7513_clk yc422_rgb_inst/yc444_rgb_inst/r_o_4_s0
10 5.115 5.365 0.250 High Pulse Width O_adv7513_clk yc422_rgb_inst/yc444_rgb_inst/b_o_3_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 0.347
Data Arrival Time 15.719
Data Required Time 16.066
From Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0
To Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_0_s0
Launch Clk lane3_pcs_tx_o_fabric_clk:[R]
Latch Clk lane3_pcs_tx_o_fabric_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 lane3_pcs_tx_o_fabric_clk
0.000 0.000 tCL RR 1022 - Serdes_Top_inst/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
2.624 2.624 tNET RR 1 R48C118[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0/CLK
3.007 0.382 tC2Q RR 7 R48C118[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0/Q
4.679 1.673 tNET RR 1 R54C118[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1911_s25/I2
5.258 0.579 tINS RR 10 R54C118[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1911_s25/F
7.763 2.505 tNET RR 1 R56C124[3][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s60/I0
8.054 0.291 tINS RR 4 R56C124[3][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s60/F
9.192 1.138 tNET RR 1 R54C122[3][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s24/I2
9.483 0.291 tINS RR 3 R54C122[3][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s24/F
10.830 1.348 tNET RR 1 R58C119[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s10/I2
11.409 0.579 tINS RR 10 R58C119[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s10/F
12.640 1.231 tNET RR 1 R57C123[2][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1907_s12/I2
13.219 0.579 tINS RR 1 R57C123[2][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1907_s12/F
13.222 0.003 tNET RR 1 R57C123[3][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1907_s4/I0
13.769 0.548 tINS RR 5 R57C123[3][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1907_s4/F
15.152 1.383 tNET RR 1 R62C122[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1924_s0/I0
15.719 0.567 tINS RR 1 R62C122[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1924_s0/F
15.719 0.000 tNET RR 1 R62C122[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 lane3_pcs_tx_o_fabric_clk
13.468 0.000 tCL RR 1022 - Serdes_Top_inst/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
16.130 2.662 tNET RR 1 R62C122[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_0_s0/CLK
16.066 -0.064 tSu 1 R62C122[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_0_s0

Path Statistics:

Clock Skew 0.038
Setup Relationship 13.468
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.624, 100.000%
Arrival Data Path Delay cell: 3.434, 26.222%; route: 9.279, 70.857%; tC2Q: 0.382, 2.921%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.662, 100.000%

Path2

Path Summary:

Slack 0.783
Data Arrival Time 15.269
Data Required Time 16.052
From Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0
To Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_17_s0
Launch Clk lane3_pcs_tx_o_fabric_clk:[R]
Latch Clk lane3_pcs_tx_o_fabric_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 lane3_pcs_tx_o_fabric_clk
0.000 0.000 tCL RR 1022 - Serdes_Top_inst/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
2.624 2.624 tNET RR 1 R48C118[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0/CLK
3.007 0.382 tC2Q RR 7 R48C118[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0/Q
4.679 1.673 tNET RR 1 R54C118[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1911_s25/I2
5.258 0.579 tINS RR 10 R54C118[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1911_s25/F
7.763 2.505 tNET RR 1 R56C124[3][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s60/I0
8.054 0.291 tINS RR 4 R56C124[3][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s60/F
9.192 1.138 tNET RR 1 R54C122[3][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s24/I2
9.483 0.291 tINS RR 3 R54C122[3][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s24/F
10.830 1.348 tNET RR 1 R58C119[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s10/I2
11.409 0.579 tINS RR 10 R58C119[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s10/F
12.640 1.231 tNET RR 1 R57C123[2][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1907_s12/I2
13.219 0.579 tINS RR 1 R57C123[2][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1907_s12/F
13.222 0.003 tNET RR 1 R57C123[3][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1907_s4/I0
13.769 0.548 tINS RR 5 R57C123[3][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1907_s4/F
14.690 0.921 tNET RR 1 R54C124[2][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1907_s0/I3
15.269 0.579 tINS RR 1 R54C124[2][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1907_s0/F
15.269 0.000 tNET RR 1 R54C124[2][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_17_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 lane3_pcs_tx_o_fabric_clk
13.468 0.000 tCL RR 1022 - Serdes_Top_inst/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
16.116 2.648 tNET RR 1 R54C124[2][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_17_s0/CLK
16.052 -0.064 tSu 1 R54C124[2][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_17_s0

Path Statistics:

Clock Skew 0.023
Setup Relationship 13.468
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.624, 100.000%
Arrival Data Path Delay cell: 3.445, 27.244%; route: 8.818, 69.731%; tC2Q: 0.382, 3.025%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.648, 100.000%

Path3

Path Summary:

Slack 1.202
Data Arrival Time 14.864
Data Required Time 16.066
From Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0
To Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_1_s0
Launch Clk lane3_pcs_tx_o_fabric_clk:[R]
Latch Clk lane3_pcs_tx_o_fabric_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 lane3_pcs_tx_o_fabric_clk
0.000 0.000 tCL RR 1022 - Serdes_Top_inst/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
2.624 2.624 tNET RR 1 R48C118[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0/CLK
3.007 0.382 tC2Q RR 7 R48C118[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0/Q
4.679 1.673 tNET RR 1 R54C118[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1911_s25/I2
5.258 0.579 tINS RR 10 R54C118[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1911_s25/F
7.763 2.505 tNET RR 1 R56C124[3][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s60/I0
8.054 0.291 tINS RR 4 R56C124[3][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s60/F
9.192 1.138 tNET RR 1 R54C122[3][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s24/I2
9.483 0.291 tINS RR 3 R54C122[3][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s24/F
10.830 1.348 tNET RR 1 R58C119[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s10/I2
11.409 0.579 tINS RR 10 R58C119[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s10/F
12.640 1.231 tNET RR 1 R57C123[2][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1907_s12/I2
13.219 0.579 tINS RR 1 R57C123[2][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1907_s12/F
13.222 0.003 tNET RR 1 R57C123[3][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1907_s4/I0
13.769 0.548 tINS RR 5 R57C123[3][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1907_s4/F
14.575 0.806 tNET RR 1 R62C122[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1923_s0/I0
14.864 0.289 tINS RR 1 R62C122[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1923_s0/F
14.864 0.000 tNET RR 1 R62C122[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 lane3_pcs_tx_o_fabric_clk
13.468 0.000 tCL RR 1022 - Serdes_Top_inst/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
16.130 2.662 tNET RR 1 R62C122[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_1_s0/CLK
16.066 -0.064 tSu 1 R62C122[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_1_s0

Path Statistics:

Clock Skew 0.038
Setup Relationship 13.468
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.624, 100.000%
Arrival Data Path Delay cell: 3.155, 25.776%; route: 8.703, 71.099%; tC2Q: 0.382, 3.125%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.662, 100.000%

Path4

Path Summary:

Slack 1.202
Data Arrival Time 14.864
Data Required Time 16.066
From Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0
To Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_10_s0
Launch Clk lane3_pcs_tx_o_fabric_clk:[R]
Latch Clk lane3_pcs_tx_o_fabric_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 lane3_pcs_tx_o_fabric_clk
0.000 0.000 tCL RR 1022 - Serdes_Top_inst/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
2.624 2.624 tNET RR 1 R48C118[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0/CLK
3.007 0.382 tC2Q RR 7 R48C118[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0/Q
4.679 1.673 tNET RR 1 R54C118[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1911_s25/I2
5.258 0.579 tINS RR 10 R54C118[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1911_s25/F
7.763 2.505 tNET RR 1 R56C124[3][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s60/I0
8.054 0.291 tINS RR 4 R56C124[3][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s60/F
9.192 1.138 tNET RR 1 R54C122[3][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s24/I2
9.483 0.291 tINS RR 3 R54C122[3][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s24/F
10.830 1.348 tNET RR 1 R58C119[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s10/I2
11.409 0.579 tINS RR 10 R58C119[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s10/F
12.640 1.231 tNET RR 1 R57C123[2][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1907_s12/I2
13.219 0.579 tINS RR 1 R57C123[2][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1907_s12/F
13.222 0.003 tNET RR 1 R57C123[3][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1907_s4/I0
13.769 0.548 tINS RR 5 R57C123[3][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1907_s4/F
14.575 0.806 tNET RR 1 R62C122[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1914_s0/I0
14.864 0.289 tINS RR 1 R62C122[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1914_s0/F
14.864 0.000 tNET RR 1 R62C122[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_10_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 lane3_pcs_tx_o_fabric_clk
13.468 0.000 tCL RR 1022 - Serdes_Top_inst/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
16.130 2.662 tNET RR 1 R62C122[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_10_s0/CLK
16.066 -0.064 tSu 1 R62C122[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_10_s0

Path Statistics:

Clock Skew 0.038
Setup Relationship 13.468
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.624, 100.000%
Arrival Data Path Delay cell: 3.155, 25.776%; route: 8.703, 71.099%; tC2Q: 0.382, 3.125%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.662, 100.000%

Path5

Path Summary:

Slack 1.327
Data Arrival Time 14.757
Data Required Time 16.084
From Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0
To Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_18_s0
Launch Clk lane3_pcs_tx_o_fabric_clk:[R]
Latch Clk lane3_pcs_tx_o_fabric_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 lane3_pcs_tx_o_fabric_clk
0.000 0.000 tCL RR 1022 - Serdes_Top_inst/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
2.624 2.624 tNET RR 1 R48C118[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0/CLK
3.007 0.382 tC2Q RR 7 R48C118[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0/Q
4.679 1.673 tNET RR 1 R54C118[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1911_s25/I2
5.258 0.579 tINS RR 10 R54C118[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1911_s25/F
7.763 2.505 tNET RR 1 R56C124[3][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s60/I0
8.054 0.291 tINS RR 4 R56C124[3][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s60/F
9.192 1.138 tNET RR 1 R54C122[3][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s24/I2
9.483 0.291 tINS RR 3 R54C122[3][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s24/F
10.830 1.348 tNET RR 1 R58C119[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s10/I2
11.409 0.579 tINS RR 10 R58C119[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s10/F
11.565 0.156 tNET RR 1 R58C119[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1905_s11/I3
12.133 0.567 tINS RR 3 R58C119[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1905_s11/F
13.602 1.469 tNET RR 1 R57C124[3][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s2/I1
14.175 0.574 tINS RR 1 R57C124[3][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s2/F
14.178 0.003 tNET RR 1 R57C124[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s0/I1
14.757 0.579 tINS RR 1 R57C124[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s0/F
14.757 0.000 tNET RR 1 R57C124[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_18_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 lane3_pcs_tx_o_fabric_clk
13.468 0.000 tCL RR 1022 - Serdes_Top_inst/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
16.147 2.679 tNET RR 1 R57C124[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_18_s0/CLK
16.084 -0.064 tSu 1 R57C124[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_18_s0

Path Statistics:

Clock Skew 0.055
Setup Relationship 13.468
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.624, 100.000%
Arrival Data Path Delay cell: 3.460, 28.518%; route: 8.290, 68.329%; tC2Q: 0.382, 3.153%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.679, 100.000%

Path6

Path Summary:

Slack 1.363
Data Arrival Time 14.713
Data Required Time 16.076
From Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0
To Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_13_s0
Launch Clk lane3_pcs_tx_o_fabric_clk:[R]
Latch Clk lane3_pcs_tx_o_fabric_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 lane3_pcs_tx_o_fabric_clk
0.000 0.000 tCL RR 1022 - Serdes_Top_inst/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
2.624 2.624 tNET RR 1 R48C118[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0/CLK
3.007 0.382 tC2Q RR 7 R48C118[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0/Q
4.679 1.673 tNET RR 1 R54C118[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1911_s25/I2
5.258 0.579 tINS RR 10 R54C118[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1911_s25/F
7.763 2.505 tNET RR 1 R56C124[3][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s60/I0
8.054 0.291 tINS RR 4 R56C124[3][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s60/F
9.192 1.138 tNET RR 1 R54C122[3][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s24/I2
9.483 0.291 tINS RR 3 R54C122[3][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s24/F
10.830 1.348 tNET RR 1 R58C119[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s10/I2
11.409 0.579 tINS RR 10 R58C119[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s10/F
12.429 1.020 tNET RR 1 R62C122[3][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1911_s7/I1
12.748 0.319 tINS RF 2 R62C122[3][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1911_s7/F
13.160 0.412 tNET FF 1 R61C120[2][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1911_s2/I2
13.728 0.567 tINS FR 1 R61C120[2][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1911_s2/F
14.134 0.406 tNET RR 1 R60C118[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1911_s0/I1
14.713 0.579 tINS RR 1 R60C118[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1911_s0/F
14.713 0.000 tNET RR 1 R60C118[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_13_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 lane3_pcs_tx_o_fabric_clk
13.468 0.000 tCL RR 1022 - Serdes_Top_inst/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
16.140 2.672 tNET RR 1 R60C118[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_13_s0/CLK
16.076 -0.064 tSu 1 R60C118[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_13_s0

Path Statistics:

Clock Skew 0.048
Setup Relationship 13.468
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.624, 100.000%
Arrival Data Path Delay cell: 3.205, 26.512%; route: 8.501, 70.324%; tC2Q: 0.382, 3.164%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.672, 100.000%

Path7

Path Summary:

Slack 1.417
Data Arrival Time 14.657
Data Required Time 16.074
From Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0
To Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_12_s0
Launch Clk lane3_pcs_tx_o_fabric_clk:[R]
Latch Clk lane3_pcs_tx_o_fabric_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 lane3_pcs_tx_o_fabric_clk
0.000 0.000 tCL RR 1022 - Serdes_Top_inst/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
2.624 2.624 tNET RR 1 R48C118[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0/CLK
3.007 0.382 tC2Q RR 7 R48C118[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0/Q
4.679 1.673 tNET RR 1 R54C118[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1911_s25/I2
5.258 0.579 tINS RR 10 R54C118[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1911_s25/F
7.763 2.505 tNET RR 1 R56C124[3][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s60/I0
8.054 0.291 tINS RR 4 R56C124[3][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s60/F
9.192 1.138 tNET RR 1 R54C122[3][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s24/I2
9.483 0.291 tINS RR 3 R54C122[3][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s24/F
10.830 1.348 tNET RR 1 R58C119[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s10/I2
11.409 0.579 tINS RR 10 R58C119[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s10/F
12.223 0.814 tNET RR 1 R60C123[2][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1912_s7/I1
12.790 0.567 tINS RR 2 R60C123[2][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1912_s7/F
13.383 0.593 tNET RR 1 R61C120[2][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1912_s2/I2
13.962 0.579 tINS RR 1 R61C120[2][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1912_s2/F
14.368 0.406 tNET RR 1 R61C118[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1912_s0/I1
14.657 0.289 tINS RR 1 R61C118[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1912_s0/F
14.657 0.000 tNET RR 1 R61C118[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_12_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 lane3_pcs_tx_o_fabric_clk
13.468 0.000 tCL RR 1022 - Serdes_Top_inst/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
16.137 2.669 tNET RR 1 R61C118[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_12_s0/CLK
16.074 -0.064 tSu 1 R61C118[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_12_s0

Path Statistics:

Clock Skew 0.045
Setup Relationship 13.468
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.624, 100.000%
Arrival Data Path Delay cell: 3.175, 26.387%; route: 8.475, 70.434%; tC2Q: 0.382, 3.179%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.669, 100.000%

Path8

Path Summary:

Slack 1.423
Data Arrival Time 14.653
Data Required Time 16.076
From Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0
To Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_11_s0
Launch Clk lane3_pcs_tx_o_fabric_clk:[R]
Latch Clk lane3_pcs_tx_o_fabric_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 lane3_pcs_tx_o_fabric_clk
0.000 0.000 tCL RR 1022 - Serdes_Top_inst/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
2.624 2.624 tNET RR 1 R48C118[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0/CLK
3.007 0.382 tC2Q RR 7 R48C118[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0/Q
4.679 1.673 tNET RR 1 R54C118[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1911_s25/I2
5.258 0.579 tINS RR 10 R54C118[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1911_s25/F
7.763 2.505 tNET RR 1 R56C124[3][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s60/I0
8.054 0.291 tINS RR 4 R56C124[3][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s60/F
9.192 1.138 tNET RR 1 R54C122[3][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s24/I2
9.483 0.291 tINS RR 3 R54C122[3][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s24/F
10.830 1.348 tNET RR 1 R58C119[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s10/I2
11.409 0.579 tINS RR 10 R58C119[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s10/F
12.640 1.231 tNET RR 1 R57C123[2][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1907_s12/I2
13.219 0.579 tINS RR 1 R57C123[2][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1907_s12/F
13.222 0.003 tNET RR 1 R57C123[3][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1907_s4/I0
13.769 0.548 tINS RR 5 R57C123[3][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1907_s4/F
14.364 0.595 tNET RR 1 R60C122[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1913_s0/I0
14.653 0.289 tINS RR 1 R60C122[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1913_s0/F
14.653 0.000 tNET RR 1 R60C122[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_11_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 lane3_pcs_tx_o_fabric_clk
13.468 0.000 tCL RR 1022 - Serdes_Top_inst/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
16.140 2.672 tNET RR 1 R60C122[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_11_s0/CLK
16.076 -0.064 tSu 1 R60C122[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_11_s0

Path Statistics:

Clock Skew 0.048
Setup Relationship 13.468
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.624, 100.000%
Arrival Data Path Delay cell: 3.155, 26.229%; route: 8.491, 70.591%; tC2Q: 0.382, 3.180%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.672, 100.000%

Path9

Path Summary:

Slack 1.454
Data Arrival Time 14.622
Data Required Time 16.076
From Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0
To Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_16_s0
Launch Clk lane3_pcs_tx_o_fabric_clk:[R]
Latch Clk lane3_pcs_tx_o_fabric_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 lane3_pcs_tx_o_fabric_clk
0.000 0.000 tCL RR 1022 - Serdes_Top_inst/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
2.624 2.624 tNET RR 1 R48C118[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0/CLK
3.007 0.382 tC2Q RR 7 R48C118[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0/Q
4.679 1.673 tNET RR 1 R54C118[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1911_s25/I2
5.258 0.579 tINS RR 10 R54C118[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1911_s25/F
6.740 1.483 tNET RR 1 R56C122[1][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1913_s11/I0
7.248 0.507 tINS RR 3 R56C122[1][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1913_s11/F
7.673 0.425 tNET RR 1 R57C120[3][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1905_s46/I3
8.220 0.548 tINS RR 23 R57C120[3][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1905_s46/F
9.733 1.513 tNET RR 1 R56C124[3][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1905_s27/I2
10.280 0.548 tINS RR 4 R56C124[3][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1905_s27/F
11.862 1.581 tNET RR 1 R60C120[2][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1908_s11/I1
12.150 0.289 tINS RR 2 R60C120[2][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1908_s11/F
12.573 0.423 tNET RR 1 R60C123[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1908_s23/I0
13.152 0.579 tINS RR 1 R60C123[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1908_s23/F
13.533 0.381 tNET RR 1 R62C123[2][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1908_s3/I1
14.112 0.579 tINS RR 1 R62C123[2][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1908_s3/F
14.114 0.003 tNET RR 1 R62C123[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1908_s0/I2
14.622 0.507 tINS RR 1 R62C123[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1908_s0/F
14.622 0.000 tNET RR 1 R62C123[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_16_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 lane3_pcs_tx_o_fabric_clk
13.468 0.000 tCL RR 1022 - Serdes_Top_inst/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
16.140 2.672 tNET RR 1 R62C123[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_16_s0/CLK
16.076 -0.064 tSu 1 R62C123[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_16_s0

Path Statistics:

Clock Skew 0.047
Setup Relationship 13.468
Logic Level 9
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.624, 100.000%
Arrival Data Path Delay cell: 4.135, 34.466%; route: 7.480, 62.346%; tC2Q: 0.382, 3.188%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.672, 100.000%

Path10

Path Summary:

Slack 1.492
Data Arrival Time 14.569
Data Required Time 16.061
From Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0
To Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_8_s0
Launch Clk lane3_pcs_tx_o_fabric_clk:[R]
Latch Clk lane3_pcs_tx_o_fabric_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 lane3_pcs_tx_o_fabric_clk
0.000 0.000 tCL RR 1022 - Serdes_Top_inst/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
2.624 2.624 tNET RR 1 R48C118[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0/CLK
3.007 0.382 tC2Q RR 7 R48C118[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0/Q
4.679 1.673 tNET RR 1 R54C118[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1911_s25/I2
5.258 0.579 tINS RR 10 R54C118[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1911_s25/F
7.763 2.505 tNET RR 1 R56C124[3][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s60/I0
8.054 0.291 tINS RR 4 R56C124[3][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s60/F
9.192 1.138 tNET RR 1 R54C122[3][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s24/I2
9.483 0.291 tINS RR 3 R54C122[3][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s24/F
10.830 1.348 tNET RR 1 R58C119[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s10/I2
11.409 0.579 tINS RR 10 R58C119[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s10/F
12.844 1.435 tNET RR 1 R54C123[3][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1916_s24/I1
13.418 0.574 tINS RR 1 R54C123[3][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1916_s24/F
13.420 0.003 tNET RR 1 R54C123[1][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1916_s2/I3
13.999 0.579 tINS RR 1 R54C123[1][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1916_s2/F
14.002 0.003 tNET RR 1 R54C123[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1916_s0/I1
14.569 0.567 tINS RR 1 R54C123[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1916_s0/F
14.569 0.000 tNET RR 1 R54C123[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_8_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 lane3_pcs_tx_o_fabric_clk
13.468 0.000 tCL RR 1022 - Serdes_Top_inst/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
16.125 2.657 tNET RR 1 R54C123[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_8_s0/CLK
16.061 -0.064 tSu 1 R54C123[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_8_s0

Path Statistics:

Clock Skew 0.033
Setup Relationship 13.468
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.624, 100.000%
Arrival Data Path Delay cell: 3.460, 28.966%; route: 8.102, 67.832%; tC2Q: 0.382, 3.202%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.657, 100.000%

Path11

Path Summary:

Slack 1.614
Data Arrival Time 14.443
Data Required Time 16.057
From Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0
To Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_9_s0
Launch Clk lane3_pcs_tx_o_fabric_clk:[R]
Latch Clk lane3_pcs_tx_o_fabric_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 lane3_pcs_tx_o_fabric_clk
0.000 0.000 tCL RR 1022 - Serdes_Top_inst/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
2.624 2.624 tNET RR 1 R48C118[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0/CLK
3.007 0.382 tC2Q RR 7 R48C118[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0/Q
4.679 1.673 tNET RR 1 R54C118[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1911_s25/I2
5.258 0.579 tINS RR 10 R54C118[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1911_s25/F
7.763 2.505 tNET RR 1 R56C124[3][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s60/I0
8.054 0.291 tINS RR 4 R56C124[3][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s60/F
9.192 1.138 tNET RR 1 R54C122[3][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s24/I2
9.483 0.291 tINS RR 3 R54C122[3][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s24/F
10.830 1.348 tNET RR 1 R58C119[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s10/I2
11.409 0.579 tINS RR 10 R58C119[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s10/F
11.565 0.156 tNET RR 1 R58C119[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1905_s11/I3
12.133 0.567 tINS RR 3 R58C119[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1905_s11/F
12.975 0.843 tNET RR 1 R61C123[2][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1915_s1/I2
13.483 0.507 tINS RR 1 R61C123[2][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1915_s1/F
13.864 0.381 tNET RR 1 R62C125[2][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1915_s0/I0
14.443 0.579 tINS RR 1 R62C125[2][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1915_s0/F
14.443 0.000 tNET RR 1 R62C125[2][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_9_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 lane3_pcs_tx_o_fabric_clk
13.468 0.000 tCL RR 1022 - Serdes_Top_inst/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
16.121 2.653 tNET RR 1 R62C125[2][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_9_s0/CLK
16.057 -0.064 tSu 1 R62C125[2][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_9_s0

Path Statistics:

Clock Skew 0.029
Setup Relationship 13.468
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.624, 100.000%
Arrival Data Path Delay cell: 3.394, 28.715%; route: 8.043, 68.049%; tC2Q: 0.382, 3.236%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.653, 100.000%

Path12

Path Summary:

Slack 1.780
Data Arrival Time 14.302
Data Required Time 16.081
From Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0
To Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_7_s0
Launch Clk lane3_pcs_tx_o_fabric_clk:[R]
Latch Clk lane3_pcs_tx_o_fabric_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 lane3_pcs_tx_o_fabric_clk
0.000 0.000 tCL RR 1022 - Serdes_Top_inst/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
2.624 2.624 tNET RR 1 R48C118[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0/CLK
3.007 0.382 tC2Q RR 7 R48C118[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0/Q
4.679 1.673 tNET RR 1 R54C118[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1911_s25/I2
5.258 0.579 tINS RR 10 R54C118[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1911_s25/F
6.740 1.483 tNET RR 1 R56C122[1][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1913_s11/I0
7.248 0.507 tINS RR 3 R56C122[1][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1913_s11/F
7.673 0.425 tNET RR 1 R57C120[3][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1905_s46/I3
8.220 0.548 tINS RR 23 R57C120[3][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1905_s46/F
9.944 1.724 tNET RR 1 R56C125[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1907_s29/I1
10.512 0.567 tINS RR 7 R56C125[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1907_s29/F
11.532 1.020 tNET RR 1 R58C119[2][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1907_s16/I1
12.039 0.507 tINS RR 1 R58C119[2][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1907_s16/F
12.042 0.003 tNET RR 1 R58C119[2][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1907_s34/I3
12.620 0.579 tINS RR 2 R58C119[2][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1907_s34/F
13.213 0.593 tNET RR 1 R58C124[2][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1917_s2/I2
13.720 0.507 tINS RR 1 R58C124[2][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1917_s2/F
13.723 0.003 tNET RR 1 R58C124[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1917_s0/I1
14.302 0.579 tINS RR 1 R58C124[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1917_s0/F
14.302 0.000 tNET RR 1 R58C124[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_7_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 lane3_pcs_tx_o_fabric_clk
13.468 0.000 tCL RR 1022 - Serdes_Top_inst/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
16.145 2.677 tNET RR 1 R58C124[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_7_s0/CLK
16.081 -0.064 tSu 1 R58C124[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_7_s0

Path Statistics:

Clock Skew 0.053
Setup Relationship 13.468
Logic Level 9
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.624, 100.000%
Arrival Data Path Delay cell: 4.374, 37.455%; route: 6.921, 59.270%; tC2Q: 0.382, 3.276%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.677, 100.000%

Path13

Path Summary:

Slack 1.899
Data Arrival Time 20.639
Data Required Time 22.537
From Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/next_state_0_s3
To Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/current_state_0_s0
Launch Clk O_led:[F]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 O_led
15.000 0.000 tCL FF 1461 R51C98[0][A] key_debounceN_inst0/key_n_out1_s1/Q
19.490 4.490 tNET FF 1 R53C102[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/next_state_0_s3/I3
20.069 0.579 tINS FR 1 R53C102[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/next_state_0_s3/F
20.071 0.003 tNET RR 1 R53C102[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/next_state_0_s1/I3
20.639 0.567 tINS RR 1 R53C102[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/next_state_0_s1/F
20.639 0.000 tNET RR 1 R53C102[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/current_state_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 sclk
20.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
22.636 2.636 tNET RR 1 R53C102[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/current_state_0_s0/CLK
22.601 -0.035 tUnc Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/current_state_0_s0
22.538 -0.064 tSu 1 R53C102[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/current_state_0_s0

Path Statistics:

Clock Skew 2.636
Setup Relationship 5.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 1.146, 20.328%; route: 0.003, 0.044%; tC2Q: 4.490, 79.628%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.636, 100.000%

Path14

Path Summary:

Slack 1.940
Data Arrival Time 14.129
Data Required Time 16.069
From Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0
To Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_4_s0
Launch Clk lane3_pcs_tx_o_fabric_clk:[R]
Latch Clk lane3_pcs_tx_o_fabric_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 lane3_pcs_tx_o_fabric_clk
0.000 0.000 tCL RR 1022 - Serdes_Top_inst/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
2.624 2.624 tNET RR 1 R48C118[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0/CLK
3.007 0.382 tC2Q RR 7 R48C118[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0/Q
4.679 1.673 tNET RR 1 R54C118[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1911_s25/I2
5.258 0.579 tINS RR 10 R54C118[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1911_s25/F
7.763 2.505 tNET RR 1 R56C124[3][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s60/I0
8.054 0.291 tINS RR 4 R56C124[3][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s60/F
9.192 1.138 tNET RR 1 R54C122[3][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s24/I2
9.483 0.291 tINS RR 3 R54C122[3][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s24/F
10.830 1.348 tNET RR 1 R58C119[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s10/I2
11.409 0.579 tINS RR 10 R58C119[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s10/F
12.640 1.231 tNET RR 1 R63C123[3][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1910_s4/I1
12.959 0.319 tINS RF 2 R63C123[3][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1910_s4/F
12.969 0.010 tNET FF 1 R63C123[2][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1920_s2/I2
13.548 0.579 tINS FR 1 R63C123[2][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1920_s2/F
13.550 0.003 tNET RR 1 R63C123[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1920_s0/I1
14.129 0.579 tINS RR 1 R63C123[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1920_s0/F
14.129 0.000 tNET RR 1 R63C123[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_4_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 lane3_pcs_tx_o_fabric_clk
13.468 0.000 tCL RR 1022 - Serdes_Top_inst/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
16.132 2.664 tNET RR 1 R63C123[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_4_s0/CLK
16.069 -0.064 tSu 1 R63C123[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_4_s0

Path Statistics:

Clock Skew 0.040
Setup Relationship 13.468
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.624, 100.000%
Arrival Data Path Delay cell: 3.216, 27.955%; route: 7.906, 68.720%; tC2Q: 0.382, 3.325%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.664, 100.000%

Path15

Path Summary:

Slack 1.966
Data Arrival Time 14.119
Data Required Time 16.086
From Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0
To Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_19_s0
Launch Clk lane3_pcs_tx_o_fabric_clk:[R]
Latch Clk lane3_pcs_tx_o_fabric_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 lane3_pcs_tx_o_fabric_clk
0.000 0.000 tCL RR 1022 - Serdes_Top_inst/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
2.624 2.624 tNET RR 1 R48C118[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0/CLK
3.007 0.382 tC2Q RR 7 R48C118[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0/Q
4.679 1.673 tNET RR 1 R54C118[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1911_s25/I2
5.258 0.579 tINS RR 10 R54C118[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1911_s25/F
6.740 1.483 tNET RR 1 R56C122[1][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1913_s11/I0
7.248 0.507 tINS RR 3 R56C122[1][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1913_s11/F
7.673 0.425 tNET RR 1 R57C120[3][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1905_s46/I3
8.220 0.548 tINS RR 23 R57C120[3][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1905_s46/F
9.663 1.442 tNET RR 1 R59C125[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s67/I1
10.230 0.567 tINS RR 12 R59C125[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s67/F
10.408 0.177 tNET RR 1 R58C125[2][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1909_s6/I1
10.987 0.579 tINS RR 12 R58C125[2][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1909_s6/F
12.284 1.298 tNET RR 1 R61C119[3][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1905_s14/I1
12.858 0.574 tINS RR 1 R61C119[3][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1905_s14/F
12.860 0.003 tNET RR 1 R61C119[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1905_s4/I1
13.439 0.579 tINS RR 1 R61C119[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1905_s4/F
13.612 0.172 tNET RR 1 R60C119[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1905_s0/I3
14.119 0.507 tINS RR 1 R60C119[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1905_s0/F
14.119 0.000 tNET RR 1 R60C119[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_19_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 lane3_pcs_tx_o_fabric_clk
13.468 0.000 tCL RR 1022 - Serdes_Top_inst/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
16.149 2.681 tNET RR 1 R60C119[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_19_s0/CLK
16.086 -0.064 tSu 1 R60C119[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_19_s0

Path Statistics:

Clock Skew 0.057
Setup Relationship 13.468
Logic Level 9
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.624, 100.000%
Arrival Data Path Delay cell: 4.440, 38.625%; route: 6.673, 58.047%; tC2Q: 0.382, 3.328%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.681, 100.000%

Path16

Path Summary:

Slack 1.982
Data Arrival Time 14.082
Data Required Time 16.063
From Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0
To Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_3_s0
Launch Clk lane3_pcs_tx_o_fabric_clk:[R]
Latch Clk lane3_pcs_tx_o_fabric_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 lane3_pcs_tx_o_fabric_clk
0.000 0.000 tCL RR 1022 - Serdes_Top_inst/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
2.624 2.624 tNET RR 1 R48C118[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0/CLK
3.007 0.382 tC2Q RR 7 R48C118[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0/Q
4.679 1.673 tNET RR 1 R54C118[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1911_s25/I2
5.258 0.579 tINS RR 10 R54C118[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1911_s25/F
7.763 2.505 tNET RR 1 R56C124[3][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s60/I0
8.054 0.291 tINS RR 4 R56C124[3][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s60/F
9.192 1.138 tNET RR 1 R54C122[3][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s24/I2
9.483 0.291 tINS RR 3 R54C122[3][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s24/F
10.830 1.348 tNET RR 1 R58C119[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s10/I2
11.409 0.579 tINS RR 10 R58C119[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s10/F
12.429 1.020 tNET RR 1 R62C122[3][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1911_s7/I1
12.720 0.291 tINS RR 2 R62C122[3][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1911_s7/F
13.083 0.363 tNET RR 1 R62C124[2][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1921_s2/I2
13.590 0.507 tINS RR 1 R62C124[2][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1921_s2/F
13.763 0.172 tNET RR 1 R62C125[3][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1921_s0/I1
14.082 0.319 tINS RF 1 R62C125[3][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1921_s0/F
14.082 0.000 tNET FF 1 R62C125[3][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_3_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 lane3_pcs_tx_o_fabric_clk
13.468 0.000 tCL RR 1022 - Serdes_Top_inst/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
16.121 2.653 tNET RR 1 R62C125[3][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_3_s0/CLK
16.063 -0.058 tSu 1 R62C125[3][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_3_s0

Path Statistics:

Clock Skew 0.029
Setup Relationship 13.468
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.624, 100.000%
Arrival Data Path Delay cell: 2.857, 24.940%; route: 8.217, 71.722%; tC2Q: 0.382, 3.338%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.653, 100.000%

Path17

Path Summary:

Slack 2.080
Data Arrival Time 13.979
Data Required Time 16.059
From Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0
To Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_14_s0
Launch Clk lane3_pcs_tx_o_fabric_clk:[R]
Latch Clk lane3_pcs_tx_o_fabric_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 lane3_pcs_tx_o_fabric_clk
0.000 0.000 tCL RR 1022 - Serdes_Top_inst/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
2.624 2.624 tNET RR 1 R48C118[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0/CLK
3.007 0.382 tC2Q RR 7 R48C118[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0/Q
4.679 1.673 tNET RR 1 R54C118[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1911_s25/I2
5.258 0.579 tINS RR 10 R54C118[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1911_s25/F
7.763 2.505 tNET RR 1 R56C124[3][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s60/I0
8.054 0.291 tINS RR 4 R56C124[3][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s60/F
9.192 1.138 tNET RR 1 R54C122[3][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s24/I2
9.483 0.291 tINS RR 3 R54C122[3][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s24/F
10.830 1.348 tNET RR 1 R58C119[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s10/I2
11.409 0.579 tINS RR 10 R58C119[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s10/F
12.640 1.231 tNET RR 1 R63C123[3][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1910_s4/I1
12.959 0.319 tINS RF 2 R63C123[3][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1910_s4/F
13.120 0.161 tNET FF 1 R63C124[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1910_s1/I0
13.409 0.289 tINS FR 1 R63C124[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1910_s1/F
13.412 0.003 tNET RR 1 R63C124[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1910_s0/I0
13.979 0.567 tINS RR 1 R63C124[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1910_s0/F
13.979 0.000 tNET RR 1 R63C124[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_14_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 lane3_pcs_tx_o_fabric_clk
13.468 0.000 tCL RR 1022 - Serdes_Top_inst/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
16.123 2.655 tNET RR 1 R63C124[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_14_s0/CLK
16.059 -0.064 tSu 1 R63C124[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_14_s0

Path Statistics:

Clock Skew 0.031
Setup Relationship 13.468
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.624, 100.000%
Arrival Data Path Delay cell: 2.915, 25.672%; route: 8.057, 70.960%; tC2Q: 0.382, 3.369%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.655, 100.000%

Path18

Path Summary:

Slack 2.285
Data Arrival Time 13.792
Data Required Time 16.076
From Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0
To Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_6_s0
Launch Clk lane3_pcs_tx_o_fabric_clk:[R]
Latch Clk lane3_pcs_tx_o_fabric_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 lane3_pcs_tx_o_fabric_clk
0.000 0.000 tCL RR 1022 - Serdes_Top_inst/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
2.624 2.624 tNET RR 1 R48C118[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0/CLK
3.007 0.382 tC2Q RR 7 R48C118[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0/Q
4.679 1.673 tNET RR 1 R54C118[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1911_s25/I2
5.258 0.579 tINS RR 10 R54C118[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1911_s25/F
6.740 1.483 tNET RR 1 R56C122[1][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1913_s11/I0
7.248 0.507 tINS RR 3 R56C122[1][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1913_s11/F
7.673 0.425 tNET RR 1 R57C120[3][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1905_s46/I3
8.220 0.548 tINS RR 23 R57C120[3][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1905_s46/F
9.733 1.513 tNET RR 1 R56C124[3][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1905_s27/I2
10.280 0.548 tINS RR 4 R56C124[3][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1905_s27/F
11.862 1.581 tNET RR 1 R60C120[2][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1908_s11/I1
12.150 0.289 tINS RR 2 R60C120[2][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1908_s11/F
12.325 0.175 tNET RR 1 R60C119[3][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1918_s8/I1
12.644 0.319 tINS RF 1 R60C119[3][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1918_s8/F
12.825 0.181 tNET FF 1 R60C118[3][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1918_s3/I2
13.282 0.456 tINS FR 1 R60C118[3][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1918_s3/F
13.284 0.003 tNET RR 1 R60C118[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1918_s0/I2
13.792 0.507 tINS RR 1 R60C118[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1918_s0/F
13.792 0.000 tNET RR 1 R60C118[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_6_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 lane3_pcs_tx_o_fabric_clk
13.468 0.000 tCL RR 1022 - Serdes_Top_inst/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
16.140 2.672 tNET RR 1 R60C118[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_6_s0/CLK
16.076 -0.064 tSu 1 R60C118[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_6_s0

Path Statistics:

Clock Skew 0.048
Setup Relationship 13.468
Logic Level 9
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.624, 100.000%
Arrival Data Path Delay cell: 3.752, 33.602%; route: 7.033, 62.973%; tC2Q: 0.382, 3.425%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.672, 100.000%

Path19

Path Summary:

Slack 2.420
Data Arrival Time 13.665
Data Required Time 16.086
From Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0
To Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_2_s0
Launch Clk lane3_pcs_tx_o_fabric_clk:[R]
Latch Clk lane3_pcs_tx_o_fabric_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 lane3_pcs_tx_o_fabric_clk
0.000 0.000 tCL RR 1022 - Serdes_Top_inst/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
2.624 2.624 tNET RR 1 R48C118[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0/CLK
3.007 0.382 tC2Q RR 7 R48C118[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0/Q
4.679 1.673 tNET RR 1 R54C118[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1911_s25/I2
5.258 0.579 tINS RR 10 R54C118[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1911_s25/F
7.763 2.505 tNET RR 1 R56C124[3][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s60/I0
8.054 0.291 tINS RR 4 R56C124[3][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s60/F
9.192 1.138 tNET RR 1 R54C122[3][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s24/I2
9.483 0.291 tINS RR 3 R54C122[3][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s24/F
10.830 1.348 tNET RR 1 R58C119[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s10/I2
11.409 0.579 tINS RR 10 R58C119[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s10/F
12.223 0.814 tNET RR 1 R60C123[2][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1912_s7/I1
12.790 0.567 tINS RR 2 R60C123[2][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1912_s7/F
12.795 0.005 tNET RR 1 R60C123[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1922_s2/I2
13.374 0.579 tINS RR 1 R60C123[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1922_s2/F
13.377 0.003 tNET RR 1 R60C123[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1922_s0/I1
13.665 0.289 tINS RR 1 R60C123[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1922_s0/F
13.665 0.000 tNET RR 1 R60C123[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 lane3_pcs_tx_o_fabric_clk
13.468 0.000 tCL RR 1022 - Serdes_Top_inst/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
16.149 2.681 tNET RR 1 R60C123[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_2_s0/CLK
16.086 -0.064 tSu 1 R60C123[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_2_s0

Path Statistics:

Clock Skew 0.057
Setup Relationship 13.468
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.624, 100.000%
Arrival Data Path Delay cell: 3.175, 28.756%; route: 7.484, 67.780%; tC2Q: 0.382, 3.464%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.681, 100.000%

Path20

Path Summary:

Slack 2.472
Data Arrival Time 20.084
Data Required Time 22.556
From Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/next_state_1_s1
To Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/current_state_1_s0
Launch Clk O_led:[F]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 O_led
15.000 0.000 tCL FF 1461 R51C98[0][A] key_debounceN_inst0/key_n_out1_s1/Q
19.505 4.505 tNET FF 1 R53C100[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/next_state_1_s1/I3
20.084 0.579 tINS FR 1 R53C100[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/next_state_1_s1/F
20.084 0.000 tNET RR 1 R53C100[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/current_state_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 sclk
20.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
22.655 2.655 tNET RR 1 R53C100[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/current_state_1_s0/CLK
22.620 -0.035 tUnc Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/current_state_1_s0
22.556 -0.064 tSu 1 R53C100[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/current_state_1_s0

Path Statistics:

Clock Skew 2.655
Setup Relationship 5.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.579, 11.384%; route: 0.000, 0.000%; tC2Q: 4.505, 88.616%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.655, 100.000%

Path21

Path Summary:

Slack 2.472
Data Arrival Time 20.084
Data Required Time 22.556
From Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/next_state_2_s1
To Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/current_state_2_s0
Launch Clk O_led:[F]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 O_led
15.000 0.000 tCL FF 1461 R51C98[0][A] key_debounceN_inst0/key_n_out1_s1/Q
19.505 4.505 tNET FF 1 R53C100[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/next_state_2_s1/I3
20.084 0.579 tINS FR 1 R53C100[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/next_state_2_s1/F
20.084 0.000 tNET RR 1 R53C100[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/current_state_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 sclk
20.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
22.655 2.655 tNET RR 1 R53C100[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/current_state_2_s0/CLK
22.620 -0.035 tUnc Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/current_state_2_s0
22.556 -0.064 tSu 1 R53C100[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/current_state_2_s0

Path Statistics:

Clock Skew 2.655
Setup Relationship 5.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.579, 11.384%; route: 0.000, 0.000%; tC2Q: 4.505, 88.616%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.655, 100.000%

Path22

Path Summary:

Slack 2.595
Data Arrival Time 19.961
Data Required Time 22.556
From Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/next_state_3_s1
To Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/current_state_3_s0
Launch Clk O_led:[F]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 O_led
15.000 0.000 tCL FF 1461 R51C98[0][A] key_debounceN_inst0/key_n_out1_s1/Q
19.505 4.505 tNET FF 1 R53C100[3][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/next_state_3_s1/I1
19.961 0.456 tINS FR 1 R53C100[3][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/next_state_3_s1/F
19.961 0.000 tNET RR 1 R53C100[3][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/current_state_3_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 sclk
20.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
22.655 2.655 tNET RR 1 R53C100[3][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/current_state_3_s0/CLK
22.620 -0.035 tUnc Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/current_state_3_s0
22.556 -0.064 tSu 1 R53C100[3][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/current_state_3_s0

Path Statistics:

Clock Skew 2.655
Setup Relationship 5.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.456, 9.196%; route: 0.000, 0.000%; tC2Q: 4.505, 90.804%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.655, 100.000%

Path23

Path Summary:

Slack 2.799
Data Arrival Time 13.268
Data Required Time 16.067
From Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0
To Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_5_s0
Launch Clk lane3_pcs_tx_o_fabric_clk:[R]
Latch Clk lane3_pcs_tx_o_fabric_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 lane3_pcs_tx_o_fabric_clk
0.000 0.000 tCL RR 1022 - Serdes_Top_inst/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
2.624 2.624 tNET RR 1 R48C118[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0/CLK
3.007 0.382 tC2Q RR 7 R48C118[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0/Q
4.679 1.673 tNET RR 1 R54C118[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1911_s25/I2
5.258 0.579 tINS RR 10 R54C118[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1911_s25/F
7.763 2.505 tNET RR 1 R56C124[3][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s60/I0
8.054 0.291 tINS RR 4 R56C124[3][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s60/F
9.192 1.138 tNET RR 1 R54C122[3][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s24/I2
9.483 0.291 tINS RR 3 R54C122[3][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s24/F
10.237 0.754 tNET RR 1 R58C122[3][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1909_s11/I2
10.693 0.456 tINS RR 4 R58C122[3][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1909_s11/F
11.329 0.636 tNET RR 1 R61C124[1][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1909_s13/I0
11.908 0.579 tINS RR 1 R61C124[1][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1909_s13/F
12.080 0.172 tNET RR 1 R60C124[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1919_s2/I1
12.588 0.507 tINS RR 1 R60C124[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1919_s2/F
12.760 0.172 tNET RR 1 R60C125[2][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1919_s0/I1
13.268 0.507 tINS RR 1 R60C125[2][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1919_s0/F
13.268 0.000 tNET RR 1 R60C125[2][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_5_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 lane3_pcs_tx_o_fabric_clk
13.468 0.000 tCL RR 1022 - Serdes_Top_inst/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
16.131 2.663 tNET RR 1 R60C125[2][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_5_s0/CLK
16.067 -0.064 tSu 1 R60C125[2][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_5_s0

Path Statistics:

Clock Skew 0.038
Setup Relationship 13.468
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.624, 100.000%
Arrival Data Path Delay cell: 3.211, 30.170%; route: 7.050, 66.236%; tC2Q: 0.382, 3.594%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.663, 100.000%

Path24

Path Summary:

Slack 3.160
Data Arrival Time 12.917
Data Required Time 16.076
From Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0
To Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_15_s0
Launch Clk lane3_pcs_tx_o_fabric_clk:[R]
Latch Clk lane3_pcs_tx_o_fabric_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 lane3_pcs_tx_o_fabric_clk
0.000 0.000 tCL RR 1022 - Serdes_Top_inst/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
2.624 2.624 tNET RR 1 R48C118[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0/CLK
3.007 0.382 tC2Q RR 7 R48C118[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_14_s0/Q
4.679 1.673 tNET RR 1 R54C118[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1911_s25/I2
5.258 0.579 tINS RR 10 R54C118[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1911_s25/F
6.740 1.483 tNET RR 1 R56C122[1][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1913_s11/I0
7.248 0.507 tINS RR 3 R56C122[1][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1913_s11/F
7.673 0.425 tNET RR 1 R57C120[3][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1905_s46/I3
8.220 0.548 tINS RR 23 R57C120[3][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1905_s46/F
8.637 0.416 tNET RR 1 R58C119[3][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1905_s35/I1
8.955 0.319 tINS RF 2 R58C119[3][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1905_s35/F
9.142 0.186 tNET FF 1 R58C118[2][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1905_s19/I2
9.709 0.567 tINS FR 8 R58C118[2][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1905_s19/F
10.819 1.110 tNET RR 1 R62C124[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1909_s10/I0
11.387 0.567 tINS RR 6 R62C124[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1909_s10/F
11.757 0.370 tNET RR 1 R60C124[2][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1909_s3/I0
12.335 0.579 tINS RR 1 R60C124[2][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1909_s3/F
12.338 0.003 tNET RR 1 R60C124[1][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1909_s0/I2
12.917 0.579 tINS RR 1 R60C124[1][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1909_s0/F
12.917 0.000 tNET RR 1 R60C124[1][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_15_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 lane3_pcs_tx_o_fabric_clk
13.468 0.000 tCL RR 1022 - Serdes_Top_inst/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
16.140 2.672 tNET RR 1 R60C124[1][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_15_s0/CLK
16.076 -0.064 tSu 1 R60C124[1][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_15_s0

Path Statistics:

Clock Skew 0.048
Setup Relationship 13.468
Logic Level 9
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.624, 100.000%
Arrival Data Path Delay cell: 4.245, 41.244%; route: 5.665, 55.040%; tC2Q: 0.382, 3.716%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.672, 100.000%

Path25

Path Summary:

Slack 4.276
Data Arrival Time 11.771
Data Required Time 16.047
From Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/rx_data_d2_15_s0
To Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_align_phase_1_s0
Launch Clk O_adv7513_clk:[R]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 O_adv7513_clk
0.000 0.000 tCL RR 581 - Serdes_Top_inst/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
2.859 2.859 tNET RR 1 R49C104[3][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/rx_data_d2_15_s0/CLK
3.242 0.382 tC2Q RR 8 R49C104[3][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/rx_data_d2_15_s0/Q
4.721 1.479 tNET RR 1 R50C107[2][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/n1110_s23/I2
5.288 0.567 tINS RR 4 R50C107[2][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/n1110_s23/F
5.656 0.368 tNET RR 1 R48C107[3][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/n1113_s36/I2
6.229 0.574 tINS RR 2 R48C107[3][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/n1113_s36/F
6.443 0.214 tNET RR 1 R48C106[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/n1113_s13/I2
6.951 0.507 tINS RR 3 R48C106[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/n1113_s13/F
7.752 0.801 tNET RR 1 R52C106[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/n1111_s7/I3
8.041 0.289 tINS RR 1 R52C106[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/n1111_s7/F
8.043 0.003 tNET RR 1 R52C106[2][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/n1111_s5/I3
8.332 0.289 tINS RR 3 R52C106[2][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/n1111_s5/F
9.174 0.843 tNET RR 1 R49C104[3][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/n1265_s23/I1
9.748 0.574 tINS RR 2 R49C104[3][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/n1265_s23/F
10.196 0.448 tNET RR 1 R49C101[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_align_phase_0_s4/I1
10.774 0.579 tINS RR 5 R49C101[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_align_phase_0_s4/F
11.771 0.996 tNET RR 1 R51C106[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_align_phase_1_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 O_adv7513_clk
13.468 0.000 tCL RR 581 - Serdes_Top_inst/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
16.358 2.890 tNET RR 1 R51C106[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_align_phase_1_s0/CLK
16.047 -0.311 tSu 1 R51C106[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_align_phase_1_s0

Path Statistics:

Clock Skew 0.031
Setup Relationship 13.468
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.859, 100.000%
Arrival Data Path Delay cell: 3.379, 37.916%; route: 5.150, 57.792%; tC2Q: 0.382, 4.292%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.890, 100.000%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 0.321
Data Arrival Time 1.622
Data Required Time 1.301
From Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_hd_data_extract_inst/I_data20_d1_10_s10
To Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_hd_data_extract_inst/I_data20_d3_15_s0
Launch Clk O_adv7513_clk:[R]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 O_adv7513_clk
0.000 0.000 tCL RR 581 - Serdes_Top_inst/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.295 1.295 tNET RR 4 R60C100 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_hd_data_extract_inst/I_data20_d1_10_s10/CLK
1.315 0.020 tC2Q RR 1 R60C100 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_hd_data_extract_inst/I_data20_d1_10_s10/DO[1]
1.431 0.116 tNET RR 1 R60C99[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_hd_data_extract_inst/I_data20_d2_15_s3/I2
1.622 0.191 tINS RF 1 R60C99[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_hd_data_extract_inst/I_data20_d2_15_s3/F
1.622 0.000 tNET FF 1 R60C99[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_hd_data_extract_inst/I_data20_d3_15_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 O_adv7513_clk
0.000 0.000 tCL RR 581 - Serdes_Top_inst/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.300 1.300 tNET RR 1 R60C99[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_hd_data_extract_inst/I_data20_d3_15_s0/CLK
1.301 0.001 tHld 1 R60C99[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_hd_data_extract_inst/I_data20_d3_15_s0

Path Statistics:

Clock Skew 0.005
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.295, 100.000%
Arrival Data Path Delay cell: 0.191, 58.397%; route: 0.116, 35.496%; tC2Q: 0.020, 6.107%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.300, 100.000%

Path2

Path Summary:

Slack 0.374
Data Arrival Time 1.666
Data Required Time 1.293
From Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_hd_data_extract_inst/I_data20_d1_10_s2
To Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_hd_data_extract_inst/I_data20_d1_10_s2
Launch Clk O_adv7513_clk:[R]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 O_adv7513_clk
0.000 0.000 tCL RR 581 - Serdes_Top_inst/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.291 1.291 tNET RR 1 R62C99[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_hd_data_extract_inst/I_data20_d1_10_s2/CLK
1.467 0.176 tC2Q RF 9 R62C99[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_hd_data_extract_inst/I_data20_d1_10_s2/Q
1.475 0.008 tNET FF 1 R62C99[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_hd_data_extract_inst/I_data20_d1_10_s18/I0
1.666 0.191 tINS FF 1 R62C99[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_hd_data_extract_inst/I_data20_d1_10_s18/F
1.666 0.000 tNET FF 1 R62C99[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_hd_data_extract_inst/I_data20_d1_10_s2/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 O_adv7513_clk
0.000 0.000 tCL RR 581 - Serdes_Top_inst/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.291 1.291 tNET RR 1 R62C99[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_hd_data_extract_inst/I_data20_d1_10_s2/CLK
1.293 0.001 tHld 1 R62C99[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_hd_data_extract_inst/I_data20_d1_10_s2

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.291, 100.000%
Arrival Data Path Delay cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.291, 100.000%

Path3

Path Summary:

Slack 0.374
Data Arrival Time 1.683
Data Required Time 1.310
From Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_hd_data_extract_inst/dot_cnt_9_s0
To Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_hd_data_extract_inst/dot_cnt_9_s0
Launch Clk O_adv7513_clk:[R]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 O_adv7513_clk
0.000 0.000 tCL RR 581 - Serdes_Top_inst/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.308 1.308 tNET RR 1 R56C113[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_hd_data_extract_inst/dot_cnt_9_s0/CLK
1.485 0.176 tC2Q RF 6 R56C113[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_hd_data_extract_inst/dot_cnt_9_s0/Q
1.492 0.008 tNET FF 1 R56C113[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_hd_data_extract_inst/n240_s3/I1
1.683 0.191 tINS FF 1 R56C113[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_hd_data_extract_inst/n240_s3/F
1.683 0.000 tNET FF 1 R56C113[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_hd_data_extract_inst/dot_cnt_9_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 O_adv7513_clk
0.000 0.000 tCL RR 581 - Serdes_Top_inst/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.308 1.308 tNET RR 1 R56C113[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_hd_data_extract_inst/dot_cnt_9_s0/CLK
1.310 0.001 tHld 1 R56C113[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_hd_data_extract_inst/dot_cnt_9_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.308, 100.000%
Arrival Data Path Delay cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.308, 100.000%

Path4

Path Summary:

Slack 0.374
Data Arrival Time 1.644
Data Required Time 1.270
From Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/drp_cnt_0_s2
To Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/drp_cnt_0_s2
Launch Clk sclk:[R]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
1.269 1.269 tNET RR 1 R58C100[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/drp_cnt_0_s2/CLK
1.445 0.176 tC2Q RF 6 R58C100[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/drp_cnt_0_s2/Q
1.453 0.008 tNET FF 1 R58C100[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/n326_s3/I3
1.644 0.191 tINS FF 1 R58C100[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/n326_s3/F
1.644 0.000 tNET FF 1 R58C100[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/drp_cnt_0_s2/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
1.269 1.269 tNET RR 1 R58C100[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/drp_cnt_0_s2/CLK
1.270 0.001 tHld 1 R58C100[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/drp_cnt_0_s2

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.269, 100.000%
Arrival Data Path Delay cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.269, 100.000%

Path5

Path Summary:

Slack 0.374
Data Arrival Time 1.641
Data Required Time 1.267
From Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/drp_cnt_3_s4
To Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/drp_cnt_3_s4
Launch Clk sclk:[R]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
1.266 1.266 tNET RR 1 R57C101[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/drp_cnt_3_s4/CLK
1.442 0.176 tC2Q RF 5 R57C101[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/drp_cnt_3_s4/Q
1.450 0.008 tNET FF 1 R57C101[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/n323_s3/I0
1.641 0.191 tINS FF 1 R57C101[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/n323_s3/F
1.641 0.000 tNET FF 1 R57C101[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/drp_cnt_3_s4/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
1.266 1.266 tNET RR 1 R57C101[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/drp_cnt_3_s4/CLK
1.267 0.001 tHld 1 R57C101[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/drp_cnt_3_s4

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.266, 100.000%
Arrival Data Path Delay cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.266, 100.000%

Path6

Path Summary:

Slack 0.374
Data Arrival Time 1.649
Data Required Time 1.276
From Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_check_phase_0_s1
To Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_check_phase_0_s1
Launch Clk O_adv7513_clk:[R]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 O_adv7513_clk
0.000 0.000 tCL RR 581 - Serdes_Top_inst/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.274 1.274 tNET RR 1 R53C104[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_check_phase_0_s1/CLK
1.451 0.176 tC2Q RF 2 R53C104[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_check_phase_0_s1/Q
1.458 0.008 tNET FF 1 R53C104[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/n1283_s21/I2
1.649 0.191 tINS FF 1 R53C104[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/n1283_s21/F
1.649 0.000 tNET FF 1 R53C104[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_check_phase_0_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 O_adv7513_clk
0.000 0.000 tCL RR 581 - Serdes_Top_inst/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.274 1.274 tNET RR 1 R53C104[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_check_phase_0_s1/CLK
1.276 0.001 tHld 1 R53C104[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_check_phase_0_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.274, 100.000%
Arrival Data Path Delay cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.274, 100.000%

Path7

Path Summary:

Slack 0.374
Data Arrival Time 1.641
Data Required Time 1.267
From Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_check_phase_3_s1
To Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_check_phase_3_s1
Launch Clk O_adv7513_clk:[R]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 O_adv7513_clk
0.000 0.000 tCL RR 581 - Serdes_Top_inst/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.266 1.266 tNET RR 1 R49C99[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_check_phase_3_s1/CLK
1.442 0.176 tC2Q RF 2 R49C99[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_check_phase_3_s1/Q
1.450 0.008 tNET FF 1 R49C99[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/n1280_s21/I2
1.641 0.191 tINS FF 1 R49C99[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/n1280_s21/F
1.641 0.000 tNET FF 1 R49C99[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_check_phase_3_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 O_adv7513_clk
0.000 0.000 tCL RR 581 - Serdes_Top_inst/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.266 1.266 tNET RR 1 R49C99[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_check_phase_3_s1/CLK
1.267 0.001 tHld 1 R49C99[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_check_phase_3_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.266, 100.000%
Arrival Data Path Delay cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.266, 100.000%

Path8

Path Summary:

Slack 0.374
Data Arrival Time 1.651
Data Required Time 1.277
From Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/match_cnt_1_s1
To Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/match_cnt_1_s1
Launch Clk O_adv7513_clk:[R]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 O_adv7513_clk
0.000 0.000 tCL RR 581 - Serdes_Top_inst/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.276 1.276 tNET RR 1 R51C101[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/match_cnt_1_s1/CLK
1.452 0.176 tC2Q RF 4 R51C101[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/match_cnt_1_s1/Q
1.460 0.008 tNET FF 1 R51C101[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/n1277_s30/I3
1.651 0.191 tINS FF 1 R51C101[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/n1277_s30/F
1.651 0.000 tNET FF 1 R51C101[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/match_cnt_1_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 O_adv7513_clk
0.000 0.000 tCL RR 581 - Serdes_Top_inst/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.276 1.276 tNET RR 1 R51C101[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/match_cnt_1_s1/CLK
1.277 0.001 tHld 1 R51C101[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/match_cnt_1_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.276, 100.000%
Arrival Data Path Delay cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.276, 100.000%

Path9

Path Summary:

Slack 0.374
Data Arrival Time 1.642
Data Required Time 1.268
From Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/mod_cnt_0_s1
To Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/mod_cnt_0_s1
Launch Clk sclk:[R]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
1.267 1.267 tNET RR 1 R59C100[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/mod_cnt_0_s1/CLK
1.443 0.176 tC2Q RF 4 R59C100[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/mod_cnt_0_s1/Q
1.451 0.008 tNET FF 1 R59C100[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/n357_s4/I0
1.642 0.191 tINS FF 1 R59C100[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/n357_s4/F
1.642 0.000 tNET FF 1 R59C100[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/mod_cnt_0_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
1.267 1.267 tNET RR 1 R59C100[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/mod_cnt_0_s1/CLK
1.268 0.001 tHld 1 R59C100[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/mod_cnt_0_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.267, 100.000%
Arrival Data Path Delay cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.267, 100.000%

Path10

Path Summary:

Slack 0.374
Data Arrival Time 1.644
Data Required Time 1.270
From Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/drp_cnt_1_s0
To Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/drp_cnt_1_s0
Launch Clk sclk:[R]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
1.269 1.269 tNET RR 1 R58C100[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/drp_cnt_1_s0/CLK
1.445 0.176 tC2Q RF 5 R58C100[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/drp_cnt_1_s0/Q
1.453 0.008 tNET FF 1 R58C100[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/n325_s1/I1
1.644 0.191 tINS FF 1 R58C100[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/n325_s1/F
1.644 0.000 tNET FF 1 R58C100[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/drp_cnt_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
1.269 1.269 tNET RR 1 R58C100[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/drp_cnt_1_s0/CLK
1.270 0.001 tHld 1 R58C100[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/drp_cnt_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.269, 100.000%
Arrival Data Path Delay cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.269, 100.000%

Path11

Path Summary:

Slack 0.374
Data Arrival Time 1.637
Data Required Time 1.263
From Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_2_s0
To Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_2_s0
Launch Clk sclk:[R]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
1.262 1.262 tNET RR 1 R59C101[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_2_s0/CLK
1.438 0.176 tC2Q RF 3 R59C101[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_2_s0/Q
1.446 0.008 tNET FF 1 R59C101[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/n233_s1/I2
1.637 0.191 tINS FF 1 R59C101[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/n233_s1/F
1.637 0.000 tNET FF 1 R59C101[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
1.262 1.262 tNET RR 1 R59C101[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_2_s0/CLK
1.263 0.001 tHld 1 R59C101[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_2_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.262, 100.000%
Arrival Data Path Delay cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.262, 100.000%

Path12

Path Summary:

Slack 0.374
Data Arrival Time 1.639
Data Required Time 1.265
From Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_5_s0
To Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_5_s0
Launch Clk sclk:[R]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
1.264 1.264 tNET RR 1 R58C101[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_5_s0/CLK
1.440 0.176 tC2Q RF 3 R58C101[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_5_s0/Q
1.448 0.008 tNET FF 1 R58C101[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/n230_s3/I0
1.639 0.191 tINS FF 1 R58C101[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/n230_s3/F
1.639 0.000 tNET FF 1 R58C101[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_5_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
1.264 1.264 tNET RR 1 R58C101[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_5_s0/CLK
1.265 0.001 tHld 1 R58C101[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_5_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.264, 100.000%
Arrival Data Path Delay cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.264, 100.000%

Path13

Path Summary:

Slack 0.374
Data Arrival Time 1.636
Data Required Time 1.262
From Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_15_s0
To Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_15_s0
Launch Clk sclk:[R]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
1.261 1.261 tNET RR 1 R57C106[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_15_s0/CLK
1.437 0.176 tC2Q RF 5 R57C106[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_15_s0/Q
1.445 0.008 tNET FF 1 R57C106[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/n220_s1/I0
1.636 0.191 tINS FF 1 R57C106[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/n220_s1/F
1.636 0.000 tNET FF 1 R57C106[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_15_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
1.261 1.261 tNET RR 1 R57C106[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_15_s0/CLK
1.262 0.001 tHld 1 R57C106[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_15_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.261, 100.000%
Arrival Data Path Delay cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.261, 100.000%

Path14

Path Summary:

Slack 0.374
Data Arrival Time 1.637
Data Required Time 1.263
From Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_23_s0
To Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_23_s0
Launch Clk sclk:[R]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
1.262 1.262 tNET RR 1 R59C111[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_23_s0/CLK
1.438 0.176 tC2Q RF 5 R59C111[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_23_s0/Q
1.446 0.008 tNET FF 1 R59C111[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/n212_s1/I0
1.637 0.191 tINS FF 1 R59C111[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/n212_s1/F
1.637 0.000 tNET FF 1 R59C111[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_23_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
1.262 1.262 tNET RR 1 R59C111[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_23_s0/CLK
1.263 0.001 tHld 1 R59C111[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_23_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.262, 100.000%
Arrival Data Path Delay cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.262, 100.000%

Path15

Path Summary:

Slack 0.374
Data Arrival Time 1.637
Data Required Time 1.263
From Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_26_s0
To Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_26_s0
Launch Clk sclk:[R]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
1.262 1.262 tNET RR 1 R59C103[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_26_s0/CLK
1.438 0.176 tC2Q RF 3 R59C103[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_26_s0/Q
1.446 0.008 tNET FF 1 R59C103[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/n209_s1/I2
1.637 0.191 tINS FF 1 R59C103[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/n209_s1/F
1.637 0.000 tNET FF 1 R59C103[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_26_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
1.262 1.262 tNET RR 1 R59C103[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_26_s0/CLK
1.263 0.001 tHld 1 R59C103[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_26_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.262, 100.000%
Arrival Data Path Delay cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.262, 100.000%

Path16

Path Summary:

Slack 0.374
Data Arrival Time 1.643
Data Required Time 1.270
From Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_29_s0
To Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_29_s0
Launch Clk sclk:[R]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
1.268 1.268 tNET RR 1 R56C105[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_29_s0/CLK
1.445 0.176 tC2Q RF 3 R56C105[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_29_s0/Q
1.452 0.008 tNET FF 1 R56C105[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/n206_s3/I0
1.643 0.191 tINS FF 1 R56C105[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/n206_s3/F
1.643 0.000 tNET FF 1 R56C105[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_29_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
1.268 1.268 tNET RR 1 R56C105[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_29_s0/CLK
1.270 0.001 tHld 1 R56C105[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_29_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.268, 100.000%
Arrival Data Path Delay cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.268, 100.000%

Path17

Path Summary:

Slack 0.374
Data Arrival Time 1.642
Data Required Time 1.268
From Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_0_s0
To Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_0_s0
Launch Clk sclk:[R]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
1.267 1.267 tNET RR 1 R59C100[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_0_s0/CLK
1.443 0.176 tC2Q RF 5 R59C100[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_0_s0/Q
1.451 0.008 tNET FF 1 R59C100[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/n127_s3/I0
1.642 0.191 tINS FF 1 R59C100[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/n127_s3/F
1.642 0.000 tNET FF 1 R59C100[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
1.267 1.267 tNET RR 1 R59C100[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_0_s0/CLK
1.268 0.001 tHld 1 R59C100[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.267, 100.000%
Arrival Data Path Delay cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.267, 100.000%

Path18

Path Summary:

Slack 0.374
Data Arrival Time 1.632
Data Required Time 1.258
From Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_5_s0
To Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_5_s0
Launch Clk sclk:[R]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
1.257 1.257 tNET RR 1 R59C110[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_5_s0/CLK
1.433 0.176 tC2Q RF 3 R59C110[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_5_s0/Q
1.441 0.008 tNET FF 1 R59C110[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/n122_s3/I0
1.632 0.191 tINS FF 1 R59C110[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/n122_s3/F
1.632 0.000 tNET FF 1 R59C110[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_5_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
1.257 1.257 tNET RR 1 R59C110[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_5_s0/CLK
1.258 0.001 tHld 1 R59C110[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_5_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.257, 100.000%
Arrival Data Path Delay cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.257, 100.000%

Path19

Path Summary:

Slack 0.374
Data Arrival Time 1.634
Data Required Time 1.260
From Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_10_s0
To Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_10_s0
Launch Clk sclk:[R]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
1.259 1.259 tNET RR 1 R58C110[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_10_s0/CLK
1.435 0.176 tC2Q RF 3 R58C110[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_10_s0/Q
1.443 0.008 tNET FF 1 R58C110[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/n117_s1/I2
1.634 0.191 tINS FF 1 R58C110[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/n117_s1/F
1.634 0.000 tNET FF 1 R58C110[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_10_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
1.259 1.259 tNET RR 1 R58C110[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_10_s0/CLK
1.260 0.001 tHld 1 R58C110[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_10_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.259, 100.000%
Arrival Data Path Delay cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.259, 100.000%

Path20

Path Summary:

Slack 0.374
Data Arrival Time 1.637
Data Required Time 1.263
From Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_28_s0
To Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_28_s0
Launch Clk sclk:[R]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
1.262 1.262 tNET RR 1 R59C105[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_28_s0/CLK
1.438 0.176 tC2Q RF 5 R59C105[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_28_s0/Q
1.446 0.008 tNET FF 1 R59C105[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/n99_s3/I0
1.637 0.191 tINS FF 1 R59C105[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/n99_s3/F
1.637 0.000 tNET FF 1 R59C105[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_28_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
1.262 1.262 tNET RR 1 R59C105[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_28_s0/CLK
1.263 0.001 tHld 1 R59C105[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_28_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.262, 100.000%
Arrival Data Path Delay cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.262, 100.000%

Path21

Path Summary:

Slack 0.374
Data Arrival Time 1.637
Data Required Time 1.263
From Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_29_s0
To Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_29_s0
Launch Clk sclk:[R]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
1.262 1.262 tNET RR 1 R59C105[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_29_s0/CLK
1.438 0.176 tC2Q RF 4 R59C105[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_29_s0/Q
1.446 0.008 tNET FF 1 R59C105[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/n98_s1/I2
1.637 0.191 tINS FF 1 R59C105[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/n98_s1/F
1.637 0.000 tNET FF 1 R59C105[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_29_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
1.262 1.262 tNET RR 1 R59C105[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_29_s0/CLK
1.263 0.001 tHld 1 R59C105[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_29_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.262, 100.000%
Arrival Data Path Delay cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.262, 100.000%

Path22

Path Summary:

Slack 0.374
Data Arrival Time 1.641
Data Required Time 1.267
From Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_crc_inst/ycr1_9_s1
To Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_crc_inst/ycr1_9_s1
Launch Clk lane3_pcs_tx_o_fabric_clk:[R]
Latch Clk lane3_pcs_tx_o_fabric_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 lane3_pcs_tx_o_fabric_clk
0.000 0.000 tCL RR 1022 - Serdes_Top_inst/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
1.266 1.266 tNET RR 1 R57C114[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_crc_inst/ycr1_9_s1/CLK
1.442 0.176 tC2Q RF 2 R57C114[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_crc_inst/ycr1_9_s1/Q
1.450 0.008 tNET FF 1 R57C114[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_crc_inst/n375_s3/I2
1.641 0.191 tINS FF 1 R57C114[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_crc_inst/n375_s3/F
1.641 0.000 tNET FF 1 R57C114[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_crc_inst/ycr1_9_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 lane3_pcs_tx_o_fabric_clk
0.000 0.000 tCL RR 1022 - Serdes_Top_inst/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
1.266 1.266 tNET RR 1 R57C114[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_crc_inst/ycr1_9_s1/CLK
1.267 0.001 tHld 1 R57C114[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_crc_inst/ycr1_9_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.266, 100.000%
Arrival Data Path Delay cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.266, 100.000%

Path23

Path Summary:

Slack 0.374
Data Arrival Time 1.601
Data Required Time 1.227
From Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/de_cnt_0_s1
To Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/de_cnt_0_s1
Launch Clk lane3_pcs_tx_o_fabric_clk:[R]
Latch Clk lane3_pcs_tx_o_fabric_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 lane3_pcs_tx_o_fabric_clk
0.000 0.000 tCL RR 1022 - Serdes_Top_inst/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
1.226 1.226 tNET RR 1 R49C126[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/de_cnt_0_s1/CLK
1.402 0.176 tC2Q RF 3 R49C126[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/de_cnt_0_s1/Q
1.410 0.008 tNET FF 1 R49C126[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/n234_s3/I0
1.601 0.191 tINS FF 1 R49C126[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/n234_s3/F
1.601 0.000 tNET FF 1 R49C126[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/de_cnt_0_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 lane3_pcs_tx_o_fabric_clk
0.000 0.000 tCL RR 1022 - Serdes_Top_inst/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
1.226 1.226 tNET RR 1 R49C126[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/de_cnt_0_s1/CLK
1.227 0.001 tHld 1 R49C126[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/de_cnt_0_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.226, 100.000%
Arrival Data Path Delay cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.226, 100.000%

Path24

Path Summary:

Slack 0.374
Data Arrival Time 1.601
Data Required Time 1.227
From Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/line_cnt_7_s1
To Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/line_cnt_7_s1
Launch Clk lane3_pcs_tx_o_fabric_clk:[R]
Latch Clk lane3_pcs_tx_o_fabric_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 lane3_pcs_tx_o_fabric_clk
0.000 0.000 tCL RR 1022 - Serdes_Top_inst/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
1.226 1.226 tNET RR 1 R48C123[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/line_cnt_7_s1/CLK
1.402 0.176 tC2Q RF 8 R48C123[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/line_cnt_7_s1/Q
1.410 0.008 tNET FF 1 R48C123[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/n483_s2/I3
1.601 0.191 tINS FF 1 R48C123[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/n483_s2/F
1.601 0.000 tNET FF 1 R48C123[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/line_cnt_7_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 lane3_pcs_tx_o_fabric_clk
0.000 0.000 tCL RR 1022 - Serdes_Top_inst/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
1.226 1.226 tNET RR 1 R48C123[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/line_cnt_7_s1/CLK
1.227 0.001 tHld 1 R48C123[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/line_cnt_7_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.226, 100.000%
Arrival Data Path Delay cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.226, 100.000%

Path25

Path Summary:

Slack 0.374
Data Arrival Time 1.611
Data Required Time 1.237
From Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/vcnt_13_s1
To Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/vcnt_13_s1
Launch Clk lane3_pcs_tx_o_fabric_clk:[R]
Latch Clk lane3_pcs_tx_o_fabric_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 lane3_pcs_tx_o_fabric_clk
0.000 0.000 tCL RR 1022 - Serdes_Top_inst/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
1.236 1.236 tNET RR 1 R51C124[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/vcnt_13_s1/CLK
1.412 0.176 tC2Q RF 3 R51C124[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/vcnt_13_s1/Q
1.420 0.008 tNET FF 1 R51C124[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/n151_s2/I1
1.611 0.191 tINS FF 1 R51C124[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/n151_s2/F
1.611 0.000 tNET FF 1 R51C124[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/vcnt_13_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 lane3_pcs_tx_o_fabric_clk
0.000 0.000 tCL RR 1022 - Serdes_Top_inst/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
1.236 1.236 tNET RR 1 R51C124[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/vcnt_13_s1/CLK
1.237 0.001 tHld 1 R51C124[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/vcnt_13_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.236, 100.000%
Arrival Data Path Delay cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.236, 100.000%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 2.244
Data Arrival Time 20.005
Data Required Time 22.249
From adv7513_iic_init_inst0/state_4_s0
To adv7513_iic_init_inst0/state_4_s0
Launch Clk O_led:[F]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 O_led
15.000 0.000 tCL FF 1461 R51C98[0][A] key_debounceN_inst0/key_n_out1_s1/Q
20.005 5.005 tNET FF 1 R65C98[0][B] adv7513_iic_init_inst0/state_4_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 sclk
20.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
22.631 2.631 tNET RR 1 R65C98[0][B] adv7513_iic_init_inst0/state_4_s0/CLK
22.596 -0.035 tUnc adv7513_iic_init_inst0/state_4_s0
22.249 -0.347 tSu 1 R65C98[0][B] adv7513_iic_init_inst0/state_4_s0

Path Statistics:

Clock Skew 2.631
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 5.005, 100.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.631, 100.000%

Path2

Path Summary:

Slack 2.244
Data Arrival Time 20.005
Data Required Time 22.249
From adv7513_iic_init_inst0/start_d2_s0
To adv7513_iic_init_inst0/start_d2_s0
Launch Clk O_led:[F]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 O_led
15.000 0.000 tCL FF 1461 R51C98[0][A] key_debounceN_inst0/key_n_out1_s1/Q
20.005 5.005 tNET FF 1 R65C98[0][A] adv7513_iic_init_inst0/start_d2_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 sclk
20.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
22.631 2.631 tNET RR 1 R65C98[0][A] adv7513_iic_init_inst0/start_d2_s0/CLK
22.596 -0.035 tUnc adv7513_iic_init_inst0/start_d2_s0
22.249 -0.347 tSu 1 R65C98[0][A] adv7513_iic_init_inst0/start_d2_s0

Path Statistics:

Clock Skew 2.631
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 5.005, 100.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.631, 100.000%

Path3

Path Summary:

Slack 2.499
Data Arrival Time 19.786
Data Required Time 22.285
From Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_4_s0
To Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_4_s0
Launch Clk O_led:[F]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 O_led
15.000 0.000 tCL FF 1461 R51C98[0][A] key_debounceN_inst0/key_n_out1_s1/Q
19.786 4.786 tNET FF 1 R58C110[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_4_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 sclk
20.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
22.667 2.668 tNET RR 1 R58C110[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_4_s0/CLK
22.632 -0.035 tUnc Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_4_s0
22.285 -0.347 tSu 1 R58C110[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_4_s0

Path Statistics:

Clock Skew 2.668
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 4.786, 100.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.668, 100.000%

Path4

Path Summary:

Slack 2.499
Data Arrival Time 19.786
Data Required Time 22.285
From Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_7_s0
To Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_7_s0
Launch Clk O_led:[F]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 O_led
15.000 0.000 tCL FF 1461 R51C98[0][A] key_debounceN_inst0/key_n_out1_s1/Q
19.786 4.786 tNET FF 1 R58C110[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_7_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 sclk
20.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
22.667 2.668 tNET RR 1 R58C110[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_7_s0/CLK
22.632 -0.035 tUnc Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_7_s0
22.285 -0.347 tSu 1 R58C110[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_7_s0

Path Statistics:

Clock Skew 2.668
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 4.786, 100.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.668, 100.000%

Path5

Path Summary:

Slack 2.499
Data Arrival Time 19.786
Data Required Time 22.285
From Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_10_s0
To Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_10_s0
Launch Clk O_led:[F]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 O_led
15.000 0.000 tCL FF 1461 R51C98[0][A] key_debounceN_inst0/key_n_out1_s1/Q
19.786 4.786 tNET FF 1 R58C110[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_10_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 sclk
20.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
22.667 2.668 tNET RR 1 R58C110[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_10_s0/CLK
22.632 -0.035 tUnc Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_10_s0
22.285 -0.347 tSu 1 R58C110[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_10_s0

Path Statistics:

Clock Skew 2.668
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 4.786, 100.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.668, 100.000%

Path6

Path Summary:

Slack 2.511
Data Arrival Time 19.781
Data Required Time 22.292
From Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_1_s0
To Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_1_s0
Launch Clk O_led:[F]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 O_led
15.000 0.000 tCL FF 1461 R51C98[0][A] key_debounceN_inst0/key_n_out1_s1/Q
19.781 4.781 tNET FF 1 R59C109[1][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 sclk
20.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
22.674 2.674 tNET RR 1 R59C109[1][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_1_s0/CLK
22.639 -0.035 tUnc Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_1_s0
22.292 -0.347 tSu 1 R59C109[1][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_1_s0

Path Statistics:

Clock Skew 2.674
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 4.781, 100.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.674, 100.000%

Path7

Path Summary:

Slack 2.511
Data Arrival Time 19.781
Data Required Time 22.292
From Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_2_s0
To Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_2_s0
Launch Clk O_led:[F]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 O_led
15.000 0.000 tCL FF 1461 R51C98[0][A] key_debounceN_inst0/key_n_out1_s1/Q
19.781 4.781 tNET FF 1 R59C109[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_2_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 sclk
20.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
22.674 2.674 tNET RR 1 R59C109[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_2_s0/CLK
22.639 -0.035 tUnc Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_2_s0
22.292 -0.347 tSu 1 R59C109[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_2_s0

Path Statistics:

Clock Skew 2.674
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 4.781, 100.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.674, 100.000%

Path8

Path Summary:

Slack 2.511
Data Arrival Time 19.781
Data Required Time 22.292
From Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_3_s0
To Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_3_s0
Launch Clk O_led:[F]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 O_led
15.000 0.000 tCL FF 1461 R51C98[0][A] key_debounceN_inst0/key_n_out1_s1/Q
19.781 4.781 tNET FF 1 R59C109[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_3_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 sclk
20.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
22.674 2.674 tNET RR 1 R59C109[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_3_s0/CLK
22.639 -0.035 tUnc Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_3_s0
22.292 -0.347 tSu 1 R59C109[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_3_s0

Path Statistics:

Clock Skew 2.674
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 4.781, 100.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.674, 100.000%

Path9

Path Summary:

Slack 2.520
Data Arrival Time 19.781
Data Required Time 22.301
From Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_24_s0
To Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_24_s0
Launch Clk O_led:[F]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 O_led
15.000 0.000 tCL FF 1461 R51C98[0][A] key_debounceN_inst0/key_n_out1_s1/Q
19.781 4.781 tNET FF 1 R59C108[1][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_24_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 sclk
20.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
22.684 2.684 tNET RR 1 R59C108[1][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_24_s0/CLK
22.649 -0.035 tUnc Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_24_s0
22.301 -0.347 tSu 1 R59C108[1][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_24_s0

Path Statistics:

Clock Skew 2.684
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 4.781, 100.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.684, 100.000%

Path10

Path Summary:

Slack 2.520
Data Arrival Time 19.781
Data Required Time 22.301
From Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_25_s0
To Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_25_s0
Launch Clk O_led:[F]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 O_led
15.000 0.000 tCL FF 1461 R51C98[0][A] key_debounceN_inst0/key_n_out1_s1/Q
19.781 4.781 tNET FF 1 R59C108[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_25_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 sclk
20.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
22.684 2.684 tNET RR 1 R59C108[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_25_s0/CLK
22.649 -0.035 tUnc Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_25_s0
22.301 -0.347 tSu 1 R59C108[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_25_s0

Path Statistics:

Clock Skew 2.684
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 4.781, 100.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.684, 100.000%

Path11

Path Summary:

Slack 2.520
Data Arrival Time 19.781
Data Required Time 22.301
From Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_27_s0
To Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_27_s0
Launch Clk O_led:[F]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 O_led
15.000 0.000 tCL FF 1461 R51C98[0][A] key_debounceN_inst0/key_n_out1_s1/Q
19.781 4.781 tNET FF 1 R59C108[2][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_27_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 sclk
20.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
22.684 2.684 tNET RR 1 R59C108[2][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_27_s0/CLK
22.649 -0.035 tUnc Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_27_s0
22.301 -0.347 tSu 1 R59C108[2][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_27_s0

Path Statistics:

Clock Skew 2.684
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 4.781, 100.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.684, 100.000%

Path12

Path Summary:

Slack 2.522
Data Arrival Time 19.770
Data Required Time 22.292
From Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_0_s0
To Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_0_s0
Launch Clk O_led:[F]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 O_led
15.000 0.000 tCL FF 1461 R51C98[0][A] key_debounceN_inst0/key_n_out1_s1/Q
19.770 4.770 tNET FF 1 R59C101[1][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 sclk
20.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
22.674 2.674 tNET RR 1 R59C101[1][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_0_s0/CLK
22.639 -0.035 tUnc Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_0_s0
22.292 -0.347 tSu 1 R59C101[1][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_0_s0

Path Statistics:

Clock Skew 2.674
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 4.770, 100.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.674, 100.000%

Path13

Path Summary:

Slack 2.522
Data Arrival Time 19.770
Data Required Time 22.292
From Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_1_s0
To Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_1_s0
Launch Clk O_led:[F]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 O_led
15.000 0.000 tCL FF 1461 R51C98[0][A] key_debounceN_inst0/key_n_out1_s1/Q
19.770 4.770 tNET FF 1 R59C101[2][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 sclk
20.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
22.674 2.674 tNET RR 1 R59C101[2][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_1_s0/CLK
22.639 -0.035 tUnc Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_1_s0
22.292 -0.347 tSu 1 R59C101[2][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_1_s0

Path Statistics:

Clock Skew 2.674
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 4.770, 100.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.674, 100.000%

Path14

Path Summary:

Slack 2.522
Data Arrival Time 19.770
Data Required Time 22.292
From Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_2_s0
To Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_2_s0
Launch Clk O_led:[F]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 O_led
15.000 0.000 tCL FF 1461 R51C98[0][A] key_debounceN_inst0/key_n_out1_s1/Q
19.770 4.770 tNET FF 1 R59C101[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_2_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 sclk
20.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
22.674 2.674 tNET RR 1 R59C101[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_2_s0/CLK
22.639 -0.035 tUnc Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_2_s0
22.292 -0.347 tSu 1 R59C101[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_2_s0

Path Statistics:

Clock Skew 2.674
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 4.770, 100.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.674, 100.000%

Path15

Path Summary:

Slack 2.522
Data Arrival Time 19.770
Data Required Time 22.292
From Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_30_s0
To Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_30_s0
Launch Clk O_led:[F]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 O_led
15.000 0.000 tCL FF 1461 R51C98[0][A] key_debounceN_inst0/key_n_out1_s1/Q
19.770 4.770 tNET FF 1 R59C101[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_30_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 sclk
20.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
22.674 2.674 tNET RR 1 R59C101[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_30_s0/CLK
22.639 -0.035 tUnc Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_30_s0
22.292 -0.347 tSu 1 R59C101[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_30_s0

Path Statistics:

Clock Skew 2.674
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 4.770, 100.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.674, 100.000%

Path16

Path Summary:

Slack 2.522
Data Arrival Time 19.770
Data Required Time 22.292
From Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_31_s0
To Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_31_s0
Launch Clk O_led:[F]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 O_led
15.000 0.000 tCL FF 1461 R51C98[0][A] key_debounceN_inst0/key_n_out1_s1/Q
19.770 4.770 tNET FF 1 R59C101[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_31_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 sclk
20.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
22.674 2.674 tNET RR 1 R59C101[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_31_s0/CLK
22.639 -0.035 tUnc Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_31_s0
22.292 -0.347 tSu 1 R59C101[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_31_s0

Path Statistics:

Clock Skew 2.674
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 4.770, 100.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.674, 100.000%

Path17

Path Summary:

Slack 2.522
Data Arrival Time 19.770
Data Required Time 22.292
From Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_18_s0
To Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_18_s0
Launch Clk O_led:[F]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 O_led
15.000 0.000 tCL FF 1461 R51C98[0][A] key_debounceN_inst0/key_n_out1_s1/Q
19.770 4.770 tNET FF 1 R59C109[3][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_18_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 sclk
20.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
22.674 2.674 tNET RR 1 R59C109[3][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_18_s0/CLK
22.639 -0.035 tUnc Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_18_s0
22.292 -0.347 tSu 1 R59C109[3][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_18_s0

Path Statistics:

Clock Skew 2.674
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 4.770, 100.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.674, 100.000%

Path18

Path Summary:

Slack 2.522
Data Arrival Time 19.770
Data Required Time 22.292
From Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_19_s0
To Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_19_s0
Launch Clk O_led:[F]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 O_led
15.000 0.000 tCL FF 1461 R51C98[0][A] key_debounceN_inst0/key_n_out1_s1/Q
19.770 4.770 tNET FF 1 R59C109[2][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_19_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 sclk
20.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
22.674 2.674 tNET RR 1 R59C109[2][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_19_s0/CLK
22.639 -0.035 tUnc Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_19_s0
22.292 -0.347 tSu 1 R59C109[2][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_19_s0

Path Statistics:

Clock Skew 2.674
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 4.770, 100.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.674, 100.000%

Path19

Path Summary:

Slack 2.523
Data Arrival Time 19.772
Data Required Time 22.294
From Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_6_s0
To Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_6_s0
Launch Clk O_led:[F]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 O_led
15.000 0.000 tCL FF 1461 R51C98[0][A] key_debounceN_inst0/key_n_out1_s1/Q
19.772 4.772 tNET FF 1 R58C109[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_6_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 sclk
20.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
22.677 2.677 tNET RR 1 R58C109[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_6_s0/CLK
22.642 -0.035 tUnc Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_6_s0
22.294 -0.347 tSu 1 R58C109[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_6_s0

Path Statistics:

Clock Skew 2.677
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 4.772, 100.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.677, 100.000%

Path20

Path Summary:

Slack 2.523
Data Arrival Time 19.772
Data Required Time 22.294
From Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_8_s0
To Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_8_s0
Launch Clk O_led:[F]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 O_led
15.000 0.000 tCL FF 1461 R51C98[0][A] key_debounceN_inst0/key_n_out1_s1/Q
19.772 4.772 tNET FF 1 R58C109[1][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_8_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 sclk
20.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
22.677 2.677 tNET RR 1 R58C109[1][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_8_s0/CLK
22.642 -0.035 tUnc Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_8_s0
22.294 -0.347 tSu 1 R58C109[1][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_8_s0

Path Statistics:

Clock Skew 2.677
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 4.772, 100.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.677, 100.000%

Path21

Path Summary:

Slack 2.523
Data Arrival Time 19.772
Data Required Time 22.294
From Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_9_s0
To Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_9_s0
Launch Clk O_led:[F]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 O_led
15.000 0.000 tCL FF 1461 R51C98[0][A] key_debounceN_inst0/key_n_out1_s1/Q
19.772 4.772 tNET FF 1 R58C109[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_9_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 sclk
20.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
22.677 2.677 tNET RR 1 R58C109[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_9_s0/CLK
22.642 -0.035 tUnc Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_9_s0
22.294 -0.347 tSu 1 R58C109[1][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_9_s0

Path Statistics:

Clock Skew 2.677
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 4.772, 100.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.677, 100.000%

Path22

Path Summary:

Slack 2.528
Data Arrival Time 19.755
Data Required Time 22.283
From Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_24_s0
To Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_24_s0
Launch Clk O_led:[F]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 O_led
15.000 0.000 tCL FF 1461 R51C98[0][A] key_debounceN_inst0/key_n_out1_s1/Q
19.755 4.755 tNET FF 1 R59C110[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_24_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 sclk
20.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
22.665 2.665 tNET RR 1 R59C110[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_24_s0/CLK
22.630 -0.035 tUnc Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_24_s0
22.283 -0.347 tSu 1 R59C110[0][B] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/sd_time_cnt_24_s0

Path Statistics:

Clock Skew 2.665
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 4.755, 100.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.665, 100.000%

Path23

Path Summary:

Slack 2.528
Data Arrival Time 19.755
Data Required Time 22.283
From Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_5_s0
To Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_5_s0
Launch Clk O_led:[F]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 O_led
15.000 0.000 tCL FF 1461 R51C98[0][A] key_debounceN_inst0/key_n_out1_s1/Q
19.755 4.755 tNET FF 1 R59C110[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_5_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 sclk
20.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
22.665 2.665 tNET RR 1 R59C110[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_5_s0/CLK
22.630 -0.035 tUnc Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_5_s0
22.283 -0.347 tSu 1 R59C110[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_5_s0

Path Statistics:

Clock Skew 2.665
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 4.755, 100.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.665, 100.000%

Path24

Path Summary:

Slack 2.529
Data Arrival Time 19.743
Data Required Time 22.272
From Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/current_state_3_s0
To Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/current_state_3_s0
Launch Clk O_led:[F]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 O_led
15.000 0.000 tCL FF 1461 R51C98[0][A] key_debounceN_inst0/key_n_out1_s1/Q
19.743 4.743 tNET FF 1 R53C100[3][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/current_state_3_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 sclk
20.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
22.655 2.655 tNET RR 1 R53C100[3][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/current_state_3_s0/CLK
22.620 -0.035 tUnc Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/current_state_3_s0
22.273 -0.347 tSu 1 R53C100[3][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/current_state_3_s0

Path Statistics:

Clock Skew 2.655
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 4.743, 100.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.655, 100.000%

Path25

Path Summary:

Slack 2.529
Data Arrival Time 19.743
Data Required Time 22.272
From Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/current_state_1_s0
To Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/current_state_1_s0
Launch Clk O_led:[F]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 O_led
15.000 0.000 tCL FF 1461 R51C98[0][A] key_debounceN_inst0/key_n_out1_s1/Q
19.743 4.743 tNET FF 1 R53C100[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/current_state_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 sclk
20.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
22.655 2.655 tNET RR 1 R53C100[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/current_state_1_s0/CLK
22.620 -0.035 tUnc Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/current_state_1_s0
22.273 -0.347 tSu 1 R53C100[0][A] Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/current_state_1_s0

Path Statistics:

Clock Skew 2.655
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 4.743, 100.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.655, 100.000%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 0.539
Data Arrival Time 2.631
Data Required Time 2.092
From rgb_yc422_inst/yc444_yc422_inst/n251_s1
To rgb_yc422_inst/yc444_yc422_inst/count_s6
Launch Clk O_led:[R]
Latch Clk O_led:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 O_led
0.000 0.000 tCL RR 1461 R51C98[0][A] key_debounceN_inst0/key_n_out1_s1/Q
2.347 2.347 tNET RR 1 R44C128[2][B] rgb_yc422_inst/yc444_yc422_inst/n251_s1/I1
2.530 0.183 tINS RR 2 R44C128[2][B] rgb_yc422_inst/yc444_yc422_inst/n251_s1/F
2.631 0.101 tNET RR 1 R44C128[0][B] rgb_yc422_inst/yc444_yc422_inst/count_s6/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 O_led
0.000 0.000 tCL RR 1461 R51C98[0][A] key_debounceN_inst0/key_n_out1_s1/Q
2.226 2.226 tNET RR 1 R44C128[0][B] rgb_yc422_inst/yc444_yc422_inst/count_s6/G
2.092 -0.134 tHld 1 R44C128[0][B] rgb_yc422_inst/yc444_yc422_inst/count_s6

Path Statistics:

Clock Skew 2.226
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.183, 6.936%; route: 0.101, 3.848%; tC2Q: 2.347, 89.216%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.226, 100.000%

Path2

Path Summary:

Slack 0.614
Data Arrival Time 1.660
Data Required Time 1.046
From key_debounceN_inst0/key_n_out2_s1
To I2C_MASTER_Top_inst0/u_i2c_master/byte_controller/c_state_2_s0
Launch Clk sclk:[R]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
1.226 1.226 tNET RR 1 R50C98[0][A] key_debounceN_inst0/key_n_out2_s1/CLK
1.406 0.180 tC2Q RR 106 R50C98[0][A] key_debounceN_inst0/key_n_out2_s1/Q
1.660 0.254 tNET RR 1 R53C98[0][A] I2C_MASTER_Top_inst0/u_i2c_master/byte_controller/c_state_2_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
1.234 1.234 tNET RR 1 R53C98[0][A] I2C_MASTER_Top_inst0/u_i2c_master/byte_controller/c_state_2_s0/CLK
1.046 -0.189 tHld 1 R53C98[0][A] I2C_MASTER_Top_inst0/u_i2c_master/byte_controller/c_state_2_s0

Path Statistics:

Clock Skew 0.008
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.226, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.254, 58.501%; tC2Q: 0.180, 41.499%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.234, 100.000%

Path3

Path Summary:

Slack 0.614
Data Arrival Time 1.660
Data Required Time 1.046
From key_debounceN_inst0/key_n_out2_s1
To I2C_MASTER_Top_inst0/u_i2c_master/byte_controller/CORE_CMD_2_s0
Launch Clk sclk:[R]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
1.226 1.226 tNET RR 1 R50C98[0][A] key_debounceN_inst0/key_n_out2_s1/CLK
1.406 0.180 tC2Q RR 106 R50C98[0][A] key_debounceN_inst0/key_n_out2_s1/Q
1.660 0.254 tNET RR 1 R53C98[1][A] I2C_MASTER_Top_inst0/u_i2c_master/byte_controller/CORE_CMD_2_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
1.234 1.234 tNET RR 1 R53C98[1][A] I2C_MASTER_Top_inst0/u_i2c_master/byte_controller/CORE_CMD_2_s0/CLK
1.046 -0.189 tHld 1 R53C98[1][A] I2C_MASTER_Top_inst0/u_i2c_master/byte_controller/CORE_CMD_2_s0

Path Statistics:

Clock Skew 0.008
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.226, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.254, 58.501%; tC2Q: 0.180, 41.499%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.234, 100.000%

Path4

Path Summary:

Slack 0.614
Data Arrival Time 1.660
Data Required Time 1.046
From key_debounceN_inst0/key_n_out2_s1
To I2C_MASTER_Top_inst0/u_i2c_master/byte_controller/CORE_CMD_3_s0
Launch Clk sclk:[R]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
1.226 1.226 tNET RR 1 R50C98[0][A] key_debounceN_inst0/key_n_out2_s1/CLK
1.406 0.180 tC2Q RR 106 R50C98[0][A] key_debounceN_inst0/key_n_out2_s1/Q
1.660 0.254 tNET RR 1 R53C98[0][B] I2C_MASTER_Top_inst0/u_i2c_master/byte_controller/CORE_CMD_3_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
1.234 1.234 tNET RR 1 R53C98[0][B] I2C_MASTER_Top_inst0/u_i2c_master/byte_controller/CORE_CMD_3_s0/CLK
1.046 -0.189 tHld 1 R53C98[0][B] I2C_MASTER_Top_inst0/u_i2c_master/byte_controller/CORE_CMD_3_s0

Path Statistics:

Clock Skew 0.008
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.226, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.254, 58.501%; tC2Q: 0.180, 41.499%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.234, 100.000%

Path5

Path Summary:

Slack 0.618
Data Arrival Time 1.665
Data Required Time 1.047
From key_debounceN_inst0/key_n_out2_s1
To I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_15_s1
Launch Clk sclk:[R]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
1.226 1.226 tNET RR 1 R50C98[0][A] key_debounceN_inst0/key_n_out2_s1/CLK
1.406 0.180 tC2Q RR 106 R50C98[0][A] key_debounceN_inst0/key_n_out2_s1/Q
1.665 0.259 tNET RR 1 R50C96[2][A] I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_15_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
1.236 1.236 tNET RR 1 R50C96[2][A] I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_15_s1/CLK
1.047 -0.189 tHld 1 R50C96[2][A] I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_15_s1

Path Statistics:

Clock Skew 0.010
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.226, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.259, 58.974%; tC2Q: 0.180, 41.026%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.236, 100.000%

Path6

Path Summary:

Slack 0.618
Data Arrival Time 1.665
Data Required Time 1.047
From key_debounceN_inst0/key_n_out2_s1
To I2C_MASTER_Top_inst0/u_i2c_master/control_reg_7_s0
Launch Clk sclk:[R]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
1.226 1.226 tNET RR 1 R50C98[0][A] key_debounceN_inst0/key_n_out2_s1/CLK
1.406 0.180 tC2Q RR 106 R50C98[0][A] key_debounceN_inst0/key_n_out2_s1/Q
1.665 0.259 tNET RR 1 R50C96[0][A] I2C_MASTER_Top_inst0/u_i2c_master/control_reg_7_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
1.236 1.236 tNET RR 1 R50C96[0][A] I2C_MASTER_Top_inst0/u_i2c_master/control_reg_7_s0/CLK
1.047 -0.189 tHld 1 R50C96[0][A] I2C_MASTER_Top_inst0/u_i2c_master/control_reg_7_s0

Path Statistics:

Clock Skew 0.010
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.226, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.259, 58.974%; tC2Q: 0.180, 41.026%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.236, 100.000%

Path7

Path Summary:

Slack 0.618
Data Arrival Time 1.668
Data Required Time 1.049
From key_debounceN_inst0/key_n_out2_s1
To I2C_MASTER_Top_inst0/u_i2c_master/byte_controller/CORE_CMD_0_s1
Launch Clk sclk:[R]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
1.226 1.226 tNET RR 1 R50C98[0][A] key_debounceN_inst0/key_n_out2_s1/CLK
1.406 0.180 tC2Q RR 106 R50C98[0][A] key_debounceN_inst0/key_n_out2_s1/Q
1.667 0.261 tNET RR 1 R52C97[0][A] I2C_MASTER_Top_inst0/u_i2c_master/byte_controller/CORE_CMD_0_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
1.238 1.238 tNET RR 1 R52C97[0][A] I2C_MASTER_Top_inst0/u_i2c_master/byte_controller/CORE_CMD_0_s1/CLK
1.049 -0.189 tHld 1 R52C97[0][A] I2C_MASTER_Top_inst0/u_i2c_master/byte_controller/CORE_CMD_0_s1

Path Statistics:

Clock Skew 0.012
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.226, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.261, 59.207%; tC2Q: 0.180, 40.793%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.238, 100.000%

Path8

Path Summary:

Slack 0.620
Data Arrival Time 1.668
Data Required Time 1.047
From key_debounceN_inst0/key_n_out2_s1
To I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_16_s1
Launch Clk sclk:[R]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
1.226 1.226 tNET RR 1 R50C98[0][A] key_debounceN_inst0/key_n_out2_s1/CLK
1.406 0.180 tC2Q RR 106 R50C98[0][A] key_debounceN_inst0/key_n_out2_s1/Q
1.667 0.261 tNET RR 1 R51C97[0][A] I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_16_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
1.236 1.236 tNET RR 1 R51C97[0][A] I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_16_s1/CLK
1.047 -0.189 tHld 1 R51C97[0][A] I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_16_s1

Path Statistics:

Clock Skew 0.010
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.226, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.261, 59.207%; tC2Q: 0.180, 40.793%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.236, 100.000%

Path9

Path Summary:

Slack 0.620
Data Arrival Time 1.668
Data Required Time 1.047
From key_debounceN_inst0/key_n_out2_s1
To I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/CMD_ACK_s0
Launch Clk sclk:[R]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
1.226 1.226 tNET RR 1 R50C98[0][A] key_debounceN_inst0/key_n_out2_s1/CLK
1.406 0.180 tC2Q RR 106 R50C98[0][A] key_debounceN_inst0/key_n_out2_s1/Q
1.667 0.261 tNET RR 1 R51C97[1][A] I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/CMD_ACK_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
1.236 1.236 tNET RR 1 R51C97[1][A] I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/CMD_ACK_s0/CLK
1.047 -0.189 tHld 1 R51C97[1][A] I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/CMD_ACK_s0

Path Statistics:

Clock Skew 0.010
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.226, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.261, 59.207%; tC2Q: 0.180, 40.793%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.236, 100.000%

Path10

Path Summary:

Slack 0.623
Data Arrival Time 1.665
Data Required Time 1.042
From key_debounceN_inst0/key_n_out2_s1
To I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_0_s1
Launch Clk sclk:[R]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
1.226 1.226 tNET RR 1 R50C98[0][A] key_debounceN_inst0/key_n_out2_s1/CLK
1.406 0.180 tC2Q RR 106 R50C98[0][A] key_debounceN_inst0/key_n_out2_s1/Q
1.665 0.259 tNET RR 1 R49C96[1][B] I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_0_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
1.231 1.231 tNET RR 1 R49C96[1][B] I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_0_s1/CLK
1.042 -0.189 tHld 1 R49C96[1][B] I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_0_s1

Path Statistics:

Clock Skew 0.005
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.226, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.259, 58.974%; tC2Q: 0.180, 41.026%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.231, 100.000%

Path11

Path Summary:

Slack 0.623
Data Arrival Time 1.665
Data Required Time 1.042
From key_debounceN_inst0/key_n_out2_s1
To I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_5_s1
Launch Clk sclk:[R]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
1.226 1.226 tNET RR 1 R50C98[0][A] key_debounceN_inst0/key_n_out2_s1/CLK
1.406 0.180 tC2Q RR 106 R50C98[0][A] key_debounceN_inst0/key_n_out2_s1/Q
1.665 0.259 tNET RR 1 R49C96[2][B] I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_5_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
1.231 1.231 tNET RR 1 R49C96[2][B] I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_5_s1/CLK
1.042 -0.189 tHld 1 R49C96[2][B] I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_5_s1

Path Statistics:

Clock Skew 0.005
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.226, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.259, 58.974%; tC2Q: 0.180, 41.026%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.231, 100.000%

Path12

Path Summary:

Slack 0.623
Data Arrival Time 1.665
Data Required Time 1.042
From key_debounceN_inst0/key_n_out2_s1
To I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_9_s1
Launch Clk sclk:[R]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
1.226 1.226 tNET RR 1 R50C98[0][A] key_debounceN_inst0/key_n_out2_s1/CLK
1.406 0.180 tC2Q RR 106 R50C98[0][A] key_debounceN_inst0/key_n_out2_s1/Q
1.665 0.259 tNET RR 1 R49C96[2][A] I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_9_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
1.231 1.231 tNET RR 1 R49C96[2][A] I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_9_s1/CLK
1.042 -0.189 tHld 1 R49C96[2][A] I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_9_s1

Path Statistics:

Clock Skew 0.005
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.226, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.259, 58.974%; tC2Q: 0.180, 41.026%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.231, 100.000%

Path13

Path Summary:

Slack 0.623
Data Arrival Time 1.665
Data Required Time 1.042
From key_debounceN_inst0/key_n_out2_s1
To I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_13_s1
Launch Clk sclk:[R]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
1.226 1.226 tNET RR 1 R50C98[0][A] key_debounceN_inst0/key_n_out2_s1/CLK
1.406 0.180 tC2Q RR 106 R50C98[0][A] key_debounceN_inst0/key_n_out2_s1/Q
1.665 0.259 tNET RR 1 R49C96[1][A] I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_13_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
1.231 1.231 tNET RR 1 R49C96[1][A] I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_13_s1/CLK
1.042 -0.189 tHld 1 R49C96[1][A] I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_13_s1

Path Statistics:

Clock Skew 0.005
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.226, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.259, 58.974%; tC2Q: 0.180, 41.026%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.231, 100.000%

Path14

Path Summary:

Slack 0.623
Data Arrival Time 1.665
Data Required Time 1.042
From key_debounceN_inst0/key_n_out2_s1
To I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_14_s1
Launch Clk sclk:[R]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
1.226 1.226 tNET RR 1 R50C98[0][A] key_debounceN_inst0/key_n_out2_s1/CLK
1.406 0.180 tC2Q RR 106 R50C98[0][A] key_debounceN_inst0/key_n_out2_s1/Q
1.665 0.259 tNET RR 1 R49C96[0][B] I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_14_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
1.231 1.231 tNET RR 1 R49C96[0][B] I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_14_s1/CLK
1.042 -0.189 tHld 1 R49C96[0][B] I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/c_state_14_s1

Path Statistics:

Clock Skew 0.005
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.226, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.259, 58.974%; tC2Q: 0.180, 41.026%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.231, 100.000%

Path15

Path Summary:

Slack 0.636
Data Arrival Time 1.675
Data Required Time 1.039
From key_debounceN_inst0/key_n_out2_s1
To I2C_MASTER_Top_inst0/u_i2c_master/prescale_reg0_7_s0
Launch Clk sclk:[R]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
1.226 1.226 tNET RR 1 R50C98[0][A] key_debounceN_inst0/key_n_out2_s1/CLK
1.406 0.180 tC2Q RR 106 R50C98[0][A] key_debounceN_inst0/key_n_out2_s1/Q
1.675 0.269 tNET RR 1 R47C98[2][A] I2C_MASTER_Top_inst0/u_i2c_master/prescale_reg0_7_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
1.227 1.227 tNET RR 1 R47C98[2][A] I2C_MASTER_Top_inst0/u_i2c_master/prescale_reg0_7_s0/CLK
1.039 -0.189 tHld 1 R47C98[2][A] I2C_MASTER_Top_inst0/u_i2c_master/prescale_reg0_7_s0

Path Statistics:

Clock Skew 0.001
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.226, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.269, 59.889%; tC2Q: 0.180, 40.111%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.227, 100.000%

Path16

Path Summary:

Slack 0.636
Data Arrival Time 1.675
Data Required Time 1.039
From key_debounceN_inst0/key_n_out2_s1
To I2C_MASTER_Top_inst0/u_i2c_master/prescale_reg1_0_s0
Launch Clk sclk:[R]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
1.226 1.226 tNET RR 1 R50C98[0][A] key_debounceN_inst0/key_n_out2_s1/CLK
1.406 0.180 tC2Q RR 106 R50C98[0][A] key_debounceN_inst0/key_n_out2_s1/Q
1.675 0.269 tNET RR 1 R47C98[1][A] I2C_MASTER_Top_inst0/u_i2c_master/prescale_reg1_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
1.227 1.227 tNET RR 1 R47C98[1][A] I2C_MASTER_Top_inst0/u_i2c_master/prescale_reg1_0_s0/CLK
1.039 -0.189 tHld 1 R47C98[1][A] I2C_MASTER_Top_inst0/u_i2c_master/prescale_reg1_0_s0

Path Statistics:

Clock Skew 0.001
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.226, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.269, 59.889%; tC2Q: 0.180, 40.111%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.227, 100.000%

Path17

Path Summary:

Slack 0.636
Data Arrival Time 1.675
Data Required Time 1.039
From key_debounceN_inst0/key_n_out2_s1
To I2C_MASTER_Top_inst0/u_i2c_master/prescale_reg1_7_s0
Launch Clk sclk:[R]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
1.226 1.226 tNET RR 1 R50C98[0][A] key_debounceN_inst0/key_n_out2_s1/CLK
1.406 0.180 tC2Q RR 106 R50C98[0][A] key_debounceN_inst0/key_n_out2_s1/Q
1.675 0.269 tNET RR 1 R47C98[1][B] I2C_MASTER_Top_inst0/u_i2c_master/prescale_reg1_7_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
1.227 1.227 tNET RR 1 R47C98[1][B] I2C_MASTER_Top_inst0/u_i2c_master/prescale_reg1_7_s0/CLK
1.039 -0.189 tHld 1 R47C98[1][B] I2C_MASTER_Top_inst0/u_i2c_master/prescale_reg1_7_s0

Path Statistics:

Clock Skew 0.001
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.226, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.269, 59.889%; tC2Q: 0.180, 40.111%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.227, 100.000%

Path18

Path Summary:

Slack 0.636
Data Arrival Time 1.675
Data Required Time 1.039
From key_debounceN_inst0/key_n_out2_s1
To I2C_MASTER_Top_inst0/u_i2c_master/prescale_reg0_0_s0
Launch Clk sclk:[R]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
1.226 1.226 tNET RR 1 R50C98[0][A] key_debounceN_inst0/key_n_out2_s1/CLK
1.406 0.180 tC2Q RR 106 R50C98[0][A] key_debounceN_inst0/key_n_out2_s1/Q
1.675 0.269 tNET RR 1 R47C98[0][A] I2C_MASTER_Top_inst0/u_i2c_master/prescale_reg0_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
1.227 1.227 tNET RR 1 R47C98[0][A] I2C_MASTER_Top_inst0/u_i2c_master/prescale_reg0_0_s0/CLK
1.039 -0.189 tHld 1 R47C98[0][A] I2C_MASTER_Top_inst0/u_i2c_master/prescale_reg0_0_s0

Path Statistics:

Clock Skew 0.001
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.226, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.269, 59.889%; tC2Q: 0.180, 40.111%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.227, 100.000%

Path19

Path Summary:

Slack 0.638
Data Arrival Time 1.670
Data Required Time 1.032
From key_debounceN_inst0/key_n_out2_s1
To I2C_MASTER_Top_inst0/u_i2c_master/prescale_reg1_2_s0
Launch Clk sclk:[R]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
1.226 1.226 tNET RR 1 R50C98[0][A] key_debounceN_inst0/key_n_out2_s1/CLK
1.406 0.180 tC2Q RR 106 R50C98[0][A] key_debounceN_inst0/key_n_out2_s1/Q
1.670 0.264 tNET RR 1 R48C97[1][A] I2C_MASTER_Top_inst0/u_i2c_master/prescale_reg1_2_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
1.221 1.221 tNET RR 1 R48C97[1][A] I2C_MASTER_Top_inst0/u_i2c_master/prescale_reg1_2_s0/CLK
1.032 -0.189 tHld 1 R48C97[1][A] I2C_MASTER_Top_inst0/u_i2c_master/prescale_reg1_2_s0

Path Statistics:

Clock Skew -0.005
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.226, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.264, 59.437%; tC2Q: 0.180, 40.563%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.221, 100.000%

Path20

Path Summary:

Slack 0.638
Data Arrival Time 1.670
Data Required Time 1.032
From key_debounceN_inst0/key_n_out2_s1
To I2C_MASTER_Top_inst0/u_i2c_master/prescale_reg1_3_s0
Launch Clk sclk:[R]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
1.226 1.226 tNET RR 1 R50C98[0][A] key_debounceN_inst0/key_n_out2_s1/CLK
1.406 0.180 tC2Q RR 106 R50C98[0][A] key_debounceN_inst0/key_n_out2_s1/Q
1.670 0.264 tNET RR 1 R48C97[1][B] I2C_MASTER_Top_inst0/u_i2c_master/prescale_reg1_3_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
1.221 1.221 tNET RR 1 R48C97[1][B] I2C_MASTER_Top_inst0/u_i2c_master/prescale_reg1_3_s0/CLK
1.032 -0.189 tHld 1 R48C97[1][B] I2C_MASTER_Top_inst0/u_i2c_master/prescale_reg1_3_s0

Path Statistics:

Clock Skew -0.005
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.226, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.264, 59.437%; tC2Q: 0.180, 40.563%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.221, 100.000%

Path21

Path Summary:

Slack 0.638
Data Arrival Time 1.670
Data Required Time 1.032
From key_debounceN_inst0/key_n_out2_s1
To I2C_MASTER_Top_inst0/u_i2c_master/prescale_reg1_4_s0
Launch Clk sclk:[R]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
1.226 1.226 tNET RR 1 R50C98[0][A] key_debounceN_inst0/key_n_out2_s1/CLK
1.406 0.180 tC2Q RR 106 R50C98[0][A] key_debounceN_inst0/key_n_out2_s1/Q
1.670 0.264 tNET RR 1 R48C97[2][A] I2C_MASTER_Top_inst0/u_i2c_master/prescale_reg1_4_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
1.221 1.221 tNET RR 1 R48C97[2][A] I2C_MASTER_Top_inst0/u_i2c_master/prescale_reg1_4_s0/CLK
1.032 -0.189 tHld 1 R48C97[2][A] I2C_MASTER_Top_inst0/u_i2c_master/prescale_reg1_4_s0

Path Statistics:

Clock Skew -0.005
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.226, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.264, 59.437%; tC2Q: 0.180, 40.563%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.221, 100.000%

Path22

Path Summary:

Slack 0.638
Data Arrival Time 1.670
Data Required Time 1.032
From key_debounceN_inst0/key_n_out2_s1
To I2C_MASTER_Top_inst0/u_i2c_master/prescale_reg1_5_s0
Launch Clk sclk:[R]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
1.226 1.226 tNET RR 1 R50C98[0][A] key_debounceN_inst0/key_n_out2_s1/CLK
1.406 0.180 tC2Q RR 106 R50C98[0][A] key_debounceN_inst0/key_n_out2_s1/Q
1.670 0.264 tNET RR 1 R48C97[2][B] I2C_MASTER_Top_inst0/u_i2c_master/prescale_reg1_5_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
1.221 1.221 tNET RR 1 R48C97[2][B] I2C_MASTER_Top_inst0/u_i2c_master/prescale_reg1_5_s0/CLK
1.032 -0.189 tHld 1 R48C97[2][B] I2C_MASTER_Top_inst0/u_i2c_master/prescale_reg1_5_s0

Path Statistics:

Clock Skew -0.005
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.226, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.264, 59.437%; tC2Q: 0.180, 40.563%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.221, 100.000%

Path23

Path Summary:

Slack 0.638
Data Arrival Time 1.670
Data Required Time 1.032
From key_debounceN_inst0/key_n_out2_s1
To I2C_MASTER_Top_inst0/u_i2c_master/prescale_reg1_6_s0
Launch Clk sclk:[R]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
1.226 1.226 tNET RR 1 R50C98[0][A] key_debounceN_inst0/key_n_out2_s1/CLK
1.406 0.180 tC2Q RR 106 R50C98[0][A] key_debounceN_inst0/key_n_out2_s1/Q
1.670 0.264 tNET RR 1 R48C97[3][A] I2C_MASTER_Top_inst0/u_i2c_master/prescale_reg1_6_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
1.221 1.221 tNET RR 1 R48C97[3][A] I2C_MASTER_Top_inst0/u_i2c_master/prescale_reg1_6_s0/CLK
1.032 -0.189 tHld 1 R48C97[3][A] I2C_MASTER_Top_inst0/u_i2c_master/prescale_reg1_6_s0

Path Statistics:

Clock Skew -0.005
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.226, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.264, 59.437%; tC2Q: 0.180, 40.563%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.221, 100.000%

Path24

Path Summary:

Slack 0.638
Data Arrival Time 1.670
Data Required Time 1.032
From key_debounceN_inst0/key_n_out2_s1
To I2C_MASTER_Top_inst0/u_i2c_master/prescale_reg0_5_s0
Launch Clk sclk:[R]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
1.226 1.226 tNET RR 1 R50C98[0][A] key_debounceN_inst0/key_n_out2_s1/CLK
1.406 0.180 tC2Q RR 106 R50C98[0][A] key_debounceN_inst0/key_n_out2_s1/Q
1.670 0.264 tNET RR 1 R48C97[0][A] I2C_MASTER_Top_inst0/u_i2c_master/prescale_reg0_5_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
1.221 1.221 tNET RR 1 R48C97[0][A] I2C_MASTER_Top_inst0/u_i2c_master/prescale_reg0_5_s0/CLK
1.032 -0.189 tHld 1 R48C97[0][A] I2C_MASTER_Top_inst0/u_i2c_master/prescale_reg0_5_s0

Path Statistics:

Clock Skew -0.005
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.226, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.264, 59.437%; tC2Q: 0.180, 40.563%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.221, 100.000%

Path25

Path Summary:

Slack 0.647
Data Arrival Time 1.675
Data Required Time 1.027
From key_debounceN_inst0/key_n_out2_s1
To I2C_MASTER_Top_inst0/u_i2c_master/prescale_reg0_1_s0
Launch Clk sclk:[R]
Latch Clk sclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
1.226 1.226 tNET RR 1 R50C98[0][A] key_debounceN_inst0/key_n_out2_s1/CLK
1.406 0.180 tC2Q RR 106 R50C98[0][A] key_debounceN_inst0/key_n_out2_s1/Q
1.675 0.269 tNET RR 1 R48C98[2][A] I2C_MASTER_Top_inst0/u_i2c_master/prescale_reg0_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sclk
0.000 0.000 tCL RR 255 PLL_R[3] Gowin_PLL_inst/PLL_inst/CLKOUT0
1.216 1.216 tNET RR 1 R48C98[2][A] I2C_MASTER_Top_inst0/u_i2c_master/prescale_reg0_1_s0/CLK
1.027 -0.189 tHld 1 R48C98[2][A] I2C_MASTER_Top_inst0/u_i2c_master/prescale_reg0_1_s0

Path Statistics:

Clock Skew -0.010
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.226, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.269, 59.889%; tC2Q: 0.180, 40.111%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.216, 100.000%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack: 5.110
Actual Width: 5.360
Required Width: 0.250
Type: High Pulse Width
Clock: O_adv7513_clk
Objects: yc422_rgb_inst/yc444_rgb_inst/r_o_6_s0

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 O_adv7513_clk
0.000 0.000 tCL RR Serdes_Top_inst/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
2.946 2.946 tNET RR yc422_rgb_inst/yc444_rgb_inst/r_o_6_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
6.734 0.000 active clock edge time
6.734 0.000 O_adv7513_clk
6.734 0.000 tCL FF Serdes_Top_inst/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
8.307 1.572 tNET FF yc422_rgb_inst/yc444_rgb_inst/r_o_6_s0/CLK

MPW2

MPW Summary:

Slack: 5.110
Actual Width: 5.360
Required Width: 0.250
Type: High Pulse Width
Clock: O_adv7513_clk
Objects: yc422_rgb_inst/yc444_rgb_inst/r_o_3_s0

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 O_adv7513_clk
0.000 0.000 tCL RR Serdes_Top_inst/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
2.946 2.946 tNET RR yc422_rgb_inst/yc444_rgb_inst/r_o_3_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
6.734 0.000 active clock edge time
6.734 0.000 O_adv7513_clk
6.734 0.000 tCL FF Serdes_Top_inst/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
8.307 1.572 tNET FF yc422_rgb_inst/yc444_rgb_inst/r_o_3_s0/CLK

MPW3

MPW Summary:

Slack: 5.110
Actual Width: 5.360
Required Width: 0.250
Type: High Pulse Width
Clock: O_adv7513_clk
Objects: yc422_rgb_inst/yc444_rgb_inst/g_o_0_s0

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 O_adv7513_clk
0.000 0.000 tCL RR Serdes_Top_inst/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
2.946 2.946 tNET RR yc422_rgb_inst/yc444_rgb_inst/g_o_0_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
6.734 0.000 active clock edge time
6.734 0.000 O_adv7513_clk
6.734 0.000 tCL FF Serdes_Top_inst/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
8.307 1.572 tNET FF yc422_rgb_inst/yc444_rgb_inst/g_o_0_s0/CLK

MPW4

MPW Summary:

Slack: 5.110
Actual Width: 5.360
Required Width: 0.250
Type: High Pulse Width
Clock: O_adv7513_clk
Objects: yc422_rgb_inst/yc444_rgb_inst/b_o_7_s0

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 O_adv7513_clk
0.000 0.000 tCL RR Serdes_Top_inst/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
2.946 2.946 tNET RR yc422_rgb_inst/yc444_rgb_inst/b_o_7_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
6.734 0.000 active clock edge time
6.734 0.000 O_adv7513_clk
6.734 0.000 tCL FF Serdes_Top_inst/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
8.307 1.572 tNET FF yc422_rgb_inst/yc444_rgb_inst/b_o_7_s0/CLK

MPW5

MPW Summary:

Slack: 5.110
Actual Width: 5.360
Required Width: 0.250
Type: High Pulse Width
Clock: O_adv7513_clk
Objects: yc422_rgb_inst/yc444_rgb_inst/vs_o_3_s0

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 O_adv7513_clk
0.000 0.000 tCL RR Serdes_Top_inst/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
2.946 2.946 tNET RR yc422_rgb_inst/yc444_rgb_inst/vs_o_3_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
6.734 0.000 active clock edge time
6.734 0.000 O_adv7513_clk
6.734 0.000 tCL FF Serdes_Top_inst/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
8.307 1.572 tNET FF yc422_rgb_inst/yc444_rgb_inst/vs_o_3_s0/CLK

MPW6

MPW Summary:

Slack: 5.115
Actual Width: 5.365
Required Width: 0.250
Type: High Pulse Width
Clock: O_adv7513_clk
Objects: yc422_rgb_inst/yc444_rgb_inst/dout_valid_s0

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 O_adv7513_clk
0.000 0.000 tCL RR Serdes_Top_inst/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
2.937 2.937 tNET RR yc422_rgb_inst/yc444_rgb_inst/dout_valid_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
6.734 0.000 active clock edge time
6.734 0.000 O_adv7513_clk
6.734 0.000 tCL FF Serdes_Top_inst/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
8.302 1.567 tNET FF yc422_rgb_inst/yc444_rgb_inst/dout_valid_s0/CLK

MPW7

MPW Summary:

Slack: 5.115
Actual Width: 5.365
Required Width: 0.250
Type: High Pulse Width
Clock: O_adv7513_clk
Objects: yc422_rgb_inst/yc444_rgb_inst/r_o_7_s0

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 O_adv7513_clk
0.000 0.000 tCL RR Serdes_Top_inst/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
2.937 2.937 tNET RR yc422_rgb_inst/yc444_rgb_inst/r_o_7_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
6.734 0.000 active clock edge time
6.734 0.000 O_adv7513_clk
6.734 0.000 tCL FF Serdes_Top_inst/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
8.302 1.567 tNET FF yc422_rgb_inst/yc444_rgb_inst/r_o_7_s0/CLK

MPW8

MPW Summary:

Slack: 5.115
Actual Width: 5.365
Required Width: 0.250
Type: High Pulse Width
Clock: O_adv7513_clk
Objects: yc422_rgb_inst/yc444_rgb_inst/hs_o_3_s0

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 O_adv7513_clk
0.000 0.000 tCL RR Serdes_Top_inst/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
2.937 2.937 tNET RR yc422_rgb_inst/yc444_rgb_inst/hs_o_3_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
6.734 0.000 active clock edge time
6.734 0.000 O_adv7513_clk
6.734 0.000 tCL FF Serdes_Top_inst/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
8.302 1.567 tNET FF yc422_rgb_inst/yc444_rgb_inst/hs_o_3_s0/CLK

MPW9

MPW Summary:

Slack: 5.115
Actual Width: 5.365
Required Width: 0.250
Type: High Pulse Width
Clock: O_adv7513_clk
Objects: yc422_rgb_inst/yc444_rgb_inst/r_o_4_s0

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 O_adv7513_clk
0.000 0.000 tCL RR Serdes_Top_inst/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
2.937 2.937 tNET RR yc422_rgb_inst/yc444_rgb_inst/r_o_4_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
6.734 0.000 active clock edge time
6.734 0.000 O_adv7513_clk
6.734 0.000 tCL FF Serdes_Top_inst/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
8.302 1.567 tNET FF yc422_rgb_inst/yc444_rgb_inst/r_o_4_s0/CLK

MPW10

MPW Summary:

Slack: 5.115
Actual Width: 5.365
Required Width: 0.250
Type: High Pulse Width
Clock: O_adv7513_clk
Objects: yc422_rgb_inst/yc444_rgb_inst/b_o_3_s0

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 O_adv7513_clk
0.000 0.000 tCL RR Serdes_Top_inst/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
2.937 2.937 tNET RR yc422_rgb_inst/yc444_rgb_inst/b_o_3_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
6.734 0.000 active clock edge time
6.734 0.000 O_adv7513_clk
6.734 0.000 tCL FF Serdes_Top_inst/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
8.302 1.567 tNET FF yc422_rgb_inst/yc444_rgb_inst/b_o_3_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT NET NAME WORST SLACK MAX DELAY
1461 O_led_d_0[2] 1.899 5.264
1022 lane3_pcs_tx_o_fabric_clk 0.347 2.691
581 O_adv7513_clk_d 4.276 3.098
255 sclk 11.804 2.691
106 O_led_d_0[3] 16.844 7.763
86 data0_g[7] 7.166 2.916
64 data0_r[7] 5.570 1.745
64 I_de_d2 6.954 2.615
52 data0_b[7] 7.011 3.429
49 hd_match_phase[2] 8.884 1.692

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC ROUTE CONGESTIONS
R54C120 66.67%
R54C97 59.72%
R62C136 59.72%
R50C108 58.33%
R60C97 58.33%
R48C115 56.94%
R52C97 56.94%
R52C99 56.94%
R47C115 56.94%
R60C119 56.94%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type State Detail Command
TC_CLOCK Actived create_clock -name O_led -period 10 -waveform {0 5} [get_nets {O_led_d_0[2]}]
TC_CLOCK Actived create_clock -name lane3_pcs_tx_o_fabric_clk -period 13.468 -waveform {0 6.734} [get_nets {lane3_pcs_tx_o_fabric_clk}] -add
TC_CLOCK Actived create_clock -name O_adv7513_clk -period 13.468 -waveform {0 6.734} [get_ports {O_adv7513_clk}] -add
TC_CLOCK Actived create_clock -name sclk -period 20 -waveform {0 10} [get_nets {sclk}] -add
TC_CLOCK Actived create_clock -name I_clk -period 20 -waveform {0 10} [get_ports {I_clk}] -add
TC_FALSE_PATH Actived set_false_path -from [get_clocks {sclk}] -to [get_clocks {lane3_pcs_tx_o_fabric_clk}]
TC_FALSE_PATH Actived set_false_path -from [get_clocks {lane3_pcs_tx_o_fabric_clk}] -to [get_clocks {sclk}]
TC_FALSE_PATH Actived set_false_path -from [get_clocks {sclk}] -to [get_clocks {O_adv7513_clk}]
TC_FALSE_PATH Actived set_false_path -from [get_clocks {O_adv7513_clk}] -to [get_clocks {sclk}]
TC_CLOCK_GROUP Actived set_clock_groups -asynchronous -group [get_clocks {lane3_pcs_tx_o_fabric_clk}] -group [get_clocks {O_led}] -group [get_clocks {O_adv7513_clk}]