Synthesis Messages

Report Title GowinSynthesis Report
Design File E:\Gowin_Board_5ast_SDI\Gowin_SDI_RefDesign_231025_t1_720_60p\project\src\adv7513_iic_init.v
E:\Gowin_Board_5ast_SDI\Gowin_SDI_RefDesign_231025_t1_720_60p\project\src\gowin_pll\gowin_pll.v
E:\Gowin_Board_5ast_SDI\Gowin_SDI_RefDesign_231025_t1_720_60p\project\src\i2c_master\i2c_master.v
E:\Gowin_Board_5ast_SDI\Gowin_SDI_RefDesign_231025_t1_720_60p\project\src\key_debounceN.v
E:\Gowin_Board_5ast_SDI\Gowin_SDI_RefDesign_231025_t1_720_60p\project\src\rgb_to_yc\rgb_yc422.v
E:\Gowin_Board_5ast_SDI\Gowin_SDI_RefDesign_231025_t1_720_60p\project\src\serdes\sdi\sdi.v
E:\Gowin_Board_5ast_SDI\Gowin_SDI_RefDesign_231025_t1_720_60p\project\src\serdes\serdes.v
E:\Gowin_Board_5ast_SDI\Gowin_SDI_RefDesign_231025_t1_720_60p\project\src\testpattern.v
E:\Gowin_Board_5ast_SDI\Gowin_SDI_RefDesign_231025_t1_720_60p\project\src\video_top.v
E:\Gowin_Board_5ast_SDI\Gowin_SDI_RefDesign_231025_t1_720_60p\project\src\yc_to_rgb\yc422_rgb.v
GowinSynthesis Constraints File ---
Version V1.9.9 Beta-4
Part Number GW5AST-LV138FPG676AES
Device GW5AST-138
Device Version B
Created Time Wed Oct 25 15:45:07 2023
Legal Announcement Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module video_top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.796s, Elapsed time = 0h 0m 0.911s, Peak memory usage = 102.227MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.082s, Peak memory usage = 102.227MB
    Optimizing Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.054s, Peak memory usage = 102.227MB
    Optimizing Phase 2: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.108s, Peak memory usage = 102.227MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.037s, Peak memory usage = 102.227MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 102.227MB
    Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 102.227MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 102.227MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.103s, Peak memory usage = 102.227MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.044s, Peak memory usage = 102.227MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.014s, Peak memory usage = 102.227MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 109.074MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.135s, Peak memory usage = 109.074MB
Generate output files:
    CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.115s, Peak memory usage = 109.074MB
Total Time and Memory Usage CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 109.074MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 36
I/O Buf 36
    IBUF 2
    OBUF 32
    IOBUF 2
Register 1855
    DFFSE 1
    DFFRE 66
    DFFPE 20
    DFFCE 1767
    DLCE 1
LUT 2505
    LUT2 330
    LUT3 719
    LUT4 1456
ALU 527
    ALU 527
SSRAM 3
    RAM16S4 3
INV 29
    INV 29
CLOCK 1
    PLL 1
GTR12_QUAD 1

Resource Utilization Summary

Resource Usage Utilization
Logic 3079(2534 LUT, 527 ALU, 3 RAM16) / 138240 3%
Register 1855 / 139140 2%
  --Register as Latch 1 / 139140 <1%
  --Register as FF 1854 / 139140 2%
BSRAM 0 / 340 0%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
I_clk Base 20.000 50.0 0.000 10.000 I_clk_ibuf/I
rgb_yc422_inst/yc444_yc422_inst/rst_n_d Base 10.000 100.0 0.000 5.000 rgb_yc422_inst/yc444_yc422_inst/rst_n_d_s/O
Gowin_PLL_inst/PLL_inst/CLKOUT0.default_gen_clk Generated 20.000 50.0 0.000 10.000 I_clk_ibuf/I I_clk Gowin_PLL_inst/PLL_inst/CLKOUT0

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 Gowin_PLL_inst/PLL_inst/CLKOUT0.default_gen_clk 50.0(MHz) 187.5(MHz) 8 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 2.834
Data Arrival Time 2.238
Data Required Time 5.072
From key_debounceN_inst0/key_n_out1_s1
To rgb_yc422_inst/yc444_yc422_inst/count_s6
Launch Clk Gowin_PLL_inst/PLL_inst/CLKOUT0.default_gen_clk[F]
Latch Clk rgb_yc422_inst/yc444_yc422_inst/rst_n_d[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 Gowin_PLL_inst/PLL_inst/CLKOUT0.default_gen_clk
0.825 0.825 tCL RR 255 Gowin_PLL_inst/PLL_inst/CLKOUT0
1.005 0.180 tNET RR 1 key_debounceN_inst0/key_n_out1_s1/CLK
1.373 0.367 tC2Q RR 15 key_debounceN_inst0/key_n_out1_s1/Q
1.553 0.180 tNET RR 1 rgb_yc422_inst/yc444_yc422_inst/n249_s1/I0
2.058 0.505 tINS RR 2 rgb_yc422_inst/yc444_yc422_inst/n249_s1/F
2.238 0.180 tNET RR 1 rgb_yc422_inst/yc444_yc422_inst/count_s6/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
5.000 0.000 rgb_yc422_inst/yc444_yc422_inst/rst_n_d
5.000 0.000 tCL FF 1 rgb_yc422_inst/yc444_yc422_inst/rst_n_d_s/O
5.168 0.168 tNET FF 1 rgb_yc422_inst/yc444_yc422_inst/count_s6/G
5.133 -0.035 tUnc rgb_yc422_inst/yc444_yc422_inst/count_s6
5.072 -0.061 tSu 1 rgb_yc422_inst/yc444_yc422_inst/count_s6
Path Statistics:
Clock Skew: -0.837
Setup Relationship: 5.000
Logic Level: 2
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay: cell: 0.505, 40.993%; route: 0.360, 29.211%; tC2Q: 0.367, 29.796%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.180, 100.000%

Path 2

Path Summary:
Slack 14.667
Data Arrival Time 6.277
Data Required Time 20.944
From Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_6_s0
To Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/current_state_2_s0
Launch Clk Gowin_PLL_inst/PLL_inst/CLKOUT0.default_gen_clk[R]
Latch Clk Gowin_PLL_inst/PLL_inst/CLKOUT0.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 Gowin_PLL_inst/PLL_inst/CLKOUT0.default_gen_clk
0.825 0.825 tCL RR 255 Gowin_PLL_inst/PLL_inst/CLKOUT0
1.005 0.180 tNET RR 1 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_6_s0/CLK
1.373 0.367 tC2Q RR 3 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_6_s0/Q
1.553 0.180 tNET RR 1 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/next_state_0_s15/I0
2.058 0.505 tINS RR 1 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/next_state_0_s15/F
2.238 0.180 tNET RR 1 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/next_state_0_s14/I0
2.743 0.505 tINS RR 1 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/next_state_0_s14/F
2.923 0.180 tNET RR 1 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/next_state_0_s11/I2
3.366 0.443 tINS RR 1 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/next_state_0_s11/F
3.546 0.180 tNET RR 1 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/next_state_0_s7/I1
4.041 0.496 tINS RR 1 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/next_state_0_s7/F
4.221 0.180 tNET RR 1 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/next_state_0_s5/I0
4.727 0.505 tINS RR 3 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/next_state_0_s5/F
4.907 0.180 tNET RR 1 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/next_state_2_s2/I0
5.412 0.505 tINS RR 1 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/next_state_2_s2/F
5.592 0.180 tNET RR 1 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/next_state_2_s1/I0
6.097 0.505 tINS RR 1 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/next_state_2_s1/F
6.277 0.180 tNET RR 1 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/current_state_2_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 Gowin_PLL_inst/PLL_inst/CLKOUT0.default_gen_clk
20.825 0.825 tCL RR 255 Gowin_PLL_inst/PLL_inst/CLKOUT0
21.005 0.180 tNET RR 1 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/current_state_2_s0/CLK
20.944 -0.061 tSu 1 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/current_state_2_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 8
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay: cell: 3.464, 65.718%; route: 1.440, 27.316%; tC2Q: 0.367, 6.966%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.180, 100.000%

Path 3

Path Summary:
Slack 14.677
Data Arrival Time 6.267
Data Required Time 20.944
From Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_6_s0
To Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/current_state_1_s0
Launch Clk Gowin_PLL_inst/PLL_inst/CLKOUT0.default_gen_clk[R]
Latch Clk Gowin_PLL_inst/PLL_inst/CLKOUT0.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 Gowin_PLL_inst/PLL_inst/CLKOUT0.default_gen_clk
0.825 0.825 tCL RR 255 Gowin_PLL_inst/PLL_inst/CLKOUT0
1.005 0.180 tNET RR 1 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_6_s0/CLK
1.373 0.367 tC2Q RR 3 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_6_s0/Q
1.553 0.180 tNET RR 1 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/next_state_0_s15/I0
2.058 0.505 tINS RR 1 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/next_state_0_s15/F
2.238 0.180 tNET RR 1 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/next_state_0_s14/I0
2.743 0.505 tINS RR 1 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/next_state_0_s14/F
2.923 0.180 tNET RR 1 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/next_state_0_s11/I2
3.366 0.443 tINS RR 1 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/next_state_0_s11/F
3.546 0.180 tNET RR 1 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/next_state_0_s7/I1
4.041 0.496 tINS RR 1 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/next_state_0_s7/F
4.221 0.180 tNET RR 1 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/next_state_0_s5/I0
4.727 0.505 tINS RR 3 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/next_state_0_s5/F
4.907 0.180 tNET RR 1 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/next_state_1_s2/I1
5.402 0.496 tINS RR 1 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/next_state_1_s2/F
5.582 0.180 tNET RR 1 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/next_state_1_s1/I0
6.087 0.505 tINS RR 1 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/next_state_1_s1/F
6.267 0.180 tNET RR 1 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/current_state_1_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 Gowin_PLL_inst/PLL_inst/CLKOUT0.default_gen_clk
20.825 0.825 tCL RR 255 Gowin_PLL_inst/PLL_inst/CLKOUT0
21.005 0.180 tNET RR 1 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/current_state_1_s0/CLK
20.944 -0.061 tSu 1 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/current_state_1_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 8
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay: cell: 3.455, 65.656%; route: 1.440, 27.366%; tC2Q: 0.367, 6.978%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.180, 100.000%

Path 4

Path Summary:
Slack 14.739
Data Arrival Time 6.205
Data Required Time 20.944
From Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_6_s0
To Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/current_state_0_s0
Launch Clk Gowin_PLL_inst/PLL_inst/CLKOUT0.default_gen_clk[R]
Latch Clk Gowin_PLL_inst/PLL_inst/CLKOUT0.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 Gowin_PLL_inst/PLL_inst/CLKOUT0.default_gen_clk
0.825 0.825 tCL RR 255 Gowin_PLL_inst/PLL_inst/CLKOUT0
1.005 0.180 tNET RR 1 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_6_s0/CLK
1.373 0.367 tC2Q RR 3 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_6_s0/Q
1.553 0.180 tNET RR 1 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/next_state_0_s15/I0
2.058 0.505 tINS RR 1 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/next_state_0_s15/F
2.238 0.180 tNET RR 1 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/next_state_0_s14/I0
2.743 0.505 tINS RR 1 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/next_state_0_s14/F
2.923 0.180 tNET RR 1 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/next_state_0_s11/I2
3.366 0.443 tINS RR 1 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/next_state_0_s11/F
3.546 0.180 tNET RR 1 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/next_state_0_s7/I1
4.041 0.496 tINS RR 1 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/next_state_0_s7/F
4.221 0.180 tNET RR 1 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/next_state_0_s5/I0
4.727 0.505 tINS RR 3 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/next_state_0_s5/F
4.907 0.180 tNET RR 1 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/next_state_0_s2/I2
5.349 0.443 tINS RR 1 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/next_state_0_s2/F
5.529 0.180 tNET RR 1 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/next_state_0_s1/I1
6.025 0.496 tINS RR 1 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/next_state_0_s1/F
6.205 0.180 tNET RR 1 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/current_state_0_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 Gowin_PLL_inst/PLL_inst/CLKOUT0.default_gen_clk
20.825 0.825 tCL RR 255 Gowin_PLL_inst/PLL_inst/CLKOUT0
21.005 0.180 tNET RR 1 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/current_state_0_s0/CLK
20.944 -0.061 tSu 1 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/current_state_0_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 8
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay: cell: 3.392, 65.244%; route: 1.440, 27.694%; tC2Q: 0.367, 7.062%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.180, 100.000%

Path 5

Path Summary:
Slack 15.364
Data Arrival Time 5.580
Data Required Time 20.944
From Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_1_s0
To Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_21_s0
Launch Clk Gowin_PLL_inst/PLL_inst/CLKOUT0.default_gen_clk[R]
Latch Clk Gowin_PLL_inst/PLL_inst/CLKOUT0.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 Gowin_PLL_inst/PLL_inst/CLKOUT0.default_gen_clk
0.825 0.825 tCL RR 255 Gowin_PLL_inst/PLL_inst/CLKOUT0
1.005 0.180 tNET RR 1 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_1_s0/CLK
1.373 0.367 tC2Q RR 4 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_1_s0/Q
1.553 0.180 tNET RR 1 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/n123_s2/I0
2.058 0.505 tINS RR 4 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/n123_s2/F
2.238 0.180 tNET RR 1 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/n120_s2/I3
2.490 0.252 tINS RR 4 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/n120_s2/F
2.670 0.180 tNET RR 1 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/n116_s2/I3
2.922 0.252 tINS RR 4 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/n116_s2/F
3.102 0.180 tNET RR 1 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/n113_s2/I3
3.354 0.252 tINS RR 6 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/n113_s2/F
3.534 0.180 tNET RR 1 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/n110_s5/I0
4.039 0.505 tINS RR 5 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/n110_s5/F
4.219 0.180 tNET RR 1 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/n106_s2/I0
4.724 0.505 tINS RR 2 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/n106_s2/F
4.904 0.180 tNET RR 1 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/n106_s1/I1
5.400 0.496 tINS RR 1 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/n106_s1/F
5.580 0.180 tNET RR 1 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_21_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 Gowin_PLL_inst/PLL_inst/CLKOUT0.default_gen_clk
20.825 0.825 tCL RR 255 Gowin_PLL_inst/PLL_inst/CLKOUT0
21.005 0.180 tNET RR 1 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_21_s0/CLK
20.944 -0.061 tSu 1 Serdes_Top_inst/SDI_Top_inst/sdi_wrapper_inst/rx_sdi_top_inst/rx_data_align_inst/hd_time_cnt_21_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 8
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay: cell: 2.767, 60.493%; route: 1.440, 31.480%; tC2Q: 0.367, 8.027%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.180, 100.000%