Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | C:\Gowin\Gowin_V1.9.9Beta1-1\IDE\ipcore\I2CMASTER\data\I2C_MASTER_TOP.v C:\Gowin\Gowin_V1.9.9Beta1-1\IDE\ipcore\I2CMASTER\data\I2C_MASTER.vp |
GowinSynthesis Constraints File | --- |
Version | GowinSynthesis V1.9.9 Beta1-1 |
Part Number | GW5AT-LV138FPG676AES |
Device | GW5AT-138 |
Created Time | Mon Nov 14 15:17:38 2022 |
Legal Announcement | Copyright (C)2014-2022 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | I2C_MASTER_Top |
Synthesis Process | Running parser: CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.179s, Peak memory usage = 38.352MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 38.352MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 38.352MB Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 38.352MB Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 38.352MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 38.352MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 38.352MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 38.352MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 38.352MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 38.352MB Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 38.352MB Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 38.352MB Tech-Mapping Phase 3: CPU time = 0h 0m 0.687s, Elapsed time = 0h 0m 0.69s, Peak memory usage = 51.801MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.03s, Peak memory usage = 51.801MB Generate output files: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.024s, Peak memory usage = 51.801MB |
Total Time and Memory Usage | CPU time = 0h 0m 0.918s, Elapsed time = 0h 0m 0.955s, Peak memory usage = 51.801MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 29 |
I/O Buf | 29 |
    IBUF | 18 |
    OBUF | 9 |
    IOBUF | 2 |
Register | 124 |
    DFFPE | 7 |
    DFFCE | 117 |
LUT | 216 |
    LUT2 | 27 |
    LUT3 | 75 |
    LUT4 | 114 |
INV | 1 |
    INV | 1 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 217(217 LUTs, 0 ALUs) / 138240 | 1% |
Register | 124 / 139176 | 1% |
  --Register as Latch | 0 / 139176 | 0% |
  --Register as FF | 124 / 139176 | 1% |
BSRAM | 0 / 340 | 0% |
Timing
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|
I_CLK | Base | 10.000 | 100.0 | 0.000 | 5.000 | I_CLK_ibuf/I |
Max Frequency Summary:
No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | I_CLK | 100.0(MHz) | 315.9(MHz) | 5 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | 6.835 |
Data Arrival Time | 3.879 |
Data Required Time | 10.713 |
From | u_i2c_master/bit_controller/cnt_10_s1 |
To | u_i2c_master/bit_controller/cnt_14_s1 |
Launch Clk | I_CLK[R] |
Latch Clk | I_CLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | I_CLK | |||
0.000 | 0.000 | tCL | RR | 1 | I_CLK_ibuf/I |
0.588 | 0.588 | tINS | RR | 124 | I_CLK_ibuf/O |
0.743 | 0.155 | tNET | RR | 1 | u_i2c_master/bit_controller/cnt_10_s1/CLK |
0.943 | 0.200 | tC2Q | RF | 4 | u_i2c_master/bit_controller/cnt_10_s1/Q |
1.148 | 0.204 | tNET | FF | 1 | u_i2c_master/bit_controller/n13_s3/I1 |
1.626 | 0.478 | tINS | FF | 1 | u_i2c_master/bit_controller/n13_s3/F |
1.830 | 0.204 | tNET | FF | 1 | u_i2c_master/bit_controller/n13_s1/I1 |
2.309 | 0.478 | tINS | FF | 4 | u_i2c_master/bit_controller/n13_s1/F |
2.513 | 0.204 | tNET | FF | 1 | u_i2c_master/bit_controller/n32_s1/I1 |
2.992 | 0.478 | tINS | FF | 1 | u_i2c_master/bit_controller/n32_s1/F |
3.196 | 0.204 | tNET | FF | 1 | u_i2c_master/bit_controller/n32_s0/I1 |
3.674 | 0.478 | tINS | FF | 1 | u_i2c_master/bit_controller/n32_s0/F |
3.879 | 0.204 | tNET | FF | 1 | u_i2c_master/bit_controller/cnt_14_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | I_CLK | |||
10.000 | 0.000 | tCL | RR | 1 | I_CLK_ibuf/I |
10.588 | 0.588 | tINS | RR | 124 | I_CLK_ibuf/O |
10.743 | 0.155 | tNET | RR | 1 | u_i2c_master/bit_controller/cnt_14_s1/CLK |
10.713 | -0.030 | tSu | 1 | u_i2c_master/bit_controller/cnt_14_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.588, 79.130%; route: 0.155, 20.870% |
Arrival Data Path Delay: | cell: 1.914, 61.039%; route: 1.021, 32.582%; tC2Q: 0.200, 6.379% |
Required Clock Path Delay: | cell: 0.588, 79.130%; route: 0.155, 20.870% |
Path 2
Path Summary:Slack | 6.867 |
Data Arrival Time | 3.846 |
Data Required Time | 10.713 |
From | u_i2c_master/byte_controller/c_state_2_s0 |
To | u_i2c_master/byte_controller/CORE_CMD_2_s0 |
Launch Clk | I_CLK[R] |
Latch Clk | I_CLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | I_CLK | |||
0.000 | 0.000 | tCL | RR | 1 | I_CLK_ibuf/I |
0.588 | 0.588 | tINS | RR | 124 | I_CLK_ibuf/O |
0.743 | 0.155 | tNET | RR | 1 | u_i2c_master/byte_controller/c_state_2_s0/CLK |
0.943 | 0.200 | tC2Q | RF | 8 | u_i2c_master/byte_controller/c_state_2_s0/Q |
1.148 | 0.204 | tNET | FF | 1 | u_i2c_master/byte_controller/n208_s4/I1 |
1.626 | 0.478 | tINS | FF | 2 | u_i2c_master/byte_controller/n208_s4/F |
1.830 | 0.204 | tNET | FF | 1 | u_i2c_master/byte_controller/n200_s5/I0 |
2.276 | 0.446 | tINS | FF | 1 | u_i2c_master/byte_controller/n200_s5/F |
2.480 | 0.204 | tNET | FF | 1 | u_i2c_master/byte_controller/n200_s3/I1 |
2.959 | 0.478 | tINS | FF | 2 | u_i2c_master/byte_controller/n200_s3/F |
3.163 | 0.204 | tNET | FF | 1 | u_i2c_master/byte_controller/n200_s2/I1 |
3.642 | 0.478 | tINS | FF | 1 | u_i2c_master/byte_controller/n200_s2/F |
3.846 | 0.204 | tNET | FF | 1 | u_i2c_master/byte_controller/CORE_CMD_2_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | I_CLK | |||
10.000 | 0.000 | tCL | RR | 1 | I_CLK_ibuf/I |
10.588 | 0.588 | tINS | RR | 124 | I_CLK_ibuf/O |
10.743 | 0.155 | tNET | RR | 1 | u_i2c_master/byte_controller/CORE_CMD_2_s0/CLK |
10.713 | -0.030 | tSu | 1 | u_i2c_master/byte_controller/CORE_CMD_2_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.588, 79.130%; route: 0.155, 20.870% |
Arrival Data Path Delay: | cell: 1.881, 60.628%; route: 1.021, 32.926%; tC2Q: 0.200, 6.446% |
Required Clock Path Delay: | cell: 0.588, 79.130%; route: 0.155, 20.870% |
Path 3
Path Summary:Slack | 6.867 |
Data Arrival Time | 3.846 |
Data Required Time | 10.713 |
From | u_i2c_master/byte_controller/c_state_2_s0 |
To | u_i2c_master/byte_controller/CORE_CMD_3_s0 |
Launch Clk | I_CLK[R] |
Latch Clk | I_CLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | I_CLK | |||
0.000 | 0.000 | tCL | RR | 1 | I_CLK_ibuf/I |
0.588 | 0.588 | tINS | RR | 124 | I_CLK_ibuf/O |
0.743 | 0.155 | tNET | RR | 1 | u_i2c_master/byte_controller/c_state_2_s0/CLK |
0.943 | 0.200 | tC2Q | RF | 8 | u_i2c_master/byte_controller/c_state_2_s0/Q |
1.148 | 0.204 | tNET | FF | 1 | u_i2c_master/byte_controller/n208_s4/I1 |
1.626 | 0.478 | tINS | FF | 2 | u_i2c_master/byte_controller/n208_s4/F |
1.830 | 0.204 | tNET | FF | 1 | u_i2c_master/byte_controller/n200_s5/I0 |
2.276 | 0.446 | tINS | FF | 1 | u_i2c_master/byte_controller/n200_s5/F |
2.480 | 0.204 | tNET | FF | 1 | u_i2c_master/byte_controller/n200_s3/I1 |
2.959 | 0.478 | tINS | FF | 2 | u_i2c_master/byte_controller/n200_s3/F |
3.163 | 0.204 | tNET | FF | 1 | u_i2c_master/byte_controller/n199_s2/I1 |
3.642 | 0.478 | tINS | FF | 1 | u_i2c_master/byte_controller/n199_s2/F |
3.846 | 0.204 | tNET | FF | 1 | u_i2c_master/byte_controller/CORE_CMD_3_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | I_CLK | |||
10.000 | 0.000 | tCL | RR | 1 | I_CLK_ibuf/I |
10.588 | 0.588 | tINS | RR | 124 | I_CLK_ibuf/O |
10.743 | 0.155 | tNET | RR | 1 | u_i2c_master/byte_controller/CORE_CMD_3_s0/CLK |
10.713 | -0.030 | tSu | 1 | u_i2c_master/byte_controller/CORE_CMD_3_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.588, 79.130%; route: 0.155, 20.870% |
Arrival Data Path Delay: | cell: 1.881, 60.628%; route: 1.021, 32.926%; tC2Q: 0.200, 6.446% |
Required Clock Path Delay: | cell: 0.588, 79.130%; route: 0.155, 20.870% |
Path 4
Path Summary:Slack | 6.889 |
Data Arrival Time | 3.824 |
Data Required Time | 10.713 |
From | u_i2c_master/bit_controller/c_state_3_s1 |
To | u_i2c_master/bit_controller/SCL_OEN_s1 |
Launch Clk | I_CLK[R] |
Latch Clk | I_CLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | I_CLK | |||
0.000 | 0.000 | tCL | RR | 1 | I_CLK_ibuf/I |
0.588 | 0.588 | tINS | RR | 124 | I_CLK_ibuf/O |
0.743 | 0.155 | tNET | RR | 1 | u_i2c_master/bit_controller/c_state_3_s1/CLK |
0.943 | 0.200 | tC2Q | RF | 6 | u_i2c_master/bit_controller/c_state_3_s1/Q |
1.148 | 0.204 | tNET | FF | 1 | u_i2c_master/bit_controller/n227_s6/I1 |
1.626 | 0.478 | tINS | FF | 7 | u_i2c_master/bit_controller/n227_s6/F |
1.830 | 0.204 | tNET | FF | 1 | u_i2c_master/bit_controller/n214_s4/I1 |
2.309 | 0.478 | tINS | FF | 7 | u_i2c_master/bit_controller/n214_s4/F |
2.513 | 0.204 | tNET | FF | 1 | u_i2c_master/bit_controller/n228_s4/I1 |
2.992 | 0.478 | tINS | FF | 4 | u_i2c_master/bit_controller/n228_s4/F |
3.196 | 0.204 | tNET | FF | 1 | u_i2c_master/bit_controller/SCL_OEN_s5/I0 |
3.669 | 0.473 | tINS | FR | 1 | u_i2c_master/bit_controller/SCL_OEN_s5/F |
3.824 | 0.155 | tNET | RR | 1 | u_i2c_master/bit_controller/SCL_OEN_s1/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | I_CLK | |||
10.000 | 0.000 | tCL | RR | 1 | I_CLK_ibuf/I |
10.588 | 0.588 | tINS | RR | 124 | I_CLK_ibuf/O |
10.743 | 0.155 | tNET | RR | 1 | u_i2c_master/bit_controller/SCL_OEN_s1/CLK |
10.713 | -0.030 | tSu | 1 | u_i2c_master/bit_controller/SCL_OEN_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.588, 79.130%; route: 0.155, 20.870% |
Arrival Data Path Delay: | cell: 1.908, 61.948%; route: 0.972, 31.561%; tC2Q: 0.200, 6.491% |
Required Clock Path Delay: | cell: 0.588, 79.130%; route: 0.155, 20.870% |
Path 5
Path Summary:Slack | 6.900 |
Data Arrival Time | 3.813 |
Data Required Time | 10.713 |
From | u_i2c_master/bit_controller/c_state_3_s1 |
To | u_i2c_master/bit_controller/SDA_OEN_s1 |
Launch Clk | I_CLK[R] |
Latch Clk | I_CLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | I_CLK | |||
0.000 | 0.000 | tCL | RR | 1 | I_CLK_ibuf/I |
0.588 | 0.588 | tINS | RR | 124 | I_CLK_ibuf/O |
0.743 | 0.155 | tNET | RR | 1 | u_i2c_master/bit_controller/c_state_3_s1/CLK |
0.943 | 0.200 | tC2Q | RF | 6 | u_i2c_master/bit_controller/c_state_3_s1/Q |
1.148 | 0.204 | tNET | FF | 1 | u_i2c_master/bit_controller/n227_s6/I1 |
1.626 | 0.478 | tINS | FF | 7 | u_i2c_master/bit_controller/n227_s6/F |
1.830 | 0.204 | tNET | FF | 1 | u_i2c_master/bit_controller/n226_s4/I1 |
2.309 | 0.478 | tINS | FF | 4 | u_i2c_master/bit_controller/n226_s4/F |
2.513 | 0.204 | tNET | FF | 1 | u_i2c_master/bit_controller/n230_s8/I0 |
2.959 | 0.446 | tINS | FF | 1 | u_i2c_master/bit_controller/n230_s8/F |
3.163 | 0.204 | tNET | FF | 1 | u_i2c_master/bit_controller/n230_s1/I0 |
3.609 | 0.446 | tINS | FF | 1 | u_i2c_master/bit_controller/n230_s1/F |
3.813 | 0.204 | tNET | FF | 1 | u_i2c_master/bit_controller/SDA_OEN_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | I_CLK | |||
10.000 | 0.000 | tCL | RR | 1 | I_CLK_ibuf/I |
10.588 | 0.588 | tINS | RR | 124 | I_CLK_ibuf/O |
10.743 | 0.155 | tNET | RR | 1 | u_i2c_master/bit_controller/SDA_OEN_s1/CLK |
10.713 | -0.030 | tSu | 1 | u_i2c_master/bit_controller/SDA_OEN_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.588, 79.130%; route: 0.155, 20.870% |
Arrival Data Path Delay: | cell: 1.848, 60.208%; route: 1.021, 33.277%; tC2Q: 0.200, 6.515% |
Required Clock Path Delay: | cell: 0.588, 79.130%; route: 0.155, 20.870% |