Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | D:\Gowin\Gowin_V1.9.9Beta-4_0911\Gowin_V1.9.9Beta-4\IDE\ipcore\SERDES_IP\IPlib\SDI\data\sdi_top.v D:\Gowin\Gowin_V1.9.9Beta-4_0911\Gowin_V1.9.9Beta-4\IDE\ipcore\SERDES_IP\IPlib\SDI\data\sdi_wrapper.v |
GowinSynthesis Constraints File | --- |
Version | V1.9.9 Beta-4 |
Part Number | GW5AST-LV138FPG676AES |
Device | GW5AST-138 |
Device Version | B |
Created Time | Mon Sep 11 10:56:21 2023 |
Legal Announcement | Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | SDI_Top |
Synthesis Process | Running parser: CPU time = 0h 0m 0.39s, Elapsed time = 0h 0m 0.433s, Peak memory usage = 47.484MB Running netlist conversion: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.02s, Peak memory usage = 47.484MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.079s, Peak memory usage = 47.484MB Optimizing Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.045s, Peak memory usage = 47.484MB Optimizing Phase 2: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.065s, Peak memory usage = 47.484MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.02s, Peak memory usage = 47.484MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 47.484MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 47.484MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 47.484MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.076s, Peak memory usage = 47.484MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.055s, Peak memory usage = 47.484MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.027s, Peak memory usage = 47.484MB Tech-Mapping Phase 3: CPU time = 0h 0m 6s, Elapsed time = 0h 0m 6s, Peak memory usage = 60.055MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.132s, Peak memory usage = 60.055MB Generate output files: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.102s, Peak memory usage = 60.055MB |
Total Time and Memory Usage | CPU time = 0h 0m 7s, Elapsed time = 0h 0m 7s, Peak memory usage = 60.055MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 351 |
I/O Buf | 266 |
    IBUF | 82 |
    OBUF | 184 |
Register | 1114 |
    DFFSE | 1 |
    DFFPE | 3 |
    DFFCE | 1110 |
LUT | 1565 |
    LUT2 | 193 |
    LUT3 | 496 |
    LUT4 | 876 |
ALU | 63 |
    ALU | 63 |
SSRAM | 3 |
    RAM16S4 | 3 |
INV | 12 |
    INV | 12 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 1658(1577 LUT, 63 ALU, 3 RAM16) / 138240 | 2% |
Register | 1114 / 139140 | <1% |
  --Register as Latch | 0 / 139140 | 0% |
  --Register as FF | 1114 / 139140 | <1% |
BSRAM | 0 / 340 | 0% |
Timing
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|
serdes_pcs_tx_clk_i | Base | 10.000 | 100.0 | 0.000 | 5.000 | serdes_pcs_tx_clk_i_ibuf/I | ||
serdes_pcs_rx_clk_i | Base | 10.000 | 100.0 | 0.000 | 5.000 | serdes_pcs_rx_clk_i_ibuf/I | ||
sdi_rx_drp_clk_i | Base | 10.000 | 100.0 | 0.000 | 5.000 | sdi_rx_drp_clk_i_ibuf/I |
Max Frequency Summary:
No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | serdes_pcs_tx_clk_i | 100.0(MHz) | 173.5(MHz) | 9 | TOP |
2 | serdes_pcs_rx_clk_i | 100.0(MHz) | 179.5(MHz) | 8 | TOP |
3 | sdi_rx_drp_clk_i | 100.0(MHz) | 187.5(MHz) | 8 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | 4.235 |
Data Arrival Time | 6.566 |
Data Required Time | 10.801 |
From | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_12_s0 |
To | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_0_s0 |
Launch Clk | serdes_pcs_tx_clk_i[R] |
Latch Clk | serdes_pcs_tx_clk_i[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | serdes_pcs_tx_clk_i | |||
0.000 | 0.000 | tCL | RR | 1 | serdes_pcs_tx_clk_i_ibuf/I |
0.683 | 0.683 | tINS | RR | 666 | serdes_pcs_tx_clk_i_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_12_s0/CLK |
1.230 | 0.367 | tC2Q | RR | 6 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_12_s0/Q |
1.410 | 0.180 | tNET | RR | 1 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1911_s25/I0 |
1.915 | 0.505 | tINS | RR | 10 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1911_s25/F |
2.095 | 0.180 | tNET | RR | 1 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1913_s11/I0 |
2.600 | 0.505 | tINS | RR | 3 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1913_s11/F |
2.780 | 0.180 | tNET | RR | 1 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1905_s46/I3 |
3.032 | 0.252 | tINS | RR | 23 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1905_s46/F |
3.212 | 0.180 | tNET | RR | 1 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1905_s18/I2 |
3.655 | 0.443 | tINS | RR | 3 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1905_s18/F |
3.835 | 0.180 | tNET | RR | 1 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1905_s49/I0 |
4.340 | 0.505 | tINS | RR | 3 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1905_s49/F |
4.520 | 0.180 | tNET | RR | 1 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1907_s13/I0 |
5.025 | 0.505 | tINS | RR | 1 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1907_s13/F |
5.205 | 0.180 | tNET | RR | 1 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1907_s4/I1 |
5.701 | 0.496 | tINS | RR | 5 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1907_s4/F |
5.881 | 0.180 | tNET | RR | 1 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1924_s0/I0 |
6.386 | 0.505 | tINS | RR | 1 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1924_s0/F |
6.566 | 0.180 | tNET | RR | 1 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_0_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | serdes_pcs_tx_clk_i | |||
10.000 | 0.000 | tCL | RR | 1 | serdes_pcs_tx_clk_i_ibuf/I |
10.682 | 0.683 | tINS | RR | 666 | serdes_pcs_tx_clk_i_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_0_s0/CLK |
10.801 | -0.061 | tSu | 1 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_0_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 9 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 3.716, 65.159%; route: 1.620, 28.403%; tC2Q: 0.367, 6.438% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 2
Path Summary:Slack | 4.235 |
Data Arrival Time | 6.566 |
Data Required Time | 10.801 |
From | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_12_s0 |
To | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_1_s0 |
Launch Clk | serdes_pcs_tx_clk_i[R] |
Latch Clk | serdes_pcs_tx_clk_i[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | serdes_pcs_tx_clk_i | |||
0.000 | 0.000 | tCL | RR | 1 | serdes_pcs_tx_clk_i_ibuf/I |
0.683 | 0.683 | tINS | RR | 666 | serdes_pcs_tx_clk_i_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_12_s0/CLK |
1.230 | 0.367 | tC2Q | RR | 6 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_12_s0/Q |
1.410 | 0.180 | tNET | RR | 1 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1911_s25/I0 |
1.915 | 0.505 | tINS | RR | 10 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1911_s25/F |
2.095 | 0.180 | tNET | RR | 1 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1913_s11/I0 |
2.600 | 0.505 | tINS | RR | 3 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1913_s11/F |
2.780 | 0.180 | tNET | RR | 1 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1905_s46/I3 |
3.032 | 0.252 | tINS | RR | 23 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1905_s46/F |
3.212 | 0.180 | tNET | RR | 1 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1905_s18/I2 |
3.655 | 0.443 | tINS | RR | 3 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1905_s18/F |
3.835 | 0.180 | tNET | RR | 1 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1905_s49/I0 |
4.340 | 0.505 | tINS | RR | 3 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1905_s49/F |
4.520 | 0.180 | tNET | RR | 1 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1907_s13/I0 |
5.025 | 0.505 | tINS | RR | 1 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1907_s13/F |
5.205 | 0.180 | tNET | RR | 1 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1907_s4/I1 |
5.701 | 0.496 | tINS | RR | 5 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1907_s4/F |
5.881 | 0.180 | tNET | RR | 1 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1923_s0/I0 |
6.386 | 0.505 | tINS | RR | 1 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1923_s0/F |
6.566 | 0.180 | tNET | RR | 1 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_1_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | serdes_pcs_tx_clk_i | |||
10.000 | 0.000 | tCL | RR | 1 | serdes_pcs_tx_clk_i_ibuf/I |
10.682 | 0.683 | tINS | RR | 666 | serdes_pcs_tx_clk_i_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_1_s0/CLK |
10.801 | -0.061 | tSu | 1 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_1_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 9 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 3.716, 65.159%; route: 1.620, 28.403%; tC2Q: 0.367, 6.438% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 3
Path Summary:Slack | 4.235 |
Data Arrival Time | 6.566 |
Data Required Time | 10.801 |
From | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_12_s0 |
To | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_10_s0 |
Launch Clk | serdes_pcs_tx_clk_i[R] |
Latch Clk | serdes_pcs_tx_clk_i[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | serdes_pcs_tx_clk_i | |||
0.000 | 0.000 | tCL | RR | 1 | serdes_pcs_tx_clk_i_ibuf/I |
0.683 | 0.683 | tINS | RR | 666 | serdes_pcs_tx_clk_i_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_12_s0/CLK |
1.230 | 0.367 | tC2Q | RR | 6 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_12_s0/Q |
1.410 | 0.180 | tNET | RR | 1 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1911_s25/I0 |
1.915 | 0.505 | tINS | RR | 10 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1911_s25/F |
2.095 | 0.180 | tNET | RR | 1 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1913_s11/I0 |
2.600 | 0.505 | tINS | RR | 3 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1913_s11/F |
2.780 | 0.180 | tNET | RR | 1 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1905_s46/I3 |
3.032 | 0.252 | tINS | RR | 23 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1905_s46/F |
3.212 | 0.180 | tNET | RR | 1 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1905_s18/I2 |
3.655 | 0.443 | tINS | RR | 3 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1905_s18/F |
3.835 | 0.180 | tNET | RR | 1 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1905_s49/I0 |
4.340 | 0.505 | tINS | RR | 3 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1905_s49/F |
4.520 | 0.180 | tNET | RR | 1 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1907_s13/I0 |
5.025 | 0.505 | tINS | RR | 1 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1907_s13/F |
5.205 | 0.180 | tNET | RR | 1 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1907_s4/I1 |
5.701 | 0.496 | tINS | RR | 5 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1907_s4/F |
5.881 | 0.180 | tNET | RR | 1 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1914_s0/I0 |
6.386 | 0.505 | tINS | RR | 1 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1914_s0/F |
6.566 | 0.180 | tNET | RR | 1 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_10_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | serdes_pcs_tx_clk_i | |||
10.000 | 0.000 | tCL | RR | 1 | serdes_pcs_tx_clk_i_ibuf/I |
10.682 | 0.683 | tINS | RR | 666 | serdes_pcs_tx_clk_i_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_10_s0/CLK |
10.801 | -0.061 | tSu | 1 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_10_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 9 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 3.716, 65.159%; route: 1.620, 28.403%; tC2Q: 0.367, 6.438% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 4
Path Summary:Slack | 4.235 |
Data Arrival Time | 6.566 |
Data Required Time | 10.801 |
From | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_12_s0 |
To | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_11_s0 |
Launch Clk | serdes_pcs_tx_clk_i[R] |
Latch Clk | serdes_pcs_tx_clk_i[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | serdes_pcs_tx_clk_i | |||
0.000 | 0.000 | tCL | RR | 1 | serdes_pcs_tx_clk_i_ibuf/I |
0.683 | 0.683 | tINS | RR | 666 | serdes_pcs_tx_clk_i_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_12_s0/CLK |
1.230 | 0.367 | tC2Q | RR | 6 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_12_s0/Q |
1.410 | 0.180 | tNET | RR | 1 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1911_s25/I0 |
1.915 | 0.505 | tINS | RR | 10 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1911_s25/F |
2.095 | 0.180 | tNET | RR | 1 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1913_s11/I0 |
2.600 | 0.505 | tINS | RR | 3 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1913_s11/F |
2.780 | 0.180 | tNET | RR | 1 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1905_s46/I3 |
3.032 | 0.252 | tINS | RR | 23 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1905_s46/F |
3.212 | 0.180 | tNET | RR | 1 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1905_s18/I2 |
3.655 | 0.443 | tINS | RR | 3 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1905_s18/F |
3.835 | 0.180 | tNET | RR | 1 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1905_s49/I0 |
4.340 | 0.505 | tINS | RR | 3 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1905_s49/F |
4.520 | 0.180 | tNET | RR | 1 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1907_s13/I0 |
5.025 | 0.505 | tINS | RR | 1 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1907_s13/F |
5.205 | 0.180 | tNET | RR | 1 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1907_s4/I1 |
5.701 | 0.496 | tINS | RR | 5 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1907_s4/F |
5.881 | 0.180 | tNET | RR | 1 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1913_s0/I0 |
6.386 | 0.505 | tINS | RR | 1 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1913_s0/F |
6.566 | 0.180 | tNET | RR | 1 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_11_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | serdes_pcs_tx_clk_i | |||
10.000 | 0.000 | tCL | RR | 1 | serdes_pcs_tx_clk_i_ibuf/I |
10.682 | 0.683 | tINS | RR | 666 | serdes_pcs_tx_clk_i_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_11_s0/CLK |
10.801 | -0.061 | tSu | 1 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_11_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 9 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 3.716, 65.159%; route: 1.620, 28.403%; tC2Q: 0.367, 6.438% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 5
Path Summary:Slack | 4.235 |
Data Arrival Time | 6.566 |
Data Required Time | 10.801 |
From | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_12_s0 |
To | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_7_s0 |
Launch Clk | serdes_pcs_tx_clk_i[R] |
Latch Clk | serdes_pcs_tx_clk_i[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | serdes_pcs_tx_clk_i | |||
0.000 | 0.000 | tCL | RR | 1 | serdes_pcs_tx_clk_i_ibuf/I |
0.683 | 0.683 | tINS | RR | 666 | serdes_pcs_tx_clk_i_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_12_s0/CLK |
1.230 | 0.367 | tC2Q | RR | 6 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_cnt_gen_inst/dot_cnt_12_s0/Q |
1.410 | 0.180 | tNET | RR | 1 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1911_s25/I0 |
1.915 | 0.505 | tINS | RR | 10 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1911_s25/F |
2.095 | 0.180 | tNET | RR | 1 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1913_s11/I0 |
2.600 | 0.505 | tINS | RR | 3 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1913_s11/F |
2.780 | 0.180 | tNET | RR | 1 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1905_s46/I3 |
3.032 | 0.252 | tINS | RR | 23 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1905_s46/F |
3.212 | 0.180 | tNET | RR | 1 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1905_s35/I1 |
3.708 | 0.496 | tINS | RR | 2 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1905_s35/F |
3.888 | 0.180 | tNET | RR | 1 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1905_s19/I2 |
4.331 | 0.443 | tINS | RR | 8 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1905_s19/F |
4.510 | 0.180 | tNET | RR | 1 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s59/I0 |
5.016 | 0.505 | tINS | RR | 2 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1906_s59/F |
5.196 | 0.180 | tNET | RR | 1 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1917_s1/I0 |
5.701 | 0.505 | tINS | RR | 1 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1917_s1/F |
5.881 | 0.180 | tNET | RR | 1 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1917_s0/I0 |
6.386 | 0.505 | tINS | RR | 1 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/n1917_s0/F |
6.566 | 0.180 | tNET | RR | 1 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_7_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | serdes_pcs_tx_clk_i | |||
10.000 | 0.000 | tCL | RR | 1 | serdes_pcs_tx_clk_i_ibuf/I |
10.682 | 0.683 | tINS | RR | 666 | serdes_pcs_tx_clk_i_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_7_s0/CLK |
10.801 | -0.061 | tSu | 1 | sdi_wrapper_inst/tx_sdi_top_inst/tx_hd_esl_insert_inst/data_ins_7_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 9 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 3.716, 65.159%; route: 1.620, 28.403%; tC2Q: 0.367, 6.438% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |