Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Gowin\Gowin_V1.9.9_x64\IDE\ipcore\DDR3\data\ddr3_1_4code_hs\ddr3_1_4code_hs.v
C:\Gowin\Gowin_V1.9.9_x64\IDE\ipcore\DDR3\data\ddr3_1_4code_hs\DDR3_TOP.v
GowinSynthesis Constraints File ---
Tool Version V1.9.9 (64-bit)
Part Number GW5AST-LV138FPG676AES
Device GW5AST-138
Device Version B
Created Time Thu Dec 21 16:08:35 2023
Legal Announcement Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module DDR3_Memory_Interface_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 125.941MB
Running netlist conversion:
    CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.149s, Peak memory usage = 125.941MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.578s, Elapsed time = 0h 0m 0.585s, Peak memory usage = 125.941MB
    Optimizing Phase 1: CPU time = 0h 0m 0.328s, Elapsed time = 0h 0m 0.317s, Peak memory usage = 125.941MB
    Optimizing Phase 2: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 125.941MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 125.941MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 125.941MB
    Inferring Phase 2: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.121s, Peak memory usage = 125.941MB
    Inferring Phase 3: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.03s, Peak memory usage = 125.941MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.765s, Elapsed time = 0h 0m 0.769s, Peak memory usage = 125.941MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.201s, Peak memory usage = 125.941MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.161s, Peak memory usage = 125.941MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 131.090MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.656s, Elapsed time = 0h 0m 0.652s, Peak memory usage = 131.090MB
Generate output files:
    CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 141.793MB
Total Time and Memory Usage CPU time = 0h 0m 9s, Elapsed time = 0h 0m 9s, Peak memory usage = 141.793MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 665
I/O Buf 657
    IBUF 326
    OBUF 290
    TBUF 4
    IOBUF 32
    ELVDS_OBUF 1
    ELVDS_IOBUF 4
Register 5567
    DFFSE 1
    DFFRE 445
    DFFPE 70
    DFFCE 5051
LUT 3333
    LUT2 650
    LUT3 1510
    LUT4 1173
ALU 206
    ALU 206
INV 28
    INV 28
IOLOGIC 128
    IDES8_MEM 32
    OSER8 24
    OSER8_MEM 40
    IODELAY 32
BSRAM 24
    SDPB 8
    SDPX9B 16
CLOCK 6
    CLKDIV 1
    DQS 4
    DDRDLL 1

Resource Utilization Summary

Resource Usage Utilization
Logic 3567(3361 LUT, 206 ALU) / 138240 3%
Register 5567 / 139140 5%
  --Register as Latch 0 / 139140 0%
  --Register as FF 5567 / 139140 5%
BSRAM 24 / 340 8%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
memory_clk Base 10.000 100.0 0.000 5.000 memory_clk_ibuf/I
clk Base 10.000 100.0 0.000 5.000 clk_ibuf/I
gw3_top/u_ddr_phy_top/u_ddr_init/n2447_6 Base 10.000 100.0 0.000 5.000 gw3_top/u_ddr_phy_top/u_ddr_init/n2447_s2/O
gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk Generated 40.000 25.0 0.000 20.000 memory_clk_ibuf/I memory_clk gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 memory_clk 100.0(MHz) 1448.7(MHz) 1 TOP
2 clk 100.0(MHz) 238.6(MHz) 7 TOP
3 gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk 25.0(MHz) 152.6(MHz) 8 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 3.613
Data Arrival Time 1.748
Data Required Time 5.361
From gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_3_s0
To gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Launch Clk gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[F]
Latch Clk memory_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.168 0.168 tCL RR 5674 gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.374 0.206 tNET RR 1 gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_3_s0/CLK
0.757 0.382 tC2Q RR 9 gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_3_s0/Q
0.963 0.206 tNET RR 1 gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_3_s/I0
1.542 0.579 tINS RR 1 gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_3_s/F
1.748 0.206 tNET RR 1 gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
5.000 0.000 memory_clk
5.000 0.000 tCL FF 1 memory_clk_ibuf/I
5.688 0.688 tINS FF 102 memory_clk_ibuf/O
5.880 0.192 tNET FF 1 gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
5.845 -0.035 tUnc gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
5.361 -0.484 tSu 1 gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Path Statistics:
Clock Skew: 0.506
Setup Relationship: 5.000
Logic Level: 2
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.206, 100.000%
Arrival Data Path Delay: cell: 0.579, 42.130%; route: 0.413, 30.027%; tC2Q: 0.382, 27.843%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.206, 100.000%

Path 2

Path Summary:
Slack 3.613
Data Arrival Time 1.748
Data Required Time 5.361
From gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_2_s0
To gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Launch Clk gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[F]
Latch Clk memory_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.168 0.168 tCL RR 5674 gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.374 0.206 tNET RR 1 gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_2_s0/CLK
0.757 0.382 tC2Q RR 9 gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_2_s0/Q
0.963 0.206 tNET RR 1 gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_2_s/I0
1.542 0.579 tINS RR 1 gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_2_s/F
1.748 0.206 tNET RR 1 gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
5.000 0.000 memory_clk
5.000 0.000 tCL FF 1 memory_clk_ibuf/I
5.688 0.688 tINS FF 102 memory_clk_ibuf/O
5.880 0.192 tNET FF 1 gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
5.845 -0.035 tUnc gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
5.361 -0.484 tSu 1 gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Path Statistics:
Clock Skew: 0.506
Setup Relationship: 5.000
Logic Level: 2
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.206, 100.000%
Arrival Data Path Delay: cell: 0.579, 42.130%; route: 0.413, 30.027%; tC2Q: 0.382, 27.843%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.206, 100.000%

Path 3

Path Summary:
Slack 3.613
Data Arrival Time 1.748
Data Required Time 5.361
From gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_1_s0
To gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Launch Clk gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[F]
Latch Clk memory_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.168 0.168 tCL RR 5674 gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.374 0.206 tNET RR 1 gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_1_s0/CLK
0.757 0.382 tC2Q RR 9 gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_1_s0/Q
0.963 0.206 tNET RR 1 gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_1_s/I0
1.542 0.579 tINS RR 1 gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_1_s/F
1.748 0.206 tNET RR 1 gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
5.000 0.000 memory_clk
5.000 0.000 tCL FF 1 memory_clk_ibuf/I
5.688 0.688 tINS FF 102 memory_clk_ibuf/O
5.880 0.192 tNET FF 1 gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
5.845 -0.035 tUnc gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
5.361 -0.484 tSu 1 gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Path Statistics:
Clock Skew: 0.506
Setup Relationship: 5.000
Logic Level: 2
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.206, 100.000%
Arrival Data Path Delay: cell: 0.579, 42.130%; route: 0.413, 30.027%; tC2Q: 0.382, 27.843%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.206, 100.000%

Path 4

Path Summary:
Slack 3.613
Data Arrival Time 1.748
Data Required Time 5.361
From gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_0_s0
To gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Launch Clk gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[F]
Latch Clk memory_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.168 0.168 tCL RR 5674 gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.374 0.206 tNET RR 1 gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_0_s0/CLK
0.757 0.382 tC2Q RR 9 gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_0_s0/Q
0.963 0.206 tNET RR 1 gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_0_s/I0
1.542 0.579 tINS RR 1 gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_0_s/F
1.748 0.206 tNET RR 1 gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
5.000 0.000 memory_clk
5.000 0.000 tCL FF 1 memory_clk_ibuf/I
5.688 0.688 tINS FF 102 memory_clk_ibuf/O
5.880 0.192 tNET FF 1 gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
5.845 -0.035 tUnc gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
5.361 -0.484 tSu 1 gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Path Statistics:
Clock Skew: 0.506
Setup Relationship: 5.000
Logic Level: 2
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.206, 100.000%
Arrival Data Path Delay: cell: 0.579, 42.130%; route: 0.413, 30.027%; tC2Q: 0.382, 27.843%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.206, 100.000%

Path 5

Path Summary:
Slack 5.317
Data Arrival Time 34.959
Data Required Time 40.275
From gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0
To gw3_top/u_ddr_phy_top/u_ddr_init/init_state.READ_CALIBRATION_s0
Launch Clk clk[R]
Latch Clk gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
30.000 0.000 clk
30.000 0.000 tCL RR 1 clk_ibuf/I
30.683 0.683 tINS RR 39 clk_ibuf/O
30.889 0.206 tNET RR 1 gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0/CLK
31.271 0.382 tC2Q RR 2 gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0/Q
31.477 0.206 tNET RR 1 gw3_top/u_ddr_phy_top/u_ddr_init/timer_cnt0_7_s9/I3
31.766 0.289 tINS RR 1 gw3_top/u_ddr_phy_top/u_ddr_init/timer_cnt0_7_s9/F
31.972 0.206 tNET RR 1 gw3_top/u_ddr_phy_top/u_ddr_init/timer_cnt0_7_s7/I2
32.480 0.507 tINS RR 2 gw3_top/u_ddr_phy_top/u_ddr_init/timer_cnt0_7_s7/F
32.686 0.206 tNET RR 1 gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.LOAD_MR_s21/I2
33.194 0.507 tINS RR 5 gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.LOAD_MR_s21/F
33.400 0.206 tNET RR 1 gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.WRLVL_LOAD_MR1_s20/I1
33.968 0.567 tINS RR 15 gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.WRLVL_LOAD_MR1_s20/F
34.174 0.206 tNET RR 1 gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.READ_CALIBRATION_s19/I0
34.753 0.579 tINS RR 1 gw3_top/u_ddr_phy_top/u_ddr_init/init_next_state.READ_CALIBRATION_s19/F
34.959 0.206 tNET RR 1 gw3_top/u_ddr_phy_top/u_ddr_init/init_state.READ_CALIBRATION_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
40.000 0.000 gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
40.168 0.168 tCL RR 5674 gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
40.374 0.206 tNET RR 1 gw3_top/u_ddr_phy_top/u_ddr_init/init_state.READ_CALIBRATION_s0/CLK
40.339 -0.035 tUnc gw3_top/u_ddr_phy_top/u_ddr_init/init_state.READ_CALIBRATION_s0
40.275 -0.064 tSu 1 gw3_top/u_ddr_phy_top/u_ddr_init/init_state.READ_CALIBRATION_s0
Path Statistics:
Clock Skew: -0.515
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.683, 76.793%; route: 0.206, 23.207%
Arrival Data Path Delay: cell: 2.450, 60.197%; route: 1.237, 30.405%; tC2Q: 0.382, 9.398%
Required Clock Path Delay: cell: 0.683, 76.793%; route: 0.206, 23.207%