Top Level Module |
Video_Frame_Buffer_Top |
Synthesis Process |
Running parser: CPU time = 0h 0m 0.265s, Elapsed time = 0h 0m 0.255s, Peak memory usage = 56.344MB Running netlist conversion: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.033s, Peak memory usage = 56.344MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.043s, Peak memory usage = 56.344MB Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.021s, Peak memory usage = 56.344MB Optimizing Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.054s, Peak memory usage = 56.344MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.021s, Peak memory usage = 56.344MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 56.344MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 56.344MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 56.344MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.042s, Peak memory usage = 56.344MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 56.344MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 56.344MB Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 80.805MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.098s, Peak memory usage = 80.805MB Generate output files: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.092s, Peak memory usage = 80.805MB
|
Total Time and Memory Usage |
CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 80.805MB |
AT |
DELAY |
TYPE |
RF |
FANOUT |
NODE |
0.000 |
0.000 |
|
|
|
I_dma_clk |
0.000 |
0.000 |
tCL |
RR |
1 |
I_dma_clk_ibuf/I |
0.683 |
0.683 |
tINS |
RR |
231 |
I_dma_clk_ibuf/O |
0.889 |
0.206 |
tNET |
RR |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_cnt_6_s1/CLK |
1.271 |
0.382 |
tC2Q |
RR |
4 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_cnt_6_s1/Q |
1.477 |
0.206 |
tNET |
RR |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma0_wr_data_end_s/I0 |
2.056 |
0.579 |
tINS |
RR |
25 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma0_wr_data_end_s/F |
2.263 |
0.206 |
tNET |
RR |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_3_s4/I2 |
2.770 |
0.507 |
tINS |
RR |
9 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_3_s4/F |
2.976 |
0.206 |
tNET |
RR |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_4_s4/I1 |
3.544 |
0.567 |
tINS |
RR |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_4_s4/F |
3.750 |
0.206 |
tNET |
RR |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_6_s5/I0 |
4.329 |
0.579 |
tINS |
RR |
5 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_6_s5/F |
4.535 |
0.206 |
tNET |
RR |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rgraynext_5_s0/I0 |
5.114 |
0.579 |
tINS |
RR |
2 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rgraynext_5_s0/F |
5.320 |
0.206 |
tNET |
RR |
2 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n1210_s0/I0 |
5.915 |
0.595 |
tINS |
RF |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n1210_s0/COUT |
5.915 |
0.000 |
tNET |
FF |
2 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n1211_s0/CIN |
5.965 |
0.050 |
tINS |
FR |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n1211_s0/COUT |
5.965 |
0.000 |
tNET |
RR |
2 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n1212_s0/CIN |
6.015 |
0.050 |
tINS |
RR |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n1212_s0/COUT |
6.221 |
0.206 |
tNET |
RR |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rempty_val_s1/I2 |
6.729 |
0.507 |
tINS |
RR |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rempty_val_s1/F |
6.935 |
0.206 |
tNET |
RR |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Empty_s0/D |
AT |
DELAY |
TYPE |
RF |
FANOUT |
NODE |
0.000 |
0.000 |
|
|
|
I_vout0_clk |
0.000 |
0.000 |
tCL |
RR |
1 |
I_vout0_clk_ibuf/I |
0.683 |
0.683 |
tINS |
RR |
57 |
I_vout0_clk_ibuf/O |
0.889 |
0.206 |
tNET |
RR |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Empty_s0/CLK |
1.271 |
0.382 |
tC2Q |
RR |
6 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Empty_s0/Q |
1.477 |
0.206 |
tNET |
RR |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n68_s0/I0 |
2.056 |
0.579 |
tINS |
RR |
11 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n68_s0/F |
2.263 |
0.206 |
tNET |
RR |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rgraynext_2_s1/I2 |
2.770 |
0.507 |
tINS |
RR |
8 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rgraynext_2_s1/F |
2.976 |
0.206 |
tNET |
RR |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rgraynext_4_s1/I2 |
3.484 |
0.507 |
tINS |
RR |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rgraynext_4_s1/F |
3.690 |
0.206 |
tNET |
RR |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rgraynext_4_s0/I1 |
4.257 |
0.567 |
tINS |
RR |
2 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rgraynext_4_s0/F |
4.464 |
0.206 |
tNET |
RR |
2 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n1023_s0/I0 |
5.059 |
0.595 |
tINS |
RF |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n1023_s0/COUT |
5.059 |
0.000 |
tNET |
FF |
2 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n1024_s0/CIN |
5.109 |
0.050 |
tINS |
FR |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n1024_s0/COUT |
5.109 |
0.000 |
tNET |
RR |
2 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n1025_s0/CIN |
5.159 |
0.050 |
tINS |
RR |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n1025_s0/COUT |
5.365 |
0.206 |
tNET |
RR |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rempty_val_s1/I2 |
5.873 |
0.507 |
tINS |
RR |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rempty_val_s1/F |
6.079 |
0.206 |
tNET |
RR |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Empty_s0/D |
AT |
DELAY |
TYPE |
RF |
FANOUT |
NODE |
0.000 |
0.000 |
|
|
|
I_dma_clk |
0.000 |
0.000 |
tCL |
RR |
1 |
I_dma_clk_ibuf/I |
0.683 |
0.683 |
tINS |
RR |
231 |
I_dma_clk_ibuf/O |
0.889 |
0.206 |
tNET |
RR |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq2_wptr_6_s1/CLK |
1.271 |
0.382 |
tC2Q |
RR |
3 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq2_wptr_6_s1/Q |
1.477 |
0.206 |
tNET |
RR |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_5_s1/I0 |
2.056 |
0.579 |
tINS |
RR |
4 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_5_s1/F |
2.263 |
0.206 |
tNET |
RR |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_4_s0/I1 |
2.830 |
0.567 |
tINS |
RR |
2 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_4_s0/F |
3.036 |
0.206 |
tNET |
RR |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_1_s0/I3 |
3.325 |
0.289 |
tINS |
RR |
2 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_1_s0/F |
3.531 |
0.206 |
tNET |
RR |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_0_s0/I1 |
4.099 |
0.567 |
tINS |
RR |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_0_s0/F |
4.305 |
0.206 |
tNET |
RR |
2 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_0_s/I0 |
4.900 |
0.595 |
tINS |
RF |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_0_s/COUT |
4.900 |
0.000 |
tNET |
FF |
2 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_1_s/CIN |
4.950 |
0.050 |
tINS |
FR |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_1_s/COUT |
4.950 |
0.000 |
tNET |
RR |
2 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_2_s/CIN |
5.000 |
0.050 |
tINS |
RR |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_2_s/COUT |
5.000 |
0.000 |
tNET |
RR |
2 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_3_s/CIN |
5.050 |
0.050 |
tINS |
RR |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_3_s/COUT |
5.050 |
0.000 |
tNET |
RR |
2 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_4_s/CIN |
5.100 |
0.050 |
tINS |
RR |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_4_s/COUT |
5.100 |
0.000 |
tNET |
RR |
2 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_5_s/CIN |
5.150 |
0.050 |
tINS |
RR |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_5_s/COUT |
5.150 |
0.000 |
tNET |
RR |
2 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_6_s/CIN |
5.200 |
0.050 |
tINS |
RR |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_6_s/COUT |
5.200 |
0.000 |
tNET |
RR |
2 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_7_s/CIN |
5.250 |
0.050 |
tINS |
RR |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_7_s/COUT |
5.250 |
0.000 |
tNET |
RR |
2 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_8_s/CIN |
5.494 |
0.244 |
tINS |
RR |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_8_s/SUM |
5.700 |
0.206 |
tNET |
RR |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_8_s0/D |
AT |
DELAY |
TYPE |
RF |
FANOUT |
NODE |
0.000 |
0.000 |
|
|
|
I_dma_clk |
0.000 |
0.000 |
tCL |
RR |
1 |
I_dma_clk_ibuf/I |
0.683 |
0.683 |
tINS |
RR |
231 |
I_dma_clk_ibuf/O |
0.889 |
0.206 |
tNET |
RR |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq2_wptr_6_s1/CLK |
1.271 |
0.382 |
tC2Q |
RR |
3 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq2_wptr_6_s1/Q |
1.477 |
0.206 |
tNET |
RR |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_5_s1/I0 |
2.056 |
0.579 |
tINS |
RR |
4 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_5_s1/F |
2.263 |
0.206 |
tNET |
RR |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_4_s0/I1 |
2.830 |
0.567 |
tINS |
RR |
2 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_4_s0/F |
3.036 |
0.206 |
tNET |
RR |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_1_s0/I3 |
3.325 |
0.289 |
tINS |
RR |
2 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_1_s0/F |
3.531 |
0.206 |
tNET |
RR |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_0_s0/I1 |
4.099 |
0.567 |
tINS |
RR |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_0_s0/F |
4.305 |
0.206 |
tNET |
RR |
2 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_0_s/I0 |
4.900 |
0.595 |
tINS |
RF |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_0_s/COUT |
4.900 |
0.000 |
tNET |
FF |
2 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_1_s/CIN |
4.950 |
0.050 |
tINS |
FR |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_1_s/COUT |
4.950 |
0.000 |
tNET |
RR |
2 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_2_s/CIN |
5.000 |
0.050 |
tINS |
RR |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_2_s/COUT |
5.000 |
0.000 |
tNET |
RR |
2 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_3_s/CIN |
5.050 |
0.050 |
tINS |
RR |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_3_s/COUT |
5.050 |
0.000 |
tNET |
RR |
2 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_4_s/CIN |
5.100 |
0.050 |
tINS |
RR |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_4_s/COUT |
5.100 |
0.000 |
tNET |
RR |
2 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_5_s/CIN |
5.150 |
0.050 |
tINS |
RR |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_5_s/COUT |
5.150 |
0.000 |
tNET |
RR |
2 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_6_s/CIN |
5.200 |
0.050 |
tINS |
RR |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_6_s/COUT |
5.200 |
0.000 |
tNET |
RR |
2 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_7_s/CIN |
5.444 |
0.244 |
tINS |
RR |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_7_s/SUM |
5.650 |
0.206 |
tNET |
RR |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_7_s0/D |
AT |
DELAY |
TYPE |
RF |
FANOUT |
NODE |
0.000 |
0.000 |
|
|
|
I_dma_clk |
0.000 |
0.000 |
tCL |
RR |
1 |
I_dma_clk_ibuf/I |
0.683 |
0.683 |
tINS |
RR |
231 |
I_dma_clk_ibuf/O |
0.889 |
0.206 |
tNET |
RR |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq2_wptr_6_s1/CLK |
1.271 |
0.382 |
tC2Q |
RR |
3 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq2_wptr_6_s1/Q |
1.477 |
0.206 |
tNET |
RR |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_5_s1/I0 |
2.056 |
0.579 |
tINS |
RR |
4 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_5_s1/F |
2.263 |
0.206 |
tNET |
RR |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_4_s0/I1 |
2.830 |
0.567 |
tINS |
RR |
2 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_4_s0/F |
3.036 |
0.206 |
tNET |
RR |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_1_s0/I3 |
3.325 |
0.289 |
tINS |
RR |
2 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_1_s0/F |
3.531 |
0.206 |
tNET |
RR |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_0_s0/I1 |
4.099 |
0.567 |
tINS |
RR |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_0_s0/F |
4.305 |
0.206 |
tNET |
RR |
2 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_0_s/I0 |
4.900 |
0.595 |
tINS |
RF |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_0_s/COUT |
4.900 |
0.000 |
tNET |
FF |
2 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_1_s/CIN |
4.950 |
0.050 |
tINS |
FR |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_1_s/COUT |
4.950 |
0.000 |
tNET |
RR |
2 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_2_s/CIN |
5.000 |
0.050 |
tINS |
RR |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_2_s/COUT |
5.000 |
0.000 |
tNET |
RR |
2 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_3_s/CIN |
5.050 |
0.050 |
tINS |
RR |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_3_s/COUT |
5.050 |
0.000 |
tNET |
RR |
2 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_4_s/CIN |
5.100 |
0.050 |
tINS |
RR |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_4_s/COUT |
5.100 |
0.000 |
tNET |
RR |
2 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_5_s/CIN |
5.150 |
0.050 |
tINS |
RR |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_5_s/COUT |
5.150 |
0.000 |
tNET |
RR |
2 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_6_s/CIN |
5.394 |
0.244 |
tINS |
RR |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_6_s/SUM |
5.600 |
0.206 |
tNET |
RR |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_6_s0/D |