Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Gowin\Gowin_V1.9.9_x64\IDE\ipcore\VFB\data\vfb_top.v
C:\Gowin\Gowin_V1.9.9_x64\IDE\ipcore\VFB\data\vfb_wrapper.v
GowinSynthesis Constraints File ---
Tool Version V1.9.9 (64-bit)
Part Number GW5AST-LV138FPG676AES
Device GW5AST-138
Device Version B
Created Time Thu Nov 30 09:53:10 2023
Legal Announcement Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module Video_Frame_Buffer_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.265s, Elapsed time = 0h 0m 0.255s, Peak memory usage = 56.344MB
Running netlist conversion:
    CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.033s, Peak memory usage = 56.344MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.043s, Peak memory usage = 56.344MB
    Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.021s, Peak memory usage = 56.344MB
    Optimizing Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.054s, Peak memory usage = 56.344MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.021s, Peak memory usage = 56.344MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 56.344MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 56.344MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 56.344MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.042s, Peak memory usage = 56.344MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 56.344MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 56.344MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 80.805MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.098s, Peak memory usage = 80.805MB
Generate output files:
    CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.092s, Peak memory usage = 80.805MB
Total Time and Memory Usage CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 80.805MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 644
I/O Buf 643
    IBUF 302
    OBUF 341
Register 344
    DFFSE 8
    DFFRE 2
    DFFPE 32
    DFFCE 302
LUT 1072
    LUT2 348
    LUT3 341
    LUT4 383
ALU 32
    ALU 32
INV 5
    INV 5
BSRAM 16
    SDPB 16

Resource Utilization Summary

Resource Usage Utilization
Logic 1109(1077 LUT, 32 ALU) / 138240 <1%
Register 344 / 139140 <1%
  --Register as Latch 0 / 139140 0%
  --Register as FF 344 / 139140 <1%
BSRAM 16 / 340 5%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
I_vin0_clk Base 10.000 100.0 0.000 5.000 I_vin0_clk_ibuf/I
I_dma_clk Base 10.000 100.0 0.000 5.000 I_dma_clk_ibuf/I
I_vout0_clk Base 10.000 100.0 0.000 5.000 I_vout0_clk_ibuf/I
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n29_6 Base 10.000 100.0 0.000 5.000 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n29_s2/O
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n34_6 Base 10.000 100.0 0.000 5.000 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n34_s2/O
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n38_6 Base 10.000 100.0 0.000 5.000 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n38_s2/O

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 I_vin0_clk 100.0(MHz) 222.5(MHz) 6 TOP
2 I_dma_clk 100.0(MHz) 163.7(MHz) 9 TOP
3 I_vout0_clk 100.0(MHz) 190.3(MHz) 8 TOP
4 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n29_6 100.0(MHz) 1532.6(MHz) 1 TOP
5 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n34_6 100.0(MHz) 1532.6(MHz) 1 TOP
6 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n38_6 100.0(MHz) 1532.6(MHz) 1 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 3.890
Data Arrival Time 6.935
Data Required Time 10.825
From vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_cnt_6_s1
To vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Empty_s0
Launch Clk I_dma_clk[R]
Latch Clk I_dma_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_dma_clk
0.000 0.000 tCL RR 1 I_dma_clk_ibuf/I
0.683 0.683 tINS RR 231 I_dma_clk_ibuf/O
0.889 0.206 tNET RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_cnt_6_s1/CLK
1.271 0.382 tC2Q RR 4 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_cnt_6_s1/Q
1.477 0.206 tNET RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma0_wr_data_end_s/I0
2.056 0.579 tINS RR 25 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma0_wr_data_end_s/F
2.263 0.206 tNET RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_3_s4/I2
2.770 0.507 tINS RR 9 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_3_s4/F
2.976 0.206 tNET RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_4_s4/I1
3.544 0.567 tINS RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_4_s4/F
3.750 0.206 tNET RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_6_s5/I0
4.329 0.579 tINS RR 5 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_6_s5/F
4.535 0.206 tNET RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rgraynext_5_s0/I0
5.114 0.579 tINS RR 2 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rgraynext_5_s0/F
5.320 0.206 tNET RR 2 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n1210_s0/I0
5.915 0.595 tINS RF 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n1210_s0/COUT
5.915 0.000 tNET FF 2 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n1211_s0/CIN
5.965 0.050 tINS FR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n1211_s0/COUT
5.965 0.000 tNET RR 2 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n1212_s0/CIN
6.015 0.050 tINS RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n1212_s0/COUT
6.221 0.206 tNET RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rempty_val_s1/I2
6.729 0.507 tINS RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rempty_val_s1/F
6.935 0.206 tNET RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Empty_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_dma_clk
10.000 0.000 tCL RR 1 I_dma_clk_ibuf/I
10.682 0.683 tINS RR 231 I_dma_clk_ibuf/O
10.889 0.206 tNET RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Empty_s0/CLK
10.825 -0.064 tSu 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Empty_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.683, 76.793%; route: 0.206, 23.207%
Arrival Data Path Delay: cell: 4.014, 66.384%; route: 1.650, 27.290%; tC2Q: 0.382, 6.326%
Required Clock Path Delay: cell: 0.683, 76.793%; route: 0.206, 23.207%

Path 2

Path Summary:
Slack 4.746
Data Arrival Time 6.079
Data Required Time 10.825
From vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Empty_s0
To vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Empty_s0
Launch Clk I_vout0_clk[R]
Latch Clk I_vout0_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_vout0_clk
0.000 0.000 tCL RR 1 I_vout0_clk_ibuf/I
0.683 0.683 tINS RR 57 I_vout0_clk_ibuf/O
0.889 0.206 tNET RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Empty_s0/CLK
1.271 0.382 tC2Q RR 6 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Empty_s0/Q
1.477 0.206 tNET RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n68_s0/I0
2.056 0.579 tINS RR 11 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n68_s0/F
2.263 0.206 tNET RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rgraynext_2_s1/I2
2.770 0.507 tINS RR 8 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rgraynext_2_s1/F
2.976 0.206 tNET RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rgraynext_4_s1/I2
3.484 0.507 tINS RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rgraynext_4_s1/F
3.690 0.206 tNET RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rgraynext_4_s0/I1
4.257 0.567 tINS RR 2 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rgraynext_4_s0/F
4.464 0.206 tNET RR 2 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n1023_s0/I0
5.059 0.595 tINS RF 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n1023_s0/COUT
5.059 0.000 tNET FF 2 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n1024_s0/CIN
5.109 0.050 tINS FR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n1024_s0/COUT
5.109 0.000 tNET RR 2 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n1025_s0/CIN
5.159 0.050 tINS RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n1025_s0/COUT
5.365 0.206 tNET RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rempty_val_s1/I2
5.873 0.507 tINS RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rempty_val_s1/F
6.079 0.206 tNET RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Empty_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_vout0_clk
10.000 0.000 tCL RR 1 I_vout0_clk_ibuf/I
10.682 0.683 tINS RR 57 I_vout0_clk_ibuf/O
10.889 0.206 tNET RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Empty_s0/CLK
10.825 -0.064 tSu 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Empty_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 8
Arrival Clock Path Delay: cell: 0.683, 76.793%; route: 0.206, 23.207%
Arrival Data Path Delay: cell: 3.364, 64.812%; route: 1.444, 27.818%; tC2Q: 0.382, 7.370%
Required Clock Path Delay: cell: 0.683, 76.793%; route: 0.206, 23.207%

Path 3

Path Summary:
Slack 5.125
Data Arrival Time 5.700
Data Required Time 10.825
From vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq2_wptr_6_s1
To vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_8_s0
Launch Clk I_dma_clk[R]
Latch Clk I_dma_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_dma_clk
0.000 0.000 tCL RR 1 I_dma_clk_ibuf/I
0.683 0.683 tINS RR 231 I_dma_clk_ibuf/O
0.889 0.206 tNET RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq2_wptr_6_s1/CLK
1.271 0.382 tC2Q RR 3 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq2_wptr_6_s1/Q
1.477 0.206 tNET RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_5_s1/I0
2.056 0.579 tINS RR 4 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_5_s1/F
2.263 0.206 tNET RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_4_s0/I1
2.830 0.567 tINS RR 2 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_4_s0/F
3.036 0.206 tNET RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_1_s0/I3
3.325 0.289 tINS RR 2 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_1_s0/F
3.531 0.206 tNET RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_0_s0/I1
4.099 0.567 tINS RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_0_s0/F
4.305 0.206 tNET RR 2 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_0_s/I0
4.900 0.595 tINS RF 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_0_s/COUT
4.900 0.000 tNET FF 2 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_1_s/CIN
4.950 0.050 tINS FR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_1_s/COUT
4.950 0.000 tNET RR 2 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_2_s/CIN
5.000 0.050 tINS RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_2_s/COUT
5.000 0.000 tNET RR 2 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_3_s/CIN
5.050 0.050 tINS RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_3_s/COUT
5.050 0.000 tNET RR 2 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_4_s/CIN
5.100 0.050 tINS RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_4_s/COUT
5.100 0.000 tNET RR 2 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_5_s/CIN
5.150 0.050 tINS RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_5_s/COUT
5.150 0.000 tNET RR 2 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_6_s/CIN
5.200 0.050 tINS RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_6_s/COUT
5.200 0.000 tNET RR 2 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_7_s/CIN
5.250 0.050 tINS RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_7_s/COUT
5.250 0.000 tNET RR 2 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_8_s/CIN
5.494 0.244 tINS RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_8_s/SUM
5.700 0.206 tNET RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_8_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_dma_clk
10.000 0.000 tCL RR 1 I_dma_clk_ibuf/I
10.682 0.683 tINS RR 231 I_dma_clk_ibuf/O
10.889 0.206 tNET RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_8_s0/CLK
10.825 -0.064 tSu 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_8_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 8
Arrival Clock Path Delay: cell: 0.683, 76.793%; route: 0.206, 23.207%
Arrival Data Path Delay: cell: 3.191, 66.329%; route: 1.237, 25.721%; tC2Q: 0.382, 7.950%
Required Clock Path Delay: cell: 0.683, 76.793%; route: 0.206, 23.207%

Path 4

Path Summary:
Slack 5.175
Data Arrival Time 5.650
Data Required Time 10.825
From vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq2_wptr_6_s1
To vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_7_s0
Launch Clk I_dma_clk[R]
Latch Clk I_dma_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_dma_clk
0.000 0.000 tCL RR 1 I_dma_clk_ibuf/I
0.683 0.683 tINS RR 231 I_dma_clk_ibuf/O
0.889 0.206 tNET RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq2_wptr_6_s1/CLK
1.271 0.382 tC2Q RR 3 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq2_wptr_6_s1/Q
1.477 0.206 tNET RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_5_s1/I0
2.056 0.579 tINS RR 4 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_5_s1/F
2.263 0.206 tNET RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_4_s0/I1
2.830 0.567 tINS RR 2 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_4_s0/F
3.036 0.206 tNET RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_1_s0/I3
3.325 0.289 tINS RR 2 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_1_s0/F
3.531 0.206 tNET RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_0_s0/I1
4.099 0.567 tINS RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_0_s0/F
4.305 0.206 tNET RR 2 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_0_s/I0
4.900 0.595 tINS RF 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_0_s/COUT
4.900 0.000 tNET FF 2 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_1_s/CIN
4.950 0.050 tINS FR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_1_s/COUT
4.950 0.000 tNET RR 2 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_2_s/CIN
5.000 0.050 tINS RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_2_s/COUT
5.000 0.000 tNET RR 2 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_3_s/CIN
5.050 0.050 tINS RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_3_s/COUT
5.050 0.000 tNET RR 2 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_4_s/CIN
5.100 0.050 tINS RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_4_s/COUT
5.100 0.000 tNET RR 2 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_5_s/CIN
5.150 0.050 tINS RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_5_s/COUT
5.150 0.000 tNET RR 2 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_6_s/CIN
5.200 0.050 tINS RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_6_s/COUT
5.200 0.000 tNET RR 2 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_7_s/CIN
5.444 0.244 tINS RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_7_s/SUM
5.650 0.206 tNET RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_7_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_dma_clk
10.000 0.000 tCL RR 1 I_dma_clk_ibuf/I
10.682 0.683 tINS RR 231 I_dma_clk_ibuf/O
10.889 0.206 tNET RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_7_s0/CLK
10.825 -0.064 tSu 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_7_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 8
Arrival Clock Path Delay: cell: 0.683, 76.793%; route: 0.206, 23.207%
Arrival Data Path Delay: cell: 3.141, 65.975%; route: 1.237, 25.991%; tC2Q: 0.382, 8.034%
Required Clock Path Delay: cell: 0.683, 76.793%; route: 0.206, 23.207%

Path 5

Path Summary:
Slack 5.225
Data Arrival Time 5.600
Data Required Time 10.825
From vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq2_wptr_6_s1
To vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_6_s0
Launch Clk I_dma_clk[R]
Latch Clk I_dma_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_dma_clk
0.000 0.000 tCL RR 1 I_dma_clk_ibuf/I
0.683 0.683 tINS RR 231 I_dma_clk_ibuf/O
0.889 0.206 tNET RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq2_wptr_6_s1/CLK
1.271 0.382 tC2Q RR 3 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq2_wptr_6_s1/Q
1.477 0.206 tNET RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_5_s1/I0
2.056 0.579 tINS RR 4 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_5_s1/F
2.263 0.206 tNET RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_4_s0/I1
2.830 0.567 tINS RR 2 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_4_s0/F
3.036 0.206 tNET RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_1_s0/I3
3.325 0.289 tINS RR 2 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_1_s0/F
3.531 0.206 tNET RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_0_s0/I1
4.099 0.567 tINS RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_0_s0/F
4.305 0.206 tNET RR 2 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_0_s/I0
4.900 0.595 tINS RF 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_0_s/COUT
4.900 0.000 tNET FF 2 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_1_s/CIN
4.950 0.050 tINS FR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_1_s/COUT
4.950 0.000 tNET RR 2 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_2_s/CIN
5.000 0.050 tINS RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_2_s/COUT
5.000 0.000 tNET RR 2 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_3_s/CIN
5.050 0.050 tINS RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_3_s/COUT
5.050 0.000 tNET RR 2 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_4_s/CIN
5.100 0.050 tINS RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_4_s/COUT
5.100 0.000 tNET RR 2 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_5_s/CIN
5.150 0.050 tINS RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_5_s/COUT
5.150 0.000 tNET RR 2 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_6_s/CIN
5.394 0.244 tINS RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_6_s/SUM
5.600 0.206 tNET RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_6_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_dma_clk
10.000 0.000 tCL RR 1 I_dma_clk_ibuf/I
10.682 0.683 tINS RR 231 I_dma_clk_ibuf/O
10.889 0.206 tNET RR 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_6_s0/CLK
10.825 -0.064 tSu 1 vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_6_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.683, 76.793%; route: 0.206, 23.207%
Arrival Data Path Delay: cell: 3.091, 65.614%; route: 1.237, 26.267%; tC2Q: 0.382, 8.119%
Required Clock Path Delay: cell: 0.683, 76.793%; route: 0.206, 23.207%