Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Gowin\Gowin_V1.9.9_x64\IDE\ipcore\SERDES_IP\IPlib\SLVSEC_RX\data\slvs_ec_rx_top.v
C:\Gowin\Gowin_V1.9.9_x64\IDE\ipcore\SERDES_IP\IPlib\SLVSEC_RX\data\fifo_sc.v
C:\Gowin\Gowin_V1.9.9_x64\IDE\ipcore\SERDES_IP\IPlib\SLVSEC_RX\data\slvs_ec_rx_wrapper.v
GowinSynthesis Constraints File ---
Tool Version V1.9.9 (64-bit)
Part Number GW5AST-LV138FPG676AES
Device GW5AST-138
Device Version B
Created Time Wed Dec 20 16:38:15 2023
Legal Announcement Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module SLVS_EC_RX_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 93.367MB
Running netlist conversion:
    CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.049s, Peak memory usage = 93.367MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.165s, Peak memory usage = 93.367MB
    Optimizing Phase 1: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.09s, Peak memory usage = 93.367MB
    Optimizing Phase 2: CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.161s, Peak memory usage = 93.367MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.054s, Peak memory usage = 93.367MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 93.367MB
    Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.02s, Peak memory usage = 93.367MB
    Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 93.367MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.117s, Peak memory usage = 93.367MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.049s, Peak memory usage = 93.367MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.088s, Peak memory usage = 93.367MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s, Peak memory usage = 105.625MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.18s, Peak memory usage = 105.625MB
Generate output files:
    CPU time = 0h 0m 0.25s, Elapsed time = 0h 0m 0.286s, Peak memory usage = 105.625MB
Total Time and Memory Usage CPU time = 0h 0m 6s, Elapsed time = 0h 0m 6s, Peak memory usage = 105.625MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 480
I/O Buf 391
    IBUF 105
    OBUF 286
Register 1452
    DFFRE 45
    DFFPE 1
    DFFCE 1390
    DLCE 16
LUT 4118
    LUT2 149
    LUT3 2207
    LUT4 1762
ALU 147
    ALU 147
INV 3
    INV 3
BSRAM 1
    SDPB 1

Resource Utilization Summary

Resource Usage Utilization
Logic 4268(4121 LUT, 147 ALU) / 138240 4%
Register 1452 / 139140 2%
  --Register as Latch 16 / 139140 <1%
  --Register as FF 1436 / 139140 2%
BSRAM 1 / 340 <1%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
i_clk Base 10.000 100.0 0.000 5.000 i_clk_ibuf/I
slvs_ec_rx_wrapper_inst/slvs_rx_phy/n122_9 Base 10.000 100.0 0.000 5.000 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n101_s6/F
slvs_ec_rx_wrapper_inst/slvs_rx_link/unpacket_inst/n107_11 Base 10.000 100.0 0.000 5.000 slvs_ec_rx_wrapper_inst/slvs_rx_link/unpacket_inst/n107_s6/F

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 i_clk 100.0(MHz) 146.4(MHz) 10 TOP
2 slvs_ec_rx_wrapper_inst/slvs_rx_link/unpacket_inst/n107_11 100.0(MHz) 587.4(MHz) 2 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack -1.447
Data Arrival Time 6.541
Data Required Time 5.094
From slvs_ec_rx_wrapper_inst/slvs_rx_phy/idle_code_0_s0
To slvs_ec_rx_wrapper_inst/slvs_rx_phy/next_state_6_s0
Launch Clk i_clk[F]
Latch Clk slvs_ec_rx_wrapper_inst/slvs_rx_phy/n122_9[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 i_clk
0.000 0.000 tCL RR 1 i_clk_ibuf/I
0.683 0.683 tINS RR 1438 i_clk_ibuf/O
0.889 0.206 tNET RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/idle_code_0_s0/CLK
1.271 0.382 tC2Q RR 2 slvs_ec_rx_wrapper_inst/slvs_rx_phy/idle_code_0_s0/Q
1.477 0.206 tNET RR 2 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1478_s0/I1
2.077 0.600 tINS RF 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1478_s0/COUT
2.077 0.000 tNET FF 2 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1479_s0/CIN
2.127 0.050 tINS FR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1479_s0/COUT
2.127 0.000 tNET RR 2 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1480_s0/CIN
2.177 0.050 tINS RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1480_s0/COUT
2.177 0.000 tNET RR 2 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1481_s0/CIN
2.227 0.050 tINS RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1481_s0/COUT
2.227 0.000 tNET RR 2 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1482_s0/CIN
2.277 0.050 tINS RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1482_s0/COUT
2.277 0.000 tNET RR 2 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1483_s0/CIN
2.327 0.050 tINS RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1483_s0/COUT
2.327 0.000 tNET RR 2 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1484_s0/CIN
2.377 0.050 tINS RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1484_s0/COUT
2.377 0.000 tNET RR 2 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1485_s0/CIN
2.427 0.050 tINS RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1485_s0/COUT
2.427 0.000 tNET RR 2 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1486_s0/CIN
2.477 0.050 tINS RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1486_s0/COUT
2.477 0.000 tNET RR 2 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1487_s0/CIN
2.527 0.050 tINS RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1487_s0/COUT
2.527 0.000 tNET RR 2 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1488_s0/CIN
2.577 0.050 tINS RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1488_s0/COUT
2.577 0.000 tNET RR 2 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1489_s0/CIN
2.627 0.050 tINS RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1489_s0/COUT
2.627 0.000 tNET RR 2 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1490_s0/CIN
2.677 0.050 tINS RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1490_s0/COUT
2.677 0.000 tNET RR 2 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1491_s0/CIN
2.727 0.050 tINS RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1491_s0/COUT
2.727 0.000 tNET RR 2 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1492_s0/CIN
2.777 0.050 tINS RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1492_s0/COUT
2.777 0.000 tNET RR 2 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1493_s0/CIN
2.827 0.050 tINS RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1493_s0/COUT
2.827 0.000 tNET RR 2 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1494_s0/CIN
2.877 0.050 tINS RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1494_s0/COUT
2.877 0.000 tNET RR 2 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1495_s0/CIN
2.927 0.050 tINS RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1495_s0/COUT
2.927 0.000 tNET RR 2 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1496_s0/CIN
2.977 0.050 tINS RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1496_s0/COUT
2.977 0.000 tNET RR 2 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1497_s0/CIN
3.027 0.050 tINS RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1497_s0/COUT
3.027 0.000 tNET RR 2 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1498_s0/CIN
3.077 0.050 tINS RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1498_s0/COUT
3.077 0.000 tNET RR 2 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1499_s0/CIN
3.127 0.050 tINS RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1499_s0/COUT
3.127 0.000 tNET RR 2 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1500_s0/CIN
3.177 0.050 tINS RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1500_s0/COUT
3.177 0.000 tNET RR 2 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1501_s0/CIN
3.227 0.050 tINS RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1501_s0/COUT
3.227 0.000 tNET RR 2 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1502_s0/CIN
3.277 0.050 tINS RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1502_s0/COUT
3.277 0.000 tNET RR 2 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1503_s0/CIN
3.327 0.050 tINS RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1503_s0/COUT
3.327 0.000 tNET RR 2 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1504_s0/CIN
3.377 0.050 tINS RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1504_s0/COUT
3.377 0.000 tNET RR 2 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1505_s0/CIN
3.427 0.050 tINS RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1505_s0/COUT
3.427 0.000 tNET RR 2 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1506_s0/CIN
3.477 0.050 tINS RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1506_s0/COUT
3.477 0.000 tNET RR 2 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1507_s0/CIN
3.527 0.050 tINS RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1507_s0/COUT
3.527 0.000 tNET RR 2 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1508_s0/CIN
3.577 0.050 tINS RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1508_s0/COUT
3.577 0.000 tNET RR 2 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1509_s0/CIN
3.627 0.050 tINS RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1509_s0/COUT
3.834 0.206 tNET RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n100_s19/I0
4.412 0.579 tINS RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n100_s19/F
4.619 0.206 tNET RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n100_s31/I3
4.907 0.289 tINS RR 2 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n100_s31/F
5.114 0.206 tNET RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n103_s10/I2
5.621 0.507 tINS RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n103_s10/F
5.827 0.206 tNET RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n103_s8/I2
6.335 0.507 tINS RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n103_s8/F
6.541 0.206 tNET RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/next_state_6_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
5.000 0.000 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n122_9
5.000 0.000 tCL FF 8 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n101_s6/F
5.193 0.192 tNET FF 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/next_state_6_s0/G
5.158 -0.035 tUnc slvs_ec_rx_wrapper_inst/slvs_rx_phy/next_state_6_s0
5.094 -0.064 tSu 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/next_state_6_s0
Path Statistics:
Clock Skew: -0.696
Setup Relationship: 5.000
Logic Level: 10
Arrival Clock Path Delay: cell: 0.683, 76.793%; route: 0.206, 23.207%
Arrival Data Path Delay: cell: 4.032, 71.340%; route: 1.237, 21.893%; tC2Q: 0.382, 6.767%
Required Clock Path Delay: cell: 0.683, 76.793%; route: 0.206, 23.207%

Path 2

Path Summary:
Slack -0.515
Data Arrival Time 5.609
Data Required Time 5.094
From slvs_ec_rx_wrapper_inst/slvs_rx_phy/idle_code_0_s0
To slvs_ec_rx_wrapper_inst/slvs_rx_phy/next_state_7_s0
Launch Clk i_clk[F]
Latch Clk slvs_ec_rx_wrapper_inst/slvs_rx_phy/n122_9[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 i_clk
0.000 0.000 tCL RR 1 i_clk_ibuf/I
0.683 0.683 tINS RR 1438 i_clk_ibuf/O
0.889 0.206 tNET RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/idle_code_0_s0/CLK
1.271 0.382 tC2Q RR 2 slvs_ec_rx_wrapper_inst/slvs_rx_phy/idle_code_0_s0/Q
1.477 0.206 tNET RR 2 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1478_s0/I1
2.077 0.600 tINS RF 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1478_s0/COUT
2.077 0.000 tNET FF 2 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1479_s0/CIN
2.127 0.050 tINS FR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1479_s0/COUT
2.127 0.000 tNET RR 2 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1480_s0/CIN
2.177 0.050 tINS RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1480_s0/COUT
2.177 0.000 tNET RR 2 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1481_s0/CIN
2.227 0.050 tINS RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1481_s0/COUT
2.227 0.000 tNET RR 2 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1482_s0/CIN
2.277 0.050 tINS RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1482_s0/COUT
2.277 0.000 tNET RR 2 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1483_s0/CIN
2.327 0.050 tINS RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1483_s0/COUT
2.327 0.000 tNET RR 2 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1484_s0/CIN
2.377 0.050 tINS RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1484_s0/COUT
2.377 0.000 tNET RR 2 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1485_s0/CIN
2.427 0.050 tINS RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1485_s0/COUT
2.427 0.000 tNET RR 2 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1486_s0/CIN
2.477 0.050 tINS RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1486_s0/COUT
2.477 0.000 tNET RR 2 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1487_s0/CIN
2.527 0.050 tINS RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1487_s0/COUT
2.527 0.000 tNET RR 2 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1488_s0/CIN
2.577 0.050 tINS RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1488_s0/COUT
2.577 0.000 tNET RR 2 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1489_s0/CIN
2.627 0.050 tINS RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1489_s0/COUT
2.627 0.000 tNET RR 2 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1490_s0/CIN
2.677 0.050 tINS RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1490_s0/COUT
2.677 0.000 tNET RR 2 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1491_s0/CIN
2.727 0.050 tINS RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1491_s0/COUT
2.727 0.000 tNET RR 2 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1492_s0/CIN
2.777 0.050 tINS RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1492_s0/COUT
2.777 0.000 tNET RR 2 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1493_s0/CIN
2.827 0.050 tINS RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1493_s0/COUT
2.827 0.000 tNET RR 2 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1494_s0/CIN
2.877 0.050 tINS RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1494_s0/COUT
2.877 0.000 tNET RR 2 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1495_s0/CIN
2.927 0.050 tINS RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1495_s0/COUT
2.927 0.000 tNET RR 2 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1496_s0/CIN
2.977 0.050 tINS RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1496_s0/COUT
2.977 0.000 tNET RR 2 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1497_s0/CIN
3.027 0.050 tINS RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1497_s0/COUT
3.027 0.000 tNET RR 2 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1498_s0/CIN
3.077 0.050 tINS RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1498_s0/COUT
3.077 0.000 tNET RR 2 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1499_s0/CIN
3.127 0.050 tINS RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1499_s0/COUT
3.127 0.000 tNET RR 2 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1500_s0/CIN
3.177 0.050 tINS RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1500_s0/COUT
3.177 0.000 tNET RR 2 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1501_s0/CIN
3.227 0.050 tINS RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1501_s0/COUT
3.227 0.000 tNET RR 2 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1502_s0/CIN
3.277 0.050 tINS RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1502_s0/COUT
3.277 0.000 tNET RR 2 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1503_s0/CIN
3.327 0.050 tINS RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1503_s0/COUT
3.327 0.000 tNET RR 2 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1504_s0/CIN
3.377 0.050 tINS RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1504_s0/COUT
3.377 0.000 tNET RR 2 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1505_s0/CIN
3.427 0.050 tINS RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1505_s0/COUT
3.427 0.000 tNET RR 2 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1506_s0/CIN
3.477 0.050 tINS RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1506_s0/COUT
3.477 0.000 tNET RR 2 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1507_s0/CIN
3.527 0.050 tINS RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1507_s0/COUT
3.527 0.000 tNET RR 2 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1508_s0/CIN
3.577 0.050 tINS RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1508_s0/COUT
3.577 0.000 tNET RR 2 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1509_s0/CIN
3.627 0.050 tINS RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n1509_s0/COUT
3.834 0.206 tNET RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n100_s19/I0
4.412 0.579 tINS RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n100_s19/F
4.619 0.206 tNET RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n100_s31/I3
4.907 0.289 tINS RR 2 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n100_s31/F
5.114 0.206 tNET RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n100_s8/I3
5.402 0.289 tINS RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n100_s8/F
5.609 0.206 tNET RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/next_state_7_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
5.000 0.000 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n122_9
5.000 0.000 tCL FF 8 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n101_s6/F
5.193 0.192 tNET FF 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/next_state_7_s0/G
5.158 -0.035 tUnc slvs_ec_rx_wrapper_inst/slvs_rx_phy/next_state_7_s0
5.094 -0.064 tSu 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/next_state_7_s0
Path Statistics:
Clock Skew: -0.696
Setup Relationship: 5.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.683, 76.793%; route: 0.206, 23.207%
Arrival Data Path Delay: cell: 3.306, 70.047%; route: 1.031, 21.849%; tC2Q: 0.382, 8.104%
Required Clock Path Delay: cell: 0.683, 76.793%; route: 0.206, 23.207%

Path 3

Path Summary:
Slack -0.226
Data Arrival Time 5.320
Data Required Time 5.094
From slvs_ec_rx_wrapper_inst/slvs_rx_phy/current_state_0_s0
To slvs_ec_rx_wrapper_inst/slvs_rx_phy/next_state_4_s0
Launch Clk i_clk[F]
Latch Clk slvs_ec_rx_wrapper_inst/slvs_rx_phy/n122_9[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 i_clk
0.000 0.000 tCL RR 1 i_clk_ibuf/I
0.683 0.683 tINS RR 1438 i_clk_ibuf/O
0.889 0.206 tNET RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/current_state_0_s0/CLK
1.271 0.382 tC2Q RR 6 slvs_ec_rx_wrapper_inst/slvs_rx_phy/current_state_0_s0/Q
1.477 0.206 tNET RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n112_s11/I0
2.056 0.579 tINS RR 4 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n112_s11/F
2.263 0.206 tNET RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n103_s11/I2
2.770 0.507 tINS RR 3 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n103_s11/F
2.976 0.206 tNET RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n106_s11/I0
3.555 0.579 tINS RR 2 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n106_s11/F
3.761 0.206 tNET RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n109_s23/I0
4.340 0.579 tINS RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n109_s23/F
4.546 0.206 tNET RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n109_s7/I1
5.114 0.567 tINS RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n109_s7/F
5.320 0.206 tNET RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/next_state_4_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
5.000 0.000 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n122_9
5.000 0.000 tCL FF 8 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n101_s6/F
5.193 0.192 tNET FF 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/next_state_4_s0/G
5.158 -0.035 tUnc slvs_ec_rx_wrapper_inst/slvs_rx_phy/next_state_4_s0
5.094 -0.064 tSu 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/next_state_4_s0
Path Statistics:
Clock Skew: -0.696
Setup Relationship: 5.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.683, 76.793%; route: 0.206, 23.207%
Arrival Data Path Delay: cell: 2.811, 63.441%; route: 1.237, 27.927%; tC2Q: 0.382, 8.632%
Required Clock Path Delay: cell: 0.683, 76.793%; route: 0.206, 23.207%

Path 4

Path Summary:
Slack -0.215
Data Arrival Time 5.309
Data Required Time 5.094
From slvs_ec_rx_wrapper_inst/slvs_rx_phy/lane0_data_d5_10_s0
To slvs_ec_rx_wrapper_inst/slvs_rx_phy/next_state_5_s0
Launch Clk i_clk[F]
Latch Clk slvs_ec_rx_wrapper_inst/slvs_rx_phy/n122_9[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 i_clk
0.000 0.000 tCL RR 1 i_clk_ibuf/I
0.683 0.683 tINS RR 1438 i_clk_ibuf/O
0.889 0.206 tNET RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/lane0_data_d5_10_s0/CLK
1.271 0.382 tC2Q RR 5 slvs_ec_rx_wrapper_inst/slvs_rx_phy/lane0_data_d5_10_s0/Q
1.477 0.206 tNET RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/standby_code_dect_s18/I0
2.056 0.579 tINS RR 3 slvs_ec_rx_wrapper_inst/slvs_rx_phy/standby_code_dect_s18/F
2.263 0.206 tNET RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/standby_code_dect_s8/I1
2.830 0.567 tINS RR 2 slvs_ec_rx_wrapper_inst/slvs_rx_phy/standby_code_dect_s8/F
3.036 0.206 tNET RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n109_s12/I1
3.604 0.567 tINS RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n109_s12/F
3.810 0.206 tNET RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n109_s8/I2
4.317 0.507 tINS RR 3 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n109_s8/F
4.524 0.206 tNET RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n106_s8/I0
5.102 0.579 tINS RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n106_s8/F
5.309 0.206 tNET RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/next_state_5_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
5.000 0.000 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n122_9
5.000 0.000 tCL FF 8 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n101_s6/F
5.193 0.192 tNET FF 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/next_state_5_s0/G
5.158 -0.035 tUnc slvs_ec_rx_wrapper_inst/slvs_rx_phy/next_state_5_s0
5.094 -0.064 tSu 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/next_state_5_s0
Path Statistics:
Clock Skew: -0.696
Setup Relationship: 5.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.683, 76.793%; route: 0.206, 23.207%
Arrival Data Path Delay: cell: 2.800, 63.348%; route: 1.237, 27.998%; tC2Q: 0.382, 8.654%
Required Clock Path Delay: cell: 0.683, 76.793%; route: 0.206, 23.207%

Path 5

Path Summary:
Slack -0.019
Data Arrival Time 5.113
Data Required Time 5.094
From slvs_ec_rx_wrapper_inst/slvs_rx_phy/lane0_data_d4_12_s0
To slvs_ec_rx_wrapper_inst/slvs_rx_phy/next_state_3_s0
Launch Clk i_clk[F]
Latch Clk slvs_ec_rx_wrapper_inst/slvs_rx_phy/n122_9[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 i_clk
0.000 0.000 tCL RR 1 i_clk_ibuf/I
0.683 0.683 tINS RR 1438 i_clk_ibuf/O
0.889 0.206 tNET RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/lane0_data_d4_12_s0/CLK
1.271 0.382 tC2Q RR 6 slvs_ec_rx_wrapper_inst/slvs_rx_phy/lane0_data_d4_12_s0/Q
1.477 0.206 tNET RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n5462_s7/I0
2.056 0.579 tINS RR 2 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n5462_s7/F
2.263 0.206 tNET RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n5462_s3/I0
2.841 0.579 tINS RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n5462_s3/F
3.047 0.206 tNET RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n5462_s2/I0
3.626 0.579 tINS RR 3 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n5462_s2/F
3.832 0.206 tNET RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n112_s9/I0
4.411 0.579 tINS RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n112_s9/F
4.617 0.206 tNET RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n112_s7/I3
4.906 0.289 tINS RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n112_s7/F
5.113 0.206 tNET RR 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/next_state_3_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
5.000 0.000 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n122_9
5.000 0.000 tCL FF 8 slvs_ec_rx_wrapper_inst/slvs_rx_phy/n101_s6/F
5.193 0.192 tNET FF 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/next_state_3_s0/G
5.158 -0.035 tUnc slvs_ec_rx_wrapper_inst/slvs_rx_phy/next_state_3_s0
5.094 -0.064 tSu 1 slvs_ec_rx_wrapper_inst/slvs_rx_phy/next_state_3_s0
Path Statistics:
Clock Skew: -0.696
Setup Relationship: 5.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.683, 76.793%; route: 0.206, 23.207%
Arrival Data Path Delay: cell: 2.604, 61.645%; route: 1.237, 29.299%; tC2Q: 0.382, 9.056%
Required Clock Path Delay: cell: 0.683, 76.793%; route: 0.206, 23.207%