Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | D:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\I2CMASTER\data\I2C_MASTER_TOP.v D:\Gowin\Gowin_V1.9.9Beta3-1\IDE\ipcore\I2CMASTER\data\I2C_MASTER.vp |
GowinSynthesis Constraints File | --- |
Version | V1.9.9 Beta3-1 |
Part Number | GW5AST-LV138FPG676AES |
Device | GW5AST-138 |
Device Version | B |
Created Time | Mon Apr 10 09:04:36 2023 |
Legal Announcement | Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | I2C_MASTER_Top |
Synthesis Process | Running parser: CPU time = 0h 0m 0.328s, Elapsed time = 0h 0m 0.396s, Peak memory usage = 39.422MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 39.422MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 39.422MB Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 39.422MB Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 39.422MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 39.422MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 39.422MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 39.422MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 39.422MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.017s, Peak memory usage = 39.422MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 39.422MB Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 39.422MB Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 51.191MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.051s, Peak memory usage = 51.191MB Generate output files: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.027s, Peak memory usage = 51.191MB |
Total Time and Memory Usage | CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 51.191MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 29 |
I/O Buf | 29 |
    IBUF | 18 |
    OBUF | 9 |
    IOBUF | 2 |
Register | 124 |
    DFFPE | 7 |
    DFFCE | 117 |
LUT | 216 |
    LUT2 | 27 |
    LUT3 | 75 |
    LUT4 | 114 |
INV | 1 |
    INV | 1 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 217(217 LUTs, 0 ALUs) / 138240 | <1% |
Register | 124 / 139140 | <1% |
  --Register as Latch | 0 / 139140 | 0% |
  --Register as FF | 124 / 139140 | <1% |
BSRAM | 0 / 340 | 0% |
Timing
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|
I_CLK | Base | 10.000 | 100.0 | 0.000 | 5.000 | I_CLK_ibuf/I |
Max Frequency Summary:
No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | I_CLK | 100.0(MHz) | 272.3(MHz) | 5 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | 6.328 |
Data Arrival Time | 4.500 |
Data Required Time | 10.828 |
From | u_i2c_master/bit_controller/cnt_10_s1 |
To | u_i2c_master/bit_controller/cnt_14_s1 |
Launch Clk | I_CLK[R] |
Latch Clk | I_CLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | I_CLK | |||
0.000 | 0.000 | tCL | RR | 1 | I_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 124 | I_CLK_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | u_i2c_master/bit_controller/cnt_10_s1/CLK |
1.095 | 0.232 | tC2Q | RF | 4 | u_i2c_master/bit_controller/cnt_10_s1/Q |
1.332 | 0.237 | tNET | FF | 1 | u_i2c_master/bit_controller/n13_s3/I1 |
1.887 | 0.555 | tINS | FF | 1 | u_i2c_master/bit_controller/n13_s3/F |
2.124 | 0.237 | tNET | FF | 1 | u_i2c_master/bit_controller/n13_s1/I1 |
2.679 | 0.555 | tINS | FF | 4 | u_i2c_master/bit_controller/n13_s1/F |
2.916 | 0.237 | tNET | FF | 1 | u_i2c_master/bit_controller/n32_s1/I1 |
3.471 | 0.555 | tINS | FF | 1 | u_i2c_master/bit_controller/n32_s1/F |
3.708 | 0.237 | tNET | FF | 1 | u_i2c_master/bit_controller/n32_s0/I1 |
4.263 | 0.555 | tINS | FF | 1 | u_i2c_master/bit_controller/n32_s0/F |
4.500 | 0.237 | tNET | FF | 1 | u_i2c_master/bit_controller/cnt_14_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | I_CLK | |||
10.000 | 0.000 | tCL | RR | 1 | I_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 124 | I_CLK_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | u_i2c_master/bit_controller/cnt_14_s1/CLK |
10.828 | -0.035 | tSu | 1 | u_i2c_master/bit_controller/cnt_14_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 2.220, 61.039%; route: 1.185, 32.582%; tC2Q: 0.232, 6.379% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 2
Path Summary:Slack | 6.366 |
Data Arrival Time | 4.462 |
Data Required Time | 10.828 |
From | u_i2c_master/byte_controller/c_state_2_s0 |
To | u_i2c_master/byte_controller/CORE_CMD_2_s0 |
Launch Clk | I_CLK[R] |
Latch Clk | I_CLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | I_CLK | |||
0.000 | 0.000 | tCL | RR | 1 | I_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 124 | I_CLK_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | u_i2c_master/byte_controller/c_state_2_s0/CLK |
1.095 | 0.232 | tC2Q | RF | 8 | u_i2c_master/byte_controller/c_state_2_s0/Q |
1.332 | 0.237 | tNET | FF | 1 | u_i2c_master/byte_controller/n208_s4/I1 |
1.887 | 0.555 | tINS | FF | 2 | u_i2c_master/byte_controller/n208_s4/F |
2.124 | 0.237 | tNET | FF | 1 | u_i2c_master/byte_controller/n200_s5/I0 |
2.641 | 0.517 | tINS | FF | 1 | u_i2c_master/byte_controller/n200_s5/F |
2.878 | 0.237 | tNET | FF | 1 | u_i2c_master/byte_controller/n200_s3/I1 |
3.433 | 0.555 | tINS | FF | 2 | u_i2c_master/byte_controller/n200_s3/F |
3.670 | 0.237 | tNET | FF | 1 | u_i2c_master/byte_controller/n200_s2/I1 |
4.225 | 0.555 | tINS | FF | 1 | u_i2c_master/byte_controller/n200_s2/F |
4.462 | 0.237 | tNET | FF | 1 | u_i2c_master/byte_controller/CORE_CMD_2_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | I_CLK | |||
10.000 | 0.000 | tCL | RR | 1 | I_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 124 | I_CLK_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | u_i2c_master/byte_controller/CORE_CMD_2_s0/CLK |
10.828 | -0.035 | tSu | 1 | u_i2c_master/byte_controller/CORE_CMD_2_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 2.182, 60.628%; route: 1.185, 32.926%; tC2Q: 0.232, 6.446% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 3
Path Summary:Slack | 6.366 |
Data Arrival Time | 4.462 |
Data Required Time | 10.828 |
From | u_i2c_master/byte_controller/c_state_2_s0 |
To | u_i2c_master/byte_controller/CORE_CMD_3_s0 |
Launch Clk | I_CLK[R] |
Latch Clk | I_CLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | I_CLK | |||
0.000 | 0.000 | tCL | RR | 1 | I_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 124 | I_CLK_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | u_i2c_master/byte_controller/c_state_2_s0/CLK |
1.095 | 0.232 | tC2Q | RF | 8 | u_i2c_master/byte_controller/c_state_2_s0/Q |
1.332 | 0.237 | tNET | FF | 1 | u_i2c_master/byte_controller/n208_s4/I1 |
1.887 | 0.555 | tINS | FF | 2 | u_i2c_master/byte_controller/n208_s4/F |
2.124 | 0.237 | tNET | FF | 1 | u_i2c_master/byte_controller/n200_s5/I0 |
2.641 | 0.517 | tINS | FF | 1 | u_i2c_master/byte_controller/n200_s5/F |
2.878 | 0.237 | tNET | FF | 1 | u_i2c_master/byte_controller/n200_s3/I1 |
3.433 | 0.555 | tINS | FF | 2 | u_i2c_master/byte_controller/n200_s3/F |
3.670 | 0.237 | tNET | FF | 1 | u_i2c_master/byte_controller/n199_s2/I1 |
4.225 | 0.555 | tINS | FF | 1 | u_i2c_master/byte_controller/n199_s2/F |
4.462 | 0.237 | tNET | FF | 1 | u_i2c_master/byte_controller/CORE_CMD_3_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | I_CLK | |||
10.000 | 0.000 | tCL | RR | 1 | I_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 124 | I_CLK_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | u_i2c_master/byte_controller/CORE_CMD_3_s0/CLK |
10.828 | -0.035 | tSu | 1 | u_i2c_master/byte_controller/CORE_CMD_3_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 2.182, 60.628%; route: 1.185, 32.926%; tC2Q: 0.232, 6.446% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 4
Path Summary:Slack | 6.391 |
Data Arrival Time | 4.437 |
Data Required Time | 10.828 |
From | u_i2c_master/bit_controller/c_state_3_s1 |
To | u_i2c_master/bit_controller/SCL_OEN_s1 |
Launch Clk | I_CLK[R] |
Latch Clk | I_CLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | I_CLK | |||
0.000 | 0.000 | tCL | RR | 1 | I_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 124 | I_CLK_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | u_i2c_master/bit_controller/c_state_3_s1/CLK |
1.095 | 0.232 | tC2Q | RF | 6 | u_i2c_master/bit_controller/c_state_3_s1/Q |
1.332 | 0.237 | tNET | FF | 1 | u_i2c_master/bit_controller/n227_s6/I1 |
1.887 | 0.555 | tINS | FF | 7 | u_i2c_master/bit_controller/n227_s6/F |
2.124 | 0.237 | tNET | FF | 1 | u_i2c_master/bit_controller/n214_s4/I1 |
2.679 | 0.555 | tINS | FF | 7 | u_i2c_master/bit_controller/n214_s4/F |
2.916 | 0.237 | tNET | FF | 1 | u_i2c_master/bit_controller/n228_s4/I1 |
3.471 | 0.555 | tINS | FF | 4 | u_i2c_master/bit_controller/n228_s4/F |
3.708 | 0.237 | tNET | FF | 1 | u_i2c_master/bit_controller/SCL_OEN_s5/I0 |
4.257 | 0.549 | tINS | FR | 1 | u_i2c_master/bit_controller/SCL_OEN_s5/F |
4.437 | 0.180 | tNET | RR | 1 | u_i2c_master/bit_controller/SCL_OEN_s1/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | I_CLK | |||
10.000 | 0.000 | tCL | RR | 1 | I_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 124 | I_CLK_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | u_i2c_master/bit_controller/SCL_OEN_s1/CLK |
10.828 | -0.035 | tSu | 1 | u_i2c_master/bit_controller/SCL_OEN_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 2.214, 61.948%; route: 1.128, 31.561%; tC2Q: 0.232, 6.491% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 5
Path Summary:Slack | 6.404 |
Data Arrival Time | 4.424 |
Data Required Time | 10.828 |
From | u_i2c_master/bit_controller/c_state_3_s1 |
To | u_i2c_master/bit_controller/SDA_OEN_s1 |
Launch Clk | I_CLK[R] |
Latch Clk | I_CLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | I_CLK | |||
0.000 | 0.000 | tCL | RR | 1 | I_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 124 | I_CLK_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | u_i2c_master/bit_controller/c_state_3_s1/CLK |
1.095 | 0.232 | tC2Q | RF | 6 | u_i2c_master/bit_controller/c_state_3_s1/Q |
1.332 | 0.237 | tNET | FF | 1 | u_i2c_master/bit_controller/n227_s6/I1 |
1.887 | 0.555 | tINS | FF | 7 | u_i2c_master/bit_controller/n227_s6/F |
2.124 | 0.237 | tNET | FF | 1 | u_i2c_master/bit_controller/n226_s4/I1 |
2.679 | 0.555 | tINS | FF | 4 | u_i2c_master/bit_controller/n226_s4/F |
2.916 | 0.237 | tNET | FF | 1 | u_i2c_master/bit_controller/n230_s8/I0 |
3.433 | 0.517 | tINS | FF | 1 | u_i2c_master/bit_controller/n230_s8/F |
3.670 | 0.237 | tNET | FF | 1 | u_i2c_master/bit_controller/n230_s1/I0 |
4.187 | 0.517 | tINS | FF | 1 | u_i2c_master/bit_controller/n230_s1/F |
4.424 | 0.237 | tNET | FF | 1 | u_i2c_master/bit_controller/SDA_OEN_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | I_CLK | |||
10.000 | 0.000 | tCL | RR | 1 | I_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 124 | I_CLK_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | u_i2c_master/bit_controller/SDA_OEN_s1/CLK |
10.828 | -0.035 | tSu | 1 | u_i2c_master/bit_controller/SDA_OEN_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 2.144, 60.208%; route: 1.185, 33.277%; tC2Q: 0.232, 6.515% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |