Power Messages
Report Title | Power Analysis Report |
Design File | E:\IP_Release\SSCPLL\1.1\ref_design\Gowin_SSCPLL_RefDesign\project\impl\gwsynthesis\fpga_project.vg |
Physical Constraints File | E:\IP_Release\SSCPLL\1.1\ref_design\Gowin_SSCPLL_RefDesign\project\src\fpga.cst |
Timing Constraints File | --- |
Tool Version | V1.9.11 (64-bit) |
Part Number | GW5AST-LV138FPG676AC1/I0 |
Device | GW5AST-138 |
Device Version | B |
Created Time | Fri Dec 20 16:50:45 2024 |
Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved. |
Configure Information:
Grade | Commercial |
Process | Typical |
Ambient Temperature | 25.000 |
Use Custom Theta JA | false |
Heat Sink | None |
Air Flow | LFM_0 |
Use Custom Theta SA | false |
Board Thermal Model | None |
Use Custom Theta JB | false |
Related Vcd File | |
Related Saif File | |
Filter Glitches | false |
Default IO Toggle Rate | 0.125 |
Default Remain Toggle Rate | 0.125 |
Power Summary
Power Information:
Total Power (mW) | 124.910 |
Quiescent Power (mW) | 100.679 |
Dynamic Power (mW) | 24.231 |
Thermal Information:
Junction Temperature | 26.624 |
Theta JA | 13.000 |
Max Allowed Ambient Temperature | 83.376 |
Supply Information:
Voltage Source | Voltage | Dynamic Current(mA) | Quiescent Current(mA) | Power(mW) |
---|---|---|---|---|
VCC | 0.900 | 0.050 | 80.001 | 72.046 |
VCCX | 1.800 | 0.050 | 7.200 | 13.050 |
VCCIO33 | 3.300 | 0.050 | 3.017 | 10.123 |
VCC_LDO | 1.200 | 19.941 | 4.800 | 29.690 |
Power Details
Power By Block Type:
Block Type | Total Power(mW) | Static Power(mW) | Average Toggle Rate(millions of transitions/sec) |
---|---|---|---|
IO | 10.422 | 10.121 | 9.375 |
PLL | 23.930 | NA | NA |
Power By Hierarchy:
Hierarchy Entity | Total Power(mW) | Block Dynamic Power(mW) |
---|---|---|
top | 23.930 | 23.930(23.930) |
top/sscpll0/ | 23.930 | 23.930(23.930) |
top/sscpll0/u_gwfpll/ | 23.930 | 23.930(23.930) |
top/sscpll0/u_gwfpll/u_mdiv_code_conv/ | 0.000 | 0.000(0.000) |
top/sscpll0/u_gwfpll/u_pll0/ | 23.930 | 23.930(0.000) |
top/sscpll0/u_gwfpll/u_sdm2/ | 0.000 | 0.000(0.000) |
top/sscpll0/u_gwfpll/u_sdm2/mod_h_inst/ | 0.000 | 0.000(0.000) |
top/sscpll0/u_gwfpll/u_triangle_codegen/ | 0.000 | 0.000(0.000) |
top/sscpll0/u_gwfpll/u_triangle_codegen/clkdiv_u0/ | 0.000 | 0.000(0.000) |
Power By Clock Domain:
Clock Domain | Clock Frequency(Mhz) | Total Dynamic Power(mW) |
---|---|---|
NO CLOCK DOMAIN | 0.000 | 0.000 |
sys_clk | 50.000 | 23.930 |