Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\SERDES_IP\IPlib\SRIO\data\srio_top.v
C:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\SERDES_IP\IPlib\SRIO\data\srio_core_encryption.v
GowinSynthesis Constraints File ---
Version V1.9.9 Beta-3
Part Number GW5AST-LV138FPG676AES
Device GW5AST-138
Device Version B
Created Time Thu Jul 27 11:32:48 2023
Legal Announcement Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module SRIO_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 113.785MB
Running netlist conversion:
    CPU time = 0h 0m 0.187s, Elapsed time = 0h 0m 0.198s, Peak memory usage = 113.785MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.953s, Elapsed time = 0h 0m 0.941s, Peak memory usage = 113.785MB
    Optimizing Phase 1: CPU time = 0h 0m 0.546s, Elapsed time = 0h 0m 0.552s, Peak memory usage = 113.785MB
    Optimizing Phase 2: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 113.785MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.468s, Elapsed time = 0h 0m 0.478s, Peak memory usage = 113.785MB
    Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 113.785MB
    Inferring Phase 2: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.108s, Peak memory usage = 113.785MB
    Inferring Phase 3: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.037s, Peak memory usage = 113.785MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 113.785MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.265s, Elapsed time = 0h 0m 0.258s, Peak memory usage = 113.785MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.531s, Elapsed time = 0h 0m 0.526s, Peak memory usage = 113.785MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 28s, Elapsed time = 0h 0m 29s, Peak memory usage = 117.176MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 117.176MB
Generate output files:
    CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 126.285MB
Total Time and Memory Usage CPU time = 0h 0m 36s, Elapsed time = 0h 0m 37s, Peak memory usage = 126.285MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 955
I/O Buf 853
    IBUF 357
    OBUF 496
Register 7453
    DFFSE 439
    DFFRE 7008
    DFFPE 6
LUT 6683
    LUT2 982
    LUT3 2001
    LUT4 3700
ALU 649
    ALU 649
INV 114
    INV 114
BSRAM 24
    SDPB 16
    SDPX9B 8

Resource Utilization Summary

Resource Usage Utilization
Logic 7446(6797 LUTs, 649 ALUs) / 138240 6%
Register 7453 / 139140 6%
  --Register as Latch 0 / 139140 0%
  --Register as FF 7453 / 139140 6%
BSRAM 24 / 340 8%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
srio_clk_i Base 10.000 100.0 0.000 5.000 srio_clk_i_ibuf/I
user_pcs_clk_i Base 10.000 100.0 0.000 5.000 user_pcs_clk_i_ibuf/I
cfg_clk_i Base 10.000 100.0 0.000 5.000 cfg_clk_i_ibuf/I

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 srio_clk_i 100.0(MHz) 145.7(MHz) 10 TOP
2 user_pcs_clk_i 100.0(MHz) 231.3(MHz) 6 TOP
3 cfg_clk_i 100.0(MHz) 201.9(MHz) 7 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 3.136
Data Arrival Time 7.692
Data Required Time 10.828
From u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/stage2_reg_valid_s1
To u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/first_beat_mask_s1
Launch Clk srio_clk_i[R]
Latch Clk srio_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 srio_clk_i
0.000 0.000 tCL RR 1 srio_clk_i_ibuf/I
0.683 0.683 tINS RR 5056 srio_clk_i_ibuf/O
0.863 0.180 tNET RR 1 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/stage2_reg_valid_s1/CLK
1.095 0.232 tC2Q RF 12 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/stage2_reg_valid_s1/Q
1.332 0.237 tNET FF 1 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/pipe_tx_ready_s1/I1
1.887 0.555 tINS FF 24 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/pipe_tx_ready_s1/F
2.124 0.237 tNET FF 1 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/grant_1_s1/I1
2.679 0.555 tINS FF 5 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/grant_1_s1/F
2.916 0.237 tNET FF 1 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/pre_req_1_s2/I2
3.369 0.453 tINS FF 2 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/pre_req_1_s2/F
3.606 0.237 tNET FF 1 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/pre_req_2_s2/I3
3.977 0.371 tINS FF 1 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/pre_req_2_s2/F
4.214 0.237 tNET FF 1 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/grant_3_s1/I0
4.731 0.517 tINS FF 8 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/grant_3_s1/F
4.968 0.237 tNET FF 1 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/single_beat_s11/I3
5.339 0.371 tINS FF 1 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/single_beat_s11/F
5.576 0.237 tNET FF 1 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/single_beat_s8/I0
6.093 0.517 tINS FF 1 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/single_beat_s8/F
6.330 0.237 tNET FF 1 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/single_beat_s6/I3
6.701 0.371 tINS FF 2 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/single_beat_s6/F
6.938 0.237 tNET FF 1 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/n728_s1/I0
7.455 0.517 tINS FF 1 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/n728_s1/F
7.692 0.237 tNET FF 1 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/first_beat_mask_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 srio_clk_i
10.000 0.000 tCL RR 1 srio_clk_i_ibuf/I
10.682 0.683 tINS RR 5056 srio_clk_i_ibuf/O
10.863 0.180 tNET RR 1 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/first_beat_mask_s1/CLK
10.828 -0.035 tSu 1 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/first_beat_mask_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 10
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 4.227, 61.898%; route: 2.370, 34.705%; tC2Q: 0.232, 3.397%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 2

Path Summary:
Slack 3.140
Data Arrival Time 7.688
Data Required Time 10.828
From u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/stage2_reg_valid_s1
To u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/single_beat_s0
Launch Clk srio_clk_i[R]
Latch Clk srio_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 srio_clk_i
0.000 0.000 tCL RR 1 srio_clk_i_ibuf/I
0.683 0.683 tINS RR 5056 srio_clk_i_ibuf/O
0.863 0.180 tNET RR 1 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/stage2_reg_valid_s1/CLK
1.095 0.232 tC2Q RF 12 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/stage2_reg_valid_s1/Q
1.332 0.237 tNET FF 1 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/pipe_tx_ready_s1/I1
1.887 0.555 tINS FF 24 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/pipe_tx_ready_s1/F
2.124 0.237 tNET FF 1 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/grant_1_s1/I1
2.679 0.555 tINS FF 5 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/grant_1_s1/F
2.916 0.237 tNET FF 1 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/pre_req_1_s2/I2
3.369 0.453 tINS FF 2 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/pre_req_1_s2/F
3.606 0.237 tNET FF 1 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/pre_req_2_s2/I3
3.977 0.371 tINS FF 1 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/pre_req_2_s2/F
4.214 0.237 tNET FF 1 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/grant_3_s1/I0
4.731 0.517 tINS FF 8 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/grant_3_s1/F
4.968 0.237 tNET FF 1 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/single_beat_s11/I3
5.339 0.371 tINS FF 1 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/single_beat_s11/F
5.576 0.237 tNET FF 1 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/single_beat_s8/I0
6.093 0.517 tINS FF 1 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/single_beat_s8/F
6.330 0.237 tNET FF 1 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/single_beat_s6/I3
6.701 0.371 tINS FF 2 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/single_beat_s6/F
6.938 0.237 tNET FF 1 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/single_beat_s5/I1
7.508 0.570 tINS FR 1 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/single_beat_s5/F
7.688 0.180 tNET RR 1 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/single_beat_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 srio_clk_i
10.000 0.000 tCL RR 1 srio_clk_i_ibuf/I
10.682 0.683 tINS RR 5056 srio_clk_i_ibuf/O
10.863 0.180 tNET RR 1 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/single_beat_s0/CLK
10.828 -0.035 tSu 1 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/single_beat_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 10
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 4.280, 62.711%; route: 2.313, 33.890%; tC2Q: 0.232, 3.399%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 3

Path Summary:
Slack 3.808
Data Arrival Time 7.020
Data Required Time 10.828
From u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/stage2_reg_valid_s1
To u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/port_pend_s_beat_0_s1
Launch Clk srio_clk_i[R]
Latch Clk srio_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 srio_clk_i
0.000 0.000 tCL RR 1 srio_clk_i_ibuf/I
0.683 0.683 tINS RR 5056 srio_clk_i_ibuf/O
0.863 0.180 tNET RR 1 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/stage2_reg_valid_s1/CLK
1.095 0.232 tC2Q RF 12 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/stage2_reg_valid_s1/Q
1.332 0.237 tNET FF 1 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/pipe_tx_ready_s1/I1
1.887 0.555 tINS FF 24 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/pipe_tx_ready_s1/F
2.124 0.237 tNET FF 1 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/grant_1_s1/I1
2.679 0.555 tINS FF 5 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/grant_1_s1/F
2.916 0.237 tNET FF 1 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/pre_req_1_s2/I2
3.369 0.453 tINS FF 2 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/pre_req_1_s2/F
3.606 0.237 tNET FF 1 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/pre_req_2_s2/I3
3.977 0.371 tINS FF 1 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/pre_req_2_s2/F
4.214 0.237 tNET FF 1 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/grant_3_s1/I0
4.731 0.517 tINS FF 8 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/grant_3_s1/F
4.968 0.237 tNET FF 1 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/n497_s0/I3
5.339 0.371 tINS FF 2 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/n497_s0/F
5.576 0.237 tNET FF 1 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/n627_s1/I0
6.093 0.517 tINS FF 1 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/n627_s1/F
6.330 0.237 tNET FF 1 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/n627_s0/I2
6.783 0.453 tINS FF 1 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/n627_s0/F
7.020 0.237 tNET FF 1 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/port_pend_s_beat_0_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 srio_clk_i
10.000 0.000 tCL RR 1 srio_clk_i_ibuf/I
10.682 0.683 tINS RR 5056 srio_clk_i_ibuf/O
10.863 0.180 tNET RR 1 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/port_pend_s_beat_0_s1/CLK
10.828 -0.035 tSu 1 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/port_pend_s_beat_0_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 3.792, 61.589%; route: 2.133, 34.643%; tC2Q: 0.232, 3.768%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 4

Path Summary:
Slack 3.808
Data Arrival Time 7.020
Data Required Time 10.828
From u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/stage2_reg_valid_s1
To u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/single_beat_s0
Launch Clk srio_clk_i[R]
Latch Clk srio_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 srio_clk_i
0.000 0.000 tCL RR 1 srio_clk_i_ibuf/I
0.683 0.683 tINS RR 5056 srio_clk_i_ibuf/O
0.863 0.180 tNET RR 1 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/stage2_reg_valid_s1/CLK
1.095 0.232 tC2Q RF 12 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/stage2_reg_valid_s1/Q
1.332 0.237 tNET FF 1 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/pipe_tx_ready_s1/I1
1.887 0.555 tINS FF 24 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/pipe_tx_ready_s1/F
2.124 0.237 tNET FF 1 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/grant_1_s1/I1
2.679 0.555 tINS FF 5 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/grant_1_s1/F
2.916 0.237 tNET FF 1 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/pre_req_1_s2/I2
3.369 0.453 tINS FF 2 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/pre_req_1_s2/F
3.606 0.237 tNET FF 1 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/pre_req_2_s2/I3
3.977 0.371 tINS FF 1 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/pre_req_2_s2/F
4.214 0.237 tNET FF 1 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/grant_3_s1/I0
4.731 0.517 tINS FF 8 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/grant_3_s1/F
4.968 0.237 tNET FF 1 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/n784_s26/I3
5.339 0.371 tINS FF 1 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/n784_s26/F
5.576 0.237 tNET FF 1 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/n784_s23/I0
6.093 0.517 tINS FF 1 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/n784_s23/F
6.330 0.237 tNET FF 1 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/n784_s20/I2
6.783 0.453 tINS FF 2 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/n784_s20/F
7.020 0.237 tNET FF 1 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/single_beat_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 srio_clk_i
10.000 0.000 tCL RR 1 srio_clk_i_ibuf/I
10.682 0.683 tINS RR 5056 srio_clk_i_ibuf/O
10.863 0.180 tNET RR 1 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/single_beat_s0/CLK
10.828 -0.035 tSu 1 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/single_beat_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 3.792, 61.589%; route: 2.133, 34.643%; tC2Q: 0.232, 3.768%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 5

Path Summary:
Slack 3.852
Data Arrival Time 6.976
Data Required Time 10.828
From u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/stage2_reg_valid_s1
To u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/win_valid_s0
Launch Clk srio_clk_i[R]
Latch Clk srio_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 srio_clk_i
0.000 0.000 tCL RR 1 srio_clk_i_ibuf/I
0.683 0.683 tINS RR 5056 srio_clk_i_ibuf/O
0.863 0.180 tNET RR 1 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/stage2_reg_valid_s1/CLK
1.095 0.232 tC2Q RF 12 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/stage2_reg_valid_s1/Q
1.332 0.237 tNET FF 1 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/pipe_tx_ready_s1/I1
1.887 0.555 tINS FF 24 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/pipe_tx_ready_s1/F
2.124 0.237 tNET FF 1 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/grant_1_s1/I1
2.679 0.555 tINS FF 5 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/grant_1_s1/F
2.916 0.237 tNET FF 1 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/pre_req_1_s2/I2
3.369 0.453 tINS FF 2 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/pre_req_1_s2/F
3.606 0.237 tNET FF 1 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/pre_req_2_s2/I3
3.977 0.371 tINS FF 1 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/pre_req_2_s2/F
4.214 0.237 tNET FF 1 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/grant_3_s1/I0
4.731 0.517 tINS FF 8 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/grant_3_s1/F
4.968 0.237 tNET FF 1 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/win_index_1_s5/I3
5.339 0.371 tINS FF 5 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/win_index_1_s5/F
5.576 0.237 tNET FF 1 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/win_index_1_s4/I1
6.131 0.555 tINS FF 3 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/win_index_1_s4/F
6.368 0.237 tNET FF 1 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/n479_s0/I3
6.739 0.371 tINS FF 1 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/n479_s0/F
6.976 0.237 tNET FF 1 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/win_valid_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 srio_clk_i
10.000 0.000 tCL RR 1 srio_clk_i_ibuf/I
10.682 0.683 tINS RR 5056 srio_clk_i_ibuf/O
10.863 0.180 tNET RR 1 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/win_valid_s0/CLK
10.828 -0.035 tSu 1 u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/win_valid_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 3.748, 61.312%; route: 2.133, 34.893%; tC2Q: 0.232, 3.795%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%