Synthesis Messages

Report Title GowinSynthesis Report
Design File E:\Lab_Demo-Guide_Book\Gowin_Serial_RapidIO_RefDesign\project\src\debug\cfg_2to1.v
E:\Lab_Demo-Guide_Book\Gowin_Serial_RapidIO_RefDesign\project\src\debug\testreg.v
E:\Lab_Demo-Guide_Book\Gowin_Serial_RapidIO_RefDesign\project\src\fifo_sc_top\fifo_sc_top.v
E:\Lab_Demo-Guide_Book\Gowin_Serial_RapidIO_RefDesign\project\src\gowin_pll\gowin_pll.v
E:\Lab_Demo-Guide_Book\Gowin_Serial_RapidIO_RefDesign\project\src\gowin_pll\gowin_serdes_pll_1p25g.v
E:\Lab_Demo-Guide_Book\Gowin_Serial_RapidIO_RefDesign\project\src\gowin_pll\gowin_serdes_pll_2p5g.v
E:\Lab_Demo-Guide_Book\Gowin_Serial_RapidIO_RefDesign\project\src\gowin_pll\gowin_serdes_pll_3p125g.v
E:\Lab_Demo-Guide_Book\Gowin_Serial_RapidIO_RefDesign\project\src\gowin_pll\gowin_serdes_pll_5g.v
E:\Lab_Demo-Guide_Book\Gowin_Serial_RapidIO_RefDesign\project\src\serdes\serdes.v
E:\Lab_Demo-Guide_Book\Gowin_Serial_RapidIO_RefDesign\project\src\serdes\srio\srio.v
E:\Lab_Demo-Guide_Book\Gowin_Serial_RapidIO_RefDesign\project\src\srio_board.v
E:\Lab_Demo-Guide_Book\Gowin_Serial_RapidIO_RefDesign\project\src\test\gowin_sdpram.v
E:\Lab_Demo-Guide_Book\Gowin_Serial_RapidIO_RefDesign\project\src\test\gowin_srio_maints.v
E:\Lab_Demo-Guide_Book\Gowin_Serial_RapidIO_RefDesign\project\src\test\gowin_srio_request_gen.v
E:\Lab_Demo-Guide_Book\Gowin_Serial_RapidIO_RefDesign\project\src\test\gowin_srio_response_gen.v
E:\Lab_Demo-Guide_Book\Gowin_Serial_RapidIO_RefDesign\project\src\uart_to_bus\uart_to_bus.v
GowinSynthesis Constraints File ---
Version V1.9.9 Beta-3
Part Number GW5AST-LV138FPG676AES
Device GW5AST-138
Device Version B
Created Time Thu Aug 03 14:20:21 2023
Legal Announcement Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module srio_board
Synthesis Process Running parser:
    CPU time = 0h 0m 5s, Elapsed time = 0h 0m 6s, Peak memory usage = 901.703MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.515s, Elapsed time = 0h 0m 0.519s, Peak memory usage = 901.703MB
    Optimizing Phase 1: CPU time = 0h 0m 0.281s, Elapsed time = 0h 0m 0.276s, Peak memory usage = 901.703MB
    Optimizing Phase 2: CPU time = 0h 0m 0.687s, Elapsed time = 0h 0m 0.664s, Peak memory usage = 901.703MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.224s, Peak memory usage = 901.703MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 901.703MB
    Inferring Phase 2: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.152s, Peak memory usage = 901.703MB
    Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.025s, Peak memory usage = 901.703MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 0.98s, Peak memory usage = 901.703MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.12s, Peak memory usage = 901.703MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.06s, Peak memory usage = 901.703MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 901.703MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.343s, Elapsed time = 0h 0m 0.34s, Peak memory usage = 901.703MB
Generate output files:
    CPU time = 0h 0m 0.875s, Elapsed time = 0h 0m 0.867s, Peak memory usage = 901.703MB
Total Time and Memory Usage CPU time = 0h 0m 11s, Elapsed time = 0h 0m 12s, Peak memory usage = 901.703MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 13
I/O Buf 13
    IBUF 4
    OBUF 9
Register 10895
    DFFSE 463
    DFFRE 8531
    DFFPE 20
    DFFCE 1881
LUT 8696
    LUT2 1299
    LUT3 3020
    LUT4 4377
ALU 852
    ALU 852
INV 139
    INV 139
BSRAM 32
    SDPB 22
    SDPX9B 8
    pROM 2
CLOCK 2
    PLL 2
GTR12_QUAD 1

Resource Utilization Summary

Resource Usage Utilization
Logic 9687(8835 LUTs, 852 ALUs) / 138240 8%
Register 10895 / 139140 8%
  --Register as Latch 0 / 139140 0%
  --Register as FF 10895 / 139140 8%
BSRAM 32 / 340 10%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
sys_clk_i Base 20.000 50.0 0.000 10.000 sys_clk_i_ibuf/I

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity

No timing path found in the netlist.