Timing Messages

Report Title Timing Analysis Report
Design File E:\Lab_Demo-Guide_Book\Gowin_Serial_RapidIO_RefDesign\project\impl\gwsynthesis\srio_ed_prj.vg
Physical Constraints File E:\Lab_Demo-Guide_Book\Gowin_Serial_RapidIO_RefDesign\project\src\srio_ed_prj.cst
Timing Constraint File E:\Lab_Demo-Guide_Book\Gowin_Serial_RapidIO_RefDesign\project\src\srio_ed_prj.sdc
Version V1.9.9 Beta-3
Part Number GW5AST-LV138FPG676AES
Device GW5AST-138B
Device Version B
Created Time Thu Aug 03 14:21:29 2023
Legal Announcement Copyright (C)2014-2023 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model Slow 0.855V 85C ES
Hold Delay Model Fast 0.945V 0C ES
Numbers of Paths Analyzed 21331
Numbers of Endpoints Analyzed 21335
Numbers of Falling Endpoints 0
Numbers of Setup Violated Endpoints 0
Numbers of Hold Violated Endpoints 0

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Objects
srio_clk Base 12.800 78.125 0.000 6.400 srio_clk
cfg_clk Base 100.000 10.000 0.000 50.000 clk_10m
pll_ref_clk Base 20.000 50.000 0.000 10.000 sys_clk_i

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 srio_clk 78.125(MHz) 85.507(MHz) 7 TOP
2 cfg_clk 10.000(MHz) 79.290(MHz) 9 TOP

No timing paths to get frequency of pll_ref_clk!

Total Negative Slack Summary:

Clock Name Analysis Type Endpoints TNS Number of Endpoints
srio_clk Setup 0.000 0
srio_clk Hold 0.000 0
cfg_clk Setup 0.000 0
cfg_clk Hold 0.000 0
pll_ref_clk Setup 0.000 0
pll_ref_clk Hold 0.000 0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 1.105 u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/Q u0_srio_response_gen/tdata_out_59_s0/D srio_clk:[R] srio_clk:[R] 12.800 0.000 11.660
2 1.316 u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/Q u0_srio_request_gen/tdata_out_55_s0/D srio_clk:[R] srio_clk:[R] 12.800 0.000 11.449
3 1.331 u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/Q u0_srio_request_gen/tdata_out_27_s0/D srio_clk:[R] srio_clk:[R] 12.800 0.000 11.434
4 1.337 u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/Q u0_srio_request_gen/tdata_out_47_s0/D srio_clk:[R] srio_clk:[R] 12.800 0.000 11.428
5 1.390 u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/Q u0_srio_request_gen/tdata_out_17_s0/D srio_clk:[R] srio_clk:[R] 12.800 0.000 11.375
6 1.390 u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/Q u0_srio_request_gen/tdata_out_25_s0/D srio_clk:[R] srio_clk:[R] 12.800 0.000 11.375
7 1.390 u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/Q u0_srio_request_gen/tdata_out_33_s0/D srio_clk:[R] srio_clk:[R] 12.800 0.000 11.375
8 1.530 u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/Q u0_srio_request_gen/tdata_out_57_s0/D srio_clk:[R] srio_clk:[R] 12.800 0.000 11.235
9 1.551 u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/Q u0_srio_request_gen/tdata_out_1_s0/D srio_clk:[R] srio_clk:[R] 12.800 0.000 11.214
10 1.551 u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/Q u0_srio_request_gen/tdata_out_9_s0/D srio_clk:[R] srio_clk:[R] 12.800 0.000 11.214
11 1.551 u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/Q u0_srio_request_gen/tdata_out_41_s0/D srio_clk:[R] srio_clk:[R] 12.800 0.000 11.214
12 1.551 u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/Q u0_srio_request_gen/tdata_out_49_s0/D srio_clk:[R] srio_clk:[R] 12.800 0.000 11.214
13 1.585 u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/Q u0_srio_response_gen/tdata_out_57_s0/D srio_clk:[R] srio_clk:[R] 12.800 0.000 11.180
14 1.587 u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/Q u0_srio_request_gen/tdata_out_51_s0/D srio_clk:[R] srio_clk:[R] 12.800 0.000 11.178
15 1.587 u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/Q u0_srio_request_gen/tdata_out_59_s0/D srio_clk:[R] srio_clk:[R] 12.800 0.000 11.178
16 1.607 u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/Q u0_srio_response_gen/tdata_out_51_s0/D srio_clk:[R] srio_clk:[R] 12.800 0.000 11.158
17 1.611 u0_srio_response_gen/fifo_nafull_2d_s0/Q u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/rx_port_data_8_s0/D srio_clk:[R] srio_clk:[R] 12.800 0.000 11.154
18 1.717 u0_srio_response_gen/state_1_s0/Q u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/single_beat_s0/CE srio_clk:[R] srio_clk:[R] 12.800 0.000 11.048
19 1.727 u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/u_sdpram_dat/mem_data_mem_data_0_3_s/DO[10] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/pri_fifo_array[0].u_pri_fifo/ram_full_int_s4/D srio_clk:[R] srio_clk:[R] 12.800 0.000 11.038
20 1.742 u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/Q u0_srio_request_gen/tdata_out_35_s0/D srio_clk:[R] srio_clk:[R] 12.800 0.000 11.023
21 1.803 u0_srio_response_gen/state_1_s0/Q u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/first_beat_mask_s1/D srio_clk:[R] srio_clk:[R] 12.800 0.000 10.962
22 1.818 u0_srio_response_gen/state_1_s0/Q u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/port_pend_s_beat_1_s1/D srio_clk:[R] srio_clk:[R] 12.800 0.000 10.947
23 1.828 u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/Q u0_srio_request_gen/tdata_out_7_s0/D srio_clk:[R] srio_clk:[R] 12.800 0.000 10.937
24 1.828 u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/Q u0_srio_request_gen/tdata_out_15_s0/D srio_clk:[R] srio_clk:[R] 12.800 0.000 10.937
25 1.845 u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/Q u0_srio_request_gen/tdata_out_63_s0/D srio_clk:[R] srio_clk:[R] 12.800 0.000 10.920

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.071 u0_srio_response_gen/fifo_wdata_64_s0/Q u0_srio_response_gen/u_fifo_top/fifo_sc_inst/mem_mem_0_2_s/DI[0] srio_clk:[R] srio_clk:[R] 0.000 0.000 0.320
2 0.071 u0_srio_response_gen/fifo_wdata_21_s0/Q u0_srio_response_gen/u_fifo_top/fifo_sc_inst/mem_mem_0_0_s/DI[21] srio_clk:[R] srio_clk:[R] 0.000 0.000 0.320
3 0.071 u0_srio_response_gen/fifo_wdata_15_s0/Q u0_srio_response_gen/u_fifo_top/fifo_sc_inst/mem_mem_0_0_s/DI[15] srio_clk:[R] srio_clk:[R] 0.000 0.000 0.320
4 0.071 u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo1_wdata_48_s0/Q u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u1_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/DI[0] srio_clk:[R] srio_clk:[R] 0.000 0.000 0.320
5 0.071 u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo1_wdata_5_s0/Q u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u1_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s/DI[5] srio_clk:[R] srio_clk:[R] 0.000 0.000 0.320
6 0.071 u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo1_wdata_0_s0/Q u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u1_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s/DI[0] srio_clk:[R] srio_clk:[R] 0.000 0.000 0.320
7 0.071 u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo0_wdata_49_s0/Q u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u0_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/DI[4] srio_clk:[R] srio_clk:[R] 0.000 0.000 0.320
8 0.071 u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo0_wdata_48_s0/Q u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u0_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/DI[3] srio_clk:[R] srio_clk:[R] 0.000 0.000 0.320
9 0.071 u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo0_wdata_5_s0/Q u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u0_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s/DI[5] srio_clk:[R] srio_clk:[R] 0.000 0.000 0.320
10 0.071 u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_rx_buf/phy_rx_data_r_0_s0/Q u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_rx_buf/u_rx_data_fifo/mem_data_mem_data_0_0_s/DI[0] srio_clk:[R] srio_clk:[R] 0.000 0.000 0.320
11 0.078 u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo1_wdata_58_s0/Q u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u1_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/DI[6] srio_clk:[R] srio_clk:[R] 0.000 0.000 0.327
12 0.078 u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo1_wdata_51_s0/Q u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u1_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/DI[3] srio_clk:[R] srio_clk:[R] 0.000 0.000 0.327
13 0.078 u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo1_wdata_49_s0/Q u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u1_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/DI[1] srio_clk:[R] srio_clk:[R] 0.000 0.000 0.327
14 0.078 u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_rx_buf/phy_rx_data_r_23_s0/Q u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_rx_buf/u_rx_data_fifo/mem_data_mem_data_0_1_s/DI[5] srio_clk:[R] srio_clk:[R] 0.000 0.000 0.327
15 0.078 u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_rx_buf/phy_rx_data_r_2_s0/Q u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_rx_buf/u_rx_data_fifo/mem_data_mem_data_0_0_s/DI[2] srio_clk:[R] srio_clk:[R] 0.000 0.000 0.327
16 0.201 u0_srio_response_gen/rx_req_din_87_s0/Q u0_srio_response_gen/u0_sdpram_dat/mem_data_mem_data_0_2_s/DI[15] srio_clk:[R] srio_clk:[R] 0.000 0.000 0.450
17 0.201 u0_srio_response_gen/rx_req_din_45_s0/Q u0_srio_response_gen/u0_sdpram_dat/mem_data_mem_data_0_1_s/DI[13] srio_clk:[R] srio_clk:[R] 0.000 0.000 0.450
18 0.201 u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo1_wdata_24_s0/Q u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u1_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s/DI[24] srio_clk:[R] srio_clk:[R] 0.000 0.000 0.450
19 0.201 u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo1_wdata_4_s0/Q u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u1_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s/DI[4] srio_clk:[R] srio_clk:[R] 0.000 0.000 0.450
20 0.201 u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo0_wdata_24_s0/Q u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u0_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s/DI[24] srio_clk:[R] srio_clk:[R] 0.000 0.000 0.450
21 0.201 u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo0_wdata_4_s0/Q u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u0_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s/DI[4] srio_clk:[R] srio_clk:[R] 0.000 0.000 0.450
22 0.201 u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_resp_maints/o_tx_maint_resp_trac_fifo_wdata_54_s0/Q u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_tx_maints/u1_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s/DI[22] cfg_clk:[R] cfg_clk:[R] 0.000 0.000 0.450
23 0.201 u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_resp_maints/o_tx_maint_resp_trac_fifo_wdata_12_s0/Q u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_tx_maints/u1_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s/DI[12] cfg_clk:[R] cfg_clk:[R] 0.000 0.000 0.450
24 0.203 u0_srio_response_gen/fifo_wdata_7_s0/Q u0_srio_response_gen/u_fifo_top/fifo_sc_inst/mem_mem_0_0_s/DI[7] srio_clk:[R] srio_clk:[R] 0.000 0.000 0.452
25 0.203 u0_srio_response_gen/fifo_wdata_6_s0/Q u0_srio_response_gen/u_fifo_top/fifo_sc_inst/mem_mem_0_0_s/DI[6] srio_clk:[R] srio_clk:[R] 0.000 0.000 0.452

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 10.154 u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q u0_srio_response_gen/u_fifo_top/fifo_sc_inst/mem_mem_0_2_s/RESET srio_clk:[R] srio_clk:[R] 12.800 0.000 2.208
2 10.154 u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q u0_srio_response_gen/u_fifo_top/fifo_sc_inst/mem_mem_0_0_s/RESET srio_clk:[R] srio_clk:[R] 12.800 0.000 2.208
3 10.154 u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q u0_srio_request_gen/u_fifo_top/fifo_sc_inst/mem_mem_0_0_s/RESET srio_clk:[R] srio_clk:[R] 12.800 0.000 2.208
4 10.544 u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_6_s0/CLEAR srio_clk:[R] srio_clk:[R] 12.800 0.000 2.221
5 10.544 u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_7_s0/CLEAR srio_clk:[R] srio_clk:[R] 12.800 0.000 2.221
6 10.544 u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_8_s0/CLEAR srio_clk:[R] srio_clk:[R] 12.800 0.000 2.221
7 10.544 u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_4_s0/CLEAR srio_clk:[R] srio_clk:[R] 12.800 0.000 2.221
8 10.544 u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_5_s0/CLEAR srio_clk:[R] srio_clk:[R] 12.800 0.000 2.221
9 10.544 u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_6_s0/CLEAR srio_clk:[R] srio_clk:[R] 12.800 0.000 2.221
10 10.544 u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_7_s0/CLEAR srio_clk:[R] srio_clk:[R] 12.800 0.000 2.221
11 10.544 u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_8_s0/CLEAR srio_clk:[R] srio_clk:[R] 12.800 0.000 2.221
12 10.544 u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q u0_srio_request_gen/u_fifo_top/fifo_sc_inst/wbin_2_s0/CLEAR srio_clk:[R] srio_clk:[R] 12.800 0.000 2.221
13 10.544 u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q u0_srio_request_gen/u_fifo_top/fifo_sc_inst/wbin_3_s0/CLEAR srio_clk:[R] srio_clk:[R] 12.800 0.000 2.221
14 10.544 u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q u0_srio_request_gen/u_fifo_top/fifo_sc_inst/wbin_4_s0/CLEAR srio_clk:[R] srio_clk:[R] 12.800 0.000 2.221
15 10.544 u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q u0_srio_request_gen/u_fifo_top/fifo_sc_inst/wbin_5_s0/CLEAR srio_clk:[R] srio_clk:[R] 12.800 0.000 2.221
16 10.544 u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q u0_srio_request_gen/u_fifo_top/fifo_sc_inst/wbin_6_s0/CLEAR srio_clk:[R] srio_clk:[R] 12.800 0.000 2.221
17 10.544 u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q u0_srio_request_gen/u_fifo_top/fifo_sc_inst/wbin_7_s0/CLEAR srio_clk:[R] srio_clk:[R] 12.800 0.000 2.221
18 10.544 u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q u0_srio_request_gen/u_fifo_top/fifo_sc_inst/wbin_9_s0/CLEAR srio_clk:[R] srio_clk:[R] 12.800 0.000 2.221
19 10.544 u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q u0_srio_request_gen/u_fifo_top/fifo_sc_inst/rbin_2_s0/CLEAR srio_clk:[R] srio_clk:[R] 12.800 0.000 2.221
20 10.550 u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_0_s0/CLEAR srio_clk:[R] srio_clk:[R] 12.800 0.000 2.215
21 10.550 u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_1_s0/CLEAR srio_clk:[R] srio_clk:[R] 12.800 0.000 2.215
22 10.550 u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_3_s0/CLEAR srio_clk:[R] srio_clk:[R] 12.800 0.000 2.215
23 10.550 u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_4_s0/CLEAR srio_clk:[R] srio_clk:[R] 12.800 0.000 2.215
24 10.550 u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_0_s0/CLEAR srio_clk:[R] srio_clk:[R] 12.800 0.000 2.215
25 10.550 u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_1_s0/CLEAR srio_clk:[R] srio_clk:[R] 12.800 0.000 2.215

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 1.506 u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q u0_srio_response_gen/u_fifo_top/fifo_sc_inst/mem_mem_0_2_s/RESET srio_clk:[R] srio_clk:[R] 0.000 0.000 1.518
2 1.506 u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q u0_srio_response_gen/u_fifo_top/fifo_sc_inst/mem_mem_0_0_s/RESET srio_clk:[R] srio_clk:[R] 0.000 0.000 1.518
3 1.506 u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q u0_srio_request_gen/u_fifo_top/fifo_sc_inst/mem_mem_0_0_s/RESET srio_clk:[R] srio_clk:[R] 0.000 0.000 1.518
4 1.507 u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q u0_srio_response_gen/u_fifo_top/fifo_sc_inst/Empty_s0/PRESET srio_clk:[R] srio_clk:[R] 0.000 0.000 1.518
5 1.507 u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q u0_srio_response_gen/u_fifo_top/fifo_sc_inst/Almost_Full_s0/CLEAR srio_clk:[R] srio_clk:[R] 0.000 0.000 1.518
6 1.507 u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q u0_srio_response_gen/u_fifo_top/fifo_sc_inst/Full_s0/CLEAR srio_clk:[R] srio_clk:[R] 0.000 0.000 1.518
7 1.507 u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_2_s0/CLEAR srio_clk:[R] srio_clk:[R] 0.000 0.000 1.518
8 1.507 u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_5_s0/CLEAR srio_clk:[R] srio_clk:[R] 0.000 0.000 1.518
9 1.507 u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_9_s0/CLEAR srio_clk:[R] srio_clk:[R] 0.000 0.000 1.518
10 1.507 u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_2_s0/CLEAR srio_clk:[R] srio_clk:[R] 0.000 0.000 1.518
11 1.507 u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_9_s0/CLEAR srio_clk:[R] srio_clk:[R] 0.000 0.000 1.518
12 1.507 u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q u0_srio_request_gen/u_fifo_top/fifo_sc_inst/Empty_s0/PRESET srio_clk:[R] srio_clk:[R] 0.000 0.000 1.518
13 1.507 u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q u0_srio_request_gen/u_fifo_top/fifo_sc_inst/Almost_Full_s0/CLEAR srio_clk:[R] srio_clk:[R] 0.000 0.000 1.518
14 1.507 u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q u0_srio_request_gen/u_fifo_top/fifo_sc_inst/Full_s0/CLEAR srio_clk:[R] srio_clk:[R] 0.000 0.000 1.518
15 1.507 u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q u0_srio_request_gen/u_fifo_top/fifo_sc_inst/wbin_8_s0/CLEAR srio_clk:[R] srio_clk:[R] 0.000 0.000 1.518
16 1.507 u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q u0_srio_request_gen/u_fifo_top/fifo_sc_inst/rbin_0_s0/CLEAR srio_clk:[R] srio_clk:[R] 0.000 0.000 1.518
17 1.507 u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q u0_srio_request_gen/u_fifo_top/fifo_sc_inst/rbin_1_s0/CLEAR srio_clk:[R] srio_clk:[R] 0.000 0.000 1.518
18 1.507 u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q u0_srio_request_gen/u_fifo_top/fifo_sc_inst/rbin_4_s0/CLEAR srio_clk:[R] srio_clk:[R] 0.000 0.000 1.518
19 1.507 u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q u0_srio_request_gen/u_fifo_top/fifo_sc_inst/rbin_5_s0/CLEAR srio_clk:[R] srio_clk:[R] 0.000 0.000 1.518
20 1.507 u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q u0_srio_request_gen/u_fifo_top/fifo_sc_inst/rbin_6_s0/CLEAR srio_clk:[R] srio_clk:[R] 0.000 0.000 1.518
21 1.507 u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q u0_srio_request_gen/u_fifo_top/fifo_sc_inst/rbin_9_s0/CLEAR srio_clk:[R] srio_clk:[R] 0.000 0.000 1.518
22 1.512 u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_0_s0/CLEAR srio_clk:[R] srio_clk:[R] 0.000 0.000 1.523
23 1.512 u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_1_s0/CLEAR srio_clk:[R] srio_clk:[R] 0.000 0.000 1.523
24 1.512 u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_3_s0/CLEAR srio_clk:[R] srio_clk:[R] 0.000 0.000 1.523
25 1.512 u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_4_s0/CLEAR srio_clk:[R] srio_clk:[R] 0.000 0.000 1.523

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number Slack Actual Width Required Width Type Clock Objects
1 5.323 6.323 1.000 Low Pulse Width srio_clk test_start_1d_s1
2 5.323 6.323 1.000 Low Pulse Width srio_clk test_start_2d_s1
3 5.323 6.323 1.000 Low Pulse Width srio_clk sw_start_1d_s0
4 5.323 6.323 1.000 Low Pulse Width srio_clk u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/stage1_reg[0]_8_s0
5 5.323 6.323 1.000 Low Pulse Width srio_clk u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/stage1_reg[2]_42_s0
6 5.323 6.323 1.000 Low Pulse Width srio_clk u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/stage1_reg[3]_59_s0
7 5.323 6.323 1.000 Low Pulse Width srio_clk u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/stage1_reg[3]_27_s0
8 5.323 6.323 1.000 Low Pulse Width srio_clk u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/stage1_reg[3]_11_s0
9 5.323 6.323 1.000 Low Pulse Width srio_clk u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/stage1_reg[3]_3_s0
10 5.323 6.323 1.000 Low Pulse Width srio_clk u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/stage1_reg_last_3_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 1.105
Data Arrival Time 14.903
Data Required Time 16.008
From u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1
To u0_srio_response_gen/tdata_out_59_s0
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.243 3.243 tNET RR 1 R75C138[0][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/CLK
3.475 0.232 tC2Q RF 5 R75C138[0][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/Q
4.133 0.657 tNET FF 1 R75C128[1][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/pipe_tx_ready_s1/I0
4.586 0.453 tINS FF 24 R75C128[1][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/pipe_tx_ready_s1/F
5.210 0.624 tNET FF 1 R74C127[3][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_resp_trac_ready_o_d_s0/I2
5.780 0.570 tINS FR 1 R74C127[3][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_resp_trac_ready_o_d_s0/F
5.926 0.146 tNET RR 1 R74C127[3][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_resp_trac_ready_o_d_s/I2
6.379 0.453 tINS RF 7 R74C127[3][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_resp_trac_ready_o_d_s/F
10.264 3.885 tNET FF 1 R60C53[3][A] u0_srio_response_gen/n1809_s0/I3
10.635 0.371 tINS FF 19 R60C53[3][A] u0_srio_response_gen/n1809_s0/F
12.587 1.952 tNET FF 1 R72C54[1][B] u0_srio_response_gen/increase_data_3_s0/I2
13.142 0.555 tINS FF 3 R72C54[1][B] u0_srio_response_gen/increase_data_3_s0/F
14.333 1.192 tNET FF 1 R60C53[2][A] u0_srio_response_gen/n1681_s0/I0
14.903 0.570 tINS FR 1 R60C53[2][A] u0_srio_response_gen/n1681_s0/F
14.903 0.000 tNET RR 1 R60C53[2][A] u0_srio_response_gen/tdata_out_59_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.800 12.800 active clock edge time
12.800 0.000 srio_clk
12.800 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.043 3.243 tNET RR 1 R60C53[2][A] u0_srio_response_gen/tdata_out_59_s0/CLK
16.008 -0.035 tSu 1 R60C53[2][A] u0_srio_response_gen/tdata_out_59_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.800
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 2.972, 25.489%; route: 8.456, 72.521%; tC2Q: 0.232, 1.990%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path2

Path Summary:

Slack 1.316
Data Arrival Time 14.692
Data Required Time 16.008
From u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1
To u0_srio_request_gen/tdata_out_55_s0
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.243 3.243 tNET RR 1 R75C138[0][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/CLK
3.475 0.232 tC2Q RF 5 R75C138[0][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/Q
4.133 0.657 tNET FF 1 R75C128[1][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/pipe_tx_ready_s1/I0
4.586 0.453 tINS FF 24 R75C128[1][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/pipe_tx_ready_s1/F
5.258 0.673 tNET FF 1 R72C126[3][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s0/I2
5.629 0.371 tINS FF 1 R72C126[3][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s0/F
5.634 0.004 tNET FF 1 R72C126[3][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s/I2
6.151 0.517 tINS FF 8 R72C126[3][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s/F
9.731 3.580 tNET FF 1 R54C59[1][B] u0_srio_request_gen/n32793_s1/I2
10.286 0.555 tINS FF 9 R54C59[1][B] u0_srio_request_gen/n32793_s1/F
11.282 0.997 tNET FF 1 R69C58[0][A] u0_srio_request_gen/n32793_s0/I0
11.799 0.517 tINS FF 18 R69C58[0][A] u0_srio_request_gen/n32793_s0/F
12.080 0.280 tNET FF 1 R67C58[0][B] u0_srio_request_gen/n33670_s2/I3
12.451 0.371 tINS FF 8 R67C58[0][B] u0_srio_request_gen/n33670_s2/F
14.122 1.672 tNET FF 1 R57C56[2][A] u0_srio_request_gen/n33678_s0/I2
14.692 0.570 tINS FR 1 R57C56[2][A] u0_srio_request_gen/n33678_s0/F
14.692 0.000 tNET RR 1 R57C56[2][A] u0_srio_request_gen/tdata_out_55_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.800 12.800 active clock edge time
12.800 0.000 srio_clk
12.800 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.043 3.243 tNET RR 1 R57C56[2][A] u0_srio_request_gen/tdata_out_55_s0/CLK
16.008 -0.035 tSu 1 R57C56[2][A] u0_srio_request_gen/tdata_out_55_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.800
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 3.354, 29.295%; route: 7.863, 68.679%; tC2Q: 0.232, 2.026%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path3

Path Summary:

Slack 1.331
Data Arrival Time 14.678
Data Required Time 16.008
From u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1
To u0_srio_request_gen/tdata_out_27_s0
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.243 3.243 tNET RR 1 R75C138[0][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/CLK
3.475 0.232 tC2Q RF 5 R75C138[0][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/Q
4.133 0.657 tNET FF 1 R75C128[1][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/pipe_tx_ready_s1/I0
4.586 0.453 tINS FF 24 R75C128[1][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/pipe_tx_ready_s1/F
5.258 0.673 tNET FF 1 R72C126[3][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s0/I2
5.629 0.371 tINS FF 1 R72C126[3][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s0/F
5.634 0.004 tNET FF 1 R72C126[3][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s/I2
6.151 0.517 tINS FF 8 R72C126[3][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s/F
9.731 3.580 tNET FF 1 R54C59[1][B] u0_srio_request_gen/n32793_s1/I2
10.286 0.555 tINS FF 9 R54C59[1][B] u0_srio_request_gen/n32793_s1/F
11.282 0.997 tNET FF 1 R69C58[0][A] u0_srio_request_gen/n32793_s0/I0
11.799 0.517 tINS FF 18 R69C58[0][A] u0_srio_request_gen/n32793_s0/F
12.516 0.716 tNET FF 1 R63C57[3][A] u0_srio_request_gen/n33674_s2/I3
13.033 0.517 tINS FF 8 R63C57[3][A] u0_srio_request_gen/n33674_s2/F
14.108 1.075 tNET FF 1 R60C58[0][A] u0_srio_request_gen/n33706_s0/I3
14.678 0.570 tINS FR 1 R60C58[0][A] u0_srio_request_gen/n33706_s0/F
14.678 0.000 tNET RR 1 R60C58[0][A] u0_srio_request_gen/tdata_out_27_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.800 12.800 active clock edge time
12.800 0.000 srio_clk
12.800 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.043 3.243 tNET RR 1 R60C58[0][A] u0_srio_request_gen/tdata_out_27_s0/CLK
16.008 -0.035 tSu 1 R60C58[0][A] u0_srio_request_gen/tdata_out_27_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.800
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 3.500, 30.610%; route: 7.702, 67.361%; tC2Q: 0.232, 2.029%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path4

Path Summary:

Slack 1.337
Data Arrival Time 14.671
Data Required Time 16.008
From u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1
To u0_srio_request_gen/tdata_out_47_s0
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.243 3.243 tNET RR 1 R75C138[0][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/CLK
3.475 0.232 tC2Q RF 5 R75C138[0][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/Q
4.133 0.657 tNET FF 1 R75C128[1][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/pipe_tx_ready_s1/I0
4.586 0.453 tINS FF 24 R75C128[1][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/pipe_tx_ready_s1/F
5.258 0.673 tNET FF 1 R72C126[3][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s0/I2
5.629 0.371 tINS FF 1 R72C126[3][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s0/F
5.634 0.004 tNET FF 1 R72C126[3][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s/I2
6.151 0.517 tINS FF 8 R72C126[3][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s/F
9.731 3.580 tNET FF 1 R54C59[1][B] u0_srio_request_gen/n32793_s1/I2
10.286 0.555 tINS FF 9 R54C59[1][B] u0_srio_request_gen/n32793_s1/F
11.282 0.997 tNET FF 1 R69C58[0][A] u0_srio_request_gen/n32793_s0/I0
11.799 0.517 tINS FF 18 R69C58[0][A] u0_srio_request_gen/n32793_s0/F
12.080 0.280 tNET FF 1 R67C58[0][B] u0_srio_request_gen/n33670_s2/I3
12.451 0.371 tINS FF 8 R67C58[0][B] u0_srio_request_gen/n33670_s2/F
14.122 1.672 tNET FF 1 R57C56[1][B] u0_srio_request_gen/n33686_s0/I2
14.671 0.549 tINS FR 1 R57C56[1][B] u0_srio_request_gen/n33686_s0/F
14.671 0.000 tNET RR 1 R57C56[1][B] u0_srio_request_gen/tdata_out_47_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.800 12.800 active clock edge time
12.800 0.000 srio_clk
12.800 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.043 3.243 tNET RR 1 R57C56[1][B] u0_srio_request_gen/tdata_out_47_s0/CLK
16.008 -0.035 tSu 1 R57C56[1][B] u0_srio_request_gen/tdata_out_47_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.800
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 3.333, 29.165%; route: 7.863, 68.805%; tC2Q: 0.232, 2.030%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path5

Path Summary:

Slack 1.390
Data Arrival Time 14.619
Data Required Time 16.008
From u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1
To u0_srio_request_gen/tdata_out_17_s0
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.243 3.243 tNET RR 1 R75C138[0][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/CLK
3.475 0.232 tC2Q RF 5 R75C138[0][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/Q
4.133 0.657 tNET FF 1 R75C128[1][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/pipe_tx_ready_s1/I0
4.586 0.453 tINS FF 24 R75C128[1][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/pipe_tx_ready_s1/F
5.258 0.673 tNET FF 1 R72C126[3][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s0/I2
5.629 0.371 tINS FF 1 R72C126[3][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s0/F
5.634 0.004 tNET FF 1 R72C126[3][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s/I2
6.151 0.517 tINS FF 8 R72C126[3][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s/F
9.731 3.580 tNET FF 1 R54C59[1][B] u0_srio_request_gen/n32793_s1/I2
10.286 0.555 tINS FF 9 R54C59[1][B] u0_srio_request_gen/n32793_s1/F
11.282 0.997 tNET FF 1 R69C58[0][A] u0_srio_request_gen/n32793_s0/I0
11.799 0.517 tINS FF 18 R69C58[0][A] u0_srio_request_gen/n32793_s0/F
13.025 1.225 tNET FF 1 R63C57[3][B] u0_srio_request_gen/n33676_s1/I3
13.478 0.453 tINS FF 8 R63C57[3][B] u0_srio_request_gen/n33676_s1/F
14.070 0.592 tNET FF 1 R61C57[2][A] u0_srio_request_gen/n33716_s0/I2
14.619 0.549 tINS FR 1 R61C57[2][A] u0_srio_request_gen/n33716_s0/F
14.619 0.000 tNET RR 1 R61C57[2][A] u0_srio_request_gen/tdata_out_17_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.800 12.800 active clock edge time
12.800 0.000 srio_clk
12.800 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.043 3.243 tNET RR 1 R61C57[2][A] u0_srio_request_gen/tdata_out_17_s0/CLK
16.008 -0.035 tSu 1 R61C57[2][A] u0_srio_request_gen/tdata_out_17_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.800
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 3.415, 30.021%; route: 7.728, 67.940%; tC2Q: 0.232, 2.039%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path6

Path Summary:

Slack 1.390
Data Arrival Time 14.619
Data Required Time 16.008
From u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1
To u0_srio_request_gen/tdata_out_25_s0
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.243 3.243 tNET RR 1 R75C138[0][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/CLK
3.475 0.232 tC2Q RF 5 R75C138[0][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/Q
4.133 0.657 tNET FF 1 R75C128[1][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/pipe_tx_ready_s1/I0
4.586 0.453 tINS FF 24 R75C128[1][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/pipe_tx_ready_s1/F
5.258 0.673 tNET FF 1 R72C126[3][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s0/I2
5.629 0.371 tINS FF 1 R72C126[3][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s0/F
5.634 0.004 tNET FF 1 R72C126[3][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s/I2
6.151 0.517 tINS FF 8 R72C126[3][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s/F
9.731 3.580 tNET FF 1 R54C59[1][B] u0_srio_request_gen/n32793_s1/I2
10.286 0.555 tINS FF 9 R54C59[1][B] u0_srio_request_gen/n32793_s1/F
11.282 0.997 tNET FF 1 R69C58[0][A] u0_srio_request_gen/n32793_s0/I0
11.799 0.517 tINS FF 18 R69C58[0][A] u0_srio_request_gen/n32793_s0/F
13.025 1.225 tNET FF 1 R63C57[3][B] u0_srio_request_gen/n33676_s1/I3
13.478 0.453 tINS FF 8 R63C57[3][B] u0_srio_request_gen/n33676_s1/F
14.070 0.592 tNET FF 1 R61C57[2][B] u0_srio_request_gen/n33708_s0/I2
14.619 0.549 tINS FR 1 R61C57[2][B] u0_srio_request_gen/n33708_s0/F
14.619 0.000 tNET RR 1 R61C57[2][B] u0_srio_request_gen/tdata_out_25_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.800 12.800 active clock edge time
12.800 0.000 srio_clk
12.800 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.043 3.243 tNET RR 1 R61C57[2][B] u0_srio_request_gen/tdata_out_25_s0/CLK
16.008 -0.035 tSu 1 R61C57[2][B] u0_srio_request_gen/tdata_out_25_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.800
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 3.415, 30.021%; route: 7.728, 67.940%; tC2Q: 0.232, 2.039%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path7

Path Summary:

Slack 1.390
Data Arrival Time 14.619
Data Required Time 16.008
From u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1
To u0_srio_request_gen/tdata_out_33_s0
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.243 3.243 tNET RR 1 R75C138[0][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/CLK
3.475 0.232 tC2Q RF 5 R75C138[0][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/Q
4.133 0.657 tNET FF 1 R75C128[1][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/pipe_tx_ready_s1/I0
4.586 0.453 tINS FF 24 R75C128[1][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/pipe_tx_ready_s1/F
5.258 0.673 tNET FF 1 R72C126[3][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s0/I2
5.629 0.371 tINS FF 1 R72C126[3][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s0/F
5.634 0.004 tNET FF 1 R72C126[3][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s/I2
6.151 0.517 tINS FF 8 R72C126[3][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s/F
9.731 3.580 tNET FF 1 R54C59[1][B] u0_srio_request_gen/n32793_s1/I2
10.286 0.555 tINS FF 9 R54C59[1][B] u0_srio_request_gen/n32793_s1/F
11.282 0.997 tNET FF 1 R69C58[0][A] u0_srio_request_gen/n32793_s0/I0
11.799 0.517 tINS FF 18 R69C58[0][A] u0_srio_request_gen/n32793_s0/F
13.025 1.225 tNET FF 1 R63C57[3][B] u0_srio_request_gen/n33676_s1/I3
13.478 0.453 tINS FF 8 R63C57[3][B] u0_srio_request_gen/n33676_s1/F
14.070 0.592 tNET FF 1 R61C57[3][A] u0_srio_request_gen/n33700_s0/I2
14.619 0.549 tINS FR 1 R61C57[3][A] u0_srio_request_gen/n33700_s0/F
14.619 0.000 tNET RR 1 R61C57[3][A] u0_srio_request_gen/tdata_out_33_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.800 12.800 active clock edge time
12.800 0.000 srio_clk
12.800 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.043 3.243 tNET RR 1 R61C57[3][A] u0_srio_request_gen/tdata_out_33_s0/CLK
16.008 -0.035 tSu 1 R61C57[3][A] u0_srio_request_gen/tdata_out_33_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.800
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 3.415, 30.021%; route: 7.728, 67.940%; tC2Q: 0.232, 2.039%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path8

Path Summary:

Slack 1.530
Data Arrival Time 14.479
Data Required Time 16.008
From u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1
To u0_srio_request_gen/tdata_out_57_s0
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.243 3.243 tNET RR 1 R75C138[0][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/CLK
3.475 0.232 tC2Q RF 5 R75C138[0][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/Q
4.133 0.657 tNET FF 1 R75C128[1][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/pipe_tx_ready_s1/I0
4.586 0.453 tINS FF 24 R75C128[1][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/pipe_tx_ready_s1/F
5.258 0.673 tNET FF 1 R72C126[3][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s0/I2
5.629 0.371 tINS FF 1 R72C126[3][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s0/F
5.634 0.004 tNET FF 1 R72C126[3][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s/I2
6.151 0.517 tINS FF 8 R72C126[3][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s/F
9.731 3.580 tNET FF 1 R54C59[1][B] u0_srio_request_gen/n32793_s1/I2
10.286 0.555 tINS FF 9 R54C59[1][B] u0_srio_request_gen/n32793_s1/F
11.282 0.997 tNET FF 1 R69C58[0][A] u0_srio_request_gen/n32793_s0/I0
11.799 0.517 tINS FF 18 R69C58[0][A] u0_srio_request_gen/n32793_s0/F
13.025 1.225 tNET FF 1 R63C57[3][B] u0_srio_request_gen/n33676_s1/I3
13.478 0.453 tINS FF 8 R63C57[3][B] u0_srio_request_gen/n33676_s1/F
13.909 0.431 tNET FF 1 R60C57[2][A] u0_srio_request_gen/n33676_s0/I2
14.479 0.570 tINS FR 1 R60C57[2][A] u0_srio_request_gen/n33676_s0/F
14.479 0.000 tNET RR 1 R60C57[2][A] u0_srio_request_gen/tdata_out_57_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.800 12.800 active clock edge time
12.800 0.000 srio_clk
12.800 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.043 3.243 tNET RR 1 R60C57[2][A] u0_srio_request_gen/tdata_out_57_s0/CLK
16.008 -0.035 tSu 1 R60C57[2][A] u0_srio_request_gen/tdata_out_57_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.800
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 3.436, 30.582%; route: 7.567, 67.353%; tC2Q: 0.232, 2.065%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path9

Path Summary:

Slack 1.551
Data Arrival Time 14.458
Data Required Time 16.008
From u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1
To u0_srio_request_gen/tdata_out_1_s0
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.243 3.243 tNET RR 1 R75C138[0][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/CLK
3.475 0.232 tC2Q RF 5 R75C138[0][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/Q
4.133 0.657 tNET FF 1 R75C128[1][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/pipe_tx_ready_s1/I0
4.586 0.453 tINS FF 24 R75C128[1][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/pipe_tx_ready_s1/F
5.258 0.673 tNET FF 1 R72C126[3][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s0/I2
5.629 0.371 tINS FF 1 R72C126[3][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s0/F
5.634 0.004 tNET FF 1 R72C126[3][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s/I2
6.151 0.517 tINS FF 8 R72C126[3][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s/F
9.731 3.580 tNET FF 1 R54C59[1][B] u0_srio_request_gen/n32793_s1/I2
10.286 0.555 tINS FF 9 R54C59[1][B] u0_srio_request_gen/n32793_s1/F
11.282 0.997 tNET FF 1 R69C58[0][A] u0_srio_request_gen/n32793_s0/I0
11.799 0.517 tINS FF 18 R69C58[0][A] u0_srio_request_gen/n32793_s0/F
13.025 1.225 tNET FF 1 R63C57[3][B] u0_srio_request_gen/n33676_s1/I3
13.478 0.453 tINS FF 8 R63C57[3][B] u0_srio_request_gen/n33676_s1/F
13.909 0.431 tNET FF 1 R61C57[1][A] u0_srio_request_gen/n33732_s0/I2
14.458 0.549 tINS FR 1 R61C57[1][A] u0_srio_request_gen/n33732_s0/F
14.458 0.000 tNET RR 1 R61C57[1][A] u0_srio_request_gen/tdata_out_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.800 12.800 active clock edge time
12.800 0.000 srio_clk
12.800 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.043 3.243 tNET RR 1 R61C57[1][A] u0_srio_request_gen/tdata_out_1_s0/CLK
16.008 -0.035 tSu 1 R61C57[1][A] u0_srio_request_gen/tdata_out_1_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.800
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 3.415, 30.452%; route: 7.567, 67.479%; tC2Q: 0.232, 2.069%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path10

Path Summary:

Slack 1.551
Data Arrival Time 14.458
Data Required Time 16.008
From u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1
To u0_srio_request_gen/tdata_out_9_s0
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.243 3.243 tNET RR 1 R75C138[0][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/CLK
3.475 0.232 tC2Q RF 5 R75C138[0][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/Q
4.133 0.657 tNET FF 1 R75C128[1][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/pipe_tx_ready_s1/I0
4.586 0.453 tINS FF 24 R75C128[1][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/pipe_tx_ready_s1/F
5.258 0.673 tNET FF 1 R72C126[3][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s0/I2
5.629 0.371 tINS FF 1 R72C126[3][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s0/F
5.634 0.004 tNET FF 1 R72C126[3][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s/I2
6.151 0.517 tINS FF 8 R72C126[3][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s/F
9.731 3.580 tNET FF 1 R54C59[1][B] u0_srio_request_gen/n32793_s1/I2
10.286 0.555 tINS FF 9 R54C59[1][B] u0_srio_request_gen/n32793_s1/F
11.282 0.997 tNET FF 1 R69C58[0][A] u0_srio_request_gen/n32793_s0/I0
11.799 0.517 tINS FF 18 R69C58[0][A] u0_srio_request_gen/n32793_s0/F
13.025 1.225 tNET FF 1 R63C57[3][B] u0_srio_request_gen/n33676_s1/I3
13.478 0.453 tINS FF 8 R63C57[3][B] u0_srio_request_gen/n33676_s1/F
13.909 0.431 tNET FF 1 R61C57[1][B] u0_srio_request_gen/n33724_s0/I2
14.458 0.549 tINS FR 1 R61C57[1][B] u0_srio_request_gen/n33724_s0/F
14.458 0.000 tNET RR 1 R61C57[1][B] u0_srio_request_gen/tdata_out_9_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.800 12.800 active clock edge time
12.800 0.000 srio_clk
12.800 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.043 3.243 tNET RR 1 R61C57[1][B] u0_srio_request_gen/tdata_out_9_s0/CLK
16.008 -0.035 tSu 1 R61C57[1][B] u0_srio_request_gen/tdata_out_9_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.800
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 3.415, 30.452%; route: 7.567, 67.479%; tC2Q: 0.232, 2.069%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path11

Path Summary:

Slack 1.551
Data Arrival Time 14.458
Data Required Time 16.008
From u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1
To u0_srio_request_gen/tdata_out_41_s0
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.243 3.243 tNET RR 1 R75C138[0][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/CLK
3.475 0.232 tC2Q RF 5 R75C138[0][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/Q
4.133 0.657 tNET FF 1 R75C128[1][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/pipe_tx_ready_s1/I0
4.586 0.453 tINS FF 24 R75C128[1][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/pipe_tx_ready_s1/F
5.258 0.673 tNET FF 1 R72C126[3][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s0/I2
5.629 0.371 tINS FF 1 R72C126[3][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s0/F
5.634 0.004 tNET FF 1 R72C126[3][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s/I2
6.151 0.517 tINS FF 8 R72C126[3][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s/F
9.731 3.580 tNET FF 1 R54C59[1][B] u0_srio_request_gen/n32793_s1/I2
10.286 0.555 tINS FF 9 R54C59[1][B] u0_srio_request_gen/n32793_s1/F
11.282 0.997 tNET FF 1 R69C58[0][A] u0_srio_request_gen/n32793_s0/I0
11.799 0.517 tINS FF 18 R69C58[0][A] u0_srio_request_gen/n32793_s0/F
13.025 1.225 tNET FF 1 R63C57[3][B] u0_srio_request_gen/n33676_s1/I3
13.478 0.453 tINS FF 8 R63C57[3][B] u0_srio_request_gen/n33676_s1/F
13.909 0.431 tNET FF 1 R60C57[1][A] u0_srio_request_gen/n33692_s0/I2
14.458 0.549 tINS FR 1 R60C57[1][A] u0_srio_request_gen/n33692_s0/F
14.458 0.000 tNET RR 1 R60C57[1][A] u0_srio_request_gen/tdata_out_41_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.800 12.800 active clock edge time
12.800 0.000 srio_clk
12.800 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.043 3.243 tNET RR 1 R60C57[1][A] u0_srio_request_gen/tdata_out_41_s0/CLK
16.008 -0.035 tSu 1 R60C57[1][A] u0_srio_request_gen/tdata_out_41_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.800
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 3.415, 30.452%; route: 7.567, 67.479%; tC2Q: 0.232, 2.069%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path12

Path Summary:

Slack 1.551
Data Arrival Time 14.458
Data Required Time 16.008
From u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1
To u0_srio_request_gen/tdata_out_49_s0
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.243 3.243 tNET RR 1 R75C138[0][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/CLK
3.475 0.232 tC2Q RF 5 R75C138[0][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/Q
4.133 0.657 tNET FF 1 R75C128[1][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/pipe_tx_ready_s1/I0
4.586 0.453 tINS FF 24 R75C128[1][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/pipe_tx_ready_s1/F
5.258 0.673 tNET FF 1 R72C126[3][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s0/I2
5.629 0.371 tINS FF 1 R72C126[3][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s0/F
5.634 0.004 tNET FF 1 R72C126[3][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s/I2
6.151 0.517 tINS FF 8 R72C126[3][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s/F
9.731 3.580 tNET FF 1 R54C59[1][B] u0_srio_request_gen/n32793_s1/I2
10.286 0.555 tINS FF 9 R54C59[1][B] u0_srio_request_gen/n32793_s1/F
11.282 0.997 tNET FF 1 R69C58[0][A] u0_srio_request_gen/n32793_s0/I0
11.799 0.517 tINS FF 18 R69C58[0][A] u0_srio_request_gen/n32793_s0/F
13.025 1.225 tNET FF 1 R63C57[3][B] u0_srio_request_gen/n33676_s1/I3
13.478 0.453 tINS FF 8 R63C57[3][B] u0_srio_request_gen/n33676_s1/F
13.909 0.431 tNET FF 1 R60C57[1][B] u0_srio_request_gen/n33684_s0/I2
14.458 0.549 tINS FR 1 R60C57[1][B] u0_srio_request_gen/n33684_s0/F
14.458 0.000 tNET RR 1 R60C57[1][B] u0_srio_request_gen/tdata_out_49_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.800 12.800 active clock edge time
12.800 0.000 srio_clk
12.800 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.043 3.243 tNET RR 1 R60C57[1][B] u0_srio_request_gen/tdata_out_49_s0/CLK
16.008 -0.035 tSu 1 R60C57[1][B] u0_srio_request_gen/tdata_out_49_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.800
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 3.415, 30.452%; route: 7.567, 67.479%; tC2Q: 0.232, 2.069%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path13

Path Summary:

Slack 1.585
Data Arrival Time 14.424
Data Required Time 16.008
From u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1
To u0_srio_response_gen/tdata_out_57_s0
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.243 3.243 tNET RR 1 R75C138[0][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/CLK
3.475 0.232 tC2Q RF 5 R75C138[0][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/Q
4.133 0.657 tNET FF 1 R75C128[1][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/pipe_tx_ready_s1/I0
4.586 0.453 tINS FF 24 R75C128[1][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/pipe_tx_ready_s1/F
5.210 0.624 tNET FF 1 R74C127[3][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_resp_trac_ready_o_d_s0/I2
5.780 0.570 tINS FR 1 R74C127[3][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_resp_trac_ready_o_d_s0/F
5.926 0.146 tNET RR 1 R74C127[3][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_resp_trac_ready_o_d_s/I2
6.379 0.453 tINS RF 7 R74C127[3][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_resp_trac_ready_o_d_s/F
10.264 3.885 tNET FF 1 R60C53[3][A] u0_srio_response_gen/n1809_s0/I3
10.635 0.371 tINS FF 19 R60C53[3][A] u0_srio_response_gen/n1809_s0/F
12.587 1.952 tNET FF 1 R72C52[3][B] u0_srio_response_gen/increase_data_1_s0/I1
13.142 0.555 tINS FF 3 R72C52[3][B] u0_srio_response_gen/increase_data_1_s0/F
13.854 0.712 tNET FF 1 R63C53[0][A] u0_srio_response_gen/n1683_s0/I0
14.424 0.570 tINS FR 1 R63C53[0][A] u0_srio_response_gen/n1683_s0/F
14.424 0.000 tNET RR 1 R63C53[0][A] u0_srio_response_gen/tdata_out_57_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.800 12.800 active clock edge time
12.800 0.000 srio_clk
12.800 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.043 3.243 tNET RR 1 R63C53[0][A] u0_srio_response_gen/tdata_out_57_s0/CLK
16.008 -0.035 tSu 1 R63C53[0][A] u0_srio_response_gen/tdata_out_57_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.800
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 2.972, 26.583%; route: 7.976, 71.342%; tC2Q: 0.232, 2.075%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path14

Path Summary:

Slack 1.587
Data Arrival Time 14.421
Data Required Time 16.008
From u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1
To u0_srio_request_gen/tdata_out_51_s0
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.243 3.243 tNET RR 1 R75C138[0][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/CLK
3.475 0.232 tC2Q RF 5 R75C138[0][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/Q
4.133 0.657 tNET FF 1 R75C128[1][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/pipe_tx_ready_s1/I0
4.586 0.453 tINS FF 24 R75C128[1][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/pipe_tx_ready_s1/F
5.258 0.673 tNET FF 1 R72C126[3][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s0/I2
5.629 0.371 tINS FF 1 R72C126[3][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s0/F
5.634 0.004 tNET FF 1 R72C126[3][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s/I2
6.151 0.517 tINS FF 8 R72C126[3][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s/F
9.731 3.580 tNET FF 1 R54C59[1][B] u0_srio_request_gen/n32793_s1/I2
10.286 0.555 tINS FF 9 R54C59[1][B] u0_srio_request_gen/n32793_s1/F
11.282 0.997 tNET FF 1 R69C58[0][A] u0_srio_request_gen/n32793_s0/I0
11.799 0.517 tINS FF 18 R69C58[0][A] u0_srio_request_gen/n32793_s0/F
12.516 0.716 tNET FF 1 R63C57[3][A] u0_srio_request_gen/n33674_s2/I3
13.033 0.517 tINS FF 8 R63C57[3][A] u0_srio_request_gen/n33674_s2/F
13.959 0.926 tNET FF 1 R60C58[1][A] u0_srio_request_gen/n33682_s0/I3
14.421 0.462 tINS FR 1 R60C58[1][A] u0_srio_request_gen/n33682_s0/F
14.421 0.000 tNET RR 1 R60C58[1][A] u0_srio_request_gen/tdata_out_51_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.800 12.800 active clock edge time
12.800 0.000 srio_clk
12.800 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.043 3.243 tNET RR 1 R60C58[1][A] u0_srio_request_gen/tdata_out_51_s0/CLK
16.008 -0.035 tSu 1 R60C58[1][A] u0_srio_request_gen/tdata_out_51_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.800
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 3.392, 30.346%; route: 7.554, 67.579%; tC2Q: 0.232, 2.076%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path15

Path Summary:

Slack 1.587
Data Arrival Time 14.421
Data Required Time 16.008
From u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1
To u0_srio_request_gen/tdata_out_59_s0
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.243 3.243 tNET RR 1 R75C138[0][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/CLK
3.475 0.232 tC2Q RF 5 R75C138[0][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/Q
4.133 0.657 tNET FF 1 R75C128[1][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/pipe_tx_ready_s1/I0
4.586 0.453 tINS FF 24 R75C128[1][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/pipe_tx_ready_s1/F
5.258 0.673 tNET FF 1 R72C126[3][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s0/I2
5.629 0.371 tINS FF 1 R72C126[3][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s0/F
5.634 0.004 tNET FF 1 R72C126[3][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s/I2
6.151 0.517 tINS FF 8 R72C126[3][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s/F
9.731 3.580 tNET FF 1 R54C59[1][B] u0_srio_request_gen/n32793_s1/I2
10.286 0.555 tINS FF 9 R54C59[1][B] u0_srio_request_gen/n32793_s1/F
11.282 0.997 tNET FF 1 R69C58[0][A] u0_srio_request_gen/n32793_s0/I0
11.799 0.517 tINS FF 18 R69C58[0][A] u0_srio_request_gen/n32793_s0/F
12.516 0.716 tNET FF 1 R63C57[3][A] u0_srio_request_gen/n33674_s2/I3
13.033 0.517 tINS FF 8 R63C57[3][A] u0_srio_request_gen/n33674_s2/F
13.959 0.926 tNET FF 1 R60C58[1][B] u0_srio_request_gen/n33674_s0/I3
14.421 0.462 tINS FR 1 R60C58[1][B] u0_srio_request_gen/n33674_s0/F
14.421 0.000 tNET RR 1 R60C58[1][B] u0_srio_request_gen/tdata_out_59_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.800 12.800 active clock edge time
12.800 0.000 srio_clk
12.800 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.043 3.243 tNET RR 1 R60C58[1][B] u0_srio_request_gen/tdata_out_59_s0/CLK
16.008 -0.035 tSu 1 R60C58[1][B] u0_srio_request_gen/tdata_out_59_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.800
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 3.392, 30.346%; route: 7.554, 67.579%; tC2Q: 0.232, 2.076%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path16

Path Summary:

Slack 1.607
Data Arrival Time 14.401
Data Required Time 16.008
From u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1
To u0_srio_response_gen/tdata_out_51_s0
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.243 3.243 tNET RR 1 R75C138[0][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/CLK
3.475 0.232 tC2Q RF 5 R75C138[0][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/Q
4.133 0.657 tNET FF 1 R75C128[1][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/pipe_tx_ready_s1/I0
4.586 0.453 tINS FF 24 R75C128[1][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/pipe_tx_ready_s1/F
5.210 0.624 tNET FF 1 R74C127[3][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_resp_trac_ready_o_d_s0/I2
5.780 0.570 tINS FR 1 R74C127[3][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_resp_trac_ready_o_d_s0/F
5.926 0.146 tNET RR 1 R74C127[3][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_resp_trac_ready_o_d_s/I2
6.379 0.453 tINS RF 7 R74C127[3][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_resp_trac_ready_o_d_s/F
10.264 3.885 tNET FF 1 R60C53[3][A] u0_srio_response_gen/n1809_s0/I3
10.635 0.371 tINS FF 19 R60C53[3][A] u0_srio_response_gen/n1809_s0/F
12.587 1.952 tNET FF 1 R72C54[1][B] u0_srio_response_gen/increase_data_3_s0/I2
13.142 0.555 tINS FF 3 R72C54[1][B] u0_srio_response_gen/increase_data_3_s0/F
13.939 0.798 tNET FF 1 R60C54[0][B] u0_srio_response_gen/n1689_s0/I0
14.401 0.462 tINS FR 1 R60C54[0][B] u0_srio_response_gen/n1689_s0/F
14.401 0.000 tNET RR 1 R60C54[0][B] u0_srio_response_gen/tdata_out_51_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.800 12.800 active clock edge time
12.800 0.000 srio_clk
12.800 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.043 3.243 tNET RR 1 R60C54[0][B] u0_srio_response_gen/tdata_out_51_s0/CLK
16.008 -0.035 tSu 1 R60C54[0][B] u0_srio_response_gen/tdata_out_51_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.800
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 2.864, 25.668%; route: 8.062, 72.253%; tC2Q: 0.232, 2.079%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path17

Path Summary:

Slack 1.611
Data Arrival Time 14.397
Data Required Time 16.008
From u0_srio_response_gen/fifo_nafull_2d_s0
To u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/rx_port_data_8_s0
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.243 3.243 tNET RR 1 R68C54[0][B] u0_srio_response_gen/fifo_nafull_2d_s0/CLK
3.475 0.232 tC2Q RF 5 R68C54[0][B] u0_srio_response_gen/fifo_nafull_2d_s0/Q
7.373 3.898 tNET FF 1 R57C133[2][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/next_rx_data_7_s3/I0
7.922 0.549 tINS FR 1 R57C133[2][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/next_rx_data_7_s3/F
7.924 0.001 tNET RR 1 R57C133[3][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/next_rx_data_7_s1/I0
8.377 0.453 tINS RF 12 R57C133[3][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/next_rx_data_7_s1/F
9.064 0.688 tNET FF 1 R57C137[2][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/next_rx_data_5_s2/I0
9.435 0.371 tINS FF 6 R57C137[2][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/next_rx_data_5_s2/F
11.234 1.799 tNET FF 1 R69C137[0][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/next_rx_data_5_s0/I2
11.751 0.517 tINS FF 1 R69C137[0][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/next_rx_data_5_s0/F
12.291 0.539 tNET FF 1 R62C137[1][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/n2132_s7/I2
12.846 0.555 tINS FF 1 R62C137[1][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/n2132_s7/F
13.385 0.539 tNET FF 1 R68C137[3][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/n2132_s1/I3
13.934 0.549 tINS FR 1 R68C137[3][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/n2132_s1/F
13.935 0.001 tNET RR 1 R68C137[0][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/n2132_s0/I0
14.397 0.462 tINS RR 1 R68C137[0][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/n2132_s0/F
14.397 0.000 tNET RR 1 R68C137[0][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/rx_port_data_8_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.800 12.800 active clock edge time
12.800 0.000 srio_clk
12.800 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.043 3.243 tNET RR 1 R68C137[0][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/rx_port_data_8_s0/CLK
16.008 -0.035 tSu 1 R68C137[0][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_rx/rx_port_data_8_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.800
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 3.456, 30.985%; route: 7.466, 66.935%; tC2Q: 0.232, 2.080%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path18

Path Summary:

Slack 1.717
Data Arrival Time 14.291
Data Required Time 16.008
From u0_srio_response_gen/state_1_s0
To u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/single_beat_s0
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.243 3.243 tNET RR 1 R58C55[1][B] u0_srio_response_gen/state_1_s0/CLK
3.475 0.232 tC2Q RF 10 R58C55[1][B] u0_srio_response_gen/state_1_s0/Q
3.914 0.438 tNET FF 1 R60C55[1][B] u0_srio_response_gen/tx_resp_trac_valid_s/I0
4.431 0.517 tINS FF 11 R60C55[1][B] u0_srio_response_gen/tx_resp_trac_valid_s/F
8.545 4.115 tNET FF 1 R75C126[1][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/grant_0_s3/I0
9.062 0.517 tINS FF 10 R75C126[1][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/grant_0_s3/F
9.507 0.445 tNET FF 1 R76C125[3][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/pre_req_1_s2/I3
10.056 0.549 tINS FR 2 R76C125[3][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/pre_req_1_s2/F
10.233 0.177 tNET RR 1 R76C124[3][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/pre_req_2_s2/I3
10.695 0.462 tINS RR 1 R76C124[3][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/pre_req_2_s2/F
10.697 0.001 tNET RR 1 R76C124[3][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/grant_3_s1/I0
11.214 0.517 tINS RF 8 R76C124[3][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/grant_3_s1/F
11.901 0.688 tNET FF 1 R75C126[0][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/single_beat_s11/I3
12.471 0.570 tINS FR 1 R75C126[0][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/single_beat_s11/F
12.647 0.176 tNET RR 1 R74C126[3][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/single_beat_s8/I0
13.109 0.462 tINS RR 1 R74C126[3][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/single_beat_s8/F
13.110 0.001 tNET RR 1 R74C126[1][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/single_beat_s6/I3
13.572 0.462 tINS RR 2 R74C126[1][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/single_beat_s6/F
13.575 0.003 tNET RR 1 R74C126[0][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/single_beat_s5/I1
14.145 0.570 tINS RR 1 R74C126[0][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/single_beat_s5/F
14.291 0.146 tNET RR 1 R74C126[1][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/single_beat_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.800 12.800 active clock edge time
12.800 0.000 srio_clk
12.800 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.043 3.243 tNET RR 1 R74C126[1][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/single_beat_s0/CLK
16.008 -0.035 tSu 1 R74C126[1][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/single_beat_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.800
Logic Level 10
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 4.626, 41.872%; route: 6.190, 56.028%; tC2Q: 0.232, 2.100%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path19

Path Summary:

Slack 1.727
Data Arrival Time 14.281
Data Required Time 16.008
From u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/u_sdpram_dat/mem_data_mem_data_0_3_s
To u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/pri_fifo_array[0].u_pri_fifo/ram_full_int_s4
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.243 3.243 tNET RR 15 BSRAM_R64[31][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/u_sdpram_dat/mem_data_mem_data_0_3_s/CLKB
5.503 2.260 tC2Q RF 7 BSRAM_R64[31][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/u_sdpram_dat/mem_data_mem_data_0_3_s/DO[10]
6.728 1.225 tNET FF 1 R68C144[1][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/n1897_s1/I1
7.190 0.462 tINS FR 2 R68C144[1][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/n1897_s1/F
7.193 0.003 tNET RR 1 R68C144[0][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/n1897_s0/I0
7.748 0.555 tINS RF 29 R68C144[0][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/n1897_s0/F
8.874 1.126 tNET FF 1 R69C150[1][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/pri_fifo_array[0].u_pri_fifo/ram_rd_en_i_s3/I2
9.391 0.517 tINS FF 5 R69C150[1][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/pri_fifo_array[0].u_pri_fifo/ram_rd_en_i_s3/F
10.370 0.979 tNET FF 1 R57C150[0][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/pri_fifo_array[0].u_pri_fifo/ram_rd_en_i_s2/I0
10.823 0.453 tINS FF 7 R57C150[0][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/pri_fifo_array[0].u_pri_fifo/ram_rd_en_i_s2/F
13.269 2.446 tNET FF 1 R52C146[2][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/pri_fifo_array[0].u_pri_fifo/n182_s3/I0
13.731 0.462 tINS FR 1 R52C146[2][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/pri_fifo_array[0].u_pri_fifo/n182_s3/F
13.732 0.001 tNET RR 1 R52C146[2][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/pri_fifo_array[0].u_pri_fifo/n182_s2/I0
14.281 0.549 tINS RR 1 R52C146[2][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/pri_fifo_array[0].u_pri_fifo/n182_s2/F
14.281 0.000 tNET RR 1 R52C146[2][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/pri_fifo_array[0].u_pri_fifo/ram_full_int_s4/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.800 12.800 active clock edge time
12.800 0.000 srio_clk
12.800 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.043 3.243 tNET RR 1 R52C146[2][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/pri_fifo_array[0].u_pri_fifo/ram_full_int_s4/CLK
16.008 -0.035 tSu 1 R52C146[2][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_tx_buf/pri_fifo_array[0].u_pri_fifo/ram_full_int_s4

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.800
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 2.998, 27.161%; route: 5.780, 52.365%; tC2Q: 2.260, 20.475%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path20

Path Summary:

Slack 1.742
Data Arrival Time 14.267
Data Required Time 16.008
From u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1
To u0_srio_request_gen/tdata_out_35_s0
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.243 3.243 tNET RR 1 R75C138[0][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/CLK
3.475 0.232 tC2Q RF 5 R75C138[0][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/Q
4.133 0.657 tNET FF 1 R75C128[1][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/pipe_tx_ready_s1/I0
4.586 0.453 tINS FF 24 R75C128[1][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/pipe_tx_ready_s1/F
5.258 0.673 tNET FF 1 R72C126[3][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s0/I2
5.629 0.371 tINS FF 1 R72C126[3][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s0/F
5.634 0.004 tNET FF 1 R72C126[3][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s/I2
6.151 0.517 tINS FF 8 R72C126[3][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s/F
9.731 3.580 tNET FF 1 R54C59[1][B] u0_srio_request_gen/n32793_s1/I2
10.286 0.555 tINS FF 9 R54C59[1][B] u0_srio_request_gen/n32793_s1/F
11.282 0.997 tNET FF 1 R69C58[0][A] u0_srio_request_gen/n32793_s0/I0
11.799 0.517 tINS FF 18 R69C58[0][A] u0_srio_request_gen/n32793_s0/F
12.516 0.716 tNET FF 1 R63C57[3][A] u0_srio_request_gen/n33674_s2/I3
13.033 0.517 tINS FF 8 R63C57[3][A] u0_srio_request_gen/n33674_s2/F
13.697 0.664 tNET FF 1 R60C58[0][B] u0_srio_request_gen/n33698_s0/I3
14.267 0.570 tINS FR 1 R60C58[0][B] u0_srio_request_gen/n33698_s0/F
14.267 0.000 tNET RR 1 R60C58[0][B] u0_srio_request_gen/tdata_out_35_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.800 12.800 active clock edge time
12.800 0.000 srio_clk
12.800 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.043 3.243 tNET RR 1 R60C58[0][B] u0_srio_request_gen/tdata_out_35_s0/CLK
16.008 -0.035 tSu 1 R60C58[0][B] u0_srio_request_gen/tdata_out_35_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.800
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 3.500, 31.751%; route: 7.291, 66.144%; tC2Q: 0.232, 2.105%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path21

Path Summary:

Slack 1.803
Data Arrival Time 14.206
Data Required Time 16.008
From u0_srio_response_gen/state_1_s0
To u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/first_beat_mask_s1
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.243 3.243 tNET RR 1 R58C55[1][B] u0_srio_response_gen/state_1_s0/CLK
3.475 0.232 tC2Q RF 10 R58C55[1][B] u0_srio_response_gen/state_1_s0/Q
3.914 0.438 tNET FF 1 R60C55[1][B] u0_srio_response_gen/tx_resp_trac_valid_s/I0
4.431 0.517 tINS FF 11 R60C55[1][B] u0_srio_response_gen/tx_resp_trac_valid_s/F
8.545 4.115 tNET FF 1 R75C126[1][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/grant_0_s3/I0
9.062 0.517 tINS FF 10 R75C126[1][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/grant_0_s3/F
9.507 0.445 tNET FF 1 R76C125[3][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/pre_req_1_s2/I3
10.056 0.549 tINS FR 2 R76C125[3][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/pre_req_1_s2/F
10.233 0.177 tNET RR 1 R76C124[3][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/pre_req_2_s2/I3
10.695 0.462 tINS RR 1 R76C124[3][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/pre_req_2_s2/F
10.697 0.001 tNET RR 1 R76C124[3][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/grant_3_s1/I0
11.246 0.549 tINS RR 8 R76C124[3][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/grant_3_s1/F
11.429 0.183 tNET RR 1 R76C123[3][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/n784_s26/I3
11.946 0.517 tINS RF 1 R76C123[3][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/n784_s26/F
12.359 0.414 tNET FF 1 R75C125[3][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/n784_s23/I0
12.821 0.462 tINS FR 1 R75C125[3][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/n784_s23/F
12.997 0.176 tNET RR 1 R75C126[0][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/n784_s20/I2
13.567 0.570 tINS RR 2 R75C126[0][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/n784_s20/F
13.744 0.177 tNET RR 1 R74C126[0][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/n728_s1/I3
14.206 0.462 tINS RR 1 R74C126[0][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/n728_s1/F
14.206 0.000 tNET RR 1 R74C126[0][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/first_beat_mask_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.800 12.800 active clock edge time
12.800 0.000 srio_clk
12.800 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.043 3.243 tNET RR 1 R74C126[0][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/first_beat_mask_s1/CLK
16.008 -0.035 tSu 1 R74C126[0][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/first_beat_mask_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.800
Logic Level 10
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 4.605, 42.007%; route: 6.125, 55.876%; tC2Q: 0.232, 2.116%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path22

Path Summary:

Slack 1.818
Data Arrival Time 14.190
Data Required Time 16.008
From u0_srio_response_gen/state_1_s0
To u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/port_pend_s_beat_1_s1
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.243 3.243 tNET RR 1 R58C55[1][B] u0_srio_response_gen/state_1_s0/CLK
3.475 0.232 tC2Q RF 10 R58C55[1][B] u0_srio_response_gen/state_1_s0/Q
3.914 0.438 tNET FF 1 R60C55[1][B] u0_srio_response_gen/tx_resp_trac_valid_s/I0
4.431 0.517 tINS FF 11 R60C55[1][B] u0_srio_response_gen/tx_resp_trac_valid_s/F
8.545 4.115 tNET FF 1 R75C126[1][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/grant_0_s3/I0
9.062 0.517 tINS FF 10 R75C126[1][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/grant_0_s3/F
9.507 0.445 tNET FF 1 R76C125[3][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/pre_req_1_s2/I3
10.056 0.549 tINS FR 2 R76C125[3][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/pre_req_1_s2/F
10.233 0.177 tNET RR 1 R76C124[3][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/pre_req_2_s2/I3
10.695 0.462 tINS RR 1 R76C124[3][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/pre_req_2_s2/F
10.697 0.001 tNET RR 1 R76C124[3][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/grant_3_s1/I0
11.214 0.517 tINS RF 8 R76C124[3][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/arb_fixed.u_fixed_prio/grant_3_s1/F
11.647 0.434 tNET FF 1 R75C125[1][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/win_index_1_s5/I3
12.202 0.555 tINS FF 5 R75C125[1][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/win_index_1_s5/F
12.875 0.672 tNET FF 1 R72C126[1][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/n634_s1/I2
13.445 0.570 tINS FR 1 R72C126[1][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/n634_s1/F
13.620 0.176 tNET RR 1 R72C127[1][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/n634_s0/I2
14.190 0.570 tINS RR 1 R72C127[1][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/n634_s0/F
14.190 0.000 tNET RR 1 R72C127[1][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/port_pend_s_beat_1_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.800 12.800 active clock edge time
12.800 0.000 srio_clk
12.800 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.043 3.243 tNET RR 1 R72C127[1][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/port_pend_s_beat_1_s1/CLK
16.008 -0.035 tSu 1 R72C127[1][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/port_pend_s_beat_1_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.800
Logic Level 9
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 4.257, 38.888%; route: 6.458, 58.992%; tC2Q: 0.232, 2.119%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path23

Path Summary:

Slack 1.828
Data Arrival Time 14.180
Data Required Time 16.008
From u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1
To u0_srio_request_gen/tdata_out_7_s0
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.243 3.243 tNET RR 1 R75C138[0][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/CLK
3.475 0.232 tC2Q RF 5 R75C138[0][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/Q
4.133 0.657 tNET FF 1 R75C128[1][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/pipe_tx_ready_s1/I0
4.586 0.453 tINS FF 24 R75C128[1][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/pipe_tx_ready_s1/F
5.258 0.673 tNET FF 1 R72C126[3][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s0/I2
5.629 0.371 tINS FF 1 R72C126[3][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s0/F
5.634 0.004 tNET FF 1 R72C126[3][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s/I2
6.151 0.517 tINS FF 8 R72C126[3][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s/F
9.731 3.580 tNET FF 1 R54C59[1][B] u0_srio_request_gen/n32793_s1/I2
10.286 0.555 tINS FF 9 R54C59[1][B] u0_srio_request_gen/n32793_s1/F
11.282 0.997 tNET FF 1 R69C58[0][A] u0_srio_request_gen/n32793_s0/I0
11.799 0.517 tINS FF 18 R69C58[0][A] u0_srio_request_gen/n32793_s0/F
12.080 0.280 tNET FF 1 R67C58[0][B] u0_srio_request_gen/n33670_s2/I3
12.451 0.371 tINS FF 8 R67C58[0][B] u0_srio_request_gen/n33670_s2/F
13.631 1.181 tNET FF 1 R59C58[1][A] u0_srio_request_gen/n33726_s0/I2
14.180 0.549 tINS FR 1 R59C58[1][A] u0_srio_request_gen/n33726_s0/F
14.180 0.000 tNET RR 1 R59C58[1][A] u0_srio_request_gen/tdata_out_7_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.800 12.800 active clock edge time
12.800 0.000 srio_clk
12.800 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.043 3.243 tNET RR 1 R59C58[1][A] u0_srio_request_gen/tdata_out_7_s0/CLK
16.008 -0.035 tSu 1 R59C58[1][A] u0_srio_request_gen/tdata_out_7_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.800
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 3.333, 30.475%; route: 7.372, 67.404%; tC2Q: 0.232, 2.121%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path24

Path Summary:

Slack 1.828
Data Arrival Time 14.180
Data Required Time 16.008
From u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1
To u0_srio_request_gen/tdata_out_15_s0
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.243 3.243 tNET RR 1 R75C138[0][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/CLK
3.475 0.232 tC2Q RF 5 R75C138[0][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/Q
4.133 0.657 tNET FF 1 R75C128[1][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/pipe_tx_ready_s1/I0
4.586 0.453 tINS FF 24 R75C128[1][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/pipe_tx_ready_s1/F
5.258 0.673 tNET FF 1 R72C126[3][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s0/I2
5.629 0.371 tINS FF 1 R72C126[3][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s0/F
5.634 0.004 tNET FF 1 R72C126[3][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s/I2
6.151 0.517 tINS FF 8 R72C126[3][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s/F
9.731 3.580 tNET FF 1 R54C59[1][B] u0_srio_request_gen/n32793_s1/I2
10.286 0.555 tINS FF 9 R54C59[1][B] u0_srio_request_gen/n32793_s1/F
11.282 0.997 tNET FF 1 R69C58[0][A] u0_srio_request_gen/n32793_s0/I0
11.799 0.517 tINS FF 18 R69C58[0][A] u0_srio_request_gen/n32793_s0/F
12.080 0.280 tNET FF 1 R67C58[0][B] u0_srio_request_gen/n33670_s2/I3
12.451 0.371 tINS FF 8 R67C58[0][B] u0_srio_request_gen/n33670_s2/F
13.631 1.181 tNET FF 1 R59C58[0][A] u0_srio_request_gen/n33718_s0/I2
14.180 0.549 tINS FR 1 R59C58[0][A] u0_srio_request_gen/n33718_s0/F
14.180 0.000 tNET RR 1 R59C58[0][A] u0_srio_request_gen/tdata_out_15_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.800 12.800 active clock edge time
12.800 0.000 srio_clk
12.800 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.043 3.243 tNET RR 1 R59C58[0][A] u0_srio_request_gen/tdata_out_15_s0/CLK
16.008 -0.035 tSu 1 R59C58[0][A] u0_srio_request_gen/tdata_out_15_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.800
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 3.333, 30.475%; route: 7.372, 67.404%; tC2Q: 0.232, 2.121%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path25

Path Summary:

Slack 1.845
Data Arrival Time 14.163
Data Required Time 16.008
From u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1
To u0_srio_request_gen/tdata_out_63_s0
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.243 3.243 tNET RR 1 R75C138[0][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/CLK
3.475 0.232 tC2Q RF 5 R75C138[0][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_encap/pipe_tx_ready_s1/Q
4.133 0.657 tNET FF 1 R75C128[1][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/pipe_tx_ready_s1/I0
4.586 0.453 tINS FF 24 R75C128[1][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/pipe_tx_ready_s1/F
5.258 0.673 tNET FF 1 R72C126[3][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s0/I2
5.629 0.371 tINS FF 1 R72C126[3][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s0/F
5.634 0.004 tNET FF 1 R72C126[3][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s/I2
6.151 0.517 tINS FF 8 R72C126[3][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/tx_req_trac_ready_o_d_s/F
9.731 3.580 tNET FF 1 R54C59[1][B] u0_srio_request_gen/n32793_s1/I2
10.286 0.555 tINS FF 9 R54C59[1][B] u0_srio_request_gen/n32793_s1/F
11.282 0.997 tNET FF 1 R69C58[0][A] u0_srio_request_gen/n32793_s0/I0
11.799 0.517 tINS FF 18 R69C58[0][A] u0_srio_request_gen/n32793_s0/F
12.080 0.280 tNET FF 1 R67C58[0][B] u0_srio_request_gen/n33670_s2/I3
12.451 0.371 tINS FF 8 R67C58[0][B] u0_srio_request_gen/n33670_s2/F
13.614 1.163 tNET FF 1 R61C57[0][B] u0_srio_request_gen/n33670_s0/I2
14.163 0.549 tINS FR 1 R61C57[0][B] u0_srio_request_gen/n33670_s0/F
14.163 0.000 tNET RR 1 R61C57[0][B] u0_srio_request_gen/tdata_out_63_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.800 12.800 active clock edge time
12.800 0.000 srio_clk
12.800 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.043 3.243 tNET RR 1 R61C57[0][B] u0_srio_request_gen/tdata_out_63_s0/CLK
16.008 -0.035 tSu 1 R61C57[0][B] u0_srio_request_gen/tdata_out_63_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.800
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 3.333, 30.522%; route: 7.355, 67.353%; tC2Q: 0.232, 2.125%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 0.071
Data Arrival Time 3.504
Data Required Time 3.433
From u0_srio_response_gen/fifo_wdata_64_s0
To u0_srio_response_gen/u_fifo_top/fifo_sc_inst/mem_mem_0_2_s
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 R65C53[1][A] u0_srio_response_gen/fifo_wdata_64_s0/CLK
3.385 0.201 tC2Q RF 1 R65C53[1][A] u0_srio_response_gen/fifo_wdata_64_s0/Q
3.504 0.119 tNET FF 1 BSRAM_R64[10][B] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/mem_mem_0_2_s/DI[0]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 BSRAM_R64[10][B] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/mem_mem_0_2_s/CLKA
3.433 0.249 tHld 1 BSRAM_R64[10][B] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/mem_mem_0_2_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.119, 37.200%; tC2Q: 0.201, 62.800%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path2

Path Summary:

Slack 0.071
Data Arrival Time 3.504
Data Required Time 3.433
From u0_srio_response_gen/fifo_wdata_21_s0
To u0_srio_response_gen/u_fifo_top/fifo_sc_inst/mem_mem_0_0_s
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 R65C51[0][A] u0_srio_response_gen/fifo_wdata_21_s0/CLK
3.385 0.201 tC2Q RF 1 R65C51[0][A] u0_srio_response_gen/fifo_wdata_21_s0/Q
3.504 0.119 tNET FF 1 BSRAM_R64[10][A] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/mem_mem_0_0_s/DI[21]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 BSRAM_R64[10][A] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/mem_mem_0_0_s/CLKA
3.433 0.249 tHld 1 BSRAM_R64[10][A] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/mem_mem_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.119, 37.200%; tC2Q: 0.201, 62.800%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path3

Path Summary:

Slack 0.071
Data Arrival Time 3.504
Data Required Time 3.433
From u0_srio_response_gen/fifo_wdata_15_s0
To u0_srio_response_gen/u_fifo_top/fifo_sc_inst/mem_mem_0_0_s
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 R63C51[0][B] u0_srio_response_gen/fifo_wdata_15_s0/CLK
3.385 0.201 tC2Q RF 1 R63C51[0][B] u0_srio_response_gen/fifo_wdata_15_s0/Q
3.504 0.119 tNET FF 1 BSRAM_R64[10][A] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/mem_mem_0_0_s/DI[15]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 BSRAM_R64[10][A] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/mem_mem_0_0_s/CLKA
3.433 0.249 tHld 1 BSRAM_R64[10][A] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/mem_mem_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.119, 37.200%; tC2Q: 0.201, 62.800%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path4

Path Summary:

Slack 0.071
Data Arrival Time 3.504
Data Required Time 3.433
From u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo1_wdata_48_s0
To u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u1_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 R83C104[1][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo1_wdata_48_s0/CLK
3.385 0.201 tC2Q RF 1 R83C104[1][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo1_wdata_48_s0/Q
3.504 0.119 tNET FF 1 BSRAM_R82[19][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u1_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/DI[0]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 BSRAM_R82[19][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u1_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/CLKA
3.433 0.249 tHld 1 BSRAM_R82[19][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u1_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.119, 37.200%; tC2Q: 0.201, 62.800%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path5

Path Summary:

Slack 0.071
Data Arrival Time 3.504
Data Required Time 3.433
From u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo1_wdata_5_s0
To u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u1_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 R83C101[0][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo1_wdata_5_s0/CLK
3.385 0.201 tC2Q RF 1 R83C101[0][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo1_wdata_5_s0/Q
3.504 0.119 tNET FF 1 BSRAM_R82[19][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u1_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s/DI[5]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 BSRAM_R82[19][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u1_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s/CLKA
3.433 0.249 tHld 1 BSRAM_R82[19][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u1_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.119, 37.200%; tC2Q: 0.201, 62.800%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path6

Path Summary:

Slack 0.071
Data Arrival Time 3.504
Data Required Time 3.433
From u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo1_wdata_0_s0
To u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u1_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 R81C101[1][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo1_wdata_0_s0/CLK
3.385 0.201 tC2Q RF 1 R81C101[1][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo1_wdata_0_s0/Q
3.504 0.119 tNET FF 1 BSRAM_R82[19][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u1_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s/DI[0]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 BSRAM_R82[19][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u1_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s/CLKA
3.433 0.249 tHld 1 BSRAM_R82[19][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u1_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.119, 37.200%; tC2Q: 0.201, 62.800%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path7

Path Summary:

Slack 0.071
Data Arrival Time 3.504
Data Required Time 3.433
From u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo0_wdata_49_s0
To u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u0_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 R83C110[2][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo0_wdata_49_s0/CLK
3.385 0.201 tC2Q RF 1 R83C110[2][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo0_wdata_49_s0/Q
3.504 0.119 tNET FF 1 BSRAM_R82[21][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u0_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/DI[4]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 BSRAM_R82[21][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u0_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/CLKA
3.433 0.249 tHld 1 BSRAM_R82[21][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u0_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.119, 37.200%; tC2Q: 0.201, 62.800%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path8

Path Summary:

Slack 0.071
Data Arrival Time 3.504
Data Required Time 3.433
From u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo0_wdata_48_s0
To u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u0_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 R83C110[2][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo0_wdata_48_s0/CLK
3.385 0.201 tC2Q RF 1 R83C110[2][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo0_wdata_48_s0/Q
3.504 0.119 tNET FF 1 BSRAM_R82[21][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u0_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/DI[3]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 BSRAM_R82[21][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u0_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/CLKA
3.433 0.249 tHld 1 BSRAM_R82[21][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u0_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.119, 37.200%; tC2Q: 0.201, 62.800%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path9

Path Summary:

Slack 0.071
Data Arrival Time 3.504
Data Required Time 3.433
From u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo0_wdata_5_s0
To u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u0_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 R83C107[0][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo0_wdata_5_s0/CLK
3.385 0.201 tC2Q RF 1 R83C107[0][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo0_wdata_5_s0/Q
3.504 0.119 tNET FF 1 BSRAM_R82[20] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u0_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s/DI[5]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 BSRAM_R82[20] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u0_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s/CLKA
3.433 0.249 tHld 1 BSRAM_R82[20] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u0_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.119, 37.200%; tC2Q: 0.201, 62.800%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path10

Path Summary:

Slack 0.071
Data Arrival Time 3.504
Data Required Time 3.433
From u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_rx_buf/phy_rx_data_r_0_s0
To u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_rx_buf/u_rx_data_fifo/mem_data_mem_data_0_0_s
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 R65C116[2][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_rx_buf/phy_rx_data_r_0_s0/CLK
3.385 0.201 tC2Q RF 1 R65C116[2][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_rx_buf/phy_rx_data_r_0_s0/Q
3.504 0.119 tNET FF 1 BSRAM_R64[24] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_rx_buf/u_rx_data_fifo/mem_data_mem_data_0_0_s/DI[0]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 BSRAM_R64[24] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_rx_buf/u_rx_data_fifo/mem_data_mem_data_0_0_s/CLKA
3.433 0.249 tHld 1 BSRAM_R64[24] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_rx_buf/u_rx_data_fifo/mem_data_mem_data_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.119, 37.200%; tC2Q: 0.201, 62.800%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path11

Path Summary:

Slack 0.078
Data Arrival Time 3.511
Data Required Time 3.433
From u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo1_wdata_58_s0
To u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u1_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 R81C104[3][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo1_wdata_58_s0/CLK
3.386 0.202 tC2Q RR 1 R81C104[3][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo1_wdata_58_s0/Q
3.511 0.125 tNET RR 1 BSRAM_R82[19][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u1_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/DI[6]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 BSRAM_R82[19][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u1_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/CLKA
3.433 0.249 tHld 1 BSRAM_R82[19][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u1_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.125, 38.162%; tC2Q: 0.202, 61.838%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path12

Path Summary:

Slack 0.078
Data Arrival Time 3.511
Data Required Time 3.433
From u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo1_wdata_51_s0
To u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u1_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 R83C104[0][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo1_wdata_51_s0/CLK
3.386 0.202 tC2Q RR 1 R83C104[0][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo1_wdata_51_s0/Q
3.511 0.125 tNET RR 1 BSRAM_R82[19][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u1_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/DI[3]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 BSRAM_R82[19][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u1_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/CLKA
3.433 0.249 tHld 1 BSRAM_R82[19][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u1_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.125, 38.162%; tC2Q: 0.202, 61.838%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path13

Path Summary:

Slack 0.078
Data Arrival Time 3.511
Data Required Time 3.433
From u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo1_wdata_49_s0
To u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u1_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 R83C104[1][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo1_wdata_49_s0/CLK
3.386 0.202 tC2Q RR 1 R83C104[1][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo1_wdata_49_s0/Q
3.511 0.125 tNET RR 1 BSRAM_R82[19][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u1_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/DI[1]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 BSRAM_R82[19][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u1_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/CLKA
3.433 0.249 tHld 1 BSRAM_R82[19][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u1_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.125, 38.162%; tC2Q: 0.202, 61.838%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path14

Path Summary:

Slack 0.078
Data Arrival Time 3.511
Data Required Time 3.433
From u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_rx_buf/phy_rx_data_r_23_s0
To u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_rx_buf/u_rx_data_fifo/mem_data_mem_data_0_1_s
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 R63C119[3][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_rx_buf/phy_rx_data_r_23_s0/CLK
3.386 0.202 tC2Q RR 1 R63C119[3][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_rx_buf/phy_rx_data_r_23_s0/Q
3.511 0.125 tNET RR 1 BSRAM_R64[25][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_rx_buf/u_rx_data_fifo/mem_data_mem_data_0_1_s/DI[5]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 BSRAM_R64[25][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_rx_buf/u_rx_data_fifo/mem_data_mem_data_0_1_s/CLKA
3.433 0.249 tHld 1 BSRAM_R64[25][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_rx_buf/u_rx_data_fifo/mem_data_mem_data_0_1_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.125, 38.162%; tC2Q: 0.202, 61.838%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path15

Path Summary:

Slack 0.078
Data Arrival Time 3.511
Data Required Time 3.433
From u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_rx_buf/phy_rx_data_r_2_s0
To u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_rx_buf/u_rx_data_fifo/mem_data_mem_data_0_0_s
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 R65C116[1][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_rx_buf/phy_rx_data_r_2_s0/CLK
3.386 0.202 tC2Q RR 1 R65C116[1][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_rx_buf/phy_rx_data_r_2_s0/Q
3.511 0.125 tNET RR 1 BSRAM_R64[24] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_rx_buf/u_rx_data_fifo/mem_data_mem_data_0_0_s/DI[2]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 BSRAM_R64[24] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_rx_buf/u_rx_data_fifo/mem_data_mem_data_0_0_s/CLKA
3.433 0.249 tHld 1 BSRAM_R64[24] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_buf_top/u_srio_rx_buf/u_rx_data_fifo/mem_data_mem_data_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.125, 38.162%; tC2Q: 0.202, 61.838%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path16

Path Summary:

Slack 0.201
Data Arrival Time 3.634
Data Required Time 3.433
From u0_srio_response_gen/rx_req_din_87_s0
To u0_srio_response_gen/u0_sdpram_dat/mem_data_mem_data_0_2_s
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 R78C54[1][A] u0_srio_response_gen/rx_req_din_87_s0/CLK
3.386 0.202 tC2Q RR 1 R78C54[1][A] u0_srio_response_gen/rx_req_din_87_s0/Q
3.634 0.248 tNET RR 1 BSRAM_R82[10][B] u0_srio_response_gen/u0_sdpram_dat/mem_data_mem_data_0_2_s/DI[15]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 BSRAM_R82[10][B] u0_srio_response_gen/u0_sdpram_dat/mem_data_mem_data_0_2_s/CLKA
3.433 0.249 tHld 1 BSRAM_R82[10][B] u0_srio_response_gen/u0_sdpram_dat/mem_data_mem_data_0_2_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.248, 55.121%; tC2Q: 0.202, 44.879%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path17

Path Summary:

Slack 0.201
Data Arrival Time 3.634
Data Required Time 3.433
From u0_srio_response_gen/rx_req_din_45_s0
To u0_srio_response_gen/u0_sdpram_dat/mem_data_mem_data_0_1_s
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 R78C51[0][B] u0_srio_response_gen/rx_req_din_45_s0/CLK
3.386 0.202 tC2Q RR 1 R78C51[0][B] u0_srio_response_gen/rx_req_din_45_s0/Q
3.634 0.248 tNET RR 1 BSRAM_R82[10][A] u0_srio_response_gen/u0_sdpram_dat/mem_data_mem_data_0_1_s/DI[13]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 BSRAM_R82[10][A] u0_srio_response_gen/u0_sdpram_dat/mem_data_mem_data_0_1_s/CLKA
3.433 0.249 tHld 1 BSRAM_R82[10][A] u0_srio_response_gen/u0_sdpram_dat/mem_data_mem_data_0_1_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.248, 55.121%; tC2Q: 0.202, 44.879%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path18

Path Summary:

Slack 0.201
Data Arrival Time 3.634
Data Required Time 3.433
From u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo1_wdata_24_s0
To u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u1_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 R81C101[0][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo1_wdata_24_s0/CLK
3.386 0.202 tC2Q RR 1 R81C101[0][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo1_wdata_24_s0/Q
3.634 0.248 tNET RR 1 BSRAM_R82[19][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u1_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s/DI[24]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 BSRAM_R82[19][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u1_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s/CLKA
3.433 0.249 tHld 1 BSRAM_R82[19][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u1_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.248, 55.121%; tC2Q: 0.202, 44.879%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path19

Path Summary:

Slack 0.201
Data Arrival Time 3.634
Data Required Time 3.433
From u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo1_wdata_4_s0
To u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u1_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 R78C101[3][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo1_wdata_4_s0/CLK
3.386 0.202 tC2Q RR 1 R78C101[3][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo1_wdata_4_s0/Q
3.634 0.248 tNET RR 1 BSRAM_R82[19][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u1_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s/DI[4]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 BSRAM_R82[19][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u1_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s/CLKA
3.433 0.249 tHld 1 BSRAM_R82[19][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u1_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.248, 55.121%; tC2Q: 0.202, 44.879%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path20

Path Summary:

Slack 0.201
Data Arrival Time 3.634
Data Required Time 3.433
From u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo0_wdata_24_s0
To u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u0_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 R80C107[0][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo0_wdata_24_s0/CLK
3.386 0.202 tC2Q RR 1 R80C107[0][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo0_wdata_24_s0/Q
3.634 0.248 tNET RR 1 BSRAM_R82[20] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u0_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s/DI[24]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 BSRAM_R82[20] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u0_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s/CLKA
3.433 0.249 tHld 1 BSRAM_R82[20] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u0_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.248, 55.121%; tC2Q: 0.202, 44.879%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path21

Path Summary:

Slack 0.201
Data Arrival Time 3.634
Data Required Time 3.433
From u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo0_wdata_4_s0
To u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u0_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 R78C107[2][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo0_wdata_4_s0/CLK
3.386 0.202 tC2Q RR 1 R78C107[2][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/fifo0_wdata_4_s0/Q
3.634 0.248 tNET RR 1 BSRAM_R82[20] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u0_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s/DI[4]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 BSRAM_R82[20] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u0_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s/CLKA
3.433 0.249 tHld 1 BSRAM_R82[20] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_maints/u0_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.248, 55.121%; tC2Q: 0.202, 44.879%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path22

Path Summary:

Slack 0.201
Data Arrival Time 3.634
Data Required Time 3.433
From u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_resp_maints/o_tx_maint_resp_trac_fifo_wdata_54_s0
To u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_tx_maints/u1_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s
Launch Clk cfg_clk:[R]
Latch Clk cfg_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 cfg_clk
0.000 0.000 tCL RR 3711 PLL_R[3] u_gowin_pll/PLL_inst/CLKOUT0
3.184 3.184 tNET RR 1 R80C115[2][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_resp_maints/o_tx_maint_resp_trac_fifo_wdata_54_s0/CLK
3.386 0.202 tC2Q RR 2 R80C115[2][B] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_resp_maints/o_tx_maint_resp_trac_fifo_wdata_54_s0/Q
3.634 0.248 tNET RR 1 BSRAM_R82[22] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_tx_maints/u1_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s/DI[22]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 cfg_clk
0.000 0.000 tCL RR 3711 PLL_R[3] u_gowin_pll/PLL_inst/CLKOUT0
3.184 3.184 tNET RR 1 BSRAM_R82[22] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_tx_maints/u1_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s/CLKA
3.433 0.249 tHld 1 BSRAM_R82[22] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_tx_maints/u1_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.248, 55.121%; tC2Q: 0.202, 44.879%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path23

Path Summary:

Slack 0.201
Data Arrival Time 3.634
Data Required Time 3.433
From u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_resp_maints/o_tx_maint_resp_trac_fifo_wdata_12_s0
To u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_tx_maints/u1_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s
Launch Clk cfg_clk:[R]
Latch Clk cfg_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 cfg_clk
0.000 0.000 tCL RR 3711 PLL_R[3] u_gowin_pll/PLL_inst/CLKOUT0
3.184 3.184 tNET RR 1 R80C115[1][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_resp_maints/o_tx_maint_resp_trac_fifo_wdata_12_s0/CLK
3.386 0.202 tC2Q RR 1 R80C115[1][A] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_rx_resp_maints/o_tx_maint_resp_trac_fifo_wdata_12_s0/Q
3.634 0.248 tNET RR 1 BSRAM_R82[22] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_tx_maints/u1_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s/DI[12]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 cfg_clk
0.000 0.000 tCL RR 3711 PLL_R[3] u_gowin_pll/PLL_inst/CLKOUT0
3.184 3.184 tNET RR 1 BSRAM_R82[22] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_tx_maints/u1_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s/CLKA
3.433 0.249 tHld 1 BSRAM_R82[22] u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_maints_top/u_tx_maints/u1_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.248, 55.121%; tC2Q: 0.202, 44.879%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path24

Path Summary:

Slack 0.203
Data Arrival Time 3.636
Data Required Time 3.433
From u0_srio_response_gen/fifo_wdata_7_s0
To u0_srio_response_gen/u_fifo_top/fifo_sc_inst/mem_mem_0_0_s
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 R62C50[1][A] u0_srio_response_gen/fifo_wdata_7_s0/CLK
3.386 0.202 tC2Q RR 1 R62C50[1][A] u0_srio_response_gen/fifo_wdata_7_s0/Q
3.636 0.250 tNET RR 1 BSRAM_R64[10][A] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/mem_mem_0_0_s/DI[7]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 BSRAM_R64[10][A] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/mem_mem_0_0_s/CLKA
3.433 0.249 tHld 1 BSRAM_R64[10][A] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/mem_mem_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.250, 55.321%; tC2Q: 0.202, 44.679%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path25

Path Summary:

Slack 0.203
Data Arrival Time 3.636
Data Required Time 3.433
From u0_srio_response_gen/fifo_wdata_6_s0
To u0_srio_response_gen/u_fifo_top/fifo_sc_inst/mem_mem_0_0_s
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 R62C50[1][B] u0_srio_response_gen/fifo_wdata_6_s0/CLK
3.386 0.202 tC2Q RR 1 R62C50[1][B] u0_srio_response_gen/fifo_wdata_6_s0/Q
3.636 0.250 tNET RR 1 BSRAM_R64[10][A] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/mem_mem_0_0_s/DI[6]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 BSRAM_R64[10][A] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/mem_mem_0_0_s/CLKA
3.433 0.249 tHld 1 BSRAM_R64[10][A] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/mem_mem_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.250, 55.321%; tC2Q: 0.202, 44.679%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 10.154
Data Arrival Time 5.452
Data Required Time 15.605
From u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0
To u0_srio_response_gen/u_fifo_top/fifo_sc_inst/mem_mem_0_2_s
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.243 3.243 tNET RR 1 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/CLK
3.475 0.232 tC2Q RF 764 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q
5.452 1.976 tNET FF 16 BSRAM_R64[10][B] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/mem_mem_0_2_s/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.800 12.800 active clock edge time
12.800 0.000 srio_clk
12.800 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.043 3.243 tNET RR 1 BSRAM_R64[10][B] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/mem_mem_0_2_s/CLKB
15.605 -0.438 tSu 1 BSRAM_R64[10][B] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/mem_mem_0_2_s

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.800
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.976, 89.494%; tC2Q: 0.232, 10.506%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path2

Path Summary:

Slack 10.154
Data Arrival Time 5.452
Data Required Time 15.605
From u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0
To u0_srio_response_gen/u_fifo_top/fifo_sc_inst/mem_mem_0_0_s
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.243 3.243 tNET RR 1 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/CLK
3.475 0.232 tC2Q RF 764 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q
5.452 1.976 tNET FF 19 BSRAM_R64[10][A] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/mem_mem_0_0_s/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.800 12.800 active clock edge time
12.800 0.000 srio_clk
12.800 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.043 3.243 tNET RR 1 BSRAM_R64[10][A] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/mem_mem_0_0_s/CLKB
15.605 -0.438 tSu 1 BSRAM_R64[10][A] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/mem_mem_0_0_s

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.800
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.976, 89.494%; tC2Q: 0.232, 10.506%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path3

Path Summary:

Slack 10.154
Data Arrival Time 5.452
Data Required Time 15.605
From u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0
To u0_srio_request_gen/u_fifo_top/fifo_sc_inst/mem_mem_0_0_s
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.243 3.243 tNET RR 1 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/CLK
3.475 0.232 tC2Q RF 764 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q
5.452 1.976 tNET FF 12 BSRAM_R82[12][A] u0_srio_request_gen/u_fifo_top/fifo_sc_inst/mem_mem_0_0_s/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.800 12.800 active clock edge time
12.800 0.000 srio_clk
12.800 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.043 3.243 tNET RR 1 BSRAM_R82[12][A] u0_srio_request_gen/u_fifo_top/fifo_sc_inst/mem_mem_0_0_s/CLKB
15.605 -0.438 tSu 1 BSRAM_R82[12][A] u0_srio_request_gen/u_fifo_top/fifo_sc_inst/mem_mem_0_0_s

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.800
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.976, 89.494%; tC2Q: 0.232, 10.506%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path4

Path Summary:

Slack 10.544
Data Arrival Time 5.464
Data Required Time 16.008
From u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0
To u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_6_s0
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.243 3.243 tNET RR 1 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/CLK
3.475 0.232 tC2Q RF 764 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q
5.464 1.989 tNET FF 1 R53C53[0][B] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_6_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.800 12.800 active clock edge time
12.800 0.000 srio_clk
12.800 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.043 3.243 tNET RR 1 R53C53[0][B] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_6_s0/CLK
16.008 -0.035 tSu 1 R53C53[0][B] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_6_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.800
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.989, 89.554%; tC2Q: 0.232, 10.446%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path5

Path Summary:

Slack 10.544
Data Arrival Time 5.464
Data Required Time 16.008
From u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0
To u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_7_s0
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.243 3.243 tNET RR 1 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/CLK
3.475 0.232 tC2Q RF 764 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q
5.464 1.989 tNET FF 1 R53C53[1][A] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_7_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.800 12.800 active clock edge time
12.800 0.000 srio_clk
12.800 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.043 3.243 tNET RR 1 R53C53[1][A] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_7_s0/CLK
16.008 -0.035 tSu 1 R53C53[1][A] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_7_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.800
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.989, 89.554%; tC2Q: 0.232, 10.446%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path6

Path Summary:

Slack 10.544
Data Arrival Time 5.464
Data Required Time 16.008
From u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0
To u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_8_s0
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.243 3.243 tNET RR 1 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/CLK
3.475 0.232 tC2Q RF 764 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q
5.464 1.989 tNET FF 1 R53C54[2][A] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_8_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.800 12.800 active clock edge time
12.800 0.000 srio_clk
12.800 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.043 3.243 tNET RR 1 R53C54[2][A] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_8_s0/CLK
16.008 -0.035 tSu 1 R53C54[2][A] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_8_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.800
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.989, 89.554%; tC2Q: 0.232, 10.446%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path7

Path Summary:

Slack 10.544
Data Arrival Time 5.464
Data Required Time 16.008
From u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0
To u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_4_s0
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.243 3.243 tNET RR 1 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/CLK
3.475 0.232 tC2Q RF 764 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q
5.464 1.989 tNET FF 1 R53C53[2][A] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_4_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.800 12.800 active clock edge time
12.800 0.000 srio_clk
12.800 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.043 3.243 tNET RR 1 R53C53[2][A] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_4_s0/CLK
16.008 -0.035 tSu 1 R53C53[2][A] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_4_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.800
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.989, 89.554%; tC2Q: 0.232, 10.446%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path8

Path Summary:

Slack 10.544
Data Arrival Time 5.464
Data Required Time 16.008
From u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0
To u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_5_s0
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.243 3.243 tNET RR 1 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/CLK
3.475 0.232 tC2Q RF 764 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q
5.464 1.989 tNET FF 1 R53C53[1][B] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_5_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.800 12.800 active clock edge time
12.800 0.000 srio_clk
12.800 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.043 3.243 tNET RR 1 R53C53[1][B] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_5_s0/CLK
16.008 -0.035 tSu 1 R53C53[1][B] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_5_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.800
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.989, 89.554%; tC2Q: 0.232, 10.446%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path9

Path Summary:

Slack 10.544
Data Arrival Time 5.464
Data Required Time 16.008
From u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0
To u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_6_s0
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.243 3.243 tNET RR 1 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/CLK
3.475 0.232 tC2Q RF 764 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q
5.464 1.989 tNET FF 1 R53C54[1][B] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_6_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.800 12.800 active clock edge time
12.800 0.000 srio_clk
12.800 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.043 3.243 tNET RR 1 R53C54[1][B] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_6_s0/CLK
16.008 -0.035 tSu 1 R53C54[1][B] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_6_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.800
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.989, 89.554%; tC2Q: 0.232, 10.446%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path10

Path Summary:

Slack 10.544
Data Arrival Time 5.464
Data Required Time 16.008
From u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0
To u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_7_s0
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.243 3.243 tNET RR 1 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/CLK
3.475 0.232 tC2Q RF 764 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q
5.464 1.989 tNET FF 1 R53C54[1][A] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_7_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.800 12.800 active clock edge time
12.800 0.000 srio_clk
12.800 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.043 3.243 tNET RR 1 R53C54[1][A] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_7_s0/CLK
16.008 -0.035 tSu 1 R53C54[1][A] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_7_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.800
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.989, 89.554%; tC2Q: 0.232, 10.446%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path11

Path Summary:

Slack 10.544
Data Arrival Time 5.464
Data Required Time 16.008
From u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0
To u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_8_s0
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.243 3.243 tNET RR 1 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/CLK
3.475 0.232 tC2Q RF 764 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q
5.464 1.989 tNET FF 1 R53C54[0][B] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_8_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.800 12.800 active clock edge time
12.800 0.000 srio_clk
12.800 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.043 3.243 tNET RR 1 R53C54[0][B] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_8_s0/CLK
16.008 -0.035 tSu 1 R53C54[0][B] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_8_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.800
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.989, 89.554%; tC2Q: 0.232, 10.446%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path12

Path Summary:

Slack 10.544
Data Arrival Time 5.464
Data Required Time 16.008
From u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0
To u0_srio_request_gen/u_fifo_top/fifo_sc_inst/wbin_2_s0
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.243 3.243 tNET RR 1 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/CLK
3.475 0.232 tC2Q RF 764 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q
5.464 1.989 tNET FF 1 R72C57[2][B] u0_srio_request_gen/u_fifo_top/fifo_sc_inst/wbin_2_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.800 12.800 active clock edge time
12.800 0.000 srio_clk
12.800 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.043 3.243 tNET RR 1 R72C57[2][B] u0_srio_request_gen/u_fifo_top/fifo_sc_inst/wbin_2_s0/CLK
16.008 -0.035 tSu 1 R72C57[2][B] u0_srio_request_gen/u_fifo_top/fifo_sc_inst/wbin_2_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.800
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.989, 89.554%; tC2Q: 0.232, 10.446%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path13

Path Summary:

Slack 10.544
Data Arrival Time 5.464
Data Required Time 16.008
From u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0
To u0_srio_request_gen/u_fifo_top/fifo_sc_inst/wbin_3_s0
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.243 3.243 tNET RR 1 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/CLK
3.475 0.232 tC2Q RF 764 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q
5.464 1.989 tNET FF 1 R71C58[0][A] u0_srio_request_gen/u_fifo_top/fifo_sc_inst/wbin_3_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.800 12.800 active clock edge time
12.800 0.000 srio_clk
12.800 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.043 3.243 tNET RR 1 R71C58[0][A] u0_srio_request_gen/u_fifo_top/fifo_sc_inst/wbin_3_s0/CLK
16.008 -0.035 tSu 1 R71C58[0][A] u0_srio_request_gen/u_fifo_top/fifo_sc_inst/wbin_3_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.800
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.989, 89.554%; tC2Q: 0.232, 10.446%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path14

Path Summary:

Slack 10.544
Data Arrival Time 5.464
Data Required Time 16.008
From u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0
To u0_srio_request_gen/u_fifo_top/fifo_sc_inst/wbin_4_s0
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.243 3.243 tNET RR 1 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/CLK
3.475 0.232 tC2Q RF 764 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q
5.464 1.989 tNET FF 1 R72C57[1][B] u0_srio_request_gen/u_fifo_top/fifo_sc_inst/wbin_4_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.800 12.800 active clock edge time
12.800 0.000 srio_clk
12.800 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.043 3.243 tNET RR 1 R72C57[1][B] u0_srio_request_gen/u_fifo_top/fifo_sc_inst/wbin_4_s0/CLK
16.008 -0.035 tSu 1 R72C57[1][B] u0_srio_request_gen/u_fifo_top/fifo_sc_inst/wbin_4_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.800
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.989, 89.554%; tC2Q: 0.232, 10.446%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path15

Path Summary:

Slack 10.544
Data Arrival Time 5.464
Data Required Time 16.008
From u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0
To u0_srio_request_gen/u_fifo_top/fifo_sc_inst/wbin_5_s0
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.243 3.243 tNET RR 1 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/CLK
3.475 0.232 tC2Q RF 764 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q
5.464 1.989 tNET FF 1 R71C58[1][A] u0_srio_request_gen/u_fifo_top/fifo_sc_inst/wbin_5_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.800 12.800 active clock edge time
12.800 0.000 srio_clk
12.800 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.043 3.243 tNET RR 1 R71C58[1][A] u0_srio_request_gen/u_fifo_top/fifo_sc_inst/wbin_5_s0/CLK
16.008 -0.035 tSu 1 R71C58[1][A] u0_srio_request_gen/u_fifo_top/fifo_sc_inst/wbin_5_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.800
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.989, 89.554%; tC2Q: 0.232, 10.446%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path16

Path Summary:

Slack 10.544
Data Arrival Time 5.464
Data Required Time 16.008
From u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0
To u0_srio_request_gen/u_fifo_top/fifo_sc_inst/wbin_6_s0
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.243 3.243 tNET RR 1 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/CLK
3.475 0.232 tC2Q RF 764 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q
5.464 1.989 tNET FF 1 R71C58[0][B] u0_srio_request_gen/u_fifo_top/fifo_sc_inst/wbin_6_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.800 12.800 active clock edge time
12.800 0.000 srio_clk
12.800 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.043 3.243 tNET RR 1 R71C58[0][B] u0_srio_request_gen/u_fifo_top/fifo_sc_inst/wbin_6_s0/CLK
16.008 -0.035 tSu 1 R71C58[0][B] u0_srio_request_gen/u_fifo_top/fifo_sc_inst/wbin_6_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.800
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.989, 89.554%; tC2Q: 0.232, 10.446%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path17

Path Summary:

Slack 10.544
Data Arrival Time 5.464
Data Required Time 16.008
From u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0
To u0_srio_request_gen/u_fifo_top/fifo_sc_inst/wbin_7_s0
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.243 3.243 tNET RR 1 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/CLK
3.475 0.232 tC2Q RF 764 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q
5.464 1.989 tNET FF 1 R71C58[2][B] u0_srio_request_gen/u_fifo_top/fifo_sc_inst/wbin_7_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.800 12.800 active clock edge time
12.800 0.000 srio_clk
12.800 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.043 3.243 tNET RR 1 R71C58[2][B] u0_srio_request_gen/u_fifo_top/fifo_sc_inst/wbin_7_s0/CLK
16.008 -0.035 tSu 1 R71C58[2][B] u0_srio_request_gen/u_fifo_top/fifo_sc_inst/wbin_7_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.800
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.989, 89.554%; tC2Q: 0.232, 10.446%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path18

Path Summary:

Slack 10.544
Data Arrival Time 5.464
Data Required Time 16.008
From u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0
To u0_srio_request_gen/u_fifo_top/fifo_sc_inst/wbin_9_s0
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.243 3.243 tNET RR 1 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/CLK
3.475 0.232 tC2Q RF 764 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q
5.464 1.989 tNET FF 1 R71C58[1][B] u0_srio_request_gen/u_fifo_top/fifo_sc_inst/wbin_9_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.800 12.800 active clock edge time
12.800 0.000 srio_clk
12.800 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.043 3.243 tNET RR 1 R71C58[1][B] u0_srio_request_gen/u_fifo_top/fifo_sc_inst/wbin_9_s0/CLK
16.008 -0.035 tSu 1 R71C58[1][B] u0_srio_request_gen/u_fifo_top/fifo_sc_inst/wbin_9_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.800
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.989, 89.554%; tC2Q: 0.232, 10.446%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path19

Path Summary:

Slack 10.544
Data Arrival Time 5.464
Data Required Time 16.008
From u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0
To u0_srio_request_gen/u_fifo_top/fifo_sc_inst/rbin_2_s0
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.243 3.243 tNET RR 1 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/CLK
3.475 0.232 tC2Q RF 764 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q
5.464 1.989 tNET FF 1 R72C57[0][A] u0_srio_request_gen/u_fifo_top/fifo_sc_inst/rbin_2_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.800 12.800 active clock edge time
12.800 0.000 srio_clk
12.800 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.043 3.243 tNET RR 1 R72C57[0][A] u0_srio_request_gen/u_fifo_top/fifo_sc_inst/rbin_2_s0/CLK
16.008 -0.035 tSu 1 R72C57[0][A] u0_srio_request_gen/u_fifo_top/fifo_sc_inst/rbin_2_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.800
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.989, 89.554%; tC2Q: 0.232, 10.446%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path20

Path Summary:

Slack 10.550
Data Arrival Time 5.458
Data Required Time 16.008
From u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0
To u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_0_s0
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.243 3.243 tNET RR 1 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/CLK
3.475 0.232 tC2Q RF 764 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q
5.458 1.983 tNET FF 1 R53C52[1][A] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.800 12.800 active clock edge time
12.800 0.000 srio_clk
12.800 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.043 3.243 tNET RR 1 R53C52[1][A] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_0_s0/CLK
16.008 -0.035 tSu 1 R53C52[1][A] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_0_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.800
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.983, 89.524%; tC2Q: 0.232, 10.476%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path21

Path Summary:

Slack 10.550
Data Arrival Time 5.458
Data Required Time 16.008
From u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0
To u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_1_s0
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.243 3.243 tNET RR 1 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/CLK
3.475 0.232 tC2Q RF 764 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q
5.458 1.983 tNET FF 1 R53C52[0][B] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.800 12.800 active clock edge time
12.800 0.000 srio_clk
12.800 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.043 3.243 tNET RR 1 R53C52[0][B] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_1_s0/CLK
16.008 -0.035 tSu 1 R53C52[0][B] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_1_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.800
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.983, 89.524%; tC2Q: 0.232, 10.476%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path22

Path Summary:

Slack 10.550
Data Arrival Time 5.458
Data Required Time 16.008
From u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0
To u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_3_s0
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.243 3.243 tNET RR 1 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/CLK
3.475 0.232 tC2Q RF 764 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q
5.458 1.983 tNET FF 1 R52C51[3][A] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_3_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.800 12.800 active clock edge time
12.800 0.000 srio_clk
12.800 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.043 3.243 tNET RR 1 R52C51[3][A] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_3_s0/CLK
16.008 -0.035 tSu 1 R52C51[3][A] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_3_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.800
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.983, 89.524%; tC2Q: 0.232, 10.476%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path23

Path Summary:

Slack 10.550
Data Arrival Time 5.458
Data Required Time 16.008
From u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0
To u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_4_s0
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.243 3.243 tNET RR 1 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/CLK
3.475 0.232 tC2Q RF 764 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q
5.458 1.983 tNET FF 1 R52C51[0][A] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_4_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.800 12.800 active clock edge time
12.800 0.000 srio_clk
12.800 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.043 3.243 tNET RR 1 R52C51[0][A] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_4_s0/CLK
16.008 -0.035 tSu 1 R52C51[0][A] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_4_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.800
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.983, 89.524%; tC2Q: 0.232, 10.476%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path24

Path Summary:

Slack 10.550
Data Arrival Time 5.458
Data Required Time 16.008
From u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0
To u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_0_s0
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.243 3.243 tNET RR 1 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/CLK
3.475 0.232 tC2Q RF 764 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q
5.458 1.983 tNET FF 1 R52C52[1][A] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.800 12.800 active clock edge time
12.800 0.000 srio_clk
12.800 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.043 3.243 tNET RR 1 R52C52[1][A] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_0_s0/CLK
16.008 -0.035 tSu 1 R52C52[1][A] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_0_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.800
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.983, 89.524%; tC2Q: 0.232, 10.476%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path25

Path Summary:

Slack 10.550
Data Arrival Time 5.458
Data Required Time 16.008
From u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0
To u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_1_s0
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.243 3.243 tNET RR 1 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/CLK
3.475 0.232 tC2Q RF 764 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q
5.458 1.983 tNET FF 1 R52C52[0][B] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.800 12.800 active clock edge time
12.800 0.000 srio_clk
12.800 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
16.043 3.243 tNET RR 1 R52C52[0][B] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_1_s0/CLK
16.008 -0.035 tSu 1 R52C52[0][B] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_1_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.800
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.983, 89.524%; tC2Q: 0.232, 10.476%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 1.506
Data Arrival Time 4.702
Data Required Time 3.196
From u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0
To u0_srio_response_gen/u_fifo_top/fifo_sc_inst/mem_mem_0_2_s
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/CLK
3.386 0.202 tC2Q RR 764 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q
4.702 1.316 tNET RR 16 BSRAM_R64[10][B] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/mem_mem_0_2_s/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 BSRAM_R64[10][B] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/mem_mem_0_2_s/CLKB
3.196 0.012 tHld 1 BSRAM_R64[10][B] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/mem_mem_0_2_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.316, 86.695%; tC2Q: 0.202, 13.305%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path2

Path Summary:

Slack 1.506
Data Arrival Time 4.702
Data Required Time 3.196
From u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0
To u0_srio_response_gen/u_fifo_top/fifo_sc_inst/mem_mem_0_0_s
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/CLK
3.386 0.202 tC2Q RR 764 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q
4.702 1.316 tNET RR 19 BSRAM_R64[10][A] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/mem_mem_0_0_s/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 BSRAM_R64[10][A] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/mem_mem_0_0_s/CLKB
3.196 0.012 tHld 1 BSRAM_R64[10][A] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/mem_mem_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.316, 86.695%; tC2Q: 0.202, 13.305%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path3

Path Summary:

Slack 1.506
Data Arrival Time 4.702
Data Required Time 3.196
From u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0
To u0_srio_request_gen/u_fifo_top/fifo_sc_inst/mem_mem_0_0_s
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/CLK
3.386 0.202 tC2Q RR 764 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q
4.702 1.316 tNET RR 12 BSRAM_R82[12][A] u0_srio_request_gen/u_fifo_top/fifo_sc_inst/mem_mem_0_0_s/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 BSRAM_R82[12][A] u0_srio_request_gen/u_fifo_top/fifo_sc_inst/mem_mem_0_0_s/CLKB
3.196 0.012 tHld 1 BSRAM_R82[12][A] u0_srio_request_gen/u_fifo_top/fifo_sc_inst/mem_mem_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.316, 86.695%; tC2Q: 0.202, 13.305%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path4

Path Summary:

Slack 1.507
Data Arrival Time 4.702
Data Required Time 3.195
From u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0
To u0_srio_response_gen/u_fifo_top/fifo_sc_inst/Empty_s0
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/CLK
3.386 0.202 tC2Q RR 764 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q
4.702 1.316 tNET RR 1 R52C54[1][A] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/Empty_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 R52C54[1][A] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/Empty_s0/CLK
3.195 0.011 tHld 1 R52C54[1][A] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/Empty_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.316, 86.695%; tC2Q: 0.202, 13.305%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path5

Path Summary:

Slack 1.507
Data Arrival Time 4.702
Data Required Time 3.195
From u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0
To u0_srio_response_gen/u_fifo_top/fifo_sc_inst/Almost_Full_s0
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/CLK
3.386 0.202 tC2Q RR 764 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q
4.702 1.316 tNET RR 1 R54C53[3][A] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/Almost_Full_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 R54C53[3][A] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/Almost_Full_s0/CLK
3.195 0.011 tHld 1 R54C53[3][A] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/Almost_Full_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.316, 86.695%; tC2Q: 0.202, 13.305%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path6

Path Summary:

Slack 1.507
Data Arrival Time 4.702
Data Required Time 3.195
From u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0
To u0_srio_response_gen/u_fifo_top/fifo_sc_inst/Full_s0
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/CLK
3.386 0.202 tC2Q RR 764 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q
4.702 1.316 tNET RR 1 R52C53[2][B] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/Full_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 R52C53[2][B] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/Full_s0/CLK
3.195 0.011 tHld 1 R52C53[2][B] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/Full_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.316, 86.695%; tC2Q: 0.202, 13.305%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path7

Path Summary:

Slack 1.507
Data Arrival Time 4.702
Data Required Time 3.195
From u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0
To u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_2_s0
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/CLK
3.386 0.202 tC2Q RR 764 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q
4.702 1.316 tNET RR 1 R52C50[0][B] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_2_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 R52C50[0][B] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_2_s0/CLK
3.195 0.011 tHld 1 R52C50[0][B] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_2_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.316, 86.695%; tC2Q: 0.202, 13.305%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path8

Path Summary:

Slack 1.507
Data Arrival Time 4.702
Data Required Time 3.195
From u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0
To u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_5_s0
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/CLK
3.386 0.202 tC2Q RR 764 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q
4.702 1.316 tNET RR 1 R53C51[0][A] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_5_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 R53C51[0][A] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_5_s0/CLK
3.195 0.011 tHld 1 R53C51[0][A] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_5_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.316, 86.695%; tC2Q: 0.202, 13.305%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path9

Path Summary:

Slack 1.507
Data Arrival Time 4.702
Data Required Time 3.195
From u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0
To u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_9_s0
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/CLK
3.386 0.202 tC2Q RR 764 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q
4.702 1.316 tNET RR 1 R56C53[0][A] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_9_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 R56C53[0][A] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_9_s0/CLK
3.195 0.011 tHld 1 R56C53[0][A] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_9_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.316, 86.695%; tC2Q: 0.202, 13.305%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path10

Path Summary:

Slack 1.507
Data Arrival Time 4.702
Data Required Time 3.195
From u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0
To u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_2_s0
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/CLK
3.386 0.202 tC2Q RR 764 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q
4.702 1.316 tNET RR 1 R53C51[0][B] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_2_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 R53C51[0][B] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_2_s0/CLK
3.195 0.011 tHld 1 R53C51[0][B] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_2_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.316, 86.695%; tC2Q: 0.202, 13.305%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path11

Path Summary:

Slack 1.507
Data Arrival Time 4.702
Data Required Time 3.195
From u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0
To u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_9_s0
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/CLK
3.386 0.202 tC2Q RR 764 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q
4.702 1.316 tNET RR 1 R52C55[3][A] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_9_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 R52C55[3][A] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_9_s0/CLK
3.195 0.011 tHld 1 R52C55[3][A] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/rbin_9_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.316, 86.695%; tC2Q: 0.202, 13.305%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path12

Path Summary:

Slack 1.507
Data Arrival Time 4.702
Data Required Time 3.195
From u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0
To u0_srio_request_gen/u_fifo_top/fifo_sc_inst/Empty_s0
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/CLK
3.386 0.202 tC2Q RR 764 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q
4.702 1.316 tNET RR 1 R72C58[0][B] u0_srio_request_gen/u_fifo_top/fifo_sc_inst/Empty_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 R72C58[0][B] u0_srio_request_gen/u_fifo_top/fifo_sc_inst/Empty_s0/CLK
3.195 0.011 tHld 1 R72C58[0][B] u0_srio_request_gen/u_fifo_top/fifo_sc_inst/Empty_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.316, 86.695%; tC2Q: 0.202, 13.305%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path13

Path Summary:

Slack 1.507
Data Arrival Time 4.702
Data Required Time 3.195
From u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0
To u0_srio_request_gen/u_fifo_top/fifo_sc_inst/Almost_Full_s0
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/CLK
3.386 0.202 tC2Q RR 764 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q
4.702 1.316 tNET RR 1 R75C57[3][A] u0_srio_request_gen/u_fifo_top/fifo_sc_inst/Almost_Full_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 R75C57[3][A] u0_srio_request_gen/u_fifo_top/fifo_sc_inst/Almost_Full_s0/CLK
3.195 0.011 tHld 1 R75C57[3][A] u0_srio_request_gen/u_fifo_top/fifo_sc_inst/Almost_Full_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.316, 86.695%; tC2Q: 0.202, 13.305%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path14

Path Summary:

Slack 1.507
Data Arrival Time 4.702
Data Required Time 3.195
From u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0
To u0_srio_request_gen/u_fifo_top/fifo_sc_inst/Full_s0
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/CLK
3.386 0.202 tC2Q RR 764 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q
4.702 1.316 tNET RR 1 R71C59[1][B] u0_srio_request_gen/u_fifo_top/fifo_sc_inst/Full_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 R71C59[1][B] u0_srio_request_gen/u_fifo_top/fifo_sc_inst/Full_s0/CLK
3.195 0.011 tHld 1 R71C59[1][B] u0_srio_request_gen/u_fifo_top/fifo_sc_inst/Full_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.316, 86.695%; tC2Q: 0.202, 13.305%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path15

Path Summary:

Slack 1.507
Data Arrival Time 4.702
Data Required Time 3.195
From u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0
To u0_srio_request_gen/u_fifo_top/fifo_sc_inst/wbin_8_s0
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/CLK
3.386 0.202 tC2Q RR 764 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q
4.702 1.316 tNET RR 1 R74C58[2][A] u0_srio_request_gen/u_fifo_top/fifo_sc_inst/wbin_8_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 R74C58[2][A] u0_srio_request_gen/u_fifo_top/fifo_sc_inst/wbin_8_s0/CLK
3.195 0.011 tHld 1 R74C58[2][A] u0_srio_request_gen/u_fifo_top/fifo_sc_inst/wbin_8_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.316, 86.695%; tC2Q: 0.202, 13.305%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path16

Path Summary:

Slack 1.507
Data Arrival Time 4.702
Data Required Time 3.195
From u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0
To u0_srio_request_gen/u_fifo_top/fifo_sc_inst/rbin_0_s0
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/CLK
3.386 0.202 tC2Q RR 764 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q
4.702 1.316 tNET RR 1 R74C56[2][A] u0_srio_request_gen/u_fifo_top/fifo_sc_inst/rbin_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 R74C56[2][A] u0_srio_request_gen/u_fifo_top/fifo_sc_inst/rbin_0_s0/CLK
3.195 0.011 tHld 1 R74C56[2][A] u0_srio_request_gen/u_fifo_top/fifo_sc_inst/rbin_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.316, 86.695%; tC2Q: 0.202, 13.305%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path17

Path Summary:

Slack 1.507
Data Arrival Time 4.702
Data Required Time 3.195
From u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0
To u0_srio_request_gen/u_fifo_top/fifo_sc_inst/rbin_1_s0
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/CLK
3.386 0.202 tC2Q RR 764 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q
4.702 1.316 tNET RR 1 R74C57[3][A] u0_srio_request_gen/u_fifo_top/fifo_sc_inst/rbin_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 R74C57[3][A] u0_srio_request_gen/u_fifo_top/fifo_sc_inst/rbin_1_s0/CLK
3.195 0.011 tHld 1 R74C57[3][A] u0_srio_request_gen/u_fifo_top/fifo_sc_inst/rbin_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.316, 86.695%; tC2Q: 0.202, 13.305%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path18

Path Summary:

Slack 1.507
Data Arrival Time 4.702
Data Required Time 3.195
From u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0
To u0_srio_request_gen/u_fifo_top/fifo_sc_inst/rbin_4_s0
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/CLK
3.386 0.202 tC2Q RR 764 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q
4.702 1.316 tNET RR 1 R74C59[2][B] u0_srio_request_gen/u_fifo_top/fifo_sc_inst/rbin_4_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 R74C59[2][B] u0_srio_request_gen/u_fifo_top/fifo_sc_inst/rbin_4_s0/CLK
3.195 0.011 tHld 1 R74C59[2][B] u0_srio_request_gen/u_fifo_top/fifo_sc_inst/rbin_4_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.316, 86.695%; tC2Q: 0.202, 13.305%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path19

Path Summary:

Slack 1.507
Data Arrival Time 4.702
Data Required Time 3.195
From u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0
To u0_srio_request_gen/u_fifo_top/fifo_sc_inst/rbin_5_s0
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/CLK
3.386 0.202 tC2Q RR 764 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q
4.702 1.316 tNET RR 1 R75C58[2][B] u0_srio_request_gen/u_fifo_top/fifo_sc_inst/rbin_5_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 R75C58[2][B] u0_srio_request_gen/u_fifo_top/fifo_sc_inst/rbin_5_s0/CLK
3.195 0.011 tHld 1 R75C58[2][B] u0_srio_request_gen/u_fifo_top/fifo_sc_inst/rbin_5_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.316, 86.695%; tC2Q: 0.202, 13.305%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path20

Path Summary:

Slack 1.507
Data Arrival Time 4.702
Data Required Time 3.195
From u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0
To u0_srio_request_gen/u_fifo_top/fifo_sc_inst/rbin_6_s0
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/CLK
3.386 0.202 tC2Q RR 764 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q
4.702 1.316 tNET RR 1 R75C58[2][A] u0_srio_request_gen/u_fifo_top/fifo_sc_inst/rbin_6_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 R75C58[2][A] u0_srio_request_gen/u_fifo_top/fifo_sc_inst/rbin_6_s0/CLK
3.195 0.011 tHld 1 R75C58[2][A] u0_srio_request_gen/u_fifo_top/fifo_sc_inst/rbin_6_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.316, 86.695%; tC2Q: 0.202, 13.305%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path21

Path Summary:

Slack 1.507
Data Arrival Time 4.702
Data Required Time 3.195
From u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0
To u0_srio_request_gen/u_fifo_top/fifo_sc_inst/rbin_9_s0
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/CLK
3.386 0.202 tC2Q RR 764 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q
4.702 1.316 tNET RR 1 R72C58[0][A] u0_srio_request_gen/u_fifo_top/fifo_sc_inst/rbin_9_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 R72C58[0][A] u0_srio_request_gen/u_fifo_top/fifo_sc_inst/rbin_9_s0/CLK
3.195 0.011 tHld 1 R72C58[0][A] u0_srio_request_gen/u_fifo_top/fifo_sc_inst/rbin_9_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.316, 86.695%; tC2Q: 0.202, 13.305%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path22

Path Summary:

Slack 1.512
Data Arrival Time 4.707
Data Required Time 3.195
From u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0
To u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_0_s0
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/CLK
3.386 0.202 tC2Q RR 764 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q
4.707 1.321 tNET RR 1 R53C52[1][A] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 R53C52[1][A] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_0_s0/CLK
3.195 0.011 tHld 1 R53C52[1][A] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.321, 86.734%; tC2Q: 0.202, 13.266%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path23

Path Summary:

Slack 1.512
Data Arrival Time 4.707
Data Required Time 3.195
From u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0
To u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_1_s0
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/CLK
3.386 0.202 tC2Q RR 764 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q
4.707 1.321 tNET RR 1 R53C52[0][B] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 R53C52[0][B] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_1_s0/CLK
3.195 0.011 tHld 1 R53C52[0][B] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.321, 86.734%; tC2Q: 0.202, 13.266%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path24

Path Summary:

Slack 1.512
Data Arrival Time 4.707
Data Required Time 3.195
From u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0
To u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_3_s0
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/CLK
3.386 0.202 tC2Q RR 764 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q
4.707 1.321 tNET RR 1 R52C51[3][A] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_3_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 R52C51[3][A] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_3_s0/CLK
3.195 0.011 tHld 1 R52C51[3][A] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_3_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.321, 86.734%; tC2Q: 0.202, 13.266%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path25

Path Summary:

Slack 1.512
Data Arrival Time 4.707
Data Required Time 3.195
From u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0
To u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_4_s0
Launch Clk srio_clk:[R]
Latch Clk srio_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/CLK
3.386 0.202 tC2Q RR 764 R52C109[1][A] u_Serdes_Top/SRIO_Top_inst/srio_rst_srl_2_s0/Q
4.707 1.321 tNET RR 1 R52C51[0][A] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_4_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 srio_clk
0.000 0.000 tCL RR 7250 PLL_L[0] u_gowin_serdes_pll/PLL_inst/CLKOUT1
3.184 3.184 tNET RR 1 R52C51[0][A] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_4_s0/CLK
3.195 0.011 tHld 1 R52C51[0][A] u0_srio_response_gen/u_fifo_top/fifo_sc_inst/wbin_4_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.321, 86.734%; tC2Q: 0.202, 13.266%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack: 5.323
Actual Width: 6.323
Required Width: 1.000
Type: Low Pulse Width
Clock: srio_clk
Objects: test_start_1d_s1

Late clock Path:

AT DELAY TYPE RF NODE
6.400 0.000 active clock edge time
6.400 0.000 srio_clk
6.400 0.000 tCL FF u_gowin_serdes_pll/PLL_inst/CLKOUT1
9.661 3.261 tNET FF test_start_1d_s1/CLK

Early clock Path:

AT DELAY TYPE RF NODE
12.800 0.000 active clock edge time
12.800 0.000 srio_clk
12.800 0.000 tCL RR u_gowin_serdes_pll/PLL_inst/CLKOUT1
15.984 3.184 tNET RR test_start_1d_s1/CLK

MPW2

MPW Summary:

Slack: 5.323
Actual Width: 6.323
Required Width: 1.000
Type: Low Pulse Width
Clock: srio_clk
Objects: test_start_2d_s1

Late clock Path:

AT DELAY TYPE RF NODE
6.400 0.000 active clock edge time
6.400 0.000 srio_clk
6.400 0.000 tCL FF u_gowin_serdes_pll/PLL_inst/CLKOUT1
9.661 3.261 tNET FF test_start_2d_s1/CLK

Early clock Path:

AT DELAY TYPE RF NODE
12.800 0.000 active clock edge time
12.800 0.000 srio_clk
12.800 0.000 tCL RR u_gowin_serdes_pll/PLL_inst/CLKOUT1
15.984 3.184 tNET RR test_start_2d_s1/CLK

MPW3

MPW Summary:

Slack: 5.323
Actual Width: 6.323
Required Width: 1.000
Type: Low Pulse Width
Clock: srio_clk
Objects: sw_start_1d_s0

Late clock Path:

AT DELAY TYPE RF NODE
6.400 0.000 active clock edge time
6.400 0.000 srio_clk
6.400 0.000 tCL FF u_gowin_serdes_pll/PLL_inst/CLKOUT1
9.661 3.261 tNET FF sw_start_1d_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
12.800 0.000 active clock edge time
12.800 0.000 srio_clk
12.800 0.000 tCL RR u_gowin_serdes_pll/PLL_inst/CLKOUT1
15.984 3.184 tNET RR sw_start_1d_s0/CLK

MPW4

MPW Summary:

Slack: 5.323
Actual Width: 6.323
Required Width: 1.000
Type: Low Pulse Width
Clock: srio_clk
Objects: u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/stage1_reg[0]_8_s0

Late clock Path:

AT DELAY TYPE RF NODE
6.400 0.000 active clock edge time
6.400 0.000 srio_clk
6.400 0.000 tCL FF u_gowin_serdes_pll/PLL_inst/CLKOUT1
9.661 3.261 tNET FF u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/stage1_reg[0]_8_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
12.800 0.000 active clock edge time
12.800 0.000 srio_clk
12.800 0.000 tCL RR u_gowin_serdes_pll/PLL_inst/CLKOUT1
15.984 3.184 tNET RR u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/stage1_reg[0]_8_s0/CLK

MPW5

MPW Summary:

Slack: 5.323
Actual Width: 6.323
Required Width: 1.000
Type: Low Pulse Width
Clock: srio_clk
Objects: u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/stage1_reg[2]_42_s0

Late clock Path:

AT DELAY TYPE RF NODE
6.400 0.000 active clock edge time
6.400 0.000 srio_clk
6.400 0.000 tCL FF u_gowin_serdes_pll/PLL_inst/CLKOUT1
9.661 3.261 tNET FF u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/stage1_reg[2]_42_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
12.800 0.000 active clock edge time
12.800 0.000 srio_clk
12.800 0.000 tCL RR u_gowin_serdes_pll/PLL_inst/CLKOUT1
15.984 3.184 tNET RR u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/stage1_reg[2]_42_s0/CLK

MPW6

MPW Summary:

Slack: 5.323
Actual Width: 6.323
Required Width: 1.000
Type: Low Pulse Width
Clock: srio_clk
Objects: u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/stage1_reg[3]_59_s0

Late clock Path:

AT DELAY TYPE RF NODE
6.400 0.000 active clock edge time
6.400 0.000 srio_clk
6.400 0.000 tCL FF u_gowin_serdes_pll/PLL_inst/CLKOUT1
9.661 3.261 tNET FF u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/stage1_reg[3]_59_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
12.800 0.000 active clock edge time
12.800 0.000 srio_clk
12.800 0.000 tCL RR u_gowin_serdes_pll/PLL_inst/CLKOUT1
15.984 3.184 tNET RR u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/stage1_reg[3]_59_s0/CLK

MPW7

MPW Summary:

Slack: 5.323
Actual Width: 6.323
Required Width: 1.000
Type: Low Pulse Width
Clock: srio_clk
Objects: u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/stage1_reg[3]_27_s0

Late clock Path:

AT DELAY TYPE RF NODE
6.400 0.000 active clock edge time
6.400 0.000 srio_clk
6.400 0.000 tCL FF u_gowin_serdes_pll/PLL_inst/CLKOUT1
9.661 3.261 tNET FF u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/stage1_reg[3]_27_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
12.800 0.000 active clock edge time
12.800 0.000 srio_clk
12.800 0.000 tCL RR u_gowin_serdes_pll/PLL_inst/CLKOUT1
15.984 3.184 tNET RR u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/stage1_reg[3]_27_s0/CLK

MPW8

MPW Summary:

Slack: 5.323
Actual Width: 6.323
Required Width: 1.000
Type: Low Pulse Width
Clock: srio_clk
Objects: u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/stage1_reg[3]_11_s0

Late clock Path:

AT DELAY TYPE RF NODE
6.400 0.000 active clock edge time
6.400 0.000 srio_clk
6.400 0.000 tCL FF u_gowin_serdes_pll/PLL_inst/CLKOUT1
9.661 3.261 tNET FF u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/stage1_reg[3]_11_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
12.800 0.000 active clock edge time
12.800 0.000 srio_clk
12.800 0.000 tCL RR u_gowin_serdes_pll/PLL_inst/CLKOUT1
15.984 3.184 tNET RR u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/stage1_reg[3]_11_s0/CLK

MPW9

MPW Summary:

Slack: 5.323
Actual Width: 6.323
Required Width: 1.000
Type: Low Pulse Width
Clock: srio_clk
Objects: u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/stage1_reg[3]_3_s0

Late clock Path:

AT DELAY TYPE RF NODE
6.400 0.000 active clock edge time
6.400 0.000 srio_clk
6.400 0.000 tCL FF u_gowin_serdes_pll/PLL_inst/CLKOUT1
9.661 3.261 tNET FF u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/stage1_reg[3]_3_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
12.800 0.000 active clock edge time
12.800 0.000 srio_clk
12.800 0.000 tCL RR u_gowin_serdes_pll/PLL_inst/CLKOUT1
15.984 3.184 tNET RR u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/stage1_reg[3]_3_s0/CLK

MPW10

MPW Summary:

Slack: 5.323
Actual Width: 6.323
Required Width: 1.000
Type: Low Pulse Width
Clock: srio_clk
Objects: u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/stage1_reg_last_3_s0

Late clock Path:

AT DELAY TYPE RF NODE
6.400 0.000 active clock edge time
6.400 0.000 srio_clk
6.400 0.000 tCL FF u_gowin_serdes_pll/PLL_inst/CLKOUT1
9.661 3.261 tNET FF u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/stage1_reg_last_3_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
12.800 0.000 active clock edge time
12.800 0.000 srio_clk
12.800 0.000 tCL RR u_gowin_serdes_pll/PLL_inst/CLKOUT1
15.984 3.184 tNET RR u_Serdes_Top/SRIO_Top_inst/u_srio_core/u_srio_log_top/u_log_tx/u_log_tx_arb/stage1_reg_last_3_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT NET NAME WORST SLACK MAX DELAY
7250 srio_clk 1.105 3.261
3711 clk_10m 87.388 3.261
1056 cfg_rst_srl[2] 94.089 2.911
764 srio_ui_rst 8.001 1.989
260 rd_ptr[2] 95.365 1.918
256 rd_ptr[2] 94.339 3.279
171 win_index[0] 1.661 2.781
163 byte_align_pos[2] 9.696 1.745
162 byte_align_pos[3] 9.295 2.293
156 stage1_reg_start 3.917 2.373

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC ROUTE CONGESTIONS
R54C103 76.39%
R58C105 76.39%
R59C103 75.00%
R68C128 75.00%
R60C97 72.22%
R63C129 72.22%
R58C97 70.83%
R59C105 70.83%
R57C100 70.83%
R69C128 70.83%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type State Detail Command
TC_CLOCK Actived create_clock -name srio_clk -period 12.8 -waveform {0 6.4} [get_nets {srio_clk}]
TC_CLOCK Actived create_clock -name cfg_clk -period 100 -waveform {0 50} [get_nets {clk_10m}]
TC_CLOCK Actived create_clock -name pll_ref_clk -period 20 -waveform {0 10} [get_ports {sys_clk_i}]
TC_FALSE_PATH Actived set_false_path -from [get_clocks {srio_clk}] -to [get_clocks {cfg_clk}]
TC_FALSE_PATH Actived set_false_path -from [get_clocks {cfg_clk}] -to [get_clocks {srio_clk}]