Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\TDC\data\tdc_wrapper.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\TDC\data\tdc.v |
GowinSynthesis Constraints File | --- |
Tool Version | V1.9.11.02 (64-bit) |
Part Number | GW1N-LV9QN88C6/I5 |
Device | GW1N-9 |
Device Version | C |
Created Time | Thu Apr 3 16:39:47 2025 |
Legal Announcement | Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | TDC_Top |
Synthesis Process | Running parser: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.049s, Peak memory usage = 66.035MB Running netlist conversion: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0s, Peak memory usage = 66.035MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 66.035MB Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 66.035MB Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 66.035MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 66.035MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 66.035MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 66.035MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 66.035MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 66.035MB Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 66.035MB Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 66.035MB Tech-Mapping Phase 3: CPU time = 0h 0m 0.343s, Elapsed time = 0h 0m 0.393s, Peak memory usage = 94.355MB Tech-Mapping Phase 4: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 94.355MB Generate output files: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 94.355MB |
Total Time and Memory Usage | CPU time = 0h 0m 0.389s, Elapsed time = 0h 0m 0.451s, Peak memory usage = 94.355MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 17 |
I/O Buf | 17 |
    IBUF | 6 |
    OBUF | 11 |
Register | 36 |
    DFF | 12 |
    DFFP | 2 |
    DFFC | 12 |
    DFFCE | 10 |
LUT | 66 |
    LUT2 | 9 |
    LUT3 | 17 |
    LUT4 | 40 |
IOLOGIC | 1 |
    IDES8 | 1 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 66(66 LUT, 0 ALU) / 8640 | <1% |
Register | 36 / 6693 | <1% |
  --Register as Latch | 0 / 6693 | 0% |
  --Register as FF | 36 / 6693 | <1% |
BSRAM | 0 / 26 | 0% |
Timing
Clock Summary:
NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|---|
1 | pclk_i | Base | 20.000 | 50.000 | 0.000 | 10.000 | pclk_i_ibuf/I | ||
2 | fclk_i | Base | 20.000 | 50.000 | 0.000 | 10.000 | fclk_i_ibuf/I |
Max Frequency Summary:
NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | pclk_i | 50.000(MHz) | 83.013(MHz) | 6 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | 7.954 |
Data Arrival Time | 12.372 |
Data Required Time | 20.326 |
From | u_tdc/q_d_0_s0 |
To | u_tdc/count_tmp_5_s1 |
Launch Clk | pclk_i[R] |
Latch Clk | pclk_i[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | pclk_i | |||
0.000 | 0.000 | tCL | RR | 1 | pclk_i_ibuf/I |
0.000 | 0.000 | tINS | RR | 37 | pclk_i_ibuf/O |
0.726 | 0.726 | tNET | RR | 1 | u_tdc/q_d_0_s0/CLK |
1.184 | 0.458 | tC2Q | RF | 2 | u_tdc/q_d_0_s0/Q |
2.144 | 0.960 | tNET | FF | 1 | u_tdc/n176_s4/I1 |
3.243 | 1.099 | tINS | FF | 3 | u_tdc/n176_s4/F |
4.203 | 0.960 | tNET | FF | 1 | u_tdc/n175_s6/I1 |
5.302 | 1.099 | tINS | FF | 5 | u_tdc/n175_s6/F |
6.262 | 0.960 | tNET | FF | 1 | u_tdc/n174_s3/I1 |
7.361 | 1.099 | tINS | FF | 4 | u_tdc/n174_s3/F |
8.321 | 0.960 | tNET | FF | 1 | u_tdc/n172_s4/I0 |
9.353 | 1.032 | tINS | FF | 2 | u_tdc/n172_s4/F |
10.313 | 0.960 | tNET | FF | 1 | u_tdc/n171_s2/I1 |
11.412 | 1.099 | tINS | FF | 1 | u_tdc/n171_s2/F |
12.372 | 0.960 | tNET | FF | 1 | u_tdc/count_tmp_5_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
20.000 | 0.000 | pclk_i | |||
20.000 | 0.000 | tCL | RR | 1 | pclk_i_ibuf/I |
20.000 | 0.000 | tINS | RR | 37 | pclk_i_ibuf/O |
20.726 | 0.726 | tNET | RR | 1 | u_tdc/count_tmp_5_s1/CLK |
20.326 | -0.400 | tSu | 1 | u_tdc/count_tmp_5_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 20.000 |
Logic Level: | 6 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Arrival Data Path Delay: | cell: 5.428, 46.607%; route: 5.760, 49.458%; tC2Q: 0.458, 3.935% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Path 2
Path Summary:Slack | 7.954 |
Data Arrival Time | 12.372 |
Data Required Time | 20.326 |
From | u_tdc/q_d_0_s0 |
To | u_tdc/count_tmp_6_s1 |
Launch Clk | pclk_i[R] |
Latch Clk | pclk_i[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | pclk_i | |||
0.000 | 0.000 | tCL | RR | 1 | pclk_i_ibuf/I |
0.000 | 0.000 | tINS | RR | 37 | pclk_i_ibuf/O |
0.726 | 0.726 | tNET | RR | 1 | u_tdc/q_d_0_s0/CLK |
1.184 | 0.458 | tC2Q | RF | 2 | u_tdc/q_d_0_s0/Q |
2.144 | 0.960 | tNET | FF | 1 | u_tdc/n176_s4/I1 |
3.243 | 1.099 | tINS | FF | 3 | u_tdc/n176_s4/F |
4.203 | 0.960 | tNET | FF | 1 | u_tdc/n175_s6/I1 |
5.302 | 1.099 | tINS | FF | 5 | u_tdc/n175_s6/F |
6.262 | 0.960 | tNET | FF | 1 | u_tdc/n174_s3/I1 |
7.361 | 1.099 | tINS | FF | 4 | u_tdc/n174_s3/F |
8.321 | 0.960 | tNET | FF | 1 | u_tdc/n170_s3/I0 |
9.353 | 1.032 | tINS | FF | 4 | u_tdc/n170_s3/F |
10.313 | 0.960 | tNET | FF | 1 | u_tdc/n170_s10/I1 |
11.412 | 1.099 | tINS | FF | 1 | u_tdc/n170_s10/F |
12.372 | 0.960 | tNET | FF | 1 | u_tdc/count_tmp_6_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
20.000 | 0.000 | pclk_i | |||
20.000 | 0.000 | tCL | RR | 1 | pclk_i_ibuf/I |
20.000 | 0.000 | tINS | RR | 37 | pclk_i_ibuf/O |
20.726 | 0.726 | tNET | RR | 1 | u_tdc/count_tmp_6_s1/CLK |
20.326 | -0.400 | tSu | 1 | u_tdc/count_tmp_6_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 20.000 |
Logic Level: | 6 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Arrival Data Path Delay: | cell: 5.428, 46.607%; route: 5.760, 49.458%; tC2Q: 0.458, 3.935% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Path 3
Path Summary:Slack | 8.021 |
Data Arrival Time | 12.305 |
Data Required Time | 20.326 |
From | u_tdc/q_d_0_s0 |
To | u_tdc/count_tmp_7_s1 |
Launch Clk | pclk_i[R] |
Latch Clk | pclk_i[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | pclk_i | |||
0.000 | 0.000 | tCL | RR | 1 | pclk_i_ibuf/I |
0.000 | 0.000 | tINS | RR | 37 | pclk_i_ibuf/O |
0.726 | 0.726 | tNET | RR | 1 | u_tdc/q_d_0_s0/CLK |
1.184 | 0.458 | tC2Q | RF | 2 | u_tdc/q_d_0_s0/Q |
2.144 | 0.960 | tNET | FF | 1 | u_tdc/n176_s4/I1 |
3.243 | 1.099 | tINS | FF | 3 | u_tdc/n176_s4/F |
4.203 | 0.960 | tNET | FF | 1 | u_tdc/n175_s6/I1 |
5.302 | 1.099 | tINS | FF | 5 | u_tdc/n175_s6/F |
6.262 | 0.960 | tNET | FF | 1 | u_tdc/n170_s6/I0 |
7.294 | 1.032 | tINS | FF | 5 | u_tdc/n170_s6/F |
8.254 | 0.960 | tNET | FF | 1 | u_tdc/n170_s4/I0 |
9.286 | 1.032 | tINS | FF | 1 | u_tdc/n170_s4/F |
10.246 | 0.960 | tNET | FF | 1 | u_tdc/n169_s2/I1 |
11.345 | 1.099 | tINS | FF | 1 | u_tdc/n169_s2/F |
12.305 | 0.960 | tNET | FF | 1 | u_tdc/count_tmp_7_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
20.000 | 0.000 | pclk_i | |||
20.000 | 0.000 | tCL | RR | 1 | pclk_i_ibuf/I |
20.000 | 0.000 | tINS | RR | 37 | pclk_i_ibuf/O |
20.726 | 0.726 | tNET | RR | 1 | u_tdc/count_tmp_7_s1/CLK |
20.326 | -0.400 | tSu | 1 | u_tdc/count_tmp_7_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 20.000 |
Logic Level: | 6 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Arrival Data Path Delay: | cell: 5.361, 46.298%; route: 5.760, 49.744%; tC2Q: 0.458, 3.958% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Path 4
Path Summary:Slack | 8.021 |
Data Arrival Time | 12.305 |
Data Required Time | 20.326 |
From | u_tdc/q_d_0_s0 |
To | u_tdc/count_tmp_8_s1 |
Launch Clk | pclk_i[R] |
Latch Clk | pclk_i[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | pclk_i | |||
0.000 | 0.000 | tCL | RR | 1 | pclk_i_ibuf/I |
0.000 | 0.000 | tINS | RR | 37 | pclk_i_ibuf/O |
0.726 | 0.726 | tNET | RR | 1 | u_tdc/q_d_0_s0/CLK |
1.184 | 0.458 | tC2Q | RF | 2 | u_tdc/q_d_0_s0/Q |
2.144 | 0.960 | tNET | FF | 1 | u_tdc/n176_s4/I1 |
3.243 | 1.099 | tINS | FF | 3 | u_tdc/n176_s4/F |
4.203 | 0.960 | tNET | FF | 1 | u_tdc/n175_s6/I1 |
5.302 | 1.099 | tINS | FF | 5 | u_tdc/n175_s6/F |
6.262 | 0.960 | tNET | FF | 1 | u_tdc/n174_s3/I1 |
7.361 | 1.099 | tINS | FF | 4 | u_tdc/n174_s3/F |
8.321 | 0.960 | tNET | FF | 1 | u_tdc/n170_s3/I0 |
9.353 | 1.032 | tINS | FF | 4 | u_tdc/n170_s3/F |
10.313 | 0.960 | tNET | FF | 1 | u_tdc/n168_s2/I0 |
11.345 | 1.032 | tINS | FF | 1 | u_tdc/n168_s2/F |
12.305 | 0.960 | tNET | FF | 1 | u_tdc/count_tmp_8_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
20.000 | 0.000 | pclk_i | |||
20.000 | 0.000 | tCL | RR | 1 | pclk_i_ibuf/I |
20.000 | 0.000 | tINS | RR | 37 | pclk_i_ibuf/O |
20.726 | 0.726 | tNET | RR | 1 | u_tdc/count_tmp_8_s1/CLK |
20.326 | -0.400 | tSu | 1 | u_tdc/count_tmp_8_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 20.000 |
Logic Level: | 6 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Arrival Data Path Delay: | cell: 5.361, 46.298%; route: 5.760, 49.744%; tC2Q: 0.458, 3.958% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Path 5
Path Summary:Slack | 8.021 |
Data Arrival Time | 12.305 |
Data Required Time | 20.326 |
From | u_tdc/q_d_0_s0 |
To | u_tdc/count_tmp_9_s1 |
Launch Clk | pclk_i[R] |
Latch Clk | pclk_i[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | pclk_i | |||
0.000 | 0.000 | tCL | RR | 1 | pclk_i_ibuf/I |
0.000 | 0.000 | tINS | RR | 37 | pclk_i_ibuf/O |
0.726 | 0.726 | tNET | RR | 1 | u_tdc/q_d_0_s0/CLK |
1.184 | 0.458 | tC2Q | RF | 2 | u_tdc/q_d_0_s0/Q |
2.144 | 0.960 | tNET | FF | 1 | u_tdc/n176_s4/I1 |
3.243 | 1.099 | tINS | FF | 3 | u_tdc/n176_s4/F |
4.203 | 0.960 | tNET | FF | 1 | u_tdc/n175_s6/I1 |
5.302 | 1.099 | tINS | FF | 5 | u_tdc/n175_s6/F |
6.262 | 0.960 | tNET | FF | 1 | u_tdc/n174_s3/I1 |
7.361 | 1.099 | tINS | FF | 4 | u_tdc/n174_s3/F |
8.321 | 0.960 | tNET | FF | 1 | u_tdc/n170_s3/I0 |
9.353 | 1.032 | tINS | FF | 4 | u_tdc/n170_s3/F |
10.313 | 0.960 | tNET | FF | 1 | u_tdc/n167_s2/I0 |
11.345 | 1.032 | tINS | FF | 1 | u_tdc/n167_s2/F |
12.305 | 0.960 | tNET | FF | 1 | u_tdc/count_tmp_9_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
20.000 | 0.000 | pclk_i | |||
20.000 | 0.000 | tCL | RR | 1 | pclk_i_ibuf/I |
20.000 | 0.000 | tINS | RR | 37 | pclk_i_ibuf/O |
20.726 | 0.726 | tNET | RR | 1 | u_tdc/count_tmp_9_s1/CLK |
20.326 | -0.400 | tSu | 1 | u_tdc/count_tmp_9_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 20.000 |
Logic Level: | 6 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Arrival Data Path Delay: | cell: 5.361, 46.298%; route: 5.760, 49.744%; tC2Q: 0.458, 3.958% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |