Timing Messages
Report Title | Timing Analysis Report |
Design File | E:\myWork\IP\releaseVerify\version\1.9.11.02\Gowin_TDC_RefDesign\project\impl\gwsynthesis\fpga_project.vg |
Physical Constraints File | E:\myWork\IP\releaseVerify\version\1.9.11.02\Gowin_TDC_RefDesign\project\src\fpga_project.cst |
Timing Constraint File | E:\myWork\IP\releaseVerify\version\1.9.11.02\Gowin_TDC_RefDesign\project\src\fpga_project.sdc |
Tool Version | V1.9.11.02 (64-bit) |
Part Number | GW1N-LV9QN88C6/I5 |
Device | GW1N-9 |
Device Version | C |
Created Time | Wed Apr 30 14:08:31 2025 |
Legal Announcement | Copyright (C)2014-2025 Gowin Semiconductor Corporation. All rights reserved. |
Timing Summaries
STA Tool Run Summary:
Setup Delay Model | Slow 1.14V 85C C6/I5 |
Hold Delay Model | Fast 1.26V 0C C6/I5 |
Numbers of Paths Analyzed | 772 |
Numbers of Endpoints Analyzed | 993 |
Numbers of Falling Endpoints | 3 |
Numbers of Setup Violated Endpoints | 0 |
Numbers of Hold Violated Endpoints | 0 |
Clock Summary:
NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Objects |
---|---|---|---|---|---|---|---|---|---|
1 | tck_pad_i | Base | 50.000 | 20.000 | 0.000 | 25.000 | tck_pad_i | ||
2 | pclk | Base | 10.000 | 100.000 | 0.000 | 5.000 | u_CLKDIV/CLKOUT | ||
3 | clk | Base | 20.000 | 50.000 | 0.000 | 10.000 | clk_ibuf/I | ||
4 | Gowin_PLL/rpll_inst/CLKOUT.default_gen_clk | Generated | 2.500 | 400.000 | 0.000 | 1.250 | clk_ibuf/I | clk | Gowin_PLL/rpll_inst/CLKOUT |
5 | Gowin_PLL/rpll_inst/CLKOUTP.default_gen_clk | Generated | 2.500 | 400.000 | 0.000 | 1.250 | clk_ibuf/I | clk | Gowin_PLL/rpll_inst/CLKOUTP |
6 | Gowin_PLL/rpll_inst/CLKOUTD.default_gen_clk | Generated | 5.000 | 200.000 | 0.000 | 2.500 | clk_ibuf/I | clk | Gowin_PLL/rpll_inst/CLKOUTD |
7 | Gowin_PLL/rpll_inst/CLKOUTD3.default_gen_clk | Generated | 7.500 | 133.333 | 0.000 | 3.750 | clk_ibuf/I | clk | Gowin_PLL/rpll_inst/CLKOUTD3 |
Max Frequency Summary:
NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | tck_pad_i | 20.000(MHz) | 86.538(MHz) | 6 | TOP |
2 | pclk | 100.000(MHz) | 101.557(MHz) | 6 | TOP |
No timing paths to get frequency of clk!
No timing paths to get frequency of Gowin_PLL/rpll_inst/CLKOUT.default_gen_clk!
No timing paths to get frequency of Gowin_PLL/rpll_inst/CLKOUTP.default_gen_clk!
No timing paths to get frequency of Gowin_PLL/rpll_inst/CLKOUTD.default_gen_clk!
No timing paths to get frequency of Gowin_PLL/rpll_inst/CLKOUTD3.default_gen_clk!
Total Negative Slack Summary:
Clock Name | Analysis Type | Endpoints TNS | Number of Endpoints |
---|---|---|---|
tck_pad_i | Setup | 0.000 | 0 |
tck_pad_i | Hold | 0.000 | 0 |
pclk | Setup | 0.000 | 0 |
pclk | Hold | 0.000 | 0 |
clk | Setup | 0.000 | 0 |
clk | Hold | 0.000 | 0 |
Gowin_PLL/rpll_inst/CLKOUT.default_gen_clk | Setup | 0.000 | 0 |
Gowin_PLL/rpll_inst/CLKOUT.default_gen_clk | Hold | 0.000 | 0 |
Gowin_PLL/rpll_inst/CLKOUTP.default_gen_clk | Setup | 0.000 | 0 |
Gowin_PLL/rpll_inst/CLKOUTP.default_gen_clk | Hold | 0.000 | 0 |
Gowin_PLL/rpll_inst/CLKOUTD.default_gen_clk | Setup | 0.000 | 0 |
Gowin_PLL/rpll_inst/CLKOUTD.default_gen_clk | Hold | 0.000 | 0 |
Gowin_PLL/rpll_inst/CLKOUTD3.default_gen_clk | Setup | 0.000 | 0 |
Gowin_PLL/rpll_inst/CLKOUTD3.default_gen_clk | Hold | 0.000 | 0 |
Timing Details
Path Slacks Table:
Setup Paths Table
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 0.153 | dut/u_tdc/q_d_2_s0/Q | dut/u_tdc/count_tmp_4_s1/D | pclk:[R] | pclk:[R] | 10.000 | 0.000 | 9.447 |
2 | 0.285 | dut/u_tdc/q_d_2_s0/Q | dut/u_tdc/count_tmp_5_s1/D | pclk:[R] | pclk:[R] | 10.000 | 0.000 | 9.315 |
3 | 0.804 | dut/u_tdc/q_d_2_s0/Q | dut/u_tdc/count_tmp_7_s1/D | pclk:[R] | pclk:[R] | 10.000 | 0.000 | 8.796 |
4 | 0.917 | dut/u_tdc/q_d_2_s0/Q | dut/u_tdc/count_tmp_8_s1/D | pclk:[R] | pclk:[R] | 10.000 | 0.000 | 8.683 |
5 | 1.204 | dut/u_tdc/q_d_2_s0/Q | dut/u_tdc/count_tmp_9_s1/D | pclk:[R] | pclk:[R] | 10.000 | 0.000 | 8.396 |
6 | 1.360 | dut/u_tdc/q_d_7_s0/Q | dut/u_tdc/count_tmp_3_s1/D | pclk:[R] | pclk:[R] | 10.000 | 0.000 | 8.240 |
7 | 1.618 | dut/u_tdc/q_d_7_s0/Q | dut/u_tdc/count_tmp_6_s1/D | pclk:[R] | pclk:[R] | 10.000 | 0.000 | 7.982 |
8 | 1.797 | dut/u_tdc/q_d_2_s0/Q | dut/u_tdc/count_tmp_2_s1/D | pclk:[R] | pclk:[R] | 10.000 | 0.000 | 7.803 |
9 | 2.278 | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/Q | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/D | pclk:[R] | pclk:[R] | 10.000 | 0.000 | 7.322 |
10 | 2.318 | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/Q | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/D | pclk:[R] | pclk:[R] | 10.000 | 0.000 | 7.282 |
11 | 2.318 | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/Q | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/D | pclk:[R] | pclk:[R] | 10.000 | 0.000 | 7.282 |
12 | 2.454 | dut/u_tdc/q_d_7_s0/Q | dut/u_tdc/count_tmp_1_s1/D | pclk:[R] | pclk:[R] | 10.000 | 0.000 | 7.146 |
13 | 2.555 | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/Q | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/D | pclk:[R] | pclk:[R] | 10.000 | 0.000 | 7.045 |
14 | 2.555 | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/Q | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/D | pclk:[R] | pclk:[R] | 10.000 | 0.000 | 7.045 |
15 | 2.615 | gw_gao_gvio_inst_0/u_la0_top/triger_level_cnt_3_s1/Q | gw_gao_gvio_inst_0/u_la0_top/trigger_seq_start_s1/CE | pclk:[R] | pclk:[R] | 10.000 | 0.000 | 7.341 |
16 | 2.751 | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/Q | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/D | pclk:[R] | pclk:[R] | 10.000 | 0.000 | 6.849 |
17 | 2.786 | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/Q | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CE | pclk:[R] | pclk:[R] | 10.000 | 0.000 | 7.170 |
18 | 3.112 | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/Q | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CE | pclk:[R] | pclk:[R] | 10.000 | 0.000 | 6.845 |
19 | 3.403 | gw_gao_gvio_inst_0/u_la0_top/triger_level_cnt_3_s1/Q | gw_gao_gvio_inst_0/u_la0_top/triger_s0/D | pclk:[R] | pclk:[R] | 10.000 | 0.000 | 6.197 |
20 | 3.459 | dut/u_tdc/u_IDES8/Q4 | dut/u_tdc/c_state_3_s0/D | pclk:[R] | pclk:[R] | 10.000 | 0.000 | 6.141 |
21 | 3.550 | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/Q | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/D | pclk:[R] | pclk:[R] | 10.000 | 0.000 | 6.050 |
22 | 3.550 | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/Q | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/D | pclk:[R] | pclk:[R] | 10.000 | 0.000 | 6.050 |
23 | 3.557 | dut/u_tdc/start_d0_s0/Q | dut/u_tdc/c_state_0_s0/D | pclk:[R] | pclk:[R] | 10.000 | 0.000 | 6.043 |
24 | 3.716 | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_1_s1/Q | gw_gao_gvio_inst_0/u_la0_top/start_reg_s0/D | pclk:[R] | pclk:[R] | 10.000 | 0.000 | 5.884 |
25 | 3.886 | dut/u_tdc/u_IDES8/Q4 | dut/u_tdc/c_state_2_s0/D | pclk:[R] | pclk:[R] | 10.000 | 0.000 | 5.714 |
Hold Paths Table
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 0.571 | gw_gao_gvio_inst_0/u_la0_top/capture_end_tck_1_s0/Q | gw_gao_gvio_inst_0/u_la0_top/capture_end_tck_2_s0/D | tck_pad_i:[R] | tck_pad_i:[R] | 0.000 | 0.000 | 0.571 |
2 | 0.703 | gw_gao_gvio_inst_0/u_la0_top/address_counter_7_s0/Q | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/ADB[11] | tck_pad_i:[R] | tck_pad_i:[R] | 0.000 | 0.000 | 0.863 |
3 | 0.708 | gw_gao_gvio_inst_0/u_la0_top/bit_count_3_s1/Q | gw_gao_gvio_inst_0/u_la0_top/bit_count_3_s1/D | tck_pad_i:[R] | tck_pad_i:[R] | 0.000 | 0.000 | 0.708 |
4 | 0.708 | gw_gao_gvio_inst_0/u_la0_top/word_count_8_s0/Q | gw_gao_gvio_inst_0/u_la0_top/word_count_8_s0/D | tck_pad_i:[R] | tck_pad_i:[R] | 0.000 | 0.000 | 0.708 |
5 | 0.708 | gw_gao_gvio_inst_0/u_gvio0_top/word_count_0_s1/Q | gw_gao_gvio_inst_0/u_gvio0_top/word_count_0_s1/D | tck_pad_i:[R] | tck_pad_i:[R] | 0.000 | 0.000 | 0.708 |
6 | 0.708 | gw_gao_gvio_inst_0/u_gvio0_top/word_count_1_s0/Q | gw_gao_gvio_inst_0/u_gvio0_top/word_count_1_s0/D | tck_pad_i:[R] | tck_pad_i:[R] | 0.000 | 0.000 | 0.708 |
7 | 0.708 | gw_gao_gvio_inst_0/u_gvio0_top/word_count_3_s0/Q | gw_gao_gvio_inst_0/u_gvio0_top/word_count_3_s0/D | tck_pad_i:[R] | tck_pad_i:[R] | 0.000 | 0.000 | 0.708 |
8 | 0.708 | gw_gao_gvio_inst_0/u_gvio0_top/word_count_5_s0/Q | gw_gao_gvio_inst_0/u_gvio0_top/word_count_5_s0/D | tck_pad_i:[R] | tck_pad_i:[R] | 0.000 | 0.000 | 0.708 |
9 | 0.708 | gw_gao_gvio_inst_0/u_gvio0_top/word_count_6_s0/Q | gw_gao_gvio_inst_0/u_gvio0_top/word_count_6_s0/D | tck_pad_i:[R] | tck_pad_i:[R] | 0.000 | 0.000 | 0.708 |
10 | 0.708 | gw_gao_gvio_inst_0/u_gvio0_top/word_count_8_s0/Q | gw_gao_gvio_inst_0/u_gvio0_top/word_count_8_s0/D | tck_pad_i:[R] | tck_pad_i:[R] | 0.000 | 0.000 | 0.708 |
11 | 0.708 | gw_gao_gvio_inst_0/u_gvio0_top/word_count_11_s0/Q | gw_gao_gvio_inst_0/u_gvio0_top/word_count_11_s0/D | tck_pad_i:[R] | tck_pad_i:[R] | 0.000 | 0.000 | 0.708 |
12 | 0.708 | gw_gao_gvio_inst_0/u_gvio_icon_top/tdo_select_s5/Q | gw_gao_gvio_inst_0/u_gvio_icon_top/tdo_select_s5/D | tck_pad_i:[R] | tck_pad_i:[R] | 0.000 | 0.000 | 0.708 |
13 | 0.708 | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/Q | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/D | pclk:[R] | pclk:[R] | 0.000 | 0.000 | 0.708 |
14 | 0.708 | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_6_s1/Q | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_6_s1/D | pclk:[R] | pclk:[R] | 0.000 | 0.000 | 0.708 |
15 | 0.709 | gw_gao_gvio_inst_0/u_la0_top/bit_count_0_s1/Q | gw_gao_gvio_inst_0/u_la0_top/bit_count_0_s1/D | tck_pad_i:[R] | tck_pad_i:[R] | 0.000 | 0.000 | 0.709 |
16 | 0.709 | gw_gao_gvio_inst_0/u_gvio0_top/bit_count_3_s1/Q | gw_gao_gvio_inst_0/u_gvio0_top/bit_count_3_s1/D | tck_pad_i:[R] | tck_pad_i:[R] | 0.000 | 0.000 | 0.709 |
17 | 0.709 | gw_gao_gvio_inst_0/u_gvio0_top/bit_count_5_s1/Q | gw_gao_gvio_inst_0/u_gvio0_top/bit_count_5_s1/D | tck_pad_i:[R] | tck_pad_i:[R] | 0.000 | 0.000 | 0.709 |
18 | 0.709 | gw_gao_gvio_inst_0/u_gvio0_top/bit_count_6_s1/Q | gw_gao_gvio_inst_0/u_gvio0_top/bit_count_6_s1/D | tck_pad_i:[R] | tck_pad_i:[R] | 0.000 | 0.000 | 0.709 |
19 | 0.710 | gw_gao_gvio_inst_0/u_la0_top/word_count_4_s0/Q | gw_gao_gvio_inst_0/u_la0_top/word_count_4_s0/D | tck_pad_i:[R] | tck_pad_i:[R] | 0.000 | 0.000 | 0.710 |
20 | 0.710 | gw_gao_gvio_inst_0/u_gvio0_top/module_state_1_s0/Q | gw_gao_gvio_inst_0/u_gvio0_top/module_state_1_s0/D | tck_pad_i:[R] | tck_pad_i:[R] | 0.000 | 0.000 | 0.710 |
21 | 0.711 | gw_gao_gvio_inst_0/u_la0_top/word_count_0_s0/Q | gw_gao_gvio_inst_0/u_la0_top/word_count_0_s0/D | tck_pad_i:[R] | tck_pad_i:[R] | 0.000 | 0.000 | 0.711 |
22 | 0.711 | gw_gao_gvio_inst_0/u_la0_top/address_counter_0_s0/Q | gw_gao_gvio_inst_0/u_la0_top/address_counter_0_s0/D | tck_pad_i:[R] | tck_pad_i:[R] | 0.000 | 0.000 | 0.711 |
23 | 0.711 | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_0_s3/Q | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_0_s3/D | pclk:[R] | pclk:[R] | 0.000 | 0.000 | 0.711 |
24 | 0.712 | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_1_s1/Q | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_1_s1/D | pclk:[R] | pclk:[R] | 0.000 | 0.000 | 0.712 |
25 | 0.712 | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_4_s1/Q | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_4_s1/D | pclk:[R] | pclk:[R] | 0.000 | 0.000 | 0.712 |
Recovery Paths Table
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 2.304 | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_gvio_inst_0/u_la0_top/triger_level_cnt_0_s3/CLEAR | pclk:[F] | pclk:[R] | 5.000 | 0.015 | 2.637 |
2 | 2.304 | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_gvio_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR | pclk:[F] | pclk:[R] | 5.000 | 0.015 | 2.637 |
3 | 2.304 | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_gvio_inst_0/u_la0_top/triger_level_cnt_2_s1/CLEAR | pclk:[F] | pclk:[R] | 5.000 | 0.015 | 2.637 |
4 | 2.304 | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_gvio_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR | pclk:[F] | pclk:[R] | 5.000 | 0.015 | 2.637 |
5 | 2.327 | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_gvio_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR | pclk:[F] | pclk:[R] | 5.000 | 0.015 | 2.615 |
6 | 2.327 | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_gvio_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR | pclk:[F] | pclk:[R] | 5.000 | 0.015 | 2.615 |
7 | 2.353 | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_gvio_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR | pclk:[F] | pclk:[R] | 5.000 | 0.015 | 2.588 |
8 | 2.486 | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR | pclk:[F] | pclk:[R] | 5.000 | 0.015 | 2.456 |
9 | 2.486 | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR | pclk:[F] | pclk:[R] | 5.000 | 0.015 | 2.456 |
10 | 2.963 | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET | pclk:[F] | pclk:[R] | 5.000 | 0.015 | 1.979 |
11 | 2.963 | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR | pclk:[F] | pclk:[R] | 5.000 | 0.015 | 1.979 |
12 | 2.969 | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_gvio_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR | pclk:[F] | pclk:[R] | 5.000 | 0.015 | 1.973 |
13 | 2.980 | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR | pclk:[F] | pclk:[R] | 5.000 | 0.015 | 1.962 |
14 | 2.986 | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_gvio_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR | pclk:[F] | pclk:[R] | 5.000 | 0.015 | 1.956 |
15 | 2.986 | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_gvio_inst_0/u_la0_top/u_ao_match_0/trig_dly_0_s0/CLEAR | pclk:[F] | pclk:[R] | 5.000 | 0.015 | 1.956 |
16 | 2.998 | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR | pclk:[F] | pclk:[R] | 5.000 | 0.015 | 1.944 |
17 | 2.998 | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR | pclk:[F] | pclk:[R] | 5.000 | 0.015 | 1.944 |
18 | 2.998 | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR | pclk:[F] | pclk:[R] | 5.000 | 0.015 | 1.944 |
19 | 3.120 | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR | pclk:[F] | pclk:[R] | 5.000 | 0.015 | 1.822 |
20 | 3.120 | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR | pclk:[F] | pclk:[R] | 5.000 | 0.015 | 1.822 |
21 | 3.124 | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_gvio_inst_0/u_la0_top/capture_end_dly_s0/PRESET | pclk:[F] | pclk:[R] | 5.000 | 0.015 | 1.818 |
22 | 3.151 | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR | pclk:[F] | pclk:[R] | 5.000 | 0.015 | 1.791 |
23 | 3.151 | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR | pclk:[F] | pclk:[R] | 5.000 | 0.015 | 1.791 |
24 | 3.278 | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR | pclk:[F] | pclk:[R] | 5.000 | 0.015 | 1.664 |
25 | 3.625 | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR | pclk:[F] | pclk:[R] | 5.000 | 0.015 | 1.316 |
Removal Paths Table
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 5.837 | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/CLEAR | pclk:[F] | pclk:[R] | -5.000 | 0.008 | 0.842 |
2 | 5.843 | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR | pclk:[F] | pclk:[R] | -5.000 | 0.008 | 0.848 |
3 | 5.843 | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR | pclk:[F] | pclk:[R] | -5.000 | 0.008 | 0.848 |
4 | 5.843 | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR | pclk:[F] | pclk:[R] | -5.000 | 0.008 | 0.848 |
5 | 5.843 | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_4_s1/CLEAR | pclk:[F] | pclk:[R] | -5.000 | 0.008 | 0.848 |
6 | 5.843 | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_5_s1/CLEAR | pclk:[F] | pclk:[R] | -5.000 | 0.008 | 0.848 |
7 | 5.843 | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_6_s1/CLEAR | pclk:[F] | pclk:[R] | -5.000 | 0.008 | 0.848 |
8 | 5.843 | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_7_s1/CLEAR | pclk:[F] | pclk:[R] | -5.000 | 0.008 | 0.848 |
9 | 5.907 | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_gvio_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLEAR | pclk:[F] | pclk:[R] | -5.000 | 0.008 | 0.912 |
10 | 5.907 | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_gvio_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLEAR | pclk:[F] | pclk:[R] | -5.000 | 0.008 | 0.912 |
11 | 5.911 | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR | pclk:[F] | pclk:[R] | -5.000 | 0.008 | 0.916 |
12 | 5.911 | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR | pclk:[F] | pclk:[R] | -5.000 | 0.008 | 0.916 |
13 | 5.911 | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_0_s3/CLEAR | pclk:[F] | pclk:[R] | -5.000 | 0.008 | 0.916 |
14 | 5.911 | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR | pclk:[F] | pclk:[R] | -5.000 | 0.008 | 0.916 |
15 | 5.915 | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR | pclk:[F] | pclk:[R] | -5.000 | 0.008 | 0.919 |
16 | 5.915 | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR | pclk:[F] | pclk:[R] | -5.000 | 0.008 | 0.919 |
17 | 5.915 | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_gvio_inst_0/u_la0_top/trigger_seq_start_s1/CLEAR | pclk:[F] | pclk:[R] | -5.000 | 0.008 | 0.919 |
18 | 5.915 | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_gvio_inst_0/u_la0_top/triger_s0/CLEAR | pclk:[F] | pclk:[R] | -5.000 | 0.008 | 0.919 |
19 | 5.915 | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_gvio_inst_0/u_la0_top/start_reg_s0/CLEAR | pclk:[F] | pclk:[R] | -5.000 | 0.008 | 0.919 |
20 | 5.915 | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_gvio_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLEAR | pclk:[F] | pclk:[R] | -5.000 | 0.008 | 0.919 |
21 | 5.915 | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_gvio_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLEAR | pclk:[F] | pclk:[R] | -5.000 | 0.008 | 0.919 |
22 | 6.101 | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR | pclk:[F] | pclk:[R] | -5.000 | 0.008 | 1.105 |
23 | 6.101 | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR | pclk:[F] | pclk:[R] | -5.000 | 0.008 | 1.105 |
24 | 6.120 | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_gvio_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR | pclk:[F] | pclk:[R] | -5.000 | 0.008 | 1.125 |
25 | 6.120 | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_gvio_inst_0/u_la0_top/u_ao_match_0/trig_dly_0_s0/CLEAR | pclk:[F] | pclk:[R] | -5.000 | 0.008 | 1.125 |
Minimum Pulse Width Table:
Number | Slack | Actual Width | Required Width | Type | Clock | Objects |
---|---|---|---|---|---|---|
1 | 3.676 | 4.926 | 1.250 | Low Pulse Width | pclk | gw_gao_gvio_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0 |
2 | 3.676 | 4.926 | 1.250 | Low Pulse Width | pclk | gw_gao_gvio_inst_0/u_la0_top/internal_reg_start_syn_1_s0 |
3 | 3.676 | 4.926 | 1.250 | Low Pulse Width | pclk | gw_gao_gvio_inst_0/u_la0_top/start_reg_s0 |
4 | 3.676 | 4.926 | 1.250 | Low Pulse Width | pclk | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_6_s1 |
5 | 3.676 | 4.926 | 1.250 | Low Pulse Width | pclk | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_2_s0 |
6 | 3.676 | 4.926 | 1.250 | Low Pulse Width | pclk | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1 |
7 | 3.676 | 4.926 | 1.250 | Low Pulse Width | pclk | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1 |
8 | 3.676 | 4.926 | 1.250 | Low Pulse Width | pclk | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_3_s0 |
9 | 3.676 | 4.926 | 1.250 | Low Pulse Width | pclk | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1 |
10 | 3.676 | 4.926 | 1.250 | Low Pulse Width | pclk | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1 |
Timing Report By Analysis Type:
Setup Analysis Report
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 0.153 |
Data Arrival Time | 9.689 |
Data Required Time | 9.842 |
From | dut/u_tdc/q_d_2_s0 |
To | dut/u_tdc/count_tmp_4_s1 |
Launch Clk | pclk:[R] |
Latch Clk | pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pclk | ||||
0.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
0.242 | 0.242 | tNET | RR | 1 | R22C22[1][A] | dut/u_tdc/q_d_2_s0/CLK |
0.700 | 0.458 | tC2Q | RR | 2 | R22C22[1][A] | dut/u_tdc/q_d_2_s0/Q |
1.120 | 0.420 | tNET | RR | 1 | R21C22[2][B] | dut/u_tdc/n175_s8/I2 |
2.219 | 1.099 | tINS | RF | 9 | R21C22[2][B] | dut/u_tdc/n175_s8/F |
3.050 | 0.831 | tNET | FF | 1 | R20C22[3][B] | dut/u_tdc/n174_s5/I1 |
3.676 | 0.626 | tINS | FF | 3 | R20C22[3][B] | dut/u_tdc/n174_s5/F |
5.459 | 1.783 | tNET | FF | 1 | R17C22[2][A] | dut/u_tdc/n172_s5/I2 |
6.558 | 1.099 | tINS | FF | 2 | R17C22[2][A] | dut/u_tdc/n172_s5/F |
7.367 | 0.809 | tNET | FF | 1 | R18C21[0][A] | dut/u_tdc/n172_s3/I0 |
8.169 | 0.802 | tINS | FR | 2 | R18C21[0][A] | dut/u_tdc/n172_s3/F |
8.590 | 0.421 | tNET | RR | 1 | R18C22[2][A] | dut/u_tdc/n172_s10/I2 |
9.689 | 1.099 | tINS | RF | 1 | R18C22[2][A] | dut/u_tdc/n172_s10/F |
9.689 | 0.000 | tNET | FF | 1 | R18C22[2][A] | dut/u_tdc/count_tmp_4_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | pclk | ||||
10.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
10.242 | 0.242 | tNET | RR | 1 | R18C22[2][A] | dut/u_tdc/count_tmp_4_s1/CLK |
9.842 | -0.400 | tSu | 1 | R18C22[2][A] | dut/u_tdc/count_tmp_4_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000% |
Arrival Data Path Delay | cell: 4.725, 50.018%; route: 4.263, 45.130%; tC2Q: 0.458, 4.852% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000% |
Path2
Path Summary:
Slack | 0.285 |
Data Arrival Time | 9.557 |
Data Required Time | 9.842 |
From | dut/u_tdc/q_d_2_s0 |
To | dut/u_tdc/count_tmp_5_s1 |
Launch Clk | pclk:[R] |
Latch Clk | pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pclk | ||||
0.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
0.242 | 0.242 | tNET | RR | 1 | R22C22[1][A] | dut/u_tdc/q_d_2_s0/CLK |
0.700 | 0.458 | tC2Q | RR | 2 | R22C22[1][A] | dut/u_tdc/q_d_2_s0/Q |
1.120 | 0.420 | tNET | RR | 1 | R21C22[2][B] | dut/u_tdc/n175_s8/I2 |
2.219 | 1.099 | tINS | RF | 9 | R21C22[2][B] | dut/u_tdc/n175_s8/F |
3.050 | 0.831 | tNET | FF | 1 | R20C22[3][B] | dut/u_tdc/n174_s5/I1 |
3.676 | 0.626 | tINS | FF | 3 | R20C22[3][B] | dut/u_tdc/n174_s5/F |
5.459 | 1.783 | tNET | FF | 1 | R17C22[2][A] | dut/u_tdc/n172_s5/I2 |
6.558 | 1.099 | tINS | FF | 2 | R17C22[2][A] | dut/u_tdc/n172_s5/F |
7.367 | 0.809 | tNET | FF | 1 | R18C21[1][A] | dut/u_tdc/n171_s3/I1 |
8.189 | 0.822 | tINS | FF | 1 | R18C21[1][A] | dut/u_tdc/n171_s3/F |
8.525 | 0.336 | tNET | FF | 1 | R18C21[2][B] | dut/u_tdc/n171_s2/I3 |
9.557 | 1.032 | tINS | FF | 1 | R18C21[2][B] | dut/u_tdc/n171_s2/F |
9.557 | 0.000 | tNET | FF | 1 | R18C21[2][B] | dut/u_tdc/count_tmp_5_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | pclk | ||||
10.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
10.242 | 0.242 | tNET | RR | 1 | R18C21[2][B] | dut/u_tdc/count_tmp_5_s1/CLK |
9.842 | -0.400 | tSu | 1 | R18C21[2][B] | dut/u_tdc/count_tmp_5_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000% |
Arrival Data Path Delay | cell: 4.678, 50.220%; route: 4.179, 44.860%; tC2Q: 0.458, 4.920% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000% |
Path3
Path Summary:
Slack | 0.804 |
Data Arrival Time | 9.038 |
Data Required Time | 9.842 |
From | dut/u_tdc/q_d_2_s0 |
To | dut/u_tdc/count_tmp_7_s1 |
Launch Clk | pclk:[R] |
Latch Clk | pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pclk | ||||
0.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
0.242 | 0.242 | tNET | RR | 1 | R22C22[1][A] | dut/u_tdc/q_d_2_s0/CLK |
0.700 | 0.458 | tC2Q | RR | 2 | R22C22[1][A] | dut/u_tdc/q_d_2_s0/Q |
1.120 | 0.420 | tNET | RR | 1 | R21C22[2][B] | dut/u_tdc/n175_s8/I2 |
2.219 | 1.099 | tINS | RF | 9 | R21C22[2][B] | dut/u_tdc/n175_s8/F |
3.050 | 0.831 | tNET | FF | 1 | R20C22[3][B] | dut/u_tdc/n174_s5/I1 |
3.676 | 0.626 | tINS | FF | 3 | R20C22[3][B] | dut/u_tdc/n174_s5/F |
5.459 | 1.783 | tNET | FF | 1 | R17C22[2][B] | dut/u_tdc/n170_s6/I2 |
6.558 | 1.099 | tINS | FF | 5 | R17C22[2][B] | dut/u_tdc/n170_s6/F |
7.388 | 0.830 | tNET | FF | 1 | R18C23[2][A] | dut/u_tdc/n170_s4/I0 |
8.210 | 0.822 | tINS | FF | 1 | R18C23[2][A] | dut/u_tdc/n170_s4/F |
8.216 | 0.005 | tNET | FF | 1 | R18C23[1][B] | dut/u_tdc/n169_s2/I1 |
9.038 | 0.822 | tINS | FF | 1 | R18C23[1][B] | dut/u_tdc/n169_s2/F |
9.038 | 0.000 | tNET | FF | 1 | R18C23[1][B] | dut/u_tdc/count_tmp_7_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | pclk | ||||
10.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
10.242 | 0.242 | tNET | RR | 1 | R18C23[1][B] | dut/u_tdc/count_tmp_7_s1/CLK |
9.842 | -0.400 | tSu | 1 | R18C23[1][B] | dut/u_tdc/count_tmp_7_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000% |
Arrival Data Path Delay | cell: 4.468, 50.798%; route: 3.869, 43.991%; tC2Q: 0.458, 5.211% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000% |
Path4
Path Summary:
Slack | 0.917 |
Data Arrival Time | 8.925 |
Data Required Time | 9.842 |
From | dut/u_tdc/q_d_2_s0 |
To | dut/u_tdc/count_tmp_8_s1 |
Launch Clk | pclk:[R] |
Latch Clk | pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pclk | ||||
0.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
0.242 | 0.242 | tNET | RR | 1 | R22C22[1][A] | dut/u_tdc/q_d_2_s0/CLK |
0.700 | 0.458 | tC2Q | RR | 2 | R22C22[1][A] | dut/u_tdc/q_d_2_s0/Q |
1.120 | 0.420 | tNET | RR | 1 | R21C22[2][B] | dut/u_tdc/n175_s8/I2 |
2.219 | 1.099 | tINS | RF | 9 | R21C22[2][B] | dut/u_tdc/n175_s8/F |
3.050 | 0.831 | tNET | FF | 1 | R20C22[3][B] | dut/u_tdc/n174_s5/I1 |
3.676 | 0.626 | tINS | FF | 3 | R20C22[3][B] | dut/u_tdc/n174_s5/F |
5.459 | 1.783 | tNET | FF | 1 | R17C22[2][B] | dut/u_tdc/n170_s6/I2 |
6.520 | 1.061 | tINS | FR | 5 | R17C22[2][B] | dut/u_tdc/n170_s6/F |
6.945 | 0.425 | tNET | RR | 1 | R17C23[0][B] | dut/u_tdc/n168_s6/I0 |
7.767 | 0.822 | tINS | RF | 1 | R17C23[0][B] | dut/u_tdc/n168_s6/F |
8.103 | 0.336 | tNET | FF | 1 | R17C23[0][A] | dut/u_tdc/n168_s2/I3 |
8.925 | 0.822 | tINS | FF | 1 | R17C23[0][A] | dut/u_tdc/n168_s2/F |
8.925 | 0.000 | tNET | FF | 1 | R17C23[0][A] | dut/u_tdc/count_tmp_8_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | pclk | ||||
10.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
10.242 | 0.242 | tNET | RR | 1 | R17C23[0][A] | dut/u_tdc/count_tmp_8_s1/CLK |
9.842 | -0.400 | tSu | 1 | R17C23[0][A] | dut/u_tdc/count_tmp_8_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000% |
Arrival Data Path Delay | cell: 4.430, 51.019%; route: 3.795, 43.702%; tC2Q: 0.458, 5.279% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000% |
Path5
Path Summary:
Slack | 1.204 |
Data Arrival Time | 8.638 |
Data Required Time | 9.842 |
From | dut/u_tdc/q_d_2_s0 |
To | dut/u_tdc/count_tmp_9_s1 |
Launch Clk | pclk:[R] |
Latch Clk | pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pclk | ||||
0.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
0.242 | 0.242 | tNET | RR | 1 | R22C22[1][A] | dut/u_tdc/q_d_2_s0/CLK |
0.700 | 0.458 | tC2Q | RR | 2 | R22C22[1][A] | dut/u_tdc/q_d_2_s0/Q |
1.120 | 0.420 | tNET | RR | 1 | R21C22[2][B] | dut/u_tdc/n175_s8/I2 |
2.219 | 1.099 | tINS | RF | 9 | R21C22[2][B] | dut/u_tdc/n175_s8/F |
3.050 | 0.831 | tNET | FF | 1 | R20C22[3][B] | dut/u_tdc/n174_s5/I1 |
3.676 | 0.626 | tINS | FF | 3 | R20C22[3][B] | dut/u_tdc/n174_s5/F |
5.459 | 1.783 | tNET | FF | 1 | R17C22[2][B] | dut/u_tdc/n170_s6/I2 |
6.558 | 1.099 | tINS | FF | 5 | R17C22[2][B] | dut/u_tdc/n170_s6/F |
6.569 | 0.011 | tNET | FF | 1 | R17C22[3][B] | dut/u_tdc/n167_s4/I0 |
7.601 | 1.032 | tINS | FF | 1 | R17C22[3][B] | dut/u_tdc/n167_s4/F |
7.606 | 0.005 | tNET | FF | 1 | R17C22[0][B] | dut/u_tdc/n167_s2/I3 |
8.638 | 1.032 | tINS | FF | 1 | R17C22[0][B] | dut/u_tdc/n167_s2/F |
8.638 | 0.000 | tNET | FF | 1 | R17C22[0][B] | dut/u_tdc/count_tmp_9_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | pclk | ||||
10.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
10.242 | 0.242 | tNET | RR | 1 | R17C22[0][B] | dut/u_tdc/count_tmp_9_s1/CLK |
9.842 | -0.400 | tSu | 1 | R17C22[0][B] | dut/u_tdc/count_tmp_9_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000% |
Arrival Data Path Delay | cell: 4.888, 58.216%; route: 3.050, 36.325%; tC2Q: 0.458, 5.459% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000% |
Path6
Path Summary:
Slack | 1.360 |
Data Arrival Time | 8.482 |
Data Required Time | 9.842 |
From | dut/u_tdc/q_d_7_s0 |
To | dut/u_tdc/count_tmp_3_s1 |
Launch Clk | pclk:[R] |
Latch Clk | pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pclk | ||||
0.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
0.242 | 0.242 | tNET | RR | 1 | R24C22[0][A] | dut/u_tdc/q_d_7_s0/CLK |
0.700 | 0.458 | tC2Q | RR | 2 | R24C22[0][A] | dut/u_tdc/q_d_7_s0/Q |
1.123 | 0.422 | tNET | RR | 1 | R23C22[3][A] | dut/u_tdc/n176_s3/I1 |
2.222 | 1.099 | tINS | RF | 2 | R23C22[3][A] | dut/u_tdc/n176_s3/F |
3.032 | 0.810 | tNET | FF | 1 | R21C22[0][B] | dut/u_tdc/n175_s4/I0 |
4.131 | 1.099 | tINS | FF | 2 | R21C22[0][B] | dut/u_tdc/n175_s4/F |
4.940 | 0.809 | tNET | FF | 1 | R20C23[2][B] | dut/u_tdc/n174_s4/I0 |
5.566 | 0.626 | tINS | FF | 4 | R20C23[2][B] | dut/u_tdc/n174_s4/F |
6.071 | 0.506 | tNET | FF | 1 | R18C23[3][A] | dut/u_tdc/n173_s3/I1 |
7.170 | 1.099 | tINS | FF | 1 | R18C23[3][A] | dut/u_tdc/n173_s3/F |
7.660 | 0.490 | tNET | FF | 1 | R18C22[2][B] | dut/u_tdc/n173_s5/I2 |
8.482 | 0.822 | tINS | FF | 1 | R18C22[2][B] | dut/u_tdc/n173_s5/F |
8.482 | 0.000 | tNET | FF | 1 | R18C22[2][B] | dut/u_tdc/count_tmp_3_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | pclk | ||||
10.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
10.242 | 0.242 | tNET | RR | 1 | R18C22[2][B] | dut/u_tdc/count_tmp_3_s1/CLK |
9.842 | -0.400 | tSu | 1 | R18C22[2][B] | dut/u_tdc/count_tmp_3_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000% |
Arrival Data Path Delay | cell: 4.745, 57.584%; route: 3.037, 36.854%; tC2Q: 0.458, 5.562% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000% |
Path7
Path Summary:
Slack | 1.618 |
Data Arrival Time | 8.224 |
Data Required Time | 9.842 |
From | dut/u_tdc/q_d_7_s0 |
To | dut/u_tdc/count_tmp_6_s1 |
Launch Clk | pclk:[R] |
Latch Clk | pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pclk | ||||
0.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
0.242 | 0.242 | tNET | RR | 1 | R24C22[0][A] | dut/u_tdc/q_d_7_s0/CLK |
0.700 | 0.458 | tC2Q | RR | 2 | R24C22[0][A] | dut/u_tdc/q_d_7_s0/Q |
1.123 | 0.422 | tNET | RR | 1 | R23C22[3][A] | dut/u_tdc/n176_s3/I1 |
2.222 | 1.099 | tINS | RF | 2 | R23C22[3][A] | dut/u_tdc/n176_s3/F |
3.032 | 0.810 | tNET | FF | 1 | R21C22[0][B] | dut/u_tdc/n175_s4/I0 |
4.131 | 1.099 | tINS | FF | 2 | R21C22[0][B] | dut/u_tdc/n175_s4/F |
4.940 | 0.809 | tNET | FF | 1 | R20C23[2][B] | dut/u_tdc/n174_s4/I0 |
5.566 | 0.626 | tINS | FF | 4 | R20C23[2][B] | dut/u_tdc/n174_s4/F |
6.071 | 0.506 | tNET | FF | 1 | R18C23[3][B] | dut/u_tdc/n170_s3/I2 |
7.170 | 1.099 | tINS | FF | 4 | R18C23[3][B] | dut/u_tdc/n170_s3/F |
7.192 | 0.022 | tNET | FF | 1 | R18C23[1][A] | dut/u_tdc/n170_s10/I1 |
8.224 | 1.032 | tINS | FF | 1 | R18C23[1][A] | dut/u_tdc/n170_s10/F |
8.224 | 0.000 | tNET | FF | 1 | R18C23[1][A] | dut/u_tdc/count_tmp_6_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | pclk | ||||
10.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
10.242 | 0.242 | tNET | RR | 1 | R18C23[1][A] | dut/u_tdc/count_tmp_6_s1/CLK |
9.842 | -0.400 | tSu | 1 | R18C23[1][A] | dut/u_tdc/count_tmp_6_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000% |
Arrival Data Path Delay | cell: 4.955, 62.077%; route: 2.569, 32.181%; tC2Q: 0.458, 5.742% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000% |
Path8
Path Summary:
Slack | 1.797 |
Data Arrival Time | 8.045 |
Data Required Time | 9.842 |
From | dut/u_tdc/q_d_2_s0 |
To | dut/u_tdc/count_tmp_2_s1 |
Launch Clk | pclk:[R] |
Latch Clk | pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pclk | ||||
0.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
0.242 | 0.242 | tNET | RR | 1 | R22C22[1][A] | dut/u_tdc/q_d_2_s0/CLK |
0.700 | 0.458 | tC2Q | RR | 2 | R22C22[1][A] | dut/u_tdc/q_d_2_s0/Q |
1.120 | 0.420 | tNET | RR | 1 | R21C22[2][B] | dut/u_tdc/n175_s8/I2 |
2.219 | 1.099 | tINS | RF | 9 | R21C22[2][B] | dut/u_tdc/n175_s8/F |
3.066 | 0.846 | tNET | FF | 1 | R18C22[1][A] | dut/u_tdc/n174_s6/I0 |
4.098 | 1.032 | tINS | FF | 2 | R18C22[1][A] | dut/u_tdc/n174_s6/F |
4.923 | 0.825 | tNET | FF | 1 | R18C23[2][B] | dut/u_tdc/n174_s3/I3 |
6.022 | 1.099 | tINS | FF | 4 | R18C23[2][B] | dut/u_tdc/n174_s3/F |
7.013 | 0.991 | tNET | FF | 1 | R20C22[2][A] | dut/u_tdc/n174_s7/I2 |
8.045 | 1.032 | tINS | FF | 1 | R20C22[2][A] | dut/u_tdc/n174_s7/F |
8.045 | 0.000 | tNET | FF | 1 | R20C22[2][A] | dut/u_tdc/count_tmp_2_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | pclk | ||||
10.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
10.242 | 0.242 | tNET | RR | 1 | R20C22[2][A] | dut/u_tdc/count_tmp_2_s1/CLK |
9.842 | -0.400 | tSu | 1 | R20C22[2][A] | dut/u_tdc/count_tmp_2_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000% |
Arrival Data Path Delay | cell: 4.262, 54.620%; route: 3.083, 39.506%; tC2Q: 0.458, 5.874% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000% |
Path9
Path Summary:
Slack | 2.278 |
Data Arrival Time | 7.564 |
Data Required Time | 9.842 |
From | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1 |
To | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1 |
Launch Clk | pclk:[R] |
Latch Clk | pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pclk | ||||
0.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
0.242 | 0.242 | tNET | RR | 1 | R21C21[1][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK |
0.700 | 0.458 | tC2Q | RF | 4 | R21C21[1][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/Q |
1.682 | 0.981 | tNET | FF | 1 | R21C17[3][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s9/I2 |
2.781 | 1.099 | tINS | FF | 1 | R21C17[3][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s9/F |
3.585 | 0.804 | tNET | FF | 1 | R20C18[3][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s6/I1 |
4.387 | 0.802 | tINS | FR | 1 | R20C18[3][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s6/F |
4.806 | 0.419 | tNET | RR | 1 | R21C18[1][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s4/I1 |
5.628 | 0.822 | tINS | RF | 9 | R21C18[1][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s4/F |
6.465 | 0.837 | tNET | FF | 1 | R21C21[2][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n240_s1/I3 |
7.564 | 1.099 | tINS | FF | 1 | R21C21[2][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n240_s1/F |
7.564 | 0.000 | tNET | FF | 1 | R21C21[2][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | pclk | ||||
10.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
10.242 | 0.242 | tNET | RR | 1 | R21C21[2][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK |
9.842 | -0.400 | tSu | 1 | R21C21[2][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000% |
Arrival Data Path Delay | cell: 3.822, 52.197%; route: 3.042, 41.543%; tC2Q: 0.458, 6.259% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000% |
Path10
Path Summary:
Slack | 2.318 |
Data Arrival Time | 7.524 |
Data Required Time | 9.842 |
From | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1 |
To | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1 |
Launch Clk | pclk:[R] |
Latch Clk | pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pclk | ||||
0.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
0.242 | 0.242 | tNET | RR | 1 | R21C21[1][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK |
0.700 | 0.458 | tC2Q | RF | 4 | R21C21[1][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/Q |
1.682 | 0.981 | tNET | FF | 1 | R21C17[3][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s9/I2 |
2.781 | 1.099 | tINS | FF | 1 | R21C17[3][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s9/F |
3.585 | 0.804 | tNET | FF | 1 | R20C18[3][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s6/I1 |
4.387 | 0.802 | tINS | FR | 1 | R20C18[3][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s6/F |
4.806 | 0.419 | tNET | RR | 1 | R21C18[1][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s4/I1 |
5.628 | 0.822 | tINS | RF | 9 | R21C18[1][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s4/F |
6.492 | 0.864 | tNET | FF | 1 | R21C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n239_s1/I2 |
7.524 | 1.032 | tINS | FF | 1 | R21C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n239_s1/F |
7.524 | 0.000 | tNET | FF | 1 | R21C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | pclk | ||||
10.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
10.242 | 0.242 | tNET | RR | 1 | R21C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK |
9.842 | -0.400 | tSu | 1 | R21C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000% |
Arrival Data Path Delay | cell: 3.755, 51.569%; route: 3.068, 42.137%; tC2Q: 0.458, 6.294% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000% |
Path11
Path Summary:
Slack | 2.318 |
Data Arrival Time | 7.524 |
Data Required Time | 9.842 |
From | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1 |
To | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1 |
Launch Clk | pclk:[R] |
Latch Clk | pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pclk | ||||
0.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
0.242 | 0.242 | tNET | RR | 1 | R21C21[1][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK |
0.700 | 0.458 | tC2Q | RF | 4 | R21C21[1][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/Q |
1.682 | 0.981 | tNET | FF | 1 | R21C17[3][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s9/I2 |
2.781 | 1.099 | tINS | FF | 1 | R21C17[3][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s9/F |
3.585 | 0.804 | tNET | FF | 1 | R20C18[3][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s6/I1 |
4.387 | 0.802 | tINS | FR | 1 | R20C18[3][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s6/F |
4.806 | 0.419 | tNET | RR | 1 | R21C18[1][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s4/I1 |
5.628 | 0.822 | tINS | RF | 9 | R21C18[1][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s4/F |
6.492 | 0.864 | tNET | FF | 1 | R21C20[2][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n238_s1/I2 |
7.524 | 1.032 | tINS | FF | 1 | R21C20[2][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n238_s1/F |
7.524 | 0.000 | tNET | FF | 1 | R21C20[2][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | pclk | ||||
10.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
10.242 | 0.242 | tNET | RR | 1 | R21C20[2][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK |
9.842 | -0.400 | tSu | 1 | R21C20[2][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000% |
Arrival Data Path Delay | cell: 3.755, 51.569%; route: 3.068, 42.137%; tC2Q: 0.458, 6.294% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000% |
Path12
Path Summary:
Slack | 2.454 |
Data Arrival Time | 7.388 |
Data Required Time | 9.842 |
From | dut/u_tdc/q_d_7_s0 |
To | dut/u_tdc/count_tmp_1_s1 |
Launch Clk | pclk:[R] |
Latch Clk | pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pclk | ||||
0.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
0.242 | 0.242 | tNET | RR | 1 | R24C22[0][A] | dut/u_tdc/q_d_7_s0/CLK |
0.700 | 0.458 | tC2Q | RR | 2 | R24C22[0][A] | dut/u_tdc/q_d_7_s0/Q |
1.123 | 0.422 | tNET | RR | 1 | R23C22[3][A] | dut/u_tdc/n176_s3/I1 |
2.222 | 1.099 | tINS | RF | 2 | R23C22[3][A] | dut/u_tdc/n176_s3/F |
3.032 | 0.810 | tNET | FF | 1 | R21C22[0][B] | dut/u_tdc/n175_s4/I0 |
4.131 | 1.099 | tINS | FF | 2 | R21C22[0][B] | dut/u_tdc/n175_s4/F |
4.940 | 0.809 | tNET | FF | 1 | R20C23[1][B] | dut/u_tdc/n175_s3/I0 |
5.762 | 0.822 | tINS | FF | 1 | R20C23[1][B] | dut/u_tdc/n175_s3/F |
6.566 | 0.804 | tNET | FF | 1 | R21C22[0][A] | dut/u_tdc/n175_s9/I2 |
7.388 | 0.822 | tINS | FF | 1 | R21C22[0][A] | dut/u_tdc/n175_s9/F |
7.388 | 0.000 | tNET | FF | 1 | R21C22[0][A] | dut/u_tdc/count_tmp_1_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | pclk | ||||
10.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
10.242 | 0.242 | tNET | RR | 1 | R21C22[0][A] | dut/u_tdc/count_tmp_1_s1/CLK |
9.842 | -0.400 | tSu | 1 | R21C22[0][A] | dut/u_tdc/count_tmp_1_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000% |
Arrival Data Path Delay | cell: 3.842, 53.765%; route: 2.846, 39.821%; tC2Q: 0.458, 6.414% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000% |
Path13
Path Summary:
Slack | 2.555 |
Data Arrival Time | 7.287 |
Data Required Time | 9.842 |
From | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1 |
To | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1 |
Launch Clk | pclk:[R] |
Latch Clk | pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pclk | ||||
0.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
0.242 | 0.242 | tNET | RR | 1 | R21C21[1][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK |
0.700 | 0.458 | tC2Q | RF | 4 | R21C21[1][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/Q |
1.682 | 0.981 | tNET | FF | 1 | R21C17[3][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s9/I2 |
2.781 | 1.099 | tINS | FF | 1 | R21C17[3][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s9/F |
3.585 | 0.804 | tNET | FF | 1 | R20C18[3][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s6/I1 |
4.387 | 0.802 | tINS | FR | 1 | R20C18[3][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s6/F |
4.806 | 0.419 | tNET | RR | 1 | R21C18[1][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s4/I1 |
5.628 | 0.822 | tINS | RF | 9 | R21C18[1][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s4/F |
6.465 | 0.837 | tNET | FF | 1 | R21C21[1][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n241_s1/I2 |
7.287 | 0.822 | tINS | FF | 1 | R21C21[1][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n241_s1/F |
7.287 | 0.000 | tNET | FF | 1 | R21C21[1][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | pclk | ||||
10.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
10.242 | 0.242 | tNET | RR | 1 | R21C21[1][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK |
9.842 | -0.400 | tSu | 1 | R21C21[1][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000% |
Arrival Data Path Delay | cell: 3.545, 50.318%; route: 3.042, 43.177%; tC2Q: 0.458, 6.506% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000% |
Path14
Path Summary:
Slack | 2.555 |
Data Arrival Time | 7.287 |
Data Required Time | 9.842 |
From | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1 |
To | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1 |
Launch Clk | pclk:[R] |
Latch Clk | pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pclk | ||||
0.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
0.242 | 0.242 | tNET | RR | 1 | R21C21[1][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK |
0.700 | 0.458 | tC2Q | RF | 4 | R21C21[1][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/Q |
1.682 | 0.981 | tNET | FF | 1 | R21C17[3][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s9/I2 |
2.781 | 1.099 | tINS | FF | 1 | R21C17[3][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s9/F |
3.585 | 0.804 | tNET | FF | 1 | R20C18[3][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s6/I1 |
4.387 | 0.802 | tINS | FR | 1 | R20C18[3][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s6/F |
4.806 | 0.419 | tNET | RR | 1 | R21C18[1][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s4/I1 |
5.628 | 0.822 | tINS | RF | 9 | R21C18[1][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s4/F |
6.465 | 0.837 | tNET | FF | 1 | R21C20[1][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s2/I3 |
7.287 | 0.822 | tINS | FF | 1 | R21C20[1][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s2/F |
7.287 | 0.000 | tNET | FF | 1 | R21C20[1][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | pclk | ||||
10.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
10.242 | 0.242 | tNET | RR | 1 | R21C20[1][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK |
9.842 | -0.400 | tSu | 1 | R21C20[1][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000% |
Arrival Data Path Delay | cell: 3.545, 50.318%; route: 3.042, 43.177%; tC2Q: 0.458, 6.506% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000% |
Path15
Path Summary:
Slack | 2.615 |
Data Arrival Time | 7.583 |
Data Required Time | 10.199 |
From | gw_gao_gvio_inst_0/u_la0_top/triger_level_cnt_3_s1 |
To | gw_gao_gvio_inst_0/u_la0_top/trigger_seq_start_s1 |
Launch Clk | pclk:[R] |
Latch Clk | pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pclk | ||||
0.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
0.242 | 0.242 | tNET | RR | 1 | R18C11[1][A] | gw_gao_gvio_inst_0/u_la0_top/triger_level_cnt_3_s1/CLK |
0.700 | 0.458 | tC2Q | RR | 3 | R18C11[1][A] | gw_gao_gvio_inst_0/u_la0_top/triger_level_cnt_3_s1/Q |
1.122 | 0.422 | tNET | RR | 1 | R18C11[3][B] | gw_gao_gvio_inst_0/u_la0_top/triger_level_cnt_3_s5/I2 |
2.183 | 1.061 | tINS | RR | 1 | R18C11[3][B] | gw_gao_gvio_inst_0/u_la0_top/triger_level_cnt_3_s5/F |
2.602 | 0.419 | tNET | RR | 1 | R18C12[2][B] | gw_gao_gvio_inst_0/u_la0_top/triger_level_cnt_3_s4/I2 |
3.701 | 1.099 | tINS | RF | 4 | R18C12[2][B] | gw_gao_gvio_inst_0/u_la0_top/triger_level_cnt_3_s4/F |
5.813 | 2.113 | tNET | FF | 1 | R23C18[3][A] | gw_gao_gvio_inst_0/u_la0_top/n1318_s1/I1 |
6.439 | 0.626 | tINS | FF | 1 | R23C18[3][A] | gw_gao_gvio_inst_0/u_la0_top/n1318_s1/F |
6.445 | 0.005 | tNET | FF | 1 | R23C18[2][B] | gw_gao_gvio_inst_0/u_la0_top/trigger_seq_start_s3/I3 |
7.247 | 0.802 | tINS | FR | 1 | R23C18[2][B] | gw_gao_gvio_inst_0/u_la0_top/trigger_seq_start_s3/F |
7.583 | 0.336 | tNET | RR | 1 | R23C18[2][A] | gw_gao_gvio_inst_0/u_la0_top/trigger_seq_start_s1/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | pclk | ||||
10.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
10.242 | 0.242 | tNET | RR | 1 | R23C18[2][A] | gw_gao_gvio_inst_0/u_la0_top/trigger_seq_start_s1/CLK |
10.199 | -0.043 | tSu | 1 | R23C18[2][A] | gw_gao_gvio_inst_0/u_la0_top/trigger_seq_start_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000% |
Arrival Data Path Delay | cell: 3.588, 48.874%; route: 3.295, 44.882%; tC2Q: 0.458, 6.243% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000% |
Path16
Path Summary:
Slack | 2.751 |
Data Arrival Time | 7.091 |
Data Required Time | 9.842 |
From | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1 |
To | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5 |
Launch Clk | pclk:[R] |
Latch Clk | pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pclk | ||||
0.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
0.242 | 0.242 | tNET | RR | 1 | R21C21[1][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK |
0.700 | 0.458 | tC2Q | RF | 4 | R21C21[1][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/Q |
1.682 | 0.981 | tNET | FF | 1 | R21C17[3][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s9/I2 |
2.781 | 1.099 | tINS | FF | 1 | R21C17[3][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s9/F |
3.585 | 0.804 | tNET | FF | 1 | R20C18[3][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s6/I1 |
4.387 | 0.802 | tINS | FR | 1 | R20C18[3][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s6/F |
4.806 | 0.419 | tNET | RR | 1 | R21C18[1][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s4/I1 |
5.628 | 0.822 | tINS | RF | 9 | R21C18[1][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s4/F |
6.465 | 0.837 | tNET | FF | 1 | R22C20[2][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n244_s3/I2 |
7.091 | 0.626 | tINS | FF | 1 | R22C20[2][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n244_s3/F |
7.091 | 0.000 | tNET | FF | 1 | R22C20[2][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | pclk | ||||
10.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
10.242 | 0.242 | tNET | RR | 1 | R22C20[2][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/CLK |
9.842 | -0.400 | tSu | 1 | R22C20[2][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000% |
Arrival Data Path Delay | cell: 3.349, 48.896%; route: 3.042, 44.412%; tC2Q: 0.458, 6.692% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000% |
Path17
Path Summary:
Slack | 2.786 |
Data Arrival Time | 7.412 |
Data Required Time | 10.199 |
From | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1 |
To | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1 |
Launch Clk | pclk:[R] |
Latch Clk | pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pclk | ||||
0.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
0.242 | 0.242 | tNET | RR | 1 | R21C21[1][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK |
0.700 | 0.458 | tC2Q | RF | 4 | R21C21[1][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/Q |
1.682 | 0.981 | tNET | FF | 1 | R21C17[3][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s9/I2 |
2.781 | 1.099 | tINS | FF | 1 | R21C17[3][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s9/F |
3.585 | 0.804 | tNET | FF | 1 | R20C18[3][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s6/I1 |
4.387 | 0.802 | tINS | FR | 1 | R20C18[3][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s6/F |
4.806 | 0.419 | tNET | RR | 1 | R21C18[1][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s4/I1 |
5.628 | 0.822 | tINS | RF | 9 | R21C18[1][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s4/F |
5.666 | 0.038 | tNET | FF | 1 | R21C18[2][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s4/I0 |
6.291 | 0.625 | tINS | FR | 1 | R21C18[2][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s4/F |
7.412 | 1.121 | tNET | RR | 1 | R18C18[1][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | pclk | ||||
10.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
10.242 | 0.242 | tNET | RR | 1 | R18C18[1][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK |
10.199 | -0.043 | tSu | 1 | R18C18[1][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000% |
Arrival Data Path Delay | cell: 3.348, 46.693%; route: 3.364, 46.915%; tC2Q: 0.458, 6.392% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000% |
Path18
Path Summary:
Slack | 3.112 |
Data Arrival Time | 7.087 |
Data Required Time | 10.199 |
From | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1 |
To | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1 |
Launch Clk | pclk:[R] |
Latch Clk | pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pclk | ||||
0.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
0.242 | 0.242 | tNET | RR | 1 | R20C20[1][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLK |
0.700 | 0.458 | tC2Q | RF | 6 | R20C20[1][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/Q |
2.010 | 1.309 | tNET | FF | 1 | R17C19[0][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s6/I3 |
2.812 | 0.802 | tINS | FR | 1 | R17C19[0][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s6/F |
3.231 | 0.419 | tNET | RR | 1 | R18C19[1][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s4/I3 |
4.263 | 1.032 | tINS | RF | 2 | R18C19[1][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s4/F |
5.093 | 0.831 | tNET | FF | 1 | R20C19[2][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s5/I0 |
5.719 | 0.626 | tINS | FF | 1 | R20C19[2][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s5/F |
5.725 | 0.005 | tNET | FF | 1 | R20C19[3][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s3/I2 |
6.751 | 1.026 | tINS | FR | 1 | R20C19[3][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s3/F |
7.087 | 0.336 | tNET | RR | 1 | R20C19[0][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | pclk | ||||
10.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
10.242 | 0.242 | tNET | RR | 1 | R20C19[0][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK |
10.199 | -0.043 | tSu | 1 | R20C19[0][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000% |
Arrival Data Path Delay | cell: 3.486, 50.927%; route: 2.901, 42.377%; tC2Q: 0.458, 6.696% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000% |
Path19
Path Summary:
Slack | 3.403 |
Data Arrival Time | 6.439 |
Data Required Time | 9.842 |
From | gw_gao_gvio_inst_0/u_la0_top/triger_level_cnt_3_s1 |
To | gw_gao_gvio_inst_0/u_la0_top/triger_s0 |
Launch Clk | pclk:[R] |
Latch Clk | pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pclk | ||||
0.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
0.242 | 0.242 | tNET | RR | 1 | R18C11[1][A] | gw_gao_gvio_inst_0/u_la0_top/triger_level_cnt_3_s1/CLK |
0.700 | 0.458 | tC2Q | RR | 3 | R18C11[1][A] | gw_gao_gvio_inst_0/u_la0_top/triger_level_cnt_3_s1/Q |
1.122 | 0.422 | tNET | RR | 1 | R18C11[3][B] | gw_gao_gvio_inst_0/u_la0_top/triger_level_cnt_3_s5/I2 |
2.183 | 1.061 | tINS | RR | 1 | R18C11[3][B] | gw_gao_gvio_inst_0/u_la0_top/triger_level_cnt_3_s5/F |
2.602 | 0.419 | tNET | RR | 1 | R18C12[2][B] | gw_gao_gvio_inst_0/u_la0_top/triger_level_cnt_3_s4/I2 |
3.701 | 1.099 | tINS | RF | 4 | R18C12[2][B] | gw_gao_gvio_inst_0/u_la0_top/triger_level_cnt_3_s4/F |
5.813 | 2.113 | tNET | FF | 1 | R23C18[0][B] | gw_gao_gvio_inst_0/u_la0_top/n1318_s2/I2 |
6.439 | 0.626 | tINS | FF | 1 | R23C18[0][B] | gw_gao_gvio_inst_0/u_la0_top/n1318_s2/F |
6.439 | 0.000 | tNET | FF | 1 | R23C18[0][B] | gw_gao_gvio_inst_0/u_la0_top/triger_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | pclk | ||||
10.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
10.242 | 0.242 | tNET | RR | 1 | R23C18[0][B] | gw_gao_gvio_inst_0/u_la0_top/triger_s0/CLK |
9.842 | -0.400 | tSu | 1 | R23C18[0][B] | gw_gao_gvio_inst_0/u_la0_top/triger_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000% |
Arrival Data Path Delay | cell: 2.786, 44.954%; route: 2.953, 47.651%; tC2Q: 0.458, 7.395% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000% |
Path20
Path Summary:
Slack | 3.459 |
Data Arrival Time | 6.383 |
Data Required Time | 9.842 |
From | dut/u_tdc/u_IDES8 |
To | dut/u_tdc/c_state_3_s0 |
Launch Clk | pclk:[R] |
Latch Clk | pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pclk | ||||
0.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
0.242 | 0.242 | tNET | RR | 8 | IOB23[B] | dut/u_tdc/u_IDES8/PCLK |
0.877 | 0.635 | tC2Q | RF | 3 | IOB23[B] | dut/u_tdc/u_IDES8/Q4 |
2.337 | 1.460 | tNET | FF | 1 | R24C22[1][B] | dut/u_tdc/n_state_3_s13/I0 |
3.436 | 1.099 | tINS | FF | 1 | R24C22[1][B] | dut/u_tdc/n_state_3_s13/F |
3.442 | 0.005 | tNET | FF | 1 | R24C22[2][B] | dut/u_tdc/n_state_3_s10/I0 |
4.541 | 1.099 | tINS | FF | 2 | R24C22[2][B] | dut/u_tdc/n_state_3_s10/F |
5.351 | 0.810 | tNET | FF | 1 | R25C23[0][A] | dut/u_tdc/n_state_3_s7/I2 |
6.383 | 1.032 | tINS | FF | 1 | R25C23[0][A] | dut/u_tdc/n_state_3_s7/F |
6.383 | 0.000 | tNET | FF | 1 | R25C23[0][A] | dut/u_tdc/c_state_3_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | pclk | ||||
10.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
10.242 | 0.242 | tNET | RR | 1 | R25C23[0][A] | dut/u_tdc/c_state_3_s0/CLK |
9.842 | -0.400 | tSu | 1 | R25C23[0][A] | dut/u_tdc/c_state_3_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000% |
Arrival Data Path Delay | cell: 3.230, 52.601%; route: 2.276, 37.058%; tC2Q: 0.635, 10.341% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000% |
Path21
Path Summary:
Slack | 3.550 |
Data Arrival Time | 6.292 |
Data Required Time | 9.842 |
From | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1 |
To | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1 |
Launch Clk | pclk:[R] |
Latch Clk | pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pclk | ||||
0.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
0.242 | 0.242 | tNET | RR | 1 | R21C21[1][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK |
0.700 | 0.458 | tC2Q | RF | 4 | R21C21[1][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/Q |
1.682 | 0.981 | tNET | FF | 1 | R21C17[3][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s9/I2 |
2.781 | 1.099 | tINS | FF | 1 | R21C17[3][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s9/F |
3.585 | 0.804 | tNET | FF | 1 | R20C18[3][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s6/I1 |
4.387 | 0.802 | tINS | FR | 1 | R20C18[3][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s6/F |
4.806 | 0.419 | tNET | RR | 1 | R21C18[1][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s4/I1 |
5.628 | 0.822 | tINS | RF | 9 | R21C18[1][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s4/F |
5.666 | 0.038 | tNET | FF | 1 | R21C18[0][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n243_s1/I2 |
6.292 | 0.626 | tINS | FF | 1 | R21C18[0][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n243_s1/F |
6.292 | 0.000 | tNET | FF | 1 | R21C18[0][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | pclk | ||||
10.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
10.242 | 0.242 | tNET | RR | 1 | R21C18[0][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK |
9.842 | -0.400 | tSu | 1 | R21C18[0][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000% |
Arrival Data Path Delay | cell: 3.349, 55.352%; route: 2.243, 37.073%; tC2Q: 0.458, 7.575% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000% |
Path22
Path Summary:
Slack | 3.550 |
Data Arrival Time | 6.292 |
Data Required Time | 9.842 |
From | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1 |
To | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1 |
Launch Clk | pclk:[R] |
Latch Clk | pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pclk | ||||
0.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
0.242 | 0.242 | tNET | RR | 1 | R21C21[1][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK |
0.700 | 0.458 | tC2Q | RF | 4 | R21C21[1][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/Q |
1.682 | 0.981 | tNET | FF | 1 | R21C17[3][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s9/I2 |
2.781 | 1.099 | tINS | FF | 1 | R21C17[3][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s9/F |
3.585 | 0.804 | tNET | FF | 1 | R20C18[3][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s6/I1 |
4.387 | 0.802 | tINS | FR | 1 | R20C18[3][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s6/F |
4.806 | 0.419 | tNET | RR | 1 | R21C18[1][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s4/I1 |
5.628 | 0.822 | tINS | RF | 9 | R21C18[1][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n237_s4/F |
5.666 | 0.038 | tNET | FF | 1 | R21C18[0][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n242_s1/I3 |
6.292 | 0.626 | tINS | FF | 1 | R21C18[0][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n242_s1/F |
6.292 | 0.000 | tNET | FF | 1 | R21C18[0][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | pclk | ||||
10.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
10.242 | 0.242 | tNET | RR | 1 | R21C18[0][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK |
9.842 | -0.400 | tSu | 1 | R21C18[0][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000% |
Arrival Data Path Delay | cell: 3.349, 55.352%; route: 2.243, 37.073%; tC2Q: 0.458, 7.575% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000% |
Path23
Path Summary:
Slack | 3.557 |
Data Arrival Time | 6.285 |
Data Required Time | 9.842 |
From | dut/u_tdc/start_d0_s0 |
To | dut/u_tdc/c_state_0_s0 |
Launch Clk | pclk:[R] |
Latch Clk | pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pclk | ||||
0.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
0.242 | 0.242 | tNET | RR | 1 | R18C22[1][B] | dut/u_tdc/start_d0_s0/CLK |
0.700 | 0.458 | tC2Q | RF | 7 | R18C22[1][B] | dut/u_tdc/start_d0_s0/Q |
1.695 | 0.995 | tNET | FF | 1 | R22C22[1][B] | dut/u_tdc/count_tmp_9_s5/I1 |
2.517 | 0.822 | tINS | FF | 7 | R22C22[1][B] | dut/u_tdc/count_tmp_9_s5/F |
3.338 | 0.821 | tNET | FF | 1 | R25C22[1][A] | dut/u_tdc/n_state_1_s9/I2 |
4.370 | 1.032 | tINS | FF | 2 | R25C22[1][A] | dut/u_tdc/n_state_1_s9/F |
5.186 | 0.816 | tNET | FF | 1 | R24C23[0][A] | dut/u_tdc/n_state_0_s8/I2 |
6.285 | 1.099 | tINS | FF | 1 | R24C23[0][A] | dut/u_tdc/n_state_0_s8/F |
6.285 | 0.000 | tNET | FF | 1 | R24C23[0][A] | dut/u_tdc/c_state_0_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | pclk | ||||
10.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
10.242 | 0.242 | tNET | RR | 1 | R24C23[0][A] | dut/u_tdc/c_state_0_s0/CLK |
9.842 | -0.400 | tSu | 1 | R24C23[0][A] | dut/u_tdc/c_state_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000% |
Arrival Data Path Delay | cell: 2.953, 48.867%; route: 2.632, 43.548%; tC2Q: 0.458, 7.585% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000% |
Path24
Path Summary:
Slack | 3.716 |
Data Arrival Time | 6.126 |
Data Required Time | 9.842 |
From | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_1_s1 |
To | gw_gao_gvio_inst_0/u_la0_top/start_reg_s0 |
Launch Clk | pclk:[R] |
Latch Clk | pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pclk | ||||
0.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
0.242 | 0.242 | tNET | RR | 1 | R24C19[1][A] | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_1_s1/CLK |
0.700 | 0.458 | tC2Q | RF | 10 | R24C19[1][A] | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_1_s1/Q |
1.866 | 1.166 | tNET | FF | 2 | R22C18[0][B] | gw_gao_gvio_inst_0/u_la0_top/n1248_s17/I1 |
2.416 | 0.550 | tINS | FR | 1 | R22C18[0][B] | gw_gao_gvio_inst_0/u_la0_top/n1248_s17/COUT |
2.416 | 0.000 | tNET | RR | 2 | R22C18[1][A] | gw_gao_gvio_inst_0/u_la0_top/n1248_s18/CIN |
2.473 | 0.057 | tINS | RF | 1 | R22C18[1][A] | gw_gao_gvio_inst_0/u_la0_top/n1248_s18/COUT |
2.473 | 0.000 | tNET | FF | 2 | R22C18[1][B] | gw_gao_gvio_inst_0/u_la0_top/n1248_s19/CIN |
2.530 | 0.057 | tINS | FF | 1 | R22C18[1][B] | gw_gao_gvio_inst_0/u_la0_top/n1248_s19/COUT |
2.530 | 0.000 | tNET | FF | 2 | R22C18[2][A] | gw_gao_gvio_inst_0/u_la0_top/n1248_s20/CIN |
2.587 | 0.057 | tINS | FF | 1 | R22C18[2][A] | gw_gao_gvio_inst_0/u_la0_top/n1248_s20/COUT |
2.587 | 0.000 | tNET | FF | 2 | R22C18[2][B] | gw_gao_gvio_inst_0/u_la0_top/n1248_s21/CIN |
2.644 | 0.057 | tINS | FF | 1 | R22C18[2][B] | gw_gao_gvio_inst_0/u_la0_top/n1248_s21/COUT |
2.644 | 0.000 | tNET | FF | 2 | R22C19[0][A] | gw_gao_gvio_inst_0/u_la0_top/n1248_s22/CIN |
2.698 | 0.054 | tINS | FR | 2 | R22C19[0][A] | gw_gao_gvio_inst_0/u_la0_top/n1248_s22/COUT |
3.649 | 0.951 | tNET | RR | 1 | R23C19[3][B] | gw_gao_gvio_inst_0/u_la0_top/start_reg1_s1/I1 |
4.675 | 1.026 | tINS | RR | 1 | R23C19[3][B] | gw_gao_gvio_inst_0/u_la0_top/start_reg1_s1/F |
5.094 | 0.419 | tNET | RR | 1 | R23C18[0][A] | gw_gao_gvio_inst_0/u_la0_top/start_reg1_s0/I1 |
6.126 | 1.032 | tINS | RF | 1 | R23C18[0][A] | gw_gao_gvio_inst_0/u_la0_top/start_reg1_s0/F |
6.126 | 0.000 | tNET | FF | 1 | R23C18[0][A] | gw_gao_gvio_inst_0/u_la0_top/start_reg_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | pclk | ||||
10.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
10.242 | 0.242 | tNET | RR | 1 | R23C18[0][A] | gw_gao_gvio_inst_0/u_la0_top/start_reg_s0/CLK |
9.842 | -0.400 | tSu | 1 | R23C18[0][A] | gw_gao_gvio_inst_0/u_la0_top/start_reg_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000% |
Arrival Data Path Delay | cell: 2.890, 49.119%; route: 2.535, 43.091%; tC2Q: 0.458, 7.790% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000% |
Path25
Path Summary:
Slack | 3.886 |
Data Arrival Time | 5.956 |
Data Required Time | 9.842 |
From | dut/u_tdc/u_IDES8 |
To | dut/u_tdc/c_state_2_s0 |
Launch Clk | pclk:[R] |
Latch Clk | pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pclk | ||||
0.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
0.242 | 0.242 | tNET | RR | 8 | IOB23[B] | dut/u_tdc/u_IDES8/PCLK |
0.877 | 0.635 | tC2Q | RF | 3 | IOB23[B] | dut/u_tdc/u_IDES8/Q4 |
2.337 | 1.460 | tNET | FF | 1 | R24C22[1][B] | dut/u_tdc/n_state_3_s13/I0 |
3.436 | 1.099 | tINS | FF | 1 | R24C22[1][B] | dut/u_tdc/n_state_3_s13/F |
3.442 | 0.005 | tNET | FF | 1 | R24C22[2][B] | dut/u_tdc/n_state_3_s10/I0 |
4.503 | 1.061 | tINS | FR | 2 | R24C22[2][B] | dut/u_tdc/n_state_3_s10/F |
4.924 | 0.421 | tNET | RR | 1 | R25C22[0][B] | dut/u_tdc/n_state_2_s8/I1 |
5.956 | 1.032 | tINS | RF | 1 | R25C22[0][B] | dut/u_tdc/n_state_2_s8/F |
5.956 | 0.000 | tNET | FF | 1 | R25C22[0][B] | dut/u_tdc/c_state_2_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | pclk | ||||
10.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
10.242 | 0.242 | tNET | RR | 1 | R25C22[0][B] | dut/u_tdc/c_state_2_s0/CLK |
9.842 | -0.400 | tSu | 1 | R25C22[0][B] | dut/u_tdc/c_state_2_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000% |
Arrival Data Path Delay | cell: 3.192, 55.867%; route: 1.887, 33.019%; tC2Q: 0.635, 11.114% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000% |
Hold Analysis Report
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 0.571 |
Data Arrival Time | 3.773 |
Data Required Time | 3.202 |
From | gw_gao_gvio_inst_0/u_la0_top/capture_end_tck_1_s0 |
To | gw_gao_gvio_inst_0/u_la0_top/capture_end_tck_2_s0 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | tck_pad_i:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL11[B] | tck_pad_i_ibuf/I |
1.392 | 1.392 | tINS | RR | 1 | IOL11[B] | tck_pad_i_ibuf/O |
1.392 | 0.000 | tNET | RR | 1 | R1C1 | gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i |
2.236 | 0.844 | tINS | RR | 242 | R1C1 | gw_gao_gvio_inst_0/u_gw_jtag/tck_o |
3.202 | 0.966 | tNET | RR | 1 | R22C19[0][B] | gw_gao_gvio_inst_0/u_la0_top/capture_end_tck_1_s0/CLK |
3.536 | 0.333 | tC2Q | RR | 2 | R22C19[0][B] | gw_gao_gvio_inst_0/u_la0_top/capture_end_tck_1_s0/Q |
3.773 | 0.238 | tNET | RR | 1 | R22C19[0][A] | gw_gao_gvio_inst_0/u_la0_top/capture_end_tck_2_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL11[B] | tck_pad_i_ibuf/I |
1.392 | 1.392 | tINS | RR | 1 | IOL11[B] | tck_pad_i_ibuf/O |
1.392 | 0.000 | tNET | RR | 1 | R1C1 | gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i |
2.236 | 0.844 | tINS | RR | 242 | R1C1 | gw_gao_gvio_inst_0/u_gw_jtag/tck_o |
3.202 | 0.966 | tNET | RR | 1 | R22C19[0][A] | gw_gao_gvio_inst_0/u_la0_top/capture_end_tck_2_s0/CLK |
3.202 | 0.000 | tHld | 1 | R22C19[0][A] | gw_gao_gvio_inst_0/u_la0_top/capture_end_tck_2_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 2.236, 69.836%; route: 0.966, 30.164% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.238, 41.613%; tC2Q: 0.333, 58.387% |
Required Clock Path Delay | cell: 2.236, 69.836%; route: 0.966, 30.164% |
Path2
Path Summary:
Slack | 0.703 |
Data Arrival Time | 4.066 |
Data Required Time | 3.362 |
From | gw_gao_gvio_inst_0/u_la0_top/address_counter_7_s0 |
To | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s |
Launch Clk | tck_pad_i:[R] |
Latch Clk | tck_pad_i:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL11[B] | tck_pad_i_ibuf/I |
1.392 | 1.392 | tINS | RR | 1 | IOL11[B] | tck_pad_i_ibuf/O |
1.392 | 0.000 | tNET | RR | 1 | R1C1 | gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i |
2.236 | 0.844 | tINS | RR | 242 | R1C1 | gw_gao_gvio_inst_0/u_gw_jtag/tck_o |
3.202 | 0.966 | tNET | RR | 1 | R24C11[0][B] | gw_gao_gvio_inst_0/u_la0_top/address_counter_7_s0/CLK |
3.536 | 0.333 | tC2Q | RR | 2 | R24C11[0][B] | gw_gao_gvio_inst_0/u_la0_top/address_counter_7_s0/Q |
4.066 | 0.530 | tNET | RR | 1 | BSRAM_R28[3] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/ADB[11] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL11[B] | tck_pad_i_ibuf/I |
1.392 | 1.392 | tINS | RR | 1 | IOL11[B] | tck_pad_i_ibuf/O |
1.392 | 0.000 | tNET | RR | 1 | R1C1 | gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i |
2.236 | 0.844 | tINS | RR | 242 | R1C1 | gw_gao_gvio_inst_0/u_gw_jtag/tck_o |
3.202 | 0.966 | tNET | RR | 1 | BSRAM_R28[3] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKB |
3.362 | 0.160 | tHld | 1 | BSRAM_R28[3] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 2.236, 69.836%; route: 0.966, 30.164% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.530, 61.384%; tC2Q: 0.333, 38.616% |
Required Clock Path Delay | cell: 2.236, 69.836%; route: 0.966, 30.164% |
Path3
Path Summary:
Slack | 0.708 |
Data Arrival Time | 3.910 |
Data Required Time | 3.202 |
From | gw_gao_gvio_inst_0/u_la0_top/bit_count_3_s1 |
To | gw_gao_gvio_inst_0/u_la0_top/bit_count_3_s1 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | tck_pad_i:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL11[B] | tck_pad_i_ibuf/I |
1.392 | 1.392 | tINS | RR | 1 | IOL11[B] | tck_pad_i_ibuf/O |
1.392 | 0.000 | tNET | RR | 1 | R1C1 | gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i |
2.236 | 0.844 | tINS | RR | 242 | R1C1 | gw_gao_gvio_inst_0/u_gw_jtag/tck_o |
3.202 | 0.966 | tNET | RR | 1 | R23C9[0][A] | gw_gao_gvio_inst_0/u_la0_top/bit_count_3_s1/CLK |
3.536 | 0.333 | tC2Q | RR | 3 | R23C9[0][A] | gw_gao_gvio_inst_0/u_la0_top/bit_count_3_s1/Q |
3.538 | 0.002 | tNET | RR | 1 | R23C9[0][A] | gw_gao_gvio_inst_0/u_la0_top/n482_s2/I2 |
3.910 | 0.372 | tINS | RF | 1 | R23C9[0][A] | gw_gao_gvio_inst_0/u_la0_top/n482_s2/F |
3.910 | 0.000 | tNET | FF | 1 | R23C9[0][A] | gw_gao_gvio_inst_0/u_la0_top/bit_count_3_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL11[B] | tck_pad_i_ibuf/I |
1.392 | 1.392 | tINS | RR | 1 | IOL11[B] | tck_pad_i_ibuf/O |
1.392 | 0.000 | tNET | RR | 1 | R1C1 | gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i |
2.236 | 0.844 | tINS | RR | 242 | R1C1 | gw_gao_gvio_inst_0/u_gw_jtag/tck_o |
3.202 | 0.966 | tNET | RR | 1 | R23C9[0][A] | gw_gao_gvio_inst_0/u_la0_top/bit_count_3_s1/CLK |
3.202 | 0.000 | tHld | 1 | R23C9[0][A] | gw_gao_gvio_inst_0/u_la0_top/bit_count_3_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 2.236, 69.836%; route: 0.966, 30.164% |
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101% |
Required Clock Path Delay | cell: 2.236, 69.836%; route: 0.966, 30.164% |
Path4
Path Summary:
Slack | 0.708 |
Data Arrival Time | 3.910 |
Data Required Time | 3.202 |
From | gw_gao_gvio_inst_0/u_la0_top/word_count_8_s0 |
To | gw_gao_gvio_inst_0/u_la0_top/word_count_8_s0 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | tck_pad_i:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL11[B] | tck_pad_i_ibuf/I |
1.392 | 1.392 | tINS | RR | 1 | IOL11[B] | tck_pad_i_ibuf/O |
1.392 | 0.000 | tNET | RR | 1 | R1C1 | gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i |
2.236 | 0.844 | tINS | RR | 242 | R1C1 | gw_gao_gvio_inst_0/u_gw_jtag/tck_o |
3.202 | 0.966 | tNET | RR | 1 | R17C13[1][A] | gw_gao_gvio_inst_0/u_la0_top/word_count_8_s0/CLK |
3.536 | 0.333 | tC2Q | RR | 5 | R17C13[1][A] | gw_gao_gvio_inst_0/u_la0_top/word_count_8_s0/Q |
3.538 | 0.002 | tNET | RR | 1 | R17C13[1][A] | gw_gao_gvio_inst_0/u_la0_top/data_to_word_counter_8_s0/I1 |
3.910 | 0.372 | tINS | RF | 1 | R17C13[1][A] | gw_gao_gvio_inst_0/u_la0_top/data_to_word_counter_8_s0/F |
3.910 | 0.000 | tNET | FF | 1 | R17C13[1][A] | gw_gao_gvio_inst_0/u_la0_top/word_count_8_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL11[B] | tck_pad_i_ibuf/I |
1.392 | 1.392 | tINS | RR | 1 | IOL11[B] | tck_pad_i_ibuf/O |
1.392 | 0.000 | tNET | RR | 1 | R1C1 | gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i |
2.236 | 0.844 | tINS | RR | 242 | R1C1 | gw_gao_gvio_inst_0/u_gw_jtag/tck_o |
3.202 | 0.966 | tNET | RR | 1 | R17C13[1][A] | gw_gao_gvio_inst_0/u_la0_top/word_count_8_s0/CLK |
3.202 | 0.000 | tHld | 1 | R17C13[1][A] | gw_gao_gvio_inst_0/u_la0_top/word_count_8_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 2.236, 69.836%; route: 0.966, 30.164% |
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101% |
Required Clock Path Delay | cell: 2.236, 69.836%; route: 0.966, 30.164% |
Path5
Path Summary:
Slack | 0.708 |
Data Arrival Time | 3.910 |
Data Required Time | 3.202 |
From | gw_gao_gvio_inst_0/u_gvio0_top/word_count_0_s1 |
To | gw_gao_gvio_inst_0/u_gvio0_top/word_count_0_s1 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | tck_pad_i:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL11[B] | tck_pad_i_ibuf/I |
1.392 | 1.392 | tINS | RR | 1 | IOL11[B] | tck_pad_i_ibuf/O |
1.392 | 0.000 | tNET | RR | 1 | R1C1 | gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i |
2.236 | 0.844 | tINS | RR | 242 | R1C1 | gw_gao_gvio_inst_0/u_gw_jtag/tck_o |
3.202 | 0.966 | tNET | RR | 1 | R21C6[1][A] | gw_gao_gvio_inst_0/u_gvio0_top/word_count_0_s1/CLK |
3.536 | 0.333 | tC2Q | RR | 5 | R21C6[1][A] | gw_gao_gvio_inst_0/u_gvio0_top/word_count_0_s1/Q |
3.538 | 0.002 | tNET | RR | 1 | R21C6[1][A] | gw_gao_gvio_inst_0/u_gvio0_top/data_to_word_counter_0_s3/I3 |
3.910 | 0.372 | tINS | RF | 1 | R21C6[1][A] | gw_gao_gvio_inst_0/u_gvio0_top/data_to_word_counter_0_s3/F |
3.910 | 0.000 | tNET | FF | 1 | R21C6[1][A] | gw_gao_gvio_inst_0/u_gvio0_top/word_count_0_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL11[B] | tck_pad_i_ibuf/I |
1.392 | 1.392 | tINS | RR | 1 | IOL11[B] | tck_pad_i_ibuf/O |
1.392 | 0.000 | tNET | RR | 1 | R1C1 | gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i |
2.236 | 0.844 | tINS | RR | 242 | R1C1 | gw_gao_gvio_inst_0/u_gw_jtag/tck_o |
3.202 | 0.966 | tNET | RR | 1 | R21C6[1][A] | gw_gao_gvio_inst_0/u_gvio0_top/word_count_0_s1/CLK |
3.202 | 0.000 | tHld | 1 | R21C6[1][A] | gw_gao_gvio_inst_0/u_gvio0_top/word_count_0_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 2.236, 69.836%; route: 0.966, 30.164% |
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101% |
Required Clock Path Delay | cell: 2.236, 69.836%; route: 0.966, 30.164% |
Path6
Path Summary:
Slack | 0.708 |
Data Arrival Time | 3.910 |
Data Required Time | 3.202 |
From | gw_gao_gvio_inst_0/u_gvio0_top/word_count_1_s0 |
To | gw_gao_gvio_inst_0/u_gvio0_top/word_count_1_s0 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | tck_pad_i:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL11[B] | tck_pad_i_ibuf/I |
1.392 | 1.392 | tINS | RR | 1 | IOL11[B] | tck_pad_i_ibuf/O |
1.392 | 0.000 | tNET | RR | 1 | R1C1 | gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i |
2.236 | 0.844 | tINS | RR | 242 | R1C1 | gw_gao_gvio_inst_0/u_gw_jtag/tck_o |
3.202 | 0.966 | tNET | RR | 1 | R23C4[0][A] | gw_gao_gvio_inst_0/u_gvio0_top/word_count_1_s0/CLK |
3.536 | 0.333 | tC2Q | RR | 4 | R23C4[0][A] | gw_gao_gvio_inst_0/u_gvio0_top/word_count_1_s0/Q |
3.538 | 0.002 | tNET | RR | 1 | R23C4[0][A] | gw_gao_gvio_inst_0/u_gvio0_top/data_to_word_counter_1_s2/I1 |
3.910 | 0.372 | tINS | RF | 1 | R23C4[0][A] | gw_gao_gvio_inst_0/u_gvio0_top/data_to_word_counter_1_s2/F |
3.910 | 0.000 | tNET | FF | 1 | R23C4[0][A] | gw_gao_gvio_inst_0/u_gvio0_top/word_count_1_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL11[B] | tck_pad_i_ibuf/I |
1.392 | 1.392 | tINS | RR | 1 | IOL11[B] | tck_pad_i_ibuf/O |
1.392 | 0.000 | tNET | RR | 1 | R1C1 | gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i |
2.236 | 0.844 | tINS | RR | 242 | R1C1 | gw_gao_gvio_inst_0/u_gw_jtag/tck_o |
3.202 | 0.966 | tNET | RR | 1 | R23C4[0][A] | gw_gao_gvio_inst_0/u_gvio0_top/word_count_1_s0/CLK |
3.202 | 0.000 | tHld | 1 | R23C4[0][A] | gw_gao_gvio_inst_0/u_gvio0_top/word_count_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 2.236, 69.836%; route: 0.966, 30.164% |
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101% |
Required Clock Path Delay | cell: 2.236, 69.836%; route: 0.966, 30.164% |
Path7
Path Summary:
Slack | 0.708 |
Data Arrival Time | 3.910 |
Data Required Time | 3.202 |
From | gw_gao_gvio_inst_0/u_gvio0_top/word_count_3_s0 |
To | gw_gao_gvio_inst_0/u_gvio0_top/word_count_3_s0 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | tck_pad_i:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL11[B] | tck_pad_i_ibuf/I |
1.392 | 1.392 | tINS | RR | 1 | IOL11[B] | tck_pad_i_ibuf/O |
1.392 | 0.000 | tNET | RR | 1 | R1C1 | gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i |
2.236 | 0.844 | tINS | RR | 242 | R1C1 | gw_gao_gvio_inst_0/u_gw_jtag/tck_o |
3.202 | 0.966 | tNET | RR | 1 | R21C4[0][A] | gw_gao_gvio_inst_0/u_gvio0_top/word_count_3_s0/CLK |
3.536 | 0.333 | tC2Q | RR | 2 | R21C4[0][A] | gw_gao_gvio_inst_0/u_gvio0_top/word_count_3_s0/Q |
3.538 | 0.002 | tNET | RR | 1 | R21C4[0][A] | gw_gao_gvio_inst_0/u_gvio0_top/data_to_word_counter_3_s2/I3 |
3.910 | 0.372 | tINS | RF | 1 | R21C4[0][A] | gw_gao_gvio_inst_0/u_gvio0_top/data_to_word_counter_3_s2/F |
3.910 | 0.000 | tNET | FF | 1 | R21C4[0][A] | gw_gao_gvio_inst_0/u_gvio0_top/word_count_3_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL11[B] | tck_pad_i_ibuf/I |
1.392 | 1.392 | tINS | RR | 1 | IOL11[B] | tck_pad_i_ibuf/O |
1.392 | 0.000 | tNET | RR | 1 | R1C1 | gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i |
2.236 | 0.844 | tINS | RR | 242 | R1C1 | gw_gao_gvio_inst_0/u_gw_jtag/tck_o |
3.202 | 0.966 | tNET | RR | 1 | R21C4[0][A] | gw_gao_gvio_inst_0/u_gvio0_top/word_count_3_s0/CLK |
3.202 | 0.000 | tHld | 1 | R21C4[0][A] | gw_gao_gvio_inst_0/u_gvio0_top/word_count_3_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 2.236, 69.836%; route: 0.966, 30.164% |
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101% |
Required Clock Path Delay | cell: 2.236, 69.836%; route: 0.966, 30.164% |
Path8
Path Summary:
Slack | 0.708 |
Data Arrival Time | 3.910 |
Data Required Time | 3.202 |
From | gw_gao_gvio_inst_0/u_gvio0_top/word_count_5_s0 |
To | gw_gao_gvio_inst_0/u_gvio0_top/word_count_5_s0 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | tck_pad_i:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL11[B] | tck_pad_i_ibuf/I |
1.392 | 1.392 | tINS | RR | 1 | IOL11[B] | tck_pad_i_ibuf/O |
1.392 | 0.000 | tNET | RR | 1 | R1C1 | gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i |
2.236 | 0.844 | tINS | RR | 242 | R1C1 | gw_gao_gvio_inst_0/u_gw_jtag/tck_o |
3.202 | 0.966 | tNET | RR | 1 | R20C6[0][A] | gw_gao_gvio_inst_0/u_gvio0_top/word_count_5_s0/CLK |
3.536 | 0.333 | tC2Q | RR | 3 | R20C6[0][A] | gw_gao_gvio_inst_0/u_gvio0_top/word_count_5_s0/Q |
3.538 | 0.002 | tNET | RR | 1 | R20C6[0][A] | gw_gao_gvio_inst_0/u_gvio0_top/data_to_word_counter_5_s2/I3 |
3.910 | 0.372 | tINS | RF | 1 | R20C6[0][A] | gw_gao_gvio_inst_0/u_gvio0_top/data_to_word_counter_5_s2/F |
3.910 | 0.000 | tNET | FF | 1 | R20C6[0][A] | gw_gao_gvio_inst_0/u_gvio0_top/word_count_5_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL11[B] | tck_pad_i_ibuf/I |
1.392 | 1.392 | tINS | RR | 1 | IOL11[B] | tck_pad_i_ibuf/O |
1.392 | 0.000 | tNET | RR | 1 | R1C1 | gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i |
2.236 | 0.844 | tINS | RR | 242 | R1C1 | gw_gao_gvio_inst_0/u_gw_jtag/tck_o |
3.202 | 0.966 | tNET | RR | 1 | R20C6[0][A] | gw_gao_gvio_inst_0/u_gvio0_top/word_count_5_s0/CLK |
3.202 | 0.000 | tHld | 1 | R20C6[0][A] | gw_gao_gvio_inst_0/u_gvio0_top/word_count_5_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 2.236, 69.836%; route: 0.966, 30.164% |
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101% |
Required Clock Path Delay | cell: 2.236, 69.836%; route: 0.966, 30.164% |
Path9
Path Summary:
Slack | 0.708 |
Data Arrival Time | 3.910 |
Data Required Time | 3.202 |
From | gw_gao_gvio_inst_0/u_gvio0_top/word_count_6_s0 |
To | gw_gao_gvio_inst_0/u_gvio0_top/word_count_6_s0 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | tck_pad_i:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL11[B] | tck_pad_i_ibuf/I |
1.392 | 1.392 | tINS | RR | 1 | IOL11[B] | tck_pad_i_ibuf/O |
1.392 | 0.000 | tNET | RR | 1 | R1C1 | gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i |
2.236 | 0.844 | tINS | RR | 242 | R1C1 | gw_gao_gvio_inst_0/u_gw_jtag/tck_o |
3.202 | 0.966 | tNET | RR | 1 | R20C6[1][A] | gw_gao_gvio_inst_0/u_gvio0_top/word_count_6_s0/CLK |
3.536 | 0.333 | tC2Q | RR | 2 | R20C6[1][A] | gw_gao_gvio_inst_0/u_gvio0_top/word_count_6_s0/Q |
3.538 | 0.002 | tNET | RR | 1 | R20C6[1][A] | gw_gao_gvio_inst_0/u_gvio0_top/data_to_word_counter_6_s2/I3 |
3.910 | 0.372 | tINS | RF | 1 | R20C6[1][A] | gw_gao_gvio_inst_0/u_gvio0_top/data_to_word_counter_6_s2/F |
3.910 | 0.000 | tNET | FF | 1 | R20C6[1][A] | gw_gao_gvio_inst_0/u_gvio0_top/word_count_6_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL11[B] | tck_pad_i_ibuf/I |
1.392 | 1.392 | tINS | RR | 1 | IOL11[B] | tck_pad_i_ibuf/O |
1.392 | 0.000 | tNET | RR | 1 | R1C1 | gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i |
2.236 | 0.844 | tINS | RR | 242 | R1C1 | gw_gao_gvio_inst_0/u_gw_jtag/tck_o |
3.202 | 0.966 | tNET | RR | 1 | R20C6[1][A] | gw_gao_gvio_inst_0/u_gvio0_top/word_count_6_s0/CLK |
3.202 | 0.000 | tHld | 1 | R20C6[1][A] | gw_gao_gvio_inst_0/u_gvio0_top/word_count_6_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 2.236, 69.836%; route: 0.966, 30.164% |
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101% |
Required Clock Path Delay | cell: 2.236, 69.836%; route: 0.966, 30.164% |
Path10
Path Summary:
Slack | 0.708 |
Data Arrival Time | 3.910 |
Data Required Time | 3.202 |
From | gw_gao_gvio_inst_0/u_gvio0_top/word_count_8_s0 |
To | gw_gao_gvio_inst_0/u_gvio0_top/word_count_8_s0 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | tck_pad_i:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL11[B] | tck_pad_i_ibuf/I |
1.392 | 1.392 | tINS | RR | 1 | IOL11[B] | tck_pad_i_ibuf/O |
1.392 | 0.000 | tNET | RR | 1 | R1C1 | gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i |
2.236 | 0.844 | tINS | RR | 242 | R1C1 | gw_gao_gvio_inst_0/u_gw_jtag/tck_o |
3.202 | 0.966 | tNET | RR | 1 | R23C4[1][A] | gw_gao_gvio_inst_0/u_gvio0_top/word_count_8_s0/CLK |
3.536 | 0.333 | tC2Q | RR | 4 | R23C4[1][A] | gw_gao_gvio_inst_0/u_gvio0_top/word_count_8_s0/Q |
3.538 | 0.002 | tNET | RR | 1 | R23C4[1][A] | gw_gao_gvio_inst_0/u_gvio0_top/data_to_word_counter_8_s2/I3 |
3.910 | 0.372 | tINS | RF | 1 | R23C4[1][A] | gw_gao_gvio_inst_0/u_gvio0_top/data_to_word_counter_8_s2/F |
3.910 | 0.000 | tNET | FF | 1 | R23C4[1][A] | gw_gao_gvio_inst_0/u_gvio0_top/word_count_8_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL11[B] | tck_pad_i_ibuf/I |
1.392 | 1.392 | tINS | RR | 1 | IOL11[B] | tck_pad_i_ibuf/O |
1.392 | 0.000 | tNET | RR | 1 | R1C1 | gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i |
2.236 | 0.844 | tINS | RR | 242 | R1C1 | gw_gao_gvio_inst_0/u_gw_jtag/tck_o |
3.202 | 0.966 | tNET | RR | 1 | R23C4[1][A] | gw_gao_gvio_inst_0/u_gvio0_top/word_count_8_s0/CLK |
3.202 | 0.000 | tHld | 1 | R23C4[1][A] | gw_gao_gvio_inst_0/u_gvio0_top/word_count_8_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 2.236, 69.836%; route: 0.966, 30.164% |
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101% |
Required Clock Path Delay | cell: 2.236, 69.836%; route: 0.966, 30.164% |
Path11
Path Summary:
Slack | 0.708 |
Data Arrival Time | 3.910 |
Data Required Time | 3.202 |
From | gw_gao_gvio_inst_0/u_gvio0_top/word_count_11_s0 |
To | gw_gao_gvio_inst_0/u_gvio0_top/word_count_11_s0 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | tck_pad_i:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL11[B] | tck_pad_i_ibuf/I |
1.392 | 1.392 | tINS | RR | 1 | IOL11[B] | tck_pad_i_ibuf/O |
1.392 | 0.000 | tNET | RR | 1 | R1C1 | gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i |
2.236 | 0.844 | tINS | RR | 242 | R1C1 | gw_gao_gvio_inst_0/u_gw_jtag/tck_o |
3.202 | 0.966 | tNET | RR | 1 | R22C4[1][A] | gw_gao_gvio_inst_0/u_gvio0_top/word_count_11_s0/CLK |
3.536 | 0.333 | tC2Q | RR | 3 | R22C4[1][A] | gw_gao_gvio_inst_0/u_gvio0_top/word_count_11_s0/Q |
3.538 | 0.002 | tNET | RR | 1 | R22C4[1][A] | gw_gao_gvio_inst_0/u_gvio0_top/data_to_word_counter_11_s2/I3 |
3.910 | 0.372 | tINS | RF | 1 | R22C4[1][A] | gw_gao_gvio_inst_0/u_gvio0_top/data_to_word_counter_11_s2/F |
3.910 | 0.000 | tNET | FF | 1 | R22C4[1][A] | gw_gao_gvio_inst_0/u_gvio0_top/word_count_11_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL11[B] | tck_pad_i_ibuf/I |
1.392 | 1.392 | tINS | RR | 1 | IOL11[B] | tck_pad_i_ibuf/O |
1.392 | 0.000 | tNET | RR | 1 | R1C1 | gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i |
2.236 | 0.844 | tINS | RR | 242 | R1C1 | gw_gao_gvio_inst_0/u_gw_jtag/tck_o |
3.202 | 0.966 | tNET | RR | 1 | R22C4[1][A] | gw_gao_gvio_inst_0/u_gvio0_top/word_count_11_s0/CLK |
3.202 | 0.000 | tHld | 1 | R22C4[1][A] | gw_gao_gvio_inst_0/u_gvio0_top/word_count_11_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 2.236, 69.836%; route: 0.966, 30.164% |
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101% |
Required Clock Path Delay | cell: 2.236, 69.836%; route: 0.966, 30.164% |
Path12
Path Summary:
Slack | 0.708 |
Data Arrival Time | 3.910 |
Data Required Time | 3.202 |
From | gw_gao_gvio_inst_0/u_gvio_icon_top/tdo_select_s5 |
To | gw_gao_gvio_inst_0/u_gvio_icon_top/tdo_select_s5 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | tck_pad_i:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL11[B] | tck_pad_i_ibuf/I |
1.392 | 1.392 | tINS | RR | 1 | IOL11[B] | tck_pad_i_ibuf/O |
1.392 | 0.000 | tNET | RR | 1 | R1C1 | gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i |
2.236 | 0.844 | tINS | RR | 242 | R1C1 | gw_gao_gvio_inst_0/u_gw_jtag/tck_o |
3.202 | 0.966 | tNET | RR | 1 | R18C6[0][A] | gw_gao_gvio_inst_0/u_gvio_icon_top/tdo_select_s5/CLK |
3.536 | 0.333 | tC2Q | RR | 2 | R18C6[0][A] | gw_gao_gvio_inst_0/u_gvio_icon_top/tdo_select_s5/Q |
3.538 | 0.002 | tNET | RR | 1 | R18C6[0][A] | gw_gao_gvio_inst_0/u_gvio_icon_top/n47_s4/I1 |
3.910 | 0.372 | tINS | RF | 1 | R18C6[0][A] | gw_gao_gvio_inst_0/u_gvio_icon_top/n47_s4/F |
3.910 | 0.000 | tNET | FF | 1 | R18C6[0][A] | gw_gao_gvio_inst_0/u_gvio_icon_top/tdo_select_s5/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL11[B] | tck_pad_i_ibuf/I |
1.392 | 1.392 | tINS | RR | 1 | IOL11[B] | tck_pad_i_ibuf/O |
1.392 | 0.000 | tNET | RR | 1 | R1C1 | gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i |
2.236 | 0.844 | tINS | RR | 242 | R1C1 | gw_gao_gvio_inst_0/u_gw_jtag/tck_o |
3.202 | 0.966 | tNET | RR | 1 | R18C6[0][A] | gw_gao_gvio_inst_0/u_gvio_icon_top/tdo_select_s5/CLK |
3.202 | 0.000 | tHld | 1 | R18C6[0][A] | gw_gao_gvio_inst_0/u_gvio_icon_top/tdo_select_s5 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 2.236, 69.836%; route: 0.966, 30.164% |
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101% |
Required Clock Path Delay | cell: 2.236, 69.836%; route: 0.966, 30.164% |
Path13
Path Summary:
Slack | 0.708 |
Data Arrival Time | 0.891 |
Data Required Time | 0.183 |
From | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1 |
To | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1 |
Launch Clk | pclk:[R] |
Latch Clk | pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pclk | ||||
0.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
0.183 | 0.183 | tNET | RR | 1 | R17C19[0][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLK |
0.516 | 0.333 | tC2Q | RR | 4 | R17C19[0][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/Q |
0.519 | 0.002 | tNET | RR | 1 | R17C19[0][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n165_s0/I1 |
0.891 | 0.372 | tINS | RF | 1 | R17C19[0][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/n165_s0/F |
0.891 | 0.000 | tNET | FF | 1 | R17C19[0][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pclk | ||||
0.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
0.183 | 0.183 | tNET | RR | 1 | R17C19[0][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLK |
0.183 | 0.000 | tHld | 1 | R17C19[0][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.183, 100.000% |
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.183, 100.000% |
Path14
Path Summary:
Slack | 0.708 |
Data Arrival Time | 0.891 |
Data Required Time | 0.183 |
From | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_6_s1 |
To | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_6_s1 |
Launch Clk | pclk:[R] |
Latch Clk | pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pclk | ||||
0.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
0.183 | 0.183 | tNET | RR | 1 | R23C19[1][A] | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_6_s1/CLK |
0.516 | 0.333 | tC2Q | RR | 3 | R23C19[1][A] | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_6_s1/Q |
0.519 | 0.002 | tNET | RR | 1 | R23C19[1][A] | gw_gao_gvio_inst_0/u_la0_top/n1336_s1/I2 |
0.891 | 0.372 | tINS | RF | 1 | R23C19[1][A] | gw_gao_gvio_inst_0/u_la0_top/n1336_s1/F |
0.891 | 0.000 | tNET | FF | 1 | R23C19[1][A] | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_6_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pclk | ||||
0.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
0.183 | 0.183 | tNET | RR | 1 | R23C19[1][A] | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_6_s1/CLK |
0.183 | 0.000 | tHld | 1 | R23C19[1][A] | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_6_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.183, 100.000% |
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.183, 100.000% |
Path15
Path Summary:
Slack | 0.709 |
Data Arrival Time | 3.911 |
Data Required Time | 3.202 |
From | gw_gao_gvio_inst_0/u_la0_top/bit_count_0_s1 |
To | gw_gao_gvio_inst_0/u_la0_top/bit_count_0_s1 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | tck_pad_i:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL11[B] | tck_pad_i_ibuf/I |
1.392 | 1.392 | tINS | RR | 1 | IOL11[B] | tck_pad_i_ibuf/O |
1.392 | 0.000 | tNET | RR | 1 | R1C1 | gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i |
2.236 | 0.844 | tINS | RR | 242 | R1C1 | gw_gao_gvio_inst_0/u_gw_jtag/tck_o |
3.202 | 0.966 | tNET | RR | 1 | R23C9[1][A] | gw_gao_gvio_inst_0/u_la0_top/bit_count_0_s1/CLK |
3.536 | 0.333 | tC2Q | RR | 6 | R23C9[1][A] | gw_gao_gvio_inst_0/u_la0_top/bit_count_0_s1/Q |
3.539 | 0.004 | tNET | RR | 1 | R23C9[1][A] | gw_gao_gvio_inst_0/u_la0_top/n485_s3/I0 |
3.911 | 0.372 | tINS | RF | 1 | R23C9[1][A] | gw_gao_gvio_inst_0/u_la0_top/n485_s3/F |
3.911 | 0.000 | tNET | FF | 1 | R23C9[1][A] | gw_gao_gvio_inst_0/u_la0_top/bit_count_0_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL11[B] | tck_pad_i_ibuf/I |
1.392 | 1.392 | tINS | RR | 1 | IOL11[B] | tck_pad_i_ibuf/O |
1.392 | 0.000 | tNET | RR | 1 | R1C1 | gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i |
2.236 | 0.844 | tINS | RR | 242 | R1C1 | gw_gao_gvio_inst_0/u_gw_jtag/tck_o |
3.202 | 0.966 | tNET | RR | 1 | R23C9[1][A] | gw_gao_gvio_inst_0/u_la0_top/bit_count_0_s1/CLK |
3.202 | 0.000 | tHld | 1 | R23C9[1][A] | gw_gao_gvio_inst_0/u_la0_top/bit_count_0_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 2.236, 69.836%; route: 0.966, 30.164% |
Arrival Data Path Delay | cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023% |
Required Clock Path Delay | cell: 2.236, 69.836%; route: 0.966, 30.164% |
Path16
Path Summary:
Slack | 0.709 |
Data Arrival Time | 3.911 |
Data Required Time | 3.202 |
From | gw_gao_gvio_inst_0/u_gvio0_top/bit_count_3_s1 |
To | gw_gao_gvio_inst_0/u_gvio0_top/bit_count_3_s1 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | tck_pad_i:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL11[B] | tck_pad_i_ibuf/I |
1.392 | 1.392 | tINS | RR | 1 | IOL11[B] | tck_pad_i_ibuf/O |
1.392 | 0.000 | tNET | RR | 1 | R1C1 | gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i |
2.236 | 0.844 | tINS | RR | 242 | R1C1 | gw_gao_gvio_inst_0/u_gw_jtag/tck_o |
3.202 | 0.966 | tNET | RR | 1 | R20C5[1][A] | gw_gao_gvio_inst_0/u_gvio0_top/bit_count_3_s1/CLK |
3.536 | 0.333 | tC2Q | RR | 3 | R20C5[1][A] | gw_gao_gvio_inst_0/u_gvio0_top/bit_count_3_s1/Q |
3.539 | 0.004 | tNET | RR | 1 | R20C5[1][A] | gw_gao_gvio_inst_0/u_gvio0_top/n536_s2/I3 |
3.911 | 0.372 | tINS | RF | 1 | R20C5[1][A] | gw_gao_gvio_inst_0/u_gvio0_top/n536_s2/F |
3.911 | 0.000 | tNET | FF | 1 | R20C5[1][A] | gw_gao_gvio_inst_0/u_gvio0_top/bit_count_3_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL11[B] | tck_pad_i_ibuf/I |
1.392 | 1.392 | tINS | RR | 1 | IOL11[B] | tck_pad_i_ibuf/O |
1.392 | 0.000 | tNET | RR | 1 | R1C1 | gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i |
2.236 | 0.844 | tINS | RR | 242 | R1C1 | gw_gao_gvio_inst_0/u_gw_jtag/tck_o |
3.202 | 0.966 | tNET | RR | 1 | R20C5[1][A] | gw_gao_gvio_inst_0/u_gvio0_top/bit_count_3_s1/CLK |
3.202 | 0.000 | tHld | 1 | R20C5[1][A] | gw_gao_gvio_inst_0/u_gvio0_top/bit_count_3_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 2.236, 69.836%; route: 0.966, 30.164% |
Arrival Data Path Delay | cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023% |
Required Clock Path Delay | cell: 2.236, 69.836%; route: 0.966, 30.164% |
Path17
Path Summary:
Slack | 0.709 |
Data Arrival Time | 3.911 |
Data Required Time | 3.202 |
From | gw_gao_gvio_inst_0/u_gvio0_top/bit_count_5_s1 |
To | gw_gao_gvio_inst_0/u_gvio0_top/bit_count_5_s1 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | tck_pad_i:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL11[B] | tck_pad_i_ibuf/I |
1.392 | 1.392 | tINS | RR | 1 | IOL11[B] | tck_pad_i_ibuf/O |
1.392 | 0.000 | tNET | RR | 1 | R1C1 | gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i |
2.236 | 0.844 | tINS | RR | 242 | R1C1 | gw_gao_gvio_inst_0/u_gw_jtag/tck_o |
3.202 | 0.966 | tNET | RR | 1 | R21C6[0][A] | gw_gao_gvio_inst_0/u_gvio0_top/bit_count_5_s1/CLK |
3.536 | 0.333 | tC2Q | RR | 3 | R21C6[0][A] | gw_gao_gvio_inst_0/u_gvio0_top/bit_count_5_s1/Q |
3.539 | 0.004 | tNET | RR | 1 | R21C6[0][A] | gw_gao_gvio_inst_0/u_gvio0_top/n534_s2/I3 |
3.911 | 0.372 | tINS | RF | 1 | R21C6[0][A] | gw_gao_gvio_inst_0/u_gvio0_top/n534_s2/F |
3.911 | 0.000 | tNET | FF | 1 | R21C6[0][A] | gw_gao_gvio_inst_0/u_gvio0_top/bit_count_5_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL11[B] | tck_pad_i_ibuf/I |
1.392 | 1.392 | tINS | RR | 1 | IOL11[B] | tck_pad_i_ibuf/O |
1.392 | 0.000 | tNET | RR | 1 | R1C1 | gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i |
2.236 | 0.844 | tINS | RR | 242 | R1C1 | gw_gao_gvio_inst_0/u_gw_jtag/tck_o |
3.202 | 0.966 | tNET | RR | 1 | R21C6[0][A] | gw_gao_gvio_inst_0/u_gvio0_top/bit_count_5_s1/CLK |
3.202 | 0.000 | tHld | 1 | R21C6[0][A] | gw_gao_gvio_inst_0/u_gvio0_top/bit_count_5_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 2.236, 69.836%; route: 0.966, 30.164% |
Arrival Data Path Delay | cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023% |
Required Clock Path Delay | cell: 2.236, 69.836%; route: 0.966, 30.164% |
Path18
Path Summary:
Slack | 0.709 |
Data Arrival Time | 3.911 |
Data Required Time | 3.202 |
From | gw_gao_gvio_inst_0/u_gvio0_top/bit_count_6_s1 |
To | gw_gao_gvio_inst_0/u_gvio0_top/bit_count_6_s1 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | tck_pad_i:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL11[B] | tck_pad_i_ibuf/I |
1.392 | 1.392 | tINS | RR | 1 | IOL11[B] | tck_pad_i_ibuf/O |
1.392 | 0.000 | tNET | RR | 1 | R1C1 | gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i |
2.236 | 0.844 | tINS | RR | 242 | R1C1 | gw_gao_gvio_inst_0/u_gw_jtag/tck_o |
3.202 | 0.966 | tNET | RR | 1 | R21C5[1][A] | gw_gao_gvio_inst_0/u_gvio0_top/bit_count_6_s1/CLK |
3.536 | 0.333 | tC2Q | RR | 3 | R21C5[1][A] | gw_gao_gvio_inst_0/u_gvio0_top/bit_count_6_s1/Q |
3.539 | 0.004 | tNET | RR | 1 | R21C5[1][A] | gw_gao_gvio_inst_0/u_gvio0_top/n533_s4/I2 |
3.911 | 0.372 | tINS | RF | 1 | R21C5[1][A] | gw_gao_gvio_inst_0/u_gvio0_top/n533_s4/F |
3.911 | 0.000 | tNET | FF | 1 | R21C5[1][A] | gw_gao_gvio_inst_0/u_gvio0_top/bit_count_6_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL11[B] | tck_pad_i_ibuf/I |
1.392 | 1.392 | tINS | RR | 1 | IOL11[B] | tck_pad_i_ibuf/O |
1.392 | 0.000 | tNET | RR | 1 | R1C1 | gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i |
2.236 | 0.844 | tINS | RR | 242 | R1C1 | gw_gao_gvio_inst_0/u_gw_jtag/tck_o |
3.202 | 0.966 | tNET | RR | 1 | R21C5[1][A] | gw_gao_gvio_inst_0/u_gvio0_top/bit_count_6_s1/CLK |
3.202 | 0.000 | tHld | 1 | R21C5[1][A] | gw_gao_gvio_inst_0/u_gvio0_top/bit_count_6_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 2.236, 69.836%; route: 0.966, 30.164% |
Arrival Data Path Delay | cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023% |
Required Clock Path Delay | cell: 2.236, 69.836%; route: 0.966, 30.164% |
Path19
Path Summary:
Slack | 0.710 |
Data Arrival Time | 3.912 |
Data Required Time | 3.202 |
From | gw_gao_gvio_inst_0/u_la0_top/word_count_4_s0 |
To | gw_gao_gvio_inst_0/u_la0_top/word_count_4_s0 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | tck_pad_i:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL11[B] | tck_pad_i_ibuf/I |
1.392 | 1.392 | tINS | RR | 1 | IOL11[B] | tck_pad_i_ibuf/O |
1.392 | 0.000 | tNET | RR | 1 | R1C1 | gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i |
2.236 | 0.844 | tINS | RR | 242 | R1C1 | gw_gao_gvio_inst_0/u_gw_jtag/tck_o |
3.202 | 0.966 | tNET | RR | 1 | R18C13[1][A] | gw_gao_gvio_inst_0/u_la0_top/word_count_4_s0/CLK |
3.536 | 0.333 | tC2Q | RR | 4 | R18C13[1][A] | gw_gao_gvio_inst_0/u_la0_top/word_count_4_s0/Q |
3.540 | 0.005 | tNET | RR | 1 | R18C13[1][A] | gw_gao_gvio_inst_0/u_la0_top/data_to_word_counter_4_s0/I1 |
3.912 | 0.372 | tINS | RF | 1 | R18C13[1][A] | gw_gao_gvio_inst_0/u_la0_top/data_to_word_counter_4_s0/F |
3.912 | 0.000 | tNET | FF | 1 | R18C13[1][A] | gw_gao_gvio_inst_0/u_la0_top/word_count_4_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL11[B] | tck_pad_i_ibuf/I |
1.392 | 1.392 | tINS | RR | 1 | IOL11[B] | tck_pad_i_ibuf/O |
1.392 | 0.000 | tNET | RR | 1 | R1C1 | gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i |
2.236 | 0.844 | tINS | RR | 242 | R1C1 | gw_gao_gvio_inst_0/u_gw_jtag/tck_o |
3.202 | 0.966 | tNET | RR | 1 | R18C13[1][A] | gw_gao_gvio_inst_0/u_la0_top/word_count_4_s0/CLK |
3.202 | 0.000 | tHld | 1 | R18C13[1][A] | gw_gao_gvio_inst_0/u_la0_top/word_count_4_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 2.236, 69.836%; route: 0.966, 30.164% |
Arrival Data Path Delay | cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945% |
Required Clock Path Delay | cell: 2.236, 69.836%; route: 0.966, 30.164% |
Path20
Path Summary:
Slack | 0.710 |
Data Arrival Time | 3.912 |
Data Required Time | 3.202 |
From | gw_gao_gvio_inst_0/u_gvio0_top/module_state_1_s0 |
To | gw_gao_gvio_inst_0/u_gvio0_top/module_state_1_s0 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | tck_pad_i:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL11[B] | tck_pad_i_ibuf/I |
1.392 | 1.392 | tINS | RR | 1 | IOL11[B] | tck_pad_i_ibuf/O |
1.392 | 0.000 | tNET | RR | 1 | R1C1 | gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i |
2.236 | 0.844 | tINS | RR | 242 | R1C1 | gw_gao_gvio_inst_0/u_gw_jtag/tck_o |
3.202 | 0.966 | tNET | RR | 1 | R20C4[0][A] | gw_gao_gvio_inst_0/u_gvio0_top/module_state_1_s0/CLK |
3.536 | 0.333 | tC2Q | RR | 8 | R20C4[0][A] | gw_gao_gvio_inst_0/u_gvio0_top/module_state_1_s0/Q |
3.540 | 0.005 | tNET | RR | 1 | R20C4[0][A] | gw_gao_gvio_inst_0/u_gvio0_top/module_next_state_1_s5/I2 |
3.912 | 0.372 | tINS | RF | 1 | R20C4[0][A] | gw_gao_gvio_inst_0/u_gvio0_top/module_next_state_1_s5/F |
3.912 | 0.000 | tNET | FF | 1 | R20C4[0][A] | gw_gao_gvio_inst_0/u_gvio0_top/module_state_1_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL11[B] | tck_pad_i_ibuf/I |
1.392 | 1.392 | tINS | RR | 1 | IOL11[B] | tck_pad_i_ibuf/O |
1.392 | 0.000 | tNET | RR | 1 | R1C1 | gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i |
2.236 | 0.844 | tINS | RR | 242 | R1C1 | gw_gao_gvio_inst_0/u_gw_jtag/tck_o |
3.202 | 0.966 | tNET | RR | 1 | R20C4[0][A] | gw_gao_gvio_inst_0/u_gvio0_top/module_state_1_s0/CLK |
3.202 | 0.000 | tHld | 1 | R20C4[0][A] | gw_gao_gvio_inst_0/u_gvio0_top/module_state_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 2.236, 69.836%; route: 0.966, 30.164% |
Arrival Data Path Delay | cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945% |
Required Clock Path Delay | cell: 2.236, 69.836%; route: 0.966, 30.164% |
Path21
Path Summary:
Slack | 0.711 |
Data Arrival Time | 3.914 |
Data Required Time | 3.202 |
From | gw_gao_gvio_inst_0/u_la0_top/word_count_0_s0 |
To | gw_gao_gvio_inst_0/u_la0_top/word_count_0_s0 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | tck_pad_i:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL11[B] | tck_pad_i_ibuf/I |
1.392 | 1.392 | tINS | RR | 1 | IOL11[B] | tck_pad_i_ibuf/O |
1.392 | 0.000 | tNET | RR | 1 | R1C1 | gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i |
2.236 | 0.844 | tINS | RR | 242 | R1C1 | gw_gao_gvio_inst_0/u_gw_jtag/tck_o |
3.202 | 0.966 | tNET | RR | 1 | R20C13[1][A] | gw_gao_gvio_inst_0/u_la0_top/word_count_0_s0/CLK |
3.536 | 0.333 | tC2Q | RR | 5 | R20C13[1][A] | gw_gao_gvio_inst_0/u_la0_top/word_count_0_s0/Q |
3.542 | 0.006 | tNET | RR | 1 | R20C13[1][A] | gw_gao_gvio_inst_0/u_la0_top/data_to_word_counter_0_s1/I1 |
3.914 | 0.372 | tINS | RF | 1 | R20C13[1][A] | gw_gao_gvio_inst_0/u_la0_top/data_to_word_counter_0_s1/F |
3.914 | 0.000 | tNET | FF | 1 | R20C13[1][A] | gw_gao_gvio_inst_0/u_la0_top/word_count_0_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL11[B] | tck_pad_i_ibuf/I |
1.392 | 1.392 | tINS | RR | 1 | IOL11[B] | tck_pad_i_ibuf/O |
1.392 | 0.000 | tNET | RR | 1 | R1C1 | gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i |
2.236 | 0.844 | tINS | RR | 242 | R1C1 | gw_gao_gvio_inst_0/u_gw_jtag/tck_o |
3.202 | 0.966 | tNET | RR | 1 | R20C13[1][A] | gw_gao_gvio_inst_0/u_la0_top/word_count_0_s0/CLK |
3.202 | 0.000 | tHld | 1 | R20C13[1][A] | gw_gao_gvio_inst_0/u_la0_top/word_count_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 2.236, 69.836%; route: 0.966, 30.164% |
Arrival Data Path Delay | cell: 0.372, 52.303%; route: 0.006, 0.830%; tC2Q: 0.333, 46.867% |
Required Clock Path Delay | cell: 2.236, 69.836%; route: 0.966, 30.164% |
Path22
Path Summary:
Slack | 0.711 |
Data Arrival Time | 3.914 |
Data Required Time | 3.202 |
From | gw_gao_gvio_inst_0/u_la0_top/address_counter_0_s0 |
To | gw_gao_gvio_inst_0/u_la0_top/address_counter_0_s0 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | tck_pad_i:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL11[B] | tck_pad_i_ibuf/I |
1.392 | 1.392 | tINS | RR | 1 | IOL11[B] | tck_pad_i_ibuf/O |
1.392 | 0.000 | tNET | RR | 1 | R1C1 | gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i |
2.236 | 0.844 | tINS | RR | 242 | R1C1 | gw_gao_gvio_inst_0/u_gw_jtag/tck_o |
3.202 | 0.966 | tNET | RR | 1 | R23C13[1][A] | gw_gao_gvio_inst_0/u_la0_top/address_counter_0_s0/CLK |
3.536 | 0.333 | tC2Q | RR | 6 | R23C13[1][A] | gw_gao_gvio_inst_0/u_la0_top/address_counter_0_s0/Q |
3.542 | 0.006 | tNET | RR | 1 | R23C13[1][A] | gw_gao_gvio_inst_0/u_la0_top/data_to_addr_counter_0_s0/I0 |
3.914 | 0.372 | tINS | RF | 1 | R23C13[1][A] | gw_gao_gvio_inst_0/u_la0_top/data_to_addr_counter_0_s0/F |
3.914 | 0.000 | tNET | FF | 1 | R23C13[1][A] | gw_gao_gvio_inst_0/u_la0_top/address_counter_0_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL11[B] | tck_pad_i_ibuf/I |
1.392 | 1.392 | tINS | RR | 1 | IOL11[B] | tck_pad_i_ibuf/O |
1.392 | 0.000 | tNET | RR | 1 | R1C1 | gw_gao_gvio_inst_0/u_gw_jtag/tck_pad_i |
2.236 | 0.844 | tINS | RR | 242 | R1C1 | gw_gao_gvio_inst_0/u_gw_jtag/tck_o |
3.202 | 0.966 | tNET | RR | 1 | R23C13[1][A] | gw_gao_gvio_inst_0/u_la0_top/address_counter_0_s0/CLK |
3.202 | 0.000 | tHld | 1 | R23C13[1][A] | gw_gao_gvio_inst_0/u_la0_top/address_counter_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 2.236, 69.836%; route: 0.966, 30.164% |
Arrival Data Path Delay | cell: 0.372, 52.303%; route: 0.006, 0.830%; tC2Q: 0.333, 46.867% |
Required Clock Path Delay | cell: 2.236, 69.836%; route: 0.966, 30.164% |
Path23
Path Summary:
Slack | 0.711 |
Data Arrival Time | 0.894 |
Data Required Time | 0.183 |
From | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_0_s3 |
To | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_0_s3 |
Launch Clk | pclk:[R] |
Latch Clk | pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pclk | ||||
0.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
0.183 | 0.183 | tNET | RR | 1 | R24C19[0][A] | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_0_s3/CLK |
0.516 | 0.333 | tC2Q | RR | 12 | R24C19[0][A] | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_0_s3/Q |
0.522 | 0.006 | tNET | RR | 1 | R24C19[0][A] | gw_gao_gvio_inst_0/u_la0_top/n1342_s3/I2 |
0.894 | 0.372 | tINS | RF | 1 | R24C19[0][A] | gw_gao_gvio_inst_0/u_la0_top/n1342_s3/F |
0.894 | 0.000 | tNET | FF | 1 | R24C19[0][A] | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_0_s3/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pclk | ||||
0.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
0.183 | 0.183 | tNET | RR | 1 | R24C19[0][A] | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_0_s3/CLK |
0.183 | 0.000 | tHld | 1 | R24C19[0][A] | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_0_s3 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.183, 100.000% |
Arrival Data Path Delay | cell: 0.372, 52.303%; route: 0.006, 0.830%; tC2Q: 0.333, 46.867% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.183, 100.000% |
Path24
Path Summary:
Slack | 0.712 |
Data Arrival Time | 0.895 |
Data Required Time | 0.183 |
From | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_1_s1 |
To | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_1_s1 |
Launch Clk | pclk:[R] |
Latch Clk | pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pclk | ||||
0.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
0.183 | 0.183 | tNET | RR | 1 | R24C19[1][A] | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_1_s1/CLK |
0.516 | 0.333 | tC2Q | RR | 10 | R24C19[1][A] | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_1_s1/Q |
0.523 | 0.007 | tNET | RR | 1 | R24C19[1][A] | gw_gao_gvio_inst_0/u_la0_top/n1341_s1/I0 |
0.895 | 0.372 | tINS | RF | 1 | R24C19[1][A] | gw_gao_gvio_inst_0/u_la0_top/n1341_s1/F |
0.895 | 0.000 | tNET | FF | 1 | R24C19[1][A] | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_1_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pclk | ||||
0.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
0.183 | 0.183 | tNET | RR | 1 | R24C19[1][A] | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_1_s1/CLK |
0.183 | 0.000 | tHld | 1 | R24C19[1][A] | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_1_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.183, 100.000% |
Arrival Data Path Delay | cell: 0.372, 52.217%; route: 0.007, 0.994%; tC2Q: 0.333, 46.789% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.183, 100.000% |
Path25
Path Summary:
Slack | 0.712 |
Data Arrival Time | 0.895 |
Data Required Time | 0.183 |
From | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_4_s1 |
To | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_4_s1 |
Launch Clk | pclk:[R] |
Latch Clk | pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pclk | ||||
0.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
0.183 | 0.183 | tNET | RR | 1 | R23C19[0][A] | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_4_s1/CLK |
0.516 | 0.333 | tC2Q | RR | 7 | R23C19[0][A] | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_4_s1/Q |
0.523 | 0.007 | tNET | RR | 1 | R23C19[0][A] | gw_gao_gvio_inst_0/u_la0_top/n1338_s1/I0 |
0.895 | 0.372 | tINS | RF | 1 | R23C19[0][A] | gw_gao_gvio_inst_0/u_la0_top/n1338_s1/F |
0.895 | 0.000 | tNET | FF | 1 | R23C19[0][A] | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_4_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pclk | ||||
0.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
0.183 | 0.183 | tNET | RR | 1 | R23C19[0][A] | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_4_s1/CLK |
0.183 | 0.000 | tHld | 1 | R23C19[0][A] | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_4_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.183, 100.000% |
Arrival Data Path Delay | cell: 0.372, 52.217%; route: 0.007, 0.994%; tC2Q: 0.333, 46.789% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.183, 100.000% |
Recovery Analysis Report
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 2.304 |
Data Arrival Time | 7.894 |
Data Required Time | 10.199 |
From | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_gvio_inst_0/u_la0_top/triger_level_cnt_0_s3 |
Launch Clk | pclk:[F] |
Latch Clk | pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | pclk | ||||
5.000 | 0.000 | tCL | FF | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
5.257 | 0.257 | tNET | FF | 1 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/CLK |
5.715 | 0.458 | tC2Q | FF | 48 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q |
7.894 | 2.179 | tNET | FF | 1 | R18C11[2][A] | gw_gao_gvio_inst_0/u_la0_top/triger_level_cnt_0_s3/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | pclk | ||||
10.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
10.242 | 0.242 | tNET | RR | 1 | R18C11[2][A] | gw_gao_gvio_inst_0/u_la0_top/triger_level_cnt_0_s3/CLK |
10.199 | -0.043 | tSu | 1 | R18C11[2][A] | gw_gao_gvio_inst_0/u_la0_top/triger_level_cnt_0_s3 |
Path Statistics:
Clock Skew | -0.015 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.257, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.179, 82.621%; tC2Q: 0.458, 17.379% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000% |
Path2
Path Summary:
Slack | 2.304 |
Data Arrival Time | 7.894 |
Data Required Time | 10.199 |
From | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_gvio_inst_0/u_la0_top/triger_level_cnt_1_s1 |
Launch Clk | pclk:[F] |
Latch Clk | pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | pclk | ||||
5.000 | 0.000 | tCL | FF | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
5.257 | 0.257 | tNET | FF | 1 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/CLK |
5.715 | 0.458 | tC2Q | FF | 48 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q |
7.894 | 2.179 | tNET | FF | 1 | R18C11[1][B] | gw_gao_gvio_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | pclk | ||||
10.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
10.242 | 0.242 | tNET | RR | 1 | R18C11[1][B] | gw_gao_gvio_inst_0/u_la0_top/triger_level_cnt_1_s1/CLK |
10.199 | -0.043 | tSu | 1 | R18C11[1][B] | gw_gao_gvio_inst_0/u_la0_top/triger_level_cnt_1_s1 |
Path Statistics:
Clock Skew | -0.015 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.257, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.179, 82.621%; tC2Q: 0.458, 17.379% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000% |
Path3
Path Summary:
Slack | 2.304 |
Data Arrival Time | 7.894 |
Data Required Time | 10.199 |
From | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_gvio_inst_0/u_la0_top/triger_level_cnt_2_s1 |
Launch Clk | pclk:[F] |
Latch Clk | pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | pclk | ||||
5.000 | 0.000 | tCL | FF | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
5.257 | 0.257 | tNET | FF | 1 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/CLK |
5.715 | 0.458 | tC2Q | FF | 48 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q |
7.894 | 2.179 | tNET | FF | 1 | R18C11[0][B] | gw_gao_gvio_inst_0/u_la0_top/triger_level_cnt_2_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | pclk | ||||
10.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
10.242 | 0.242 | tNET | RR | 1 | R18C11[0][B] | gw_gao_gvio_inst_0/u_la0_top/triger_level_cnt_2_s1/CLK |
10.199 | -0.043 | tSu | 1 | R18C11[0][B] | gw_gao_gvio_inst_0/u_la0_top/triger_level_cnt_2_s1 |
Path Statistics:
Clock Skew | -0.015 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.257, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.179, 82.621%; tC2Q: 0.458, 17.379% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000% |
Path4
Path Summary:
Slack | 2.304 |
Data Arrival Time | 7.894 |
Data Required Time | 10.199 |
From | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_gvio_inst_0/u_la0_top/triger_level_cnt_3_s1 |
Launch Clk | pclk:[F] |
Latch Clk | pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | pclk | ||||
5.000 | 0.000 | tCL | FF | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
5.257 | 0.257 | tNET | FF | 1 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/CLK |
5.715 | 0.458 | tC2Q | FF | 48 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q |
7.894 | 2.179 | tNET | FF | 1 | R18C11[1][A] | gw_gao_gvio_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | pclk | ||||
10.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
10.242 | 0.242 | tNET | RR | 1 | R18C11[1][A] | gw_gao_gvio_inst_0/u_la0_top/triger_level_cnt_3_s1/CLK |
10.199 | -0.043 | tSu | 1 | R18C11[1][A] | gw_gao_gvio_inst_0/u_la0_top/triger_level_cnt_3_s1 |
Path Statistics:
Clock Skew | -0.015 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.257, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.179, 82.621%; tC2Q: 0.458, 17.379% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000% |
Path5
Path Summary:
Slack | 2.327 |
Data Arrival Time | 7.872 |
Data Required Time | 10.199 |
From | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_gvio_inst_0/u_la0_top/u_ao_match_0/match_sep_s0 |
Launch Clk | pclk:[F] |
Latch Clk | pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | pclk | ||||
5.000 | 0.000 | tCL | FF | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
5.257 | 0.257 | tNET | FF | 1 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/CLK |
5.715 | 0.458 | tC2Q | FF | 48 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q |
7.872 | 2.156 | tNET | FF | 1 | R18C12[0][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | pclk | ||||
10.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
10.242 | 0.242 | tNET | RR | 1 | R18C12[0][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLK |
10.199 | -0.043 | tSu | 1 | R18C12[0][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_match_0/match_sep_s0 |
Path Statistics:
Clock Skew | -0.015 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.257, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.156, 82.470%; tC2Q: 0.458, 17.530% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000% |
Path6
Path Summary:
Slack | 2.327 |
Data Arrival Time | 7.872 |
Data Required Time | 10.199 |
From | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_gvio_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0 |
Launch Clk | pclk:[F] |
Latch Clk | pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | pclk | ||||
5.000 | 0.000 | tCL | FF | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
5.257 | 0.257 | tNET | FF | 1 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/CLK |
5.715 | 0.458 | tC2Q | FF | 48 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q |
7.872 | 2.156 | tNET | FF | 1 | R18C12[1][A] | gw_gao_gvio_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | pclk | ||||
10.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
10.242 | 0.242 | tNET | RR | 1 | R18C12[1][A] | gw_gao_gvio_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLK |
10.199 | -0.043 | tSu | 1 | R18C12[1][A] | gw_gao_gvio_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0 |
Path Statistics:
Clock Skew | -0.015 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.257, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.156, 82.470%; tC2Q: 0.458, 17.530% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000% |
Path7
Path Summary:
Slack | 2.353 |
Data Arrival Time | 7.845 |
Data Required Time | 10.199 |
From | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_gvio_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0 |
Launch Clk | pclk:[F] |
Latch Clk | pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | pclk | ||||
5.000 | 0.000 | tCL | FF | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
5.257 | 0.257 | tNET | FF | 1 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/CLK |
5.715 | 0.458 | tC2Q | FF | 48 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q |
7.845 | 2.130 | tNET | FF | 1 | R17C11[0][A] | gw_gao_gvio_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | pclk | ||||
10.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
10.242 | 0.242 | tNET | RR | 1 | R17C11[0][A] | gw_gao_gvio_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLK |
10.199 | -0.043 | tSu | 1 | R17C11[0][A] | gw_gao_gvio_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0 |
Path Statistics:
Clock Skew | -0.015 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.257, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.130, 82.291%; tC2Q: 0.458, 17.709% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000% |
Path8
Path Summary:
Slack | 2.486 |
Data Arrival Time | 7.713 |
Data Required Time | 10.199 |
From | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1 |
Launch Clk | pclk:[F] |
Latch Clk | pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | pclk | ||||
5.000 | 0.000 | tCL | FF | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
5.257 | 0.257 | tNET | FF | 1 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/CLK |
5.715 | 0.458 | tC2Q | FF | 48 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q |
7.713 | 1.998 | tNET | FF | 1 | R17C18[0][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | pclk | ||||
10.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
10.242 | 0.242 | tNET | RR | 1 | R17C18[0][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLK |
10.199 | -0.043 | tSu | 1 | R17C18[0][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1 |
Path Statistics:
Clock Skew | -0.015 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.257, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.998, 81.339%; tC2Q: 0.458, 18.661% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000% |
Path9
Path Summary:
Slack | 2.486 |
Data Arrival Time | 7.713 |
Data Required Time | 10.199 |
From | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1 |
Launch Clk | pclk:[F] |
Latch Clk | pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | pclk | ||||
5.000 | 0.000 | tCL | FF | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
5.257 | 0.257 | tNET | FF | 1 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/CLK |
5.715 | 0.458 | tC2Q | FF | 48 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q |
7.713 | 1.998 | tNET | FF | 1 | R17C18[1][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | pclk | ||||
10.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
10.242 | 0.242 | tNET | RR | 1 | R17C18[1][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLK |
10.199 | -0.043 | tSu | 1 | R17C18[1][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1 |
Path Statistics:
Clock Skew | -0.015 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.257, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.998, 81.339%; tC2Q: 0.458, 18.661% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000% |
Path10
Path Summary:
Slack | 2.963 |
Data Arrival Time | 7.236 |
Data Required Time | 10.199 |
From | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1 |
Launch Clk | pclk:[F] |
Latch Clk | pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | pclk | ||||
5.000 | 0.000 | tCL | FF | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
5.257 | 0.257 | tNET | FF | 1 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/CLK |
5.715 | 0.458 | tC2Q | FF | 48 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q |
7.236 | 1.521 | tNET | FF | 1 | R18C19[1][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | pclk | ||||
10.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
10.242 | 0.242 | tNET | RR | 1 | R18C19[1][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/CLK |
10.199 | -0.043 | tSu | 1 | R18C19[1][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1 |
Path Statistics:
Clock Skew | -0.015 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.257, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.521, 76.842%; tC2Q: 0.458, 23.158% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000% |
Path11
Path Summary:
Slack | 2.963 |
Data Arrival Time | 7.236 |
Data Required Time | 10.199 |
From | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1 |
Launch Clk | pclk:[F] |
Latch Clk | pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | pclk | ||||
5.000 | 0.000 | tCL | FF | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
5.257 | 0.257 | tNET | FF | 1 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/CLK |
5.715 | 0.458 | tC2Q | FF | 48 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q |
7.236 | 1.521 | tNET | FF | 1 | R18C18[1][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | pclk | ||||
10.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
10.242 | 0.242 | tNET | RR | 1 | R18C18[1][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK |
10.199 | -0.043 | tSu | 1 | R18C18[1][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1 |
Path Statistics:
Clock Skew | -0.015 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.257, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.521, 76.842%; tC2Q: 0.458, 23.158% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000% |
Path12
Path Summary:
Slack | 2.969 |
Data Arrival Time | 7.230 |
Data Required Time | 10.199 |
From | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_gvio_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0 |
Launch Clk | pclk:[F] |
Latch Clk | pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | pclk | ||||
5.000 | 0.000 | tCL | FF | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
5.257 | 0.257 | tNET | FF | 1 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/CLK |
5.715 | 0.458 | tC2Q | FF | 48 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q |
7.230 | 1.515 | tNET | FF | 1 | R22C11[0][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | pclk | ||||
10.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
10.242 | 0.242 | tNET | RR | 1 | R22C11[0][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLK |
10.199 | -0.043 | tSu | 1 | R22C11[0][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0 |
Path Statistics:
Clock Skew | -0.015 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.257, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.515, 76.770%; tC2Q: 0.458, 23.230% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000% |
Path13
Path Summary:
Slack | 2.980 |
Data Arrival Time | 7.219 |
Data Required Time | 10.199 |
From | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1 |
Launch Clk | pclk:[F] |
Latch Clk | pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | pclk | ||||
5.000 | 0.000 | tCL | FF | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
5.257 | 0.257 | tNET | FF | 1 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/CLK |
5.715 | 0.458 | tC2Q | FF | 48 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q |
7.219 | 1.503 | tNET | FF | 1 | R17C20[1][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | pclk | ||||
10.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
10.242 | 0.242 | tNET | RR | 1 | R17C20[1][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLK |
10.199 | -0.043 | tSu | 1 | R17C20[1][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1 |
Path Statistics:
Clock Skew | -0.015 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.257, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.503, 76.636%; tC2Q: 0.458, 23.364% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000% |
Path14
Path Summary:
Slack | 2.986 |
Data Arrival Time | 7.213 |
Data Required Time | 10.199 |
From | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_gvio_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0 |
Launch Clk | pclk:[F] |
Latch Clk | pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | pclk | ||||
5.000 | 0.000 | tCL | FF | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
5.257 | 0.257 | tNET | FF | 1 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/CLK |
5.715 | 0.458 | tC2Q | FF | 48 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q |
7.213 | 1.497 | tNET | FF | 1 | R22C12[0][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | pclk | ||||
10.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
10.242 | 0.242 | tNET | RR | 1 | R22C12[0][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLK |
10.199 | -0.043 | tSu | 1 | R22C12[0][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0 |
Path Statistics:
Clock Skew | -0.015 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.257, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.497, 76.563%; tC2Q: 0.458, 23.437% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000% |
Path15
Path Summary:
Slack | 2.986 |
Data Arrival Time | 7.213 |
Data Required Time | 10.199 |
From | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_gvio_inst_0/u_la0_top/u_ao_match_0/trig_dly_0_s0 |
Launch Clk | pclk:[F] |
Latch Clk | pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | pclk | ||||
5.000 | 0.000 | tCL | FF | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
5.257 | 0.257 | tNET | FF | 1 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/CLK |
5.715 | 0.458 | tC2Q | FF | 48 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q |
7.213 | 1.497 | tNET | FF | 1 | R22C12[0][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_match_0/trig_dly_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | pclk | ||||
10.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
10.242 | 0.242 | tNET | RR | 1 | R22C12[0][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_match_0/trig_dly_0_s0/CLK |
10.199 | -0.043 | tSu | 1 | R22C12[0][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_match_0/trig_dly_0_s0 |
Path Statistics:
Clock Skew | -0.015 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.257, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.497, 76.563%; tC2Q: 0.458, 23.437% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000% |
Path16
Path Summary:
Slack | 2.998 |
Data Arrival Time | 7.201 |
Data Required Time | 10.199 |
From | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1 |
Launch Clk | pclk:[F] |
Latch Clk | pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | pclk | ||||
5.000 | 0.000 | tCL | FF | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
5.257 | 0.257 | tNET | FF | 1 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/CLK |
5.715 | 0.458 | tC2Q | FF | 48 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q |
7.201 | 1.485 | tNET | FF | 1 | R17C19[0][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | pclk | ||||
10.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
10.242 | 0.242 | tNET | RR | 1 | R17C19[0][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLK |
10.199 | -0.043 | tSu | 1 | R17C19[0][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1 |
Path Statistics:
Clock Skew | -0.015 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.257, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.485, 76.419%; tC2Q: 0.458, 23.581% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000% |
Path17
Path Summary:
Slack | 2.998 |
Data Arrival Time | 7.201 |
Data Required Time | 10.199 |
From | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1 |
Launch Clk | pclk:[F] |
Latch Clk | pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | pclk | ||||
5.000 | 0.000 | tCL | FF | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
5.257 | 0.257 | tNET | FF | 1 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/CLK |
5.715 | 0.458 | tC2Q | FF | 48 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q |
7.201 | 1.485 | tNET | FF | 1 | R17C19[1][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | pclk | ||||
10.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
10.242 | 0.242 | tNET | RR | 1 | R17C19[1][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLK |
10.199 | -0.043 | tSu | 1 | R17C19[1][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1 |
Path Statistics:
Clock Skew | -0.015 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.257, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.485, 76.419%; tC2Q: 0.458, 23.581% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000% |
Path18
Path Summary:
Slack | 2.998 |
Data Arrival Time | 7.201 |
Data Required Time | 10.199 |
From | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1 |
Launch Clk | pclk:[F] |
Latch Clk | pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | pclk | ||||
5.000 | 0.000 | tCL | FF | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
5.257 | 0.257 | tNET | FF | 1 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/CLK |
5.715 | 0.458 | tC2Q | FF | 48 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q |
7.201 | 1.485 | tNET | FF | 1 | R17C19[1][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | pclk | ||||
10.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
10.242 | 0.242 | tNET | RR | 1 | R17C19[1][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLK |
10.199 | -0.043 | tSu | 1 | R17C19[1][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1 |
Path Statistics:
Clock Skew | -0.015 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.257, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.485, 76.419%; tC2Q: 0.458, 23.581% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000% |
Path19
Path Summary:
Slack | 3.120 |
Data Arrival Time | 7.079 |
Data Required Time | 10.199 |
From | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1 |
Launch Clk | pclk:[F] |
Latch Clk | pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | pclk | ||||
5.000 | 0.000 | tCL | FF | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
5.257 | 0.257 | tNET | FF | 1 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/CLK |
5.715 | 0.458 | tC2Q | FF | 48 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q |
7.079 | 1.364 | tNET | FF | 1 | R20C19[1][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | pclk | ||||
10.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
10.242 | 0.242 | tNET | RR | 1 | R20C19[1][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLK |
10.199 | -0.043 | tSu | 1 | R20C19[1][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1 |
Path Statistics:
Clock Skew | -0.015 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.257, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.364, 74.846%; tC2Q: 0.458, 25.154% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000% |
Path20
Path Summary:
Slack | 3.120 |
Data Arrival Time | 7.079 |
Data Required Time | 10.199 |
From | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1 |
Launch Clk | pclk:[F] |
Latch Clk | pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | pclk | ||||
5.000 | 0.000 | tCL | FF | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
5.257 | 0.257 | tNET | FF | 1 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/CLK |
5.715 | 0.458 | tC2Q | FF | 48 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q |
7.079 | 1.364 | tNET | FF | 1 | R20C19[0][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | pclk | ||||
10.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
10.242 | 0.242 | tNET | RR | 1 | R20C19[0][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK |
10.199 | -0.043 | tSu | 1 | R20C19[0][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1 |
Path Statistics:
Clock Skew | -0.015 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.257, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.364, 74.846%; tC2Q: 0.458, 25.154% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000% |
Path21
Path Summary:
Slack | 3.124 |
Data Arrival Time | 7.075 |
Data Required Time | 10.199 |
From | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_gvio_inst_0/u_la0_top/capture_end_dly_s0 |
Launch Clk | pclk:[F] |
Latch Clk | pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | pclk | ||||
5.000 | 0.000 | tCL | FF | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
5.257 | 0.257 | tNET | FF | 1 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/CLK |
5.715 | 0.458 | tC2Q | FF | 48 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q |
7.075 | 1.359 | tNET | FF | 1 | R20C21[1][A] | gw_gao_gvio_inst_0/u_la0_top/capture_end_dly_s0/PRESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | pclk | ||||
10.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
10.242 | 0.242 | tNET | RR | 1 | R20C21[1][A] | gw_gao_gvio_inst_0/u_la0_top/capture_end_dly_s0/CLK |
10.199 | -0.043 | tSu | 1 | R20C21[1][A] | gw_gao_gvio_inst_0/u_la0_top/capture_end_dly_s0 |
Path Statistics:
Clock Skew | -0.015 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.257, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.359, 74.783%; tC2Q: 0.458, 25.217% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000% |
Path22
Path Summary:
Slack | 3.151 |
Data Arrival Time | 7.048 |
Data Required Time | 10.199 |
From | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1 |
Launch Clk | pclk:[F] |
Latch Clk | pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | pclk | ||||
5.000 | 0.000 | tCL | FF | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
5.257 | 0.257 | tNET | FF | 1 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/CLK |
5.715 | 0.458 | tC2Q | FF | 48 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q |
7.048 | 1.333 | tNET | FF | 1 | R21C18[0][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | pclk | ||||
10.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
10.242 | 0.242 | tNET | RR | 1 | R21C18[0][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK |
10.199 | -0.043 | tSu | 1 | R21C18[0][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1 |
Path Statistics:
Clock Skew | -0.015 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.257, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.333, 74.410%; tC2Q: 0.458, 25.590% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000% |
Path23
Path Summary:
Slack | 3.151 |
Data Arrival Time | 7.048 |
Data Required Time | 10.199 |
From | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1 |
Launch Clk | pclk:[F] |
Latch Clk | pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | pclk | ||||
5.000 | 0.000 | tCL | FF | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
5.257 | 0.257 | tNET | FF | 1 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/CLK |
5.715 | 0.458 | tC2Q | FF | 48 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q |
7.048 | 1.333 | tNET | FF | 1 | R21C18[0][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | pclk | ||||
10.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
10.242 | 0.242 | tNET | RR | 1 | R21C18[0][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK |
10.199 | -0.043 | tSu | 1 | R21C18[0][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1 |
Path Statistics:
Clock Skew | -0.015 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.257, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.333, 74.410%; tC2Q: 0.458, 25.590% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000% |
Path24
Path Summary:
Slack | 3.278 |
Data Arrival Time | 6.921 |
Data Required Time | 10.199 |
From | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1 |
Launch Clk | pclk:[F] |
Latch Clk | pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | pclk | ||||
5.000 | 0.000 | tCL | FF | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
5.257 | 0.257 | tNET | FF | 1 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/CLK |
5.715 | 0.458 | tC2Q | FF | 48 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q |
6.921 | 1.205 | tNET | FF | 1 | R20C20[1][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | pclk | ||||
10.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
10.242 | 0.242 | tNET | RR | 1 | R20C20[1][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLK |
10.199 | -0.043 | tSu | 1 | R20C20[1][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1 |
Path Statistics:
Clock Skew | -0.015 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.257, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.205, 72.453%; tC2Q: 0.458, 27.547% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000% |
Path25
Path Summary:
Slack | 3.625 |
Data Arrival Time | 6.573 |
Data Required Time | 10.199 |
From | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1 |
Launch Clk | pclk:[F] |
Latch Clk | pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | pclk | ||||
5.000 | 0.000 | tCL | FF | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
5.257 | 0.257 | tNET | FF | 1 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/CLK |
5.715 | 0.458 | tC2Q | FF | 48 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q |
6.573 | 0.858 | tNET | FF | 1 | R21C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | pclk | ||||
10.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
10.242 | 0.242 | tNET | RR | 1 | R21C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK |
10.199 | -0.043 | tSu | 1 | R21C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1 |
Path Statistics:
Clock Skew | -0.015 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.257, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.858, 65.180%; tC2Q: 0.458, 34.820% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.242, 100.000% |
Removal Analysis Report
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 5.837 |
Data Arrival Time | 6.033 |
Data Required Time | 0.196 |
From | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5 |
Launch Clk | pclk:[F] |
Latch Clk | pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | pclk | ||||
5.000 | 0.000 | tCL | FF | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
5.191 | 0.191 | tNET | FF | 1 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/CLK |
5.524 | 0.333 | tC2Q | FR | 48 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q |
6.033 | 0.508 | tNET | RR | 1 | R22C20[2][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pclk | ||||
0.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
0.183 | 0.183 | tNET | RR | 1 | R22C20[2][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/CLK |
0.196 | 0.012 | tHld | 1 | R22C20[2][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5 |
Path Statistics:
Clock Skew | -0.008 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.191, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.508, 60.399%; tC2Q: 0.333, 39.601% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.183, 100.000% |
Path2
Path Summary:
Slack | 5.843 |
Data Arrival Time | 6.039 |
Data Required Time | 0.196 |
From | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1 |
Launch Clk | pclk:[F] |
Latch Clk | pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | pclk | ||||
5.000 | 0.000 | tCL | FF | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
5.191 | 0.191 | tNET | FF | 1 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/CLK |
5.524 | 0.333 | tC2Q | FR | 48 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q |
6.039 | 0.515 | tNET | RR | 1 | R21C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pclk | ||||
0.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
0.183 | 0.183 | tNET | RR | 1 | R21C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK |
0.196 | 0.012 | tHld | 1 | R21C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1 |
Path Statistics:
Clock Skew | -0.008 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.191, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.515, 60.690%; tC2Q: 0.333, 39.310% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.183, 100.000% |
Path3
Path Summary:
Slack | 5.843 |
Data Arrival Time | 6.039 |
Data Required Time | 0.196 |
From | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1 |
Launch Clk | pclk:[F] |
Latch Clk | pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | pclk | ||||
5.000 | 0.000 | tCL | FF | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
5.191 | 0.191 | tNET | FF | 1 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/CLK |
5.524 | 0.333 | tC2Q | FR | 48 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q |
6.039 | 0.515 | tNET | RR | 1 | R21C20[2][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pclk | ||||
0.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
0.183 | 0.183 | tNET | RR | 1 | R21C20[2][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK |
0.196 | 0.012 | tHld | 1 | R21C20[2][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1 |
Path Statistics:
Clock Skew | -0.008 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.191, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.515, 60.690%; tC2Q: 0.333, 39.310% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.183, 100.000% |
Path4
Path Summary:
Slack | 5.843 |
Data Arrival Time | 6.039 |
Data Required Time | 0.196 |
From | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1 |
Launch Clk | pclk:[F] |
Latch Clk | pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | pclk | ||||
5.000 | 0.000 | tCL | FF | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
5.191 | 0.191 | tNET | FF | 1 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/CLK |
5.524 | 0.333 | tC2Q | FR | 48 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q |
6.039 | 0.515 | tNET | RR | 1 | R21C20[1][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pclk | ||||
0.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
0.183 | 0.183 | tNET | RR | 1 | R21C20[1][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK |
0.196 | 0.012 | tHld | 1 | R21C20[1][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1 |
Path Statistics:
Clock Skew | -0.008 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.191, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.515, 60.690%; tC2Q: 0.333, 39.310% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.183, 100.000% |
Path5
Path Summary:
Slack | 5.843 |
Data Arrival Time | 6.039 |
Data Required Time | 0.196 |
From | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_4_s1 |
Launch Clk | pclk:[F] |
Latch Clk | pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | pclk | ||||
5.000 | 0.000 | tCL | FF | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
5.191 | 0.191 | tNET | FF | 1 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/CLK |
5.524 | 0.333 | tC2Q | FR | 48 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q |
6.039 | 0.515 | tNET | RR | 1 | R23C19[0][A] | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_4_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pclk | ||||
0.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
0.183 | 0.183 | tNET | RR | 1 | R23C19[0][A] | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_4_s1/CLK |
0.196 | 0.012 | tHld | 1 | R23C19[0][A] | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_4_s1 |
Path Statistics:
Clock Skew | -0.008 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.191, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.515, 60.690%; tC2Q: 0.333, 39.310% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.183, 100.000% |
Path6
Path Summary:
Slack | 5.843 |
Data Arrival Time | 6.039 |
Data Required Time | 0.196 |
From | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_5_s1 |
Launch Clk | pclk:[F] |
Latch Clk | pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | pclk | ||||
5.000 | 0.000 | tCL | FF | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
5.191 | 0.191 | tNET | FF | 1 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/CLK |
5.524 | 0.333 | tC2Q | FR | 48 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q |
6.039 | 0.515 | tNET | RR | 1 | R23C19[0][B] | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_5_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pclk | ||||
0.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
0.183 | 0.183 | tNET | RR | 1 | R23C19[0][B] | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_5_s1/CLK |
0.196 | 0.012 | tHld | 1 | R23C19[0][B] | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_5_s1 |
Path Statistics:
Clock Skew | -0.008 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.191, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.515, 60.690%; tC2Q: 0.333, 39.310% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.183, 100.000% |
Path7
Path Summary:
Slack | 5.843 |
Data Arrival Time | 6.039 |
Data Required Time | 0.196 |
From | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_6_s1 |
Launch Clk | pclk:[F] |
Latch Clk | pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | pclk | ||||
5.000 | 0.000 | tCL | FF | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
5.191 | 0.191 | tNET | FF | 1 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/CLK |
5.524 | 0.333 | tC2Q | FR | 48 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q |
6.039 | 0.515 | tNET | RR | 1 | R23C19[1][A] | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_6_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pclk | ||||
0.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
0.183 | 0.183 | tNET | RR | 1 | R23C19[1][A] | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_6_s1/CLK |
0.196 | 0.012 | tHld | 1 | R23C19[1][A] | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_6_s1 |
Path Statistics:
Clock Skew | -0.008 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.191, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.515, 60.690%; tC2Q: 0.333, 39.310% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.183, 100.000% |
Path8
Path Summary:
Slack | 5.843 |
Data Arrival Time | 6.039 |
Data Required Time | 0.196 |
From | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_7_s1 |
Launch Clk | pclk:[F] |
Latch Clk | pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | pclk | ||||
5.000 | 0.000 | tCL | FF | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
5.191 | 0.191 | tNET | FF | 1 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/CLK |
5.524 | 0.333 | tC2Q | FR | 48 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q |
6.039 | 0.515 | tNET | RR | 1 | R23C19[1][B] | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_7_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pclk | ||||
0.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
0.183 | 0.183 | tNET | RR | 1 | R23C19[1][B] | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_7_s1/CLK |
0.196 | 0.012 | tHld | 1 | R23C19[1][B] | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_7_s1 |
Path Statistics:
Clock Skew | -0.008 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.191, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.515, 60.690%; tC2Q: 0.333, 39.310% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.183, 100.000% |
Path9
Path Summary:
Slack | 5.907 |
Data Arrival Time | 6.103 |
Data Required Time | 0.196 |
From | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_gvio_inst_0/u_la0_top/internal_reg_start_syn_0_s0 |
Launch Clk | pclk:[F] |
Latch Clk | pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | pclk | ||||
5.000 | 0.000 | tCL | FF | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
5.191 | 0.191 | tNET | FF | 1 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/CLK |
5.524 | 0.333 | tC2Q | FR | 48 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q |
6.103 | 0.579 | tNET | RR | 1 | R23C17[0][A] | gw_gao_gvio_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pclk | ||||
0.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
0.183 | 0.183 | tNET | RR | 1 | R23C17[0][A] | gw_gao_gvio_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLK |
0.196 | 0.012 | tHld | 1 | R23C17[0][A] | gw_gao_gvio_inst_0/u_la0_top/internal_reg_start_syn_0_s0 |
Path Statistics:
Clock Skew | -0.008 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.191, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.579, 63.450%; tC2Q: 0.333, 36.550% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.183, 100.000% |
Path10
Path Summary:
Slack | 5.907 |
Data Arrival Time | 6.103 |
Data Required Time | 0.196 |
From | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_gvio_inst_0/u_la0_top/internal_reg_start_syn_1_s0 |
Launch Clk | pclk:[F] |
Latch Clk | pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | pclk | ||||
5.000 | 0.000 | tCL | FF | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
5.191 | 0.191 | tNET | FF | 1 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/CLK |
5.524 | 0.333 | tC2Q | FR | 48 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q |
6.103 | 0.579 | tNET | RR | 1 | R23C17[0][B] | gw_gao_gvio_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pclk | ||||
0.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
0.183 | 0.183 | tNET | RR | 1 | R23C17[0][B] | gw_gao_gvio_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLK |
0.196 | 0.012 | tHld | 1 | R23C17[0][B] | gw_gao_gvio_inst_0/u_la0_top/internal_reg_start_syn_1_s0 |
Path Statistics:
Clock Skew | -0.008 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.191, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.579, 63.450%; tC2Q: 0.333, 36.550% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.183, 100.000% |
Path11
Path Summary:
Slack | 5.911 |
Data Arrival Time | 6.107 |
Data Required Time | 0.196 |
From | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1 |
Launch Clk | pclk:[F] |
Latch Clk | pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | pclk | ||||
5.000 | 0.000 | tCL | FF | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
5.191 | 0.191 | tNET | FF | 1 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/CLK |
5.524 | 0.333 | tC2Q | FR | 48 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q |
6.107 | 0.582 | tNET | RR | 1 | R21C21[1][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pclk | ||||
0.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
0.183 | 0.183 | tNET | RR | 1 | R21C21[1][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK |
0.196 | 0.012 | tHld | 1 | R21C21[1][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1 |
Path Statistics:
Clock Skew | -0.008 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.191, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.582, 63.599%; tC2Q: 0.333, 36.401% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.183, 100.000% |
Path12
Path Summary:
Slack | 5.911 |
Data Arrival Time | 6.107 |
Data Required Time | 0.196 |
From | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1 |
Launch Clk | pclk:[F] |
Latch Clk | pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | pclk | ||||
5.000 | 0.000 | tCL | FF | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
5.191 | 0.191 | tNET | FF | 1 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/CLK |
5.524 | 0.333 | tC2Q | FR | 48 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q |
6.107 | 0.582 | tNET | RR | 1 | R21C21[2][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pclk | ||||
0.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
0.183 | 0.183 | tNET | RR | 1 | R21C21[2][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK |
0.196 | 0.012 | tHld | 1 | R21C21[2][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1 |
Path Statistics:
Clock Skew | -0.008 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.191, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.582, 63.599%; tC2Q: 0.333, 36.401% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.183, 100.000% |
Path13
Path Summary:
Slack | 5.911 |
Data Arrival Time | 6.107 |
Data Required Time | 0.196 |
From | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_0_s3 |
Launch Clk | pclk:[F] |
Latch Clk | pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | pclk | ||||
5.000 | 0.000 | tCL | FF | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
5.191 | 0.191 | tNET | FF | 1 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/CLK |
5.524 | 0.333 | tC2Q | FR | 48 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q |
6.107 | 0.582 | tNET | RR | 1 | R24C19[0][A] | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_0_s3/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pclk | ||||
0.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
0.183 | 0.183 | tNET | RR | 1 | R24C19[0][A] | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_0_s3/CLK |
0.196 | 0.012 | tHld | 1 | R24C19[0][A] | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_0_s3 |
Path Statistics:
Clock Skew | -0.008 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.191, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.582, 63.599%; tC2Q: 0.333, 36.401% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.183, 100.000% |
Path14
Path Summary:
Slack | 5.911 |
Data Arrival Time | 6.107 |
Data Required Time | 0.196 |
From | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_1_s1 |
Launch Clk | pclk:[F] |
Latch Clk | pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | pclk | ||||
5.000 | 0.000 | tCL | FF | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
5.191 | 0.191 | tNET | FF | 1 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/CLK |
5.524 | 0.333 | tC2Q | FR | 48 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q |
6.107 | 0.582 | tNET | RR | 1 | R24C19[1][A] | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pclk | ||||
0.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
0.183 | 0.183 | tNET | RR | 1 | R24C19[1][A] | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_1_s1/CLK |
0.196 | 0.012 | tHld | 1 | R24C19[1][A] | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_1_s1 |
Path Statistics:
Clock Skew | -0.008 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.191, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.582, 63.599%; tC2Q: 0.333, 36.401% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.183, 100.000% |
Path15
Path Summary:
Slack | 5.915 |
Data Arrival Time | 6.110 |
Data Required Time | 0.196 |
From | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_2_s1 |
Launch Clk | pclk:[F] |
Latch Clk | pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | pclk | ||||
5.000 | 0.000 | tCL | FF | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
5.191 | 0.191 | tNET | FF | 1 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/CLK |
5.524 | 0.333 | tC2Q | FR | 48 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q |
6.110 | 0.586 | tNET | RR | 1 | R24C18[0][B] | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pclk | ||||
0.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
0.183 | 0.183 | tNET | RR | 1 | R24C18[0][B] | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_2_s1/CLK |
0.196 | 0.012 | tHld | 1 | R24C18[0][B] | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_2_s1 |
Path Statistics:
Clock Skew | -0.008 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.191, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.586, 63.748%; tC2Q: 0.333, 36.252% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.183, 100.000% |
Path16
Path Summary:
Slack | 5.915 |
Data Arrival Time | 6.110 |
Data Required Time | 0.196 |
From | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_3_s1 |
Launch Clk | pclk:[F] |
Latch Clk | pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | pclk | ||||
5.000 | 0.000 | tCL | FF | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
5.191 | 0.191 | tNET | FF | 1 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/CLK |
5.524 | 0.333 | tC2Q | FR | 48 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q |
6.110 | 0.586 | tNET | RR | 1 | R24C18[1][A] | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pclk | ||||
0.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
0.183 | 0.183 | tNET | RR | 1 | R24C18[1][A] | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_3_s1/CLK |
0.196 | 0.012 | tHld | 1 | R24C18[1][A] | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_3_s1 |
Path Statistics:
Clock Skew | -0.008 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.191, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.586, 63.748%; tC2Q: 0.333, 36.252% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.183, 100.000% |
Path17
Path Summary:
Slack | 5.915 |
Data Arrival Time | 6.110 |
Data Required Time | 0.196 |
From | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_gvio_inst_0/u_la0_top/trigger_seq_start_s1 |
Launch Clk | pclk:[F] |
Latch Clk | pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | pclk | ||||
5.000 | 0.000 | tCL | FF | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
5.191 | 0.191 | tNET | FF | 1 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/CLK |
5.524 | 0.333 | tC2Q | FR | 48 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q |
6.110 | 0.586 | tNET | RR | 1 | R23C18[2][A] | gw_gao_gvio_inst_0/u_la0_top/trigger_seq_start_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pclk | ||||
0.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
0.183 | 0.183 | tNET | RR | 1 | R23C18[2][A] | gw_gao_gvio_inst_0/u_la0_top/trigger_seq_start_s1/CLK |
0.196 | 0.012 | tHld | 1 | R23C18[2][A] | gw_gao_gvio_inst_0/u_la0_top/trigger_seq_start_s1 |
Path Statistics:
Clock Skew | -0.008 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.191, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.586, 63.748%; tC2Q: 0.333, 36.252% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.183, 100.000% |
Path18
Path Summary:
Slack | 5.915 |
Data Arrival Time | 6.110 |
Data Required Time | 0.196 |
From | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_gvio_inst_0/u_la0_top/triger_s0 |
Launch Clk | pclk:[F] |
Latch Clk | pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | pclk | ||||
5.000 | 0.000 | tCL | FF | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
5.191 | 0.191 | tNET | FF | 1 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/CLK |
5.524 | 0.333 | tC2Q | FR | 48 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q |
6.110 | 0.586 | tNET | RR | 1 | R23C18[0][B] | gw_gao_gvio_inst_0/u_la0_top/triger_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pclk | ||||
0.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
0.183 | 0.183 | tNET | RR | 1 | R23C18[0][B] | gw_gao_gvio_inst_0/u_la0_top/triger_s0/CLK |
0.196 | 0.012 | tHld | 1 | R23C18[0][B] | gw_gao_gvio_inst_0/u_la0_top/triger_s0 |
Path Statistics:
Clock Skew | -0.008 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.191, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.586, 63.748%; tC2Q: 0.333, 36.252% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.183, 100.000% |
Path19
Path Summary:
Slack | 5.915 |
Data Arrival Time | 6.110 |
Data Required Time | 0.196 |
From | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_gvio_inst_0/u_la0_top/start_reg_s0 |
Launch Clk | pclk:[F] |
Latch Clk | pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | pclk | ||||
5.000 | 0.000 | tCL | FF | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
5.191 | 0.191 | tNET | FF | 1 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/CLK |
5.524 | 0.333 | tC2Q | FR | 48 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q |
6.110 | 0.586 | tNET | RR | 1 | R23C18[0][A] | gw_gao_gvio_inst_0/u_la0_top/start_reg_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pclk | ||||
0.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
0.183 | 0.183 | tNET | RR | 1 | R23C18[0][A] | gw_gao_gvio_inst_0/u_la0_top/start_reg_s0/CLK |
0.196 | 0.012 | tHld | 1 | R23C18[0][A] | gw_gao_gvio_inst_0/u_la0_top/start_reg_s0 |
Path Statistics:
Clock Skew | -0.008 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.191, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.586, 63.748%; tC2Q: 0.333, 36.252% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.183, 100.000% |
Path20
Path Summary:
Slack | 5.915 |
Data Arrival Time | 6.110 |
Data Required Time | 0.196 |
From | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_gvio_inst_0/u_la0_top/internal_reg_start_dly_0_s0 |
Launch Clk | pclk:[F] |
Latch Clk | pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | pclk | ||||
5.000 | 0.000 | tCL | FF | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
5.191 | 0.191 | tNET | FF | 1 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/CLK |
5.524 | 0.333 | tC2Q | FR | 48 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q |
6.110 | 0.586 | tNET | RR | 1 | R24C18[2][A] | gw_gao_gvio_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pclk | ||||
0.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
0.183 | 0.183 | tNET | RR | 1 | R24C18[2][A] | gw_gao_gvio_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLK |
0.196 | 0.012 | tHld | 1 | R24C18[2][A] | gw_gao_gvio_inst_0/u_la0_top/internal_reg_start_dly_0_s0 |
Path Statistics:
Clock Skew | -0.008 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.191, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.586, 63.748%; tC2Q: 0.333, 36.252% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.183, 100.000% |
Path21
Path Summary:
Slack | 5.915 |
Data Arrival Time | 6.110 |
Data Required Time | 0.196 |
From | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_gvio_inst_0/u_la0_top/internal_reg_start_dly_1_s0 |
Launch Clk | pclk:[F] |
Latch Clk | pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | pclk | ||||
5.000 | 0.000 | tCL | FF | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
5.191 | 0.191 | tNET | FF | 1 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/CLK |
5.524 | 0.333 | tC2Q | FR | 48 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q |
6.110 | 0.586 | tNET | RR | 1 | R23C18[1][A] | gw_gao_gvio_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pclk | ||||
0.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
0.183 | 0.183 | tNET | RR | 1 | R23C18[1][A] | gw_gao_gvio_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLK |
0.196 | 0.012 | tHld | 1 | R23C18[1][A] | gw_gao_gvio_inst_0/u_la0_top/internal_reg_start_dly_1_s0 |
Path Statistics:
Clock Skew | -0.008 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.191, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.586, 63.748%; tC2Q: 0.333, 36.252% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.183, 100.000% |
Path22
Path Summary:
Slack | 6.101 |
Data Arrival Time | 6.296 |
Data Required Time | 0.196 |
From | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1 |
Launch Clk | pclk:[F] |
Latch Clk | pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | pclk | ||||
5.000 | 0.000 | tCL | FF | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
5.191 | 0.191 | tNET | FF | 1 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/CLK |
5.524 | 0.333 | tC2Q | FR | 48 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q |
6.296 | 0.772 | tNET | RR | 1 | R21C18[0][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pclk | ||||
0.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
0.183 | 0.183 | tNET | RR | 1 | R21C18[0][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK |
0.196 | 0.012 | tHld | 1 | R21C18[0][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1 |
Path Statistics:
Clock Skew | -0.008 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.191, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.772, 69.847%; tC2Q: 0.333, 30.153% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.183, 100.000% |
Path23
Path Summary:
Slack | 6.101 |
Data Arrival Time | 6.296 |
Data Required Time | 0.196 |
From | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1 |
Launch Clk | pclk:[F] |
Latch Clk | pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | pclk | ||||
5.000 | 0.000 | tCL | FF | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
5.191 | 0.191 | tNET | FF | 1 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/CLK |
5.524 | 0.333 | tC2Q | FR | 48 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q |
6.296 | 0.772 | tNET | RR | 1 | R21C18[0][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pclk | ||||
0.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
0.183 | 0.183 | tNET | RR | 1 | R21C18[0][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK |
0.196 | 0.012 | tHld | 1 | R21C18[0][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1 |
Path Statistics:
Clock Skew | -0.008 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.191, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.772, 69.847%; tC2Q: 0.333, 30.153% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.183, 100.000% |
Path24
Path Summary:
Slack | 6.120 |
Data Arrival Time | 6.316 |
Data Required Time | 0.196 |
From | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_gvio_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0 |
Launch Clk | pclk:[F] |
Latch Clk | pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | pclk | ||||
5.000 | 0.000 | tCL | FF | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
5.191 | 0.191 | tNET | FF | 1 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/CLK |
5.524 | 0.333 | tC2Q | FR | 48 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q |
6.316 | 0.791 | tNET | RR | 1 | R22C12[0][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pclk | ||||
0.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
0.183 | 0.183 | tNET | RR | 1 | R22C12[0][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLK |
0.196 | 0.012 | tHld | 1 | R22C12[0][A] | gw_gao_gvio_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0 |
Path Statistics:
Clock Skew | -0.008 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.191, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.791, 70.359%; tC2Q: 0.333, 29.641% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.183, 100.000% |
Path25
Path Summary:
Slack | 6.120 |
Data Arrival Time | 6.316 |
Data Required Time | 0.196 |
From | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_gvio_inst_0/u_la0_top/u_ao_match_0/trig_dly_0_s0 |
Launch Clk | pclk:[F] |
Latch Clk | pclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | pclk | ||||
5.000 | 0.000 | tCL | FF | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
5.191 | 0.191 | tNET | FF | 1 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/CLK |
5.524 | 0.333 | tC2Q | FR | 48 | R23C20[2][B] | gw_gao_gvio_inst_0/u_la0_top/rst_ao_s0/Q |
6.316 | 0.791 | tNET | RR | 1 | R22C12[0][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_match_0/trig_dly_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pclk | ||||
0.000 | 0.000 | tCL | RR | 116 | BOTTOMSIDE[0] | u_CLKDIV/CLKOUT |
0.183 | 0.183 | tNET | RR | 1 | R22C12[0][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_match_0/trig_dly_0_s0/CLK |
0.196 | 0.012 | tHld | 1 | R22C12[0][B] | gw_gao_gvio_inst_0/u_la0_top/u_ao_match_0/trig_dly_0_s0 |
Path Statistics:
Clock Skew | -0.008 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.191, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.791, 70.359%; tC2Q: 0.333, 29.641% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.183, 100.000% |
Minimum Pulse Width Report:
Report Command:report_min_pulse_width -nworst 10 -detail
MPW1
MPW Summary:
Slack: | 3.676 |
Actual Width: | 4.926 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | pclk |
Objects: | gw_gao_gvio_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | pclk | ||
5.000 | 0.000 | tCL | FF | u_CLKDIV/CLKOUT |
5.257 | 0.257 | tNET | FF | gw_gao_gvio_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | pclk | ||
10.000 | 0.000 | tCL | RR | u_CLKDIV/CLKOUT |
10.183 | 0.183 | tNET | RR | gw_gao_gvio_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLK |
MPW2
MPW Summary:
Slack: | 3.676 |
Actual Width: | 4.926 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | pclk |
Objects: | gw_gao_gvio_inst_0/u_la0_top/internal_reg_start_syn_1_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | pclk | ||
5.000 | 0.000 | tCL | FF | u_CLKDIV/CLKOUT |
5.257 | 0.257 | tNET | FF | gw_gao_gvio_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | pclk | ||
10.000 | 0.000 | tCL | RR | u_CLKDIV/CLKOUT |
10.183 | 0.183 | tNET | RR | gw_gao_gvio_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLK |
MPW3
MPW Summary:
Slack: | 3.676 |
Actual Width: | 4.926 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | pclk |
Objects: | gw_gao_gvio_inst_0/u_la0_top/start_reg_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | pclk | ||
5.000 | 0.000 | tCL | FF | u_CLKDIV/CLKOUT |
5.257 | 0.257 | tNET | FF | gw_gao_gvio_inst_0/u_la0_top/start_reg_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | pclk | ||
10.000 | 0.000 | tCL | RR | u_CLKDIV/CLKOUT |
10.183 | 0.183 | tNET | RR | gw_gao_gvio_inst_0/u_la0_top/start_reg_s0/CLK |
MPW4
MPW Summary:
Slack: | 3.676 |
Actual Width: | 4.926 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | pclk |
Objects: | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_6_s1 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | pclk | ||
5.000 | 0.000 | tCL | FF | u_CLKDIV/CLKOUT |
5.257 | 0.257 | tNET | FF | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_6_s1/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | pclk | ||
10.000 | 0.000 | tCL | RR | u_CLKDIV/CLKOUT |
10.183 | 0.183 | tNET | RR | gw_gao_gvio_inst_0/u_la0_top/capture_window_sel_6_s1/CLK |
MPW5
MPW Summary:
Slack: | 3.676 |
Actual Width: | 4.926 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | pclk |
Objects: | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_2_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | pclk | ||
5.000 | 0.000 | tCL | FF | u_CLKDIV/CLKOUT |
5.257 | 0.257 | tNET | FF | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_2_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | pclk | ||
10.000 | 0.000 | tCL | RR | u_CLKDIV/CLKOUT |
10.183 | 0.183 | tNET | RR | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_2_s0/CLK |
MPW6
MPW Summary:
Slack: | 3.676 |
Actual Width: | 4.926 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | pclk |
Objects: | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | pclk | ||
5.000 | 0.000 | tCL | FF | u_CLKDIV/CLKOUT |
5.257 | 0.257 | tNET | FF | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | pclk | ||
10.000 | 0.000 | tCL | RR | u_CLKDIV/CLKOUT |
10.183 | 0.183 | tNET | RR | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK |
MPW7
MPW Summary:
Slack: | 3.676 |
Actual Width: | 4.926 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | pclk |
Objects: | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | pclk | ||
5.000 | 0.000 | tCL | FF | u_CLKDIV/CLKOUT |
5.257 | 0.257 | tNET | FF | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | pclk | ||
10.000 | 0.000 | tCL | RR | u_CLKDIV/CLKOUT |
10.183 | 0.183 | tNET | RR | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK |
MPW8
MPW Summary:
Slack: | 3.676 |
Actual Width: | 4.926 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | pclk |
Objects: | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_3_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | pclk | ||
5.000 | 0.000 | tCL | FF | u_CLKDIV/CLKOUT |
5.257 | 0.257 | tNET | FF | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_3_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | pclk | ||
10.000 | 0.000 | tCL | RR | u_CLKDIV/CLKOUT |
10.183 | 0.183 | tNET | RR | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_3_s0/CLK |
MPW9
MPW Summary:
Slack: | 3.676 |
Actual Width: | 4.926 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | pclk |
Objects: | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | pclk | ||
5.000 | 0.000 | tCL | FF | u_CLKDIV/CLKOUT |
5.257 | 0.257 | tNET | FF | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | pclk | ||
10.000 | 0.000 | tCL | RR | u_CLKDIV/CLKOUT |
10.183 | 0.183 | tNET | RR | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLK |
MPW10
MPW Summary:
Slack: | 3.676 |
Actual Width: | 4.926 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | pclk |
Objects: | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | pclk | ||
5.000 | 0.000 | tCL | FF | u_CLKDIV/CLKOUT |
5.257 | 0.257 | tNET | FF | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | pclk | ||
10.000 | 0.000 | tCL | RR | u_CLKDIV/CLKOUT |
10.183 | 0.183 | tNET | RR | gw_gao_gvio_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLK |
High Fanout Nets Report:
Report Command:report_high_fanout_nets -max_nets 10
FANOUT | NET NAME | WORST SLACK | MAX DELAY |
---|---|---|---|
242 | gw_gao_gvio_inst_0/gao_control0[0] | 38.444 | 1.726 |
116 | pclk_d | 0.153 | 0.659 |
48 | gw_gao_gvio_inst_0/u_la0_top/rst_ao | 2.304 | 2.179 |
37 | gw_gao_gvio_inst_0/u_la0_top/n20_3 | 44.041 | 3.421 |
36 | gw_gao_gvio_inst_0/u_la0_top/data_to_word_counter_15_5 | 40.558 | 2.006 |
32 | gw_gao_gvio_inst_0/u_la0_top/u_ao_crc32/crc_28_7 | 41.428 | 1.653 |
27 | gw_gao_gvio_inst_0/u_la0_top/n20_4 | 39.117 | 1.691 |
24 | gw_gao_gvio_inst_0/u_la0_top/module_state[1] | 39.524 | 2.009 |
22 | gw_gao_gvio_inst_0/u_la0_top/module_state[0] | 39.339 | 1.828 |
21 | gw_gao_gvio_inst_0/u_la0_top/op_reg_en_10 | 39.551 | 1.824 |
Route Congestions Report:
Report Command:report_route_congestion -max_grids 10
GRID LOC | ROUTE CONGESTIONS |
---|---|
R2C2 | 100.00% |
R2C7 | 100.00% |
R2C9 | 100.00% |
R2C10 | 100.00% |
R2C26 | 100.00% |
R3C13 | 100.00% |
R4C32 | 100.00% |
R7C24 | 100.00% |
R13C46 | 100.00% |
R25C40 | 100.00% |
Timing Exceptions Report:
Setup Analysis Report
Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Hold Analysis Report
Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Recovery Analysis Report
Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Removal Analysis Report
Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Timing Constraints Report:
SDC Command Type | State | Detail Command |
---|---|---|
TC_CLOCK | Actived | create_clock -name tck_pad_i -period 50 -waveform {0 25} [get_ports {tck_pad_i}] |
TC_CLOCK | Actived | create_clock -name pclk -period 10 -waveform {0 5} [get_pins {u_CLKDIV/CLKOUT}] |
TC_CLOCK_GROUP | Actived | set_clock_groups -asynchronous -group [get_clocks {tck_pad_i}] -group [get_clocks {pclk}] |